A collection of advanced cache design algorithms including LRU, LFU, ARC, TinyLFU, Count-Min Sketch, and Segmented LRU, implemented in TypeScript.
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Nov 19, 2025 - JavaScript
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cache-design
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Computer Architecture: 01:198:211 This course covers the fundamental issues in the design of modern computer systems, including the design and implementation of key hardware components such as the processor, memory, and I/O devices, and the software/hardware interface.
c data-representation assembly-x86 digital-logic-design computer-arithmetic processor-design cache-design main-memory-design
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Sep 18, 2018 - C
Verilog implementation of L1 cache (direct-mapped, 4-way, fully-associative) with simulation outputs
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Dec 17, 2025 - Verilog
COE758 - This course covers advanced computing systems with emphasis on system architecture, memory hierarchy (Cache, Virtual memory), processor-peripheral interfacing, and bus organization. Laboratory projects include Cache Controller and VGA display design using FPGA. This course is taken at TMU, formally known as Ryerson.
vhdl virtual-memory dma memory-hierarchy vga-controller cache-memory cache-design video-output subsystems cache-controller digital-systems-design fpga-projects
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Dec 19, 2025 - C
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