common: Make sure to always assign all 'reg's in processes to avoid latches

If you don't assign all 'reg's in a process, this effectively describes
a latch, and the HW doesn't have any HW latches which leads yosys to create
a logic loop, which is definitely not good in FPGA !

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>

Author: smunaut

common/usb_fs_in_arb.v

@@ -20,6 +20,8 @@ module usb_fs_in_arb #(
   always @* begin
     grant = 0;
 
+    arb_in_ep_data <= 0;
+
     for (i = 0; i < NUM_IN_EPS; i = i + 1) begin
       in_ep_grant[i] <= 0;
 
@@ -29,9 +31,5 @@ module usb_fs_in_arb #(
         grant = 1;
       end
     end
-
-    if (!grant) begin
-      arb_in_ep_data <= 0;
-    end
   end
 endmodule

common/usb_fs_in_pe.v

@@ -166,6 +166,8 @@ module usb_fs_in_pe #(
       always @* begin
         in_ep_acked[ep_num] <= 0;
 
+        ep_state_next[ep_num] <= ep_state[ep_num];
+
         if (in_ep_stall[ep_num]) begin
           ep_state_next[ep_num] <= STALL;
 
@@ -277,9 +279,11 @@ module usb_fs_in_pe #(
   reg rollback_in_xfr;
 
   always @* begin
+    in_xfr_state_next <= in_xfr_state;
     in_xfr_start <= 0;
     in_xfr_end <= 0;
     tx_pkt_start <= 0;
+    tx_pid <= 4'b0000;
     rollback_in_xfr <= 0;
 
     case (in_xfr_state)

common/usb_fs_out_pe.v

@@ -154,6 +154,8 @@ module usb_fs_out_pe #(
     for (ep_num = 0; ep_num < NUM_OUT_EPS; ep_num = ep_num + 1) begin
       always @* begin
 
+        ep_state_next[ep_num] <= ep_state[ep_num];
+
         if (out_ep_stall[ep_num]) begin
           ep_state_next[ep_num] <= STALL;
 
@@ -272,7 +274,9 @@ module usb_fs_out_pe #(
   ////////////////////////////////////////////////////////////////////////////////
 
   always @* begin
+    out_ep_acked <= 0;
     out_xfr_start <= 0;
+    out_xfr_state_next <= out_xfr_state;
     tx_pkt_start <= 0;
     tx_pid <= 0;
     new_pkt_end <= 0;