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@MatzeB MatzeB commented Dec 17, 2025

Summary:
X-link: https://github.com/facebookresearch/FBGEMM/pull/2235

This adds an autovectorized implementation of the GenerateEmbeddingSpMDMNBitRowWiseSparse kernels.

This first version is around 10x improvement compared to the reference C++ implementation, but slower than the asmjit verison (which is x86 only), see list below for how to close this gap:

Room for further enhacements (see some of the surrounding kernels that do implement them):

  • This is only specialized for bit_rate right now. Specializing for common block sizes typically nets good improvements.
  • Directly operates on the out buffer. This is good for unknown block-sizes, but if we specialize for fixed small block-sizes then a separate buffer is better as it can be promoted completely to vector registers (for fixed vector register size anyway, doesn't work for variable size AArch64 SVE registers).
  • No prefetching logic yet.

Differential Revision: D89086019

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meta-codesync bot commented Dec 17, 2025

@MatzeB has exported this pull request. If you are a Meta employee, you can view the originating Diff in D89086019.

@meta-cla meta-cla bot added the cla signed label Dec 17, 2025
MatzeB added a commit to MatzeB/FBGEMM that referenced this pull request Dec 19, 2025
)

Summary:

X-link: facebookresearch/FBGEMM#2235

This adds an autovectorized implementation of the `GenerateEmbeddingSpMDMNBitRowWiseSparse` kernels.

This first version is around 10x improvement compared to the reference C++ implementation, but slower than the asmjit verison (which is x86 only), see list below for how to close this gap:

Room for further enhacements (see some of the surrounding kernels that do implement them):
- This is only specialized for `bit_rate` right now. Specializing for common block sizes typically nets good improvements.
- Directly operates on the `out` buffer. This is good for unknown block-sizes, but if we specialize for fixed small block-sizes then a separate buffer is better as it can be promoted completely to vector registers (for fixed vector register size anyway, doesn't work for variable size AArch64 SVE registers).
- No prefetching logic yet.

Differential Revision: D89086019
MatzeB added a commit to MatzeB/FBGEMM that referenced this pull request Dec 19, 2025
)

Summary:

X-link: facebookresearch/FBGEMM#2235

This adds an autovectorized implementation of the `GenerateEmbeddingSpMDMNBitRowWiseSparse` kernels.

This first version is around 10x improvement compared to the reference C++ implementation, but slower than the asmjit verison (which is x86 only), see list below for how to close this gap:

Room for further enhacements (see some of the surrounding kernels that do implement them):
- This is only specialized for `bit_rate` right now. Specializing for common block sizes typically nets good improvements.
- Directly operates on the `out` buffer. This is good for unknown block-sizes, but if we specialize for fixed small block-sizes then a separate buffer is better as it can be promoted completely to vector registers (for fixed vector register size anyway, doesn't work for variable size AArch64 SVE registers).
- No prefetching logic yet.

Reviewed By: excelle08

Differential Revision: D89086019
MatzeB added a commit to MatzeB/FBGEMM that referenced this pull request Dec 19, 2025
)

Summary:

X-link: facebookresearch/FBGEMM#2235

This adds an autovectorized implementation of the `GenerateEmbeddingSpMDMNBitRowWiseSparse` kernels.

This first version is around 10x improvement compared to the reference C++ implementation, but slower than the asmjit verison (which is x86 only), see list below for how to close this gap:

Room for further enhacements (see some of the surrounding kernels that do implement them):
- This is only specialized for `bit_rate` right now. Specializing for common block sizes typically nets good improvements.
- Directly operates on the `out` buffer. This is good for unknown block-sizes, but if we specialize for fixed small block-sizes then a separate buffer is better as it can be promoted completely to vector registers (for fixed vector register size anyway, doesn't work for variable size AArch64 SVE registers).
- No prefetching logic yet.

Reviewed By: excelle08

Differential Revision: D89086019
MatzeB added a commit to MatzeB/FBGEMM that referenced this pull request Dec 19, 2025
)

Summary:

X-link: facebookresearch/FBGEMM#2235

This adds an autovectorized implementation of the `GenerateEmbeddingSpMDMNBitRowWiseSparse` kernels.

This first version is around 10x improvement compared to the reference C++ implementation, but slower than the asmjit verison (which is x86 only), see list below for how to close this gap:

Room for further enhacements (see some of the surrounding kernels that do implement them):
- This is only specialized for `bit_rate` right now. Specializing for common block sizes typically nets good improvements.
- Directly operates on the `out` buffer. This is good for unknown block-sizes, but if we specialize for fixed small block-sizes then a separate buffer is better as it can be promoted completely to vector registers (for fixed vector register size anyway, doesn't work for variable size AArch64 SVE registers).
- No prefetching logic yet.

Reviewed By: excelle08

Differential Revision: D89086019
)

Summary:

X-link: facebookresearch/FBGEMM#2235

This adds an autovectorized implementation of the `GenerateEmbeddingSpMDMNBitRowWiseSparse` kernels.

This first version is around 10x improvement compared to the reference C++ implementation, but slower than the asmjit verison (which is x86 only), see list below for how to close this gap:

Room for further enhacements (see some of the surrounding kernels that do implement them):
- This is only specialized for `bit_rate` right now. Specializing for common block sizes typically nets good improvements.
- Directly operates on the `out` buffer. This is good for unknown block-sizes, but if we specialize for fixed small block-sizes then a separate buffer is better as it can be promoted completely to vector registers (for fixed vector register size anyway, doesn't work for variable size AArch64 SVE registers).
- No prefetching logic yet.

Reviewed By: excelle08

Differential Revision: D89086019
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