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boards/TinyFPGA_B2: Setup bootloader build for board
Using the TinyFPGA_BX as a base, setup the constraints and module definition to build the bootloader bitstream for the TinyFPGA B2. All build artifacts are populated into a build/ subdirectory to simplify `make clean` and .gitignore setup. The `fw.bin` targets builds a complete SPI flash image. It includes the metadata section in flash for "bootmeta", however it leaves the security page setup as an external process/step. Also included as preliminary Make targets to build this design with nextpnr instead of arachne-pnr. The firmware image can be build with the follow command `make build/bootloader.nextpnr.img`.
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‎boards/TinyFPGA_B2/Makefile‎

Lines changed: 48 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -14,49 +14,67 @@
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# ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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# OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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17-
PROJ = TinyFPGA_BX
17+
PROJ = bootloader
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OUTDIR = build
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1920
PIN_DEF = pins.pcf
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DEVICE = lp8k
21-
22-
all: $(PROJ).rpt $(PROJ).bin
23-
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%.blif: %.v *.v
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yosys -p 'synth_ice40 -top $(PROJ) -blif $@' $^
26-
27-
%.asc: $(PIN_DEF) %.blif
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arachne-pnr -d 8k -P cm81 -o $@ -p $^
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PKG = cm81
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all: $(OUTDIR)/fw.bin
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$(OUTDIR)/fw.bin: $(OUTDIR)/$(PROJ).img
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cp $< $@
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$(OUTDIR)/$(PROJ).blif $(OUTDIR)/$(PROJ).yosys.json $(OUTDIR)/$(PROJ).synthesis.rpt: $(PROJ).v ../../common/*.v
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$(OUTDIR)/$(PROJ).asc: $(PIN_DEF)
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$(OUTDIR)/$(PROJ).nextpnr.asc: $(PIN_DEF)
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$(OUTDIR)/bootmeta.json:
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@mkdir -p $(@D)
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echo '{' > $@
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echo ' "bootloader": "TinyFPGA USB Bootloader",' >> $@
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echo ' "bver": "$(shell git describe --tags || echo "Unknown")",' >> $@
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echo ' "addrmap": {' >> $@
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echo ' "bootloader": "0x00000-0x27FFF",' >> $@
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echo ' "userimage": "0x28000-0x4FFFF",' >> $@
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echo ' "userdata": "0x50000-0x7EFFF",' >> $@
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echo ' "bootmeta": "0x7F000-0x7FFFF"' >> $@
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echo ' }' >> $@
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echo '}' >> $@
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%.img: %.bin %.rpt $(OUTDIR)/bootmeta.json
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@mkdir -p $(@D)
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cp $< $(patsubst %.bin,%_0.bin,$<)
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cp $< $(patsubst %.bin,%_1.bin,$<)
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icemulti -v -o $@ -a15 -p0 $(patsubst %.bin,%_0.bin,$<) $(patsubst %.bin,%_1.bin,$<)
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truncate -s 512K $@
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dd if=$(OUTDIR)/bootmeta.json of=$@ bs=1 seek=508K conv=notrunc
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%.blif %.yosys.json %.synthesis.rpt:
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@mkdir -p $(@D)
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yosys -q -l $*.synthesis.rpt -p 'synth_ice40 -top $(PROJ) -blif $*.blif -json $*.yosys.json' $^
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%.asc: %.blif
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@mkdir -p $(@D)
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arachne-pnr -d 8k -P $(PKG) -o $@ -p $(filter %.pcf,$^) $(filter %.blif,$^)
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%.nextpnr.asc: %.yosys.json
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@mkdir -p $(@D)
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nextpnr-ice40 --lp8k --package $(PKG) --json $(filter %.yosys.json,$^) --pcf $(filter %.pcf,$^) --asc $@
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%.bin: %.asc
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@mkdir -p $(@D)
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icepack $< $@
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%.rpt: %.asc
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icetime -d $(DEVICE) -mtr $@ $<
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36-
%_tb: %_tb.v %.v
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iverilog -o $@ $^
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%_tb.vcd: %_tb
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vvp -N $< +vcd=$@
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%_syn.v: %.blif
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yosys -p 'read_blif -wideports $^; write_verilog $@'
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45-
%_syntb: %_tb.v %_syn.v
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iverilog -o $@ $^ `yosys-config --datdir/ice40/cells_sim.v`
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%_syntb.vcd: %_syntb
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vvp -N $< +vcd=$@
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prog: $(PROJ).bin
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iceprog $<
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sudo-prog: $(PROJ).bin
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@echo 'Executing prog as root!!!'
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sudo iceprog $<
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clean:
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rm -f $(PROJ).blif $(PROJ).asc $(PROJ).rpt $(PROJ).bin
77+
[ -z "$(OUTDIR)" ] || rm -rf $(OUTDIR)/
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.SECONDARY:
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.PHONY: all prog clean
80+
.PHONY: all clean

‎boards/TinyFPGA_B2/TinyFPGA_B2.v‎

Lines changed: 0 additions & 99 deletions
This file was deleted.

‎boards/TinyFPGA_B2/bootloader.v‎

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,90 @@
1+
module bootloader (
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input pin_clk,
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inout pin_usbp,
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inout pin_usbn,
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input pin_miso,
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output pin_cs,
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output pin_mosi,
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output pin_sck
11+
);
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// generate 48 mhz clock
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wire clk_48mhz;
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15+
SB_PLL40_CORE #(
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.DIVR(4'b0000),
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.DIVF(7'b0101111),
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.DIVQ(3'b100),
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.FILTER_RANGE(3'b001),
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.FEEDBACK_PATH("SIMPLE"),
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.DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"),
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.FDA_FEEDBACK(4'b0000),
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.DELAY_ADJUSTMENT_MODE_RELATIVE("FIXED"),
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.FDA_RELATIVE(4'b0000),
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.SHIFTREG_DIV_MODE(2'b00),
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.PLLOUT_SELECT("GENCLK"),
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.ENABLE_ICEGATE(1'b0)
28+
) usb_pll_inst (
29+
.REFERENCECLK(pin_clk),
30+
.PLLOUTCORE(clk_48mhz),
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.PLLOUTGLOBAL(),
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.EXTFEEDBACK(),
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.DYNAMICDELAY(),
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.RESETB(1'b1),
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.BYPASS(1'b0),
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.LATCHINPUTVALUE(),
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.LOCK(),
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.SDI(),
39+
.SDO(),
40+
.SCLK()
41+
);
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// interface with iCE40 warmboot/multiboot capability
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wire boot;
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SB_WARMBOOT warmboot_inst (
47+
.S1(1'b0),
48+
.S0(1'b1),
49+
.BOOT(boot)
50+
);
51+
52+
// instantiate tinyfpga bootloader
53+
wire reset;
54+
wire usb_p_tx;
55+
wire usb_n_tx;
56+
wire usb_p_rx;
57+
wire usb_n_rx;
58+
wire usb_tx_en;
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60+
tinyfpga_bootloader tinyfpga_bootloader_inst (
61+
.clk_48mhz(clk_48mhz),
62+
.reset(reset),
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.usb_p_tx(usb_p_tx),
64+
.usb_n_tx(usb_n_tx),
65+
.usb_p_rx(usb_p_rx),
66+
.usb_n_rx(usb_n_rx),
67+
.usb_tx_en(usb_tx_en),
68+
.spi_miso(pin_miso),
69+
.spi_cs(pin_cs),
70+
.spi_mosi(pin_mosi),
71+
.spi_sck(pin_sck),
72+
.boot(boot)
73+
);
74+
75+
wire usb_p_rx_in;
76+
wire usb_n_rx_in;
77+
SB_IO #(
78+
.PIN_TYPE(6'b1010_01), // simple input, tristate output
79+
.PULLUP(1'b0)
80+
) usb_io_buf [1:0] (
81+
.PACKAGE_PIN({pin_usbp, pin_usbn}),
82+
.OUTPUT_ENABLE({usb_tx_en, usb_tx_en}),
83+
.D_OUT_0({usb_p_tx, usb_n_tx}),
84+
.D_IN_0({usb_p_rx_in, usb_n_rx_in})
85+
);
86+
assign usb_p_rx = usb_tx_en ? 1'b1 : usb_p_rx_in;
87+
assign usb_n_rx = usb_tx_en ? 1'b0 : usb_n_rx_in;
88+
89+
assign reset = 1'b0;
90+
endmodule

‎boards/TinyFPGA_B2/pins.pcf‎

Lines changed: 13 additions & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -1,48 +1,13 @@
1-
###############################################################################
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# Family & Device: iCE40LP8K
3-
# Package: CM81
4-
###############################################################################
5-
6-
#set_io pin_1 A2
7-
#set_io pin_2 A1
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#set_io pin_3 B1
9-
#set_io pin_4 C2
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#set_io pin_5 C1
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#set_io pin_6 D2
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#set_io pin_7 D1
13-
#set_io pin_8 E2
14-
#set_io pin_9 E1
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#set_io pin_10 G2
16-
#set_io pin_11 H1
17-
#set_io pin_12 J1
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#set_io pin_13 H2
19-
#set_io pin_14 H9
20-
#set_io pin_15 D9
21-
#set_io pin_16 D8
22-
#set_io pin_17 C9
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#set_io pin_18 A9
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#set_io pin_19 B8
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#set_io pin_20 A8
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#set_io pin_21 B7
27-
#set_io pin_22 A7
28-
#set_io pin_23 B6
29-
#set_io pin_24 A6
30-
#set_io pin_25 G1
31-
#set_io pin_26 J3
32-
#set_io pin_27 J4
33-
#set_io pin_28 H4
34-
set_io pin_29_miso H7
35-
set_io pin_30_cs F7
36-
set_io pin_31_mosi G6
37-
set_io pin_32_sck G7
38-
#set_io pin_33 J8
39-
#set_io pin_34 G9
40-
#set_io pin_35 J9
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#set_io pin_36 E8
42-
#set_io pin_37 J2
43-
set_io pin_led B3
44-
set_io pin_usbp B4
45-
set_io pin_usbn A4
46-
set_io pin_pu A3
47-
set_io pin_clk B2
48-
1+
###############################################################################
2+
# Family & Device: iCE40LP8K
3+
# Package: CM81
4+
###############################################################################
5+
6+
set_io pin_cs F7
7+
set_io pin_sck G7
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set_io pin_mosi G6
9+
set_io pin_miso H7
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set_io pin_usbp A3
11+
set_io pin_usbn A4
12+
set_io pin_clk C4
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