testing rv32 with access_adapters disabled

Author: Maillew

crates/vm/src/arch/execution_mode/metered/ctx.rs

@@ -64,11 +64,13 @@ impl<const PAGE_BITS: usize> MeteredCtx<PAGE_BITS> {
                 air_names[merkle_tree_index]
             );
         }
-        debug_assert!(
-            air_names[memory_ctx.adapter_offset].contains("AccessAdapterAir<2>"),
-            "air_name={}",
-            air_names[memory_ctx.adapter_offset]
-        );
+        if memory_ctx.access_adapters_enabled {
+            debug_assert!(
+                air_names[memory_ctx.adapter_offset].contains("AccessAdapterAir<2>"),
+                "air_name={}",
+                air_names[memory_ctx.adapter_offset]
+            );
+        }
 
         let segmentation_ctx =
             SegmentationCtx::new(air_names, widths, interactions, config.segmentation_limits);

crates/vm/src/arch/execution_mode/metered/memory_ctx.rs

@@ -105,7 +105,7 @@ pub struct MemoryCtx<const PAGE_BITS: usize> {
     pub boundary_idx: usize,
     pub merkle_tree_index: Option<usize>,
     pub adapter_offset: usize,
-    access_adapters_enabled: bool,
+    pub access_adapters_enabled: bool,
     continuations_enabled: bool,
     chunk: u32,
     chunk_bits: u32,

crates/vm/src/arch/testing/cpu.rs

@@ -404,7 +404,7 @@ impl<F: PrimeField32> Default for VmChipTestBuilder<F> {
         // removed when tests are updated.
         mem_config.addr_spaces[RV32_REGISTER_AS as usize].num_cells = 1 << 29;
         mem_config.addr_spaces[NATIVE_AS as usize].num_cells = 0;
-        Self::volatile(mem_config)
+        Self::persistent(mem_config)
     }
 }
 

crates/vm/src/arch/vm.rs

@@ -622,7 +622,13 @@ where
         let system_config: &SystemConfig = self.config().as_ref();
         let adapter_offset = system_config.access_adapter_air_id_offset();
         // ATTENTION: this must agree with `num_memory_airs`
-        let num_adapters = log2_strict_usize(system_config.memory_config.max_access_adapter_n);
+
+        let num_adapters = if system_config.memory_config.access_adapters_enabled {
+            log2_strict_usize(system_config.memory_config.max_access_adapter_n)
+        } else {
+            0
+        };
+
         assert_eq!(adapter_offset + num_adapters, system_config.num_airs());
         let access_adapter_arena_size_bound = records::arena_size_bound(
             &trace_heights[adapter_offset..adapter_offset + num_adapters],

crates/vm/src/system/memory/online.rs

@@ -580,6 +580,7 @@ impl TracingMemory {
         if header.block_size == header.lowest_block_size {
             return;
         }
+        assert_eq!(1, 0);
         // SAFETY:
         // - header.address_space is validated during instruction decoding and within bounds
         // - header.pointer and header.type_size define valid memory bounds within the address space
@@ -612,7 +613,7 @@ impl TracingMemory {
         if header.block_size == header.lowest_block_size {
             return;
         }
-
+        assert_eq!(1, 0);
         let record_mut = self
             .access_adapter_records
             .alloc(AccessLayout::from_record_header(&header));

extensions/rv32im/circuit/src/base_alu/tests.rs

@@ -163,8 +163,11 @@ fn rand_rv32_alu_test(opcode: BaseAluOpcode, num_ops: usize) {
     // TODO(AG): make a more meaningful test for memory accesses
     tester.write(2, 1024, [F::ONE; 4]);
     tester.write(2, 1028, [F::ONE; 4]);
-    let sm = tester.read(2, 1024);
-    assert_eq!(sm, [F::ONE; 8]);
+    // Avoid wider-than-min-block accesses when access adapters are disabled
+    let sm1 = tester.read(2, 1024);
+    let sm2 = tester.read(2, 1028);
+    assert_eq!(sm1, [F::ONE; 4]);
+    assert_eq!(sm2, [F::ONE; 4]);
 
     for _ in 0..num_ops {
         set_and_execute(
@@ -201,8 +204,11 @@ fn rand_rv32_alu_test_persistent(opcode: BaseAluOpcode, num_ops: usize) {
     // TODO(AG): make a more meaningful test for memory accesses
     tester.write(2, 1024, [F::ONE; 4]);
     tester.write(2, 1028, [F::ONE; 4]);
-    let sm = tester.read(2, 1024);
-    assert_eq!(sm, [F::ONE; 8]);
+    // Avoid wider-than-min-block accesses when access adapters are disabled
+    let sm1 = tester.read(2, 1024);
+    let sm2 = tester.read(2, 1028);
+    assert_eq!(sm1, [F::ONE; 4]);
+    assert_eq!(sm2, [F::ONE; 4]);
 
     for _ in 0..num_ops {
         set_and_execute(

extensions/rv32im/circuit/src/loadstore/tests.rs

@@ -10,7 +10,7 @@ use openvm_circuit::{
     },
 };
 use openvm_circuit_primitives::var_range::VariableRangeCheckerChip;
-use openvm_instructions::{instruction::Instruction, riscv::RV32_REGISTER_AS, LocalOpcode};
+use openvm_instructions::{instruction::Instruction, riscv::RV32_REGISTER_AS, LocalOpcode, NATIVE_AS};
 use openvm_rv32im_transpiler::Rv32LoadStoreOpcode::{self, *};
 use openvm_stark_backend::{
     p3_air::BaseAir,
@@ -131,7 +131,8 @@ fn set_and_execute<RA: Arena, E: PreflightExecutor<F, RA>>(
     let mem_as = mem_as.unwrap_or(if is_load {
         2
     } else {
-        *[2, 3, 4].choose(rng).unwrap()
+        // Avoid Native AS while access adapters are disabled.
+        *[2, 3].choose(rng).unwrap()
     });
 
     let shift_amount = ptr_val % 4;
@@ -215,10 +216,13 @@ fn rand_loadstore_test(opcode: Rv32LoadStoreOpcode, num_ops: usize) {
     let mut rng = create_seeded_rng();
     let mut mem_config = MemoryConfig::default();
     mem_config.addr_spaces[RV32_REGISTER_AS as usize].num_cells = 1 << 29;
+    mem_config.addr_spaces[NATIVE_AS as usize].num_cells = 0;
     if [STOREW, STOREB, STOREH].contains(&opcode) {
         mem_config.addr_spaces[PUBLIC_VALUES_AS as usize].num_cells = 1 << 29;
     }
-    let mut tester = VmChipTestBuilder::volatile(mem_config);
+    // Use persistent memory so initial block size matches the 4-byte alignment and
+    // avoids access-adapter split/merge paths when adapters are disabled.
+    let mut tester = VmChipTestBuilder::persistent(mem_config);
     let mut harness = create_harness(&mut tester);
 
     for _ in 0..num_ops {
@@ -268,10 +272,12 @@ fn run_negative_loadstore_test(
     let mut rng = create_seeded_rng();
     let mut mem_config = MemoryConfig::default();
     mem_config.addr_spaces[RV32_REGISTER_AS as usize].num_cells = 1 << 29;
+    mem_config.addr_spaces[NATIVE_AS as usize].num_cells = 0;
     if [STOREW, STOREB, STOREH].contains(&opcode) {
         mem_config.addr_spaces[PUBLIC_VALUES_AS as usize].num_cells = 1 << 29;
     }
-    let mut tester = VmChipTestBuilder::volatile(mem_config);
+    // Use persistent memory so the min block size matches alignment without needing adapters.
+    let mut tester = VmChipTestBuilder::persistent(mem_config);
     let mut harness = create_harness(&mut tester);
 
     set_and_execute(

extensions/rv32im/tests/src/lib.rs

@@ -33,7 +33,7 @@ mod tests {
     fn test_rv32im_config() -> Rv32ImConfig {
         Rv32ImConfig {
             rv32i: Rv32IConfig {
-                system: test_system_config(),
+                system: test_system_config().without_access_adapters(),
                 ..Default::default()
             },
             ..Default::default()