What is the SYCL code compilation flow on RISC-V CPU?

[TJU-PanYizhe]

I had llvm(this project) and oneapi-construction-kit installed on my RISC-V CPU hardware.

• OCK here is to provide OpenCL implementation for RISC-V CPU.

clinfo and sycl-ls output as below:

For example:

main.cpp

#include <sycl/sycl.hpp>
#include <vector>
#include <iostream>
using namespace sycl;
using namespace std;
constexpr int N = 16;
int main()
{
    cpu_selector d_selector;
    queue q(d_selector);
    vector<int> v(N);
    {
        buffer buf(v);
        q.submit([&](handler &h)
                 {
            accessor a(buf, h, write_only);
            h.parallel_for(N, [=](auto i)
                           { a[i] = i; }); })
            .wait();
    }
    for (int i = 0; i < N; i++)
        cout << v[i] << " ";
    cout << "\n";
    return 0;
}

# compile and execute command
clang++ -fsycl main.cpp -o main
./main

Output is as below:

What is the exactly SYCL code compilation flow and execution process on RISC-V CPU?

1. Code is splited into two parts, host code and device code, respectively.
2. Host code is compiled with integration header by host compiler.
3. Device code is compiled by device compiler and is translated into LLVM IR.
4. llvm-spirv converts the LLVM IR of device code to SPIR-V.
5. Device compiler then compile the SPIR-V to target binary or wrap the SPIR-V to the object file of host code.
6. Executable binary file is generated.

During execution:

1. If JIT is enabled, the SPIR-V needs to be compiled by device compiler. In this scenario, device compiler find OpenCL environment as mentioned. So SPIR-V is translated to OpenCL code then the rest of the compilation is done by OpenCL runtime?
2. If AOT is enabled, the binary can run directly.

• Host and device are the same RISC-V CPU in this scenario. Therefore host compiler and device compiler are the same?
• How to set the mode of compilation, AOT or JIT? Is JIT enabled in default?

Please correct me if I was wrong. Thanks a lot!

[AlexeySachkov]

Hi @TJU-PanYizhe,

What is the exactly SYCL code compilation flow and execution process on RISC-V CPU?

Steps that you describe here are correct. Note that SYCL toolchain is quite generic, so this flow is the same for every device.

If JIT is enabled, the SPIR-V needs to be compiled by device compiler. In this scenario, device compiler find OpenCL environment as mentioned. So SPIR-V is translated to OpenCL code then the rest of the compilation is done by OpenCL runtime?

Correct

If AOT is enabled, the binary can run directly.

Note that an OpenCL program object is still created in this flow and it is managed by the corresponding OpenCL implementation. There could still be some post-processing involved even for AOT binaries - that depends on implementation details of a low-level backend that you use (i.e. specific OpenCL implementation)

Host and device are the same RISC-V CPU in this scenario. Therefore host compiler and device compiler are the same?

At SYCL level, those compilers are technically the same clang, but launched with different flags and we always have two separate clang invocations: one for host program, another for device part of the program. Device clang is invoked with some extra flags to enable different optimization pipeline, enforcing of SYCL device code restrictions and other things.

How to set the mode of compilation, AOT or JIT? Is JIT enabled in default?

JIT is default flow. Selection between AOT and JIT happens through -fsycl-targets command line option. spir64 value means JIT (and it is implicitly set by default). You can pass a comma-separated list of targets there to select AOT targets or even enable both JIT & AOT at the same time (to be able to fallback to JIT if you ran your application on a target you have not AOT-compiled for).

Our AOT compiler for CPUs is a handwritten OpenCL app which does a regular JIT compilation and grabs it results, you can find it sources here: https://github.com/intel/llvm/tree/sycl/opencl/opencl-aot Even though we have only been testing it for x86 targets here at intel/llvm, it should be generic enough to work for any OpenCL implementation.

According to our Users Manual, you need to specify spir64_x86_64 target in -fsycl-targets to enable AOT compilation for CPU.