SystemVerilog: sequence and property ports

This adds SV sequence and property ports.

Author: kroening

regression/verilog/property/property_port1.desc

@@ -0,0 +1,8 @@
+CORE
+property_port1.sv
+
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring
+--

regression/verilog/property/property_port1.sv

@@ -0,0 +1,11 @@
+module main;
+
+  wire [31:0] x = 10;
+
+  property is_ten(something);
+    something == 10
+  endproperty : is_ten
+
+  assert property (is_ten(x));
+
+endmodule

src/verilog/parser.y

@@ -794,7 +794,7 @@ checker_port_list_opt:
 checker_port_list:
 	  checker_port_item
 		{ init($$); mts($$, $1); }
-	| checker_port_list checker_port_item
+	| checker_port_list ',' checker_port_item
 		{ $$ = $1; mts($$, $2); }
 	;
 
@@ -2515,6 +2515,7 @@ property_declaration:
           TOK_ENDPROPERTY property_identifier_opt
 		{ init($$, ID_verilog_property_declaration);
 		  stack_expr($$).set(ID_base_name, stack_expr($2).id());
+		  stack_expr($$).set(ID_ports, stack_expr($3));
 		  mto($$, $5); }
         ;
 
@@ -2526,27 +2527,53 @@ property_identifier_opt:
 property_port_list_paren_opt:
 	  /* optional */
 	| '(' property_port_list_opt ')'
+		{ $$ = $2; }
 	;
 
 property_port_list_opt:
 	  /* optional */
+		{ init($$); }
 	| property_port_list
 	;
 
 property_port_list:
 	  property_port_item
+		{ init($$); mts($$, $1); }
 	| property_port_list_opt ',' property_port_item
+		{ $$ = $1; mts($$, $3); }
 	;
 
 property_port_item:
-	  attribute_instance_brace property_formal_type formal_port_identifier variable_dimension_brace
+	  attribute_instance_brace
+	  property_formal_type
+	  formal_port_identifier
+	  variable_dimension_brace
+	  property_actual_arg_opt
+		{
+		  init($$, ID_decl);
+		  addswap($$, ID_type, $2);
+		  addswap($3, ID_type, $4);
+		  mto($$, $3); /* declarator */
+		  addswap($$, ID_value, $5);
+		}
 	;
 
 property_formal_type:
 	  sequence_formal_type
 	| TOK_PROPERTY
 	;
 
+property_actual_arg_opt:
+	  /* Optional */
+		{ init($$, ID_nil); }
+	| '=' property_actual_arg
+		{ $$ = $2; }
+	;
+
+property_actual_arg:
+	  property_expr
+	;
+
 property_spec:
 	  clocking_event TOK_DISABLE TOK_IFF '(' expression ')' property_expr
 		{ init($$, ID_sva_disable_iff); mto($$, $5); mto($$, $7); }
@@ -2556,7 +2583,7 @@ property_spec:
 	;
 
 sequence_formal_type:
-	  data_type
+	  data_type_or_implicit
 	| TOK_SEQUENCE
 		{ init($$, ID_verilog_sequence); }
 	| TOK_UNTYPED
@@ -2723,12 +2750,33 @@ sequence_port_list_opt:
 sequence_port_list:
 	  sequence_port_item
 		{ init($$); mto($$, $1); }
-	| sequence_port_list sequence_port_item
+	| sequence_port_list ',' sequence_port_item
 		{ $$=$1; mto($$, $2); }
 	;
 
 sequence_port_item:
+	  attribute_instance_brace
+	  sequence_formal_type
 	  formal_port_identifier
+	  variable_dimension_brace
+	  sequence_actual_arg_opt
+		{
+		  init($$, ID_decl);
+		  addswap($$, ID_type, $2);
+		  addswap($3, ID_type, $4);
+		  mto($$, $3); /* declarator */
+		  addswap($$, ID_value, $5);
+		}
+	;
+
+sequence_actual_arg_opt:
+	  /* Optional */
+		{ init($$, ID_nil); }
+	| sequence_actual_arg
+	;
+
+sequence_actual_arg:
+	  sequence_expr
 	;
 
 sequence_identifier_opt: