Verilog: test for non-constant parameter

Author: kroening

regression/verilog/modules/parameters10.desc

@@ -0,0 +1,8 @@
+CORE
+parameters10.v
+--bound 0
+^file .* line 6: expected constant expression, but got `main\.x'$
+^EXIT=2$
+^SIGNAL=0$
+--
+^warning: ignoring

regression/verilog/modules/parameters10.v

@@ -0,0 +1,8 @@
+module main;
+
+  wire x;
+
+  // x is not a constant
+  parameter p = x;
+
+endmodule