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Merge pull request #777 from diffblue/implicit-net-port
Verilog: fix for implicit nets for port connections
2 parents b72f0c4 + 4f02822 commit b970dd2

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4 files changed

+17
-8
lines changed

4 files changed

+17
-8
lines changed
Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,11 @@
11
module main;
22

3-
// implicit nets are allowed in the port connection list of a module
3+
// Implicit nets are allowed in the port connection list of a module.
4+
// The type of the implicit net is _not_ the type of the port,
5+
// but an "implicit scalar net of default net type".
46
and [3:0] (O, A, B);
57

68
always assert final (O == (A & B));
7-
always assert final ($bits(O) == 4);
9+
always assert final ($bits(O) == 1);
810

911
endmodule

regression/verilog/nets/implicit6.sv

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2,9 +2,11 @@ module main;
22

33
parameter P = 2;
44

5-
// implicit nets are allowed in the port connection list of a module
5+
// Implicit nets are allowed in the port connection list of a module.
6+
// The type of the implicit net is _not_ the type of the port,
7+
// but an "implicit scalar net of default net type".
68
and [P:0] (O, A, B);
79

8-
assert final ($bits(O) == P+1);
10+
assert final ($bits(O) == 1);
911

1012
endmodule

regression/verilog/nets/implicit7.sv

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -5,10 +5,11 @@ module main;
55
// implicit nets are allowed in the port connection list of a module
66
sub #(P) my_sub(x);
77

8-
// The type of the implict net could be used to define another parameter
8+
// The type of the implicit net is _not_ the type of the port,
9+
// but an "implicit scalar net of default net type".
910
parameter Q = $bits(x);
1011

11-
assert final (Q == P + 1);
12+
assert final (Q == 1);
1213

1314
endmodule
1415

src/verilog/verilog_typecheck.cpp

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -60,7 +60,9 @@ void verilog_typecheckt::typecheck_port_connection(
6060
// used in a port connection.
6161
if(op.id() == ID_symbol)
6262
{
63-
op = convert_symbol(to_symbol_expr(op), port.type());
63+
// The type of the implicit net is _not_ the type of the port,
64+
// but an "implicit scalar net of default net type".
65+
op = convert_symbol(to_symbol_expr(op), bool_typet{});
6466
}
6567
else
6668
{
@@ -242,7 +244,9 @@ void verilog_typecheckt::typecheck_builtin_port_connections(
242244
// used in a port connection.
243245
if(connection.id() == ID_symbol)
244246
{
245-
connection = convert_symbol(to_symbol_expr(connection), type);
247+
// The type of the implicit net is _not_ the type of the port,
248+
// but an "implicit scalar net of default net type".
249+
connection = convert_symbol(to_symbol_expr(connection), bool_typet{});
246250
}
247251
else
248252
{

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