We read every piece of feedback, and take your input very seriously.
To see all available qualifiers, see our documentation.
There was an error while loading. Please reload this page.
1 parent 35e5313 commit 9f54b2fCopy full SHA for 9f54b2f
regression/verilog/elaboration/type_operator.desc
@@ -1,9 +1,8 @@
1
-KNOWNBUG
+CORE
2
type_operator.sv
3
--bound 0
4
^EXIT=0$
5
^SIGNAL=0$
6
--
7
^warning: ignoring
8
9
-We need to add support for the System Verilog type operator.
0 commit comments