Merge pull request #688 from diffblue/use-expr2verilog-resultt

Verilog: use `resultt` for methods in `expr2verilogt`

Author: tautschnig

regression/verilog/SVA/eventually1.desc

@@ -1,7 +1,7 @@
 CORE
 eventually1.sv
 --bound 20
-^\[main\.p0\] always main\.counter == 1 implies \(eventually \[1:2\] main\.counter == 3\): PROVED up to bound 20$
+^\[main\.p0\] always \(main\.counter == 1 implies \(eventually \[1:2\] main\.counter == 3\)\): PROVED up to bound 20$
 ^EXIT=0$
 ^SIGNAL=0$
 --

regression/verilog/SVA/sva_and1.desc

@@ -1,9 +1,9 @@
 CORE
 sva_and1.sv
 --bound 0
-^\[main\.p0\] always 1 and 1: PROVED up to bound 0$
-^\[main\.p1\] always 1 and 0: REFUTED$
-^\[main\.p2\] always 1 and 32'b0000000000000000000000000000000x: PROVED up to bound 0$
+^\[main\.p0\] always \(1 and 1\): PROVED up to bound 0$
+^\[main\.p1\] always \(1 and 0\): REFUTED$
+^\[main\.p2\] always \(1 and 32'b0000000000000000000000000000000x\): PROVED up to bound 0$
 ^EXIT=10$
 ^SIGNAL=0$
 --

regression/verilog/SVA/sva_iff1.desc

@@ -1,9 +1,9 @@
 CORE
 sva_iff1.sv
 --bound 0
-^\[main\.p0\] always 1 iff 1: PROVED up to bound 0$
-^\[main\.p1\] always 1 iff 0: REFUTED$
-^\[main\.p2\] always 1 iff 32'b0000000000000000000000000000000x: PROVED up to bound 0$
+^\[main\.p0\] always \(1 iff 1\): PROVED up to bound 0$
+^\[main\.p1\] always \(1 iff 0\): REFUTED$
+^\[main\.p2\] always \(1 iff 32'b0000000000000000000000000000000x\): PROVED up to bound 0$
 ^EXIT=10$
 ^SIGNAL=0$
 --

regression/verilog/SVA/sva_implies1.desc

@@ -1,9 +1,9 @@
 CORE
 sva_implies1.sv
 --bound 0
-^\[main\.p0\] always 1 implies 1: PROVED up to bound 0$
-^\[main\.p1\] always 1 implies 0: REFUTED$
-^\[main\.p2\] always 1 implies 32'b0000000000000000000000000000000x: PROVED up to bound 0$
+^\[main\.p0\] always \(1 implies 1\): PROVED up to bound 0$
+^\[main\.p1\] always \(1 implies 0\): REFUTED$
+^\[main\.p2\] always \(1 implies 32'b0000000000000000000000000000000x\): PROVED up to bound 0$
 ^EXIT=10$
 ^SIGNAL=0$
 --