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Merge pull request #725 from diffblue/verilog-increasing
Verilog: big_endian -> increasing
2 parents 870c537 + 2769813 commit 78bb686

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7 files changed

+28
-24
lines changed

7 files changed

+28
-24
lines changed

src/hw_cbmc_irep_ids.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -70,7 +70,7 @@ IREP_ID_ONE(sva_not)
7070
IREP_ID_ONE(sva_or)
7171
IREP_ID_ONE(module_instance)
7272
IREP_ID_TWO(C_offset, #offset)
73-
IREP_ID_TWO(C_big_endian, #big_endian)
73+
IREP_ID_TWO(C_increasing, #increasing)
7474
IREP_ID_ONE(ports)
7575
IREP_ID_ONE(inst)
7676
IREP_ID_ONE(Verilog)

src/trans-netlist/trans_trace.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -656,7 +656,7 @@ static std::string vcd_suffix(
656656
left_bound = offset;
657657
right_bound = left_bound+width-1;
658658

659-
if(!type.get_bool(ID_C_big_endian))
659+
if(!type.get_bool(ID_C_increasing))
660660
std::swap(left_bound, right_bound);
661661

662662
return "["+integer2string(left_bound)+":"+integer2string(right_bound)+"]";

src/verilog/expr2verilog.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1623,7 +1623,7 @@ std::string expr2verilogt::convert(const typet &type)
16231623
else if(type.id()==ID_unsignedbv || type.id()==ID_signedbv)
16241624
{
16251625
unsigned width=to_bitvector_type(type).get_width();
1626-
bool big_endian = type.get_bool(ID_C_big_endian);
1626+
bool increasing = type.get_bool(ID_C_increasing);
16271627
unsigned offset=atoi(type.get(ID_C_offset).c_str());
16281628

16291629
if(width!=0)
@@ -1636,7 +1636,7 @@ std::string expr2verilogt::convert(const typet &type)
16361636

16371637
dest+='[';
16381638

1639-
if(big_endian)
1639+
if(increasing)
16401640
{
16411641
dest+=std::to_string(offset);
16421642
dest += ":";

src/verilog/verilog_elaborate_type.cpp

Lines changed: 5 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -39,19 +39,19 @@ array_typet verilog_typecheck_exprt::convert_unpacked_array_type(
3939
const exprt &size_expr = static_cast<const exprt &>(src.find(ID_size));
4040

4141
mp_integer size, offset;
42-
bool big_endian;
42+
bool increasing;
4343

4444
if(range_expr.is_not_nil())
4545
{
4646
// these may be negative
4747
auto range = convert_range(range_expr);
48-
big_endian = (range.lsb > range.msb);
48+
increasing = range.increasing();
4949
size = range.length();
5050
offset = range.smallest_index();
5151
}
5252
else if(size_expr.is_not_nil())
5353
{
54-
big_endian = false;
54+
increasing = false;
5555
size = convert_integer_constant_expression(size_expr);
5656
offset = 0;
5757
if(size < 0)
@@ -72,7 +72,7 @@ array_typet verilog_typecheck_exprt::convert_unpacked_array_type(
7272
const exprt final_size_expr = from_integer(size, integer_typet());
7373
auto result = array_typet{element_type, final_size_expr};
7474
result.set(ID_offset, from_integer(offset, integer_typet()));
75-
result.set(ID_C_big_endian, big_endian);
75+
result.set(ID_C_increasing, increasing);
7676

7777
return result;
7878
}
@@ -99,8 +99,6 @@ typet verilog_typecheck_exprt::convert_packed_array_type(
9999

100100
auto range = convert_range(range_expr);
101101

102-
bool big_endian = (range.lsb > range.msb);
103-
104102
mp_integer width = range.length();
105103
mp_integer offset = range.smallest_index();
106104

@@ -122,7 +120,7 @@ typet verilog_typecheck_exprt::convert_packed_array_type(
122120

123121
dest.add_source_location() = source_location;
124122
dest.set_width(width.to_ulong());
125-
dest.set(ID_C_big_endian, big_endian);
123+
dest.set(ID_C_increasing, range.increasing());
126124
dest.set(ID_C_offset, integer2string(offset));
127125

128126
return std::move(dest).with_source_location(source_location);

src/verilog/verilog_typecheck_expr.cpp

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -484,7 +484,7 @@ constant_exprt verilog_typecheck_exprt::left(const exprt &expr)
484484
type.id() == ID_bool)
485485
{
486486
auto offset = type.get_int(ID_C_offset);
487-
if(type.get_bool(ID_C_big_endian))
487+
if(type.get_bool(ID_C_increasing))
488488
return offset;
489489
else
490490
return offset + get_width(type) - 1;
@@ -493,7 +493,7 @@ constant_exprt verilog_typecheck_exprt::left(const exprt &expr)
493493
{
494494
auto offset = numeric_cast_v<mp_integer>(
495495
to_constant_expr(static_cast<const exprt &>(type.find(ID_offset))));
496-
if(type.get_bool(ID_C_big_endian))
496+
if(type.get_bool(ID_C_increasing))
497497
return offset;
498498
else
499499
{
@@ -534,7 +534,7 @@ constant_exprt verilog_typecheck_exprt::right(const exprt &expr)
534534
type.id() == ID_bool)
535535
{
536536
auto offset = type.get_int(ID_C_offset);
537-
if(type.get_bool(ID_C_big_endian))
537+
if(type.get_bool(ID_C_increasing))
538538
return offset + get_width(type) - 1;
539539
else
540540
return offset;
@@ -543,7 +543,7 @@ constant_exprt verilog_typecheck_exprt::right(const exprt &expr)
543543
{
544544
auto offset = numeric_cast_v<mp_integer>(
545545
to_constant_expr(static_cast<const exprt &>(type.find(ID_offset))));
546-
if(type.get_bool(ID_C_big_endian))
546+
if(type.get_bool(ID_C_increasing))
547547
{
548548
return offset +
549549
numeric_cast_v<mp_integer>(
@@ -608,7 +608,7 @@ constant_exprt verilog_typecheck_exprt::increment(const exprt &expr)
608608
type.id() == ID_verilog_unsignedbv || type.id() == ID_verilog_signedbv ||
609609
type.id() == ID_array)
610610
{
611-
if(type.get_bool(ID_C_big_endian))
611+
if(type.get_bool(ID_C_increasing))
612612
return -1;
613613
else
614614
return 1;
@@ -2516,7 +2516,7 @@ exprt verilog_typecheck_exprt::convert_bit_select_expr(binary_exprt expr)
25162516

25172517
op1_int -= offset;
25182518

2519-
if(op0.type().get_bool(ID_C_big_endian))
2519+
if(op0.type().get_bool(ID_C_increasing))
25202520
op1_int = width - op1_int - 1;
25212521

25222522
expr.op1() = from_integer(op1_int, natural_typet());
@@ -2529,7 +2529,7 @@ exprt verilog_typecheck_exprt::convert_bit_select_expr(binary_exprt expr)
25292529
minus_exprt{expr.op1(), from_integer(offset, expr.op1().type())};
25302530
}
25312531

2532-
if(op0.type().get_bool(ID_C_big_endian))
2532+
if(op0.type().get_bool(ID_C_increasing))
25332533
{
25342534
expr.op1() =
25352535
minus_exprt{from_integer(width - 1, expr.op1().type()), expr.op1()};

src/verilog/verilog_typecheck_expr.h

Lines changed: 9 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -79,13 +79,19 @@ class verilog_typecheck_exprt:public verilog_typecheck_baset
7979

8080
mp_integer msb, lsb;
8181

82-
/// return true iff the bit with the higest index
83-
/// is the most significant bit
84-
bool highest_index_is_msb() const
82+
/// Return true iff the bit with the higest index
83+
/// is the most significant bit, i.e., the vector
84+
/// is indexed left-to-right with decreasing indices.
85+
bool decreasing() const
8586
{
8687
return msb >= lsb;
8788
}
8889

90+
bool increasing() const
91+
{
92+
return !decreasing();
93+
}
94+
8995
mp_integer length() const
9096
{
9197
if(msb >= lsb)

src/vhdl/expr2vhdl.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -745,7 +745,7 @@ std::string expr2vhdlt::convert(const typet &type)
745745
else if(type.id()==ID_unsignedbv || type.id()==ID_signedbv)
746746
{
747747
unsigned width=to_bitvector_type(type).get_width();
748-
bool little_endian = type.get_bool(ID_C_big_endian);
748+
bool increasing = type.get_bool(ID_C_increasing);
749749
unsigned offset=atoi(type.get(ID_C_offset).c_str());
750750

751751
if(width!=0)
@@ -757,8 +757,8 @@ std::string expr2vhdlt::convert(const typet &type)
757757
dest="signed bv";
758758

759759
dest+='[';
760-
761-
if(little_endian)
760+
761+
if(!increasing)
762762
{
763763
dest+=std::to_string(offset+width-1);
764764
dest+=":";

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