@@ -144,10 +144,7 @@ exprt verilog_synthesist::synth_expr(exprt expr, symbol_statet symbol_state)
144144
145145 // Construct the extractbits expression
146146 return extractbits_exprt{
147- src_padded,
148- from_integer (op1, integer_typet ()),
149- from_integer (op2, integer_typet ()),
150- expr.type ()}
147+ src_padded, from_integer (op2, integer_typet ()), expr.type ()}
151148 .with_source_location (expr.source_location ());
152149 }
153150 else if (
@@ -187,10 +184,7 @@ exprt verilog_synthesist::synth_expr(exprt expr, symbol_statet symbol_state)
187184 }
188185
189186 return extractbits_exprt{
190- std::move (src),
191- from_integer (top, integer_typet{}),
192- from_integer (bottom, integer_typet{}),
193- expr.type ()}
187+ std::move (src), from_integer (bottom, integer_typet{}), expr.type ()}
194188 .with_source_location (expr);
195189 }
196190 else
@@ -203,10 +197,7 @@ exprt verilog_synthesist::synth_expr(exprt expr, symbol_statet symbol_state)
203197 auto src_shifted = lshr_exprt (src, index_adjusted);
204198
205199 return extractbits_exprt{
206- std::move (src_shifted),
207- from_integer (width - 1 , integer_typet{}),
208- from_integer (0 , integer_typet{}),
209- expr.type ()}
200+ std::move (src_shifted), from_integer (0 , integer_typet{}), expr.type ()}
210201 .with_source_location (expr);
211202 }
212203 }
@@ -507,17 +498,11 @@ void verilog_synthesist::assignment_rec(
507498 else if (it->type ().id ()==ID_signedbv ||
508499 it->type ().id ()==ID_unsignedbv)
509500 {
510- auto width = get_width (it->type ());
511-
512- auto offset_constant2 =
513- from_integer (offset + width - 1 , natural_typet{});
514-
515- // extractbits requires that upper >= lower, i.e. op1 >= op2
516- extractbits_exprt bit_extract (rhs, offset_constant2, offset_constant,
517- it->type ());
501+ extractbits_exprt bit_extract (rhs, offset_constant, it->type ());
518502
519503 assignment_rec (*it, bit_extract, blocking);
520504
505+ auto width = get_width (it->type ());
521506 offset+=width;
522507 }
523508 else
@@ -2006,9 +1991,7 @@ void verilog_synthesist::synth_force_rec(
20061991 it->type ().id ()==ID_unsignedbv)
20071992 {
20081993 auto width = get_width (it->type ());
2009- auto sum_constant = from_integer (offset + width - 1 , natural_typet{});
2010- extractbits_exprt bit_extract (
2011- rhs, offset_constant, sum_constant, it->type ());
1994+ extractbits_exprt bit_extract (rhs, offset_constant, it->type ());
20121995 synth_force_rec (*it, bit_extract);
20131996 offset+=width;
20141997 }
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