Merge pull request #746 from diffblue/eventually4

SVA: KNOWNBUG test for `s_eventually`

Author: tautschnig

regression/verilog/SVA/eventually4.desc

@@ -0,0 +1,9 @@
+KNOWNBUG
+eventually4.sv
+--bound 2
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring
+--
+Property gives counterexample but should pass.

regression/verilog/SVA/eventually4.sv

@@ -0,0 +1,6 @@
+module main(input a);
+
+  // should pass for any bound
+  assert property ((s_eventually !a) or (always a));
+
+endmodule