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lines changed Original file line number Diff line number Diff line change 66* Verilog: allow indexed part select
77* word-level BMC: fix for F/s_eventually and U/s_until
88* IC3: liveness to safety translation
9+ * Assumptions are not disabled when using --property
910
1011# EBMC 5.2
1112
Original file line number Diff line number Diff line change 11CORE
2- main .v
2+ assume1 .v
33--module main --bound 3 --aig --vl2smv-extensions
44^\[main\.property\.a1\] assume always 10 <= main\.a && main\.a <= 100: ASSUMED$
55^\[main\.property\.p1\] always main\.a != 200: PROVED up to bound 3$
File renamed without changes.
Original file line number Diff line number Diff line change 1+ CORE
2+ assume2.sv
3+ --bound 0 --property main.p1
4+ ^\[main\.a1\] assume always 10 <= main\.a && main\.a <= 100: ASSUMED$
5+ ^\[main\.p1\] always main\.a != 200: PROVED up to bound 0$
6+ ^EXIT=0$
7+ ^SIGNAL=0$
Original file line number Diff line number Diff line change 1+ module main (input [31 : 0 ] a);
2+
3+ a1: assume final (10 <= a && a<= 100 );
4+
5+ p1 : assert final (a!= 200 );
6+
7+ // would fail
8+ p2 : assert final (a!= 20 );
9+
10+ endmodule
Original file line number Diff line number Diff line change @@ -110,8 +110,10 @@ bool ebmc_propertiest::select_property(
110110 {
111111 std::string property = cmdline.get_value (" property" );
112112
113+ // disable all assertions (not: assumptions)
113114 for (auto &p : properties)
114- p.status = propertyt::statust::DISABLED;
115+ if (!p.is_assumed ())
116+ p.status = propertyt::statust::DISABLED;
115117
116118 bool found = false ;
117119
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