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Verilog: add classes, interfaces, packages to parse tree
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13 files changed

+374
-66
lines changed

13 files changed

+374
-66
lines changed

‎regression/verilog/class/class1.desc‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
CORE
22
class1.sv
3-
--bound 0 --module main
4-
^no properties$
5-
^EXIT=10$
3+
--show-parse
4+
^Class: myClass$
5+
^EXIT=0$
66
^SIGNAL=0$
77
--

‎regression/verilog/interface/interface1.desc‎

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,7 @@
1+
CORE
2+
interface1.sv
3+
--show-parse
4+
^Interface: myInterface$
5+
^EXIT=0$
6+
^SIGNAL=0$
7+
--

‎regression/verilog/interface/interface1.sv‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,5 @@
1+
interface myInterface;
2+
endinterface
3+
4+
module main;
5+
endmodule

‎regression/verilog/packages/package1.desc‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
CORE
22
package1.sv
3-
--bound 0 --module main
4-
^no properties$
5-
^EXIT=10$
3+
--show-parse
4+
^Pacakge: my_pkg$
5+
^EXIT=0$
66
^SIGNAL=0$
77
--

‎src/hw_cbmc_irep_ids.h‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -229,8 +229,13 @@ IREP_ID_ONE(specify)
229229
IREP_ID_ONE(x)
230230
IREP_ID_ONE(verilog_empty_item)
231231
IREP_ID_ONE(verilog_import_item)
232+
IREP_ID_ONE(verilog_interface)
233+
IREP_ID_ONE(verilog_class)
232234
IREP_ID_ONE(verilog_module)
235+
IREP_ID_ONE(verilog_package)
233236
IREP_ID_ONE(verilog_package_import)
237+
IREP_ID_ONE(verilog_program)
238+
IREP_ID_ONE(verilog_udp)
234239
IREP_ID_ONE(module_source)
235240
IREP_ID_ONE(module_items)
236241
IREP_ID_ONE(parameter_port_list)

‎src/verilog/parser.y‎

Lines changed: 74 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -616,9 +616,13 @@ description:
616616
module_declaration
617617
{ PARSER.parse_tree.add_item(stack_expr($1)); }
618618
| udp_declaration
619+
{ PARSER.parse_tree.add_item(stack_expr($1)); }
619620
| interface_declaration
621+
{ PARSER.parse_tree.add_item(stack_expr($1)); }
620622
| program_declaration
623+
{ PARSER.parse_tree.add_item(stack_expr($1)); }
621624
| package_declaration
625+
{ PARSER.parse_tree.add_item(stack_expr($1)); }
622626
| attribute_instance_brace package_item
623627
{ add_attributes($2, $1);
624628
PARSER.parse_tree.add_item(stack_expr($2)); }
@@ -713,9 +717,31 @@ module_keyword:
713717
;
714718

715719
interface_declaration:
716-
TOK_INTERFACE TOK_ENDINTERFACE
720+
interface_nonansi_header
721+
timeunits_declaration_opt
722+
interface_item_brace
723+
TOK_ENDINTERFACE
724+
{ $$ = $1; }
717725
;
718726

727+
interface_nonansi_header:
728+
attribute_instance_brace
729+
TOK_INTERFACE
730+
lifetime_opt
731+
interface_identifier
732+
{
733+
init($$, ID_verilog_interface);
734+
stack_expr($$).set(ID_base_name, stack_expr($4).id());
735+
}
736+
package_import_declaration_brace
737+
parameter_port_list_opt
738+
list_of_ports_opt
739+
';'
740+
{
741+
$$ = $5;
742+
}
743+
;
744+
719745
program_declaration:
720746
TOK_PROGRAM TOK_ENDPROGRAM
721747
;
@@ -724,32 +750,42 @@ class_declaration:
724750
TOK_CLASS class_identifier
725751
';'
726752
{
727-
$$ = $1;
753+
init($$, ID_verilog_class);
754+
stack_expr($$).set(ID_base_name, stack_expr($2).id());
728755
push_scope(stack_expr($2).id(), "::");
729756
}
730757
class_item_brace
731758
TOK_ENDCLASS
732759
{
760+
$$ = $4;
733761
pop_scope();
734762
}
735763
;
736764

737765
package_declaration:
738766
attribute_instance_brace TOK_PACKAGE
767+
{ init($$, ID_verilog_package); }
739768
lifetime_opt
740769
package_identifier ';'
741770
{
742-
$$ = $1;
743-
push_scope(stack_expr($4).id(), "::");
771+
push_scope(stack_expr($5).id(), "::");
744772
}
745773
timeunits_declaration_opt
746774
package_item_brace
747-
TOK_ENDPACKAGE
775+
TOK_ENDPACKAGE endpackage_identifier_opt
748776
{
749777
pop_scope();
778+
$$ = $3;
779+
addswap($$, ID_module_items, $9);
780+
stack_expr($$).set(ID_base_name, stack_expr($5).id());
750781
}
751782
;
752783

784+
endpackage_identifier_opt:
785+
/* Optional */
786+
| TOK_COLON package_identifier
787+
;
788+
753789
timeunits_declaration_opt:
754790
/* Optional */
755791
;
@@ -939,6 +975,38 @@ config_declaration:
939975
bind_directive:
940976
TOK_BIND
941977
;
978+
979+
// System Verilog standard 1800-2017
980+
// A.1.6 Interface items
981+
982+
interface_or_generate_item:
983+
attribute_instance_brace module_common_item
984+
| attribute_instance_brace extern_tf_declaration
985+
;
986+
987+
extern_tf_declaration:
988+
TOK_EXTERN method_prototype ';'
989+
| TOK_EXTERN TOK_FORKJOIN task_prototype ';'
990+
;
991+
992+
interface_item_brace:
993+
/* Optional */
994+
| interface_item_brace interface_item
995+
;
996+
997+
interface_item:
998+
port_declaration ';'
999+
| non_port_interface_item
1000+
;
1001+
1002+
non_port_interface_item:
1003+
generate_region
1004+
| interface_or_generate_item
1005+
| program_declaration
1006+
/* | modport_declaration */
1007+
| interface_declaration
1008+
/* | timeunits_declaration */
1009+
;
9421010

9431011
// System Verilog standard 1800-2017
9441012
// A.1.9 Class items
@@ -3920,8 +3988,7 @@ genvar_identifier: identifier;
39203988
hierarchical_parameter_identifier: hierarchical_identifier
39213989
;
39223990

3923-
interface_identifier:
3924-
;
3991+
interface_identifier: TOK_NON_TYPE_IDENTIFIER;
39253992

39263993
module_identifier: TOK_NON_TYPE_IDENTIFIER;
39273994

‎src/verilog/verilog_expr.cpp‎

Lines changed: 68 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -63,7 +63,7 @@ void verilog_module_sourcet::show(std::ostream &out) const
6363
out << '\n';
6464
}
6565

66-
static void submodules_rec(
66+
static void dependencies_rec(
6767
const verilog_module_itemt &module_item,
6868
std::vector<irep_idt> &dest)
6969
{
@@ -75,31 +75,91 @@ static void submodules_rec(
7575
else if(module_item.id() == ID_generate_block)
7676
{
7777
for(auto &sub_item : to_verilog_generate_block(module_item).module_items())
78-
submodules_rec(sub_item, dest);
78+
dependencies_rec(sub_item, dest);
7979
}
8080
else if(module_item.id() == ID_generate_if)
8181
{
8282
auto &generate_if = to_verilog_generate_if(module_item);
83-
submodules_rec(generate_if.then_case(), dest);
83+
dependencies_rec(generate_if.then_case(), dest);
8484
if(generate_if.has_else_case())
85-
submodules_rec(generate_if.else_case(), dest);
85+
dependencies_rec(generate_if.else_case(), dest);
8686
}
8787
else if(module_item.id() == ID_generate_for)
8888
{
89-
submodules_rec(to_verilog_generate_for(module_item).body(), dest);
89+
dependencies_rec(to_verilog_generate_for(module_item).body(), dest);
9090
}
9191
}
9292

93-
std::vector<irep_idt> verilog_module_sourcet::submodules() const
93+
std::vector<irep_idt> verilog_item_containert::dependencies() const
9494
{
9595
std::vector<irep_idt> result;
9696

97-
for(auto &item : module_items())
98-
submodules_rec(item, result);
97+
for(auto &item : items())
98+
dependencies_rec(item, result);
9999

100100
return result;
101101
}
102102

103+
void verilog_packaget::show(std::ostream &out) const
104+
{
105+
out << "Pacakge: " << base_name() << '\n';
106+
107+
out << " Items:\n";
108+
109+
for(auto &item : items())
110+
out << " " << item.pretty() << '\n';
111+
112+
out << '\n';
113+
}
114+
115+
void verilog_programt::show(std::ostream &out) const
116+
{
117+
out << "Program: " << base_name() << '\n';
118+
119+
out << " Items:\n";
120+
121+
for(auto &item : items())
122+
out << " " << item.pretty() << '\n';
123+
124+
out << '\n';
125+
}
126+
127+
void verilog_classt::show(std::ostream &out) const
128+
{
129+
out << "Class: " << base_name() << '\n';
130+
131+
out << " Items:\n";
132+
133+
for(auto &item : items())
134+
out << " " << item.pretty() << '\n';
135+
136+
out << '\n';
137+
}
138+
139+
void verilog_interfacet::show(std::ostream &out) const
140+
{
141+
out << "Interface: " << base_name() << '\n';
142+
143+
out << " Items:\n";
144+
145+
for(auto &item : items())
146+
out << " " << item.pretty() << '\n';
147+
148+
out << '\n';
149+
}
150+
151+
void verilog_udpt::show(std::ostream &out) const
152+
{
153+
out << "UDP: " << base_name() << '\n';
154+
155+
out << " Items:\n";
156+
157+
for(auto &item : items())
158+
out << " " << item.pretty() << '\n';
159+
160+
out << '\n';
161+
}
162+
103163
static exprt lower(const verilog_non_indexed_part_select_exprt &part_select)
104164
{
105165
auto get_width = [](const typet &t) -> mp_integer

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