diff --git a/docs/projects/adaq23875/adaq2387x_zed_block_diagram_default.svg b/docs/projects/adaq23875/adaq2387x_zed_block_diagram_default.svg new file mode 100644 index 0000000000..d2497b86bd --- /dev/null +++ b/docs/projects/adaq23875/adaq2387x_zed_block_diagram_default.svg @@ -0,0 +1,2721 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + + + + + + + + + + + Ethernet + UART + DDRx + SPI + I2C + Interrupts + + Timer + + Receive path + + MEMORY INTERCONNECT + Zed + + + FMC CONNECTOR + + + DMA + DMA_clk= 100MHz + + + LVDS INTERFACE + + ref_clk = 100MHz + + + DAC core frame + + LTC2387 CORE + + ARM (Zynq) + + + + + + + + + da_p + cnv_p + cnv_n + clk_gate + da_n + ref_clk_p + ref_clk_n + clk_p + + clk_n + + + + sampling_clk = ref_clk + sampling_clk_s + + + + + db_p + db_n + + + + dco_p + dco_n + + + + + + + + AXI_PWM_GEN + + + + ltc_clk + + pwm_0 + pwm_1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + DATAMONITORING + + + 64 + 16/18 + + + clk_s + + cnv + + + + + + + BUFG + + + IBUFGDS + + + + ad_data_clk + + + + + + + + + diff --git a/docs/projects/adaq23875/adaq2387x_zed_block_diagram_mmcm.svg b/docs/projects/adaq23875/adaq2387x_zed_block_diagram_mmcm.svg new file mode 100644 index 0000000000..ae61d22c53 --- /dev/null +++ b/docs/projects/adaq23875/adaq2387x_zed_block_diagram_mmcm.svg @@ -0,0 +1,2732 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + + + + + + + + + + + Ethernet + UART + DDRx + SPI + I2C + Interrupts + + Timer + + Receive path + + MEMORY INTERCONNECT + Zed + + + FMC CONNECTOR + + + DMA + DMA_clk= 100MHz + + + LVDS INTERFACE + + ref_clk = 100MHz + + + DAC core frame + + LTC2387 CORE + + ARM (Zynq) + + + + + + + + + da_p + cnv_p + cnv_n + clk_gate + da_n + ref_clk_p + ref_clk_n + clk_p + + clk_n + + + + ref_clk + sampling_clk + sampling_clk_s + + + + + db_p + db_n + + + + dco_p + dco_n + + + + + + + + AXI_PWM_GEN + + + + ltc_clk + + pwm_0 + pwm_1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + DATAMONITORING + + + 64 + 16/18 + + + clk_s + + cnv + + + + + + + BUFG + + + IBUFGDS + + + + ad_data_clk + + + + + + + + + diff --git a/docs/projects/adaq23875/index.rst b/docs/projects/adaq23875/index.rst new file mode 100644 index 0000000000..2f62b65a22 --- /dev/null +++ b/docs/projects/adaq23875/index.rst @@ -0,0 +1,293 @@ +.. _adaq23875: + +ADAQ23875 HDL project +================================================================================ + +Overview +------------------------------------------------------------------------------- + +The :adi:`ADAQ23875`/ :adi:`ADAQ23876`/ :adi:`ADAQ23878` provide an analog +front-end and an FMC digital interface for :adi:`LTC2387-18`/ :adi:`LTC2387-16`, +its core. It is a low noise, high speed successive approximation register (SAR) +ADC with a resolution of 18/16 bits and sampling rate up to 15MSPS. + +The ADAQ2387x family includes an on-board reference oscillator and a +retiming circuit to minimize signal-to-noise ratio (SNR) degradation due to +the FPGA additive jitter. + +In order to support high speed operations while minimizing the number of data +lines, a serial LVDS digital interface is used. It has a one-lane and two-lane +output modes, allowing the user to optimize the interface data rate for each +application, through setting a parameter. + +Supported boards +------------------------------------------------------------------------------- + +- :adi:`EVAL-ADAQ23875` +- :adi:`EVAL-ADAQ23876` +- :adi:`EVAL-ADAQ23878` + +Supported devices +------------------------------------------------------------------------------- + +- :adi:`ADAQ23875` +- :adi:`ADAQ23876` +- :adi:`ADAQ23878` +- :adi:`LTC2387-16` +- :adi:`LTC2387-18` + +Supported carriers +------------------------------------------------------------------------------- + +- `ZedBoard `__ on FMC slot + +Block design +------------------------------------------------------------------------------- + +.. warning:: + + The VADJ for the Zedboard must be set to 2.5V. + +Block diagram +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The data path and clock domains are depicted in the below diagrams: + +Default timing configuration (USE_MMCM=0) +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +.. image:: adaq2387x_zed_block_diagram_default.svg + :width: 800 + :align: center + :alt: ADAQ2387X/ZedBoard block diagram for ref_clk = sampling_clk = 100MHz + +Enhanced timing configuration (USE_MMCM=1) +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +.. image:: adaq2387x_zed_block_diagram_mmcm.svg + :width: 800 + :align: center + :alt: ADAQ2387X/ZedBoard block diagram for ref_clk = 100MHz & sampling_clk = 120Mhz + +Configuration modes +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- TWOLANES: specifies the number of lanes used + + - 1 - two-lane output mode (default) + - 0 - one-lane output mode + +- ADC_RES: resolution in bits; selects between :adi:`EVAL-ADAQ23878` (18-bit, + default) and :adi:`EVAL-ADAQ23875`/:adi:`EVAL-ADAQ23876` (16-bit) + + - 18 - 18 bits ADC resolution, :adi:`EVAL-ADAQ23878` (default) + - 16 - 16 bits ADC resoluton, :adi:`EVAL-ADAQ23875`/:adi:`EVAL-ADAQ23876` + +- USE_MMCM: specifies if a clock wizard is used to generate the sampling clock + of 120MHz, or use the default 100MHz clock directly from the on-board VCXO. + + - 1 - MMCM is used; When operating with a 120MHz sampling clock, the system + achieves the maximum supported sampling rate of 15MSPS. + - 0 - MMCM is not used (default); When operating with a 100MHz sampling + clock, the system achieves half of the maximum supported sampling rate, + which is 7.5MSPS. + +Jumper setup +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Depending on what configuration of pins is chosen on the jumpers P1, P2 and P3, +the device can act in different modes, as described below. Of course, the PD +jumper overrides the PD signal from the FPGA. It is controlled by a +one-bit-adc-dac, in software. + +- P1 - configures PD_N + + - Shorting pins 1 and 2 → PD_N = 1, device is not powered down + - Shorting pins 2 and 3 → PD_N = 0, device is powered down + +- P2 - configures TESTPAT + + - Shorting pins 1 and 2 → TESTPAT = 1, pattern testing is active + - Shorting pins 2 and 3 → TESTPAT = 0, pattern testing is inactive + +- P3 - configures TWOLANES parameter + + - Shorting pins 1 and 2 → TWOLANES = 1 (TWO LANES mode) + - Shorting pins 2 and 3 → TWOLANES = 0 (ONE LANE mode) + +Clock scheme +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- The clock architecture of the EVAL-ADAQ2387X is designed + with careful consideration to ensure low jitter and low phase noise. +- An on-board 100 MHz voltage controlled crystal oscillator (VCXO) is used to + provide the clock for the EVAL-ADAQ2387X boards and the FPGA. + It is further named as reference clock. This clock is gated and fed back to + the device as the sampling clock, on which the data was sampled. +- The DMA runs on the Zynq PS clock FCLK_CLK0 which has a frequency of 100MHz. + +CPU/Memory interconnects addresses +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The addresses are dependent on the architecture of the FPGA, having an offset +added to the base address from HDL +(see more at :ref:`architecture cpu-intercon-addr`). + +==================== =============== +Instance Zynq/Microblaze +==================== =============== +axi_ltc2387 0x44A0_0000 +axi_ltc2387_dma 0x44A3_0000 +axi_pwm_gen 0x44A6_0000 +==================== =============== + +GPIOs +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. list-table:: + :widths: 25 20 20 20 15 + :header-rows: 2 + + * - GPIO signal + - Direction + - HDL GPIO EMIO + - Software GPIO + - Software GPIO + * - + - (from FPGA view) + - + - Zynq-7000 + - Zynq MP + * - testpat_cntrl + - IN + - 32 + - 86 + - 110 + * - pd_cntrl + - IN + - 33 + - 87 + - 111 + +Interrupts +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Below are the Programmable Logic interrupts used in this project. + +================ === ========== =========== +Instance name HDL Linux Zynq Actual Zynq +================ === ========== =========== +axi_ltc2387_dma 13 57 89 +================ === ========== =========== + +Building the HDL project +------------------------------------------------------------------------------- + +The design is built upon ADI's generic HDL reference design framework. +ADI distributes the bit/elf files of these projects as part of the +:dokuwiki:`ADI Kuiper Linux `. +If you want to build the sources, ADI makes them available on the +:git-hdl:`HDL repository `. To get the source you must +`clone `__ +the HDL repository. + +Default configuration, TWOLANES=1, ADC_RES=18 (:adi:`EVAL-ADAQ23878` in +two-lane mode): + +.. shell:: bash + + $cd hdl/projects/adaq23875/zed + $make + +Example configuration for :adi:`EVAL-ADAQ23878` in one-lane mode (TWOLANES=0, +ADC_RES=18, USE_MMCM=0): + +.. shell:: bash + + ~/hdl/projects/adaq23875/zed + $make TWOLANES=0 ADC_RES=18 USE_MMCM=0 + +Example configuration for :adi:`EVAL-ADAQ23875`/:adi:`EVAL-ADQ23876` in +two-lane mode (TWOLANES=1, ADC_RES=16, USE_MMCM=1): + +.. shell:: bash + + ~/hdl/projects/adaq23875/zed + $make TWOLANES=1 ADC_RES=16 USE_MMCM=1 + +A more comprehensive build guide can be found in the :ref:`build_hdl` user +guide. + +Resources +------------------------------------------------------------------------------- + +Systems related +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- :dokuwiki:`[Wiki] EVAL-CN0577-FMCZ User Guide ` + +Hardware related +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- Product datasheets: + + - :adi:`ADAQ23875` + - :adi:`ADAQ23876` + - :adi:`ADAQ23878` + - :adi:`LTC2387-16` + - :adi:`LTC2387-18` + +HDL related +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- :git-hdl:`ADAQ23875 HDL project source code ` + +.. list-table:: + :widths: 30 35 35 + :header-rows: 1 + + * - IP name + - Source code link + - Documentation link + * - AXI_LTC2387 + - :git-hdl:`library/axi_ltc2387` + - :ref:`axi_ltc2387` + * - AXI_CLKGEN + - :git-hdl:`library/axi_clkgen` + - :ref:`axi_clkgen` + * - AXI_DMAC + - :git-hdl:`library/axi_dmac` + - :ref:`axi_dmac` + * - AXI_SYSID + - :git-hdl:`library/axi_sysid` + - :ref:`axi_sysid` + * - AXI_PWM_GEN + - :git-hdl:`library/axi_pwm_gen` + - :ref:`axi_pwm_gen` + * - AXI_HDMI_TX + - :git-hdl:`library/axi_hdmi_tx` + - :ref:`axi_hdmi_tx` + * - AXI_I2S_ADI + - :git-hdl:`library/axi_i2s_adi` + - --- + * - AXI_SPDIF_TX + - :git-hdl:`library/axi_spdif_tx` + - --- + * - SYSID_ROM + - :git-hdl:`library/sysid_rom` + - :ref:`axi_sysid` + * - UTIL_I2C_MIXER + - :git-hdl:`library/util_i2c_mixer` + - --- + +Software related +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- :dokuwiki:`[Wiki] LTC2387 SAR ADC IIO Linux driver page ` +- :git-linux:`ADAQ23875/ADAQ23876 Linux device tree ` +- :git-linux:`ADAQ23878 Linux device tree ` +- :git-linux:`LTC2387 Linux driver ` + +.. include:: ../common/more_information.rst + +.. include:: ../common/support.rst diff --git a/docs/projects/index.rst b/docs/projects/index.rst index 9718e9c7d9..6d3c77e1dd 100644 --- a/docs/projects/index.rst +++ b/docs/projects/index.rst @@ -64,6 +64,7 @@ Contents AD9695-FMC AD9783-EBZ ADA4355-FMC + ADAQ23875 ADAQ7980-SDZ ADAQ8092-FMC ADMX100X-EVB diff --git a/library/axi_ltc2387/Makefile b/library/axi_ltc2387/Makefile index c4518f0030..49059703d1 100644 --- a/library/axi_ltc2387/Makefile +++ b/library/axi_ltc2387/Makefile @@ -1,5 +1,5 @@ #################################################################################### -## Copyright (c) 2018 - 2023 Analog Devices, Inc. +## Copyright (c) 2018 - 2023, 2025 Analog Devices, Inc. ### SPDX short identifier: BSD-1-Clause ## Auto-generated, do not modify! #################################################################################### @@ -18,6 +18,7 @@ GENERIC_DEPS += ../common/up_xfer_status.v GENERIC_DEPS += axi_ltc2387.v GENERIC_DEPS += axi_ltc2387_channel.v GENERIC_DEPS += axi_ltc2387_if.v +GENERIC_DEPS += axi_ltc2387_constr.xdc XILINX_DEPS += ../xilinx/common/ad_data_clk.v XILINX_DEPS += ../xilinx/common/ad_data_in.v diff --git a/library/axi_ltc2387/axi_ltc2387_constr.xdc b/library/axi_ltc2387/axi_ltc2387_constr.xdc new file mode 100644 index 0000000000..fb87755389 --- /dev/null +++ b/library/axi_ltc2387/axi_ltc2387_constr.xdc @@ -0,0 +1,16 @@ +############################################################################### +## Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set_multicycle_path -setup -from [get_pins -hier -filter {name=~*i_if/adc_data_d*_*_reg[*]/C}] 2 +set_multicycle_path -hold -from [get_pins -hier -filter {name=~*i_if/adc_data_d*_*_reg[*]/C}] 1 + +set_multicycle_path -setup -from [get_pins -hier -filter {name=~*i_if/i_rx_d*/i_rx_data_iddr/C}] 2 +set_multicycle_path -hold -from [get_pins -hier -filter {name=~*i_if/i_rx_d*/i_rx_data_iddr/C}] 1 + +set_multicycle_path -setup -to [get_pins -hier -filter {name=~*i_if/i_rx_d*/i_rx_data_iddr/D}] 2 +set_multicycle_path -hold -to [get_pins -hier -filter {name=~*i_if/i_rx_d*/i_rx_data_iddr/D}] 1 + +set_multicycle_path -setup -to [get_pins -hier -filter {name=~*i_if/adc_data_reg[*]/D}] 2 +set_multicycle_path -hold -to [get_pins -hier -filter {name=~*i_if/adc_data_reg[*]/D}] 1 diff --git a/library/axi_ltc2387/axi_ltc2387_ip.tcl b/library/axi_ltc2387/axi_ltc2387_ip.tcl index 6d184b42b3..cf9a284cac 100644 --- a/library/axi_ltc2387/axi_ltc2387_ip.tcl +++ b/library/axi_ltc2387/axi_ltc2387_ip.tcl @@ -26,6 +26,7 @@ adi_ip_files axi_ltc2387 [list \ "$ad_hdl_dir/library/xilinx/common/up_clock_mon_constr.xdc" \ "$ad_hdl_dir/library/xilinx/common/up_xfer_status_constr.xdc" \ "axi_ltc2387_if.v" \ + "axi_ltc2387_constr.xdc" \ "axi_ltc2387_channel.v" \ "axi_ltc2387.v" ] diff --git a/projects/adaq23875/Makefile b/projects/adaq23875/Makefile new file mode 100644 index 0000000000..68a7ed005c --- /dev/null +++ b/projects/adaq23875/Makefile @@ -0,0 +1,7 @@ +#################################################################################### +## Copyright (c) 2018 - 2025 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +include ../scripts/project-toplevel.mk diff --git a/projects/adaq23875/README.md b/projects/adaq23875/README.md new file mode 100644 index 0000000000..72f1e90e97 --- /dev/null +++ b/projects/adaq23875/README.md @@ -0,0 +1,21 @@ +# ADAQ2387X HDL Project + +- Evaluation board product page: + - [EVAL-ADAQ23878](https://analog.com/eval-adaq23878) + - [EVAL-ADAQ23876](https://analog.com/eval-adaq23876) + - [EVAL-ADAQ23875](https://analog.com/eval-adaq23875) +- System documentation: https://wiki.analog.com/resources/eval/user-guides/circuits-from-the-lab/cn0577 +- HDL project documentation: http://analogdevicesinc.github.io/hdl/projects/cn0577/index.html +- Evaluation board VADJ: 2.5V + +## Supported parts + +| Part name | Description | +|-----------------------------------------------|----------------------------------------------------| +| [ADAQ23878](https://www.analog.com/ADAQ23878) | 18-Bit, 15 MSPS, μModule Data Acquisition Solution | +| [ADAQ23876](https://www.analog.com/ADAQ23876) | 16-Bit, 15 MSPS, μModule Data Acquisition Solution | +| [ADAQ23875](https://www.analog.com/ADAQ23875) | 16-Bit, 15 MSPS, μModule Data Acquisition Solution | + +## Building the project + +Please enter the folder for the FPGA carrier you want to use and read the README.md. diff --git a/projects/adaq23875/common/adaq23875_bd.tcl b/projects/adaq23875/common/adaq23875_bd.tcl new file mode 100644 index 0000000000..4cf119333d --- /dev/null +++ b/projects/adaq23875/common/adaq23875_bd.tcl @@ -0,0 +1,124 @@ +############################################################################### +## Copyright (C) 2022-2023, 2025 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# env params + +set TWOLANES $ad_project_params(TWOLANES); # two-lane mode (1) or one-lane mode (0); default two-lane +set ADC_RES $ad_project_params(ADC_RES); # ADC resolution: (18) or (16); default 18 bits +set USE_MMCM $ad_project_params(USE_MMCM); # ref_clk frequency: 120MHz (1) or 100MHz (0); default 0 +set OUT_RES [expr {$ADC_RES == 16 ? 16 : 32}] +set CLK_GATE_WIDTH [expr {($TWOLANES == 0 && $ADC_RES == 18) ? 9 : \ + ($TWOLANES == 0 && $ADC_RES == 16) ? 8 : \ + ($TWOLANES == 1 && $ADC_RES == 18) ? 5 : \ + 4}] + +# adaq23875 i/o + +create_bd_port -dir I ref_clk +create_bd_port -dir O sampling_clk +create_bd_port -dir I dco_p +create_bd_port -dir I dco_n +create_bd_port -dir O cnv +create_bd_port -dir I da_p +create_bd_port -dir I da_n +create_bd_port -dir I db_p +create_bd_port -dir I db_n +create_bd_port -dir O clk_gate + +# adc peripheral + +ad_ip_instance axi_ltc2387 axi_ltc2387 +ad_ip_parameter axi_ltc2387 CONFIG.ADC_RES $ADC_RES +ad_ip_parameter axi_ltc2387 CONFIG.OUT_RES $OUT_RES +ad_ip_parameter axi_ltc2387 CONFIG.TWOLANES $TWOLANES +ad_ip_parameter axi_ltc2387 CONFIG.ADC_INIT_DELAY 27 + +# axi pwm gen + +ad_ip_instance axi_pwm_gen axi_pwm_gen +ad_ip_parameter axi_pwm_gen CONFIG.N_PWMS 2 +# pwm0 - cnv +ad_ip_parameter axi_pwm_gen CONFIG.PULSE_0_WIDTH 1 +ad_ip_parameter axi_pwm_gen CONFIG.PULSE_0_PERIOD 8 +# pwm1 - clk_gate +ad_ip_parameter axi_pwm_gen CONFIG.PULSE_1_WIDTH $CLK_GATE_WIDTH +ad_ip_parameter axi_pwm_gen CONFIG.PULSE_1_PERIOD 8 +ad_ip_parameter axi_pwm_gen CONFIG.PULSE_1_OFFSET 0 + +# dma + +ad_ip_instance axi_dmac axi_ltc2387_dma +ad_ip_parameter axi_ltc2387_dma CONFIG.DMA_TYPE_SRC 2 +ad_ip_parameter axi_ltc2387_dma CONFIG.DMA_TYPE_DEST 0 +ad_ip_parameter axi_ltc2387_dma CONFIG.CYCLIC 0 +ad_ip_parameter axi_ltc2387_dma CONFIG.SYNC_TRANSFER_START 0 +ad_ip_parameter axi_ltc2387_dma CONFIG.AXI_SLICE_SRC 0 +ad_ip_parameter axi_ltc2387_dma CONFIG.AXI_SLICE_DEST 0 +ad_ip_parameter axi_ltc2387_dma CONFIG.DMA_2D_TRANSFER 0 +ad_ip_parameter axi_ltc2387_dma CONFIG.DMA_DATA_WIDTH_SRC $OUT_RES +ad_ip_parameter axi_ltc2387_dma CONFIG.DMA_DATA_WIDTH_DEST 64 + +# clk wizard + +if {$USE_MMCM == "1"} { + create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_0 + + set_property -dict [list \ + CONFIG.PRIM_IN_FREQ {100.000} \ + CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {120.000} \ + ] [get_bd_cells clk_wiz_0] + + ad_connect ref_clk clk_wiz_0/clk_in1 + ad_connect sys_rstgen/peripheral_reset clk_wiz_0/reset + ad_connect clk_wiz_0/clk_out1 sampling_clk + ad_connect clk_wiz_0/clk_out1 axi_ltc2387/ref_clk + ad_connect clk_wiz_0/clk_out1 axi_ltc2387_dma/fifo_wr_clk + ad_connect clk_wiz_0/clk_out1 axi_pwm_gen/ext_clk +} else { + ad_connect ref_clk sampling_clk + ad_connect ref_clk axi_ltc2387/ref_clk + ad_connect ref_clk axi_ltc2387_dma/fifo_wr_clk + ad_connect ref_clk axi_pwm_gen/ext_clk +} + +# connections + +ad_connect sys_200m_clk axi_ltc2387/delay_clk + +ad_connect clk_gate axi_ltc2387/clk_gate +ad_connect dco_p axi_ltc2387/dco_p +ad_connect dco_n axi_ltc2387/dco_n +ad_connect da_p axi_ltc2387/da_p +ad_connect da_n axi_ltc2387/da_n + +if {$TWOLANES == "1"} { + ad_connect db_p axi_ltc2387/db_p + ad_connect db_n axi_ltc2387/db_n +} + +ad_connect axi_ltc2387/adc_valid axi_ltc2387_dma/fifo_wr_en +ad_connect axi_ltc2387/adc_data axi_ltc2387_dma/fifo_wr_din +ad_connect axi_ltc2387/adc_dovf axi_ltc2387_dma/fifo_wr_overflow + +ad_connect cnv axi_pwm_gen/pwm_0 +ad_connect clk_gate axi_pwm_gen/pwm_1 +ad_connect sys_cpu_resetn axi_pwm_gen/s_axi_aresetn +ad_connect sys_cpu_clk axi_pwm_gen/s_axi_aclk + +# address mapping + +ad_cpu_interconnect 0x44A00000 axi_ltc2387 +ad_cpu_interconnect 0x44A30000 axi_ltc2387_dma +ad_cpu_interconnect 0x44A60000 axi_pwm_gen + +# interconnect (adc) + +ad_mem_hp2_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP2 +ad_mem_hp2_interconnect $sys_cpu_clk axi_ltc2387_dma/m_dest_axi +ad_connect $sys_cpu_resetn axi_ltc2387_dma/m_dest_axi_aresetn + +# interrupts + +ad_cpu_interrupt ps-13 mb-13 axi_ltc2387_dma/irq diff --git a/projects/adaq23875/zed/Makefile b/projects/adaq23875/zed/Makefile new file mode 100644 index 0000000000..faa2e82e3b --- /dev/null +++ b/projects/adaq23875/zed/Makefile @@ -0,0 +1,27 @@ +#################################################################################### +## Copyright (c) 2018 - 2025 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +PROJECT_NAME := adaq23875_zed + +M_DEPS += ../../scripts/adi_pd.tcl +M_DEPS += ../../common/zed/zed_system_constr.xdc +M_DEPS += ../../common/zed/zed_system_bd.tcl +M_DEPS += ../../adaq23875/common/adaq23875_bd.tcl +M_DEPS += ../../../library/xilinx/common/ad_data_clk.v +M_DEPS += ../../../library/common/ad_iobuf.v + +LIB_DEPS += axi_clkgen +LIB_DEPS += axi_dmac +LIB_DEPS += axi_hdmi_tx +LIB_DEPS += axi_i2s_adi +LIB_DEPS += axi_ltc2387 +LIB_DEPS += axi_pwm_gen +LIB_DEPS += axi_spdif_tx +LIB_DEPS += axi_sysid +LIB_DEPS += sysid_rom +LIB_DEPS += util_i2c_mixer + +include ../../scripts/project-xilinx.mk diff --git a/projects/adaq23875/zed/README.md b/projects/adaq23875/zed/README.md new file mode 100644 index 0000000000..7a2f887c5f --- /dev/null +++ b/projects/adaq23875/zed/README.md @@ -0,0 +1,63 @@ + + +# ADAQ23875/ZED HDL Project + +- VADJ with which it was tested in hardware: 2.5V + +## Building the project + +The parameters configurable through the ``make`` command, can be found below, as well as in the **system_project.tcl** file; it contains the default configuration. + +``` +cd projects/adaq23875/zed +make +``` + +The overwritable parameters from the environment are: + +- TWOLANES: whether to use two lanes or one lane mode; + - 1 - two-lane mode used (default) + - 0 - one-lane mode used +- ADC_RES: the resolution of the ADC input data; + - 18 - the resolution is 18 bits (default) + - 16 - the resolution is 16 bits +- USE_MMCM: choose between default 100MHz ref_clk or 120MHz + - 1 - 120Mhz + - 0 - 100MHz (default) + +### Example configurations + +#### Two lanes, 18-bit resolution, 100MHz ref_clk (default) + +This specific command is equivalent to running `make` only: + +``` +make TWOLANES=1 \ +ADC_RES=18 \ +USE_MMCM=0 +``` + +Corresponding device tree: [zynq-zed-adv7511-adaq23878.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-adaq23878.dts) + +#### One lane, 18-bit resolution + +``` +make TWOLANES=0 \ +ADC_RES=18 +``` + +#### Two lanes, 16-bit resolution + +``` +make TWOLANES=1 \ +ADC_RES=16 +``` + +Corresponding device tree: [zynq-zed-adv7511-adaq23875.dts](https://github.com/analogdevicesinc/linux/blob/main/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-adaq23875.dts) + +#### One lane, 16-bit resolution + +``` +make TWOLANES=0 \ +ADC_RES=16 +``` diff --git a/projects/adaq23875/zed/system_bd.tcl b/projects/adaq23875/zed/system_bd.tcl new file mode 100644 index 0000000000..2c695219ef --- /dev/null +++ b/projects/adaq23875/zed/system_bd.tcl @@ -0,0 +1,20 @@ +############################################################################### +## Copyright (C) 2022-2023, 2025 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl +source $ad_hdl_dir/projects/scripts/adi_pd.tcl +# sourcing the common design +source $ad_hdl_dir/projects/adaq23875/common/adaq23875_bd.tcl + +# system ID +ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9 +ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "$mem_init_sys_file_path/mem_init_sys.txt" +ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 + +set sys_cstring "TWOLANES=$ad_project_params(TWOLANES) \ +ADC_RES=$ad_project_params(ADC_RES) \ +USE_MMCM=$ad_project_params(USE_MMCM)" + +sysid_gen_sys_init_file $sys_cstring diff --git a/projects/adaq23875/zed/system_constr.xdc b/projects/adaq23875/zed/system_constr.xdc new file mode 100644 index 0000000000..cd636b2cdf --- /dev/null +++ b/projects/adaq23875/zed/system_constr.xdc @@ -0,0 +1,44 @@ +############################################################################### +## Copyright (C) 2022-2023, 2025 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# adaq23875/adaq23876/adaq23878 +# clocks + +set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports ref_clk_p] ; ## G2 FMC_CLK1_M2C_P IO_L12P_T1_MRCC_35 +set_property -dict {PACKAGE_PIN C19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports ref_clk_n] ; ## G3 FMC_CLK1_M2C_N IO_L12N_T1_MRCC_35 +set_property -dict {PACKAGE_PIN M19 IOSTANDARD LVDS_25} [get_ports clk_p] ; ## G6 FMC_LA00_CC_P IO_L13P_T2_MRCC_34 +set_property -dict {PACKAGE_PIN M20 IOSTANDARD LVDS_25} [get_ports clk_n] ; ## G7 FMC_LA00_CC_N IO_L13N_T2_MRCC_34 + +# fpga_cnv + +set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVDS_25} [get_ports cnv_p] ; ## D8 FMC_LA01_CC_P IO_L14P_T2_SRCC_34 +set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVDS_25} [get_ports cnv_n] ; ## D9 FMC_LA01_CC_N IO_L14N_T2_SRCC_34 +set_property -dict {PACKAGE_PIN P22 IOSTANDARD LVCMOS25} [get_ports cnv_en] ; ## G10 FMC_LA03_N IO_L16N_T2_34 + +# dco, da, db + +set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports dco_p] ; ## H4 FMC_CLK0_M2C_P IO_L12P_T1_MRCC_34 +set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports dco_n] ; ## H5 FMC_CLK0_M2C_N IO_L12N_T1_MRCC_34 +set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports da_p] ; ## H7 FMC_LA02_P IO_L20P_T3_34 +set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports da_n] ; ## H8 FMC_LA02_N IO_L20N_T3_34 +set_property -dict {PACKAGE_PIN M21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports db_p] ; ## H10 FMC_LA04_P IO_L15P_T2_DQS_34 +set_property -dict {PACKAGE_PIN M22 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports db_n] ; ## H11 FMC_LA04_N IO_L15N_T2_DQS_34 + +# 100MHz clock +set clk_period 10 +# differential propagation delay for ref_clk +set tref_early 0.3 +set tref_late 1.5 + +# clocks + +create_clock -period $clk_period -name ref_clk [get_ports ref_clk_p] + +# clock latencies + +# minimum source latency values +set_clock_latency -source -early $tref_early [get_clocks ref_clk] +# maximum source latency values +set_clock_latency -source -late $tref_late [get_clocks ref_clk] diff --git a/projects/adaq23875/zed/system_project.tcl b/projects/adaq23875/zed/system_project.tcl new file mode 100644 index 0000000000..a1a6260b28 --- /dev/null +++ b/projects/adaq23875/zed/system_project.tcl @@ -0,0 +1,57 @@ +############################################################################### +## Copyright (C) 2022-2023, 2025 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# load scripts +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +# TWOLANES: parameter describing the number of lanes +# - 1: in two-lane mode (default) +# - 0: in one-lane mode +# +# ADC_RES: parameter describing the ADC input resolution, thus selecting +# between ADAQ23878 (18-bit, default) and ADAQ23875/ADAQ23876 (16-bit) +# - 18: 18 bits, ADAQ23878 (default) +# - 16: 16 bits, ADAQ23875 & ADAQ23876 +# +# USE_MMCM: parameter used to select between the 100MHz ref_clk or passing it +# through a clk_wizard and increase it to 120MHz +# - 1: use the default clocking scheme +# - 0: use the clk_wizard to increase the clk frequency +# +# The valid configurations for each supported evaluation board, depending on +# the above parameters, are: +# +# Eval board | ADC_RES | TWOLANES | USE_MMCM | +# ============================================ +# ADAQ23875 | 16 | 0 or 1 | 0 or 1 | +# ADAQ23876 | 16 | 0 or 1 | 0 or 1 | +# ADAQ23878 | 18 | 0 or 1 | 0 or 1 | + +adi_project adaq23875_zed 0 [list \ + TWOLANES [get_env_param TWOLANES 1 ] \ + ADC_RES [get_env_param ADC_RES 18 ] \ + USE_MMCM [get_env_param USE_MMCM 0 ]] + +# Base files +set base_files [list \ + "system_top.v" \ + "system_constr.xdc" \ + "$ad_hdl_dir/library/xilinx/common/ad_data_clk.v" \ + "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc"] + +# Append timing constraint file based on USE_MMCM +if { [get_env_param USE_MMCM 0] == 1 } { + lappend base_files "timing_mmcm.xdc" +} else { + lappend base_files "timing_default.xdc" +} + +# Register final list +adi_project_files adaq23875_zed $base_files + +adi_project_run adaq23875_zed diff --git a/projects/adaq23875/zed/system_top.v b/projects/adaq23875/zed/system_top.v new file mode 100644 index 0000000000..d892ba9fe6 --- /dev/null +++ b/projects/adaq23875/zed/system_top.v @@ -0,0 +1,265 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2022-2023, 2025 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/main/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, + + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, + + inout [31:0] gpio_bd, + + output hdmi_out_clk, + output hdmi_vsync, + output hdmi_hsync, + output hdmi_data_e, + output [15:0] hdmi_data, + + output i2s_mclk, + output i2s_bclk, + output i2s_lrclk, + output i2s_sdata_out, + input i2s_sdata_in, + + output spdif, + + inout iic_scl, + inout iic_sda, + inout [ 1:0] iic_mux_scl, + inout [ 1:0] iic_mux_sda, + + input otg_vbusoc, + + input ref_clk_p, + input ref_clk_n, + output clk_p, + output clk_n, + input dco_p, + input dco_n, + input da_n, + input da_p, + input db_n, + input db_p, + output cnv_p, + output cnv_n, + output cnv_en +); + + // internal signals + + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + + wire [ 1:0] iic_mux_scl_i_s; + wire [ 1:0] iic_mux_scl_o_s; + wire iic_mux_scl_t_s; + wire [ 1:0] iic_mux_sda_i_s; + wire [ 1:0] iic_mux_sda_o_s; + wire iic_mux_sda_t_s; + + wire clk_s; + wire cnv_s; + wire cnv; + wire clk_gate; + wire sampling_clk_s; + wire ltc_clk; + + assign gpio_i[63:32] = gpio_o[63:32]; + assign cnv_en = cnv; + + // instantiations + + ad_data_clk #( + .SINGLE_ENDED (0) + ) i_ref_clk ( + .rst (1'b0), + .locked (), + .clk_in_p (ref_clk_p), + .clk_in_n (ref_clk_n), + .clk (clk_s)); + + ODDR #( + .DDR_CLK_EDGE ("SAME_EDGE") + ) i_tx_clk_oddr ( + .CE (1'b1), + .R (1'b0), + .S (1'b0), + .C (sampling_clk_s), + .D1 (clk_gate), + .D2 (1'b0), + .Q (ltc_clk)); + + ODDR #( + .DDR_CLK_EDGE ("SAME_EDGE") + ) i_cnv_oddr ( + .CE (1'b1), + .R (1'b0), + .S (1'b0), + .C (sampling_clk_s), + .D1 (cnv), + .D2 (cnv), + .Q (cnv_s)); + + OBUFDS i_tx_data_obuf ( + .I (ltc_clk), + .O (clk_p), + .OB (clk_n)); + + OBUFDS OBUFDS_cnv ( + .O (cnv_p), + .OB (cnv_n), + .I (cnv_s)); + + ad_iobuf #( + .DATA_WIDTH (32) + ) iobuf_gpio_bd ( + .dio_i (gpio_o[31:0]), + .dio_o (gpio_i[31:0]), + .dio_t (gpio_t[31:0]), + .dio_p (gpio_bd)); + + ad_iobuf #( + .DATA_WIDTH (2) + ) i_iic_mux_scl ( + .dio_t ({iic_mux_scl_t_s, iic_mux_scl_t_s}), + .dio_i (iic_mux_scl_o_s), + .dio_o (iic_mux_scl_i_s), + .dio_p (iic_mux_scl)); + + ad_iobuf #( + .DATA_WIDTH (2) + ) i_iic_mux_sda ( + .dio_t ({iic_mux_sda_t_s, iic_mux_sda_t_s}), + .dio_i (iic_mux_sda_o_s), + .dio_o (iic_mux_sda_i_s), + .dio_p (iic_mux_sda)); + + system_wrapper i_system_wrapper ( + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + .hdmi_data (hdmi_data), + .hdmi_data_e (hdmi_data_e), + .hdmi_hsync (hdmi_hsync), + .hdmi_out_clk (hdmi_out_clk), + .hdmi_vsync (hdmi_vsync), + .i2s_bclk (i2s_bclk), + .i2s_lrclk (i2s_lrclk), + .i2s_mclk (i2s_mclk), + .i2s_sdata_in (i2s_sdata_in), + .i2s_sdata_out (i2s_sdata_out), + .iic_fmc_scl_io (iic_scl), + .iic_fmc_sda_io (iic_sda), + .iic_mux_scl_i (iic_mux_scl_i_s), + .iic_mux_scl_o (iic_mux_scl_o_s), + .iic_mux_scl_t (iic_mux_scl_t_s), + .iic_mux_sda_i (iic_mux_sda_i_s), + .iic_mux_sda_o (iic_mux_sda_o_s), + .iic_mux_sda_t (iic_mux_sda_t_s), + .otg_vbusoc (otg_vbusoc), + .spdif (spdif), + .ref_clk (clk_s), + .sampling_clk (sampling_clk_s), + .dco_p (dco_p), + .dco_n (dco_n), + .da_n (da_n), + .da_p (da_p), + .db_n (db_n), + .db_p (db_p), + .cnv (cnv), + .clk_gate (clk_gate), + .spi0_clk_i (1'b0), + .spi0_clk_o (), + .spi0_csn_0_o (), + .spi0_csn_1_o (), + .spi0_csn_2_o (), + .spi0_csn_i (1'b1), + .spi0_sdi_i (1'b0), + .spi0_sdo_i (1'b0), + .spi0_sdo_o (), + .spi1_clk_i (1'b0), + .spi1_clk_o (), + .spi1_csn_0_o (), + .spi1_csn_1_o (), + .spi1_csn_2_o (), + .spi1_csn_i (1'b1), + .spi1_sdi_i (1'b0), + .spi1_sdo_i (1'b0), + .spi1_sdo_o ()); + +endmodule diff --git a/projects/adaq23875/zed/timing_default.xdc b/projects/adaq23875/zed/timing_default.xdc new file mode 100644 index 0000000000..4b32752da5 --- /dev/null +++ b/projects/adaq23875/zed/timing_default.xdc @@ -0,0 +1,22 @@ +############################################################################### +## Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set dco_clk_period 10 +create_clock -period $dco_clk_period -name dco [get_ports dco_p] + +# input delays for 100MHz clk + +set_input_delay -clock [get_clocks dco] -clock_fall -min -add_delay 2.300 [get_ports da_p] +set_input_delay -clock [get_clocks dco] -clock_fall -max -add_delay 2.700 [get_ports da_p] +set_input_delay -clock [get_clocks dco] -min -add_delay 2.300 [get_ports da_p] +set_input_delay -clock [get_clocks dco] -max -add_delay 2.700 [get_ports da_p] + +set_input_delay -clock [get_clocks dco] -clock_fall -min -add_delay 2.300 [get_ports db_p] +set_input_delay -clock [get_clocks dco] -clock_fall -max -add_delay 2.700 [get_ports db_p] +set_input_delay -clock [get_clocks dco] -min -add_delay 2.300 [get_ports db_p] +set_input_delay -clock [get_clocks dco] -max -add_delay 2.700 [get_ports db_p] + +set_property IDELAY_VALUE 27 [get_cells i_system_wrapper/system_i/axi_ltc2387/inst/i_if/i_rx_db/i_rx_data_idelay] +set_property IDELAY_VALUE 27 [get_cells i_system_wrapper/system_i/axi_ltc2387/inst/i_if/i_rx_da/i_rx_data_idelay] diff --git a/projects/adaq23875/zed/timing_mmcm.xdc b/projects/adaq23875/zed/timing_mmcm.xdc new file mode 100644 index 0000000000..e343359c1d --- /dev/null +++ b/projects/adaq23875/zed/timing_mmcm.xdc @@ -0,0 +1,22 @@ +############################################################################### +## Copyright (C) 2025 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set dco_clk_period 8.33 +create_clock -period $dco_clk_period -name dco [get_ports dco_p] + +# input delays for 120MHz clk + +set_input_delay -clock [get_clocks dco] -clock_fall -min -add_delay 1.880 [get_ports da_p] +set_input_delay -clock [get_clocks dco] -clock_fall -max -add_delay 3.120 [get_ports da_p] +set_input_delay -clock [get_clocks dco] -min -add_delay 1.880 [get_ports da_p] +set_input_delay -clock [get_clocks dco] -max -add_delay 3.120 [get_ports da_p] + +set_input_delay -clock [get_clocks dco] -clock_fall -min -add_delay 1.880 [get_ports db_p] +set_input_delay -clock [get_clocks dco] -clock_fall -max -add_delay 3.120 [get_ports db_p] +set_input_delay -clock [get_clocks dco] -min -add_delay 1.880 [get_ports db_p] +set_input_delay -clock [get_clocks dco] -max -add_delay 3.120 [get_ports db_p] + +set_property IDELAY_VALUE 27 [get_cells i_system_wrapper/system_i/axi_ltc2387/inst/i_if/i_rx_db/i_rx_data_idelay] +set_property IDELAY_VALUE 27 [get_cells i_system_wrapper/system_i/axi_ltc2387/inst/i_if/i_rx_da/i_rx_data_idelay]