diff --git a/library/axi_dmac/axi_dmac_regmap.v b/library/axi_dmac/axi_dmac_regmap.v
index 0e812d64b94..7b2ccacbea0 100644
--- a/library/axi_dmac/axi_dmac_regmap.v
+++ b/library/axi_dmac/axi_dmac_regmap.v
@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2014-2025 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -266,8 +266,8 @@ module axi_dmac_regmap #(
       9'h10f: up_rdata <= DISABLE_DEBUG_REGISTERS ? 32'h00 : dbg_status;
       9'h110: up_rdata <= DISABLE_DEBUG_REGISTERS ? 32'h00 : dbg_ids0;
       9'h111: up_rdata <= DISABLE_DEBUG_REGISTERS ? 32'h00 : dbg_ids1;
-      9'h126: up_rdata <= (HAS_ADDR_HIGH && !DISABLE_DEBUG_REGISTERS) ? dbg_dest_addr[DMA_AXI_ADDR_WIDTH-1:32] : 32'h00;
-      9'h127: up_rdata <= (HAS_ADDR_HIGH && !DISABLE_DEBUG_REGISTERS) ? dbg_src_addr[DMA_AXI_ADDR_WIDTH-1:32] : 32'h00;
+      9'h126: up_rdata <= (HAS_ADDR_HIGH && !DISABLE_DEBUG_REGISTERS) ? dbg_dest_addr[DMA_AXI_ADDR_WIDTH-1:HAS_ADDR_HIGH*32] : 32'h00;
+      9'h127: up_rdata <= (HAS_ADDR_HIGH && !DISABLE_DEBUG_REGISTERS) ? dbg_src_addr[DMA_AXI_ADDR_WIDTH-1:HAS_ADDR_HIGH*32] : 32'h00;
       default: up_rdata <= up_rdata_request;
       endcase
     end
diff --git a/library/axi_dmac/axi_dmac_regmap_request.v b/library/axi_dmac/axi_dmac_regmap_request.v
index 3b7090f8c1a..fc9f735397f 100644
--- a/library/axi_dmac/axi_dmac_regmap_request.v
+++ b/library/axi_dmac/axi_dmac_regmap_request.v
@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2018-2024 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2018-2025 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
@@ -194,11 +194,11 @@ module axi_dmac_regmap_request #(
         9'h106: up_dma_x_length[DMA_LENGTH_WIDTH-1:DMA_LENGTH_ALIGN] <= up_wdata[DMA_LENGTH_WIDTH-1:DMA_LENGTH_ALIGN];
         9'h124:
           if (HAS_ADDR_HIGH) begin
-            up_dma_dest_address[DMA_AXI_ADDR_WIDTH-1:32] <= up_wdata[ADDR_HIGH_MSB:0];
+            up_dma_dest_address[DMA_AXI_ADDR_WIDTH-1:HAS_ADDR_HIGH*32] <= up_wdata[ADDR_HIGH_MSB:0];
           end
         9'h125:
           if (HAS_ADDR_HIGH) begin
-            up_dma_src_address[DMA_AXI_ADDR_WIDTH-1:32] <= up_wdata[ADDR_HIGH_MSB:0];
+            up_dma_src_address[DMA_AXI_ADDR_WIDTH-1:HAS_ADDR_HIGH*32] <= up_wdata[ADDR_HIGH_MSB:0];
           end
         endcase
       end
@@ -232,9 +232,9 @@ module axi_dmac_regmap_request #(
             end
     9'h117: up_rdata <= request_flock_stride;
     9'h11f: up_rdata <= {request_sg_address[ADDR_LOW_MSB:BYTES_PER_BEAT_WIDTH_SG],{BYTES_PER_BEAT_WIDTH_SG{1'b0}}};
-    9'h124: up_rdata <= (HAS_ADDR_HIGH && HAS_DEST_ADDR) ? up_dma_dest_address[DMA_AXI_ADDR_WIDTH-1:32] : 32'h00;
-    9'h125: up_rdata <= (HAS_ADDR_HIGH && HAS_SRC_ADDR) ? up_dma_src_address[DMA_AXI_ADDR_WIDTH-1:32] : 32'h00;
-    9'h12f: up_rdata <= HAS_ADDR_HIGH ? request_sg_address[DMA_AXI_ADDR_WIDTH-1:32] : 32'h00;
+    9'h124: up_rdata <= (HAS_ADDR_HIGH && HAS_DEST_ADDR) ? up_dma_dest_address[DMA_AXI_ADDR_WIDTH-1:HAS_ADDR_HIGH*32] : 32'h00;
+    9'h125: up_rdata <= (HAS_ADDR_HIGH && HAS_SRC_ADDR) ? up_dma_src_address[DMA_AXI_ADDR_WIDTH-1:HAS_ADDR_HIGH*32] : 32'h00;
+    9'h12f: up_rdata <= HAS_ADDR_HIGH ? request_sg_address[DMA_AXI_ADDR_WIDTH-1:HAS_ADDR_HIGH*32] : 32'h00;
     default: up_rdata <= 32'h00;
     endcase
   end
@@ -342,7 +342,7 @@ module axi_dmac_regmap_request #(
         9'h11f: up_dma_sg_address[ADDR_LOW_MSB:BYTES_PER_BEAT_WIDTH_SG] <= up_wdata[ADDR_LOW_MSB:BYTES_PER_BEAT_WIDTH_SG];
         9'h12f:
           if (HAS_ADDR_HIGH) begin
-            up_dma_sg_address[DMA_AXI_ADDR_WIDTH-1:32] <= up_wdata[ADDR_HIGH_MSB:0];
+            up_dma_sg_address[DMA_AXI_ADDR_WIDTH-1:HAS_ADDR_HIGH*32] <= up_wdata[ADDR_HIGH_MSB:0];
           end
         endcase
       end
diff --git a/library/spi_engine/spi_engine_execution/spi_engine_execution_shiftreg.v b/library/spi_engine/spi_engine_execution/spi_engine_execution_shiftreg.v
index fd264a6423f..5b2ccd2a331 100644
--- a/library/spi_engine/spi_engine_execution/spi_engine_execution_shiftreg.v
+++ b/library/spi_engine/spi_engine_execution/spi_engine_execution_shiftreg.v
@@ -226,6 +226,8 @@ module spi_engine_execution_shiftreg #(
 
     end
 
+    reg [3:0] last_sdi_bit_m = 4'b0;
+
     assign sdi_data = sdi_data_latch;
     assign last_sdi_bit = last_sdi_bit_r;
     assign echo_last_bit =  !last_sdi_bit_m[3] && last_sdi_bit_m[2];
@@ -233,7 +235,6 @@ module spi_engine_execution_shiftreg #(
     // sdi_data_valid is synchronous to SPI clock, so synchronize the
     // last_sdi_bit to SPI clock
 
-    reg [3:0] last_sdi_bit_m = 4'b0;
     always @(posedge clk) begin
       if (cs_activate) begin
         last_sdi_bit_m <= 4'b0;