diff --git a/docs/library/spi_engine/axi_spi_engine.rst b/docs/library/spi_engine/axi_spi_engine.rst
index aa219216312..40ffa389fa4 100644
--- a/docs/library/spi_engine/axi_spi_engine.rst
+++ b/docs/library/spi_engine/axi_spi_engine.rst
@@ -42,8 +42,8 @@ Configuration Parameters
      - Configures the size of the serial-data out FIFO.
    * - SDI_FIFO_ADDRESS_WIDTH
      - Configures the size of the serial-data in FIFO.
-   * - NUM_OFFLOAD
-     - The number of offload control interfaces.
+   * - OFFLOAD_EN
+     - Enable the offload module interface.
 
 Signal and Interface Pins
 --------------------------------------------------------------------------------
diff --git a/docs/library/spi_engine/tutorial.rst b/docs/library/spi_engine/tutorial.rst
index 3f892fd3820..c66080d2b9a 100644
--- a/docs/library/spi_engine/tutorial.rst
+++ b/docs/library/spi_engine/tutorial.rst
@@ -72,32 +72,49 @@ each IP individually or by using the function provided by the
 
 Using the script ensures that the correct connections are being made and that
 the IP cores will receive the correct parameter configuration since certain
-parameters need to be set to the same value. The function takes the following
-arguments:
+parameters need to be set to the same value. The same script can be used for
+Intel and Xilinx projects, and it is expected to have the same script for other
+vendors in the future. The function takes the following arguments:
 
 .. code:: tcl
 
-   proc spi_engine_create {{name "spi_engine"} {data_width 32} {async_spi_clk 1} {num_cs 1} {num_sdi 1} {num_sdo 1} {sdi_delay 0} {echo_sclk 0} {cmd_mem_addr_width 4} {data_mem_addr_width 4} {sdi_fifo_addr_width 5} {sdo_fifo_addr_width 5} {sync_fifo_addr_width 4} {cmd_fifo_addr_width 4}}
+   proc spi_engine_create {args}
 
-**data_width** will set the width of the data bus / data line used by the SPI
-engine to connect to the DMA and which serves the purpose of sending ADC sample
-data to the DDR memory. The data_width value will also set the maximum word
-length for the SPI transfer. Valid values are are 8/16/24/32. The DMA valid
-values are 16/32/64/128[…]. Since the Pulsar_ADC devices are all single SDI/SDO
-and some of them require 18bit transfers, this value will be rounded to 32bit.
+**args[0] - name** is mandatory for all Xilinx projects.
 
-**async_spi_clk** will chose the reference clock for the SPI Engine. Setting
-this parameter to 0 will configure the hierarchy to use the axi clock (100MHz)
-as the reference clock. Setting it to 1 will allow for an external reference
-clock (spi_clk). Because some devices need 80MHz SCLK, a 160MHz reference clock
-is required which implies an external reference.
+**args[1] - data_width** will set the width of the data bus / data line used by
+the SPI engine to connect to the DMA and which serves the purpose of sending
+ADC sample data to the DDR memory. The data_width value will also set the
+maximum word length for the SPI transfer. Valid values are are 8/16/24/32. The
+DMA valid values are 16/32/64/128[…]. Since the Pulsar_ADC devices are all
+single SDI/SDO and some of them require 18bit transfers, this value will be
+rounded to 32bit.
 
-**num_cs** selects the number of CS lines.
+**args[2] - async_spi_clk** will chose the reference clock for the SPI Engine.
+Setting this parameter to 0 will configure the hierarchy to use the axi clock
+(100MHz) as the reference clock. Setting it to 1 will allow for an external
+reference clock (spi_clk). Because some devices need 80MHz SCLK, a 160MHz
+reference clock is required which implies an external reference.
 
-**num_sdi** selects the number of SDI lines.
+**args[3] - offload_en** enables the offload mode of the SPI Engine. This is
+useful for situation where only FIFO mode are needed. By default, offload mode
+is enabled.
+
+**args[4] - num_cs** selects the number of CS lines.
+
+**args[5] - num_sdi** selects the number of SDI lines.
+
+**args[6] - num_sdo** selects the number of SDO lines.
+
+**args[7] - sdi_delay** The latch of the SDI line can be delayed with 1, 2 or
+3 SPI core clock cycle. Needed for designs with high SCLK rate (>50MHz).
+
+**args[8] - echo_sclk** enables the usage of external echo_sclk.
+
+**args[9] - sdo_streaming** Enables the s_axis_sdo interface. This allows for
+sourcing the SDO data stream from a DMA or other similar sources, useful for
+DACs.
 
-**sdi_delay** The latch of the SDI line can be delayed with 1, 2 or 3 SPI core
-clock cycle. Needed for designs with high SCLK rate (>50MHz).
 
 Configuration tcl code and result below:
 
@@ -107,12 +124,13 @@ Configuration tcl code and result below:
 
    set data_width    32
    set async_spi_clk 1
+   set offload_en    1
    set num_cs        1
    set num_sdi       1
    set sdi_delay     1
    set hier_spi_engine spi_pulsar_adc
 
-   spi_engine_create $hier_spi_engine $data_width $async_spi_clk $num_cs $num_sdi $sdi_delay
+   spi_engine_create $hier_spi_engine $data_width $async_spi_clk $offload_en $num_cs $num_sdi $sdi_delay
 
 .. image:: tutorial/pulsar_hdl_1.svg
    :align: center
diff --git a/docs/user_guide/ip_cores/use_adi_ips.rst b/docs/user_guide/ip_cores/use_adi_ips.rst
index a8865fe4858..c4010f4932c 100644
--- a/docs/user_guide/ip_cores/use_adi_ips.rst
+++ b/docs/user_guide/ip_cores/use_adi_ips.rst
@@ -154,9 +154,9 @@ Vivado
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 
 The SPI Engine is a special module too, since it consists of more than one IP.
-In order to use it into your own project, you will have to add all of its components.
-For this example, the code shown here is from the ad4630_fmc project:
-:git-hdl:`projects/ad4630_fmc/common/ad463x_bd.tcl`
+In order to use it into your own project, you will have to add all of its
+components. For this example, the code shown here is from the ad4630_fmc
+project: :git-hdl:`projects/ad4630_fmc/common/ad463x_bd.tcl`
 
 Let's start with sourcing the spi_engine.tcl script inside your ``<project>_db.tcl``.
 
@@ -167,22 +167,61 @@ Let's start with sourcing the spi_engine.tcl script inside your ``<project>_db.t
 The SPI engine has 4 modules: execution, interconnect, regmap and offload.
 
 All of the modules are instantiated inside the ``spi_engine_create`` function.
-This function requires 13 parameters. The default values for them are as follow,
-but feel free to configure it as you want:
+Offload_en variable define whether offload and interconnect are necessary or
+not for the project. This function requires 15 parameters for Xilinx projects,
+and 18 parameters for Quartus projects. The default values (Xilinx) for them are as
+follows, but feel free to configure it as you want:
 
 .. code:: tcl
 
-   {{name "spi_engine"} {data_width 32} {async_spi_clk 1} {num_cs 1} {num_sdi 1} {num_sdo 1} {sdi_delay 0} {echo_sclk 0} {cmd_mem_addr_width 4} {data_mem_addr_width 4} {sdi_fifo_addr_width 5} {sdo_fifo_addr_width 5} {sync_fifo_addr_width 4} {cmd_fifo_addr_width 4}}
+   {{name "spi_engine"} {data_width 32} {async_spi_clk 1} {offload_en 1} {num_cs 1} {num_sdi 1} {num_sdo 1} {sdi_delay 0} {echo_sclk 0} {sdo_streaming 0} {cmd_mem_addr_width 4} {data_mem_addr_width 4} {sdi_fifo_addr_width 5} {sdo_fifo_addr_width 5} {sync_fifo_addr_width 4} {cmd_fifo_addr_width 4}}
 
-An example of instantiation, using the default values for ``cmd_mem_addr_width``, ``data_mem_addr_width``, ``sdi_fifo_addr_width``, ``sdo_fifo_addr_width``, ``sync_fifo_addr_width`` and ``cmd_fifo_addr_width``:
+Name is a mandatory input. An example of instantiation (Xilinx project), using
+the default values for ``sdo_streaming``, ``cmd_mem_addr_width``,
+``data_mem_addr_width``, ``sdi_fifo_addr_width``, ``sdo_fifo_addr_width``,
+``sync_fifo_addr_width`` and ``cmd_fifo_addr_width``:
 
 .. code:: tcl
 
-   #                 name         data_width async_spi_clk num_csn num_sdi     sdi_delay  echo_sclk
-   spi_engine_create "spi_ad463x" 32         1             1       $NUM_OF_SDI 0          1
+   #                 name         data_width async_spi_clk offload_en num_csn num_sdi     sdi_delay  echo_sclk
+   spi_engine_create "spi_ad463x" 32         1             1          1       $NUM_OF_SDI 0          1
    ad_ip_parameter spi_ad463x/execution CONFIG.DEFAULT_SPI_CFG 1   ;
 
    ad_ip_parameter spi_ad463x/axi_regmap CONFIG.CFG_INFO_0 $NUM_OF_SDI
    ad_ip_parameter spi_ad463x/axi_regmap CONFIG.CFG_INFO_1 $CAPTURE_ZONE
    ad_ip_parameter spi_ad463x/axi_regmap CONFIG.CFG_INFO_2 $CLK_MODE
    ad_ip_parameter spi_ad463x/axi_regmap CONFIG.CFG_INFO_3 $DDR_EN
+
+Parameters and default values for Quartus projects:
+
+.. code:: tcl
+
+   {{name "spi_engine"} {axi_clk sys_clk.clk} {axi_reset sys_clk.clk_reset} {spi_clk spi_clk_pll.outclk0} {data_width 32} {async_spi_clk 1} {offload_en 1} {num_cs 1} {num_sdi 1} {num_sdo 1} {sdi_delay 0} {echo_sclk 0} {sdo_streaming 0} {cmd_mem_addr_width 4} {data_mem_addr_width 4} {sdi_fifo_addr_width 5} {sdo_fifo_addr_width 5} {sync_fifo_addr_width 4} {cmd_fifo_addr_width 4}}
+
+Name, axi_clk, axi_reset, and spi_clk are mandatory inputs. An example of
+instantiation (Quartus project), using the default values for
+``sdo_streaming``, ``cmd_mem_addr_width``, ``data_mem_addr_width``,
+``sdi_fifo_addr_width``, ``sdo_fifo_addr_width``, ``sync_fifo_addr_width``,
+and ``cmd_fifo_addr_width``:
+
+.. code:: tcl
+
+   source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl
+
+   set spi_engine_hier spi_ad57xx
+
+   set data_width     32
+   set async_spi_clk  1
+   set offload_en     1
+   set num_cs         1
+   set num_sdi        1
+   set num_sdo        1
+   set sdi_delay      0
+   set echo_sclk      0
+   set sdo_streaming  1
+
+   set axi_clk sys_clk.clk
+   set axi_reset sys_clk.clk_reset
+   set spi_clk spi_clk_pll.outclk0
+
+   spi_engine_create $spi_engine_hier $axi_clk $axi_reset $spi_clk $data_width $async_spi_clk $offload_en $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk $sdo_streaming
diff --git a/library/spi_engine/axi_spi_engine/axi_spi_engine.v b/library/spi_engine/axi_spi_engine/axi_spi_engine.v
index 628595b0c88..fbf868da6f0 100644
--- a/library/spi_engine/axi_spi_engine/axi_spi_engine.v
+++ b/library/spi_engine/axi_spi_engine/axi_spi_engine.v
@@ -43,7 +43,7 @@ module axi_spi_engine #(
   parameter SDI_FIFO_ADDRESS_WIDTH = 5,
   parameter MM_IF_TYPE = 0,
   parameter ASYNC_SPI_CLK = 0,
-  parameter NUM_OFFLOAD = 0,
+  parameter OFFLOAD_EN = 1,
   parameter OFFLOAD0_CMD_MEM_ADDRESS_WIDTH = 4,
   parameter OFFLOAD0_SDO_MEM_ADDRESS_WIDTH = 4,
   parameter ID = 0,
diff --git a/library/spi_engine/axi_spi_engine/axi_spi_engine_hw.tcl b/library/spi_engine/axi_spi_engine/axi_spi_engine_hw.tcl
index e96c981a925..b7a06be7a65 100644
--- a/library/spi_engine/axi_spi_engine/axi_spi_engine_hw.tcl
+++ b/library/spi_engine/axi_spi_engine/axi_spi_engine_hw.tcl
@@ -28,7 +28,7 @@ ad_ip_parameter SDO_FIFO_ADDRESS_WIDTH INTEGER 5
 ad_ip_parameter SDI_FIFO_ADDRESS_WIDTH INTEGER 5
 ad_ip_parameter MM_IF_TYPE INTEGER 1
 ad_ip_parameter ASYNC_SPI_CLK INTEGER 0
-ad_ip_parameter NUM_OFFLOAD INTEGER 1
+ad_ip_parameter OFFLOAD_EN INTEGER 1
 ad_ip_parameter OFFLOAD0_CMD_MEM_ADDRESS_WIDTH INTEGER 4
 ad_ip_parameter OFFLOAD0_SDO_MEM_ADDRESS_WIDTH INTEGER 4
 ad_ip_parameter ID INTEGER 0
@@ -43,6 +43,7 @@ proc p_elaboration {} {
 
   set num_of_sdi [get_parameter_value NUM_OF_SDI]
   set data_width [get_parameter_value DATA_WIDTH]
+  set offload_en [get_parameter_value OFFLOAD_EN]
 
   # interrupt
 
@@ -152,31 +153,32 @@ proc p_elaboration {} {
 
   # Offload interfaces
 
-  add_interface offload0_cmd conduit end
-  add_interface_port offload0_cmd offload0_cmd_wr_en    wre   output  1
-  add_interface_port offload0_cmd offload0_cmd_wr_data  data  output  16
+  if {$offload_en == 1} {
+    add_interface offload0_cmd conduit end
+    add_interface_port offload0_cmd offload0_cmd_wr_en    wre   output  1
+    add_interface_port offload0_cmd offload0_cmd_wr_data  data  output  16
 
-  set_interface_property offload0_cmd associatedClock if_spi_clk
-  set_interface_property offload0_cmd associatedReset none
+    set_interface_property offload0_cmd associatedClock if_spi_clk
+    set_interface_property offload0_cmd associatedReset none
 
-  add_interface offload0_sdo conduit end
-  add_interface_port offload0_sdo offload0_sdo_wr_en    wre   output  1
-  add_interface_port offload0_sdo offload0_sdo_wr_data  data  output  $data_width
+    add_interface offload0_sdo conduit end
+    add_interface_port offload0_sdo offload0_sdo_wr_en    wre   output  1
+    add_interface_port offload0_sdo offload0_sdo_wr_data  data  output  $data_width
 
-  set_interface_property offload0_sdo associatedClock if_spi_clk
-  set_interface_property offload0_sdo associatedReset none
+    set_interface_property offload0_sdo associatedClock if_spi_clk
+    set_interface_property offload0_sdo associatedReset none
 
-  ad_interface signal  offload0_mem_reset  output  1   reset
-  ad_interface signal  offload0_enable     output  1   enable
-  ad_interface signal  offload0_enabled    input   1   enabled
+    ad_interface signal  offload0_mem_reset  output  1   reset
+    ad_interface signal  offload0_enable     output  1   enable
+    ad_interface signal  offload0_enabled    input   1   enabled
 
-  add_interface offload_sync axi4stream end
-  add_interface_port offload_sync offload_sync_valid  tvalid input   1
-  add_interface_port offload_sync offload_sync_ready  tready output  1
-  add_interface_port offload_sync offload_sync_data   tdata  input   8
-
-  set_interface_property offload_sync associatedClock if_spi_clk
-  set_interface_property offload_sync associatedReset if_spi_resetn
+    add_interface offload_sync axi4stream end
+    add_interface_port offload_sync offload_sync_valid  tvalid input   1
+    add_interface_port offload_sync offload_sync_ready  tready output  1
+    add_interface_port offload_sync offload_sync_data   tdata  input   8
 
+    set_interface_property offload_sync associatedClock if_spi_clk
+    set_interface_property offload_sync associatedReset if_spi_resetn
+  }
 }
 
diff --git a/library/spi_engine/axi_spi_engine/axi_spi_engine_ip.tcl b/library/spi_engine/axi_spi_engine/axi_spi_engine_ip.tcl
index b775c377c78..d0a099d2b07 100644
--- a/library/spi_engine/axi_spi_engine/axi_spi_engine_ip.tcl
+++ b/library/spi_engine/axi_spi_engine/axi_spi_engine_ip.tcl
@@ -70,7 +70,7 @@ foreach port {"up_clk" "up_rstn" "up_wreq" "up_waddr" "up_wdata" "up_rreq" "up_r
   set_property DRIVER_VALUE "0" [ipx::get_ports $port]
 }
 adi_set_bus_dependency "spi_engine_offload_ctrl0" "spi_engine_offload_ctrl0" \
-	"(spirit:decode(id('MODELPARAM_VALUE.NUM_OFFLOAD')) > 0)"
+	"(spirit:decode(id('MODELPARAM_VALUE.OFFLOAD_EN')) == 1)"
 
 adi_set_bus_dependency "s_axi" "s_axi" \
       "(spirit:decode(id('MODELPARAM_VALUE.MM_IF_TYPE')) = 0)"
@@ -162,13 +162,12 @@ set_property -dict [list \
  ] \
  [ipx::get_hdl_parameters ASYNC_SPI_CLK -of_objects $cc]
 
-## NUM_OFFLOAD
+## OFFLOAD_EN
 set_property -dict [list \
-  "value_validation_type" "range_long" \
-  "value_validation_range_minimum" "0" \
-  "value_validation_range_maximum" "8" \
+  "value_format" "bool" \
+  "value" "true" \
  ] \
- [ipx::get_user_parameters NUM_OFFLOAD -of_objects $cc]
+ [ipx::get_user_parameters OFFLOAD_EN -of_objects $cc]
 
 ## OFFLOAD0_CMD_MEM_ADDRESS_WIDTH
 set_property -dict [list \
@@ -277,25 +276,25 @@ set_property -dict [list \
 set offload_group [ipgui::add_group -name "Offload module configuration" -component $cc \
     -parent $page0 -display_name "Offload module configuration" ]
 
-ipgui::add_param -name "NUM_OFFLOAD" -component $cc -parent $offload_group
+ipgui::add_param -name "OFFLOAD_EN" -component $cc -parent $offload_group
 set_property -dict [list \
-  "display_name" "Number of offloads" \
-  "tooltip" "\[NUM_OFFLOAD\] Number of offloads" \
-] [ipgui::get_guiparamspec -name "NUM_OFFLOAD" -component $cc]
+  "display_name" "Offload interface enable" \
+  "tooltip" "\[OFFLOAD_EN\] Enable the offload module interface" \
+] [ipgui::get_guiparamspec -name "OFFLOAD_EN" -component $cc]
 
 ipgui::add_param -name "OFFLOAD0_CMD_MEM_ADDRESS_WIDTH" -component $cc -parent $offload_group
 set_property -dict [list \
   "display_name" "Offload command FIFO address width" \
   "tooltip" "\[OFFLOAD0_CMD_MEM_ADDRESS_WIDTH\] Define the depth of the FIFO" \
 ] [ipgui::get_guiparamspec -name "OFFLOAD0_CMD_MEM_ADDRESS_WIDTH" -component $cc]
-set_property enablement_tcl_expr {$NUM_OFFLOAD > 0} [ipx::get_user_parameters OFFLOAD0_CMD_MEM_ADDRESS_WIDTH -of_objects $cc]
+set_property enablement_tcl_expr {$OFFLOAD_EN == 1} [ipx::get_user_parameters OFFLOAD0_CMD_MEM_ADDRESS_WIDTH -of_objects $cc]
 
 ipgui::add_param -name "OFFLOAD0_SDO_MEM_ADDRESS_WIDTH" -component $cc -parent $offload_group
 set_property -dict [list \
   "display_name" "Offload MOSI FIFO address width" \
   "tooltip" "\[OFFLOAD0_SDO_MEM_ADDRESS_WIDTH\] Define the depth of the FIFO" \
 ] [ipgui::get_guiparamspec -name "OFFLOAD0_SDO_MEM_ADDRESS_WIDTH" -component $cc]
-set_property enablement_tcl_expr {$NUM_OFFLOAD > 0} [ipx::get_user_parameters OFFLOAD0_SDO_MEM_ADDRESS_WIDTH -of_objects $cc]
+set_property enablement_tcl_expr {$OFFLOAD_EN == 1} [ipx::get_user_parameters OFFLOAD0_SDO_MEM_ADDRESS_WIDTH -of_objects $cc]
 
 ## Create and save the XGUI file
 ipx::create_xgui_files $cc
diff --git a/library/spi_engine/axi_spi_engine/axi_spi_engine_ltt.tcl b/library/spi_engine/axi_spi_engine/axi_spi_engine_ltt.tcl
index 1cdcb38f060..0b229fdd46d 100755
--- a/library/spi_engine/axi_spi_engine/axi_spi_engine_ltt.tcl
+++ b/library/spi_engine/axi_spi_engine/axi_spi_engine_ltt.tcl
@@ -194,14 +194,14 @@ set ip [ipl::set_parameter -ip $ip \
     -group2 Config]
 
 set ip [ipl::set_parameter -ip $ip \
-    -id NUM_OFFLOAD \
+    -id OFFLOAD_EN \
     -type param \
     -value_type int \
     -conn_mod axi_spi_engine \
-    -title {Number of offloads} \
-    -default 0 \
+    -title {Offload interface enable} \
+    -default 1 \
     -output_formatter nostr \
-    -value_range {(0, 8)} \
+    -options {[('True', 1), ('False', 0)]} \
     -group1 {Offload module configuration} \
     -group2 Config]
 set ip [ipl::set_parameter -ip $ip \
@@ -212,7 +212,7 @@ set ip [ipl::set_parameter -ip $ip \
     -title {Offload command FIFO address width} \
     -default 4 \
     -output_formatter nostr \
-    -editable {(NUM_OFFLOAD > 0)} \
+    -editable {(OFFLOAD_EN == 1)} \
     -value_range {(1, 16)} \
     -group1 {Offload module configuration} \
     -group2 Config]
@@ -224,7 +224,7 @@ set ip [ipl::set_parameter -ip $ip \
     -title {Offload MOSI FIFO address width} \
     -default 4 \
     -output_formatter nostr \
-    -editable {(NUM_OFFLOAD > 0)} \
+    -editable {(OFFLOAD_EN == 0)} \
     -value_range {(1, 16)} \
     -group1 {Offload module configuration} \
     -group2 Config]
diff --git a/library/spi_engine/scripts/spi_engine.tcl b/library/spi_engine/scripts/spi_engine.tcl
index 63007966c2a..d4290ab1d0c 100644
--- a/library/spi_engine/scripts/spi_engine.tcl
+++ b/library/spi_engine/scripts/spi_engine.tcl
@@ -36,18 +36,19 @@ proc spi_engine_create {args} {
     set name                  [lindex $args 0]
     set data_width            [optional_param $args 1 32]
     set async_spi_clk         [optional_param $args 2 1]
-    set num_cs                [optional_param $args 3 1]
-    set num_sdi               [optional_param $args 4 1]
-    set num_sdo               [optional_param $args 5 1]
-    set sdi_delay             [optional_param $args 6 0]
-    set echo_sclk             [optional_param $args 7 0]
-    set sdo_streaming         [optional_param $args 8 0]
-    set cmd_mem_addr_width    [optional_param $args 9 4]
-    set data_mem_addr_width   [optional_param $args 10 4]
-    set sdi_fifo_addr_width   [optional_param $args 11 5]
-    set sdo_fifo_addr_width   [optional_param $args 12 5]
-    set sync_fifo_addr_width  [optional_param $args 13 4]
-    set cmd_fifo_addr_width   [optional_param $args 14 4]
+    set offload_en            [optional_param $args 3 1]
+    set num_cs                [optional_param $args 4 1]
+    set num_sdi               [optional_param $args 5 1]
+    set num_sdo               [optional_param $args 6 1]
+    set sdi_delay             [optional_param $args 7 0]
+    set echo_sclk             [optional_param $args 8 0]
+    set sdo_streaming         [optional_param $args 9 0]
+    set cmd_mem_addr_width    [optional_param $args 10 4]
+    set data_mem_addr_width   [optional_param $args 11 4]
+    set sdi_fifo_addr_width   [optional_param $args 12 5]
+    set sdo_fifo_addr_width   [optional_param $args 13 5]
+    set sync_fifo_addr_width  [optional_param $args 14 4]
+    set cmd_fifo_addr_width   [optional_param $args 15 4]
 
   } elseif {$vendor == "intel"} {
     # Intel: name + clocks & resets + optional parameters
@@ -60,18 +61,19 @@ proc spi_engine_create {args} {
     set spi_clk               [lindex $args 3]
     set data_width            [optional_param $args 4 32]
     set async_spi_clk         [optional_param $args 5 1]
-    set num_cs                [optional_param $args 6 1]
-    set num_sdi               [optional_param $args 7 1]
-    set num_sdo               [optional_param $args 8 1]
-    set sdi_delay             [optional_param $args 9 0]
-    set echo_sclk             [optional_param $args 10 0]
-    set sdo_streaming         [optional_param $args 11 0]
-    set cmd_mem_addr_width    [optional_param $args 12 4]
-    set data_mem_addr_width   [optional_param $args 13 4]
-    set sdi_fifo_addr_width   [optional_param $args 14 5]
-    set sdo_fifo_addr_width   [optional_param $args 15 5]
-    set sync_fifo_addr_width  [optional_param $args 16 4]
-    set cmd_fifo_addr_width   [optional_param $args 17 4]
+    set offload_en            [optional_param $args 6 1]
+    set num_cs                [optional_param $args 7 1]
+    set num_sdi               [optional_param $args 8 1]
+    set num_sdo               [optional_param $args 9 1]
+    set sdi_delay             [optional_param $args 10 0]
+    set echo_sclk             [optional_param $args 11 0]
+    set sdo_streaming         [optional_param $args 12 0]
+    set cmd_mem_addr_width    [optional_param $args 13 4]
+    set data_mem_addr_width   [optional_param $args 14 4]
+    set sdi_fifo_addr_width   [optional_param $args 15 5]
+    set sdo_fifo_addr_width   [optional_param $args 16 5]
+    set sync_fifo_addr_width  [optional_param $args 17 4]
+    set cmd_fifo_addr_width   [optional_param $args 18 4]
   }
 
   # Component instance names
@@ -80,6 +82,11 @@ proc spi_engine_create {args} {
   set offload "${name}_offload"
   set interconnect "${name}_interconnect"
 
+  if {$sdo_streaming == 1 && $offload_en == 0} {
+    puts "ERROR: SDO streaming requires offload to be enabled"
+    exit 2
+  }
+
   if {$vendor == "xilinx"} {
   # Create hierarchy for Xilinx only
     create_bd_cell -type hier $name
@@ -101,7 +108,6 @@ proc spi_engine_create {args} {
     }
   }
 
-
   # IP instances
   ad_ip_instance spi_engine_execution $execution
   ad_ip_parameter $execution CONFIG.DATA_WIDTH $data_width
@@ -114,7 +120,7 @@ proc spi_engine_create {args} {
   ad_ip_instance axi_spi_engine $axi_regmap
   ad_ip_parameter $axi_regmap CONFIG.MM_IF_TYPE 0
   ad_ip_parameter $axi_regmap CONFIG.DATA_WIDTH $data_width
-  ad_ip_parameter $axi_regmap CONFIG.NUM_OFFLOAD 1
+  ad_ip_parameter $axi_regmap CONFIG.OFFLOAD_EN $offload_en
   ad_ip_parameter $axi_regmap CONFIG.NUM_OF_SDI $num_sdi
   ad_ip_parameter $axi_regmap CONFIG.ASYNC_SPI_CLK $async_spi_clk
   ad_ip_parameter $axi_regmap CONFIG.OFFLOAD0_CMD_MEM_ADDRESS_WIDTH $cmd_mem_addr_width
@@ -124,65 +130,77 @@ proc spi_engine_create {args} {
   ad_ip_parameter $axi_regmap CONFIG.SYNC_FIFO_ADDRESS_WIDTH $sync_fifo_addr_width
   ad_ip_parameter $axi_regmap CONFIG.CMD_FIFO_ADDRESS_WIDTH $cmd_fifo_addr_width
 
-  ad_ip_instance spi_engine_offload $offload
-  ad_ip_parameter $offload CONFIG.DATA_WIDTH $data_width
-  ad_ip_parameter $offload CONFIG.ASYNC_SPI_CLK 0
-  ad_ip_parameter $offload CONFIG.NUM_OF_SDI $num_sdi
-  ad_ip_parameter $offload CONFIG.CMD_MEM_ADDRESS_WIDTH $cmd_mem_addr_width
-  ad_ip_parameter $offload CONFIG.SDO_MEM_ADDRESS_WIDTH $data_mem_addr_width
-  ad_ip_parameter $offload CONFIG.SDO_STREAMING $sdo_streaming
-  ad_ip_parameter $offload CONFIG.ASYNC_TRIG 0
+  # Instantiate Offload and interconnect modules only if offload is enabled
+  if {$offload_en == 1} {
+    ad_ip_instance spi_engine_offload $offload
+    ad_ip_parameter $offload CONFIG.DATA_WIDTH $data_width
+    ad_ip_parameter $offload CONFIG.ASYNC_SPI_CLK 0
+    ad_ip_parameter $offload CONFIG.NUM_OF_SDI $num_sdi
+    ad_ip_parameter $offload CONFIG.CMD_MEM_ADDRESS_WIDTH $cmd_mem_addr_width
+    ad_ip_parameter $offload CONFIG.SDO_MEM_ADDRESS_WIDTH $data_mem_addr_width
+    ad_ip_parameter $offload CONFIG.SDO_STREAMING $sdo_streaming
+    ad_ip_parameter $offload CONFIG.ASYNC_TRIG 0
 
-  ad_ip_instance spi_engine_interconnect $interconnect
-  ad_ip_parameter $interconnect CONFIG.DATA_WIDTH $data_width
-  ad_ip_parameter $interconnect CONFIG.NUM_OF_SDI $num_sdi
+    ad_ip_instance spi_engine_interconnect $interconnect
+    ad_ip_parameter $interconnect CONFIG.DATA_WIDTH $data_width
+    ad_ip_parameter $interconnect CONFIG.NUM_OF_SDI $num_sdi
+  }
 
   # Connections based on vendor
   if {$vendor == "xilinx"} {
 
-    # Clock connections
-    ad_connect clk $axi_regmap/s_axi_aclk
-
     if {$async_spi_clk == 1} {
-      ad_connect spi_clk $offload/spi_clk
-      ad_connect spi_clk $offload/ctrl_clk
-      ad_connect spi_clk $execution/clk
-      ad_connect spi_clk $axi_regmap/spi_clk
-      ad_connect spi_clk $interconnect/clk
+      set inner_clk spi_clk
     } else {
-      ad_connect clk $offload/spi_clk
-      ad_connect clk $offload/ctrl_clk
-      ad_connect clk $execution/clk
-      ad_connect clk $axi_regmap/spi_clk
-      ad_connect clk $interconnect/clk
+      set inner_clk clk
     }
 
+    # Clock connections
+    ad_connect clk $axi_regmap/s_axi_aclk
+    ad_connect $inner_clk $axi_regmap/spi_clk
+    ad_connect $inner_clk $execution/clk
+
     if {$echo_sclk == 1} {
       ad_connect echo_sclk $execution/echo_sclk
     }
 
+    if {$offload_en == 1} {
+      ad_connect $inner_clk $offload/spi_clk
+      ad_connect $inner_clk $offload/ctrl_clk
+      ad_connect $inner_clk $interconnect/clk
+    }
+
     # Reset connections
-    ad_connect $axi_regmap/spi_resetn $offload/spi_resetn
     ad_connect $axi_regmap/spi_resetn $execution/resetn
-    ad_connect $axi_regmap/spi_resetn $interconnect/resetn
     ad_connect resetn $axi_regmap/s_axi_aresetn
+
+    if {$offload_en == 1} {
+      ad_connect $axi_regmap/spi_resetn $offload/spi_resetn
+      ad_connect $axi_regmap/spi_resetn $interconnect/resetn
+    }
+
+    # IRQ connection
     ad_connect irq $axi_regmap/irq
 
     #Data path connections
-    ad_connect $axi_regmap/spi_engine_offload_ctrl0 $offload/spi_engine_offload_ctrl
-    ad_connect $offload/m_interconnect_ctrl $interconnect/s_interconnect_ctrl
-    ad_connect $offload/spi_engine_ctrl $interconnect/s0_ctrl
-    ad_connect $axi_regmap/spi_engine_ctrl $interconnect/s1_ctrl
-    ad_connect $interconnect/m_ctrl $execution/ctrl
-    ad_connect $offload/offload_sdi m_axis_sample
-    ad_connect $offload/trigger trigger
     ad_connect $execution/spi m_spi
 
+    if {$offload_en == 1} {
+      ad_connect $axi_regmap/spi_engine_offload_ctrl0 $offload/spi_engine_offload_ctrl
+      ad_connect $offload/m_interconnect_ctrl $interconnect/s_interconnect_ctrl
+      ad_connect $offload/spi_engine_ctrl $interconnect/s0_ctrl
+      ad_connect $axi_regmap/spi_engine_ctrl $interconnect/s1_ctrl
+      ad_connect $interconnect/m_ctrl $execution/ctrl
+      ad_connect $offload/offload_sdi m_axis_sample
+      ad_connect $offload/trigger trigger
+    } else {
+      ad_connect $axi_regmap/spi_engine_ctrl $execution/ctrl
+    }
+
     if {$sdo_streaming == 1} {
       ad_connect $offload/s_axis_sdo s_axis_sample
     }
 
-
     # Exit hierarchy
     current_bd_instance /
 
@@ -193,35 +211,48 @@ proc spi_engine_create {args} {
     ad_connect $axi_clk $axi_regmap.s_axi_clock
     ad_connect $spi_clk $axi_regmap.if_spi_clk
     ad_connect $spi_clk $execution.if_clk
-    ad_connect $spi_clk $interconnect.if_clk
-    ad_connect $spi_clk $offload.if_ctrl_clk
-    ad_connect $spi_clk $offload.if_spi_clk
+
+    if {$offload_en == 1} {
+      ad_connect $spi_clk $interconnect.if_clk
+      ad_connect $spi_clk $offload.if_ctrl_clk
+      ad_connect $spi_clk $offload.if_spi_clk
+    }
 
     # Reset connections
-    ad_connect $axi_reset $axi_regmap.s_axi_reset
     ad_connect $axi_regmap.if_spi_resetn $execution.if_resetn
-    ad_connect $axi_regmap.if_spi_resetn $interconnect.if_resetn
-    ad_connect $axi_regmap.if_spi_resetn $offload.if_spi_resetn
+    ad_connect $axi_reset $axi_regmap.s_axi_reset
+
+    if {$offload_en == 1} {
+      ad_connect $axi_regmap.if_spi_resetn $offload.if_spi_resetn
+      ad_connect $axi_regmap.if_spi_resetn $interconnect.if_resetn
+    }
 
     # Data path connections
-    ad_connect $interconnect.m_cmd $execution.cmd
-    ad_connect $execution.sdi_data $interconnect.m_sdi
-    ad_connect $interconnect.m_sdo $execution.sdo_data
-    ad_connect $execution.sync $interconnect.m_sync
-    ad_connect $axi_regmap.cmd $interconnect.s1_cmd
-    ad_connect $interconnect.s1_sdi $axi_regmap.sdi_data
-    ad_connect $axi_regmap.sdo_data $interconnect.s1_sdo
-    ad_connect $interconnect.s1_sync $axi_regmap.sync
-    ad_connect $offload.cmd $interconnect.s0_cmd
-    ad_connect $interconnect.s0_sdi $offload.sdi_data
-    ad_connect $offload.sdo_data $interconnect.s0_sdo
-    ad_connect $interconnect.s0_sync $offload.sync
-    ad_connect $offload.m_interconnect_ctrl $interconnect.s_interconnect_ctrl
-    ad_connect $offload.ctrl_cmd_wr $axi_regmap.offload0_cmd
-    ad_connect $offload.ctrl_sdo_wr $axi_regmap.offload0_sdo
-    ad_connect $offload.if_ctrl_enable $axi_regmap.if_offload0_enable
-    ad_connect $offload.if_ctrl_enabled $axi_regmap.if_offload0_enabled
-    ad_connect $offload.if_ctrl_mem_reset $axi_regmap.if_offload0_mem_reset
-    ad_connect $offload.status_sync $axi_regmap.offload_sync
+    if {$offload_en == 1} {
+      ad_connect $offload.ctrl_cmd_wr $axi_regmap.offload0_cmd
+      ad_connect $offload.ctrl_sdo_wr $axi_regmap.offload0_sdo
+      ad_connect $offload.if_ctrl_enable $axi_regmap.if_offload0_enable
+      ad_connect $offload.if_ctrl_enabled $axi_regmap.if_offload0_enabled
+      ad_connect $offload.if_ctrl_mem_reset $axi_regmap.if_offload0_mem_reset
+      ad_connect $offload.status_sync $axi_regmap.offload_sync
+      ad_connect $offload.m_interconnect_ctrl $interconnect.s_interconnect_ctrl
+      ad_connect $offload.cmd $interconnect.s0_cmd
+      ad_connect $offload.sdo_data $interconnect.s0_sdo
+      ad_connect $interconnect.s0_sdi $offload.sdi_data
+      ad_connect $interconnect.s0_sync $offload.sync
+      ad_connect $axi_regmap.cmd $interconnect.s1_cmd
+      ad_connect $axi_regmap.sdo_data $interconnect.s1_sdo
+      ad_connect $interconnect.s1_sdi $axi_regmap.sdi_data
+      ad_connect $interconnect.s1_sync $axi_regmap.sync
+      ad_connect $interconnect.m_cmd $execution.cmd
+      ad_connect $interconnect.m_sdo $execution.sdo_data
+      ad_connect $execution.sdi_data $interconnect.m_sdi
+      ad_connect $execution.sync $interconnect.m_sync
+    } else {
+    ad_connect $axi_regmap.cmd $execution.cmd
+    ad_connect $axi_regmap.sdo_data $execution.sdo_data
+    ad_connect $execution.sdi_data $axi_regmap.sdi_data
+    ad_connect $execution.sync $axi_regmap.sync
+    }
   }
 }
\ No newline at end of file
diff --git a/projects/ad4052_ardz/common/ad4052_bd.tcl b/projects/ad4052_ardz/common/ad4052_bd.tcl
index 0b01a486e02..1488a93015f 100644
--- a/projects/ad4052_ardz/common/ad4052_bd.tcl
+++ b/projects/ad4052_ardz/common/ad4052_bd.tcl
@@ -9,17 +9,17 @@ create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_engine_rtl:1.0 a
 
 source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl
 
-set data_width    32
-set async_spi_clk 1
-set num_cs        1
-set num_sdi       1
-set num_sdo       1
-set sdi_delay     1
-set echo_sclk     0
-
-set hier_spi_engine spi_adc
-
-spi_engine_create $hier_spi_engine $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk
+set hier_spi_engine  spi_adc
+set data_width       32
+set async_spi_clk    1
+set offload_en       1
+set num_cs           1
+set num_sdi          1
+set num_sdo          1
+set sdi_delay        1
+set echo_sclk        0
+
+spi_engine_create $hier_spi_engine $data_width $async_spi_clk $offload_en $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk
 
 ad_ip_parameter $hier_spi_engine/${hier_spi_engine}_offload CONFIG.ASYNC_TRIG 1
 
diff --git a/projects/ad4052_ardz/common/ad4052_qsys.tcl b/projects/ad4052_ardz/common/ad4052_qsys.tcl
index 353a68732e9..f286858048d 100644
--- a/projects/ad4052_ardz/common/ad4052_qsys.tcl
+++ b/projects/ad4052_ardz/common/ad4052_qsys.tcl
@@ -60,20 +60,19 @@ set_connection_parameter_value spi_clk_pll.reconfig_to_pll/spi_clk_pll_reconfig.
 # spi engine
 source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl
 
-set spi_engine_hier spi_ad4052
-
-set data_width 32
-set async_spi_clk 1
-set num_cs 1
-set num_sdi 1
-set num_sdo 1
-set sdi_delay 0
-set echo_sclk 0
-set sdo_streaming 0
-
-set axi_clk sys_clk.clk
-set axi_reset sys_clk.clk_reset
-set spi_clk spi_clk_pll.outclk0
+set spi_engine_hier  spi_ad4052
+set axi_clk          sys_clk.clk
+set axi_reset        sys_clk.clk_reset
+set spi_clk          spi_clk_pll.outclk0
+set data_width       32
+set async_spi_clk    1
+set offload_en       1
+set num_cs           1
+set num_sdi          1
+set num_sdo          1
+set sdi_delay        0
+set echo_sclk        0
+set sdo_streaming    0
 
 spi_engine_create $spi_engine_hier $axi_clk $axi_reset $spi_clk $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk $sdo_streaming
 set_instance_parameter_value ${spi_engine_hier}_offload {ASYNC_TRIG} {1}
diff --git a/projects/ad411x_ad717x/common/ad411x_ad717x_asdz_qsys.tcl b/projects/ad411x_ad717x/common/ad411x_ad717x_asdz_qsys.tcl
index dc60a0b0b23..4010ec50e3d 100644
--- a/projects/ad411x_ad717x/common/ad411x_ad717x_asdz_qsys.tcl
+++ b/projects/ad411x_ad717x/common/ad411x_ad717x_asdz_qsys.tcl
@@ -20,22 +20,21 @@ set_instance_parameter_value util_sigma_delta_spi {NUM_OF_CS} {1}
 # spi engine
 source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl
 
-set spi_engine_hier spi_ad411x_ad717x
-
-set data_width 32
-set async_spi_clk 1
-set num_cs 1
-set num_sdi 1
-set num_sdo 1
-set sdi_delay 0
-set echo_sclk 0
-set sdo_streaming 0
-
-set axi_clk sys_clk.clk
-set axi_reset sys_clk.clk_reset
-set spi_clk sys_dma_clk.clk
-
-spi_engine_create $spi_engine_hier $axi_clk $axi_reset $spi_clk $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk $sdo_streaming
+set spi_engine_hier  spi_ad411x_ad717x
+set axi_clk          sys_clk.clk
+set axi_reset        sys_clk.clk_reset
+set spi_clk          sys_dma_clk.clk
+set data_width       32
+set async_spi_clk    1
+set offload_en       1
+set num_cs           1
+set num_sdi          1
+set num_sdo          1
+set sdi_delay        0
+set echo_sclk        0
+set sdo_streaming    0
+
+spi_engine_create $spi_engine_hier $axi_clk $axi_reset $spi_clk $data_width $async_spi_clk $offload_en $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk $sdo_streaming
 set_instance_parameter_value ${spi_engine_hier}_offload {ASYNC_TRIG}    {1}
 
 # exported interface
diff --git a/projects/ad4134_fmc/common/ad4134_bd.tcl b/projects/ad4134_fmc/common/ad4134_bd.tcl
index 255ef9292d4..1436ce3aa61 100644
--- a/projects/ad4134_fmc/common/ad4134_bd.tcl
+++ b/projects/ad4134_fmc/common/ad4134_bd.tcl
@@ -10,17 +10,17 @@ create_bd_port -dir O ad4134_odr
 
 source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl
 
-set data_width    32
-set async_spi_clk 1
-set num_cs        1
-set num_sdi       4
-set num_sdo       0
-set sdi_delay     0
-set echo_sclk     0
-
-set hier_spi_engine spi_ad4134
-
-spi_engine_create $hier_spi_engine $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk
+set hier_spi_engine  spi_ad4134
+set data_width       32
+set async_spi_clk    1
+set offload_en       1
+set num_cs           1
+set num_sdi          4
+set num_sdo          0
+set sdi_delay        0
+set echo_sclk        0
+
+spi_engine_create $hier_spi_engine $data_width $async_spi_clk $offload_en $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk
 
 # clkgen
 
diff --git a/projects/ad4170_asdz/common/ad4170_asdz_bd.tcl b/projects/ad4170_asdz/common/ad4170_asdz_bd.tcl
index a89e1a34230..f70d0309a92 100644
--- a/projects/ad4170_asdz/common/ad4170_asdz_bd.tcl
+++ b/projects/ad4170_asdz/common/ad4170_asdz_bd.tcl
@@ -9,17 +9,17 @@ create_bd_port -dir I adc_data_ready
 
 source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl
 
-set data_width    32
-set async_spi_clk 1
-set num_cs        1
-set num_sdi       1
-set num_sdo       1
-set sdi_delay     0
-set echo_sclk     0
-
-set hier_spi_engine spi_ad4170
-
-spi_engine_create $hier_spi_engine $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk
+set hier_spi_engine  spi_ad4170
+set data_width       32
+set async_spi_clk    1
+set offload_en       1
+set num_cs           1
+set num_sdi          1
+set num_sdo          1
+set sdi_delay        0
+set echo_sclk        0
+
+spi_engine_create $hier_spi_engine $data_width $async_spi_clk $offload_en $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk
 
 # Generate a 80MHz spi_clk for the SPI Engine (targeted SCLK is 20MHz)
 
diff --git a/projects/ad4170_asdz/common/ad4170_asdz_qsys.tcl b/projects/ad4170_asdz/common/ad4170_asdz_qsys.tcl
index a7a44e79d35..32088b87f10 100644
--- a/projects/ad4170_asdz/common/ad4170_asdz_qsys.tcl
+++ b/projects/ad4170_asdz/common/ad4170_asdz_qsys.tcl
@@ -16,22 +16,21 @@ set_instance_parameter_value axi_dmac_0 {DMA_DATA_WIDTH_DEST} {64}
 # spi engine
 source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl
 
-set spi_engine_hier spi_ad4170
-
-set data_width 32
-set async_spi_clk 1
-set num_cs 1
-set num_sdi 1
-set num_sdo 1
-set sdi_delay 0
-set echo_sclk 0
-set sdo_streaming 0
-
-set axi_clk sys_clk.clk
-set axi_reset sys_clk.clk_reset
-set spi_clk sys_dma_clk.clk
-
-spi_engine_create $spi_engine_hier $axi_clk $axi_reset $spi_clk $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk $sdo_streaming
+set spi_engine_hier  spi_ad4170
+set axi_clk          sys_clk.clk
+set axi_reset        sys_clk.clk_reset
+set spi_clk          sys_dma_clk.clk
+set data_width       32
+set async_spi_clk    1
+set offload_en       1
+set num_cs           1
+set num_sdi          1
+set num_sdo          1
+set sdi_delay        0
+set echo_sclk        0
+set sdo_streaming    0
+
+spi_engine_create $spi_engine_hier $axi_clk $axi_reset $spi_clk $data_width $async_spi_clk $offload_en $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk $sdo_streaming
 set_instance_parameter_value ${spi_engine_hier}_offload {ASYNC_TRIG} {1}
 
 # exported interface
diff --git a/projects/ad4630_fmc/common/ad463x_bd.tcl b/projects/ad4630_fmc/common/ad463x_bd.tcl
index 0be531bfbc3..99ef08e8fb0 100644
--- a/projects/ad4630_fmc/common/ad463x_bd.tcl
+++ b/projects/ad4630_fmc/common/ad463x_bd.tcl
@@ -51,19 +51,19 @@ ad_connect spi_clk spi_clkgen/clk_0
 
 # create a SPI Engine architecture
 
-#spi_engine_create "spi_ad463x" 32         1             1       $NUM_OF_SDI 0          1
-
-set data_width    32
-set async_spi_clk 1
-set num_cs        1
-set num_sdi       $NUM_OF_SDI
-set num_sdo       1
-set sdi_delay     1
-set echo_sclk     1
-
-set hier_spi_engine spi_ad463x
-
-spi_engine_create $hier_spi_engine $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk
+#spi_engine_create "spi_ad463x" 32         1            1             1       $NUM_OF_SDI 0          1
+
+set hier_spi_engine  spi_ad463x
+set data_width       32
+set async_spi_clk    1
+set offload_en       1
+set num_cs           1
+set num_sdi          $NUM_OF_SDI
+set num_sdo          1
+set sdi_delay        1
+set echo_sclk        1
+
+spi_engine_create $hier_spi_engine $data_width $async_spi_clk $offload_en $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk
 
 ad_ip_parameter $hier_spi_engine/${hier_spi_engine}_execution CONFIG.DEFAULT_SPI_CFG 1   ; # latching MISO on negative edge - hardware only
 
diff --git a/projects/ad469x_evb/common/ad469x_bd.tcl b/projects/ad469x_evb/common/ad469x_bd.tcl
index 93c71dd47db..c726bc9a887 100644
--- a/projects/ad469x_evb/common/ad469x_bd.tcl
+++ b/projects/ad469x_evb/common/ad469x_bd.tcl
@@ -16,17 +16,17 @@ create_bd_port -dir I gpio_cnv
 
 source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl
 
-set data_width    32
-set async_spi_clk 1
-set num_cs        1
-set num_sdi       1
-set num_sdo       1
-set sdi_delay     1
-set echo_sclk     0
-
-set hier_spi_engine spi_ad469x
-
-spi_engine_create $hier_spi_engine $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk
+set hier_spi_engine  spi_ad469x
+set data_width       32
+set async_spi_clk    1
+set offload_en       1
+set num_cs           1
+set num_sdi          1
+set num_sdo          1
+set sdi_delay        1
+set echo_sclk        0
+
+spi_engine_create $hier_spi_engine $data_width $async_spi_clk $offload_en $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk
 
 # To support the 1MSPS (SCLK == 80 MHz), set the spi clock to 160 MHz
 
diff --git a/projects/ad469x_evb/common/ad469x_qsys.tcl b/projects/ad469x_evb/common/ad469x_qsys.tcl
index 162c090f82b..90550672943 100644
--- a/projects/ad469x_evb/common/ad469x_qsys.tcl
+++ b/projects/ad469x_evb/common/ad469x_qsys.tcl
@@ -63,20 +63,18 @@ set_connection_parameter_value spi_clk_pll.reconfig_to_pll/spi_clk_pll_reconfig.
 # spi engine
 source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl
 
-set spi_engine_hier ad469x_spi
-
-set data_width 32
-set async_spi_clk 1
-set num_cs 1
-set num_sdi 1
-set num_sdo 1
-set sdi_delay 0
-set echo_sclk 0
-set sdo_streaming 0
-
-set axi_clk sys_clk.clk
-set axi_reset sys_clk.clk_reset
-set spi_clk spi_clk_pll.outclk0
+set spi_engine_hier  ad469x_spi
+set axi_clk          sys_clk.clk
+set axi_reset        sys_clk.clk_reset
+set spi_clk          spi_clk_pll.outclk0
+set data_width       32
+set async_spi_clk    1
+set num_cs           1
+set num_sdi          1
+set num_sdo          1
+set sdi_delay        0
+set echo_sclk        0
+set sdo_streaming    0
 
 spi_engine_create $spi_engine_hier $axi_clk $axi_reset $spi_clk $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk $sdo_streaming
 set_instance_parameter_value ${spi_engine_hier}_offload {ASYNC_TRIG} {1}
diff --git a/projects/ad57xx_ardz/common/ad57xx_ardz_bd.tcl b/projects/ad57xx_ardz/common/ad57xx_ardz_bd.tcl
index 35330a82881..143757d02ca 100644
--- a/projects/ad57xx_ardz/common/ad57xx_ardz_bd.tcl
+++ b/projects/ad57xx_ardz/common/ad57xx_ardz_bd.tcl
@@ -11,18 +11,18 @@ create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_engine_rtl:1.0 a
 
 source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl
 
-set data_width    32
-set async_spi_clk 1
-set num_cs        1
-set num_sdi       1
-set num_sdo       1
-set sdi_delay     0
-set echo_sclk     0
-set sdo_streaming 1
-
-set hier_spi_engine spi_ad57xx
-
-spi_engine_create $hier_spi_engine $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk $sdo_streaming
+set hier_spi_engine  spi_ad57xx
+set data_width       32
+set async_spi_clk    1
+set offload_en       1
+set num_cs           1
+set num_sdi          1
+set num_sdo          1
+set sdi_delay        0
+set echo_sclk        0
+set sdo_streaming    1
+
+spi_engine_create $hier_spi_engine $data_width $async_spi_clk $offload_en $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk $sdo_streaming
 
 # clkgen
 
diff --git a/projects/ad57xx_ardz/common/ad57xx_ardz_qsys.tcl b/projects/ad57xx_ardz/common/ad57xx_ardz_qsys.tcl
index d8bbdddcd3e..3e2bfffa7fc 100644
--- a/projects/ad57xx_ardz/common/ad57xx_ardz_qsys.tcl
+++ b/projects/ad57xx_ardz/common/ad57xx_ardz_qsys.tcl
@@ -62,22 +62,21 @@ set_connection_parameter_value spi_clk_pll.reconfig_to_pll/spi_clk_pll_reconfig.
 # spi engine
 source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl
 
-set spi_engine_hier spi_ad57xx
-
-set data_width 32
-set async_spi_clk 1
-set num_cs 1
-set num_sdi 1
-set num_sdo 1
-set sdi_delay 0
-set echo_sclk 0
-set sdo_streaming 1
-
-set axi_clk sys_clk.clk
-set axi_reset sys_clk.clk_reset
-set spi_clk spi_clk_pll.outclk0
-
-spi_engine_create $spi_engine_hier $axi_clk $axi_reset $spi_clk $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk $sdo_streaming
+set spi_engine_hier  spi_ad57xx
+set axi_clk          sys_clk.clk
+set axi_reset        sys_clk.clk_reset
+set spi_clk          spi_clk_pll.outclk0
+set data_width       32
+set async_spi_clk    1
+set offload_en       1
+set num_cs           1
+set num_sdi          1
+set num_sdo          1
+set sdi_delay        0
+set echo_sclk        0
+set sdo_streaming    1
+
+spi_engine_create $spi_engine_hier $axi_clk $axi_reset $spi_clk $data_width $async_spi_clk $offload_en $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk $sdo_streaming
 
 # exported interface
 
diff --git a/projects/ad7134_fmc/common/ad7134_bd.tcl b/projects/ad7134_fmc/common/ad7134_bd.tcl
index a861bc3f70f..c09c18ad53a 100644
--- a/projects/ad7134_fmc/common/ad7134_bd.tcl
+++ b/projects/ad7134_fmc/common/ad7134_bd.tcl
@@ -11,18 +11,18 @@ create_bd_port -dir O ad713x_sdpclk
 # this design supports AD7132/AD7134/AD7136
 
 source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl
- 
-set data_width    32
-set async_spi_clk 1
-set num_cs        1
-set num_sdi       8
-set num_sdo       0
-set sdi_delay     0
-set echo_sclk     0
-
-set hier_spi_engine dual_ad7134
-
-spi_engine_create $hier_spi_engine $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk
+
+set hier_spi_engine  dual_ad7134
+set data_width       32
+set async_spi_clk    1
+set offload_en       1
+set num_cs           1
+set num_sdi          8
+set num_sdo          0
+set sdi_delay        0
+set echo_sclk        0
+
+spi_engine_create $hier_spi_engine $data_width $async_spi_clk $offload_en $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk
 
 # clkgen
 
diff --git a/projects/ad738x_fmc/common/ad738x_bd.tcl b/projects/ad738x_fmc/common/ad738x_bd.tcl
index b1a95a2d829..53c876e5e9e 100644
--- a/projects/ad738x_fmc/common/ad738x_bd.tcl
+++ b/projects/ad738x_fmc/common/ad738x_bd.tcl
@@ -15,17 +15,17 @@ create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_engine_rtl:1.0 a
 
 source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl
 
-set data_width    32
-set async_spi_clk 1
-set num_cs        1
-set num_sdi       [expr {$ALERT_SPI_N ? 1 : $NUM_OF_SDI}]
-set num_sdo       1
-set sdi_delay     1
-set echo_sclk     0
-
-set hier_spi_engine spi_ad738x_adc
-
-spi_engine_create $hier_spi_engine $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk
+set hier_spi_engine  spi_ad738x_adc
+set data_width       32
+set async_spi_clk    1
+set offload_en       1
+set num_cs           1
+set num_sdi          [expr {$ALERT_SPI_N ? 1 : $NUM_OF_SDI}]
+set num_sdo          1
+set sdi_delay        1
+set echo_sclk        0
+
+spi_engine_create $hier_spi_engine $data_width $async_spi_clk $offload_en $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk
 
 ad_ip_instance axi_pwm_gen spi_trigger_gen
 # 300ns pwm period
diff --git a/projects/ad7606x_fmc/common/ad7606x_bd.tcl b/projects/ad7606x_fmc/common/ad7606x_bd.tcl
index 2ea60699faf..f6ffd5b167c 100644
--- a/projects/ad7606x_fmc/common/ad7606x_bd.tcl
+++ b/projects/ad7606x_fmc/common/ad7606x_bd.tcl
@@ -116,16 +116,16 @@ switch $INTF {
     # spi engine
     source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl
 
-    set data_width    32
-    set async_spi_clk 1
-    set num_cs        1
-    set num_sdi       $NUM_OF_SDI
-    set num_sdo       1
-    set sdi_delay     1
-
-    set hier_spi_engine spi_ad7606
-
-    spi_engine_create $hier_spi_engine $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay
+    set hier_spi_engine  spi_ad7606
+    set data_width       32
+    set async_spi_clk    1
+    set offload_en       1
+    set num_cs           1
+    set num_sdi          $NUM_OF_SDI
+    set num_sdo          1
+    set sdi_delay        1
+
+    spi_engine_create $hier_spi_engine $data_width $async_spi_clk $offload_en $num_cs $num_sdi $num_sdo $sdi_delay
 
     # axi_pwm_gen
     ad_ip_parameter ad7606_pwm_gen CONFIG.PULSE_0_PERIOD 120
diff --git a/projects/ad7616_sdz/common/ad7616_bd.tcl b/projects/ad7616_sdz/common/ad7616_bd.tcl
index d628377c6ef..9c1bf31aeb5 100644
--- a/projects/ad7616_sdz/common/ad7616_bd.tcl
+++ b/projects/ad7616_sdz/common/ad7616_bd.tcl
@@ -53,12 +53,13 @@ if {$INTF == 1} {
 
   set data_width    16
   set async_spi_clk 1
+  set offload_en    1
   set num_cs        1
   set num_sdi       $NUM_OF_SDI
   set sdi_delay     1
   set hier_spi_engine spi_ad7616
 
-  spi_engine_create $hier_spi_engine $data_width $async_spi_clk $num_cs $num_sdi $sdi_delay
+  spi_engine_create $hier_spi_engine $data_width $async_spi_clk $offload_en $num_cs $num_sdi $sdi_delay
 
   ad_ip_parameter axi_ad7616_dma CONFIG.DMA_DATA_WIDTH_SRC [expr $data_width * $num_sdi]
   ad_ip_parameter axi_ad7616_dma CONFIG.DMA_TYPE_SRC 1
diff --git a/projects/ad77681evb/common/ad77681evb_bd.tcl b/projects/ad77681evb/common/ad77681evb_bd.tcl
index 87db7c51c3a..0fdf86482ce 100644
--- a/projects/ad77681evb/common/ad77681evb_bd.tcl
+++ b/projects/ad77681evb/common/ad77681evb_bd.tcl
@@ -11,17 +11,17 @@ create_bd_port -dir I adc_data_ready
 
 source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl
 
-set data_width    32
-set async_spi_clk 1
-set num_cs        1
-set num_sdi       1
-set num_sdo       1
-set sdi_delay     1
-set echo_sclk     0
-
-set hier_spi_engine spi_ad77681
-
-spi_engine_create $hier_spi_engine $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk
+set hier_spi_engine  spi_ad77681
+set data_width       32
+set async_spi_clk    1
+set offload_en       1
+set num_cs           1
+set num_sdi          1
+set num_sdo          1
+set sdi_delay        1
+set echo_sclk        0
+
+spi_engine_create $hier_spi_engine $data_width $async_spi_clk $offload_en $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk
 
 ad_ip_parameter $hier_spi_engine/${hier_spi_engine}_offload CONFIG.ASYNC_TRIG 1
 
diff --git a/projects/adaq7980_sdz/common/adaq7980_bd.tcl b/projects/adaq7980_sdz/common/adaq7980_bd.tcl
index 6f81d32e770..7042c1a8f56 100644
--- a/projects/adaq7980_sdz/common/adaq7980_bd.tcl
+++ b/projects/adaq7980_sdz/common/adaq7980_bd.tcl
@@ -6,17 +6,17 @@
 create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_engine_rtl:1.0 adaq7980_spi
 source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl
 
-set data_width    16
-set async_spi_clk 1 
-set num_cs        1
-set num_sdi       1 
-set num_sdo       1 
-set sdi_delay     1 
-set echo_sclk     0 
+set hier_spi_engine  spi_adaq7980_adc
+set data_width       16
+set async_spi_clk    1
+set offload_en       1
+set num_cs           1
+set num_sdi          1
+set num_sdo          1
+set sdi_delay        1
+set echo_sclk        0
 
-set hier_spi_engine spi_adaq7980_adc
-
-spi_engine_create $hier_spi_engine $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk
+spi_engine_create $hier_spi_engine $data_width $async_spi_clk $offload_en $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk
 
 # axi_pwm_gen
 ad_ip_instance axi_pwm_gen spi_trigger_gen
diff --git a/projects/cn0363/common/cn0363_bd.tcl b/projects/cn0363/common/cn0363_bd.tcl
index a03302e3a3a..bb1d5c63554 100644
--- a/projects/cn0363/common/cn0363_bd.tcl
+++ b/projects/cn0363/common/cn0363_bd.tcl
@@ -47,17 +47,17 @@ ad_ip_parameter axi_dma CONFIG.DMA_AXI_PROTOCOL_DEST 1
 
 # Create SPI engine controller with offload
 
-set data_width    8
-set async_spi_clk 0
-set num_cs        2
-set num_sdi       1
-set num_sdo       1
-set sdi_delay     1
-set echo_sclk     0
-
-set hier_spi_engine spi_cn0363
-
-spi_engine_create $hier_spi_engine $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk
+set hier_spi_engine  spi_cn0363
+set data_width       8
+set async_spi_clk    0
+set offload_en       1
+set num_cs           2
+set num_sdi          1
+set num_sdo          1
+set sdi_delay        1
+set echo_sclk        0
+
+spi_engine_create $hier_spi_engine $data_width $async_spi_clk $offload_en $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk
 
 ad_connect $sys_cpu_clk $hier_spi_engine/clk
 ad_connect sys_cpu_resetn $hier_spi_engine/resetn
diff --git a/projects/cn0540/common/cn0540_bd.tcl b/projects/cn0540/common/cn0540_bd.tcl
index 55f6d2c18fc..182f387a31e 100755
--- a/projects/cn0540/common/cn0540_bd.tcl
+++ b/projects/cn0540/common/cn0540_bd.tcl
@@ -16,17 +16,17 @@ create_bd_port -dir I adc_data_ready
 
 source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl
 
-set data_width    32
-set async_spi_clk 1
-set num_cs        1
-set num_sdi       1
-set num_sdo       1
-set sdi_delay     0
-set echo_sclk     0
-
-set hier_spi_engine spi_cn0540
-
-spi_engine_create $hier_spi_engine $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk
+set hier_spi_engine  spi_cn0540
+set data_width       32
+set async_spi_clk    1
+set offload_en       1
+set num_cs           1
+set num_sdi          1
+set num_sdo          1
+set sdi_delay        0
+set echo_sclk        0
+
+spi_engine_create $hier_spi_engine $data_width $async_spi_clk $offload_en $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk
 
 # Generate a 80MHz spi_clk for the SPI Engine (targeted SCLK is 20MHz)
 
diff --git a/projects/cn0540/common/cn0540_qsys.tcl b/projects/cn0540/common/cn0540_qsys.tcl
index b5adf8a4d2f..69a31c51235 100755
--- a/projects/cn0540/common/cn0540_qsys.tcl
+++ b/projects/cn0540/common/cn0540_qsys.tcl
@@ -15,22 +15,21 @@ set_instance_parameter_value axi_dmac_0 {DMA_DATA_WIDTH_DEST} {128}
 # spi engine
 source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl
 
-set spi_engine_hier cn0540_spi
-
-set data_width 32
-set async_spi_clk 1
-set num_cs 1
-set num_sdi 1
-set num_sdo 1
-set sdi_delay 0
-set echo_sclk 0
-set sdo_streaming 0
-
-set axi_clk sys_clk.clk
-set axi_reset sys_clk.clk_reset
-set spi_clk sys_dma_clk.clk
-
-spi_engine_create $spi_engine_hier $axi_clk $axi_reset $spi_clk $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk $sdo_streaming
+set spi_engine_hier  cn0540_spi
+set axi_clk          sys_clk.clk
+set axi_reset        sys_clk.clk_reset
+set spi_clk          sys_dma_clk.clk
+set data_width       32
+set async_spi_clk    1
+set offload_en       1
+set num_cs           1
+set num_sdi          1
+set num_sdo          1
+set sdi_delay        0
+set echo_sclk        0
+set sdo_streaming    0
+
+spi_engine_create $spi_engine_hier $axi_clk $axi_reset $spi_clk $data_width $async_spi_clk $offload_en $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk $sdo_streaming
 set_instance_parameter_value ${spi_engine_hier}_offload {ASYNC_TRIG} {1}
 
 # exported interface
diff --git a/projects/cn0561/common/cn0561_bd.tcl b/projects/cn0561/common/cn0561_bd.tcl
index d0ecf3424a7..e8422828354 100644
--- a/projects/cn0561/common/cn0561_bd.tcl
+++ b/projects/cn0561/common/cn0561_bd.tcl
@@ -10,17 +10,17 @@ create_bd_port -dir O cn0561_odr
 
 source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl
 
-set data_width    32
-set async_spi_clk 1
-set num_cs        1
-set num_sdi       4
-set num_sdo       0
-set sdi_delay     0
-set echo_sclk     0
-
-set hier_spi_engine spi_cn0561
-
-spi_engine_create $hier_spi_engine $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk
+set hier_spi_engine  spi_cn0561
+set data_width       32
+set async_spi_clk    1
+set offload_en       1
+set num_cs           1
+set num_sdi          4
+set num_sdo          0
+set sdi_delay        0
+set echo_sclk        0
+
+spi_engine_create $hier_spi_engine $data_width $async_spi_clk $offload_en $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk
 
 # clkgen
 
diff --git a/projects/cn0561/common/cn0561_qsys.tcl b/projects/cn0561/common/cn0561_qsys.tcl
index e3dd25dca61..3633933a4ea 100644
--- a/projects/cn0561/common/cn0561_qsys.tcl
+++ b/projects/cn0561/common/cn0561_qsys.tcl
@@ -64,22 +64,21 @@ set_connection_parameter_value spi_clk_pll.reconfig_to_pll/spi_clk_pll_reconfig.
 # spi engine
 source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl
 
-set spi_engine_hier cn0561_spi
-
-set data_width 32
-set async_spi_clk 1
-set num_cs 1
-set num_sdi 4
-set num_sdo 1
-set sdi_delay 0
-set echo_sclk 0
-set sdo_streaming 0
-
-set axi_clk sys_clk.clk
-set axi_reset sys_clk.clk_reset
-set spi_clk spi_clk_pll.outclk0
-
-spi_engine_create $spi_engine_hier $axi_clk $axi_reset $spi_clk $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk $sdo_streaming
+set spi_engine_hier  cn0561_spi
+set axi_clk          sys_clk.clk
+set axi_reset        sys_clk.clk_reset
+set spi_clk          spi_clk_pll.outclk0
+set data_width       32
+set async_spi_clk    1
+set offload_en       1
+set num_cs           1
+set num_sdi          4
+set num_sdo          1
+set sdi_delay        0
+set echo_sclk        0
+set sdo_streaming    0
+
+spi_engine_create $spi_engine_hier $axi_clk $axi_reset $spi_clk $data_width $async_spi_clk $offload_en $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk $sdo_streaming
 set_instance_parameter_value ${spi_engine_hier}_offload {ASYNC_TRIG} {1}
 
 # exported interface
diff --git a/projects/ltc2378_fmc/common/ltc2378_bd.tcl b/projects/ltc2378_fmc/common/ltc2378_bd.tcl
index 98ca2bc8097..43f83af0db7 100644
--- a/projects/ltc2378_fmc/common/ltc2378_bd.tcl
+++ b/projects/ltc2378_fmc/common/ltc2378_bd.tcl
@@ -10,17 +10,17 @@ create_bd_port -dir I ltc2378_ext_clk
 
 source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl
 
-set data_width    32
-set async_spi_clk 1
-set num_cs        1
-set num_sdi       1
-set num_sdo       1
-set sdi_delay     0
-set echo_sclk     0
-
-set hier_spi_engine spi_ltc2378
-
-spi_engine_create $hier_spi_engine $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk
+set hier_spi_engine  spi_ltc2378
+set data_width       32
+set async_spi_clk    1
+set offload_en       1
+set num_cs           1
+set num_sdi          1
+set num_sdo          1
+set sdi_delay        0
+set echo_sclk        0
+
+spi_engine_create $hier_spi_engine $data_width $async_spi_clk $offload_en $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk
 
 # activate internal SPI Engine Offload synchronizer
 ad_ip_parameter $hier_spi_engine/${hier_spi_engine}_offload CONFIG.ASYNC_TRIG 1
diff --git a/projects/pulsar_adc/common/pulsar_adc_bd.tcl b/projects/pulsar_adc/common/pulsar_adc_bd.tcl
index eec33060ad5..5558c8ac5f7 100644
--- a/projects/pulsar_adc/common/pulsar_adc_bd.tcl
+++ b/projects/pulsar_adc/common/pulsar_adc_bd.tcl
@@ -7,17 +7,17 @@ create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_engine_rtl:1.0 p
 source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl
 
 # If the ADC resolution <= 16, data_width is set 16 else 32
-set data_width    32
-set async_spi_clk 1
-set num_cs        1
-set num_sdi       1
-set num_sdo       1
-set sdi_delay     1
-set echo_sclk     0
+set hier_spi_engine  spi_pulsar_adc
+set data_width       32
+set async_spi_clk    1
+set offload_en       1
+set num_cs           1
+set num_sdi          1
+set num_sdo          1
+set sdi_delay        1
+set echo_sclk        0
 
-set hier_spi_engine spi_pulsar_adc
-
-spi_engine_create $hier_spi_engine $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk
+spi_engine_create $hier_spi_engine $data_width $async_spi_clk $offload_en $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk
 
 ad_ip_instance axi_clkgen spi_clkgen
 ad_ip_parameter spi_clkgen CONFIG.CLK0_DIV 5