From e780ce7bcd2c6f716d26c8f9e046a3401104d4c4 Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Mon, 27 May 2024 12:15:15 +0800 Subject: [PATCH 0001/1868] drm/amdgpu: Add flags to distinguish vf/pf/pt mode Add extra flag definition for ids_flag field to distinguish between vf/pf/pt modes v2: Updated kms driver minor version & removed pf check as default is 0 v3: Fix up version (Alex) Signed-off-by: Asad Kamal Reviewed-by: Lijo Lazar Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 9 +++++++++ include/uapi/drm/amdgpu_drm.h | 10 ++++++++++ 3 files changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 094498a0964b5..b9bab30caa66a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -117,9 +117,10 @@ * - 3.56.0 - Update IB start address and size alignment for decode and encode * - 3.57.0 - Compute tunneling on GFX10+ * - 3.58.0 - Add GFX12 DCC support + * - 3.59.0 - Add AMDGPU_IDS_FLAGS_MODE_PF, AMDGPU_IDS_FLAGS_MODE_VF & AMDGPU_IDS_FLAGS_MODE_PT */ #define KMS_DRIVER_MAJOR 3 -#define KMS_DRIVER_MINOR 58 +#define KMS_DRIVER_MINOR 59 #define KMS_DRIVER_PATCHLEVEL 0 /* diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index 96af9ff1acb67..d9fde38f6ee27 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -888,6 +888,15 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) if (adev->gfx.config.ta_cntl2_truncate_coord_mode) dev_info->ids_flags |= AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD; + if (amdgpu_passthrough(adev)) + dev_info->ids_flags |= (AMDGPU_IDS_FLAGS_MODE_PT << + AMDGPU_IDS_FLAGS_MODE_SHIFT) & + AMDGPU_IDS_FLAGS_MODE_MASK; + else if (amdgpu_sriov_vf(adev)) + dev_info->ids_flags |= (AMDGPU_IDS_FLAGS_MODE_VF << + AMDGPU_IDS_FLAGS_MODE_SHIFT) & + AMDGPU_IDS_FLAGS_MODE_MASK; + vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; vm_size -= AMDGPU_VA_RESERVED_TOP; diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index efe5de6ce208a..e8135ebb51b7b 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -756,6 +756,16 @@ struct drm_amdgpu_cs_chunk_cp_gfx_shadow { #define AMDGPU_IDS_FLAGS_TMZ 0x4 #define AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD 0x8 +/* + * Query h/w info: Flag identifying VF/PF/PT mode + * + */ +#define AMDGPU_IDS_FLAGS_MODE_MASK 0x300 +#define AMDGPU_IDS_FLAGS_MODE_SHIFT 0x8 +#define AMDGPU_IDS_FLAGS_MODE_PF 0x0 +#define AMDGPU_IDS_FLAGS_MODE_VF 0x1 +#define AMDGPU_IDS_FLAGS_MODE_PT 0x2 + /* indicate if acceleration can be working */ #define AMDGPU_INFO_ACCEL_WORKING 0x00 /* get the crtc_id from the mode object id? */ From 0228c214deebf8f05f7d158b688beb747e4183fa Mon Sep 17 00:00:00 2001 From: Yong Zhao Date: Tue, 10 Sep 2019 11:24:42 -0400 Subject: [PATCH 0002/1868] Add rock-dbg_defconfig which turns on KFD This file only turns on a substantial smaller set of kernel options, together with all AMD stuff, and supports most use cases on common HW configurations. As a result, building kernel with this config is super fast. Moreover, with this config, KFD folks can easily build the kernel with build_kernel.sh script and verify the change before we push the commit out for review on amd-gfx mailist. Signed-off-by: Yong Zhao Signed-off-by: Alex Deucher --- arch/x86/configs/rock-dbg_defconfig | 4688 +++++++++++++++++++++++++++ 1 file changed, 4688 insertions(+) create mode 100644 arch/x86/configs/rock-dbg_defconfig diff --git a/arch/x86/configs/rock-dbg_defconfig b/arch/x86/configs/rock-dbg_defconfig new file mode 100644 index 0000000000000..5e1de51be9553 --- /dev/null +++ b/arch/x86/configs/rock-dbg_defconfig @@ -0,0 +1,4688 @@ +# +# Automatically generated file; DO NOT EDIT. +# Linux/x86 5.3.0-rc3 Kernel Configuration +# + +# +# Compiler: gcc (Ubuntu 7.4.0-1ubuntu1~18.04.1) 7.4.0 +# +CONFIG_CC_IS_GCC=y +CONFIG_GCC_VERSION=70400 +CONFIG_CLANG_VERSION=0 +CONFIG_CC_CAN_LINK=y +CONFIG_CC_HAS_ASM_GOTO=y +CONFIG_CC_HAS_WARN_MAYBE_UNINITIALIZED=y +CONFIG_IRQ_WORK=y +CONFIG_BUILDTIME_EXTABLE_SORT=y +CONFIG_THREAD_INFO_IN_TASK=y + +# +# General setup +# +CONFIG_INIT_ENV_ARG_LIMIT=32 +# CONFIG_COMPILE_TEST is not set +# CONFIG_HEADER_TEST is not set +CONFIG_LOCALVERSION="-kfd" +# CONFIG_LOCALVERSION_AUTO is not set +CONFIG_BUILD_SALT="" +CONFIG_HAVE_KERNEL_GZIP=y +CONFIG_HAVE_KERNEL_BZIP2=y +CONFIG_HAVE_KERNEL_LZMA=y +CONFIG_HAVE_KERNEL_XZ=y +CONFIG_HAVE_KERNEL_LZO=y +CONFIG_HAVE_KERNEL_LZ4=y +CONFIG_KERNEL_GZIP=y +# CONFIG_KERNEL_BZIP2 is not set +# CONFIG_KERNEL_LZMA is not set +# CONFIG_KERNEL_XZ is not set +# CONFIG_KERNEL_LZO is not set +# CONFIG_KERNEL_LZ4 is not set +CONFIG_DEFAULT_HOSTNAME="(none)" +CONFIG_SWAP=y +CONFIG_SYSVIPC=y +CONFIG_SYSVIPC_SYSCTL=y +CONFIG_POSIX_MQUEUE=y +CONFIG_POSIX_MQUEUE_SYSCTL=y +CONFIG_CROSS_MEMORY_ATTACH=y +CONFIG_USELIB=y +CONFIG_AUDIT=y +CONFIG_HAVE_ARCH_AUDITSYSCALL=y +CONFIG_AUDITSYSCALL=y + +# +# IRQ subsystem +# +CONFIG_GENERIC_IRQ_PROBE=y +CONFIG_GENERIC_IRQ_SHOW=y +CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y +CONFIG_GENERIC_PENDING_IRQ=y +CONFIG_GENERIC_IRQ_MIGRATION=y +CONFIG_IRQ_DOMAIN=y +CONFIG_IRQ_DOMAIN_HIERARCHY=y +CONFIG_GENERIC_MSI_IRQ=y +CONFIG_GENERIC_MSI_IRQ_DOMAIN=y +CONFIG_GENERIC_IRQ_MATRIX_ALLOCATOR=y +CONFIG_GENERIC_IRQ_RESERVATION_MODE=y +CONFIG_IRQ_FORCED_THREADING=y +CONFIG_SPARSE_IRQ=y +# CONFIG_GENERIC_IRQ_DEBUGFS is not set +# end of IRQ subsystem + +CONFIG_CLOCKSOURCE_WATCHDOG=y +CONFIG_ARCH_CLOCKSOURCE_DATA=y +CONFIG_ARCH_CLOCKSOURCE_INIT=y +CONFIG_CLOCKSOURCE_VALIDATE_LAST_CYCLE=y +CONFIG_GENERIC_TIME_VSYSCALL=y +CONFIG_GENERIC_CLOCKEVENTS=y +CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y +CONFIG_GENERIC_CLOCKEVENTS_MIN_ADJUST=y +CONFIG_GENERIC_CMOS_UPDATE=y + +# +# Timers subsystem +# +CONFIG_TICK_ONESHOT=y +CONFIG_NO_HZ_COMMON=y +# CONFIG_HZ_PERIODIC is not set +CONFIG_NO_HZ_IDLE=y +# CONFIG_NO_HZ_FULL is not set +CONFIG_NO_HZ=y +CONFIG_HIGH_RES_TIMERS=y +# end of Timers subsystem + +# CONFIG_PREEMPT_NONE is not set +CONFIG_PREEMPT_VOLUNTARY=y +# CONFIG_PREEMPT is not set +CONFIG_PREEMPT_COUNT=y + +# +# CPU/Task time and stats accounting +# +CONFIG_TICK_CPU_ACCOUNTING=y +# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set +# CONFIG_IRQ_TIME_ACCOUNTING is not set +CONFIG_BSD_PROCESS_ACCT=y +CONFIG_BSD_PROCESS_ACCT_V3=y +CONFIG_TASKSTATS=y +CONFIG_TASK_DELAY_ACCT=y +CONFIG_TASK_XACCT=y +CONFIG_TASK_IO_ACCOUNTING=y +# CONFIG_PSI is not set +# end of CPU/Task time and stats accounting + +# CONFIG_CPU_ISOLATION is not set + +# +# RCU Subsystem +# +CONFIG_TREE_RCU=y +# CONFIG_RCU_EXPERT is not set +CONFIG_SRCU=y +CONFIG_TREE_SRCU=y +CONFIG_RCU_STALL_COMMON=y +CONFIG_RCU_NEED_SEGCBLIST=y +# end of RCU Subsystem + +CONFIG_BUILD_BIN2C=y +# CONFIG_IKCONFIG is not set +# CONFIG_IKHEADERS is not set +CONFIG_LOG_BUF_SHIFT=18 +CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 +CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13 +CONFIG_HAVE_UNSTABLE_SCHED_CLOCK=y + +# +# Scheduler features +# +# end of Scheduler features + +CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y +CONFIG_ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH=y +CONFIG_ARCH_SUPPORTS_INT128=y +CONFIG_NUMA_BALANCING=y +CONFIG_NUMA_BALANCING_DEFAULT_ENABLED=y +CONFIG_CGROUPS=y +CONFIG_PAGE_COUNTER=y +CONFIG_MEMCG=y +CONFIG_MEMCG_SWAP=y +# CONFIG_MEMCG_SWAP_ENABLED is not set +CONFIG_MEMCG_KMEM=y +CONFIG_BLK_CGROUP=y +CONFIG_CGROUP_WRITEBACK=y +CONFIG_CGROUP_SCHED=y +CONFIG_FAIR_GROUP_SCHED=y +CONFIG_CFS_BANDWIDTH=y +# CONFIG_RT_GROUP_SCHED is not set +CONFIG_CGROUP_PIDS=y +# CONFIG_CGROUP_RDMA is not set +CONFIG_CGROUP_FREEZER=y +CONFIG_CGROUP_HUGETLB=y +CONFIG_CPUSETS=y +CONFIG_PROC_PID_CPUSET=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_CGROUP_PERF=y +CONFIG_CGROUP_BPF=y +# CONFIG_CGROUP_DEBUG is not set +CONFIG_SOCK_CGROUP_DATA=y +CONFIG_NAMESPACES=y +CONFIG_UTS_NS=y +CONFIG_IPC_NS=y +CONFIG_USER_NS=y +CONFIG_PID_NS=y +CONFIG_NET_NS=y +CONFIG_CHECKPOINT_RESTORE=y +CONFIG_SCHED_AUTOGROUP=y +# CONFIG_SYSFS_DEPRECATED is not set +CONFIG_RELAY=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_INITRAMFS_SOURCE="" +CONFIG_RD_GZIP=y +CONFIG_RD_BZIP2=y +CONFIG_RD_LZMA=y +CONFIG_RD_XZ=y +CONFIG_RD_LZO=y +CONFIG_RD_LZ4=y +CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y +# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_SYSCTL=y +CONFIG_HAVE_UID16=y +CONFIG_SYSCTL_EXCEPTION_TRACE=y +CONFIG_HAVE_PCSPKR_PLATFORM=y +CONFIG_BPF=y +CONFIG_EXPERT=y +CONFIG_UID16=y +CONFIG_MULTIUSER=y +CONFIG_SGETMASK_SYSCALL=y +CONFIG_SYSFS_SYSCALL=y +CONFIG_SYSCTL_SYSCALL=y +CONFIG_FHANDLE=y +CONFIG_POSIX_TIMERS=y +CONFIG_PRINTK=y +CONFIG_PRINTK_NMI=y +CONFIG_BUG=y +CONFIG_ELF_CORE=y +CONFIG_PCSPKR_PLATFORM=y +CONFIG_BASE_FULL=y +CONFIG_FUTEX=y +CONFIG_FUTEX_PI=y +CONFIG_EPOLL=y +CONFIG_SIGNALFD=y +CONFIG_TIMERFD=y +CONFIG_EVENTFD=y +CONFIG_SHMEM=y +CONFIG_AIO=y +CONFIG_IO_URING=y +CONFIG_ADVISE_SYSCALLS=y +CONFIG_MEMBARRIER=y +CONFIG_KALLSYMS=y +CONFIG_KALLSYMS_ALL=y +CONFIG_KALLSYMS_ABSOLUTE_PERCPU=y +CONFIG_KALLSYMS_BASE_RELATIVE=y +CONFIG_BPF_SYSCALL=y +# CONFIG_USERFAULTFD is not set +CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y +CONFIG_RSEQ=y +# CONFIG_DEBUG_RSEQ is not set +# CONFIG_EMBEDDED is not set +CONFIG_HAVE_PERF_EVENTS=y +# CONFIG_PC104 is not set + +# +# Kernel Performance Events And Counters +# +CONFIG_PERF_EVENTS=y +# CONFIG_DEBUG_PERF_USE_VMALLOC is not set +# end of Kernel Performance Events And Counters + +CONFIG_VM_EVENT_COUNTERS=y +CONFIG_SLUB_DEBUG=y +# CONFIG_SLUB_MEMCG_SYSFS_ON is not set +# CONFIG_COMPAT_BRK is not set +# CONFIG_SLAB is not set +CONFIG_SLUB=y +# CONFIG_SLOB is not set +CONFIG_SLAB_MERGE_DEFAULT=y +# CONFIG_SLAB_FREELIST_RANDOM is not set +# CONFIG_SLAB_FREELIST_HARDENED is not set +# CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set +CONFIG_SLUB_CPU_PARTIAL=y +CONFIG_SYSTEM_DATA_VERIFICATION=y +CONFIG_PROFILING=y +CONFIG_TRACEPOINTS=y +# end of General setup + +CONFIG_64BIT=y +CONFIG_X86_64=y +CONFIG_X86=y +CONFIG_INSTRUCTION_DECODER=y +CONFIG_OUTPUT_FORMAT="elf64-x86-64" +CONFIG_ARCH_DEFCONFIG="arch/x86/configs/x86_64_defconfig" +CONFIG_LOCKDEP_SUPPORT=y +CONFIG_STACKTRACE_SUPPORT=y +CONFIG_MMU=y +CONFIG_ARCH_MMAP_RND_BITS_MIN=28 +CONFIG_ARCH_MMAP_RND_BITS_MAX=32 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8 +CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16 +CONFIG_GENERIC_ISA_DMA=y +CONFIG_GENERIC_BUG=y +CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y +CONFIG_ARCH_MAY_HAVE_PC_FDC=y +CONFIG_GENERIC_CALIBRATE_DELAY=y +CONFIG_ARCH_HAS_CPU_RELAX=y +CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y +CONFIG_ARCH_HAS_FILTER_PGPROT=y +CONFIG_HAVE_SETUP_PER_CPU_AREA=y +CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y +CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y +CONFIG_ARCH_HIBERNATION_POSSIBLE=y +CONFIG_ARCH_SUSPEND_POSSIBLE=y +CONFIG_ARCH_WANT_GENERAL_HUGETLB=y +CONFIG_ZONE_DMA32=y +CONFIG_AUDIT_ARCH=y +CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y +CONFIG_X86_64_SMP=y +CONFIG_ARCH_SUPPORTS_UPROBES=y +CONFIG_FIX_EARLYCON_MEM=y +CONFIG_PGTABLE_LEVELS=4 +CONFIG_CC_HAS_SANE_STACKPROTECTOR=y + +# +# Processor type and features +# +CONFIG_ZONE_DMA=y +CONFIG_SMP=y +CONFIG_X86_FEATURE_NAMES=y +# CONFIG_X86_X2APIC is not set +CONFIG_X86_MPPARSE=y +# CONFIG_GOLDFISH is not set +# CONFIG_RETPOLINE is not set +# CONFIG_X86_CPU_RESCTRL is not set +CONFIG_X86_EXTENDED_PLATFORM=y +# CONFIG_X86_VSMP is not set +# CONFIG_X86_GOLDFISH is not set +CONFIG_X86_INTEL_LPSS=y +# CONFIG_X86_AMD_PLATFORM_DEVICE is not set +CONFIG_IOSF_MBI=y +CONFIG_IOSF_MBI_DEBUG=y +CONFIG_X86_SUPPORTS_MEMORY_FAILURE=y +CONFIG_SCHED_OMIT_FRAME_POINTER=y +CONFIG_HYPERVISOR_GUEST=y +CONFIG_PARAVIRT=y +# CONFIG_PARAVIRT_DEBUG is not set +CONFIG_PARAVIRT_SPINLOCKS=y +# CONFIG_XEN is not set +CONFIG_KVM_GUEST=y +# CONFIG_PVH is not set +CONFIG_KVM_DEBUG_FS=y +# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set +CONFIG_PARAVIRT_CLOCK=y +# CONFIG_JAILHOUSE_GUEST is not set +# CONFIG_ACRN_GUEST is not set +# CONFIG_MK8 is not set +# CONFIG_MPSC is not set +# CONFIG_MCORE2 is not set +# CONFIG_MATOM is not set +CONFIG_GENERIC_CPU=y +CONFIG_X86_INTERNODE_CACHE_SHIFT=6 +CONFIG_X86_L1_CACHE_SHIFT=6 +CONFIG_X86_TSC=y +CONFIG_X86_CMPXCHG64=y +CONFIG_X86_CMOV=y +CONFIG_X86_MINIMUM_CPU_FAMILY=64 +CONFIG_X86_DEBUGCTLMSR=y +CONFIG_PROCESSOR_SELECT=y +CONFIG_CPU_SUP_INTEL=y +CONFIG_CPU_SUP_AMD=y +CONFIG_CPU_SUP_HYGON=y +CONFIG_CPU_SUP_CENTAUR=y +CONFIG_CPU_SUP_ZHAOXIN=y +CONFIG_HPET_TIMER=y +CONFIG_HPET_EMULATE_RTC=y +CONFIG_DMI=y +CONFIG_GART_IOMMU=y +CONFIG_CALGARY_IOMMU=y +CONFIG_CALGARY_IOMMU_ENABLED_BY_DEFAULT=y +# CONFIG_MAXSMP is not set +CONFIG_NR_CPUS_RANGE_BEGIN=2 +CONFIG_NR_CPUS_RANGE_END=512 +CONFIG_NR_CPUS_DEFAULT=64 +CONFIG_NR_CPUS=256 +CONFIG_SCHED_SMT=y +CONFIG_SCHED_MC=y +CONFIG_SCHED_MC_PRIO=y +CONFIG_X86_LOCAL_APIC=y +CONFIG_X86_IO_APIC=y +CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS=y +CONFIG_X86_MCE=y +# CONFIG_X86_MCELOG_LEGACY is not set +CONFIG_X86_MCE_INTEL=y +CONFIG_X86_MCE_AMD=y +CONFIG_X86_MCE_THRESHOLD=y +# CONFIG_X86_MCE_INJECT is not set +CONFIG_X86_THERMAL_VECTOR=y + +# +# Performance monitoring +# +CONFIG_PERF_EVENTS_INTEL_UNCORE=y +CONFIG_PERF_EVENTS_INTEL_RAPL=y +CONFIG_PERF_EVENTS_INTEL_CSTATE=y +# CONFIG_PERF_EVENTS_AMD_POWER is not set +# end of Performance monitoring + +CONFIG_X86_16BIT=y +CONFIG_X86_ESPFIX64=y +CONFIG_X86_VSYSCALL_EMULATION=y +CONFIG_I8K=m +CONFIG_MICROCODE=y +CONFIG_MICROCODE_INTEL=y +CONFIG_MICROCODE_AMD=y +CONFIG_MICROCODE_OLD_INTERFACE=y +CONFIG_X86_MSR=m +CONFIG_X86_CPUID=m +# CONFIG_X86_5LEVEL is not set +CONFIG_X86_DIRECT_GBPAGES=y +# CONFIG_X86_CPA_STATISTICS is not set +CONFIG_ARCH_HAS_MEM_ENCRYPT=y +# CONFIG_AMD_MEM_ENCRYPT is not set +CONFIG_NUMA=y +CONFIG_AMD_NUMA=y +CONFIG_X86_64_ACPI_NUMA=y +CONFIG_NODES_SPAN_OTHER_NODES=y +# CONFIG_NUMA_EMU is not set +CONFIG_NODES_SHIFT=6 +CONFIG_ARCH_SPARSEMEM_ENABLE=y +CONFIG_ARCH_SPARSEMEM_DEFAULT=y +CONFIG_ARCH_SELECT_MEMORY_MODEL=y +CONFIG_ARCH_MEMORY_PROBE=y +CONFIG_ARCH_PROC_KCORE_TEXT=y +CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 +# CONFIG_X86_PMEM_LEGACY is not set +CONFIG_X86_CHECK_BIOS_CORRUPTION=y +CONFIG_X86_BOOTPARAM_MEMORY_CORRUPTION_CHECK=y +CONFIG_X86_RESERVE_LOW=64 +CONFIG_MTRR=y +CONFIG_MTRR_SANITIZER=y +CONFIG_MTRR_SANITIZER_ENABLE_DEFAULT=1 +CONFIG_MTRR_SANITIZER_SPARE_REG_NR_DEFAULT=1 +CONFIG_X86_PAT=y +CONFIG_ARCH_USES_PG_UNCACHED=y +CONFIG_ARCH_RANDOM=y +CONFIG_X86_SMAP=y +CONFIG_X86_INTEL_UMIP=y +# CONFIG_X86_INTEL_MPX is not set +CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS=y +CONFIG_EFI=y +CONFIG_EFI_STUB=y +CONFIG_EFI_MIXED=y +CONFIG_SECCOMP=y +# CONFIG_HZ_100 is not set +CONFIG_HZ_250=y +# CONFIG_HZ_300 is not set +# CONFIG_HZ_1000 is not set +CONFIG_HZ=250 +CONFIG_SCHED_HRTICK=y +CONFIG_KEXEC=y +CONFIG_KEXEC_FILE=y +CONFIG_ARCH_HAS_KEXEC_PURGATORY=y +CONFIG_KEXEC_VERIFY_SIG=y +CONFIG_CRASH_DUMP=y +CONFIG_KEXEC_JUMP=y +CONFIG_PHYSICAL_START=0x1000000 +CONFIG_RELOCATABLE=y +CONFIG_RANDOMIZE_BASE=y +CONFIG_X86_NEED_RELOCS=y +CONFIG_PHYSICAL_ALIGN=0x1000000 +CONFIG_DYNAMIC_MEMORY_LAYOUT=y +CONFIG_RANDOMIZE_MEMORY=y +CONFIG_RANDOMIZE_MEMORY_PHYSICAL_PADDING=0xa +CONFIG_HOTPLUG_CPU=y +# CONFIG_BOOTPARAM_HOTPLUG_CPU0 is not set +# CONFIG_DEBUG_HOTPLUG_CPU0 is not set +# CONFIG_COMPAT_VDSO is not set +CONFIG_LEGACY_VSYSCALL_EMULATE=y +# CONFIG_LEGACY_VSYSCALL_XONLY is not set +# CONFIG_LEGACY_VSYSCALL_NONE is not set +# CONFIG_CMDLINE_BOOL is not set +CONFIG_MODIFY_LDT_SYSCALL=y +CONFIG_HAVE_LIVEPATCH=y +# CONFIG_LIVEPATCH is not set +# end of Processor type and features + +CONFIG_ARCH_HAS_ADD_PAGES=y +CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y +CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y +CONFIG_USE_PERCPU_NUMA_NODE_ID=y +CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y +CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y +CONFIG_ARCH_ENABLE_THP_MIGRATION=y + +# +# Power management and ACPI options +# +CONFIG_ARCH_HIBERNATION_HEADER=y +CONFIG_SUSPEND=y +CONFIG_SUSPEND_FREEZER=y +# CONFIG_SUSPEND_SKIP_SYNC is not set +CONFIG_HIBERNATE_CALLBACKS=y +CONFIG_HIBERNATION=y +CONFIG_PM_STD_PARTITION="" +CONFIG_PM_SLEEP=y +CONFIG_PM_SLEEP_SMP=y +# CONFIG_PM_AUTOSLEEP is not set +CONFIG_PM_WAKELOCKS=y +CONFIG_PM_WAKELOCKS_LIMIT=100 +CONFIG_PM_WAKELOCKS_GC=y +CONFIG_PM=y +CONFIG_PM_DEBUG=y +CONFIG_PM_ADVANCED_DEBUG=y +# CONFIG_PM_TEST_SUSPEND is not set +CONFIG_PM_SLEEP_DEBUG=y +# CONFIG_DPM_WATCHDOG is not set +CONFIG_PM_TRACE=y +CONFIG_PM_TRACE_RTC=y +CONFIG_PM_CLK=y +CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y +# CONFIG_ENERGY_MODEL is not set +CONFIG_ARCH_SUPPORTS_ACPI=y +CONFIG_ACPI=y +CONFIG_ACPI_LEGACY_TABLES_LOOKUP=y +CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y +CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y +# CONFIG_ACPI_DEBUGGER is not set +CONFIG_ACPI_SPCR_TABLE=y +CONFIG_ACPI_LPIT=y +CONFIG_ACPI_SLEEP=y +# CONFIG_ACPI_PROCFS_POWER is not set +CONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y +CONFIG_ACPI_EC_DEBUGFS=m +CONFIG_ACPI_AC=y +CONFIG_ACPI_BATTERY=y +CONFIG_ACPI_BUTTON=y +CONFIG_ACPI_VIDEO=m +CONFIG_ACPI_FAN=y +# CONFIG_ACPI_TAD is not set +CONFIG_ACPI_DOCK=y +CONFIG_ACPI_CPU_FREQ_PSS=y +CONFIG_ACPI_PROCESSOR_CSTATE=y +CONFIG_ACPI_PROCESSOR_IDLE=y +CONFIG_ACPI_CPPC_LIB=y +CONFIG_ACPI_PROCESSOR=y +CONFIG_ACPI_HOTPLUG_CPU=y +CONFIG_ACPI_PROCESSOR_AGGREGATOR=m +CONFIG_ACPI_THERMAL=y +CONFIG_ACPI_NUMA=y +CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y +CONFIG_ACPI_TABLE_UPGRADE=y +# CONFIG_ACPI_DEBUG is not set +CONFIG_ACPI_PCI_SLOT=y +CONFIG_ACPI_CONTAINER=y +CONFIG_ACPI_HOTPLUG_MEMORY=y +CONFIG_ACPI_HOTPLUG_IOAPIC=y +CONFIG_ACPI_SBS=m +CONFIG_ACPI_HED=y +# CONFIG_ACPI_CUSTOM_METHOD is not set +CONFIG_ACPI_BGRT=y +# CONFIG_ACPI_REDUCED_HARDWARE_ONLY is not set +# CONFIG_ACPI_NFIT is not set +# CONFIG_ACPI_HMAT is not set +CONFIG_HAVE_ACPI_APEI=y +CONFIG_HAVE_ACPI_APEI_NMI=y +CONFIG_ACPI_APEI=y +CONFIG_ACPI_APEI_GHES=y +CONFIG_ACPI_APEI_PCIEAER=y +CONFIG_ACPI_APEI_MEMORY_FAILURE=y +CONFIG_ACPI_APEI_EINJ=m +# CONFIG_ACPI_APEI_ERST_DEBUG is not set +# CONFIG_DPTF_POWER is not set +# CONFIG_PMIC_OPREGION is not set +# CONFIG_ACPI_CONFIGFS is not set +CONFIG_X86_PM_TIMER=y +CONFIG_SFI=y + +# +# CPU Frequency scaling +# +CONFIG_CPU_FREQ=y +CONFIG_CPU_FREQ_GOV_ATTR_SET=y +CONFIG_CPU_FREQ_GOV_COMMON=y +CONFIG_CPU_FREQ_STAT=y +CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y +# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set +# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set +CONFIG_CPU_FREQ_GOV_PERFORMANCE=y +CONFIG_CPU_FREQ_GOV_POWERSAVE=y +CONFIG_CPU_FREQ_GOV_USERSPACE=y +CONFIG_CPU_FREQ_GOV_ONDEMAND=y +CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y +# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set + +# +# CPU frequency scaling drivers +# +CONFIG_X86_INTEL_PSTATE=y +# CONFIG_X86_PCC_CPUFREQ is not set +CONFIG_X86_ACPI_CPUFREQ=y +# CONFIG_X86_ACPI_CPUFREQ_CPB is not set +# CONFIG_X86_POWERNOW_K8 is not set +# CONFIG_X86_AMD_FREQ_SENSITIVITY is not set +# CONFIG_X86_SPEEDSTEP_CENTRINO is not set +# CONFIG_X86_P4_CLOCKMOD is not set + +# +# shared options +# +# end of CPU Frequency scaling + +# +# CPU Idle +# +CONFIG_CPU_IDLE=y +CONFIG_CPU_IDLE_GOV_LADDER=y +CONFIG_CPU_IDLE_GOV_MENU=y +# CONFIG_CPU_IDLE_GOV_TEO is not set +# end of CPU Idle + +# CONFIG_INTEL_IDLE is not set +# end of Power management and ACPI options + +# +# Bus options (PCI etc.) +# +CONFIG_PCI_DIRECT=y +CONFIG_PCI_MMCONFIG=y +CONFIG_MMCONF_FAM10H=y +# CONFIG_PCI_CNB20LE_QUIRK is not set +# CONFIG_ISA_BUS is not set +CONFIG_ISA_DMA_API=y +CONFIG_AMD_NB=y +# CONFIG_X86_SYSFB is not set +# end of Bus options (PCI etc.) + +# +# Binary Emulations +# +CONFIG_IA32_EMULATION=y +# CONFIG_X86_X32 is not set +CONFIG_COMPAT_32=y +CONFIG_COMPAT=y +CONFIG_COMPAT_FOR_U64_ALIGNMENT=y +CONFIG_SYSVIPC_COMPAT=y +# end of Binary Emulations + +# +# Firmware Drivers +# +# CONFIG_EDD is not set +CONFIG_FIRMWARE_MEMMAP=y +CONFIG_DMIID=y +# CONFIG_DMI_SYSFS is not set +CONFIG_DMI_SCAN_MACHINE_NON_EFI_FALLBACK=y +# CONFIG_FW_CFG_SYSFS is not set +# CONFIG_GOOGLE_FIRMWARE is not set + +# +# EFI (Extensible Firmware Interface) Support +# +CONFIG_EFI_VARS=y +CONFIG_EFI_ESRT=y +CONFIG_EFI_VARS_PSTORE=y +# CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE is not set +CONFIG_EFI_RUNTIME_MAP=y +# CONFIG_EFI_FAKE_MEMMAP is not set +CONFIG_EFI_RUNTIME_WRAPPERS=y +# CONFIG_EFI_BOOTLOADER_CONTROL is not set +# CONFIG_EFI_CAPSULE_LOADER is not set +# CONFIG_EFI_TEST is not set +# CONFIG_APPLE_PROPERTIES is not set +# CONFIG_RESET_ATTACK_MITIGATION is not set +# end of EFI (Extensible Firmware Interface) Support + +CONFIG_UEFI_CPER=y +CONFIG_UEFI_CPER_X86=y +CONFIG_EFI_EARLYCON=y + +# +# Tegra firmware driver +# +# end of Tegra firmware driver +# end of Firmware Drivers + +CONFIG_HAVE_KVM=y +CONFIG_VIRTUALIZATION=y +# CONFIG_KVM is not set +# CONFIG_VHOST_NET is not set +# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set + +# +# General architecture-dependent options +# +CONFIG_CRASH_CORE=y +CONFIG_KEXEC_CORE=y +CONFIG_HOTPLUG_SMT=y +CONFIG_OPROFILE=m +# CONFIG_OPROFILE_EVENT_MULTIPLEX is not set +CONFIG_HAVE_OPROFILE=y +CONFIG_OPROFILE_NMI_TIMER=y +CONFIG_KPROBES=y +CONFIG_JUMP_LABEL=y +# CONFIG_STATIC_KEYS_SELFTEST is not set +CONFIG_OPTPROBES=y +CONFIG_KPROBES_ON_FTRACE=y +CONFIG_UPROBES=y +CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y +CONFIG_ARCH_USE_BUILTIN_BSWAP=y +CONFIG_KRETPROBES=y +CONFIG_HAVE_IOREMAP_PROT=y +CONFIG_HAVE_KPROBES=y +CONFIG_HAVE_KRETPROBES=y +CONFIG_HAVE_OPTPROBES=y +CONFIG_HAVE_KPROBES_ON_FTRACE=y +CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y +CONFIG_HAVE_NMI=y +CONFIG_HAVE_ARCH_TRACEHOOK=y +CONFIG_HAVE_DMA_CONTIGUOUS=y +CONFIG_GENERIC_SMP_IDLE_THREAD=y +CONFIG_ARCH_HAS_FORTIFY_SOURCE=y +CONFIG_ARCH_HAS_SET_MEMORY=y +CONFIG_ARCH_HAS_SET_DIRECT_MAP=y +CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y +CONFIG_ARCH_WANTS_DYNAMIC_TASK_STRUCT=y +CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y +CONFIG_HAVE_RSEQ=y +CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y +CONFIG_HAVE_CLK=y +CONFIG_HAVE_HW_BREAKPOINT=y +CONFIG_HAVE_MIXED_BREAKPOINTS_REGS=y +CONFIG_HAVE_USER_RETURN_NOTIFIER=y +CONFIG_HAVE_PERF_EVENTS_NMI=y +CONFIG_HAVE_HARDLOCKUP_DETECTOR_PERF=y +CONFIG_HAVE_PERF_REGS=y +CONFIG_HAVE_PERF_USER_STACK_DUMP=y +CONFIG_HAVE_ARCH_JUMP_LABEL=y +CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y +CONFIG_HAVE_RCU_TABLE_FREE=y +CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y +CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y +CONFIG_HAVE_CMPXCHG_LOCAL=y +CONFIG_HAVE_CMPXCHG_DOUBLE=y +CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y +CONFIG_ARCH_WANT_OLD_COMPAT_IPC=y +CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_SECCOMP_FILTER=y +CONFIG_HAVE_ARCH_STACKLEAK=y +CONFIG_HAVE_STACKPROTECTOR=y +CONFIG_CC_HAS_STACKPROTECTOR_NONE=y +CONFIG_STACKPROTECTOR=y +CONFIG_STACKPROTECTOR_STRONG=y +CONFIG_HAVE_ARCH_WITHIN_STACK_FRAMES=y +CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y +CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_MOVE_PMD=y +CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y +CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD=y +CONFIG_HAVE_ARCH_HUGE_VMAP=y +CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y +CONFIG_HAVE_ARCH_SOFT_DIRTY=y +CONFIG_HAVE_MOD_ARCH_SPECIFIC=y +CONFIG_MODULES_USE_ELF_RELA=y +CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y +CONFIG_ARCH_HAS_ELF_RANDOMIZE=y +CONFIG_HAVE_ARCH_MMAP_RND_BITS=y +CONFIG_HAVE_EXIT_THREAD=y +CONFIG_ARCH_MMAP_RND_BITS=28 +CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y +CONFIG_ARCH_MMAP_RND_COMPAT_BITS=8 +CONFIG_HAVE_ARCH_COMPAT_MMAP_BASES=y +CONFIG_HAVE_COPY_THREAD_TLS=y +CONFIG_HAVE_STACK_VALIDATION=y +CONFIG_HAVE_RELIABLE_STACKTRACE=y +CONFIG_OLD_SIGSUSPEND3=y +CONFIG_COMPAT_OLD_SIGACTION=y +CONFIG_64BIT_TIME=y +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_HAVE_ARCH_VMAP_STACK=y +CONFIG_VMAP_STACK=y +CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y +CONFIG_STRICT_KERNEL_RWX=y +CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y +CONFIG_STRICT_MODULE_RWX=y +CONFIG_ARCH_HAS_REFCOUNT=y +# CONFIG_REFCOUNT_FULL is not set +CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y +CONFIG_ARCH_USE_MEMREMAP_PROT=y +# CONFIG_LOCK_EVENT_COUNTS is not set + +# +# GCOV-based kernel profiling +# +# CONFIG_GCOV_KERNEL is not set +CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y +# end of GCOV-based kernel profiling + +CONFIG_PLUGIN_HOSTCC="" +CONFIG_HAVE_GCC_PLUGINS=y +# end of General architecture-dependent options + +CONFIG_RT_MUTEXES=y +CONFIG_BASE_SMALL=0 +CONFIG_MODULES=y +# CONFIG_MODULE_FORCE_LOAD is not set +CONFIG_MODULE_UNLOAD=y +# CONFIG_MODULE_FORCE_UNLOAD is not set +CONFIG_MODVERSIONS=y +CONFIG_MODULE_SRCVERSION_ALL=y +CONFIG_MODULE_SIG=y +# CONFIG_MODULE_SIG_FORCE is not set +CONFIG_MODULE_SIG_ALL=y +# CONFIG_MODULE_SIG_SHA1 is not set +# CONFIG_MODULE_SIG_SHA224 is not set +# CONFIG_MODULE_SIG_SHA256 is not set +# CONFIG_MODULE_SIG_SHA384 is not set +CONFIG_MODULE_SIG_SHA512=y +CONFIG_MODULE_SIG_HASH="sha512" +# CONFIG_MODULE_COMPRESS is not set +# CONFIG_TRIM_UNUSED_KSYMS is not set +CONFIG_MODULES_TREE_LOOKUP=y +CONFIG_BLOCK=y +CONFIG_BLK_SCSI_REQUEST=y +CONFIG_BLK_DEV_BSG=y +CONFIG_BLK_DEV_BSGLIB=y +CONFIG_BLK_DEV_INTEGRITY=y +# CONFIG_BLK_DEV_ZONED is not set +CONFIG_BLK_DEV_THROTTLING=y +# CONFIG_BLK_DEV_THROTTLING_LOW is not set +CONFIG_BLK_CMDLINE_PARSER=y +# CONFIG_BLK_WBT is not set +# CONFIG_BLK_CGROUP_IOLATENCY is not set +CONFIG_BLK_DEBUG_FS=y +# CONFIG_BLK_SED_OPAL is not set + +# +# Partition Types +# +CONFIG_PARTITION_ADVANCED=y +# CONFIG_ACORN_PARTITION is not set +# CONFIG_AIX_PARTITION is not set +# CONFIG_OSF_PARTITION is not set +# CONFIG_AMIGA_PARTITION is not set +# CONFIG_ATARI_PARTITION is not set +# CONFIG_MAC_PARTITION is not set +CONFIG_MSDOS_PARTITION=y +# CONFIG_BSD_DISKLABEL is not set +# CONFIG_MINIX_SUBPARTITION is not set +# CONFIG_SOLARIS_X86_PARTITION is not set +# CONFIG_UNIXWARE_DISKLABEL is not set +# CONFIG_LDM_PARTITION is not set +# CONFIG_SGI_PARTITION is not set +# CONFIG_ULTRIX_PARTITION is not set +# CONFIG_SUN_PARTITION is not set +# CONFIG_KARMA_PARTITION is not set +CONFIG_EFI_PARTITION=y +# CONFIG_SYSV68_PARTITION is not set +# CONFIG_CMDLINE_PARTITION is not set +# end of Partition Types + +CONFIG_BLOCK_COMPAT=y +CONFIG_BLK_MQ_PCI=y +CONFIG_BLK_PM=y + +# +# IO Schedulers +# +CONFIG_MQ_IOSCHED_DEADLINE=y +CONFIG_MQ_IOSCHED_KYBER=y +# CONFIG_IOSCHED_BFQ is not set +# end of IO Schedulers + +CONFIG_ASN1=y +CONFIG_UNINLINE_SPIN_UNLOCK=y +CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y +CONFIG_MUTEX_SPIN_ON_OWNER=y +CONFIG_RWSEM_SPIN_ON_OWNER=y +CONFIG_LOCK_SPIN_ON_OWNER=y +CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y +CONFIG_QUEUED_SPINLOCKS=y +CONFIG_ARCH_USE_QUEUED_RWLOCKS=y +CONFIG_QUEUED_RWLOCKS=y +CONFIG_ARCH_HAS_SYNC_CORE_BEFORE_USERMODE=y +CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y +CONFIG_FREEZER=y + +# +# Executable file formats +# +CONFIG_BINFMT_ELF=y +CONFIG_COMPAT_BINFMT_ELF=y +CONFIG_ELFCORE=y +CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y +CONFIG_BINFMT_SCRIPT=y +CONFIG_BINFMT_MISC=y +CONFIG_COREDUMP=y +# end of Executable file formats + +# +# Memory Management options +# +CONFIG_SELECT_MEMORY_MODEL=y +CONFIG_SPARSEMEM_MANUAL=y +CONFIG_SPARSEMEM=y +CONFIG_NEED_MULTIPLE_NODES=y +CONFIG_HAVE_MEMORY_PRESENT=y +CONFIG_SPARSEMEM_EXTREME=y +CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y +CONFIG_SPARSEMEM_VMEMMAP=y +CONFIG_HAVE_MEMBLOCK_NODE_MAP=y +CONFIG_HAVE_FAST_GUP=y +CONFIG_MEMORY_ISOLATION=y +CONFIG_HAVE_BOOTMEM_INFO_NODE=y +CONFIG_MEMORY_HOTPLUG=y +CONFIG_MEMORY_HOTPLUG_SPARSE=y +# CONFIG_MEMORY_HOTPLUG_DEFAULT_ONLINE is not set +CONFIG_MEMORY_HOTREMOVE=y +CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_COMPACTION=y +CONFIG_MIGRATION=y +CONFIG_CONTIG_ALLOC=y +CONFIG_PHYS_ADDR_T_64BIT=y +CONFIG_BOUNCE=y +CONFIG_VIRT_TO_BUS=y +CONFIG_MMU_NOTIFIER=y +CONFIG_KSM=y +CONFIG_DEFAULT_MMAP_MIN_ADDR=65536 +CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y +CONFIG_MEMORY_FAILURE=y +CONFIG_HWPOISON_INJECT=m +CONFIG_TRANSPARENT_HUGEPAGE=y +CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y +# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set +CONFIG_ARCH_WANTS_THP_SWAP=y +CONFIG_THP_SWAP=y +CONFIG_TRANSPARENT_HUGE_PAGECACHE=y +CONFIG_CLEANCACHE=y +CONFIG_FRONTSWAP=y +CONFIG_CMA=y +# CONFIG_CMA_DEBUG is not set +# CONFIG_CMA_DEBUGFS is not set +CONFIG_CMA_AREAS=7 +CONFIG_MEM_SOFT_DIRTY=y +CONFIG_ZSWAP=y +CONFIG_ZPOOL=y +CONFIG_ZBUD=y +# CONFIG_Z3FOLD is not set +CONFIG_ZSMALLOC=y +CONFIG_PGTABLE_MAPPING=y +# CONFIG_ZSMALLOC_STAT is not set +CONFIG_GENERIC_EARLY_IOREMAP=y +# CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set +# CONFIG_IDLE_PAGE_TRACKING is not set +CONFIG_ARCH_HAS_PTE_DEVMAP=y +CONFIG_ZONE_DEVICE=y +CONFIG_HMM_MIRROR=y +# CONFIG_DEVICE_PRIVATE is not set +CONFIG_ARCH_USES_HIGH_VMA_FLAGS=y +CONFIG_ARCH_HAS_PKEYS=y +# CONFIG_PERCPU_STATS is not set +# CONFIG_GUP_BENCHMARK is not set +CONFIG_ARCH_HAS_PTE_SPECIAL=y +# end of Memory Management options + +CONFIG_NET=y +CONFIG_NET_INGRESS=y +CONFIG_SKB_EXTENSIONS=y + +# +# Networking options +# +CONFIG_PACKET=y +CONFIG_PACKET_DIAG=y +CONFIG_UNIX=y +CONFIG_UNIX_SCM=y +CONFIG_UNIX_DIAG=y +# CONFIG_TLS is not set +CONFIG_XFRM=y +CONFIG_XFRM_ALGO=y +CONFIG_XFRM_USER=y +# CONFIG_XFRM_INTERFACE is not set +# CONFIG_XFRM_SUB_POLICY is not set +# CONFIG_XFRM_MIGRATE is not set +# CONFIG_XFRM_STATISTICS is not set +# CONFIG_NET_KEY is not set +# CONFIG_XDP_SOCKETS is not set +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_ADVANCED_ROUTER=y +# CONFIG_IP_FIB_TRIE_STATS is not set +CONFIG_IP_MULTIPLE_TABLES=y +CONFIG_IP_ROUTE_MULTIPATH=y +CONFIG_IP_ROUTE_VERBOSE=y +CONFIG_IP_ROUTE_CLASSID=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_IP_PNP_RARP=y +# CONFIG_NET_IPIP is not set +# CONFIG_NET_IPGRE_DEMUX is not set +CONFIG_NET_IP_TUNNEL=y +CONFIG_IP_MROUTE_COMMON=y +CONFIG_IP_MROUTE=y +# CONFIG_IP_MROUTE_MULTIPLE_TABLES is not set +CONFIG_IP_PIMSM_V1=y +CONFIG_IP_PIMSM_V2=y +CONFIG_SYN_COOKIES=y +# CONFIG_NET_IPVTI is not set +# CONFIG_NET_FOU is not set +# CONFIG_NET_FOU_IP_TUNNELS is not set +# CONFIG_INET_AH is not set +# CONFIG_INET_ESP is not set +# CONFIG_INET_IPCOMP is not set +CONFIG_INET_TUNNEL=y +CONFIG_INET_DIAG=y +CONFIG_INET_TCP_DIAG=y +# CONFIG_INET_UDP_DIAG is not set +# CONFIG_INET_RAW_DIAG is not set +# CONFIG_INET_DIAG_DESTROY is not set +CONFIG_TCP_CONG_ADVANCED=y +# CONFIG_TCP_CONG_BIC is not set +CONFIG_TCP_CONG_CUBIC=y +# CONFIG_TCP_CONG_WESTWOOD is not set +# CONFIG_TCP_CONG_HTCP is not set +# CONFIG_TCP_CONG_HSTCP is not set +# CONFIG_TCP_CONG_HYBLA is not set +# CONFIG_TCP_CONG_VEGAS is not set +# CONFIG_TCP_CONG_NV is not set +# CONFIG_TCP_CONG_SCALABLE is not set +# CONFIG_TCP_CONG_LP is not set +# CONFIG_TCP_CONG_VENO is not set +# CONFIG_TCP_CONG_YEAH is not set +# CONFIG_TCP_CONG_ILLINOIS is not set +# CONFIG_TCP_CONG_DCTCP is not set +# CONFIG_TCP_CONG_CDG is not set +# CONFIG_TCP_CONG_BBR is not set +CONFIG_DEFAULT_CUBIC=y +# CONFIG_DEFAULT_RENO is not set +CONFIG_DEFAULT_TCP_CONG="cubic" +CONFIG_TCP_MD5SIG=y +CONFIG_IPV6=y +# CONFIG_IPV6_ROUTER_PREF is not set +# CONFIG_IPV6_OPTIMISTIC_DAD is not set +CONFIG_INET6_AH=y +CONFIG_INET6_ESP=y +# CONFIG_INET6_ESP_OFFLOAD is not set +# CONFIG_INET6_IPCOMP is not set +# CONFIG_IPV6_MIP6 is not set +# CONFIG_IPV6_ILA is not set +# CONFIG_IPV6_VTI is not set +CONFIG_IPV6_SIT=y +# CONFIG_IPV6_SIT_6RD is not set +CONFIG_IPV6_NDISC_NODETYPE=y +# CONFIG_IPV6_TUNNEL is not set +# CONFIG_IPV6_MULTIPLE_TABLES is not set +# CONFIG_IPV6_MROUTE is not set +# CONFIG_IPV6_SEG6_LWTUNNEL is not set +# CONFIG_IPV6_SEG6_HMAC is not set +CONFIG_NETLABEL=y +CONFIG_NETWORK_SECMARK=y +CONFIG_NET_PTP_CLASSIFY=y +# CONFIG_NETWORK_PHY_TIMESTAMPING is not set +CONFIG_NETFILTER=y +CONFIG_NETFILTER_ADVANCED=y +CONFIG_BRIDGE_NETFILTER=m + +# +# Core Netfilter Configuration +# +CONFIG_NETFILTER_INGRESS=y +CONFIG_NETFILTER_NETLINK=m +CONFIG_NETFILTER_FAMILY_BRIDGE=y +CONFIG_NETFILTER_FAMILY_ARP=y +CONFIG_NETFILTER_NETLINK_ACCT=m +CONFIG_NETFILTER_NETLINK_QUEUE=m +CONFIG_NETFILTER_NETLINK_LOG=m +CONFIG_NETFILTER_NETLINK_OSF=m +CONFIG_NF_CONNTRACK=m +CONFIG_NF_LOG_COMMON=m +# CONFIG_NF_LOG_NETDEV is not set +CONFIG_NETFILTER_CONNCOUNT=m +CONFIG_NF_CONNTRACK_MARK=y +CONFIG_NF_CONNTRACK_SECMARK=y +CONFIG_NF_CONNTRACK_ZONES=y +# CONFIG_NF_CONNTRACK_PROCFS is not set +CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_TIMEOUT=y +CONFIG_NF_CONNTRACK_TIMESTAMP=y +CONFIG_NF_CONNTRACK_LABELS=y +CONFIG_NF_CT_PROTO_DCCP=y +CONFIG_NF_CT_PROTO_SCTP=y +CONFIG_NF_CT_PROTO_UDPLITE=y +# CONFIG_NF_CONNTRACK_AMANDA is not set +# CONFIG_NF_CONNTRACK_FTP is not set +# CONFIG_NF_CONNTRACK_H323 is not set +# CONFIG_NF_CONNTRACK_IRC is not set +# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set +# CONFIG_NF_CONNTRACK_SNMP is not set +# CONFIG_NF_CONNTRACK_PPTP is not set +# CONFIG_NF_CONNTRACK_SANE is not set +# CONFIG_NF_CONNTRACK_SIP is not set +# CONFIG_NF_CONNTRACK_TFTP is not set +# CONFIG_NF_CT_NETLINK is not set +# CONFIG_NF_CT_NETLINK_TIMEOUT is not set +CONFIG_NF_NAT=m +CONFIG_NF_NAT_REDIRECT=y +CONFIG_NF_NAT_MASQUERADE=y +CONFIG_NETFILTER_SYNPROXY=m +CONFIG_NF_TABLES=m +CONFIG_NF_TABLES_SET=m +# CONFIG_NF_TABLES_INET is not set +CONFIG_NF_TABLES_NETDEV=y +# CONFIG_NFT_NUMGEN is not set +CONFIG_NFT_CT=m +CONFIG_NFT_COUNTER=m +CONFIG_NFT_CONNLIMIT=m +CONFIG_NFT_LOG=m +CONFIG_NFT_LIMIT=m +CONFIG_NFT_MASQ=m +CONFIG_NFT_REDIR=m +CONFIG_NFT_NAT=m +CONFIG_NFT_TUNNEL=m +# CONFIG_NFT_OBJREF is not set +# CONFIG_NFT_QUEUE is not set +CONFIG_NFT_QUOTA=m +CONFIG_NFT_REJECT=m +# CONFIG_NFT_COMPAT is not set +# CONFIG_NFT_HASH is not set +CONFIG_NFT_FIB=m +CONFIG_NFT_XFRM=m +# CONFIG_NFT_SOCKET is not set +# CONFIG_NFT_OSF is not set +# CONFIG_NFT_TPROXY is not set +# CONFIG_NFT_SYNPROXY is not set +CONFIG_NF_DUP_NETDEV=m +# CONFIG_NFT_DUP_NETDEV is not set +# CONFIG_NFT_FWD_NETDEV is not set +# CONFIG_NFT_FIB_NETDEV is not set +# CONFIG_NF_FLOW_TABLE is not set +CONFIG_NETFILTER_XTABLES=m + +# +# Xtables combined modules +# +CONFIG_NETFILTER_XT_MARK=m +CONFIG_NETFILTER_XT_CONNMARK=m + +# +# Xtables targets +# +CONFIG_NETFILTER_XT_TARGET_AUDIT=m +CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m +CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m +CONFIG_NETFILTER_XT_TARGET_CONNMARK=m +CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m +CONFIG_NETFILTER_XT_TARGET_CT=m +CONFIG_NETFILTER_XT_TARGET_DSCP=m +CONFIG_NETFILTER_XT_TARGET_HL=m +CONFIG_NETFILTER_XT_TARGET_HMARK=m +CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m +CONFIG_NETFILTER_XT_TARGET_LED=m +CONFIG_NETFILTER_XT_TARGET_LOG=m +CONFIG_NETFILTER_XT_TARGET_MARK=m +CONFIG_NETFILTER_XT_NAT=m +CONFIG_NETFILTER_XT_TARGET_NETMAP=m +CONFIG_NETFILTER_XT_TARGET_NFLOG=m +CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m +# CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set +CONFIG_NETFILTER_XT_TARGET_RATEEST=m +CONFIG_NETFILTER_XT_TARGET_REDIRECT=m +CONFIG_NETFILTER_XT_TARGET_MASQUERADE=m +CONFIG_NETFILTER_XT_TARGET_TEE=m +CONFIG_NETFILTER_XT_TARGET_TPROXY=m +CONFIG_NETFILTER_XT_TARGET_TRACE=m +CONFIG_NETFILTER_XT_TARGET_SECMARK=m +CONFIG_NETFILTER_XT_TARGET_TCPMSS=m +CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m + +# +# Xtables matches +# +CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m +CONFIG_NETFILTER_XT_MATCH_BPF=m +CONFIG_NETFILTER_XT_MATCH_CGROUP=m +CONFIG_NETFILTER_XT_MATCH_CLUSTER=m +CONFIG_NETFILTER_XT_MATCH_COMMENT=m +CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m +CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m +CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m +CONFIG_NETFILTER_XT_MATCH_CONNMARK=m +CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m +CONFIG_NETFILTER_XT_MATCH_CPU=m +CONFIG_NETFILTER_XT_MATCH_DCCP=m +CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m +CONFIG_NETFILTER_XT_MATCH_DSCP=m +CONFIG_NETFILTER_XT_MATCH_ECN=m +CONFIG_NETFILTER_XT_MATCH_ESP=m +CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m +CONFIG_NETFILTER_XT_MATCH_HELPER=m +CONFIG_NETFILTER_XT_MATCH_HL=m +CONFIG_NETFILTER_XT_MATCH_IPCOMP=m +CONFIG_NETFILTER_XT_MATCH_IPRANGE=m +CONFIG_NETFILTER_XT_MATCH_L2TP=m +CONFIG_NETFILTER_XT_MATCH_LENGTH=m +CONFIG_NETFILTER_XT_MATCH_LIMIT=m +CONFIG_NETFILTER_XT_MATCH_MAC=m +CONFIG_NETFILTER_XT_MATCH_MARK=m +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m +CONFIG_NETFILTER_XT_MATCH_NFACCT=m +CONFIG_NETFILTER_XT_MATCH_OSF=m +CONFIG_NETFILTER_XT_MATCH_OWNER=m +CONFIG_NETFILTER_XT_MATCH_POLICY=m +CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m +CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m +CONFIG_NETFILTER_XT_MATCH_QUOTA=m +CONFIG_NETFILTER_XT_MATCH_RATEEST=m +CONFIG_NETFILTER_XT_MATCH_REALM=m +CONFIG_NETFILTER_XT_MATCH_RECENT=m +CONFIG_NETFILTER_XT_MATCH_SCTP=m +# CONFIG_NETFILTER_XT_MATCH_SOCKET is not set +CONFIG_NETFILTER_XT_MATCH_STATE=m +CONFIG_NETFILTER_XT_MATCH_STATISTIC=m +CONFIG_NETFILTER_XT_MATCH_STRING=m +CONFIG_NETFILTER_XT_MATCH_TCPMSS=m +CONFIG_NETFILTER_XT_MATCH_TIME=m +CONFIG_NETFILTER_XT_MATCH_U32=m +# end of Core Netfilter Configuration + +# CONFIG_IP_SET is not set +# CONFIG_IP_VS is not set + +# +# IP: Netfilter Configuration +# +CONFIG_NF_DEFRAG_IPV4=m +# CONFIG_NF_SOCKET_IPV4 is not set +CONFIG_NF_TPROXY_IPV4=m +CONFIG_NF_TABLES_IPV4=y +CONFIG_NFT_REJECT_IPV4=m +CONFIG_NFT_DUP_IPV4=m +CONFIG_NFT_FIB_IPV4=m +CONFIG_NF_TABLES_ARP=y +CONFIG_NF_DUP_IPV4=m +# CONFIG_NF_LOG_ARP is not set +CONFIG_NF_LOG_IPV4=m +CONFIG_NF_REJECT_IPV4=m +CONFIG_IP_NF_IPTABLES=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_RPFILTER=m +CONFIG_IP_NF_MATCH_TTL=m +CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_SYNPROXY=m +CONFIG_IP_NF_NAT=m +CONFIG_IP_NF_TARGET_MASQUERADE=m +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_CLUSTERIP=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_NF_RAW=m +CONFIG_IP_NF_SECURITY=m +CONFIG_IP_NF_ARPTABLES=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m +# end of IP: Netfilter Configuration + +# +# IPv6: Netfilter Configuration +# +# CONFIG_NF_SOCKET_IPV6 is not set +CONFIG_NF_TPROXY_IPV6=m +CONFIG_NF_TABLES_IPV6=y +CONFIG_NFT_REJECT_IPV6=m +CONFIG_NFT_DUP_IPV6=m +CONFIG_NFT_FIB_IPV6=m +CONFIG_NF_DUP_IPV6=m +CONFIG_NF_REJECT_IPV6=m +CONFIG_NF_LOG_IPV6=m +CONFIG_IP6_NF_IPTABLES=m +# CONFIG_IP6_NF_MATCH_AH is not set +# CONFIG_IP6_NF_MATCH_EUI64 is not set +# CONFIG_IP6_NF_MATCH_FRAG is not set +# CONFIG_IP6_NF_MATCH_OPTS is not set +# CONFIG_IP6_NF_MATCH_HL is not set +# CONFIG_IP6_NF_MATCH_IPV6HEADER is not set +# CONFIG_IP6_NF_MATCH_MH is not set +# CONFIG_IP6_NF_MATCH_RPFILTER is not set +# CONFIG_IP6_NF_MATCH_RT is not set +# CONFIG_IP6_NF_MATCH_SRH is not set +# CONFIG_IP6_NF_TARGET_HL is not set +CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_TARGET_REJECT=m +# CONFIG_IP6_NF_TARGET_SYNPROXY is not set +CONFIG_IP6_NF_MANGLE=m +# CONFIG_IP6_NF_RAW is not set +# CONFIG_IP6_NF_SECURITY is not set +CONFIG_IP6_NF_NAT=m +CONFIG_IP6_NF_TARGET_MASQUERADE=m +# CONFIG_IP6_NF_TARGET_NPT is not set +# end of IPv6: Netfilter Configuration + +CONFIG_NF_DEFRAG_IPV6=m +# CONFIG_NF_TABLES_BRIDGE is not set +# CONFIG_NF_CONNTRACK_BRIDGE is not set +# CONFIG_BRIDGE_NF_EBTABLES is not set +# CONFIG_BPFILTER is not set +# CONFIG_IP_DCCP is not set +# CONFIG_IP_SCTP is not set +# CONFIG_RDS is not set +# CONFIG_TIPC is not set +# CONFIG_ATM is not set +# CONFIG_L2TP is not set +CONFIG_STP=y +CONFIG_BRIDGE=y +CONFIG_BRIDGE_IGMP_SNOOPING=y +# CONFIG_BRIDGE_VLAN_FILTERING is not set +CONFIG_HAVE_NET_DSA=y +# CONFIG_NET_DSA is not set +CONFIG_VLAN_8021Q=y +# CONFIG_VLAN_8021Q_GVRP is not set +# CONFIG_VLAN_8021Q_MVRP is not set +# CONFIG_DECNET is not set +CONFIG_LLC=y +# CONFIG_LLC2 is not set +# CONFIG_ATALK is not set +# CONFIG_X25 is not set +# CONFIG_LAPB is not set +# CONFIG_PHONET is not set +# CONFIG_6LOWPAN is not set +# CONFIG_IEEE802154 is not set +CONFIG_NET_SCHED=y + +# +# Queueing/Scheduling +# +# CONFIG_NET_SCH_CBQ is not set +# CONFIG_NET_SCH_HTB is not set +# CONFIG_NET_SCH_HFSC is not set +# CONFIG_NET_SCH_PRIO is not set +# CONFIG_NET_SCH_MULTIQ is not set +# CONFIG_NET_SCH_RED is not set +# CONFIG_NET_SCH_SFB is not set +# CONFIG_NET_SCH_SFQ is not set +# CONFIG_NET_SCH_TEQL is not set +# CONFIG_NET_SCH_TBF is not set +# CONFIG_NET_SCH_CBS is not set +# CONFIG_NET_SCH_ETF is not set +# CONFIG_NET_SCH_TAPRIO is not set +# CONFIG_NET_SCH_GRED is not set +# CONFIG_NET_SCH_DSMARK is not set +# CONFIG_NET_SCH_NETEM is not set +# CONFIG_NET_SCH_DRR is not set +# CONFIG_NET_SCH_MQPRIO is not set +# CONFIG_NET_SCH_SKBPRIO is not set +# CONFIG_NET_SCH_CHOKE is not set +# CONFIG_NET_SCH_QFQ is not set +# CONFIG_NET_SCH_CODEL is not set +# CONFIG_NET_SCH_FQ_CODEL is not set +# CONFIG_NET_SCH_CAKE is not set +# CONFIG_NET_SCH_FQ is not set +# CONFIG_NET_SCH_HHF is not set +# CONFIG_NET_SCH_PIE is not set +# CONFIG_NET_SCH_INGRESS is not set +# CONFIG_NET_SCH_PLUG is not set +# CONFIG_NET_SCH_DEFAULT is not set + +# +# Classification +# +CONFIG_NET_CLS=y +# CONFIG_NET_CLS_BASIC is not set +# CONFIG_NET_CLS_TCINDEX is not set +# CONFIG_NET_CLS_ROUTE4 is not set +# CONFIG_NET_CLS_FW is not set +# CONFIG_NET_CLS_U32 is not set +# CONFIG_NET_CLS_RSVP is not set +# CONFIG_NET_CLS_RSVP6 is not set +# CONFIG_NET_CLS_FLOW is not set +# CONFIG_NET_CLS_CGROUP is not set +# CONFIG_NET_CLS_BPF is not set +# CONFIG_NET_CLS_FLOWER is not set +# CONFIG_NET_CLS_MATCHALL is not set +CONFIG_NET_EMATCH=y +CONFIG_NET_EMATCH_STACK=32 +# CONFIG_NET_EMATCH_CMP is not set +# CONFIG_NET_EMATCH_NBYTE is not set +# CONFIG_NET_EMATCH_U32 is not set +# CONFIG_NET_EMATCH_META is not set +# CONFIG_NET_EMATCH_TEXT is not set +# CONFIG_NET_EMATCH_IPT is not set +CONFIG_NET_CLS_ACT=y +# CONFIG_NET_ACT_POLICE is not set +# CONFIG_NET_ACT_GACT is not set +# CONFIG_NET_ACT_MIRRED is not set +# CONFIG_NET_ACT_SAMPLE is not set +# CONFIG_NET_ACT_IPT is not set +# CONFIG_NET_ACT_NAT is not set +# CONFIG_NET_ACT_PEDIT is not set +# CONFIG_NET_ACT_SIMP is not set +# CONFIG_NET_ACT_SKBEDIT is not set +# CONFIG_NET_ACT_CSUM is not set +# CONFIG_NET_ACT_MPLS is not set +# CONFIG_NET_ACT_VLAN is not set +# CONFIG_NET_ACT_BPF is not set +# CONFIG_NET_ACT_CONNMARK is not set +# CONFIG_NET_ACT_CTINFO is not set +# CONFIG_NET_ACT_SKBMOD is not set +# CONFIG_NET_ACT_IFE is not set +# CONFIG_NET_ACT_TUNNEL_KEY is not set +# CONFIG_NET_ACT_CT is not set +CONFIG_NET_SCH_FIFO=y +# CONFIG_DCB is not set +CONFIG_DNS_RESOLVER=y +# CONFIG_BATMAN_ADV is not set +# CONFIG_OPENVSWITCH is not set +# CONFIG_VSOCKETS is not set +CONFIG_NETLINK_DIAG=y +# CONFIG_MPLS is not set +# CONFIG_NET_NSH is not set +# CONFIG_HSR is not set +# CONFIG_NET_SWITCHDEV is not set +# CONFIG_NET_L3_MASTER_DEV is not set +# CONFIG_NET_NCSI is not set +CONFIG_RPS=y +CONFIG_RFS_ACCEL=y +CONFIG_XPS=y +# CONFIG_CGROUP_NET_PRIO is not set +CONFIG_CGROUP_NET_CLASSID=y +CONFIG_NET_RX_BUSY_POLL=y +CONFIG_BQL=y +# CONFIG_BPF_JIT is not set +# CONFIG_BPF_STREAM_PARSER is not set +CONFIG_NET_FLOW_LIMIT=y + +# +# Network testing +# +# CONFIG_NET_PKTGEN is not set +# CONFIG_NET_DROP_MONITOR is not set +# end of Network testing +# end of Networking options + +CONFIG_HAMRADIO=y + +# +# Packet Radio protocols +# +# CONFIG_AX25 is not set +# CONFIG_CAN is not set +# CONFIG_BT is not set +# CONFIG_AF_RXRPC is not set +# CONFIG_AF_KCM is not set +CONFIG_FIB_RULES=y +CONFIG_WIRELESS=y +# CONFIG_CFG80211 is not set + +# +# CFG80211 needs to be enabled for MAC80211 +# +CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 +# CONFIG_WIMAX is not set +CONFIG_RFKILL=y +CONFIG_RFKILL_LEDS=y +CONFIG_RFKILL_INPUT=y +# CONFIG_NET_9P is not set +# CONFIG_CAIF is not set +# CONFIG_CEPH_LIB is not set +# CONFIG_NFC is not set +# CONFIG_PSAMPLE is not set +# CONFIG_NET_IFE is not set +# CONFIG_LWTUNNEL is not set +CONFIG_DST_CACHE=y +CONFIG_GRO_CELLS=y +# CONFIG_FAILOVER is not set +CONFIG_HAVE_EBPF_JIT=y + +# +# Device Drivers +# +CONFIG_HAVE_EISA=y +# CONFIG_EISA is not set +CONFIG_HAVE_PCI=y +CONFIG_PCI=y +CONFIG_PCI_DOMAINS=y +CONFIG_PCIEPORTBUS=y +CONFIG_HOTPLUG_PCI_PCIE=y +CONFIG_PCIEAER=y +# CONFIG_PCIEAER_INJECT is not set +# CONFIG_PCIE_ECRC is not set +CONFIG_PCIEASPM=y +CONFIG_PCIEASPM_DEBUG=y +CONFIG_PCIEASPM_DEFAULT=y +# CONFIG_PCIEASPM_POWERSAVE is not set +# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set +# CONFIG_PCIEASPM_PERFORMANCE is not set +CONFIG_PCIE_PME=y +# CONFIG_PCIE_DPC is not set +# CONFIG_PCIE_PTM is not set +# CONFIG_PCIE_BW is not set +CONFIG_PCI_MSI=y +CONFIG_PCI_MSI_IRQ_DOMAIN=y +CONFIG_PCI_QUIRKS=y +# CONFIG_PCI_DEBUG is not set +CONFIG_PCI_REALLOC_ENABLE_AUTO=y +CONFIG_PCI_STUB=y +# CONFIG_PCI_PF_STUB is not set +CONFIG_PCI_ATS=y +CONFIG_PCI_LOCKLESS_CONFIG=y +CONFIG_PCI_IOV=y +CONFIG_PCI_PRI=y +CONFIG_PCI_PASID=y +# CONFIG_PCI_P2PDMA is not set +CONFIG_PCI_LABEL=y +CONFIG_HOTPLUG_PCI=y +# CONFIG_HOTPLUG_PCI_ACPI is not set +# CONFIG_HOTPLUG_PCI_CPCI is not set +# CONFIG_HOTPLUG_PCI_SHPC is not set + +# +# PCI controller drivers +# + +# +# Cadence PCIe controllers support +# +# end of Cadence PCIe controllers support + +# CONFIG_VMD is not set + +# +# DesignWare PCI Core Support +# +# CONFIG_PCIE_DW_PLAT_HOST is not set +# CONFIG_PCI_MESON is not set +# end of DesignWare PCI Core Support +# end of PCI controller drivers + +# +# PCI Endpoint +# +# CONFIG_PCI_ENDPOINT is not set +# end of PCI Endpoint + +# +# PCI switch controller drivers +# +# CONFIG_PCI_SW_SWITCHTEC is not set +# end of PCI switch controller drivers + +# CONFIG_PCCARD is not set +CONFIG_RAPIDIO=y +# CONFIG_RAPIDIO_TSI721 is not set +CONFIG_RAPIDIO_DISC_TIMEOUT=30 +# CONFIG_RAPIDIO_ENABLE_RX_TX_PORTS is not set +CONFIG_RAPIDIO_DMA_ENGINE=y +# CONFIG_RAPIDIO_DEBUG is not set +# CONFIG_RAPIDIO_ENUM_BASIC is not set +# CONFIG_RAPIDIO_CHMAN is not set +# CONFIG_RAPIDIO_MPORT_CDEV is not set + +# +# RapidIO Switch drivers +# +# CONFIG_RAPIDIO_TSI57X is not set +# CONFIG_RAPIDIO_CPS_XX is not set +# CONFIG_RAPIDIO_TSI568 is not set +# CONFIG_RAPIDIO_CPS_GEN2 is not set +# CONFIG_RAPIDIO_RXS_GEN3 is not set +# end of RapidIO Switch drivers + +# +# Generic Driver Options +# +CONFIG_UEVENT_HELPER=y +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_STANDALONE=y +# CONFIG_PREVENT_FIRMWARE_BUILD is not set + +# +# Firmware loader +# +CONFIG_FW_LOADER=y +CONFIG_EXTRA_FIRMWARE="" +# CONFIG_FW_LOADER_USER_HELPER is not set +# CONFIG_FW_LOADER_COMPRESS is not set +# end of Firmware loader + +CONFIG_ALLOW_DEV_COREDUMP=y +# CONFIG_DEBUG_DRIVER is not set +# CONFIG_DEBUG_DEVRES is not set +# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set +# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set +CONFIG_GENERIC_CPU_AUTOPROBE=y +CONFIG_GENERIC_CPU_VULNERABILITIES=y +CONFIG_REGMAP=y +CONFIG_REGMAP_I2C=y +CONFIG_DMA_SHARED_BUFFER=y +# CONFIG_DMA_FENCE_TRACE is not set +# end of Generic Driver Options + +# +# Bus devices +# +# end of Bus devices + +# CONFIG_CONNECTOR is not set +# CONFIG_GNSS is not set +# CONFIG_MTD is not set +# CONFIG_OF is not set +CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_PARPORT=y +CONFIG_PARPORT_PC=y +CONFIG_PARPORT_SERIAL=y +# CONFIG_PARPORT_PC_FIFO is not set +# CONFIG_PARPORT_PC_SUPERIO is not set +# CONFIG_PARPORT_AX88796 is not set +# CONFIG_PARPORT_1284 is not set +CONFIG_PNP=y +CONFIG_PNP_DEBUG_MESSAGES=y + +# +# Protocols +# +CONFIG_PNPACPI=y +CONFIG_BLK_DEV=y +# CONFIG_BLK_DEV_NULL_BLK is not set +# CONFIG_BLK_DEV_FD is not set +CONFIG_CDROM=y +# CONFIG_PARIDE is not set +# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set +# CONFIG_ZRAM is not set +# CONFIG_BLK_DEV_UMEM is not set +CONFIG_BLK_DEV_LOOP=y +CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 +# CONFIG_BLK_DEV_CRYPTOLOOP is not set +# CONFIG_BLK_DEV_DRBD is not set +# CONFIG_BLK_DEV_NBD is not set +# CONFIG_BLK_DEV_SKD is not set +# CONFIG_BLK_DEV_SX8 is not set +CONFIG_BLK_DEV_RAM=y +CONFIG_BLK_DEV_RAM_COUNT=16 +CONFIG_BLK_DEV_RAM_SIZE=16384 +# CONFIG_CDROM_PKTCDVD is not set +# CONFIG_ATA_OVER_ETH is not set +# CONFIG_BLK_DEV_RBD is not set +# CONFIG_BLK_DEV_RSXX is not set + +# +# NVME Support +# +CONFIG_NVME_CORE=y +CONFIG_BLK_DEV_NVME=y +# CONFIG_NVME_MULTIPATH is not set +# CONFIG_NVME_FC is not set +# CONFIG_NVME_TCP is not set +# CONFIG_NVME_TARGET is not set +# end of NVME Support + +# +# Misc devices +# +# CONFIG_AD525X_DPOT is not set +# CONFIG_DUMMY_IRQ is not set +# CONFIG_IBM_ASM is not set +# CONFIG_PHANTOM is not set +# CONFIG_SGI_IOC4 is not set +# CONFIG_TIFM_CORE is not set +# CONFIG_ICS932S401 is not set +# CONFIG_ENCLOSURE_SERVICES is not set +# CONFIG_HP_ILO is not set +# CONFIG_APDS9802ALS is not set +# CONFIG_ISL29003 is not set +# CONFIG_ISL29020 is not set +# CONFIG_SENSORS_TSL2550 is not set +# CONFIG_SENSORS_BH1770 is not set +# CONFIG_SENSORS_APDS990X is not set +# CONFIG_HMC6352 is not set +# CONFIG_DS1682 is not set +# CONFIG_SRAM is not set +# CONFIG_PCI_ENDPOINT_TEST is not set +# CONFIG_XILINX_SDFEC is not set +# CONFIG_PVPANIC is not set +# CONFIG_C2PORT is not set + +# +# EEPROM support +# +# CONFIG_EEPROM_AT24 is not set +# CONFIG_EEPROM_LEGACY is not set +# CONFIG_EEPROM_MAX6875 is not set +# CONFIG_EEPROM_93CX6 is not set +# CONFIG_EEPROM_IDT_89HPESX is not set +# CONFIG_EEPROM_EE1004 is not set +# end of EEPROM support + +# CONFIG_CB710_CORE is not set + +# +# Texas Instruments shared transport line discipline +# +# end of Texas Instruments shared transport line discipline + +# CONFIG_SENSORS_LIS3_I2C is not set +# CONFIG_ALTERA_STAPL is not set +# CONFIG_INTEL_MEI is not set +# CONFIG_INTEL_MEI_ME is not set +# CONFIG_INTEL_MEI_TXE is not set +# CONFIG_VMWARE_VMCI is not set + +# +# Intel MIC & related support +# + +# +# Intel MIC Bus Driver +# +# CONFIG_INTEL_MIC_BUS is not set + +# +# SCIF Bus Driver +# +# CONFIG_SCIF_BUS is not set + +# +# VOP Bus Driver +# +# CONFIG_VOP_BUS is not set + +# +# Intel MIC Host Driver +# + +# +# Intel MIC Card Driver +# + +# +# SCIF Driver +# + +# +# Intel MIC Coprocessor State Management (COSM) Drivers +# + +# +# VOP Driver +# +# end of Intel MIC & related support + +# CONFIG_GENWQE is not set +# CONFIG_ECHO is not set +# CONFIG_MISC_ALCOR_PCI is not set +# CONFIG_MISC_RTSX_PCI is not set +# CONFIG_MISC_RTSX_USB is not set +# CONFIG_HABANA_AI is not set +# end of Misc devices + +CONFIG_HAVE_IDE=y +# CONFIG_IDE is not set + +# +# SCSI device support +# +CONFIG_SCSI_MOD=y +# CONFIG_RAID_ATTRS is not set +CONFIG_SCSI=y +CONFIG_SCSI_DMA=y +CONFIG_SCSI_PROC_FS=y + +# +# SCSI support type (disk, tape, CD-ROM) +# +CONFIG_BLK_DEV_SD=y +# CONFIG_CHR_DEV_ST is not set +CONFIG_BLK_DEV_SR=y +# CONFIG_BLK_DEV_SR_VENDOR is not set +CONFIG_CHR_DEV_SG=y +# CONFIG_CHR_DEV_SCH is not set +CONFIG_SCSI_CONSTANTS=y +# CONFIG_SCSI_LOGGING is not set +# CONFIG_SCSI_SCAN_ASYNC is not set + +# +# SCSI Transports +# +CONFIG_SCSI_SPI_ATTRS=y +# CONFIG_SCSI_FC_ATTRS is not set +CONFIG_SCSI_ISCSI_ATTRS=y +# CONFIG_SCSI_SAS_ATTRS is not set +# CONFIG_SCSI_SAS_LIBSAS is not set +# CONFIG_SCSI_SRP_ATTRS is not set +# end of SCSI Transports + +# CONFIG_SCSI_LOWLEVEL is not set +# CONFIG_SCSI_DH is not set +# end of SCSI device support + +CONFIG_ATA=y +CONFIG_ATA_VERBOSE_ERROR=y +CONFIG_ATA_ACPI=y +# CONFIG_SATA_ZPODD is not set +CONFIG_SATA_PMP=y + +# +# Controllers with non-SFF native interface +# +CONFIG_SATA_AHCI=y +CONFIG_SATA_MOBILE_LPM_POLICY=0 +CONFIG_SATA_AHCI_PLATFORM=y +# CONFIG_SATA_INIC162X is not set +# CONFIG_SATA_ACARD_AHCI is not set +CONFIG_SATA_SIL24=y +CONFIG_ATA_SFF=y + +# +# SFF controllers with custom DMA interface +# +# CONFIG_PDC_ADMA is not set +# CONFIG_SATA_QSTOR is not set +CONFIG_SATA_SX4=y +CONFIG_ATA_BMDMA=y + +# +# SATA SFF controllers with BMDMA +# +CONFIG_ATA_PIIX=y +# CONFIG_SATA_DWC is not set +# CONFIG_SATA_MV is not set +# CONFIG_SATA_NV is not set +CONFIG_SATA_PROMISE=y +CONFIG_SATA_SIL=y +# CONFIG_SATA_SIS is not set +# CONFIG_SATA_SVW is not set +# CONFIG_SATA_ULI is not set +# CONFIG_SATA_VIA is not set +# CONFIG_SATA_VITESSE is not set + +# +# PATA SFF controllers with BMDMA +# +# CONFIG_PATA_ALI is not set +CONFIG_PATA_AMD=y +# CONFIG_PATA_ARTOP is not set +CONFIG_PATA_ATIIXP=y +# CONFIG_PATA_ATP867X is not set +# CONFIG_PATA_CMD64X is not set +# CONFIG_PATA_CYPRESS is not set +# CONFIG_PATA_EFAR is not set +# CONFIG_PATA_HPT366 is not set +# CONFIG_PATA_HPT37X is not set +# CONFIG_PATA_HPT3X2N is not set +# CONFIG_PATA_HPT3X3 is not set +# CONFIG_PATA_IT8213 is not set +# CONFIG_PATA_IT821X is not set +# CONFIG_PATA_JMICRON is not set +# CONFIG_PATA_MARVELL is not set +# CONFIG_PATA_NETCELL is not set +# CONFIG_PATA_NINJA32 is not set +# CONFIG_PATA_NS87415 is not set +CONFIG_PATA_OLDPIIX=y +# CONFIG_PATA_OPTIDMA is not set +# CONFIG_PATA_PDC2027X is not set +# CONFIG_PATA_PDC_OLD is not set +# CONFIG_PATA_RADISYS is not set +# CONFIG_PATA_RDC is not set +CONFIG_PATA_SCH=y +CONFIG_PATA_SERVERWORKS=y +# CONFIG_PATA_SIL680 is not set +# CONFIG_PATA_SIS is not set +# CONFIG_PATA_TOSHIBA is not set +# CONFIG_PATA_TRIFLEX is not set +# CONFIG_PATA_VIA is not set +# CONFIG_PATA_WINBOND is not set + +# +# PIO-only SFF controllers +# +# CONFIG_PATA_CMD640_PCI is not set +# CONFIG_PATA_MPIIX is not set +# CONFIG_PATA_NS87410 is not set +# CONFIG_PATA_OPTI is not set +# CONFIG_PATA_PLATFORM is not set +# CONFIG_PATA_RZ1000 is not set + +# +# Generic fallback / legacy drivers +# +# CONFIG_PATA_ACPI is not set +CONFIG_ATA_GENERIC=y +# CONFIG_PATA_LEGACY is not set +CONFIG_MD=y +CONFIG_BLK_DEV_MD=y +CONFIG_MD_AUTODETECT=y +# CONFIG_MD_LINEAR is not set +# CONFIG_MD_RAID0 is not set +# CONFIG_MD_RAID1 is not set +# CONFIG_MD_RAID10 is not set +# CONFIG_MD_RAID456 is not set +# CONFIG_MD_MULTIPATH is not set +# CONFIG_MD_FAULTY is not set +# CONFIG_BCACHE is not set +CONFIG_BLK_DEV_DM_BUILTIN=y +CONFIG_BLK_DEV_DM=y +# CONFIG_DM_DEBUG is not set +# CONFIG_DM_UNSTRIPED is not set +# CONFIG_DM_CRYPT is not set +# CONFIG_DM_SNAPSHOT is not set +# CONFIG_DM_THIN_PROVISIONING is not set +# CONFIG_DM_CACHE is not set +# CONFIG_DM_WRITECACHE is not set +# CONFIG_DM_ERA is not set +CONFIG_DM_MIRROR=y +# CONFIG_DM_LOG_USERSPACE is not set +# CONFIG_DM_RAID is not set +CONFIG_DM_ZERO=y +# CONFIG_DM_MULTIPATH is not set +# CONFIG_DM_DELAY is not set +# CONFIG_DM_DUST is not set +# CONFIG_DM_INIT is not set +# CONFIG_DM_UEVENT is not set +# CONFIG_DM_FLAKEY is not set +# CONFIG_DM_VERITY is not set +# CONFIG_DM_SWITCH is not set +# CONFIG_DM_LOG_WRITES is not set +# CONFIG_DM_INTEGRITY is not set +# CONFIG_TARGET_CORE is not set +CONFIG_FUSION=y +CONFIG_FUSION_SPI=y +# CONFIG_FUSION_SAS is not set +CONFIG_FUSION_MAX_SGE=128 +# CONFIG_FUSION_CTL is not set +# CONFIG_FUSION_LOGGING is not set + +# +# IEEE 1394 (FireWire) support +# +# CONFIG_FIREWIRE is not set +# CONFIG_FIREWIRE_NOSY is not set +# end of IEEE 1394 (FireWire) support + +# CONFIG_MACINTOSH_DRIVERS is not set +CONFIG_NETDEVICES=y +CONFIG_MII=y +CONFIG_NET_CORE=y +# CONFIG_BONDING is not set +# CONFIG_DUMMY is not set +# CONFIG_EQUALIZER is not set +# CONFIG_NET_FC is not set +# CONFIG_IFB is not set +# CONFIG_NET_TEAM is not set +CONFIG_MACVLAN=y +# CONFIG_MACVTAP is not set +# CONFIG_IPVLAN is not set +# CONFIG_VXLAN is not set +# CONFIG_GENEVE is not set +# CONFIG_GTP is not set +# CONFIG_MACSEC is not set +CONFIG_NETCONSOLE=y +CONFIG_NETCONSOLE_DYNAMIC=y +CONFIG_NETPOLL=y +CONFIG_NET_POLL_CONTROLLER=y +# CONFIG_RIONET is not set +# CONFIG_TUN is not set +# CONFIG_TUN_VNET_CROSS_LE is not set +CONFIG_VETH=y +# CONFIG_NLMON is not set +# CONFIG_ARCNET is not set + +# +# CAIF transport drivers +# + +# +# Distributed Switch Architecture drivers +# +# end of Distributed Switch Architecture drivers + +CONFIG_ETHERNET=y +CONFIG_MDIO=y +CONFIG_NET_VENDOR_3COM=y +# CONFIG_VORTEX is not set +# CONFIG_TYPHOON is not set +CONFIG_NET_VENDOR_ADAPTEC=y +# CONFIG_ADAPTEC_STARFIRE is not set +CONFIG_NET_VENDOR_AGERE=y +# CONFIG_ET131X is not set +CONFIG_NET_VENDOR_ALACRITECH=y +# CONFIG_SLICOSS is not set +CONFIG_NET_VENDOR_ALTEON=y +# CONFIG_ACENIC is not set +# CONFIG_ALTERA_TSE is not set +CONFIG_NET_VENDOR_AMAZON=y +# CONFIG_ENA_ETHERNET is not set +CONFIG_NET_VENDOR_AMD=y +# CONFIG_AMD8111_ETH is not set +# CONFIG_PCNET32 is not set +# CONFIG_AMD_XGBE is not set +CONFIG_NET_VENDOR_AQUANTIA=y +# CONFIG_AQTION is not set +CONFIG_NET_VENDOR_ARC=y +CONFIG_NET_VENDOR_ATHEROS=y +# CONFIG_ATL2 is not set +# CONFIG_ATL1 is not set +# CONFIG_ATL1E is not set +# CONFIG_ATL1C is not set +CONFIG_ALX=y +# CONFIG_NET_VENDOR_AURORA is not set +CONFIG_NET_VENDOR_BROADCOM=y +# CONFIG_B44 is not set +# CONFIG_BCMGENET is not set +CONFIG_BNX2=y +# CONFIG_CNIC is not set +CONFIG_TIGON3=y +CONFIG_TIGON3_HWMON=y +# CONFIG_BNX2X is not set +# CONFIG_SYSTEMPORT is not set +# CONFIG_BNXT is not set +CONFIG_NET_VENDOR_BROCADE=y +# CONFIG_BNA is not set +CONFIG_NET_VENDOR_CADENCE=y +# CONFIG_MACB is not set +CONFIG_NET_VENDOR_CAVIUM=y +# CONFIG_THUNDER_NIC_PF is not set +# CONFIG_THUNDER_NIC_VF is not set +# CONFIG_THUNDER_NIC_BGX is not set +# CONFIG_THUNDER_NIC_RGX is not set +CONFIG_CAVIUM_PTP=y +# CONFIG_LIQUIDIO is not set +# CONFIG_LIQUIDIO_VF is not set +CONFIG_NET_VENDOR_CHELSIO=y +# CONFIG_CHELSIO_T1 is not set +# CONFIG_CHELSIO_T3 is not set +# CONFIG_CHELSIO_T4 is not set +# CONFIG_CHELSIO_T4VF is not set +CONFIG_NET_VENDOR_CISCO=y +# CONFIG_ENIC is not set +CONFIG_NET_VENDOR_CORTINA=y +# CONFIG_CX_ECAT is not set +# CONFIG_DNET is not set +CONFIG_NET_VENDOR_DEC=y +CONFIG_NET_TULIP=y +# CONFIG_DE2104X is not set +# CONFIG_TULIP is not set +# CONFIG_DE4X5 is not set +# CONFIG_WINBOND_840 is not set +# CONFIG_DM9102 is not set +# CONFIG_ULI526X is not set +CONFIG_NET_VENDOR_DLINK=y +# CONFIG_DL2K is not set +# CONFIG_SUNDANCE is not set +CONFIG_NET_VENDOR_EMULEX=y +# CONFIG_BE2NET is not set +CONFIG_NET_VENDOR_EZCHIP=y +CONFIG_NET_VENDOR_GOOGLE=y +# CONFIG_GVE is not set +CONFIG_NET_VENDOR_HP=y +# CONFIG_HP100 is not set +CONFIG_NET_VENDOR_HUAWEI=y +# CONFIG_HINIC is not set +CONFIG_NET_VENDOR_I825XX=y +CONFIG_NET_VENDOR_INTEL=y +CONFIG_E100=y +CONFIG_E1000=y +CONFIG_E1000E=y +CONFIG_E1000E_HWTS=y +CONFIG_IGB=y +CONFIG_IGB_HWMON=y +CONFIG_IGBVF=y +CONFIG_IXGB=y +CONFIG_IXGBE=y +CONFIG_IXGBE_HWMON=y +# CONFIG_IXGBEVF is not set +CONFIG_I40E=y +# CONFIG_I40EVF is not set +# CONFIG_ICE is not set +# CONFIG_FM10K is not set +# CONFIG_IGC is not set +# CONFIG_JME is not set +CONFIG_NET_VENDOR_MARVELL=y +# CONFIG_MVMDIO is not set +# CONFIG_SKGE is not set +CONFIG_SKY2=y +# CONFIG_SKY2_DEBUG is not set +CONFIG_NET_VENDOR_MELLANOX=y +# CONFIG_MLX4_EN is not set +# CONFIG_MLX5_CORE is not set +# CONFIG_MLXSW_CORE is not set +# CONFIG_MLXFW is not set +CONFIG_NET_VENDOR_MICREL=y +# CONFIG_KS8842 is not set +# CONFIG_KS8851_MLL is not set +# CONFIG_KSZ884X_PCI is not set +CONFIG_NET_VENDOR_MICROCHIP=y +# CONFIG_LAN743X is not set +CONFIG_NET_VENDOR_MICROSEMI=y +CONFIG_NET_VENDOR_MYRI=y +# CONFIG_MYRI10GE is not set +# CONFIG_FEALNX is not set +CONFIG_NET_VENDOR_NATSEMI=y +# CONFIG_NATSEMI is not set +# CONFIG_NS83820 is not set +CONFIG_NET_VENDOR_NETERION=y +# CONFIG_S2IO is not set +# CONFIG_VXGE is not set +CONFIG_NET_VENDOR_NETRONOME=y +# CONFIG_NFP is not set +CONFIG_NET_VENDOR_NI=y +# CONFIG_NI_XGE_MANAGEMENT_ENET is not set +CONFIG_NET_VENDOR_8390=y +# CONFIG_NE2K_PCI is not set +CONFIG_NET_VENDOR_NVIDIA=y +CONFIG_FORCEDETH=y +CONFIG_NET_VENDOR_OKI=y +# CONFIG_ETHOC is not set +CONFIG_NET_VENDOR_PACKET_ENGINES=y +# CONFIG_HAMACHI is not set +# CONFIG_YELLOWFIN is not set +CONFIG_NET_VENDOR_QLOGIC=y +# CONFIG_QLA3XXX is not set +# CONFIG_QLCNIC is not set +# CONFIG_QLGE is not set +# CONFIG_NETXEN_NIC is not set +# CONFIG_QED is not set +CONFIG_NET_VENDOR_QUALCOMM=y +# CONFIG_QCOM_EMAC is not set +# CONFIG_RMNET is not set +CONFIG_NET_VENDOR_RDC=y +# CONFIG_R6040 is not set +CONFIG_NET_VENDOR_REALTEK=y +# CONFIG_ATP is not set +CONFIG_8139CP=y +CONFIG_8139TOO=y +CONFIG_8139TOO_PIO=y +# CONFIG_8139TOO_TUNE_TWISTER is not set +# CONFIG_8139TOO_8129 is not set +# CONFIG_8139_OLD_RX_RESET is not set +CONFIG_R8169=y +CONFIG_NET_VENDOR_RENESAS=y +CONFIG_NET_VENDOR_ROCKER=y +CONFIG_NET_VENDOR_SAMSUNG=y +# CONFIG_SXGBE_ETH is not set +CONFIG_NET_VENDOR_SEEQ=y +CONFIG_NET_VENDOR_SOLARFLARE=y +# CONFIG_SFC is not set +# CONFIG_SFC_FALCON is not set +CONFIG_NET_VENDOR_SILAN=y +# CONFIG_SC92031 is not set +CONFIG_NET_VENDOR_SIS=y +# CONFIG_SIS900 is not set +# CONFIG_SIS190 is not set +CONFIG_NET_VENDOR_SMSC=y +# CONFIG_EPIC100 is not set +# CONFIG_SMSC911X is not set +# CONFIG_SMSC9420 is not set +CONFIG_NET_VENDOR_SOCIONEXT=y +CONFIG_NET_VENDOR_STMICRO=y +# CONFIG_STMMAC_ETH is not set +CONFIG_NET_VENDOR_SUN=y +# CONFIG_HAPPYMEAL is not set +# CONFIG_SUNGEM is not set +# CONFIG_CASSINI is not set +# CONFIG_NIU is not set +CONFIG_NET_VENDOR_SYNOPSYS=y +# CONFIG_DWC_XLGMAC is not set +CONFIG_NET_VENDOR_TEHUTI=y +# CONFIG_TEHUTI is not set +CONFIG_NET_VENDOR_TI=y +# CONFIG_TI_CPSW_PHY_SEL is not set +# CONFIG_TLAN is not set +CONFIG_NET_VENDOR_VIA=y +# CONFIG_VIA_RHINE is not set +# CONFIG_VIA_VELOCITY is not set +CONFIG_NET_VENDOR_WIZNET=y +CONFIG_WIZNET_W5100=y +CONFIG_WIZNET_W5300=y +# CONFIG_WIZNET_BUS_DIRECT is not set +# CONFIG_WIZNET_BUS_INDIRECT is not set +CONFIG_WIZNET_BUS_ANY=y +CONFIG_NET_VENDOR_XILINX=y +# CONFIG_XILINX_AXI_EMAC is not set +# CONFIG_XILINX_LL_TEMAC is not set +CONFIG_FDDI=y +# CONFIG_DEFXX is not set +# CONFIG_SKFP is not set +# CONFIG_HIPPI is not set +# CONFIG_NET_SB1000 is not set +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_BUS=y +# CONFIG_MDIO_BCM_UNIMAC is not set +# CONFIG_MDIO_BITBANG is not set +# CONFIG_MDIO_MSCC_MIIM is not set +# CONFIG_MDIO_THUNDER is not set +CONFIG_PHYLIB=y +# CONFIG_LED_TRIGGER_PHY is not set + +# +# MII PHY device drivers +# +CONFIG_AMD_PHY=y +# CONFIG_AQUANTIA_PHY is not set +# CONFIG_AX88796B_PHY is not set +# CONFIG_AT803X_PHY is not set +# CONFIG_BCM7XXX_PHY is not set +# CONFIG_BCM87XX_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_CICADA_PHY is not set +# CONFIG_CORTINA_PHY is not set +# CONFIG_DAVICOM_PHY is not set +# CONFIG_DP83822_PHY is not set +# CONFIG_DP83TC811_PHY is not set +# CONFIG_DP83848_PHY is not set +# CONFIG_DP83867_PHY is not set +# CONFIG_FIXED_PHY is not set +# CONFIG_ICPLUS_PHY is not set +# CONFIG_INTEL_XWAY_PHY is not set +# CONFIG_LSI_ET1011C_PHY is not set +# CONFIG_LXT_PHY is not set +# CONFIG_MARVELL_PHY is not set +# CONFIG_MARVELL_10G_PHY is not set +# CONFIG_MICREL_PHY is not set +# CONFIG_MICROCHIP_PHY is not set +# CONFIG_MICROCHIP_T1_PHY is not set +# CONFIG_MICROSEMI_PHY is not set +# CONFIG_NATIONAL_PHY is not set +# CONFIG_NXP_TJA11XX_PHY is not set +# CONFIG_QSEMI_PHY is not set +CONFIG_REALTEK_PHY=y +# CONFIG_RENESAS_PHY is not set +# CONFIG_ROCKCHIP_PHY is not set +# CONFIG_SMSC_PHY is not set +# CONFIG_STE10XP is not set +# CONFIG_TERANETICS_PHY is not set +# CONFIG_VITESSE_PHY is not set +# CONFIG_XILINX_GMII2RGMII is not set +# CONFIG_PLIP is not set +# CONFIG_PPP is not set +# CONFIG_SLIP is not set +CONFIG_USB_NET_DRIVERS=m +# CONFIG_USB_CATC is not set +# CONFIG_USB_KAWETH is not set +# CONFIG_USB_PEGASUS is not set +# CONFIG_USB_RTL8150 is not set +CONFIG_USB_RTL8152=m +# CONFIG_USB_LAN78XX is not set +CONFIG_USB_USBNET=m +CONFIG_USB_NET_AX8817X=m +CONFIG_USB_NET_AX88179_178A=m +CONFIG_USB_NET_CDCETHER=m +# CONFIG_USB_NET_CDC_EEM is not set +CONFIG_USB_NET_CDC_NCM=m +# CONFIG_USB_NET_HUAWEI_CDC_NCM is not set +# CONFIG_USB_NET_CDC_MBIM is not set +# CONFIG_USB_NET_DM9601 is not set +# CONFIG_USB_NET_SR9700 is not set +# CONFIG_USB_NET_SR9800 is not set +# CONFIG_USB_NET_SMSC75XX is not set +# CONFIG_USB_NET_SMSC95XX is not set +# CONFIG_USB_NET_GL620A is not set +CONFIG_USB_NET_NET1080=m +# CONFIG_USB_NET_PLUSB is not set +# CONFIG_USB_NET_MCS7830 is not set +# CONFIG_USB_NET_RNDIS_HOST is not set +CONFIG_USB_NET_CDC_SUBSET_ENABLE=m +CONFIG_USB_NET_CDC_SUBSET=m +# CONFIG_USB_ALI_M5632 is not set +# CONFIG_USB_AN2720 is not set +CONFIG_USB_BELKIN=y +# CONFIG_USB_ARMLINUX is not set +# CONFIG_USB_EPSON2888 is not set +# CONFIG_USB_KC2190 is not set +# CONFIG_USB_NET_ZAURUS is not set +# CONFIG_USB_NET_CX82310_ETH is not set +# CONFIG_USB_NET_KALMIA is not set +# CONFIG_USB_NET_QMI_WWAN is not set +# CONFIG_USB_HSO is not set +# CONFIG_USB_NET_INT51X1 is not set +# CONFIG_USB_IPHETH is not set +# CONFIG_USB_SIERRA_NET is not set +# CONFIG_USB_VL600 is not set +# CONFIG_USB_NET_CH9200 is not set +# CONFIG_USB_NET_AQC111 is not set +CONFIG_WLAN=y +# CONFIG_WIRELESS_WDS is not set +CONFIG_WLAN_VENDOR_ADMTEK=y +CONFIG_WLAN_VENDOR_ATH=y +# CONFIG_ATH_DEBUG is not set +# CONFIG_ATH5K_PCI is not set +CONFIG_WLAN_VENDOR_ATMEL=y +CONFIG_WLAN_VENDOR_BROADCOM=y +CONFIG_WLAN_VENDOR_CISCO=y +CONFIG_WLAN_VENDOR_INTEL=y +CONFIG_WLAN_VENDOR_INTERSIL=y +# CONFIG_HOSTAP is not set +# CONFIG_PRISM54 is not set +CONFIG_WLAN_VENDOR_MARVELL=y +CONFIG_WLAN_VENDOR_MEDIATEK=y +CONFIG_WLAN_VENDOR_RALINK=y +CONFIG_WLAN_VENDOR_REALTEK=y +CONFIG_WLAN_VENDOR_RSI=y +CONFIG_WLAN_VENDOR_ST=y +CONFIG_WLAN_VENDOR_TI=y +CONFIG_WLAN_VENDOR_ZYDAS=y +CONFIG_WLAN_VENDOR_QUANTENNA=y + +# +# Enable WiMAX (Networking options) to see the WiMAX drivers +# +# CONFIG_WAN is not set +# CONFIG_VMXNET3 is not set +# CONFIG_FUJITSU_ES is not set +# CONFIG_NETDEVSIM is not set +# CONFIG_NET_FAILOVER is not set +# CONFIG_ISDN is not set +# CONFIG_NVM is not set + +# +# Input device support +# +CONFIG_INPUT=y +CONFIG_INPUT_LEDS=y +CONFIG_INPUT_FF_MEMLESS=y +CONFIG_INPUT_POLLDEV=y +CONFIG_INPUT_SPARSEKMAP=y +# CONFIG_INPUT_MATRIXKMAP is not set + +# +# Userland interfaces +# +CONFIG_INPUT_MOUSEDEV=y +# CONFIG_INPUT_MOUSEDEV_PSAUX is not set +CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 +CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 +# CONFIG_INPUT_JOYDEV is not set +CONFIG_INPUT_EVDEV=y +# CONFIG_INPUT_EVBUG is not set + +# +# Input Device Drivers +# +CONFIG_INPUT_KEYBOARD=y +# CONFIG_KEYBOARD_ADP5588 is not set +# CONFIG_KEYBOARD_ADP5589 is not set +CONFIG_KEYBOARD_ATKBD=y +# CONFIG_KEYBOARD_QT1050 is not set +# CONFIG_KEYBOARD_QT1070 is not set +# CONFIG_KEYBOARD_QT2160 is not set +# CONFIG_KEYBOARD_DLINK_DIR685 is not set +# CONFIG_KEYBOARD_LKKBD is not set +# CONFIG_KEYBOARD_TCA6416 is not set +# CONFIG_KEYBOARD_TCA8418 is not set +# CONFIG_KEYBOARD_LM8323 is not set +# CONFIG_KEYBOARD_LM8333 is not set +# CONFIG_KEYBOARD_MAX7359 is not set +# CONFIG_KEYBOARD_MCS is not set +# CONFIG_KEYBOARD_MPR121 is not set +# CONFIG_KEYBOARD_NEWTON is not set +# CONFIG_KEYBOARD_OPENCORES is not set +# CONFIG_KEYBOARD_SAMSUNG is not set +# CONFIG_KEYBOARD_STOWAWAY is not set +# CONFIG_KEYBOARD_SUNKBD is not set +# CONFIG_KEYBOARD_TM2_TOUCHKEY is not set +# CONFIG_KEYBOARD_XTKBD is not set +CONFIG_INPUT_MOUSE=y +CONFIG_MOUSE_PS2=y +CONFIG_MOUSE_PS2_ALPS=y +CONFIG_MOUSE_PS2_BYD=y +CONFIG_MOUSE_PS2_LOGIPS2PP=y +CONFIG_MOUSE_PS2_SYNAPTICS=y +CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y +CONFIG_MOUSE_PS2_CYPRESS=y +CONFIG_MOUSE_PS2_LIFEBOOK=y +CONFIG_MOUSE_PS2_TRACKPOINT=y +# CONFIG_MOUSE_PS2_ELANTECH is not set +# CONFIG_MOUSE_PS2_SENTELIC is not set +# CONFIG_MOUSE_PS2_TOUCHKIT is not set +CONFIG_MOUSE_PS2_FOCALTECH=y +# CONFIG_MOUSE_PS2_VMMOUSE is not set +CONFIG_MOUSE_PS2_SMBUS=y +# CONFIG_MOUSE_SERIAL is not set +# CONFIG_MOUSE_APPLETOUCH is not set +# CONFIG_MOUSE_BCM5974 is not set +# CONFIG_MOUSE_CYAPA is not set +# CONFIG_MOUSE_ELAN_I2C is not set +# CONFIG_MOUSE_VSXXXAA is not set +# CONFIG_MOUSE_SYNAPTICS_I2C is not set +# CONFIG_MOUSE_SYNAPTICS_USB is not set +# CONFIG_INPUT_JOYSTICK is not set +# CONFIG_INPUT_TABLET is not set +# CONFIG_INPUT_TOUCHSCREEN is not set +# CONFIG_INPUT_MISC is not set +# CONFIG_RMI4_CORE is not set + +# +# Hardware I/O ports +# +CONFIG_SERIO=y +CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y +CONFIG_SERIO_I8042=y +CONFIG_SERIO_SERPORT=y +# CONFIG_SERIO_CT82C710 is not set +# CONFIG_SERIO_PARKBD is not set +# CONFIG_SERIO_PCIPS2 is not set +CONFIG_SERIO_LIBPS2=y +# CONFIG_SERIO_RAW is not set +# CONFIG_SERIO_ALTERA_PS2 is not set +# CONFIG_SERIO_PS2MULT is not set +# CONFIG_SERIO_ARC_PS2 is not set +# CONFIG_USERIO is not set +# CONFIG_GAMEPORT is not set +# end of Hardware I/O ports +# end of Input device support + +# +# Character devices +# +CONFIG_TTY=y +CONFIG_VT=y +CONFIG_CONSOLE_TRANSLATIONS=y +CONFIG_VT_CONSOLE=y +CONFIG_VT_CONSOLE_SLEEP=y +CONFIG_HW_CONSOLE=y +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_UNIX98_PTYS=y +# CONFIG_LEGACY_PTYS is not set +CONFIG_SERIAL_NONSTANDARD=y +# CONFIG_ROCKETPORT is not set +# CONFIG_CYCLADES is not set +# CONFIG_MOXA_INTELLIO is not set +# CONFIG_MOXA_SMARTIO is not set +# CONFIG_SYNCLINK is not set +# CONFIG_SYNCLINKMP is not set +# CONFIG_SYNCLINK_GT is not set +# CONFIG_NOZOMI is not set +# CONFIG_ISI is not set +# CONFIG_N_HDLC is not set +# CONFIG_N_GSM is not set +# CONFIG_TRACE_SINK is not set +# CONFIG_NULL_TTY is not set +CONFIG_LDISC_AUTOLOAD=y +CONFIG_DEVMEM=y +# CONFIG_DEVKMEM is not set + +# +# Serial drivers +# +CONFIG_SERIAL_EARLYCON=y +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y +CONFIG_SERIAL_8250_PNP=y +# CONFIG_SERIAL_8250_FINTEK is not set +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_DMA=y +CONFIG_SERIAL_8250_PCI=y +CONFIG_SERIAL_8250_EXAR=y +CONFIG_SERIAL_8250_NR_UARTS=32 +CONFIG_SERIAL_8250_RUNTIME_UARTS=4 +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_MANY_PORTS=y +CONFIG_SERIAL_8250_SHARE_IRQ=y +CONFIG_SERIAL_8250_DETECT_IRQ=y +CONFIG_SERIAL_8250_RSA=y +# CONFIG_SERIAL_8250_DW is not set +# CONFIG_SERIAL_8250_RT288X is not set +CONFIG_SERIAL_8250_LPSS=y +# CONFIG_SERIAL_8250_MID is not set +# CONFIG_SERIAL_8250_MOXA is not set + +# +# Non-8250 serial port support +# +# CONFIG_SERIAL_KGDB_NMI is not set +# CONFIG_SERIAL_UARTLITE is not set +CONFIG_SERIAL_CORE=y +CONFIG_SERIAL_CORE_CONSOLE=y +CONFIG_CONSOLE_POLL=y +# CONFIG_SERIAL_JSM is not set +# CONFIG_SERIAL_SCCNXP is not set +# CONFIG_SERIAL_SC16IS7XX is not set +# CONFIG_SERIAL_ALTERA_JTAGUART is not set +# CONFIG_SERIAL_ALTERA_UART is not set +# CONFIG_SERIAL_ARC is not set +# CONFIG_SERIAL_RP2 is not set +# CONFIG_SERIAL_FSL_LPUART is not set +# end of Serial drivers + +# CONFIG_SERIAL_DEV_BUS is not set +# CONFIG_TTY_PRINTK is not set +# CONFIG_PRINTER is not set +# CONFIG_PPDEV is not set +# CONFIG_IPMI_HANDLER is not set +# CONFIG_HW_RANDOM is not set +# CONFIG_NVRAM is not set +# CONFIG_APPLICOM is not set +# CONFIG_MWAVE is not set +# CONFIG_RAW_DRIVER is not set +# CONFIG_HPET is not set +# CONFIG_HANGCHECK_TIMER is not set +# CONFIG_TCG_TPM is not set +# CONFIG_TELCLOCK is not set +CONFIG_DEVPORT=y +# CONFIG_XILLYBUS is not set +# end of Character devices + +# CONFIG_RANDOM_TRUST_CPU is not set + +# +# I2C support +# +CONFIG_I2C=y +CONFIG_ACPI_I2C_OPREGION=y +CONFIG_I2C_BOARDINFO=y +CONFIG_I2C_COMPAT=y +# CONFIG_I2C_CHARDEV is not set +# CONFIG_I2C_MUX is not set +CONFIG_I2C_HELPER_AUTO=y +CONFIG_I2C_SMBUS=y +CONFIG_I2C_ALGOBIT=y + +# +# I2C Hardware Bus support +# + +# +# PC SMBus host controller drivers +# +# CONFIG_I2C_ALI1535 is not set +# CONFIG_I2C_ALI1563 is not set +# CONFIG_I2C_ALI15X3 is not set +# CONFIG_I2C_AMD756 is not set +# CONFIG_I2C_AMD8111 is not set +# CONFIG_I2C_AMD_MP2 is not set +CONFIG_I2C_I801=y +# CONFIG_I2C_ISCH is not set +# CONFIG_I2C_ISMT is not set +CONFIG_I2C_PIIX4=m +# CONFIG_I2C_NFORCE2 is not set +# CONFIG_I2C_NVIDIA_GPU is not set +# CONFIG_I2C_SIS5595 is not set +# CONFIG_I2C_SIS630 is not set +# CONFIG_I2C_SIS96X is not set +# CONFIG_I2C_VIA is not set +# CONFIG_I2C_VIAPRO is not set + +# +# ACPI drivers +# +# CONFIG_I2C_SCMI is not set + +# +# I2C system bus drivers (mostly embedded / system-on-chip) +# +# CONFIG_I2C_DESIGNWARE_PLATFORM is not set +# CONFIG_I2C_DESIGNWARE_PCI is not set +# CONFIG_I2C_EMEV2 is not set +# CONFIG_I2C_OCORES is not set +# CONFIG_I2C_PCA_PLATFORM is not set +# CONFIG_I2C_SIMTEC is not set +# CONFIG_I2C_XILINX is not set + +# +# External I2C/SMBus adapter drivers +# +# CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_PARPORT is not set +# CONFIG_I2C_PARPORT_LIGHT is not set +# CONFIG_I2C_ROBOTFUZZ_OSIF is not set +# CONFIG_I2C_TAOS_EVM is not set +# CONFIG_I2C_TINY_USB is not set + +# +# Other I2C/SMBus bus drivers +# +# CONFIG_I2C_MLXCPLD is not set +# end of I2C Hardware Bus support + +# CONFIG_I2C_STUB is not set +# CONFIG_I2C_SLAVE is not set +# CONFIG_I2C_DEBUG_CORE is not set +# CONFIG_I2C_DEBUG_ALGO is not set +# CONFIG_I2C_DEBUG_BUS is not set +# end of I2C support + +# CONFIG_I3C is not set +# CONFIG_SPI is not set +# CONFIG_SPMI is not set +# CONFIG_HSI is not set +CONFIG_PPS=y +# CONFIG_PPS_DEBUG is not set + +# +# PPS clients support +# +# CONFIG_PPS_CLIENT_KTIMER is not set +# CONFIG_PPS_CLIENT_LDISC is not set +# CONFIG_PPS_CLIENT_PARPORT is not set +# CONFIG_PPS_CLIENT_GPIO is not set + +# +# PPS generators support +# + +# +# PTP clock support +# +CONFIG_PTP_1588_CLOCK=y + +# +# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. +# +CONFIG_PTP_1588_CLOCK_KVM=y +# end of PTP clock support + +CONFIG_PINCTRL=y +# CONFIG_DEBUG_PINCTRL is not set +# CONFIG_PINCTRL_AMD is not set +# CONFIG_PINCTRL_MCP23S08 is not set +# CONFIG_PINCTRL_SX150X is not set +# CONFIG_PINCTRL_BAYTRAIL is not set +# CONFIG_PINCTRL_CHERRYVIEW is not set +# CONFIG_PINCTRL_BROXTON is not set +# CONFIG_PINCTRL_CANNONLAKE is not set +# CONFIG_PINCTRL_CEDARFORK is not set +# CONFIG_PINCTRL_DENVERTON is not set +# CONFIG_PINCTRL_GEMINILAKE is not set +# CONFIG_PINCTRL_ICELAKE is not set +# CONFIG_PINCTRL_LEWISBURG is not set +# CONFIG_PINCTRL_SUNRISEPOINT is not set +# CONFIG_GPIOLIB is not set +# CONFIG_W1 is not set +# CONFIG_POWER_AVS is not set +# CONFIG_POWER_RESET is not set +CONFIG_POWER_SUPPLY=y +# CONFIG_POWER_SUPPLY_DEBUG is not set +CONFIG_POWER_SUPPLY_HWMON=y +# CONFIG_PDA_POWER is not set +# CONFIG_TEST_POWER is not set +# CONFIG_CHARGER_ADP5061 is not set +# CONFIG_BATTERY_DS2780 is not set +# CONFIG_BATTERY_DS2781 is not set +# CONFIG_BATTERY_DS2782 is not set +# CONFIG_BATTERY_SBS is not set +# CONFIG_CHARGER_SBS is not set +# CONFIG_BATTERY_BQ27XXX is not set +# CONFIG_BATTERY_MAX17040 is not set +# CONFIG_BATTERY_MAX17042 is not set +# CONFIG_CHARGER_MAX8903 is not set +# CONFIG_CHARGER_LP8727 is not set +# CONFIG_CHARGER_BQ2415X is not set +# CONFIG_CHARGER_SMB347 is not set +# CONFIG_BATTERY_GAUGE_LTC2941 is not set +CONFIG_HWMON=y +# CONFIG_HWMON_DEBUG_CHIP is not set + +# +# Native drivers +# +# CONFIG_SENSORS_ABITUGURU is not set +# CONFIG_SENSORS_ABITUGURU3 is not set +# CONFIG_SENSORS_AD7414 is not set +# CONFIG_SENSORS_AD7418 is not set +# CONFIG_SENSORS_ADM1021 is not set +# CONFIG_SENSORS_ADM1025 is not set +# CONFIG_SENSORS_ADM1026 is not set +# CONFIG_SENSORS_ADM1029 is not set +# CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM9240 is not set +# CONFIG_SENSORS_ADT7410 is not set +# CONFIG_SENSORS_ADT7411 is not set +# CONFIG_SENSORS_ADT7462 is not set +# CONFIG_SENSORS_ADT7470 is not set +# CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_ASC7621 is not set +# CONFIG_SENSORS_K8TEMP is not set +CONFIG_SENSORS_K10TEMP=m +# CONFIG_SENSORS_FAM15H_POWER is not set +# CONFIG_SENSORS_APPLESMC is not set +# CONFIG_SENSORS_ASB100 is not set +# CONFIG_SENSORS_ASPEED is not set +# CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_DS620 is not set +# CONFIG_SENSORS_DS1621 is not set +CONFIG_SENSORS_DELL_SMM=m +# CONFIG_SENSORS_I5K_AMB is not set +# CONFIG_SENSORS_F71805F is not set +# CONFIG_SENSORS_F71882FG is not set +# CONFIG_SENSORS_F75375S is not set +# CONFIG_SENSORS_FSCHMD is not set +# CONFIG_SENSORS_FTSTEUTATES is not set +# CONFIG_SENSORS_GL518SM is not set +# CONFIG_SENSORS_GL520SM is not set +# CONFIG_SENSORS_G760A is not set +# CONFIG_SENSORS_G762 is not set +# CONFIG_SENSORS_HIH6130 is not set +# CONFIG_SENSORS_I5500 is not set +# CONFIG_SENSORS_CORETEMP is not set +# CONFIG_SENSORS_IT87 is not set +# CONFIG_SENSORS_JC42 is not set +# CONFIG_SENSORS_POWR1220 is not set +# CONFIG_SENSORS_LINEAGE is not set +# CONFIG_SENSORS_LTC2945 is not set +# CONFIG_SENSORS_LTC2990 is not set +# CONFIG_SENSORS_LTC4151 is not set +# CONFIG_SENSORS_LTC4215 is not set +# CONFIG_SENSORS_LTC4222 is not set +# CONFIG_SENSORS_LTC4245 is not set +# CONFIG_SENSORS_LTC4260 is not set +# CONFIG_SENSORS_LTC4261 is not set +# CONFIG_SENSORS_MAX16065 is not set +# CONFIG_SENSORS_MAX1619 is not set +# CONFIG_SENSORS_MAX1668 is not set +# CONFIG_SENSORS_MAX197 is not set +# CONFIG_SENSORS_MAX6621 is not set +# CONFIG_SENSORS_MAX6639 is not set +# CONFIG_SENSORS_MAX6642 is not set +# CONFIG_SENSORS_MAX6650 is not set +# CONFIG_SENSORS_MAX6697 is not set +# CONFIG_SENSORS_MAX31790 is not set +# CONFIG_SENSORS_MCP3021 is not set +# CONFIG_SENSORS_TC654 is not set +# CONFIG_SENSORS_LM63 is not set +# CONFIG_SENSORS_LM73 is not set +# CONFIG_SENSORS_LM75 is not set +# CONFIG_SENSORS_LM77 is not set +# CONFIG_SENSORS_LM78 is not set +# CONFIG_SENSORS_LM80 is not set +# CONFIG_SENSORS_LM83 is not set +# CONFIG_SENSORS_LM85 is not set +# CONFIG_SENSORS_LM87 is not set +# CONFIG_SENSORS_LM90 is not set +# CONFIG_SENSORS_LM92 is not set +# CONFIG_SENSORS_LM93 is not set +# CONFIG_SENSORS_LM95234 is not set +# CONFIG_SENSORS_LM95241 is not set +# CONFIG_SENSORS_LM95245 is not set +# CONFIG_SENSORS_PC87360 is not set +# CONFIG_SENSORS_PC87427 is not set +# CONFIG_SENSORS_NTC_THERMISTOR is not set +# CONFIG_SENSORS_NCT6683 is not set +# CONFIG_SENSORS_NCT6775 is not set +# CONFIG_SENSORS_NCT7802 is not set +# CONFIG_SENSORS_NCT7904 is not set +# CONFIG_SENSORS_NPCM7XX is not set +# CONFIG_SENSORS_PCF8591 is not set +# CONFIG_PMBUS is not set +# CONFIG_SENSORS_SHT21 is not set +# CONFIG_SENSORS_SHT3x is not set +# CONFIG_SENSORS_SHTC1 is not set +# CONFIG_SENSORS_SIS5595 is not set +# CONFIG_SENSORS_DME1737 is not set +# CONFIG_SENSORS_EMC1403 is not set +# CONFIG_SENSORS_EMC2103 is not set +# CONFIG_SENSORS_EMC6W201 is not set +# CONFIG_SENSORS_SMSC47M1 is not set +# CONFIG_SENSORS_SMSC47M192 is not set +# CONFIG_SENSORS_SMSC47B397 is not set +# CONFIG_SENSORS_SCH5627 is not set +# CONFIG_SENSORS_SCH5636 is not set +# CONFIG_SENSORS_STTS751 is not set +# CONFIG_SENSORS_SMM665 is not set +# CONFIG_SENSORS_ADC128D818 is not set +# CONFIG_SENSORS_ADS1015 is not set +# CONFIG_SENSORS_ADS7828 is not set +# CONFIG_SENSORS_AMC6821 is not set +# CONFIG_SENSORS_INA209 is not set +# CONFIG_SENSORS_INA2XX is not set +# CONFIG_SENSORS_INA3221 is not set +# CONFIG_SENSORS_TC74 is not set +# CONFIG_SENSORS_THMC50 is not set +# CONFIG_SENSORS_TMP102 is not set +# CONFIG_SENSORS_TMP103 is not set +# CONFIG_SENSORS_TMP108 is not set +# CONFIG_SENSORS_TMP401 is not set +# CONFIG_SENSORS_TMP421 is not set +# CONFIG_SENSORS_VIA_CPUTEMP is not set +# CONFIG_SENSORS_VIA686A is not set +# CONFIG_SENSORS_VT1211 is not set +# CONFIG_SENSORS_VT8231 is not set +# CONFIG_SENSORS_W83773G is not set +# CONFIG_SENSORS_W83781D is not set +# CONFIG_SENSORS_W83791D is not set +# CONFIG_SENSORS_W83792D is not set +# CONFIG_SENSORS_W83793 is not set +# CONFIG_SENSORS_W83795 is not set +# CONFIG_SENSORS_W83L785TS is not set +# CONFIG_SENSORS_W83L786NG is not set +# CONFIG_SENSORS_W83627HF is not set +# CONFIG_SENSORS_W83627EHF is not set +# CONFIG_SENSORS_XGENE is not set + +# +# ACPI drivers +# +# CONFIG_SENSORS_ACPI_POWER is not set +# CONFIG_SENSORS_ATK0110 is not set +CONFIG_THERMAL=y +# CONFIG_THERMAL_STATISTICS is not set +CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 +CONFIG_THERMAL_HWMON=y +CONFIG_THERMAL_WRITABLE_TRIPS=y +CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y +# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set +# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set +# CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR is not set +# CONFIG_THERMAL_GOV_FAIR_SHARE is not set +CONFIG_THERMAL_GOV_STEP_WISE=y +# CONFIG_THERMAL_GOV_BANG_BANG is not set +CONFIG_THERMAL_GOV_USER_SPACE=y +# CONFIG_THERMAL_GOV_POWER_ALLOCATOR is not set +# CONFIG_THERMAL_EMULATION is not set + +# +# Intel thermal drivers +# +# CONFIG_INTEL_POWERCLAMP is not set +CONFIG_X86_PKG_TEMP_THERMAL=m +# CONFIG_INTEL_SOC_DTS_THERMAL is not set + +# +# ACPI INT340X thermal drivers +# +# CONFIG_INT340X_THERMAL is not set +# end of ACPI INT340X thermal drivers + +# CONFIG_INTEL_PCH_THERMAL is not set +# end of Intel thermal drivers + +CONFIG_WATCHDOG=y +# CONFIG_WATCHDOG_CORE is not set +# CONFIG_WATCHDOG_NOWAYOUT is not set +CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y +CONFIG_WATCHDOG_OPEN_TIMEOUT=0 +# CONFIG_WATCHDOG_SYSFS is not set + +# +# Watchdog Pretimeout Governors +# + +# +# Watchdog Device Drivers +# +# CONFIG_SOFT_WATCHDOG is not set +# CONFIG_WDAT_WDT is not set +# CONFIG_XILINX_WATCHDOG is not set +# CONFIG_ZIIRAVE_WATCHDOG is not set +# CONFIG_CADENCE_WATCHDOG is not set +# CONFIG_DW_WATCHDOG is not set +# CONFIG_MAX63XX_WATCHDOG is not set +# CONFIG_ACQUIRE_WDT is not set +# CONFIG_ADVANTECH_WDT is not set +# CONFIG_ALIM1535_WDT is not set +# CONFIG_ALIM7101_WDT is not set +# CONFIG_EBC_C384_WDT is not set +# CONFIG_F71808E_WDT is not set +# CONFIG_SP5100_TCO is not set +# CONFIG_SBC_FITPC2_WATCHDOG is not set +# CONFIG_EUROTECH_WDT is not set +# CONFIG_IB700_WDT is not set +# CONFIG_IBMASR is not set +# CONFIG_WAFER_WDT is not set +# CONFIG_I6300ESB_WDT is not set +# CONFIG_IE6XX_WDT is not set +# CONFIG_ITCO_WDT is not set +# CONFIG_IT8712F_WDT is not set +# CONFIG_IT87_WDT is not set +# CONFIG_HP_WATCHDOG is not set +# CONFIG_SC1200_WDT is not set +# CONFIG_PC87413_WDT is not set +# CONFIG_NV_TCO is not set +# CONFIG_60XX_WDT is not set +# CONFIG_CPU5_WDT is not set +# CONFIG_SMSC_SCH311X_WDT is not set +# CONFIG_SMSC37B787_WDT is not set +# CONFIG_TQMX86_WDT is not set +# CONFIG_VIA_WDT is not set +# CONFIG_W83627HF_WDT is not set +# CONFIG_W83877F_WDT is not set +# CONFIG_W83977F_WDT is not set +# CONFIG_MACHZ_WDT is not set +# CONFIG_SBC_EPX_C3_WATCHDOG is not set +# CONFIG_NI903X_WDT is not set +# CONFIG_NIC7018_WDT is not set + +# +# PCI-based Watchdog Cards +# +# CONFIG_PCIPCWATCHDOG is not set +# CONFIG_WDTPCI is not set + +# +# USB-based Watchdog Cards +# +# CONFIG_USBPCWATCHDOG is not set +CONFIG_SSB_POSSIBLE=y +# CONFIG_SSB is not set +CONFIG_BCMA_POSSIBLE=y +# CONFIG_BCMA is not set + +# +# Multifunction device drivers +# +# CONFIG_MFD_AS3711 is not set +# CONFIG_PMIC_ADP5520 is not set +# CONFIG_MFD_BCM590XX is not set +# CONFIG_MFD_BD9571MWV is not set +# CONFIG_MFD_AXP20X_I2C is not set +# CONFIG_MFD_CROS_EC is not set +# CONFIG_MFD_MADERA is not set +# CONFIG_PMIC_DA903X is not set +# CONFIG_MFD_DA9052_I2C is not set +# CONFIG_MFD_DA9055 is not set +# CONFIG_MFD_DA9062 is not set +# CONFIG_MFD_DA9063 is not set +# CONFIG_MFD_DA9150 is not set +# CONFIG_MFD_DLN2 is not set +# CONFIG_MFD_MC13XXX_I2C is not set +# CONFIG_HTC_PASIC3 is not set +# CONFIG_MFD_INTEL_QUARK_I2C_GPIO is not set +# CONFIG_LPC_ICH is not set +# CONFIG_LPC_SCH is not set +# CONFIG_MFD_INTEL_LPSS_ACPI is not set +# CONFIG_MFD_INTEL_LPSS_PCI is not set +# CONFIG_MFD_JANZ_CMODIO is not set +# CONFIG_MFD_KEMPLD is not set +# CONFIG_MFD_88PM800 is not set +# CONFIG_MFD_88PM805 is not set +# CONFIG_MFD_88PM860X is not set +# CONFIG_MFD_MAX14577 is not set +# CONFIG_MFD_MAX77693 is not set +# CONFIG_MFD_MAX77843 is not set +# CONFIG_MFD_MAX8907 is not set +# CONFIG_MFD_MAX8925 is not set +# CONFIG_MFD_MAX8997 is not set +# CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_MT6397 is not set +# CONFIG_MFD_MENF21BMC is not set +# CONFIG_MFD_VIPERBOARD is not set +# CONFIG_MFD_RETU is not set +# CONFIG_MFD_PCF50633 is not set +# CONFIG_MFD_RDC321X is not set +# CONFIG_MFD_RT5033 is not set +# CONFIG_MFD_RC5T583 is not set +# CONFIG_MFD_SEC_CORE is not set +# CONFIG_MFD_SI476X_CORE is not set +# CONFIG_MFD_SM501 is not set +# CONFIG_MFD_SKY81452 is not set +# CONFIG_MFD_SMSC is not set +# CONFIG_ABX500_CORE is not set +# CONFIG_MFD_SYSCON is not set +# CONFIG_MFD_TI_AM335X_TSCADC is not set +# CONFIG_MFD_LP3943 is not set +# CONFIG_MFD_LP8788 is not set +# CONFIG_MFD_TI_LMU is not set +# CONFIG_MFD_PALMAS is not set +# CONFIG_TPS6105X is not set +# CONFIG_TPS6507X is not set +# CONFIG_MFD_TPS65086 is not set +# CONFIG_MFD_TPS65090 is not set +# CONFIG_MFD_TI_LP873X is not set +# CONFIG_MFD_TPS6586X is not set +# CONFIG_MFD_TPS65912_I2C is not set +# CONFIG_MFD_TPS80031 is not set +# CONFIG_TWL4030_CORE is not set +# CONFIG_TWL6040_CORE is not set +# CONFIG_MFD_WL1273_CORE is not set +# CONFIG_MFD_LM3533 is not set +# CONFIG_MFD_TQMX86 is not set +# CONFIG_MFD_VX855 is not set +# CONFIG_MFD_ARIZONA_I2C is not set +# CONFIG_MFD_WM8400 is not set +# CONFIG_MFD_WM831X_I2C is not set +# CONFIG_MFD_WM8350_I2C is not set +# CONFIG_MFD_WM8994 is not set +# end of Multifunction device drivers + +# CONFIG_REGULATOR is not set +CONFIG_RC_CORE=y +CONFIG_RC_MAP=y +# CONFIG_LIRC is not set +CONFIG_RC_DECODERS=y +CONFIG_IR_NEC_DECODER=y +CONFIG_IR_RC5_DECODER=y +CONFIG_IR_RC6_DECODER=y +CONFIG_IR_JVC_DECODER=y +CONFIG_IR_SONY_DECODER=y +CONFIG_IR_SANYO_DECODER=y +CONFIG_IR_SHARP_DECODER=y +CONFIG_IR_MCE_KBD_DECODER=y +CONFIG_IR_XMP_DECODER=y +# CONFIG_IR_IMON_DECODER is not set +# CONFIG_IR_RCMM_DECODER is not set +# CONFIG_RC_DEVICES is not set +# CONFIG_MEDIA_SUPPORT is not set + +# +# Graphics support +# +CONFIG_AGP=y +CONFIG_AGP_AMD64=y +CONFIG_AGP_INTEL=y +# CONFIG_AGP_SIS is not set +# CONFIG_AGP_VIA is not set +CONFIG_INTEL_GTT=y +CONFIG_VGA_ARB=y +CONFIG_VGA_ARB_MAX_GPUS=16 +# CONFIG_VGA_SWITCHEROO is not set +CONFIG_DRM=y +# CONFIG_DRM_DP_AUX_CHARDEV is not set +# CONFIG_DRM_DEBUG_MM is not set +# CONFIG_DRM_DEBUG_SELFTEST is not set +CONFIG_DRM_KMS_HELPER=y +CONFIG_DRM_KMS_FB_HELPER=y +CONFIG_DRM_FBDEV_EMULATION=y +CONFIG_DRM_FBDEV_OVERALLOC=100 +# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set +# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set +# CONFIG_DRM_DP_CEC is not set +CONFIG_DRM_TTM=m +CONFIG_DRM_VRAM_HELPER=m +CONFIG_DRM_SCHED=m + +# +# I2C encoder or helper chips +# +# CONFIG_DRM_I2C_CH7006 is not set +# CONFIG_DRM_I2C_SIL164 is not set +# CONFIG_DRM_I2C_NXP_TDA998X is not set +# CONFIG_DRM_I2C_NXP_TDA9950 is not set +# end of I2C encoder or helper chips + +# +# ARM devices +# +# end of ARM devices + +# CONFIG_DRM_RADEON is not set +CONFIG_DRM_AMDGPU=m +CONFIG_DRM_AMDGPU_SI=y +CONFIG_DRM_AMDGPU_CIK=y +CONFIG_DRM_AMDGPU_USERPTR=y +# CONFIG_DRM_AMDGPU_GART_DEBUGFS is not set + +# +# ACP (Audio CoProcessor) Configuration +# +# CONFIG_DRM_AMD_ACP is not set +# end of ACP (Audio CoProcessor) Configuration + +# +# Display Engine Configuration +# +CONFIG_DRM_AMD_DC=y +CONFIG_DRM_AMD_DC_DCN1_0=y +CONFIG_DRM_AMD_DC_DCN2_0=y +# CONFIG_DRM_AMD_DC_DCN2_1 is not set +CONFIG_DRM_AMD_DC_DSC_SUPPORT=y +# CONFIG_DRM_AMD_DC_HDCP is not set +# CONFIG_DEBUG_KERNEL_DC is not set +# end of Display Engine Configuration + +CONFIG_HSA_AMD=y +# CONFIG_DRM_NOUVEAU is not set +# CONFIG_DRM_I915 is not set +# CONFIG_DRM_VGEM is not set +# CONFIG_DRM_VKMS is not set +# CONFIG_DRM_VMWGFX is not set +# CONFIG_DRM_GMA500 is not set +# CONFIG_DRM_UDL is not set +CONFIG_DRM_AST=m +# CONFIG_DRM_MGAG200 is not set +# CONFIG_DRM_CIRRUS_QEMU is not set +# CONFIG_DRM_QXL is not set +# CONFIG_DRM_BOCHS is not set +CONFIG_DRM_PANEL=y + +# +# Display Panels +# +# end of Display Panels + +CONFIG_DRM_BRIDGE=y +CONFIG_DRM_PANEL_BRIDGE=y + +# +# Display Interface Bridges +# +# CONFIG_DRM_ANALOGIX_ANX78XX is not set +# end of Display Interface Bridges + +# CONFIG_DRM_ETNAVIV is not set +# CONFIG_DRM_GM12U320 is not set +# CONFIG_DRM_VBOXVIDEO is not set +# CONFIG_DRM_LEGACY is not set +CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y + +# +# Frame buffer Devices +# +CONFIG_FB_CMDLINE=y +CONFIG_FB_NOTIFY=y +CONFIG_FB=y +# CONFIG_FIRMWARE_EDID is not set +CONFIG_FB_CFB_FILLRECT=y +CONFIG_FB_CFB_COPYAREA=y +CONFIG_FB_CFB_IMAGEBLIT=y +CONFIG_FB_SYS_FILLRECT=y +CONFIG_FB_SYS_COPYAREA=y +CONFIG_FB_SYS_IMAGEBLIT=y +# CONFIG_FB_FOREIGN_ENDIAN is not set +CONFIG_FB_SYS_FOPS=y +CONFIG_FB_DEFERRED_IO=y +# CONFIG_FB_MODE_HELPERS is not set +# CONFIG_FB_TILEBLITTING is not set + +# +# Frame buffer hardware drivers +# +# CONFIG_FB_CIRRUS is not set +# CONFIG_FB_PM2 is not set +# CONFIG_FB_CYBER2000 is not set +# CONFIG_FB_ARC is not set +# CONFIG_FB_ASILIANT is not set +# CONFIG_FB_IMSTT is not set +# CONFIG_FB_VGA16 is not set +# CONFIG_FB_VESA is not set +# CONFIG_FB_EFI is not set +# CONFIG_FB_N411 is not set +# CONFIG_FB_HGA is not set +# CONFIG_FB_OPENCORES is not set +# CONFIG_FB_S1D13XXX is not set +# CONFIG_FB_NVIDIA is not set +# CONFIG_FB_RIVA is not set +# CONFIG_FB_I740 is not set +# CONFIG_FB_LE80578 is not set +# CONFIG_FB_INTEL is not set +# CONFIG_FB_MATROX is not set +# CONFIG_FB_RADEON is not set +# CONFIG_FB_ATY128 is not set +# CONFIG_FB_ATY is not set +# CONFIG_FB_S3 is not set +# CONFIG_FB_SAVAGE is not set +# CONFIG_FB_SIS is not set +# CONFIG_FB_NEOMAGIC is not set +# CONFIG_FB_KYRO is not set +# CONFIG_FB_3DFX is not set +# CONFIG_FB_VOODOO1 is not set +# CONFIG_FB_VT8623 is not set +# CONFIG_FB_TRIDENT is not set +# CONFIG_FB_ARK is not set +# CONFIG_FB_PM3 is not set +# CONFIG_FB_CARMINE is not set +# CONFIG_FB_SMSCUFX is not set +# CONFIG_FB_UDL is not set +# CONFIG_FB_IBM_GXT4500 is not set +# CONFIG_FB_VIRTUAL is not set +# CONFIG_FB_METRONOME is not set +# CONFIG_FB_MB862XX is not set +# CONFIG_FB_SIMPLE is not set +# CONFIG_FB_SM712 is not set +# end of Frame buffer Devices + +# +# Backlight & LCD device support +# +# CONFIG_LCD_CLASS_DEVICE is not set +CONFIG_BACKLIGHT_CLASS_DEVICE=y +# CONFIG_BACKLIGHT_GENERIC is not set +# CONFIG_BACKLIGHT_APPLE is not set +# CONFIG_BACKLIGHT_PM8941_WLED is not set +# CONFIG_BACKLIGHT_SAHARA is not set +# CONFIG_BACKLIGHT_ADP8860 is not set +# CONFIG_BACKLIGHT_ADP8870 is not set +# CONFIG_BACKLIGHT_LM3639 is not set +# CONFIG_BACKLIGHT_LV5207LP is not set +# CONFIG_BACKLIGHT_BD6107 is not set +# CONFIG_BACKLIGHT_ARCXCNN is not set +# end of Backlight & LCD device support + +CONFIG_HDMI=y + +# +# Console display driver support +# +CONFIG_VGA_CONSOLE=y +CONFIG_VGACON_SOFT_SCROLLBACK=y +CONFIG_VGACON_SOFT_SCROLLBACK_SIZE=64 +# CONFIG_VGACON_SOFT_SCROLLBACK_PERSISTENT_ENABLE_BY_DEFAULT is not set +CONFIG_DUMMY_CONSOLE=y +CONFIG_DUMMY_CONSOLE_COLUMNS=80 +CONFIG_DUMMY_CONSOLE_ROWS=25 +CONFIG_FRAMEBUFFER_CONSOLE=y +CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y +CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y +# CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER is not set +# end of Console display driver support + +# CONFIG_LOGO is not set +# end of Graphics support + +# CONFIG_SOUND is not set + +# +# HID support +# +CONFIG_HID=y +CONFIG_HID_BATTERY_STRENGTH=y +CONFIG_HIDRAW=y +# CONFIG_UHID is not set +CONFIG_HID_GENERIC=y + +# +# Special HID drivers +# +CONFIG_HID_A4TECH=y +# CONFIG_HID_ACCUTOUCH is not set +# CONFIG_HID_ACRUX is not set +CONFIG_HID_APPLE=y +# CONFIG_HID_APPLEIR is not set +# CONFIG_HID_ASUS is not set +# CONFIG_HID_AUREAL is not set +CONFIG_HID_BELKIN=y +# CONFIG_HID_BETOP_FF is not set +# CONFIG_HID_BIGBEN_FF is not set +CONFIG_HID_CHERRY=y +CONFIG_HID_CHICONY=y +# CONFIG_HID_CORSAIR is not set +# CONFIG_HID_COUGAR is not set +# CONFIG_HID_MACALLY is not set +# CONFIG_HID_CMEDIA is not set +CONFIG_HID_CYPRESS=y +# CONFIG_HID_DRAGONRISE is not set +# CONFIG_HID_EMS_FF is not set +# CONFIG_HID_ELAN is not set +# CONFIG_HID_ELECOM is not set +# CONFIG_HID_ELO is not set +CONFIG_HID_EZKEY=y +# CONFIG_HID_GEMBIRD is not set +# CONFIG_HID_GFRM is not set +# CONFIG_HID_HOLTEK is not set +# CONFIG_HID_GT683R is not set +# CONFIG_HID_KEYTOUCH is not set +CONFIG_HID_KYE=y +# CONFIG_HID_UCLOGIC is not set +# CONFIG_HID_WALTOP is not set +# CONFIG_HID_VIEWSONIC is not set +# CONFIG_HID_GYRATION is not set +# CONFIG_HID_ICADE is not set +# CONFIG_HID_ITE is not set +# CONFIG_HID_JABRA is not set +# CONFIG_HID_TWINHAN is not set +CONFIG_HID_KENSINGTON=y +# CONFIG_HID_LCPOWER is not set +# CONFIG_HID_LED is not set +# CONFIG_HID_LENOVO is not set +CONFIG_HID_LOGITECH=y +# CONFIG_HID_LOGITECH_DJ is not set +# CONFIG_HID_LOGITECH_HIDPP is not set +# CONFIG_LOGITECH_FF is not set +# CONFIG_LOGIRUMBLEPAD2_FF is not set +# CONFIG_LOGIG940_FF is not set +# CONFIG_LOGIWHEELS_FF is not set +# CONFIG_HID_MAGICMOUSE is not set +# CONFIG_HID_MALTRON is not set +# CONFIG_HID_MAYFLASH is not set +# CONFIG_HID_REDRAGON is not set +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +# CONFIG_HID_MULTITOUCH is not set +# CONFIG_HID_NTI is not set +# CONFIG_HID_NTRIG is not set +# CONFIG_HID_ORTEK is not set +# CONFIG_HID_PANTHERLORD is not set +# CONFIG_HID_PENMOUNT is not set +# CONFIG_HID_PETALYNX is not set +# CONFIG_HID_PICOLCD is not set +CONFIG_HID_PLANTRONICS=y +# CONFIG_HID_PRIMAX is not set +# CONFIG_HID_RETRODE is not set +# CONFIG_HID_ROCCAT is not set +# CONFIG_HID_SAITEK is not set +# CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SONY is not set +# CONFIG_HID_SPEEDLINK is not set +# CONFIG_HID_STEAM is not set +# CONFIG_HID_STEELSERIES is not set +# CONFIG_HID_SUNPLUS is not set +# CONFIG_HID_RMI is not set +# CONFIG_HID_GREENASIA is not set +# CONFIG_HID_SMARTJOYPLUS is not set +# CONFIG_HID_TIVO is not set +# CONFIG_HID_TOPSEED is not set +# CONFIG_HID_THINGM is not set +# CONFIG_HID_THRUSTMASTER is not set +# CONFIG_HID_UDRAW_PS3 is not set +# CONFIG_HID_WACOM is not set +# CONFIG_HID_WIIMOTE is not set +# CONFIG_HID_XINMO is not set +# CONFIG_HID_ZEROPLUS is not set +# CONFIG_HID_ZYDACRON is not set +# CONFIG_HID_SENSOR_HUB is not set +# CONFIG_HID_ALPS is not set +# end of Special HID drivers + +# +# USB HID support +# +CONFIG_USB_HID=y +CONFIG_HID_PID=y +CONFIG_USB_HIDDEV=y +# end of USB HID support + +# +# I2C HID support +# +# CONFIG_I2C_HID is not set +# end of I2C HID support + +# +# Intel ISH HID support +# +# CONFIG_INTEL_ISH_HID is not set +# end of Intel ISH HID support +# end of HID support + +CONFIG_USB_OHCI_LITTLE_ENDIAN=y +CONFIG_USB_SUPPORT=y +CONFIG_USB_COMMON=y +CONFIG_USB_ARCH_HAS_HCD=y +CONFIG_USB=y +CONFIG_USB_PCI=y +# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set + +# +# Miscellaneous USB options +# +CONFIG_USB_DEFAULT_PERSIST=y +# CONFIG_USB_DYNAMIC_MINORS is not set +# CONFIG_USB_OTG is not set +# CONFIG_USB_OTG_WHITELIST is not set +# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_LEDS_TRIGGER_USBPORT is not set +CONFIG_USB_AUTOSUSPEND_DELAY=2 +# CONFIG_USB_MON is not set +# CONFIG_USB_WUSB_CBAF is not set + +# +# USB Host Controller Drivers +# +# CONFIG_USB_C67X00_HCD is not set +CONFIG_USB_XHCI_HCD=y +# CONFIG_USB_XHCI_DBGCAP is not set +CONFIG_USB_XHCI_PCI=y +# CONFIG_USB_XHCI_PLATFORM is not set +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_TT_NEWSCHED=y +CONFIG_USB_EHCI_PCI=y +# CONFIG_USB_EHCI_FSL is not set +CONFIG_USB_EHCI_HCD_PLATFORM=y +# CONFIG_USB_OXU210HP_HCD is not set +# CONFIG_USB_ISP116X_HCD is not set +# CONFIG_USB_FOTG210_HCD is not set +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_HCD_PCI=y +# CONFIG_USB_OHCI_HCD_PLATFORM is not set +CONFIG_USB_UHCI_HCD=y +# CONFIG_USB_SL811_HCD is not set +# CONFIG_USB_R8A66597_HCD is not set +# CONFIG_USB_HCD_TEST_MODE is not set + +# +# USB Device Class drivers +# +# CONFIG_USB_ACM is not set +# CONFIG_USB_PRINTER is not set +# CONFIG_USB_WDM is not set +# CONFIG_USB_TMC is not set + +# +# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may +# + +# +# also be needed; see USB_STORAGE Help for more info +# +CONFIG_USB_STORAGE=y +# CONFIG_USB_STORAGE_DEBUG is not set +# CONFIG_USB_STORAGE_REALTEK is not set +# CONFIG_USB_STORAGE_DATAFAB is not set +# CONFIG_USB_STORAGE_FREECOM is not set +# CONFIG_USB_STORAGE_ISD200 is not set +# CONFIG_USB_STORAGE_USBAT is not set +# CONFIG_USB_STORAGE_SDDR09 is not set +# CONFIG_USB_STORAGE_SDDR55 is not set +# CONFIG_USB_STORAGE_JUMPSHOT is not set +# CONFIG_USB_STORAGE_ALAUDA is not set +# CONFIG_USB_STORAGE_ONETOUCH is not set +# CONFIG_USB_STORAGE_KARMA is not set +# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set +# CONFIG_USB_STORAGE_ENE_UB6250 is not set +# CONFIG_USB_UAS is not set + +# +# USB Imaging devices +# +# CONFIG_USB_MDC800 is not set +# CONFIG_USB_MICROTEK is not set +# CONFIG_USBIP_CORE is not set +# CONFIG_USB_MUSB_HDRC is not set +# CONFIG_USB_DWC3 is not set +# CONFIG_USB_DWC2 is not set +# CONFIG_USB_CHIPIDEA is not set +# CONFIG_USB_ISP1760 is not set + +# +# USB port drivers +# +# CONFIG_USB_USS720 is not set +# CONFIG_USB_SERIAL is not set + +# +# USB Miscellaneous drivers +# +# CONFIG_USB_EMI62 is not set +# CONFIG_USB_EMI26 is not set +# CONFIG_USB_ADUTUX is not set +# CONFIG_USB_SEVSEG is not set +# CONFIG_USB_RIO500 is not set +# CONFIG_USB_LEGOTOWER is not set +# CONFIG_USB_LCD is not set +# CONFIG_USB_CYPRESS_CY7C63 is not set +# CONFIG_USB_CYTHERM is not set +# CONFIG_USB_IDMOUSE is not set +# CONFIG_USB_FTDI_ELAN is not set +# CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_USB_SISUSBVGA is not set +# CONFIG_USB_LD is not set +# CONFIG_USB_TRANCEVIBRATOR is not set +# CONFIG_USB_IOWARRIOR is not set +# CONFIG_USB_TEST is not set +# CONFIG_USB_EHSET_TEST_FIXTURE is not set +# CONFIG_USB_ISIGHTFW is not set +# CONFIG_USB_YUREX is not set +# CONFIG_USB_EZUSB_FX2 is not set +# CONFIG_USB_HUB_USB251XB is not set +# CONFIG_USB_HSIC_USB3503 is not set +# CONFIG_USB_HSIC_USB4604 is not set +# CONFIG_USB_LINK_LAYER_TEST is not set + +# +# USB Physical Layer drivers +# +# CONFIG_NOP_USB_XCEIV is not set +# CONFIG_USB_ISP1301 is not set +# end of USB Physical Layer drivers + +# CONFIG_USB_GADGET is not set +# CONFIG_TYPEC is not set +# CONFIG_USB_ROLE_SWITCH is not set +# CONFIG_USB_LED_TRIG is not set +# CONFIG_USB_ULPI_BUS is not set +# CONFIG_UWB is not set +# CONFIG_MMC is not set +# CONFIG_MEMSTICK is not set +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +# CONFIG_LEDS_CLASS_FLASH is not set +# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set + +# +# LED drivers +# +# CONFIG_LEDS_APU is not set +# CONFIG_LEDS_LM3530 is not set +# CONFIG_LEDS_LM3532 is not set +# CONFIG_LEDS_LM3642 is not set +# CONFIG_LEDS_PCA9532 is not set +# CONFIG_LEDS_LP3944 is not set +# CONFIG_LEDS_LP5521 is not set +# CONFIG_LEDS_LP5523 is not set +# CONFIG_LEDS_LP5562 is not set +# CONFIG_LEDS_LP8501 is not set +# CONFIG_LEDS_CLEVO_MAIL is not set +# CONFIG_LEDS_PCA955X is not set +# CONFIG_LEDS_PCA963X is not set +# CONFIG_LEDS_BD2802 is not set +# CONFIG_LEDS_INTEL_SS4200 is not set +# CONFIG_LEDS_TCA6507 is not set +# CONFIG_LEDS_TLC591XX is not set +# CONFIG_LEDS_LM355x is not set + +# +# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM) +# +# CONFIG_LEDS_BLINKM is not set +# CONFIG_LEDS_MLXCPLD is not set +# CONFIG_LEDS_MLXREG is not set +# CONFIG_LEDS_USER is not set +# CONFIG_LEDS_NIC78BX is not set +# CONFIG_LEDS_TI_LMU_COMMON is not set + +# +# LED Triggers +# +CONFIG_LEDS_TRIGGERS=y +# CONFIG_LEDS_TRIGGER_TIMER is not set +# CONFIG_LEDS_TRIGGER_ONESHOT is not set +# CONFIG_LEDS_TRIGGER_DISK is not set +# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set +# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set +# CONFIG_LEDS_TRIGGER_CPU is not set +# CONFIG_LEDS_TRIGGER_ACTIVITY is not set +# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set + +# +# iptables trigger is under Netfilter config (LED target) +# +# CONFIG_LEDS_TRIGGER_TRANSIENT is not set +# CONFIG_LEDS_TRIGGER_CAMERA is not set +# CONFIG_LEDS_TRIGGER_PANIC is not set +# CONFIG_LEDS_TRIGGER_NETDEV is not set +# CONFIG_LEDS_TRIGGER_PATTERN is not set +# CONFIG_LEDS_TRIGGER_AUDIO is not set +# CONFIG_ACCESSIBILITY is not set +# CONFIG_INFINIBAND is not set +CONFIG_EDAC_ATOMIC_SCRUB=y +CONFIG_EDAC_SUPPORT=y +# CONFIG_EDAC is not set +CONFIG_RTC_LIB=y +CONFIG_RTC_MC146818_LIB=y +CONFIG_RTC_CLASS=y +# CONFIG_RTC_HCTOSYS is not set +CONFIG_RTC_SYSTOHC=y +CONFIG_RTC_SYSTOHC_DEVICE="rtc0" +# CONFIG_RTC_DEBUG is not set +CONFIG_RTC_NVMEM=y + +# +# RTC interfaces +# +CONFIG_RTC_INTF_SYSFS=y +CONFIG_RTC_INTF_PROC=y +CONFIG_RTC_INTF_DEV=y +# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set +# CONFIG_RTC_DRV_TEST is not set + +# +# I2C RTC drivers +# +# CONFIG_RTC_DRV_ABB5ZES3 is not set +# CONFIG_RTC_DRV_ABEOZ9 is not set +# CONFIG_RTC_DRV_ABX80X is not set +# CONFIG_RTC_DRV_DS1307 is not set +# CONFIG_RTC_DRV_DS1374 is not set +# CONFIG_RTC_DRV_DS1672 is not set +# CONFIG_RTC_DRV_MAX6900 is not set +# CONFIG_RTC_DRV_RS5C372 is not set +# CONFIG_RTC_DRV_ISL1208 is not set +# CONFIG_RTC_DRV_ISL12022 is not set +# CONFIG_RTC_DRV_X1205 is not set +# CONFIG_RTC_DRV_PCF8523 is not set +# CONFIG_RTC_DRV_PCF85063 is not set +# CONFIG_RTC_DRV_PCF85363 is not set +# CONFIG_RTC_DRV_PCF8563 is not set +# CONFIG_RTC_DRV_PCF8583 is not set +# CONFIG_RTC_DRV_M41T80 is not set +# CONFIG_RTC_DRV_BD70528 is not set +# CONFIG_RTC_DRV_BQ32K is not set +# CONFIG_RTC_DRV_S35390A is not set +# CONFIG_RTC_DRV_FM3130 is not set +# CONFIG_RTC_DRV_RX8010 is not set +# CONFIG_RTC_DRV_RX8581 is not set +# CONFIG_RTC_DRV_RX8025 is not set +# CONFIG_RTC_DRV_EM3027 is not set +# CONFIG_RTC_DRV_RV3028 is not set +# CONFIG_RTC_DRV_RV8803 is not set +# CONFIG_RTC_DRV_SD3078 is not set + +# +# SPI RTC drivers +# +CONFIG_RTC_I2C_AND_SPI=y + +# +# SPI and I2C RTC drivers +# +# CONFIG_RTC_DRV_DS3232 is not set +# CONFIG_RTC_DRV_PCF2127 is not set +# CONFIG_RTC_DRV_RV3029C2 is not set + +# +# Platform RTC drivers +# +CONFIG_RTC_DRV_CMOS=y +# CONFIG_RTC_DRV_DS1286 is not set +# CONFIG_RTC_DRV_DS1511 is not set +# CONFIG_RTC_DRV_DS1553 is not set +# CONFIG_RTC_DRV_DS1685_FAMILY is not set +# CONFIG_RTC_DRV_DS1742 is not set +# CONFIG_RTC_DRV_DS2404 is not set +# CONFIG_RTC_DRV_STK17TA8 is not set +# CONFIG_RTC_DRV_M48T86 is not set +# CONFIG_RTC_DRV_M48T35 is not set +# CONFIG_RTC_DRV_M48T59 is not set +# CONFIG_RTC_DRV_MSM6242 is not set +# CONFIG_RTC_DRV_BQ4802 is not set +# CONFIG_RTC_DRV_RP5C01 is not set +# CONFIG_RTC_DRV_V3020 is not set + +# +# on-CPU RTC drivers +# +# CONFIG_RTC_DRV_FTRTC010 is not set + +# +# HID Sensor RTC drivers +# +CONFIG_DMADEVICES=y +# CONFIG_DMADEVICES_DEBUG is not set + +# +# DMA Devices +# +CONFIG_DMA_ENGINE=y +CONFIG_DMA_ACPI=y +# CONFIG_ALTERA_MSGDMA is not set +# CONFIG_INTEL_IDMA64 is not set +# CONFIG_INTEL_IOATDMA is not set +# CONFIG_QCOM_HIDMA_MGMT is not set +# CONFIG_QCOM_HIDMA is not set +CONFIG_DW_DMAC_CORE=y +# CONFIG_DW_DMAC is not set +CONFIG_DW_DMAC_PCI=y +# CONFIG_DW_EDMA is not set +# CONFIG_DW_EDMA_PCIE is not set + +# +# DMA Clients +# +# CONFIG_ASYNC_TX_DMA is not set +# CONFIG_DMATEST is not set + +# +# DMABUF options +# +CONFIG_SYNC_FILE=y +# CONFIG_SW_SYNC is not set +# CONFIG_UDMABUF is not set +# CONFIG_DMABUF_SELFTESTS is not set +# end of DMABUF options + +# CONFIG_AUXDISPLAY is not set +# CONFIG_PANEL is not set +# CONFIG_UIO is not set +# CONFIG_VFIO is not set +# CONFIG_VIRT_DRIVERS is not set +CONFIG_VIRTIO_MENU=y +# CONFIG_VIRTIO_PCI is not set +# CONFIG_VIRTIO_MMIO is not set + +# +# Microsoft Hyper-V guest support +# +# CONFIG_HYPERV is not set +# end of Microsoft Hyper-V guest support + +# CONFIG_STAGING is not set +# CONFIG_X86_PLATFORM_DEVICES is not set +CONFIG_PMC_ATOM=y +# CONFIG_CHROME_PLATFORMS is not set +# CONFIG_MELLANOX_PLATFORM is not set +CONFIG_CLKDEV_LOOKUP=y +CONFIG_HAVE_CLK_PREPARE=y +CONFIG_COMMON_CLK=y + +# +# Common Clock Framework +# +# CONFIG_COMMON_CLK_MAX9485 is not set +# CONFIG_COMMON_CLK_SI5341 is not set +# CONFIG_COMMON_CLK_SI5351 is not set +# CONFIG_COMMON_CLK_SI544 is not set +# CONFIG_COMMON_CLK_CDCE706 is not set +# CONFIG_COMMON_CLK_CS2000_CP is not set +# end of Common Clock Framework + +# CONFIG_HWSPINLOCK is not set + +# +# Clock Source drivers +# +CONFIG_CLKEVT_I8253=y +CONFIG_I8253_LOCK=y +CONFIG_CLKBLD_I8253=y +# end of Clock Source drivers + +CONFIG_MAILBOX=y +CONFIG_PCC=y +# CONFIG_ALTERA_MBOX is not set +CONFIG_IOMMU_IOVA=y +CONFIG_IOMMU_API=y +CONFIG_IOMMU_SUPPORT=y + +# +# Generic IOMMU Pagetable Support +# +# end of Generic IOMMU Pagetable Support + +# CONFIG_IOMMU_DEBUGFS is not set +# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set +CONFIG_AMD_IOMMU=y +CONFIG_AMD_IOMMU_V2=m +# CONFIG_INTEL_IOMMU is not set +# CONFIG_IRQ_REMAP is not set + +# +# Remoteproc drivers +# +# CONFIG_REMOTEPROC is not set +# end of Remoteproc drivers + +# +# Rpmsg drivers +# +# CONFIG_RPMSG_QCOM_GLINK_RPM is not set +# CONFIG_RPMSG_VIRTIO is not set +# end of Rpmsg drivers + +# CONFIG_SOUNDWIRE is not set + +# +# SOC (System On Chip) specific Drivers +# + +# +# Amlogic SoC drivers +# +# end of Amlogic SoC drivers + +# +# Aspeed SoC drivers +# +# end of Aspeed SoC drivers + +# +# Broadcom SoC drivers +# +# end of Broadcom SoC drivers + +# +# NXP/Freescale QorIQ SoC drivers +# +# end of NXP/Freescale QorIQ SoC drivers + +# +# i.MX SoC drivers +# +# end of i.MX SoC drivers + +# +# IXP4xx SoC drivers +# +# CONFIG_IXP4XX_QMGR is not set +# CONFIG_IXP4XX_NPE is not set +# end of IXP4xx SoC drivers + +# +# Qualcomm SoC drivers +# +# end of Qualcomm SoC drivers + +# CONFIG_SOC_TI is not set + +# +# Xilinx SoC drivers +# +# CONFIG_XILINX_VCU is not set +# end of Xilinx SoC drivers +# end of SOC (System On Chip) specific Drivers + +# CONFIG_PM_DEVFREQ is not set +# CONFIG_EXTCON is not set +# CONFIG_MEMORY is not set +# CONFIG_IIO is not set +# CONFIG_NTB is not set +# CONFIG_VME_BUS is not set +# CONFIG_PWM is not set + +# +# IRQ chip support +# +# end of IRQ chip support + +# CONFIG_IPACK_BUS is not set +# CONFIG_RESET_CONTROLLER is not set + +# +# PHY Subsystem +# +# CONFIG_GENERIC_PHY is not set +# CONFIG_BCM_KONA_USB2_PHY is not set +# CONFIG_PHY_PXA_28NM_HSIC is not set +# CONFIG_PHY_PXA_28NM_USB2 is not set +# end of PHY Subsystem + +# CONFIG_POWERCAP is not set +# CONFIG_MCB is not set + +# +# Performance monitor support +# +# end of Performance monitor support + +CONFIG_RAS=y +# CONFIG_RAS_CEC is not set +# CONFIG_THUNDERBOLT is not set + +# +# Android +# +# CONFIG_ANDROID is not set +# end of Android + +# CONFIG_LIBNVDIMM is not set +CONFIG_DAX=y +# CONFIG_DEV_DAX is not set +CONFIG_NVMEM=y +CONFIG_NVMEM_SYSFS=y + +# +# HW tracing support +# +# CONFIG_STM is not set +# CONFIG_INTEL_TH is not set +# end of HW tracing support + +# CONFIG_FPGA is not set +# CONFIG_UNISYS_VISORBUS is not set +# CONFIG_SIOX is not set +# CONFIG_SLIMBUS is not set +# CONFIG_INTERCONNECT is not set +# CONFIG_COUNTER is not set +# end of Device Drivers + +# +# File systems +# +CONFIG_DCACHE_WORD_ACCESS=y +CONFIG_VALIDATE_FS_PARSER=y +CONFIG_FS_IOMAP=y +# CONFIG_EXT2_FS is not set +# CONFIG_EXT3_FS is not set +CONFIG_EXT4_FS=y +CONFIG_EXT4_USE_FOR_EXT2=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +# CONFIG_EXT4_DEBUG is not set +CONFIG_JBD2=y +# CONFIG_JBD2_DEBUG is not set +CONFIG_FS_MBCACHE=y +# CONFIG_REISERFS_FS is not set +# CONFIG_JFS_FS is not set +CONFIG_XFS_FS=y +CONFIG_XFS_QUOTA=y +CONFIG_XFS_POSIX_ACL=y +CONFIG_XFS_RT=y +# CONFIG_XFS_ONLINE_SCRUB is not set +CONFIG_XFS_WARN=y +# CONFIG_XFS_DEBUG is not set +# CONFIG_GFS2_FS is not set +# CONFIG_OCFS2_FS is not set +# CONFIG_BTRFS_FS is not set +# CONFIG_NILFS2_FS is not set +# CONFIG_F2FS_FS is not set +# CONFIG_FS_DAX is not set +CONFIG_FS_POSIX_ACL=y +CONFIG_EXPORTFS=y +# CONFIG_EXPORTFS_BLOCK_OPS is not set +CONFIG_FILE_LOCKING=y +CONFIG_MANDATORY_FILE_LOCKING=y +# CONFIG_FS_ENCRYPTION is not set +CONFIG_FSNOTIFY=y +CONFIG_DNOTIFY=y +CONFIG_INOTIFY_USER=y +# CONFIG_FANOTIFY is not set +CONFIG_QUOTA=y +CONFIG_QUOTA_NETLINK_INTERFACE=y +# CONFIG_PRINT_QUOTA_WARNING is not set +# CONFIG_QUOTA_DEBUG is not set +CONFIG_QUOTA_TREE=y +# CONFIG_QFMT_V1 is not set +CONFIG_QFMT_V2=y +CONFIG_QUOTACTL=y +CONFIG_QUOTACTL_COMPAT=y +CONFIG_AUTOFS4_FS=y +CONFIG_AUTOFS_FS=y +CONFIG_FUSE_FS=m +CONFIG_CUSE=m +CONFIG_OVERLAY_FS=y +# CONFIG_OVERLAY_FS_REDIRECT_DIR is not set +CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y +# CONFIG_OVERLAY_FS_INDEX is not set +# CONFIG_OVERLAY_FS_XINO_AUTO is not set +# CONFIG_OVERLAY_FS_METACOPY is not set + +# +# Caches +# +CONFIG_FSCACHE=y +# CONFIG_FSCACHE_STATS is not set +# CONFIG_FSCACHE_HISTOGRAM is not set +# CONFIG_FSCACHE_DEBUG is not set +# CONFIG_FSCACHE_OBJECT_LIST is not set +# CONFIG_CACHEFILES is not set +# end of Caches + +# +# CD-ROM/DVD Filesystems +# +CONFIG_ISO9660_FS=y +CONFIG_JOLIET=y +CONFIG_ZISOFS=y +# CONFIG_UDF_FS is not set +# end of CD-ROM/DVD Filesystems + +# +# DOS/FAT/NT Filesystems +# +CONFIG_FAT_FS=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_FAT_DEFAULT_CODEPAGE=437 +CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" +# CONFIG_FAT_DEFAULT_UTF8 is not set +CONFIG_NTFS_FS=y +# CONFIG_NTFS_DEBUG is not set +CONFIG_NTFS_RW=y +# end of DOS/FAT/NT Filesystems + +# +# Pseudo filesystems +# +CONFIG_PROC_FS=y +CONFIG_PROC_KCORE=y +CONFIG_PROC_VMCORE=y +# CONFIG_PROC_VMCORE_DEVICE_DUMP is not set +CONFIG_PROC_SYSCTL=y +CONFIG_PROC_PAGE_MONITOR=y +CONFIG_PROC_CHILDREN=y +CONFIG_PROC_PID_ARCH_STATUS=y +CONFIG_KERNFS=y +CONFIG_SYSFS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_TMPFS_XATTR=y +CONFIG_HUGETLBFS=y +CONFIG_HUGETLB_PAGE=y +CONFIG_MEMFD_CREATE=y +CONFIG_ARCH_HAS_GIGANTIC_PAGE=y +CONFIG_CONFIGFS_FS=y +# CONFIG_EFIVAR_FS is not set +# end of Pseudo filesystems + +CONFIG_MISC_FILESYSTEMS=y +# CONFIG_ORANGEFS_FS is not set +# CONFIG_ADFS_FS is not set +# CONFIG_AFFS_FS is not set +# CONFIG_ECRYPT_FS is not set +# CONFIG_HFS_FS is not set +# CONFIG_HFSPLUS_FS is not set +# CONFIG_BEFS_FS is not set +# CONFIG_BFS_FS is not set +# CONFIG_EFS_FS is not set +# CONFIG_CRAMFS is not set +# CONFIG_SQUASHFS is not set +# CONFIG_VXFS_FS is not set +# CONFIG_MINIX_FS is not set +# CONFIG_OMFS_FS is not set +# CONFIG_HPFS_FS is not set +# CONFIG_QNX4FS_FS is not set +# CONFIG_QNX6FS_FS is not set +# CONFIG_ROMFS_FS is not set +CONFIG_PSTORE=y +CONFIG_PSTORE_DEFLATE_COMPRESS=y +# CONFIG_PSTORE_LZO_COMPRESS is not set +# CONFIG_PSTORE_LZ4_COMPRESS is not set +# CONFIG_PSTORE_LZ4HC_COMPRESS is not set +# CONFIG_PSTORE_842_COMPRESS is not set +# CONFIG_PSTORE_ZSTD_COMPRESS is not set +CONFIG_PSTORE_COMPRESS=y +CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y +CONFIG_PSTORE_COMPRESS_DEFAULT="deflate" +# CONFIG_PSTORE_CONSOLE is not set +# CONFIG_PSTORE_PMSG is not set +# CONFIG_PSTORE_FTRACE is not set +# CONFIG_PSTORE_RAM is not set +# CONFIG_SYSV_FS is not set +# CONFIG_UFS_FS is not set +CONFIG_NETWORK_FILESYSTEMS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V2=y +CONFIG_NFS_V3=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +# CONFIG_NFS_SWAP is not set +# CONFIG_NFS_V4_1 is not set +CONFIG_ROOT_NFS=y +# CONFIG_NFS_FSCACHE is not set +# CONFIG_NFS_USE_LEGACY_DNS is not set +CONFIG_NFS_USE_KERNEL_DNS=y +# CONFIG_NFSD is not set +CONFIG_GRACE_PERIOD=y +CONFIG_LOCKD=y +CONFIG_LOCKD_V4=y +CONFIG_NFS_ACL_SUPPORT=y +CONFIG_NFS_COMMON=y +CONFIG_SUNRPC=y +CONFIG_SUNRPC_GSS=y +# CONFIG_SUNRPC_DEBUG is not set +# CONFIG_CEPH_FS is not set +CONFIG_CIFS=y +# CONFIG_CIFS_STATS2 is not set +CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y +# CONFIG_CIFS_WEAK_PW_HASH is not set +# CONFIG_CIFS_UPCALL is not set +# CONFIG_CIFS_XATTR is not set +CONFIG_CIFS_DEBUG=y +# CONFIG_CIFS_DEBUG2 is not set +# CONFIG_CIFS_DEBUG_DUMP_KEYS is not set +# CONFIG_CIFS_DFS_UPCALL is not set +CONFIG_CIFS_FSCACHE=y +# CONFIG_CODA_FS is not set +# CONFIG_AFS_FS is not set +CONFIG_NLS=y +CONFIG_NLS_DEFAULT="utf8" +CONFIG_NLS_CODEPAGE_437=y +# CONFIG_NLS_CODEPAGE_737 is not set +# CONFIG_NLS_CODEPAGE_775 is not set +# CONFIG_NLS_CODEPAGE_850 is not set +# CONFIG_NLS_CODEPAGE_852 is not set +# CONFIG_NLS_CODEPAGE_855 is not set +# CONFIG_NLS_CODEPAGE_857 is not set +# CONFIG_NLS_CODEPAGE_860 is not set +# CONFIG_NLS_CODEPAGE_861 is not set +# CONFIG_NLS_CODEPAGE_862 is not set +# CONFIG_NLS_CODEPAGE_863 is not set +# CONFIG_NLS_CODEPAGE_864 is not set +# CONFIG_NLS_CODEPAGE_865 is not set +# CONFIG_NLS_CODEPAGE_866 is not set +# CONFIG_NLS_CODEPAGE_869 is not set +# CONFIG_NLS_CODEPAGE_936 is not set +# CONFIG_NLS_CODEPAGE_950 is not set +# CONFIG_NLS_CODEPAGE_932 is not set +# CONFIG_NLS_CODEPAGE_949 is not set +# CONFIG_NLS_CODEPAGE_874 is not set +# CONFIG_NLS_ISO8859_8 is not set +# CONFIG_NLS_CODEPAGE_1250 is not set +# CONFIG_NLS_CODEPAGE_1251 is not set +CONFIG_NLS_ASCII=y +CONFIG_NLS_ISO8859_1=y +# CONFIG_NLS_ISO8859_2 is not set +# CONFIG_NLS_ISO8859_3 is not set +# CONFIG_NLS_ISO8859_4 is not set +# CONFIG_NLS_ISO8859_5 is not set +# CONFIG_NLS_ISO8859_6 is not set +# CONFIG_NLS_ISO8859_7 is not set +# CONFIG_NLS_ISO8859_9 is not set +# CONFIG_NLS_ISO8859_13 is not set +# CONFIG_NLS_ISO8859_14 is not set +# CONFIG_NLS_ISO8859_15 is not set +# CONFIG_NLS_KOI8_R is not set +# CONFIG_NLS_KOI8_U is not set +# CONFIG_NLS_MAC_ROMAN is not set +# CONFIG_NLS_MAC_CELTIC is not set +# CONFIG_NLS_MAC_CENTEURO is not set +# CONFIG_NLS_MAC_CROATIAN is not set +# CONFIG_NLS_MAC_CYRILLIC is not set +# CONFIG_NLS_MAC_GAELIC is not set +# CONFIG_NLS_MAC_GREEK is not set +# CONFIG_NLS_MAC_ICELAND is not set +# CONFIG_NLS_MAC_INUIT is not set +# CONFIG_NLS_MAC_ROMANIAN is not set +# CONFIG_NLS_MAC_TURKISH is not set +CONFIG_NLS_UTF8=y +# CONFIG_DLM is not set +# CONFIG_UNICODE is not set +# end of File systems + +# +# Security options +# +CONFIG_KEYS=y +CONFIG_KEYS_COMPAT=y +# CONFIG_KEYS_REQUEST_CACHE is not set +# CONFIG_PERSISTENT_KEYRINGS is not set +# CONFIG_BIG_KEYS is not set +# CONFIG_ENCRYPTED_KEYS is not set +# CONFIG_KEY_DH_OPERATIONS is not set +# CONFIG_SECURITY_DMESG_RESTRICT is not set +CONFIG_SECURITY=y +CONFIG_SECURITY_WRITABLE_HOOKS=y +# CONFIG_SECURITYFS is not set +CONFIG_SECURITY_NETWORK=y +CONFIG_PAGE_TABLE_ISOLATION=y +# CONFIG_SECURITY_NETWORK_XFRM is not set +# CONFIG_SECURITY_PATH is not set +CONFIG_LSM_MMAP_MIN_ADDR=65536 +CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y +# CONFIG_HARDENED_USERCOPY is not set +# CONFIG_FORTIFY_SOURCE is not set +# CONFIG_STATIC_USERMODEHELPER is not set +CONFIG_SECURITY_SELINUX=y +CONFIG_SECURITY_SELINUX_BOOTPARAM=y +CONFIG_SECURITY_SELINUX_DISABLE=y +CONFIG_SECURITY_SELINUX_DEVELOP=y +CONFIG_SECURITY_SELINUX_AVC_STATS=y +CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=1 +# CONFIG_SECURITY_SMACK is not set +# CONFIG_SECURITY_TOMOYO is not set +# CONFIG_SECURITY_APPARMOR is not set +# CONFIG_SECURITY_LOADPIN is not set +# CONFIG_SECURITY_YAMA is not set +# CONFIG_SECURITY_SAFESETID is not set +CONFIG_INTEGRITY=y +# CONFIG_INTEGRITY_SIGNATURE is not set +CONFIG_INTEGRITY_AUDIT=y +# CONFIG_IMA is not set +# CONFIG_EVM is not set +CONFIG_DEFAULT_SECURITY_SELINUX=y +# CONFIG_DEFAULT_SECURITY_DAC is not set +CONFIG_LSM="yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor" + +# +# Kernel hardening options +# + +# +# Memory initialization +# +CONFIG_INIT_STACK_NONE=y +# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set +# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set +# end of Memory initialization +# end of Kernel hardening options +# end of Security options + +CONFIG_CRYPTO=y + +# +# Crypto core or helper +# +CONFIG_CRYPTO_ALGAPI=y +CONFIG_CRYPTO_ALGAPI2=y +CONFIG_CRYPTO_AEAD=y +CONFIG_CRYPTO_AEAD2=y +CONFIG_CRYPTO_BLKCIPHER=y +CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_HASH=y +CONFIG_CRYPTO_HASH2=y +CONFIG_CRYPTO_RNG=y +CONFIG_CRYPTO_RNG2=y +CONFIG_CRYPTO_RNG_DEFAULT=y +CONFIG_CRYPTO_AKCIPHER2=y +CONFIG_CRYPTO_AKCIPHER=y +CONFIG_CRYPTO_KPP2=y +CONFIG_CRYPTO_ACOMP2=y +CONFIG_CRYPTO_MANAGER=y +CONFIG_CRYPTO_MANAGER2=y +# CONFIG_CRYPTO_USER is not set +CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y +CONFIG_CRYPTO_GF128MUL=y +CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_NULL2=y +# CONFIG_CRYPTO_PCRYPT is not set +# CONFIG_CRYPTO_CRYPTD is not set +CONFIG_CRYPTO_AUTHENC=y +# CONFIG_CRYPTO_TEST is not set + +# +# Public-key cryptography +# +CONFIG_CRYPTO_RSA=y +# CONFIG_CRYPTO_DH is not set +# CONFIG_CRYPTO_ECDH is not set +# CONFIG_CRYPTO_ECRDSA is not set + +# +# Authenticated Encryption with Associated Data +# +CONFIG_CRYPTO_CCM=y +CONFIG_CRYPTO_GCM=y +# CONFIG_CRYPTO_CHACHA20POLY1305 is not set +# CONFIG_CRYPTO_AEGIS128 is not set +# CONFIG_CRYPTO_AEGIS128L is not set +# CONFIG_CRYPTO_AEGIS256 is not set +# CONFIG_CRYPTO_AEGIS128_AESNI_SSE2 is not set +# CONFIG_CRYPTO_AEGIS128L_AESNI_SSE2 is not set +# CONFIG_CRYPTO_AEGIS256_AESNI_SSE2 is not set +# CONFIG_CRYPTO_MORUS640 is not set +# CONFIG_CRYPTO_MORUS640_SSE2 is not set +# CONFIG_CRYPTO_MORUS1280 is not set +# CONFIG_CRYPTO_MORUS1280_SSE2 is not set +# CONFIG_CRYPTO_MORUS1280_AVX2 is not set +CONFIG_CRYPTO_SEQIV=y +CONFIG_CRYPTO_ECHAINIV=y + +# +# Block modes +# +CONFIG_CRYPTO_CBC=y +# CONFIG_CRYPTO_CFB is not set +CONFIG_CRYPTO_CTR=y +# CONFIG_CRYPTO_CTS is not set +CONFIG_CRYPTO_ECB=y +# CONFIG_CRYPTO_LRW is not set +# CONFIG_CRYPTO_OFB is not set +# CONFIG_CRYPTO_PCBC is not set +# CONFIG_CRYPTO_XTS is not set +# CONFIG_CRYPTO_KEYWRAP is not set +# CONFIG_CRYPTO_NHPOLY1305_SSE2 is not set +# CONFIG_CRYPTO_NHPOLY1305_AVX2 is not set +# CONFIG_CRYPTO_ADIANTUM is not set + +# +# Hash modes +# +CONFIG_CRYPTO_CMAC=y +CONFIG_CRYPTO_HMAC=y +# CONFIG_CRYPTO_XCBC is not set +# CONFIG_CRYPTO_VMAC is not set + +# +# Digest +# +CONFIG_CRYPTO_CRC32C=y +# CONFIG_CRYPTO_CRC32C_INTEL is not set +# CONFIG_CRYPTO_CRC32 is not set +# CONFIG_CRYPTO_CRC32_PCLMUL is not set +# CONFIG_CRYPTO_XXHASH is not set +CONFIG_CRYPTO_CRCT10DIF=y +# CONFIG_CRYPTO_CRCT10DIF_PCLMUL is not set +CONFIG_CRYPTO_GHASH=y +# CONFIG_CRYPTO_POLY1305 is not set +# CONFIG_CRYPTO_POLY1305_X86_64 is not set +CONFIG_CRYPTO_MD4=y +CONFIG_CRYPTO_MD5=y +# CONFIG_CRYPTO_MICHAEL_MIC is not set +# CONFIG_CRYPTO_RMD128 is not set +# CONFIG_CRYPTO_RMD160 is not set +# CONFIG_CRYPTO_RMD256 is not set +# CONFIG_CRYPTO_RMD320 is not set +CONFIG_CRYPTO_SHA1=y +# CONFIG_CRYPTO_SHA1_SSSE3 is not set +# CONFIG_CRYPTO_SHA256_SSSE3 is not set +# CONFIG_CRYPTO_SHA512_SSSE3 is not set +CONFIG_CRYPTO_SHA256=y +CONFIG_CRYPTO_SHA512=y +# CONFIG_CRYPTO_SHA3 is not set +# CONFIG_CRYPTO_SM3 is not set +# CONFIG_CRYPTO_STREEBOG is not set +# CONFIG_CRYPTO_TGR192 is not set +# CONFIG_CRYPTO_WP512 is not set +# CONFIG_CRYPTO_GHASH_CLMUL_NI_INTEL is not set + +# +# Ciphers +# +CONFIG_CRYPTO_AES=y +# CONFIG_CRYPTO_AES_TI is not set +# CONFIG_CRYPTO_AES_X86_64 is not set +# CONFIG_CRYPTO_AES_NI_INTEL is not set +# CONFIG_CRYPTO_ANUBIS is not set +CONFIG_CRYPTO_LIB_ARC4=y +CONFIG_CRYPTO_ARC4=y +# CONFIG_CRYPTO_BLOWFISH is not set +# CONFIG_CRYPTO_BLOWFISH_X86_64 is not set +# CONFIG_CRYPTO_CAMELLIA is not set +# CONFIG_CRYPTO_CAMELLIA_X86_64 is not set +# CONFIG_CRYPTO_CAMELLIA_AESNI_AVX_X86_64 is not set +# CONFIG_CRYPTO_CAMELLIA_AESNI_AVX2_X86_64 is not set +# CONFIG_CRYPTO_CAST5 is not set +# CONFIG_CRYPTO_CAST5_AVX_X86_64 is not set +# CONFIG_CRYPTO_CAST6 is not set +# CONFIG_CRYPTO_CAST6_AVX_X86_64 is not set +CONFIG_CRYPTO_DES=y +# CONFIG_CRYPTO_DES3_EDE_X86_64 is not set +# CONFIG_CRYPTO_FCRYPT is not set +# CONFIG_CRYPTO_KHAZAD is not set +# CONFIG_CRYPTO_SALSA20 is not set +# CONFIG_CRYPTO_CHACHA20 is not set +# CONFIG_CRYPTO_CHACHA20_X86_64 is not set +# CONFIG_CRYPTO_SEED is not set +# CONFIG_CRYPTO_SERPENT is not set +# CONFIG_CRYPTO_SERPENT_SSE2_X86_64 is not set +# CONFIG_CRYPTO_SERPENT_AVX_X86_64 is not set +# CONFIG_CRYPTO_SERPENT_AVX2_X86_64 is not set +# CONFIG_CRYPTO_SM4 is not set +# CONFIG_CRYPTO_TEA is not set +# CONFIG_CRYPTO_TWOFISH is not set +# CONFIG_CRYPTO_TWOFISH_X86_64 is not set +# CONFIG_CRYPTO_TWOFISH_X86_64_3WAY is not set +# CONFIG_CRYPTO_TWOFISH_AVX_X86_64 is not set + +# +# Compression +# +CONFIG_CRYPTO_DEFLATE=y +CONFIG_CRYPTO_LZO=y +# CONFIG_CRYPTO_842 is not set +# CONFIG_CRYPTO_LZ4 is not set +# CONFIG_CRYPTO_LZ4HC is not set +# CONFIG_CRYPTO_ZSTD is not set + +# +# Random Number Generation +# +# CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_DRBG_MENU=y +CONFIG_CRYPTO_DRBG_HMAC=y +# CONFIG_CRYPTO_DRBG_HASH is not set +# CONFIG_CRYPTO_DRBG_CTR is not set +CONFIG_CRYPTO_DRBG=y +CONFIG_CRYPTO_JITTERENTROPY=y +# CONFIG_CRYPTO_USER_API_HASH is not set +# CONFIG_CRYPTO_USER_API_SKCIPHER is not set +# CONFIG_CRYPTO_USER_API_RNG is not set +# CONFIG_CRYPTO_USER_API_AEAD is not set +CONFIG_CRYPTO_HASH_INFO=y +CONFIG_CRYPTO_HW=y +# CONFIG_CRYPTO_DEV_PADLOCK is not set +# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set +# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set +# CONFIG_CRYPTO_DEV_CCP is not set +# CONFIG_CRYPTO_DEV_QAT_DH895xCC is not set +# CONFIG_CRYPTO_DEV_QAT_C3XXX is not set +# CONFIG_CRYPTO_DEV_QAT_C62X is not set +# CONFIG_CRYPTO_DEV_QAT_DH895xCCVF is not set +# CONFIG_CRYPTO_DEV_QAT_C3XXXVF is not set +# CONFIG_CRYPTO_DEV_QAT_C62XVF is not set +# CONFIG_CRYPTO_DEV_NITROX_CNN55XX is not set +CONFIG_ASYMMETRIC_KEY_TYPE=y +CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y +CONFIG_X509_CERTIFICATE_PARSER=y +# CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set +CONFIG_PKCS7_MESSAGE_PARSER=y +# CONFIG_PKCS7_TEST_KEY is not set +# CONFIG_SIGNED_PE_FILE_VERIFICATION is not set + +# +# Certificates for signature checking +# +CONFIG_MODULE_SIG_KEY="certs/signing_key.pem" +CONFIG_SYSTEM_TRUSTED_KEYRING=y +CONFIG_SYSTEM_TRUSTED_KEYS="" +# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set +# CONFIG_SECONDARY_TRUSTED_KEYRING is not set +# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set +# end of Certificates for signature checking + +CONFIG_BINARY_PRINTF=y + +# +# Library routines +# +# CONFIG_PACKING is not set +CONFIG_BITREVERSE=y +CONFIG_GENERIC_STRNCPY_FROM_USER=y +CONFIG_GENERIC_STRNLEN_USER=y +CONFIG_GENERIC_NET_UTILS=y +CONFIG_GENERIC_FIND_FIRST_BIT=y +# CONFIG_CORDIC is not set +CONFIG_RATIONAL=y +CONFIG_GENERIC_PCI_IOMAP=y +CONFIG_GENERIC_IOMAP=y +CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y +CONFIG_ARCH_HAS_FAST_MULTIPLIER=y +CONFIG_CRC_CCITT=y +CONFIG_CRC16=y +CONFIG_CRC_T10DIF=y +# CONFIG_CRC_ITU_T is not set +CONFIG_CRC32=y +# CONFIG_CRC32_SELFTEST is not set +CONFIG_CRC32_SLICEBY8=y +# CONFIG_CRC32_SLICEBY4 is not set +# CONFIG_CRC32_SARWATE is not set +# CONFIG_CRC32_BIT is not set +# CONFIG_CRC64 is not set +# CONFIG_CRC4 is not set +# CONFIG_CRC7 is not set +CONFIG_LIBCRC32C=y +# CONFIG_CRC8 is not set +CONFIG_XXHASH=y +# CONFIG_RANDOM32_SELFTEST is not set +CONFIG_ZLIB_INFLATE=y +CONFIG_ZLIB_DEFLATE=y +CONFIG_LZO_COMPRESS=y +CONFIG_LZO_DECOMPRESS=y +CONFIG_LZ4_DECOMPRESS=y +CONFIG_XZ_DEC=y +CONFIG_XZ_DEC_X86=y +CONFIG_XZ_DEC_POWERPC=y +CONFIG_XZ_DEC_IA64=y +CONFIG_XZ_DEC_ARM=y +CONFIG_XZ_DEC_ARMTHUMB=y +CONFIG_XZ_DEC_SPARC=y +CONFIG_XZ_DEC_BCJ=y +# CONFIG_XZ_DEC_TEST is not set +CONFIG_DECOMPRESS_GZIP=y +CONFIG_DECOMPRESS_BZIP2=y +CONFIG_DECOMPRESS_LZMA=y +CONFIG_DECOMPRESS_XZ=y +CONFIG_DECOMPRESS_LZO=y +CONFIG_DECOMPRESS_LZ4=y +CONFIG_GENERIC_ALLOCATOR=y +CONFIG_TEXTSEARCH=y +CONFIG_TEXTSEARCH_KMP=m +CONFIG_TEXTSEARCH_BM=m +CONFIG_TEXTSEARCH_FSM=m +CONFIG_INTERVAL_TREE=y +CONFIG_XARRAY_MULTI=y +CONFIG_ASSOCIATIVE_ARRAY=y +CONFIG_HAS_IOMEM=y +CONFIG_HAS_IOPORT_MAP=y +CONFIG_HAS_DMA=y +CONFIG_NEED_SG_DMA_LENGTH=y +CONFIG_NEED_DMA_MAP_STATE=y +CONFIG_ARCH_DMA_ADDR_T_64BIT=y +CONFIG_SWIOTLB=y +# CONFIG_DMA_CMA is not set +# CONFIG_DMA_API_DEBUG is not set +CONFIG_SGL_ALLOC=y +CONFIG_IOMMU_HELPER=y +CONFIG_CHECK_SIGNATURE=y +CONFIG_CPU_RMAP=y +CONFIG_DQL=y +CONFIG_GLOB=y +# CONFIG_GLOB_SELFTEST is not set +CONFIG_NLATTR=y +CONFIG_CLZ_TAB=y +# CONFIG_IRQ_POLL is not set +CONFIG_MPILIB=y +CONFIG_DIMLIB=y +CONFIG_OID_REGISTRY=y +CONFIG_UCS2_STRING=y +CONFIG_HAVE_GENERIC_VDSO=y +CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_FONT_SUPPORT=y +# CONFIG_FONTS is not set +CONFIG_FONT_8x8=y +CONFIG_FONT_8x16=y +CONFIG_SG_POOL=y +CONFIG_ARCH_HAS_PMEM_API=y +CONFIG_ARCH_HAS_UACCESS_FLUSHCACHE=y +CONFIG_ARCH_HAS_UACCESS_MCSAFE=y +CONFIG_ARCH_STACKWALK=y +CONFIG_SBITMAP=y +# CONFIG_STRING_SELFTEST is not set +# end of Library routines + +# +# Kernel hacking +# + +# +# printk and dmesg options +# +CONFIG_PRINTK_TIME=y +# CONFIG_PRINTK_CALLER is not set +CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 +CONFIG_CONSOLE_LOGLEVEL_QUIET=4 +CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 +# CONFIG_BOOT_PRINTK_DELAY is not set +CONFIG_DYNAMIC_DEBUG=y +# end of printk and dmesg options + +# +# Compile-time checks and compiler options +# +# CONFIG_DEBUG_INFO is not set +CONFIG_ENABLE_MUST_CHECK=y +CONFIG_FRAME_WARN=2048 +# CONFIG_STRIP_ASM_SYMS is not set +# CONFIG_READABLE_ASM is not set +# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_DEBUG_FS=y +# CONFIG_HEADERS_INSTALL is not set +CONFIG_OPTIMIZE_INLINING=y +# CONFIG_DEBUG_SECTION_MISMATCH is not set +CONFIG_SECTION_MISMATCH_WARN_ONLY=y +CONFIG_STACK_VALIDATION=y +# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set +# end of Compile-time checks and compiler options + +CONFIG_MAGIC_SYSRQ=y +CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 +CONFIG_MAGIC_SYSRQ_SERIAL=y +CONFIG_DEBUG_KERNEL=y +CONFIG_DEBUG_MISC=y + +# +# Memory Debugging +# +# CONFIG_PAGE_EXTENSION is not set +# CONFIG_DEBUG_PAGEALLOC is not set +# CONFIG_PAGE_OWNER is not set +# CONFIG_PAGE_POISONING is not set +# CONFIG_DEBUG_PAGE_REF is not set +CONFIG_DEBUG_RODATA_TEST=y +# CONFIG_DEBUG_OBJECTS is not set +# CONFIG_SLUB_DEBUG_ON is not set +# CONFIG_SLUB_STATS is not set +CONFIG_HAVE_DEBUG_KMEMLEAK=y +CONFIG_DEBUG_KMEMLEAK=y +CONFIG_DEBUG_KMEMLEAK_EARLY_LOG_SIZE=400 +# CONFIG_DEBUG_KMEMLEAK_TEST is not set +CONFIG_DEBUG_KMEMLEAK_DEFAULT_OFF=y +CONFIG_DEBUG_KMEMLEAK_AUTO_SCAN=y +# CONFIG_DEBUG_STACK_USAGE is not set +# CONFIG_DEBUG_VM is not set +CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y +# CONFIG_DEBUG_VIRTUAL is not set +# CONFIG_DEBUG_MEMORY_INIT is not set +# CONFIG_DEBUG_PER_CPU_MAPS is not set +CONFIG_HAVE_ARCH_KASAN=y +CONFIG_CC_HAS_KASAN_GENERIC=y +# CONFIG_KASAN is not set +CONFIG_KASAN_STACK=1 +# end of Memory Debugging + +CONFIG_ARCH_HAS_KCOV=y +CONFIG_CC_HAS_SANCOV_TRACE_PC=y +# CONFIG_KCOV is not set +CONFIG_DEBUG_SHIRQ=y + +# +# Debug Lockups and Hangs +# +CONFIG_LOCKUP_DETECTOR=y +CONFIG_SOFTLOCKUP_DETECTOR=y +# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 +CONFIG_HARDLOCKUP_DETECTOR_PERF=y +CONFIG_HARDLOCKUP_CHECK_TIMESTAMP=y +CONFIG_HARDLOCKUP_DETECTOR=y +# CONFIG_BOOTPARAM_HARDLOCKUP_PANIC is not set +CONFIG_BOOTPARAM_HARDLOCKUP_PANIC_VALUE=0 +CONFIG_DETECT_HUNG_TASK=y +CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120 +# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set +CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 +# CONFIG_WQ_WATCHDOG is not set +# end of Debug Lockups and Hangs + +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +CONFIG_PANIC_TIMEOUT=0 +CONFIG_SCHED_DEBUG=y +CONFIG_SCHED_INFO=y +CONFIG_SCHEDSTATS=y +CONFIG_SCHED_STACK_END_CHECK=y +# CONFIG_DEBUG_TIMEKEEPING is not set + +# +# Lock Debugging (spinlocks, mutexes, etc...) +# +CONFIG_LOCK_DEBUGGING_SUPPORT=y +CONFIG_PROVE_LOCKING=y +# CONFIG_LOCK_STAT is not set +CONFIG_DEBUG_RT_MUTEXES=y +CONFIG_DEBUG_SPINLOCK=y +CONFIG_DEBUG_MUTEXES=y +CONFIG_DEBUG_WW_MUTEX_SLOWPATH=y +CONFIG_DEBUG_RWSEMS=y +CONFIG_DEBUG_LOCK_ALLOC=y +CONFIG_LOCKDEP=y +# CONFIG_DEBUG_LOCKDEP is not set +CONFIG_DEBUG_ATOMIC_SLEEP=y +# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set +# CONFIG_LOCK_TORTURE_TEST is not set +# CONFIG_WW_MUTEX_SELFTEST is not set +# end of Lock Debugging (spinlocks, mutexes, etc...) + +CONFIG_TRACE_IRQFLAGS=y +CONFIG_STACKTRACE=y +# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set +# CONFIG_DEBUG_KOBJECT is not set +CONFIG_DEBUG_BUGVERBOSE=y +# CONFIG_DEBUG_LIST is not set +# CONFIG_DEBUG_PLIST is not set +# CONFIG_DEBUG_SG is not set +# CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_DEBUG_CREDENTIALS is not set + +# +# RCU Debugging +# +CONFIG_PROVE_RCU=y +# CONFIG_RCU_PERF_TEST is not set +# CONFIG_RCU_TORTURE_TEST is not set +CONFIG_RCU_CPU_STALL_TIMEOUT=60 +# CONFIG_RCU_TRACE is not set +# CONFIG_RCU_EQS_DEBUG is not set +# end of RCU Debugging + +# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set +# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set +# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set +# CONFIG_NOTIFIER_ERROR_INJECTION is not set +CONFIG_FUNCTION_ERROR_INJECTION=y +# CONFIG_FAULT_INJECTION is not set +# CONFIG_LATENCYTOP is not set +CONFIG_USER_STACKTRACE_SUPPORT=y +CONFIG_NOP_TRACER=y +CONFIG_HAVE_FUNCTION_TRACER=y +CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y +CONFIG_HAVE_DYNAMIC_FTRACE=y +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y +CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y +CONFIG_HAVE_SYSCALL_TRACEPOINTS=y +CONFIG_HAVE_FENTRY=y +CONFIG_HAVE_C_RECORDMCOUNT=y +CONFIG_TRACER_MAX_TRACE=y +CONFIG_TRACE_CLOCK=y +CONFIG_RING_BUFFER=y +CONFIG_EVENT_TRACING=y +CONFIG_CONTEXT_SWITCH_TRACER=y +CONFIG_RING_BUFFER_ALLOW_SWAP=y +CONFIG_PREEMPTIRQ_TRACEPOINTS=y +CONFIG_TRACING=y +CONFIG_GENERIC_TRACER=y +CONFIG_TRACING_SUPPORT=y +CONFIG_FTRACE=y +CONFIG_FUNCTION_TRACER=y +CONFIG_FUNCTION_GRAPH_TRACER=y +# CONFIG_PREEMPTIRQ_EVENTS is not set +# CONFIG_IRQSOFF_TRACER is not set +CONFIG_SCHED_TRACER=y +CONFIG_HWLAT_TRACER=y +CONFIG_FTRACE_SYSCALLS=y +CONFIG_TRACER_SNAPSHOT=y +# CONFIG_TRACER_SNAPSHOT_PER_CPU_SWAP is not set +CONFIG_BRANCH_PROFILE_NONE=y +# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set +# CONFIG_PROFILE_ALL_BRANCHES is not set +CONFIG_STACK_TRACER=y +CONFIG_BLK_DEV_IO_TRACE=y +CONFIG_KPROBE_EVENTS=y +# CONFIG_KPROBE_EVENTS_ON_NOTRACE is not set +CONFIG_UPROBE_EVENTS=y +CONFIG_BPF_EVENTS=y +CONFIG_DYNAMIC_EVENTS=y +CONFIG_PROBE_EVENTS=y +CONFIG_DYNAMIC_FTRACE=y +CONFIG_DYNAMIC_FTRACE_WITH_REGS=y +CONFIG_FUNCTION_PROFILER=y +# CONFIG_BPF_KPROBE_OVERRIDE is not set +CONFIG_FTRACE_MCOUNT_RECORD=y +# CONFIG_FTRACE_STARTUP_TEST is not set +CONFIG_MMIOTRACE=y +CONFIG_TRACING_MAP=y +CONFIG_HIST_TRIGGERS=y +# CONFIG_MMIOTRACE_TEST is not set +# CONFIG_TRACEPOINT_BENCHMARK is not set +# CONFIG_RING_BUFFER_BENCHMARK is not set +# CONFIG_RING_BUFFER_STARTUP_TEST is not set +# CONFIG_PREEMPTIRQ_DELAY_TEST is not set +# CONFIG_TRACE_EVAL_MAP_FILE is not set +# CONFIG_PROVIDE_OHCI1394_DMA_INIT is not set +# CONFIG_RUNTIME_TESTING_MENU is not set +CONFIG_MEMTEST=y +# CONFIG_BUG_ON_DATA_CORRUPTION is not set +# CONFIG_SAMPLES is not set +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_KGDB=y +CONFIG_KGDB_SERIAL_CONSOLE=y +# CONFIG_KGDB_TESTS is not set +CONFIG_KGDB_LOW_LEVEL_TRAP=y +CONFIG_KGDB_KDB=y +CONFIG_KDB_DEFAULT_ENABLE=0x1 +CONFIG_KDB_KEYBOARD=y +CONFIG_KDB_CONTINUE_CATASTROPHIC=0 +CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y +# CONFIG_UBSAN is not set +CONFIG_UBSAN_ALIGNMENT=y +CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y +# CONFIG_STRICT_DEVMEM is not set +CONFIG_TRACE_IRQFLAGS_SUPPORT=y +# CONFIG_X86_VERBOSE_BOOTUP is not set +CONFIG_EARLY_PRINTK=y +# CONFIG_EARLY_PRINTK_DBGP is not set +# CONFIG_EARLY_PRINTK_USB_XDBC is not set +# CONFIG_X86_PTDUMP is not set +# CONFIG_EFI_PGT_DUMP is not set +# CONFIG_DEBUG_WX is not set +CONFIG_DOUBLEFAULT=y +# CONFIG_DEBUG_TLBFLUSH is not set +# CONFIG_IOMMU_DEBUG is not set +CONFIG_HAVE_MMIOTRACE_SUPPORT=y +# CONFIG_X86_DECODER_SELFTEST is not set +# CONFIG_IO_DELAY_0X80 is not set +CONFIG_IO_DELAY_0XED=y +# CONFIG_IO_DELAY_UDELAY is not set +# CONFIG_IO_DELAY_NONE is not set +# CONFIG_DEBUG_BOOT_PARAMS is not set +# CONFIG_CPA_DEBUG is not set +# CONFIG_DEBUG_ENTRY is not set +# CONFIG_DEBUG_NMI_SELFTEST is not set +CONFIG_X86_DEBUG_FPU=y +# CONFIG_PUNIT_ATOM_DEBUG is not set +CONFIG_UNWINDER_ORC=y +# CONFIG_UNWINDER_FRAME_POINTER is not set +# CONFIG_UNWINDER_GUESS is not set +# end of Kernel hacking From c0c43d0f56c0e30cfa5e344402076f7d043b4279 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Tue, 30 Mar 2021 18:43:07 -0400 Subject: [PATCH 0003/1868] rock-dbg_defconfig: update to 5.11 and enable DEVICE_PRIVATE Update rock-dbg_defconfig for the 5.11 kernel. Enable CONFIG_DEVICE_PRIVATE, which is needed by the new HMM-based SVM memory manager. Signed-off-by: Felix Kuehling Signed-off-by: Alex Deucher --- arch/x86/configs/rock-dbg_defconfig | 711 +++++++++++++++++----------- 1 file changed, 443 insertions(+), 268 deletions(-) diff --git a/arch/x86/configs/rock-dbg_defconfig b/arch/x86/configs/rock-dbg_defconfig index 5e1de51be9553..55fa96bf27502 100644 --- a/arch/x86/configs/rock-dbg_defconfig +++ b/arch/x86/configs/rock-dbg_defconfig @@ -1,19 +1,19 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/x86 5.3.0-rc3 Kernel Configuration -# - -# -# Compiler: gcc (Ubuntu 7.4.0-1ubuntu1~18.04.1) 7.4.0 +# Linux/x86 5.11.0 Kernel Configuration # +CONFIG_CC_VERSION_TEXT="gcc (Ubuntu 7.5.0-3ubuntu1~18.04) 7.5.0" CONFIG_CC_IS_GCC=y -CONFIG_GCC_VERSION=70400 +CONFIG_GCC_VERSION=70500 +CONFIG_LD_VERSION=230000000 CONFIG_CLANG_VERSION=0 +CONFIG_LLD_VERSION=0 CONFIG_CC_CAN_LINK=y +CONFIG_CC_CAN_LINK_STATIC=y CONFIG_CC_HAS_ASM_GOTO=y -CONFIG_CC_HAS_WARN_MAYBE_UNINITIALIZED=y +CONFIG_CC_HAS_ASM_INLINE=y CONFIG_IRQ_WORK=y -CONFIG_BUILDTIME_EXTABLE_SORT=y +CONFIG_BUILDTIME_TABLE_SORT=y CONFIG_THREAD_INFO_IN_TASK=y # @@ -21,7 +21,6 @@ CONFIG_THREAD_INFO_IN_TASK=y # CONFIG_INIT_ENV_ARG_LIMIT=32 # CONFIG_COMPILE_TEST is not set -# CONFIG_HEADER_TEST is not set CONFIG_LOCALVERSION="-kfd" # CONFIG_LOCALVERSION_AUTO is not set CONFIG_BUILD_SALT="" @@ -31,18 +30,22 @@ CONFIG_HAVE_KERNEL_LZMA=y CONFIG_HAVE_KERNEL_XZ=y CONFIG_HAVE_KERNEL_LZO=y CONFIG_HAVE_KERNEL_LZ4=y +CONFIG_HAVE_KERNEL_ZSTD=y CONFIG_KERNEL_GZIP=y # CONFIG_KERNEL_BZIP2 is not set # CONFIG_KERNEL_LZMA is not set # CONFIG_KERNEL_XZ is not set # CONFIG_KERNEL_LZO is not set # CONFIG_KERNEL_LZ4 is not set +# CONFIG_KERNEL_ZSTD is not set +CONFIG_DEFAULT_INIT="" CONFIG_DEFAULT_HOSTNAME="(none)" CONFIG_SWAP=y CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y CONFIG_POSIX_MQUEUE=y CONFIG_POSIX_MQUEUE_SYSCTL=y +# CONFIG_WATCH_QUEUE is not set CONFIG_CROSS_MEMORY_ATTACH=y CONFIG_USELIB=y CONFIG_AUDIT=y @@ -57,10 +60,12 @@ CONFIG_GENERIC_IRQ_SHOW=y CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y CONFIG_GENERIC_PENDING_IRQ=y CONFIG_GENERIC_IRQ_MIGRATION=y +CONFIG_HARDIRQS_SW_RESEND=y CONFIG_IRQ_DOMAIN=y CONFIG_IRQ_DOMAIN_HIERARCHY=y CONFIG_GENERIC_MSI_IRQ=y CONFIG_GENERIC_MSI_IRQ_DOMAIN=y +CONFIG_IRQ_MSI_IOMMU=y CONFIG_GENERIC_IRQ_MATRIX_ALLOCATOR=y CONFIG_GENERIC_IRQ_RESERVATION_MODE=y CONFIG_IRQ_FORCED_THREADING=y @@ -69,7 +74,6 @@ CONFIG_SPARSE_IRQ=y # end of IRQ subsystem CONFIG_CLOCKSOURCE_WATCHDOG=y -CONFIG_ARCH_CLOCKSOURCE_DATA=y CONFIG_ARCH_CLOCKSOURCE_INIT=y CONFIG_CLOCKSOURCE_VALIDATE_LAST_CYCLE=y CONFIG_GENERIC_TIME_VSYSCALL=y @@ -77,6 +81,8 @@ CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y CONFIG_GENERIC_CLOCKEVENTS_MIN_ADJUST=y CONFIG_GENERIC_CMOS_UPDATE=y +CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK=y +CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y # # Timers subsystem @@ -119,6 +125,9 @@ CONFIG_TREE_RCU=y # CONFIG_RCU_EXPERT is not set CONFIG_SRCU=y CONFIG_TREE_SRCU=y +CONFIG_TASKS_RCU_GENERIC=y +CONFIG_TASKS_RUDE_RCU=y +CONFIG_TASKS_TRACE_RCU=y CONFIG_RCU_STALL_COMMON=y CONFIG_RCU_NEED_SEGCBLIST=y # end of RCU Subsystem @@ -134,10 +143,12 @@ CONFIG_HAVE_UNSTABLE_SCHED_CLOCK=y # # Scheduler features # +# CONFIG_UCLAMP_TASK is not set # end of Scheduler features CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y CONFIG_ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH=y +CONFIG_CC_HAS_INT128=y CONFIG_ARCH_SUPPORTS_INT128=y CONFIG_NUMA_BALANCING=y CONFIG_NUMA_BALANCING_DEFAULT_ENABLED=y @@ -145,7 +156,6 @@ CONFIG_CGROUPS=y CONFIG_PAGE_COUNTER=y CONFIG_MEMCG=y CONFIG_MEMCG_SWAP=y -# CONFIG_MEMCG_SWAP_ENABLED is not set CONFIG_MEMCG_KMEM=y CONFIG_BLK_CGROUP=y CONFIG_CGROUP_WRITEBACK=y @@ -167,6 +177,7 @@ CONFIG_CGROUP_BPF=y CONFIG_SOCK_CGROUP_DATA=y CONFIG_NAMESPACES=y CONFIG_UTS_NS=y +CONFIG_TIME_NS=y CONFIG_IPC_NS=y CONFIG_USER_NS=y CONFIG_PID_NS=y @@ -183,8 +194,11 @@ CONFIG_RD_LZMA=y CONFIG_RD_XZ=y CONFIG_RD_LZO=y CONFIG_RD_LZ4=y +CONFIG_RD_ZSTD=y +# CONFIG_BOOT_CONFIG is not set CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y # CONFIG_CC_OPTIMIZE_FOR_SIZE is not set +CONFIG_LD_ORPHAN_WARN=y CONFIG_SYSCTL=y CONFIG_HAVE_UID16=y CONFIG_SYSCTL_EXCEPTION_TRACE=y @@ -195,7 +209,6 @@ CONFIG_UID16=y CONFIG_MULTIUSER=y CONFIG_SGETMASK_SYSCALL=y CONFIG_SYSFS_SYSCALL=y -CONFIG_SYSCTL_SYSCALL=y CONFIG_FHANDLE=y CONFIG_POSIX_TIMERS=y CONFIG_PRINTK=y @@ -220,8 +233,11 @@ CONFIG_KALLSYMS_ALL=y CONFIG_KALLSYMS_ABSOLUTE_PERCPU=y CONFIG_KALLSYMS_BASE_RELATIVE=y CONFIG_BPF_SYSCALL=y +CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y +# CONFIG_BPF_PRELOAD is not set # CONFIG_USERFAULTFD is not set CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y +CONFIG_KCMP=y CONFIG_RSEQ=y # CONFIG_DEBUG_RSEQ is not set # CONFIG_EMBEDDED is not set @@ -257,7 +273,6 @@ CONFIG_X86_64=y CONFIG_X86=y CONFIG_INSTRUCTION_DECODER=y CONFIG_OUTPUT_FORMAT="elf64-x86-64" -CONFIG_ARCH_DEFCONFIG="arch/x86/configs/x86_64_defconfig" CONFIG_LOCKDEP_SUPPORT=y CONFIG_STACKTRACE_SUPPORT=y CONFIG_MMU=y @@ -281,7 +296,6 @@ CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_ARCH_WANT_GENERAL_HUGETLB=y CONFIG_ZONE_DMA32=y CONFIG_AUDIT_ARCH=y -CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y CONFIG_X86_64_SMP=y CONFIG_ARCH_SUPPORTS_UPROBES=y CONFIG_FIX_EARLYCON_MEM=y @@ -312,10 +326,11 @@ CONFIG_HYPERVISOR_GUEST=y CONFIG_PARAVIRT=y # CONFIG_PARAVIRT_DEBUG is not set CONFIG_PARAVIRT_SPINLOCKS=y +CONFIG_X86_HV_CALLBACK_VECTOR=y # CONFIG_XEN is not set CONFIG_KVM_GUEST=y +CONFIG_ARCH_CPUIDLE_HALTPOLL=y # CONFIG_PVH is not set -CONFIG_KVM_DEBUG_FS=y # CONFIG_PARAVIRT_TIME_ACCOUNTING is not set CONFIG_PARAVIRT_CLOCK=y # CONFIG_JAILHOUSE_GUEST is not set @@ -332,6 +347,8 @@ CONFIG_X86_CMPXCHG64=y CONFIG_X86_CMOV=y CONFIG_X86_MINIMUM_CPU_FAMILY=64 CONFIG_X86_DEBUGCTLMSR=y +CONFIG_IA32_FEAT_CTL=y +CONFIG_X86_VMX_FEATURE_NAMES=y CONFIG_PROCESSOR_SELECT=y CONFIG_CPU_SUP_INTEL=y CONFIG_CPU_SUP_AMD=y @@ -342,8 +359,6 @@ CONFIG_HPET_TIMER=y CONFIG_HPET_EMULATE_RTC=y CONFIG_DMI=y CONFIG_GART_IOMMU=y -CONFIG_CALGARY_IOMMU=y -CONFIG_CALGARY_IOMMU_ENABLED_BY_DEFAULT=y # CONFIG_MAXSMP is not set CONFIG_NR_CPUS_RANGE_BEGIN=2 CONFIG_NR_CPUS_RANGE_END=512 @@ -375,6 +390,7 @@ CONFIG_PERF_EVENTS_INTEL_CSTATE=y CONFIG_X86_16BIT=y CONFIG_X86_ESPFIX64=y CONFIG_X86_VSYSCALL_EMULATION=y +CONFIG_X86_IOPL_IOPERM=y CONFIG_I8K=m CONFIG_MICROCODE=y CONFIG_MICROCODE_INTEL=y @@ -385,12 +401,10 @@ CONFIG_X86_CPUID=m # CONFIG_X86_5LEVEL is not set CONFIG_X86_DIRECT_GBPAGES=y # CONFIG_X86_CPA_STATISTICS is not set -CONFIG_ARCH_HAS_MEM_ENCRYPT=y # CONFIG_AMD_MEM_ENCRYPT is not set CONFIG_NUMA=y CONFIG_AMD_NUMA=y CONFIG_X86_64_ACPI_NUMA=y -CONFIG_NODES_SPAN_OTHER_NODES=y # CONFIG_NUMA_EMU is not set CONFIG_NODES_SHIFT=6 CONFIG_ARCH_SPARSEMEM_ENABLE=y @@ -411,13 +425,15 @@ CONFIG_X86_PAT=y CONFIG_ARCH_USES_PG_UNCACHED=y CONFIG_ARCH_RANDOM=y CONFIG_X86_SMAP=y -CONFIG_X86_INTEL_UMIP=y -# CONFIG_X86_INTEL_MPX is not set +CONFIG_X86_UMIP=y CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS=y +CONFIG_X86_INTEL_TSX_MODE_OFF=y +# CONFIG_X86_INTEL_TSX_MODE_ON is not set +# CONFIG_X86_INTEL_TSX_MODE_AUTO is not set +# CONFIG_X86_SGX is not set CONFIG_EFI=y CONFIG_EFI_STUB=y CONFIG_EFI_MIXED=y -CONFIG_SECCOMP=y # CONFIG_HZ_100 is not set CONFIG_HZ_250=y # CONFIG_HZ_300 is not set @@ -427,7 +443,7 @@ CONFIG_SCHED_HRTICK=y CONFIG_KEXEC=y CONFIG_KEXEC_FILE=y CONFIG_ARCH_HAS_KEXEC_PURGATORY=y -CONFIG_KEXEC_VERIFY_SIG=y +# CONFIG_KEXEC_SIG is not set CONFIG_CRASH_DUMP=y CONFIG_KEXEC_JUMP=y CONFIG_PHYSICAL_START=0x1000000 @@ -468,6 +484,7 @@ CONFIG_SUSPEND_FREEZER=y # CONFIG_SUSPEND_SKIP_SYNC is not set CONFIG_HIBERNATE_CALLBACKS=y CONFIG_HIBERNATION=y +CONFIG_HIBERNATION_SNAPSHOT_DEV=y CONFIG_PM_STD_PARTITION="" CONFIG_PM_SLEEP=y CONFIG_PM_SLEEP_SMP=y @@ -495,7 +512,6 @@ CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y CONFIG_ACPI_SPCR_TABLE=y CONFIG_ACPI_LPIT=y CONFIG_ACPI_SLEEP=y -# CONFIG_ACPI_PROCFS_POWER is not set CONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y CONFIG_ACPI_EC_DEBUGFS=m CONFIG_ACPI_AC=y @@ -513,7 +529,6 @@ CONFIG_ACPI_PROCESSOR=y CONFIG_ACPI_HOTPLUG_CPU=y CONFIG_ACPI_PROCESSOR_AGGREGATOR=m CONFIG_ACPI_THERMAL=y -CONFIG_ACPI_NUMA=y CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y CONFIG_ACPI_TABLE_UPGRADE=y # CONFIG_ACPI_DEBUG is not set @@ -536,9 +551,9 @@ CONFIG_ACPI_APEI_PCIEAER=y CONFIG_ACPI_APEI_MEMORY_FAILURE=y CONFIG_ACPI_APEI_EINJ=m # CONFIG_ACPI_APEI_ERST_DEBUG is not set -# CONFIG_DPTF_POWER is not set -# CONFIG_PMIC_OPREGION is not set +# CONFIG_ACPI_DPTF is not set # CONFIG_ACPI_CONFIGFS is not set +# CONFIG_PMIC_OPREGION is not set CONFIG_X86_PM_TIMER=y CONFIG_SFI=y @@ -552,15 +567,13 @@ CONFIG_CPU_FREQ_STAT=y CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y # CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set # CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set # CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set CONFIG_CPU_FREQ_GOV_PERFORMANCE=y CONFIG_CPU_FREQ_GOV_POWERSAVE=y CONFIG_CPU_FREQ_GOV_USERSPACE=y CONFIG_CPU_FREQ_GOV_ONDEMAND=y CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -# CONFIG_CPU_FREQ_GOV_SCHEDUTIL is not set +CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y # # CPU frequency scaling drivers @@ -586,6 +599,8 @@ CONFIG_CPU_IDLE=y CONFIG_CPU_IDLE_GOV_LADDER=y CONFIG_CPU_IDLE_GOV_MENU=y # CONFIG_CPU_IDLE_GOV_TEO is not set +# CONFIG_CPU_IDLE_GOV_HALTPOLL is not set +CONFIG_HALTPOLL_CPUIDLE=y # end of CPU Idle # CONFIG_INTEL_IDLE is not set @@ -636,16 +651,20 @@ CONFIG_EFI_VARS_PSTORE=y CONFIG_EFI_RUNTIME_MAP=y # CONFIG_EFI_FAKE_MEMMAP is not set CONFIG_EFI_RUNTIME_WRAPPERS=y +CONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER=y # CONFIG_EFI_BOOTLOADER_CONTROL is not set # CONFIG_EFI_CAPSULE_LOADER is not set # CONFIG_EFI_TEST is not set # CONFIG_APPLE_PROPERTIES is not set # CONFIG_RESET_ATTACK_MITIGATION is not set +# CONFIG_EFI_RCI2_TABLE is not set +# CONFIG_EFI_DISABLE_PCI_DMA is not set # end of EFI (Extensible Firmware Interface) Support CONFIG_UEFI_CPER=y CONFIG_UEFI_CPER_X86=y CONFIG_EFI_EARLYCON=y +CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y # # Tegra firmware driver @@ -656,8 +675,9 @@ CONFIG_EFI_EARLYCON=y CONFIG_HAVE_KVM=y CONFIG_VIRTUALIZATION=y # CONFIG_KVM is not set -# CONFIG_VHOST_NET is not set -# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set +CONFIG_AS_AVX512=y +CONFIG_AS_SHA1_NI=y +CONFIG_AS_SHA256_NI=y # # General architecture-dependent options @@ -665,6 +685,7 @@ CONFIG_VIRTUALIZATION=y CONFIG_CRASH_CORE=y CONFIG_KEXEC_CORE=y CONFIG_HOTPLUG_SMT=y +CONFIG_GENERIC_ENTRY=y CONFIG_OPROFILE=m # CONFIG_OPROFILE_EVENT_MULTIPLEX is not set CONFIG_HAVE_OPROFILE=y @@ -672,6 +693,7 @@ CONFIG_OPROFILE_NMI_TIMER=y CONFIG_KPROBES=y CONFIG_JUMP_LABEL=y # CONFIG_STATIC_KEYS_SELFTEST is not set +# CONFIG_STATIC_CALL_SELFTEST is not set CONFIG_OPTPROBES=y CONFIG_KPROBES_ON_FTRACE=y CONFIG_UPROBES=y @@ -693,10 +715,10 @@ CONFIG_ARCH_HAS_SET_MEMORY=y CONFIG_ARCH_HAS_SET_DIRECT_MAP=y CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y CONFIG_ARCH_WANTS_DYNAMIC_TASK_STRUCT=y +CONFIG_HAVE_ASM_MODVERSIONS=y CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y CONFIG_HAVE_RSEQ=y CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y -CONFIG_HAVE_CLK=y CONFIG_HAVE_HW_BREAKPOINT=y CONFIG_HAVE_MIXED_BREAKPOINTS_REGS=y CONFIG_HAVE_USER_RETURN_NOTIFIER=y @@ -706,24 +728,29 @@ CONFIG_HAVE_PERF_REGS=y CONFIG_HAVE_PERF_USER_STACK_DUMP=y CONFIG_HAVE_ARCH_JUMP_LABEL=y CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y -CONFIG_HAVE_RCU_TABLE_FREE=y +CONFIG_MMU_GATHER_TABLE_FREE=y +CONFIG_MMU_GATHER_RCU_TABLE_FREE=y CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y CONFIG_HAVE_CMPXCHG_LOCAL=y CONFIG_HAVE_CMPXCHG_DOUBLE=y CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y CONFIG_ARCH_WANT_OLD_COMPAT_IPC=y +CONFIG_HAVE_ARCH_SECCOMP=y CONFIG_HAVE_ARCH_SECCOMP_FILTER=y +CONFIG_SECCOMP=y CONFIG_SECCOMP_FILTER=y +# CONFIG_SECCOMP_CACHE_DEBUG is not set CONFIG_HAVE_ARCH_STACKLEAK=y CONFIG_HAVE_STACKPROTECTOR=y -CONFIG_CC_HAS_STACKPROTECTOR_NONE=y CONFIG_STACKPROTECTOR=y CONFIG_STACKPROTECTOR_STRONG=y CONFIG_HAVE_ARCH_WITHIN_STACK_FRAMES=y CONFIG_HAVE_CONTEXT_TRACKING=y +CONFIG_HAVE_CONTEXT_TRACKING_OFFSTACK=y CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y +CONFIG_HAVE_MOVE_PUD=y CONFIG_HAVE_MOVE_PMD=y CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD=y @@ -732,7 +759,6 @@ CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y CONFIG_HAVE_ARCH_SOFT_DIRTY=y CONFIG_HAVE_MOD_ARCH_SPECIFIC=y CONFIG_MODULES_USE_ELF_RELA=y -CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y CONFIG_ARCH_HAS_ELF_RANDOMIZE=y CONFIG_HAVE_ARCH_MMAP_RND_BITS=y CONFIG_HAVE_EXIT_THREAD=y @@ -740,12 +766,10 @@ CONFIG_ARCH_MMAP_RND_BITS=28 CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y CONFIG_ARCH_MMAP_RND_COMPAT_BITS=8 CONFIG_HAVE_ARCH_COMPAT_MMAP_BASES=y -CONFIG_HAVE_COPY_THREAD_TLS=y CONFIG_HAVE_STACK_VALIDATION=y CONFIG_HAVE_RELIABLE_STACKTRACE=y CONFIG_OLD_SIGSUSPEND3=y CONFIG_COMPAT_OLD_SIGACTION=y -CONFIG_64BIT_TIME=y CONFIG_COMPAT_32BIT_TIME=y CONFIG_HAVE_ARCH_VMAP_STACK=y CONFIG_VMAP_STACK=y @@ -753,11 +777,14 @@ CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y CONFIG_STRICT_KERNEL_RWX=y CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y CONFIG_STRICT_MODULE_RWX=y -CONFIG_ARCH_HAS_REFCOUNT=y -# CONFIG_REFCOUNT_FULL is not set CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y CONFIG_ARCH_USE_MEMREMAP_PROT=y # CONFIG_LOCK_EVENT_COUNTS is not set +CONFIG_ARCH_HAS_MEM_ENCRYPT=y +CONFIG_HAVE_STATIC_CALL=y +CONFIG_HAVE_STATIC_CALL_INLINE=y +CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y +CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y # # GCOV-based kernel profiling @@ -766,17 +793,18 @@ CONFIG_ARCH_USE_MEMREMAP_PROT=y CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y # end of GCOV-based kernel profiling -CONFIG_PLUGIN_HOSTCC="" CONFIG_HAVE_GCC_PLUGINS=y # end of General architecture-dependent options CONFIG_RT_MUTEXES=y CONFIG_BASE_SMALL=0 +CONFIG_MODULE_SIG_FORMAT=y CONFIG_MODULES=y # CONFIG_MODULE_FORCE_LOAD is not set CONFIG_MODULE_UNLOAD=y # CONFIG_MODULE_FORCE_UNLOAD is not set CONFIG_MODVERSIONS=y +CONFIG_ASM_MODVERSIONS=y CONFIG_MODULE_SRCVERSION_ALL=y CONFIG_MODULE_SIG=y # CONFIG_MODULE_SIG_FORCE is not set @@ -788,21 +816,27 @@ CONFIG_MODULE_SIG_ALL=y CONFIG_MODULE_SIG_SHA512=y CONFIG_MODULE_SIG_HASH="sha512" # CONFIG_MODULE_COMPRESS is not set +# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set +# CONFIG_UNUSED_SYMBOLS is not set # CONFIG_TRIM_UNUSED_KSYMS is not set CONFIG_MODULES_TREE_LOOKUP=y CONFIG_BLOCK=y CONFIG_BLK_SCSI_REQUEST=y +CONFIG_BLK_CGROUP_RWSTAT=y CONFIG_BLK_DEV_BSG=y CONFIG_BLK_DEV_BSGLIB=y CONFIG_BLK_DEV_INTEGRITY=y +CONFIG_BLK_DEV_INTEGRITY_T10=y # CONFIG_BLK_DEV_ZONED is not set CONFIG_BLK_DEV_THROTTLING=y # CONFIG_BLK_DEV_THROTTLING_LOW is not set CONFIG_BLK_CMDLINE_PARSER=y # CONFIG_BLK_WBT is not set # CONFIG_BLK_CGROUP_IOLATENCY is not set +# CONFIG_BLK_CGROUP_IOCOST is not set CONFIG_BLK_DEBUG_FS=y # CONFIG_BLK_SED_OPAL is not set +# CONFIG_BLK_INLINE_ENCRYPTION is not set # # Partition Types @@ -851,6 +885,7 @@ CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y CONFIG_QUEUED_SPINLOCKS=y CONFIG_ARCH_USE_QUEUED_RWLOCKS=y CONFIG_QUEUED_RWLOCKS=y +CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y CONFIG_ARCH_HAS_SYNC_CORE_BEFORE_USERMODE=y CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y CONFIG_FREEZER=y @@ -874,12 +909,11 @@ CONFIG_SELECT_MEMORY_MODEL=y CONFIG_SPARSEMEM_MANUAL=y CONFIG_SPARSEMEM=y CONFIG_NEED_MULTIPLE_NODES=y -CONFIG_HAVE_MEMORY_PRESENT=y CONFIG_SPARSEMEM_EXTREME=y CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y CONFIG_SPARSEMEM_VMEMMAP=y -CONFIG_HAVE_MEMBLOCK_NODE_MAP=y CONFIG_HAVE_FAST_GUP=y +CONFIG_NUMA_KEEP_MEMINFO=y CONFIG_MEMORY_ISOLATION=y CONFIG_HAVE_BOOTMEM_INFO_NODE=y CONFIG_MEMORY_HOTPLUG=y @@ -888,6 +922,7 @@ CONFIG_MEMORY_HOTPLUG_SPARSE=y CONFIG_MEMORY_HOTREMOVE=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_COMPACTION=y +# CONFIG_PAGE_REPORTING is not set CONFIG_MIGRATION=y CONFIG_CONTIG_ALLOC=y CONFIG_PHYS_ADDR_T_64BIT=y @@ -904,7 +939,6 @@ CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y # CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set CONFIG_ARCH_WANTS_THP_SWAP=y CONFIG_THP_SWAP=y -CONFIG_TRANSPARENT_HUGE_PAGECACHE=y CONFIG_CLEANCACHE=y CONFIG_FRONTSWAP=y CONFIG_CMA=y @@ -913,23 +947,36 @@ CONFIG_CMA=y CONFIG_CMA_AREAS=7 CONFIG_MEM_SOFT_DIRTY=y CONFIG_ZSWAP=y +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_DEFLATE is not set +CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZO=y +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_842 is not set +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4 is not set +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4HC is not set +# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_ZSTD is not set +CONFIG_ZSWAP_COMPRESSOR_DEFAULT="lzo" +CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD=y +# CONFIG_ZSWAP_ZPOOL_DEFAULT_Z3FOLD is not set +# CONFIG_ZSWAP_ZPOOL_DEFAULT_ZSMALLOC is not set +CONFIG_ZSWAP_ZPOOL_DEFAULT="zbud" +# CONFIG_ZSWAP_DEFAULT_ON is not set CONFIG_ZPOOL=y CONFIG_ZBUD=y # CONFIG_Z3FOLD is not set CONFIG_ZSMALLOC=y -CONFIG_PGTABLE_MAPPING=y # CONFIG_ZSMALLOC_STAT is not set CONFIG_GENERIC_EARLY_IOREMAP=y # CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set # CONFIG_IDLE_PAGE_TRACKING is not set CONFIG_ARCH_HAS_PTE_DEVMAP=y CONFIG_ZONE_DEVICE=y +CONFIG_DEV_PAGEMAP_OPS=y CONFIG_HMM_MIRROR=y -# CONFIG_DEVICE_PRIVATE is not set +CONFIG_DEVICE_PRIVATE=y CONFIG_ARCH_USES_HIGH_VMA_FLAGS=y CONFIG_ARCH_HAS_PKEYS=y # CONFIG_PERCPU_STATS is not set -# CONFIG_GUP_BENCHMARK is not set +# CONFIG_GUP_TEST is not set +# CONFIG_READ_ONLY_THP_FOR_FS is not set CONFIG_ARCH_HAS_PTE_SPECIAL=y # end of Memory Management options @@ -949,10 +996,13 @@ CONFIG_UNIX_DIAG=y CONFIG_XFRM=y CONFIG_XFRM_ALGO=y CONFIG_XFRM_USER=y +# CONFIG_XFRM_USER_COMPAT is not set # CONFIG_XFRM_INTERFACE is not set # CONFIG_XFRM_SUB_POLICY is not set # CONFIG_XFRM_MIGRATE is not set # CONFIG_XFRM_STATISTICS is not set +CONFIG_XFRM_AH=y +CONFIG_XFRM_ESP=y # CONFIG_NET_KEY is not set # CONFIG_XDP_SOCKETS is not set CONFIG_INET=y @@ -1015,6 +1065,7 @@ CONFIG_IPV6=y CONFIG_INET6_AH=y CONFIG_INET6_ESP=y # CONFIG_INET6_ESP_OFFLOAD is not set +# CONFIG_INET6_ESPINTCP is not set # CONFIG_INET6_IPCOMP is not set # CONFIG_IPV6_MIP6 is not set # CONFIG_IPV6_ILA is not set @@ -1027,7 +1078,9 @@ CONFIG_IPV6_NDISC_NODETYPE=y # CONFIG_IPV6_MROUTE is not set # CONFIG_IPV6_SEG6_LWTUNNEL is not set # CONFIG_IPV6_SEG6_HMAC is not set +# CONFIG_IPV6_RPL_LWTUNNEL is not set CONFIG_NETLABEL=y +# CONFIG_MPTCP is not set CONFIG_NETWORK_SECMARK=y CONFIG_NET_PTP_CLASSIFY=y # CONFIG_NETWORK_PHY_TIMESTAMPING is not set @@ -1078,7 +1131,6 @@ CONFIG_NF_NAT_REDIRECT=y CONFIG_NF_NAT_MASQUERADE=y CONFIG_NETFILTER_SYNPROXY=m CONFIG_NF_TABLES=m -CONFIG_NF_TABLES_SET=m # CONFIG_NF_TABLES_INET is not set CONFIG_NF_TABLES_NETDEV=y # CONFIG_NFT_NUMGEN is not set @@ -1107,6 +1159,7 @@ CONFIG_NF_DUP_NETDEV=m # CONFIG_NFT_DUP_NETDEV is not set # CONFIG_NFT_FWD_NETDEV is not set # CONFIG_NFT_FIB_NETDEV is not set +# CONFIG_NFT_REJECT_NETDEV is not set # CONFIG_NF_FLOW_TABLE is not set CONFIG_NETFILTER_XTABLES=m @@ -1288,6 +1341,8 @@ CONFIG_STP=y CONFIG_BRIDGE=y CONFIG_BRIDGE_IGMP_SNOOPING=y # CONFIG_BRIDGE_VLAN_FILTERING is not set +# CONFIG_BRIDGE_MRP is not set +# CONFIG_BRIDGE_CFM is not set CONFIG_HAVE_NET_DSA=y # CONFIG_NET_DSA is not set CONFIG_VLAN_8021Q=y @@ -1336,6 +1391,7 @@ CONFIG_NET_SCHED=y # CONFIG_NET_SCH_PIE is not set # CONFIG_NET_SCH_INGRESS is not set # CONFIG_NET_SCH_PLUG is not set +# CONFIG_NET_SCH_ETS is not set # CONFIG_NET_SCH_DEFAULT is not set # @@ -1381,7 +1437,8 @@ CONFIG_NET_CLS_ACT=y # CONFIG_NET_ACT_SKBMOD is not set # CONFIG_NET_ACT_IFE is not set # CONFIG_NET_ACT_TUNNEL_KEY is not set -# CONFIG_NET_ACT_CT is not set +# CONFIG_NET_ACT_GATE is not set +# CONFIG_NET_TC_SKB_EXT is not set CONFIG_NET_SCH_FIFO=y # CONFIG_DCB is not set CONFIG_DNS_RESOLVER=y @@ -1394,6 +1451,7 @@ CONFIG_NETLINK_DIAG=y # CONFIG_HSR is not set # CONFIG_NET_SWITCHDEV is not set # CONFIG_NET_L3_MASTER_DEV is not set +# CONFIG_QRTR is not set # CONFIG_NET_NCSI is not set CONFIG_RPS=y CONFIG_RFS_ACCEL=y @@ -1432,7 +1490,6 @@ CONFIG_WIRELESS=y # CFG80211 needs to be enabled for MAC80211 # CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 -# CONFIG_WIMAX is not set CONFIG_RFKILL=y CONFIG_RFKILL_LEDS=y CONFIG_RFKILL_INPUT=y @@ -1446,6 +1503,7 @@ CONFIG_RFKILL_INPUT=y CONFIG_DST_CACHE=y CONFIG_GRO_CELLS=y # CONFIG_FAILOVER is not set +CONFIG_ETHTOOL_NETLINK=y CONFIG_HAVE_EBPF_JIT=y # @@ -1462,7 +1520,6 @@ CONFIG_PCIEAER=y # CONFIG_PCIEAER_INJECT is not set # CONFIG_PCIE_ECRC is not set CONFIG_PCIEASPM=y -CONFIG_PCIEASPM_DEBUG=y CONFIG_PCIEASPM_DEFAULT=y # CONFIG_PCIEASPM_POWERSAVE is not set # CONFIG_PCIEASPM_POWER_SUPERSAVE is not set @@ -1485,6 +1542,11 @@ CONFIG_PCI_PRI=y CONFIG_PCI_PASID=y # CONFIG_PCI_P2PDMA is not set CONFIG_PCI_LABEL=y +# CONFIG_PCIE_BUS_TUNE_OFF is not set +CONFIG_PCIE_BUS_DEFAULT=y +# CONFIG_PCIE_BUS_SAFE is not set +# CONFIG_PCIE_BUS_PERFORMANCE is not set +# CONFIG_PCIE_BUS_PEER2PEER is not set CONFIG_HOTPLUG_PCI=y # CONFIG_HOTPLUG_PCI_ACPI is not set # CONFIG_HOTPLUG_PCI_CPCI is not set @@ -1493,12 +1555,6 @@ CONFIG_HOTPLUG_PCI=y # # PCI controller drivers # - -# -# Cadence PCIe controllers support -# -# end of Cadence PCIe controllers support - # CONFIG_VMD is not set # @@ -1507,6 +1563,16 @@ CONFIG_HOTPLUG_PCI=y # CONFIG_PCIE_DW_PLAT_HOST is not set # CONFIG_PCI_MESON is not set # end of DesignWare PCI Core Support + +# +# Mobiveil PCIe Core Support +# +# end of Mobiveil PCIe Core Support + +# +# Cadence PCIe controllers support +# +# end of Cadence PCIe controllers support # end of PCI controller drivers # @@ -1559,6 +1625,7 @@ CONFIG_FW_LOADER=y CONFIG_EXTRA_FIRMWARE="" # CONFIG_FW_LOADER_USER_HELPER is not set # CONFIG_FW_LOADER_COMPRESS is not set +CONFIG_FW_CACHE=y # end of Firmware loader CONFIG_ALLOW_DEV_COREDUMP=y @@ -1568,8 +1635,6 @@ CONFIG_ALLOW_DEV_COREDUMP=y # CONFIG_TEST_ASYNC_DRIVER_PROBE is not set CONFIG_GENERIC_CPU_AUTOPROBE=y CONFIG_GENERIC_CPU_VULNERABILITIES=y -CONFIG_REGMAP=y -CONFIG_REGMAP_I2C=y CONFIG_DMA_SHARED_BUFFER=y # CONFIG_DMA_FENCE_TRACE is not set # end of Generic Driver Options @@ -1577,6 +1642,7 @@ CONFIG_DMA_SHARED_BUFFER=y # # Bus devices # +# CONFIG_MHI_BUS is not set # end of Bus devices # CONFIG_CONNECTOR is not set @@ -1627,6 +1693,7 @@ CONFIG_BLK_DEV_RAM_SIZE=16384 CONFIG_NVME_CORE=y CONFIG_BLK_DEV_NVME=y # CONFIG_NVME_MULTIPATH is not set +# CONFIG_NVME_HWMON is not set # CONFIG_NVME_FC is not set # CONFIG_NVME_TCP is not set # CONFIG_NVME_TARGET is not set @@ -1639,7 +1706,6 @@ CONFIG_BLK_DEV_NVME=y # CONFIG_DUMMY_IRQ is not set # CONFIG_IBM_ASM is not set # CONFIG_PHANTOM is not set -# CONFIG_SGI_IOC4 is not set # CONFIG_TIFM_CORE is not set # CONFIG_ICS932S401 is not set # CONFIG_ENCLOSURE_SERVICES is not set @@ -1682,53 +1748,13 @@ CONFIG_BLK_DEV_NVME=y # CONFIG_INTEL_MEI_ME is not set # CONFIG_INTEL_MEI_TXE is not set # CONFIG_VMWARE_VMCI is not set - -# -# Intel MIC & related support -# - -# -# Intel MIC Bus Driver -# -# CONFIG_INTEL_MIC_BUS is not set - -# -# SCIF Bus Driver -# -# CONFIG_SCIF_BUS is not set - -# -# VOP Bus Driver -# -# CONFIG_VOP_BUS is not set - -# -# Intel MIC Host Driver -# - -# -# Intel MIC Card Driver -# - -# -# SCIF Driver -# - -# -# Intel MIC Coprocessor State Management (COSM) Drivers -# - -# -# VOP Driver -# -# end of Intel MIC & related support - # CONFIG_GENWQE is not set # CONFIG_ECHO is not set # CONFIG_MISC_ALCOR_PCI is not set # CONFIG_MISC_RTSX_PCI is not set # CONFIG_MISC_RTSX_USB is not set # CONFIG_HABANA_AI is not set +# CONFIG_UACCE is not set # end of Misc devices CONFIG_HAVE_IDE=y @@ -1749,7 +1775,6 @@ CONFIG_SCSI_PROC_FS=y CONFIG_BLK_DEV_SD=y # CONFIG_CHR_DEV_ST is not set CONFIG_BLK_DEV_SR=y -# CONFIG_BLK_DEV_SR_VENDOR is not set CONFIG_CHR_DEV_SG=y # CONFIG_CHR_DEV_SCH is not set CONFIG_SCSI_CONSTANTS=y @@ -1772,7 +1797,10 @@ CONFIG_SCSI_ISCSI_ATTRS=y # end of SCSI device support CONFIG_ATA=y +CONFIG_SATA_HOST=y +CONFIG_PATA_TIMINGS=y CONFIG_ATA_VERBOSE_ERROR=y +CONFIG_ATA_FORCE=y CONFIG_ATA_ACPI=y # CONFIG_SATA_ZPODD is not set CONFIG_SATA_PMP=y @@ -1884,7 +1912,9 @@ CONFIG_BLK_DEV_DM=y # CONFIG_DM_THIN_PROVISIONING is not set # CONFIG_DM_CACHE is not set # CONFIG_DM_WRITECACHE is not set +# CONFIG_DM_EBS is not set # CONFIG_DM_ERA is not set +# CONFIG_DM_CLONE is not set CONFIG_DM_MIRROR=y # CONFIG_DM_LOG_USERSPACE is not set # CONFIG_DM_RAID is not set @@ -1920,6 +1950,7 @@ CONFIG_MII=y CONFIG_NET_CORE=y # CONFIG_BONDING is not set # CONFIG_DUMMY is not set +# CONFIG_WIREGUARD is not set # CONFIG_EQUALIZER is not set # CONFIG_NET_FC is not set # CONFIG_IFB is not set @@ -1929,6 +1960,7 @@ CONFIG_MACVLAN=y # CONFIG_IPVLAN is not set # CONFIG_VXLAN is not set # CONFIG_GENEVE is not set +# CONFIG_BAREUDP is not set # CONFIG_GTP is not set # CONFIG_MACSEC is not set CONFIG_NETCONSOLE=y @@ -1942,10 +1974,6 @@ CONFIG_VETH=y # CONFIG_NLMON is not set # CONFIG_ARCNET is not set -# -# CAIF transport drivers -# - # # Distributed Switch Architecture drivers # @@ -2029,8 +2057,6 @@ CONFIG_NET_VENDOR_EMULEX=y CONFIG_NET_VENDOR_EZCHIP=y CONFIG_NET_VENDOR_GOOGLE=y # CONFIG_GVE is not set -CONFIG_NET_VENDOR_HP=y -# CONFIG_HP100 is not set CONFIG_NET_VENDOR_HUAWEI=y # CONFIG_HINIC is not set CONFIG_NET_VENDOR_I825XX=y @@ -2091,10 +2117,11 @@ CONFIG_NET_VENDOR_OKI=y CONFIG_NET_VENDOR_PACKET_ENGINES=y # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set +CONFIG_NET_VENDOR_PENSANDO=y +# CONFIG_IONIC is not set CONFIG_NET_VENDOR_QLOGIC=y # CONFIG_QLA3XXX is not set # CONFIG_QLCNIC is not set -# CONFIG_QLGE is not set # CONFIG_NETXEN_NIC is not set # CONFIG_QED is not set CONFIG_NET_VENDOR_QUALCOMM=y @@ -2160,37 +2187,29 @@ CONFIG_FDDI=y # CONFIG_SKFP is not set # CONFIG_HIPPI is not set # CONFIG_NET_SB1000 is not set -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_BUS=y -# CONFIG_MDIO_BCM_UNIMAC is not set -# CONFIG_MDIO_BITBANG is not set -# CONFIG_MDIO_MSCC_MIIM is not set -# CONFIG_MDIO_THUNDER is not set CONFIG_PHYLIB=y # CONFIG_LED_TRIGGER_PHY is not set +# CONFIG_FIXED_PHY is not set # # MII PHY device drivers # CONFIG_AMD_PHY=y +# CONFIG_ADIN_PHY is not set # CONFIG_AQUANTIA_PHY is not set # CONFIG_AX88796B_PHY is not set -# CONFIG_AT803X_PHY is not set +# CONFIG_BROADCOM_PHY is not set +# CONFIG_BCM54140_PHY is not set # CONFIG_BCM7XXX_PHY is not set +# CONFIG_BCM84881_PHY is not set # CONFIG_BCM87XX_PHY is not set -# CONFIG_BROADCOM_PHY is not set # CONFIG_CICADA_PHY is not set # CONFIG_CORTINA_PHY is not set # CONFIG_DAVICOM_PHY is not set -# CONFIG_DP83822_PHY is not set -# CONFIG_DP83TC811_PHY is not set -# CONFIG_DP83848_PHY is not set -# CONFIG_DP83867_PHY is not set -# CONFIG_FIXED_PHY is not set # CONFIG_ICPLUS_PHY is not set +# CONFIG_LXT_PHY is not set # CONFIG_INTEL_XWAY_PHY is not set # CONFIG_LSI_ET1011C_PHY is not set -# CONFIG_LXT_PHY is not set # CONFIG_MARVELL_PHY is not set # CONFIG_MARVELL_10G_PHY is not set # CONFIG_MICREL_PHY is not set @@ -2206,8 +2225,32 @@ CONFIG_REALTEK_PHY=y # CONFIG_SMSC_PHY is not set # CONFIG_STE10XP is not set # CONFIG_TERANETICS_PHY is not set +# CONFIG_DP83822_PHY is not set +# CONFIG_DP83TC811_PHY is not set +# CONFIG_DP83848_PHY is not set +# CONFIG_DP83867_PHY is not set +# CONFIG_DP83869_PHY is not set # CONFIG_VITESSE_PHY is not set # CONFIG_XILINX_GMII2RGMII is not set +CONFIG_MDIO_DEVICE=y +CONFIG_MDIO_BUS=y +CONFIG_MDIO_DEVRES=y +# CONFIG_MDIO_BITBANG is not set +# CONFIG_MDIO_BCM_UNIMAC is not set +# CONFIG_MDIO_MVUSB is not set +# CONFIG_MDIO_MSCC_MIIM is not set +# CONFIG_MDIO_THUNDER is not set + +# +# MDIO Multiplexers +# + +# +# PCS device drivers +# +# CONFIG_PCS_XPCS is not set +# end of PCS device drivers + # CONFIG_PLIP is not set # CONFIG_PPP is not set # CONFIG_SLIP is not set @@ -2255,8 +2298,8 @@ CONFIG_USB_BELKIN=y # CONFIG_USB_VL600 is not set # CONFIG_USB_NET_CH9200 is not set # CONFIG_USB_NET_AQC111 is not set +# CONFIG_USB_RTL8153_ECM is not set CONFIG_WLAN=y -# CONFIG_WIRELESS_WDS is not set CONFIG_WLAN_VENDOR_ADMTEK=y CONFIG_WLAN_VENDOR_ATH=y # CONFIG_ATH_DEBUG is not set @@ -2270,6 +2313,7 @@ CONFIG_WLAN_VENDOR_INTERSIL=y # CONFIG_PRISM54 is not set CONFIG_WLAN_VENDOR_MARVELL=y CONFIG_WLAN_VENDOR_MEDIATEK=y +CONFIG_WLAN_VENDOR_MICROCHIP=y CONFIG_WLAN_VENDOR_RALINK=y CONFIG_WLAN_VENDOR_REALTEK=y CONFIG_WLAN_VENDOR_RSI=y @@ -2277,10 +2321,6 @@ CONFIG_WLAN_VENDOR_ST=y CONFIG_WLAN_VENDOR_TI=y CONFIG_WLAN_VENDOR_ZYDAS=y CONFIG_WLAN_VENDOR_QUANTENNA=y - -# -# Enable WiMAX (Networking options) to see the WiMAX drivers -# # CONFIG_WAN is not set # CONFIG_VMXNET3 is not set # CONFIG_FUJITSU_ES is not set @@ -2295,7 +2335,6 @@ CONFIG_WLAN_VENDOR_QUANTENNA=y CONFIG_INPUT=y CONFIG_INPUT_LEDS=y CONFIG_INPUT_FF_MEMLESS=y -CONFIG_INPUT_POLLDEV=y CONFIG_INPUT_SPARSEKMAP=y # CONFIG_INPUT_MATRIXKMAP is not set @@ -2398,23 +2437,7 @@ CONFIG_HW_CONSOLE=y CONFIG_VT_HW_CONSOLE_BINDING=y CONFIG_UNIX98_PTYS=y # CONFIG_LEGACY_PTYS is not set -CONFIG_SERIAL_NONSTANDARD=y -# CONFIG_ROCKETPORT is not set -# CONFIG_CYCLADES is not set -# CONFIG_MOXA_INTELLIO is not set -# CONFIG_MOXA_SMARTIO is not set -# CONFIG_SYNCLINK is not set -# CONFIG_SYNCLINKMP is not set -# CONFIG_SYNCLINK_GT is not set -# CONFIG_NOZOMI is not set -# CONFIG_ISI is not set -# CONFIG_N_HDLC is not set -# CONFIG_N_GSM is not set -# CONFIG_TRACE_SINK is not set -# CONFIG_NULL_TTY is not set CONFIG_LDISC_AUTOLOAD=y -CONFIG_DEVMEM=y -# CONFIG_DEVKMEM is not set # # Serial drivers @@ -2423,6 +2446,7 @@ CONFIG_SERIAL_EARLYCON=y CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y CONFIG_SERIAL_8250_PNP=y +# CONFIG_SERIAL_8250_16550A_VARIANTS is not set # CONFIG_SERIAL_8250_FINTEK is not set CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_8250_DMA=y @@ -2435,11 +2459,11 @@ CONFIG_SERIAL_8250_MANY_PORTS=y CONFIG_SERIAL_8250_SHARE_IRQ=y CONFIG_SERIAL_8250_DETECT_IRQ=y CONFIG_SERIAL_8250_RSA=y +CONFIG_SERIAL_8250_DWLIB=y # CONFIG_SERIAL_8250_DW is not set # CONFIG_SERIAL_8250_RT288X is not set CONFIG_SERIAL_8250_LPSS=y # CONFIG_SERIAL_8250_MID is not set -# CONFIG_SERIAL_8250_MOXA is not set # # Non-8250 serial port support @@ -2450,34 +2474,54 @@ CONFIG_SERIAL_CORE=y CONFIG_SERIAL_CORE_CONSOLE=y CONFIG_CONSOLE_POLL=y # CONFIG_SERIAL_JSM is not set +# CONFIG_SERIAL_LANTIQ is not set # CONFIG_SERIAL_SCCNXP is not set # CONFIG_SERIAL_SC16IS7XX is not set +# CONFIG_SERIAL_BCM63XX is not set # CONFIG_SERIAL_ALTERA_JTAGUART is not set # CONFIG_SERIAL_ALTERA_UART is not set # CONFIG_SERIAL_ARC is not set # CONFIG_SERIAL_RP2 is not set # CONFIG_SERIAL_FSL_LPUART is not set +# CONFIG_SERIAL_FSL_LINFLEXUART is not set +# CONFIG_SERIAL_SPRD is not set # end of Serial drivers +CONFIG_SERIAL_NONSTANDARD=y +# CONFIG_ROCKETPORT is not set +# CONFIG_CYCLADES is not set +# CONFIG_MOXA_INTELLIO is not set +# CONFIG_MOXA_SMARTIO is not set +# CONFIG_SYNCLINK_GT is not set +# CONFIG_ISI is not set +# CONFIG_N_HDLC is not set +# CONFIG_N_GSM is not set +# CONFIG_NOZOMI is not set +# CONFIG_NULL_TTY is not set +# CONFIG_TRACE_SINK is not set # CONFIG_SERIAL_DEV_BUS is not set # CONFIG_TTY_PRINTK is not set # CONFIG_PRINTER is not set # CONFIG_PPDEV is not set +# CONFIG_VIRTIO_CONSOLE is not set # CONFIG_IPMI_HANDLER is not set # CONFIG_HW_RANDOM is not set -# CONFIG_NVRAM is not set # CONFIG_APPLICOM is not set # CONFIG_MWAVE is not set +CONFIG_DEVMEM=y +# CONFIG_DEVKMEM is not set +# CONFIG_NVRAM is not set # CONFIG_RAW_DRIVER is not set +CONFIG_DEVPORT=y # CONFIG_HPET is not set # CONFIG_HANGCHECK_TIMER is not set # CONFIG_TCG_TPM is not set # CONFIG_TELCLOCK is not set -CONFIG_DEVPORT=y # CONFIG_XILLYBUS is not set # end of Character devices # CONFIG_RANDOM_TRUST_CPU is not set +# CONFIG_RANDOM_TRUST_BOOTLOADER is not set # # I2C support @@ -2538,7 +2582,6 @@ CONFIG_I2C_PIIX4=m # # CONFIG_I2C_DIOLAN_U2C is not set # CONFIG_I2C_PARPORT is not set -# CONFIG_I2C_PARPORT_LIGHT is not set # CONFIG_I2C_ROBOTFUZZ_OSIF is not set # CONFIG_I2C_TAOS_EVM is not set # CONFIG_I2C_TINY_USB is not set @@ -2584,6 +2627,10 @@ CONFIG_PTP_1588_CLOCK=y # Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. # CONFIG_PTP_1588_CLOCK_KVM=y +# CONFIG_PTP_1588_CLOCK_IDT82P33 is not set +# CONFIG_PTP_1588_CLOCK_IDTCM is not set +# CONFIG_PTP_1588_CLOCK_VMW is not set +# CONFIG_PTP_1588_CLOCK_OCP is not set # end of PTP clock support CONFIG_PINCTRL=y @@ -2593,17 +2640,29 @@ CONFIG_PINCTRL=y # CONFIG_PINCTRL_SX150X is not set # CONFIG_PINCTRL_BAYTRAIL is not set # CONFIG_PINCTRL_CHERRYVIEW is not set +# CONFIG_PINCTRL_LYNXPOINT is not set +# CONFIG_PINCTRL_ALDERLAKE is not set # CONFIG_PINCTRL_BROXTON is not set # CONFIG_PINCTRL_CANNONLAKE is not set # CONFIG_PINCTRL_CEDARFORK is not set # CONFIG_PINCTRL_DENVERTON is not set +# CONFIG_PINCTRL_ELKHARTLAKE is not set +# CONFIG_PINCTRL_EMMITSBURG is not set # CONFIG_PINCTRL_GEMINILAKE is not set # CONFIG_PINCTRL_ICELAKE is not set +# CONFIG_PINCTRL_JASPERLAKE is not set +# CONFIG_PINCTRL_LAKEFIELD is not set # CONFIG_PINCTRL_LEWISBURG is not set # CONFIG_PINCTRL_SUNRISEPOINT is not set +# CONFIG_PINCTRL_TIGERLAKE is not set + +# +# Renesas pinctrl drivers +# +# end of Renesas pinctrl drivers + # CONFIG_GPIOLIB is not set # CONFIG_W1 is not set -# CONFIG_POWER_AVS is not set # CONFIG_POWER_RESET is not set CONFIG_POWER_SUPPLY=y # CONFIG_POWER_SUPPLY_DEBUG is not set @@ -2611,6 +2670,7 @@ CONFIG_POWER_SUPPLY_HWMON=y # CONFIG_PDA_POWER is not set # CONFIG_TEST_POWER is not set # CONFIG_CHARGER_ADP5061 is not set +# CONFIG_BATTERY_CW2015 is not set # CONFIG_BATTERY_DS2780 is not set # CONFIG_BATTERY_DS2781 is not set # CONFIG_BATTERY_DS2782 is not set @@ -2624,6 +2684,7 @@ CONFIG_POWER_SUPPLY_HWMON=y # CONFIG_CHARGER_BQ2415X is not set # CONFIG_CHARGER_SMB347 is not set # CONFIG_BATTERY_GAUGE_LTC2941 is not set +# CONFIG_CHARGER_BD99954 is not set CONFIG_HWMON=y # CONFIG_HWMON_DEBUG_CHIP is not set @@ -2639,20 +2700,27 @@ CONFIG_HWMON=y # CONFIG_SENSORS_ADM1026 is not set # CONFIG_SENSORS_ADM1029 is not set # CONFIG_SENSORS_ADM1031 is not set +# CONFIG_SENSORS_ADM1177 is not set # CONFIG_SENSORS_ADM9240 is not set # CONFIG_SENSORS_ADT7410 is not set # CONFIG_SENSORS_ADT7411 is not set # CONFIG_SENSORS_ADT7462 is not set # CONFIG_SENSORS_ADT7470 is not set # CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_AS370 is not set # CONFIG_SENSORS_ASC7621 is not set +# CONFIG_SENSORS_AXI_FAN_CONTROL is not set # CONFIG_SENSORS_K8TEMP is not set CONFIG_SENSORS_K10TEMP=m # CONFIG_SENSORS_FAM15H_POWER is not set +# CONFIG_SENSORS_AMD_ENERGY is not set # CONFIG_SENSORS_APPLESMC is not set # CONFIG_SENSORS_ASB100 is not set # CONFIG_SENSORS_ASPEED is not set # CONFIG_SENSORS_ATXP1 is not set +# CONFIG_SENSORS_CORSAIR_CPRO is not set +# CONFIG_SENSORS_CORSAIR_PSU is not set +# CONFIG_SENSORS_DRIVETEMP is not set # CONFIG_SENSORS_DS620 is not set # CONFIG_SENSORS_DS1621 is not set CONFIG_SENSORS_DELL_SMM=m @@ -2674,6 +2742,7 @@ CONFIG_SENSORS_DELL_SMM=m # CONFIG_SENSORS_POWR1220 is not set # CONFIG_SENSORS_LINEAGE is not set # CONFIG_SENSORS_LTC2945 is not set +# CONFIG_SENSORS_LTC2947_I2C is not set # CONFIG_SENSORS_LTC2990 is not set # CONFIG_SENSORS_LTC4151 is not set # CONFIG_SENSORS_LTC4215 is not set @@ -2681,10 +2750,12 @@ CONFIG_SENSORS_DELL_SMM=m # CONFIG_SENSORS_LTC4245 is not set # CONFIG_SENSORS_LTC4260 is not set # CONFIG_SENSORS_LTC4261 is not set +# CONFIG_SENSORS_MAX127 is not set # CONFIG_SENSORS_MAX16065 is not set # CONFIG_SENSORS_MAX1619 is not set # CONFIG_SENSORS_MAX1668 is not set # CONFIG_SENSORS_MAX197 is not set +# CONFIG_SENSORS_MAX31730 is not set # CONFIG_SENSORS_MAX6621 is not set # CONFIG_SENSORS_MAX6639 is not set # CONFIG_SENSORS_MAX6642 is not set @@ -2693,6 +2764,7 @@ CONFIG_SENSORS_DELL_SMM=m # CONFIG_SENSORS_MAX31790 is not set # CONFIG_SENSORS_MCP3021 is not set # CONFIG_SENSORS_TC654 is not set +# CONFIG_SENSORS_MR75203 is not set # CONFIG_SENSORS_LM63 is not set # CONFIG_SENSORS_LM73 is not set # CONFIG_SENSORS_LM75 is not set @@ -2718,6 +2790,7 @@ CONFIG_SENSORS_DELL_SMM=m # CONFIG_SENSORS_NPCM7XX is not set # CONFIG_SENSORS_PCF8591 is not set # CONFIG_PMBUS is not set +# CONFIG_SENSORS_SBTSI is not set # CONFIG_SENSORS_SHT21 is not set # CONFIG_SENSORS_SHT3x is not set # CONFIG_SENSORS_SHTC1 is not set @@ -2734,7 +2807,6 @@ CONFIG_SENSORS_DELL_SMM=m # CONFIG_SENSORS_STTS751 is not set # CONFIG_SENSORS_SMM665 is not set # CONFIG_SENSORS_ADC128D818 is not set -# CONFIG_SENSORS_ADS1015 is not set # CONFIG_SENSORS_ADS7828 is not set # CONFIG_SENSORS_AMC6821 is not set # CONFIG_SENSORS_INA209 is not set @@ -2747,6 +2819,7 @@ CONFIG_SENSORS_DELL_SMM=m # CONFIG_SENSORS_TMP108 is not set # CONFIG_SENSORS_TMP401 is not set # CONFIG_SENSORS_TMP421 is not set +# CONFIG_SENSORS_TMP513 is not set # CONFIG_SENSORS_VIA_CPUTEMP is not set # CONFIG_SENSORS_VIA686A is not set # CONFIG_SENSORS_VT1211 is not set @@ -2769,6 +2842,7 @@ CONFIG_SENSORS_DELL_SMM=m # CONFIG_SENSORS_ACPI_POWER is not set # CONFIG_SENSORS_ATK0110 is not set CONFIG_THERMAL=y +# CONFIG_THERMAL_NETLINK is not set # CONFIG_THERMAL_STATISTICS is not set CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 CONFIG_THERMAL_HWMON=y @@ -2776,12 +2850,10 @@ CONFIG_THERMAL_WRITABLE_TRIPS=y CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y # CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set # CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set -# CONFIG_THERMAL_DEFAULT_GOV_POWER_ALLOCATOR is not set # CONFIG_THERMAL_GOV_FAIR_SHARE is not set CONFIG_THERMAL_GOV_STEP_WISE=y # CONFIG_THERMAL_GOV_BANG_BANG is not set CONFIG_THERMAL_GOV_USER_SPACE=y -# CONFIG_THERMAL_GOV_POWER_ALLOCATOR is not set # CONFIG_THERMAL_EMULATION is not set # @@ -2879,7 +2951,6 @@ CONFIG_BCMA_POSSIBLE=y # CONFIG_MFD_BCM590XX is not set # CONFIG_MFD_BD9571MWV is not set # CONFIG_MFD_AXP20X_I2C is not set -# CONFIG_MFD_CROS_EC is not set # CONFIG_MFD_MADERA is not set # CONFIG_PMIC_DA903X is not set # CONFIG_MFD_DA9052_I2C is not set @@ -2889,12 +2960,15 @@ CONFIG_BCMA_POSSIBLE=y # CONFIG_MFD_DA9150 is not set # CONFIG_MFD_DLN2 is not set # CONFIG_MFD_MC13XXX_I2C is not set +# CONFIG_MFD_MP2629 is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_MFD_INTEL_QUARK_I2C_GPIO is not set # CONFIG_LPC_ICH is not set # CONFIG_LPC_SCH is not set # CONFIG_MFD_INTEL_LPSS_ACPI is not set # CONFIG_MFD_INTEL_LPSS_PCI is not set +# CONFIG_MFD_INTEL_PMT is not set +# CONFIG_MFD_IQS62X is not set # CONFIG_MFD_JANZ_CMODIO is not set # CONFIG_MFD_KEMPLD is not set # CONFIG_MFD_88PM800 is not set @@ -2907,6 +2981,7 @@ CONFIG_BCMA_POSSIBLE=y # CONFIG_MFD_MAX8925 is not set # CONFIG_MFD_MAX8997 is not set # CONFIG_MFD_MAX8998 is not set +# CONFIG_MFD_MT6360 is not set # CONFIG_MFD_MT6397 is not set # CONFIG_MFD_MENF21BMC is not set # CONFIG_MFD_VIPERBOARD is not set @@ -2919,7 +2994,6 @@ CONFIG_BCMA_POSSIBLE=y # CONFIG_MFD_SI476X_CORE is not set # CONFIG_MFD_SM501 is not set # CONFIG_MFD_SKY81452 is not set -# CONFIG_MFD_SMSC is not set # CONFIG_ABX500_CORE is not set # CONFIG_MFD_SYSCON is not set # CONFIG_MFD_TI_AM335X_TSCADC is not set @@ -2965,6 +3039,7 @@ CONFIG_IR_XMP_DECODER=y # CONFIG_IR_IMON_DECODER is not set # CONFIG_IR_RCMM_DECODER is not set # CONFIG_RC_DEVICES is not set +# CONFIG_MEDIA_CEC_SUPPORT is not set # CONFIG_MEDIA_SUPPORT is not set # @@ -2985,6 +3060,7 @@ CONFIG_DRM=y # CONFIG_DRM_DEBUG_SELFTEST is not set CONFIG_DRM_KMS_HELPER=y CONFIG_DRM_KMS_FB_HELPER=y +# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set CONFIG_DRM_FBDEV_EMULATION=y CONFIG_DRM_FBDEV_OVERALLOC=100 # CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set @@ -2992,6 +3068,7 @@ CONFIG_DRM_FBDEV_OVERALLOC=100 # CONFIG_DRM_DP_CEC is not set CONFIG_DRM_TTM=m CONFIG_DRM_VRAM_HELPER=m +CONFIG_DRM_TTM_HELPER=m CONFIG_DRM_SCHED=m # @@ -3013,7 +3090,6 @@ CONFIG_DRM_AMDGPU=m CONFIG_DRM_AMDGPU_SI=y CONFIG_DRM_AMDGPU_CIK=y CONFIG_DRM_AMDGPU_USERPTR=y -# CONFIG_DRM_AMDGPU_GART_DEBUGFS is not set # # ACP (Audio CoProcessor) Configuration @@ -3025,12 +3101,11 @@ CONFIG_DRM_AMDGPU_USERPTR=y # Display Engine Configuration # CONFIG_DRM_AMD_DC=y -CONFIG_DRM_AMD_DC_DCN1_0=y -CONFIG_DRM_AMD_DC_DCN2_0=y -# CONFIG_DRM_AMD_DC_DCN2_1 is not set -CONFIG_DRM_AMD_DC_DSC_SUPPORT=y +CONFIG_DRM_AMD_DC_DCN=y # CONFIG_DRM_AMD_DC_HDCP is not set +# CONFIG_DRM_AMD_DC_SI is not set # CONFIG_DEBUG_KERNEL_DC is not set +# CONFIG_DRM_AMD_SECURE_DISPLAY is not set # end of Display Engine Configuration CONFIG_HSA_AMD=y @@ -3043,9 +3118,9 @@ CONFIG_HSA_AMD=y # CONFIG_DRM_UDL is not set CONFIG_DRM_AST=m # CONFIG_DRM_MGAG200 is not set -# CONFIG_DRM_CIRRUS_QEMU is not set # CONFIG_DRM_QXL is not set # CONFIG_DRM_BOCHS is not set +# CONFIG_DRM_VIRTIO_GPU is not set CONFIG_DRM_PANEL=y # @@ -3063,6 +3138,7 @@ CONFIG_DRM_PANEL_BRIDGE=y # end of Display Interface Bridges # CONFIG_DRM_ETNAVIV is not set +# CONFIG_DRM_CIRRUS_QEMU is not set # CONFIG_DRM_GM12U320 is not set # CONFIG_DRM_VBOXVIDEO is not set # CONFIG_DRM_LEGACY is not set @@ -3139,9 +3215,8 @@ CONFIG_FB_DEFERRED_IO=y # # CONFIG_LCD_CLASS_DEVICE is not set CONFIG_BACKLIGHT_CLASS_DEVICE=y -# CONFIG_BACKLIGHT_GENERIC is not set # CONFIG_BACKLIGHT_APPLE is not set -# CONFIG_BACKLIGHT_PM8941_WLED is not set +# CONFIG_BACKLIGHT_QCOM_WLED is not set # CONFIG_BACKLIGHT_SAHARA is not set # CONFIG_BACKLIGHT_ADP8860 is not set # CONFIG_BACKLIGHT_ADP8870 is not set @@ -3157,9 +3232,6 @@ CONFIG_HDMI=y # Console display driver support # CONFIG_VGA_CONSOLE=y -CONFIG_VGACON_SOFT_SCROLLBACK=y -CONFIG_VGACON_SOFT_SCROLLBACK_SIZE=64 -# CONFIG_VGACON_SOFT_SCROLLBACK_PERSISTENT_ENABLE_BY_DEFAULT is not set CONFIG_DUMMY_CONSOLE=y CONFIG_DUMMY_CONSOLE_COLUMNS=80 CONFIG_DUMMY_CONSOLE_ROWS=25 @@ -3202,6 +3274,7 @@ CONFIG_HID_CHICONY=y # CONFIG_HID_COUGAR is not set # CONFIG_HID_MACALLY is not set # CONFIG_HID_CMEDIA is not set +# CONFIG_HID_CREATIVE_SB0540 is not set CONFIG_HID_CYPRESS=y # CONFIG_HID_DRAGONRISE is not set # CONFIG_HID_EMS_FF is not set @@ -3211,7 +3284,9 @@ CONFIG_HID_CYPRESS=y CONFIG_HID_EZKEY=y # CONFIG_HID_GEMBIRD is not set # CONFIG_HID_GFRM is not set +# CONFIG_HID_GLORIOUS is not set # CONFIG_HID_HOLTEK is not set +# CONFIG_HID_VIVALDI is not set # CONFIG_HID_GT683R is not set # CONFIG_HID_KEYTOUCH is not set CONFIG_HID_KYE=y @@ -3295,11 +3370,19 @@ CONFIG_USB_HIDDEV=y # # CONFIG_INTEL_ISH_HID is not set # end of Intel ISH HID support + +# +# AMD SFH HID Support +# +# CONFIG_AMD_SFH_HID is not set +# end of AMD SFH HID Support # end of HID support CONFIG_USB_OHCI_LITTLE_ENDIAN=y CONFIG_USB_SUPPORT=y CONFIG_USB_COMMON=y +# CONFIG_USB_LED_TRIG is not set +# CONFIG_USB_ULPI_BUS is not set CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB=y CONFIG_USB_PCI=y @@ -3309,14 +3392,14 @@ CONFIG_USB_PCI=y # Miscellaneous USB options # CONFIG_USB_DEFAULT_PERSIST=y +# CONFIG_USB_FEW_INIT_RETRIES is not set # CONFIG_USB_DYNAMIC_MINORS is not set # CONFIG_USB_OTG is not set -# CONFIG_USB_OTG_WHITELIST is not set -# CONFIG_USB_OTG_BLACKLIST_HUB is not set +# CONFIG_USB_OTG_PRODUCTLIST is not set +# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set # CONFIG_USB_LEDS_TRIGGER_USBPORT is not set CONFIG_USB_AUTOSUSPEND_DELAY=2 # CONFIG_USB_MON is not set -# CONFIG_USB_WUSB_CBAF is not set # # USB Host Controller Drivers @@ -3325,6 +3408,7 @@ CONFIG_USB_AUTOSUSPEND_DELAY=2 CONFIG_USB_XHCI_HCD=y # CONFIG_USB_XHCI_DBGCAP is not set CONFIG_USB_XHCI_PCI=y +# CONFIG_USB_XHCI_PCI_RENESAS is not set # CONFIG_USB_XHCI_PLATFORM is not set CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_ROOT_HUB_TT=y @@ -3381,6 +3465,7 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_MDC800 is not set # CONFIG_USB_MICROTEK is not set # CONFIG_USBIP_CORE is not set +# CONFIG_USB_CDNS3 is not set # CONFIG_USB_MUSB_HDRC is not set # CONFIG_USB_DWC3 is not set # CONFIG_USB_DWC2 is not set @@ -3400,7 +3485,6 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_EMI26 is not set # CONFIG_USB_ADUTUX is not set # CONFIG_USB_SEVSEG is not set -# CONFIG_USB_RIO500 is not set # CONFIG_USB_LEGOTOWER is not set # CONFIG_USB_LCD is not set # CONFIG_USB_CYPRESS_CY7C63 is not set @@ -3408,6 +3492,7 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_IDMOUSE is not set # CONFIG_USB_FTDI_ELAN is not set # CONFIG_USB_APPLEDISPLAY is not set +# CONFIG_APPLE_MFI_FASTCHARGE is not set # CONFIG_USB_SISUSBVGA is not set # CONFIG_USB_LD is not set # CONFIG_USB_TRANCEVIBRATOR is not set @@ -3432,14 +3517,12 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_GADGET is not set # CONFIG_TYPEC is not set # CONFIG_USB_ROLE_SWITCH is not set -# CONFIG_USB_LED_TRIG is not set -# CONFIG_USB_ULPI_BUS is not set -# CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y # CONFIG_LEDS_CLASS_FLASH is not set +# CONFIG_LEDS_CLASS_MULTICOLOR is not set # CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set # @@ -3451,10 +3534,6 @@ CONFIG_LEDS_CLASS=y # CONFIG_LEDS_LM3642 is not set # CONFIG_LEDS_PCA9532 is not set # CONFIG_LEDS_LP3944 is not set -# CONFIG_LEDS_LP5521 is not set -# CONFIG_LEDS_LP5523 is not set -# CONFIG_LEDS_LP5562 is not set -# CONFIG_LEDS_LP8501 is not set # CONFIG_LEDS_CLEVO_MAIL is not set # CONFIG_LEDS_PCA955X is not set # CONFIG_LEDS_PCA963X is not set @@ -3472,7 +3551,10 @@ CONFIG_LEDS_CLASS=y # CONFIG_LEDS_MLXREG is not set # CONFIG_LEDS_USER is not set # CONFIG_LEDS_NIC78BX is not set -# CONFIG_LEDS_TI_LMU_COMMON is not set + +# +# Flash and Torch LED drivers +# # # LED Triggers @@ -3539,7 +3621,6 @@ CONFIG_RTC_INTF_DEV=y # CONFIG_RTC_DRV_PCF8563 is not set # CONFIG_RTC_DRV_PCF8583 is not set # CONFIG_RTC_DRV_M41T80 is not set -# CONFIG_RTC_DRV_BD70528 is not set # CONFIG_RTC_DRV_BQ32K is not set # CONFIG_RTC_DRV_S35390A is not set # CONFIG_RTC_DRV_FM3130 is not set @@ -3548,6 +3629,7 @@ CONFIG_RTC_INTF_DEV=y # CONFIG_RTC_DRV_RX8025 is not set # CONFIG_RTC_DRV_EM3027 is not set # CONFIG_RTC_DRV_RV3028 is not set +# CONFIG_RTC_DRV_RV3032 is not set # CONFIG_RTC_DRV_RV8803 is not set # CONFIG_RTC_DRV_SD3078 is not set @@ -3562,6 +3644,7 @@ CONFIG_RTC_I2C_AND_SPI=y # CONFIG_RTC_DRV_DS3232 is not set # CONFIG_RTC_DRV_PCF2127 is not set # CONFIG_RTC_DRV_RV3029C2 is not set +# CONFIG_RTC_DRV_RX6110 is not set # # Platform RTC drivers @@ -3600,7 +3683,10 @@ CONFIG_DMA_ENGINE=y CONFIG_DMA_ACPI=y # CONFIG_ALTERA_MSGDMA is not set # CONFIG_INTEL_IDMA64 is not set +# CONFIG_INTEL_IDXD is not set # CONFIG_INTEL_IOATDMA is not set +# CONFIG_PLX_DMA is not set +# CONFIG_XILINX_ZYNQMP_DPDMA is not set # CONFIG_QCOM_HIDMA_MGMT is not set # CONFIG_QCOM_HIDMA is not set CONFIG_DW_DMAC_CORE=y @@ -3608,6 +3694,7 @@ CONFIG_DW_DMAC_CORE=y CONFIG_DW_DMAC_PCI=y # CONFIG_DW_EDMA is not set # CONFIG_DW_EDMA_PCIE is not set +# CONFIG_SF_PDMA is not set # # DMA Clients @@ -3621,7 +3708,10 @@ CONFIG_DW_DMAC_PCI=y CONFIG_SYNC_FILE=y # CONFIG_SW_SYNC is not set # CONFIG_UDMABUF is not set +# CONFIG_DMABUF_MOVE_NOTIFY is not set +# CONFIG_DMABUF_DEBUG is not set # CONFIG_DMABUF_SELFTESTS is not set +# CONFIG_DMABUF_HEAPS is not set # end of DMABUF options # CONFIG_AUXDISPLAY is not set @@ -3632,6 +3722,10 @@ CONFIG_SYNC_FILE=y CONFIG_VIRTIO_MENU=y # CONFIG_VIRTIO_PCI is not set # CONFIG_VIRTIO_MMIO is not set +# CONFIG_VDPA is not set +CONFIG_VHOST_MENU=y +# CONFIG_VHOST_NET is not set +# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set # # Microsoft Hyper-V guest support @@ -3639,26 +3733,26 @@ CONFIG_VIRTIO_MENU=y # CONFIG_HYPERV is not set # end of Microsoft Hyper-V guest support +# CONFIG_GREYBUS is not set # CONFIG_STAGING is not set # CONFIG_X86_PLATFORM_DEVICES is not set CONFIG_PMC_ATOM=y # CONFIG_CHROME_PLATFORMS is not set # CONFIG_MELLANOX_PLATFORM is not set +CONFIG_SURFACE_PLATFORMS=y +# CONFIG_SURFACE_3_POWER_OPREGION is not set +# CONFIG_SURFACE_GPE is not set +# CONFIG_SURFACE_PRO3_BUTTON is not set +CONFIG_HAVE_CLK=y CONFIG_CLKDEV_LOOKUP=y CONFIG_HAVE_CLK_PREPARE=y CONFIG_COMMON_CLK=y - -# -# Common Clock Framework -# # CONFIG_COMMON_CLK_MAX9485 is not set # CONFIG_COMMON_CLK_SI5341 is not set # CONFIG_COMMON_CLK_SI5351 is not set # CONFIG_COMMON_CLK_SI544 is not set # CONFIG_COMMON_CLK_CDCE706 is not set # CONFIG_COMMON_CLK_CS2000_CP is not set -# end of Common Clock Framework - # CONFIG_HWSPINLOCK is not set # @@ -3683,6 +3777,7 @@ CONFIG_IOMMU_SUPPORT=y # CONFIG_IOMMU_DEBUGFS is not set # CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set +CONFIG_IOMMU_DMA=y CONFIG_AMD_IOMMU=y CONFIG_AMD_IOMMU_V2=m # CONFIG_INTEL_IOMMU is not set @@ -3712,11 +3807,6 @@ CONFIG_AMD_IOMMU_V2=m # # end of Amlogic SoC drivers -# -# Aspeed SoC drivers -# -# end of Aspeed SoC drivers - # # Broadcom SoC drivers # @@ -3733,11 +3823,9 @@ CONFIG_AMD_IOMMU_V2=m # end of i.MX SoC drivers # -# IXP4xx SoC drivers +# Enable LiteX SoC Builder specific drivers # -# CONFIG_IXP4XX_QMGR is not set -# CONFIG_IXP4XX_NPE is not set -# end of IXP4xx SoC drivers +# end of Enable LiteX SoC Builder specific drivers # # Qualcomm SoC drivers @@ -3773,9 +3861,11 @@ CONFIG_AMD_IOMMU_V2=m # PHY Subsystem # # CONFIG_GENERIC_PHY is not set +# CONFIG_USB_LGM_PHY is not set # CONFIG_BCM_KONA_USB2_PHY is not set # CONFIG_PHY_PXA_28NM_HSIC is not set # CONFIG_PHY_PXA_28NM_USB2 is not set +# CONFIG_PHY_INTEL_LGM_EMMC is not set # end of PHY Subsystem # CONFIG_POWERCAP is not set @@ -3788,7 +3878,7 @@ CONFIG_AMD_IOMMU_V2=m CONFIG_RAS=y # CONFIG_RAS_CEC is not set -# CONFIG_THUNDERBOLT is not set +# CONFIG_USB4 is not set # # Android @@ -3799,6 +3889,7 @@ CONFIG_RAS=y # CONFIG_LIBNVDIMM is not set CONFIG_DAX=y # CONFIG_DEV_DAX is not set +# CONFIG_DEV_DAX_HMEM is not set CONFIG_NVMEM=y CONFIG_NVMEM_SYSFS=y @@ -3810,11 +3901,13 @@ CONFIG_NVMEM_SYSFS=y # end of HW tracing support # CONFIG_FPGA is not set +# CONFIG_TEE is not set # CONFIG_UNISYS_VISORBUS is not set # CONFIG_SIOX is not set # CONFIG_SLIMBUS is not set # CONFIG_INTERCONNECT is not set # CONFIG_COUNTER is not set +# CONFIG_MOST is not set # end of Device Drivers # @@ -3836,6 +3929,7 @@ CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set CONFIG_XFS_FS=y +CONFIG_XFS_SUPPORT_V4=y CONFIG_XFS_QUOTA=y CONFIG_XFS_POSIX_ACL=y CONFIG_XFS_RT=y @@ -3854,6 +3948,7 @@ CONFIG_EXPORTFS=y CONFIG_FILE_LOCKING=y CONFIG_MANDATORY_FILE_LOCKING=y # CONFIG_FS_ENCRYPTION is not set +# CONFIG_FS_VERITY is not set CONFIG_FSNOTIFY=y CONFIG_DNOTIFY=y CONFIG_INOTIFY_USER=y @@ -3866,11 +3961,11 @@ CONFIG_QUOTA_TREE=y # CONFIG_QFMT_V1 is not set CONFIG_QFMT_V2=y CONFIG_QUOTACTL=y -CONFIG_QUOTACTL_COMPAT=y CONFIG_AUTOFS4_FS=y CONFIG_AUTOFS_FS=y CONFIG_FUSE_FS=m CONFIG_CUSE=m +# CONFIG_VIRTIO_FS is not set CONFIG_OVERLAY_FS=y # CONFIG_OVERLAY_FS_REDIRECT_DIR is not set CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y @@ -3899,7 +3994,7 @@ CONFIG_ZISOFS=y # end of CD-ROM/DVD Filesystems # -# DOS/FAT/NT Filesystems +# DOS/FAT/EXFAT/NT Filesystems # CONFIG_FAT_FS=y CONFIG_MSDOS_FS=y @@ -3907,10 +4002,11 @@ CONFIG_VFAT_FS=y CONFIG_FAT_DEFAULT_CODEPAGE=437 CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" # CONFIG_FAT_DEFAULT_UTF8 is not set +# CONFIG_EXFAT_FS is not set CONFIG_NTFS_FS=y # CONFIG_NTFS_DEBUG is not set CONFIG_NTFS_RW=y -# end of DOS/FAT/NT Filesystems +# end of DOS/FAT/EXFAT/NT Filesystems # # Pseudo filesystems @@ -3928,6 +4024,7 @@ CONFIG_SYSFS=y CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y CONFIG_TMPFS_XATTR=y +# CONFIG_TMPFS_INODE64 is not set CONFIG_HUGETLBFS=y CONFIG_HUGETLB_PAGE=y CONFIG_MEMFD_CREATE=y @@ -3956,6 +4053,7 @@ CONFIG_MISC_FILESYSTEMS=y # CONFIG_QNX6FS_FS is not set # CONFIG_ROMFS_FS is not set CONFIG_PSTORE=y +CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240 CONFIG_PSTORE_DEFLATE_COMPRESS=y # CONFIG_PSTORE_LZO_COMPRESS is not set # CONFIG_PSTORE_LZ4_COMPRESS is not set @@ -3969,8 +4067,10 @@ CONFIG_PSTORE_COMPRESS_DEFAULT="deflate" # CONFIG_PSTORE_PMSG is not set # CONFIG_PSTORE_FTRACE is not set # CONFIG_PSTORE_RAM is not set +# CONFIG_PSTORE_BLK is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set +# CONFIG_EROFS_FS is not set CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=y CONFIG_NFS_V2=y @@ -3983,6 +4083,7 @@ CONFIG_ROOT_NFS=y # CONFIG_NFS_FSCACHE is not set # CONFIG_NFS_USE_LEGACY_DNS is not set CONFIG_NFS_USE_KERNEL_DNS=y +CONFIG_NFS_DISABLE_UDP_SUPPORT=y # CONFIG_NFSD is not set CONFIG_GRACE_PERIOD=y CONFIG_LOCKD=y @@ -4003,7 +4104,9 @@ CONFIG_CIFS_DEBUG=y # CONFIG_CIFS_DEBUG2 is not set # CONFIG_CIFS_DEBUG_DUMP_KEYS is not set # CONFIG_CIFS_DFS_UPCALL is not set +# CONFIG_CIFS_SWN_UPCALL is not set CONFIG_CIFS_FSCACHE=y +# CONFIG_CIFS_ROOT is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set CONFIG_NLS=y @@ -4059,16 +4162,15 @@ CONFIG_NLS_ISO8859_1=y CONFIG_NLS_UTF8=y # CONFIG_DLM is not set # CONFIG_UNICODE is not set +CONFIG_IO_WQ=y # end of File systems # # Security options # CONFIG_KEYS=y -CONFIG_KEYS_COMPAT=y # CONFIG_KEYS_REQUEST_CACHE is not set # CONFIG_PERSISTENT_KEYRINGS is not set -# CONFIG_BIG_KEYS is not set # CONFIG_ENCRYPTED_KEYS is not set # CONFIG_KEY_DH_OPERATIONS is not set # CONFIG_SECURITY_DMESG_RESTRICT is not set @@ -4090,16 +4192,20 @@ CONFIG_SECURITY_SELINUX_DISABLE=y CONFIG_SECURITY_SELINUX_DEVELOP=y CONFIG_SECURITY_SELINUX_AVC_STATS=y CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=1 +CONFIG_SECURITY_SELINUX_SIDTAB_HASH_BITS=9 +CONFIG_SECURITY_SELINUX_SID2STR_CACHE_SIZE=256 # CONFIG_SECURITY_SMACK is not set # CONFIG_SECURITY_TOMOYO is not set # CONFIG_SECURITY_APPARMOR is not set # CONFIG_SECURITY_LOADPIN is not set # CONFIG_SECURITY_YAMA is not set # CONFIG_SECURITY_SAFESETID is not set +# CONFIG_SECURITY_LOCKDOWN_LSM is not set CONFIG_INTEGRITY=y # CONFIG_INTEGRITY_SIGNATURE is not set CONFIG_INTEGRITY_AUDIT=y # CONFIG_IMA is not set +# CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT is not set # CONFIG_EVM is not set CONFIG_DEFAULT_SECURITY_SELINUX=y # CONFIG_DEFAULT_SECURITY_DAC is not set @@ -4128,8 +4234,8 @@ CONFIG_CRYPTO_ALGAPI=y CONFIG_CRYPTO_ALGAPI2=y CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_AEAD2=y -CONFIG_CRYPTO_BLKCIPHER=y -CONFIG_CRYPTO_BLKCIPHER2=y +CONFIG_CRYPTO_SKCIPHER=y +CONFIG_CRYPTO_SKCIPHER2=y CONFIG_CRYPTO_HASH=y CONFIG_CRYPTO_HASH2=y CONFIG_CRYPTO_RNG=y @@ -4158,6 +4264,9 @@ CONFIG_CRYPTO_RSA=y # CONFIG_CRYPTO_DH is not set # CONFIG_CRYPTO_ECDH is not set # CONFIG_CRYPTO_ECRDSA is not set +# CONFIG_CRYPTO_SM2 is not set +# CONFIG_CRYPTO_CURVE25519 is not set +# CONFIG_CRYPTO_CURVE25519_X86 is not set # # Authenticated Encryption with Associated Data @@ -4166,16 +4275,7 @@ CONFIG_CRYPTO_CCM=y CONFIG_CRYPTO_GCM=y # CONFIG_CRYPTO_CHACHA20POLY1305 is not set # CONFIG_CRYPTO_AEGIS128 is not set -# CONFIG_CRYPTO_AEGIS128L is not set -# CONFIG_CRYPTO_AEGIS256 is not set # CONFIG_CRYPTO_AEGIS128_AESNI_SSE2 is not set -# CONFIG_CRYPTO_AEGIS128L_AESNI_SSE2 is not set -# CONFIG_CRYPTO_AEGIS256_AESNI_SSE2 is not set -# CONFIG_CRYPTO_MORUS640 is not set -# CONFIG_CRYPTO_MORUS640_SSE2 is not set -# CONFIG_CRYPTO_MORUS1280 is not set -# CONFIG_CRYPTO_MORUS1280_SSE2 is not set -# CONFIG_CRYPTO_MORUS1280_AVX2 is not set CONFIG_CRYPTO_SEQIV=y CONFIG_CRYPTO_ECHAINIV=y @@ -4195,6 +4295,7 @@ CONFIG_CRYPTO_ECB=y # CONFIG_CRYPTO_NHPOLY1305_SSE2 is not set # CONFIG_CRYPTO_NHPOLY1305_AVX2 is not set # CONFIG_CRYPTO_ADIANTUM is not set +# CONFIG_CRYPTO_ESSIV is not set # # Hash modes @@ -4212,6 +4313,9 @@ CONFIG_CRYPTO_CRC32C=y # CONFIG_CRYPTO_CRC32 is not set # CONFIG_CRYPTO_CRC32_PCLMUL is not set # CONFIG_CRYPTO_XXHASH is not set +# CONFIG_CRYPTO_BLAKE2B is not set +# CONFIG_CRYPTO_BLAKE2S is not set +# CONFIG_CRYPTO_BLAKE2S_X86 is not set CONFIG_CRYPTO_CRCT10DIF=y # CONFIG_CRYPTO_CRCT10DIF_PCLMUL is not set CONFIG_CRYPTO_GHASH=y @@ -4242,11 +4346,7 @@ CONFIG_CRYPTO_SHA512=y # CONFIG_CRYPTO_AES=y # CONFIG_CRYPTO_AES_TI is not set -# CONFIG_CRYPTO_AES_X86_64 is not set # CONFIG_CRYPTO_AES_NI_INTEL is not set -# CONFIG_CRYPTO_ANUBIS is not set -CONFIG_CRYPTO_LIB_ARC4=y -CONFIG_CRYPTO_ARC4=y # CONFIG_CRYPTO_BLOWFISH is not set # CONFIG_CRYPTO_BLOWFISH_X86_64 is not set # CONFIG_CRYPTO_CAMELLIA is not set @@ -4260,17 +4360,14 @@ CONFIG_CRYPTO_ARC4=y CONFIG_CRYPTO_DES=y # CONFIG_CRYPTO_DES3_EDE_X86_64 is not set # CONFIG_CRYPTO_FCRYPT is not set -# CONFIG_CRYPTO_KHAZAD is not set # CONFIG_CRYPTO_SALSA20 is not set # CONFIG_CRYPTO_CHACHA20 is not set # CONFIG_CRYPTO_CHACHA20_X86_64 is not set -# CONFIG_CRYPTO_SEED is not set # CONFIG_CRYPTO_SERPENT is not set # CONFIG_CRYPTO_SERPENT_SSE2_X86_64 is not set # CONFIG_CRYPTO_SERPENT_AVX_X86_64 is not set # CONFIG_CRYPTO_SERPENT_AVX2_X86_64 is not set # CONFIG_CRYPTO_SM4 is not set -# CONFIG_CRYPTO_TEA is not set # CONFIG_CRYPTO_TWOFISH is not set # CONFIG_CRYPTO_TWOFISH_X86_64 is not set # CONFIG_CRYPTO_TWOFISH_X86_64_3WAY is not set @@ -4301,6 +4398,20 @@ CONFIG_CRYPTO_JITTERENTROPY=y # CONFIG_CRYPTO_USER_API_RNG is not set # CONFIG_CRYPTO_USER_API_AEAD is not set CONFIG_CRYPTO_HASH_INFO=y + +# +# Crypto library routines +# +CONFIG_CRYPTO_LIB_AES=y +CONFIG_CRYPTO_LIB_ARC4=y +# CONFIG_CRYPTO_LIB_BLAKE2S is not set +# CONFIG_CRYPTO_LIB_CHACHA is not set +# CONFIG_CRYPTO_LIB_CURVE25519 is not set +CONFIG_CRYPTO_LIB_DES=y +CONFIG_CRYPTO_LIB_POLY1305_RSIZE=11 +# CONFIG_CRYPTO_LIB_POLY1305 is not set +# CONFIG_CRYPTO_LIB_CHACHA20POLY1305 is not set +CONFIG_CRYPTO_LIB_SHA256=y CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_PADLOCK is not set # CONFIG_CRYPTO_DEV_ATMEL_ECC is not set @@ -4309,10 +4420,13 @@ CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_QAT_DH895xCC is not set # CONFIG_CRYPTO_DEV_QAT_C3XXX is not set # CONFIG_CRYPTO_DEV_QAT_C62X is not set +# CONFIG_CRYPTO_DEV_QAT_4XXX is not set # CONFIG_CRYPTO_DEV_QAT_DH895xCCVF is not set # CONFIG_CRYPTO_DEV_QAT_C3XXXVF is not set # CONFIG_CRYPTO_DEV_QAT_C62XVF is not set # CONFIG_CRYPTO_DEV_NITROX_CNN55XX is not set +# CONFIG_CRYPTO_DEV_SAFEXCEL is not set +# CONFIG_CRYPTO_DEV_AMLOGIC_GXL is not set CONFIG_ASYMMETRIC_KEY_TYPE=y CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y CONFIG_X509_CERTIFICATE_PARSER=y @@ -4344,11 +4458,13 @@ CONFIG_GENERIC_STRNLEN_USER=y CONFIG_GENERIC_NET_UTILS=y CONFIG_GENERIC_FIND_FIRST_BIT=y # CONFIG_CORDIC is not set +# CONFIG_PRIME_NUMBERS is not set CONFIG_RATIONAL=y CONFIG_GENERIC_PCI_IOMAP=y CONFIG_GENERIC_IOMAP=y CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y CONFIG_ARCH_HAS_FAST_MULTIPLIER=y +CONFIG_ARCH_USE_SYM_ANNOTATIONS=y CONFIG_CRC_CCITT=y CONFIG_CRC16=y CONFIG_CRC_T10DIF=y @@ -4371,6 +4487,7 @@ CONFIG_ZLIB_DEFLATE=y CONFIG_LZO_COMPRESS=y CONFIG_LZO_DECOMPRESS=y CONFIG_LZ4_DECOMPRESS=y +CONFIG_ZSTD_DECOMPRESS=y CONFIG_XZ_DEC=y CONFIG_XZ_DEC_X86=y CONFIG_XZ_DEC_POWERPC=y @@ -4386,6 +4503,7 @@ CONFIG_DECOMPRESS_LZMA=y CONFIG_DECOMPRESS_XZ=y CONFIG_DECOMPRESS_LZO=y CONFIG_DECOMPRESS_LZ4=y +CONFIG_DECOMPRESS_ZSTD=y CONFIG_GENERIC_ALLOCATOR=y CONFIG_TEXTSEARCH=y CONFIG_TEXTSEARCH_KMP=m @@ -4397,12 +4515,14 @@ CONFIG_ASSOCIATIVE_ARRAY=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT_MAP=y CONFIG_HAS_DMA=y +CONFIG_DMA_OPS=y CONFIG_NEED_SG_DMA_LENGTH=y CONFIG_NEED_DMA_MAP_STATE=y CONFIG_ARCH_DMA_ADDR_T_64BIT=y CONFIG_SWIOTLB=y # CONFIG_DMA_CMA is not set # CONFIG_DMA_API_DEBUG is not set +# CONFIG_DMA_MAP_BENCHMARK is not set CONFIG_SGL_ALLOC=y CONFIG_IOMMU_HELPER=y CONFIG_CHECK_SIGNATURE=y @@ -4414,11 +4534,11 @@ CONFIG_NLATTR=y CONFIG_CLZ_TAB=y # CONFIG_IRQ_POLL is not set CONFIG_MPILIB=y -CONFIG_DIMLIB=y CONFIG_OID_REGISTRY=y CONFIG_UCS2_STRING=y CONFIG_HAVE_GENERIC_VDSO=y CONFIG_GENERIC_GETTIMEOFDAY=y +CONFIG_GENERIC_VDSO_TIME_NS=y CONFIG_FONT_SUPPORT=y # CONFIG_FONTS is not set CONFIG_FONT_8x8=y @@ -4426,7 +4546,7 @@ CONFIG_FONT_8x16=y CONFIG_SG_POOL=y CONFIG_ARCH_HAS_PMEM_API=y CONFIG_ARCH_HAS_UACCESS_FLUSHCACHE=y -CONFIG_ARCH_HAS_UACCESS_MCSAFE=y +CONFIG_ARCH_HAS_COPY_MC=y CONFIG_ARCH_STACKWALK=y CONFIG_SBITMAP=y # CONFIG_STRING_SELFTEST is not set @@ -4446,29 +4566,53 @@ CONFIG_CONSOLE_LOGLEVEL_QUIET=4 CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 # CONFIG_BOOT_PRINTK_DELAY is not set CONFIG_DYNAMIC_DEBUG=y +CONFIG_DYNAMIC_DEBUG_CORE=y +CONFIG_SYMBOLIC_ERRNAME=y +CONFIG_DEBUG_BUGVERBOSE=y # end of printk and dmesg options # # Compile-time checks and compiler options # # CONFIG_DEBUG_INFO is not set -CONFIG_ENABLE_MUST_CHECK=y CONFIG_FRAME_WARN=2048 # CONFIG_STRIP_ASM_SYMS is not set # CONFIG_READABLE_ASM is not set -# CONFIG_UNUSED_SYMBOLS is not set -CONFIG_DEBUG_FS=y # CONFIG_HEADERS_INSTALL is not set -CONFIG_OPTIMIZE_INLINING=y # CONFIG_DEBUG_SECTION_MISMATCH is not set CONFIG_SECTION_MISMATCH_WARN_ONLY=y +# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_32B is not set CONFIG_STACK_VALIDATION=y # CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set # end of Compile-time checks and compiler options +# +# Generic Kernel Debugging Instruments +# CONFIG_MAGIC_SYSRQ=y CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 CONFIG_MAGIC_SYSRQ_SERIAL=y +CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE="" +CONFIG_DEBUG_FS=y +CONFIG_DEBUG_FS_ALLOW_ALL=y +# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set +# CONFIG_DEBUG_FS_ALLOW_NONE is not set +CONFIG_HAVE_ARCH_KGDB=y +CONFIG_KGDB=y +CONFIG_KGDB_HONOUR_BLOCKLIST=y +CONFIG_KGDB_SERIAL_CONSOLE=y +# CONFIG_KGDB_TESTS is not set +CONFIG_KGDB_LOW_LEVEL_TRAP=y +CONFIG_KGDB_KDB=y +CONFIG_KDB_DEFAULT_ENABLE=0x1 +CONFIG_KDB_KEYBOARD=y +CONFIG_KDB_CONTINUE_CATASTROPHIC=0 +CONFIG_ARCH_HAS_EARLY_DEBUG=y +CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y +# CONFIG_UBSAN is not set +CONFIG_HAVE_ARCH_KCSAN=y +# end of Generic Kernel Debugging Instruments + CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_MISC=y @@ -4481,35 +4625,43 @@ CONFIG_DEBUG_MISC=y # CONFIG_PAGE_POISONING is not set # CONFIG_DEBUG_PAGE_REF is not set CONFIG_DEBUG_RODATA_TEST=y +CONFIG_ARCH_HAS_DEBUG_WX=y +# CONFIG_DEBUG_WX is not set +CONFIG_GENERIC_PTDUMP=y +# CONFIG_PTDUMP_DEBUGFS is not set # CONFIG_DEBUG_OBJECTS is not set # CONFIG_SLUB_DEBUG_ON is not set # CONFIG_SLUB_STATS is not set CONFIG_HAVE_DEBUG_KMEMLEAK=y CONFIG_DEBUG_KMEMLEAK=y -CONFIG_DEBUG_KMEMLEAK_EARLY_LOG_SIZE=400 +CONFIG_DEBUG_KMEMLEAK_MEM_POOL_SIZE=16000 # CONFIG_DEBUG_KMEMLEAK_TEST is not set CONFIG_DEBUG_KMEMLEAK_DEFAULT_OFF=y CONFIG_DEBUG_KMEMLEAK_AUTO_SCAN=y # CONFIG_DEBUG_STACK_USAGE is not set +CONFIG_SCHED_STACK_END_CHECK=y +CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y # CONFIG_DEBUG_VM is not set +# CONFIG_DEBUG_VM_PGTABLE is not set CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y # CONFIG_DEBUG_VIRTUAL is not set # CONFIG_DEBUG_MEMORY_INIT is not set # CONFIG_DEBUG_PER_CPU_MAPS is not set +CONFIG_ARCH_SUPPORTS_KMAP_LOCAL_FORCE_MAP=y +# CONFIG_DEBUG_KMAP_LOCAL_FORCE_MAP is not set CONFIG_HAVE_ARCH_KASAN=y +CONFIG_HAVE_ARCH_KASAN_VMALLOC=y CONFIG_CC_HAS_KASAN_GENERIC=y -# CONFIG_KASAN is not set -CONFIG_KASAN_STACK=1 # end of Memory Debugging -CONFIG_ARCH_HAS_KCOV=y -CONFIG_CC_HAS_SANCOV_TRACE_PC=y -# CONFIG_KCOV is not set CONFIG_DEBUG_SHIRQ=y # -# Debug Lockups and Hangs +# Debug Oops, Lockups and Hangs # +# CONFIG_PANIC_ON_OOPS is not set +CONFIG_PANIC_ON_OOPS_VALUE=0 +CONFIG_PANIC_TIMEOUT=0 CONFIG_LOCKUP_DETECTOR=y CONFIG_SOFTLOCKUP_DETECTOR=y # CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set @@ -4524,15 +4676,17 @@ CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120 # CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 # CONFIG_WQ_WATCHDOG is not set -# end of Debug Lockups and Hangs +# CONFIG_TEST_LOCKUP is not set +# end of Debug Oops, Lockups and Hangs -# CONFIG_PANIC_ON_OOPS is not set -CONFIG_PANIC_ON_OOPS_VALUE=0 -CONFIG_PANIC_TIMEOUT=0 +# +# Scheduler Debugging +# CONFIG_SCHED_DEBUG=y CONFIG_SCHED_INFO=y CONFIG_SCHEDSTATS=y -CONFIG_SCHED_STACK_END_CHECK=y +# end of Scheduler Debugging + # CONFIG_DEBUG_TIMEKEEPING is not set # @@ -4540,6 +4694,7 @@ CONFIG_SCHED_STACK_END_CHECK=y # CONFIG_LOCK_DEBUGGING_SUPPORT=y CONFIG_PROVE_LOCKING=y +# CONFIG_PROVE_RAW_LOCK_NESTING is not set # CONFIG_LOCK_STAT is not set CONFIG_DEBUG_RT_MUTEXES=y CONFIG_DEBUG_SPINLOCK=y @@ -4553,25 +4708,35 @@ CONFIG_DEBUG_ATOMIC_SLEEP=y # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set # CONFIG_LOCK_TORTURE_TEST is not set # CONFIG_WW_MUTEX_SELFTEST is not set +# CONFIG_SCF_TORTURE_TEST is not set +# CONFIG_CSD_LOCK_WAIT_DEBUG is not set # end of Lock Debugging (spinlocks, mutexes, etc...) CONFIG_TRACE_IRQFLAGS=y +CONFIG_TRACE_IRQFLAGS_NMI=y CONFIG_STACKTRACE=y # CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set # CONFIG_DEBUG_KOBJECT is not set -CONFIG_DEBUG_BUGVERBOSE=y + +# +# Debug kernel data structures +# # CONFIG_DEBUG_LIST is not set # CONFIG_DEBUG_PLIST is not set # CONFIG_DEBUG_SG is not set # CONFIG_DEBUG_NOTIFIERS is not set +# CONFIG_BUG_ON_DATA_CORRUPTION is not set +# end of Debug kernel data structures + # CONFIG_DEBUG_CREDENTIALS is not set # # RCU Debugging # CONFIG_PROVE_RCU=y -# CONFIG_RCU_PERF_TEST is not set +# CONFIG_RCU_SCALE_TEST is not set # CONFIG_RCU_TORTURE_TEST is not set +# CONFIG_RCU_REF_SCALE_TEST is not set CONFIG_RCU_CPU_STALL_TIMEOUT=60 # CONFIG_RCU_TRACE is not set # CONFIG_RCU_EQS_DEBUG is not set @@ -4580,9 +4745,6 @@ CONFIG_RCU_CPU_STALL_TIMEOUT=60 # CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set -# CONFIG_NOTIFIER_ERROR_INJECTION is not set -CONFIG_FUNCTION_ERROR_INJECTION=y -# CONFIG_FAULT_INJECTION is not set # CONFIG_LATENCYTOP is not set CONFIG_USER_STACKTRACE_SUPPORT=y CONFIG_NOP_TRACER=y @@ -4590,6 +4752,8 @@ CONFIG_HAVE_FUNCTION_TRACER=y CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y CONFIG_HAVE_DYNAMIC_FTRACE=y CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS=y +CONFIG_HAVE_DYNAMIC_FTRACE_WITH_ARGS=y CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y CONFIG_HAVE_SYSCALL_TRACEPOINTS=y CONFIG_HAVE_FENTRY=y @@ -4602,22 +4766,28 @@ CONFIG_CONTEXT_SWITCH_TRACER=y CONFIG_RING_BUFFER_ALLOW_SWAP=y CONFIG_PREEMPTIRQ_TRACEPOINTS=y CONFIG_TRACING=y +CONFIG_GLOBAL_TRACE_BUF_SIZE=1441792 CONFIG_GENERIC_TRACER=y CONFIG_TRACING_SUPPORT=y CONFIG_FTRACE=y +# CONFIG_BOOTTIME_TRACING is not set CONFIG_FUNCTION_TRACER=y CONFIG_FUNCTION_GRAPH_TRACER=y -# CONFIG_PREEMPTIRQ_EVENTS is not set +CONFIG_DYNAMIC_FTRACE=y +CONFIG_DYNAMIC_FTRACE_WITH_REGS=y +CONFIG_DYNAMIC_FTRACE_WITH_DIRECT_CALLS=y +CONFIG_FUNCTION_PROFILER=y +CONFIG_STACK_TRACER=y # CONFIG_IRQSOFF_TRACER is not set CONFIG_SCHED_TRACER=y CONFIG_HWLAT_TRACER=y +CONFIG_MMIOTRACE=y CONFIG_FTRACE_SYSCALLS=y CONFIG_TRACER_SNAPSHOT=y # CONFIG_TRACER_SNAPSHOT_PER_CPU_SWAP is not set CONFIG_BRANCH_PROFILE_NONE=y # CONFIG_PROFILE_ANNOTATED_BRANCHES is not set # CONFIG_PROFILE_ALL_BRANCHES is not set -CONFIG_STACK_TRACER=y CONFIG_BLK_DEV_IO_TRACE=y CONFIG_KPROBE_EVENTS=y # CONFIG_KPROBE_EVENTS_ON_NOTRACE is not set @@ -4625,49 +4795,39 @@ CONFIG_UPROBE_EVENTS=y CONFIG_BPF_EVENTS=y CONFIG_DYNAMIC_EVENTS=y CONFIG_PROBE_EVENTS=y -CONFIG_DYNAMIC_FTRACE=y -CONFIG_DYNAMIC_FTRACE_WITH_REGS=y -CONFIG_FUNCTION_PROFILER=y # CONFIG_BPF_KPROBE_OVERRIDE is not set CONFIG_FTRACE_MCOUNT_RECORD=y -# CONFIG_FTRACE_STARTUP_TEST is not set -CONFIG_MMIOTRACE=y CONFIG_TRACING_MAP=y +CONFIG_SYNTH_EVENTS=y CONFIG_HIST_TRIGGERS=y -# CONFIG_MMIOTRACE_TEST is not set +# CONFIG_TRACE_EVENT_INJECT is not set # CONFIG_TRACEPOINT_BENCHMARK is not set # CONFIG_RING_BUFFER_BENCHMARK is not set +# CONFIG_TRACE_EVAL_MAP_FILE is not set +# CONFIG_FTRACE_RECORD_RECURSION is not set +# CONFIG_FTRACE_STARTUP_TEST is not set # CONFIG_RING_BUFFER_STARTUP_TEST is not set +# CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS is not set +# CONFIG_MMIOTRACE_TEST is not set # CONFIG_PREEMPTIRQ_DELAY_TEST is not set -# CONFIG_TRACE_EVAL_MAP_FILE is not set +# CONFIG_SYNTH_EVENT_GEN_TEST is not set +# CONFIG_KPROBE_EVENT_GEN_TEST is not set +# CONFIG_HIST_TRIGGERS_DEBUG is not set # CONFIG_PROVIDE_OHCI1394_DMA_INIT is not set -# CONFIG_RUNTIME_TESTING_MENU is not set -CONFIG_MEMTEST=y -# CONFIG_BUG_ON_DATA_CORRUPTION is not set # CONFIG_SAMPLES is not set -CONFIG_HAVE_ARCH_KGDB=y -CONFIG_KGDB=y -CONFIG_KGDB_SERIAL_CONSOLE=y -# CONFIG_KGDB_TESTS is not set -CONFIG_KGDB_LOW_LEVEL_TRAP=y -CONFIG_KGDB_KDB=y -CONFIG_KDB_DEFAULT_ENABLE=0x1 -CONFIG_KDB_KEYBOARD=y -CONFIG_KDB_CONTINUE_CATASTROPHIC=0 -CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y -# CONFIG_UBSAN is not set -CONFIG_UBSAN_ALIGNMENT=y CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y # CONFIG_STRICT_DEVMEM is not set + +# +# x86 Debugging +# CONFIG_TRACE_IRQFLAGS_SUPPORT=y +CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y # CONFIG_X86_VERBOSE_BOOTUP is not set CONFIG_EARLY_PRINTK=y # CONFIG_EARLY_PRINTK_DBGP is not set # CONFIG_EARLY_PRINTK_USB_XDBC is not set -# CONFIG_X86_PTDUMP is not set # CONFIG_EFI_PGT_DUMP is not set -# CONFIG_DEBUG_WX is not set -CONFIG_DOUBLEFAULT=y # CONFIG_DEBUG_TLBFLUSH is not set # CONFIG_IOMMU_DEBUG is not set CONFIG_HAVE_MMIOTRACE_SUPPORT=y @@ -4685,4 +4845,19 @@ CONFIG_X86_DEBUG_FPU=y CONFIG_UNWINDER_ORC=y # CONFIG_UNWINDER_FRAME_POINTER is not set # CONFIG_UNWINDER_GUESS is not set +# end of x86 Debugging + +# +# Kernel Testing and Coverage +# +# CONFIG_KUNIT is not set +# CONFIG_NOTIFIER_ERROR_INJECTION is not set +CONFIG_FUNCTION_ERROR_INJECTION=y +# CONFIG_FAULT_INJECTION is not set +CONFIG_ARCH_HAS_KCOV=y +CONFIG_CC_HAS_SANCOV_TRACE_PC=y +# CONFIG_KCOV is not set +# CONFIG_RUNTIME_TESTING_MENU is not set +CONFIG_MEMTEST=y +# end of Kernel Testing and Coverage # end of Kernel hacking From ac014a15e3efbef7c486fabe8fb0f2d1b6e9861c Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Wed, 14 Apr 2021 20:13:19 -0400 Subject: [PATCH 0004/1868] rock-dbg_defconfig: Enable Intel IOMMU Enable the Intel IOMMU driver in the rock-dbg_defconfig. This enables testing of DMA mappings on systems with an Intel IOMMU. Signed-off-by: Felix Kuehling Acked-by: Oak Zeng Acked-by: Ramesh Errabolu Signed-off-by: Alex Deucher --- arch/x86/configs/rock-dbg_defconfig | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/x86/configs/rock-dbg_defconfig b/arch/x86/configs/rock-dbg_defconfig index 55fa96bf27502..32191eaa2556f 100644 --- a/arch/x86/configs/rock-dbg_defconfig +++ b/arch/x86/configs/rock-dbg_defconfig @@ -296,6 +296,7 @@ CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_ARCH_WANT_GENERAL_HUGETLB=y CONFIG_ZONE_DMA32=y CONFIG_AUDIT_ARCH=y +CONFIG_HAVE_INTEL_TXT=y CONFIG_X86_64_SMP=y CONFIG_ARCH_SUPPORTS_UPROBES=y CONFIG_FIX_EARLYCON_MEM=y @@ -3109,6 +3110,7 @@ CONFIG_DRM_AMD_DC_DCN=y # end of Display Engine Configuration CONFIG_HSA_AMD=y +CONFIG_HSA_AMD_SVM=y # CONFIG_DRM_NOUVEAU is not set # CONFIG_DRM_I915 is not set # CONFIG_DRM_VGEM is not set @@ -3767,6 +3769,7 @@ CONFIG_MAILBOX=y CONFIG_PCC=y # CONFIG_ALTERA_MBOX is not set CONFIG_IOMMU_IOVA=y +CONFIG_IOASID=y CONFIG_IOMMU_API=y CONFIG_IOMMU_SUPPORT=y @@ -3780,7 +3783,12 @@ CONFIG_IOMMU_SUPPORT=y CONFIG_IOMMU_DMA=y CONFIG_AMD_IOMMU=y CONFIG_AMD_IOMMU_V2=m -# CONFIG_INTEL_IOMMU is not set +CONFIG_DMAR_TABLE=y +CONFIG_INTEL_IOMMU=y +# CONFIG_INTEL_IOMMU_SVM is not set +CONFIG_INTEL_IOMMU_DEFAULT_ON=y +CONFIG_INTEL_IOMMU_FLOPPY_WA=y +# CONFIG_INTEL_IOMMU_SCALABLE_MODE_DEFAULT_ON is not set # CONFIG_IRQ_REMAP is not set # @@ -4181,6 +4189,7 @@ CONFIG_SECURITY_NETWORK=y CONFIG_PAGE_TABLE_ISOLATION=y # CONFIG_SECURITY_NETWORK_XFRM is not set # CONFIG_SECURITY_PATH is not set +# CONFIG_INTEL_TXT is not set CONFIG_LSM_MMAP_MIN_ADDR=65536 CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y # CONFIG_HARDENED_USERCOPY is not set From 24f7fd108fc01eae99a298a7fb9d4e41eacc5610 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Wed, 7 Jul 2021 17:54:53 -0400 Subject: [PATCH 0005/1868] rock-dbg_defconfig: Update for 5.13 Also build drm as module to make debugging easier. Signed-off-by: Felix Kuehling Signed-off-by: Alex Deucher --- arch/x86/configs/rock-dbg_defconfig | 177 +++++++++++++++++----------- 1 file changed, 108 insertions(+), 69 deletions(-) diff --git a/arch/x86/configs/rock-dbg_defconfig b/arch/x86/configs/rock-dbg_defconfig index 32191eaa2556f..4877da183599f 100644 --- a/arch/x86/configs/rock-dbg_defconfig +++ b/arch/x86/configs/rock-dbg_defconfig @@ -1,12 +1,15 @@ # # Automatically generated file; DO NOT EDIT. -# Linux/x86 5.11.0 Kernel Configuration +# Linux/x86 5.13.0 Kernel Configuration # CONFIG_CC_VERSION_TEXT="gcc (Ubuntu 7.5.0-3ubuntu1~18.04) 7.5.0" CONFIG_CC_IS_GCC=y CONFIG_GCC_VERSION=70500 -CONFIG_LD_VERSION=230000000 CONFIG_CLANG_VERSION=0 +CONFIG_AS_IS_GNU=y +CONFIG_AS_VERSION=23000 +CONFIG_LD_IS_BFD=y +CONFIG_LD_VERSION=23000 CONFIG_LLD_VERSION=0 CONFIG_CC_CAN_LINK=y CONFIG_CC_CAN_LINK_STATIC=y @@ -96,6 +99,19 @@ CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y # end of Timers subsystem +CONFIG_BPF=y +CONFIG_HAVE_EBPF_JIT=y +CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y + +# +# BPF subsystem +# +CONFIG_BPF_SYSCALL=y +# CONFIG_BPF_JIT is not set +# CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set +# CONFIG_BPF_PRELOAD is not set +# end of BPF subsystem + # CONFIG_PREEMPT_NONE is not set CONFIG_PREEMPT_VOLUNTARY=y # CONFIG_PREEMPT is not set @@ -173,6 +189,7 @@ CONFIG_CGROUP_DEVICE=y CONFIG_CGROUP_CPUACCT=y CONFIG_CGROUP_PERF=y CONFIG_CGROUP_BPF=y +# CONFIG_CGROUP_MISC is not set # CONFIG_CGROUP_DEBUG is not set CONFIG_SOCK_CGROUP_DATA=y CONFIG_NAMESPACES=y @@ -203,7 +220,6 @@ CONFIG_SYSCTL=y CONFIG_HAVE_UID16=y CONFIG_SYSCTL_EXCEPTION_TRACE=y CONFIG_HAVE_PCSPKR_PLATFORM=y -CONFIG_BPF=y CONFIG_EXPERT=y CONFIG_UID16=y CONFIG_MULTIUSER=y @@ -232,9 +248,6 @@ CONFIG_KALLSYMS=y CONFIG_KALLSYMS_ALL=y CONFIG_KALLSYMS_ABSOLUTE_PERCPU=y CONFIG_KALLSYMS_BASE_RELATIVE=y -CONFIG_BPF_SYSCALL=y -CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y -# CONFIG_BPF_PRELOAD is not set # CONFIG_USERFAULTFD is not set CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y CONFIG_KCMP=y @@ -253,7 +266,6 @@ CONFIG_PERF_EVENTS=y CONFIG_VM_EVENT_COUNTERS=y CONFIG_SLUB_DEBUG=y -# CONFIG_SLUB_MEMCG_SYSFS_ON is not set # CONFIG_COMPAT_BRK is not set # CONFIG_SLAB is not set CONFIG_SLUB=y @@ -286,7 +298,6 @@ CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y CONFIG_ARCH_MAY_HAVE_PC_FDC=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_ARCH_HAS_CPU_RELAX=y -CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y CONFIG_ARCH_HAS_FILTER_PGPROT=y CONFIG_HAVE_SETUP_PER_CPU_AREA=y CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y @@ -377,7 +388,6 @@ CONFIG_X86_MCE_INTEL=y CONFIG_X86_MCE_AMD=y CONFIG_X86_MCE_THRESHOLD=y # CONFIG_X86_MCE_INJECT is not set -CONFIG_X86_THERMAL_VECTOR=y # # Performance monitoring @@ -469,12 +479,8 @@ CONFIG_HAVE_LIVEPATCH=y # end of Processor type and features CONFIG_ARCH_HAS_ADD_PAGES=y -CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y -CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y +CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y CONFIG_USE_PERCPU_NUMA_NODE_ID=y -CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y -CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y -CONFIG_ARCH_ENABLE_THP_MIGRATION=y # # Power management and ACPI options @@ -511,6 +517,7 @@ CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y # CONFIG_ACPI_DEBUGGER is not set CONFIG_ACPI_SPCR_TABLE=y +# CONFIG_ACPI_FPDT is not set CONFIG_ACPI_LPIT=y CONFIG_ACPI_SLEEP=y CONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y @@ -543,6 +550,7 @@ CONFIG_ACPI_HED=y CONFIG_ACPI_BGRT=y # CONFIG_ACPI_REDUCED_HARDWARE_ONLY is not set # CONFIG_ACPI_NFIT is not set +CONFIG_ACPI_NUMA=y # CONFIG_ACPI_HMAT is not set CONFIG_HAVE_ACPI_APEI=y CONFIG_HAVE_ACPI_APEI_NMI=y @@ -556,7 +564,6 @@ CONFIG_ACPI_APEI_EINJ=m # CONFIG_ACPI_CONFIGFS is not set # CONFIG_PMIC_OPREGION is not set CONFIG_X86_PM_TIMER=y -CONFIG_SFI=y # # CPU Frequency scaling @@ -687,10 +694,6 @@ CONFIG_CRASH_CORE=y CONFIG_KEXEC_CORE=y CONFIG_HOTPLUG_SMT=y CONFIG_GENERIC_ENTRY=y -CONFIG_OPROFILE=m -# CONFIG_OPROFILE_EVENT_MULTIPLEX is not set -CONFIG_HAVE_OPROFILE=y -CONFIG_OPROFILE_NMI_TIMER=y CONFIG_KPROBES=y CONFIG_JUMP_LABEL=y # CONFIG_STATIC_KEYS_SELFTEST is not set @@ -746,6 +749,9 @@ CONFIG_HAVE_ARCH_STACKLEAK=y CONFIG_HAVE_STACKPROTECTOR=y CONFIG_STACKPROTECTOR=y CONFIG_STACKPROTECTOR_STRONG=y +CONFIG_ARCH_SUPPORTS_LTO_CLANG=y +CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y +CONFIG_LTO_NONE=y CONFIG_HAVE_ARCH_WITHIN_STACK_FRAMES=y CONFIG_HAVE_CONTEXT_TRACKING=y CONFIG_HAVE_CONTEXT_TRACKING_OFFSTACK=y @@ -760,6 +766,8 @@ CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y CONFIG_HAVE_ARCH_SOFT_DIRTY=y CONFIG_HAVE_MOD_ARCH_SPECIFIC=y CONFIG_MODULES_USE_ELF_RELA=y +CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y +CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK=y CONFIG_ARCH_HAS_ELF_RANDOMIZE=y CONFIG_HAVE_ARCH_MMAP_RND_BITS=y CONFIG_HAVE_EXIT_THREAD=y @@ -774,6 +782,8 @@ CONFIG_COMPAT_OLD_SIGACTION=y CONFIG_COMPAT_32BIT_TIME=y CONFIG_HAVE_ARCH_VMAP_STACK=y CONFIG_VMAP_STACK=y +CONFIG_HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET=y +# CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT is not set CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y CONFIG_STRICT_KERNEL_RWX=y CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y @@ -784,8 +794,10 @@ CONFIG_ARCH_USE_MEMREMAP_PROT=y CONFIG_ARCH_HAS_MEM_ENCRYPT=y CONFIG_HAVE_STATIC_CALL=y CONFIG_HAVE_STATIC_CALL_INLINE=y +CONFIG_HAVE_PREEMPT_DYNAMIC=y CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y +CONFIG_ARCH_HAS_ELFCORE_COMPAT=y # # GCOV-based kernel profiling @@ -816,9 +828,12 @@ CONFIG_MODULE_SIG_ALL=y # CONFIG_MODULE_SIG_SHA384 is not set CONFIG_MODULE_SIG_SHA512=y CONFIG_MODULE_SIG_HASH="sha512" -# CONFIG_MODULE_COMPRESS is not set +CONFIG_MODULE_COMPRESS_NONE=y +# CONFIG_MODULE_COMPRESS_GZIP is not set +# CONFIG_MODULE_COMPRESS_XZ is not set +# CONFIG_MODULE_COMPRESS_ZSTD is not set # CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set -# CONFIG_UNUSED_SYMBOLS is not set +CONFIG_MODPROBE_PATH="/sbin/modprobe" # CONFIG_TRIM_UNUSED_KSYMS is not set CONFIG_MODULES_TREE_LOOKUP=y CONFIG_BLOCK=y @@ -917,17 +932,22 @@ CONFIG_HAVE_FAST_GUP=y CONFIG_NUMA_KEEP_MEMINFO=y CONFIG_MEMORY_ISOLATION=y CONFIG_HAVE_BOOTMEM_INFO_NODE=y +CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y CONFIG_MEMORY_HOTPLUG=y CONFIG_MEMORY_HOTPLUG_SPARSE=y # CONFIG_MEMORY_HOTPLUG_DEFAULT_ONLINE is not set +CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y CONFIG_MEMORY_HOTREMOVE=y +CONFIG_MHP_MEMMAP_ON_MEMORY=y CONFIG_SPLIT_PTLOCK_CPUS=4 +CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y CONFIG_COMPACTION=y # CONFIG_PAGE_REPORTING is not set CONFIG_MIGRATION=y +CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y +CONFIG_ARCH_ENABLE_THP_MIGRATION=y CONFIG_CONTIG_ALLOC=y CONFIG_PHYS_ADDR_T_64BIT=y -CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y CONFIG_MMU_NOTIFIER=y CONFIG_KSM=y @@ -945,6 +965,7 @@ CONFIG_FRONTSWAP=y CONFIG_CMA=y # CONFIG_CMA_DEBUG is not set # CONFIG_CMA_DEBUGFS is not set +# CONFIG_CMA_SYSFS is not set CONFIG_CMA_AREAS=7 CONFIG_MEM_SOFT_DIRTY=y CONFIG_ZSWAP=y @@ -968,6 +989,7 @@ CONFIG_ZSMALLOC=y CONFIG_GENERIC_EARLY_IOREMAP=y # CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set # CONFIG_IDLE_PAGE_TRACKING is not set +CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y CONFIG_ARCH_HAS_PTE_DEVMAP=y CONFIG_ZONE_DEVICE=y CONFIG_DEV_PAGEMAP_OPS=y @@ -1101,8 +1123,7 @@ CONFIG_NETFILTER_NETLINK_QUEUE=m CONFIG_NETFILTER_NETLINK_LOG=m CONFIG_NETFILTER_NETLINK_OSF=m CONFIG_NF_CONNTRACK=m -CONFIG_NF_LOG_COMMON=m -# CONFIG_NF_LOG_NETDEV is not set +CONFIG_NF_LOG_SYSLOG=m CONFIG_NETFILTER_CONNCOUNT=m CONFIG_NF_CONNTRACK_MARK=y CONFIG_NF_CONNTRACK_SECMARK=y @@ -1163,6 +1184,7 @@ CONFIG_NF_DUP_NETDEV=m # CONFIG_NFT_REJECT_NETDEV is not set # CONFIG_NF_FLOW_TABLE is not set CONFIG_NETFILTER_XTABLES=m +CONFIG_NETFILTER_XTABLES_COMPAT=y # # Xtables combined modules @@ -1344,7 +1366,6 @@ CONFIG_BRIDGE_IGMP_SNOOPING=y # CONFIG_BRIDGE_VLAN_FILTERING is not set # CONFIG_BRIDGE_MRP is not set # CONFIG_BRIDGE_CFM is not set -CONFIG_HAVE_NET_DSA=y # CONFIG_NET_DSA is not set CONFIG_VLAN_8021Q=y # CONFIG_VLAN_8021Q_GVRP is not set @@ -1454,14 +1475,15 @@ CONFIG_NETLINK_DIAG=y # CONFIG_NET_L3_MASTER_DEV is not set # CONFIG_QRTR is not set # CONFIG_NET_NCSI is not set +CONFIG_PCPU_DEV_REFCNT=y CONFIG_RPS=y CONFIG_RFS_ACCEL=y +CONFIG_SOCK_RX_QUEUE_MAPPING=y CONFIG_XPS=y # CONFIG_CGROUP_NET_PRIO is not set CONFIG_CGROUP_NET_CLASSID=y CONFIG_NET_RX_BUSY_POLL=y CONFIG_BQL=y -# CONFIG_BPF_JIT is not set # CONFIG_BPF_STREAM_PARSER is not set CONFIG_NET_FLOW_LIMIT=y @@ -1503,9 +1525,10 @@ CONFIG_RFKILL_INPUT=y # CONFIG_LWTUNNEL is not set CONFIG_DST_CACHE=y CONFIG_GRO_CELLS=y +CONFIG_NET_SELFTESTS=y +CONFIG_NET_SOCK_MSG=y # CONFIG_FAILOVER is not set CONFIG_ETHTOOL_NETLINK=y -CONFIG_HAVE_EBPF_JIT=y # # Device Drivers @@ -1528,7 +1551,6 @@ CONFIG_PCIEASPM_DEFAULT=y CONFIG_PCIE_PME=y # CONFIG_PCIE_DPC is not set # CONFIG_PCIE_PTM is not set -# CONFIG_PCIE_BW is not set CONFIG_PCI_MSI=y CONFIG_PCI_MSI_IRQ_DOMAIN=y CONFIG_PCI_QUIRKS=y @@ -1588,6 +1610,7 @@ CONFIG_HOTPLUG_PCI=y # CONFIG_PCI_SW_SWITCHTEC is not set # end of PCI switch controller drivers +# CONFIG_CXL_BUS is not set # CONFIG_PCCARD is not set CONFIG_RAPIDIO=y # CONFIG_RAPIDIO_TSI721 is not set @@ -1672,13 +1695,11 @@ CONFIG_CDROM=y # CONFIG_PARIDE is not set # CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set # CONFIG_ZRAM is not set -# CONFIG_BLK_DEV_UMEM is not set CONFIG_BLK_DEV_LOOP=y CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 # CONFIG_BLK_DEV_CRYPTOLOOP is not set # CONFIG_BLK_DEV_DRBD is not set # CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_SKD is not set # CONFIG_BLK_DEV_SX8 is not set CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=16 @@ -1720,9 +1741,9 @@ CONFIG_BLK_DEV_NVME=y # CONFIG_HMC6352 is not set # CONFIG_DS1682 is not set # CONFIG_SRAM is not set +# CONFIG_DW_XDATA_PCIE is not set # CONFIG_PCI_ENDPOINT_TEST is not set # CONFIG_XILINX_SDFEC is not set -# CONFIG_PVPANIC is not set # CONFIG_C2PORT is not set # @@ -1751,11 +1772,13 @@ CONFIG_BLK_DEV_NVME=y # CONFIG_VMWARE_VMCI is not set # CONFIG_GENWQE is not set # CONFIG_ECHO is not set +# CONFIG_BCM_VK is not set # CONFIG_MISC_ALCOR_PCI is not set # CONFIG_MISC_RTSX_PCI is not set # CONFIG_MISC_RTSX_USB is not set # CONFIG_HABANA_AI is not set # CONFIG_UACCE is not set +# CONFIG_PVPANIC is not set # end of Misc devices CONFIG_HAVE_IDE=y @@ -1974,12 +1997,6 @@ CONFIG_NET_POLL_CONTROLLER=y CONFIG_VETH=y # CONFIG_NLMON is not set # CONFIG_ARCNET is not set - -# -# Distributed Switch Architecture drivers -# -# end of Distributed Switch Architecture drivers - CONFIG_ETHERNET=y CONFIG_MDIO=y CONFIG_NET_VENDOR_3COM=y @@ -2009,7 +2026,6 @@ CONFIG_NET_VENDOR_ATHEROS=y # CONFIG_ATL1E is not set # CONFIG_ATL1C is not set CONFIG_ALX=y -# CONFIG_NET_VENDOR_AURORA is not set CONFIG_NET_VENDOR_BROADCOM=y # CONFIG_B44 is not set # CONFIG_BCMGENET is not set @@ -2078,6 +2094,7 @@ CONFIG_I40E=y # CONFIG_ICE is not set # CONFIG_FM10K is not set # CONFIG_IGC is not set +CONFIG_NET_VENDOR_MICROSOFT=y # CONFIG_JME is not set CONFIG_NET_VENDOR_MARVELL=y # CONFIG_MVMDIO is not set @@ -2181,6 +2198,7 @@ CONFIG_WIZNET_W5300=y # CONFIG_WIZNET_BUS_INDIRECT is not set CONFIG_WIZNET_BUS_ANY=y CONFIG_NET_VENDOR_XILINX=y +# CONFIG_XILINX_EMACLITE is not set # CONFIG_XILINX_AXI_EMAC is not set # CONFIG_XILINX_LL_TEMAC is not set CONFIG_FDDI=y @@ -2213,11 +2231,13 @@ CONFIG_AMD_PHY=y # CONFIG_LSI_ET1011C_PHY is not set # CONFIG_MARVELL_PHY is not set # CONFIG_MARVELL_10G_PHY is not set +# CONFIG_MARVELL_88X2222_PHY is not set # CONFIG_MICREL_PHY is not set # CONFIG_MICROCHIP_PHY is not set # CONFIG_MICROCHIP_T1_PHY is not set # CONFIG_MICROSEMI_PHY is not set # CONFIG_NATIONAL_PHY is not set +# CONFIG_NXP_C45_TJA11XX_PHY is not set # CONFIG_NXP_TJA11XX_PHY is not set # CONFIG_QSEMI_PHY is not set CONFIG_REALTEK_PHY=y @@ -2323,6 +2343,7 @@ CONFIG_WLAN_VENDOR_TI=y CONFIG_WLAN_VENDOR_ZYDAS=y CONFIG_WLAN_VENDOR_QUANTENNA=y # CONFIG_WAN is not set +# CONFIG_WWAN is not set # CONFIG_VMXNET3 is not set # CONFIG_FUJITSU_ES is not set # CONFIG_NETDEVSIM is not set @@ -2489,17 +2510,13 @@ CONFIG_CONSOLE_POLL=y # end of Serial drivers CONFIG_SERIAL_NONSTANDARD=y -# CONFIG_ROCKETPORT is not set -# CONFIG_CYCLADES is not set # CONFIG_MOXA_INTELLIO is not set # CONFIG_MOXA_SMARTIO is not set # CONFIG_SYNCLINK_GT is not set -# CONFIG_ISI is not set # CONFIG_N_HDLC is not set # CONFIG_N_GSM is not set # CONFIG_NOZOMI is not set # CONFIG_NULL_TTY is not set -# CONFIG_TRACE_SINK is not set # CONFIG_SERIAL_DEV_BUS is not set # CONFIG_TTY_PRINTK is not set # CONFIG_PRINTER is not set @@ -2510,7 +2527,6 @@ CONFIG_SERIAL_NONSTANDARD=y # CONFIG_APPLICOM is not set # CONFIG_MWAVE is not set CONFIG_DEVMEM=y -# CONFIG_DEVKMEM is not set # CONFIG_NVRAM is not set # CONFIG_RAW_DRIVER is not set CONFIG_DEVPORT=y @@ -2582,6 +2598,7 @@ CONFIG_I2C_PIIX4=m # External I2C/SMBus adapter drivers # # CONFIG_I2C_DIOLAN_U2C is not set +# CONFIG_I2C_CP2615 is not set # CONFIG_I2C_PARPORT is not set # CONFIG_I2C_ROBOTFUZZ_OSIF is not set # CONFIG_I2C_TAOS_EVM is not set @@ -2682,9 +2699,11 @@ CONFIG_POWER_SUPPLY_HWMON=y # CONFIG_BATTERY_MAX17042 is not set # CONFIG_CHARGER_MAX8903 is not set # CONFIG_CHARGER_LP8727 is not set +# CONFIG_CHARGER_LTC4162L is not set # CONFIG_CHARGER_BQ2415X is not set # CONFIG_CHARGER_SMB347 is not set # CONFIG_BATTERY_GAUGE_LTC2941 is not set +# CONFIG_BATTERY_GOLDFISH is not set # CONFIG_CHARGER_BD99954 is not set CONFIG_HWMON=y # CONFIG_HWMON_DEBUG_CHIP is not set @@ -2708,13 +2727,13 @@ CONFIG_HWMON=y # CONFIG_SENSORS_ADT7462 is not set # CONFIG_SENSORS_ADT7470 is not set # CONFIG_SENSORS_ADT7475 is not set +# CONFIG_SENSORS_AHT10 is not set # CONFIG_SENSORS_AS370 is not set # CONFIG_SENSORS_ASC7621 is not set # CONFIG_SENSORS_AXI_FAN_CONTROL is not set # CONFIG_SENSORS_K8TEMP is not set CONFIG_SENSORS_K10TEMP=m # CONFIG_SENSORS_FAM15H_POWER is not set -# CONFIG_SENSORS_AMD_ENERGY is not set # CONFIG_SENSORS_APPLESMC is not set # CONFIG_SENSORS_ASB100 is not set # CONFIG_SENSORS_ASPEED is not set @@ -2765,6 +2784,7 @@ CONFIG_SENSORS_DELL_SMM=m # CONFIG_SENSORS_MAX31790 is not set # CONFIG_SENSORS_MCP3021 is not set # CONFIG_SENSORS_TC654 is not set +# CONFIG_SENSORS_TPS23861 is not set # CONFIG_SENSORS_MR75203 is not set # CONFIG_SENSORS_LM63 is not set # CONFIG_SENSORS_LM73 is not set @@ -2789,6 +2809,7 @@ CONFIG_SENSORS_DELL_SMM=m # CONFIG_SENSORS_NCT7802 is not set # CONFIG_SENSORS_NCT7904 is not set # CONFIG_SENSORS_NPCM7XX is not set +# CONFIG_SENSORS_NZXT_KRAKEN2 is not set # CONFIG_SENSORS_PCF8591 is not set # CONFIG_PMBUS is not set # CONFIG_SENSORS_SBTSI is not set @@ -2861,6 +2882,7 @@ CONFIG_THERMAL_GOV_USER_SPACE=y # Intel thermal drivers # # CONFIG_INTEL_POWERCLAMP is not set +CONFIG_X86_THERMAL_VECTOR=y CONFIG_X86_PKG_TEMP_THERMAL=m # CONFIG_INTEL_SOC_DTS_THERMAL is not set @@ -2871,6 +2893,7 @@ CONFIG_X86_PKG_TEMP_THERMAL=m # end of ACPI INT340X thermal drivers # CONFIG_INTEL_PCH_THERMAL is not set +# CONFIG_INTEL_TCC_COOLING is not set # end of Intel thermal drivers CONFIG_WATCHDOG=y @@ -2995,7 +3018,6 @@ CONFIG_BCMA_POSSIBLE=y # CONFIG_MFD_SI476X_CORE is not set # CONFIG_MFD_SM501 is not set # CONFIG_MFD_SKY81452 is not set -# CONFIG_ABX500_CORE is not set # CONFIG_MFD_SYSCON is not set # CONFIG_MFD_TI_AM335X_TSCADC is not set # CONFIG_MFD_LP3943 is not set @@ -3021,6 +3043,7 @@ CONFIG_BCMA_POSSIBLE=y # CONFIG_MFD_WM831X_I2C is not set # CONFIG_MFD_WM8350_I2C is not set # CONFIG_MFD_WM8994 is not set +# CONFIG_MFD_ATC260X_I2C is not set # end of Multifunction device drivers # CONFIG_REGULATOR is not set @@ -3055,12 +3078,10 @@ CONFIG_INTEL_GTT=y CONFIG_VGA_ARB=y CONFIG_VGA_ARB_MAX_GPUS=16 # CONFIG_VGA_SWITCHEROO is not set -CONFIG_DRM=y +CONFIG_DRM=m # CONFIG_DRM_DP_AUX_CHARDEV is not set -# CONFIG_DRM_DEBUG_MM is not set # CONFIG_DRM_DEBUG_SELFTEST is not set -CONFIG_DRM_KMS_HELPER=y -CONFIG_DRM_KMS_FB_HELPER=y +CONFIG_DRM_KMS_HELPER=m # CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set CONFIG_DRM_FBDEV_EMULATION=y CONFIG_DRM_FBDEV_OVERALLOC=100 @@ -3142,9 +3163,11 @@ CONFIG_DRM_PANEL_BRIDGE=y # CONFIG_DRM_ETNAVIV is not set # CONFIG_DRM_CIRRUS_QEMU is not set # CONFIG_DRM_GM12U320 is not set +# CONFIG_DRM_SIMPLEDRM is not set # CONFIG_DRM_VBOXVIDEO is not set +# CONFIG_DRM_GUD is not set # CONFIG_DRM_LEGACY is not set -CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=y +CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=m # # Frame buffer Devices @@ -3153,14 +3176,14 @@ CONFIG_FB_CMDLINE=y CONFIG_FB_NOTIFY=y CONFIG_FB=y # CONFIG_FIRMWARE_EDID is not set -CONFIG_FB_CFB_FILLRECT=y -CONFIG_FB_CFB_COPYAREA=y -CONFIG_FB_CFB_IMAGEBLIT=y -CONFIG_FB_SYS_FILLRECT=y -CONFIG_FB_SYS_COPYAREA=y -CONFIG_FB_SYS_IMAGEBLIT=y +CONFIG_FB_CFB_FILLRECT=m +CONFIG_FB_CFB_COPYAREA=m +CONFIG_FB_CFB_IMAGEBLIT=m +CONFIG_FB_SYS_FILLRECT=m +CONFIG_FB_SYS_COPYAREA=m +CONFIG_FB_SYS_IMAGEBLIT=m # CONFIG_FB_FOREIGN_ENDIAN is not set -CONFIG_FB_SYS_FOPS=y +CONFIG_FB_SYS_FOPS=m CONFIG_FB_DEFERRED_IO=y # CONFIG_FB_MODE_HELPERS is not set # CONFIG_FB_TILEBLITTING is not set @@ -3284,6 +3307,7 @@ CONFIG_HID_CYPRESS=y # CONFIG_HID_ELECOM is not set # CONFIG_HID_ELO is not set CONFIG_HID_EZKEY=y +# CONFIG_HID_FT260 is not set # CONFIG_HID_GEMBIRD is not set # CONFIG_HID_GFRM is not set # CONFIG_HID_GLORIOUS is not set @@ -3326,11 +3350,13 @@ CONFIG_HID_MONTEREY=y # CONFIG_HID_PETALYNX is not set # CONFIG_HID_PICOLCD is not set CONFIG_HID_PLANTRONICS=y +# CONFIG_HID_PLAYSTATION is not set # CONFIG_HID_PRIMAX is not set # CONFIG_HID_RETRODE is not set # CONFIG_HID_ROCCAT is not set # CONFIG_HID_SAITEK is not set # CONFIG_HID_SAMSUNG is not set +# CONFIG_HID_SEMITEK is not set # CONFIG_HID_SONY is not set # CONFIG_HID_SPEEDLINK is not set # CONFIG_HID_STEAM is not set @@ -3364,7 +3390,7 @@ CONFIG_USB_HIDDEV=y # # I2C HID support # -# CONFIG_I2C_HID is not set +# CONFIG_I2C_HID_ACPI is not set # end of I2C HID support # @@ -3467,7 +3493,7 @@ CONFIG_USB_STORAGE=y # CONFIG_USB_MDC800 is not set # CONFIG_USB_MICROTEK is not set # CONFIG_USBIP_CORE is not set -# CONFIG_USB_CDNS3 is not set +# CONFIG_USB_CDNS_SUPPORT is not set # CONFIG_USB_MUSB_HDRC is not set # CONFIG_USB_DWC3 is not set # CONFIG_USB_DWC2 is not set @@ -3580,6 +3606,7 @@ CONFIG_LEDS_TRIGGERS=y # CONFIG_LEDS_TRIGGER_NETDEV is not set # CONFIG_LEDS_TRIGGER_PATTERN is not set # CONFIG_LEDS_TRIGGER_AUDIO is not set +# CONFIG_LEDS_TRIGGER_TTY is not set # CONFIG_ACCESSIBILITY is not set # CONFIG_INFINIBAND is not set CONFIG_EDAC_ATOMIC_SCRUB=y @@ -3675,6 +3702,7 @@ CONFIG_RTC_DRV_CMOS=y # # HID Sensor RTC drivers # +# CONFIG_RTC_DRV_GOLDFISH is not set CONFIG_DMADEVICES=y # CONFIG_DMADEVICES_DEBUG is not set @@ -3688,7 +3716,6 @@ CONFIG_DMA_ACPI=y # CONFIG_INTEL_IDXD is not set # CONFIG_INTEL_IOATDMA is not set # CONFIG_PLX_DMA is not set -# CONFIG_XILINX_ZYNQMP_DPDMA is not set # CONFIG_QCOM_HIDMA_MGMT is not set # CONFIG_QCOM_HIDMA is not set CONFIG_DW_DMAC_CORE=y @@ -3697,6 +3724,7 @@ CONFIG_DW_DMAC_PCI=y # CONFIG_DW_EDMA is not set # CONFIG_DW_EDMA_PCIE is not set # CONFIG_SF_PDMA is not set +# CONFIG_INTEL_LDMA is not set # # DMA Clients @@ -3736,6 +3764,7 @@ CONFIG_VHOST_MENU=y # end of Microsoft Hyper-V guest support # CONFIG_GREYBUS is not set +# CONFIG_COMEDI is not set # CONFIG_STAGING is not set # CONFIG_X86_PLATFORM_DEVICES is not set CONFIG_PMC_ATOM=y @@ -3755,6 +3784,7 @@ CONFIG_COMMON_CLK=y # CONFIG_COMMON_CLK_SI544 is not set # CONFIG_COMMON_CLK_CDCE706 is not set # CONFIG_COMMON_CLK_CS2000_CP is not set +# CONFIG_XILINX_VCU is not set # CONFIG_HWSPINLOCK is not set # @@ -3776,6 +3806,7 @@ CONFIG_IOMMU_SUPPORT=y # # Generic IOMMU Pagetable Support # +CONFIG_IOMMU_IO_PGTABLE=y # end of Generic IOMMU Pagetable Support # CONFIG_IOMMU_DEBUGFS is not set @@ -3845,7 +3876,6 @@ CONFIG_INTEL_IOMMU_FLOPPY_WA=y # # Xilinx SoC drivers # -# CONFIG_XILINX_VCU is not set # end of Xilinx SoC drivers # end of SOC (System On Chip) specific Drivers @@ -3897,9 +3927,9 @@ CONFIG_RAS=y # CONFIG_LIBNVDIMM is not set CONFIG_DAX=y # CONFIG_DEV_DAX is not set -# CONFIG_DEV_DAX_HMEM is not set CONFIG_NVMEM=y CONFIG_NVMEM_SYSFS=y +# CONFIG_NVMEM_RMEM is not set # # HW tracing support @@ -3984,6 +4014,8 @@ CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y # # Caches # +CONFIG_NETFS_SUPPORT=y +# CONFIG_NETFS_STATS is not set CONFIG_FSCACHE=y # CONFIG_FSCACHE_STATS is not set # CONFIG_FSCACHE_HISTOGRAM is not set @@ -4210,6 +4242,7 @@ CONFIG_SECURITY_SELINUX_SID2STR_CACHE_SIZE=256 # CONFIG_SECURITY_YAMA is not set # CONFIG_SECURITY_SAFESETID is not set # CONFIG_SECURITY_LOCKDOWN_LSM is not set +# CONFIG_SECURITY_LANDLOCK is not set CONFIG_INTEGRITY=y # CONFIG_INTEGRITY_SIGNATURE is not set CONFIG_INTEGRITY_AUDIT=y @@ -4272,6 +4305,7 @@ CONFIG_CRYPTO_AUTHENC=y CONFIG_CRYPTO_RSA=y # CONFIG_CRYPTO_DH is not set # CONFIG_CRYPTO_ECDH is not set +# CONFIG_CRYPTO_ECDSA is not set # CONFIG_CRYPTO_ECRDSA is not set # CONFIG_CRYPTO_SM2 is not set # CONFIG_CRYPTO_CURVE25519 is not set @@ -4333,10 +4367,7 @@ CONFIG_CRYPTO_GHASH=y CONFIG_CRYPTO_MD4=y CONFIG_CRYPTO_MD5=y # CONFIG_CRYPTO_MICHAEL_MIC is not set -# CONFIG_CRYPTO_RMD128 is not set # CONFIG_CRYPTO_RMD160 is not set -# CONFIG_CRYPTO_RMD256 is not set -# CONFIG_CRYPTO_RMD320 is not set CONFIG_CRYPTO_SHA1=y # CONFIG_CRYPTO_SHA1_SSSE3 is not set # CONFIG_CRYPTO_SHA256_SSSE3 is not set @@ -4346,7 +4377,6 @@ CONFIG_CRYPTO_SHA512=y # CONFIG_CRYPTO_SHA3 is not set # CONFIG_CRYPTO_SM3 is not set # CONFIG_CRYPTO_STREEBOG is not set -# CONFIG_CRYPTO_TGR192 is not set # CONFIG_CRYPTO_WP512 is not set # CONFIG_CRYPTO_GHASH_CLMUL_NI_INTEL is not set @@ -4369,7 +4399,6 @@ CONFIG_CRYPTO_AES=y CONFIG_CRYPTO_DES=y # CONFIG_CRYPTO_DES3_EDE_X86_64 is not set # CONFIG_CRYPTO_FCRYPT is not set -# CONFIG_CRYPTO_SALSA20 is not set # CONFIG_CRYPTO_CHACHA20 is not set # CONFIG_CRYPTO_CHACHA20_X86_64 is not set # CONFIG_CRYPTO_SERPENT is not set @@ -4592,6 +4621,7 @@ CONFIG_FRAME_WARN=2048 CONFIG_SECTION_MISMATCH_WARN_ONLY=y # CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_32B is not set CONFIG_STACK_VALIDATION=y +# CONFIG_VMLINUX_MAP is not set # CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set # end of Compile-time checks and compiler options @@ -4661,6 +4691,8 @@ CONFIG_ARCH_SUPPORTS_KMAP_LOCAL_FORCE_MAP=y CONFIG_HAVE_ARCH_KASAN=y CONFIG_HAVE_ARCH_KASAN_VMALLOC=y CONFIG_CC_HAS_KASAN_GENERIC=y +CONFIG_HAVE_ARCH_KFENCE=y +# CONFIG_KFENCE is not set # end of Memory Debugging CONFIG_DEBUG_SHIRQ=y @@ -4712,6 +4744,11 @@ CONFIG_DEBUG_WW_MUTEX_SLOWPATH=y CONFIG_DEBUG_RWSEMS=y CONFIG_DEBUG_LOCK_ALLOC=y CONFIG_LOCKDEP=y +CONFIG_LOCKDEP_BITS=15 +CONFIG_LOCKDEP_CHAINS_BITS=16 +CONFIG_LOCKDEP_STACK_TRACE_BITS=19 +CONFIG_LOCKDEP_STACK_TRACE_HASH_BITS=14 +CONFIG_LOCKDEP_CIRCULAR_QUEUE_BITS=12 # CONFIG_DEBUG_LOCKDEP is not set CONFIG_DEBUG_ATOMIC_SLEEP=y # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set @@ -4723,6 +4760,7 @@ CONFIG_DEBUG_ATOMIC_SLEEP=y CONFIG_TRACE_IRQFLAGS=y CONFIG_TRACE_IRQFLAGS_NMI=y +# CONFIG_DEBUG_IRQFLAGS is not set CONFIG_STACKTRACE=y # CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set # CONFIG_DEBUG_KOBJECT is not set @@ -4766,16 +4804,15 @@ CONFIG_HAVE_DYNAMIC_FTRACE_WITH_ARGS=y CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y CONFIG_HAVE_SYSCALL_TRACEPOINTS=y CONFIG_HAVE_FENTRY=y +CONFIG_HAVE_OBJTOOL_MCOUNT=y CONFIG_HAVE_C_RECORDMCOUNT=y CONFIG_TRACER_MAX_TRACE=y CONFIG_TRACE_CLOCK=y CONFIG_RING_BUFFER=y CONFIG_EVENT_TRACING=y CONFIG_CONTEXT_SWITCH_TRACER=y -CONFIG_RING_BUFFER_ALLOW_SWAP=y CONFIG_PREEMPTIRQ_TRACEPOINTS=y CONFIG_TRACING=y -CONFIG_GLOBAL_TRACE_BUF_SIZE=1441792 CONFIG_GENERIC_TRACER=y CONFIG_TRACING_SUPPORT=y CONFIG_FTRACE=y @@ -4806,6 +4843,7 @@ CONFIG_DYNAMIC_EVENTS=y CONFIG_PROBE_EVENTS=y # CONFIG_BPF_KPROBE_OVERRIDE is not set CONFIG_FTRACE_MCOUNT_RECORD=y +CONFIG_FTRACE_MCOUNT_USE_CC=y CONFIG_TRACING_MAP=y CONFIG_SYNTH_EVENTS=y CONFIG_HIST_TRIGGERS=y @@ -4867,6 +4905,7 @@ CONFIG_ARCH_HAS_KCOV=y CONFIG_CC_HAS_SANCOV_TRACE_PC=y # CONFIG_KCOV is not set # CONFIG_RUNTIME_TESTING_MENU is not set +CONFIG_ARCH_USE_MEMTEST=y CONFIG_MEMTEST=y # end of Kernel Testing and Coverage # end of Kernel hacking From f8caba3c07cd52724c20a30d9a943ab32e4c7e28 Mon Sep 17 00:00:00 2001 From: Rajneesh Bhardwaj Date: Thu, 25 Feb 2021 15:54:30 -0500 Subject: [PATCH 0006/1868] x86/configs: CRIU update debug rock defconfig - Update debug config for Checkpoint-Restore (CR) support - Also include necessary options for CR with docker containers. Reviewed-by: Felix Kuehling Signed-off-by: Rajneesh Bhardwaj Signed-off-by: Alex Deucher --- arch/x86/configs/rock-dbg_defconfig | 53 ++++++++++++++++++----------- 1 file changed, 34 insertions(+), 19 deletions(-) diff --git a/arch/x86/configs/rock-dbg_defconfig b/arch/x86/configs/rock-dbg_defconfig index 4877da183599f..bc2a34666c1d9 100644 --- a/arch/x86/configs/rock-dbg_defconfig +++ b/arch/x86/configs/rock-dbg_defconfig @@ -249,6 +249,7 @@ CONFIG_KALLSYMS_ALL=y CONFIG_KALLSYMS_ABSOLUTE_PERCPU=y CONFIG_KALLSYMS_BASE_RELATIVE=y # CONFIG_USERFAULTFD is not set +CONFIG_USERFAULTFD=y CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y CONFIG_KCMP=y CONFIG_RSEQ=y @@ -1015,6 +1016,11 @@ CONFIG_PACKET_DIAG=y CONFIG_UNIX=y CONFIG_UNIX_SCM=y CONFIG_UNIX_DIAG=y +CONFIG_SMC_DIAG=y +CONFIG_XDP_SOCKETS_DIAG=y +CONFIG_INET_MPTCP_DIAG=y +CONFIG_TIPC_DIAG=y +CONFIG_VSOCKETS_DIAG=y # CONFIG_TLS is not set CONFIG_XFRM=y CONFIG_XFRM_ALGO=y @@ -1052,15 +1058,17 @@ CONFIG_SYN_COOKIES=y # CONFIG_NET_IPVTI is not set # CONFIG_NET_FOU is not set # CONFIG_NET_FOU_IP_TUNNELS is not set -# CONFIG_INET_AH is not set -# CONFIG_INET_ESP is not set -# CONFIG_INET_IPCOMP is not set -CONFIG_INET_TUNNEL=y -CONFIG_INET_DIAG=y -CONFIG_INET_TCP_DIAG=y -# CONFIG_INET_UDP_DIAG is not set -# CONFIG_INET_RAW_DIAG is not set -# CONFIG_INET_DIAG_DESTROY is not set +CONFIG_INET_AH=m +CONFIG_INET_ESP=m +CONFIG_INET_IPCOMP=m +CONFIG_INET_ESP_OFFLOAD=m +CONFIG_INET_TUNNEL=m +CONFIG_INET_XFRM_TUNNEL=m +CONFIG_INET_DIAG=m +CONFIG_INET_TCP_DIAG=m +CONFIG_INET_UDP_DIAG=m +CONFIG_INET_RAW_DIAG=m +CONFIG_INET_DIAG_DESTROY=y CONFIG_TCP_CONG_ADVANCED=y # CONFIG_TCP_CONG_BIC is not set CONFIG_TCP_CONG_CUBIC=y @@ -1085,12 +1093,14 @@ CONFIG_TCP_MD5SIG=y CONFIG_IPV6=y # CONFIG_IPV6_ROUTER_PREF is not set # CONFIG_IPV6_OPTIMISTIC_DAD is not set -CONFIG_INET6_AH=y -CONFIG_INET6_ESP=y -# CONFIG_INET6_ESP_OFFLOAD is not set -# CONFIG_INET6_ESPINTCP is not set -# CONFIG_INET6_IPCOMP is not set -# CONFIG_IPV6_MIP6 is not set +CONFIG_INET6_AH=m +CONFIG_INET6_ESP=m +CONFIG_INET6_ESP_OFFLOAD=m +CONFIG_INET6_IPCOMP=m +CONFIG_IPV6_MIP6=m +CONFIG_INET6_XFRM_TUNNEL=m +CONFIG_INET_DCCP_DIAG=m +CONFIG_INET_SCTP_DIAG=m # CONFIG_IPV6_ILA is not set # CONFIG_IPV6_VTI is not set CONFIG_IPV6_SIT=y @@ -1146,8 +1156,13 @@ CONFIG_NF_CT_PROTO_UDPLITE=y # CONFIG_NF_CONNTRACK_SANE is not set # CONFIG_NF_CONNTRACK_SIP is not set # CONFIG_NF_CONNTRACK_TFTP is not set -# CONFIG_NF_CT_NETLINK is not set -# CONFIG_NF_CT_NETLINK_TIMEOUT is not set +CONFIG_COMPAT_NETLINK_MESSAGES=y +CONFIG_NF_CT_NETLINK=m +CONFIG_NF_CT_NETLINK_TIMEOUT=m +CONFIG_NF_CT_NETLINK_HELPER=m +CONFIG_NETFILTER_NETLINK_GLUE_CT=y +CONFIG_SCSI_NETLINK=y +CONFIG_QUOTA_NETLINK_INTERFACE=y CONFIG_NF_NAT=m CONFIG_NF_NAT_REDIRECT=y CONFIG_NF_NAT_MASQUERADE=y @@ -1992,7 +2007,7 @@ CONFIG_NETCONSOLE_DYNAMIC=y CONFIG_NETPOLL=y CONFIG_NET_POLL_CONTROLLER=y # CONFIG_RIONET is not set -# CONFIG_TUN is not set +CONFIG_TUN=y # CONFIG_TUN_VNET_CROSS_LE is not set CONFIG_VETH=y # CONFIG_NLMON is not set @@ -3990,7 +4005,7 @@ CONFIG_MANDATORY_FILE_LOCKING=y CONFIG_FSNOTIFY=y CONFIG_DNOTIFY=y CONFIG_INOTIFY_USER=y -# CONFIG_FANOTIFY is not set +CONFIG_FANOTIFY=y CONFIG_QUOTA=y CONFIG_QUOTA_NETLINK_INTERFACE=y # CONFIG_PRINT_QUOTA_WARNING is not set From aecbd6170e6b404403f0bb1294187d857b77ff6e Mon Sep 17 00:00:00 2001 From: Philip Yang Date: Wed, 23 Mar 2022 10:30:01 -0400 Subject: [PATCH 0007/1868] rock-dbg_defconfig: Update for 5.16 Also enable ACPI HMAT support, to fix boot crash or amdgpu init failure on ALDEBARAN. v2: - Use make savedefconfig to minimize the changes, skipping redundant configs that are implied by others or have same value as default. Signed-off-by: Philip Yang Reviewed-by: Felix Kuehling Signed-off-by: Alex Deucher --- arch/x86/configs/rock-dbg_defconfig | 4384 +-------------------------- 1 file changed, 3 insertions(+), 4381 deletions(-) diff --git a/arch/x86/configs/rock-dbg_defconfig b/arch/x86/configs/rock-dbg_defconfig index bc2a34666c1d9..406fdfaceb550 100644 --- a/arch/x86/configs/rock-dbg_defconfig +++ b/arch/x86/configs/rock-dbg_defconfig @@ -1,1176 +1,182 @@ -# -# Automatically generated file; DO NOT EDIT. -# Linux/x86 5.13.0 Kernel Configuration -# -CONFIG_CC_VERSION_TEXT="gcc (Ubuntu 7.5.0-3ubuntu1~18.04) 7.5.0" -CONFIG_CC_IS_GCC=y -CONFIG_GCC_VERSION=70500 -CONFIG_CLANG_VERSION=0 -CONFIG_AS_IS_GNU=y -CONFIG_AS_VERSION=23000 -CONFIG_LD_IS_BFD=y -CONFIG_LD_VERSION=23000 -CONFIG_LLD_VERSION=0 -CONFIG_CC_CAN_LINK=y -CONFIG_CC_CAN_LINK_STATIC=y -CONFIG_CC_HAS_ASM_GOTO=y -CONFIG_CC_HAS_ASM_INLINE=y -CONFIG_IRQ_WORK=y -CONFIG_BUILDTIME_TABLE_SORT=y -CONFIG_THREAD_INFO_IN_TASK=y - -# -# General setup -# -CONFIG_INIT_ENV_ARG_LIMIT=32 -# CONFIG_COMPILE_TEST is not set CONFIG_LOCALVERSION="-kfd" # CONFIG_LOCALVERSION_AUTO is not set -CONFIG_BUILD_SALT="" -CONFIG_HAVE_KERNEL_GZIP=y -CONFIG_HAVE_KERNEL_BZIP2=y -CONFIG_HAVE_KERNEL_LZMA=y -CONFIG_HAVE_KERNEL_XZ=y -CONFIG_HAVE_KERNEL_LZO=y -CONFIG_HAVE_KERNEL_LZ4=y -CONFIG_HAVE_KERNEL_ZSTD=y -CONFIG_KERNEL_GZIP=y -# CONFIG_KERNEL_BZIP2 is not set -# CONFIG_KERNEL_LZMA is not set -# CONFIG_KERNEL_XZ is not set -# CONFIG_KERNEL_LZO is not set -# CONFIG_KERNEL_LZ4 is not set -# CONFIG_KERNEL_ZSTD is not set -CONFIG_DEFAULT_INIT="" -CONFIG_DEFAULT_HOSTNAME="(none)" -CONFIG_SWAP=y CONFIG_SYSVIPC=y -CONFIG_SYSVIPC_SYSCTL=y CONFIG_POSIX_MQUEUE=y -CONFIG_POSIX_MQUEUE_SYSCTL=y -# CONFIG_WATCH_QUEUE is not set -CONFIG_CROSS_MEMORY_ATTACH=y -CONFIG_USELIB=y CONFIG_AUDIT=y -CONFIG_HAVE_ARCH_AUDITSYSCALL=y -CONFIG_AUDITSYSCALL=y - -# -# IRQ subsystem -# -CONFIG_GENERIC_IRQ_PROBE=y -CONFIG_GENERIC_IRQ_SHOW=y -CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK=y -CONFIG_GENERIC_PENDING_IRQ=y -CONFIG_GENERIC_IRQ_MIGRATION=y -CONFIG_HARDIRQS_SW_RESEND=y -CONFIG_IRQ_DOMAIN=y -CONFIG_IRQ_DOMAIN_HIERARCHY=y -CONFIG_GENERIC_MSI_IRQ=y -CONFIG_GENERIC_MSI_IRQ_DOMAIN=y -CONFIG_IRQ_MSI_IOMMU=y -CONFIG_GENERIC_IRQ_MATRIX_ALLOCATOR=y -CONFIG_GENERIC_IRQ_RESERVATION_MODE=y -CONFIG_IRQ_FORCED_THREADING=y -CONFIG_SPARSE_IRQ=y -# CONFIG_GENERIC_IRQ_DEBUGFS is not set -# end of IRQ subsystem - -CONFIG_CLOCKSOURCE_WATCHDOG=y -CONFIG_ARCH_CLOCKSOURCE_INIT=y -CONFIG_CLOCKSOURCE_VALIDATE_LAST_CYCLE=y -CONFIG_GENERIC_TIME_VSYSCALL=y -CONFIG_GENERIC_CLOCKEVENTS=y -CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y -CONFIG_GENERIC_CLOCKEVENTS_MIN_ADJUST=y -CONFIG_GENERIC_CMOS_UPDATE=y -CONFIG_HAVE_POSIX_CPU_TIMERS_TASK_WORK=y -CONFIG_POSIX_CPU_TIMERS_TASK_WORK=y - -# -# Timers subsystem -# -CONFIG_TICK_ONESHOT=y -CONFIG_NO_HZ_COMMON=y -# CONFIG_HZ_PERIODIC is not set -CONFIG_NO_HZ_IDLE=y -# CONFIG_NO_HZ_FULL is not set CONFIG_NO_HZ=y CONFIG_HIGH_RES_TIMERS=y -# end of Timers subsystem - -CONFIG_BPF=y -CONFIG_HAVE_EBPF_JIT=y -CONFIG_ARCH_WANT_DEFAULT_BPF_JIT=y - -# -# BPF subsystem -# CONFIG_BPF_SYSCALL=y -# CONFIG_BPF_JIT is not set # CONFIG_BPF_UNPRIV_DEFAULT_OFF is not set -# CONFIG_BPF_PRELOAD is not set -# end of BPF subsystem - -# CONFIG_PREEMPT_NONE is not set CONFIG_PREEMPT_VOLUNTARY=y -# CONFIG_PREEMPT is not set -CONFIG_PREEMPT_COUNT=y - -# -# CPU/Task time and stats accounting -# -CONFIG_TICK_CPU_ACCOUNTING=y -# CONFIG_VIRT_CPU_ACCOUNTING_GEN is not set -# CONFIG_IRQ_TIME_ACCOUNTING is not set CONFIG_BSD_PROCESS_ACCT=y CONFIG_BSD_PROCESS_ACCT_V3=y CONFIG_TASKSTATS=y CONFIG_TASK_DELAY_ACCT=y CONFIG_TASK_XACCT=y CONFIG_TASK_IO_ACCOUNTING=y -# CONFIG_PSI is not set -# end of CPU/Task time and stats accounting - # CONFIG_CPU_ISOLATION is not set - -# -# RCU Subsystem -# -CONFIG_TREE_RCU=y -# CONFIG_RCU_EXPERT is not set -CONFIG_SRCU=y -CONFIG_TREE_SRCU=y -CONFIG_TASKS_RCU_GENERIC=y -CONFIG_TASKS_RUDE_RCU=y -CONFIG_TASKS_TRACE_RCU=y -CONFIG_RCU_STALL_COMMON=y -CONFIG_RCU_NEED_SEGCBLIST=y -# end of RCU Subsystem - -CONFIG_BUILD_BIN2C=y -# CONFIG_IKCONFIG is not set -# CONFIG_IKHEADERS is not set CONFIG_LOG_BUF_SHIFT=18 -CONFIG_LOG_CPU_MAX_BUF_SHIFT=12 -CONFIG_PRINTK_SAFE_LOG_BUF_SHIFT=13 -CONFIG_HAVE_UNSTABLE_SCHED_CLOCK=y - -# -# Scheduler features -# -# CONFIG_UCLAMP_TASK is not set -# end of Scheduler features - -CONFIG_ARCH_SUPPORTS_NUMA_BALANCING=y -CONFIG_ARCH_WANT_BATCHED_UNMAP_TLB_FLUSH=y -CONFIG_CC_HAS_INT128=y -CONFIG_ARCH_SUPPORTS_INT128=y CONFIG_NUMA_BALANCING=y -CONFIG_NUMA_BALANCING_DEFAULT_ENABLED=y -CONFIG_CGROUPS=y -CONFIG_PAGE_COUNTER=y CONFIG_MEMCG=y -CONFIG_MEMCG_SWAP=y -CONFIG_MEMCG_KMEM=y CONFIG_BLK_CGROUP=y -CONFIG_CGROUP_WRITEBACK=y -CONFIG_CGROUP_SCHED=y -CONFIG_FAIR_GROUP_SCHED=y CONFIG_CFS_BANDWIDTH=y -# CONFIG_RT_GROUP_SCHED is not set CONFIG_CGROUP_PIDS=y -# CONFIG_CGROUP_RDMA is not set CONFIG_CGROUP_FREEZER=y CONFIG_CGROUP_HUGETLB=y CONFIG_CPUSETS=y -CONFIG_PROC_PID_CPUSET=y CONFIG_CGROUP_DEVICE=y CONFIG_CGROUP_CPUACCT=y CONFIG_CGROUP_PERF=y CONFIG_CGROUP_BPF=y -# CONFIG_CGROUP_MISC is not set -# CONFIG_CGROUP_DEBUG is not set -CONFIG_SOCK_CGROUP_DATA=y CONFIG_NAMESPACES=y -CONFIG_UTS_NS=y -CONFIG_TIME_NS=y -CONFIG_IPC_NS=y CONFIG_USER_NS=y -CONFIG_PID_NS=y -CONFIG_NET_NS=y CONFIG_CHECKPOINT_RESTORE=y CONFIG_SCHED_AUTOGROUP=y -# CONFIG_SYSFS_DEPRECATED is not set -CONFIG_RELAY=y CONFIG_BLK_DEV_INITRD=y -CONFIG_INITRAMFS_SOURCE="" -CONFIG_RD_GZIP=y -CONFIG_RD_BZIP2=y -CONFIG_RD_LZMA=y -CONFIG_RD_XZ=y -CONFIG_RD_LZO=y -CONFIG_RD_LZ4=y -CONFIG_RD_ZSTD=y -# CONFIG_BOOT_CONFIG is not set -CONFIG_CC_OPTIMIZE_FOR_PERFORMANCE=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_LD_ORPHAN_WARN=y -CONFIG_SYSCTL=y -CONFIG_HAVE_UID16=y -CONFIG_SYSCTL_EXCEPTION_TRACE=y -CONFIG_HAVE_PCSPKR_PLATFORM=y CONFIG_EXPERT=y -CONFIG_UID16=y -CONFIG_MULTIUSER=y -CONFIG_SGETMASK_SYSCALL=y -CONFIG_SYSFS_SYSCALL=y -CONFIG_FHANDLE=y -CONFIG_POSIX_TIMERS=y -CONFIG_PRINTK=y -CONFIG_PRINTK_NMI=y -CONFIG_BUG=y -CONFIG_ELF_CORE=y -CONFIG_PCSPKR_PLATFORM=y -CONFIG_BASE_FULL=y -CONFIG_FUTEX=y -CONFIG_FUTEX_PI=y -CONFIG_EPOLL=y -CONFIG_SIGNALFD=y -CONFIG_TIMERFD=y -CONFIG_EVENTFD=y -CONFIG_SHMEM=y -CONFIG_AIO=y -CONFIG_IO_URING=y -CONFIG_ADVISE_SYSCALLS=y -CONFIG_MEMBARRIER=y -CONFIG_KALLSYMS=y -CONFIG_KALLSYMS_ALL=y -CONFIG_KALLSYMS_ABSOLUTE_PERCPU=y -CONFIG_KALLSYMS_BASE_RELATIVE=y -# CONFIG_USERFAULTFD is not set CONFIG_USERFAULTFD=y -CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE=y -CONFIG_KCMP=y -CONFIG_RSEQ=y -# CONFIG_DEBUG_RSEQ is not set -# CONFIG_EMBEDDED is not set -CONFIG_HAVE_PERF_EVENTS=y -# CONFIG_PC104 is not set - -# -# Kernel Performance Events And Counters -# -CONFIG_PERF_EVENTS=y -# CONFIG_DEBUG_PERF_USE_VMALLOC is not set -# end of Kernel Performance Events And Counters - -CONFIG_VM_EVENT_COUNTERS=y -CONFIG_SLUB_DEBUG=y # CONFIG_COMPAT_BRK is not set -# CONFIG_SLAB is not set -CONFIG_SLUB=y -# CONFIG_SLOB is not set -CONFIG_SLAB_MERGE_DEFAULT=y -# CONFIG_SLAB_FREELIST_RANDOM is not set -# CONFIG_SLAB_FREELIST_HARDENED is not set -# CONFIG_SHUFFLE_PAGE_ALLOCATOR is not set -CONFIG_SLUB_CPU_PARTIAL=y -CONFIG_SYSTEM_DATA_VERIFICATION=y CONFIG_PROFILING=y -CONFIG_TRACEPOINTS=y -# end of General setup - -CONFIG_64BIT=y -CONFIG_X86_64=y -CONFIG_X86=y -CONFIG_INSTRUCTION_DECODER=y -CONFIG_OUTPUT_FORMAT="elf64-x86-64" -CONFIG_LOCKDEP_SUPPORT=y -CONFIG_STACKTRACE_SUPPORT=y -CONFIG_MMU=y -CONFIG_ARCH_MMAP_RND_BITS_MIN=28 -CONFIG_ARCH_MMAP_RND_BITS_MAX=32 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MIN=8 -CONFIG_ARCH_MMAP_RND_COMPAT_BITS_MAX=16 -CONFIG_GENERIC_ISA_DMA=y -CONFIG_GENERIC_BUG=y -CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y -CONFIG_ARCH_MAY_HAVE_PC_FDC=y -CONFIG_GENERIC_CALIBRATE_DELAY=y -CONFIG_ARCH_HAS_CPU_RELAX=y -CONFIG_ARCH_HAS_FILTER_PGPROT=y -CONFIG_HAVE_SETUP_PER_CPU_AREA=y -CONFIG_NEED_PER_CPU_EMBED_FIRST_CHUNK=y -CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y -CONFIG_ARCH_HIBERNATION_POSSIBLE=y -CONFIG_ARCH_SUSPEND_POSSIBLE=y -CONFIG_ARCH_WANT_GENERAL_HUGETLB=y -CONFIG_ZONE_DMA32=y -CONFIG_AUDIT_ARCH=y -CONFIG_HAVE_INTEL_TXT=y -CONFIG_X86_64_SMP=y -CONFIG_ARCH_SUPPORTS_UPROBES=y -CONFIG_FIX_EARLYCON_MEM=y -CONFIG_PGTABLE_LEVELS=4 -CONFIG_CC_HAS_SANE_STACKPROTECTOR=y - -# -# Processor type and features -# -CONFIG_ZONE_DMA=y CONFIG_SMP=y -CONFIG_X86_FEATURE_NAMES=y -# CONFIG_X86_X2APIC is not set -CONFIG_X86_MPPARSE=y -# CONFIG_GOLDFISH is not set # CONFIG_RETPOLINE is not set -# CONFIG_X86_CPU_RESCTRL is not set -CONFIG_X86_EXTENDED_PLATFORM=y -# CONFIG_X86_VSMP is not set -# CONFIG_X86_GOLDFISH is not set CONFIG_X86_INTEL_LPSS=y -# CONFIG_X86_AMD_PLATFORM_DEVICE is not set -CONFIG_IOSF_MBI=y CONFIG_IOSF_MBI_DEBUG=y -CONFIG_X86_SUPPORTS_MEMORY_FAILURE=y -CONFIG_SCHED_OMIT_FRAME_POINTER=y CONFIG_HYPERVISOR_GUEST=y CONFIG_PARAVIRT=y -# CONFIG_PARAVIRT_DEBUG is not set CONFIG_PARAVIRT_SPINLOCKS=y -CONFIG_X86_HV_CALLBACK_VECTOR=y -# CONFIG_XEN is not set -CONFIG_KVM_GUEST=y -CONFIG_ARCH_CPUIDLE_HALTPOLL=y -# CONFIG_PVH is not set -# CONFIG_PARAVIRT_TIME_ACCOUNTING is not set -CONFIG_PARAVIRT_CLOCK=y -# CONFIG_JAILHOUSE_GUEST is not set -# CONFIG_ACRN_GUEST is not set -# CONFIG_MK8 is not set -# CONFIG_MPSC is not set -# CONFIG_MCORE2 is not set -# CONFIG_MATOM is not set -CONFIG_GENERIC_CPU=y -CONFIG_X86_INTERNODE_CACHE_SHIFT=6 -CONFIG_X86_L1_CACHE_SHIFT=6 -CONFIG_X86_TSC=y -CONFIG_X86_CMPXCHG64=y -CONFIG_X86_CMOV=y -CONFIG_X86_MINIMUM_CPU_FAMILY=64 -CONFIG_X86_DEBUGCTLMSR=y -CONFIG_IA32_FEAT_CTL=y -CONFIG_X86_VMX_FEATURE_NAMES=y CONFIG_PROCESSOR_SELECT=y -CONFIG_CPU_SUP_INTEL=y -CONFIG_CPU_SUP_AMD=y -CONFIG_CPU_SUP_HYGON=y -CONFIG_CPU_SUP_CENTAUR=y -CONFIG_CPU_SUP_ZHAOXIN=y -CONFIG_HPET_TIMER=y -CONFIG_HPET_EMULATE_RTC=y -CONFIG_DMI=y CONFIG_GART_IOMMU=y -# CONFIG_MAXSMP is not set -CONFIG_NR_CPUS_RANGE_BEGIN=2 -CONFIG_NR_CPUS_RANGE_END=512 -CONFIG_NR_CPUS_DEFAULT=64 CONFIG_NR_CPUS=256 -CONFIG_SCHED_SMT=y -CONFIG_SCHED_MC=y -CONFIG_SCHED_MC_PRIO=y -CONFIG_X86_LOCAL_APIC=y -CONFIG_X86_IO_APIC=y CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS=y -CONFIG_X86_MCE=y -# CONFIG_X86_MCELOG_LEGACY is not set -CONFIG_X86_MCE_INTEL=y -CONFIG_X86_MCE_AMD=y -CONFIG_X86_MCE_THRESHOLD=y -# CONFIG_X86_MCE_INJECT is not set - -# -# Performance monitoring -# -CONFIG_PERF_EVENTS_INTEL_UNCORE=y -CONFIG_PERF_EVENTS_INTEL_RAPL=y -CONFIG_PERF_EVENTS_INTEL_CSTATE=y -# CONFIG_PERF_EVENTS_AMD_POWER is not set -# end of Performance monitoring - -CONFIG_X86_16BIT=y -CONFIG_X86_ESPFIX64=y -CONFIG_X86_VSYSCALL_EMULATION=y -CONFIG_X86_IOPL_IOPERM=y CONFIG_I8K=m -CONFIG_MICROCODE=y -CONFIG_MICROCODE_INTEL=y CONFIG_MICROCODE_AMD=y CONFIG_MICROCODE_OLD_INTERFACE=y CONFIG_X86_MSR=m CONFIG_X86_CPUID=m # CONFIG_X86_5LEVEL is not set -CONFIG_X86_DIRECT_GBPAGES=y -# CONFIG_X86_CPA_STATISTICS is not set -# CONFIG_AMD_MEM_ENCRYPT is not set CONFIG_NUMA=y -CONFIG_AMD_NUMA=y -CONFIG_X86_64_ACPI_NUMA=y -# CONFIG_NUMA_EMU is not set -CONFIG_NODES_SHIFT=6 -CONFIG_ARCH_SPARSEMEM_ENABLE=y -CONFIG_ARCH_SPARSEMEM_DEFAULT=y -CONFIG_ARCH_SELECT_MEMORY_MODEL=y CONFIG_ARCH_MEMORY_PROBE=y -CONFIG_ARCH_PROC_KCORE_TEXT=y -CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 -# CONFIG_X86_PMEM_LEGACY is not set CONFIG_X86_CHECK_BIOS_CORRUPTION=y -CONFIG_X86_BOOTPARAM_MEMORY_CORRUPTION_CHECK=y -CONFIG_X86_RESERVE_LOW=64 -CONFIG_MTRR=y -CONFIG_MTRR_SANITIZER=y CONFIG_MTRR_SANITIZER_ENABLE_DEFAULT=1 -CONFIG_MTRR_SANITIZER_SPARE_REG_NR_DEFAULT=1 -CONFIG_X86_PAT=y -CONFIG_ARCH_USES_PG_UNCACHED=y -CONFIG_ARCH_RANDOM=y -CONFIG_X86_SMAP=y -CONFIG_X86_UMIP=y -CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS=y -CONFIG_X86_INTEL_TSX_MODE_OFF=y -# CONFIG_X86_INTEL_TSX_MODE_ON is not set -# CONFIG_X86_INTEL_TSX_MODE_AUTO is not set -# CONFIG_X86_SGX is not set CONFIG_EFI=y CONFIG_EFI_STUB=y CONFIG_EFI_MIXED=y -# CONFIG_HZ_100 is not set -CONFIG_HZ_250=y -# CONFIG_HZ_300 is not set -# CONFIG_HZ_1000 is not set -CONFIG_HZ=250 -CONFIG_SCHED_HRTICK=y CONFIG_KEXEC=y CONFIG_KEXEC_FILE=y -CONFIG_ARCH_HAS_KEXEC_PURGATORY=y -# CONFIG_KEXEC_SIG is not set CONFIG_CRASH_DUMP=y CONFIG_KEXEC_JUMP=y -CONFIG_PHYSICAL_START=0x1000000 -CONFIG_RELOCATABLE=y -CONFIG_RANDOMIZE_BASE=y -CONFIG_X86_NEED_RELOCS=y CONFIG_PHYSICAL_ALIGN=0x1000000 -CONFIG_DYNAMIC_MEMORY_LAYOUT=y -CONFIG_RANDOMIZE_MEMORY=y -CONFIG_RANDOMIZE_MEMORY_PHYSICAL_PADDING=0xa -CONFIG_HOTPLUG_CPU=y -# CONFIG_BOOTPARAM_HOTPLUG_CPU0 is not set -# CONFIG_DEBUG_HOTPLUG_CPU0 is not set -# CONFIG_COMPAT_VDSO is not set CONFIG_LEGACY_VSYSCALL_EMULATE=y -# CONFIG_LEGACY_VSYSCALL_XONLY is not set -# CONFIG_LEGACY_VSYSCALL_NONE is not set -# CONFIG_CMDLINE_BOOL is not set -CONFIG_MODIFY_LDT_SYSCALL=y -CONFIG_HAVE_LIVEPATCH=y -# CONFIG_LIVEPATCH is not set -# end of Processor type and features - -CONFIG_ARCH_HAS_ADD_PAGES=y -CONFIG_ARCH_MHP_MEMMAP_ON_MEMORY_ENABLE=y -CONFIG_USE_PERCPU_NUMA_NODE_ID=y - -# -# Power management and ACPI options -# -CONFIG_ARCH_HIBERNATION_HEADER=y -CONFIG_SUSPEND=y -CONFIG_SUSPEND_FREEZER=y -# CONFIG_SUSPEND_SKIP_SYNC is not set -CONFIG_HIBERNATE_CALLBACKS=y CONFIG_HIBERNATION=y -CONFIG_HIBERNATION_SNAPSHOT_DEV=y -CONFIG_PM_STD_PARTITION="" -CONFIG_PM_SLEEP=y -CONFIG_PM_SLEEP_SMP=y -# CONFIG_PM_AUTOSLEEP is not set CONFIG_PM_WAKELOCKS=y -CONFIG_PM_WAKELOCKS_LIMIT=100 -CONFIG_PM_WAKELOCKS_GC=y -CONFIG_PM=y CONFIG_PM_DEBUG=y CONFIG_PM_ADVANCED_DEBUG=y -# CONFIG_PM_TEST_SUSPEND is not set -CONFIG_PM_SLEEP_DEBUG=y -# CONFIG_DPM_WATCHDOG is not set -CONFIG_PM_TRACE=y CONFIG_PM_TRACE_RTC=y -CONFIG_PM_CLK=y CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y -# CONFIG_ENERGY_MODEL is not set -CONFIG_ARCH_SUPPORTS_ACPI=y -CONFIG_ACPI=y -CONFIG_ACPI_LEGACY_TABLES_LOOKUP=y -CONFIG_ARCH_MIGHT_HAVE_ACPI_PDC=y -CONFIG_ACPI_SYSTEM_POWER_STATES_SUPPORT=y -# CONFIG_ACPI_DEBUGGER is not set -CONFIG_ACPI_SPCR_TABLE=y -# CONFIG_ACPI_FPDT is not set -CONFIG_ACPI_LPIT=y -CONFIG_ACPI_SLEEP=y -CONFIG_ACPI_REV_OVERRIDE_POSSIBLE=y CONFIG_ACPI_EC_DEBUGFS=m -CONFIG_ACPI_AC=y -CONFIG_ACPI_BATTERY=y -CONFIG_ACPI_BUTTON=y CONFIG_ACPI_VIDEO=m -CONFIG_ACPI_FAN=y -# CONFIG_ACPI_TAD is not set CONFIG_ACPI_DOCK=y -CONFIG_ACPI_CPU_FREQ_PSS=y -CONFIG_ACPI_PROCESSOR_CSTATE=y -CONFIG_ACPI_PROCESSOR_IDLE=y -CONFIG_ACPI_CPPC_LIB=y -CONFIG_ACPI_PROCESSOR=y -CONFIG_ACPI_HOTPLUG_CPU=y CONFIG_ACPI_PROCESSOR_AGGREGATOR=m -CONFIG_ACPI_THERMAL=y -CONFIG_ARCH_HAS_ACPI_TABLE_UPGRADE=y -CONFIG_ACPI_TABLE_UPGRADE=y -# CONFIG_ACPI_DEBUG is not set CONFIG_ACPI_PCI_SLOT=y -CONFIG_ACPI_CONTAINER=y CONFIG_ACPI_HOTPLUG_MEMORY=y -CONFIG_ACPI_HOTPLUG_IOAPIC=y CONFIG_ACPI_SBS=m -CONFIG_ACPI_HED=y -# CONFIG_ACPI_CUSTOM_METHOD is not set CONFIG_ACPI_BGRT=y -# CONFIG_ACPI_REDUCED_HARDWARE_ONLY is not set -# CONFIG_ACPI_NFIT is not set -CONFIG_ACPI_NUMA=y -# CONFIG_ACPI_HMAT is not set -CONFIG_HAVE_ACPI_APEI=y -CONFIG_HAVE_ACPI_APEI_NMI=y +CONFIG_ACPI_HMAT=y CONFIG_ACPI_APEI=y CONFIG_ACPI_APEI_GHES=y CONFIG_ACPI_APEI_PCIEAER=y CONFIG_ACPI_APEI_MEMORY_FAILURE=y CONFIG_ACPI_APEI_EINJ=m -# CONFIG_ACPI_APEI_ERST_DEBUG is not set -# CONFIG_ACPI_DPTF is not set -# CONFIG_ACPI_CONFIGFS is not set -# CONFIG_PMIC_OPREGION is not set -CONFIG_X86_PM_TIMER=y - -# -# CPU Frequency scaling -# -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_GOV_ATTR_SET=y -CONFIG_CPU_FREQ_GOV_COMMON=y CONFIG_CPU_FREQ_STAT=y CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y -# CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set -# CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL is not set -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y CONFIG_CPU_FREQ_GOV_POWERSAVE=y CONFIG_CPU_FREQ_GOV_USERSPACE=y CONFIG_CPU_FREQ_GOV_ONDEMAND=y CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y -CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y - -# -# CPU frequency scaling drivers -# -CONFIG_X86_INTEL_PSTATE=y -# CONFIG_X86_PCC_CPUFREQ is not set CONFIG_X86_ACPI_CPUFREQ=y # CONFIG_X86_ACPI_CPUFREQ_CPB is not set -# CONFIG_X86_POWERNOW_K8 is not set -# CONFIG_X86_AMD_FREQ_SENSITIVITY is not set -# CONFIG_X86_SPEEDSTEP_CENTRINO is not set -# CONFIG_X86_P4_CLOCKMOD is not set - -# -# shared options -# -# end of CPU Frequency scaling - -# -# CPU Idle -# -CONFIG_CPU_IDLE=y CONFIG_CPU_IDLE_GOV_LADDER=y -CONFIG_CPU_IDLE_GOV_MENU=y -# CONFIG_CPU_IDLE_GOV_TEO is not set -# CONFIG_CPU_IDLE_GOV_HALTPOLL is not set -CONFIG_HALTPOLL_CPUIDLE=y -# end of CPU Idle - -# CONFIG_INTEL_IDLE is not set -# end of Power management and ACPI options - -# -# Bus options (PCI etc.) -# -CONFIG_PCI_DIRECT=y -CONFIG_PCI_MMCONFIG=y -CONFIG_MMCONF_FAM10H=y -# CONFIG_PCI_CNB20LE_QUIRK is not set -# CONFIG_ISA_BUS is not set -CONFIG_ISA_DMA_API=y -CONFIG_AMD_NB=y -# CONFIG_X86_SYSFB is not set -# end of Bus options (PCI etc.) - -# -# Binary Emulations -# CONFIG_IA32_EMULATION=y -# CONFIG_X86_X32 is not set -CONFIG_COMPAT_32=y -CONFIG_COMPAT=y -CONFIG_COMPAT_FOR_U64_ALIGNMENT=y -CONFIG_SYSVIPC_COMPAT=y -# end of Binary Emulations - -# -# Firmware Drivers -# -# CONFIG_EDD is not set -CONFIG_FIRMWARE_MEMMAP=y -CONFIG_DMIID=y -# CONFIG_DMI_SYSFS is not set -CONFIG_DMI_SCAN_MACHINE_NON_EFI_FALLBACK=y -# CONFIG_FW_CFG_SYSFS is not set -# CONFIG_GOOGLE_FIRMWARE is not set - -# -# EFI (Extensible Firmware Interface) Support -# -CONFIG_EFI_VARS=y -CONFIG_EFI_ESRT=y -CONFIG_EFI_VARS_PSTORE=y -# CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE is not set -CONFIG_EFI_RUNTIME_MAP=y -# CONFIG_EFI_FAKE_MEMMAP is not set -CONFIG_EFI_RUNTIME_WRAPPERS=y -CONFIG_EFI_GENERIC_STUB_INITRD_CMDLINE_LOADER=y -# CONFIG_EFI_BOOTLOADER_CONTROL is not set -# CONFIG_EFI_CAPSULE_LOADER is not set -# CONFIG_EFI_TEST is not set -# CONFIG_APPLE_PROPERTIES is not set -# CONFIG_RESET_ATTACK_MITIGATION is not set -# CONFIG_EFI_RCI2_TABLE is not set -# CONFIG_EFI_DISABLE_PCI_DMA is not set -# end of EFI (Extensible Firmware Interface) Support - -CONFIG_UEFI_CPER=y -CONFIG_UEFI_CPER_X86=y -CONFIG_EFI_EARLYCON=y -CONFIG_EFI_CUSTOM_SSDT_OVERLAYS=y - -# -# Tegra firmware driver -# -# end of Tegra firmware driver -# end of Firmware Drivers - -CONFIG_HAVE_KVM=y -CONFIG_VIRTUALIZATION=y -# CONFIG_KVM is not set -CONFIG_AS_AVX512=y -CONFIG_AS_SHA1_NI=y -CONFIG_AS_SHA256_NI=y - -# -# General architecture-dependent options -# -CONFIG_CRASH_CORE=y -CONFIG_KEXEC_CORE=y -CONFIG_HOTPLUG_SMT=y -CONFIG_GENERIC_ENTRY=y -CONFIG_KPROBES=y CONFIG_JUMP_LABEL=y -# CONFIG_STATIC_KEYS_SELFTEST is not set -# CONFIG_STATIC_CALL_SELFTEST is not set -CONFIG_OPTPROBES=y -CONFIG_KPROBES_ON_FTRACE=y -CONFIG_UPROBES=y -CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y -CONFIG_ARCH_USE_BUILTIN_BSWAP=y -CONFIG_KRETPROBES=y -CONFIG_HAVE_IOREMAP_PROT=y -CONFIG_HAVE_KPROBES=y -CONFIG_HAVE_KRETPROBES=y -CONFIG_HAVE_OPTPROBES=y -CONFIG_HAVE_KPROBES_ON_FTRACE=y -CONFIG_HAVE_FUNCTION_ERROR_INJECTION=y -CONFIG_HAVE_NMI=y -CONFIG_HAVE_ARCH_TRACEHOOK=y -CONFIG_HAVE_DMA_CONTIGUOUS=y -CONFIG_GENERIC_SMP_IDLE_THREAD=y -CONFIG_ARCH_HAS_FORTIFY_SOURCE=y -CONFIG_ARCH_HAS_SET_MEMORY=y -CONFIG_ARCH_HAS_SET_DIRECT_MAP=y -CONFIG_HAVE_ARCH_THREAD_STRUCT_WHITELIST=y -CONFIG_ARCH_WANTS_DYNAMIC_TASK_STRUCT=y -CONFIG_HAVE_ASM_MODVERSIONS=y -CONFIG_HAVE_REGS_AND_STACK_ACCESS_API=y -CONFIG_HAVE_RSEQ=y -CONFIG_HAVE_FUNCTION_ARG_ACCESS_API=y -CONFIG_HAVE_HW_BREAKPOINT=y -CONFIG_HAVE_MIXED_BREAKPOINTS_REGS=y -CONFIG_HAVE_USER_RETURN_NOTIFIER=y -CONFIG_HAVE_PERF_EVENTS_NMI=y -CONFIG_HAVE_HARDLOCKUP_DETECTOR_PERF=y -CONFIG_HAVE_PERF_REGS=y -CONFIG_HAVE_PERF_USER_STACK_DUMP=y -CONFIG_HAVE_ARCH_JUMP_LABEL=y -CONFIG_HAVE_ARCH_JUMP_LABEL_RELATIVE=y -CONFIG_MMU_GATHER_TABLE_FREE=y -CONFIG_MMU_GATHER_RCU_TABLE_FREE=y -CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG=y -CONFIG_HAVE_ALIGNED_STRUCT_PAGE=y -CONFIG_HAVE_CMPXCHG_LOCAL=y -CONFIG_HAVE_CMPXCHG_DOUBLE=y -CONFIG_ARCH_WANT_COMPAT_IPC_PARSE_VERSION=y -CONFIG_ARCH_WANT_OLD_COMPAT_IPC=y -CONFIG_HAVE_ARCH_SECCOMP=y -CONFIG_HAVE_ARCH_SECCOMP_FILTER=y -CONFIG_SECCOMP=y -CONFIG_SECCOMP_FILTER=y -# CONFIG_SECCOMP_CACHE_DEBUG is not set -CONFIG_HAVE_ARCH_STACKLEAK=y -CONFIG_HAVE_STACKPROTECTOR=y -CONFIG_STACKPROTECTOR=y -CONFIG_STACKPROTECTOR_STRONG=y -CONFIG_ARCH_SUPPORTS_LTO_CLANG=y -CONFIG_ARCH_SUPPORTS_LTO_CLANG_THIN=y -CONFIG_LTO_NONE=y -CONFIG_HAVE_ARCH_WITHIN_STACK_FRAMES=y -CONFIG_HAVE_CONTEXT_TRACKING=y -CONFIG_HAVE_CONTEXT_TRACKING_OFFSTACK=y -CONFIG_HAVE_VIRT_CPU_ACCOUNTING_GEN=y -CONFIG_HAVE_IRQ_TIME_ACCOUNTING=y -CONFIG_HAVE_MOVE_PUD=y -CONFIG_HAVE_MOVE_PMD=y -CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE=y -CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD=y -CONFIG_HAVE_ARCH_HUGE_VMAP=y -CONFIG_ARCH_WANT_HUGE_PMD_SHARE=y -CONFIG_HAVE_ARCH_SOFT_DIRTY=y -CONFIG_HAVE_MOD_ARCH_SPECIFIC=y -CONFIG_MODULES_USE_ELF_RELA=y -CONFIG_HAVE_IRQ_EXIT_ON_IRQ_STACK=y -CONFIG_HAVE_SOFTIRQ_ON_OWN_STACK=y -CONFIG_ARCH_HAS_ELF_RANDOMIZE=y -CONFIG_HAVE_ARCH_MMAP_RND_BITS=y -CONFIG_HAVE_EXIT_THREAD=y -CONFIG_ARCH_MMAP_RND_BITS=28 -CONFIG_HAVE_ARCH_MMAP_RND_COMPAT_BITS=y -CONFIG_ARCH_MMAP_RND_COMPAT_BITS=8 -CONFIG_HAVE_ARCH_COMPAT_MMAP_BASES=y -CONFIG_HAVE_STACK_VALIDATION=y -CONFIG_HAVE_RELIABLE_STACKTRACE=y -CONFIG_OLD_SIGSUSPEND3=y -CONFIG_COMPAT_OLD_SIGACTION=y -CONFIG_COMPAT_32BIT_TIME=y -CONFIG_HAVE_ARCH_VMAP_STACK=y -CONFIG_VMAP_STACK=y -CONFIG_HAVE_ARCH_RANDOMIZE_KSTACK_OFFSET=y -# CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT is not set -CONFIG_ARCH_HAS_STRICT_KERNEL_RWX=y -CONFIG_STRICT_KERNEL_RWX=y -CONFIG_ARCH_HAS_STRICT_MODULE_RWX=y -CONFIG_STRICT_MODULE_RWX=y -CONFIG_HAVE_ARCH_PREL32_RELOCATIONS=y -CONFIG_ARCH_USE_MEMREMAP_PROT=y -# CONFIG_LOCK_EVENT_COUNTS is not set -CONFIG_ARCH_HAS_MEM_ENCRYPT=y -CONFIG_HAVE_STATIC_CALL=y -CONFIG_HAVE_STATIC_CALL_INLINE=y -CONFIG_HAVE_PREEMPT_DYNAMIC=y -CONFIG_ARCH_WANT_LD_ORPHAN_WARN=y -CONFIG_ARCH_SUPPORTS_DEBUG_PAGEALLOC=y -CONFIG_ARCH_HAS_ELFCORE_COMPAT=y - -# -# GCOV-based kernel profiling -# -# CONFIG_GCOV_KERNEL is not set -CONFIG_ARCH_HAS_GCOV_PROFILE_ALL=y -# end of GCOV-based kernel profiling - -CONFIG_HAVE_GCC_PLUGINS=y -# end of General architecture-dependent options - -CONFIG_RT_MUTEXES=y -CONFIG_BASE_SMALL=0 -CONFIG_MODULE_SIG_FORMAT=y CONFIG_MODULES=y -# CONFIG_MODULE_FORCE_LOAD is not set CONFIG_MODULE_UNLOAD=y -# CONFIG_MODULE_FORCE_UNLOAD is not set CONFIG_MODVERSIONS=y -CONFIG_ASM_MODVERSIONS=y CONFIG_MODULE_SRCVERSION_ALL=y CONFIG_MODULE_SIG=y -# CONFIG_MODULE_SIG_FORCE is not set -CONFIG_MODULE_SIG_ALL=y -# CONFIG_MODULE_SIG_SHA1 is not set -# CONFIG_MODULE_SIG_SHA224 is not set -# CONFIG_MODULE_SIG_SHA256 is not set -# CONFIG_MODULE_SIG_SHA384 is not set CONFIG_MODULE_SIG_SHA512=y -CONFIG_MODULE_SIG_HASH="sha512" -CONFIG_MODULE_COMPRESS_NONE=y -# CONFIG_MODULE_COMPRESS_GZIP is not set -# CONFIG_MODULE_COMPRESS_XZ is not set -# CONFIG_MODULE_COMPRESS_ZSTD is not set -# CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS is not set -CONFIG_MODPROBE_PATH="/sbin/modprobe" -# CONFIG_TRIM_UNUSED_KSYMS is not set -CONFIG_MODULES_TREE_LOOKUP=y -CONFIG_BLOCK=y -CONFIG_BLK_SCSI_REQUEST=y -CONFIG_BLK_CGROUP_RWSTAT=y -CONFIG_BLK_DEV_BSG=y -CONFIG_BLK_DEV_BSGLIB=y CONFIG_BLK_DEV_INTEGRITY=y -CONFIG_BLK_DEV_INTEGRITY_T10=y -# CONFIG_BLK_DEV_ZONED is not set CONFIG_BLK_DEV_THROTTLING=y -# CONFIG_BLK_DEV_THROTTLING_LOW is not set -CONFIG_BLK_CMDLINE_PARSER=y -# CONFIG_BLK_WBT is not set -# CONFIG_BLK_CGROUP_IOLATENCY is not set -# CONFIG_BLK_CGROUP_IOCOST is not set -CONFIG_BLK_DEBUG_FS=y -# CONFIG_BLK_SED_OPAL is not set -# CONFIG_BLK_INLINE_ENCRYPTION is not set - -# -# Partition Types -# CONFIG_PARTITION_ADVANCED=y -# CONFIG_ACORN_PARTITION is not set -# CONFIG_AIX_PARTITION is not set -# CONFIG_OSF_PARTITION is not set -# CONFIG_AMIGA_PARTITION is not set -# CONFIG_ATARI_PARTITION is not set -# CONFIG_MAC_PARTITION is not set -CONFIG_MSDOS_PARTITION=y -# CONFIG_BSD_DISKLABEL is not set -# CONFIG_MINIX_SUBPARTITION is not set -# CONFIG_SOLARIS_X86_PARTITION is not set -# CONFIG_UNIXWARE_DISKLABEL is not set -# CONFIG_LDM_PARTITION is not set -# CONFIG_SGI_PARTITION is not set -# CONFIG_ULTRIX_PARTITION is not set -# CONFIG_SUN_PARTITION is not set -# CONFIG_KARMA_PARTITION is not set -CONFIG_EFI_PARTITION=y -# CONFIG_SYSV68_PARTITION is not set -# CONFIG_CMDLINE_PARTITION is not set -# end of Partition Types - -CONFIG_BLOCK_COMPAT=y -CONFIG_BLK_MQ_PCI=y -CONFIG_BLK_PM=y - -# -# IO Schedulers -# -CONFIG_MQ_IOSCHED_DEADLINE=y -CONFIG_MQ_IOSCHED_KYBER=y -# CONFIG_IOSCHED_BFQ is not set -# end of IO Schedulers - -CONFIG_ASN1=y -CONFIG_UNINLINE_SPIN_UNLOCK=y -CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y -CONFIG_MUTEX_SPIN_ON_OWNER=y -CONFIG_RWSEM_SPIN_ON_OWNER=y -CONFIG_LOCK_SPIN_ON_OWNER=y -CONFIG_ARCH_USE_QUEUED_SPINLOCKS=y -CONFIG_QUEUED_SPINLOCKS=y -CONFIG_ARCH_USE_QUEUED_RWLOCKS=y -CONFIG_QUEUED_RWLOCKS=y -CONFIG_ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE=y -CONFIG_ARCH_HAS_SYNC_CORE_BEFORE_USERMODE=y -CONFIG_ARCH_HAS_SYSCALL_WRAPPER=y -CONFIG_FREEZER=y - -# -# Executable file formats -# -CONFIG_BINFMT_ELF=y -CONFIG_COMPAT_BINFMT_ELF=y -CONFIG_ELFCORE=y -CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS=y -CONFIG_BINFMT_SCRIPT=y CONFIG_BINFMT_MISC=y -CONFIG_COREDUMP=y -# end of Executable file formats - -# -# Memory Management options -# -CONFIG_SELECT_MEMORY_MODEL=y -CONFIG_SPARSEMEM_MANUAL=y -CONFIG_SPARSEMEM=y -CONFIG_NEED_MULTIPLE_NODES=y -CONFIG_SPARSEMEM_EXTREME=y -CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y -CONFIG_SPARSEMEM_VMEMMAP=y -CONFIG_HAVE_FAST_GUP=y -CONFIG_NUMA_KEEP_MEMINFO=y -CONFIG_MEMORY_ISOLATION=y -CONFIG_HAVE_BOOTMEM_INFO_NODE=y -CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y CONFIG_MEMORY_HOTPLUG=y -CONFIG_MEMORY_HOTPLUG_SPARSE=y -# CONFIG_MEMORY_HOTPLUG_DEFAULT_ONLINE is not set -CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y CONFIG_MEMORY_HOTREMOVE=y -CONFIG_MHP_MEMMAP_ON_MEMORY=y -CONFIG_SPLIT_PTLOCK_CPUS=4 -CONFIG_ARCH_ENABLE_SPLIT_PMD_PTLOCK=y -CONFIG_COMPACTION=y -# CONFIG_PAGE_REPORTING is not set -CONFIG_MIGRATION=y -CONFIG_ARCH_ENABLE_HUGEPAGE_MIGRATION=y -CONFIG_ARCH_ENABLE_THP_MIGRATION=y -CONFIG_CONTIG_ALLOC=y -CONFIG_PHYS_ADDR_T_64BIT=y -CONFIG_VIRT_TO_BUS=y -CONFIG_MMU_NOTIFIER=y CONFIG_KSM=y CONFIG_DEFAULT_MMAP_MIN_ADDR=65536 -CONFIG_ARCH_SUPPORTS_MEMORY_FAILURE=y CONFIG_MEMORY_FAILURE=y CONFIG_HWPOISON_INJECT=m CONFIG_TRANSPARENT_HUGEPAGE=y -CONFIG_TRANSPARENT_HUGEPAGE_ALWAYS=y -# CONFIG_TRANSPARENT_HUGEPAGE_MADVISE is not set -CONFIG_ARCH_WANTS_THP_SWAP=y -CONFIG_THP_SWAP=y CONFIG_CLEANCACHE=y CONFIG_FRONTSWAP=y CONFIG_CMA=y -# CONFIG_CMA_DEBUG is not set -# CONFIG_CMA_DEBUGFS is not set -# CONFIG_CMA_SYSFS is not set CONFIG_CMA_AREAS=7 CONFIG_MEM_SOFT_DIRTY=y CONFIG_ZSWAP=y -# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_DEFLATE is not set -CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZO=y -# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_842 is not set -# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4 is not set -# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_LZ4HC is not set -# CONFIG_ZSWAP_COMPRESSOR_DEFAULT_ZSTD is not set -CONFIG_ZSWAP_COMPRESSOR_DEFAULT="lzo" -CONFIG_ZSWAP_ZPOOL_DEFAULT_ZBUD=y -# CONFIG_ZSWAP_ZPOOL_DEFAULT_Z3FOLD is not set -# CONFIG_ZSWAP_ZPOOL_DEFAULT_ZSMALLOC is not set -CONFIG_ZSWAP_ZPOOL_DEFAULT="zbud" -# CONFIG_ZSWAP_DEFAULT_ON is not set -CONFIG_ZPOOL=y -CONFIG_ZBUD=y -# CONFIG_Z3FOLD is not set CONFIG_ZSMALLOC=y -# CONFIG_ZSMALLOC_STAT is not set -CONFIG_GENERIC_EARLY_IOREMAP=y -# CONFIG_DEFERRED_STRUCT_PAGE_INIT is not set -# CONFIG_IDLE_PAGE_TRACKING is not set -CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y -CONFIG_ARCH_HAS_PTE_DEVMAP=y CONFIG_ZONE_DEVICE=y -CONFIG_DEV_PAGEMAP_OPS=y -CONFIG_HMM_MIRROR=y CONFIG_DEVICE_PRIVATE=y -CONFIG_ARCH_USES_HIGH_VMA_FLAGS=y -CONFIG_ARCH_HAS_PKEYS=y -# CONFIG_PERCPU_STATS is not set -# CONFIG_GUP_TEST is not set -# CONFIG_READ_ONLY_THP_FOR_FS is not set -CONFIG_ARCH_HAS_PTE_SPECIAL=y -# end of Memory Management options - CONFIG_NET=y -CONFIG_NET_INGRESS=y -CONFIG_SKB_EXTENSIONS=y - -# -# Networking options -# CONFIG_PACKET=y CONFIG_PACKET_DIAG=y CONFIG_UNIX=y -CONFIG_UNIX_SCM=y CONFIG_UNIX_DIAG=y -CONFIG_SMC_DIAG=y -CONFIG_XDP_SOCKETS_DIAG=y -CONFIG_INET_MPTCP_DIAG=y -CONFIG_TIPC_DIAG=y -CONFIG_VSOCKETS_DIAG=y -# CONFIG_TLS is not set -CONFIG_XFRM=y -CONFIG_XFRM_ALGO=y CONFIG_XFRM_USER=y -# CONFIG_XFRM_USER_COMPAT is not set -# CONFIG_XFRM_INTERFACE is not set -# CONFIG_XFRM_SUB_POLICY is not set -# CONFIG_XFRM_MIGRATE is not set -# CONFIG_XFRM_STATISTICS is not set -CONFIG_XFRM_AH=y -CONFIG_XFRM_ESP=y -# CONFIG_NET_KEY is not set -# CONFIG_XDP_SOCKETS is not set CONFIG_INET=y CONFIG_IP_MULTICAST=y CONFIG_IP_ADVANCED_ROUTER=y -# CONFIG_IP_FIB_TRIE_STATS is not set CONFIG_IP_MULTIPLE_TABLES=y CONFIG_IP_ROUTE_MULTIPATH=y CONFIG_IP_ROUTE_VERBOSE=y -CONFIG_IP_ROUTE_CLASSID=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y CONFIG_IP_PNP_BOOTP=y CONFIG_IP_PNP_RARP=y -# CONFIG_NET_IPIP is not set -# CONFIG_NET_IPGRE_DEMUX is not set -CONFIG_NET_IP_TUNNEL=y -CONFIG_IP_MROUTE_COMMON=y CONFIG_IP_MROUTE=y -# CONFIG_IP_MROUTE_MULTIPLE_TABLES is not set CONFIG_IP_PIMSM_V1=y CONFIG_IP_PIMSM_V2=y -CONFIG_SYN_COOKIES=y -# CONFIG_NET_IPVTI is not set -# CONFIG_NET_FOU is not set -# CONFIG_NET_FOU_IP_TUNNELS is not set CONFIG_INET_AH=m CONFIG_INET_ESP=m -CONFIG_INET_IPCOMP=m CONFIG_INET_ESP_OFFLOAD=m -CONFIG_INET_TUNNEL=m -CONFIG_INET_XFRM_TUNNEL=m +CONFIG_INET_IPCOMP=m CONFIG_INET_DIAG=m -CONFIG_INET_TCP_DIAG=m CONFIG_INET_UDP_DIAG=m CONFIG_INET_RAW_DIAG=m CONFIG_INET_DIAG_DESTROY=y CONFIG_TCP_CONG_ADVANCED=y # CONFIG_TCP_CONG_BIC is not set -CONFIG_TCP_CONG_CUBIC=y # CONFIG_TCP_CONG_WESTWOOD is not set # CONFIG_TCP_CONG_HTCP is not set -# CONFIG_TCP_CONG_HSTCP is not set -# CONFIG_TCP_CONG_HYBLA is not set -# CONFIG_TCP_CONG_VEGAS is not set -# CONFIG_TCP_CONG_NV is not set -# CONFIG_TCP_CONG_SCALABLE is not set -# CONFIG_TCP_CONG_LP is not set -# CONFIG_TCP_CONG_VENO is not set -# CONFIG_TCP_CONG_YEAH is not set -# CONFIG_TCP_CONG_ILLINOIS is not set -# CONFIG_TCP_CONG_DCTCP is not set -# CONFIG_TCP_CONG_CDG is not set -# CONFIG_TCP_CONG_BBR is not set -CONFIG_DEFAULT_CUBIC=y -# CONFIG_DEFAULT_RENO is not set -CONFIG_DEFAULT_TCP_CONG="cubic" CONFIG_TCP_MD5SIG=y -CONFIG_IPV6=y -# CONFIG_IPV6_ROUTER_PREF is not set -# CONFIG_IPV6_OPTIMISTIC_DAD is not set CONFIG_INET6_AH=m CONFIG_INET6_ESP=m CONFIG_INET6_ESP_OFFLOAD=m CONFIG_INET6_IPCOMP=m CONFIG_IPV6_MIP6=m -CONFIG_INET6_XFRM_TUNNEL=m -CONFIG_INET_DCCP_DIAG=m -CONFIG_INET_SCTP_DIAG=m -# CONFIG_IPV6_ILA is not set -# CONFIG_IPV6_VTI is not set -CONFIG_IPV6_SIT=y -# CONFIG_IPV6_SIT_6RD is not set -CONFIG_IPV6_NDISC_NODETYPE=y -# CONFIG_IPV6_TUNNEL is not set -# CONFIG_IPV6_MULTIPLE_TABLES is not set -# CONFIG_IPV6_MROUTE is not set -# CONFIG_IPV6_SEG6_LWTUNNEL is not set -# CONFIG_IPV6_SEG6_HMAC is not set -# CONFIG_IPV6_RPL_LWTUNNEL is not set CONFIG_NETLABEL=y -# CONFIG_MPTCP is not set -CONFIG_NETWORK_SECMARK=y -CONFIG_NET_PTP_CLASSIFY=y -# CONFIG_NETWORK_PHY_TIMESTAMPING is not set CONFIG_NETFILTER=y -CONFIG_NETFILTER_ADVANCED=y CONFIG_BRIDGE_NETFILTER=m - -# -# Core Netfilter Configuration -# -CONFIG_NETFILTER_INGRESS=y -CONFIG_NETFILTER_NETLINK=m -CONFIG_NETFILTER_FAMILY_BRIDGE=y -CONFIG_NETFILTER_FAMILY_ARP=y -CONFIG_NETFILTER_NETLINK_ACCT=m -CONFIG_NETFILTER_NETLINK_QUEUE=m -CONFIG_NETFILTER_NETLINK_LOG=m -CONFIG_NETFILTER_NETLINK_OSF=m CONFIG_NF_CONNTRACK=m -CONFIG_NF_LOG_SYSLOG=m -CONFIG_NETFILTER_CONNCOUNT=m -CONFIG_NF_CONNTRACK_MARK=y CONFIG_NF_CONNTRACK_SECMARK=y CONFIG_NF_CONNTRACK_ZONES=y # CONFIG_NF_CONNTRACK_PROCFS is not set CONFIG_NF_CONNTRACK_EVENTS=y CONFIG_NF_CONNTRACK_TIMEOUT=y CONFIG_NF_CONNTRACK_TIMESTAMP=y -CONFIG_NF_CONNTRACK_LABELS=y -CONFIG_NF_CT_PROTO_DCCP=y -CONFIG_NF_CT_PROTO_SCTP=y -CONFIG_NF_CT_PROTO_UDPLITE=y -# CONFIG_NF_CONNTRACK_AMANDA is not set -# CONFIG_NF_CONNTRACK_FTP is not set -# CONFIG_NF_CONNTRACK_H323 is not set -# CONFIG_NF_CONNTRACK_IRC is not set -# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set -# CONFIG_NF_CONNTRACK_SNMP is not set -# CONFIG_NF_CONNTRACK_PPTP is not set -# CONFIG_NF_CONNTRACK_SANE is not set -# CONFIG_NF_CONNTRACK_SIP is not set -# CONFIG_NF_CONNTRACK_TFTP is not set -CONFIG_COMPAT_NETLINK_MESSAGES=y CONFIG_NF_CT_NETLINK=m CONFIG_NF_CT_NETLINK_TIMEOUT=m CONFIG_NF_CT_NETLINK_HELPER=m CONFIG_NETFILTER_NETLINK_GLUE_CT=y -CONFIG_SCSI_NETLINK=y -CONFIG_QUOTA_NETLINK_INTERFACE=y -CONFIG_NF_NAT=m -CONFIG_NF_NAT_REDIRECT=y -CONFIG_NF_NAT_MASQUERADE=y -CONFIG_NETFILTER_SYNPROXY=m CONFIG_NF_TABLES=m -# CONFIG_NF_TABLES_INET is not set CONFIG_NF_TABLES_NETDEV=y -# CONFIG_NFT_NUMGEN is not set CONFIG_NFT_CT=m CONFIG_NFT_COUNTER=m CONFIG_NFT_CONNLIMIT=m @@ -1180,36 +186,10 @@ CONFIG_NFT_MASQ=m CONFIG_NFT_REDIR=m CONFIG_NFT_NAT=m CONFIG_NFT_TUNNEL=m -# CONFIG_NFT_OBJREF is not set -# CONFIG_NFT_QUEUE is not set CONFIG_NFT_QUOTA=m CONFIG_NFT_REJECT=m -# CONFIG_NFT_COMPAT is not set -# CONFIG_NFT_HASH is not set -CONFIG_NFT_FIB=m CONFIG_NFT_XFRM=m -# CONFIG_NFT_SOCKET is not set -# CONFIG_NFT_OSF is not set -# CONFIG_NFT_TPROXY is not set -# CONFIG_NFT_SYNPROXY is not set CONFIG_NF_DUP_NETDEV=m -# CONFIG_NFT_DUP_NETDEV is not set -# CONFIG_NFT_FWD_NETDEV is not set -# CONFIG_NFT_FIB_NETDEV is not set -# CONFIG_NFT_REJECT_NETDEV is not set -# CONFIG_NF_FLOW_TABLE is not set -CONFIG_NETFILTER_XTABLES=m -CONFIG_NETFILTER_XTABLES_COMPAT=y - -# -# Xtables combined modules -# -CONFIG_NETFILTER_XT_MARK=m -CONFIG_NETFILTER_XT_CONNMARK=m - -# -# Xtables targets -# CONFIG_NETFILTER_XT_TARGET_AUDIT=m CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m @@ -1217,30 +197,19 @@ CONFIG_NETFILTER_XT_TARGET_CONNMARK=m CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m CONFIG_NETFILTER_XT_TARGET_CT=m CONFIG_NETFILTER_XT_TARGET_DSCP=m -CONFIG_NETFILTER_XT_TARGET_HL=m CONFIG_NETFILTER_XT_TARGET_HMARK=m CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m CONFIG_NETFILTER_XT_TARGET_LED=m CONFIG_NETFILTER_XT_TARGET_LOG=m CONFIG_NETFILTER_XT_TARGET_MARK=m -CONFIG_NETFILTER_XT_NAT=m -CONFIG_NETFILTER_XT_TARGET_NETMAP=m CONFIG_NETFILTER_XT_TARGET_NFLOG=m CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m -# CONFIG_NETFILTER_XT_TARGET_NOTRACK is not set -CONFIG_NETFILTER_XT_TARGET_RATEEST=m -CONFIG_NETFILTER_XT_TARGET_REDIRECT=m -CONFIG_NETFILTER_XT_TARGET_MASQUERADE=m CONFIG_NETFILTER_XT_TARGET_TEE=m CONFIG_NETFILTER_XT_TARGET_TPROXY=m CONFIG_NETFILTER_XT_TARGET_TRACE=m CONFIG_NETFILTER_XT_TARGET_SECMARK=m CONFIG_NETFILTER_XT_TARGET_TCPMSS=m CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m - -# -# Xtables matches -# CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m CONFIG_NETFILTER_XT_MATCH_BPF=m CONFIG_NETFILTER_XT_MATCH_CGROUP=m @@ -1255,11 +224,9 @@ CONFIG_NETFILTER_XT_MATCH_CPU=m CONFIG_NETFILTER_XT_MATCH_DCCP=m CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m CONFIG_NETFILTER_XT_MATCH_DSCP=m -CONFIG_NETFILTER_XT_MATCH_ECN=m CONFIG_NETFILTER_XT_MATCH_ESP=m CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m CONFIG_NETFILTER_XT_MATCH_HELPER=m -CONFIG_NETFILTER_XT_MATCH_HL=m CONFIG_NETFILTER_XT_MATCH_IPCOMP=m CONFIG_NETFILTER_XT_MATCH_IPRANGE=m CONFIG_NETFILTER_XT_MATCH_L2TP=m @@ -1279,33 +246,17 @@ CONFIG_NETFILTER_XT_MATCH_RATEEST=m CONFIG_NETFILTER_XT_MATCH_REALM=m CONFIG_NETFILTER_XT_MATCH_RECENT=m CONFIG_NETFILTER_XT_MATCH_SCTP=m -# CONFIG_NETFILTER_XT_MATCH_SOCKET is not set CONFIG_NETFILTER_XT_MATCH_STATE=m CONFIG_NETFILTER_XT_MATCH_STATISTIC=m CONFIG_NETFILTER_XT_MATCH_STRING=m CONFIG_NETFILTER_XT_MATCH_TCPMSS=m CONFIG_NETFILTER_XT_MATCH_TIME=m CONFIG_NETFILTER_XT_MATCH_U32=m -# end of Core Netfilter Configuration - -# CONFIG_IP_SET is not set -# CONFIG_IP_VS is not set - -# -# IP: Netfilter Configuration -# -CONFIG_NF_DEFRAG_IPV4=m -# CONFIG_NF_SOCKET_IPV4 is not set -CONFIG_NF_TPROXY_IPV4=m CONFIG_NF_TABLES_IPV4=y -CONFIG_NFT_REJECT_IPV4=m CONFIG_NFT_DUP_IPV4=m CONFIG_NFT_FIB_IPV4=m CONFIG_NF_TABLES_ARP=y -CONFIG_NF_DUP_IPV4=m -# CONFIG_NF_LOG_ARP is not set CONFIG_NF_LOG_IPV4=m -CONFIG_NF_REJECT_IPV4=m CONFIG_IP_NF_IPTABLES=m CONFIG_IP_NF_MATCH_AH=m CONFIG_IP_NF_MATCH_ECN=m @@ -1327,1744 +278,127 @@ CONFIG_IP_NF_SECURITY=m CONFIG_IP_NF_ARPTABLES=m CONFIG_IP_NF_ARPFILTER=m CONFIG_IP_NF_ARP_MANGLE=m -# end of IP: Netfilter Configuration - -# -# IPv6: Netfilter Configuration -# -# CONFIG_NF_SOCKET_IPV6 is not set -CONFIG_NF_TPROXY_IPV6=m CONFIG_NF_TABLES_IPV6=y -CONFIG_NFT_REJECT_IPV6=m CONFIG_NFT_DUP_IPV6=m CONFIG_NFT_FIB_IPV6=m -CONFIG_NF_DUP_IPV6=m -CONFIG_NF_REJECT_IPV6=m -CONFIG_NF_LOG_IPV6=m CONFIG_IP6_NF_IPTABLES=m -# CONFIG_IP6_NF_MATCH_AH is not set -# CONFIG_IP6_NF_MATCH_EUI64 is not set -# CONFIG_IP6_NF_MATCH_FRAG is not set -# CONFIG_IP6_NF_MATCH_OPTS is not set -# CONFIG_IP6_NF_MATCH_HL is not set -# CONFIG_IP6_NF_MATCH_IPV6HEADER is not set -# CONFIG_IP6_NF_MATCH_MH is not set -# CONFIG_IP6_NF_MATCH_RPFILTER is not set -# CONFIG_IP6_NF_MATCH_RT is not set -# CONFIG_IP6_NF_MATCH_SRH is not set -# CONFIG_IP6_NF_TARGET_HL is not set CONFIG_IP6_NF_FILTER=m CONFIG_IP6_NF_TARGET_REJECT=m -# CONFIG_IP6_NF_TARGET_SYNPROXY is not set CONFIG_IP6_NF_MANGLE=m -# CONFIG_IP6_NF_RAW is not set -# CONFIG_IP6_NF_SECURITY is not set CONFIG_IP6_NF_NAT=m CONFIG_IP6_NF_TARGET_MASQUERADE=m -# CONFIG_IP6_NF_TARGET_NPT is not set -# end of IPv6: Netfilter Configuration - -CONFIG_NF_DEFRAG_IPV6=m -# CONFIG_NF_TABLES_BRIDGE is not set -# CONFIG_NF_CONNTRACK_BRIDGE is not set -# CONFIG_BRIDGE_NF_EBTABLES is not set -# CONFIG_BPFILTER is not set -# CONFIG_IP_DCCP is not set -# CONFIG_IP_SCTP is not set -# CONFIG_RDS is not set -# CONFIG_TIPC is not set -# CONFIG_ATM is not set -# CONFIG_L2TP is not set -CONFIG_STP=y CONFIG_BRIDGE=y -CONFIG_BRIDGE_IGMP_SNOOPING=y -# CONFIG_BRIDGE_VLAN_FILTERING is not set -# CONFIG_BRIDGE_MRP is not set -# CONFIG_BRIDGE_CFM is not set -# CONFIG_NET_DSA is not set CONFIG_VLAN_8021Q=y -# CONFIG_VLAN_8021Q_GVRP is not set -# CONFIG_VLAN_8021Q_MVRP is not set -# CONFIG_DECNET is not set -CONFIG_LLC=y -# CONFIG_LLC2 is not set -# CONFIG_ATALK is not set -# CONFIG_X25 is not set -# CONFIG_LAPB is not set -# CONFIG_PHONET is not set -# CONFIG_6LOWPAN is not set -# CONFIG_IEEE802154 is not set CONFIG_NET_SCHED=y - -# -# Queueing/Scheduling -# -# CONFIG_NET_SCH_CBQ is not set -# CONFIG_NET_SCH_HTB is not set -# CONFIG_NET_SCH_HFSC is not set -# CONFIG_NET_SCH_PRIO is not set -# CONFIG_NET_SCH_MULTIQ is not set -# CONFIG_NET_SCH_RED is not set -# CONFIG_NET_SCH_SFB is not set -# CONFIG_NET_SCH_SFQ is not set -# CONFIG_NET_SCH_TEQL is not set -# CONFIG_NET_SCH_TBF is not set -# CONFIG_NET_SCH_CBS is not set -# CONFIG_NET_SCH_ETF is not set -# CONFIG_NET_SCH_TAPRIO is not set -# CONFIG_NET_SCH_GRED is not set -# CONFIG_NET_SCH_DSMARK is not set -# CONFIG_NET_SCH_NETEM is not set -# CONFIG_NET_SCH_DRR is not set -# CONFIG_NET_SCH_MQPRIO is not set -# CONFIG_NET_SCH_SKBPRIO is not set -# CONFIG_NET_SCH_CHOKE is not set -# CONFIG_NET_SCH_QFQ is not set -# CONFIG_NET_SCH_CODEL is not set -# CONFIG_NET_SCH_FQ_CODEL is not set -# CONFIG_NET_SCH_CAKE is not set -# CONFIG_NET_SCH_FQ is not set -# CONFIG_NET_SCH_HHF is not set -# CONFIG_NET_SCH_PIE is not set -# CONFIG_NET_SCH_INGRESS is not set -# CONFIG_NET_SCH_PLUG is not set -# CONFIG_NET_SCH_ETS is not set -# CONFIG_NET_SCH_DEFAULT is not set - -# -# Classification -# -CONFIG_NET_CLS=y -# CONFIG_NET_CLS_BASIC is not set -# CONFIG_NET_CLS_TCINDEX is not set -# CONFIG_NET_CLS_ROUTE4 is not set -# CONFIG_NET_CLS_FW is not set -# CONFIG_NET_CLS_U32 is not set -# CONFIG_NET_CLS_RSVP is not set -# CONFIG_NET_CLS_RSVP6 is not set -# CONFIG_NET_CLS_FLOW is not set -# CONFIG_NET_CLS_CGROUP is not set -# CONFIG_NET_CLS_BPF is not set -# CONFIG_NET_CLS_FLOWER is not set -# CONFIG_NET_CLS_MATCHALL is not set CONFIG_NET_EMATCH=y -CONFIG_NET_EMATCH_STACK=32 -# CONFIG_NET_EMATCH_CMP is not set -# CONFIG_NET_EMATCH_NBYTE is not set -# CONFIG_NET_EMATCH_U32 is not set -# CONFIG_NET_EMATCH_META is not set -# CONFIG_NET_EMATCH_TEXT is not set -# CONFIG_NET_EMATCH_IPT is not set CONFIG_NET_CLS_ACT=y -# CONFIG_NET_ACT_POLICE is not set -# CONFIG_NET_ACT_GACT is not set -# CONFIG_NET_ACT_MIRRED is not set -# CONFIG_NET_ACT_SAMPLE is not set -# CONFIG_NET_ACT_IPT is not set -# CONFIG_NET_ACT_NAT is not set -# CONFIG_NET_ACT_PEDIT is not set -# CONFIG_NET_ACT_SIMP is not set -# CONFIG_NET_ACT_SKBEDIT is not set -# CONFIG_NET_ACT_CSUM is not set -# CONFIG_NET_ACT_MPLS is not set -# CONFIG_NET_ACT_VLAN is not set -# CONFIG_NET_ACT_BPF is not set -# CONFIG_NET_ACT_CONNMARK is not set -# CONFIG_NET_ACT_CTINFO is not set -# CONFIG_NET_ACT_SKBMOD is not set -# CONFIG_NET_ACT_IFE is not set -# CONFIG_NET_ACT_TUNNEL_KEY is not set -# CONFIG_NET_ACT_GATE is not set -# CONFIG_NET_TC_SKB_EXT is not set -CONFIG_NET_SCH_FIFO=y -# CONFIG_DCB is not set -CONFIG_DNS_RESOLVER=y -# CONFIG_BATMAN_ADV is not set -# CONFIG_OPENVSWITCH is not set -# CONFIG_VSOCKETS is not set CONFIG_NETLINK_DIAG=y -# CONFIG_MPLS is not set -# CONFIG_NET_NSH is not set -# CONFIG_HSR is not set -# CONFIG_NET_SWITCHDEV is not set -# CONFIG_NET_L3_MASTER_DEV is not set -# CONFIG_QRTR is not set -# CONFIG_NET_NCSI is not set -CONFIG_PCPU_DEV_REFCNT=y -CONFIG_RPS=y -CONFIG_RFS_ACCEL=y -CONFIG_SOCK_RX_QUEUE_MAPPING=y -CONFIG_XPS=y -# CONFIG_CGROUP_NET_PRIO is not set -CONFIG_CGROUP_NET_CLASSID=y -CONFIG_NET_RX_BUSY_POLL=y -CONFIG_BQL=y -# CONFIG_BPF_STREAM_PARSER is not set -CONFIG_NET_FLOW_LIMIT=y - -# -# Network testing -# -# CONFIG_NET_PKTGEN is not set -# CONFIG_NET_DROP_MONITOR is not set -# end of Network testing -# end of Networking options - CONFIG_HAMRADIO=y - -# -# Packet Radio protocols -# -# CONFIG_AX25 is not set -# CONFIG_CAN is not set -# CONFIG_BT is not set -# CONFIG_AF_RXRPC is not set -# CONFIG_AF_KCM is not set -CONFIG_FIB_RULES=y -CONFIG_WIRELESS=y -# CONFIG_CFG80211 is not set - -# -# CFG80211 needs to be enabled for MAC80211 -# -CONFIG_MAC80211_STA_HASH_MAX_SIZE=0 CONFIG_RFKILL=y -CONFIG_RFKILL_LEDS=y CONFIG_RFKILL_INPUT=y -# CONFIG_NET_9P is not set -# CONFIG_CAIF is not set -# CONFIG_CEPH_LIB is not set -# CONFIG_NFC is not set -# CONFIG_PSAMPLE is not set -# CONFIG_NET_IFE is not set -# CONFIG_LWTUNNEL is not set -CONFIG_DST_CACHE=y -CONFIG_GRO_CELLS=y -CONFIG_NET_SELFTESTS=y -CONFIG_NET_SOCK_MSG=y -# CONFIG_FAILOVER is not set -CONFIG_ETHTOOL_NETLINK=y - -# -# Device Drivers -# -CONFIG_HAVE_EISA=y -# CONFIG_EISA is not set -CONFIG_HAVE_PCI=y CONFIG_PCI=y -CONFIG_PCI_DOMAINS=y CONFIG_PCIEPORTBUS=y CONFIG_HOTPLUG_PCI_PCIE=y CONFIG_PCIEAER=y -# CONFIG_PCIEAER_INJECT is not set -# CONFIG_PCIE_ECRC is not set -CONFIG_PCIEASPM=y -CONFIG_PCIEASPM_DEFAULT=y -# CONFIG_PCIEASPM_POWERSAVE is not set -# CONFIG_PCIEASPM_POWER_SUPERSAVE is not set -# CONFIG_PCIEASPM_PERFORMANCE is not set -CONFIG_PCIE_PME=y -# CONFIG_PCIE_DPC is not set -# CONFIG_PCIE_PTM is not set -CONFIG_PCI_MSI=y -CONFIG_PCI_MSI_IRQ_DOMAIN=y -CONFIG_PCI_QUIRKS=y -# CONFIG_PCI_DEBUG is not set CONFIG_PCI_REALLOC_ENABLE_AUTO=y CONFIG_PCI_STUB=y -# CONFIG_PCI_PF_STUB is not set -CONFIG_PCI_ATS=y -CONFIG_PCI_LOCKLESS_CONFIG=y CONFIG_PCI_IOV=y -CONFIG_PCI_PRI=y -CONFIG_PCI_PASID=y -# CONFIG_PCI_P2PDMA is not set -CONFIG_PCI_LABEL=y -# CONFIG_PCIE_BUS_TUNE_OFF is not set -CONFIG_PCIE_BUS_DEFAULT=y -# CONFIG_PCIE_BUS_SAFE is not set -# CONFIG_PCIE_BUS_PERFORMANCE is not set -# CONFIG_PCIE_BUS_PEER2PEER is not set CONFIG_HOTPLUG_PCI=y -# CONFIG_HOTPLUG_PCI_ACPI is not set -# CONFIG_HOTPLUG_PCI_CPCI is not set -# CONFIG_HOTPLUG_PCI_SHPC is not set - -# -# PCI controller drivers -# -# CONFIG_VMD is not set - -# -# DesignWare PCI Core Support -# -# CONFIG_PCIE_DW_PLAT_HOST is not set -# CONFIG_PCI_MESON is not set -# end of DesignWare PCI Core Support - -# -# Mobiveil PCIe Core Support -# -# end of Mobiveil PCIe Core Support - -# -# Cadence PCIe controllers support -# -# end of Cadence PCIe controllers support -# end of PCI controller drivers - -# -# PCI Endpoint -# -# CONFIG_PCI_ENDPOINT is not set -# end of PCI Endpoint - -# -# PCI switch controller drivers -# -# CONFIG_PCI_SW_SWITCHTEC is not set -# end of PCI switch controller drivers - -# CONFIG_CXL_BUS is not set -# CONFIG_PCCARD is not set CONFIG_RAPIDIO=y -# CONFIG_RAPIDIO_TSI721 is not set -CONFIG_RAPIDIO_DISC_TIMEOUT=30 -# CONFIG_RAPIDIO_ENABLE_RX_TX_PORTS is not set CONFIG_RAPIDIO_DMA_ENGINE=y -# CONFIG_RAPIDIO_DEBUG is not set -# CONFIG_RAPIDIO_ENUM_BASIC is not set -# CONFIG_RAPIDIO_CHMAN is not set -# CONFIG_RAPIDIO_MPORT_CDEV is not set - -# -# RapidIO Switch drivers -# -# CONFIG_RAPIDIO_TSI57X is not set -# CONFIG_RAPIDIO_CPS_XX is not set -# CONFIG_RAPIDIO_TSI568 is not set -# CONFIG_RAPIDIO_CPS_GEN2 is not set -# CONFIG_RAPIDIO_RXS_GEN3 is not set -# end of RapidIO Switch drivers - -# -# Generic Driver Options -# CONFIG_UEVENT_HELPER=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y -CONFIG_STANDALONE=y # CONFIG_PREVENT_FIRMWARE_BUILD is not set - -# -# Firmware loader -# -CONFIG_FW_LOADER=y -CONFIG_EXTRA_FIRMWARE="" -# CONFIG_FW_LOADER_USER_HELPER is not set -# CONFIG_FW_LOADER_COMPRESS is not set -CONFIG_FW_CACHE=y -# end of Firmware loader - -CONFIG_ALLOW_DEV_COREDUMP=y -# CONFIG_DEBUG_DRIVER is not set -# CONFIG_DEBUG_DEVRES is not set -# CONFIG_DEBUG_TEST_DRIVER_REMOVE is not set -# CONFIG_TEST_ASYNC_DRIVER_PROBE is not set -CONFIG_GENERIC_CPU_AUTOPROBE=y -CONFIG_GENERIC_CPU_VULNERABILITIES=y -CONFIG_DMA_SHARED_BUFFER=y -# CONFIG_DMA_FENCE_TRACE is not set -# end of Generic Driver Options - -# -# Bus devices -# -# CONFIG_MHI_BUS is not set -# end of Bus devices - -# CONFIG_CONNECTOR is not set -# CONFIG_GNSS is not set -# CONFIG_MTD is not set -# CONFIG_OF is not set -CONFIG_ARCH_MIGHT_HAVE_PC_PARPORT=y +CONFIG_EFI_VARS=y CONFIG_PARPORT=y CONFIG_PARPORT_PC=y CONFIG_PARPORT_SERIAL=y -# CONFIG_PARPORT_PC_FIFO is not set -# CONFIG_PARPORT_PC_SUPERIO is not set -# CONFIG_PARPORT_AX88796 is not set -# CONFIG_PARPORT_1284 is not set -CONFIG_PNP=y -CONFIG_PNP_DEBUG_MESSAGES=y - -# -# Protocols -# -CONFIG_PNPACPI=y -CONFIG_BLK_DEV=y -# CONFIG_BLK_DEV_NULL_BLK is not set -# CONFIG_BLK_DEV_FD is not set -CONFIG_CDROM=y -# CONFIG_PARIDE is not set -# CONFIG_BLK_DEV_PCIESSD_MTIP32XX is not set -# CONFIG_ZRAM is not set CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_LOOP_MIN_COUNT=8 -# CONFIG_BLK_DEV_CRYPTOLOOP is not set -# CONFIG_BLK_DEV_DRBD is not set -# CONFIG_BLK_DEV_NBD is not set -# CONFIG_BLK_DEV_SX8 is not set CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=16384 -# CONFIG_CDROM_PKTCDVD is not set -# CONFIG_ATA_OVER_ETH is not set -# CONFIG_BLK_DEV_RBD is not set -# CONFIG_BLK_DEV_RSXX is not set - -# -# NVME Support -# -CONFIG_NVME_CORE=y CONFIG_BLK_DEV_NVME=y -# CONFIG_NVME_MULTIPATH is not set -# CONFIG_NVME_HWMON is not set -# CONFIG_NVME_FC is not set -# CONFIG_NVME_TCP is not set -# CONFIG_NVME_TARGET is not set -# end of NVME Support - -# -# Misc devices -# -# CONFIG_AD525X_DPOT is not set -# CONFIG_DUMMY_IRQ is not set -# CONFIG_IBM_ASM is not set -# CONFIG_PHANTOM is not set -# CONFIG_TIFM_CORE is not set -# CONFIG_ICS932S401 is not set -# CONFIG_ENCLOSURE_SERVICES is not set -# CONFIG_HP_ILO is not set -# CONFIG_APDS9802ALS is not set -# CONFIG_ISL29003 is not set -# CONFIG_ISL29020 is not set -# CONFIG_SENSORS_TSL2550 is not set -# CONFIG_SENSORS_BH1770 is not set -# CONFIG_SENSORS_APDS990X is not set -# CONFIG_HMC6352 is not set -# CONFIG_DS1682 is not set -# CONFIG_SRAM is not set -# CONFIG_DW_XDATA_PCIE is not set -# CONFIG_PCI_ENDPOINT_TEST is not set -# CONFIG_XILINX_SDFEC is not set -# CONFIG_C2PORT is not set - -# -# EEPROM support -# -# CONFIG_EEPROM_AT24 is not set -# CONFIG_EEPROM_LEGACY is not set -# CONFIG_EEPROM_MAX6875 is not set -# CONFIG_EEPROM_93CX6 is not set -# CONFIG_EEPROM_IDT_89HPESX is not set -# CONFIG_EEPROM_EE1004 is not set -# end of EEPROM support - -# CONFIG_CB710_CORE is not set - -# -# Texas Instruments shared transport line discipline -# -# end of Texas Instruments shared transport line discipline - -# CONFIG_SENSORS_LIS3_I2C is not set -# CONFIG_ALTERA_STAPL is not set -# CONFIG_INTEL_MEI is not set -# CONFIG_INTEL_MEI_ME is not set -# CONFIG_INTEL_MEI_TXE is not set -# CONFIG_VMWARE_VMCI is not set -# CONFIG_GENWQE is not set -# CONFIG_ECHO is not set -# CONFIG_BCM_VK is not set -# CONFIG_MISC_ALCOR_PCI is not set -# CONFIG_MISC_RTSX_PCI is not set -# CONFIG_MISC_RTSX_USB is not set -# CONFIG_HABANA_AI is not set -# CONFIG_UACCE is not set -# CONFIG_PVPANIC is not set -# end of Misc devices - -CONFIG_HAVE_IDE=y -# CONFIG_IDE is not set - -# -# SCSI device support -# -CONFIG_SCSI_MOD=y -# CONFIG_RAID_ATTRS is not set -CONFIG_SCSI=y -CONFIG_SCSI_DMA=y -CONFIG_SCSI_PROC_FS=y - -# -# SCSI support type (disk, tape, CD-ROM) -# CONFIG_BLK_DEV_SD=y -# CONFIG_CHR_DEV_ST is not set CONFIG_BLK_DEV_SR=y CONFIG_CHR_DEV_SG=y -# CONFIG_CHR_DEV_SCH is not set CONFIG_SCSI_CONSTANTS=y -# CONFIG_SCSI_LOGGING is not set -# CONFIG_SCSI_SCAN_ASYNC is not set - -# -# SCSI Transports -# -CONFIG_SCSI_SPI_ATTRS=y -# CONFIG_SCSI_FC_ATTRS is not set CONFIG_SCSI_ISCSI_ATTRS=y -# CONFIG_SCSI_SAS_ATTRS is not set -# CONFIG_SCSI_SAS_LIBSAS is not set -# CONFIG_SCSI_SRP_ATTRS is not set -# end of SCSI Transports - # CONFIG_SCSI_LOWLEVEL is not set -# CONFIG_SCSI_DH is not set -# end of SCSI device support - CONFIG_ATA=y -CONFIG_SATA_HOST=y -CONFIG_PATA_TIMINGS=y -CONFIG_ATA_VERBOSE_ERROR=y -CONFIG_ATA_FORCE=y -CONFIG_ATA_ACPI=y -# CONFIG_SATA_ZPODD is not set -CONFIG_SATA_PMP=y - -# -# Controllers with non-SFF native interface -# CONFIG_SATA_AHCI=y -CONFIG_SATA_MOBILE_LPM_POLICY=0 CONFIG_SATA_AHCI_PLATFORM=y -# CONFIG_SATA_INIC162X is not set -# CONFIG_SATA_ACARD_AHCI is not set CONFIG_SATA_SIL24=y -CONFIG_ATA_SFF=y - -# -# SFF controllers with custom DMA interface -# -# CONFIG_PDC_ADMA is not set -# CONFIG_SATA_QSTOR is not set CONFIG_SATA_SX4=y -CONFIG_ATA_BMDMA=y - -# -# SATA SFF controllers with BMDMA -# CONFIG_ATA_PIIX=y -# CONFIG_SATA_DWC is not set -# CONFIG_SATA_MV is not set -# CONFIG_SATA_NV is not set CONFIG_SATA_PROMISE=y CONFIG_SATA_SIL=y -# CONFIG_SATA_SIS is not set -# CONFIG_SATA_SVW is not set -# CONFIG_SATA_ULI is not set -# CONFIG_SATA_VIA is not set -# CONFIG_SATA_VITESSE is not set - -# -# PATA SFF controllers with BMDMA -# -# CONFIG_PATA_ALI is not set CONFIG_PATA_AMD=y -# CONFIG_PATA_ARTOP is not set CONFIG_PATA_ATIIXP=y -# CONFIG_PATA_ATP867X is not set -# CONFIG_PATA_CMD64X is not set -# CONFIG_PATA_CYPRESS is not set -# CONFIG_PATA_EFAR is not set -# CONFIG_PATA_HPT366 is not set -# CONFIG_PATA_HPT37X is not set -# CONFIG_PATA_HPT3X2N is not set -# CONFIG_PATA_HPT3X3 is not set -# CONFIG_PATA_IT8213 is not set -# CONFIG_PATA_IT821X is not set -# CONFIG_PATA_JMICRON is not set -# CONFIG_PATA_MARVELL is not set -# CONFIG_PATA_NETCELL is not set -# CONFIG_PATA_NINJA32 is not set -# CONFIG_PATA_NS87415 is not set CONFIG_PATA_OLDPIIX=y -# CONFIG_PATA_OPTIDMA is not set -# CONFIG_PATA_PDC2027X is not set -# CONFIG_PATA_PDC_OLD is not set -# CONFIG_PATA_RADISYS is not set -# CONFIG_PATA_RDC is not set CONFIG_PATA_SCH=y CONFIG_PATA_SERVERWORKS=y -# CONFIG_PATA_SIL680 is not set -# CONFIG_PATA_SIS is not set -# CONFIG_PATA_TOSHIBA is not set -# CONFIG_PATA_TRIFLEX is not set -# CONFIG_PATA_VIA is not set -# CONFIG_PATA_WINBOND is not set - -# -# PIO-only SFF controllers -# -# CONFIG_PATA_CMD640_PCI is not set -# CONFIG_PATA_MPIIX is not set -# CONFIG_PATA_NS87410 is not set -# CONFIG_PATA_OPTI is not set -# CONFIG_PATA_PLATFORM is not set -# CONFIG_PATA_RZ1000 is not set - -# -# Generic fallback / legacy drivers -# -# CONFIG_PATA_ACPI is not set CONFIG_ATA_GENERIC=y -# CONFIG_PATA_LEGACY is not set CONFIG_MD=y CONFIG_BLK_DEV_MD=y -CONFIG_MD_AUTODETECT=y -# CONFIG_MD_LINEAR is not set -# CONFIG_MD_RAID0 is not set -# CONFIG_MD_RAID1 is not set -# CONFIG_MD_RAID10 is not set -# CONFIG_MD_RAID456 is not set -# CONFIG_MD_MULTIPATH is not set -# CONFIG_MD_FAULTY is not set -# CONFIG_BCACHE is not set -CONFIG_BLK_DEV_DM_BUILTIN=y CONFIG_BLK_DEV_DM=y -# CONFIG_DM_DEBUG is not set -# CONFIG_DM_UNSTRIPED is not set -# CONFIG_DM_CRYPT is not set -# CONFIG_DM_SNAPSHOT is not set -# CONFIG_DM_THIN_PROVISIONING is not set -# CONFIG_DM_CACHE is not set -# CONFIG_DM_WRITECACHE is not set -# CONFIG_DM_EBS is not set -# CONFIG_DM_ERA is not set -# CONFIG_DM_CLONE is not set CONFIG_DM_MIRROR=y -# CONFIG_DM_LOG_USERSPACE is not set -# CONFIG_DM_RAID is not set CONFIG_DM_ZERO=y -# CONFIG_DM_MULTIPATH is not set -# CONFIG_DM_DELAY is not set -# CONFIG_DM_DUST is not set -# CONFIG_DM_INIT is not set -# CONFIG_DM_UEVENT is not set -# CONFIG_DM_FLAKEY is not set -# CONFIG_DM_VERITY is not set -# CONFIG_DM_SWITCH is not set -# CONFIG_DM_LOG_WRITES is not set -# CONFIG_DM_INTEGRITY is not set -# CONFIG_TARGET_CORE is not set CONFIG_FUSION=y CONFIG_FUSION_SPI=y -# CONFIG_FUSION_SAS is not set -CONFIG_FUSION_MAX_SGE=128 -# CONFIG_FUSION_CTL is not set -# CONFIG_FUSION_LOGGING is not set - -# -# IEEE 1394 (FireWire) support -# -# CONFIG_FIREWIRE is not set -# CONFIG_FIREWIRE_NOSY is not set -# end of IEEE 1394 (FireWire) support - -# CONFIG_MACINTOSH_DRIVERS is not set CONFIG_NETDEVICES=y -CONFIG_MII=y -CONFIG_NET_CORE=y -# CONFIG_BONDING is not set -# CONFIG_DUMMY is not set -# CONFIG_WIREGUARD is not set -# CONFIG_EQUALIZER is not set -# CONFIG_NET_FC is not set -# CONFIG_IFB is not set -# CONFIG_NET_TEAM is not set CONFIG_MACVLAN=y -# CONFIG_MACVTAP is not set -# CONFIG_IPVLAN is not set -# CONFIG_VXLAN is not set -# CONFIG_GENEVE is not set -# CONFIG_BAREUDP is not set -# CONFIG_GTP is not set -# CONFIG_MACSEC is not set CONFIG_NETCONSOLE=y CONFIG_NETCONSOLE_DYNAMIC=y -CONFIG_NETPOLL=y -CONFIG_NET_POLL_CONTROLLER=y -# CONFIG_RIONET is not set CONFIG_TUN=y -# CONFIG_TUN_VNET_CROSS_LE is not set CONFIG_VETH=y -# CONFIG_NLMON is not set -# CONFIG_ARCNET is not set -CONFIG_ETHERNET=y -CONFIG_MDIO=y -CONFIG_NET_VENDOR_3COM=y -# CONFIG_VORTEX is not set -# CONFIG_TYPHOON is not set -CONFIG_NET_VENDOR_ADAPTEC=y -# CONFIG_ADAPTEC_STARFIRE is not set -CONFIG_NET_VENDOR_AGERE=y -# CONFIG_ET131X is not set -CONFIG_NET_VENDOR_ALACRITECH=y -# CONFIG_SLICOSS is not set -CONFIG_NET_VENDOR_ALTEON=y -# CONFIG_ACENIC is not set -# CONFIG_ALTERA_TSE is not set -CONFIG_NET_VENDOR_AMAZON=y -# CONFIG_ENA_ETHERNET is not set -CONFIG_NET_VENDOR_AMD=y -# CONFIG_AMD8111_ETH is not set -# CONFIG_PCNET32 is not set -# CONFIG_AMD_XGBE is not set -CONFIG_NET_VENDOR_AQUANTIA=y -# CONFIG_AQTION is not set -CONFIG_NET_VENDOR_ARC=y -CONFIG_NET_VENDOR_ATHEROS=y -# CONFIG_ATL2 is not set -# CONFIG_ATL1 is not set -# CONFIG_ATL1E is not set -# CONFIG_ATL1C is not set CONFIG_ALX=y -CONFIG_NET_VENDOR_BROADCOM=y -# CONFIG_B44 is not set -# CONFIG_BCMGENET is not set CONFIG_BNX2=y -# CONFIG_CNIC is not set CONFIG_TIGON3=y -CONFIG_TIGON3_HWMON=y -# CONFIG_BNX2X is not set -# CONFIG_SYSTEMPORT is not set -# CONFIG_BNXT is not set -CONFIG_NET_VENDOR_BROCADE=y -# CONFIG_BNA is not set -CONFIG_NET_VENDOR_CADENCE=y -# CONFIG_MACB is not set -CONFIG_NET_VENDOR_CAVIUM=y -# CONFIG_THUNDER_NIC_PF is not set -# CONFIG_THUNDER_NIC_VF is not set -# CONFIG_THUNDER_NIC_BGX is not set -# CONFIG_THUNDER_NIC_RGX is not set CONFIG_CAVIUM_PTP=y -# CONFIG_LIQUIDIO is not set -# CONFIG_LIQUIDIO_VF is not set -CONFIG_NET_VENDOR_CHELSIO=y -# CONFIG_CHELSIO_T1 is not set -# CONFIG_CHELSIO_T3 is not set -# CONFIG_CHELSIO_T4 is not set -# CONFIG_CHELSIO_T4VF is not set -CONFIG_NET_VENDOR_CISCO=y -# CONFIG_ENIC is not set -CONFIG_NET_VENDOR_CORTINA=y -# CONFIG_CX_ECAT is not set -# CONFIG_DNET is not set -CONFIG_NET_VENDOR_DEC=y CONFIG_NET_TULIP=y -# CONFIG_DE2104X is not set -# CONFIG_TULIP is not set -# CONFIG_DE4X5 is not set -# CONFIG_WINBOND_840 is not set -# CONFIG_DM9102 is not set -# CONFIG_ULI526X is not set -CONFIG_NET_VENDOR_DLINK=y -# CONFIG_DL2K is not set -# CONFIG_SUNDANCE is not set -CONFIG_NET_VENDOR_EMULEX=y -# CONFIG_BE2NET is not set -CONFIG_NET_VENDOR_EZCHIP=y -CONFIG_NET_VENDOR_GOOGLE=y -# CONFIG_GVE is not set -CONFIG_NET_VENDOR_HUAWEI=y -# CONFIG_HINIC is not set -CONFIG_NET_VENDOR_I825XX=y -CONFIG_NET_VENDOR_INTEL=y CONFIG_E100=y CONFIG_E1000=y CONFIG_E1000E=y -CONFIG_E1000E_HWTS=y CONFIG_IGB=y -CONFIG_IGB_HWMON=y CONFIG_IGBVF=y CONFIG_IXGB=y CONFIG_IXGBE=y -CONFIG_IXGBE_HWMON=y -# CONFIG_IXGBEVF is not set CONFIG_I40E=y -# CONFIG_I40EVF is not set -# CONFIG_ICE is not set -# CONFIG_FM10K is not set -# CONFIG_IGC is not set -CONFIG_NET_VENDOR_MICROSOFT=y -# CONFIG_JME is not set -CONFIG_NET_VENDOR_MARVELL=y -# CONFIG_MVMDIO is not set -# CONFIG_SKGE is not set CONFIG_SKY2=y -# CONFIG_SKY2_DEBUG is not set -CONFIG_NET_VENDOR_MELLANOX=y -# CONFIG_MLX4_EN is not set -# CONFIG_MLX5_CORE is not set -# CONFIG_MLXSW_CORE is not set -# CONFIG_MLXFW is not set -CONFIG_NET_VENDOR_MICREL=y -# CONFIG_KS8842 is not set -# CONFIG_KS8851_MLL is not set -# CONFIG_KSZ884X_PCI is not set -CONFIG_NET_VENDOR_MICROCHIP=y -# CONFIG_LAN743X is not set -CONFIG_NET_VENDOR_MICROSEMI=y -CONFIG_NET_VENDOR_MYRI=y -# CONFIG_MYRI10GE is not set -# CONFIG_FEALNX is not set -CONFIG_NET_VENDOR_NATSEMI=y -# CONFIG_NATSEMI is not set -# CONFIG_NS83820 is not set -CONFIG_NET_VENDOR_NETERION=y -# CONFIG_S2IO is not set -# CONFIG_VXGE is not set -CONFIG_NET_VENDOR_NETRONOME=y -# CONFIG_NFP is not set -CONFIG_NET_VENDOR_NI=y -# CONFIG_NI_XGE_MANAGEMENT_ENET is not set -CONFIG_NET_VENDOR_8390=y -# CONFIG_NE2K_PCI is not set -CONFIG_NET_VENDOR_NVIDIA=y CONFIG_FORCEDETH=y -CONFIG_NET_VENDOR_OKI=y -# CONFIG_ETHOC is not set -CONFIG_NET_VENDOR_PACKET_ENGINES=y -# CONFIG_HAMACHI is not set -# CONFIG_YELLOWFIN is not set -CONFIG_NET_VENDOR_PENSANDO=y -# CONFIG_IONIC is not set -CONFIG_NET_VENDOR_QLOGIC=y -# CONFIG_QLA3XXX is not set -# CONFIG_QLCNIC is not set -# CONFIG_NETXEN_NIC is not set -# CONFIG_QED is not set -CONFIG_NET_VENDOR_QUALCOMM=y -# CONFIG_QCOM_EMAC is not set -# CONFIG_RMNET is not set -CONFIG_NET_VENDOR_RDC=y -# CONFIG_R6040 is not set -CONFIG_NET_VENDOR_REALTEK=y -# CONFIG_ATP is not set CONFIG_8139CP=y CONFIG_8139TOO=y -CONFIG_8139TOO_PIO=y -# CONFIG_8139TOO_TUNE_TWISTER is not set -# CONFIG_8139TOO_8129 is not set -# CONFIG_8139_OLD_RX_RESET is not set CONFIG_R8169=y -CONFIG_NET_VENDOR_RENESAS=y -CONFIG_NET_VENDOR_ROCKER=y -CONFIG_NET_VENDOR_SAMSUNG=y -# CONFIG_SXGBE_ETH is not set -CONFIG_NET_VENDOR_SEEQ=y -CONFIG_NET_VENDOR_SOLARFLARE=y -# CONFIG_SFC is not set -# CONFIG_SFC_FALCON is not set -CONFIG_NET_VENDOR_SILAN=y -# CONFIG_SC92031 is not set -CONFIG_NET_VENDOR_SIS=y -# CONFIG_SIS900 is not set -# CONFIG_SIS190 is not set -CONFIG_NET_VENDOR_SMSC=y -# CONFIG_EPIC100 is not set -# CONFIG_SMSC911X is not set -# CONFIG_SMSC9420 is not set -CONFIG_NET_VENDOR_SOCIONEXT=y -CONFIG_NET_VENDOR_STMICRO=y -# CONFIG_STMMAC_ETH is not set -CONFIG_NET_VENDOR_SUN=y -# CONFIG_HAPPYMEAL is not set -# CONFIG_SUNGEM is not set -# CONFIG_CASSINI is not set -# CONFIG_NIU is not set -CONFIG_NET_VENDOR_SYNOPSYS=y -# CONFIG_DWC_XLGMAC is not set -CONFIG_NET_VENDOR_TEHUTI=y -# CONFIG_TEHUTI is not set -CONFIG_NET_VENDOR_TI=y -# CONFIG_TI_CPSW_PHY_SEL is not set -# CONFIG_TLAN is not set -CONFIG_NET_VENDOR_VIA=y -# CONFIG_VIA_RHINE is not set -# CONFIG_VIA_VELOCITY is not set -CONFIG_NET_VENDOR_WIZNET=y CONFIG_WIZNET_W5100=y CONFIG_WIZNET_W5300=y -# CONFIG_WIZNET_BUS_DIRECT is not set -# CONFIG_WIZNET_BUS_INDIRECT is not set -CONFIG_WIZNET_BUS_ANY=y -CONFIG_NET_VENDOR_XILINX=y -# CONFIG_XILINX_EMACLITE is not set -# CONFIG_XILINX_AXI_EMAC is not set -# CONFIG_XILINX_LL_TEMAC is not set CONFIG_FDDI=y -# CONFIG_DEFXX is not set -# CONFIG_SKFP is not set -# CONFIG_HIPPI is not set -# CONFIG_NET_SB1000 is not set -CONFIG_PHYLIB=y -# CONFIG_LED_TRIGGER_PHY is not set -# CONFIG_FIXED_PHY is not set - -# -# MII PHY device drivers -# CONFIG_AMD_PHY=y -# CONFIG_ADIN_PHY is not set -# CONFIG_AQUANTIA_PHY is not set -# CONFIG_AX88796B_PHY is not set -# CONFIG_BROADCOM_PHY is not set -# CONFIG_BCM54140_PHY is not set -# CONFIG_BCM7XXX_PHY is not set -# CONFIG_BCM84881_PHY is not set -# CONFIG_BCM87XX_PHY is not set -# CONFIG_CICADA_PHY is not set -# CONFIG_CORTINA_PHY is not set -# CONFIG_DAVICOM_PHY is not set -# CONFIG_ICPLUS_PHY is not set -# CONFIG_LXT_PHY is not set -# CONFIG_INTEL_XWAY_PHY is not set -# CONFIG_LSI_ET1011C_PHY is not set -# CONFIG_MARVELL_PHY is not set -# CONFIG_MARVELL_10G_PHY is not set -# CONFIG_MARVELL_88X2222_PHY is not set -# CONFIG_MICREL_PHY is not set -# CONFIG_MICROCHIP_PHY is not set -# CONFIG_MICROCHIP_T1_PHY is not set -# CONFIG_MICROSEMI_PHY is not set -# CONFIG_NATIONAL_PHY is not set -# CONFIG_NXP_C45_TJA11XX_PHY is not set -# CONFIG_NXP_TJA11XX_PHY is not set -# CONFIG_QSEMI_PHY is not set -CONFIG_REALTEK_PHY=y -# CONFIG_RENESAS_PHY is not set -# CONFIG_ROCKCHIP_PHY is not set -# CONFIG_SMSC_PHY is not set -# CONFIG_STE10XP is not set -# CONFIG_TERANETICS_PHY is not set -# CONFIG_DP83822_PHY is not set -# CONFIG_DP83TC811_PHY is not set -# CONFIG_DP83848_PHY is not set -# CONFIG_DP83867_PHY is not set -# CONFIG_DP83869_PHY is not set -# CONFIG_VITESSE_PHY is not set -# CONFIG_XILINX_GMII2RGMII is not set -CONFIG_MDIO_DEVICE=y -CONFIG_MDIO_BUS=y -CONFIG_MDIO_DEVRES=y -# CONFIG_MDIO_BITBANG is not set -# CONFIG_MDIO_BCM_UNIMAC is not set -# CONFIG_MDIO_MVUSB is not set -# CONFIG_MDIO_MSCC_MIIM is not set -# CONFIG_MDIO_THUNDER is not set - -# -# MDIO Multiplexers -# - -# -# PCS device drivers -# -# CONFIG_PCS_XPCS is not set -# end of PCS device drivers - -# CONFIG_PLIP is not set -# CONFIG_PPP is not set -# CONFIG_SLIP is not set CONFIG_USB_NET_DRIVERS=m -# CONFIG_USB_CATC is not set -# CONFIG_USB_KAWETH is not set -# CONFIG_USB_PEGASUS is not set -# CONFIG_USB_RTL8150 is not set CONFIG_USB_RTL8152=m -# CONFIG_USB_LAN78XX is not set CONFIG_USB_USBNET=m -CONFIG_USB_NET_AX8817X=m -CONFIG_USB_NET_AX88179_178A=m -CONFIG_USB_NET_CDCETHER=m -# CONFIG_USB_NET_CDC_EEM is not set -CONFIG_USB_NET_CDC_NCM=m -# CONFIG_USB_NET_HUAWEI_CDC_NCM is not set -# CONFIG_USB_NET_CDC_MBIM is not set -# CONFIG_USB_NET_DM9601 is not set -# CONFIG_USB_NET_SR9700 is not set -# CONFIG_USB_NET_SR9800 is not set -# CONFIG_USB_NET_SMSC75XX is not set -# CONFIG_USB_NET_SMSC95XX is not set -# CONFIG_USB_NET_GL620A is not set -CONFIG_USB_NET_NET1080=m -# CONFIG_USB_NET_PLUSB is not set -# CONFIG_USB_NET_MCS7830 is not set -# CONFIG_USB_NET_RNDIS_HOST is not set -CONFIG_USB_NET_CDC_SUBSET_ENABLE=m -CONFIG_USB_NET_CDC_SUBSET=m -# CONFIG_USB_ALI_M5632 is not set -# CONFIG_USB_AN2720 is not set -CONFIG_USB_BELKIN=y # CONFIG_USB_ARMLINUX is not set -# CONFIG_USB_EPSON2888 is not set -# CONFIG_USB_KC2190 is not set # CONFIG_USB_NET_ZAURUS is not set -# CONFIG_USB_NET_CX82310_ETH is not set -# CONFIG_USB_NET_KALMIA is not set -# CONFIG_USB_NET_QMI_WWAN is not set -# CONFIG_USB_HSO is not set -# CONFIG_USB_NET_INT51X1 is not set -# CONFIG_USB_IPHETH is not set -# CONFIG_USB_SIERRA_NET is not set -# CONFIG_USB_VL600 is not set -# CONFIG_USB_NET_CH9200 is not set -# CONFIG_USB_NET_AQC111 is not set -# CONFIG_USB_RTL8153_ECM is not set -CONFIG_WLAN=y -CONFIG_WLAN_VENDOR_ADMTEK=y -CONFIG_WLAN_VENDOR_ATH=y -# CONFIG_ATH_DEBUG is not set -# CONFIG_ATH5K_PCI is not set -CONFIG_WLAN_VENDOR_ATMEL=y -CONFIG_WLAN_VENDOR_BROADCOM=y -CONFIG_WLAN_VENDOR_CISCO=y -CONFIG_WLAN_VENDOR_INTEL=y -CONFIG_WLAN_VENDOR_INTERSIL=y -# CONFIG_HOSTAP is not set -# CONFIG_PRISM54 is not set -CONFIG_WLAN_VENDOR_MARVELL=y -CONFIG_WLAN_VENDOR_MEDIATEK=y -CONFIG_WLAN_VENDOR_MICROCHIP=y -CONFIG_WLAN_VENDOR_RALINK=y -CONFIG_WLAN_VENDOR_REALTEK=y -CONFIG_WLAN_VENDOR_RSI=y -CONFIG_WLAN_VENDOR_ST=y -CONFIG_WLAN_VENDOR_TI=y -CONFIG_WLAN_VENDOR_ZYDAS=y -CONFIG_WLAN_VENDOR_QUANTENNA=y -# CONFIG_WAN is not set -# CONFIG_WWAN is not set -# CONFIG_VMXNET3 is not set -# CONFIG_FUJITSU_ES is not set -# CONFIG_NETDEVSIM is not set -# CONFIG_NET_FAILOVER is not set -# CONFIG_ISDN is not set -# CONFIG_NVM is not set - -# -# Input device support -# -CONFIG_INPUT=y -CONFIG_INPUT_LEDS=y -CONFIG_INPUT_FF_MEMLESS=y CONFIG_INPUT_SPARSEKMAP=y -# CONFIG_INPUT_MATRIXKMAP is not set - -# -# Userland interfaces -# CONFIG_INPUT_MOUSEDEV=y -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 -# CONFIG_INPUT_JOYDEV is not set CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_EVBUG is not set - -# -# Input Device Drivers -# -CONFIG_INPUT_KEYBOARD=y -# CONFIG_KEYBOARD_ADP5588 is not set -# CONFIG_KEYBOARD_ADP5589 is not set -CONFIG_KEYBOARD_ATKBD=y -# CONFIG_KEYBOARD_QT1050 is not set -# CONFIG_KEYBOARD_QT1070 is not set -# CONFIG_KEYBOARD_QT2160 is not set -# CONFIG_KEYBOARD_DLINK_DIR685 is not set -# CONFIG_KEYBOARD_LKKBD is not set -# CONFIG_KEYBOARD_TCA6416 is not set -# CONFIG_KEYBOARD_TCA8418 is not set -# CONFIG_KEYBOARD_LM8323 is not set -# CONFIG_KEYBOARD_LM8333 is not set -# CONFIG_KEYBOARD_MAX7359 is not set -# CONFIG_KEYBOARD_MCS is not set -# CONFIG_KEYBOARD_MPR121 is not set -# CONFIG_KEYBOARD_NEWTON is not set -# CONFIG_KEYBOARD_OPENCORES is not set -# CONFIG_KEYBOARD_SAMSUNG is not set -# CONFIG_KEYBOARD_STOWAWAY is not set -# CONFIG_KEYBOARD_SUNKBD is not set -# CONFIG_KEYBOARD_TM2_TOUCHKEY is not set -# CONFIG_KEYBOARD_XTKBD is not set -CONFIG_INPUT_MOUSE=y -CONFIG_MOUSE_PS2=y -CONFIG_MOUSE_PS2_ALPS=y -CONFIG_MOUSE_PS2_BYD=y -CONFIG_MOUSE_PS2_LOGIPS2PP=y -CONFIG_MOUSE_PS2_SYNAPTICS=y -CONFIG_MOUSE_PS2_SYNAPTICS_SMBUS=y -CONFIG_MOUSE_PS2_CYPRESS=y -CONFIG_MOUSE_PS2_LIFEBOOK=y -CONFIG_MOUSE_PS2_TRACKPOINT=y -# CONFIG_MOUSE_PS2_ELANTECH is not set -# CONFIG_MOUSE_PS2_SENTELIC is not set -# CONFIG_MOUSE_PS2_TOUCHKIT is not set -CONFIG_MOUSE_PS2_FOCALTECH=y -# CONFIG_MOUSE_PS2_VMMOUSE is not set -CONFIG_MOUSE_PS2_SMBUS=y -# CONFIG_MOUSE_SERIAL is not set -# CONFIG_MOUSE_APPLETOUCH is not set -# CONFIG_MOUSE_BCM5974 is not set -# CONFIG_MOUSE_CYAPA is not set -# CONFIG_MOUSE_ELAN_I2C is not set -# CONFIG_MOUSE_VSXXXAA is not set -# CONFIG_MOUSE_SYNAPTICS_I2C is not set -# CONFIG_MOUSE_SYNAPTICS_USB is not set -# CONFIG_INPUT_JOYSTICK is not set -# CONFIG_INPUT_TABLET is not set -# CONFIG_INPUT_TOUCHSCREEN is not set -# CONFIG_INPUT_MISC is not set -# CONFIG_RMI4_CORE is not set - -# -# Hardware I/O ports -# -CONFIG_SERIO=y -CONFIG_ARCH_MIGHT_HAVE_PC_SERIO=y -CONFIG_SERIO_I8042=y -CONFIG_SERIO_SERPORT=y -# CONFIG_SERIO_CT82C710 is not set -# CONFIG_SERIO_PARKBD is not set -# CONFIG_SERIO_PCIPS2 is not set -CONFIG_SERIO_LIBPS2=y -# CONFIG_SERIO_RAW is not set -# CONFIG_SERIO_ALTERA_PS2 is not set -# CONFIG_SERIO_PS2MULT is not set -# CONFIG_SERIO_ARC_PS2 is not set -# CONFIG_USERIO is not set -# CONFIG_GAMEPORT is not set -# end of Hardware I/O ports -# end of Input device support - -# -# Character devices -# -CONFIG_TTY=y -CONFIG_VT=y -CONFIG_CONSOLE_TRANSLATIONS=y -CONFIG_VT_CONSOLE=y -CONFIG_VT_CONSOLE_SLEEP=y -CONFIG_HW_CONSOLE=y -CONFIG_VT_HW_CONSOLE_BINDING=y -CONFIG_UNIX98_PTYS=y # CONFIG_LEGACY_PTYS is not set -CONFIG_LDISC_AUTOLOAD=y - -# -# Serial drivers -# -CONFIG_SERIAL_EARLYCON=y CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_DEPRECATED_OPTIONS=y -CONFIG_SERIAL_8250_PNP=y -# CONFIG_SERIAL_8250_16550A_VARIANTS is not set -# CONFIG_SERIAL_8250_FINTEK is not set CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_DMA=y -CONFIG_SERIAL_8250_PCI=y -CONFIG_SERIAL_8250_EXAR=y CONFIG_SERIAL_8250_NR_UARTS=32 -CONFIG_SERIAL_8250_RUNTIME_UARTS=4 CONFIG_SERIAL_8250_EXTENDED=y CONFIG_SERIAL_8250_MANY_PORTS=y CONFIG_SERIAL_8250_SHARE_IRQ=y CONFIG_SERIAL_8250_DETECT_IRQ=y CONFIG_SERIAL_8250_RSA=y -CONFIG_SERIAL_8250_DWLIB=y -# CONFIG_SERIAL_8250_DW is not set -# CONFIG_SERIAL_8250_RT288X is not set -CONFIG_SERIAL_8250_LPSS=y # CONFIG_SERIAL_8250_MID is not set - -# -# Non-8250 serial port support -# -# CONFIG_SERIAL_KGDB_NMI is not set -# CONFIG_SERIAL_UARTLITE is not set -CONFIG_SERIAL_CORE=y -CONFIG_SERIAL_CORE_CONSOLE=y -CONFIG_CONSOLE_POLL=y -# CONFIG_SERIAL_JSM is not set -# CONFIG_SERIAL_LANTIQ is not set -# CONFIG_SERIAL_SCCNXP is not set -# CONFIG_SERIAL_SC16IS7XX is not set -# CONFIG_SERIAL_BCM63XX is not set -# CONFIG_SERIAL_ALTERA_JTAGUART is not set -# CONFIG_SERIAL_ALTERA_UART is not set -# CONFIG_SERIAL_ARC is not set -# CONFIG_SERIAL_RP2 is not set -# CONFIG_SERIAL_FSL_LPUART is not set -# CONFIG_SERIAL_FSL_LINFLEXUART is not set -# CONFIG_SERIAL_SPRD is not set -# end of Serial drivers - CONFIG_SERIAL_NONSTANDARD=y -# CONFIG_MOXA_INTELLIO is not set -# CONFIG_MOXA_SMARTIO is not set -# CONFIG_SYNCLINK_GT is not set -# CONFIG_N_HDLC is not set -# CONFIG_N_GSM is not set -# CONFIG_NOZOMI is not set -# CONFIG_NULL_TTY is not set -# CONFIG_SERIAL_DEV_BUS is not set -# CONFIG_TTY_PRINTK is not set -# CONFIG_PRINTER is not set -# CONFIG_PPDEV is not set -# CONFIG_VIRTIO_CONSOLE is not set -# CONFIG_IPMI_HANDLER is not set # CONFIG_HW_RANDOM is not set -# CONFIG_APPLICOM is not set -# CONFIG_MWAVE is not set -CONFIG_DEVMEM=y -# CONFIG_NVRAM is not set -# CONFIG_RAW_DRIVER is not set -CONFIG_DEVPORT=y -# CONFIG_HPET is not set -# CONFIG_HANGCHECK_TIMER is not set -# CONFIG_TCG_TPM is not set -# CONFIG_TELCLOCK is not set -# CONFIG_XILLYBUS is not set -# end of Character devices - -# CONFIG_RANDOM_TRUST_CPU is not set -# CONFIG_RANDOM_TRUST_BOOTLOADER is not set - -# -# I2C support -# -CONFIG_I2C=y -CONFIG_ACPI_I2C_OPREGION=y -CONFIG_I2C_BOARDINFO=y -CONFIG_I2C_COMPAT=y -# CONFIG_I2C_CHARDEV is not set -# CONFIG_I2C_MUX is not set -CONFIG_I2C_HELPER_AUTO=y -CONFIG_I2C_SMBUS=y -CONFIG_I2C_ALGOBIT=y - -# -# I2C Hardware Bus support -# - -# -# PC SMBus host controller drivers -# -# CONFIG_I2C_ALI1535 is not set -# CONFIG_I2C_ALI1563 is not set -# CONFIG_I2C_ALI15X3 is not set -# CONFIG_I2C_AMD756 is not set -# CONFIG_I2C_AMD8111 is not set -# CONFIG_I2C_AMD_MP2 is not set CONFIG_I2C_I801=y -# CONFIG_I2C_ISCH is not set -# CONFIG_I2C_ISMT is not set CONFIG_I2C_PIIX4=m -# CONFIG_I2C_NFORCE2 is not set -# CONFIG_I2C_NVIDIA_GPU is not set -# CONFIG_I2C_SIS5595 is not set -# CONFIG_I2C_SIS630 is not set -# CONFIG_I2C_SIS96X is not set -# CONFIG_I2C_VIA is not set -# CONFIG_I2C_VIAPRO is not set - -# -# ACPI drivers -# -# CONFIG_I2C_SCMI is not set - -# -# I2C system bus drivers (mostly embedded / system-on-chip) -# -# CONFIG_I2C_DESIGNWARE_PLATFORM is not set -# CONFIG_I2C_DESIGNWARE_PCI is not set -# CONFIG_I2C_EMEV2 is not set -# CONFIG_I2C_OCORES is not set -# CONFIG_I2C_PCA_PLATFORM is not set -# CONFIG_I2C_SIMTEC is not set -# CONFIG_I2C_XILINX is not set - -# -# External I2C/SMBus adapter drivers -# -# CONFIG_I2C_DIOLAN_U2C is not set -# CONFIG_I2C_CP2615 is not set -# CONFIG_I2C_PARPORT is not set -# CONFIG_I2C_ROBOTFUZZ_OSIF is not set -# CONFIG_I2C_TAOS_EVM is not set -# CONFIG_I2C_TINY_USB is not set - -# -# Other I2C/SMBus bus drivers -# -# CONFIG_I2C_MLXCPLD is not set -# end of I2C Hardware Bus support - -# CONFIG_I2C_STUB is not set -# CONFIG_I2C_SLAVE is not set -# CONFIG_I2C_DEBUG_CORE is not set -# CONFIG_I2C_DEBUG_ALGO is not set -# CONFIG_I2C_DEBUG_BUS is not set -# end of I2C support - -# CONFIG_I3C is not set -# CONFIG_SPI is not set -# CONFIG_SPMI is not set -# CONFIG_HSI is not set -CONFIG_PPS=y -# CONFIG_PPS_DEBUG is not set - -# -# PPS clients support -# -# CONFIG_PPS_CLIENT_KTIMER is not set -# CONFIG_PPS_CLIENT_LDISC is not set -# CONFIG_PPS_CLIENT_PARPORT is not set -# CONFIG_PPS_CLIENT_GPIO is not set - -# -# PPS generators support -# - -# -# PTP clock support -# -CONFIG_PTP_1588_CLOCK=y - -# -# Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks. -# -CONFIG_PTP_1588_CLOCK_KVM=y -# CONFIG_PTP_1588_CLOCK_IDT82P33 is not set -# CONFIG_PTP_1588_CLOCK_IDTCM is not set -# CONFIG_PTP_1588_CLOCK_VMW is not set -# CONFIG_PTP_1588_CLOCK_OCP is not set -# end of PTP clock support - -CONFIG_PINCTRL=y -# CONFIG_DEBUG_PINCTRL is not set -# CONFIG_PINCTRL_AMD is not set -# CONFIG_PINCTRL_MCP23S08 is not set -# CONFIG_PINCTRL_SX150X is not set -# CONFIG_PINCTRL_BAYTRAIL is not set -# CONFIG_PINCTRL_CHERRYVIEW is not set -# CONFIG_PINCTRL_LYNXPOINT is not set -# CONFIG_PINCTRL_ALDERLAKE is not set -# CONFIG_PINCTRL_BROXTON is not set -# CONFIG_PINCTRL_CANNONLAKE is not set -# CONFIG_PINCTRL_CEDARFORK is not set -# CONFIG_PINCTRL_DENVERTON is not set -# CONFIG_PINCTRL_ELKHARTLAKE is not set -# CONFIG_PINCTRL_EMMITSBURG is not set -# CONFIG_PINCTRL_GEMINILAKE is not set -# CONFIG_PINCTRL_ICELAKE is not set -# CONFIG_PINCTRL_JASPERLAKE is not set -# CONFIG_PINCTRL_LAKEFIELD is not set -# CONFIG_PINCTRL_LEWISBURG is not set -# CONFIG_PINCTRL_SUNRISEPOINT is not set -# CONFIG_PINCTRL_TIGERLAKE is not set - -# -# Renesas pinctrl drivers -# -# end of Renesas pinctrl drivers - -# CONFIG_GPIOLIB is not set -# CONFIG_W1 is not set -# CONFIG_POWER_RESET is not set -CONFIG_POWER_SUPPLY=y -# CONFIG_POWER_SUPPLY_DEBUG is not set -CONFIG_POWER_SUPPLY_HWMON=y -# CONFIG_PDA_POWER is not set -# CONFIG_TEST_POWER is not set -# CONFIG_CHARGER_ADP5061 is not set -# CONFIG_BATTERY_CW2015 is not set -# CONFIG_BATTERY_DS2780 is not set -# CONFIG_BATTERY_DS2781 is not set -# CONFIG_BATTERY_DS2782 is not set -# CONFIG_BATTERY_SBS is not set -# CONFIG_CHARGER_SBS is not set -# CONFIG_BATTERY_BQ27XXX is not set -# CONFIG_BATTERY_MAX17040 is not set -# CONFIG_BATTERY_MAX17042 is not set -# CONFIG_CHARGER_MAX8903 is not set -# CONFIG_CHARGER_LP8727 is not set -# CONFIG_CHARGER_LTC4162L is not set -# CONFIG_CHARGER_BQ2415X is not set -# CONFIG_CHARGER_SMB347 is not set -# CONFIG_BATTERY_GAUGE_LTC2941 is not set -# CONFIG_BATTERY_GOLDFISH is not set -# CONFIG_CHARGER_BD99954 is not set -CONFIG_HWMON=y -# CONFIG_HWMON_DEBUG_CHIP is not set - -# -# Native drivers -# -# CONFIG_SENSORS_ABITUGURU is not set -# CONFIG_SENSORS_ABITUGURU3 is not set -# CONFIG_SENSORS_AD7414 is not set -# CONFIG_SENSORS_AD7418 is not set -# CONFIG_SENSORS_ADM1021 is not set -# CONFIG_SENSORS_ADM1025 is not set -# CONFIG_SENSORS_ADM1026 is not set -# CONFIG_SENSORS_ADM1029 is not set -# CONFIG_SENSORS_ADM1031 is not set -# CONFIG_SENSORS_ADM1177 is not set -# CONFIG_SENSORS_ADM9240 is not set -# CONFIG_SENSORS_ADT7410 is not set -# CONFIG_SENSORS_ADT7411 is not set -# CONFIG_SENSORS_ADT7462 is not set -# CONFIG_SENSORS_ADT7470 is not set -# CONFIG_SENSORS_ADT7475 is not set -# CONFIG_SENSORS_AHT10 is not set -# CONFIG_SENSORS_AS370 is not set -# CONFIG_SENSORS_ASC7621 is not set -# CONFIG_SENSORS_AXI_FAN_CONTROL is not set -# CONFIG_SENSORS_K8TEMP is not set CONFIG_SENSORS_K10TEMP=m -# CONFIG_SENSORS_FAM15H_POWER is not set -# CONFIG_SENSORS_APPLESMC is not set -# CONFIG_SENSORS_ASB100 is not set -# CONFIG_SENSORS_ASPEED is not set -# CONFIG_SENSORS_ATXP1 is not set -# CONFIG_SENSORS_CORSAIR_CPRO is not set -# CONFIG_SENSORS_CORSAIR_PSU is not set -# CONFIG_SENSORS_DRIVETEMP is not set -# CONFIG_SENSORS_DS620 is not set -# CONFIG_SENSORS_DS1621 is not set -CONFIG_SENSORS_DELL_SMM=m -# CONFIG_SENSORS_I5K_AMB is not set -# CONFIG_SENSORS_F71805F is not set -# CONFIG_SENSORS_F71882FG is not set -# CONFIG_SENSORS_F75375S is not set -# CONFIG_SENSORS_FSCHMD is not set -# CONFIG_SENSORS_FTSTEUTATES is not set -# CONFIG_SENSORS_GL518SM is not set -# CONFIG_SENSORS_GL520SM is not set -# CONFIG_SENSORS_G760A is not set -# CONFIG_SENSORS_G762 is not set -# CONFIG_SENSORS_HIH6130 is not set -# CONFIG_SENSORS_I5500 is not set -# CONFIG_SENSORS_CORETEMP is not set -# CONFIG_SENSORS_IT87 is not set -# CONFIG_SENSORS_JC42 is not set -# CONFIG_SENSORS_POWR1220 is not set -# CONFIG_SENSORS_LINEAGE is not set -# CONFIG_SENSORS_LTC2945 is not set -# CONFIG_SENSORS_LTC2947_I2C is not set -# CONFIG_SENSORS_LTC2990 is not set -# CONFIG_SENSORS_LTC4151 is not set -# CONFIG_SENSORS_LTC4215 is not set -# CONFIG_SENSORS_LTC4222 is not set -# CONFIG_SENSORS_LTC4245 is not set -# CONFIG_SENSORS_LTC4260 is not set -# CONFIG_SENSORS_LTC4261 is not set -# CONFIG_SENSORS_MAX127 is not set -# CONFIG_SENSORS_MAX16065 is not set -# CONFIG_SENSORS_MAX1619 is not set -# CONFIG_SENSORS_MAX1668 is not set -# CONFIG_SENSORS_MAX197 is not set -# CONFIG_SENSORS_MAX31730 is not set -# CONFIG_SENSORS_MAX6621 is not set -# CONFIG_SENSORS_MAX6639 is not set -# CONFIG_SENSORS_MAX6642 is not set -# CONFIG_SENSORS_MAX6650 is not set -# CONFIG_SENSORS_MAX6697 is not set -# CONFIG_SENSORS_MAX31790 is not set -# CONFIG_SENSORS_MCP3021 is not set -# CONFIG_SENSORS_TC654 is not set -# CONFIG_SENSORS_TPS23861 is not set -# CONFIG_SENSORS_MR75203 is not set -# CONFIG_SENSORS_LM63 is not set -# CONFIG_SENSORS_LM73 is not set -# CONFIG_SENSORS_LM75 is not set -# CONFIG_SENSORS_LM77 is not set -# CONFIG_SENSORS_LM78 is not set -# CONFIG_SENSORS_LM80 is not set -# CONFIG_SENSORS_LM83 is not set -# CONFIG_SENSORS_LM85 is not set -# CONFIG_SENSORS_LM87 is not set -# CONFIG_SENSORS_LM90 is not set -# CONFIG_SENSORS_LM92 is not set -# CONFIG_SENSORS_LM93 is not set -# CONFIG_SENSORS_LM95234 is not set -# CONFIG_SENSORS_LM95241 is not set -# CONFIG_SENSORS_LM95245 is not set -# CONFIG_SENSORS_PC87360 is not set -# CONFIG_SENSORS_PC87427 is not set -# CONFIG_SENSORS_NTC_THERMISTOR is not set -# CONFIG_SENSORS_NCT6683 is not set -# CONFIG_SENSORS_NCT6775 is not set -# CONFIG_SENSORS_NCT7802 is not set -# CONFIG_SENSORS_NCT7904 is not set -# CONFIG_SENSORS_NPCM7XX is not set -# CONFIG_SENSORS_NZXT_KRAKEN2 is not set -# CONFIG_SENSORS_PCF8591 is not set -# CONFIG_PMBUS is not set -# CONFIG_SENSORS_SBTSI is not set -# CONFIG_SENSORS_SHT21 is not set -# CONFIG_SENSORS_SHT3x is not set -# CONFIG_SENSORS_SHTC1 is not set -# CONFIG_SENSORS_SIS5595 is not set -# CONFIG_SENSORS_DME1737 is not set -# CONFIG_SENSORS_EMC1403 is not set -# CONFIG_SENSORS_EMC2103 is not set -# CONFIG_SENSORS_EMC6W201 is not set -# CONFIG_SENSORS_SMSC47M1 is not set -# CONFIG_SENSORS_SMSC47M192 is not set -# CONFIG_SENSORS_SMSC47B397 is not set -# CONFIG_SENSORS_SCH5627 is not set -# CONFIG_SENSORS_SCH5636 is not set -# CONFIG_SENSORS_STTS751 is not set -# CONFIG_SENSORS_SMM665 is not set -# CONFIG_SENSORS_ADC128D818 is not set -# CONFIG_SENSORS_ADS7828 is not set -# CONFIG_SENSORS_AMC6821 is not set -# CONFIG_SENSORS_INA209 is not set -# CONFIG_SENSORS_INA2XX is not set -# CONFIG_SENSORS_INA3221 is not set -# CONFIG_SENSORS_TC74 is not set -# CONFIG_SENSORS_THMC50 is not set -# CONFIG_SENSORS_TMP102 is not set -# CONFIG_SENSORS_TMP103 is not set -# CONFIG_SENSORS_TMP108 is not set -# CONFIG_SENSORS_TMP401 is not set -# CONFIG_SENSORS_TMP421 is not set -# CONFIG_SENSORS_TMP513 is not set -# CONFIG_SENSORS_VIA_CPUTEMP is not set -# CONFIG_SENSORS_VIA686A is not set -# CONFIG_SENSORS_VT1211 is not set -# CONFIG_SENSORS_VT8231 is not set -# CONFIG_SENSORS_W83773G is not set -# CONFIG_SENSORS_W83781D is not set -# CONFIG_SENSORS_W83791D is not set -# CONFIG_SENSORS_W83792D is not set -# CONFIG_SENSORS_W83793 is not set -# CONFIG_SENSORS_W83795 is not set -# CONFIG_SENSORS_W83L785TS is not set -# CONFIG_SENSORS_W83L786NG is not set -# CONFIG_SENSORS_W83627HF is not set -# CONFIG_SENSORS_W83627EHF is not set -# CONFIG_SENSORS_XGENE is not set - -# -# ACPI drivers -# -# CONFIG_SENSORS_ACPI_POWER is not set -# CONFIG_SENSORS_ATK0110 is not set -CONFIG_THERMAL=y -# CONFIG_THERMAL_NETLINK is not set -# CONFIG_THERMAL_STATISTICS is not set -CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=0 -CONFIG_THERMAL_HWMON=y -CONFIG_THERMAL_WRITABLE_TRIPS=y -CONFIG_THERMAL_DEFAULT_GOV_STEP_WISE=y -# CONFIG_THERMAL_DEFAULT_GOV_FAIR_SHARE is not set -# CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE is not set -# CONFIG_THERMAL_GOV_FAIR_SHARE is not set -CONFIG_THERMAL_GOV_STEP_WISE=y -# CONFIG_THERMAL_GOV_BANG_BANG is not set -CONFIG_THERMAL_GOV_USER_SPACE=y -# CONFIG_THERMAL_EMULATION is not set - -# -# Intel thermal drivers -# -# CONFIG_INTEL_POWERCLAMP is not set -CONFIG_X86_THERMAL_VECTOR=y -CONFIG_X86_PKG_TEMP_THERMAL=m -# CONFIG_INTEL_SOC_DTS_THERMAL is not set - -# -# ACPI INT340X thermal drivers -# -# CONFIG_INT340X_THERMAL is not set -# end of ACPI INT340X thermal drivers - -# CONFIG_INTEL_PCH_THERMAL is not set -# CONFIG_INTEL_TCC_COOLING is not set -# end of Intel thermal drivers - CONFIG_WATCHDOG=y -# CONFIG_WATCHDOG_CORE is not set -# CONFIG_WATCHDOG_NOWAYOUT is not set -CONFIG_WATCHDOG_HANDLE_BOOT_ENABLED=y -CONFIG_WATCHDOG_OPEN_TIMEOUT=0 -# CONFIG_WATCHDOG_SYSFS is not set - -# -# Watchdog Pretimeout Governors -# - -# -# Watchdog Device Drivers -# -# CONFIG_SOFT_WATCHDOG is not set -# CONFIG_WDAT_WDT is not set -# CONFIG_XILINX_WATCHDOG is not set -# CONFIG_ZIIRAVE_WATCHDOG is not set -# CONFIG_CADENCE_WATCHDOG is not set -# CONFIG_DW_WATCHDOG is not set -# CONFIG_MAX63XX_WATCHDOG is not set -# CONFIG_ACQUIRE_WDT is not set -# CONFIG_ADVANTECH_WDT is not set -# CONFIG_ALIM1535_WDT is not set -# CONFIG_ALIM7101_WDT is not set -# CONFIG_EBC_C384_WDT is not set -# CONFIG_F71808E_WDT is not set -# CONFIG_SP5100_TCO is not set -# CONFIG_SBC_FITPC2_WATCHDOG is not set -# CONFIG_EUROTECH_WDT is not set -# CONFIG_IB700_WDT is not set -# CONFIG_IBMASR is not set -# CONFIG_WAFER_WDT is not set -# CONFIG_I6300ESB_WDT is not set -# CONFIG_IE6XX_WDT is not set -# CONFIG_ITCO_WDT is not set -# CONFIG_IT8712F_WDT is not set -# CONFIG_IT87_WDT is not set -# CONFIG_HP_WATCHDOG is not set -# CONFIG_SC1200_WDT is not set -# CONFIG_PC87413_WDT is not set -# CONFIG_NV_TCO is not set -# CONFIG_60XX_WDT is not set -# CONFIG_CPU5_WDT is not set -# CONFIG_SMSC_SCH311X_WDT is not set -# CONFIG_SMSC37B787_WDT is not set -# CONFIG_TQMX86_WDT is not set -# CONFIG_VIA_WDT is not set -# CONFIG_W83627HF_WDT is not set -# CONFIG_W83877F_WDT is not set -# CONFIG_W83977F_WDT is not set -# CONFIG_MACHZ_WDT is not set -# CONFIG_SBC_EPX_C3_WATCHDOG is not set -# CONFIG_NI903X_WDT is not set -# CONFIG_NIC7018_WDT is not set - -# -# PCI-based Watchdog Cards -# -# CONFIG_PCIPCWATCHDOG is not set -# CONFIG_WDTPCI is not set - -# -# USB-based Watchdog Cards -# -# CONFIG_USBPCWATCHDOG is not set -CONFIG_SSB_POSSIBLE=y -# CONFIG_SSB is not set -CONFIG_BCMA_POSSIBLE=y -# CONFIG_BCMA is not set - -# -# Multifunction device drivers -# -# CONFIG_MFD_AS3711 is not set -# CONFIG_PMIC_ADP5520 is not set -# CONFIG_MFD_BCM590XX is not set -# CONFIG_MFD_BD9571MWV is not set -# CONFIG_MFD_AXP20X_I2C is not set -# CONFIG_MFD_MADERA is not set -# CONFIG_PMIC_DA903X is not set -# CONFIG_MFD_DA9052_I2C is not set -# CONFIG_MFD_DA9055 is not set -# CONFIG_MFD_DA9062 is not set -# CONFIG_MFD_DA9063 is not set -# CONFIG_MFD_DA9150 is not set -# CONFIG_MFD_DLN2 is not set -# CONFIG_MFD_MC13XXX_I2C is not set -# CONFIG_MFD_MP2629 is not set -# CONFIG_HTC_PASIC3 is not set -# CONFIG_MFD_INTEL_QUARK_I2C_GPIO is not set -# CONFIG_LPC_ICH is not set -# CONFIG_LPC_SCH is not set -# CONFIG_MFD_INTEL_LPSS_ACPI is not set -# CONFIG_MFD_INTEL_LPSS_PCI is not set -# CONFIG_MFD_INTEL_PMT is not set -# CONFIG_MFD_IQS62X is not set -# CONFIG_MFD_JANZ_CMODIO is not set -# CONFIG_MFD_KEMPLD is not set -# CONFIG_MFD_88PM800 is not set -# CONFIG_MFD_88PM805 is not set -# CONFIG_MFD_88PM860X is not set -# CONFIG_MFD_MAX14577 is not set -# CONFIG_MFD_MAX77693 is not set -# CONFIG_MFD_MAX77843 is not set -# CONFIG_MFD_MAX8907 is not set -# CONFIG_MFD_MAX8925 is not set -# CONFIG_MFD_MAX8997 is not set -# CONFIG_MFD_MAX8998 is not set -# CONFIG_MFD_MT6360 is not set -# CONFIG_MFD_MT6397 is not set -# CONFIG_MFD_MENF21BMC is not set -# CONFIG_MFD_VIPERBOARD is not set -# CONFIG_MFD_RETU is not set -# CONFIG_MFD_PCF50633 is not set -# CONFIG_MFD_RDC321X is not set -# CONFIG_MFD_RT5033 is not set -# CONFIG_MFD_RC5T583 is not set -# CONFIG_MFD_SEC_CORE is not set -# CONFIG_MFD_SI476X_CORE is not set -# CONFIG_MFD_SM501 is not set -# CONFIG_MFD_SKY81452 is not set -# CONFIG_MFD_SYSCON is not set -# CONFIG_MFD_TI_AM335X_TSCADC is not set -# CONFIG_MFD_LP3943 is not set -# CONFIG_MFD_LP8788 is not set -# CONFIG_MFD_TI_LMU is not set -# CONFIG_MFD_PALMAS is not set -# CONFIG_TPS6105X is not set -# CONFIG_TPS6507X is not set -# CONFIG_MFD_TPS65086 is not set -# CONFIG_MFD_TPS65090 is not set -# CONFIG_MFD_TI_LP873X is not set -# CONFIG_MFD_TPS6586X is not set -# CONFIG_MFD_TPS65912_I2C is not set -# CONFIG_MFD_TPS80031 is not set -# CONFIG_TWL4030_CORE is not set -# CONFIG_TWL6040_CORE is not set -# CONFIG_MFD_WL1273_CORE is not set -# CONFIG_MFD_LM3533 is not set -# CONFIG_MFD_TQMX86 is not set -# CONFIG_MFD_VX855 is not set -# CONFIG_MFD_ARIZONA_I2C is not set -# CONFIG_MFD_WM8400 is not set -# CONFIG_MFD_WM831X_I2C is not set -# CONFIG_MFD_WM8350_I2C is not set -# CONFIG_MFD_WM8994 is not set -# CONFIG_MFD_ATC260X_I2C is not set -# end of Multifunction device drivers - -# CONFIG_REGULATOR is not set CONFIG_RC_CORE=y -CONFIG_RC_MAP=y -# CONFIG_LIRC is not set CONFIG_RC_DECODERS=y CONFIG_IR_NEC_DECODER=y CONFIG_IR_RC5_DECODER=y @@ -3075,1852 +409,140 @@ CONFIG_IR_SANYO_DECODER=y CONFIG_IR_SHARP_DECODER=y CONFIG_IR_MCE_KBD_DECODER=y CONFIG_IR_XMP_DECODER=y -# CONFIG_IR_IMON_DECODER is not set -# CONFIG_IR_RCMM_DECODER is not set -# CONFIG_RC_DEVICES is not set -# CONFIG_MEDIA_CEC_SUPPORT is not set -# CONFIG_MEDIA_SUPPORT is not set - -# -# Graphics support -# CONFIG_AGP=y CONFIG_AGP_AMD64=y CONFIG_AGP_INTEL=y -# CONFIG_AGP_SIS is not set -# CONFIG_AGP_VIA is not set -CONFIG_INTEL_GTT=y -CONFIG_VGA_ARB=y -CONFIG_VGA_ARB_MAX_GPUS=16 -# CONFIG_VGA_SWITCHEROO is not set CONFIG_DRM=m -# CONFIG_DRM_DP_AUX_CHARDEV is not set -# CONFIG_DRM_DEBUG_SELFTEST is not set -CONFIG_DRM_KMS_HELPER=m -# CONFIG_DRM_DEBUG_DP_MST_TOPOLOGY_REFS is not set -CONFIG_DRM_FBDEV_EMULATION=y -CONFIG_DRM_FBDEV_OVERALLOC=100 -# CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM is not set -# CONFIG_DRM_LOAD_EDID_FIRMWARE is not set -# CONFIG_DRM_DP_CEC is not set -CONFIG_DRM_TTM=m -CONFIG_DRM_VRAM_HELPER=m -CONFIG_DRM_TTM_HELPER=m -CONFIG_DRM_SCHED=m - -# -# I2C encoder or helper chips -# -# CONFIG_DRM_I2C_CH7006 is not set -# CONFIG_DRM_I2C_SIL164 is not set -# CONFIG_DRM_I2C_NXP_TDA998X is not set -# CONFIG_DRM_I2C_NXP_TDA9950 is not set -# end of I2C encoder or helper chips - -# -# ARM devices -# -# end of ARM devices - -# CONFIG_DRM_RADEON is not set CONFIG_DRM_AMDGPU=m CONFIG_DRM_AMDGPU_SI=y CONFIG_DRM_AMDGPU_CIK=y -CONFIG_DRM_AMDGPU_USERPTR=y - -# -# ACP (Audio CoProcessor) Configuration -# -# CONFIG_DRM_AMD_ACP is not set -# end of ACP (Audio CoProcessor) Configuration - -# -# Display Engine Configuration -# -CONFIG_DRM_AMD_DC=y -CONFIG_DRM_AMD_DC_DCN=y -# CONFIG_DRM_AMD_DC_HDCP is not set -# CONFIG_DRM_AMD_DC_SI is not set -# CONFIG_DEBUG_KERNEL_DC is not set -# CONFIG_DRM_AMD_SECURE_DISPLAY is not set -# end of Display Engine Configuration - CONFIG_HSA_AMD=y -CONFIG_HSA_AMD_SVM=y -# CONFIG_DRM_NOUVEAU is not set -# CONFIG_DRM_I915 is not set -# CONFIG_DRM_VGEM is not set -# CONFIG_DRM_VKMS is not set -# CONFIG_DRM_VMWGFX is not set -# CONFIG_DRM_GMA500 is not set -# CONFIG_DRM_UDL is not set CONFIG_DRM_AST=m -# CONFIG_DRM_MGAG200 is not set -# CONFIG_DRM_QXL is not set -# CONFIG_DRM_BOCHS is not set -# CONFIG_DRM_VIRTIO_GPU is not set -CONFIG_DRM_PANEL=y - -# -# Display Panels -# -# end of Display Panels - -CONFIG_DRM_BRIDGE=y -CONFIG_DRM_PANEL_BRIDGE=y - -# -# Display Interface Bridges -# -# CONFIG_DRM_ANALOGIX_ANX78XX is not set -# end of Display Interface Bridges - -# CONFIG_DRM_ETNAVIV is not set -# CONFIG_DRM_CIRRUS_QEMU is not set -# CONFIG_DRM_GM12U320 is not set -# CONFIG_DRM_SIMPLEDRM is not set -# CONFIG_DRM_VBOXVIDEO is not set -# CONFIG_DRM_GUD is not set -# CONFIG_DRM_LEGACY is not set -CONFIG_DRM_PANEL_ORIENTATION_QUIRKS=m - -# -# Frame buffer Devices -# -CONFIG_FB_CMDLINE=y -CONFIG_FB_NOTIFY=y CONFIG_FB=y -# CONFIG_FIRMWARE_EDID is not set -CONFIG_FB_CFB_FILLRECT=m -CONFIG_FB_CFB_COPYAREA=m -CONFIG_FB_CFB_IMAGEBLIT=m -CONFIG_FB_SYS_FILLRECT=m -CONFIG_FB_SYS_COPYAREA=m -CONFIG_FB_SYS_IMAGEBLIT=m -# CONFIG_FB_FOREIGN_ENDIAN is not set -CONFIG_FB_SYS_FOPS=m -CONFIG_FB_DEFERRED_IO=y -# CONFIG_FB_MODE_HELPERS is not set -# CONFIG_FB_TILEBLITTING is not set - -# -# Frame buffer hardware drivers -# -# CONFIG_FB_CIRRUS is not set -# CONFIG_FB_PM2 is not set -# CONFIG_FB_CYBER2000 is not set -# CONFIG_FB_ARC is not set -# CONFIG_FB_ASILIANT is not set -# CONFIG_FB_IMSTT is not set -# CONFIG_FB_VGA16 is not set -# CONFIG_FB_VESA is not set -# CONFIG_FB_EFI is not set -# CONFIG_FB_N411 is not set -# CONFIG_FB_HGA is not set -# CONFIG_FB_OPENCORES is not set -# CONFIG_FB_S1D13XXX is not set -# CONFIG_FB_NVIDIA is not set -# CONFIG_FB_RIVA is not set -# CONFIG_FB_I740 is not set -# CONFIG_FB_LE80578 is not set -# CONFIG_FB_INTEL is not set -# CONFIG_FB_MATROX is not set -# CONFIG_FB_RADEON is not set -# CONFIG_FB_ATY128 is not set -# CONFIG_FB_ATY is not set -# CONFIG_FB_S3 is not set -# CONFIG_FB_SAVAGE is not set -# CONFIG_FB_SIS is not set -# CONFIG_FB_NEOMAGIC is not set -# CONFIG_FB_KYRO is not set -# CONFIG_FB_3DFX is not set -# CONFIG_FB_VOODOO1 is not set -# CONFIG_FB_VT8623 is not set -# CONFIG_FB_TRIDENT is not set -# CONFIG_FB_ARK is not set -# CONFIG_FB_PM3 is not set -# CONFIG_FB_CARMINE is not set -# CONFIG_FB_SMSCUFX is not set -# CONFIG_FB_UDL is not set -# CONFIG_FB_IBM_GXT4500 is not set -# CONFIG_FB_VIRTUAL is not set -# CONFIG_FB_METRONOME is not set -# CONFIG_FB_MB862XX is not set -# CONFIG_FB_SIMPLE is not set -# CONFIG_FB_SM712 is not set -# end of Frame buffer Devices - -# -# Backlight & LCD device support -# -# CONFIG_LCD_CLASS_DEVICE is not set CONFIG_BACKLIGHT_CLASS_DEVICE=y -# CONFIG_BACKLIGHT_APPLE is not set -# CONFIG_BACKLIGHT_QCOM_WLED is not set -# CONFIG_BACKLIGHT_SAHARA is not set -# CONFIG_BACKLIGHT_ADP8860 is not set -# CONFIG_BACKLIGHT_ADP8870 is not set -# CONFIG_BACKLIGHT_LM3639 is not set -# CONFIG_BACKLIGHT_LV5207LP is not set -# CONFIG_BACKLIGHT_BD6107 is not set -# CONFIG_BACKLIGHT_ARCXCNN is not set -# end of Backlight & LCD device support - -CONFIG_HDMI=y - -# -# Console display driver support -# -CONFIG_VGA_CONSOLE=y -CONFIG_DUMMY_CONSOLE=y -CONFIG_DUMMY_CONSOLE_COLUMNS=80 -CONFIG_DUMMY_CONSOLE_ROWS=25 CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y -# CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER is not set -# end of Console display driver support - -# CONFIG_LOGO is not set -# end of Graphics support - -# CONFIG_SOUND is not set - -# -# HID support -# -CONFIG_HID=y CONFIG_HID_BATTERY_STRENGTH=y CONFIG_HIDRAW=y -# CONFIG_UHID is not set -CONFIG_HID_GENERIC=y - -# -# Special HID drivers -# CONFIG_HID_A4TECH=y -# CONFIG_HID_ACCUTOUCH is not set -# CONFIG_HID_ACRUX is not set CONFIG_HID_APPLE=y -# CONFIG_HID_APPLEIR is not set -# CONFIG_HID_ASUS is not set -# CONFIG_HID_AUREAL is not set CONFIG_HID_BELKIN=y -# CONFIG_HID_BETOP_FF is not set -# CONFIG_HID_BIGBEN_FF is not set CONFIG_HID_CHERRY=y CONFIG_HID_CHICONY=y -# CONFIG_HID_CORSAIR is not set -# CONFIG_HID_COUGAR is not set -# CONFIG_HID_MACALLY is not set -# CONFIG_HID_CMEDIA is not set -# CONFIG_HID_CREATIVE_SB0540 is not set CONFIG_HID_CYPRESS=y -# CONFIG_HID_DRAGONRISE is not set -# CONFIG_HID_EMS_FF is not set -# CONFIG_HID_ELAN is not set -# CONFIG_HID_ELECOM is not set -# CONFIG_HID_ELO is not set CONFIG_HID_EZKEY=y -# CONFIG_HID_FT260 is not set -# CONFIG_HID_GEMBIRD is not set -# CONFIG_HID_GFRM is not set -# CONFIG_HID_GLORIOUS is not set -# CONFIG_HID_HOLTEK is not set -# CONFIG_HID_VIVALDI is not set -# CONFIG_HID_GT683R is not set -# CONFIG_HID_KEYTOUCH is not set CONFIG_HID_KYE=y -# CONFIG_HID_UCLOGIC is not set -# CONFIG_HID_WALTOP is not set -# CONFIG_HID_VIEWSONIC is not set -# CONFIG_HID_GYRATION is not set -# CONFIG_HID_ICADE is not set -# CONFIG_HID_ITE is not set -# CONFIG_HID_JABRA is not set -# CONFIG_HID_TWINHAN is not set CONFIG_HID_KENSINGTON=y -# CONFIG_HID_LCPOWER is not set -# CONFIG_HID_LED is not set -# CONFIG_HID_LENOVO is not set CONFIG_HID_LOGITECH=y -# CONFIG_HID_LOGITECH_DJ is not set -# CONFIG_HID_LOGITECH_HIDPP is not set -# CONFIG_LOGITECH_FF is not set -# CONFIG_LOGIRUMBLEPAD2_FF is not set -# CONFIG_LOGIG940_FF is not set -# CONFIG_LOGIWHEELS_FF is not set -# CONFIG_HID_MAGICMOUSE is not set -# CONFIG_HID_MALTRON is not set -# CONFIG_HID_MAYFLASH is not set -# CONFIG_HID_REDRAGON is not set CONFIG_HID_MICROSOFT=y CONFIG_HID_MONTEREY=y -# CONFIG_HID_MULTITOUCH is not set -# CONFIG_HID_NTI is not set -# CONFIG_HID_NTRIG is not set -# CONFIG_HID_ORTEK is not set -# CONFIG_HID_PANTHERLORD is not set -# CONFIG_HID_PENMOUNT is not set -# CONFIG_HID_PETALYNX is not set -# CONFIG_HID_PICOLCD is not set CONFIG_HID_PLANTRONICS=y -# CONFIG_HID_PLAYSTATION is not set -# CONFIG_HID_PRIMAX is not set -# CONFIG_HID_RETRODE is not set -# CONFIG_HID_ROCCAT is not set -# CONFIG_HID_SAITEK is not set -# CONFIG_HID_SAMSUNG is not set -# CONFIG_HID_SEMITEK is not set -# CONFIG_HID_SONY is not set -# CONFIG_HID_SPEEDLINK is not set -# CONFIG_HID_STEAM is not set -# CONFIG_HID_STEELSERIES is not set -# CONFIG_HID_SUNPLUS is not set -# CONFIG_HID_RMI is not set -# CONFIG_HID_GREENASIA is not set -# CONFIG_HID_SMARTJOYPLUS is not set -# CONFIG_HID_TIVO is not set -# CONFIG_HID_TOPSEED is not set -# CONFIG_HID_THINGM is not set -# CONFIG_HID_THRUSTMASTER is not set -# CONFIG_HID_UDRAW_PS3 is not set -# CONFIG_HID_WACOM is not set -# CONFIG_HID_WIIMOTE is not set -# CONFIG_HID_XINMO is not set -# CONFIG_HID_ZEROPLUS is not set -# CONFIG_HID_ZYDACRON is not set -# CONFIG_HID_SENSOR_HUB is not set -# CONFIG_HID_ALPS is not set -# end of Special HID drivers - -# -# USB HID support -# -CONFIG_USB_HID=y CONFIG_HID_PID=y CONFIG_USB_HIDDEV=y -# end of USB HID support - -# -# I2C HID support -# -# CONFIG_I2C_HID_ACPI is not set -# end of I2C HID support - -# -# Intel ISH HID support -# -# CONFIG_INTEL_ISH_HID is not set -# end of Intel ISH HID support - -# -# AMD SFH HID Support -# -# CONFIG_AMD_SFH_HID is not set -# end of AMD SFH HID Support -# end of HID support - -CONFIG_USB_OHCI_LITTLE_ENDIAN=y -CONFIG_USB_SUPPORT=y -CONFIG_USB_COMMON=y -# CONFIG_USB_LED_TRIG is not set -# CONFIG_USB_ULPI_BUS is not set -CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB=y -CONFIG_USB_PCI=y -# CONFIG_USB_ANNOUNCE_NEW_DEVICES is not set - -# -# Miscellaneous USB options -# -CONFIG_USB_DEFAULT_PERSIST=y -# CONFIG_USB_FEW_INIT_RETRIES is not set -# CONFIG_USB_DYNAMIC_MINORS is not set -# CONFIG_USB_OTG is not set -# CONFIG_USB_OTG_PRODUCTLIST is not set -# CONFIG_USB_OTG_DISABLE_EXTERNAL_HUB is not set -# CONFIG_USB_LEDS_TRIGGER_USBPORT is not set -CONFIG_USB_AUTOSUSPEND_DELAY=2 -# CONFIG_USB_MON is not set - -# -# USB Host Controller Drivers -# -# CONFIG_USB_C67X00_HCD is not set CONFIG_USB_XHCI_HCD=y -# CONFIG_USB_XHCI_DBGCAP is not set -CONFIG_USB_XHCI_PCI=y -# CONFIG_USB_XHCI_PCI_RENESAS is not set -# CONFIG_USB_XHCI_PLATFORM is not set CONFIG_USB_EHCI_HCD=y CONFIG_USB_EHCI_ROOT_HUB_TT=y -CONFIG_USB_EHCI_TT_NEWSCHED=y -CONFIG_USB_EHCI_PCI=y -# CONFIG_USB_EHCI_FSL is not set CONFIG_USB_EHCI_HCD_PLATFORM=y -# CONFIG_USB_OXU210HP_HCD is not set -# CONFIG_USB_ISP116X_HCD is not set -# CONFIG_USB_FOTG210_HCD is not set CONFIG_USB_OHCI_HCD=y -CONFIG_USB_OHCI_HCD_PCI=y -# CONFIG_USB_OHCI_HCD_PLATFORM is not set CONFIG_USB_UHCI_HCD=y -# CONFIG_USB_SL811_HCD is not set -# CONFIG_USB_R8A66597_HCD is not set -# CONFIG_USB_HCD_TEST_MODE is not set - -# -# USB Device Class drivers -# -# CONFIG_USB_ACM is not set -# CONFIG_USB_PRINTER is not set -# CONFIG_USB_WDM is not set -# CONFIG_USB_TMC is not set - -# -# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may -# - -# -# also be needed; see USB_STORAGE Help for more info -# CONFIG_USB_STORAGE=y -# CONFIG_USB_STORAGE_DEBUG is not set -# CONFIG_USB_STORAGE_REALTEK is not set -# CONFIG_USB_STORAGE_DATAFAB is not set -# CONFIG_USB_STORAGE_FREECOM is not set -# CONFIG_USB_STORAGE_ISD200 is not set -# CONFIG_USB_STORAGE_USBAT is not set -# CONFIG_USB_STORAGE_SDDR09 is not set -# CONFIG_USB_STORAGE_SDDR55 is not set -# CONFIG_USB_STORAGE_JUMPSHOT is not set -# CONFIG_USB_STORAGE_ALAUDA is not set -# CONFIG_USB_STORAGE_ONETOUCH is not set -# CONFIG_USB_STORAGE_KARMA is not set -# CONFIG_USB_STORAGE_CYPRESS_ATACB is not set -# CONFIG_USB_STORAGE_ENE_UB6250 is not set -# CONFIG_USB_UAS is not set - -# -# USB Imaging devices -# -# CONFIG_USB_MDC800 is not set -# CONFIG_USB_MICROTEK is not set -# CONFIG_USBIP_CORE is not set -# CONFIG_USB_CDNS_SUPPORT is not set -# CONFIG_USB_MUSB_HDRC is not set -# CONFIG_USB_DWC3 is not set -# CONFIG_USB_DWC2 is not set -# CONFIG_USB_CHIPIDEA is not set -# CONFIG_USB_ISP1760 is not set - -# -# USB port drivers -# -# CONFIG_USB_USS720 is not set -# CONFIG_USB_SERIAL is not set - -# -# USB Miscellaneous drivers -# -# CONFIG_USB_EMI62 is not set -# CONFIG_USB_EMI26 is not set -# CONFIG_USB_ADUTUX is not set -# CONFIG_USB_SEVSEG is not set -# CONFIG_USB_LEGOTOWER is not set -# CONFIG_USB_LCD is not set -# CONFIG_USB_CYPRESS_CY7C63 is not set -# CONFIG_USB_CYTHERM is not set -# CONFIG_USB_IDMOUSE is not set -# CONFIG_USB_FTDI_ELAN is not set -# CONFIG_USB_APPLEDISPLAY is not set -# CONFIG_APPLE_MFI_FASTCHARGE is not set -# CONFIG_USB_SISUSBVGA is not set -# CONFIG_USB_LD is not set -# CONFIG_USB_TRANCEVIBRATOR is not set -# CONFIG_USB_IOWARRIOR is not set -# CONFIG_USB_TEST is not set -# CONFIG_USB_EHSET_TEST_FIXTURE is not set -# CONFIG_USB_ISIGHTFW is not set -# CONFIG_USB_YUREX is not set -# CONFIG_USB_EZUSB_FX2 is not set -# CONFIG_USB_HUB_USB251XB is not set -# CONFIG_USB_HSIC_USB3503 is not set -# CONFIG_USB_HSIC_USB4604 is not set -# CONFIG_USB_LINK_LAYER_TEST is not set - -# -# USB Physical Layer drivers -# -# CONFIG_NOP_USB_XCEIV is not set -# CONFIG_USB_ISP1301 is not set -# end of USB Physical Layer drivers - -# CONFIG_USB_GADGET is not set -# CONFIG_TYPEC is not set -# CONFIG_USB_ROLE_SWITCH is not set -# CONFIG_MMC is not set -# CONFIG_MEMSTICK is not set CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y -# CONFIG_LEDS_CLASS_FLASH is not set -# CONFIG_LEDS_CLASS_MULTICOLOR is not set -# CONFIG_LEDS_BRIGHTNESS_HW_CHANGED is not set - -# -# LED drivers -# -# CONFIG_LEDS_APU is not set -# CONFIG_LEDS_LM3530 is not set -# CONFIG_LEDS_LM3532 is not set -# CONFIG_LEDS_LM3642 is not set -# CONFIG_LEDS_PCA9532 is not set -# CONFIG_LEDS_LP3944 is not set -# CONFIG_LEDS_CLEVO_MAIL is not set -# CONFIG_LEDS_PCA955X is not set -# CONFIG_LEDS_PCA963X is not set -# CONFIG_LEDS_BD2802 is not set -# CONFIG_LEDS_INTEL_SS4200 is not set -# CONFIG_LEDS_TCA6507 is not set -# CONFIG_LEDS_TLC591XX is not set -# CONFIG_LEDS_LM355x is not set - -# -# LED driver for blink(1) USB RGB LED is under Special HID drivers (HID_THINGM) -# -# CONFIG_LEDS_BLINKM is not set -# CONFIG_LEDS_MLXCPLD is not set -# CONFIG_LEDS_MLXREG is not set -# CONFIG_LEDS_USER is not set -# CONFIG_LEDS_NIC78BX is not set - -# -# Flash and Torch LED drivers -# - -# -# LED Triggers -# CONFIG_LEDS_TRIGGERS=y -# CONFIG_LEDS_TRIGGER_TIMER is not set -# CONFIG_LEDS_TRIGGER_ONESHOT is not set -# CONFIG_LEDS_TRIGGER_DISK is not set -# CONFIG_LEDS_TRIGGER_HEARTBEAT is not set -# CONFIG_LEDS_TRIGGER_BACKLIGHT is not set -# CONFIG_LEDS_TRIGGER_CPU is not set -# CONFIG_LEDS_TRIGGER_ACTIVITY is not set -# CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set - -# -# iptables trigger is under Netfilter config (LED target) -# -# CONFIG_LEDS_TRIGGER_TRANSIENT is not set -# CONFIG_LEDS_TRIGGER_CAMERA is not set -# CONFIG_LEDS_TRIGGER_PANIC is not set -# CONFIG_LEDS_TRIGGER_NETDEV is not set -# CONFIG_LEDS_TRIGGER_PATTERN is not set -# CONFIG_LEDS_TRIGGER_AUDIO is not set -# CONFIG_LEDS_TRIGGER_TTY is not set -# CONFIG_ACCESSIBILITY is not set -# CONFIG_INFINIBAND is not set -CONFIG_EDAC_ATOMIC_SCRUB=y -CONFIG_EDAC_SUPPORT=y -# CONFIG_EDAC is not set -CONFIG_RTC_LIB=y -CONFIG_RTC_MC146818_LIB=y CONFIG_RTC_CLASS=y # CONFIG_RTC_HCTOSYS is not set -CONFIG_RTC_SYSTOHC=y -CONFIG_RTC_SYSTOHC_DEVICE="rtc0" -# CONFIG_RTC_DEBUG is not set -CONFIG_RTC_NVMEM=y - -# -# RTC interfaces -# -CONFIG_RTC_INTF_SYSFS=y -CONFIG_RTC_INTF_PROC=y -CONFIG_RTC_INTF_DEV=y -# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set -# CONFIG_RTC_DRV_TEST is not set - -# -# I2C RTC drivers -# -# CONFIG_RTC_DRV_ABB5ZES3 is not set -# CONFIG_RTC_DRV_ABEOZ9 is not set -# CONFIG_RTC_DRV_ABX80X is not set -# CONFIG_RTC_DRV_DS1307 is not set -# CONFIG_RTC_DRV_DS1374 is not set -# CONFIG_RTC_DRV_DS1672 is not set -# CONFIG_RTC_DRV_MAX6900 is not set -# CONFIG_RTC_DRV_RS5C372 is not set -# CONFIG_RTC_DRV_ISL1208 is not set -# CONFIG_RTC_DRV_ISL12022 is not set -# CONFIG_RTC_DRV_X1205 is not set -# CONFIG_RTC_DRV_PCF8523 is not set -# CONFIG_RTC_DRV_PCF85063 is not set -# CONFIG_RTC_DRV_PCF85363 is not set -# CONFIG_RTC_DRV_PCF8563 is not set -# CONFIG_RTC_DRV_PCF8583 is not set -# CONFIG_RTC_DRV_M41T80 is not set -# CONFIG_RTC_DRV_BQ32K is not set -# CONFIG_RTC_DRV_S35390A is not set -# CONFIG_RTC_DRV_FM3130 is not set -# CONFIG_RTC_DRV_RX8010 is not set -# CONFIG_RTC_DRV_RX8581 is not set -# CONFIG_RTC_DRV_RX8025 is not set -# CONFIG_RTC_DRV_EM3027 is not set -# CONFIG_RTC_DRV_RV3028 is not set -# CONFIG_RTC_DRV_RV3032 is not set -# CONFIG_RTC_DRV_RV8803 is not set -# CONFIG_RTC_DRV_SD3078 is not set - -# -# SPI RTC drivers -# -CONFIG_RTC_I2C_AND_SPI=y - -# -# SPI and I2C RTC drivers -# -# CONFIG_RTC_DRV_DS3232 is not set -# CONFIG_RTC_DRV_PCF2127 is not set -# CONFIG_RTC_DRV_RV3029C2 is not set -# CONFIG_RTC_DRV_RX6110 is not set - -# -# Platform RTC drivers -# -CONFIG_RTC_DRV_CMOS=y -# CONFIG_RTC_DRV_DS1286 is not set -# CONFIG_RTC_DRV_DS1511 is not set -# CONFIG_RTC_DRV_DS1553 is not set -# CONFIG_RTC_DRV_DS1685_FAMILY is not set -# CONFIG_RTC_DRV_DS1742 is not set -# CONFIG_RTC_DRV_DS2404 is not set -# CONFIG_RTC_DRV_STK17TA8 is not set -# CONFIG_RTC_DRV_M48T86 is not set -# CONFIG_RTC_DRV_M48T35 is not set -# CONFIG_RTC_DRV_M48T59 is not set -# CONFIG_RTC_DRV_MSM6242 is not set -# CONFIG_RTC_DRV_BQ4802 is not set -# CONFIG_RTC_DRV_RP5C01 is not set -# CONFIG_RTC_DRV_V3020 is not set - -# -# on-CPU RTC drivers -# -# CONFIG_RTC_DRV_FTRTC010 is not set - -# -# HID Sensor RTC drivers -# -# CONFIG_RTC_DRV_GOLDFISH is not set CONFIG_DMADEVICES=y -# CONFIG_DMADEVICES_DEBUG is not set - -# -# DMA Devices -# -CONFIG_DMA_ENGINE=y -CONFIG_DMA_ACPI=y -# CONFIG_ALTERA_MSGDMA is not set -# CONFIG_INTEL_IDMA64 is not set -# CONFIG_INTEL_IDXD is not set -# CONFIG_INTEL_IOATDMA is not set -# CONFIG_PLX_DMA is not set -# CONFIG_QCOM_HIDMA_MGMT is not set -# CONFIG_QCOM_HIDMA is not set -CONFIG_DW_DMAC_CORE=y -# CONFIG_DW_DMAC is not set -CONFIG_DW_DMAC_PCI=y -# CONFIG_DW_EDMA is not set -# CONFIG_DW_EDMA_PCIE is not set -# CONFIG_SF_PDMA is not set -# CONFIG_INTEL_LDMA is not set - -# -# DMA Clients -# -# CONFIG_ASYNC_TX_DMA is not set -# CONFIG_DMATEST is not set - -# -# DMABUF options -# -CONFIG_SYNC_FILE=y -# CONFIG_SW_SYNC is not set -# CONFIG_UDMABUF is not set -# CONFIG_DMABUF_MOVE_NOTIFY is not set -# CONFIG_DMABUF_DEBUG is not set -# CONFIG_DMABUF_SELFTESTS is not set -# CONFIG_DMABUF_HEAPS is not set -# end of DMABUF options - -# CONFIG_AUXDISPLAY is not set -# CONFIG_PANEL is not set -# CONFIG_UIO is not set -# CONFIG_VFIO is not set -# CONFIG_VIRT_DRIVERS is not set -CONFIG_VIRTIO_MENU=y -# CONFIG_VIRTIO_PCI is not set -# CONFIG_VIRTIO_MMIO is not set -# CONFIG_VDPA is not set -CONFIG_VHOST_MENU=y -# CONFIG_VHOST_NET is not set -# CONFIG_VHOST_CROSS_ENDIAN_LEGACY is not set - -# -# Microsoft Hyper-V guest support -# -# CONFIG_HYPERV is not set -# end of Microsoft Hyper-V guest support - -# CONFIG_GREYBUS is not set -# CONFIG_COMEDI is not set -# CONFIG_STAGING is not set # CONFIG_X86_PLATFORM_DEVICES is not set -CONFIG_PMC_ATOM=y -# CONFIG_CHROME_PLATFORMS is not set -# CONFIG_MELLANOX_PLATFORM is not set -CONFIG_SURFACE_PLATFORMS=y -# CONFIG_SURFACE_3_POWER_OPREGION is not set -# CONFIG_SURFACE_GPE is not set -# CONFIG_SURFACE_PRO3_BUTTON is not set -CONFIG_HAVE_CLK=y -CONFIG_CLKDEV_LOOKUP=y -CONFIG_HAVE_CLK_PREPARE=y -CONFIG_COMMON_CLK=y -# CONFIG_COMMON_CLK_MAX9485 is not set -# CONFIG_COMMON_CLK_SI5341 is not set -# CONFIG_COMMON_CLK_SI5351 is not set -# CONFIG_COMMON_CLK_SI544 is not set -# CONFIG_COMMON_CLK_CDCE706 is not set -# CONFIG_COMMON_CLK_CS2000_CP is not set -# CONFIG_XILINX_VCU is not set -# CONFIG_HWSPINLOCK is not set - -# -# Clock Source drivers -# -CONFIG_CLKEVT_I8253=y -CONFIG_I8253_LOCK=y -CONFIG_CLKBLD_I8253=y -# end of Clock Source drivers - -CONFIG_MAILBOX=y -CONFIG_PCC=y -# CONFIG_ALTERA_MBOX is not set -CONFIG_IOMMU_IOVA=y -CONFIG_IOASID=y -CONFIG_IOMMU_API=y -CONFIG_IOMMU_SUPPORT=y - -# -# Generic IOMMU Pagetable Support -# -CONFIG_IOMMU_IO_PGTABLE=y -# end of Generic IOMMU Pagetable Support - -# CONFIG_IOMMU_DEBUGFS is not set -# CONFIG_IOMMU_DEFAULT_PASSTHROUGH is not set -CONFIG_IOMMU_DMA=y CONFIG_AMD_IOMMU=y -CONFIG_AMD_IOMMU_V2=m -CONFIG_DMAR_TABLE=y CONFIG_INTEL_IOMMU=y -# CONFIG_INTEL_IOMMU_SVM is not set -CONFIG_INTEL_IOMMU_DEFAULT_ON=y -CONFIG_INTEL_IOMMU_FLOPPY_WA=y # CONFIG_INTEL_IOMMU_SCALABLE_MODE_DEFAULT_ON is not set -# CONFIG_IRQ_REMAP is not set - -# -# Remoteproc drivers -# -# CONFIG_REMOTEPROC is not set -# end of Remoteproc drivers - -# -# Rpmsg drivers -# -# CONFIG_RPMSG_QCOM_GLINK_RPM is not set -# CONFIG_RPMSG_VIRTIO is not set -# end of Rpmsg drivers - -# CONFIG_SOUNDWIRE is not set - -# -# SOC (System On Chip) specific Drivers -# - -# -# Amlogic SoC drivers -# -# end of Amlogic SoC drivers - -# -# Broadcom SoC drivers -# -# end of Broadcom SoC drivers - -# -# NXP/Freescale QorIQ SoC drivers -# -# end of NXP/Freescale QorIQ SoC drivers - -# -# i.MX SoC drivers -# -# end of i.MX SoC drivers - -# -# Enable LiteX SoC Builder specific drivers -# -# end of Enable LiteX SoC Builder specific drivers - -# -# Qualcomm SoC drivers -# -# end of Qualcomm SoC drivers - -# CONFIG_SOC_TI is not set - -# -# Xilinx SoC drivers -# -# end of Xilinx SoC drivers -# end of SOC (System On Chip) specific Drivers - -# CONFIG_PM_DEVFREQ is not set -# CONFIG_EXTCON is not set -# CONFIG_MEMORY is not set -# CONFIG_IIO is not set -# CONFIG_NTB is not set -# CONFIG_VME_BUS is not set -# CONFIG_PWM is not set - -# -# IRQ chip support -# -# end of IRQ chip support - -# CONFIG_IPACK_BUS is not set -# CONFIG_RESET_CONTROLLER is not set - -# -# PHY Subsystem -# -# CONFIG_GENERIC_PHY is not set -# CONFIG_USB_LGM_PHY is not set -# CONFIG_BCM_KONA_USB2_PHY is not set -# CONFIG_PHY_PXA_28NM_HSIC is not set -# CONFIG_PHY_PXA_28NM_USB2 is not set -# CONFIG_PHY_INTEL_LGM_EMMC is not set -# end of PHY Subsystem - -# CONFIG_POWERCAP is not set -# CONFIG_MCB is not set - -# -# Performance monitor support -# -# end of Performance monitor support - -CONFIG_RAS=y -# CONFIG_RAS_CEC is not set -# CONFIG_USB4 is not set - -# -# Android -# -# CONFIG_ANDROID is not set -# end of Android - -# CONFIG_LIBNVDIMM is not set CONFIG_DAX=y -# CONFIG_DEV_DAX is not set -CONFIG_NVMEM=y -CONFIG_NVMEM_SYSFS=y -# CONFIG_NVMEM_RMEM is not set - -# -# HW tracing support -# -# CONFIG_STM is not set -# CONFIG_INTEL_TH is not set -# end of HW tracing support - -# CONFIG_FPGA is not set -# CONFIG_TEE is not set -# CONFIG_UNISYS_VISORBUS is not set -# CONFIG_SIOX is not set -# CONFIG_SLIMBUS is not set -# CONFIG_INTERCONNECT is not set -# CONFIG_COUNTER is not set -# CONFIG_MOST is not set -# end of Device Drivers - -# -# File systems -# -CONFIG_DCACHE_WORD_ACCESS=y CONFIG_VALIDATE_FS_PARSER=y -CONFIG_FS_IOMAP=y -# CONFIG_EXT2_FS is not set -# CONFIG_EXT3_FS is not set CONFIG_EXT4_FS=y -CONFIG_EXT4_USE_FOR_EXT2=y CONFIG_EXT4_FS_POSIX_ACL=y CONFIG_EXT4_FS_SECURITY=y -# CONFIG_EXT4_DEBUG is not set -CONFIG_JBD2=y -# CONFIG_JBD2_DEBUG is not set -CONFIG_FS_MBCACHE=y -# CONFIG_REISERFS_FS is not set -# CONFIG_JFS_FS is not set CONFIG_XFS_FS=y -CONFIG_XFS_SUPPORT_V4=y CONFIG_XFS_QUOTA=y CONFIG_XFS_POSIX_ACL=y CONFIG_XFS_RT=y -# CONFIG_XFS_ONLINE_SCRUB is not set CONFIG_XFS_WARN=y -# CONFIG_XFS_DEBUG is not set -# CONFIG_GFS2_FS is not set -# CONFIG_OCFS2_FS is not set -# CONFIG_BTRFS_FS is not set -# CONFIG_NILFS2_FS is not set -# CONFIG_F2FS_FS is not set -# CONFIG_FS_DAX is not set -CONFIG_FS_POSIX_ACL=y -CONFIG_EXPORTFS=y -# CONFIG_EXPORTFS_BLOCK_OPS is not set -CONFIG_FILE_LOCKING=y -CONFIG_MANDATORY_FILE_LOCKING=y -# CONFIG_FS_ENCRYPTION is not set -# CONFIG_FS_VERITY is not set -CONFIG_FSNOTIFY=y -CONFIG_DNOTIFY=y -CONFIG_INOTIFY_USER=y CONFIG_FANOTIFY=y CONFIG_QUOTA=y CONFIG_QUOTA_NETLINK_INTERFACE=y # CONFIG_PRINT_QUOTA_WARNING is not set -# CONFIG_QUOTA_DEBUG is not set -CONFIG_QUOTA_TREE=y -# CONFIG_QFMT_V1 is not set CONFIG_QFMT_V2=y -CONFIG_QUOTACTL=y CONFIG_AUTOFS4_FS=y -CONFIG_AUTOFS_FS=y CONFIG_FUSE_FS=m CONFIG_CUSE=m -# CONFIG_VIRTIO_FS is not set CONFIG_OVERLAY_FS=y -# CONFIG_OVERLAY_FS_REDIRECT_DIR is not set -CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW=y -# CONFIG_OVERLAY_FS_INDEX is not set -# CONFIG_OVERLAY_FS_XINO_AUTO is not set -# CONFIG_OVERLAY_FS_METACOPY is not set - -# -# Caches -# -CONFIG_NETFS_SUPPORT=y -# CONFIG_NETFS_STATS is not set CONFIG_FSCACHE=y -# CONFIG_FSCACHE_STATS is not set -# CONFIG_FSCACHE_HISTOGRAM is not set -# CONFIG_FSCACHE_DEBUG is not set -# CONFIG_FSCACHE_OBJECT_LIST is not set -# CONFIG_CACHEFILES is not set -# end of Caches - -# -# CD-ROM/DVD Filesystems -# CONFIG_ISO9660_FS=y CONFIG_JOLIET=y CONFIG_ZISOFS=y -# CONFIG_UDF_FS is not set -# end of CD-ROM/DVD Filesystems - -# -# DOS/FAT/EXFAT/NT Filesystems -# -CONFIG_FAT_FS=y CONFIG_MSDOS_FS=y CONFIG_VFAT_FS=y -CONFIG_FAT_DEFAULT_CODEPAGE=437 -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" -# CONFIG_FAT_DEFAULT_UTF8 is not set -# CONFIG_EXFAT_FS is not set CONFIG_NTFS_FS=y -# CONFIG_NTFS_DEBUG is not set CONFIG_NTFS_RW=y -# end of DOS/FAT/EXFAT/NT Filesystems - -# -# Pseudo filesystems -# -CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y -CONFIG_PROC_VMCORE=y -# CONFIG_PROC_VMCORE_DEVICE_DUMP is not set -CONFIG_PROC_SYSCTL=y -CONFIG_PROC_PAGE_MONITOR=y -CONFIG_PROC_CHILDREN=y -CONFIG_PROC_PID_ARCH_STATUS=y -CONFIG_KERNFS=y -CONFIG_SYSFS=y CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y -CONFIG_TMPFS_XATTR=y -# CONFIG_TMPFS_INODE64 is not set CONFIG_HUGETLBFS=y -CONFIG_HUGETLB_PAGE=y -CONFIG_MEMFD_CREATE=y -CONFIG_ARCH_HAS_GIGANTIC_PAGE=y CONFIG_CONFIGFS_FS=y # CONFIG_EFIVAR_FS is not set -# end of Pseudo filesystems - -CONFIG_MISC_FILESYSTEMS=y -# CONFIG_ORANGEFS_FS is not set -# CONFIG_ADFS_FS is not set -# CONFIG_AFFS_FS is not set -# CONFIG_ECRYPT_FS is not set -# CONFIG_HFS_FS is not set -# CONFIG_HFSPLUS_FS is not set -# CONFIG_BEFS_FS is not set -# CONFIG_BFS_FS is not set -# CONFIG_EFS_FS is not set -# CONFIG_CRAMFS is not set -# CONFIG_SQUASHFS is not set -# CONFIG_VXFS_FS is not set -# CONFIG_MINIX_FS is not set -# CONFIG_OMFS_FS is not set -# CONFIG_HPFS_FS is not set -# CONFIG_QNX4FS_FS is not set -# CONFIG_QNX6FS_FS is not set -# CONFIG_ROMFS_FS is not set -CONFIG_PSTORE=y -CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240 -CONFIG_PSTORE_DEFLATE_COMPRESS=y -# CONFIG_PSTORE_LZO_COMPRESS is not set -# CONFIG_PSTORE_LZ4_COMPRESS is not set -# CONFIG_PSTORE_LZ4HC_COMPRESS is not set -# CONFIG_PSTORE_842_COMPRESS is not set -# CONFIG_PSTORE_ZSTD_COMPRESS is not set -CONFIG_PSTORE_COMPRESS=y -CONFIG_PSTORE_DEFLATE_COMPRESS_DEFAULT=y -CONFIG_PSTORE_COMPRESS_DEFAULT="deflate" -# CONFIG_PSTORE_CONSOLE is not set -# CONFIG_PSTORE_PMSG is not set -# CONFIG_PSTORE_FTRACE is not set -# CONFIG_PSTORE_RAM is not set -# CONFIG_PSTORE_BLK is not set -# CONFIG_SYSV_FS is not set -# CONFIG_UFS_FS is not set -# CONFIG_EROFS_FS is not set -CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=y -CONFIG_NFS_V2=y -CONFIG_NFS_V3=y CONFIG_NFS_V3_ACL=y CONFIG_NFS_V4=y -# CONFIG_NFS_SWAP is not set -# CONFIG_NFS_V4_1 is not set CONFIG_ROOT_NFS=y -# CONFIG_NFS_FSCACHE is not set -# CONFIG_NFS_USE_LEGACY_DNS is not set -CONFIG_NFS_USE_KERNEL_DNS=y -CONFIG_NFS_DISABLE_UDP_SUPPORT=y -# CONFIG_NFSD is not set -CONFIG_GRACE_PERIOD=y -CONFIG_LOCKD=y -CONFIG_LOCKD_V4=y -CONFIG_NFS_ACL_SUPPORT=y -CONFIG_NFS_COMMON=y -CONFIG_SUNRPC=y -CONFIG_SUNRPC_GSS=y -# CONFIG_SUNRPC_DEBUG is not set -# CONFIG_CEPH_FS is not set CONFIG_CIFS=y # CONFIG_CIFS_STATS2 is not set -CONFIG_CIFS_ALLOW_INSECURE_LEGACY=y -# CONFIG_CIFS_WEAK_PW_HASH is not set -# CONFIG_CIFS_UPCALL is not set -# CONFIG_CIFS_XATTR is not set -CONFIG_CIFS_DEBUG=y -# CONFIG_CIFS_DEBUG2 is not set -# CONFIG_CIFS_DEBUG_DUMP_KEYS is not set -# CONFIG_CIFS_DFS_UPCALL is not set -# CONFIG_CIFS_SWN_UPCALL is not set CONFIG_CIFS_FSCACHE=y -# CONFIG_CIFS_ROOT is not set -# CONFIG_CODA_FS is not set -# CONFIG_AFS_FS is not set -CONFIG_NLS=y CONFIG_NLS_DEFAULT="utf8" CONFIG_NLS_CODEPAGE_437=y -# CONFIG_NLS_CODEPAGE_737 is not set -# CONFIG_NLS_CODEPAGE_775 is not set -# CONFIG_NLS_CODEPAGE_850 is not set -# CONFIG_NLS_CODEPAGE_852 is not set -# CONFIG_NLS_CODEPAGE_855 is not set -# CONFIG_NLS_CODEPAGE_857 is not set -# CONFIG_NLS_CODEPAGE_860 is not set -# CONFIG_NLS_CODEPAGE_861 is not set -# CONFIG_NLS_CODEPAGE_862 is not set -# CONFIG_NLS_CODEPAGE_863 is not set -# CONFIG_NLS_CODEPAGE_864 is not set -# CONFIG_NLS_CODEPAGE_865 is not set -# CONFIG_NLS_CODEPAGE_866 is not set -# CONFIG_NLS_CODEPAGE_869 is not set -# CONFIG_NLS_CODEPAGE_936 is not set -# CONFIG_NLS_CODEPAGE_950 is not set -# CONFIG_NLS_CODEPAGE_932 is not set -# CONFIG_NLS_CODEPAGE_949 is not set -# CONFIG_NLS_CODEPAGE_874 is not set -# CONFIG_NLS_ISO8859_8 is not set -# CONFIG_NLS_CODEPAGE_1250 is not set -# CONFIG_NLS_CODEPAGE_1251 is not set CONFIG_NLS_ASCII=y CONFIG_NLS_ISO8859_1=y -# CONFIG_NLS_ISO8859_2 is not set -# CONFIG_NLS_ISO8859_3 is not set -# CONFIG_NLS_ISO8859_4 is not set -# CONFIG_NLS_ISO8859_5 is not set -# CONFIG_NLS_ISO8859_6 is not set -# CONFIG_NLS_ISO8859_7 is not set -# CONFIG_NLS_ISO8859_9 is not set -# CONFIG_NLS_ISO8859_13 is not set -# CONFIG_NLS_ISO8859_14 is not set -# CONFIG_NLS_ISO8859_15 is not set -# CONFIG_NLS_KOI8_R is not set -# CONFIG_NLS_KOI8_U is not set -# CONFIG_NLS_MAC_ROMAN is not set -# CONFIG_NLS_MAC_CELTIC is not set -# CONFIG_NLS_MAC_CENTEURO is not set -# CONFIG_NLS_MAC_CROATIAN is not set -# CONFIG_NLS_MAC_CYRILLIC is not set -# CONFIG_NLS_MAC_GAELIC is not set -# CONFIG_NLS_MAC_GREEK is not set -# CONFIG_NLS_MAC_ICELAND is not set -# CONFIG_NLS_MAC_INUIT is not set -# CONFIG_NLS_MAC_ROMANIAN is not set -# CONFIG_NLS_MAC_TURKISH is not set CONFIG_NLS_UTF8=y -# CONFIG_DLM is not set -# CONFIG_UNICODE is not set -CONFIG_IO_WQ=y -# end of File systems - -# -# Security options -# -CONFIG_KEYS=y -# CONFIG_KEYS_REQUEST_CACHE is not set -# CONFIG_PERSISTENT_KEYRINGS is not set -# CONFIG_ENCRYPTED_KEYS is not set -# CONFIG_KEY_DH_OPERATIONS is not set -# CONFIG_SECURITY_DMESG_RESTRICT is not set CONFIG_SECURITY=y -CONFIG_SECURITY_WRITABLE_HOOKS=y -# CONFIG_SECURITYFS is not set CONFIG_SECURITY_NETWORK=y -CONFIG_PAGE_TABLE_ISOLATION=y -# CONFIG_SECURITY_NETWORK_XFRM is not set -# CONFIG_SECURITY_PATH is not set -# CONFIG_INTEL_TXT is not set -CONFIG_LSM_MMAP_MIN_ADDR=65536 -CONFIG_HAVE_HARDENED_USERCOPY_ALLOCATOR=y -# CONFIG_HARDENED_USERCOPY is not set -# CONFIG_FORTIFY_SOURCE is not set -# CONFIG_STATIC_USERMODEHELPER is not set CONFIG_SECURITY_SELINUX=y CONFIG_SECURITY_SELINUX_BOOTPARAM=y CONFIG_SECURITY_SELINUX_DISABLE=y -CONFIG_SECURITY_SELINUX_DEVELOP=y -CONFIG_SECURITY_SELINUX_AVC_STATS=y CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=1 -CONFIG_SECURITY_SELINUX_SIDTAB_HASH_BITS=9 -CONFIG_SECURITY_SELINUX_SID2STR_CACHE_SIZE=256 -# CONFIG_SECURITY_SMACK is not set -# CONFIG_SECURITY_TOMOYO is not set -# CONFIG_SECURITY_APPARMOR is not set -# CONFIG_SECURITY_LOADPIN is not set -# CONFIG_SECURITY_YAMA is not set -# CONFIG_SECURITY_SAFESETID is not set -# CONFIG_SECURITY_LOCKDOWN_LSM is not set -# CONFIG_SECURITY_LANDLOCK is not set -CONFIG_INTEGRITY=y -# CONFIG_INTEGRITY_SIGNATURE is not set -CONFIG_INTEGRITY_AUDIT=y -# CONFIG_IMA is not set -# CONFIG_IMA_SECURE_AND_OR_TRUSTED_BOOT is not set -# CONFIG_EVM is not set -CONFIG_DEFAULT_SECURITY_SELINUX=y -# CONFIG_DEFAULT_SECURITY_DAC is not set CONFIG_LSM="yama,loadpin,safesetid,integrity,selinux,smack,tomoyo,apparmor" - -# -# Kernel hardening options -# - -# -# Memory initialization -# -CONFIG_INIT_STACK_NONE=y -# CONFIG_INIT_ON_ALLOC_DEFAULT_ON is not set -# CONFIG_INIT_ON_FREE_DEFAULT_ON is not set -# end of Memory initialization -# end of Kernel hardening options -# end of Security options - -CONFIG_CRYPTO=y - -# -# Crypto core or helper -# -CONFIG_CRYPTO_ALGAPI=y -CONFIG_CRYPTO_ALGAPI2=y -CONFIG_CRYPTO_AEAD=y -CONFIG_CRYPTO_AEAD2=y -CONFIG_CRYPTO_SKCIPHER=y -CONFIG_CRYPTO_SKCIPHER2=y -CONFIG_CRYPTO_HASH=y -CONFIG_CRYPTO_HASH2=y -CONFIG_CRYPTO_RNG=y -CONFIG_CRYPTO_RNG2=y -CONFIG_CRYPTO_RNG_DEFAULT=y -CONFIG_CRYPTO_AKCIPHER2=y -CONFIG_CRYPTO_AKCIPHER=y -CONFIG_CRYPTO_KPP2=y -CONFIG_CRYPTO_ACOMP2=y -CONFIG_CRYPTO_MANAGER=y -CONFIG_CRYPTO_MANAGER2=y -# CONFIG_CRYPTO_USER is not set -CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y -CONFIG_CRYPTO_GF128MUL=y -CONFIG_CRYPTO_NULL=y -CONFIG_CRYPTO_NULL2=y -# CONFIG_CRYPTO_PCRYPT is not set -# CONFIG_CRYPTO_CRYPTD is not set CONFIG_CRYPTO_AUTHENC=y -# CONFIG_CRYPTO_TEST is not set - -# -# Public-key cryptography -# -CONFIG_CRYPTO_RSA=y -# CONFIG_CRYPTO_DH is not set -# CONFIG_CRYPTO_ECDH is not set -# CONFIG_CRYPTO_ECDSA is not set -# CONFIG_CRYPTO_ECRDSA is not set -# CONFIG_CRYPTO_SM2 is not set -# CONFIG_CRYPTO_CURVE25519 is not set -# CONFIG_CRYPTO_CURVE25519_X86 is not set - -# -# Authenticated Encryption with Associated Data -# -CONFIG_CRYPTO_CCM=y -CONFIG_CRYPTO_GCM=y -# CONFIG_CRYPTO_CHACHA20POLY1305 is not set -# CONFIG_CRYPTO_AEGIS128 is not set -# CONFIG_CRYPTO_AEGIS128_AESNI_SSE2 is not set CONFIG_CRYPTO_SEQIV=y CONFIG_CRYPTO_ECHAINIV=y - -# -# Block modes -# CONFIG_CRYPTO_CBC=y -# CONFIG_CRYPTO_CFB is not set -CONFIG_CRYPTO_CTR=y -# CONFIG_CRYPTO_CTS is not set -CONFIG_CRYPTO_ECB=y -# CONFIG_CRYPTO_LRW is not set -# CONFIG_CRYPTO_OFB is not set -# CONFIG_CRYPTO_PCBC is not set -# CONFIG_CRYPTO_XTS is not set -# CONFIG_CRYPTO_KEYWRAP is not set -# CONFIG_CRYPTO_NHPOLY1305_SSE2 is not set -# CONFIG_CRYPTO_NHPOLY1305_AVX2 is not set -# CONFIG_CRYPTO_ADIANTUM is not set -# CONFIG_CRYPTO_ESSIV is not set - -# -# Hash modes -# -CONFIG_CRYPTO_CMAC=y -CONFIG_CRYPTO_HMAC=y -# CONFIG_CRYPTO_XCBC is not set -# CONFIG_CRYPTO_VMAC is not set - -# -# Digest -# -CONFIG_CRYPTO_CRC32C=y -# CONFIG_CRYPTO_CRC32C_INTEL is not set -# CONFIG_CRYPTO_CRC32 is not set -# CONFIG_CRYPTO_CRC32_PCLMUL is not set -# CONFIG_CRYPTO_XXHASH is not set -# CONFIG_CRYPTO_BLAKE2B is not set -# CONFIG_CRYPTO_BLAKE2S is not set -# CONFIG_CRYPTO_BLAKE2S_X86 is not set -CONFIG_CRYPTO_CRCT10DIF=y -# CONFIG_CRYPTO_CRCT10DIF_PCLMUL is not set -CONFIG_CRYPTO_GHASH=y -# CONFIG_CRYPTO_POLY1305 is not set -# CONFIG_CRYPTO_POLY1305_X86_64 is not set CONFIG_CRYPTO_MD4=y -CONFIG_CRYPTO_MD5=y -# CONFIG_CRYPTO_MICHAEL_MIC is not set -# CONFIG_CRYPTO_RMD160 is not set CONFIG_CRYPTO_SHA1=y -# CONFIG_CRYPTO_SHA1_SSSE3 is not set -# CONFIG_CRYPTO_SHA256_SSSE3 is not set -# CONFIG_CRYPTO_SHA512_SSSE3 is not set -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_SHA512=y -# CONFIG_CRYPTO_SHA3 is not set -# CONFIG_CRYPTO_SM3 is not set -# CONFIG_CRYPTO_STREEBOG is not set -# CONFIG_CRYPTO_WP512 is not set -# CONFIG_CRYPTO_GHASH_CLMUL_NI_INTEL is not set - -# -# Ciphers -# -CONFIG_CRYPTO_AES=y -# CONFIG_CRYPTO_AES_TI is not set -# CONFIG_CRYPTO_AES_NI_INTEL is not set -# CONFIG_CRYPTO_BLOWFISH is not set -# CONFIG_CRYPTO_BLOWFISH_X86_64 is not set -# CONFIG_CRYPTO_CAMELLIA is not set -# CONFIG_CRYPTO_CAMELLIA_X86_64 is not set -# CONFIG_CRYPTO_CAMELLIA_AESNI_AVX_X86_64 is not set -# CONFIG_CRYPTO_CAMELLIA_AESNI_AVX2_X86_64 is not set -# CONFIG_CRYPTO_CAST5 is not set -# CONFIG_CRYPTO_CAST5_AVX_X86_64 is not set -# CONFIG_CRYPTO_CAST6 is not set -# CONFIG_CRYPTO_CAST6_AVX_X86_64 is not set CONFIG_CRYPTO_DES=y -# CONFIG_CRYPTO_DES3_EDE_X86_64 is not set -# CONFIG_CRYPTO_FCRYPT is not set -# CONFIG_CRYPTO_CHACHA20 is not set -# CONFIG_CRYPTO_CHACHA20_X86_64 is not set -# CONFIG_CRYPTO_SERPENT is not set -# CONFIG_CRYPTO_SERPENT_SSE2_X86_64 is not set -# CONFIG_CRYPTO_SERPENT_AVX_X86_64 is not set -# CONFIG_CRYPTO_SERPENT_AVX2_X86_64 is not set -# CONFIG_CRYPTO_SM4 is not set -# CONFIG_CRYPTO_TWOFISH is not set -# CONFIG_CRYPTO_TWOFISH_X86_64 is not set -# CONFIG_CRYPTO_TWOFISH_X86_64_3WAY is not set -# CONFIG_CRYPTO_TWOFISH_AVX_X86_64 is not set - -# -# Compression -# -CONFIG_CRYPTO_DEFLATE=y -CONFIG_CRYPTO_LZO=y -# CONFIG_CRYPTO_842 is not set -# CONFIG_CRYPTO_LZ4 is not set -# CONFIG_CRYPTO_LZ4HC is not set -# CONFIG_CRYPTO_ZSTD is not set - -# -# Random Number Generation -# -# CONFIG_CRYPTO_ANSI_CPRNG is not set -CONFIG_CRYPTO_DRBG_MENU=y -CONFIG_CRYPTO_DRBG_HMAC=y -# CONFIG_CRYPTO_DRBG_HASH is not set -# CONFIG_CRYPTO_DRBG_CTR is not set -CONFIG_CRYPTO_DRBG=y -CONFIG_CRYPTO_JITTERENTROPY=y -# CONFIG_CRYPTO_USER_API_HASH is not set -# CONFIG_CRYPTO_USER_API_SKCIPHER is not set -# CONFIG_CRYPTO_USER_API_RNG is not set -# CONFIG_CRYPTO_USER_API_AEAD is not set -CONFIG_CRYPTO_HASH_INFO=y - -# -# Crypto library routines -# -CONFIG_CRYPTO_LIB_AES=y -CONFIG_CRYPTO_LIB_ARC4=y -# CONFIG_CRYPTO_LIB_BLAKE2S is not set -# CONFIG_CRYPTO_LIB_CHACHA is not set -# CONFIG_CRYPTO_LIB_CURVE25519 is not set -CONFIG_CRYPTO_LIB_DES=y -CONFIG_CRYPTO_LIB_POLY1305_RSIZE=11 -# CONFIG_CRYPTO_LIB_POLY1305 is not set -# CONFIG_CRYPTO_LIB_CHACHA20POLY1305 is not set -CONFIG_CRYPTO_LIB_SHA256=y -CONFIG_CRYPTO_HW=y -# CONFIG_CRYPTO_DEV_PADLOCK is not set -# CONFIG_CRYPTO_DEV_ATMEL_ECC is not set -# CONFIG_CRYPTO_DEV_ATMEL_SHA204A is not set -# CONFIG_CRYPTO_DEV_CCP is not set -# CONFIG_CRYPTO_DEV_QAT_DH895xCC is not set -# CONFIG_CRYPTO_DEV_QAT_C3XXX is not set -# CONFIG_CRYPTO_DEV_QAT_C62X is not set -# CONFIG_CRYPTO_DEV_QAT_4XXX is not set -# CONFIG_CRYPTO_DEV_QAT_DH895xCCVF is not set -# CONFIG_CRYPTO_DEV_QAT_C3XXXVF is not set -# CONFIG_CRYPTO_DEV_QAT_C62XVF is not set -# CONFIG_CRYPTO_DEV_NITROX_CNN55XX is not set -# CONFIG_CRYPTO_DEV_SAFEXCEL is not set -# CONFIG_CRYPTO_DEV_AMLOGIC_GXL is not set -CONFIG_ASYMMETRIC_KEY_TYPE=y -CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y -CONFIG_X509_CERTIFICATE_PARSER=y -# CONFIG_PKCS8_PRIVATE_KEY_PARSER is not set -CONFIG_PKCS7_MESSAGE_PARSER=y -# CONFIG_PKCS7_TEST_KEY is not set -# CONFIG_SIGNED_PE_FILE_VERIFICATION is not set - -# -# Certificates for signature checking -# -CONFIG_MODULE_SIG_KEY="certs/signing_key.pem" -CONFIG_SYSTEM_TRUSTED_KEYRING=y -CONFIG_SYSTEM_TRUSTED_KEYS="" -# CONFIG_SYSTEM_EXTRA_CERTIFICATE is not set -# CONFIG_SECONDARY_TRUSTED_KEYRING is not set -# CONFIG_SYSTEM_BLACKLIST_KEYRING is not set -# end of Certificates for signature checking - -CONFIG_BINARY_PRINTF=y - -# -# Library routines -# -# CONFIG_PACKING is not set -CONFIG_BITREVERSE=y -CONFIG_GENERIC_STRNCPY_FROM_USER=y -CONFIG_GENERIC_STRNLEN_USER=y -CONFIG_GENERIC_NET_UTILS=y -CONFIG_GENERIC_FIND_FIRST_BIT=y -# CONFIG_CORDIC is not set -# CONFIG_PRIME_NUMBERS is not set -CONFIG_RATIONAL=y -CONFIG_GENERIC_PCI_IOMAP=y -CONFIG_GENERIC_IOMAP=y -CONFIG_ARCH_USE_CMPXCHG_LOCKREF=y -CONFIG_ARCH_HAS_FAST_MULTIPLIER=y -CONFIG_ARCH_USE_SYM_ANNOTATIONS=y -CONFIG_CRC_CCITT=y -CONFIG_CRC16=y -CONFIG_CRC_T10DIF=y -# CONFIG_CRC_ITU_T is not set -CONFIG_CRC32=y -# CONFIG_CRC32_SELFTEST is not set -CONFIG_CRC32_SLICEBY8=y -# CONFIG_CRC32_SLICEBY4 is not set -# CONFIG_CRC32_SARWATE is not set -# CONFIG_CRC32_BIT is not set -# CONFIG_CRC64 is not set -# CONFIG_CRC4 is not set -# CONFIG_CRC7 is not set -CONFIG_LIBCRC32C=y -# CONFIG_CRC8 is not set -CONFIG_XXHASH=y -# CONFIG_RANDOM32_SELFTEST is not set -CONFIG_ZLIB_INFLATE=y -CONFIG_ZLIB_DEFLATE=y -CONFIG_LZO_COMPRESS=y -CONFIG_LZO_DECOMPRESS=y -CONFIG_LZ4_DECOMPRESS=y -CONFIG_ZSTD_DECOMPRESS=y -CONFIG_XZ_DEC=y -CONFIG_XZ_DEC_X86=y -CONFIG_XZ_DEC_POWERPC=y -CONFIG_XZ_DEC_IA64=y -CONFIG_XZ_DEC_ARM=y -CONFIG_XZ_DEC_ARMTHUMB=y -CONFIG_XZ_DEC_SPARC=y -CONFIG_XZ_DEC_BCJ=y -# CONFIG_XZ_DEC_TEST is not set -CONFIG_DECOMPRESS_GZIP=y -CONFIG_DECOMPRESS_BZIP2=y -CONFIG_DECOMPRESS_LZMA=y -CONFIG_DECOMPRESS_XZ=y -CONFIG_DECOMPRESS_LZO=y -CONFIG_DECOMPRESS_LZ4=y -CONFIG_DECOMPRESS_ZSTD=y -CONFIG_GENERIC_ALLOCATOR=y -CONFIG_TEXTSEARCH=y -CONFIG_TEXTSEARCH_KMP=m -CONFIG_TEXTSEARCH_BM=m -CONFIG_TEXTSEARCH_FSM=m -CONFIG_INTERVAL_TREE=y -CONFIG_XARRAY_MULTI=y -CONFIG_ASSOCIATIVE_ARRAY=y -CONFIG_HAS_IOMEM=y -CONFIG_HAS_IOPORT_MAP=y -CONFIG_HAS_DMA=y -CONFIG_DMA_OPS=y -CONFIG_NEED_SG_DMA_LENGTH=y -CONFIG_NEED_DMA_MAP_STATE=y -CONFIG_ARCH_DMA_ADDR_T_64BIT=y -CONFIG_SWIOTLB=y -# CONFIG_DMA_CMA is not set -# CONFIG_DMA_API_DEBUG is not set -# CONFIG_DMA_MAP_BENCHMARK is not set -CONFIG_SGL_ALLOC=y -CONFIG_IOMMU_HELPER=y -CONFIG_CHECK_SIGNATURE=y -CONFIG_CPU_RMAP=y -CONFIG_DQL=y -CONFIG_GLOB=y -# CONFIG_GLOB_SELFTEST is not set -CONFIG_NLATTR=y -CONFIG_CLZ_TAB=y -# CONFIG_IRQ_POLL is not set -CONFIG_MPILIB=y -CONFIG_OID_REGISTRY=y -CONFIG_UCS2_STRING=y -CONFIG_HAVE_GENERIC_VDSO=y -CONFIG_GENERIC_GETTIMEOFDAY=y -CONFIG_GENERIC_VDSO_TIME_NS=y -CONFIG_FONT_SUPPORT=y -# CONFIG_FONTS is not set -CONFIG_FONT_8x8=y -CONFIG_FONT_8x16=y -CONFIG_SG_POOL=y -CONFIG_ARCH_HAS_PMEM_API=y -CONFIG_ARCH_HAS_UACCESS_FLUSHCACHE=y -CONFIG_ARCH_HAS_COPY_MC=y -CONFIG_ARCH_STACKWALK=y -CONFIG_SBITMAP=y -# CONFIG_STRING_SELFTEST is not set -# end of Library routines - -# -# Kernel hacking -# - -# -# printk and dmesg options -# CONFIG_PRINTK_TIME=y -# CONFIG_PRINTK_CALLER is not set -CONFIG_CONSOLE_LOGLEVEL_DEFAULT=7 -CONFIG_CONSOLE_LOGLEVEL_QUIET=4 -CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4 -# CONFIG_BOOT_PRINTK_DELAY is not set CONFIG_DYNAMIC_DEBUG=y -CONFIG_DYNAMIC_DEBUG_CORE=y -CONFIG_SYMBOLIC_ERRNAME=y -CONFIG_DEBUG_BUGVERBOSE=y -# end of printk and dmesg options - -# -# Compile-time checks and compiler options -# -# CONFIG_DEBUG_INFO is not set -CONFIG_FRAME_WARN=2048 -# CONFIG_STRIP_ASM_SYMS is not set -# CONFIG_READABLE_ASM is not set -# CONFIG_HEADERS_INSTALL is not set -# CONFIG_DEBUG_SECTION_MISMATCH is not set -CONFIG_SECTION_MISMATCH_WARN_ONLY=y -# CONFIG_DEBUG_FORCE_FUNCTION_ALIGN_32B is not set -CONFIG_STACK_VALIDATION=y -# CONFIG_VMLINUX_MAP is not set -# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set -# end of Compile-time checks and compiler options - -# -# Generic Kernel Debugging Instruments -# -CONFIG_MAGIC_SYSRQ=y -CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x1 -CONFIG_MAGIC_SYSRQ_SERIAL=y -CONFIG_MAGIC_SYSRQ_SERIAL_SEQUENCE="" -CONFIG_DEBUG_FS=y -CONFIG_DEBUG_FS_ALLOW_ALL=y -# CONFIG_DEBUG_FS_DISALLOW_MOUNT is not set -# CONFIG_DEBUG_FS_ALLOW_NONE is not set -CONFIG_HAVE_ARCH_KGDB=y CONFIG_KGDB=y -CONFIG_KGDB_HONOUR_BLOCKLIST=y -CONFIG_KGDB_SERIAL_CONSOLE=y -# CONFIG_KGDB_TESTS is not set CONFIG_KGDB_LOW_LEVEL_TRAP=y CONFIG_KGDB_KDB=y -CONFIG_KDB_DEFAULT_ENABLE=0x1 CONFIG_KDB_KEYBOARD=y -CONFIG_KDB_CONTINUE_CATASTROPHIC=0 -CONFIG_ARCH_HAS_EARLY_DEBUG=y -CONFIG_ARCH_HAS_UBSAN_SANITIZE_ALL=y -# CONFIG_UBSAN is not set -CONFIG_HAVE_ARCH_KCSAN=y -# end of Generic Kernel Debugging Instruments - -CONFIG_DEBUG_KERNEL=y -CONFIG_DEBUG_MISC=y - -# -# Memory Debugging -# -# CONFIG_PAGE_EXTENSION is not set -# CONFIG_DEBUG_PAGEALLOC is not set -# CONFIG_PAGE_OWNER is not set -# CONFIG_PAGE_POISONING is not set -# CONFIG_DEBUG_PAGE_REF is not set CONFIG_DEBUG_RODATA_TEST=y -CONFIG_ARCH_HAS_DEBUG_WX=y -# CONFIG_DEBUG_WX is not set -CONFIG_GENERIC_PTDUMP=y -# CONFIG_PTDUMP_DEBUGFS is not set -# CONFIG_DEBUG_OBJECTS is not set -# CONFIG_SLUB_DEBUG_ON is not set -# CONFIG_SLUB_STATS is not set -CONFIG_HAVE_DEBUG_KMEMLEAK=y CONFIG_DEBUG_KMEMLEAK=y -CONFIG_DEBUG_KMEMLEAK_MEM_POOL_SIZE=16000 -# CONFIG_DEBUG_KMEMLEAK_TEST is not set CONFIG_DEBUG_KMEMLEAK_DEFAULT_OFF=y -CONFIG_DEBUG_KMEMLEAK_AUTO_SCAN=y -# CONFIG_DEBUG_STACK_USAGE is not set CONFIG_SCHED_STACK_END_CHECK=y -CONFIG_ARCH_HAS_DEBUG_VM_PGTABLE=y -# CONFIG_DEBUG_VM is not set -# CONFIG_DEBUG_VM_PGTABLE is not set -CONFIG_ARCH_HAS_DEBUG_VIRTUAL=y -# CONFIG_DEBUG_VIRTUAL is not set -# CONFIG_DEBUG_MEMORY_INIT is not set -# CONFIG_DEBUG_PER_CPU_MAPS is not set -CONFIG_ARCH_SUPPORTS_KMAP_LOCAL_FORCE_MAP=y -# CONFIG_DEBUG_KMAP_LOCAL_FORCE_MAP is not set -CONFIG_HAVE_ARCH_KASAN=y -CONFIG_HAVE_ARCH_KASAN_VMALLOC=y -CONFIG_CC_HAS_KASAN_GENERIC=y -CONFIG_HAVE_ARCH_KFENCE=y -# CONFIG_KFENCE is not set -# end of Memory Debugging - CONFIG_DEBUG_SHIRQ=y - -# -# Debug Oops, Lockups and Hangs -# -# CONFIG_PANIC_ON_OOPS is not set -CONFIG_PANIC_ON_OOPS_VALUE=0 -CONFIG_PANIC_TIMEOUT=0 -CONFIG_LOCKUP_DETECTOR=y -CONFIG_SOFTLOCKUP_DETECTOR=y -# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set -CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0 -CONFIG_HARDLOCKUP_DETECTOR_PERF=y -CONFIG_HARDLOCKUP_CHECK_TIMESTAMP=y CONFIG_HARDLOCKUP_DETECTOR=y -# CONFIG_BOOTPARAM_HARDLOCKUP_PANIC is not set -CONFIG_BOOTPARAM_HARDLOCKUP_PANIC_VALUE=0 -CONFIG_DETECT_HUNG_TASK=y -CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=120 -# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set -CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 -# CONFIG_WQ_WATCHDOG is not set -# CONFIG_TEST_LOCKUP is not set -# end of Debug Oops, Lockups and Hangs - -# -# Scheduler Debugging -# -CONFIG_SCHED_DEBUG=y -CONFIG_SCHED_INFO=y CONFIG_SCHEDSTATS=y -# end of Scheduler Debugging - -# CONFIG_DEBUG_TIMEKEEPING is not set - -# -# Lock Debugging (spinlocks, mutexes, etc...) -# -CONFIG_LOCK_DEBUGGING_SUPPORT=y CONFIG_PROVE_LOCKING=y -# CONFIG_PROVE_RAW_LOCK_NESTING is not set -# CONFIG_LOCK_STAT is not set -CONFIG_DEBUG_RT_MUTEXES=y -CONFIG_DEBUG_SPINLOCK=y -CONFIG_DEBUG_MUTEXES=y -CONFIG_DEBUG_WW_MUTEX_SLOWPATH=y -CONFIG_DEBUG_RWSEMS=y -CONFIG_DEBUG_LOCK_ALLOC=y -CONFIG_LOCKDEP=y -CONFIG_LOCKDEP_BITS=15 -CONFIG_LOCKDEP_CHAINS_BITS=16 -CONFIG_LOCKDEP_STACK_TRACE_BITS=19 -CONFIG_LOCKDEP_STACK_TRACE_HASH_BITS=14 -CONFIG_LOCKDEP_CIRCULAR_QUEUE_BITS=12 -# CONFIG_DEBUG_LOCKDEP is not set CONFIG_DEBUG_ATOMIC_SLEEP=y -# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set -# CONFIG_LOCK_TORTURE_TEST is not set -# CONFIG_WW_MUTEX_SELFTEST is not set -# CONFIG_SCF_TORTURE_TEST is not set -# CONFIG_CSD_LOCK_WAIT_DEBUG is not set -# end of Lock Debugging (spinlocks, mutexes, etc...) - -CONFIG_TRACE_IRQFLAGS=y -CONFIG_TRACE_IRQFLAGS_NMI=y -# CONFIG_DEBUG_IRQFLAGS is not set -CONFIG_STACKTRACE=y -# CONFIG_WARN_ALL_UNSEEDED_RANDOM is not set -# CONFIG_DEBUG_KOBJECT is not set - -# -# Debug kernel data structures -# -# CONFIG_DEBUG_LIST is not set -# CONFIG_DEBUG_PLIST is not set -# CONFIG_DEBUG_SG is not set -# CONFIG_DEBUG_NOTIFIERS is not set -# CONFIG_BUG_ON_DATA_CORRUPTION is not set -# end of Debug kernel data structures - -# CONFIG_DEBUG_CREDENTIALS is not set - -# -# RCU Debugging -# -CONFIG_PROVE_RCU=y -# CONFIG_RCU_SCALE_TEST is not set -# CONFIG_RCU_TORTURE_TEST is not set -# CONFIG_RCU_REF_SCALE_TEST is not set CONFIG_RCU_CPU_STALL_TIMEOUT=60 # CONFIG_RCU_TRACE is not set -# CONFIG_RCU_EQS_DEBUG is not set -# end of RCU Debugging - -# CONFIG_DEBUG_WQ_FORCE_RR_CPU is not set -# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set -# CONFIG_CPU_HOTPLUG_STATE_CONTROL is not set -# CONFIG_LATENCYTOP is not set -CONFIG_USER_STACKTRACE_SUPPORT=y -CONFIG_NOP_TRACER=y -CONFIG_HAVE_FUNCTION_TRACER=y -CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y -CONFIG_HAVE_DYNAMIC_FTRACE=y -CONFIG_HAVE_DYNAMIC_FTRACE_WITH_REGS=y -CONFIG_HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS=y -CONFIG_HAVE_DYNAMIC_FTRACE_WITH_ARGS=y -CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y -CONFIG_HAVE_SYSCALL_TRACEPOINTS=y -CONFIG_HAVE_FENTRY=y -CONFIG_HAVE_OBJTOOL_MCOUNT=y -CONFIG_HAVE_C_RECORDMCOUNT=y -CONFIG_TRACER_MAX_TRACE=y -CONFIG_TRACE_CLOCK=y -CONFIG_RING_BUFFER=y -CONFIG_EVENT_TRACING=y -CONFIG_CONTEXT_SWITCH_TRACER=y -CONFIG_PREEMPTIRQ_TRACEPOINTS=y -CONFIG_TRACING=y -CONFIG_GENERIC_TRACER=y -CONFIG_TRACING_SUPPORT=y -CONFIG_FTRACE=y -# CONFIG_BOOTTIME_TRACING is not set -CONFIG_FUNCTION_TRACER=y -CONFIG_FUNCTION_GRAPH_TRACER=y -CONFIG_DYNAMIC_FTRACE=y -CONFIG_DYNAMIC_FTRACE_WITH_REGS=y -CONFIG_DYNAMIC_FTRACE_WITH_DIRECT_CALLS=y CONFIG_FUNCTION_PROFILER=y CONFIG_STACK_TRACER=y -# CONFIG_IRQSOFF_TRACER is not set CONFIG_SCHED_TRACER=y CONFIG_HWLAT_TRACER=y CONFIG_MMIOTRACE=y CONFIG_FTRACE_SYSCALLS=y -CONFIG_TRACER_SNAPSHOT=y -# CONFIG_TRACER_SNAPSHOT_PER_CPU_SWAP is not set -CONFIG_BRANCH_PROFILE_NONE=y -# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set -# CONFIG_PROFILE_ALL_BRANCHES is not set CONFIG_BLK_DEV_IO_TRACE=y -CONFIG_KPROBE_EVENTS=y -# CONFIG_KPROBE_EVENTS_ON_NOTRACE is not set -CONFIG_UPROBE_EVENTS=y -CONFIG_BPF_EVENTS=y -CONFIG_DYNAMIC_EVENTS=y -CONFIG_PROBE_EVENTS=y -# CONFIG_BPF_KPROBE_OVERRIDE is not set -CONFIG_FTRACE_MCOUNT_RECORD=y -CONFIG_FTRACE_MCOUNT_USE_CC=y -CONFIG_TRACING_MAP=y -CONFIG_SYNTH_EVENTS=y CONFIG_HIST_TRIGGERS=y -# CONFIG_TRACE_EVENT_INJECT is not set -# CONFIG_TRACEPOINT_BENCHMARK is not set -# CONFIG_RING_BUFFER_BENCHMARK is not set -# CONFIG_TRACE_EVAL_MAP_FILE is not set -# CONFIG_FTRACE_RECORD_RECURSION is not set -# CONFIG_FTRACE_STARTUP_TEST is not set -# CONFIG_RING_BUFFER_STARTUP_TEST is not set -# CONFIG_RING_BUFFER_VALIDATE_TIME_DELTAS is not set -# CONFIG_MMIOTRACE_TEST is not set -# CONFIG_PREEMPTIRQ_DELAY_TEST is not set -# CONFIG_SYNTH_EVENT_GEN_TEST is not set -# CONFIG_KPROBE_EVENT_GEN_TEST is not set -# CONFIG_HIST_TRIGGERS_DEBUG is not set -# CONFIG_PROVIDE_OHCI1394_DMA_INIT is not set -# CONFIG_SAMPLES is not set -CONFIG_ARCH_HAS_DEVMEM_IS_ALLOWED=y # CONFIG_STRICT_DEVMEM is not set - -# -# x86 Debugging -# -CONFIG_TRACE_IRQFLAGS_SUPPORT=y -CONFIG_TRACE_IRQFLAGS_NMI_SUPPORT=y # CONFIG_X86_VERBOSE_BOOTUP is not set -CONFIG_EARLY_PRINTK=y -# CONFIG_EARLY_PRINTK_DBGP is not set -# CONFIG_EARLY_PRINTK_USB_XDBC is not set -# CONFIG_EFI_PGT_DUMP is not set -# CONFIG_DEBUG_TLBFLUSH is not set -# CONFIG_IOMMU_DEBUG is not set -CONFIG_HAVE_MMIOTRACE_SUPPORT=y -# CONFIG_X86_DECODER_SELFTEST is not set -# CONFIG_IO_DELAY_0X80 is not set CONFIG_IO_DELAY_0XED=y -# CONFIG_IO_DELAY_UDELAY is not set -# CONFIG_IO_DELAY_NONE is not set -# CONFIG_DEBUG_BOOT_PARAMS is not set -# CONFIG_CPA_DEBUG is not set -# CONFIG_DEBUG_ENTRY is not set -# CONFIG_DEBUG_NMI_SELFTEST is not set -CONFIG_X86_DEBUG_FPU=y -# CONFIG_PUNIT_ATOM_DEBUG is not set -CONFIG_UNWINDER_ORC=y -# CONFIG_UNWINDER_FRAME_POINTER is not set -# CONFIG_UNWINDER_GUESS is not set -# end of x86 Debugging - -# -# Kernel Testing and Coverage -# -# CONFIG_KUNIT is not set -# CONFIG_NOTIFIER_ERROR_INJECTION is not set -CONFIG_FUNCTION_ERROR_INJECTION=y -# CONFIG_FAULT_INJECTION is not set -CONFIG_ARCH_HAS_KCOV=y -CONFIG_CC_HAS_SANCOV_TRACE_PC=y -# CONFIG_KCOV is not set # CONFIG_RUNTIME_TESTING_MENU is not set -CONFIG_ARCH_USE_MEMTEST=y CONFIG_MEMTEST=y -# end of Kernel Testing and Coverage -# end of Kernel hacking From 6cdd6f1ccf5f069d256aae88db877f88226a4e97 Mon Sep 17 00:00:00 2001 From: Ramesh Errabolu Date: Wed, 29 Jun 2022 12:43:19 -0500 Subject: [PATCH 0008/1868] x86/configs: Update defconfig with peer-to-peer configs - Update defconfig for PCI_P2PDMA - Update defconfig for DMABUF_MOVE_NOTIFY - Update defconfig for HSA_AMD_P2P Signed-off-by: Ramesh Errabolu Reviewed-by: Felix Kuehling Signed-off-by: Alex Deucher --- arch/x86/configs/rock-dbg_defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/x86/configs/rock-dbg_defconfig b/arch/x86/configs/rock-dbg_defconfig index 406fdfaceb550..0ad80a8c8eab0 100644 --- a/arch/x86/configs/rock-dbg_defconfig +++ b/arch/x86/configs/rock-dbg_defconfig @@ -303,6 +303,7 @@ CONFIG_PCIEAER=y CONFIG_PCI_REALLOC_ENABLE_AUTO=y CONFIG_PCI_STUB=y CONFIG_PCI_IOV=y +CONFIG_PCI_P2PDMA=y CONFIG_HOTPLUG_PCI=y CONFIG_RAPIDIO=y CONFIG_RAPIDIO_DMA_ENGINE=y @@ -417,6 +418,7 @@ CONFIG_DRM_AMDGPU=m CONFIG_DRM_AMDGPU_SI=y CONFIG_DRM_AMDGPU_CIK=y CONFIG_HSA_AMD=y +CONFIG_HSA_AMD_P2P=y CONFIG_DRM_AST=m CONFIG_FB=y CONFIG_BACKLIGHT_CLASS_DEVICE=y @@ -453,6 +455,7 @@ CONFIG_LEDS_TRIGGERS=y CONFIG_RTC_CLASS=y # CONFIG_RTC_HCTOSYS is not set CONFIG_DMADEVICES=y +CONFIG_DMABUF_MOVE_NOTIFY=y # CONFIG_X86_PLATFORM_DEVICES is not set CONFIG_AMD_IOMMU=y CONFIG_INTEL_IOMMU=y From e365cccabe04722a4869baf8cb8fb6ef5935ba0c Mon Sep 17 00:00:00 2001 From: Rajneesh Bhardwaj Date: Mon, 8 Jul 2024 12:06:36 -0400 Subject: [PATCH 0009/1868] drm/ttm: Allow direct reclaim to allocate local memory v2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Limiting the allocation of higher order pages to the closest NUMA node and enabling direct memory reclaim provides not only failsafe against situations when memory becomes too much fragmented and the allocator is not able to satisfy the request from the local node but falls back to remote pages (HUGEPAGE) but also offers performance improvement. Accessing remote pages suffers due to bandwidth limitations and could be avoided if memory becomes defragmented and in most cases without using manual compaction. (/proc/sys/vm/compact_memory) Note: On certain distros such as RHEL, the proactive compaction is disabled. (https://tinyurl.com/4f32f7rs) v2 (chk): drop __GFP_RECLAIM since that is already set by GFP_USER Cc: Dave Airlie Cc: Vlastimil Babka Cc: Daniel Vetter Reviewed-by: Christian König Signed-off-by: Rajneesh Bhardwaj Link: https://patchwork.freedesktop.org/patch/msgid/20240708160636.1147308-1-rajneesh.bhardwaj@amd.com Signed-off-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/ttm/ttm_pool.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/ttm/ttm_pool.c b/drivers/gpu/drm/ttm/ttm_pool.c index 6e1fd6985ffcb..8504dbe19c1a0 100644 --- a/drivers/gpu/drm/ttm/ttm_pool.c +++ b/drivers/gpu/drm/ttm/ttm_pool.c @@ -91,7 +91,7 @@ static struct page *ttm_pool_alloc_page(struct ttm_pool *pool, gfp_t gfp_flags, */ if (order) gfp_flags |= __GFP_NOMEMALLOC | __GFP_NORETRY | __GFP_NOWARN | - __GFP_KSWAPD_RECLAIM; + __GFP_THISNODE; if (!pool->use_dma_alloc) { p = alloc_pages_node(pool->nid, gfp_flags, order); From 089b28bfa5340f5435f7e9854f64d7de86262d86 Mon Sep 17 00:00:00 2001 From: Junwei Zhang Date: Wed, 13 Nov 2019 11:12:23 +0800 Subject: [PATCH 0010/1868] drm/amdkcl: add dkms support It's a squash of 6a2ef7359800 drm/amdkcl: fix include path in schduler 6d5954b6cff6 drm/amdkcl: describe the 'sources' file format 5579697e0041 drm/amdkcl: update sources file 3f3db2b92b63 drm/amdkcl: properly define and initialize Makefile variables d96876c7258e drm/amdkcl: cleanup LINUXINCLUDE in dkms package fdc3c5d4df0e drm/amdkcl: add dkms support Signed-off-by: Junwei Zhang Signed-off-by: Adam Yang Reviewed-by: Qiang Yu Reviewed-by: Flora Cui Signed-off-by: Flora Cui Reviewed-by: Yang Xiong Signed-off-by: Slava Grigorev Acked-by: Jonathan Kim Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/symbols | 1 + drivers/gpu/drm/amd/dkms/Makefile | 23 +++++++++++++ drivers/gpu/drm/amd/dkms/dkms.conf | 40 ++++++++++++++++++++++ drivers/gpu/drm/amd/dkms/pre-build.sh | 48 +++++++++++++++++++++++++++ drivers/gpu/drm/amd/dkms/sources | 26 +++++++++++++++ 5 files changed, 138 insertions(+) create mode 100644 drivers/gpu/drm/amd/amdkcl/symbols create mode 100644 drivers/gpu/drm/amd/dkms/Makefile create mode 100644 drivers/gpu/drm/amd/dkms/dkms.conf create mode 100755 drivers/gpu/drm/amd/dkms/pre-build.sh create mode 100644 drivers/gpu/drm/amd/dkms/sources diff --git a/drivers/gpu/drm/amd/amdkcl/symbols b/drivers/gpu/drm/amd/amdkcl/symbols new file mode 100644 index 0000000000000..fe167314985be --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/symbols @@ -0,0 +1 @@ +SYMS="" diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile new file mode 100644 index 0000000000000..f5d9b8d250ed6 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -0,0 +1,23 @@ +LINUXINCLUDE := \ + -I$(src)/include \ + -I$(src)/include/uapi \ + -include $(src)/include/kcl/kcl_version.h \ + -include $(src)/include/rename_symbol.h \ + $(LINUXINCLUDE) + +export CONFIG_DRM_TTM=m +export CONFIG_DRM_AMDGPU=m +export CONFIG_DRM_SCHED=m +export CONFIG_DRM_AMDGPU_CIK=y +export CONFIG_DRM_AMDGPU_SI=y +export CONFIG_DRM_AMDGPU_USERPTR=y +export CONFIG_DRM_AMD_DC=y +export CONFIG_DRM_AMD_DC_DCN1_0=y + +subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_CIK +subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_SI +subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_USERPTR +subdir-ccflags-y += -DCONFIG_DRM_AMD_DC +subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN1_0 + +obj-m += scheduler/ amd/amdgpu/ ttm/ amd/amdkcl/ diff --git a/drivers/gpu/drm/amd/dkms/dkms.conf b/drivers/gpu/drm/amd/dkms/dkms.conf new file mode 100644 index 0000000000000..e9e8db1bdd64e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/dkms.conf @@ -0,0 +1,40 @@ +PACKAGE_NAME="amdgpu" +PACKAGE_VERSION="1.0" +AUTOINSTALL="yes" +REMAKE_INITRD="yes" +PRE_BUILD="pre-build.sh $kernelver" + +# not work with RHEL DKMS +#MODULES_CONF[0]="blacklist radeon" + +BUILT_MODULE_NAME[0]="amdgpu" +BUILT_MODULE_LOCATION[0]="amd/amdgpu" +DEST_MODULE_LOCATION[0]="/updates" + +BUILT_MODULE_NAME[1]="amdttm" +BUILT_MODULE_LOCATION[1]="ttm" +DEST_MODULE_LOCATION[1]="/updates" + +BUILT_MODULE_NAME[2]="amdkcl" +BUILT_MODULE_LOCATION[2]="amd/amdkcl" +DEST_MODULE_LOCATION[2]="/updates" + +BUILT_MODULE_NAME[3]="amd-sched" +BUILT_MODULE_LOCATION[3]="scheduler" +DEST_MODULE_LOCATION[3]="/updates" + +# Find out how many CPU cores can be use if we pass appropriate -j option to make. +# DKMS could use all cores on multicore systems to build the kernel module. +num_cpu_cores() +{ + if [ -x /usr/bin/nproc ]; then + nproc + else + echo "1" + fi +} + +MAKE[0]="make -j$(num_cpu_cores) TTM_NAME=${BUILT_MODULE_NAME[1]} \ + SCHED_NAME=${BUILT_MODULE_NAME[3]} \ + -C $kernel_source_dir \ + M=$dkms_tree/$module/$module_version/build" diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh new file mode 100755 index 0000000000000..72929ce8ae064 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -0,0 +1,48 @@ +#!/bin/bash + +KCL="amd/amdkcl" +INC="include" +SRC="amd/dkms" + +KERNELVER=$1 +KERNELVER_BASE=${KERNELVER%%-*} + +version_lt () { + newest=$((echo "$KERNELVER_BASE"; echo "$1") | sort -V | tail -n1) + [ "$KERNELVER_BASE" != "$newest" ] +} + +version_ge () { + newest=$((echo "$KERNELVER_BASE"; echo "$1") | sort -V | tail -n1) + [ "$KERNELVER_BASE" = "$newest" ] +} + +version_gt () { + oldest=$((echo "$KERNELVER_BASE"; echo "$1") | sort -V | head -n1) + [ "$KERNELVER_BASE" != "$oldest" ] +} + +version_le () { + oldest=$((echo "$KERNELVER_BASE"; echo "$1") | sort -V | head -n1) + [ "$KERNELVER_BASE" = "$oldest" ] +} + +source $KCL/symbols + +# lookup symbol address. obsolete. +echo '// auto generated by DKMS pre-build.sh' > $KCL/symbols.c +for sym in $SYMS; do + addr=$(grep "\<$sym\>" /boot/System.map-$KERNELVER | awk -F' ' '{print $1}') + echo "void *_kcl_$sym = (void *)0x$addr;" >> $KCL/symbols.c +done + +# add amd prefix to exported symbols +find ttm -name '*.c' -exec grep EXPORT_SYMBOL {} + \ + | sort -u \ + | awk -F'[()]' '{print "#define "$2" amd"$2" //"$0}'\ + >> $INC/rename_symbol.h + +find scheduler -name '*.c' -exec grep EXPORT_SYMBOL {} + \ + | sort -u \ + | awk -F'[()]' '{print "#define "$2" amd"$2" //"$0}'\ + >> $INC/rename_symbol.h diff --git a/drivers/gpu/drm/amd/dkms/sources b/drivers/gpu/drm/amd/dkms/sources new file mode 100644 index 0000000000000..b8f2af052e55a --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/sources @@ -0,0 +1,26 @@ +# +# The 'sources' file contains source/destination directives to be used +# by the build framework to construct the DKMS source tree +# +# File format: +# source destination +# ------ ----------- +# directory[/file] name directory/[file] name +# must exist at the directory: must have explicit directory name +# source path e.g. dir/ (with '/'). The name without +# slash is treated as a file if it does +# not exist +# the directory will be created if it +# does not exist +# file: optional file name at the destination +# +drivers/gpu/drm/amd . +drivers/gpu/drm/ttm . +include/drm/ttm include/drm/ +include/uapi/drm/amdgpu_drm.h include/uapi/drm/ +include/kcl include/ +drivers/gpu/drm/scheduler . +include/drm/gpu_scheduler.h include/drm/ +include/drm/amd_asic_type.h include/drm/ +include/drm/spsc_queue.h include/drm/ +include/uapi/linux/kfd_ioctl.h include/uapi/linux/ From df7d58a3d35c1c9bccfa98ba9b8e20854762e4dc Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Wed, 18 Nov 2020 10:13:46 -0500 Subject: [PATCH 0011/1868] drm/amdkcl:Fix values of DEST_MODULE_LOCATION directives The directive is used for finding original modules and must point to the original module locations. If it points to /updates the original module is placed to /updates after DKMS uninstallation that breaks the /lib/modules/ directory integrity. v2: fix quotation mark typo on dkms.conf. The path string should be enclosed in quotion marks. Signed-off-by: Slava Grigorev Signed-off-by: Rui Teng Reviewed-by: Flora Cui Change-Id: Id48f89a190c0d354147db346a468573775548c9f --- drivers/gpu/drm/amd/dkms/dkms.conf | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/dkms.conf b/drivers/gpu/drm/amd/dkms/dkms.conf index e9e8db1bdd64e..86826daa80072 100644 --- a/drivers/gpu/drm/amd/dkms/dkms.conf +++ b/drivers/gpu/drm/amd/dkms/dkms.conf @@ -9,19 +9,19 @@ PRE_BUILD="pre-build.sh $kernelver" BUILT_MODULE_NAME[0]="amdgpu" BUILT_MODULE_LOCATION[0]="amd/amdgpu" -DEST_MODULE_LOCATION[0]="/updates" +DEST_MODULE_LOCATION[0]="/kernel/drivers/gpu/drm/amd/amdgpu" BUILT_MODULE_NAME[1]="amdttm" BUILT_MODULE_LOCATION[1]="ttm" -DEST_MODULE_LOCATION[1]="/updates" +DEST_MODULE_LOCATION[1]="/kernel/drivers/gpu/drm/ttm" BUILT_MODULE_NAME[2]="amdkcl" BUILT_MODULE_LOCATION[2]="amd/amdkcl" -DEST_MODULE_LOCATION[2]="/updates" +DEST_MODULE_LOCATION[2]="/kernel/drivers/gpu/drm/amd/amdkcl" BUILT_MODULE_NAME[3]="amd-sched" BUILT_MODULE_LOCATION[3]="scheduler" -DEST_MODULE_LOCATION[3]="/updates" +DEST_MODULE_LOCATION[3]="/kernel/drivers/gpu/drm/scheduler" # Find out how many CPU cores can be use if we pass appropriate -j option to make. # DKMS could use all cores on multicore systems to build the kernel module. From 3aec33a1c513fd9e1acd2e8e8894a39e9ba1fd87 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 30 Oct 2019 10:27:35 +0800 Subject: [PATCH 0012/1868] drm/amdkcl: add amdkcl/files to include all files containing EXPORT_SYMBOL to deal with Signed-off-by: Flora Cui Reviewed-by: Kevin Wang --- drivers/gpu/drm/amd/amdkcl/files | 1 + drivers/gpu/drm/amd/dkms/pre-build.sh | 16 +++++++--------- 2 files changed, 8 insertions(+), 9 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/files diff --git a/drivers/gpu/drm/amd/amdkcl/files b/drivers/gpu/drm/amd/amdkcl/files new file mode 100644 index 0000000000000..501b9055ad408 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/files @@ -0,0 +1 @@ +FILES="ttm/*.c scheduler/*.c" diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index 72929ce8ae064..0970ec311e687 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -28,6 +28,7 @@ version_le () { } source $KCL/symbols +source $KCL/files # lookup symbol address. obsolete. echo '// auto generated by DKMS pre-build.sh' > $KCL/symbols.c @@ -37,12 +38,9 @@ for sym in $SYMS; do done # add amd prefix to exported symbols -find ttm -name '*.c' -exec grep EXPORT_SYMBOL {} + \ - | sort -u \ - | awk -F'[()]' '{print "#define "$2" amd"$2" //"$0}'\ - >> $INC/rename_symbol.h - -find scheduler -name '*.c' -exec grep EXPORT_SYMBOL {} + \ - | sort -u \ - | awk -F'[()]' '{print "#define "$2" amd"$2" //"$0}'\ - >> $INC/rename_symbol.h +for file in $FILES; do + grep EXPORT_SYMBOL $file \ + | sort -u \ + | awk -F'[()]' '{print "#define "$2" amd"$2" //"$0}'\ + >> $INC/rename_symbol.h +done From 352236ce7d292148a5543bb43394e3ece294b693 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Mon, 16 Mar 2020 10:55:26 -0400 Subject: [PATCH 0013/1868] amd/amdkcl: simplify pre-build.sh script code Signed-off-by: Slava Grigorev Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/pre-build.sh | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index 0970ec311e687..5e6a61aa8d83e 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -33,14 +33,14 @@ source $KCL/files # lookup symbol address. obsolete. echo '// auto generated by DKMS pre-build.sh' > $KCL/symbols.c for sym in $SYMS; do - addr=$(grep "\<$sym\>" /boot/System.map-$KERNELVER | awk -F' ' '{print $1}') - echo "void *_kcl_$sym = (void *)0x$addr;" >> $KCL/symbols.c + awk -v sym=$sym '/\/ { + print "void *_kcl_" $3 " = (void *)0x" $1 ";" + }' /boot/System.map-$KERNELVER >>$KCL/symbols.c done # add amd prefix to exported symbols for file in $FILES; do - grep EXPORT_SYMBOL $file \ - | sort -u \ - | awk -F'[()]' '{print "#define "$2" amd"$2" //"$0}'\ - >> $INC/rename_symbol.h + awk -F'[()]' '/EXPORT_SYMBOL/ { + print "#define "$2" amd"$2" //"$0 + }' $file | sort -u >>$INC/rename_symbol.h done From 323bc604aefd92c169cf0e476ce81257cc46495f Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 22 Jul 2020 11:10:32 +0800 Subject: [PATCH 0014/1868] drm/amdkcl: rename CONFIG_DRM_xxx & amdgpu configs otherwise kernel config would override dkms package config v2: update ttm/schduler configs, incase ttm/schduler is built-in Signed-off-by: Flora Cui Reviewed-by: Yang Xiong --- drivers/gpu/drm/amd/dkms/pre-build.sh | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index 5e6a61aa8d83e..9fb471b43a708 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -44,3 +44,15 @@ for file in $FILES; do print "#define "$2" amd"$2" //"$0 }' $file | sort -u >>$INC/rename_symbol.h done + +# rename CONFIG_xxx to CONFIG_xxx_AMDKCL +# otherwise kernel config would override dkms package config +AMDGPU_CONFIG=$(find -name Kconfig -exec grep -h '^config' {} + | sed 's/ /_/' | tr 'a-z' 'A-Z') +TTM_CONFIG=$(awk '/CONFIG_DRM/{gsub(".*\\(CONFIG_DRM","CONFIG_DRM");gsub("\\).*","");print $0}' ttm/Makefile) +SCHED_CONFIG=$(awk '/CONFIG_DRM/{gsub(".*\\(CONFIG_DRM","CONFIG_DRM");gsub("\\).*","");print $0}' scheduler/Makefile) +for config in $AMDGPU_CONFIG $TTM_CONFIG $SCHED_CONFIG; do + for file in $(grep -rl $config ./); do + sed -i "s/\<$config\>/&_AMDKCL/" $file + done + sed -i "/${config}$/s/$/_AMDKCL/" amd/dkms/Makefile +done From adbbd7ebadce4b47d1c71499ba94180884b7ee47 Mon Sep 17 00:00:00 2001 From: Junwei Zhang Date: Fri, 23 Dec 2016 14:23:29 +0800 Subject: [PATCH 0015/1868] drm/amdkcl: add backport support for amdgpu v2: drop kcl_amdgpu.o It's a squash of 221c1ea7b3dbd drm/amdkcl: fix license 3f3db2b92b63 drm/amdkcl: properly define and initialize Makefile variables 0275f0fd138c drm/amdkcl: fix out of tree build 383595ad14e1 drm/amdkcl: add backport support for amdgpu Signed-off-by: Junwei Zhang Signed-off-by: Flora Cui Reviewed-by: Qiang Yu Signed-off-by: Qiang Yu Reviewed-by: Junwei Zhang Signed-off-by: Flora Cui Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang Signed-off-by: Slava Grigorev Acked-by: Jonathan Kim Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/Makefile | 2 ++ drivers/gpu/drm/amd/backport/Makefile | 8 ++++++++ drivers/gpu/drm/amd/backport/backport.h | 7 +++++++ 3 files changed, 17 insertions(+) create mode 100644 drivers/gpu/drm/amd/backport/Makefile create mode 100644 drivers/gpu/drm/amd/backport/backport.h diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index 38408e4e158e5..57bd3e788817d 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -332,4 +332,6 @@ amdgpu-y += \ isp_v4_1_1.o endif +include $(FULL_AMD_PATH)/backport/Makefile + obj-$(CONFIG_DRM_AMDGPU)+= amdgpu.o diff --git a/drivers/gpu/drm/amd/backport/Makefile b/drivers/gpu/drm/amd/backport/Makefile new file mode 100644 index 0000000000000..ca667992f6f72 --- /dev/null +++ b/drivers/gpu/drm/amd/backport/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: MIT +BACKPORT_OBJS := + +amdgpu-y += $(addprefix ../backport/,$(BACKPORT_OBJS)) + +ccflags-y += \ + -I$(FULL_AMD_PATH)/backport/include \ + -include ../backport/backport.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h new file mode 100644 index 0000000000000..89cd9143a9c0a --- /dev/null +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef AMDGPU_BACKPORT_H +#define AMDGPU_BACKPORT_H + +#include +#include +#endif /* AMDGPU_BACKPORT_H */ From 97dce7a6213bc9ddf3ab30eff4e7cb2890e158ab Mon Sep 17 00:00:00 2001 From: Junwei Zhang Date: Wed, 13 Nov 2019 11:15:31 +0800 Subject: [PATCH 0016/1868] drm/amdkcl: add backport support for scheduler It's a squash of 6a2ef7359800 drm/amdkcl: fix include path in schduler 221c1ea7b3dbd drm/amdkcl: fix license 6e5bc9b8e7ea amd/amdkcl: drop use of BUILD_AS_DKMS in Makefile files 3f3db2b92b63 drm/amdkcl: properly define and initialize Makefile variables de12801935af drm/amdkcl: add backport support for scheduler Signed-off-by: Le.Ma Reviewed-by: Qiang Yu Signed-off-by: Flora Cui Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang Signed-off-by: Slava Grigorev Acked-by: Jonathan Kim Reviewed-by: Flora Cui Signed-off-by: Slava Grigorev Reviewed-by: Flora Cui Signed-off-by: Flora Cui Reviewed-by: Yang Xiong --- drivers/gpu/drm/scheduler/Makefile | 16 ++++++++++++++-- drivers/gpu/drm/scheduler/backport/Makefile | 4 ++++ drivers/gpu/drm/scheduler/backport/backport.h | 7 +++++++ 3 files changed, 25 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/scheduler/backport/Makefile create mode 100644 drivers/gpu/drm/scheduler/backport/backport.h diff --git a/drivers/gpu/drm/scheduler/Makefile b/drivers/gpu/drm/scheduler/Makefile index 53863621829f1..1ccff60ee9710 100644 --- a/drivers/gpu/drm/scheduler/Makefile +++ b/drivers/gpu/drm/scheduler/Makefile @@ -20,6 +20,18 @@ # OTHER DEALINGS IN THE SOFTWARE. # # -gpu-sched-y := sched_main.o sched_fence.o sched_entity.o -obj-$(CONFIG_DRM_SCHED) += gpu-sched.o +# +# In DKMS mode the module can be renamed by passing SCHED_NAME as a parameter +# to 'make' if required +# +SCHED_NAME = gpu-sched + +$(SCHED_NAME)-y := sched_main.o sched_fence.o sched_entity.o +obj-$(CONFIG_DRM_SCHED) += $(SCHED_NAME).o + +SCHED_FULL_PATH = $(src) + +ccflags-y := -I$(SCHED_FULL_PATH) + +include $(SCHED_FULL_PATH)/backport/Makefile diff --git a/drivers/gpu/drm/scheduler/backport/Makefile b/drivers/gpu/drm/scheduler/backport/Makefile new file mode 100644 index 0000000000000..5fe7a0b580f33 --- /dev/null +++ b/drivers/gpu/drm/scheduler/backport/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: MIT +ccflags-y += \ + -I$(SCHED_FULL_PATH) \ + -include backport/backport.h diff --git a/drivers/gpu/drm/scheduler/backport/backport.h b/drivers/gpu/drm/scheduler/backport/backport.h new file mode 100644 index 0000000000000..b8c8be307a2e7 --- /dev/null +++ b/drivers/gpu/drm/scheduler/backport/backport.h @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef AMDSCHED_BACKPORT_H +#define AMDSCHED_BACKPORT_H + +#include + +#endif From 50cd2d3b9de995b79e7c6c5e12efaea53183ebf9 Mon Sep 17 00:00:00 2001 From: Junwei Zhang Date: Wed, 13 Nov 2019 11:16:11 +0800 Subject: [PATCH 0017/1868] drm/amdkcl: add backport support for ttm It's a squash of 221c1ea7b3dbd drm/amdkcl: fix license 6e5bc9b8e7ea amd/amdkcl: drop use of BUILD_AS_DKMS in Makefile files 3f3db2b92b63 drm/amdkcl: properly define and initialize Makefile variables e173231be48f drm/amdkcl: add backport support for ttm Signed-off-by: Junwei Zhang Reviewed-by: Qiang Yu Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang Signed-off-by: Slava Grigorev Acked-by: Jonathan Kim Reviewed-by: Flora Cui --- drivers/gpu/drm/ttm/Makefile | 15 ++++++++++++--- drivers/gpu/drm/ttm/backport/Makefile | 4 ++++ drivers/gpu/drm/ttm/backport/backport.h | 7 +++++++ 3 files changed, 23 insertions(+), 3 deletions(-) create mode 100644 drivers/gpu/drm/ttm/backport/Makefile create mode 100644 drivers/gpu/drm/ttm/backport/backport.h diff --git a/drivers/gpu/drm/ttm/Makefile b/drivers/gpu/drm/ttm/Makefile index dad298127226c..c5b547aa54298 100644 --- a/drivers/gpu/drm/ttm/Makefile +++ b/drivers/gpu/drm/ttm/Makefile @@ -2,10 +2,19 @@ # # Makefile for the drm device driver. This driver provides support for the -ttm-y := ttm_tt.o ttm_bo.o ttm_bo_util.o ttm_bo_vm.o ttm_module.o \ +# +# In DKMS mode the module can be renamed by passing TTM_NAME as a parameter +# to 'make' if required +# +TTM_NAME = ttm + +$(TTM_NAME)-y := ttm_tt.o ttm_bo.o ttm_bo_util.o ttm_bo_vm.o ttm_module.o \ ttm_execbuf_util.o ttm_range_manager.o ttm_resource.o ttm_pool.o \ ttm_device.o ttm_sys_manager.o -ttm-$(CONFIG_AGP) += ttm_agp_backend.o +$(TTM_NAME)-$(CONFIG_AGP) += ttm_agp_backend.o -obj-$(CONFIG_DRM_TTM) += ttm.o +obj-$(CONFIG_DRM_TTM) += $(TTM_NAME).o obj-$(CONFIG_DRM_TTM_KUNIT_TEST) += tests/ + +TTM_FULL_PATH = $(src) +include $(TTM_FULL_PATH)/backport/Makefile diff --git a/drivers/gpu/drm/ttm/backport/Makefile b/drivers/gpu/drm/ttm/backport/Makefile new file mode 100644 index 0000000000000..839110332c785 --- /dev/null +++ b/drivers/gpu/drm/ttm/backport/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: MIT +ccflags-y += \ + -I$(TTM_FULL_PATH) \ + -include backport/backport.h diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h new file mode 100644 index 0000000000000..524d2a01b50df --- /dev/null +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef AMDTTM_BACKPORT_H +#define AMDTTM_BACKPORT_H + +#include + +#endif From f3409bebdaa58511e34277abd1363f0822bf9ee0 Mon Sep 17 00:00:00 2001 From: Qiang Yu Date: Thu, 15 Dec 2016 11:52:56 +0800 Subject: [PATCH 0018/1868] drm/amdkcl[ttm]: rename the device name to amdttm v2: fix ttm name to differentia package driver Signed-off-by: Qiang Yu Reviewed-by: Junwei Zhang Signed-off-by: Jack Gui Reviewed-by: Shiwu Zhang Signed-off-by: Flora Cui --- drivers/gpu/drm/ttm/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/ttm/Makefile b/drivers/gpu/drm/ttm/Makefile index c5b547aa54298..36a31797771e6 100644 --- a/drivers/gpu/drm/ttm/Makefile +++ b/drivers/gpu/drm/ttm/Makefile @@ -7,6 +7,8 @@ # to 'make' if required # TTM_NAME = ttm +ccflags-y += \ + -DTTM_NAME="\"$(TTM_NAME)\"" $(TTM_NAME)-y := ttm_tt.o ttm_bo.o ttm_bo_util.o ttm_bo_vm.o ttm_module.o \ ttm_execbuf_util.o ttm_range_manager.o ttm_resource.o ttm_pool.o \ From d4cbccabc017b442e694956627dbbf564958f311 Mon Sep 17 00:00:00 2001 From: Adam Yang Date: Mon, 16 Sep 2019 11:48:05 +0800 Subject: [PATCH 0019/1868] drm/amdkcl: use $(src) in Makefile when built with dkms v2: Properly define ..._FULL_PATH variables in amdgpu, ttm, and scheduler trees. That fixes 'make -C ... M=... modiles' build to succeed correctly. It's a squash of 3f3db2b92b63 drm/amdkcl: properly define and initialize Makefile variables a5abb9e0c999 drm/amdkcl: use $(src) in Makefile when built with dkms Signed-off-by: Adam Yang Signed-off-by: Slava Grigorev Acked-by: Jonathan Kim Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/Makefile | 2 +- drivers/gpu/drm/scheduler/Makefile | 3 ++- drivers/gpu/drm/ttm/Makefile | 2 +- 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index 57bd3e788817d..6a90cbf44be5e 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -23,7 +23,7 @@ # Makefile for the drm device driver. This driver provides support for the # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher. -FULL_AMD_PATH=$(src)/.. +FULL_AMD_PATH := $(patsubst %/amdgpu,%,$(src)) DISPLAY_FOLDER_NAME=display FULL_AMD_DISPLAY_PATH = $(FULL_AMD_PATH)/$(DISPLAY_FOLDER_NAME) diff --git a/drivers/gpu/drm/scheduler/Makefile b/drivers/gpu/drm/scheduler/Makefile index 1ccff60ee9710..b5a6b6a6203af 100644 --- a/drivers/gpu/drm/scheduler/Makefile +++ b/drivers/gpu/drm/scheduler/Makefile @@ -30,7 +30,8 @@ SCHED_NAME = gpu-sched $(SCHED_NAME)-y := sched_main.o sched_fence.o sched_entity.o obj-$(CONFIG_DRM_SCHED) += $(SCHED_NAME).o -SCHED_FULL_PATH = $(src) +SCHED_FULL_PATH := $(src) + ccflags-y := -I$(SCHED_FULL_PATH) diff --git a/drivers/gpu/drm/ttm/Makefile b/drivers/gpu/drm/ttm/Makefile index 36a31797771e6..40e1d3ff14a5b 100644 --- a/drivers/gpu/drm/ttm/Makefile +++ b/drivers/gpu/drm/ttm/Makefile @@ -18,5 +18,5 @@ $(TTM_NAME)-$(CONFIG_AGP) += ttm_agp_backend.o obj-$(CONFIG_DRM_TTM) += $(TTM_NAME).o obj-$(CONFIG_DRM_TTM_KUNIT_TEST) += tests/ -TTM_FULL_PATH = $(src) +TTM_FULL_PATH := $(src) include $(TTM_FULL_PATH)/backport/Makefile From 6f5f8fe65f88c72834463bab4a50f4ee238fd9df Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Sat, 21 Mar 2020 19:19:35 -0400 Subject: [PATCH 0020/1868] amd/amdkcl: drop use of BUILD_AS_DKMS in Makefile files Signed-off-by: Slava Grigorev Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/Makefile | 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 2 +- drivers/gpu/drm/scheduler/gpu_scheduler_trace.h | 2 +- 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index 6a90cbf44be5e..ba8b60ebeb195 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -335,3 +335,5 @@ endif include $(FULL_AMD_PATH)/backport/Makefile obj-$(CONFIG_DRM_AMDGPU)+= amdgpu.o + +CFLAGS_amdgpu_trace_points.o := -I$(src) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h index 383fce40d4dd7..471c3ab919f1b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h @@ -559,5 +559,5 @@ TRACE_EVENT(amdgpu_reset_reg_dumps, /* This part must be outside protection */ #undef TRACE_INCLUDE_PATH -#define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/amd/amdgpu +#define TRACE_INCLUDE_PATH . #include diff --git a/drivers/gpu/drm/scheduler/gpu_scheduler_trace.h b/drivers/gpu/drm/scheduler/gpu_scheduler_trace.h index c75302ca3427c..f512527364351 100644 --- a/drivers/gpu/drm/scheduler/gpu_scheduler_trace.h +++ b/drivers/gpu/drm/scheduler/gpu_scheduler_trace.h @@ -110,5 +110,5 @@ TRACE_EVENT(drm_sched_job_wait_dep, /* This part must be outside protection */ #undef TRACE_INCLUDE_PATH -#define TRACE_INCLUDE_PATH ../../drivers/gpu/drm/scheduler +#define TRACE_INCLUDE_PATH . #include From df86f256949ac14e2970cd08370f29ae68ac4fb1 Mon Sep 17 00:00:00 2001 From: Junwei Zhang Date: Fri, 8 Nov 2019 12:13:34 +0800 Subject: [PATCH 0021/1868] drm/amdkcl: add amdkcl support It's a squash of 221c1ea7b3dbd drm/amdkcl: fix license 3f3db2b92b63 drm/amdkcl: properly define and initialize Makefile variables 079a1dd78a42 drm/amdkcl: add amdkcl support Signed-off-by: Junwei Zhang Reviewed-by: Qiang Yu Signed-off-by: Flora Cui Signed-off-by: Slava Grigorev Acked-by: Jonathan Kim Reviewed-by: Flora Cui Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang --- drivers/gpu/drm/amd/amdkcl/Makefile | 4 ++++ drivers/gpu/drm/amd/amdkcl/main.c | 20 ++++++++++++++++++++ 2 files changed, 24 insertions(+) create mode 100644 drivers/gpu/drm/amd/amdkcl/Makefile create mode 100644 drivers/gpu/drm/amd/amdkcl/main.c diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile new file mode 100644 index 0000000000000..018792c49a249 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: MIT +amdkcl-y += main.o + +obj-m += amdkcl.o diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c new file mode 100644 index 0000000000000..59f4520c9a8bd --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: MIT */ +#include +#include + +int __init amdkcl_init(void) +{ + return 0; +} +module_init(amdkcl_init); + +void __exit amdkcl_exit(void) +{ +} + +module_exit(amdkcl_exit); + +MODULE_AUTHOR("AMD linux driver team"); +MODULE_DESCRIPTION("Module for OS kernel compatible layer"); +MODULE_LICENSE("GPL"); +MODULE_VERSION("1.0"); From a550f21609bff112dc5ee7a16036c87a1f8d3bda Mon Sep 17 00:00:00 2001 From: Junwei Zhang Date: Thu, 29 Dec 2016 15:07:05 +0800 Subject: [PATCH 0022/1868] drm/amdkcl: use system drm header include uapi/drm/drm.h in $(srctree) Signed-off-by: Junwei Zhang Reviewed-by: Qiang Yu Signed-off-by: Flora Cui --- include/uapi/drm/amdgpu_drm.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index e8135ebb51b7b..da8f1afb16a72 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -32,7 +32,7 @@ #ifndef __AMDGPU_DRM_H__ #define __AMDGPU_DRM_H__ -#include "drm.h" +#include #if defined(__cplusplus) extern "C" { From 92e9cf71e40bbdabe1bea5230029acfd3ec15f38 Mon Sep 17 00:00:00 2001 From: Kevin Wang Date: Fri, 10 Aug 2018 16:36:26 +0800 Subject: [PATCH 0023/1868] drm/amdkcl: add drm version support (v3) v2: detect building kernel automatically custom kernel build support v3: support specific kbuild path v4: VERSION & PATCHLEVEL are exported in kernel Makefile and can be accessed directly It's a squash of 5eb73682006d drm/amdkcl: refactor dkms/Makefile b3160e09da52 drm/amdkcl: simplify DRM_VER retrieve 225506373f54 drm/amdkcl: add drm version support (v3) Signed-off-by: Junwei Zhang Reviewed-by: Qiang Yu Reviewed-by: Yang Xiong Signed-off-by: Flora Cui --- Makefile | 7 ++++++- drivers/gpu/drm/amd/dkms/Makefile | 12 ++++++++++++ include/kcl/kcl_version.h | 8 ++++++++ 3 files changed, 26 insertions(+), 1 deletion(-) create mode 100644 include/kcl/kcl_version.h diff --git a/Makefile b/Makefile index 3d10e3aadeda2..9d3080e06d7e1 100644 --- a/Makefile +++ b/Makefile @@ -1256,7 +1256,12 @@ define filechk_version.h ((c) > 255 ? 255 : (c)))'; \ echo \#define LINUX_VERSION_MAJOR $(VERSION); \ echo \#define LINUX_VERSION_PATCHLEVEL $(PATCHLEVEL); \ - echo \#define LINUX_VERSION_SUBLEVEL $(SUBLEVEL) + echo \#define LINUX_VERSION_SUBLEVEL $(SUBLEVEL); \ + echo '#define DRM_VER $(VERSION)'; \ + echo '#define DRM_PATCH $(PATCHLEVEL)'; \ + echo '#define DRM_SUB $(SUBLEVEL)'; \ + echo \#define DRM_VERSION_CODE LINUX_VERSION_CODE; \ + echo '#define DRM_VERSION(a,b,c) (((a) << 16) + ((b) << 8) + (c))' endef $(version_h): private PATCHLEVEL := $(or $(PATCHLEVEL), 0) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index f5d9b8d250ed6..359ad88155b58 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -1,3 +1,15 @@ +DRM_VER=$(shell sed -n 's/^RHEL_DRM_VERSION = \(.*\)/\1/p' $(srctree)/Makefile) +DRM_PATCH=$(shell sed -n 's/^RHEL_DRM_PATCHLEVEL = \(.*\)/\1/p' $(srctree)/Makefile) +ifeq ($(DRM_VER),) +DRM_VER = $(VERSION) +DRM_PATCH = $(PATCHLEVEL) +endif + +subdir-ccflags-y += \ + -DDRM_VER=$(DRM_VER) \ + -DDRM_PATCH=$(DRM_PATCH) \ + -DDRM_SUB="0" + LINUXINCLUDE := \ -I$(src)/include \ -I$(src)/include/uapi \ diff --git a/include/kcl/kcl_version.h b/include/kcl/kcl_version.h new file mode 100644 index 0000000000000..4a470ef6dbbc7 --- /dev/null +++ b/include/kcl/kcl_version.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef AMDKCL_VERSION_H +#define AMDKCL_VERSION_H + +#define DRM_VERSION(a, b, c) (((a) << 16) + ((b) << 8) + (c)) +#define DRM_VERSION_CODE DRM_VERSION(DRM_VER, DRM_PATCH, DRM_SUB) + +#endif From 6ca1d301a0821900c3b2360601394cfe8b6506f7 Mon Sep 17 00:00:00 2001 From: Kevin Wang Date: Mon, 17 Aug 2020 17:05:09 +0800 Subject: [PATCH 0024/1868] drm/amdkcl: add RHEL_MAJOR/RHEL_MINOR v2: for not generic RHEL OS eg:rhel6 rootfs + rhel7.2 kernel before: define macro OS_NAME_RHEL_6 (error) after: define macro OS_NAME_RHEL_7_2 (ok) It's a squash of 10fee5987c68 drm/amdkcl: refactor get_rhel_version 5eb73682006d drm/amdkcl: refactor dkms/Makefile 2b4eefb780d3 drm/amdkcl: drop kdir in dkms package 01253fdd953b drm/amdkcl: fix RHEL_ version check for rhel8.x 1dbfa0ac3b7f drm/amdkcl: update dkms detect OS method fdc3c5d4df0e drm/amdkcl: add dkms support Signed-off-by: Junwei Zhang Signed-off-by: Adam Yang Reviewed-by: Qiang Yu Reviewed-by: Flora Cui Signed-off-by: Kevin Wang Reviewed-by: Junwei Zhang Signed-off-by: Flora Cui Reviewed-by: Yang Xiong --- drivers/gpu/drm/amd/dkms/Makefile | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 359ad88155b58..37cfe6546b880 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -10,6 +10,12 @@ subdir-ccflags-y += \ -DDRM_PATCH=$(DRM_PATCH) \ -DDRM_SUB="0" +define get_rhel_version +printf "#include \n$(1)" | $(CC) $(LINUXINCLUDE) -E -x c - | tail -n 1 | grep -v $(1) +endef +RHEL_MAJOR := $(shell $(call get_rhel_version,RHEL_MAJOR)) +RHEL_MINOR := $(shell $(call get_rhel_version,RHEL_MINOR)) + LINUXINCLUDE := \ -I$(src)/include \ -I$(src)/include/uapi \ From 94e38ab0cd1fd651a0d23a5f0c4396b1e00bdb4b Mon Sep 17 00:00:00 2001 From: Junwei Zhang Date: Mon, 17 Aug 2020 17:12:12 +0800 Subject: [PATCH 0025/1868] drm/amdkcl: add various os support for RHEL 8.0: (Changfeng.Zhu@amd.com) Both KERNEL VERSION and DRM VERSION of redhat 8.0 are 4.18.0.So it needs some changes in Makefile for redhat 8.0. There is no drm_backport.h for RHEL 8.0.So it doesn't need to include drm_backport.h for customized CentOS/RHEL: (Amber.Lin@amd.com) When RHEL_MAJOR doesn't exist in kernel's Makefile, this is not a standard kernel source distributed from CentOS/RHEL. If /etc/os-release identifies a CentOS/RHEL OS, we should treat it as a customized rhel platform. An example is to install upstream 4.16 kernel from elrepo.org on CentOS 7.5. /etc/centos-release-upstream tells OS version as 7.5 but this is not a 3.10.0-862 kernel. for DEBIAN 9.3 (with kernel-4.19): (yttao@amd.com) Because there are two Makefile path in Debian. One is at xxx-amd64(kernel version is always 2.6) and another is at xxx-common(kernel version is correct). And the real one is actually located at xxx-common. So we need manually specify the Makefile at xxx-common in order to read the correct kernel version. for Debian (custom kernels): (63921018+emollier@users.noreply.github.com) The current rock-dkms Makefile takes properly into account the specificities of the Debian native kernel. However, when a custom upstream kernel is installed, notably through packages obtained via `make deb-pkg`, the driver is not built against that specific kernel. Falling back to the initial kdir value when there is no source/ directory allows to build against such kernels on Debian. for OS_VERSION str: (Flora.Cui@amd.com) simplify OS_VERSION macro handling Signed-off-by: changzhu Reviewed-by: Rui Teng Signed-off-by: Keivn Wang Reviewed-by: Junwei Zhang Signed-off-by: Amber Lin Acked-by: Felix Kuehling Reviewed-by: Junwei Zhang Signed-off-by: Jeremy Newton Reviewed-by: Slava Abramov Signed-off-by: Yintian Tao Reviewed-by: changzhu Signed-off-by: changzhu Signed-off-by: Anatoli Antonovitch Signed-off-by: Yifan Zhang Reviewed-by: Rui Teng Signed-off-by: Adam Yang Reviewed-by: Flora Cui Reviewed-by: Rui Teng Signed-off-by: Slava Grigorev Signed-off-by: Etienne Mollier Signed-off-by: Kent Russell Signed-off-by: Anatoli Antonovitch Tested-by: Anatoli Antonovitch Reviewed-by: Flora Cui Signed-off-by: Flora Cui Reviewed-by: Shiwu Zhang --- drivers/gpu/drm/amd/dkms/Makefile | 78 +++++++++++++++++++++++++++++++ 1 file changed, 78 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 37cfe6546b880..cb38a2549c569 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -16,6 +16,84 @@ endef RHEL_MAJOR := $(shell $(call get_rhel_version,RHEL_MAJOR)) RHEL_MINOR := $(shell $(call get_rhel_version,RHEL_MINOR)) +ifneq (,$(RHEL_MAJOR)) +OS_NAME = "rhel" +OS_VERSION = "$(RHEL_MAJOR).$(RHEL_MINOR)" +else ifneq (,$(wildcard /etc/os-release)) +OS_NAME = "$(shell sed -n 's/^ID=\(.*\)/\1/p' /etc/os-release | tr -d '\"')" +# On CentOS/RHEL, users could have installed a kernel not distributed from RHEL +ifeq ("centos",$(OS_NAME)) +OS_NAME="custom-rhel" +else ifeq ("rhel",$(OS_NAME)) +OS_NAME="custom-rhel" +else ifeq ("linuxmint",$(OS_NAME)) +OS_NAME="ubuntu" +endif +OS_VERSION = $(shell sed -n 's/^VERSION_ID=\(.*\)/\1/p' /etc/os-release) +else +OS_NAME = "unknown" +OS_VERSION = "0.0" +endif + +OS_VERSION_STR = $(subst .,_,$(OS_VERSION)) + +ifeq ("ubuntu",$(OS_NAME)) +subdir-ccflags-y += -DOS_NAME_UBUNTU +else ifeq ("rhel",$(OS_NAME)) +subdir-ccflags-y += -DOS_NAME_RHEL +else ifeq ("steamos",$(OS_NAME)) +subdir-ccflags-y += -DOS_NAME_STEAMOS +else ifeq ("sled",$(OS_NAME)) +subdir-ccflags-y += -DOS_NAME_SLE +else ifeq ("sles",$(OS_NAME)) +subdir-ccflags-y += -DOS_NAME_SLE +else ifeq ("amzn",$(OS_NAME)) +subdir-ccflags-y += -DOS_NAME_AMZ +else ifeq ("debian",$(OS_NAME)) +subdir-ccflags-y += -DOS_NAME_DEBIAN +else +subdir-ccflags-y += -DOS_NAME_UNKNOWN +endif + +subdir-ccflags-y += \ + -DOS_VERSION_MAJOR=$(shell echo $(OS_VERSION).0 | cut -d. -f1) \ + -DOS_VERSION_MINOR=$(shell echo $(OS_VERSION).0 | cut -d. -f2) + +ifeq ($(OS_NAME),"opensuse-leap") +subdir-ccflags-y += -DOS_NAME_SUSE_$(OS_VERSION_STR) +endif + +ifeq ($(OS_NAME),"sled") +subdir-ccflags-y += -DOS_NAME_SUSE_$(OS_VERSION_STR) +endif + +ifeq ($(OS_NAME),"sles") +subdir-ccflags-y += -DOS_NAME_SUSE_$(OS_VERSION_STR) +endif + +ifeq ($(OS_NAME),"ubuntu") +OS_BUILD_NUM = $(shell echo $(KERNELRELEASE) | cut -d '-' -f 2) +subdir-ccflags-y += -DUBUNTU_BUILD_NUM=$(OS_BUILD_NUM) +OS_OEM = "$(shell echo $(KERNELRELEASE) | cut -d '-' -f 3)" +ifeq ($(OS_OEM),"oem") +subdir-ccflags-y += -DOS_NAME_UBUNTU_OEM +endif +subdir-ccflags-y += -DOS_NAME_UBUNTU_$(OS_VERSION_STR) +endif + +ifeq ($(OS_NAME),"rhel") +subdir-ccflags-y += -DOS_NAME_RHEL_$(OS_VERSION_STR) + +ifeq ($(RHEL_MAJOR),7) +subdir-ccflags-y += -DOS_NAME_RHEL_7_X \ + -include /usr/src/kernels/$(KERNELRELEASE)/include/drm/drm_backport.h +else ifeq ($(RHEL_MAJOR),8) +subdir-ccflags-y += -DOS_NAME_RHEL_8_X +endif +endif + +export OS_NAME OS_VERSION + LINUXINCLUDE := \ -I$(src)/include \ -I$(src)/include/uapi \ From a6081ba1e06ef6346e36430c0663e4dd74fdbd2b Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 27 Jul 2020 15:13:05 +0800 Subject: [PATCH 0026/1868] drm/amdkcl: check the prerequisites first fail early if DRM is disabled or DRM_AMDGPU is built-in. Signed-off-by: Flora Cui Reviewed-by: Yang Xiong --- drivers/gpu/drm/amd/dkms/Makefile | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index cb38a2549c569..940586b3cebf1 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -1,3 +1,11 @@ +ifndef CONFIG_DRM +$(error CONFIG_DRM disabled, exit...) +endif + +ifeq (y,$(CONFIG_DRM_AMDGPU)) +$(error DRM_AMDGPU is built-in, exit...) +endif + DRM_VER=$(shell sed -n 's/^RHEL_DRM_VERSION = \(.*\)/\1/p' $(srctree)/Makefile) DRM_PATCH=$(shell sed -n 's/^RHEL_DRM_PATCHLEVEL = \(.*\)/\1/p' $(srctree)/Makefile) ifeq ($(DRM_VER),) From 2b862ce67b862f949b5dd5afdfd5f327bff2b53b Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 19 Aug 2020 15:16:19 +0800 Subject: [PATCH 0027/1868] drm/amdkcl: add dependency for CONFIG_KALLSYMS kallsyms_lookup_name() is a must for legacy kernel support. fail dkms install if CONFIG_KALLSYMS disabled. Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Makefile | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 940586b3cebf1..a23742b01fa26 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -6,6 +6,10 @@ ifeq (y,$(CONFIG_DRM_AMDGPU)) $(error DRM_AMDGPU is built-in, exit...) endif +ifndef CONFIG_KALLSYMS +$(error CONFIG_KALLSYMS disabled, kallsyms_lookup_name() is absent, exit...) +endif + DRM_VER=$(shell sed -n 's/^RHEL_DRM_VERSION = \(.*\)/\1/p' $(srctree)/Makefile) DRM_PATCH=$(shell sed -n 's/^RHEL_DRM_PATCHLEVEL = \(.*\)/\1/p' $(srctree)/Makefile) ifeq ($(DRM_VER),) From 2cff91d6d93a99744b4e2b00f2d8386487bb34f5 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 16 Oct 2020 13:47:30 +0800 Subject: [PATCH 0028/1868] drm/amdkcl: extract _is_kcl_macro_defined to check a macro defined in config.h Signed-off-by: Flora Cui Reviewed-by: shiwu.zhang --- drivers/gpu/drm/amd/dkms/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index a23742b01fa26..509625a2b36e0 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -10,6 +10,8 @@ ifndef CONFIG_KALLSYMS $(error CONFIG_KALLSYMS disabled, kallsyms_lookup_name() is absent, exit...) endif +_is_kcl_macro_defined=$(shell grep $1 $(src)/amd/dkms/config/config.h | grep -q "define" && echo "y" || echo "n") + DRM_VER=$(shell sed -n 's/^RHEL_DRM_VERSION = \(.*\)/\1/p' $(srctree)/Makefile) DRM_PATCH=$(shell sed -n 's/^RHEL_DRM_PATCHLEVEL = \(.*\)/\1/p' $(srctree)/Makefile) ifeq ($(DRM_VER),) From 1825081043b6625645ca4229c15b37ce64152cda Mon Sep 17 00:00:00 2001 From: Kent Russell Date: Tue, 28 Jul 2020 13:22:40 -0400 Subject: [PATCH 0029/1868] drm/amdkcl: Add warning when GCCs do not match v2 If the GCC used to compile the kernel doesn't match the current GCC on the system, print a warning to let the user know. This can hopefully help to find bugs from differing GCC versions causing unexpected and hard-to-track-down errors v2: Avoid quirks with cc-ifversion, don't hardcode gcc v3: drm/amdkcl: update the func to get gcc version get gcc version the same way with $(srctree)/scripts/gcc-version.sh can't leverage gcc-version.sh/gcc-version as the interface changes. the history for gcc-version.sh/gcc-version is: v5.6-12065-g77342a02ff6e gcc-plugins: drop support for GCC <= 4.7 v5.0-rc4-38-gfa7295ab69a3 kbuild: clean up scripts/gcc-version.sh v4.17-6942-g59f53855babf gcc-plugins: test plugin support in Kconfig and clean up Makefile v4.17-6936-ga4353898980c kconfig: add CC_IS_GCC and GCC_VERSION Signed-off-by: Kent Russell Reviewed-by: Felix Kuehling Reviewed-by: Kent Russell Signed-off-by: Flora Cui Change-Id: Ibf64db43988609d8b48865d1eeee8efdc2ed98e2 --- drivers/gpu/drm/amd/dkms/Makefile | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 509625a2b36e0..8ca4f3cba1457 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -12,6 +12,18 @@ endif _is_kcl_macro_defined=$(shell grep $1 $(src)/amd/dkms/config/config.h | grep -q "define" && echo "y" || echo "n") +ifdef CONFIG_CC_IS_GCC +GCCMAJ=$(shell echo __GNUC__ | $(CC) -E -x c - | tail -n 1) +GCCMIN=$(shell echo __GNUC_MINOR__ | $(CC) -E -x c - | tail -n 1) +GCCPAT=$(shell echo __GNUC_MINOR__ | $(CC) -E -x c - | tail -n 1) +# CONFIG_GCC_VERSION returns x.xx.xx as the version format +GCCSTR=$(shell printf "%d%02d%02d" $(GCCMAJ) $(GCCMIN) $(GCCPAT)) +ifeq ($(shell [ $(CONFIG_GCC_VERSION) -ne $(GCCSTR) ] && echo y), y) +$(warning "Local GCC version $(GCCSTR) does not match kernel compiler GCC version $(CONFIG_GCC_VERSION)") +$(warning "This may cause unexpected and hard-to-isolate compiler-related issues") +endif +endif + DRM_VER=$(shell sed -n 's/^RHEL_DRM_VERSION = \(.*\)/\1/p' $(srctree)/Makefile) DRM_PATCH=$(shell sed -n 's/^RHEL_DRM_PATCHLEVEL = \(.*\)/\1/p' $(srctree)/Makefile) ifeq ($(DRM_VER),) From b2d2c772ddb979ef95d929d84d70fdbe3b39b2b2 Mon Sep 17 00:00:00 2001 From: Kevin Wang Date: Wed, 22 Aug 2018 12:42:06 +0800 Subject: [PATCH 0030/1868] drm/amdkcl: enable CONFIG_HSA_AMD v1: 05b0848bf51c drm/amdkcl: [KFD] add kfd dkms support v2: 5fb3731bafd8 drm/amdkcl: fix amdkfd module confusion by correcting value of CONFIG_HSA_AMD v3: 77843fb3174f drm/amdkcl: add DKMS support for amdkfd module build in amdgpu. Signed-off-by: Kevin Wang Signed-off-by: changzhu Signed-off-by: Prike Liang Reviewed-by: Junwei Zhang Reviewed-by: Tianci Yin Reviewed-by: Xiaojie Yuan --- drivers/gpu/drm/amd/dkms/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 8ca4f3cba1457..e147eaa68e72d 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -127,6 +127,7 @@ LINUXINCLUDE := \ -include $(src)/include/rename_symbol.h \ $(LINUXINCLUDE) +export CONFIG_HSA_AMD=y export CONFIG_DRM_TTM=m export CONFIG_DRM_AMDGPU=m export CONFIG_DRM_SCHED=m @@ -136,6 +137,7 @@ export CONFIG_DRM_AMDGPU_USERPTR=y export CONFIG_DRM_AMD_DC=y export CONFIG_DRM_AMD_DC_DCN1_0=y +subdir-ccflags-y += -DCONFIG_HSA_AMD subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_CIK subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_SI subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_USERPTR From c4cc827027934b3286c66e4d4c4186f638d95573 Mon Sep 17 00:00:00 2001 From: Huang Rui Date: Fri, 26 Jan 2018 10:27:17 +0800 Subject: [PATCH 0031/1868] drm/amdkcl: enable dcn2_x support in dkms Reviewed-by: Hawking Zhang Signed-off-by: Jack Xiao Signed-off-by: chen gong Reviewed-by: Roman Li Reviewed-by: changzhu Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index e147eaa68e72d..20c23f2ebf2fb 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -136,6 +136,7 @@ export CONFIG_DRM_AMDGPU_SI=y export CONFIG_DRM_AMDGPU_USERPTR=y export CONFIG_DRM_AMD_DC=y export CONFIG_DRM_AMD_DC_DCN1_0=y +export CONFIG_DRM_AMD_DC_DCN2_x=y subdir-ccflags-y += -DCONFIG_HSA_AMD subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_CIK @@ -143,5 +144,6 @@ subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_SI subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_USERPTR subdir-ccflags-y += -DCONFIG_DRM_AMD_DC subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN1_0 +subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN2_x obj-m += scheduler/ amd/amdgpu/ ttm/ amd/amdkcl/ From 4a7265b4c9edac9a1d0d78d6d7f169e5f85a934a Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 5 Jun 2020 13:50:05 +0800 Subject: [PATCH 0032/1868] drm/amdkcl: enable dcn3_x in dkms package Signed-off-by: Flora Cui Reviewed-by: Yang Xiong --- drivers/gpu/drm/amd/dkms/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 20c23f2ebf2fb..4ed76a92cf2b1 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -137,6 +137,7 @@ export CONFIG_DRM_AMDGPU_USERPTR=y export CONFIG_DRM_AMD_DC=y export CONFIG_DRM_AMD_DC_DCN1_0=y export CONFIG_DRM_AMD_DC_DCN2_x=y +export CONFIG_DRM_AMD_DC_DCN3_x=y subdir-ccflags-y += -DCONFIG_HSA_AMD subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_CIK @@ -145,5 +146,6 @@ subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_USERPTR subdir-ccflags-y += -DCONFIG_DRM_AMD_DC subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN1_0 subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN2_x +subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN3_x obj-m += scheduler/ amd/amdgpu/ ttm/ amd/amdkcl/ From d64fe168f432af81560aa5f7acd0eb08206a9855 Mon Sep 17 00:00:00 2001 From: Kent Russell Date: Thu, 30 Jul 2020 09:18:22 -0400 Subject: [PATCH 0033/1868] drm/amd/dkms: Guard DCN2/3 with regard to core2 These won't work with core2, so we can guard it for now until code consolidation takes place. This avoids a hack in packaging, and also makes transitioning to removing the DCN guards easier in the future Signed-off-by: Kent Russell Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Makefile | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 4ed76a92cf2b1..ce753462ac58c 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -136,8 +136,6 @@ export CONFIG_DRM_AMDGPU_SI=y export CONFIG_DRM_AMDGPU_USERPTR=y export CONFIG_DRM_AMD_DC=y export CONFIG_DRM_AMD_DC_DCN1_0=y -export CONFIG_DRM_AMD_DC_DCN2_x=y -export CONFIG_DRM_AMD_DC_DCN3_x=y subdir-ccflags-y += -DCONFIG_HSA_AMD subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_CIK @@ -145,7 +143,17 @@ subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_SI subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_USERPTR subdir-ccflags-y += -DCONFIG_DRM_AMD_DC subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN1_0 + + +# Trying to enable DCN2/3 with core2 optimizations will result in +# older versions of GCC hanging during building/installing. Check +# if the compiler is using core2 optimizations and only build DCN2/3 +# if core2 isn't in the compiler flags +ifeq ($(filter %core2, $(KBUILD_CFLAGS)),) +export CONFIG_DRM_AMD_DC_DCN2_x=y +export CONFIG_DRM_AMD_DC_DCN3_x=y subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN2_x subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN3_x +endif obj-m += scheduler/ amd/amdgpu/ ttm/ amd/amdkcl/ From 2ac0a0a89f2db115884ad80619329bb4402e4bb6 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Fri, 25 May 2018 16:51:17 -0400 Subject: [PATCH 0034/1868] drm/amdkcl/autoconf: Add initial autoconf framework to DKMS build Signed-off-by: Slava Grigorev Reviewed-by: Feifei Xu Change-Id: I6c9a8dd9e6eb51f40ef4c448038654c09372f200 --- drivers/gpu/drm/amd/dkms/Makefile | 2 + drivers/gpu/drm/amd/dkms/autogen.sh | 4 + drivers/gpu/drm/amd/dkms/config/install-sh | 508 +++++++++++++++++++++ drivers/gpu/drm/amd/dkms/configure.ac | 7 + drivers/gpu/drm/amd/dkms/pre-build.sh | 3 + 5 files changed, 524 insertions(+) create mode 100755 drivers/gpu/drm/amd/dkms/autogen.sh create mode 100755 drivers/gpu/drm/amd/dkms/config/install-sh create mode 100644 drivers/gpu/drm/amd/dkms/configure.ac diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index ce753462ac58c..d628e1b4340ad 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -120,6 +120,8 @@ endif export OS_NAME OS_VERSION +subdir-ccflags-y += -include $(src)/config/config.h + LINUXINCLUDE := \ -I$(src)/include \ -I$(src)/include/uapi \ diff --git a/drivers/gpu/drm/amd/dkms/autogen.sh b/drivers/gpu/drm/amd/dkms/autogen.sh new file mode 100755 index 0000000000000..992eac90a5a18 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/autogen.sh @@ -0,0 +1,4 @@ +#!/bin/bash + +autoreconf -fiv +rm -Rf autom4te.cache diff --git a/drivers/gpu/drm/amd/dkms/config/install-sh b/drivers/gpu/drm/amd/dkms/config/install-sh new file mode 100755 index 0000000000000..59990a1049267 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/config/install-sh @@ -0,0 +1,508 @@ +#!/bin/sh +# install - install a program, script, or datafile + +scriptversion=2014-09-12.12; # UTC + +# This originates from X11R5 (mit/util/scripts/install.sh), which was +# later released in X11R6 (xc/config/util/install.sh) with the +# following copyright and license. +# +# Copyright (C) 1994 X Consortium +# +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to +# deal in the Software without restriction, including without limitation the +# rights to use, copy, modify, merge, publish, distribute, sublicense, and/or +# sell copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. +# +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN +# AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNEC- +# TION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +# +# Except as contained in this notice, the name of the X Consortium shall not +# be used in advertising or otherwise to promote the sale, use or other deal- +# ings in this Software without prior written authorization from the X Consor- +# tium. +# +# +# FSF changes to this file are in the public domain. +# +# Calling this script install-sh is preferred over install.sh, to prevent +# 'make' implicit rules from creating a file called install from it +# when there is no Makefile. +# +# This script is compatible with the BSD install script, but was written +# from scratch. + +tab=' ' +nl=' +' +IFS=" $tab$nl" + +# Set DOITPROG to "echo" to test this script. + +doit=${DOITPROG-} +doit_exec=${doit:-exec} + +# Put in absolute file names if you don't have them in your path; +# or use environment vars. + +chgrpprog=${CHGRPPROG-chgrp} +chmodprog=${CHMODPROG-chmod} +chownprog=${CHOWNPROG-chown} +cmpprog=${CMPPROG-cmp} +cpprog=${CPPROG-cp} +mkdirprog=${MKDIRPROG-mkdir} +mvprog=${MVPROG-mv} +rmprog=${RMPROG-rm} +stripprog=${STRIPPROG-strip} + +posix_mkdir= + +# Desired mode of installed file. +mode=0755 + +chgrpcmd= +chmodcmd=$chmodprog +chowncmd= +mvcmd=$mvprog +rmcmd="$rmprog -f" +stripcmd= + +src= +dst= +dir_arg= +dst_arg= + +copy_on_change=false +is_target_a_directory=possibly + +usage="\ +Usage: $0 [OPTION]... [-T] SRCFILE DSTFILE + or: $0 [OPTION]... SRCFILES... DIRECTORY + or: $0 [OPTION]... -t DIRECTORY SRCFILES... + or: $0 [OPTION]... -d DIRECTORIES... + +In the 1st form, copy SRCFILE to DSTFILE. +In the 2nd and 3rd, copy all SRCFILES to DIRECTORY. +In the 4th, create DIRECTORIES. + +Options: + --help display this help and exit. + --version display version info and exit. + + -c (ignored) + -C install only if different (preserve the last data modification time) + -d create directories instead of installing files. + -g GROUP $chgrpprog installed files to GROUP. + -m MODE $chmodprog installed files to MODE. + -o USER $chownprog installed files to USER. + -s $stripprog installed files. + -t DIRECTORY install into DIRECTORY. + -T report an error if DSTFILE is a directory. + +Environment variables override the default commands: + CHGRPPROG CHMODPROG CHOWNPROG CMPPROG CPPROG MKDIRPROG MVPROG + RMPROG STRIPPROG +" + +while test $# -ne 0; do + case $1 in + -c) ;; + + -C) copy_on_change=true;; + + -d) dir_arg=true;; + + -g) chgrpcmd="$chgrpprog $2" + shift;; + + --help) echo "$usage"; exit $?;; + + -m) mode=$2 + case $mode in + *' '* | *"$tab"* | *"$nl"* | *'*'* | *'?'* | *'['*) + echo "$0: invalid mode: $mode" >&2 + exit 1;; + esac + shift;; + + -o) chowncmd="$chownprog $2" + shift;; + + -s) stripcmd=$stripprog;; + + -t) + is_target_a_directory=always + dst_arg=$2 + # Protect names problematic for 'test' and other utilities. + case $dst_arg in + -* | [=\(\)!]) dst_arg=./$dst_arg;; + esac + shift;; + + -T) is_target_a_directory=never;; + + --version) echo "$0 $scriptversion"; exit $?;; + + --) shift + break;; + + -*) echo "$0: invalid option: $1" >&2 + exit 1;; + + *) break;; + esac + shift +done + +# We allow the use of options -d and -T together, by making -d +# take the precedence; this is for compatibility with GNU install. + +if test -n "$dir_arg"; then + if test -n "$dst_arg"; then + echo "$0: target directory not allowed when installing a directory." >&2 + exit 1 + fi +fi + +if test $# -ne 0 && test -z "$dir_arg$dst_arg"; then + # When -d is used, all remaining arguments are directories to create. + # When -t is used, the destination is already specified. + # Otherwise, the last argument is the destination. Remove it from $@. + for arg + do + if test -n "$dst_arg"; then + # $@ is not empty: it contains at least $arg. + set fnord "$@" "$dst_arg" + shift # fnord + fi + shift # arg + dst_arg=$arg + # Protect names problematic for 'test' and other utilities. + case $dst_arg in + -* | [=\(\)!]) dst_arg=./$dst_arg;; + esac + done +fi + +if test $# -eq 0; then + if test -z "$dir_arg"; then + echo "$0: no input file specified." >&2 + exit 1 + fi + # It's OK to call 'install-sh -d' without argument. + # This can happen when creating conditional directories. + exit 0 +fi + +if test -z "$dir_arg"; then + if test $# -gt 1 || test "$is_target_a_directory" = always; then + if test ! -d "$dst_arg"; then + echo "$0: $dst_arg: Is not a directory." >&2 + exit 1 + fi + fi +fi + +if test -z "$dir_arg"; then + do_exit='(exit $ret); exit $ret' + trap "ret=129; $do_exit" 1 + trap "ret=130; $do_exit" 2 + trap "ret=141; $do_exit" 13 + trap "ret=143; $do_exit" 15 + + # Set umask so as not to create temps with too-generous modes. + # However, 'strip' requires both read and write access to temps. + case $mode in + # Optimize common cases. + *644) cp_umask=133;; + *755) cp_umask=22;; + + *[0-7]) + if test -z "$stripcmd"; then + u_plus_rw= + else + u_plus_rw='% 200' + fi + cp_umask=`expr '(' 777 - $mode % 1000 ')' $u_plus_rw`;; + *) + if test -z "$stripcmd"; then + u_plus_rw= + else + u_plus_rw=,u+rw + fi + cp_umask=$mode$u_plus_rw;; + esac +fi + +for src +do + # Protect names problematic for 'test' and other utilities. + case $src in + -* | [=\(\)!]) src=./$src;; + esac + + if test -n "$dir_arg"; then + dst=$src + dstdir=$dst + test -d "$dstdir" + dstdir_status=$? + else + + # Waiting for this to be detected by the "$cpprog $src $dsttmp" command + # might cause directories to be created, which would be especially bad + # if $src (and thus $dsttmp) contains '*'. + if test ! -f "$src" && test ! -d "$src"; then + echo "$0: $src does not exist." >&2 + exit 1 + fi + + if test -z "$dst_arg"; then + echo "$0: no destination specified." >&2 + exit 1 + fi + dst=$dst_arg + + # If destination is a directory, append the input filename; won't work + # if double slashes aren't ignored. + if test -d "$dst"; then + if test "$is_target_a_directory" = never; then + echo "$0: $dst_arg: Is a directory" >&2 + exit 1 + fi + dstdir=$dst + dst=$dstdir/`basename "$src"` + dstdir_status=0 + else + dstdir=`dirname "$dst"` + test -d "$dstdir" + dstdir_status=$? + fi + fi + + obsolete_mkdir_used=false + + if test $dstdir_status != 0; then + case $posix_mkdir in + '') + # Create intermediate dirs using mode 755 as modified by the umask. + # This is like FreeBSD 'install' as of 1997-10-28. + umask=`umask` + case $stripcmd.$umask in + # Optimize common cases. + *[2367][2367]) mkdir_umask=$umask;; + .*0[02][02] | .[02][02] | .[02]) mkdir_umask=22;; + + *[0-7]) + mkdir_umask=`expr $umask + 22 \ + - $umask % 100 % 40 + $umask % 20 \ + - $umask % 10 % 4 + $umask % 2 + `;; + *) mkdir_umask=$umask,go-w;; + esac + + # With -d, create the new directory with the user-specified mode. + # Otherwise, rely on $mkdir_umask. + if test -n "$dir_arg"; then + mkdir_mode=-m$mode + else + mkdir_mode= + fi + + posix_mkdir=false + case $umask in + *[123567][0-7][0-7]) + # POSIX mkdir -p sets u+wx bits regardless of umask, which + # is incompatible with FreeBSD 'install' when (umask & 300) != 0. + ;; + *) + # $RANDOM is not portable (e.g. dash); use it when possible to + # lower collision chance + tmpdir=${TMPDIR-/tmp}/ins$RANDOM-$$ + trap 'ret=$?; rmdir "$tmpdir/a/b" "$tmpdir/a" "$tmpdir" 2>/dev/null; exit $ret' 0 + + # As "mkdir -p" follows symlinks and we work in /tmp possibly; so + # create the $tmpdir first (and fail if unsuccessful) to make sure + # that nobody tries to guess the $tmpdir name. + if (umask $mkdir_umask && + $mkdirprog $mkdir_mode "$tmpdir" && + exec $mkdirprog $mkdir_mode -p -- "$tmpdir/a/b") >/dev/null 2>&1 + then + if test -z "$dir_arg" || { + # Check for POSIX incompatibilities with -m. + # HP-UX 11.23 and IRIX 6.5 mkdir -m -p sets group- or + # other-writable bit of parent directory when it shouldn't. + # FreeBSD 6.1 mkdir -m -p sets mode of existing directory. + test_tmpdir="$tmpdir/a" + ls_ld_tmpdir=`ls -ld "$test_tmpdir"` + case $ls_ld_tmpdir in + d????-?r-*) different_mode=700;; + d????-?--*) different_mode=755;; + *) false;; + esac && + $mkdirprog -m$different_mode -p -- "$test_tmpdir" && { + ls_ld_tmpdir_1=`ls -ld "$test_tmpdir"` + test "$ls_ld_tmpdir" = "$ls_ld_tmpdir_1" + } + } + then posix_mkdir=: + fi + rmdir "$tmpdir/a/b" "$tmpdir/a" "$tmpdir" + else + # Remove any dirs left behind by ancient mkdir implementations. + rmdir ./$mkdir_mode ./-p ./-- "$tmpdir" 2>/dev/null + fi + trap '' 0;; + esac;; + esac + + if + $posix_mkdir && ( + umask $mkdir_umask && + $doit_exec $mkdirprog $mkdir_mode -p -- "$dstdir" + ) + then : + else + + # The umask is ridiculous, or mkdir does not conform to POSIX, + # or it failed possibly due to a race condition. Create the + # directory the slow way, step by step, checking for races as we go. + + case $dstdir in + /*) prefix='/';; + [-=\(\)!]*) prefix='./';; + *) prefix='';; + esac + + oIFS=$IFS + IFS=/ + set -f + set fnord $dstdir + shift + set +f + IFS=$oIFS + + prefixes= + + for d + do + test X"$d" = X && continue + + prefix=$prefix$d + if test -d "$prefix"; then + prefixes= + else + if $posix_mkdir; then + (umask=$mkdir_umask && + $doit_exec $mkdirprog $mkdir_mode -p -- "$dstdir") && break + # Don't fail if two instances are running concurrently. + test -d "$prefix" || exit 1 + else + case $prefix in + *\'*) qprefix=`echo "$prefix" | sed "s/'/'\\\\\\\\''/g"`;; + *) qprefix=$prefix;; + esac + prefixes="$prefixes '$qprefix'" + fi + fi + prefix=$prefix/ + done + + if test -n "$prefixes"; then + # Don't fail if two instances are running concurrently. + (umask $mkdir_umask && + eval "\$doit_exec \$mkdirprog $prefixes") || + test -d "$dstdir" || exit 1 + obsolete_mkdir_used=true + fi + fi + fi + + if test -n "$dir_arg"; then + { test -z "$chowncmd" || $doit $chowncmd "$dst"; } && + { test -z "$chgrpcmd" || $doit $chgrpcmd "$dst"; } && + { test "$obsolete_mkdir_used$chowncmd$chgrpcmd" = false || + test -z "$chmodcmd" || $doit $chmodcmd $mode "$dst"; } || exit 1 + else + + # Make a couple of temp file names in the proper directory. + dsttmp=$dstdir/_inst.$$_ + rmtmp=$dstdir/_rm.$$_ + + # Trap to clean up those temp files at exit. + trap 'ret=$?; rm -f "$dsttmp" "$rmtmp" && exit $ret' 0 + + # Copy the file name to the temp name. + (umask $cp_umask && $doit_exec $cpprog "$src" "$dsttmp") && + + # and set any options; do chmod last to preserve setuid bits. + # + # If any of these fail, we abort the whole thing. If we want to + # ignore errors from any of these, just make sure not to ignore + # errors from the above "$doit $cpprog $src $dsttmp" command. + # + { test -z "$chowncmd" || $doit $chowncmd "$dsttmp"; } && + { test -z "$chgrpcmd" || $doit $chgrpcmd "$dsttmp"; } && + { test -z "$stripcmd" || $doit $stripcmd "$dsttmp"; } && + { test -z "$chmodcmd" || $doit $chmodcmd $mode "$dsttmp"; } && + + # If -C, don't bother to copy if it wouldn't change the file. + if $copy_on_change && + old=`LC_ALL=C ls -dlL "$dst" 2>/dev/null` && + new=`LC_ALL=C ls -dlL "$dsttmp" 2>/dev/null` && + set -f && + set X $old && old=:$2:$4:$5:$6 && + set X $new && new=:$2:$4:$5:$6 && + set +f && + test "$old" = "$new" && + $cmpprog "$dst" "$dsttmp" >/dev/null 2>&1 + then + rm -f "$dsttmp" + else + # Rename the file to the real destination. + $doit $mvcmd -f "$dsttmp" "$dst" 2>/dev/null || + + # The rename failed, perhaps because mv can't rename something else + # to itself, or perhaps because mv is so ancient that it does not + # support -f. + { + # Now remove or move aside any old file at destination location. + # We try this two ways since rm can't unlink itself on some + # systems and the destination file might be busy for other + # reasons. In this case, the final cleanup might fail but the new + # file should still install successfully. + { + test ! -f "$dst" || + $doit $rmcmd -f "$dst" 2>/dev/null || + { $doit $mvcmd -f "$dst" "$rmtmp" 2>/dev/null && + { $doit $rmcmd -f "$rmtmp" 2>/dev/null; :; } + } || + { echo "$0: cannot unlink or rename $dst" >&2 + (exit 1); exit 1 + } + } && + + # Now rename the file to the real destination. + $doit $mvcmd "$dsttmp" "$dst" + } + fi || exit 1 + + trap '' 0 + fi +done + +# Local variables: +# eval: (add-hook 'write-file-hooks 'time-stamp) +# time-stamp-start: "scriptversion=" +# time-stamp-format: "%:y-%02m-%02d.%02H" +# time-stamp-time-zone: "UTC" +# time-stamp-end: "; # UTC" +# End: diff --git a/drivers/gpu/drm/amd/dkms/configure.ac b/drivers/gpu/drm/amd/dkms/configure.ac new file mode 100644 index 0000000000000..385dda9ac3bfc --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/configure.ac @@ -0,0 +1,7 @@ +AC_INIT(amdgpu-dkms, 19.40) +AC_LANG(C) +AC_CONFIG_AUX_DIR([config]) +AC_CONFIG_HEADERS([config/config.h]) +AC_PROG_INSTALL +AC_PROG_CC +AC_OUTPUT diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index 9fb471b43a708..070b72aedb1ab 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -56,3 +56,6 @@ for config in $AMDGPU_CONFIG $TTM_CONFIG $SCHED_CONFIG; do done sed -i "/${config}$/s/$/_AMDKCL/" amd/dkms/Makefile done + +./autogen.sh +./configure From df148cd50ac34b5e3e42a2ade6fc3b5f33deda83 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Wed, 1 Apr 2020 17:55:00 -0400 Subject: [PATCH 0035/1868] drm/amdkcl/autoconf: make autogen.sh script return status on exit Change-Id: I3248f3f121f28ac821802b25ccc0b2faca075ee7 Signed-off-by: Slava Grigorev Reviewed-by: Jeremy Newton --- drivers/gpu/drm/amd/dkms/autogen.sh | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/dkms/autogen.sh b/drivers/gpu/drm/amd/dkms/autogen.sh index 992eac90a5a18..d72f86b5a2f97 100755 --- a/drivers/gpu/drm/amd/dkms/autogen.sh +++ b/drivers/gpu/drm/amd/dkms/autogen.sh @@ -1,4 +1,5 @@ #!/bin/bash autoreconf -fiv +[[ $? -eq 0 ]] || exit $? rm -Rf autom4te.cache From 1d77d1ff32789e1fa6cfc2074a98d8bc19111287 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Wed, 12 Feb 2020 09:56:54 -0500 Subject: [PATCH 0036/1868] drm/amdkcl/autoconf: use AC_CONFIG_MACRO_DIR macro to include m4 files Signed-off-by: Slava Grigorev --- drivers/gpu/drm/amd/dkms/configure.ac | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/configure.ac b/drivers/gpu/drm/amd/dkms/configure.ac index 385dda9ac3bfc..ed144e0a2a235 100644 --- a/drivers/gpu/drm/amd/dkms/configure.ac +++ b/drivers/gpu/drm/amd/dkms/configure.ac @@ -4,4 +4,6 @@ AC_CONFIG_AUX_DIR([config]) AC_CONFIG_HEADERS([config/config.h]) AC_PROG_INSTALL AC_PROG_CC +AC_CONFIG_MACRO_DIR([m4]) + AC_OUTPUT From c247603f635a148621421d2c7498c0b237676364 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Tue, 29 May 2018 12:46:20 -0400 Subject: [PATCH 0037/1868] drm/amdkcl/autoconf: Add AC_KERNEL_TRY_COMPILE macro Signed-off-by: Slava Grigorev Reviewed-by: Feifei Xu --- drivers/gpu/drm/amd/dkms/configure.ac | 3 + drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 212 ++++++++++++++++++++++++++ 2 files changed, 215 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/kernel.m4 diff --git a/drivers/gpu/drm/amd/dkms/configure.ac b/drivers/gpu/drm/amd/dkms/configure.ac index ed144e0a2a235..20954e53b8326 100644 --- a/drivers/gpu/drm/amd/dkms/configure.ac +++ b/drivers/gpu/drm/amd/dkms/configure.ac @@ -1,4 +1,5 @@ AC_INIT(amdgpu-dkms, 19.40) + AC_LANG(C) AC_CONFIG_AUX_DIR([config]) AC_CONFIG_HEADERS([config/config.h]) @@ -6,4 +7,6 @@ AC_PROG_INSTALL AC_PROG_CC AC_CONFIG_MACRO_DIR([m4]) +AC_CONFIG_KERNEL + AC_OUTPUT diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 new file mode 100644 index 0000000000000..50fe3cba42270 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -0,0 +1,212 @@ +dnl # +dnl # Default kernel configuration +dnl # +AC_DEFUN([AC_CONFIG_KERNEL], [ + AC_KERNEL + + AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ + KERNEL_MAKE="$KERNEL_MAKE O=$LINUX_OBJ" + ]) + + AC_SUBST(KERNEL_MAKE) +]) + +dnl # +dnl # Detect name used for Module.symvers file in kernel +dnl # +AC_DEFUN([AC_MODULE_SYMVERS], [ + modpost=$LINUX/scripts/Makefile.modpost + AC_MSG_CHECKING([kernel file name for module symbols]) + AS_IF([test "x$enable_linux_builtin" != xyes -a -f "$modpost"], [ + AS_IF([grep -q Modules.symvers $modpost], [ + LINUX_SYMBOLS=Modules.symvers + ], [ + LINUX_SYMBOLS=Module.symvers + ]) + + AS_IF([test ! -f "$LINUX_OBJ/$LINUX_SYMBOLS"], [ + AC_MSG_ERROR([ + *** Please make sure the kernel devel package for your distribution + *** is installed. If you are building with a custom kernel, make sure the + *** kernel is configured, built, and the '--with-linux=PATH' configure + *** option refers to the location of the kernel source.]) + ]) + ], [ + LINUX_SYMBOLS=NONE + ]) + AC_MSG_RESULT($LINUX_SYMBOLS) + AC_SUBST(LINUX_SYMBOLS) +]) + +dnl # +dnl # Detect the kernel to be built against +dnl # +AC_DEFUN([AC_KERNEL], [ + AC_ARG_WITH([linux], + AS_HELP_STRING([--with-linux=PATH], + [Path to kernel source]), + [kernelsrc="$withval"]) + + AC_ARG_WITH(linux-obj, + AS_HELP_STRING([--with-linux-obj=PATH], + [Path to kernel build objects]), + [kernelbuild="$withval"]) + + AC_MSG_CHECKING([kernel source directory]) + AS_IF([test -z "$kernelsrc"], [ + AS_IF([test -e "/lib/modules/$(uname -r)/source"], [ + headersdir="/lib/modules/$(uname -r)/source" + sourcelink=$(readlink -f "$headersdir") + ], [test -e "/lib/modules/$(uname -r)/build"], [ + headersdir="/lib/modules/$(uname -r)/build" + sourcelink=$(readlink -f "$headersdir") + ], [ + sourcelink=$(ls -1d /usr/src/kernels/* \ + /usr/src/linux-* \ + 2>/dev/null | grep -v obj | tail -1) + ]) + + AS_IF([test -n "$sourcelink" && test -e ${sourcelink}], [ + kernelsrc=`readlink -f ${sourcelink}` + ], [ + kernelsrc="[Not found]" + ]) + ], [ + AS_IF([test "$kernelsrc" = "NONE"], [ + kernsrcver=NONE + ]) + withlinux=yes + ]) + + AC_MSG_RESULT([$kernelsrc]) + AS_IF([test ! -d "$kernelsrc"], [ + AC_MSG_ERROR([ + *** Please make sure the kernel devel package for your distribution + *** is installed and then try again. If that fails, you can specify the + *** location of the kernel source with the '--with-linux=PATH' option.]) + ]) + + AC_MSG_CHECKING([kernel build directory]) + AS_IF([test -z "$kernelbuild"], [ + AS_IF([test x$withlinux != xyes -a -e "/lib/modules/$(uname -r)/build"], [ + kernelbuild=`readlink -f /lib/modules/$(uname -r)/build` + ], [test -d ${kernelsrc}-obj/${target_cpu}/${target_cpu}], [ + kernelbuild=${kernelsrc}-obj/${target_cpu}/${target_cpu} + ], [test -d ${kernelsrc}-obj/${target_cpu}/default], [ + kernelbuild=${kernelsrc}-obj/${target_cpu}/default + ], [test -d `dirname ${kernelsrc}`/build-${target_cpu}], [ + kernelbuild=`dirname ${kernelsrc}`/build-${target_cpu} + ], [ + kernelbuild=${kernelsrc} + ]) + ]) + AC_MSG_RESULT([$kernelbuild]) + + AC_MSG_CHECKING([kernel source version]) + utsrelease1=$kernelbuild/include/linux/version.h + utsrelease2=$kernelbuild/include/linux/utsrelease.h + utsrelease3=$kernelbuild/include/generated/utsrelease.h + AS_IF([test -r $utsrelease1 && fgrep -q UTS_RELEASE $utsrelease1], [ + utsrelease=linux/version.h + ], [test -r $utsrelease2 && fgrep -q UTS_RELEASE $utsrelease2], [ + utsrelease=linux/utsrelease.h + ], [test -r $utsrelease3 && fgrep -q UTS_RELEASE $utsrelease3], [ + utsrelease=generated/utsrelease.h + ]) + + AS_IF([test "$utsrelease"], [ + kernsrcver=`(echo "#include <$utsrelease>"; + echo "kernsrcver=UTS_RELEASE") | + cpp -I $kernelbuild/include | + grep "^kernsrcver=" | cut -d \" -f 2` + + AS_IF([test -z "$kernsrcver"], [ + AC_MSG_RESULT([Not found]) + AC_MSG_ERROR([*** Cannot determine kernel version.]) + ]) + ], [ + AC_MSG_RESULT([Not found]) + if test "x$enable_linux_builtin" != xyes; then + AC_MSG_ERROR([*** Cannot find UTS_RELEASE definition.]) + else + AC_MSG_ERROR([ + *** Cannot find UTS_RELEASE definition. + *** Please run 'make prepare' inside the kernel source tree.]) + fi + ]) + + AC_MSG_RESULT([$kernsrcver]) + + LINUX=${kernelsrc} + LINUX_OBJ=${kernelbuild} + LINUX_VERSION=${kernsrcver} + + AC_SUBST(LINUX) + AC_SUBST(LINUX_OBJ) + AC_SUBST(LINUX_VERSION) + + AC_MODULE_SYMVERS +]) + +dnl # +dnl # AC_KERNEL_CONFTEST_H +dnl # +AC_DEFUN([AC_KERNEL_CONFTEST_H], [ +cat - <<_ACEOF >conftest.h +$1 +_ACEOF +]) + +dnl # +dnl # AC_KERNEL_CONFTEST_C +dnl # +AC_DEFUN([AC_KERNEL_CONFTEST_C], [ +cat confdefs.h - <<_ACEOF >conftest.c +$1 +_ACEOF +]) + +dnl # +dnl # AC_KERNEL_LANG_PROGRAM(C)([PROLOGUE], [BODY]) +dnl # +AC_DEFUN([AC_KERNEL_LANG_PROGRAM], [ +$1 +int +main (void) +{ +dnl Do *not* indent the following line: there may be CPP directives. +dnl Don't move the `;' right after for the same reason. +$2 + ; + return 0; +} +]) + +dnl # +dnl # AC_KERNEL_COMPILE_IFELSE / like AC_COMPILE_IFELSE +dnl # +AC_DEFUN([AC_KERNEL_COMPILE_IFELSE], [ + m4_ifvaln([$1], [AC_KERNEL_CONFTEST_C([$1])]) + m4_ifvaln([$6], [AC_KERNEL_CONFTEST_H([$6])], [AC_KERNEL_CONFTEST_H([])]) + rm -Rf build && mkdir -p build && touch build/conftest.mod.c + echo "obj-m := conftest.o" >build/Makefile + modpost_flag='' + test "x$enable_linux_builtin" = xyes && modpost_flag='modpost=true' # fake modpost stage + AS_IF( + [AC_TRY_COMMAND(cp conftest.c conftest.h build && make [$2] -C $LINUX_OBJ EXTRA_CFLAGS="-Werror" M=$PWD/build $modpost_flag) >/dev/null && AC_TRY_COMMAND([$3])], + [$4], + [_AC_MSG_LOG_CONFTEST m4_ifvaln([$5],[$5])] + ) + rm -Rf build +]) + +dnl # +dnl # AC_KERNEL_TRY_COMPILE like AC_TRY_COMPILE +dnl # +AC_DEFUN([AC_KERNEL_TRY_COMPILE], + [AC_KERNEL_COMPILE_IFELSE( + [AC_LANG_SOURCE([AC_KERNEL_LANG_PROGRAM([[$1]], [[$2]])])], + [modules], + [test -s build/conftest.o], + [$3], [$4]) +]) From ec26d96ab4bf537d2e702af4ed768bd8127a7701 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Fri, 1 Jun 2018 12:00:42 -0400 Subject: [PATCH 0038/1868] drm/amdkcl/autoconf: Add AC_AMDGPU_CONFIG macro with basic configuration it is a squash of: drm/amdkcl/autoconf: Add AC_AMDGPU_CONFIG macro with basic configuration Signed-off-by: Slava Grigorev Reviewed-by: Feifei Xu Signed-off-by: Yifan Zhang commit b979e488f77894bb89aee6424cd803f76f6d760d Author: Slava Grigorev Date: Wed Feb 12 09:56:54 2020 -0500 drm/amdkcl: use AC_CONFIG_MACRO_DIR macro to include m4 files Change-Id: I01581d410f6c45d41c40852ed44a0e451bbe8622 Signed-off-by: Slava Grigorev Change-Id: If3a07ed5064cc5cdddeb0abd0ce562be582d32ad --- drivers/gpu/drm/amd/dkms/configure.ac | 2 +- drivers/gpu/drm/amd/dkms/m4/config.m4 | 9 +++++++++ 2 files changed, 10 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/config.m4 diff --git a/drivers/gpu/drm/amd/dkms/configure.ac b/drivers/gpu/drm/amd/dkms/configure.ac index 20954e53b8326..b367e452d4cbb 100644 --- a/drivers/gpu/drm/amd/dkms/configure.ac +++ b/drivers/gpu/drm/amd/dkms/configure.ac @@ -7,6 +7,6 @@ AC_PROG_INSTALL AC_PROG_CC AC_CONFIG_MACRO_DIR([m4]) -AC_CONFIG_KERNEL +AC_AMDGPU_CONFIG AC_OUTPUT diff --git a/drivers/gpu/drm/amd/dkms/m4/config.m4 b/drivers/gpu/drm/amd/dkms/m4/config.m4 new file mode 100644 index 0000000000000..e22a4a49a5233 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/config.m4 @@ -0,0 +1,9 @@ +AC_DEFUN([AC_AMDGPU_CONFIG], [ + AC_ARG_ENABLE([linux-builtin], + [AC_HELP_STRING([--enable-linux-builtin], + [Configure for builtin kernel modules @<:@default=no@:>@])], + [], + [enable_linux_builtin=no]) + + AC_CONFIG_KERNEL +]) From c28dc9682e7fd808325126490bea9721d002a94a Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Mon, 3 Jun 2019 13:32:52 +0800 Subject: [PATCH 0039/1868] drm/amdkcl/autoconf: Add AC_KERNEL_TRY_COMPILE_SYMBOL macro v2: Correct AC_KERNEL_CHECK_SYMBOL_EXPORT macro to handle multiple symbols v3: Make 'AC_KERNEL_CHECK_SYMBOL_EXPORT' applicable to mawk Signed-off-by: Slava Grigorev Signed-off-by: chen gong Reviewed-by: Feifei Xu --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 73 +++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 50fe3cba42270..05612f1db34fa 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -210,3 +210,76 @@ AC_DEFUN([AC_KERNEL_TRY_COMPILE], [test -s build/conftest.o], [$3], [$4]) ]) + +dnl # +dnl # AC_KERNEL_CHECK_SYMBOL_EXPORT +dnl # check symbol exported or not +dnl # +AC_DEFUN([AC_KERNEL_CHECK_SYMBOL_EXPORT], [ + awk -v s="$1" ' + BEGIN { + n = 0; + num = split(s, symbols, " ") + } { + for (i in symbols) + if (symbols[[i]] == $[2]) + n++ + } END { + if (num == n) + exit 0; + else + exit 1 + }' $LINUX_OBJ/$LINUX_SYMBOLS 2>/dev/null + rc=$? + if test $rc -ne 0; then + n=0 + export=0 + for file in $2; do + n=$(awk -v s="$1" ' + BEGIN { + n = 0; + split(s, symbols, " ") + } { + for (i in symbols) { + s="EXPORT_SYMBOL.*"symbols[[i]]; + if ($[0] ~ s) + n++ + } + } END { + print n + }' $LINUX/$file 2>/dev/null) + rc=$? + if test $rc -eq 0; then + (( export+=n )) + fi + done + if test $(wc -w <<< "$1") -eq $export; then : + $3 + else : + $4 + fi + else : + $3 + fi +]) + +dnl # +dnl # AC_KERNEL_TRY_COMPILE_SYMBOL +dnl # like AC_KERNEL_TRY_COMPILE, except AC_KERNEL_CHECK_SYMBOL_EXPORT +dnl # is called if not compiling for builtin +dnl # +AC_DEFUN([AC_KERNEL_TRY_COMPILE_SYMBOL], [ + AC_KERNEL_TRY_COMPILE([$1], [$2], [rc=0], [rc=1]) + if test $rc -ne 0; then : + $6 + else + if test "x$enable_linux_builtin" != xyes; then + AC_KERNEL_CHECK_SYMBOL_EXPORT([$3], [$4], [rc=0], [rc=1]) + fi + if test $rc -ne 0; then : + $6 + else : + $5 + fi + fi +]) From 0161220cf904c88c3b5b24aa547c2bcb2e814a9d Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Fri, 5 Jul 2019 15:26:46 -0400 Subject: [PATCH 0040/1868] drm/amdkcl/autoconf: Drop autogen.sh call Signed-off-by: Slava Grigorev --- drivers/gpu/drm/amd/dkms/pre-build.sh | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index 070b72aedb1ab..87b972dc63e5e 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -57,5 +57,4 @@ for config in $AMDGPU_CONFIG $TTM_CONFIG $SCHED_CONFIG; do sed -i "/${config}$/s/$/_AMDKCL/" amd/dkms/Makefile done -./autogen.sh ./configure From c238102b3333887e3a311836df1c460382bf061c Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 8 Aug 2019 09:45:06 +0800 Subject: [PATCH 0041/1868] drm/amdkcl/autoconf: fix in-tree check for exported symbols Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 05612f1db34fa..3f79152c41c8d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -17,14 +17,14 @@ dnl # AC_DEFUN([AC_MODULE_SYMVERS], [ modpost=$LINUX/scripts/Makefile.modpost AC_MSG_CHECKING([kernel file name for module symbols]) - AS_IF([test "x$enable_linux_builtin" != xyes -a -f "$modpost"], [ + AS_IF([test -f "$modpost"], [ AS_IF([grep -q Modules.symvers $modpost], [ LINUX_SYMBOLS=Modules.symvers ], [ LINUX_SYMBOLS=Module.symvers ]) - AS_IF([test ! -f "$LINUX_OBJ/$LINUX_SYMBOLS"], [ + AS_IF([test "x$enable_linux_builtin" != xyes -a ! -f "$LINUX_OBJ/$LINUX_SYMBOLS"], [ AC_MSG_ERROR([ *** Please make sure the kernel devel package for your distribution *** is installed. If you are building with a custom kernel, make sure the @@ -273,9 +273,7 @@ AC_DEFUN([AC_KERNEL_TRY_COMPILE_SYMBOL], [ if test $rc -ne 0; then : $6 else - if test "x$enable_linux_builtin" != xyes; then - AC_KERNEL_CHECK_SYMBOL_EXPORT([$3], [$4], [rc=0], [rc=1]) - fi + AC_KERNEL_CHECK_SYMBOL_EXPORT([$3], [$4], [rc=0], [rc=1]) if test $rc -ne 0; then : $6 else : From 9eacd72636766ae86b9afb0589ea97f0914ecc12 Mon Sep 17 00:00:00 2001 From: Adam Yang Date: Thu, 8 Aug 2019 09:43:50 +0800 Subject: [PATCH 0042/1868] drm/amdkcl/autoconf: fix awk syntax error this could fix in-tree build error on ubuntu16.04.4 Signed-off-by: Adam Yang Reviewed-by: Yifan Zhang --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 3f79152c41c8d..b2fb779404579 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -241,7 +241,7 @@ AC_DEFUN([AC_KERNEL_CHECK_SYMBOL_EXPORT], [ split(s, symbols, " ") } { for (i in symbols) { - s="EXPORT_SYMBOL.*"symbols[[i]]; + s="EXPORT_SYMBOL.*\\("symbols[[i]]"\\);" if ($[0] ~ s) n++ } From 211d5d2dac8ac1b28d8a8878efaa05a5c2d16e0f Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 25 Jul 2019 16:10:42 +0800 Subject: [PATCH 0043/1868] drm/amdkcl/autoconf: fix dkms build kernel version check the original behavior install dkms package with the current kernel, which is not expected. Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 12 ++++++------ drivers/gpu/drm/amd/dkms/pre-build.sh | 1 + 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index b2fb779404579..fd06f6ee28951 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -54,11 +54,11 @@ AC_DEFUN([AC_KERNEL], [ AC_MSG_CHECKING([kernel source directory]) AS_IF([test -z "$kernelsrc"], [ - AS_IF([test -e "/lib/modules/$(uname -r)/source"], [ - headersdir="/lib/modules/$(uname -r)/source" + AS_IF([test -e "/lib/modules/$KERNELVER/source"], [ + headersdir="/lib/modules/$KERNELVER/source" sourcelink=$(readlink -f "$headersdir") - ], [test -e "/lib/modules/$(uname -r)/build"], [ - headersdir="/lib/modules/$(uname -r)/build" + ], [test -e "/lib/modules/$KERNELVER/build"], [ + headersdir="/lib/modules/$KERNELVER/build" sourcelink=$(readlink -f "$headersdir") ], [ sourcelink=$(ls -1d /usr/src/kernels/* \ @@ -88,8 +88,8 @@ AC_DEFUN([AC_KERNEL], [ AC_MSG_CHECKING([kernel build directory]) AS_IF([test -z "$kernelbuild"], [ - AS_IF([test x$withlinux != xyes -a -e "/lib/modules/$(uname -r)/build"], [ - kernelbuild=`readlink -f /lib/modules/$(uname -r)/build` + AS_IF([test x$withlinux != xyes -a -e "/lib/modules/$KERNELVER/build"], [ + kernelbuild=`readlink -f /lib/modules/$KERNELVER/build` ], [test -d ${kernelsrc}-obj/${target_cpu}/${target_cpu}], [ kernelbuild=${kernelsrc}-obj/${target_cpu}/${target_cpu} ], [test -d ${kernelsrc}-obj/${target_cpu}/default], [ diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index 87b972dc63e5e..264b42dd2af4d 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -57,4 +57,5 @@ for config in $AMDGPU_CONFIG $TTM_CONFIG $SCHED_CONFIG; do sed -i "/${config}$/s/$/_AMDKCL/" amd/dkms/Makefile done +export KERNELVER ./configure From 86061f289ea636521bdb5b9d4784799c55561164 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 30 Jul 2019 14:03:13 +0800 Subject: [PATCH 0044/1868] drm/amdkcl/autoconf: add documentation for autoconf macros Add documentation for AC_KERNEL_* macros. Signed-off-by: Flora Cui Reviewed-by: Feifei Xu --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index fd06f6ee28951..ea4b86472c6e4 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -150,6 +150,7 @@ AC_DEFUN([AC_KERNEL], [ dnl # dnl # AC_KERNEL_CONFTEST_H +dnl # $1: contents to be filled in conftest.h dnl # AC_DEFUN([AC_KERNEL_CONFTEST_H], [ cat - <<_ACEOF >conftest.h @@ -159,6 +160,8 @@ _ACEOF dnl # dnl # AC_KERNEL_CONFTEST_C +dnl # fill in contents of conftest.h and $1 to conftest.c +dnl # $1: contents to be filled in conftest.c dnl # AC_DEFUN([AC_KERNEL_CONFTEST_C], [ cat confdefs.h - <<_ACEOF >conftest.c @@ -167,7 +170,7 @@ _ACEOF ]) dnl # -dnl # AC_KERNEL_LANG_PROGRAM(C)([PROLOGUE], [BODY]) +dnl # AC_KERNEL_LANG_PROGRAM([PROLOGUE], [BODY]) dnl # AC_DEFUN([AC_KERNEL_LANG_PROGRAM], [ $1 @@ -184,6 +187,12 @@ $2 dnl # dnl # AC_KERNEL_COMPILE_IFELSE / like AC_COMPILE_IFELSE +dnl # $1: contents to be filled in conftest.c +dnl # $2: make target. "modules" for most case +dnl # $3: user defined commands. It "AND" the make command to check the result. If true, expands to $4. Otherwise $5. +dnl # $4: run it if make & $3 pass. +dnl # $5: run it if make & $3 fail. +dnl # $6: contents to be filled in conftest.h. Could be null. dnl # AC_DEFUN([AC_KERNEL_COMPILE_IFELSE], [ m4_ifvaln([$1], [AC_KERNEL_CONFTEST_C([$1])]) @@ -202,6 +211,10 @@ AC_DEFUN([AC_KERNEL_COMPILE_IFELSE], [ dnl # dnl # AC_KERNEL_TRY_COMPILE like AC_TRY_COMPILE +dnl # $1: Prologue for conftest.c. including header files, extends, etc +dnl # $2: Body for conftest.c. +dnl # $3: run it if compile pass. +dnl # $4: run it if compile fail. dnl # AC_DEFUN([AC_KERNEL_TRY_COMPILE], [AC_KERNEL_COMPILE_IFELSE( @@ -214,6 +227,10 @@ AC_DEFUN([AC_KERNEL_TRY_COMPILE], dnl # dnl # AC_KERNEL_CHECK_SYMBOL_EXPORT dnl # check symbol exported or not +dnl # $1: symbol list to look for +dnl # $2: file list to look for $1 +dnl # $3: run it if pass. +dnl # $4: run it if fail. dnl # AC_DEFUN([AC_KERNEL_CHECK_SYMBOL_EXPORT], [ awk -v s="$1" ' @@ -267,6 +284,12 @@ dnl # dnl # AC_KERNEL_TRY_COMPILE_SYMBOL dnl # like AC_KERNEL_TRY_COMPILE, except AC_KERNEL_CHECK_SYMBOL_EXPORT dnl # is called if not compiling for builtin +dnl # $1: Prologue for conftest.c. including header files, extends, etc +dnl # $2: Body for conftest.c. +dnl # $3: AC_KERNEL_CHECK_SYMBOL_EXPORT $1 +dnl # $4: AC_KERNEL_CHECK_SYMBOL_EXPORT $2 +dnl # $5: run it if checking pass +dnl # $6: run it if checking fail dnl # AC_DEFUN([AC_KERNEL_TRY_COMPILE_SYMBOL], [ AC_KERNEL_TRY_COMPILE([$1], [$2], [rc=0], [rc=1]) From 04da66eb5d13ca68312a3f5bc4b5bf5faba77cac Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 26 Jul 2019 11:28:47 +0800 Subject: [PATCH 0045/1868] drm/amdkcl/autoconf: add more flags to compile conftest v1: b1c3905f5703 drm/amdkcl/autoconf: make uninitialized warning not error v2: ab8d6b1a69d6 drm/amdkcl/autoconf: add more flags to compile conftest Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index ea4b86472c6e4..d491a3d205ded 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -202,7 +202,7 @@ AC_DEFUN([AC_KERNEL_COMPILE_IFELSE], [ modpost_flag='' test "x$enable_linux_builtin" = xyes && modpost_flag='modpost=true' # fake modpost stage AS_IF( - [AC_TRY_COMMAND(cp conftest.c conftest.h build && make [$2] -C $LINUX_OBJ EXTRA_CFLAGS="-Werror" M=$PWD/build $modpost_flag) >/dev/null && AC_TRY_COMMAND([$3])], + [AC_TRY_COMMAND(cp conftest.c conftest.h build && make [$2] -C $LINUX_OBJ EXTRA_CFLAGS="-Werror -Wno-error=uninitialized -Wno-error=unused-variable" M=$PWD/build $modpost_flag $kbuild_src_flag) >/dev/null && AC_TRY_COMMAND([$3])], [$4], [_AC_MSG_LOG_CONFTEST m4_ifvaln([$5],[$5])] ) From a3c761e173df43ff84c6f3b919f6cd66285831b9 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 1 Aug 2019 17:27:15 +0800 Subject: [PATCH 0046/1868] drm/amdkcl/autoconf: add AC_KERNEL_TEST_HEADER_FILE_EXIST macro AC_KERNEL_TEST_HEADER_FILE_EXIST is added to detect whether the desired header file is available. It could save dkms install time. and could help to avoid errors that the depent header files missing in conftest.c due to kernel version changes. v1: 77102303c630 drm/amd/autoconf: add AC_KERNEL_TEST_HEADER_FILE_EXIST v2: ecb0feb54350 drm/amd/autoconf: fix test header exists error in SLED15.1 v3: bae172b63d85 drm/amd/autoconf: fix AC_KERNEL_TEST_HEADER_FILE_EXIST() Signed-off-by: Flora Cui Signed-off-by: Yifan Zhang Reviewed-by: Feifei Xu Reviewed-by: Flora Cui Reviewed-by: Yifan Zhang --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index d491a3d205ded..75cf807577c7c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -304,3 +304,21 @@ AC_DEFUN([AC_KERNEL_TRY_COMPILE_SYMBOL], [ fi fi ]) + +dnl # +dnl # AC_KERNEL_TEST_HEADER_FILE_EXIST +dnl # check header file exist +dnl # $1: header file to check +dnl # $2: run it if header file exist +dnl # $3: run it if header file nonexistent +dnl # +AC_DEFUN([AC_KERNEL_TEST_HEADER_FILE_EXIST], [ + header_file=m4_normalize([$1]) + header_file_obj=$LINUX_OBJ/include/$header_file + header_file_src=$LINUX/include/$header_file + AS_IF([test -e $header_file_obj -o -e $header_file_src], [ + $2 + ], [ + $3 + ]) +]) From 310683c31dcc52a1ed5f83c80b1763f0be9045af Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Fri, 10 Apr 2020 10:55:37 +0800 Subject: [PATCH 0047/1868] drm/amdkcl/autoconf: introduce parallel autoconf tests execution Signed-off-by: Slava Grigorev --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 69 +++++++++++++++++++++++---- 1 file changed, 60 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 75cf807577c7c..7f07aafc7cc59 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -4,6 +4,7 @@ dnl # AC_DEFUN([AC_CONFIG_KERNEL], [ AC_KERNEL + AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ KERNEL_MAKE="$KERNEL_MAKE O=$LINUX_OBJ" ]) @@ -164,7 +165,7 @@ dnl # fill in contents of conftest.h and $1 to conftest.c dnl # $1: contents to be filled in conftest.c dnl # AC_DEFUN([AC_KERNEL_CONFTEST_C], [ -cat confdefs.h - <<_ACEOF >conftest.c +cat $ac_build_root_dir/confdefs.h - <<_ACEOF >conftest.c $1 _ACEOF ]) @@ -197,16 +198,34 @@ dnl # AC_DEFUN([AC_KERNEL_COMPILE_IFELSE], [ m4_ifvaln([$1], [AC_KERNEL_CONFTEST_C([$1])]) m4_ifvaln([$6], [AC_KERNEL_CONFTEST_H([$6])], [AC_KERNEL_CONFTEST_H([])]) - rm -Rf build && mkdir -p build && touch build/conftest.mod.c - echo "obj-m := conftest.o" >build/Makefile - modpost_flag='' - test "x$enable_linux_builtin" = xyes && modpost_flag='modpost=true' # fake modpost stage + touch conftest.mod.c + echo "obj-m := conftest.o" >Makefile + kbuild_src_flag='' + kbuild_modpost_flag='KBUILD_MODPOST_NOFINAL=1 KBUILD_MODPOST_WARN=1' + kbuild_workaround_flag='' + test "x$enable_linux_builtin" = xyes && kbuild_src_flag='KBUILD_SRC=' # override KBUILD_SRC + test "x$enable_linux_builtin" = xyes && kbuild_workaround_flag='sub_make_done=' # override sub_make_done AS_IF( - [AC_TRY_COMMAND(cp conftest.c conftest.h build && make [$2] -C $LINUX_OBJ EXTRA_CFLAGS="-Werror -Wno-error=uninitialized -Wno-error=unused-variable" M=$PWD/build $modpost_flag $kbuild_src_flag) >/dev/null && AC_TRY_COMMAND([$3])], + [AC_TRY_COMMAND(make [$2] -C $LINUX_OBJ EXTRA_CFLAGS="-Werror -Wno-error=uninitialized -Wno-error=unused-variable" M=$PWD $kbuild_src_flag $kbuild_workaround_flag $kbuild_modpost_flag) >/dev/null && AC_TRY_COMMAND([$3])], [$4], [_AC_MSG_LOG_CONFTEST m4_ifvaln([$5],[$5])] ) - rm -Rf build +]) + +dnl # +dnl # AC_KERNEL_TMP_BUILD_DIR +dnl # $1: contents to be executed in a temporary directory +dnl # +AC_DEFUN([AC_KERNEL_TMP_BUILD_DIR], [ + local build_dir=$(mktemp -d -t build-XXXXXXXX -p .) + pushd $build_dir >/dev/null + $1 + build_dir=$PWD + popd >/dev/null + AS_IF([test -s $build_dir/confdefs.h], [ + cat $build_dir/confdefs.h >>$ac_build_root_dir/confdefs.h + ]) + rm -rf $build_dir ]) dnl # @@ -217,11 +236,15 @@ dnl # $3: run it if compile pass. dnl # $4: run it if compile fail. dnl # AC_DEFUN([AC_KERNEL_TRY_COMPILE], + target='modules' + test "x$enable_linux_builtin" = xyes && target='conftest.o' + [AC_KERNEL_TMP_BUILD_DIR( [AC_KERNEL_COMPILE_IFELSE( [AC_LANG_SOURCE([AC_KERNEL_LANG_PROGRAM([[$1]], [[$2]])])], - [modules], - [test -s build/conftest.o], + [$target], + [test -s conftest.o], [$3], [$4]) + ]) ]) dnl # @@ -322,3 +345,31 @@ AC_DEFUN([AC_KERNEL_TEST_HEADER_FILE_EXIST], [ $3 ]) ]) + +dnl # +dnl # AC_KERNEL_DO_BACKGROUND +dnl # $1: contents to be executed +dnl # +AC_DEFUN([AC_KERNEL_DO_BACKGROUND], [ + do_background() { + $1 + } + do_background & + procs+=( "$!" ) +]) + +dnl # +dnl # AC_KERNEL_WAIT +dnl # wait for all tests to be finished +dnl # +AC_DEFUN([AC_KERNEL_WAIT], [ + AC_MSG_CHECKING([for module configuration]) + wait ${procs[[@]]} + AS_IF([[[ $? -eq 0 ]]], [ + AC_MSG_RESULT([done]) + ], [ + AC_MSG_RESULT([failed]) + ]) +]) + +ac_build_root_dir=$PWD From 4e2b77e6b3d0cc23d9b08dbc1ce5a83237758aed Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 22 Jul 2020 10:39:05 +0800 Subject: [PATCH 0048/1868] drm/amdkcl/autoconf: drop compile target for conftest use the default one Signed-off-by: Flora Cui Reviewed-by: Yang Xiong --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 7f07aafc7cc59..7fd72165bb096 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -189,7 +189,7 @@ $2 dnl # dnl # AC_KERNEL_COMPILE_IFELSE / like AC_COMPILE_IFELSE dnl # $1: contents to be filled in conftest.c -dnl # $2: make target. "modules" for most case +dnl # $2: make target. dnl # $3: user defined commands. It "AND" the make command to check the result. If true, expands to $4. Otherwise $5. dnl # $4: run it if make & $3 pass. dnl # $5: run it if make & $3 fail. @@ -236,7 +236,7 @@ dnl # $3: run it if compile pass. dnl # $4: run it if compile fail. dnl # AC_DEFUN([AC_KERNEL_TRY_COMPILE], - target='modules' + target='' test "x$enable_linux_builtin" = xyes && target='conftest.o' [AC_KERNEL_TMP_BUILD_DIR( [AC_KERNEL_COMPILE_IFELSE( From b4ce67d2feb5aea6f802a817ed11eaa07aaeec69 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Thu, 13 Feb 2020 12:43:57 -0500 Subject: [PATCH 0049/1868] drm/amdkcl/autoconf: properly define the root of the build directories Signed-off-by: Slava Grigorev --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 7fd72165bb096..9f789fb192974 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -141,6 +141,7 @@ AC_DEFUN([AC_KERNEL], [ LINUX=${kernelsrc} LINUX_OBJ=${kernelbuild} LINUX_VERSION=${kernsrcver} + build_dir_root=$(cd "${0%/*}" && pwd) AC_SUBST(LINUX) AC_SUBST(LINUX_OBJ) @@ -165,7 +166,7 @@ dnl # fill in contents of conftest.h and $1 to conftest.c dnl # $1: contents to be filled in conftest.c dnl # AC_DEFUN([AC_KERNEL_CONFTEST_C], [ -cat $ac_build_root_dir/confdefs.h - <<_ACEOF >conftest.c +cat $build_dir_root/confdefs.h - <<_ACEOF >conftest.c $1 _ACEOF ]) @@ -223,7 +224,7 @@ AC_DEFUN([AC_KERNEL_TMP_BUILD_DIR], [ build_dir=$PWD popd >/dev/null AS_IF([test -s $build_dir/confdefs.h], [ - cat $build_dir/confdefs.h >>$ac_build_root_dir/confdefs.h + cat $build_dir/confdefs.h >>$build_dir_root/confdefs.h ]) rm -rf $build_dir ]) @@ -371,5 +372,3 @@ AC_DEFUN([AC_KERNEL_WAIT], [ AC_MSG_RESULT([failed]) ]) ]) - -ac_build_root_dir=$PWD From 14eee2b5d60cb7cb8d053bead49ff2e3af06230b Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Fri, 14 Feb 2020 22:28:57 -0500 Subject: [PATCH 0050/1868] drm/amdkcl/autoconf: fix background function execution Signed-off-by: Slava Grigorev --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 9f789fb192974..fc1ec9b67a109 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -239,13 +239,11 @@ dnl # AC_DEFUN([AC_KERNEL_TRY_COMPILE], target='' test "x$enable_linux_builtin" = xyes && target='conftest.o' - [AC_KERNEL_TMP_BUILD_DIR( [AC_KERNEL_COMPILE_IFELSE( [AC_LANG_SOURCE([AC_KERNEL_LANG_PROGRAM([[$1]], [[$2]])])], [$target], [test -s conftest.o], [$3], [$4]) - ]) ]) dnl # @@ -353,7 +351,7 @@ dnl # $1: contents to be executed dnl # AC_DEFUN([AC_KERNEL_DO_BACKGROUND], [ do_background() { - $1 + AC_KERNEL_TMP_BUILD_DIR([$1]) } do_background & procs+=( "$!" ) From b996797dade9738f6348c3bc8e52e869c512576a Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Mon, 2 Dec 2019 10:37:07 +0800 Subject: [PATCH 0051/1868] drm/amdkcl/autoconf: remove bash specific commands squash of 9b50ddbd026a drm/amdkcl/autoconf: remove bash specific commands 4d0397689a82 drm/amdkcl/autoconf: fix in-tree failure for v5.4 Signed-off-by: Slava Grigorev Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index fc1ec9b67a109..ed40d9a3728a8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -218,14 +218,13 @@ dnl # AC_KERNEL_TMP_BUILD_DIR dnl # $1: contents to be executed in a temporary directory dnl # AC_DEFUN([AC_KERNEL_TMP_BUILD_DIR], [ - local build_dir=$(mktemp -d -t build-XXXXXXXX -p .) - pushd $build_dir >/dev/null + build_dir=$(mktemp -d -t build-XXXXXXXX -p $build_dir_root) + cd $build_dir $1 - build_dir=$PWD - popd >/dev/null - AS_IF([test -s $build_dir/confdefs.h], [ - cat $build_dir/confdefs.h >>$build_dir_root/confdefs.h + AS_IF([test -s confdefs.h], [ + cat confdefs.h >>$build_dir_root/confdefs.h ]) + cd $build_dir_root rm -rf $build_dir ]) @@ -289,10 +288,10 @@ AC_DEFUN([AC_KERNEL_CHECK_SYMBOL_EXPORT], [ }' $LINUX/$file 2>/dev/null) rc=$? if test $rc -eq 0; then - (( export+=n )) + export=$(( $export+$n )) fi done - if test $(wc -w <<< "$1") -eq $export; then : + if test $(echo "$1" | wc -w) -eq $export; then : $3 else : $4 @@ -354,7 +353,7 @@ AC_DEFUN([AC_KERNEL_DO_BACKGROUND], [ AC_KERNEL_TMP_BUILD_DIR([$1]) } do_background & - procs+=( "$!" ) + procs="$! $procs" ]) dnl # @@ -363,7 +362,7 @@ dnl # wait for all tests to be finished dnl # AC_DEFUN([AC_KERNEL_WAIT], [ AC_MSG_CHECKING([for module configuration]) - wait ${procs[[@]]} + wait $procs AS_IF([[[ $? -eq 0 ]]], [ AC_MSG_RESULT([done]) ], [ From 732ef53c8cdbc517c98750c7184461e009ca1b31 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Fri, 10 Apr 2020 11:10:41 +0800 Subject: [PATCH 0052/1868] drm/amdkcl/autoconf: add AC_KERNEL_CHECK_HEADERS macro The macro uses autoconf AC_CHECK_HEADER to find kernel header files by using the preprocessor Squash of c1b19bb1c3cd drm/amdkcl: fix SUSE DKMS build a67541030f43 drm/amdkcl/autoconf: add AC_KERNEL_CHECK_HEADERS macro Signed-off-by: Slava Grigorev Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 9 +++++++++ drivers/gpu/drm/amd/dkms/pre-build.sh | 23 ++++++++++++++++++++++- 2 files changed, 31 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index ed40d9a3728a8..0f35e04f1f51c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -344,6 +344,15 @@ AC_DEFUN([AC_KERNEL_TEST_HEADER_FILE_EXIST], [ ]) ]) +dnl # +dnl # AC_KERNEL_CHECK_HEADERS +dnl # check whether header file(s) is(are) present +dnl # $1: header filei(s) to check +dnl # +AC_DEFUN([AC_KERNEL_CHECK_HEADERS], [ + AC_CHECK_HEADERS([$1],[AS_TR_CPP([HAVE_$1])=1],,[-]) +]) + dnl # dnl # AC_KERNEL_DO_BACKGROUND dnl # $1: contents to be executed diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index 264b42dd2af4d..7d1dca12d6f33 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -6,6 +6,21 @@ SRC="amd/dkms" KERNELVER=$1 KERNELVER_BASE=${KERNELVER%%-*} +SRCTREE=/lib/modules/$KERNELVER + +if [ -L $SRCTREE/source ]; then + BLDTREE="$SRCTREE/build" + SRCTREE="$SRCTREE/source" +else + SRCTREE="$SRCTREE/build" + BLDTREE="$SRCTREE" +fi + +SRCARCH=$(uname -m | sed -e "s/i.86/x86/" -e "s/x86_64/x86/" \ + -e "s/sun4u/sparc64/" -e "s/arm.*/arm/" -e "s/sa110/arm/" \ + -e "s/s390x/s390/" -e "s/parisc64/parisc/" \ + -e "s/ppc.*/powerpc/" -e "s/mips.*/mips/" \ + -e "s/sh[234].*/sh/" -e "s/aarch64.*/arm64/") version_lt () { newest=$((echo "$KERNELVER_BASE"; echo "$1") | sort -V | tail -n1) @@ -58,4 +73,10 @@ for config in $AMDGPU_CONFIG $TTM_CONFIG $SCHED_CONFIG; do done export KERNELVER -./configure +CPPFLAGS="-I$SRCTREE/arch/$SRCARCH/include \ + -I$BLDTREE/arch/$SRCARCH/include/generated \ + -I$SRCTREE/include \ + -I$BLDTREE/include \ + -I$SRCTREE/include/uapi \ + -include linux/kconfig.h" \ + ./configure From 4da353595e234fd262c8ffcadf6a4b5de72296dd Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Tue, 10 Mar 2020 13:49:38 -0400 Subject: [PATCH 0053/1868] drm/amdkcl/autoconf: add Makefile.config to DKMS code The Makefile helps developers to regenerate config.h file after changes made to either configure.ac or .m4 files Signed-off-by: Slava Grigorev --- drivers/gpu/drm/amd/dkms/Makefile.config | 40 ++++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/Makefile.config diff --git a/drivers/gpu/drm/amd/dkms/Makefile.config b/drivers/gpu/drm/amd/dkms/Makefile.config new file mode 100644 index 0000000000000..2b1a73c63bee3 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/Makefile.config @@ -0,0 +1,40 @@ +dkmstree := drivers/gpu/drm/amd/dkms +srctree := $(subst /$(dkmstree),,$(realpath $(dir $(lastword $(MAKEFILE_LIST))))) + +srcarch := $(shell uname -m | sed -e "s/i.86/x86/" -e "s/x86_64/x86/" \ + -e "s/sun4u/sparc64/" -e "s/arm.*/arm/" -e "s/sa110/arm/" \ + -e "s/s390x/s390/" -e "s/parisc64/parisc/" \ + -e "s/ppc.*/powerpc/" -e "s/mips.*/mips/" \ + -e "s/sh[234].*/sh/" -e "s/aarch64.*/arm64/") + +userinclude := \ + -I$(srctree)/arch/$(srcarch)/include/uapi \ + -I$(srctree)/arch/$(srcarch)/include/generated/uapi \ + -I$(srctree)/include/uapi \ + -I$(srctree)/include/generated/uapi \ + -include $(srctree)/include/linux/kconfig.h + +linuxinclude := \ + -I$(srctree)/arch/$(srcarch)/include \ + -I$(srctree)/arch/$(srcarch)/include/generated \ + -I$(srctree)/include \ + $(userinclude) + +all: config clean + +config: force + @( \ + cd $(srctree)/$(dkmstree); \ + ./autogen.sh; \ + CPPFLAGS="$(linuxinclude)" ./configure \ + --enable-linux-builtin \ + --with-linux=$(srctree) \ + ) + +clean: force + @( \ + cd $(srctree)/$(dkmstree); \ + rm -f aclocal.m4 config.* configure config/*.in* \ + ) + +.PHONY: all force From 76d9919408df255bcad3e938d53f29d5930c122e Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Wed, 11 Mar 2020 18:13:25 -0400 Subject: [PATCH 0054/1868] drm/amdkcl/autoconf: properly define and initialize Makefile variables 1. Properly define ..._FULL_PATH variables in amdgpu, ttm, and scheduler trees. That fixes 'make -C ... M=... modiles' build to succeed correctly. 2. Cleanup of the DKMS Makefile and modified DKMS pre-build.sh script to execute 'configure' from the original directory location It's a squash of 65727463b0e9 drm/ttm,scheduler,amdgpu: properly define and initialize Makefile variables db30b3d31f5f amd/amdkcl: fix Makefile include paths 08ebd9dfa583 amd/amdkcl: use relative path in DKMS pre-build.sh Signed-off-by: Slava Grigorev Acked-by: Jonathan Kim Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/Makefile | 6 +++--- drivers/gpu/drm/amd/dkms/Makefile | 2 +- drivers/gpu/drm/amd/dkms/dkms.conf | 2 +- drivers/gpu/drm/amd/dkms/pre-build.sh | 6 +++--- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index ba8b60ebeb195..1c9429376f66b 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -24,8 +24,8 @@ # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher. FULL_AMD_PATH := $(patsubst %/amdgpu,%,$(src)) -DISPLAY_FOLDER_NAME=display -FULL_AMD_DISPLAY_PATH = $(FULL_AMD_PATH)/$(DISPLAY_FOLDER_NAME) +DISPLAY_FOLDER_NAME := display +FULL_AMD_DISPLAY_PATH := $(FULL_AMD_PATH)/$(DISPLAY_FOLDER_NAME) ccflags-y := -I$(FULL_AMD_PATH)/include/asic_reg \ -I$(FULL_AMD_PATH)/include \ @@ -317,7 +317,7 @@ amdgpu-y += $(AMD_POWERPLAY_FILES) ifneq ($(CONFIG_DRM_AMD_DC),) -RELATIVE_AMD_DISPLAY_PATH = ../$(DISPLAY_FOLDER_NAME) +RELATIVE_AMD_DISPLAY_PATH := ../$(DISPLAY_FOLDER_NAME) include $(FULL_AMD_DISPLAY_PATH)/Makefile amdgpu-y += $(AMD_DISPLAY_FILES) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index d628e1b4340ad..f960a4375859e 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -120,7 +120,7 @@ endif export OS_NAME OS_VERSION -subdir-ccflags-y += -include $(src)/config/config.h +subdir-ccflags-y += -include $(src)/amd/dkms/config/config.h LINUXINCLUDE := \ -I$(src)/include \ diff --git a/drivers/gpu/drm/amd/dkms/dkms.conf b/drivers/gpu/drm/amd/dkms/dkms.conf index 86826daa80072..7a6075f32cb5a 100644 --- a/drivers/gpu/drm/amd/dkms/dkms.conf +++ b/drivers/gpu/drm/amd/dkms/dkms.conf @@ -2,7 +2,7 @@ PACKAGE_NAME="amdgpu" PACKAGE_VERSION="1.0" AUTOINSTALL="yes" REMAKE_INITRD="yes" -PRE_BUILD="pre-build.sh $kernelver" +PRE_BUILD="amd/dkms/pre-build.sh $kernelver" # not work with RHEL DKMS #MODULES_CONF[0]="blacklist radeon" diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index 7d1dca12d6f33..a6be48877eec8 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -73,10 +73,10 @@ for config in $AMDGPU_CONFIG $TTM_CONFIG $SCHED_CONFIG; do done export KERNELVER -CPPFLAGS="-I$SRCTREE/arch/$SRCARCH/include \ +(cd $SRC && CPPFLAGS="-I$SRCTREE/arch/$SRCARCH/include \ -I$BLDTREE/arch/$SRCARCH/include/generated \ -I$SRCTREE/include \ -I$BLDTREE/include \ -I$SRCTREE/include/uapi \ - -include linux/kconfig.h" \ - ./configure + -include $SRCTREE/include/linux/kconfig.h" \ + ./configure) From b26d03b4feebbc5edf8634804d912f2b32592afc Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 8 Jan 2021 10:29:46 +0800 Subject: [PATCH 0055/1868] drm/amdkcl/autoconf: build conftest.o directly no need to build a module v2: detect single target build capability in autoconf test instead of grep Makefile directly. Reviewed-by: Guchun Chen Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 8 ++++++-- .../gpu/drm/amd/dkms/m4/kernel_single_target.m4 | 16 ++++++++++++++++ 2 files changed, 22 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 0f35e04f1f51c..51e88cfc25d17 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -3,6 +3,7 @@ dnl # Default kernel configuration dnl # AC_DEFUN([AC_CONFIG_KERNEL], [ AC_KERNEL + AC_KERNEL_SINGLE_TARGET AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ @@ -200,6 +201,10 @@ AC_DEFUN([AC_KERNEL_COMPILE_IFELSE], [ m4_ifvaln([$1], [AC_KERNEL_CONFTEST_C([$1])]) m4_ifvaln([$6], [AC_KERNEL_CONFTEST_H([$6])], [AC_KERNEL_CONFTEST_H([])]) touch conftest.mod.c + if test "x$SINGLE_TARGET_BUILD_NO_TMP_VERSIONS" = x1; then + test -d $SINGLE_TARGET_BUILD_MODVERDIR || mkdir $SINGLE_TARGET_BUILD_MODVERDIR + rm -f $SINGLE_TARGET_BUILD_MODVERDIR/* + fi echo "obj-m := conftest.o" >Makefile kbuild_src_flag='' kbuild_modpost_flag='KBUILD_MODPOST_NOFINAL=1 KBUILD_MODPOST_WARN=1' @@ -236,8 +241,7 @@ dnl # $3: run it if compile pass. dnl # $4: run it if compile fail. dnl # AC_DEFUN([AC_KERNEL_TRY_COMPILE], - target='' - test "x$enable_linux_builtin" = xyes && target='conftest.o' + target='conftest.o' [AC_KERNEL_COMPILE_IFELSE( [AC_LANG_SOURCE([AC_KERNEL_LANG_PROGRAM([[$1]], [[$2]])])], [$target], diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 new file mode 100644 index 0000000000000..6793169a5624d --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v4.20-rc2-10-ge07db28eea38 +dnl # kbuild: fix single target build for external module +dnl # +AC_DEFUN([AC_KERNEL_SINGLE_TARGET], [ + AC_KERNEL_TMP_BUILD_DIR([ + AC_KERNEL_TRY_COMPILE([], [], [], [ + SINGLE_TARGET_BUILD_MODVERDIR=.tmp_versions + AS_IF([test ! -d $SINGLE_TARGET_BUILD_MODVERDIR], [ + SINGLE_TARGET_BUILD_NO_TMP_VERSIONS=1 + ], [ + AC_MSG_WARN([compile single target fail expectedly]) + ]) + ]) + ]) +]) From 48c70a8a09abc586f3ef02186d3152d3b45c904b Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 11 Jan 2021 14:12:52 +0800 Subject: [PATCH 0056/1868] drm/amdkcl/autoconf: extract cc&&cppflags to test header files Reviewed-by: Guchun Chen Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Makefile.config | 21 +---------- .../drm/amd/dkms/m4/kernel_single_target.m4 | 36 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/pre-build.sh | 23 +----------- 3 files changed, 38 insertions(+), 42 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/Makefile.config b/drivers/gpu/drm/amd/dkms/Makefile.config index 2b1a73c63bee3..f6d23defbaae6 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile.config +++ b/drivers/gpu/drm/amd/dkms/Makefile.config @@ -1,32 +1,13 @@ dkmstree := drivers/gpu/drm/amd/dkms srctree := $(subst /$(dkmstree),,$(realpath $(dir $(lastword $(MAKEFILE_LIST))))) -srcarch := $(shell uname -m | sed -e "s/i.86/x86/" -e "s/x86_64/x86/" \ - -e "s/sun4u/sparc64/" -e "s/arm.*/arm/" -e "s/sa110/arm/" \ - -e "s/s390x/s390/" -e "s/parisc64/parisc/" \ - -e "s/ppc.*/powerpc/" -e "s/mips.*/mips/" \ - -e "s/sh[234].*/sh/" -e "s/aarch64.*/arm64/") - -userinclude := \ - -I$(srctree)/arch/$(srcarch)/include/uapi \ - -I$(srctree)/arch/$(srcarch)/include/generated/uapi \ - -I$(srctree)/include/uapi \ - -I$(srctree)/include/generated/uapi \ - -include $(srctree)/include/linux/kconfig.h - -linuxinclude := \ - -I$(srctree)/arch/$(srcarch)/include \ - -I$(srctree)/arch/$(srcarch)/include/generated \ - -I$(srctree)/include \ - $(userinclude) - all: config clean config: force @( \ cd $(srctree)/$(dkmstree); \ ./autogen.sh; \ - CPPFLAGS="$(linuxinclude)" ./configure \ + ./configure \ --enable-linux-builtin \ --with-linux=$(srctree) \ ) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 index 6793169a5624d..ca2404840d5cb 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 @@ -1,3 +1,38 @@ +dnl # +dnl # extract cc, cflags, cppflags +dnl # +AC_DEFUN([AC_KERNEL_SINGLE_TARGET_CFLAGS], [ + AS_IF([test -s .conftest.o.cmd], [ + _base_cflags="-DKBUILD_BASENAME='\"conftest\"' -DKBUILD_MODNAME='\"conftest\"'" + _base_dir=$(basename $PWD) + _conftest_cmd=$(head -1 .conftest.o.cmd) + + CC=$(echo $_conftest_cmd | awk -F ' ' '{print $[3]}') + CFLAGS=$(echo $_conftest_cmd | \ + sed -e 's| -|\n&|g' | \ + sed -e "s|\./|${LINUX_OBJ}/|" \ + -e "s|-I\([[[a-z]]]*\)|-I${LINUX_OBJ}/\1|" \ + -e "s|-include \([[[a-z]]]*\)|-include ${LINUX_OBJ}/\1|" \ + -e '/conftest/d' \ + -e '/KBUILD_/d' \ + -e "/$_base_dir/d" | \ + xargs) + CPPFLAGS=$(echo $CFLAGS | \ + sed 's| -|\n&|g' | \ + sed -n '/-I/p; /-include/p; /-isystem/p; /-D/p' | \ + xargs) + + CFLAGS="$CFLAGS $_base_cflags" + CPPFLAGS="$CPPFLAGS $_base_cflags" + + AC_SUBST(CC) + AC_SUBST(CFLAGS) + AC_SUBST(CPPFLAGS) + ], [ + AC_MSG_ERROR([cannot detect CFLAGS...]) + ]) +]) + dnl # dnl # v4.20-rc2-10-ge07db28eea38 dnl # kbuild: fix single target build for external module @@ -12,5 +47,6 @@ AC_DEFUN([AC_KERNEL_SINGLE_TARGET], [ AC_MSG_WARN([compile single target fail expectedly]) ]) ]) + AC_KERNEL_SINGLE_TARGET_CFLAGS ]) ]) diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index a6be48877eec8..b87289082387a 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -6,21 +6,6 @@ SRC="amd/dkms" KERNELVER=$1 KERNELVER_BASE=${KERNELVER%%-*} -SRCTREE=/lib/modules/$KERNELVER - -if [ -L $SRCTREE/source ]; then - BLDTREE="$SRCTREE/build" - SRCTREE="$SRCTREE/source" -else - SRCTREE="$SRCTREE/build" - BLDTREE="$SRCTREE" -fi - -SRCARCH=$(uname -m | sed -e "s/i.86/x86/" -e "s/x86_64/x86/" \ - -e "s/sun4u/sparc64/" -e "s/arm.*/arm/" -e "s/sa110/arm/" \ - -e "s/s390x/s390/" -e "s/parisc64/parisc/" \ - -e "s/ppc.*/powerpc/" -e "s/mips.*/mips/" \ - -e "s/sh[234].*/sh/" -e "s/aarch64.*/arm64/") version_lt () { newest=$((echo "$KERNELVER_BASE"; echo "$1") | sort -V | tail -n1) @@ -73,10 +58,4 @@ for config in $AMDGPU_CONFIG $TTM_CONFIG $SCHED_CONFIG; do done export KERNELVER -(cd $SRC && CPPFLAGS="-I$SRCTREE/arch/$SRCARCH/include \ - -I$BLDTREE/arch/$SRCARCH/include/generated \ - -I$SRCTREE/include \ - -I$BLDTREE/include \ - -I$SRCTREE/include/uapi \ - -include $SRCTREE/include/linux/kconfig.h" \ - ./configure) +(cd $SRC && ./configure) From cbb8158f5da9acc0c5e7b391015878bd67959c27 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 11 Jan 2021 14:58:12 +0800 Subject: [PATCH 0057/1868] drm/amdkcl/autoconf: extract cflags to compile contest.o directly Reviewed-by: Guchun Chen Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 39 +++++++++++++++++-- .../drm/amd/dkms/m4/kernel_single_target.m4 | 2 +- 2 files changed, 36 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 51e88cfc25d17..0593e48224aaa 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -189,7 +189,7 @@ $2 ]) dnl # -dnl # AC_KERNEL_COMPILE_IFELSE / like AC_COMPILE_IFELSE +dnl # AC_KERNEL_COMPILE_MODULE_IFELSE / like AC_COMPILE_IFELSE dnl # $1: contents to be filled in conftest.c dnl # $2: make target. dnl # $3: user defined commands. It "AND" the make command to check the result. If true, expands to $4. Otherwise $5. @@ -197,7 +197,7 @@ dnl # $4: run it if make & $3 pass. dnl # $5: run it if make & $3 fail. dnl # $6: contents to be filled in conftest.h. Could be null. dnl # -AC_DEFUN([AC_KERNEL_COMPILE_IFELSE], [ +AC_DEFUN([AC_KERNEL_COMPILE_MODULE_IFELSE], [ m4_ifvaln([$1], [AC_KERNEL_CONFTEST_C([$1])]) m4_ifvaln([$6], [AC_KERNEL_CONFTEST_H([$6])], [AC_KERNEL_CONFTEST_H([])]) touch conftest.mod.c @@ -233,6 +233,39 @@ AC_DEFUN([AC_KERNEL_TMP_BUILD_DIR], [ rm -rf $build_dir ]) +dnl # +dnl # AC_KERNEL_TRY_COMPILE_MODULE like AC_TRY_COMPILE +dnl # $1: Prologue for conftest.c. including header files, extends, etc +dnl # $2: Body for conftest.c. +dnl # $3: run it if compile pass. +dnl # $4: run it if compile fail. +dnl # +AC_DEFUN([AC_KERNEL_TRY_COMPILE_MODULE], + target='conftest.o' + [AC_KERNEL_COMPILE_MODULE_IFELSE( + [AC_LANG_SOURCE([AC_KERNEL_LANG_PROGRAM([[$1]], [[$2]])])], + [$target], + [test -s conftest.o], + [$3], [$4]) +]) + +dnl # +dnl # AC_KERNEL_COMPILE_IFELSE / like AC_COMPILE_IFELSE +dnl # $1: contents to be filled in conftest.c +dnl # $2: user defined commands. It "AND" the make command to check the result. If true, expands to $4. Otherwise $5. +dnl # $3: run it if make & $3 pass. +dnl # $4: run it if make & $3 fail. +dnl # $5: contents to be filled in conftest.h. Could be null. +dnl # +AC_DEFUN([AC_KERNEL_COMPILE_IFELSE], [ + m4_ifvaln([$1], [AC_KERNEL_CONFTEST_C([$1])]) + m4_ifvaln([$5], [AC_KERNEL_CONFTEST_H([$5])], [AC_KERNEL_CONFTEST_H([])]) + AS_IF( + [AC_TRY_COMMAND($CC $CFLAGS -o conftest.o conftest.c) >/dev/null && AC_TRY_COMMAND([$2])], + [$3], + [_AC_MSG_LOG_CONFTEST m4_ifvaln([$4],[$4])] + ) +]) dnl # dnl # AC_KERNEL_TRY_COMPILE like AC_TRY_COMPILE dnl # $1: Prologue for conftest.c. including header files, extends, etc @@ -241,10 +274,8 @@ dnl # $3: run it if compile pass. dnl # $4: run it if compile fail. dnl # AC_DEFUN([AC_KERNEL_TRY_COMPILE], - target='conftest.o' [AC_KERNEL_COMPILE_IFELSE( [AC_LANG_SOURCE([AC_KERNEL_LANG_PROGRAM([[$1]], [[$2]])])], - [$target], [test -s conftest.o], [$3], [$4]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 index ca2404840d5cb..7eb3fe010ee93 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 @@ -39,7 +39,7 @@ dnl # kbuild: fix single target build for external module dnl # AC_DEFUN([AC_KERNEL_SINGLE_TARGET], [ AC_KERNEL_TMP_BUILD_DIR([ - AC_KERNEL_TRY_COMPILE([], [], [], [ + AC_KERNEL_TRY_COMPILE_MODULE([], [], [], [ SINGLE_TARGET_BUILD_MODVERDIR=.tmp_versions AS_IF([test ! -d $SINGLE_TARGET_BUILD_MODVERDIR], [ SINGLE_TARGET_BUILD_NO_TMP_VERSIONS=1 From 73ebebb6ce362265b6a8806effb9952b92e6658a Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 13 Jan 2021 14:18:20 +0800 Subject: [PATCH 0058/1868] drm/amdkcl/autoconf: rework *FLAGS_.o handle of path Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 | 12 ++++++++++++ drivers/gpu/drm/amd/dkms/pre-build.sh | 7 +++++++ 2 files changed, 19 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 index 7eb3fe010ee93..b4af835c8928f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 @@ -33,6 +33,17 @@ AC_DEFUN([AC_KERNEL_SINGLE_TARGET_CFLAGS], [ ]) ]) +dnl # +dnl # v5.3-rc4-54-g54b8ae66ae1a +dnl # kbuild: change *FLAGS_.o to take the path relative to $(obj) +dnl # +AC_DEFUN([AC_KERNEL_FLAGS_TAKE_PATH], [ + AS_IF([grep -qsm 1 "target-stem" ${LINUX}/scripts/Makefile.lib], [ + AC_DEFINE(HAVE_AMDKCL_FLAGS_TAKE_PATH, 1, + [*FLAGS_.o support to take the path relative to $(obj)]) + ]) +]) + dnl # dnl # v4.20-rc2-10-ge07db28eea38 dnl # kbuild: fix single target build for external module @@ -48,5 +59,6 @@ AC_DEFUN([AC_KERNEL_SINGLE_TARGET], [ ]) ]) AC_KERNEL_SINGLE_TARGET_CFLAGS + AC_KERNEL_FLAGS_TAKE_PATH ]) ]) diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index b87289082387a..745124a028bc7 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -59,3 +59,10 @@ done export KERNELVER (cd $SRC && ./configure) + +# rename CFLAGS_target.o to CFLAGS_target.o +if ! grep -q 'define HAVE_AMDKCL_FLAGS_TAKE_PATH' $SRC/config/config.h; then + for file in $(grep -rl 'CFLAGS_' amd/display/); do + sed -i 's|$(AMDDALPATH)/.*/\(.*\.o\)|\1|' $file + done +fi From eada38d3645964ffb8590db51f89e8b95be4a02b Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Tue, 24 Mar 2020 19:24:29 -0400 Subject: [PATCH 0059/1868] drm/amdkcl/autoconf: add includes config.h in Makefile It's a squash of 70619a89cb10 amd/amdkcl: drop BUILD_AS_DKMS compilation flag 9bdcf23b7b68 drm/amdkcl: drop DKMS build when in the source tree 4304e2beb859 amd/amdkcl: clean up includes in backport/Makefile Signed-off-by: Slava Grigorev Reviewed-by: Flora Cui Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/Makefile | 5 +++++ drivers/gpu/drm/amd/backport/Makefile | 7 ++++++- drivers/gpu/drm/amd/dkms/Makefile | 2 -- drivers/gpu/drm/scheduler/backport/Makefile | 2 ++ drivers/gpu/drm/ttm/backport/Makefile | 4 ++++ 5 files changed, 17 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 018792c49a249..5dcd2f97fc29b 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -1,4 +1,9 @@ # SPDX-License-Identifier: MIT amdkcl-y += main.o +ccflags-y += \ + -include $(src)/../dkms/config/config.h + +ccflags-y += -DHAVE_CONFIG_H + obj-m += amdkcl.o diff --git a/drivers/gpu/drm/amd/backport/Makefile b/drivers/gpu/drm/amd/backport/Makefile index ca667992f6f72..1ad8a02a4b19f 100644 --- a/drivers/gpu/drm/amd/backport/Makefile +++ b/drivers/gpu/drm/amd/backport/Makefile @@ -4,5 +4,10 @@ BACKPORT_OBJS := amdgpu-y += $(addprefix ../backport/,$(BACKPORT_OBJS)) ccflags-y += \ + -I$(FULL_AMD_PATH) \ -I$(FULL_AMD_PATH)/backport/include \ - -include ../backport/backport.h + -I$(FULL_AMD_PATH)/dkms \ + -include config/config.h \ + -include backport/backport.h + +ccflags-y += -DHAVE_CONFIG_H diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index f960a4375859e..ce753462ac58c 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -120,8 +120,6 @@ endif export OS_NAME OS_VERSION -subdir-ccflags-y += -include $(src)/amd/dkms/config/config.h - LINUXINCLUDE := \ -I$(src)/include \ -I$(src)/include/uapi \ diff --git a/drivers/gpu/drm/scheduler/backport/Makefile b/drivers/gpu/drm/scheduler/backport/Makefile index 5fe7a0b580f33..01bf391770a05 100644 --- a/drivers/gpu/drm/scheduler/backport/Makefile +++ b/drivers/gpu/drm/scheduler/backport/Makefile @@ -1,4 +1,6 @@ # SPDX-License-Identifier: MIT ccflags-y += \ -I$(SCHED_FULL_PATH) \ + -I$(SCHED_FULL_PATH)/../amd/dkms \ + -include config/config.h \ -include backport/backport.h diff --git a/drivers/gpu/drm/ttm/backport/Makefile b/drivers/gpu/drm/ttm/backport/Makefile index 839110332c785..0ccfec344b665 100644 --- a/drivers/gpu/drm/ttm/backport/Makefile +++ b/drivers/gpu/drm/ttm/backport/Makefile @@ -1,4 +1,8 @@ # SPDX-License-Identifier: MIT ccflags-y += \ -I$(TTM_FULL_PATH) \ + -I$(TTM_FULL_PATH)/../amd/dkms \ + -include config/config.h \ -include backport/backport.h + +ccflags-y += -DHAVE_CONFIG_H From 4be4ad9ca5d29f45d65a58e29a2e502c99a1cc37 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 20 Jan 2021 17:58:01 +0800 Subject: [PATCH 0060/1868] drm/amdkcl: fix include path for dkms package Reviewed-by: Guchun Chen Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Makefile | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index ce753462ac58c..7c227452be97c 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -120,12 +120,20 @@ endif export OS_NAME OS_VERSION +LINUX_SRCTREE_INCLUDE := \ + $(filter-out -I%/uapi -include %/kconfig.h,$(LINUXINCLUDE)) +USER_INCLUDE := $(filter-out $(LINUX_SRCTREE_INCLUDE), $(LINUXINCLUDE)) + LINUXINCLUDE := \ -I$(src)/include \ - -I$(src)/include/uapi \ + -I$(src)/include/kcl/header \ -include $(src)/include/kcl/kcl_version.h \ -include $(src)/include/rename_symbol.h \ - $(LINUXINCLUDE) + -include $(src)/amd/dkms/config/config.h \ + $(LINUX_SRCTREE_INCLUDE) \ + -I$(src)/include/uapi \ + -I$(src)/include/kcl/header/uapi \ + $(USER_INCLUDE) export CONFIG_HSA_AMD=y export CONFIG_DRM_TTM=m From 33134fd1067cfacf5764727ac5b635ffb9f59296 Mon Sep 17 00:00:00 2001 From: Jeremy Newton Date: Fri, 9 Mar 2018 11:23:15 -0500 Subject: [PATCH 0061/1868] drm/amdkcl: Add wattman example script Signed-off-by: Jeremy Newton Acked-by: Slava Grigorev --- .../dkms/docs/examples/wattman-example-script | 74 +++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/docs/examples/wattman-example-script diff --git a/drivers/gpu/drm/amd/dkms/docs/examples/wattman-example-script b/drivers/gpu/drm/amd/dkms/docs/examples/wattman-example-script new file mode 100644 index 0000000000000..90b14faec6dbf --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/docs/examples/wattman-example-script @@ -0,0 +1,74 @@ +## wattman-like functionality +# boot with amdgpu.ppfeaturemask=0xffffffff (make sure PP_OVERDRIVE_MASK bit is set see hwmgr.h) +# see the current dpm clock and voltage levels +cat /sys/class/drm/card0/device/pp_od_clk_voltage +#OD_SCLK: +#0: 300Mhz 900 mV +#1: 484Mhz 925 mV +#2: 709Mhz 962 mV +#3: 858Mhz 1112 mV +#4: 891Mhz 1150 mV +#5: 917Mhz 1175 mV +#6: 949Mhz 1175 mV +#7: 973Mhz 1175 mV +#OD_MCLK: +#0: 150Mhz 900 mV +#1: 1375Mhz 975 mV +# change mclk dpm level 0 from 150 to 155Mhz, no change to voltage +# format is "m dpm_level clock_in_mhz voltage_in_mv" +echo "m 0 155 900" > /sys/class/drm/card0/device/pp_od_clk_voltage +# change sclk dpm level 7 from 973 to 975Mhz, change voltage from 1175 to 1180 mV +# format is "s dpm_level clock_in_mhz voltage_in_mv" +echo "s 7 975 1180" > /sys/class/drm/card0/device/pp_od_clk_voltage +# change sclk dpm level 5 from 917 to 910Mhz, change voltage from 1175 to 1160 mV +# format is "s dpm_level clock_in_mhz voltage_in_mv" +echo "s 7 910 1160" > /sys/class/drm/card0/device/pp_od_clk_voltage +# see the current dpm clock and voltage levels +cat /sys/class/drm/card0/device/pp_od_clk_voltage +#OD_SCLK: +#0: 300Mhz 900 mV +#1: 484Mhz 925 mV +#2: 709Mhz 962 mV +#3: 858Mhz 1112 mV +#4: 891Mhz 1150 mV +#5: 910Mhz 1160 mV +#6: 949Mhz 1175 mV +#7: 975Mhz 1180 mV +#OD_MCLK: +#0: 155Mhz 900 mV +#1: 1375Mhz 975 mV +# commit the changes to the hw +echo "c" > /sys/class/drm/card0/device/pp_od_clk_voltage +# reset to the default dpm states +echo "r" > /sys/class/drm/card0/device/pp_od_clk_voltage +# commit the reset state to the hw +echo "c" > /sys/class/drm/card0/device/pp_od_clk_voltage + +## reading/adjusting hwmon values +# https://www.kernel.org/doc/Documentation/hwmon/sysfs-interface +# see which hwmon device this is +cat /sys/class/hwmon/hwmon0/name +# readback current vddgfx/vddnb voltages +# see which one this is +cat /sys/class/hwmon/hwmon0/in0_label +# read the voltage (mV) +cat /sys/class/hwmon/hwmon0/in0_input +# see current power (microwatts) +cat /sys/class/hwmon/hwmon0/power1_average +# current temp (millidegrees C) +cat /sys/class/hwmon/hwmon0/temp1_input +# see fan speed (rpm) +cat /sys/class/hwmon/hwmon0/fan1_input +# see fan speed pwm (0-255) +cat /sys/class/hwmon/hwmon0/pwm1 +# see min/max pwm limits +cat /sys/class/hwmon/hwmon0/pwm1_min +cat /sys/class/hwmon/hwmon0/pwm1_max +# see current fan control mode (0 none, 1 manual fan control, 2 dynamic fan control) +cat /sys/class/hwmon/hwmon0/pwm1_enable +# enable manual fan control +echo 1 > /sys/class/hwmon/hwmon0/pwm1_enable +# manually set the fan speed (100/255 = 39%) +echo 100 > /sys/class/hwmon/hwmon0/pwm1 +# enable automatic fan control +echo 2 > /sys/class/hwmon/hwmon0/pwm1_enable From e8d6251be3b4637546f77c00523ec2186460c8d2 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 17 Dec 2020 16:55:26 +0800 Subject: [PATCH 0062/1868] drm/amdkcl: add prefix for amdkcl log Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/Makefile | 3 ++- drivers/gpu/drm/amd/amdkcl/kcl_common.h | 10 ++++++++++ 2 files changed, 12 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_common.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 5dcd2f97fc29b..0bed0b09bc09f 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -2,7 +2,8 @@ amdkcl-y += main.o ccflags-y += \ - -include $(src)/../dkms/config/config.h + -include $(src)/../dkms/config/config.h \ + -include $(src)/kcl_common.h ccflags-y += -DHAVE_CONFIG_H diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_common.h b/drivers/gpu/drm/amd/amdkcl/kcl_common.h new file mode 100644 index 0000000000000..d547bd5608e47 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_common.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef AMDKCL_COMMON_H +#define AMDKCL_COMMON_H + +#ifdef pr_fmt +#undef pr_fmt +#endif +#define pr_fmt(fmt) "amdkcl: " fmt + +#endif From 96ebd2da9788ccc5d17e7bb8c59833f53f0a4a20 Mon Sep 17 00:00:00 2001 From: Junwei Zhang Date: Fri, 8 Nov 2019 12:14:03 +0800 Subject: [PATCH 0063/1868] drm/amdkcl: add lookpup unexported symbol support v2: test kallsyms_lookup_name() is exported. v3: fix awk syntax to find kallsyms_lookup_name() addr. v4: use kprobe to find out kallsyms_lookup_name() Signed-off-by: Junwei Zhang Reviewed-by: Qiang Yu Signed-off-by: Flora Cui Signed-off-by: Chengming Gui Reviewed-by: Flora Cui Signed-off-by: Jack Gui Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_common.c | 49 +++++++++++++++++++ drivers/gpu/drm/amd/amdkcl/kcl_common.h | 5 ++ drivers/gpu/drm/amd/amdkcl/main.c | 3 ++ .../drm/amd/dkms/m4/kallsyms-lookup-name.m4 | 14 ++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/pre-build.sh | 2 +- 7 files changed, 74 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_common.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/kallsyms-lookup-name.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 0bed0b09bc09f..a805915aba6b9 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: MIT -amdkcl-y += main.o +amdkcl-y += main.o symbols.o kcl_common.o ccflags-y += \ -include $(src)/../dkms/config/config.h \ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_common.c b/drivers/gpu/drm/amd/amdkcl/kcl_common.c new file mode 100644 index 0000000000000..5867b4d1a6c38 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_common.c @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: MIT */ +#include +#include +#include +#include +#include + +unsigned long (*_kcl_kallsyms_lookup_name)(const char *name); + +void *amdkcl_fp_setup(const char *symbol, void *dummy) +{ + unsigned long addr; + void *fp = dummy; + + addr = _kcl_kallsyms_lookup_name(symbol); + if (addr == 0) { + if (fp) + pr_warn("Warning: fail to get symbol %s, replace it with kcl stub\n", symbol); + else { + pr_err("Error: fail to get symbol %s, abort...\n", symbol); + BUG(); + } + } else { + fp = (void *)addr; + } + + return fp; +} + +void amdkcl_symbol_init(void) +{ +#ifndef HAVE_KALLSYMS_LOOKUP_NAME + struct kprobe kp; + int r; + + memset(&kp, 0, sizeof(kp)); + kp.symbol_name = "kallsyms_lookup_name"; + r = register_kprobe(&kp); + if (!r) { + _kcl_kallsyms_lookup_name = (void *)kp.addr; + unregister_kprobe(&kp); + } else { + pr_err("fail to get kallsyms_lookup_name, abort...\n"); + BUG(); + } +#else + _kcl_kallsyms_lookup_name = kallsyms_lookup_name; +#endif +} diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_common.h b/drivers/gpu/drm/amd/amdkcl/kcl_common.h index d547bd5608e47..de8bdd481dc98 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_common.h +++ b/drivers/gpu/drm/amd/amdkcl/kcl_common.h @@ -2,9 +2,14 @@ #ifndef AMDKCL_COMMON_H #define AMDKCL_COMMON_H +#include +#include + #ifdef pr_fmt #undef pr_fmt #endif #define pr_fmt(fmt) "amdkcl: " fmt +void *amdkcl_fp_setup(const char *symbol, void *dummy); + #endif diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c index 59f4520c9a8bd..4a0f67981e1c4 100644 --- a/drivers/gpu/drm/amd/amdkcl/main.c +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -2,8 +2,11 @@ #include #include +extern void amdkcl_symbol_init(void); + int __init amdkcl_init(void) { + amdkcl_symbol_init(); return 0; } module_init(amdkcl_init); diff --git a/drivers/gpu/drm/amd/dkms/m4/kallsyms-lookup-name.m4 b/drivers/gpu/drm/amd/dkms/m4/kallsyms-lookup-name.m4 new file mode 100644 index 0000000000000..62e540f41a7df --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/kallsyms-lookup-name.m4 @@ -0,0 +1,14 @@ +dnl # +dnl # v5.6-11591-g0bd476e6c671 kallsyms: unexport kallsyms_lookup_name() and kallsyms_on_each_symbol() +dnl # v2.6.32-rc4-272-gf60d24d2ad04 hw-breakpoints: Fix broken hw-breakpoint sample module +dnl # +AC_DEFUN([AC_AMDGPU_KALLSYMS_LOOKUP_NAME], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([kallsyms_lookup_name], + [kernel/kallsyms.c], + [ + AC_DEFINE(HAVE_KALLSYMS_LOOKUP_NAME, 1, + [kallsyms_lookup_name is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 0593e48224aaa..d3555facee09e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -4,6 +4,7 @@ dnl # AC_DEFUN([AC_CONFIG_KERNEL], [ AC_KERNEL AC_KERNEL_SINGLE_TARGET + AC_AMDGPU_KALLSYMS_LOOKUP_NAME AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index 745124a028bc7..698e69b364c03 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -33,7 +33,7 @@ source $KCL/files # lookup symbol address. obsolete. echo '// auto generated by DKMS pre-build.sh' > $KCL/symbols.c for sym in $SYMS; do - awk -v sym=$sym '/\/ { + awk -v sym=$sym '$3 == sym { print "void *_kcl_" $3 " = (void *)0x" $1 ";" }' /boot/System.map-$KERNELVER >>$KCL/symbols.c done From 4504fa37b014b4fecfad3d9c52ba834aadf59d82 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 13 May 2020 15:41:04 +0800 Subject: [PATCH 0064/1868] drm/amdkcl: create dummy func for funcs unavailable Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang --- drivers/gpu/drm/amd/amdkcl/kcl_common.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_common.h b/drivers/gpu/drm/amd/amdkcl/kcl_common.h index de8bdd481dc98..9c9eca94212b9 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_common.h +++ b/drivers/gpu/drm/amd/amdkcl/kcl_common.h @@ -12,4 +12,15 @@ void *amdkcl_fp_setup(const char *symbol, void *dummy); +/* + * create dummy func + */ +#define amdkcl_dummy_symbol(name, ret_type, ret, ...) \ +ret_type name(__VA_ARGS__) \ +{ \ + pr_warn_once("%s is not supported\n", #name); \ + ret ;\ +} \ +EXPORT_SYMBOL(name); + #endif From f6c2c9feb5d0bae7a9002d6e7a0cb1ea91532d34 Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Mon, 13 Apr 2020 21:51:37 +0800 Subject: [PATCH 0065/1868] drm/amdkcl: add AC_AMDGPU_LINUX_HEADERS it is a squash of: 5ded515e0816 drm/amdkcl: update test for linux/dma-resv.h 0b63eb175dbb drm/amdkcl: drop individual tests for header files 221c1ea7b3db drm/amdkcl: fix license c444a2fe2e49 drm/amdkcl: move kcl wrapper for linux header to header dir 627af54ab135 drm/amdkcl: add AC_AMDGPU_LINUX_HEADERS Signed-off-by: Slava Grigorev Reviewed-by: Flora Cui Signed-off-by: Yifan Zhang Signed-off-by: Flora Cui Reviewed-by: Jack Gui Reviewed-by: Yifan Zhang Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 | 75 +++++++++++++++++++ include/kcl/header/asm/set_memory.h | 11 +++ include/kcl/header/linux/bits.h | 11 +++ include/kcl/header/linux/dma-buf-map.h | 9 +++ .../kcl/header/linux/io-64-nonatomic-lo-hi.h | 11 +++ include/kcl/header/linux/pci-p2pdma.h | 9 +++ include/kcl/header/uapi/linux/sched/types.h | 9 +++ 8 files changed, 136 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 create mode 100644 include/kcl/header/asm/set_memory.h create mode 100644 include/kcl/header/linux/bits.h create mode 100644 include/kcl/header/linux/dma-buf-map.h create mode 100644 include/kcl/header/linux/io-64-nonatomic-lo-hi.h create mode 100644 include/kcl/header/linux/pci-p2pdma.h create mode 100644 include/kcl/header/uapi/linux/sched/types.h diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index d3555facee09e..6f85d0821c5f3 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -4,6 +4,7 @@ dnl # AC_DEFUN([AC_CONFIG_KERNEL], [ AC_KERNEL AC_KERNEL_SINGLE_TARGET + AC_AMDGPU_LINUX_HEADERS AC_AMDGPU_KALLSYMS_LOOKUP_NAME AC_KERNEL_WAIT diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 new file mode 100644 index 0000000000000..38b46427e3689 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 @@ -0,0 +1,75 @@ +AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ + + dnl # + dnl # commit 8bd9cb51daac89337295b6f037b0486911e1b408 + dnl # locking/atomics, asm-generic: Move some macros from + dnl # to a new file + dnl # + AC_KERNEL_CHECK_HEADERS([linux/bits.h]) + + dnl # + dnl # commit v4.3-rc4-1-g2f8e2c877784 + dnl # move io-64-nonatomic*.h out of asm-generic + dnl # + AC_KERNEL_CHECK_HEADERS([linux/io-64-nonatomic-lo-hi.h]) + + dnl # + dnl # commit 299878bac326c890699c696ebba26f56fe93fc75 + dnl # treewide: move set_memory_* functions away from cacheflush.h + dnl # + AC_KERNEL_CHECK_HEADERS([asm/set_memory.h]) + + dnl # + dnl # commit df6b35f409af0a8ff1ef62f552b8402f3fef8665 + dnl # x86/fpu: Rename i387.h to fpu/api.h + dnl # + AC_KERNEL_CHECK_HEADERS([asm/fpu/api.h]) + + dnl # + dnl # commit 607ca46e97a1b6594b29647d98a32d545c24bdff + dnl # UAPI: (Scripted) Disintegrate include/linux + dnl # + AC_KERNEL_CHECK_HEADERS([uapi/linux/sched/types.h]) + + dnl # + dnl # v4.19-rc6-7-ga3f8a30f3f00 + dnl # Compiler Attributes: use feature checks instead of version checks + dnl # + AC_KERNEL_CHECK_HEADERS([linux/compiler_attributes.h]) + + dnl # + dnl # v4.9-rc2-299-gf54d1867005c + dnl # dma-buf: Rename struct fence to dma_fence + dnl # + AC_KERNEL_CHECK_HEADERS([linux/dma-fence.h]) + + dnl # + dnl # v5.3-rc1-449-g52791eeec1d9 + dnl $ dma-buf: rename reservation_object to dma_resv + dnl # + AC_KERNEL_CHECK_HEADERS([linux/dma-resv.h]) + + dnl # + dnl # v5.7-13149-g9740ca4e95b4 + dnl # mmap locking API: initial implementation as rwsem wrappers + dnl # + AC_KERNEL_CHECK_HEADERS([linux/mmap_lock.h]) + + dnl # + dnl # v4.19-rc4-1-g52916982af48 + dnl # PCI/P2PDMA: Support peer-to-peer memory + dnl # + AC_KERNEL_CHECK_HEADERS([linux/pci-p2pdma.h]) + + dnl # + dnl # v4.7-11546-g00085f1efa38 + dnl # dma-mapping: use unsigned long for dma_attrs + dnl # + AC_KERNEL_CHECK_HEADERS([linux/dma-attrs.h]) + + dnl # + dnl # 01fd30da0474 + dnl # dma-buf: Add struct dma-buf-map for storing struct dma_buf.vaddr_ptr + dnl # + AC_KERNEL_CHECK_HEADERS([linux/dma-buf-map.h]) +]) diff --git a/include/kcl/header/asm/set_memory.h b/include/kcl/header/asm/set_memory.h new file mode 100644 index 0000000000000..4614c4c1c4630 --- /dev/null +++ b/include/kcl/header/asm/set_memory.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER__ASM_SET_MEMORY_H_H_ +#define _KCL_HEADER__ASM_SET_MEMORY_H_H_ + +#if defined(HAVE_ASM_SET_MEMORY_H) +#include_next +#else +#include +#endif + +#endif diff --git a/include/kcl/header/linux/bits.h b/include/kcl/header/linux/bits.h new file mode 100644 index 0000000000000..28a84955dc780 --- /dev/null +++ b/include/kcl/header/linux/bits.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER__LINUX_BITS_H_H_ +#define _KCL_HEADER__LINUX_BITS_H_H_ + +#if defined(HAVE_LINUX_BITS_H) +#include_next +#else +#include +#endif + +#endif diff --git a/include/kcl/header/linux/dma-buf-map.h b/include/kcl/header/linux/dma-buf-map.h new file mode 100644 index 0000000000000..523dfcfabda8b --- /dev/null +++ b/include/kcl/header/linux/dma-buf-map.h @@ -0,0 +1,9 @@ +#ifndef _KCL_HEADER___DMA_BUF_MAP_H___H_ +#define _KCL_HEADER___DMA_BUF_MAP_H___H_ + +#ifdef HAVE_LINUX_DMA_BUF_MAP_H +#include_next +#endif + +#endif + diff --git a/include/kcl/header/linux/io-64-nonatomic-lo-hi.h b/include/kcl/header/linux/io-64-nonatomic-lo-hi.h new file mode 100644 index 0000000000000..0fa2e108091b7 --- /dev/null +++ b/include/kcl/header/linux/io-64-nonatomic-lo-hi.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_LINUX_IO_64_NONATOMIC_LO_HI_H_H_ +#define _KCL_HEADER_LINUX_IO_64_NONATOMIC_LO_HI_H_H_ + +#ifdef HAVE_LINUX_IO_64_NONATOMIC_LO_HI_H +#include_next +#else +#include +#endif + +#endif diff --git a/include/kcl/header/linux/pci-p2pdma.h b/include/kcl/header/linux/pci-p2pdma.h new file mode 100644 index 0000000000000..84ad226012bdc --- /dev/null +++ b/include/kcl/header/linux/pci-p2pdma.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_LINUX_PCI_P2PDMA_H_H_ +#define _KCL_HEADER_LINUX_PCI_P2PDMA_H_H_ + +#ifdef HAVE_LINUX_PCI_P2PDMA_H +#include_next +#endif + +#endif diff --git a/include/kcl/header/uapi/linux/sched/types.h b/include/kcl/header/uapi/linux/sched/types.h new file mode 100644 index 0000000000000..871f2abf23d37 --- /dev/null +++ b/include/kcl/header/uapi/linux/sched/types.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_UAPI_LINUX_SCHED_TYPES_H_H_ +#define _KCL_HEADER_UAPI_LINUX_SCHED_TYPES_H_H_ + +#ifdef HAVE_UAPI_LINUX_SCHED_TYPES_H +#include_next +#endif + +#endif From da596973d3b04714b55451a679f8b061e253b111 Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Mon, 13 Apr 2020 21:53:07 +0800 Subject: [PATCH 0066/1868] drm/amdkcl: add AC_AMDGPU_DRM_HEADERS v2: test for drm/drm_backport.h (Flora.Cui@amd.com) RHEL 7.x wraps some API in drm/drm_backport.h header file Signed-off-by: Yifan Zhang Signed-off-by: Flora Cui Reviewed-by: Jack Gui Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang Signed-off-by: Slava Grigorev Reviewed-by: Flora Cui Change-Id: I2717f0cfb3caaeb93f409656c6ce7c88fecc36de Reviewed-by: Yang Xiong Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 41 ++++++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/header/drm/drmP.h | 9 +++++ include/kcl/header/drm/drm_managed.h | 9 +++++ include/kcl/header/drm/drm_print.h | 10 ++++++ include/kcl/header/drm/drm_probe_helper.h | 11 ++++++ include/kcl/header/drm/task_barrier.h | 9 +++++ 7 files changed, 90 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 create mode 100644 include/kcl/header/drm/drmP.h create mode 100644 include/kcl/header/drm/drm_managed.h create mode 100644 include/kcl/header/drm/drm_print.h create mode 100644 include/kcl/header/drm/drm_probe_helper.h create mode 100644 include/kcl/header/drm/task_barrier.h diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 new file mode 100644 index 0000000000000..5db23c22d9fe3 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -0,0 +1,41 @@ +AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ + dnl # + dnl # RHEL 7.x wrapper + dnl # + AC_KERNEL_CHECK_HEADERS([drm/drm_backport.h]) + + dnl # + dnl # Optional devices ID for amdgpu driver + dnl # + AC_KERNEL_CHECK_HEADERS([drm/amdgpu_pciid.h]) + + dnl # + dnl # commit v4.9-rc2-477-gd8187177b0b1 + dnl # drm: add helper for printing to log or seq_file + dnl # + AC_KERNEL_CHECK_HEADERS([drm/drm_print.h]) + + dnl # + dnl # commit v5.0-rc1-342-gfcd70cd36b9b + dnl # drm: Split out drm_probe_helper.h + dnl # + AC_KERNEL_CHECK_HEADERS([drm/drm_probe_helper.h]) + + dnl # + dnl # v5.4-rc1-214-g4e98f871bcff + dnl # drm: delete drmP.h + drm_os_linux.h + dnl # + AC_KERNEL_CHECK_HEADERS([drm/drmP.h]) + + dnl # + dnl # commit v5.5-rc2-783-g368fd0aad1be + dnl # drm: Add Reusable task barrier. + dnl # + AC_KERNEL_CHECK_HEADERS([drm/task_barrier.h]) + + dnl # + dnl # v5.6-rc5-1258-gc6603c740e0e + dnl # drm: add managed resources tied to drm_device + dnl # + AC_KERNEL_CHECK_HEADERS([drm/drm_managed.h]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 6f85d0821c5f3..a61ba77924c84 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -5,6 +5,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_KERNEL AC_KERNEL_SINGLE_TARGET AC_AMDGPU_LINUX_HEADERS + AC_AMDGPU_DRM_HEADERS AC_AMDGPU_KALLSYMS_LOOKUP_NAME AC_KERNEL_WAIT diff --git a/include/kcl/header/drm/drmP.h b/include/kcl/header/drm/drmP.h new file mode 100644 index 0000000000000..008236685b081 --- /dev/null +++ b/include/kcl/header/drm/drmP.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DRMP_H_H_ +#define _KCL_HEADER_DRMP_H_H_ + +#ifdef HAVE_DRM_DRMP_H +#include_next +#endif + +#endif diff --git a/include/kcl/header/drm/drm_managed.h b/include/kcl/header/drm/drm_managed.h new file mode 100644 index 0000000000000..d6f211d64b346 --- /dev/null +++ b/include/kcl/header/drm/drm_managed.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_KCL_DRM_MANAGED_H_H +#define _KCL_HEADER_KCL_DRM_MANAGED_H_H + +#ifdef HAVE_DRM_DRM_MANAGED_H +#include_next +#endif + +#endif diff --git a/include/kcl/header/drm/drm_print.h b/include/kcl/header/drm/drm_print.h new file mode 100644 index 0000000000000..0f1db6376a8a3 --- /dev/null +++ b/include/kcl/header/drm/drm_print.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DRM_PRINT_H_H_ +#define _KCL_HEADER_DRM_PRINT_H_H_ + +#if defined(HAVE_DRM_DRM_PRINT_H) +#include_next +#endif +#include + +#endif diff --git a/include/kcl/header/drm/drm_probe_helper.h b/include/kcl/header/drm/drm_probe_helper.h new file mode 100644 index 0000000000000..a454fe92ea203 --- /dev/null +++ b/include/kcl/header/drm/drm_probe_helper.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DRM_PROBE_HELPER_H_H_ +#define _KCL_HEADER_DRM_PROBE_HELPER_H_H_ + +#ifdef HAVE_DRM_DRM_PROBE_HELPER_H +#include_next +#else +#include +#endif + +#endif diff --git a/include/kcl/header/drm/task_barrier.h b/include/kcl/header/drm/task_barrier.h new file mode 100644 index 0000000000000..e93315f493f3e --- /dev/null +++ b/include/kcl/header/drm/task_barrier.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DRM_TASK_BARRIER_H_H_ +#define _KCL_HEADER_DRM_TASK_BARRIER_H_H_ + +#ifdef HAVE_DRM_TASK_BARRIER_H +#include_next +#endif + +#endif From 0304762a34d00e4df84ac81b0e44da2b813744d8 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 3 Feb 2021 11:07:04 +0800 Subject: [PATCH 0067/1868] drm/amdkcl: DROPME: include amdgpu_amdkfd.h in kfd_priv.h Change-Id: Ia5f684b21b7cbd3cc98b048cf8a586a6b79c46f1 Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index f7c12d4f0abb9..c60c0623287bf 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -46,6 +46,7 @@ #include #include +#include "amdgpu_amdkfd.h" #include "amd_shared.h" #include "amdgpu.h" From 448cecfe8f58fffb49d8bb8868af89ed57b87f47 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 9 Mar 2021 09:59:48 +0800 Subject: [PATCH 0068/1868] drm/amdkcl: DROPME: include linux/sched/mm.h in ttm_tt.c Change-Id: I3cbc5f6e03c28c7db1895cb8d2015e5f698546ee Signed-off-by: Flora Cui --- drivers/gpu/drm/ttm/ttm_tt.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c index 4b51b90231267..1c50cadd96e5e 100644 --- a/drivers/gpu/drm/ttm/ttm_tt.c +++ b/drivers/gpu/drm/ttm/ttm_tt.c @@ -36,6 +36,8 @@ #include #include #include +#include +#include #include #include #include From 7e829ea2ad080580793803088267e7931cbbccc3 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 9 Mar 2021 10:14:58 +0800 Subject: [PATCH 0069/1868] drm/amdkcl: REWORKME: config.h Change-Id: I981875bb459ee1d29553b026e33b316e185250cb Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/dkms/config/config.h | 147 +++++++++++++++++++++++ 1 file changed, 147 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/config/config.h diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h new file mode 100644 index 0000000000000..5c604c53ed971 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -0,0 +1,147 @@ +/* config/config.h. Generated from config.h.in by configure. */ +/* config/config.h.in. Generated from configure.ac by autoheader. */ + +/* *FLAGS_.o support to take the path relative to $(obj) */ +#define HAVE_AMDKCL_FLAGS_TAKE_PATH 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_ASM_FPU_API_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_ASM_SET_MEMORY_H 1 + +/* Define to 1 if you have the header file. */ +/* #undef HAVE_DRM_AMDGPU_PCIID_H */ + +/* Define to 1 if you have the header file. */ +/* #undef HAVE_DRM_DRMP_H */ + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_ATOMIC_UAPI_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_AUDIO_COMPONENT_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_AUTH_H 1 + +/* Define to 1 if you have the header file. */ +/* #undef HAVE_DRM_DRM_BACKPORT_H */ + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_CONNECTOR_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_DEBUGFS_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_DEVICE_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_DRV_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_ENCODER_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_FILE_H 1 + +/* Define to 1 if you have the header file. + */ +#define HAVE_DRM_DRM_GEM_FRAMEBUFFER_HELPER_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_HDCP_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_IOCTL_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_IRQ_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_MANAGED_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_PLANE_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_PRINT_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_PROBE_HELPER_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_UTIL_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_VBLANK_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_TASK_BARRIER_H 1 + +/* kallsyms_lookup_name is available */ +/* #undef HAVE_KALLSYMS_LOOKUP_NAME */ + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_BITS_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_COMPILER_ATTRIBUTES_H 1 + +/* Define to 1 if you have the header file. */ +/* #undef HAVE_LINUX_DMA_ATTRS_H */ + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_DMA_FENCE_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_DMA_RESV_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_IO_64_NONATOMIC_LO_HI_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_MEM_ENCRYPT_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_MMAP_LOCK_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_NOSPEC_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_OVERFLOW_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_PCI_P2PDMA_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_SCHED_MM_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_SCHED_SIGNAL_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_SCHED_TASK_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_UAPI_LINUX_SCHED_TYPES_H 1 + +/* Define to the address where bug reports for this package should be sent. */ +#define PACKAGE_BUGREPORT "" + +/* Define to the full name of this package. */ +#define PACKAGE_NAME "amdgpu-dkms" + +/* Define to the full name and version of this package. */ +#define PACKAGE_STRING "amdgpu-dkms 19.40" + +/* Define to the one symbol short name of this package. */ +#define PACKAGE_TARNAME "amdgpu-dkms" + +/* Define to the home page for this package. */ +#define PACKAGE_URL "" + +/* Define to the version of this package. */ +#define PACKAGE_VERSION "19.40" From 17c215b10d1774bfdcd4431574bf6b2eceecda95 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 9 Mar 2021 11:52:01 +0800 Subject: [PATCH 0070/1868] drm/amdkcl: fake hexint support for module_param Change-Id: Ic6b3fd5e2ca1e6e645c658924cc051b6119297b6 Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 ++ .../gpu/drm/amd/amdkcl/kcl_kernel_params.c | 29 +++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_moduleparam.h | 17 +++++++++++ 4 files changed, 49 insertions(+) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_kernel_params.c create mode 100644 include/kcl/kcl_moduleparam.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index a805915aba6b9..6d6d62a8e05a1 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -1,6 +1,8 @@ # SPDX-License-Identifier: MIT amdkcl-y += main.o symbols.o kcl_common.o +amdkcl-y += kcl_kernel_params.o + ccflags-y += \ -include $(src)/../dkms/config/config.h \ -include $(src)/kcl_common.h diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_kernel_params.c b/drivers/gpu/drm/amd/amdkcl/kcl_kernel_params.c new file mode 100644 index 0000000000000..d350a6bd07769 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_kernel_params.c @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* Helpers for initial module or kernel cmdline parsing + Copyright (C) 2001 Rusty Russell. + +*/ +#include + +// Copied from kernel/params.c +#define STANDARD_PARAM_DEF(name, type, format, strtolfn) \ + int param_set_##name(const char *val, const struct kernel_param *kp) \ + { \ + return strtolfn(val, 0, (type *)kp->arg); \ + } \ + int param_get_##name(char *buffer, const struct kernel_param *kp) \ + { \ + return scnprintf(buffer, PAGE_SIZE, format "\n", \ + *((type *)kp->arg)); \ + } \ + const struct kernel_param_ops param_ops_##name = { \ + .set = param_set_##name, \ + .get = param_get_##name, \ + }; \ + EXPORT_SYMBOL(param_set_##name); \ + EXPORT_SYMBOL(param_get_##name); \ + EXPORT_SYMBOL(param_ops_##name) + +#ifdef _kcl_param_check_hexint +STANDARD_PARAM_DEF(hexint, unsigned int, "%#08x", kstrtouint); +#endif diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 89cd9143a9c0a..e30fbea884c07 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -4,4 +4,5 @@ #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_moduleparam.h b/include/kcl/kcl_moduleparam.h new file mode 100644 index 0000000000000..427abe45ea8af --- /dev/null +++ b/include/kcl/kcl_moduleparam.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _KCL_KCL_LINUX_MODULE_PARAMS_H_H +#define _KCL_KCL_LINUX_MODULE_PARAMS_H_H + +#include +#include + +/* Copied from v5.8-rc2-514-g7d8365771ffb include/linux/moduleparam.h */ +#ifndef param_check_hexint +#define _kcl_param_check_hexint +extern const struct kernel_param_ops param_ops_hexint; +extern int param_set_hexint(const char *val, const struct kernel_param *kp); +extern int param_get_hexint(char *buffer, const struct kernel_param *kp); +#define param_check_hexint(name, p) param_check_uint(name, p) +#endif /* param_check_hexint */ + +#endif From e0c6a276b1dbf3c4c5c77cad5321723f053c73e8 Mon Sep 17 00:00:00 2001 From: Evan Quan Date: Mon, 18 Feb 2019 10:31:07 +0800 Subject: [PATCH 0071/1868] drm/amdkcl: Test whether kref_read() function is available drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling drm/amdkcl: [4.11] fix for kref_read - v2: define a common api instead of referring individually Change-Id: I9ae193c10ab864534a4d64bd8dd71e03284c59b1 Signed-off-by: Evan Quan Reviewed-by: Junwei Zhang Signed-off-by: Jack Gui drm/amdkcl: Test whether kref_read() function is available Signed-off-by: Slava Grigorev Signed-off-by: Yifan Zhang Signed-off-by: Jack Gui Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/kref-read.m4 | 16 +++++++++++++++ drivers/gpu/drm/ttm/backport/backport.h | 2 +- include/kcl/kcl_kref.h | 25 ++++++++++++++++++++++++ 5 files changed, 44 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/kref-read.m4 create mode 100644 include/kcl/kcl_kref.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index e30fbea884c07..9845b606cb752 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -5,4 +5,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index a61ba77924c84..d3c709f916a9c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -7,6 +7,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_LINUX_HEADERS AC_AMDGPU_DRM_HEADERS AC_AMDGPU_KALLSYMS_LOOKUP_NAME + AC_AMDGPU_KREF_READ AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/kref-read.m4 b/drivers/gpu/drm/amd/dkms/m4/kref-read.m4 new file mode 100644 index 0000000000000..da7e2bf0aac37 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/kref-read.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit 2c935bc57221cc2edc787c72ea0e2d30cdcd3d5e +dnl # locking/atomic, kref: Add kref_read() +dnl # +AC_DEFUN([AC_AMDGPU_KREF_READ], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + kref_read(NULL); + ], [ + AC_DEFINE(HAVE_KREF_READ, 1, + [kref_read() function is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index 524d2a01b50df..11a9f3a7c0b36 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -3,5 +3,5 @@ #define AMDTTM_BACKPORT_H #include - +#include #endif diff --git a/include/kcl/kcl_kref.h b/include/kcl/kcl_kref.h new file mode 100644 index 0000000000000..0cc53e385e8db --- /dev/null +++ b/include/kcl/kcl_kref.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * kref.h - library routines for handling generic reference counted objects + * + * Copyright (C) 2004 Greg Kroah-Hartman + * Copyright (C) 2004 IBM Corp. + * + * based on kobject.h which was: + * Copyright (C) 2002-2003 Patrick Mochel + * Copyright (C) 2002-2003 Open Source Development Labs + */ +#ifndef AMDKCL_KREF_H +#define AMDKCL_KREF_H + +#include + +/* Copied from include/linux/kref.h */ +#if !defined(HAVE_KREF_READ) +static inline unsigned int kref_read(const struct kref *kref) +{ + return atomic_read(&kref->refcount); +} +#endif + +#endif /* AMDKCL_KREF_H */ From 5a22e266881559c9f338074924a8341358aab93d Mon Sep 17 00:00:00 2001 From: Chengming Gui Date: Mon, 18 Nov 2019 16:52:31 +0800 Subject: [PATCH 0072/1868] drm/amdkcl: check whether idr_for_each_entry_continue is avialable it is a squash of: c1f004d6344b drm/amdkcl: fix license for kcl part 7b1a9f7a702c drm/amdkcl: fake idr_remove() 41a5a48a1668 drm/amdkcl: check whether idr_for_each_entry_continue is avialable Signed-off-by: Chengming Gui Signed-off-by: Flora Cui Signed-off-by: Flora Cui Reviewed-by: Jiansong Chen Signed-off-by: Yifan Zhang Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/idr-remove.m4 | 19 ++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_idr.h | 38 +++++++++++++++++++++++ 4 files changed, 59 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/idr-remove.m4 create mode 100644 include/kcl/kcl_idr.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 9845b606cb752..b0ee7c7bd37c9 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -5,5 +5,6 @@ #include #include #include +#include #include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/idr-remove.m4 b/drivers/gpu/drm/amd/dkms/m4/idr-remove.m4 new file mode 100644 index 0000000000000..397c76a73ed8e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/idr-remove.m4 @@ -0,0 +1,19 @@ +dnl # +dnl # commit d3e709e63e97e5f3f129b639991cfe266da60bae +dnl # Author: Matthew Wilcox +dnl # Date: Thu Dec 22 13:30:22 2016 -0500 +dnl # idr: Return the deleted entry from idr_remove +dnl # +AC_DEFUN([AC_AMDGPU_IDR_REMOVE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + void *i; + i = idr_remove(NULL, 0); + ], [ + AC_DEFINE(HAVE_IDR_REMOVE_RETURN_VOID_POINTER, 1, + [idr_remove return void pointer]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index d3c709f916a9c..9813e2f903e53 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -7,6 +7,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_LINUX_HEADERS AC_AMDGPU_DRM_HEADERS AC_AMDGPU_KALLSYMS_LOOKUP_NAME + AC_AMDGPU_IDR_REMOVE AC_AMDGPU_KREF_READ AC_KERNEL_WAIT diff --git a/include/kcl/kcl_idr.h b/include/kcl/kcl_idr.h new file mode 100644 index 0000000000000..63473317c2ead --- /dev/null +++ b/include/kcl/kcl_idr.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * include/linux/idr.h + * + * 2002-10-18 written by Jim Houston jim.houston@ccur.com + * Copyright (C) 2002 by Concurrent Computer Corporation + * + * Small id to pointer translation service avoiding fixed sized + * tables. + */ +#ifndef AMDKCL_IDR_H +#define AMDKCL_IDR_H + +#include + +/* Copied from v4.4-rc2-61-ga55bbd375d18 include/linux/idr.h */ +#ifndef idr_for_each_entry_continue +#define idr_for_each_entry_continue(idr, entry, id) \ + for ((entry) = idr_get_next((idr), &(id)); \ + entry; \ + ++id, (entry) = idr_get_next((idr), &(id))) +#endif + +#ifndef HAVE_IDR_REMOVE_RETURN_VOID_POINTER +static inline void *_kcl_idr_remove(struct idr *idr, int id) +{ + void *ptr; + + ptr = idr_find(idr, id); + if (ptr) + idr_remove(idr, id); + + return ptr; +} +#define idr_remove _kcl_idr_remove +#endif /* HAVE_IDR_REMOVE_RETURN_VOID_POINTER */ + +#endif /* AMDKCL_IDR_H */ From 3740a5b0f3c9756256a74feecfa2f87129c28b1d Mon Sep 17 00:00:00 2001 From: changzhu Date: Fri, 16 Aug 2019 12:18:26 +0800 Subject: [PATCH 0073/1868] drm/amdkcl: Test whether type __poll_t is available [Why] __poll_t is not defined until patch: define __poll_t, annotate constants So there will be build error when using it in kfd_debug_events.c This problem is caused by patch: drm/amdkfd: add debug notification [How] Use autoconf patch to define __poll_t if it's not defined. Change-Id: I56bbeea7c27eb2974f224e8bccafb8bd97c794c1 Signed-off-by: changzhu Reviewed-by: Flora Cui Signed-off-by: Jack Gui drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling drm/amd/autoconf: Test whether type __poll_t is available(v2) Change-Id: I397a3403223f9cbcfc29d36d63544ce4ca7ed4c6 Signed-off-by: changzhu Reviewed-by: Flora Cui drm/amdkcl: fix macro define for __POLL_T Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang drm/amdkcl: drop HAVE_TYPE__POLL_T check outside of kcl Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/type--poll-t.m4 | 16 ++++++++++++++++ include/kcl/kcl_types.h | 13 +++++++++++++ 4 files changed, 31 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/type--poll-t.m4 create mode 100644 include/kcl/kcl_types.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index b0ee7c7bd37c9..0ce187a5e10a6 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -5,6 +5,7 @@ #include #include #include +#include #include #include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 9813e2f903e53..4f333f126a2a7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -9,6 +9,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_KALLSYMS_LOOKUP_NAME AC_AMDGPU_IDR_REMOVE AC_AMDGPU_KREF_READ + AC_AMDGPU_TYPE__POLL_T AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/type--poll-t.m4 b/drivers/gpu/drm/amd/dkms/m4/type--poll-t.m4 new file mode 100644 index 0000000000000..a5744a51a8ffb --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/type--poll-t.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v4.15-rc1-4-g8ced390c2b18 +dnl # define __poll_t, annotate constants +dnl # +AC_DEFUN([AC_AMDGPU_TYPE__POLL_T], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + __poll_t mask = 0; + ],[ + AC_DEFINE(HAVE_TYPE__POLL_T, 1, [__poll_t is available]) + ]) + ]) +]) + diff --git a/include/kcl/kcl_types.h b/include/kcl/kcl_types.h new file mode 100644 index 0000000000000..66ff65a627e5a --- /dev/null +++ b/include/kcl/kcl_types.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_TYPES_H +#define AMDKCL_TYPES_H + +/* Copied from v4.15-rc1-4-g8ced390c2b18 include/uapi/linux/types.h */ +#ifndef HAVE_TYPE__POLL_T +#ifdef __CHECK_POLL +typedef unsigned __bitwise __poll_t; +#else +typedef unsigned __poll_t; +#endif +#endif +#endif From 101dd08321ace3368b76c6517028815fe2798a0e Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 7 Nov 2019 11:31:51 +0800 Subject: [PATCH 0074/1868] drm/amdkcl: fake DMA_ATTR_NO_WARN if undefined Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang Signed-off-by: Jack Gui drm/amdkcl: test dma_map_sgtable() is available fake a kcl copy of dma_map_sgtable() & dma_unmap_sgtable() Signed-off-by: Flora Cui Change-Id: I277799b85805aefa105c73c88d0ba01ad44c1912 drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/backport/backport.h | 1 + .../gpu/drm/amd/dkms/m4/dma_map_sgtable.m4 | 21 +++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/ttm/backport/backport.h | 1 + include/kcl/kcl_dma_mapping.h | 90 +++++++++++++++++++ 5 files changed, 114 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/dma_map_sgtable.m4 create mode 100644 include/kcl/kcl_dma_mapping.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 0ce187a5e10a6..352104e6dadfa 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -8,4 +8,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/dma_map_sgtable.m4 b/drivers/gpu/drm/amd/dkms/m4/dma_map_sgtable.m4 new file mode 100644 index 0000000000000..09d1275020880 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dma_map_sgtable.m4 @@ -0,0 +1,21 @@ +dnl # +dnl # v5.7-rc5-32-gd9d200bcebc1 +dnl # dma-mapping: add generic helpers for mapping sgtable objects +dnl # +AC_DEFUN([AC_AMDGPU_DMA_MAP_SGTABLE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + dma_map_sgtable(NULL, NULL, 0, 0); + ], [ + AC_DEFINE(HAVE_DMA_MAP_SGTABLE, 1, + [dma_map_sgtable() is enabled]) + ] + dnl # + dnl # v4.7-11546-g00085f1efa38 + dnl # dma-mapping: use unsigned long for dma_attrs + dnl # leverage test for linux/dma-attrs.h + ) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 4f333f126a2a7..f8da5e6791870 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -10,6 +10,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_IDR_REMOVE AC_AMDGPU_KREF_READ AC_AMDGPU_TYPE__POLL_T + AC_AMDGPU_DMA_MAP_SGTABLE AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index 11a9f3a7c0b36..fbb66d01e2665 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -4,4 +4,5 @@ #include #include +#include #endif diff --git a/include/kcl/kcl_dma_mapping.h b/include/kcl/kcl_dma_mapping.h new file mode 100644 index 0000000000000..c7de48cd9aad7 --- /dev/null +++ b/include/kcl/kcl_dma_mapping.h @@ -0,0 +1,90 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_DMA_MAPPING_H +#define AMDKCL_DMA_MAPPING_H + +#include + +/* + * commit v4.8-11962-ga9a62c938441 + * dma-mapping: introduce the DMA_ATTR_NO_WARN attribute + */ +#ifndef DMA_ATTR_NO_WARN +#define DMA_ATTR_NO_WARN (0UL) +#endif + +#ifdef HAVE_LINUX_DMA_ATTRS_H +static inline +void _kcl_convert_long_to_dma_attrs(struct dma_attrs *dma_attrs, + unsigned long attrs) +{ + int i; + + init_dma_attrs(dma_attrs); + + for (i = 0; i < DMA_ATTR_MAX; i++) { + if (attrs & (1 << i)) + dma_set_attr(i, dma_attrs); + } +} +#endif + +#ifndef HAVE_DMA_MAP_SGTABLE +#ifdef HAVE_LINUX_DMA_ATTRS_H +static inline +int _kcl_dma_map_sg_attrs(struct device *dev, struct scatterlist *sg, int nents, + enum dma_data_direction dir, unsigned long attrs) +{ + struct dma_attrs dma_attrs; + + _kcl_convert_long_to_dma_attrs(&dma_attrs, attrs); + return dma_map_sg_attrs(dev, sg, nents, dir, &dma_attrs); +} + +static inline +void _kcl_dma_unmap_sg_attrs(struct device *dev, struct scatterlist *sg, + int nents, enum dma_data_direction dir, + unsigned long attrs) + +{ + struct dma_attrs dma_attrs; + + _kcl_convert_long_to_dma_attrs(&dma_attrs, attrs); + dma_unmap_sg_attrs(dev, sg, nents, dir, &dma_attrs); +} + +#else +static inline +int _kcl_dma_map_sg_attrs(struct device *dev, struct scatterlist *sg, int nents, + enum dma_data_direction dir, unsigned long attrs) +{ + return dma_map_sg_attrs(dev, sg, nents, dir, attrs); +} +static inline +void _kcl_dma_unmap_sg_attrs(struct device *dev, struct scatterlist *sg, + int nents, enum dma_data_direction dir, + unsigned long attrs) +{ + dma_unmap_sg_attrs(dev, sg, nents, dir, attrs); +} +#endif /* HAVE_LINUX_DMA_ATTRS_H */ + +static inline int dma_map_sgtable(struct device *dev, struct sg_table *sgt, + enum dma_data_direction dir, unsigned long attrs) +{ + int nents; + + nents = _kcl_dma_map_sg_attrs(dev, sgt->sgl, sgt->orig_nents, dir, attrs); + if (nents <= 0) + return -EINVAL; + sgt->nents = nents; + return 0; +} + +static inline void dma_unmap_sgtable(struct device *dev, struct sg_table *sgt, + enum dma_data_direction dir, unsigned long attrs) +{ + _kcl_dma_unmap_sg_attrs(dev, sgt->sgl, sgt->orig_nents, dir, attrs); +} +#endif + +#endif From 30bbf81aa3edbf387455b05086cabdd7c502c371 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 8 Sep 2020 14:17:21 +0800 Subject: [PATCH 0075/1868] drm/amdkcl: test i2c_new_client_device() is available v2: add extern for i2c_new_client_device() available case for phantom kernel forget to declare the func it is a squash of: b677e39b1c70 drm/amdkcl: test i2c_new_client_device() is available c1f004d6344b drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/backport/backport.h | 1 + .../drm/amd/dkms/m4/i2c_new_client_device.m4 | 13 ++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_i2c.h | 26 +++++++++++++++++++ 4 files changed, 41 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/i2c_new_client_device.m4 create mode 100644 include/kcl/kcl_i2c.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 352104e6dadfa..49648f356a682 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -9,4 +9,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/i2c_new_client_device.m4 b/drivers/gpu/drm/amd/dkms/m4/i2c_new_client_device.m4 new file mode 100644 index 0000000000000..cedd29e0fe70e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/i2c_new_client_device.m4 @@ -0,0 +1,13 @@ +dnl # +dnl # v5.1-12318-g7159dbdae3c5 +dnl # i2c: core: improve return value handling of i2c_new_device and i2c_new_dummy +dnl # +AC_DEFUN([AC_AMDGPU_I2C_NEW_CLIENT_DEVICE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([i2c_new_client_device], [drivers/i2c/i2c-core-base.c], + [ + AC_DEFINE(HAVE_I2C_NEW_CLIENT_DEVICE, 1, + [i2c_new_client_device() is enabled]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index f8da5e6791870..3ca7e932c5758 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -11,6 +11,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_KREF_READ AC_AMDGPU_TYPE__POLL_T AC_AMDGPU_DMA_MAP_SGTABLE + AC_AMDGPU_I2C_NEW_CLIENT_DEVICE AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_i2c.h b/include/kcl/kcl_i2c.h new file mode 100644 index 0000000000000..66b3195eff49d --- /dev/null +++ b/include/kcl/kcl_i2c.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * i2c.h - definitions for the Linux i2c bus interface + * Copyright (C) 1995-2000 Simon G. Vogl + * Copyright (C) 2013-2019 Wolfram Sang + * + * With some changes from Kyösti Mälkki and + * Frodo Looijaard + */ +#ifndef _KCL_KCL_I2C_H +#define _KCL_KCL_I2C_H + +#include + +#ifdef HAVE_I2C_NEW_CLIENT_DEVICE +extern struct i2c_client * +i2c_new_client_device(struct i2c_adapter *adap, struct i2c_board_info const *info); +#else +static inline struct i2c_client * +i2c_new_client_device(struct i2c_adapter *adap, struct i2c_board_info const *info) +{ + return i2c_new_device(adap, info); +} +#endif + +#endif From 655c825e3ac73ddbdf225b487b383f686de84504 Mon Sep 17 00:00:00 2001 From: Prike Liang Date: Thu, 20 Sep 2018 20:18:21 +0800 Subject: [PATCH 0076/1868] drm/amdkcl: Test whether request_firmware_direct() is available This is a squash of: v1: drm/amdkcl: [3.14] Add request_firmware_direct adaptor for load_dmcu_fw v2: drm/amdkcl: Test whether request_firmware_direct() is available c1f004d6344b drm/amdkcl: fix license for kcl part Signed-off-by: Prike Liang Reviewed-by: Junwei Zhang Signed-off-by: Anatoli Antonovitch Signed-off-by: Yifan Zhang Signed-off-by: Jack Gui Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/backport/backport.h | 2 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../drm/amd/dkms/m4/request-firmware-direct.m4 | 16 ++++++++++++++++ include/kcl/kcl_firmware.h | 12 ++++++++++++ 4 files changed, 31 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/request-firmware-direct.m4 create mode 100644 include/kcl/kcl_firmware.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 49648f356a682..6d65256b54b43 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -10,4 +10,6 @@ #include #include #include +#include + #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 3ca7e932c5758..071269037d3d4 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -12,6 +12,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_TYPE__POLL_T AC_AMDGPU_DMA_MAP_SGTABLE AC_AMDGPU_I2C_NEW_CLIENT_DEVICE + AC_AMDGPU_REQUEST_FIRMWARE_DIRECT AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/request-firmware-direct.m4 b/drivers/gpu/drm/amd/dkms/m4/request-firmware-direct.m4 new file mode 100644 index 0000000000000..218e403328bc8 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/request-firmware-direct.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v3.13-rc2-51-gbba3a87e982a +dnl # firmware: Introduce request_firmware_direct() +dnl # +AC_DEFUN([AC_AMDGPU_REQUEST_FIRMWARE_DIRECT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + request_firmware_direct(NULL, NULL, NULL); + ], [ + AC_DEFINE(HAVE_REQUEST_FIRMWARE_DIRECT, 1, + [request_firmware_direct() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_firmware.h b/include/kcl/kcl_firmware.h new file mode 100644 index 0000000000000..b846e2d4eee5d --- /dev/null +++ b/include/kcl/kcl_firmware.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_FIRMWARE_H +#define AMDKCL_FIRMWARE_H + +#if !defined(HAVE_REQUEST_FIRMWARE_DIRECT) +#include + +#define request_firmware_direct request_firmware + +#endif +#endif /* AMDKCL_FIRMWARE_H */ + From 5fd22d884d2e7af7c2cb168c6bb7417c93073931 Mon Sep 17 00:00:00 2001 From: Chengming Gui Date: Wed, 6 May 2020 17:13:38 +0800 Subject: [PATCH 0077/1868] drm/amdkcl: Test whether backlight_device_set_brightness is available introduced by kernel: v4.7-rc2~9^2^2~5 v2: add kcl copy of backlight_device_set_brightness This is a squash of: c1f004d6344b drm/amdkcl: fix license for kcl part f11810210f8a drm/amdkcl: Test whether backlight_device_set_brightness is available Signed-off-by: Chengming Gui Reviewed-by: Flora Cui Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 ++ drivers/gpu/drm/amd/amdkcl/kcl_backlight.c | 14 ++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + .../dkms/m4/backlight-device-set-brightness.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_backlight.h | 16 ++++++++++++++++ 6 files changed, 50 insertions(+) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_backlight.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/backlight-device-set-brightness.m4 create mode 100644 include/kcl/kcl_backlight.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 6d6d62a8e05a1..4b40eff8ae672 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -3,6 +3,8 @@ amdkcl-y += main.o symbols.o kcl_common.o amdkcl-y += kcl_kernel_params.o +amdkcl-y += kcl_backlight.o + ccflags-y += \ -include $(src)/../dkms/config/config.h \ -include $(src)/kcl_common.h diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_backlight.c b/drivers/gpu/drm/amd/amdkcl/kcl_backlight.c new file mode 100644 index 0000000000000..1e1da40b92c05 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_backlight.c @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Backlight Lowlevel Control Abstraction + * + * Copyright (C) 2003,2004 Hewlett-Packard Company + * + */ +#include + +#ifndef HAVE_BACKLIGHT_DEVICE_SET_BRIGHTNESS +amdkcl_dummy_symbol(backlight_device_set_brightness, int, return 0, + struct backlight_device *bd, unsigned long brightness) +#endif + diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 6d65256b54b43..7b2cdba58783f 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -11,5 +11,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/backlight-device-set-brightness.m4 b/drivers/gpu/drm/amd/dkms/m4/backlight-device-set-brightness.m4 new file mode 100644 index 0000000000000..b021cbc2ab976 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/backlight-device-set-brightness.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v4.6-rc6-1-gf6a4790a5471 +dnl # video / backlight: add two APIs for drivers to use +dnl # +AC_DEFUN([AC_AMDGPU_BACKLIGHT_DEVICE_SET_BRIGHTNESS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + backlight_device_set_brightness(NULL, 0); + ], [backlight_device_set_brightness], [drivers/video/backlight/backlight.c], [ + AC_DEFINE(HAVE_BACKLIGHT_DEVICE_SET_BRIGHTNESS, 1, + [backlight_device_set_brightness() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 071269037d3d4..c821cf258e209 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -13,6 +13,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DMA_MAP_SGTABLE AC_AMDGPU_I2C_NEW_CLIENT_DEVICE AC_AMDGPU_REQUEST_FIRMWARE_DIRECT + AC_AMDGPU_BACKLIGHT_DEVICE_SET_BRIGHTNESS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_backlight.h b/include/kcl/kcl_backlight.h new file mode 100644 index 0000000000000..1d06b61502c3c --- /dev/null +++ b/include/kcl/kcl_backlight.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Backlight Lowlevel Control Abstraction + * + * Copyright (C) 2003,2004 Hewlett-Packard Company + * + */ +#ifndef AMDKCL_BACKLIGHT_H +#define AMDKCL_BACKLIGHT_H + +#include +#ifndef HAVE_BACKLIGHT_DEVICE_SET_BRIGHTNESS +int backlight_device_set_brightness(struct backlight_device *bd, + unsigned long brightness); +#endif /* HAVE_BACKLIGHT_DEVICE_SET_BRIGHTNESS */ +#endif From d8bef01a10401fecd4e919d1b0145093a149d324 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 15 Apr 2020 10:31:41 +0800 Subject: [PATCH 0078/1868] drm/amdkcl: fake a kcl copy of compat_ptr_ioctl() This is a squash of: c1f004d6344b drm/amdkcl: fix license for kcl part 2011137fd5d7 drm/amdkcl: fake a kcl copy of compat_ptr_ioctl() Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/Makefile | 3 +- drivers/gpu/drm/amd/amdkcl/kcl_ioctl.c | 45 +++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 2 +- .../gpu/drm/amd/dkms/m4/compat_ptr_ioctl.m4 | 17 +++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_fs.h | 22 +++++++++ 6 files changed, 87 insertions(+), 3 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_ioctl.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/compat_ptr_ioctl.m4 create mode 100644 include/kcl/kcl_fs.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 4b40eff8ae672..7bb382f7c3e27 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -2,8 +2,7 @@ amdkcl-y += main.o symbols.o kcl_common.o amdkcl-y += kcl_kernel_params.o - -amdkcl-y += kcl_backlight.o +amdkcl-y += kcl_backlight.o kcl_ioctl.o ccflags-y += \ -include $(src)/../dkms/config/config.h \ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_ioctl.c b/drivers/gpu/drm/amd/amdkcl/kcl_ioctl.c new file mode 100644 index 0000000000000..aef47eda7f4ab --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_ioctl.c @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * linux/fs/ioctl.c + * + * Copyright (C) 1991, 1992 Linus Torvalds + */ +#include +#include + +/* Copied from v5.4-rc2-1-g2952db0fd51b fs/ioctl.c */ +#ifndef HAVE_COMPAT_PTR_IOCTL +#ifdef CONFIG_COMPAT +/** + * compat_ptr_ioctl - generic implementation of .compat_ioctl file operation + * + * This is not normally called as a function, but instead set in struct + * file_operations as + * + * .compat_ioctl = compat_ptr_ioctl, + * + * On most architectures, the compat_ptr_ioctl() just passes all arguments + * to the corresponding ->ioctl handler. The exception is arch/s390, where + * compat_ptr() clears the top bit of a 32-bit pointer value, so user space + * pointers to the second 2GB alias the first 2GB, as is the case for + * native 32-bit s390 user space. + * + * The compat_ptr_ioctl() function must therefore be used only with ioctl + * functions that either ignore the argument or pass a pointer to a + * compatible data type. + * + * If any ioctl command handled by fops->unlocked_ioctl passes a plain + * integer instead of a pointer, or any of the passed data types + * is incompatible between 32-bit and 64-bit architectures, a proper + * handler is required instead of compat_ptr_ioctl. + */ +long _kcl_compat_ptr_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + if (!file->f_op->unlocked_ioctl) + return -ENOIOCTLCMD; + + return file->f_op->unlocked_ioctl(file, cmd, (unsigned long)compat_ptr(arg)); +} +EXPORT_SYMBOL(_kcl_compat_ptr_ioctl); +#endif /* CONFIG_COMPAT */ +#endif /* HAVE_COMPAT_PTR_IOCTL */ diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 7b2cdba58783f..92dcca954fe64 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -12,5 +12,5 @@ #include #include #include - +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/compat_ptr_ioctl.m4 b/drivers/gpu/drm/amd/dkms/m4/compat_ptr_ioctl.m4 new file mode 100644 index 0000000000000..f9c4c12aa4b75 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/compat_ptr_ioctl.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v5.4-rc2-1-g2952db0fd51b +dnl # compat_ioctl: add compat_ptr_ioctl() +dnl # +AC_DEFUN([AC_AMDGPU_COMPAT_PTR_IOCTL], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + compat_ptr_ioctl(NULL, 0, 0); + ],[compat_ptr_ioctl],[fs/ioctl.c],[ + AC_DEFINE(HAVE_COMPAT_PTR_IOCTL, + 1, + [compat_ptr_ioctl() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index c821cf258e209..57066ae880d37 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -14,6 +14,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_I2C_NEW_CLIENT_DEVICE AC_AMDGPU_REQUEST_FIRMWARE_DIRECT AC_AMDGPU_BACKLIGHT_DEVICE_SET_BRIGHTNESS + AC_AMDGPU_COMPAT_PTR_IOCTL AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_fs.h b/include/kcl/kcl_fs.h new file mode 100644 index 0000000000000..4a4c208d833e0 --- /dev/null +++ b/include/kcl/kcl_fs.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_FS_H +#define AMDKCL_FS_H + +#include +#include + +/* Copied from v5.4-rc2-1-g2952db0fd51b linux/fs.h */ +#ifndef HAVE_COMPAT_PTR_IOCTL +#ifdef CONFIG_COMPAT +extern long _kcl_compat_ptr_ioctl(struct file *file, unsigned int cmd, + unsigned long arg); +static inline long compat_ptr_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) +{ + return _kcl_compat_ptr_ioctl(file, cmd, arg); +} +#else +#define compat_ptr_ioctl NULL +#endif /* CONFIG_COMPAT */ +#endif /* HAVE_COMPAT_PTR_IOCTL */ +#endif From fb1f299d7d929d5069bbcdff59df002a6e917307 Mon Sep 17 00:00:00 2001 From: Junwei Zhang Date: Fri, 23 Dec 2016 18:32:20 +0800 Subject: [PATCH 0079/1868] drm/amdkcl: Test whether kthread_{park/unpark/parkme/should_park}() is available History: Introduced by kernel v3.7-rc1~37^2~2^2~1^2~8 Exported by kernel v4.2-rc6~15^2~9 v2: drm/amdkcl: fix kthread functions v3: drm/amdkcl: Test whether kthread_{park/unpark/parkme/should_park}() is available (v2) v4: drm/amdkcl: drop kcl_kthread_xxx v5: drm/amdkcl: update test for kthread_xxx v6: drm/amdkcl: fix license for kcl part Change-Id: I4dfe3fe981c7d4f5f60ae0a862b2c3c52bf3fca9 Signed-off-by: Junwei Zhang Reviewed-by: Qiang Yu Signed-off-by: Jack Gui Reviewed-by: Flora Cui Acked-by: Feifei Xu Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkcl/Makefile | 3 +- drivers/gpu/drm/amd/amdkcl/kcl_kthread.c | 67 +++++++++++++++++++ drivers/gpu/drm/amd/amdkcl/main.c | 3 + drivers/gpu/drm/amd/backport/backport.h | 2 + drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../gpu/drm/amd/dkms/m4/kthread-park-xx.m4 | 14 ++++ drivers/gpu/drm/scheduler/backport/backport.h | 1 + include/kcl/backport/kcl_kthread_backport.h | 14 ++++ include/kcl/kcl_kthread.h | 14 ++++ 9 files changed, 118 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_kthread.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/kthread-park-xx.m4 create mode 100644 include/kcl/backport/kcl_kthread_backport.h create mode 100644 include/kcl/kcl_kthread.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 7bb382f7c3e27..daa8a87f99ce2 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -2,7 +2,8 @@ amdkcl-y += main.o symbols.o kcl_common.o amdkcl-y += kcl_kernel_params.o -amdkcl-y += kcl_backlight.o kcl_ioctl.o +amdkcl-y += kcl_backlight.o kcl_ioctl.o \ + kcl_kthread.o ccflags-y += \ -include $(src)/../dkms/config/config.h \ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_kthread.c b/drivers/gpu/drm/amd/amdkcl/kcl_kthread.c new file mode 100644 index 0000000000000..e6180612eaa97 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_kthread.c @@ -0,0 +1,67 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* Kernel thread helper functions. + * Copyright (C) 2004 IBM Corporation, Rusty Russell. + * Copyright (C) 2009 Red Hat, Inc. + * + * Creation is done via kthreadd, so that we get a clean environment + * even if we're invoked from userspace (think modprobe, hotplug cpu, + * etc.). + */ + +/* +* FIXME: implement below API when kernel version < 4.2 +*/ +#include +#include +#include +#include "kcl_common.h" + +#if !defined(HAVE_KTHREAD_PARK_XX) +bool (*_kcl_kthread_should_park)(void); +EXPORT_SYMBOL(_kcl_kthread_should_park); + +void (*_kcl_kthread_parkme)(void); +EXPORT_SYMBOL(_kcl_kthread_parkme); + +void (*_kcl_kthread_unpark)(struct task_struct *k); +EXPORT_SYMBOL(_kcl_kthread_unpark); + +int (*_kcl_kthread_park)(struct task_struct *k); +EXPORT_SYMBOL(_kcl_kthread_park); + +static bool _kcl_kthread_should_park_stub(void) +{ + printk_once(KERN_WARNING "This kernel version not support API: kthread_should_park!\n"); + return false; +} + +static void _kcl_kthread_parkme_stub(void) +{ + printk_once(KERN_WARNING "This kernel version not support API: kthread_parkme!\n"); +} + +static void _kcl_kthread_unpark_stub(struct task_struct *k) +{ + printk_once(KERN_WARNING "This kernel version not support API: kthread_unpark!\n"); +} + +static int _kcl_kthread_park_stub(struct task_struct *k) +{ + printk_once(KERN_WARNING "This kernel version not support API: kthread_park!\n"); + return 0; +} +#endif + +void amdkcl_kthread_init(void) +{ +#if !defined(HAVE_KTHREAD_PARK_XX) + _kcl_kthread_should_park = amdkcl_fp_setup("kthread_should_park", + _kcl_kthread_should_park_stub); + _kcl_kthread_parkme = amdkcl_fp_setup("kthread_parkme", + _kcl_kthread_parkme_stub); + _kcl_kthread_unpark = amdkcl_fp_setup("kthread_unpark", + _kcl_kthread_unpark_stub); + _kcl_kthread_park = amdkcl_fp_setup("kthread_park", + _kcl_kthread_park_stub); +#endif +} diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c index 4a0f67981e1c4..ecfe2b88b23ea 100644 --- a/drivers/gpu/drm/amd/amdkcl/main.c +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -3,10 +3,13 @@ #include extern void amdkcl_symbol_init(void); +extern void amdkcl_kthread_init(void); int __init amdkcl_init(void) { amdkcl_symbol_init(); + amdkcl_kthread_init(); + return 0; } module_init(amdkcl_init); diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 92dcca954fe64..258d847dad144 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -13,4 +13,6 @@ #include #include #include +#include + #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 57066ae880d37..af2e814709081 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -15,6 +15,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_REQUEST_FIRMWARE_DIRECT AC_AMDGPU_BACKLIGHT_DEVICE_SET_BRIGHTNESS AC_AMDGPU_COMPAT_PTR_IOCTL + AC_AMDGPU_KTHREAD_PARK_XX AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/kthread-park-xx.m4 b/drivers/gpu/drm/amd/dkms/m4/kthread-park-xx.m4 new file mode 100644 index 0000000000000..06a8af53dcfe9 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/kthread-park-xx.m4 @@ -0,0 +1,14 @@ +dnl # +dnl # introduced commit 2a1d446019f9a5983ec5a335b95e8593fdb6fa2e +dnl # kthread: Implement park/unpark facility +dnl # exported commit 18896451eaeee497ef5c397d76902c6376a8787d +dnl # kthread: export kthread functions +dnl # +AC_DEFUN([AC_AMDGPU_KTHREAD_PARK_XX], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([kthread_parkme kthread_park kthread_unpark kthread_should_park],[kernel/kthread.c],[ + AC_DEFINE(HAVE_KTHREAD_PARK_XX, 1, + [kthread_{park/unpark/parkme/should_park}() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/scheduler/backport/backport.h b/drivers/gpu/drm/scheduler/backport/backport.h index b8c8be307a2e7..7994c7b3826ac 100644 --- a/drivers/gpu/drm/scheduler/backport/backport.h +++ b/drivers/gpu/drm/scheduler/backport/backport.h @@ -3,5 +3,6 @@ #define AMDSCHED_BACKPORT_H #include +#include #endif diff --git a/include/kcl/backport/kcl_kthread_backport.h b/include/kcl/backport/kcl_kthread_backport.h new file mode 100644 index 0000000000000..03875b32951e0 --- /dev/null +++ b/include/kcl/backport/kcl_kthread_backport.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_KTHREAD_BACKPORT_H +#define AMDKCL_KTHREAD_BACKPORT_H +#include +#include +#include + +#if !defined(HAVE_KTHREAD_PARK_XX) +#define kthread_parkme _kcl_kthread_parkme +#define kthread_unpark _kcl_kthread_unpark +#define kthread_park _kcl_kthread_park +#define kthread_should_park _kcl_kthread_should_park +#endif +#endif diff --git a/include/kcl/kcl_kthread.h b/include/kcl/kcl_kthread.h new file mode 100644 index 0000000000000..44b9dac5abe3b --- /dev/null +++ b/include/kcl/kcl_kthread.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_KTHREAD_H +#define AMDKCL_KTHREAD_H + +#include +#include + +#if !defined(HAVE_KTHREAD_PARK_XX) +extern void (*_kcl_kthread_parkme)(void); +extern void (*_kcl_kthread_unpark)(struct task_struct *k); +extern int (*_kcl_kthread_park)(struct task_struct *k); +extern bool (*_kcl_kthread_should_park)(void); +#endif +#endif /* AMDKCL_KTHREAD_H */ From 48457b2a9180ec0e2d5736e07201fabb1e2c1d17 Mon Sep 17 00:00:00 2001 From: "Stanley.Yang" Date: Wed, 13 Nov 2019 15:52:33 +0800 Subject: [PATCH 0080/1868] drm/amdkcl: Test whether __kthread_should_park() is available This is a squash of: 896d32929d9e drm/amdkcl: fix log prefix c1f004d6344b drm/amdkcl: fix license for kcl part caba32ffd8e3 drm/amdkcl: include kcl_common.h in every .c dc15fe910c0e drm/amdkcl: Test whether __kthread_should_park() is available Change-Id: Ibb7a4cc431a9c0791e64f1076cee41cad7b31e82 Signed-off-by: Stanley.Yang Reviewed-by: Flora Cui Signed-off-by: Jack Gui Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkcl/kcl_kthread.c | 18 +++++++++++++----- .../drm/amd/dkms/m4/__kthread-should-park.m4 | 12 ++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/backport/kcl_kthread_backport.h | 4 ++++ include/kcl/kcl_kthread.h | 4 ++++ 5 files changed, 34 insertions(+), 5 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/__kthread-should-park.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_kthread.c b/drivers/gpu/drm/amd/amdkcl/kcl_kthread.c index e6180612eaa97..bfc57cb644dc9 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_kthread.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_kthread.c @@ -14,7 +14,15 @@ #include #include #include -#include "kcl_common.h" + +#if !defined(HAVE___KTHREAD_SHOULD_PARK) +bool __kcl_kthread_should_park(struct task_struct *k) +{ + pr_warn_once("This kernel version not support API: __kthread_should_park!\n"); + return false; +} +EXPORT_SYMBOL(__kcl_kthread_should_park); +#endif #if !defined(HAVE_KTHREAD_PARK_XX) bool (*_kcl_kthread_should_park)(void); @@ -31,23 +39,23 @@ EXPORT_SYMBOL(_kcl_kthread_park); static bool _kcl_kthread_should_park_stub(void) { - printk_once(KERN_WARNING "This kernel version not support API: kthread_should_park!\n"); + pr_warn_once("This kernel version not support API: kthread_should_park!\n"); return false; } static void _kcl_kthread_parkme_stub(void) { - printk_once(KERN_WARNING "This kernel version not support API: kthread_parkme!\n"); + pr_warn_once("This kernel version not support API: kthread_parkme!\n"); } static void _kcl_kthread_unpark_stub(struct task_struct *k) { - printk_once(KERN_WARNING "This kernel version not support API: kthread_unpark!\n"); + pr_warn_once("This kernel version not support API: kthread_unpark!\n"); } static int _kcl_kthread_park_stub(struct task_struct *k) { - printk_once(KERN_WARNING "This kernel version not support API: kthread_park!\n"); + pr_warn_once("This kernel version not support API: kthread_park!\n"); return 0; } #endif diff --git a/drivers/gpu/drm/amd/dkms/m4/__kthread-should-park.m4 b/drivers/gpu/drm/amd/dkms/m4/__kthread-should-park.m4 new file mode 100644 index 0000000000000..2cb67699eef67 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/__kthread-should-park.m4 @@ -0,0 +1,12 @@ +dnl # +dnl # introduced commit 0121805d9d2b1fff371e195c28e9b86ae38b5e47 +dnl # kthread: Add __kthread_should_park() +dnl # +AC_DEFUN([AC_AMDGPU___KTHREAD_SHOULD_PARK], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([__kthread_should_park],[kernel/kthread.c],[ + AC_DEFINE(HAVE___KTHREAD_SHOULD_PARK, 1, + [__kthread_should_park() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index af2e814709081..37f8a408640fd 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -16,6 +16,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_BACKLIGHT_DEVICE_SET_BRIGHTNESS AC_AMDGPU_COMPAT_PTR_IOCTL AC_AMDGPU_KTHREAD_PARK_XX + AC_AMDGPU___KTHREAD_SHOULD_PARK AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/backport/kcl_kthread_backport.h b/include/kcl/backport/kcl_kthread_backport.h index 03875b32951e0..898766aa6e427 100644 --- a/include/kcl/backport/kcl_kthread_backport.h +++ b/include/kcl/backport/kcl_kthread_backport.h @@ -5,6 +5,10 @@ #include #include +#if !defined(HAVE___KTHREAD_SHOULD_PARK) +#define __kthread_should_park __kcl_kthread_should_park +#endif + #if !defined(HAVE_KTHREAD_PARK_XX) #define kthread_parkme _kcl_kthread_parkme #define kthread_unpark _kcl_kthread_unpark diff --git a/include/kcl/kcl_kthread.h b/include/kcl/kcl_kthread.h index 44b9dac5abe3b..66298a3726350 100644 --- a/include/kcl/kcl_kthread.h +++ b/include/kcl/kcl_kthread.h @@ -5,6 +5,10 @@ #include #include +#if !defined(HAVE___KTHREAD_SHOULD_PATK) +extern bool __kcl_kthread_should_park(struct task_struct *k); +#endif + #if !defined(HAVE_KTHREAD_PARK_XX) extern void (*_kcl_kthread_parkme)(void); extern void (*_kcl_kthread_unpark)(struct task_struct *k); From f9444783c71ef6182fb5d3660d68a6c1bff8dba4 Mon Sep 17 00:00:00 2001 From: Yang Xiong Date: Tue, 28 Apr 2020 23:22:10 +0800 Subject: [PATCH 0081/1868] drm/amdkcl: Test whether list_rotate_to_front() and list_is_first() is available This is a squash of: b6026ffc104a drm/amdkcl: minor refactor for indent and comment style 588246ddef5a drm/amdkcl: Test whether list_rotate_to_front() and list_is_first() is available Signed-off-by: Yang Xiong Reviewed-by: Yifan Zhang Reviewed-by: Feifei Xu Reviewed-by: Shiwu Zhang Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 ++ drivers/gpu/drm/amd/dkms/m4/list-is-first.m4 | 18 ++++++++++++++ .../drm/amd/dkms/m4/list-rotate_to_front.m4 | 18 ++++++++++++++ drivers/gpu/drm/ttm/backport/backport.h | 1 + include/kcl/kcl_list.h | 24 +++++++++++++++++++ 6 files changed, 64 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/list-is-first.m4 create mode 100644 drivers/gpu/drm/amd/dkms/m4/list-rotate_to_front.m4 create mode 100644 include/kcl/kcl_list.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 258d847dad144..f544a1b4f8e2c 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -14,5 +14,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 37f8a408640fd..133b418c86745 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -17,6 +17,8 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_COMPAT_PTR_IOCTL AC_AMDGPU_KTHREAD_PARK_XX AC_AMDGPU___KTHREAD_SHOULD_PARK + AC_AMDGPU_LIST_ROTATE_TO_FRONT + AC_AMDGPU_LIST_IS_FIRST AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/list-is-first.m4 b/drivers/gpu/drm/amd/dkms/m4/list-is-first.m4 new file mode 100644 index 0000000000000..566de635a47da --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/list-is-first.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit 70b44595eafe9c7c235f076d653a268ca1ab9fdb +dnl # Author: Mel Gorman +dnl # Date: Tue Mar 5 15:44:54 2019 -0800 +dnl # mm, compaction: use free lists to quickly locate a migration source +dnl # +AC_DEFUN([AC_AMDGPU_LIST_IS_FIRST], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + list_is_first(NULL, NULL); + ], [ + AC_DEFINE(HAVE_LIST_IS_FIRST, 1, + [list_is_first() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/list-rotate_to_front.m4 b/drivers/gpu/drm/amd/dkms/m4/list-rotate_to_front.m4 new file mode 100644 index 0000000000000..2e914f0314652 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/list-rotate_to_front.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit a16b53849913e742d086bb2b6f5e069ea2850c56 +dnl # Author: Tobin C. Harding +dnl # Date: Mon May 13 17:15:59 2019 -0700 +dnl # list: add function list_rotate_to_front() +dnl # +AC_DEFUN([AC_AMDGPU_LIST_ROTATE_TO_FRONT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + list_rotate_to_front(NULL, NULL); + ], [ + AC_DEFINE(HAVE_LIST_ROTATE_TO_FRONT, 1, + [list_rotate_to_front() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index fbb66d01e2665..4dbd06d3e8b6c 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -5,4 +5,5 @@ #include #include #include +#include #endif diff --git a/include/kcl/kcl_list.h b/include/kcl/kcl_list.h new file mode 100644 index 0000000000000..20e2bee6bef61 --- /dev/null +++ b/include/kcl/kcl_list.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_LIST_H +#define AMDKCL_LIST_H + +#include + +/* Copied from include/linux/list.h */ +#if !defined(HAVE_LIST_ROTATE_TO_FRONT) +static inline void list_rotate_to_front(struct list_head *list, + struct list_head *head) +{ + list_move_tail(head, list); +} +#endif + +#if !defined(HAVE_LIST_IS_FIRST) +static inline int list_is_first(const struct list_head *list, + const struct list_head *head) +{ + return list->prev == head; +} +#endif + +#endif /*AMDKCL_LIST_H*/ From 39ed5f3d85a07706cae5e9ea082a6f351b56b932 Mon Sep 17 00:00:00 2001 From: Junwei Zhang Date: Mon, 26 Dec 2016 13:42:16 +0800 Subject: [PATCH 0082/1868] drm/amdkcl: Test whether arch_io_{reserve/free}_memtype_wc() are available arch_io_reserve_memtype_wc is introduced in v4.9-rc2-1-g8ef4227615e1. rhel < 7.8 adds an inline define to drm_backport.h squash of e07c4960e087 drm/amdkcl: update test for arch_io_reserve_memtype_wc 1943acaa561d drm/amdkcl: Test whether arch_io_{reserve/free}_memtype_wc() are available c1f004d6344b drm/amdkcl: fix license for kcl part caba32ffd8e3 drm/amdkcl: include kcl_common.h in every .c Signed-off-by: Junwei Zhang Reviewed-by: Qiang Yu Signed-off-by: Jack Gui Signed-off-by: Slava Grigorev Signed-off-by: Yifan Zhang Signed-off-by: Jack Gui Signed-off-by: Chengming Gui Reviewed-by: Yifan Zhang Signed-off-by: Jack Gui Signed-off-by: Flora Cui Signed-off-by: Slava Grigorev Signed-off-by: Flora Cui Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_io.c | 73 +++++++++++++++++++ drivers/gpu/drm/amd/amdkcl/main.c | 2 + drivers/gpu/drm/amd/backport/backport.h | 1 + .../m4/arch-io-reserve-free-memtype-wc.m4 | 34 +++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/backport/kcl_io_backport.h | 47 ++++++++++++ 7 files changed, 159 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_io.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/arch-io-reserve-free-memtype-wc.m4 create mode 100644 include/kcl/backport/kcl_io_backport.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index daa8a87f99ce2..e12717b16961b 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -3,7 +3,7 @@ amdkcl-y += main.o symbols.o kcl_common.o amdkcl-y += kcl_kernel_params.o amdkcl-y += kcl_backlight.o kcl_ioctl.o \ - kcl_kthread.o + kcl_kthread.o kcl_io.o ccflags-y += \ -include $(src)/../dkms/config/config.h \ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_io.c b/drivers/gpu/drm/amd/amdkcl/kcl_io.c new file mode 100644 index 0000000000000..c1f2307557352 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_io.c @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Page Attribute Table (PAT) support: handle memory caching attributes in page tables. + * + * Authors: Venkatesh Pallipadi + * Suresh B Siddha + * + * Loosely based on earlier PAT patchset from Eric Biederman and Andi Kleen. + * + * Basic principles: + * + * PAT is a CPU feature supported by all modern x86 CPUs, to allow the firmware and + * the kernel to set one of a handful of 'caching type' attributes for physical + * memory ranges: uncached, write-combining, write-through, write-protected, + * and the most commonly used and default attribute: write-back caching. + * + * PAT support supercedes and augments MTRR support in a compatible fashion: MTRR is + * a hardware interface to enumerate a limited number of physical memory ranges + * and set their caching attributes explicitly, programmed into the CPU via MSRs. + * Even modern CPUs have MTRRs enabled - but these are typically not touched + * by the kernel or by user-space (such as the X server), we rely on PAT for any + * additional cache attribute logic. + * + * PAT doesn't work via explicit memory ranges, but uses page table entries to add + * cache attribute information to the mapped memory range: there's 3 bits used, + * (_PAGE_PWT, _PAGE_PCD, _PAGE_PAT), with the 8 possible values mapped by the + * CPU to actual cache attributes via an MSR loaded into the CPU (MSR_IA32_CR_PAT). + * + * ( There's a metric ton of finer details, such as compatibility with CPU quirks + * that only support 4 types of PAT entries, and interaction with MTRRs, see + * below for details. ) + */ +#include +#include + +/* Copied from arch/x86/mm/pat.c and modified for KCL */ +#if !defined(HAVE_ARCH_IO_RESERVE_FREE_MEMTYPE_WC) && \ + defined(CONFIG_X86) +#include + +static int (*_kcl_io_reserve_memtype)(resource_size_t start, resource_size_t end, + enum page_cache_mode *type); +static void (*_kcl_io_free_memtype)(resource_size_t start, resource_size_t end); + +int _kcl_arch_io_reserve_memtype_wc(resource_size_t start, resource_size_t size) +{ +#ifdef _PAGE_CACHE_WC + unsigned long type = _PAGE_CACHE_WC; +#else + enum page_cache_mode type = _PAGE_CACHE_MODE_WC; +#endif + + return _kcl_io_reserve_memtype(start, start + size, &type); +} +EXPORT_SYMBOL(_kcl_arch_io_reserve_memtype_wc); + +void _kcl_arch_io_free_memtype_wc(resource_size_t start, resource_size_t size) +{ + _kcl_io_free_memtype(start, start + size); +} +EXPORT_SYMBOL(_kcl_arch_io_free_memtype_wc); + +void amdkcl_io_init(void) +{ + _kcl_io_reserve_memtype = amdkcl_fp_setup("io_reserve_memtype", NULL); + _kcl_io_free_memtype = amdkcl_fp_setup("io_free_memtype", NULL); +} +#else +void amdkcl_io_init(void) +{ + +} +#endif /* HAVE_ARCH_IO_RESERVE_FREE_MEMTYPE_WC */ diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c index ecfe2b88b23ea..f28ee41f10753 100644 --- a/drivers/gpu/drm/amd/amdkcl/main.c +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -3,11 +3,13 @@ #include extern void amdkcl_symbol_init(void); +extern void amdkcl_io_init(void); extern void amdkcl_kthread_init(void); int __init amdkcl_init(void) { amdkcl_symbol_init(); + amdkcl_io_init(); amdkcl_kthread_init(); return 0; diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index f544a1b4f8e2c..054c67da0b571 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -15,5 +15,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/arch-io-reserve-free-memtype-wc.m4 b/drivers/gpu/drm/amd/dkms/m4/arch-io-reserve-free-memtype-wc.m4 new file mode 100644 index 0000000000000..8245a8d52ee43 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/arch-io-reserve-free-memtype-wc.m4 @@ -0,0 +1,34 @@ +dnl # +dnl # commit v4.9-rc2-1-g8ef4227615e1 +dnl # x86/io: add interface to reserve io memtype for a resource range. (v1.1) +dnl # +AC_DEFUN([AC_AMDGPU_ARCH_IO_RESERVE_FREE_MEMTYPE_WC], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + arch_io_reserve_memtype_wc(0, 0); + arch_io_free_memtype_wc(0, 0); + ], [arch_io_reserve_memtype_wc arch_io_free_memtype_wc], [arch/x86/mm/pat/memtype.c arch/x86/mm/pat.c], [ + AC_DEFINE(HAVE_ARCH_IO_RESERVE_FREE_MEMTYPE_WC, 1, + [arch_io_{reserve/free}_memtype_wc() are available]) + ], [ + AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DRM_BACKPORT_H + #include + #endif + #include + ], [ + #ifdef CONFIG_X86 + #error stub arch_io_* functions found + #endif + + arch_io_reserve_memtype_wc(0, 0); + arch_io_free_memtype_wc(0, 0); + ], [ + AC_DEFINE(HAVE_ARCH_IO_RESERVE_FREE_MEMTYPE_WC, 1, + [arch_io_{reserve/free}_memtype_wc() are available]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 133b418c86745..8fc3300a39266 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -19,6 +19,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU___KTHREAD_SHOULD_PARK AC_AMDGPU_LIST_ROTATE_TO_FRONT AC_AMDGPU_LIST_IS_FIRST + AC_AMDGPU_ARCH_IO_RESERVE_FREE_MEMTYPE_WC AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/backport/kcl_io_backport.h b/include/kcl/backport/kcl_io_backport.h new file mode 100644 index 0000000000000..8fe78d238e6f4 --- /dev/null +++ b/include/kcl/backport/kcl_io_backport.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright 2006 PathScale, Inc. All Rights Reserved. + */ +#ifndef AMDKCL_IO_H +#define AMDKCL_IO_H + +#include +#include + +/* Copied from arch/x86/include/asm/io.h + * include/linux/io.h + */ +#if !defined(HAVE_ARCH_IO_RESERVE_FREE_MEMTYPE_WC) + +#ifdef CONFIG_X86 +extern int _kcl_arch_io_reserve_memtype_wc(resource_size_t start, resource_size_t size); +extern void _kcl_arch_io_free_memtype_wc(resource_size_t start, resource_size_t size); +#define arch_io_reserve_memtype_wc _kcl_arch_io_reserve_memtype_wc +#define arch_io_free_memtype_wc _kcl_arch_io_free_memtype_wc +#endif + +#ifndef arch_io_reserve_memtype_wc +/* + * On x86 PAT systems we have memory tracking that keeps track of + * the allowed mappings on memory ranges. This tracking works for + * all the in-kernel mapping APIs (ioremap*), but where the user + * wishes to map a range from a physical device into user memory + * the tracking won't be updated. This API is to be used by + * drivers which remap physical device pages into userspace, + * and wants to make sure they are mapped WC and not UC. + */ +static inline int arch_io_reserve_memtype_wc(resource_size_t base, + resource_size_t size) +{ + return 0; +} + +static inline void arch_io_free_memtype_wc(resource_size_t base, + resource_size_t size) +{ +} +#endif + +#endif /* HAVE_ARCH_IO_RESERVE_FREE_MEMTYPE_WC */ + +#endif /* AMDKCL_IO_H */ From fc24fdec688ac02e461a0c5b6ee3a08075959e06 Mon Sep 17 00:00:00 2001 From: chen gong Date: Wed, 5 Jun 2019 12:36:47 +0800 Subject: [PATCH 0083/1868] drm/amdkcl: Test whether access_ok(x, x) is available v2: drop kcl_access_ok Signed-off-by: chen gong Reviewed-by: Slava Grigorev Signed-off-by: Yifan Zhang Signed-off-by: Jack Gui Acked-by: Feifei Xu Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/access-ok.m4 | 18 ++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/backport/kcl_uaccess_backport.h | 14 ++++++++++++++ 4 files changed, 34 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/access-ok.m4 create mode 100644 include/kcl/backport/kcl_uaccess_backport.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 054c67da0b571..596f6f5fccf5b 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -16,5 +16,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/access-ok.m4 b/drivers/gpu/drm/amd/dkms/m4/access-ok.m4 new file mode 100644 index 0000000000000..066bd767ddf78 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/access-ok.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit 96d4f267e40f9509e8a66e2b39e8b95655617693 +dnl # Author: Linus Torvalds +dnl # Date: Thu Jan 3 18:57:57 2019 -0800 +dnl # Remove 'type' argument from access_ok() function +dnl # +AC_DEFUN([AC_AMDGPU_ACCESS_OK_WITH_TWO_ARGUMENTS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + access_ok(1, 1); + ],[ + AC_DEFINE(HAVE_ACCESS_OK_WITH_TWO_ARGUMENTS, 1, + [whether access_ok(x, x) is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 8fc3300a39266..6f58d726463df 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -20,6 +20,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_LIST_ROTATE_TO_FRONT AC_AMDGPU_LIST_IS_FIRST AC_AMDGPU_ARCH_IO_RESERVE_FREE_MEMTYPE_WC + AC_AMDGPU_ACCESS_OK_WITH_TWO_ARGUMENTS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/backport/kcl_uaccess_backport.h b/include/kcl/backport/kcl_uaccess_backport.h new file mode 100644 index 0000000000000..c7466949cad39 --- /dev/null +++ b/include/kcl/backport/kcl_uaccess_backport.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_UACCESS_BACKPORT_H +#define AMDKCL_UACCESS_BACKPORT_H +#include + +#if !defined(HAVE_ACCESS_OK_WITH_TWO_ARGUMENTS) +static inline int _kcl_access_ok(unsigned long addr, unsigned long size) +{ + return access_ok(VERIFY_WRITE, (addr), (size)); +} +#undef access_ok +#define access_ok _kcl_access_ok +#endif +#endif From e70db2be537d94ee72c33ffd98e27271a546c617 Mon Sep 17 00:00:00 2001 From: changzhu Date: Thu, 27 Jun 2019 11:36:46 +0800 Subject: [PATCH 0084/1868] drm/amdkcl: Test whether perf_event_update_userpage() is available (v2) perf_event_update_userpage exported from kernel v4.16-rc1~34^2~88^2~7 v2: remove BUILD_AS_DKMS Signed-off-by: Chengming Gui Reviewed-by: Flora Cui Signed-off-by: Jack Gui drm/amdkcl: [4.16] fix perf_event_update_userpage unknown symbol build error [Why] perf_event_update_userpage is not exported in core.c until kernel version 4.16.0. So there will be unknown symbol error when using it before kernel version 4.16.0 [How] look up this symbol by using amdkcl_fp_setup Use kcl_perf_event_update_userpage to replace perf_event_update_userpage This kcl patch is caused by patch: fe96b896:drm/amdgpu: add pmu counters Change-Id: I0805e0116af2026fa0958cbda4755c75eb8bf839 Signed-off-by: changzhu Reviewed-by: Tianci Yin Signed-off-by: Jack Gui drm/amdkcl: fix check for perf_event_update_userpage() this break in-tree build Signed-off-by: Chengming Gui Reviewed-by: Flora Cui Signed-off-by: Jack Gui drm/amdkcl: drop kcl_perf_event_update_userpage Signed-off-by: Flora Cui Acked-by: Feifei Xu drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_perf_event.c | 23 +++++++++++++++++++ drivers/gpu/drm/amd/amdkcl/main.c | 2 ++ drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../amd/dkms/m4/perf-event-update-userpage.m4 | 14 +++++++++++ .../kcl/backport/kcl_perf_event_backport.h | 10 ++++++++ include/kcl/kcl_perf_event.h | 22 ++++++++++++++++++ 8 files changed, 74 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_perf_event.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/perf-event-update-userpage.m4 create mode 100644 include/kcl/backport/kcl_perf_event_backport.h create mode 100644 include/kcl/kcl_perf_event.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index e12717b16961b..849d86edbb6ad 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -3,7 +3,7 @@ amdkcl-y += main.o symbols.o kcl_common.o amdkcl-y += kcl_kernel_params.o amdkcl-y += kcl_backlight.o kcl_ioctl.o \ - kcl_kthread.o kcl_io.o + kcl_kthread.o kcl_io.o kcl_perf_event.o ccflags-y += \ -include $(src)/../dkms/config/config.h \ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_perf_event.c b/drivers/gpu/drm/amd/amdkcl/kcl_perf_event.c new file mode 100644 index 0000000000000..8c7914b6ff67d --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_perf_event.c @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Performance events core code: + * + * Copyright (C) 2008 Thomas Gleixner + * Copyright (C) 2008-2011 Red Hat, Inc., Ingo Molnar + * Copyright (C) 2008-2011 Red Hat, Inc., Peter Zijlstra + * Copyright © 2009 Paul Mackerras, IBM Corp. + */ +#include + +#if !defined(HAVE_PERF_EVENT_UPDATE_USERPAGE) +void (*_kcl_perf_event_update_userpage)(struct perf_event *event); +EXPORT_SYMBOL(_kcl_perf_event_update_userpage); +#endif + +void amdkcl_perf_event_init(void) +{ +#if !defined(HAVE_PERF_EVENT_UPDATE_USERPAGE) + _kcl_perf_event_update_userpage = amdkcl_fp_setup("perf_event_update_userpage", NULL); +#endif +} + diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c index f28ee41f10753..fcffe927688b7 100644 --- a/drivers/gpu/drm/amd/amdkcl/main.c +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -5,12 +5,14 @@ extern void amdkcl_symbol_init(void); extern void amdkcl_io_init(void); extern void amdkcl_kthread_init(void); +extern void amdkcl_perf_event_init(void); int __init amdkcl_init(void) { amdkcl_symbol_init(); amdkcl_io_init(); amdkcl_kthread_init(); + amdkcl_perf_event_init(); return 0; } diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 596f6f5fccf5b..cd7d1737e3114 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -17,5 +17,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 6f58d726463df..c5f26561583d5 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -21,6 +21,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_LIST_IS_FIRST AC_AMDGPU_ARCH_IO_RESERVE_FREE_MEMTYPE_WC AC_AMDGPU_ACCESS_OK_WITH_TWO_ARGUMENTS + AC_AMDGPU_PERF_EVENT_UPDATE_USERPAGE AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/perf-event-update-userpage.m4 b/drivers/gpu/drm/amd/dkms/m4/perf-event-update-userpage.m4 new file mode 100644 index 0000000000000..bf52b37b31d84 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/perf-event-update-userpage.m4 @@ -0,0 +1,14 @@ +dnl # +dnl # commit v4.15-rc3-1-g82975c46da82 +dnl # perf: Export perf_event_update_userpage +dnl # Export perf_event_update_userpage() so that PMU driver using them, +dnl # can be built as modules +dnl # +AC_DEFUN([AC_AMDGPU_PERF_EVENT_UPDATE_USERPAGE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([perf_event_update_userpage],[kernel/events/core.c],[ + AC_DEFINE(HAVE_PERF_EVENT_UPDATE_USERPAGE, 1, + [perf_event_update_userpage() is exported]) + ]) + ]) +]) diff --git a/include/kcl/backport/kcl_perf_event_backport.h b/include/kcl/backport/kcl_perf_event_backport.h new file mode 100644 index 0000000000000..41f336d7039a7 --- /dev/null +++ b/include/kcl/backport/kcl_perf_event_backport.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMD_KCL_PERF_EVENT_BACKPORT_H +#define AMD_KCL_PERF_EVENT_BACKPORT_H +#include +#include + +#if !defined(HAVE_PERF_EVENT_UPDATE_USERPAGE) +#define perf_event_update_userpage _kcl_perf_event_update_userpage +#endif +#endif diff --git a/include/kcl/kcl_perf_event.h b/include/kcl/kcl_perf_event.h new file mode 100644 index 0000000000000..b22cbc296b484 --- /dev/null +++ b/include/kcl/kcl_perf_event.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Performance events: + * + * Copyright (C) 2008-2009, Thomas Gleixner + * Copyright (C) 2008-2011, Red Hat, Inc., Ingo Molnar + * Copyright (C) 2008-2011, Red Hat, Inc., Peter Zijlstra + * + * Data type definitions, declarations, prototypes. + * + * Started by: Thomas Gleixner and Ingo Molnar + * + * For licencing details see kernel-base/COPYING + */ +#ifndef AMD_KCL_PERF_EVENT_H +#define AMD_KCL_PERF_EVENT_H +#include + +#if !defined(HAVE_PERF_EVENT_UPDATE_USERPAGE) +extern void (*_kcl_perf_event_update_userpage)(struct perf_event *event); +#endif +#endif From 6191566aaf21c411d04d1fbc01a02730cea6f472 Mon Sep 17 00:00:00 2001 From: changzhu Date: Thu, 6 Jun 2019 14:09:09 +0800 Subject: [PATCH 0085/1868] drm/amdkcl: check whether DEFINE_SHOW_ATTRIBUTE is available [Why] DEFINE_SHOW_ATTRIBUTE is not defined until kernel version(4,16,0).So there is build error when using DEFINE_SHOW_ATTRIBUTE before kernel version(4,16,0). This kcl patch is for patch: drm/amd/display: Add connector debugfs for "output_bpc" [How] Supply the definition of DEFINE_SHOW_ATTRIBUTE before kernel version(4.16.0) Change-Id: I2211b55c64e89d0cd17f746ac6b6cf581f42420d Signed-off-by: changzhu Reviewed-by: Kevin Wang Signed-off-by: Jack Gui Signed-off-by: Flora Cui drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_seq_file.h | 21 +++++++++++++++++++++ 2 files changed, 22 insertions(+) create mode 100644 include/kcl/kcl_seq_file.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index cd7d1737e3114..6321179c56ac6 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -18,5 +18,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_seq_file.h b/include/kcl/kcl_seq_file.h new file mode 100644 index 0000000000000..4e7750f341705 --- /dev/null +++ b/include/kcl/kcl_seq_file.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef AMDKCL_SEQ_FILE_H +#define AMDKCL_SEQ_FILE_H + +#ifndef DEFINE_SHOW_ATTRIBUTE +#define DEFINE_SHOW_ATTRIBUTE(__name) \ +static int __name ## _open(struct inode *inode, struct file *file) \ +{ \ + return single_open(file, __name ## _show, inode->i_private); \ +} \ + \ +static const struct file_operations __name ## _fops = { \ + .owner = THIS_MODULE, \ + .open = __name ## _open, \ + .read = seq_read, \ + .llseek = seq_lseek, \ + .release = single_release, \ +} +#endif + +#endif From 780ecddaaa20e127917006cef151549e8e1cc6c0 Mon Sep 17 00:00:00 2001 From: Chengming Gui Date: Fri, 11 Oct 2019 18:06:11 +0800 Subject: [PATCH 0086/1868] drm/amdkcl: check whether in_task() is available Signed-off-by: Chengming Gui Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_preempt.h | 56 +++++++++++++++++++++++++ 2 files changed, 57 insertions(+) create mode 100644 include/kcl/kcl_preempt.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 6321179c56ac6..3ddc21414e365 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -19,5 +19,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_preempt.h b/include/kcl/kcl_preempt.h new file mode 100644 index 0000000000000..d76961463a6e3 --- /dev/null +++ b/include/kcl/kcl_preempt.h @@ -0,0 +1,56 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef AMDKCL_PREEMPT_H +#define AMDKCL_PREEMPT_H +#include + +#ifndef in_task +#ifndef PREEMPT_BITS +/* + * We put the hardirq and softirq counter into the preemption + * counter. The bitmask has the following meaning: + * + * - bits 0-7 are the preemption count (max preemption depth: 256) + * - bits 8-15 are the softirq count (max # of softirqs: 256) + * + * The hardirq count could in theory be the same as the number of + * interrupts in the system, but we run all interrupt handlers with + * interrupts disabled, so we cannot have nesting interrupts. Though + * there are a few palaeontologic drivers which reenable interrupts in + * the handler, so we need more than one bit here. + * + * PREEMPT_MASK: 0x000000ff + * SOFTIRQ_MASK: 0x0000ff00 + * HARDIRQ_MASK: 0x000f0000 + * NMI_MASK: 0x00100000 + * PREEMPT_NEED_RESCHED: 0x80000000 + */ +#define PREEMPT_BITS 8 +#define SOFTIRQ_BITS 8 +#define HARDIRQ_BITS 4 +#define NMI_BITS 1 + +#define PREEMPT_SHIFT 0 +#define SOFTIRQ_SHIFT (PREEMPT_SHIFT + PREEMPT_BITS) +#define HARDIRQ_SHIFT (SOFTIRQ_SHIFT + SOFTIRQ_BITS) +#define NMI_SHIFT (HARDIRQ_SHIFT + HARDIRQ_BITS) + +#define __IRQ_MASK(x) ((1UL << (x))-1) + +#define PREEMPT_MASK (__IRQ_MASK(PREEMPT_BITS) << PREEMPT_SHIFT) +#define SOFTIRQ_MASK (__IRQ_MASK(SOFTIRQ_BITS) << SOFTIRQ_SHIFT) +#define HARDIRQ_MASK (__IRQ_MASK(HARDIRQ_BITS) << HARDIRQ_SHIFT) +#define NMI_MASK (__IRQ_MASK(NMI_BITS) << NMI_SHIFT) + +#define PREEMPT_OFFSET (1UL << PREEMPT_SHIFT) +#define SOFTIRQ_OFFSET (1UL << SOFTIRQ_SHIFT) +#define HARDIRQ_OFFSET (1UL << HARDIRQ_SHIFT) +#define NMI_OFFSET (1UL << NMI_SHIFT) + +#define SOFTIRQ_DISABLE_OFFSET (2 * SOFTIRQ_OFFSET) +#endif + +#define in_task() (!(preempt_count() & \ + (NMI_MASK | HARDIRQ_MASK | SOFTIRQ_OFFSET))) +#endif + +#endif /* AMDKCL_PREEMPT_H */ From b295eda4df1d327b97a2b853a2afff17098a2ae5 Mon Sep 17 00:00:00 2001 From: Adam Yang Date: Mon, 9 Sep 2019 16:26:20 +0800 Subject: [PATCH 0087/1868] drm/amdkcl: Test whether ksys_sync_helper() is available ksys_sync_helper() is used in commit: b17092bf14111fa1a35acd3b70ca72b3209a4abe dmr/amdgpu: Add system auto reboot to RAS. ksys_sync_helper() function is introduced in kernel 5.1-rc3 (b5dee3130bb40) in "kernel/power/main.c" which calls to ksys_sync() to do a filesystem sync. ksys_sync() is a helper function for sync() syscall which was refactored in kernel 4.16-rc5 (70f68ee81e2e) in "fs/sync.c". v2: drm/amd/autoconf: Fix typo and optimize ksys_sync_helper() v3: drm/amd/autoconf: Fix sys_sync() is not found after ksys_sync() exists v4: drm/amdkcl: fix test for ksys_sync() v5: drm/amdkcl: fix test for ksys_sync_helper Change-Id: I779764f65e6b6480c2067e2d817eef2f1cbf8482 Signed-off-by: Adam Yang Reviewed-by: Flora Cui Acked-by: Feifei Xu / Reviewed-by: Yifan Zhang Signed-off-by: Jack Gui drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 + drivers/gpu/drm/amd/amdkcl/Makefile | 3 +- drivers/gpu/drm/amd/amdkcl/kcl_suspend.c | 51 +++++++++++++++++++ drivers/gpu/drm/amd/amdkcl/main.c | 2 + drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../gpu/drm/amd/dkms/m4/ksys_sync_helper.m4 | 16 ++++++ include/kcl/kcl_suspend.h | 17 +++++++ 8 files changed, 91 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_suspend.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/ksys_sync_helper.m4 create mode 100644 include/kcl/kcl_suspend.h diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index a6b8d0ba4758c..bf2d266c2f21c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -29,6 +29,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 849d86edbb6ad..f76901fb1b532 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -3,7 +3,8 @@ amdkcl-y += main.o symbols.o kcl_common.o amdkcl-y += kcl_kernel_params.o amdkcl-y += kcl_backlight.o kcl_ioctl.o \ - kcl_kthread.o kcl_io.o kcl_perf_event.o + kcl_kthread.o kcl_io.o kcl_perf_event.o \ + kcl_suspend.o ccflags-y += \ -include $(src)/../dkms/config/config.h \ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_suspend.c b/drivers/gpu/drm/amd/amdkcl/kcl_suspend.c new file mode 100644 index 0000000000000..c7f1086ebabd3 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_suspend.c @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * kernel/power/main.c - PM subsystem core functionality. + * + * Copyright (c) 2003 Patrick Mochel + * Copyright (c) 2003 Open Source Development Lab + */ +#include +#include + +#ifndef HAVE_KSYS_SYNC_HELPER +/* Copied from kernel/power/main.c */ +#ifdef CONFIG_PM_SLEEP +long (*_kcl_ksys_sync)(void); + +void _kcl_ksys_sync_helper(void) +{ + pr_info("Syncing filesystems ... "); + _kcl_ksys_sync(); + pr_cont("done.\n"); +} +EXPORT_SYMBOL(_kcl_ksys_sync_helper); + +static bool _kcl_sys_sync_stub(void) +{ + pr_warn_once("kernel symbol [k]sys_sync not found!\n"); + return false; +} +#endif /* CONFIG_PM_SLEEP */ +#endif /* HAVE_KSYS_SYNC_HELPER */ + +void amdkcl_suspend_init(void) +{ +#ifndef HAVE_KSYS_SYNC_HELPER +#ifdef CONFIG_PM_SLEEP + _kcl_ksys_sync = amdkcl_fp_setup("ksys_sync", _kcl_sys_sync_stub); + if (_kcl_ksys_sync != _kcl_sys_sync_stub) { + return; + } + + _kcl_ksys_sync = amdkcl_fp_setup("sys_sync", _kcl_sys_sync_stub); + if (_kcl_ksys_sync != _kcl_sys_sync_stub) { + return; + } + + pr_err_once("Error: fail to get symbol [k]sys_sync!\n"); + BUG(); +#endif /* CONFIG_PM_SLEEP */ +#endif /* HAVE_KSYS_SYNC_HELPER */ +} + diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c index fcffe927688b7..47f9a9f4d3099 100644 --- a/drivers/gpu/drm/amd/amdkcl/main.c +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -6,6 +6,7 @@ extern void amdkcl_symbol_init(void); extern void amdkcl_io_init(void); extern void amdkcl_kthread_init(void); extern void amdkcl_perf_event_init(void); +extern void amdkcl_suspend_init(void); int __init amdkcl_init(void) { @@ -13,6 +14,7 @@ int __init amdkcl_init(void) amdkcl_io_init(); amdkcl_kthread_init(); amdkcl_perf_event_init(); + amdkcl_suspend_init(); return 0; } diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 3ddc21414e365..1c4017c8d899c 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -20,5 +20,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index c5f26561583d5..442e52a5bac1d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -22,6 +22,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_ARCH_IO_RESERVE_FREE_MEMTYPE_WC AC_AMDGPU_ACCESS_OK_WITH_TWO_ARGUMENTS AC_AMDGPU_PERF_EVENT_UPDATE_USERPAGE + AC_AMDGPU_KSYS_SYNC_HELPER AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/ksys_sync_helper.m4 b/drivers/gpu/drm/amd/dkms/m4/ksys_sync_helper.m4 new file mode 100644 index 0000000000000..039aafc937e0c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/ksys_sync_helper.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit b5dee3130bb4014511f5d0dd46855ed843e3fdc8 +dnl # PM / sleep: Refactor filesystems sync to reduce duplication +dnl # +AC_DEFUN([AC_AMDGPU_KSYS_SYNC_HELPER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + ksys_sync_helper(); + ], [ + AC_DEFINE(HAVE_KSYS_SYNC_HELPER, 1, + [ksys_sync_helper() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_suspend.h b/include/kcl/kcl_suspend.h new file mode 100644 index 0000000000000..37a3cab923aa5 --- /dev/null +++ b/include/kcl/kcl_suspend.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_SUSPEND_H +#define AMDKCL_SUSPEND_H + +#ifndef HAVE_KSYS_SYNC_HELPER +#ifdef CONFIG_PM_SLEEP +extern void _kcl_ksys_sync_helper(void); + +static inline void ksys_sync_helper(void) +{ + _kcl_ksys_sync_helper(); +} +#else +static inline void ksys_sync_helper(void) {} +#endif /* CONFIG_PM_SLEEP */ +#endif /* HAVE_KSYS_SYNC_HELPER */ +#endif /* AMDKCL_SUSPEND_H */ From 40fb097e7fb6cf9a765f5178789e3cd64a356a35 Mon Sep 17 00:00:00 2001 From: tianci yin Date: Thu, 29 Nov 2018 13:14:08 +0800 Subject: [PATCH 0088/1868] drm/amdkcl: Test whether pcie_get_{speed/width}_cap() are available v2: drm/amdkcl: [4.18] fix pcie speed and width relevant build err v3: drm/amdkcl: [4.17] fix pcie_get_speed_cap and pcie_get_width_cap v4: drm/amdkcl: refactor HAVE_PCIE_GET_SPEED_AND_WIDTH_CAP v5: drm/amdkcl: drop kcl_pcie_get_speed_cap Signed-off-by: Slava Grigorev Reviewed-by:Kevin Wang Signed-off-by: Tianci Yin Signed-off-by: Jack Gui Signed-off-by: changzhu Reviewed-by: Junwei Zhang Signed-off-by: Flora Cui Acked-by: Feifei Xu drm/amdkcl: update check for pcie_get_{speed,width}_cap check symbols exported is enough Change-Id: I13b0ecc561a5651af73e22b7294d93eb629062df Signed-off-by: Flora Cui Acked-by: Feifei Xu drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_pci.c | 99 +++++++++++++++++++ drivers/gpu/drm/amd/amdkcl/main.c | 2 + drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../amd/dkms/m4/pcie-get-speed-width-cap.m4 | 12 +++ include/kcl/backport/kcl_pci_backport.h | 12 +++ include/kcl/kcl_pci.h | 52 ++++++++++ 8 files changed, 180 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_pci.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/pcie-get-speed-width-cap.m4 create mode 100644 include/kcl/backport/kcl_pci_backport.h create mode 100644 include/kcl/kcl_pci.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index f76901fb1b532..970c396afa2ca 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -4,7 +4,7 @@ amdkcl-y += main.o symbols.o kcl_common.o amdkcl-y += kcl_kernel_params.o amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_kthread.o kcl_io.o kcl_perf_event.o \ - kcl_suspend.o + kcl_suspend.o kcl_pci.o ccflags-y += \ -include $(src)/../dkms/config/config.h \ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_pci.c b/drivers/gpu/drm/amd/amdkcl/kcl_pci.c new file mode 100644 index 0000000000000..3068db5234542 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_pci.c @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PCI Bus Services, see include/linux/pci.h for further explanation. + * + * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter, + * David Mosberger-Tang + * + * Copyright 1997 -- 2000 Martin Mares + * For codes copied from drivers/pci/pci.c + * + * (C) Copyright 2002-2004 Greg Kroah-Hartman + * (C) Copyright 2002-2004 IBM Corp. + * (C) Copyright 2003 Matthew Wilcox + * (C) Copyright 2003 Hewlett-Packard + * (C) Copyright 2004 Jon Smirl + * (C) Copyright 2004 Silicon Graphics, Inc. Jesse Barnes + * For codes copied from drivers/pci/pci-sysfs.c + */ + +#include +#include + +#if !defined(HAVE_PCIE_GET_SPEED_AND_WIDTH_CAP) +/* + * pcie_get_speed_cap - query for the PCI device's link speed capability + * @dev: PCI device to query + * + * Query the PCI device speed capability. Return the maximum link speed + * supported by the device. + */ +enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev) +{ + u32 lnkcap2, lnkcap; + + /* + * PCIe r4.0 sec 7.5.3.18 recommends using the Supported Link + * Speeds Vector in Link Capabilities 2 when supported, falling + * back to Max Link Speed in Link Capabilities otherwise. + */ + pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2); + if (lnkcap2) { /* PCIe r3.0-compliant */ + if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB) + return PCIE_SPEED_16_0GT; + else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) + return PCIE_SPEED_8_0GT; + else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) + return PCIE_SPEED_5_0GT; + else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) + return PCIE_SPEED_2_5GT; + return PCI_SPEED_UNKNOWN; + } + + pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); + if (lnkcap) { + if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB) + return PCIE_SPEED_16_0GT; + else if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB) + return PCIE_SPEED_8_0GT; + else if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB) + return PCIE_SPEED_5_0GT; + else if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB) + return PCIE_SPEED_2_5GT; + } + + return PCI_SPEED_UNKNOWN; +} + +/** + * pcie_get_width_cap - query for the PCI device's link width capability + * @dev: PCI device to query + * + * Query the PCI device width capability. Return the maximum link width + * supported by the device. + */ +enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev) +{ + u32 lnkcap; + + pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); + if (lnkcap) + return (lnkcap & PCI_EXP_LNKCAP_MLW) >> 4; + + return PCIE_LNK_WIDTH_UNKNOWN; +} +#endif + +enum pci_bus_speed (*_kcl_pcie_get_speed_cap)(struct pci_dev *dev); +EXPORT_SYMBOL(_kcl_pcie_get_speed_cap); + +enum pcie_link_width (*_kcl_pcie_get_width_cap)(struct pci_dev *dev); +EXPORT_SYMBOL(_kcl_pcie_get_width_cap); + +void amdkcl_pci_init(void) +{ +#if !defined(HAVE_PCIE_GET_SPEED_AND_WIDTH_CAP) + _kcl_pcie_get_speed_cap = amdkcl_fp_setup("pcie_get_speed_cap", pcie_get_speed_cap); + _kcl_pcie_get_width_cap = amdkcl_fp_setup("pcie_get_width_cap", pcie_get_width_cap); +#endif +} diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c index 47f9a9f4d3099..74bc8cf250e36 100644 --- a/drivers/gpu/drm/amd/amdkcl/main.c +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -6,6 +6,7 @@ extern void amdkcl_symbol_init(void); extern void amdkcl_io_init(void); extern void amdkcl_kthread_init(void); extern void amdkcl_perf_event_init(void); +extern void amdkcl_pci_init(void); extern void amdkcl_suspend_init(void); int __init amdkcl_init(void) @@ -14,6 +15,7 @@ int __init amdkcl_init(void) amdkcl_io_init(); amdkcl_kthread_init(); amdkcl_perf_event_init(); + amdkcl_pci_init(); amdkcl_suspend_init(); return 0; diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 1c4017c8d899c..070fd090c2313 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -21,5 +21,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 442e52a5bac1d..14ca3b10a47cf 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -23,6 +23,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_ACCESS_OK_WITH_TWO_ARGUMENTS AC_AMDGPU_PERF_EVENT_UPDATE_USERPAGE AC_AMDGPU_KSYS_SYNC_HELPER + AC_AMDGPU_PCIE_GET_SPEED_AND_WIDTH_CAP AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/pcie-get-speed-width-cap.m4 b/drivers/gpu/drm/amd/dkms/m4/pcie-get-speed-width-cap.m4 new file mode 100644 index 0000000000000..905b62bc15628 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pcie-get-speed-width-cap.m4 @@ -0,0 +1,12 @@ +dnl # +dnl # commit 576c7218a1546e0153480b208b125509cec71470 +dnl # PCI: Export pcie_get_speed_cap and pcie_get_width_cap +dnl # +AC_DEFUN([AC_AMDGPU_PCIE_GET_SPEED_AND_WIDTH_CAP], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([pcie_get_speed_cap pcie_get_width_cap], [drivers/pci/pci.c], [ + AC_DEFINE(HAVE_PCIE_GET_SPEED_AND_WIDTH_CAP, 1, + [pcie_get_speed_cap() and pcie_get_width_cap() exist]) + ]) + ]) +]) diff --git a/include/kcl/backport/kcl_pci_backport.h b/include/kcl/backport/kcl_pci_backport.h new file mode 100644 index 0000000000000..cc2af255e21b5 --- /dev/null +++ b/include/kcl/backport/kcl_pci_backport.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef AMDKCL_PCI_BACKPORT_H +#define AMDKCL_PCI_BACKPORT_H + +#include +#include +#include + +#if !defined(HAVE_PCIE_GET_SPEED_AND_WIDTH_CAP) +#define pcie_get_speed_cap _kcl_pcie_get_speed_cap +#endif +#endif diff --git a/include/kcl/kcl_pci.h b/include/kcl/kcl_pci.h new file mode 100644 index 0000000000000..f6f8425cea3b6 --- /dev/null +++ b/include/kcl/kcl_pci.h @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * pci.h + * + * PCI defines and function prototypes + * Copyright 1994, Drew Eckhardt + * Copyright 1997--1999 Martin Mares + * + * PCI Express ASPM defines and function prototypes + * Copyright (c) 2007 Intel Corp. + * Zhang Yanmin (yanmin.zhang@intel.com) + * Shaohua Li (shaohua.li@intel.com) + * + * For more information, please consult the following manuals (look at + * http://www.pcisig.com/ for how to get them): + * + * PCI BIOS Specification + * PCI Local Bus Specification + * PCI to PCI Bridge Specification + * PCI Express Specification + * PCI System Design Guide + */ +#ifndef AMDKCL_PCI_H +#define AMDKCL_PCI_H + +#include +#include + +#if !defined(HAVE_PCIE_GET_SPEED_AND_WIDTH_CAP) +extern enum pci_bus_speed (*_kcl_pcie_get_speed_cap)(struct pci_dev *dev); +extern enum pcie_link_width (*_kcl_pcie_get_width_cap)(struct pci_dev *dev); +#endif + +static inline enum pci_bus_speed kcl_pcie_get_speed_cap(struct pci_dev *dev) +{ +#if defined(HAVE_PCIE_GET_SPEED_AND_WIDTH_CAP) + return pcie_get_speed_cap(dev); +#else + return _kcl_pcie_get_speed_cap(dev); +#endif +} + +static inline enum pcie_link_width kcl_pcie_get_width_cap(struct pci_dev *dev) +{ +#if defined(HAVE_PCIE_GET_SPEED_AND_WIDTH_CAP) + return pcie_get_width_cap(dev); +#else + return _kcl_pcie_get_width_cap(dev); +#endif +} + +#endif /* AMDKCL_PCI_H */ From 455ee42f50acf22fb5c38269a8ddf9a27b090f94 Mon Sep 17 00:00:00 2001 From: tianci yin Date: Thu, 20 Dec 2018 10:40:10 +0800 Subject: [PATCH 0089/1868] drm/amdkcl: Test whether ktime_get_{ns/boottime_ns}() is available drm/amdkcl: [3.17] add kcl for ktime_get_ns [why] Below commit introduce the reference to ktime_to_ns, that is not defined on linux version < 3.17, so implement it here. drm/amd/display: Use div_u64 for flip timestamp ns to ms Reviewed-by: Prike Liang Signed-off-by: Tianci Yin Signed-off-by: Jack Gui drm/amd/autoconf: Test whether ktime_get_ns() is available ktime_get_ns introduced by kernel v3.17-rc1~109^2~41 Signed-off-by: Chengming Gui Reviewed-by: Flora Cui Signed-off-by: Jack Gui drm/amdkcl: test whether ktime_get_boottime_ns() is available Signed-off-by: Flora Cui Reviewed-by: Jack Gui Signed-off-by: Jack Gui drm/amdkcl: refactor ktime_xxx in kcl Signed-off-by: Flora Cui Reviewed-by: Jack Gui Signed-off-by: Jack Gui drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../drm/amd/dkms/m4/ktime-get-boottime-ns.m4 | 32 +++++++++++++++++++ include/kcl/kcl_timekeeping.h | 30 +++++++++++++++++ 4 files changed, 64 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/ktime-get-boottime-ns.m4 create mode 100644 include/kcl/kcl_timekeeping.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 070fd090c2313..6b31d63564d30 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -22,5 +22,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 14ca3b10a47cf..4ded23a9914a8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -24,6 +24,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_PERF_EVENT_UPDATE_USERPAGE AC_AMDGPU_KSYS_SYNC_HELPER AC_AMDGPU_PCIE_GET_SPEED_AND_WIDTH_CAP + AC_AMDGPU_KTIME_GET_BOOTTIME_NS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/ktime-get-boottime-ns.m4 b/drivers/gpu/drm/amd/dkms/m4/ktime-get-boottime-ns.m4 new file mode 100644 index 0000000000000..234ef7efa54b4 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/ktime-get-boottime-ns.m4 @@ -0,0 +1,32 @@ +dnl # +dnl # commit v5.2-rc5-8-g9285ec4c8b61 +dnl # timekeeping: Use proper clock specifier names in functions +dnl # +AC_DEFUN([AC_AMDGPU_KTIME_GET_BOOTTIME_NS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + ktime_get_boottime_ns(); + ], [ + AC_DEFINE(HAVE_KTIME_GET_BOOTTIME_NS, 1, + [ktime_get_boottime_ns() is available]) + AC_DEFINE(HAVE_KTIME_GET_NS, 1, + [ktime_get_ns is available]) + ],[ + dnl # + dnl # commit v3.16-rc5-76-g897994e32b2b + dnl # timekeeping: Provide ktime_get[*]_ns() helpers + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + ktime_get_ns(); + ], [ + AC_DEFINE(HAVE_KTIME_GET_NS, 1, + [ktime_get_ns is available]) + ]) + ]) + ]) +]) diff --git a/include/kcl/kcl_timekeeping.h b/include/kcl/kcl_timekeeping.h new file mode 100644 index 0000000000000..cddc7d78548af --- /dev/null +++ b/include/kcl/kcl_timekeeping.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _KCL_LINUX_TIMEKEEPING_H +#define _KCL_LINUX_TIMEKEEPING_H +#include + +#ifndef HAVE_KTIME_GET_NS +static inline u64 ktime_get_ns(void) +{ + return ktime_to_ns(ktime_get()); +} +#endif + +#if !defined(HAVE_KTIME_GET_BOOTTIME_NS) +#if defined(HAVE_KTIME_GET_NS) +static inline u64 ktime_get_boottime_ns(void) +{ + return ktime_get_boot_ns(); +} +#else +static inline u64 ktime_get_boottime_ns(void) +{ + struct timespec time; + + get_monotonic_boottime(&time); + return (u64)timespec_to_ns(&time); +} +#endif /* HAVE_KTIME_GET_NS */ +#endif /* HAVE_KTIME_GET_BOOTTIME_NS */ + +#endif From 3e56082c6552912013cfecbe5a5e56df0edc124d Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 24 Aug 2020 15:35:12 +0800 Subject: [PATCH 0090/1868] drm/amdkcl: add kcl copy of untagged_addr Signed-off-by: Flora Cui drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_mm.h | 17 +++++++++++++++++ 2 files changed, 18 insertions(+) create mode 100644 include/kcl/kcl_mm.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 6b31d63564d30..e8f422617b83d 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -23,5 +23,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_mm.h b/include/kcl/kcl_mm.h new file mode 100644 index 0000000000000..f300ba76bf794 --- /dev/null +++ b/include/kcl/kcl_mm.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * linux/ipc/util.c + * Copyright (C) 1992 Krishna Balasubramanian + * For kvmalloc/kvzalloc + */ +#ifndef AMDKCL_MM_H +#define AMDKCL_MM_H + +#include + +#ifndef untagged_addr +/* Copied from include/linux/mm.h */ +#define untagged_addr(addr) (addr) +#endif + +#endif /* AMDKCL_MM_H */ From 8a51e3784f9dc88e45e266b19a1378cdbfad1383 Mon Sep 17 00:00:00 2001 From: Kevin Wang Date: Mon, 18 Feb 2019 11:00:12 +0800 Subject: [PATCH 0091/1868] drm/amdkcl: Test whether mm_access is available v1: 183d99136d50 - drm/amdkcl: add kcl mm_access funtions v2: 1ef72c2b349f - drm/amd/autoconf: Test whether mm_access is available Signed-off-by: Kevin Wang Reviewed-by: Junwei Zhang Reviewed-by: Felix Kuehling Reviewed-by: Harish Kasiviswanathan Signed-off-by: Chengming Gui Reviewed-by: Flora Cui drm/amdkcl: refactor mm_access() check Signed-off-by: Flora Cui Reviewed-by: Feifei Xu Signed-off-by: Jack Gui drm/amdkcl: drop kcl_mm_access Signed-off-by: Flora Cui Acked-by: Feifei Xu Signed-off-by: Flora Cui Signed-off-by: Yifan Zhang Signed-off-by: Flora Cui drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_mm.c | 11 +++++++++++ drivers/gpu/drm/amd/amdkcl/main.c | 2 ++ drivers/gpu/drm/amd/backport/backport.h | 2 +- include/kcl/backport/kcl_mm_backport.h | 8 ++++++++ 5 files changed, 23 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_mm.c create mode 100644 include/kcl/backport/kcl_mm_backport.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 970c396afa2ca..d0d3996bbc5e6 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -4,7 +4,7 @@ amdkcl-y += main.o symbols.o kcl_common.o amdkcl-y += kcl_kernel_params.o amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_kthread.o kcl_io.o kcl_perf_event.o \ - kcl_suspend.o kcl_pci.o + kcl_suspend.o kcl_pci.o kcl_mm.o ccflags-y += \ -include $(src)/../dkms/config/config.h \ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_mm.c b/drivers/gpu/drm/amd/amdkcl/kcl_mm.c new file mode 100644 index 0000000000000..e60ac00cba573 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_mm.c @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * linux/kernel/fork.c + * + * Copyright (C) 1991, 1992 Linus Torvalds + */ +#include + +void amdkcl_mm_init(void) +{ +} diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c index 74bc8cf250e36..178c0b724cc9e 100644 --- a/drivers/gpu/drm/amd/amdkcl/main.c +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -5,6 +5,7 @@ extern void amdkcl_symbol_init(void); extern void amdkcl_io_init(void); extern void amdkcl_kthread_init(void); +extern void amdkcl_mm_init(void); extern void amdkcl_perf_event_init(void); extern void amdkcl_pci_init(void); extern void amdkcl_suspend_init(void); @@ -14,6 +15,7 @@ int __init amdkcl_init(void) amdkcl_symbol_init(); amdkcl_io_init(); amdkcl_kthread_init(); + amdkcl_mm_init(); amdkcl_perf_event_init(); amdkcl_pci_init(); amdkcl_suspend_init(); diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index e8f422617b83d..d69a6c2b59c46 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -23,6 +23,6 @@ #include #include #include -#include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/backport/kcl_mm_backport.h b/include/kcl/backport/kcl_mm_backport.h new file mode 100644 index 0000000000000..055945c8728ef --- /dev/null +++ b/include/kcl/backport/kcl_mm_backport.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_MM_BACKPORT_H +#define AMDKCL_MM_BACKPORT_H +#include +#include +#include + +#endif From 0f65dedafd797d55b24927fada8d2f6669bf0d13 Mon Sep 17 00:00:00 2001 From: Adam Yang Date: Mon, 23 Sep 2019 19:59:17 +0800 Subject: [PATCH 0092/1868] drm/amdkcl: Test whether mmu_notifier_range_blockable() is available v2: drm/amdkcl: refactor kcl copy of mmu_notifier_range_blockable v3: drm/amdkcl: refactor kcl copy of mmu_notifier_range_blockable Signed-off-by: Adam Yang Signed-off-by: Flora Cui Signed-off-by: Jack Gui Reviewed-by: Yifan Zhang drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/mmu-notifier.m4 | 16 +++++++++++++ include/kcl/kcl_mmu_notifier.h | 25 +++++++++++++++++++++ 4 files changed, 43 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/mmu-notifier.m4 create mode 100644 include/kcl/kcl_mmu_notifier.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index d69a6c2b59c46..461f8acef66e4 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 4ded23a9914a8..03e7884a96ae3 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -25,6 +25,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_KSYS_SYNC_HELPER AC_AMDGPU_PCIE_GET_SPEED_AND_WIDTH_CAP AC_AMDGPU_KTIME_GET_BOOTTIME_NS + AC_AMDGPU_MMU_NOTIFIER AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/mmu-notifier.m4 b/drivers/gpu/drm/amd/dkms/m4/mmu-notifier.m4 new file mode 100644 index 0000000000000..06742541fd0d9 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/mmu-notifier.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit 4a83bfe916f3d2100df5bc8389bd182a537ced3e +dnl # mm/mmu_notifier: helper to test if a range invalidation is blockable +dnl # +AC_DEFUN([AC_AMDGPU_MMU_NOTIFIER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + mmu_notifier_range_blockable(NULL); + ], [ + AC_DEFINE(HAVE_MMU_NOTIFIER_RANGE_BLOCKABLE, 1, + [mmu_notifier_range_blockable() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_mmu_notifier.h b/include/kcl/kcl_mmu_notifier.h new file mode 100644 index 0000000000000..1af9433bdbfe5 --- /dev/null +++ b/include/kcl/kcl_mmu_notifier.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_MMU_NOTIFIER_H +#define AMDKCL_MMU_NOTIFIER_H + +#include + +#if !defined(HAVE_MMU_NOTIFIER_RANGE_BLOCKABLE) && \ + defined(HAVE_2ARGS_INVALIDATE_RANGE_START) +/* Copied from v5.1-10225-g4a83bfe916f3 include/linux/mmu_notifier.h */ +#ifdef CONFIG_MMU_NOTIFIER +static inline bool +mmu_notifier_range_blockable(const struct mmu_notifier_range *range) +{ + return range->blockable; +} +#else +static inline bool +mmu_notifier_range_blockable(const struct mmu_notifier_range *range) +{ + return true; +} +#endif +#endif /* HAVE_MMU_NOTIFIER_RANGE_BLOCKABLE */ + +#endif /* AMDKCL_MMU_NOTIFIER_H */ From 286a4b9bd96cbdbb678cbcfe45735ac008ba07c8 Mon Sep 17 00:00:00 2001 From: Anatoli Antonovitch Date: Wed, 9 Jan 2019 14:52:55 -0500 Subject: [PATCH 0093/1868] drm/amdkcl: Test whether release_pages() wants 2 args Signed-off-by: Anatoli Antonovitch Signed-off-by: Yifan Zhang Signed-off-by: Jack Gui drm/amdkcl: drop HAVE_2ARGS_MM_RELEASE_PAGES check in amdgpu Signed-off-by: Flora Cui Acked-by: Feifei Xu drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../gpu/drm/amd/dkms/m4/mm-release-pages.m4 | 19 +++++++++++++++++++ include/kcl/kcl_pagemap.h | 14 ++++++++++++++ 4 files changed, 35 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/mm-release-pages.m4 create mode 100644 include/kcl/kcl_pagemap.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 461f8acef66e4..dbc09bd4e19ec 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -25,5 +25,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 03e7884a96ae3..54f143f96c573 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -26,6 +26,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_PCIE_GET_SPEED_AND_WIDTH_CAP AC_AMDGPU_KTIME_GET_BOOTTIME_NS AC_AMDGPU_MMU_NOTIFIER + AC_AMDGPU_MM_RELEASE_PAGES AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/mm-release-pages.m4 b/drivers/gpu/drm/amd/dkms/m4/mm-release-pages.m4 new file mode 100644 index 0000000000000..7db093a925e04 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/mm-release-pages.m4 @@ -0,0 +1,19 @@ +dnl # +dnl # commit c6f92f9fbe7dbcc8903a67229aa88b4077ae4422 +dnl # mm: remove cold parameter for release_pages +dnl # +AC_DEFUN([AC_AMDGPU_MM_RELEASE_PAGES], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + struct page **pages = NULL; + int nr = 0; + + release_pages(pages, nr); + ], [release_pages], [mm/swap.c], [ + AC_DEFINE(HAVE_MM_RELEASE_PAGES_2ARGS, 1, + [release_pages() wants 2 args]) + ]) + ]) +]) diff --git a/include/kcl/kcl_pagemap.h b/include/kcl/kcl_pagemap.h new file mode 100644 index 0000000000000..f95a11d945ebc --- /dev/null +++ b/include/kcl/kcl_pagemap.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_PAGEMAP_H +#define AMDKCL_PAGEMAP_H + +#include + +#ifndef HAVE_MM_RELEASE_PAGES_2ARGS +static inline void _kcl_release_pages(struct page **pages, int nr) +{ + release_pages(pages, nr, 0); +} +#define release_pages _kcl_release_pages +#endif +#endif From 5b4cb151fd3b94c32c3d1a8504f63b42ae8b36f5 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 27 Aug 2020 16:23:54 +0800 Subject: [PATCH 0094/1868] drm/amdkcl: add kcl copy of DPM_FLAG_NO_DIRECT_COMPLETE Signed-off-by: Flora Cui drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_pm.h | 20 ++++++++++++++++++++ 2 files changed, 21 insertions(+) create mode 100644 include/kcl/kcl_pm.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index dbc09bd4e19ec..99c0e0097a95b 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -26,5 +26,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_pm.h b/include/kcl/kcl_pm.h new file mode 100644 index 0000000000000..157fc65f14708 --- /dev/null +++ b/include/kcl/kcl_pm.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * pm.h - Power management interface + * + * Copyright (C) 2000 Andrew Henroid + */ +#ifndef KCL_KCL_PM_H +#define KCL_KCL_PM_H + +#include + +/* + * v5.7-rc2-7-ge07515563d01 + * PM: sleep: core: Rename DPM_FLAG_NEVER_SKIP + */ +#ifndef DPM_FLAG_NO_DIRECT_COMPLETE +#define DPM_FLAG_NO_DIRECT_COMPLETE DPM_FLAG_NEVER_SKIP +#endif + +#endif From 4c34a216a6eda70eea9f5181e5e20bfde07640a8 Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Mon, 13 Apr 2020 16:51:26 +0800 Subject: [PATCH 0095/1868] drm/amdkcl: add AC_AMDGPU_DMA_FENCE_HEADERS it is a squash of: commit e1d2e9c077849c7aa9732709870762117e6c435a Author: Slava Grigorev Date: Tue Feb 25 21:30:21 2020 -0500 drm/amdkcl: Fix in-tree build if locate of output files (O=) specified Signed-off-by: Slava Grigorev commit 671508e545e8b7e6fda2209dfb2aae21e9b7ae54 Author: Slava Grigorev Date: Thu Feb 20 15:57:12 2020 -0500 drm/amdkcl: drop AC_KERNEL_TEST_HEADER_FILE_EXIST macro remove AC_KERNEL_TEST_HEADER_FILE_EXIST macro from AC_AMDGPU_DRM_DEV_SUPPORTED test Signed-off-by: Slava Grigorev Reviewed-by: Flora Cui commit 5ebd41454f8a12b84f590c3c68e4333246ce1b53 Author: Slava Grigorev Date: Thu Feb 20 14:55:08 2020 -0500 drm/amdkcl: modify dma-fence-headers test to use AC_KERENEL_CHECK_HERDERS macro Signed-off-by: Slava Grigorev Reviewed-by: Flora Cui commit c1f004d6344bd8c1c04343526b033c2768adfce7 Author: Flora Cui Date: Mon Nov 16 10:46:04 2020 +0800 drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling commit 49e2c50a5557ee4bd46b80c790bcca4db4cd9f3e Author: Ma Jun Date: Tue Feb 7 13:30:10 2023 +0800 drm/amdkcl: kcl-cleanup HAVE_DMA_FENCE_SET_ERROR Change-Id: I596491f1c0408de56017aa069a2211216fb08564 Signed-off-by: Ma Jun Reviewed-by: Leslie Shi commit 42c151d86739eb7be4b3db0ff66f467e6eb1f2ba Author: Ma Jun Date: Tue Feb 7 13:32:58 2023 +0800 drm/amdkcl: kcl-cleanup HAVE_DMA_FENCE_GET_STUB Change-Id: I9ca75886eed67777eb35c3958e763d485a1d9b1f Signed-off-by: Ma Jun Signed-off-by: Flora Cui Change-Id: I2ceeb8dc72f5ed53ebdd507b71faab67c59b56ab Signed-off-by: Yifan Zhang --- drivers/gpu/drm/amd/amdkcl/Makefile | 3 +- drivers/gpu/drm/amd/amdkcl/kcl_fence.c | 244 ++++++++++++++++++ drivers/gpu/drm/amd/amdkcl/kcl_fence_array.c | 149 +++++++++++ drivers/gpu/drm/amd/amdkcl/main.c | 2 + drivers/gpu/drm/amd/backport/backport.h | 1 + .../gpu/drm/amd/dkms/m4/dma-fence-headers.m4 | 18 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/scheduler/backport/backport.h | 1 + drivers/gpu/drm/ttm/backport/backport.h | 1 + include/kcl/backport/kcl_fence_backport.h | 33 +++ include/kcl/kcl_fence.h | 156 +++++++++++ include/kcl/kcl_fence_array.h | 82 ++++++ 12 files changed, 690 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_fence.c create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_fence_array.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/dma-fence-headers.m4 create mode 100644 include/kcl/backport/kcl_fence_backport.h create mode 100644 include/kcl/kcl_fence.h create mode 100644 include/kcl/kcl_fence_array.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index d0d3996bbc5e6..f705e8bab0e99 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -4,7 +4,8 @@ amdkcl-y += main.o symbols.o kcl_common.o amdkcl-y += kcl_kernel_params.o amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_kthread.o kcl_io.o kcl_perf_event.o \ - kcl_suspend.o kcl_pci.o kcl_mm.o + kcl_suspend.o kcl_pci.o kcl_mm.o \ + kcl_fence.o kcl_fence_array.o ccflags-y += \ -include $(src)/../dkms/config/config.h \ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fence.c b/drivers/gpu/drm/amd/amdkcl/kcl_fence.c new file mode 100644 index 0000000000000..c67cae784f75a --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fence.c @@ -0,0 +1,244 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Fence mechanism for dma-buf and to allow for asynchronous dma access + * + * Copyright (C) 2012 Canonical Ltd + * Copyright (C) 2012 Texas Instruments + * + * Authors: + * Rob Clark + * Maarten Lankhorst + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include + +#define CREATE_TRACE_POINTS +#include "kcl_trace.h" + +/* Copied from drivers/dma-buf/dma-fence.c */ +static bool +dma_fence_test_signaled_any(struct dma_fence **fences, uint32_t count, + uint32_t *idx) +{ + int i; + + for (i = 0; i < count; ++i) { + struct dma_fence *fence = fences[i]; + if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) { + if (idx) + *idx = i; + return true; + } + } + return false; +} + +struct default_wait_cb { + struct dma_fence_cb base; + struct task_struct *task; +}; + +static void (*_kcl_fence_default_wait_cb)(struct dma_fence *fence, struct dma_fence_cb *cb); + +#ifdef AMDKCL_FENCE_DEFAULT_WAIT_TIMEOUT +signed long +_kcl_fence_default_wait(struct dma_fence *fence, bool intr, signed long timeout) +{ + struct default_wait_cb cb; + unsigned long flags; + signed long ret = timeout ? timeout : 1; + bool was_set; + + if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) + return ret; + + spin_lock_irqsave(fence->lock, flags); + + if (intr && signal_pending(current)) { + ret = -ERESTARTSYS; + goto out; + } + + was_set = test_and_set_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, + &fence->flags); + + if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) + goto out; + + if (!was_set && fence->ops->enable_signaling) { + /* + * Modifications [2017-03-29] (c) [2017] + * Advanced Micro Devices, Inc. + */ + trace_kcl_fence_enable_signal(fence); + + if (!fence->ops->enable_signaling(fence)) { + dma_fence_signal_locked(fence); + goto out; + } + } + + if (!timeout) { + ret = 0; + goto out; + } + + cb.base.func = _kcl_fence_default_wait_cb; + cb.task = current; + list_add(&cb.base.node, &fence->cb_list); + + while (!test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags) && ret > 0) { + if (intr) + __set_current_state(TASK_INTERRUPTIBLE); + else + __set_current_state(TASK_UNINTERRUPTIBLE); + spin_unlock_irqrestore(fence->lock, flags); + + ret = schedule_timeout(ret); + + spin_lock_irqsave(fence->lock, flags); + if (ret > 0 && intr && signal_pending(current)) + ret = -ERESTARTSYS; + } + + if (!list_empty(&cb.base.node)) + list_del(&cb.base.node); + __set_current_state(TASK_RUNNING); + +out: + spin_unlock_irqrestore(fence->lock, flags); + return ret; +} +EXPORT_SYMBOL(_kcl_fence_default_wait); +#endif + + +/* + * Modifications [2017-09-19] (c) [2017] + * Advanced Micro Devices, Inc. + */ +#ifdef AMDKCL_FENCE_WAIT_ANY_TIMEOUT +signed long +_kcl_fence_wait_any_timeout(struct dma_fence **fences, uint32_t count, + bool intr, signed long timeout, uint32_t *idx) +{ + struct default_wait_cb *cb; + signed long ret = timeout; + unsigned i; + + if (WARN_ON(!fences || !count || timeout < 0)) + return -EINVAL; + + if (timeout == 0) { + for (i = 0; i < count; ++i) + if (dma_fence_is_signaled(fences[i])) { + if (idx) + *idx = i; + return 1; + } + + return 0; + } + + cb = kcalloc(count, sizeof(struct default_wait_cb), GFP_KERNEL); + if (cb == NULL) { + ret = -ENOMEM; + goto err_free_cb; + } + + for (i = 0; i < count; ++i) { + struct dma_fence *fence = fences[i]; + + + cb[i].task = current; + if (dma_fence_add_callback(fence, &cb[i].base, + _kcl_fence_default_wait_cb)) { + /* This fence is already signaled */ + if (idx) + *idx = i; + goto fence_rm_cb; + } + } + + while (ret > 0) { + if (intr) + set_current_state(TASK_INTERRUPTIBLE); + else + set_current_state(TASK_UNINTERRUPTIBLE); + + if (dma_fence_test_signaled_any(fences, count, idx)) + break; + + ret = schedule_timeout(ret); + + if (ret > 0 && intr && signal_pending(current)) + ret = -ERESTARTSYS; + } + + __set_current_state(TASK_RUNNING); + +fence_rm_cb: + while (i-- > 0) + dma_fence_remove_callback(fences[i], &cb[i].base); + +err_free_cb: + kfree(cb); + + return ret; +} +EXPORT_SYMBOL(_kcl_fence_wait_any_timeout); +#endif + +#ifdef AMDKCL_FENCE_DEFAULT_WAIT_TIMEOUT +signed long +_kcl_fence_wait_timeout(struct dma_fence *fence, bool intr, signed long timeout) +{ + signed long ret; + + if (WARN_ON(timeout < 0)) + return -EINVAL; + + /* + * Modifications [2017-03-29] (c) [2017] + * Advanced Micro Devices, Inc. + */ + trace_kcl_fence_wait_start(fence); + if (fence->ops->wait) + ret = fence->ops->wait(fence, intr, timeout); + else + ret = _kcl_fence_default_wait(fence, intr, timeout); + trace_kcl_fence_wait_end(fence); + return ret; +} +EXPORT_SYMBOL(_kcl_fence_wait_timeout); +#endif + +#ifdef AMDKCL_DMA_FENCE_OPS_ENABLE_SIGNALING +bool _kcl_fence_enable_signaling(struct dma_fence *f) +{ + return true; +} +EXPORT_SYMBOL(_kcl_fence_enable_signaling); +#endif +/* + * Modifications [2016-12-23] (c) [2016] + * Advanced Micro Devices, Inc. + */ +void amdkcl_fence_init(void) +{ +#if defined(HAVE_LINUX_DMA_FENCE_H) + _kcl_fence_default_wait_cb = amdkcl_fp_setup("dma_fence_default_wait_cb", NULL); +#else + _kcl_fence_default_wait_cb = amdkcl_fp_setup("fence_default_wait_cb", NULL); +#endif +} diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fence_array.c b/drivers/gpu/drm/amd/amdkcl/kcl_fence_array.c new file mode 100644 index 0000000000000..d42a986ecfe1d --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fence_array.c @@ -0,0 +1,149 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * fence-array: aggregate fences to be waited together + * + * Copyright (C) 2016 Collabora Ltd + * Copyright (C) 2016 Advanced Micro Devices, Inc. + * Authors: + * Gustavo Padovan + * Christian König + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include +#include +#include + +#if !defined(HAVE_LINUX_DMA_FENCE_H) && !defined(HAVE_LINUX_FENCE_ARRAY_H) +static void fence_array_cb_func(struct fence *f, struct fence_cb *cb); + +static const char *fence_array_get_driver_name(struct fence *fence) +{ + return "fence_array"; +} + +static const char *fence_array_get_timeline_name(struct fence *fence) +{ + return "unbound"; +} + +static void fence_array_cb_func(struct fence *f, struct fence_cb *cb) +{ + struct fence_array_cb *array_cb = + container_of(cb, struct fence_array_cb, cb); + struct fence_array *array = array_cb->array; + + if (atomic_dec_and_test(&array->num_pending)) + fence_signal(&array->base); + fence_put(&array->base); +} + +static bool fence_array_enable_signaling(struct fence *fence) +{ + struct fence_array *array = to_fence_array(fence); + struct fence_array_cb *cb = (void *)(&array[1]); + unsigned i; + + for (i = 0; i < array->num_fences; ++i) { + cb[i].array = array; + /* + * As we may report that the fence is signaled before all + * callbacks are complete, we need to take an additional + * reference count on the array so that we do not free it too + * early. The core fence handling will only hold the reference + * until we signal the array as complete (but that is now + * insufficient). + */ + fence_get(&array->base); + if (fence_add_callback(array->fences[i], &cb[i].cb, + fence_array_cb_func)) { + fence_put(&array->base); + if (atomic_dec_and_test(&array->num_pending)) + return false; + } + } + + return true; +} + +static bool fence_array_signaled(struct fence *fence) +{ + struct fence_array *array = to_fence_array(fence); + + return atomic_read(&array->num_pending) <= 0; +} + +static void fence_array_release(struct fence *fence) +{ + struct fence_array *array = to_fence_array(fence); + unsigned i; + + for (i = 0; i < array->num_fences; ++i) + fence_put(array->fences[i]); + + kfree(array->fences); + fence_free(fence); +} + +const struct fence_ops fence_array_ops = { + .get_driver_name = fence_array_get_driver_name, + .get_timeline_name = fence_array_get_timeline_name, + .enable_signaling = fence_array_enable_signaling, + .signaled = fence_array_signaled, + .wait = _kcl_fence_default_wait, + .release = fence_array_release, +}; + +/** + * fence_array_create - Create a custom fence array + * @num_fences: [in] number of fences to add in the array + * @fences: [in] array containing the fences + * @context: [in] fence context to use + * @seqno: [in] sequence number to use + * @signal_on_any [in] signal on any fence in the array + * + * Allocate a fence_array object and initialize the base fence with fence_init(). + * In case of error it returns NULL. + * + * The caller should allocte the fences array with num_fences size + * and fill it with the fences it wants to add to the object. Ownership of this + * array is take and fence_put() is used on each fence on release. + * + * If @signal_on_any is true the fence array signals if any fence in the array + * signals, otherwise it signals when all fences in the array signal. + */ +struct fence_array *fence_array_create(int num_fences, struct fence **fences, + u64 context, unsigned seqno, + bool signal_on_any) +{ + struct fence_array *array; + size_t size = sizeof(*array); + + /* Allocate the callback structures behind the array. */ + size += num_fences * sizeof(struct fence_array_cb); + array = kzalloc(size, GFP_KERNEL); + if (!array) + return NULL; + + spin_lock_init(&array->lock); + fence_init(&array->base, &fence_array_ops, &array->lock, + context, seqno); + + array->num_fences = num_fences; + atomic_set(&array->num_pending, signal_on_any ? 1 : num_fences); + array->fences = fences; + + return array; +} +EXPORT_SYMBOL(fence_array_create); + +#endif /* !defined(HAVE_LINUX_DMA_FENCE_H) && !defined(HAVE_LINUX_FENCE_ARRAY_H) */ diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c index 178c0b724cc9e..cc35e1e0f4385 100644 --- a/drivers/gpu/drm/amd/amdkcl/main.c +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -3,6 +3,7 @@ #include extern void amdkcl_symbol_init(void); +extern void amdkcl_fence_init(void); extern void amdkcl_io_init(void); extern void amdkcl_kthread_init(void); extern void amdkcl_mm_init(void); @@ -13,6 +14,7 @@ extern void amdkcl_suspend_init(void); int __init amdkcl_init(void) { amdkcl_symbol_init(); + amdkcl_fence_init(); amdkcl_io_init(); amdkcl_kthread_init(); amdkcl_mm_init(); diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 99c0e0097a95b..722e0b7c215e4 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -27,5 +27,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-fence-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-fence-headers.m4 new file mode 100644 index 0000000000000..843491bfe3aef --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dma-fence-headers.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit f54d1867005c3323f5d8ad83eed823e84226c429 +dnl # dma-buf: Rename struct fence to dma_fence +dnl # +AC_DEFUN([AC_AMDGPU_DMA_FENCE_HEADERS], [ + AS_IF([test $HAVE_LINUX_DMA_FENCE_H], [ + AC_KERNEL_DO_BACKGROUND([ + ]) + ], [ + dnl # + dnl # commit b3dfbdf261e076a997f812323edfdba84ba80256 + dnl # dma-buf/fence: add fence_array fences v6 + dnl # + AC_KERNEL_CHECK_HEADERS([linux/fence-array.h]) + AC_KERNEL_DO_BACKGROUND([ + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 54f143f96c573..72720629c9637 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -27,6 +27,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_KTIME_GET_BOOTTIME_NS AC_AMDGPU_MMU_NOTIFIER AC_AMDGPU_MM_RELEASE_PAGES + AC_AMDGPU_DMA_FENCE_HEADERS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/scheduler/backport/backport.h b/drivers/gpu/drm/scheduler/backport/backport.h index 7994c7b3826ac..28b00db43738f 100644 --- a/drivers/gpu/drm/scheduler/backport/backport.h +++ b/drivers/gpu/drm/scheduler/backport/backport.h @@ -4,5 +4,6 @@ #include #include +#include #endif diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index 4dbd06d3e8b6c..48f3f3bc56a71 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -6,4 +6,5 @@ #include #include #include +#include #endif diff --git a/include/kcl/backport/kcl_fence_backport.h b/include/kcl/backport/kcl_fence_backport.h new file mode 100644 index 0000000000000..022951286bb7d --- /dev/null +++ b/include/kcl/backport/kcl_fence_backport.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef AMDKCL_FENCE_BACKPORT_H +#define AMDKCL_FENCE_BACKPORT_H +#include + +/* + * commit v4.18-rc2-533-g418cc6ca0607 + * dma-fence: Allow wait_any_timeout for all fences) + */ +#ifdef AMDKCL_FENCE_WAIT_ANY_TIMEOUT +#define dma_fence_wait_any_timeout _kcl_fence_wait_any_timeout +#endif + +/* + * commit v4.9-rc2-472-gbcc004b629d2 + * dma-buf/fence: make timeout handling in fence_default_wait consistent (v2)) + * + * commit v4.9-rc2-473-g698c0f7ff216 + * dma-buf/fence: revert "don't wait when specified timeout is zero" (v2) + */ +#ifdef AMDKCL_FENCE_DEFAULT_WAIT_TIMEOUT +#define dma_fence_default_wait _kcl_fence_default_wait +#define dma_fence_wait_timeout _kcl_fence_wait_timeout +#endif + +/* + * commit v4.14-rc3-601-g5f72db59160c + * dma-buf/fence: Sparse wants __rcu on the object itself + */ +#ifdef AMDKCL_FENCE_GET_RCU_SAFE +#define dma_fence_get_rcu_safe _kcl_fence_get_rcu_safe +#endif +#endif diff --git a/include/kcl/kcl_fence.h b/include/kcl/kcl_fence.h new file mode 100644 index 0000000000000..7a869acf02b93 --- /dev/null +++ b/include/kcl/kcl_fence.h @@ -0,0 +1,156 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Fence mechanism for dma-buf to allow for asynchronous dma access + * + * Copyright (C) 2012 Canonical Ltd + * Copyright (C) 2012 Texas Instruments + * + * Authors: + * Rob Clark + * Maarten Lankhorst + */ +#ifndef AMDKCL_FENCE_H +#define AMDKCL_FENCE_H + +#include +#include +#if !defined(HAVE_LINUX_DMA_FENCE_H) +#include +#include +#else +#include +#include +#endif + +#if !defined(HAVE_LINUX_DMA_FENCE_H) +#define dma_fence_cb fence_cb +#define dma_fence_ops fence_ops +#define dma_fence_array fence_array +#define dma_fence fence +#define dma_fence_init fence_init +#define dma_fence_context_alloc fence_context_alloc +#define DMA_FENCE_TRACE FENCE_TRACE +#define DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT FENCE_FLAG_ENABLE_SIGNAL_BIT +#define DMA_FENCE_FLAG_SIGNALED_BIT FENCE_FLAG_SIGNALED_BIT +#define dma_fence_wait fence_wait +#define dma_fence_get fence_get +#define dma_fence_put fence_put +#define dma_fence_is_signaled fence_is_signaled +#define dma_fence_signal fence_signal +#define dma_fence_signal_locked fence_signal_locked +#define dma_fence_get_rcu fence_get_rcu +#define dma_fence_array_create fence_array_create +#define dma_fence_add_callback fence_add_callback +#define dma_fence_remove_callback fence_remove_callback +#define dma_fence_enable_sw_signaling fence_enable_sw_signaling +#define dma_fence_default_wait fence_default_wait + +#define dma_fence_set_error fence_set_error +#endif + +/* commit v4.5-rc3-715-gb47bcb93bbf2 + * fall back to HAVE_LINUX_DMA_FENCE_H check directly + * as it's hard to detect the implementation in kernel + */ +#if !defined(HAVE_LINUX_DMA_FENCE_H) +static inline bool dma_fence_is_later(struct dma_fence *f1, struct dma_fence *f2) +{ + if (WARN_ON(f1->context != f2->context)) + return false; + + return (int)(f1->seqno - f2->seqno) > 0; +} +#endif + +/* + * commit v4.18-rc2-533-g418cc6ca0607 + * dma-fence: Allow wait_any_timeout for all fences) + */ +#if DRM_VERSION_CODE < DRM_VERSION(4, 19, 0) +#define AMDKCL_FENCE_WAIT_ANY_TIMEOUT +signed long +_kcl_fence_wait_any_timeout(struct dma_fence **fences, uint32_t count, + bool intr, signed long timeout, uint32_t *idx); +#endif + +/* + * commit v4.9-rc2-472-gbcc004b629d2 + * dma-buf/fence: make timeout handling in fence_default_wait consistent (v2)) + * + * commit v4.9-rc2-473-g698c0f7ff216 + * dma-buf/fence: revert "don't wait when specified timeout is zero" (v2) + */ +#if DRM_VERSION_CODE < DRM_VERSION(4, 10, 0) +#define AMDKCL_FENCE_DEFAULT_WAIT_TIMEOUT +signed long +_kcl_fence_default_wait(struct dma_fence *fence, bool intr, signed long timeout); +extern signed long _kcl_fence_wait_timeout(struct fence *fence, bool intr, + signed long timeout); +#endif + +/* + * commit v4.14-rc3-601-g5f72db59160c + * dma-buf/fence: Sparse wants __rcu on the object itself + */ +#if DRM_VERSION_CODE < DRM_VERSION(4, 15, 0) +#define AMDKCL_FENCE_GET_RCU_SAFE +static inline struct dma_fence * +_kcl_fence_get_rcu_safe(struct dma_fence __rcu **fencep) +{ + do { + struct dma_fence *fence; + + fence = rcu_dereference(*fencep); + if (!fence) + return NULL; + + if (!dma_fence_get_rcu(fence)) + continue; + + /* The atomic_inc_not_zero() inside dma_fence_get_rcu() + * provides a full memory barrier upon success (such as now). + * This is paired with the write barrier from assigning + * to the __rcu protected fence pointer so that if that + * pointer still matches the current fence, we know we + * have successfully acquire a reference to it. If it no + * longer matches, we are holding a reference to some other + * reallocated pointer. This is possible if the allocator + * is using a freelist like SLAB_TYPESAFE_BY_RCU where the + * fence remains valid for the RCU grace period, but it + * may be reallocated. When using such allocators, we are + * responsible for ensuring the reference we get is to + * the right fence, as below. + */ + if (fence == rcu_access_pointer(*fencep)) + return rcu_pointer_handoff(fence); + + dma_fence_put(fence); + } while (1); +} +#endif + +/* + * commit v4.18-rc2-519-gc701317a3eb8 + * dma-fence: Make ->enable_signaling optional + */ +#if DRM_VERSION_CODE < DRM_VERSION(4, 19, 0) +#define AMDKCL_DMA_FENCE_OPS_ENABLE_SIGNALING +bool _kcl_fence_enable_signaling(struct dma_fence *f); +#define AMDKCL_DMA_FENCE_OPS_ENABLE_SIGNALING_OPTIONAL \ + .enable_signaling = _kcl_fence_enable_signaling, +#else +#define AMDKCL_DMA_FENCE_OPS_ENABLE_SIGNALING_OPTIONAL +#endif + +/* + * commit v4.18-rc2-533-g418cc6ca0607 + * dma-fence: Make ->wait callback optional + */ +#if DRM_VERSION_CODE < DRM_VERSION(4, 19, 0) +#define AMDKCL_DMA_FENCE_OPS_WAIT_OPTIONAL \ + .wait = dma_fence_default_wait, +#else +#define AMDKCL_DMA_FENCE_OPS_WAIT_OPTIONAL +#endif + +#endif /* AMDKCL_FENCE_H */ diff --git a/include/kcl/kcl_fence_array.h b/include/kcl/kcl_fence_array.h new file mode 100644 index 0000000000000..8bce1cf8ff00c --- /dev/null +++ b/include/kcl/kcl_fence_array.h @@ -0,0 +1,82 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * this file is the copy of include/linux/fence-array.h, don't modify it + * + * fence-array: aggregates fence to be waited together + * + * Copyright (C) 2016 Collabora Ltd + * Copyright (C) 2016 Advanced Micro Devices, Inc. + * Authors: + * Gustavo Padovan + * Christian König + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License version 2 as published by + * the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef AMDKCL_FENCE_ARRAY_H +#define AMDKCL_FENCE_ARRAY_H + +#if !defined(HAVE_LINUX_DMA_FENCE_H) +#if defined(HAVE_LINUX_FENCE_ARRAY_H) +#include +#else +#include + +/** + * struct fence_array_cb - callback helper for fence array + * @cb: fence callback structure for signaling + * @array: reference to the parent fence array object + */ +struct fence_array_cb { + struct fence_cb cb; + struct fence_array *array; +}; + +/** + * struct fence_array - fence to represent an array of fences + * @base: fence base class + * @lock: spinlock for fence handling + * @num_fences: number of fences in the array + * @num_pending: fences in the array still pending + * @fences: array of the fences + */ +struct fence_array { + struct fence base; + + spinlock_t lock; + unsigned num_fences; + atomic_t num_pending; + struct fence **fences; +}; + +extern const struct fence_ops fence_array_ops; + +/** + * to_fence_array - cast a fence to a fence_array + * @fence: fence to cast to a fence_array + * + * Returns NULL if the fence is not a fence_array, + * or the fence_array otherwise. + */ +static inline struct fence_array *to_fence_array(struct fence *fence) +{ + if (fence->ops != &fence_array_ops) + return NULL; + + return container_of(fence, struct fence_array, base); +} + +struct fence_array *fence_array_create(int num_fences, struct fence **fences, + u64 context, unsigned seqno, + bool signal_on_any); +#endif +#endif + +#endif /* __LINUX_FENCE_ARRAY_H */ From aa914e0153d79cb7c5d7ee83504892a9c0cdcc1d Mon Sep 17 00:00:00 2001 From: Evan Quan Date: Wed, 29 Mar 2017 09:03:10 +0800 Subject: [PATCH 0096/1868] drm/amdkcl: define kcl tracepoints v2: drop legacy kcl_fence_ defines v3: move kcl_trace.h to amdkcl Signed-off-by: Evan Quan Reviewed-by: Junwei Zhang Reviewed-by: Chunming Zhou Signed-off-by: Jack Gui Signed-off-by: Flora Cui Reviewed-by: Feifei Xu Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang drm/amdkcl: rename kcl_trace.h to kcl_fence_trace.h to clarify the trace is for kcl_fence Signed-off-by: Flora Cui Reviewed-by: Shiwu Zhang drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 + drivers/gpu/drm/amd/amdkcl/kcl_fence.c | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_fence_trace.h | 72 ++++++++++++++++++++ 3 files changed, 75 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_fence_trace.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index f705e8bab0e99..97ed40fbccb56 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -7,6 +7,8 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_suspend.o kcl_pci.o kcl_mm.o \ kcl_fence.o kcl_fence_array.o +CFLAGS_kcl_fence.o := -I$(src) + ccflags-y += \ -include $(src)/../dkms/config/config.h \ -include $(src)/kcl_common.h diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fence.c b/drivers/gpu/drm/amd/amdkcl/kcl_fence.c index c67cae784f75a..ed889c91b8dd4 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_fence.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fence.c @@ -23,7 +23,7 @@ #include #define CREATE_TRACE_POINTS -#include "kcl_trace.h" +#include "kcl_fence_trace.h" /* Copied from drivers/dma-buf/dma-fence.c */ static bool diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fence_trace.h b/drivers/gpu/drm/amd/amdkcl/kcl_fence_trace.h new file mode 100644 index 0000000000000..7c857ba3c31c0 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fence_trace.h @@ -0,0 +1,72 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copied from include/trace/events/dma_fence.h */ +#if !defined(_TRACE_KCL_FENCE_H) || defined(TRACE_HEADER_MULTI_READ) +#define _TRACE_KCL_FENCE_H + +#include + +#undef TRACE_SYSTEM +#define TRACE_SYSTEM kcl_fence +#define TRACE_INCLUDE_FILE kcl_fence_trace + +struct dma_fence; + +DECLARE_EVENT_CLASS(kcl_fence, + + TP_PROTO(struct dma_fence *fence), + + TP_ARGS(fence), + + TP_STRUCT__entry( + __string(driver, fence->ops->get_driver_name(fence)) + __string(timeline, fence->ops->get_timeline_name(fence)) + __field(unsigned int, context) + __field(unsigned int, seqno) + ), + + TP_fast_assign( + __assign_str(driver, fence->ops->get_driver_name(fence)) + __assign_str(timeline, fence->ops->get_timeline_name(fence)) + __entry->context = fence->context; + __entry->seqno = fence->seqno; + ), + + TP_printk("driver=%s timeline=%s context=%u seqno=%u", + __get_str(driver), __get_str(timeline), __entry->context, + __entry->seqno) +); + +DEFINE_EVENT(kcl_fence, kcl_fence_init, + + TP_PROTO(struct dma_fence *fence), + + TP_ARGS(fence) +); + +DEFINE_EVENT(kcl_fence, kcl_fence_enable_signal, + + TP_PROTO(struct dma_fence *fence), + + TP_ARGS(fence) +); + +DEFINE_EVENT(kcl_fence, kcl_fence_wait_start, + + TP_PROTO(struct dma_fence *fence), + + TP_ARGS(fence) +); + +DEFINE_EVENT(kcl_fence, kcl_fence_wait_end, + + TP_PROTO(struct dma_fence *fence), + + TP_ARGS(fence) +); + +#endif /* _TRACE_KCL_FENCE_H */ + +/* This part must be outside protection */ +#undef TRACE_INCLUDE_PATH +#define TRACE_INCLUDE_PATH . +#include From 8575a08be31b49971839400878a70061bea2dd27 Mon Sep 17 00:00:00 2001 From: Chengming Gui Date: Tue, 19 Nov 2019 15:23:53 +0800 Subject: [PATCH 0097/1868] drm/amdkcl: include dma-resv.{c,h} to dkms package introduced by v5.4-rc1~32^2~17^2~36 -commit 52791eeec1d9f4a7e7fe08aaba0b1553149d93bc -dma-buf: rename reservation_object to dma_resv Signed-off-by: Anatoli Antonovitch Signed-off-by: Yifan Zhang Signed-off-by: chen gong Signed-off-by: Flora Cui Signed-off-by: Chengming Gui Signed-off-by: Jiansong Chen Signed-off-by: Slava Grigorev Reviewed-by: Jiansong Chen Signed-off-by: Yifan Zhang Signed-off-by: Chengming Gui Signed-off-by: Yifan Zhang Reviewed-by: Yang Xiong Signed-off-by: Flora Cui Change-Id: I9b909f512608759f78d88a02254ab3bcdeb366fd drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkcl/Makefile | 4 +- drivers/gpu/drm/amd/amdkcl/files | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_reservation.c | 41 ++++++++++++ drivers/gpu/drm/amd/amdkcl/main.c | 2 + drivers/gpu/drm/amd/dkms/Makefile | 4 ++ drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 | 51 +++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/pre-build.sh | 5 ++ drivers/gpu/drm/amd/dkms/sources | 3 + include/kcl/kcl_dma-resv.h | 65 ++++++++++++++++++++ include/kcl/kcl_reservation.h | 12 ++++ include/kcl/reservation.h | 9 +++ 12 files changed, 197 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_reservation.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 create mode 100644 include/kcl/kcl_dma-resv.h create mode 100644 include/kcl/kcl_reservation.h create mode 100644 include/kcl/reservation.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 97ed40fbccb56..6d61493a05b1a 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -2,10 +2,12 @@ amdkcl-y += main.o symbols.o kcl_common.o amdkcl-y += kcl_kernel_params.o +amdkcl-y += dma-buf/dma-resv.o + amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_kthread.o kcl_io.o kcl_perf_event.o \ kcl_suspend.o kcl_pci.o kcl_mm.o \ - kcl_fence.o kcl_fence_array.o + kcl_fence.o kcl_fence_array.o kcl_reservation.o CFLAGS_kcl_fence.o := -I$(src) diff --git a/drivers/gpu/drm/amd/amdkcl/files b/drivers/gpu/drm/amd/amdkcl/files index 501b9055ad408..a5a39207c730e 100644 --- a/drivers/gpu/drm/amd/amdkcl/files +++ b/drivers/gpu/drm/amd/amdkcl/files @@ -1 +1 @@ -FILES="ttm/*.c scheduler/*.c" +FILES="ttm/*.c scheduler/*.c amd/amdkcl/dma-buf/dma-resv.c" diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_reservation.c b/drivers/gpu/drm/amd/amdkcl/kcl_reservation.c new file mode 100644 index 0000000000000..6dc0517f2509a --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_reservation.c @@ -0,0 +1,41 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2012-2014 Canonical Ltd (Maarten Lankhorst) + * + * Based on bo.c which bears the following copyright notice, + * but is dual licensed: + * + * Copyright (c) 2006-2009 VMware, Inc., Palo Alto, CA., USA + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + **************************************************************************/ +/* + * Authors: Thomas Hellstrom + */ +#include +#include "kcl_common.h" + +void amdkcl_reservation_init(void) +{ + amdkcl_fp_setup("reservation_ww_class", NULL); +} diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c index cc35e1e0f4385..6dc78f4f4f851 100644 --- a/drivers/gpu/drm/amd/amdkcl/main.c +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -4,6 +4,7 @@ extern void amdkcl_symbol_init(void); extern void amdkcl_fence_init(void); +extern void amdkcl_reservation_init(void); extern void amdkcl_io_init(void); extern void amdkcl_kthread_init(void); extern void amdkcl_mm_init(void); @@ -15,6 +16,7 @@ int __init amdkcl_init(void) { amdkcl_symbol_init(); amdkcl_fence_init(); + amdkcl_reservation_init(); amdkcl_io_init(); amdkcl_kthread_init(); amdkcl_mm_init(); diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 7c227452be97c..dbace6b3bc0ae 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -12,6 +12,10 @@ endif _is_kcl_macro_defined=$(shell grep $1 $(src)/amd/dkms/config/config.h | grep -q "define" && echo "y" || echo "n") +ifeq ($(shell grep "HAVE_DMA_RESV_SEQ" $(src)/amd/dkms/config/config.h | grep -q "define" && echo "y" || echo "n"),n) +$(error dma_resv->seq is missing., exit...) +endif + ifdef CONFIG_CC_IS_GCC GCCMAJ=$(shell echo __GNUC__ | $(CC) -E -x c - | tail -n 1) GCCMIN=$(shell echo __GNUC_MINOR__ | $(CC) -E -x c - | tail -n 1) diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 new file mode 100644 index 0000000000000..c1060c688a017 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 @@ -0,0 +1,51 @@ +dnl # +dnl # v5.3-rc1-476-gb016cd6ed4b7 dma-buf: Restore seqlock around dma_resv updates +dnl # v5.3-rc1-449-g52791eeec1d9 dma-buf: rename reservation_object to dma_resv +dnl # v5.3-rc1-448-g5d344f58da76 dma-buf: nuke reservation_object seq number +dnl # +AC_DEFUN([AC_AMDGPU_DMA_RESV_SEQ], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_LINUX_DMA_RESV_H + #include + #else + #include + #endif + ], [ + #ifdef HAVE_LINUX_DMA_RESV_H + struct dma_resv *resv = NULL; + #else + struct reservation_object *resv = NULL; + #endif + write_seqcount_begin(&resv->seq); + ], [ + AC_DEFINE(HAVE_DMA_RESV_SEQ, 1, + [dma_resv->seq is available]) + ]) + ]) +]) + +dnl # +dnl # v4.19-rc6-1514-g27836b641c1b +dnl # dma-buf: remove shared fence staging in reservation object +dnl # +AC_DEFUN([AC_AMDGPU_RESERVATION_OBJECT_STAGED], [ + AC_KERNEL_DO_BACKGROUND([ + AS_IF([test x$HAVE_LINUX_DMA_RESV_H = x ], [ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct reservation_object *resv = NULL; + resv->staged = NULL; + ], [ + AC_DEFINE(HAVE_RESERVATION_OBJECT_STAGED, 1, + [reservation_object->staged is available]) + ]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_DMA_RESV], [ + AC_AMDGPU_DMA_RESV_SEQ + AC_AMDGPU_RESERVATION_OBJECT_STAGED +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 72720629c9637..26a8405a75aaa 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -28,6 +28,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_MMU_NOTIFIER AC_AMDGPU_MM_RELEASE_PAGES AC_AMDGPU_DMA_FENCE_HEADERS + AC_AMDGPU_DMA_RESV AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index 698e69b364c03..7d481851f944d 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -38,6 +38,11 @@ for sym in $SYMS; do }' /boot/System.map-$KERNELVER >>$KCL/symbols.c done +sed -i -e '/DEFINE_WD_CLASS(reservation_ww_class)/,/EXPORT_SYMBOL(reservation_ww_class)/d' \ + -e '/dma_resv_lockdep/,/subsys_initcall/d' $KCL/dma-buf/dma-resv.c +sed -i -e '/extern struct ww_class reservation_ww_class/i #include ' \ + -e '/struct dma_resv {/, /}/d' $INC/linux/dma-resv.h + # add amd prefix to exported symbols for file in $FILES; do awk -F'[()]' '/EXPORT_SYMBOL/ { diff --git a/drivers/gpu/drm/amd/dkms/sources b/drivers/gpu/drm/amd/dkms/sources index b8f2af052e55a..3470a58a43676 100644 --- a/drivers/gpu/drm/amd/dkms/sources +++ b/drivers/gpu/drm/amd/dkms/sources @@ -24,3 +24,6 @@ include/drm/gpu_scheduler.h include/drm/ include/drm/amd_asic_type.h include/drm/ include/drm/spsc_queue.h include/drm/ include/uapi/linux/kfd_ioctl.h include/uapi/linux/ +drivers/dma-buf/dma-resv.c amd/amdkcl/dma-buf/ +include/linux/dma-resv.h include/linux/ +include/kcl/reservation.h include/linux/ diff --git a/include/kcl/kcl_dma-resv.h b/include/kcl/kcl_dma-resv.h new file mode 100644 index 0000000000000..be88ddb4c0d1b --- /dev/null +++ b/include/kcl/kcl_dma-resv.h @@ -0,0 +1,65 @@ +/* + * Header file for reservations for dma-buf and ttm + * + * Copyright(C) 2011 Linaro Limited. All rights reserved. + * Copyright (C) 2012-2013 Canonical Ltd + * Copyright (C) 2012 Texas Instruments + * + * Authors: + * Rob Clark + * Maarten Lankhorst + * Thomas Hellstrom + * + * Based on bo.c which bears the following copyright notice, + * but is dual licensed: + * + * Copyright (c) 2006-2009 VMware, Inc., Palo Alto, CA., USA + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +/* + * NOTICE: + * THIS HEADER IS FOR DMA-RESV.H ONLY + * DO NOT INCLUDE THIS HEADER ANY OTHER PLACE + * INCLUDE LINUX/DMA-RESV.H OR LINUX/RESERVATION.H INSTEAD + */ +#ifndef KCL_KCL_DMA_RESV_H +#define KCL_KCL_DMA_RESV_H + +#include +#include + +struct dma_resv_list; + +struct dma_resv { + struct ww_mutex lock; + seqcount_t seq; + + struct dma_fence __rcu *fence_excl; + struct dma_resv_list __rcu *fence; +}; + +#if !defined(smp_store_mb) +#define smp_store_mb set_mb +#endif +#endif diff --git a/include/kcl/kcl_reservation.h b/include/kcl/kcl_reservation.h new file mode 100644 index 0000000000000..32d6d2b8b7826 --- /dev/null +++ b/include/kcl/kcl_reservation.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef KCL_KCL_RESERVATION_H +#define KCL_KCL_RESERVATION_H + +#include + +#ifndef HAVE_LINUX_DMA_RESV_H +#define reservation_object dma_resv +#define reservation_object_list dma_resv_list +#endif + +#endif /* AMDKCL_RESERVATION_H */ diff --git a/include/kcl/reservation.h b/include/kcl/reservation.h new file mode 100644 index 0000000000000..8dcc5e3c18479 --- /dev/null +++ b/include/kcl/reservation.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef KCL_RESERVATION_H +#define KCL_RESERVATION_H + +#ifndef HAVE_LINUX_DMA_RESV_H +#include +#endif /* HAVE_LINUX_DMA_RESV_H */ + +#endif From b6c5f4140bea758648b6a9d95942b379a3ed145d Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 18 Aug 2020 12:50:51 +0800 Subject: [PATCH 0098/1868] drm/amdkcl: rework reservatio_object->staged case handle reservation_object->staged incase it get updated by 3rd-party driver. Signed-off-by: Flora Cui Reviewed-by: Yang Xiong --- drivers/gpu/drm/amd/amdkcl/kcl_reservation.c | 147 +++++++++++++++++++ include/kcl/kcl_dma-resv.h | 11 ++ include/kcl/reservation.h | 17 +++ 3 files changed, 175 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_reservation.c b/drivers/gpu/drm/amd/amdkcl/kcl_reservation.c index 6dc0517f2509a..16393735a2f43 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_reservation.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_reservation.c @@ -39,3 +39,150 @@ void amdkcl_reservation_init(void) { amdkcl_fp_setup("reservation_ww_class", NULL); } + +#if defined(HAVE_RESERVATION_OBJECT_STAGED) +static void +reservation_object_add_shared_inplace(struct reservation_object *obj, + struct reservation_object_list *fobj, + struct dma_fence *fence) +{ + struct dma_fence *signaled = NULL; + u32 i, signaled_idx; + + dma_fence_get(fence); + + preempt_disable(); + write_seqcount_begin(&obj->seq); + + for (i = 0; i < fobj->shared_count; ++i) { + struct dma_fence *old_fence; + + old_fence = rcu_dereference_protected(fobj->shared[i], + dma_resv_held(obj)); + + if (old_fence->context == fence->context) { + /* memory barrier is added by write_seqcount_begin */ + RCU_INIT_POINTER(fobj->shared[i], fence); + write_seqcount_end(&obj->seq); + preempt_enable(); + + dma_fence_put(old_fence); + return; + } + + if (!signaled && dma_fence_is_signaled(old_fence)) { + signaled = old_fence; + signaled_idx = i; + } + } + + /* + * memory barrier is added by write_seqcount_begin, + * fobj->shared_count is protected by this lock too + */ + if (signaled) { + RCU_INIT_POINTER(fobj->shared[signaled_idx], fence); + } else { + BUG_ON(fobj->shared_count >= fobj->shared_max); + RCU_INIT_POINTER(fobj->shared[fobj->shared_count], fence); + fobj->shared_count++; + } + + write_seqcount_end(&obj->seq); + preempt_enable(); + + dma_fence_put(signaled); +} + +static void +reservation_object_add_shared_replace(struct reservation_object *obj, + struct reservation_object_list *old, + struct reservation_object_list *fobj, + struct dma_fence *fence) +{ + unsigned i, j, k; + + dma_fence_get(fence); + + if (!old) { + RCU_INIT_POINTER(fobj->shared[0], fence); + fobj->shared_count = 1; + goto done; + } + + /* + * no need to bump fence refcounts, rcu_read access + * requires the use of kref_get_unless_zero, and the + * references from the old struct are carried over to + * the new. + */ + for (i = 0, j = 0, k = fobj->shared_max; i < old->shared_count; ++i) { + struct dma_fence *check; + + check = rcu_dereference_protected(old->shared[i], + dma_resv_held(obj)); + + if (check->context == fence->context || + dma_fence_is_signaled(check)) + RCU_INIT_POINTER(fobj->shared[--k], check); + else + RCU_INIT_POINTER(fobj->shared[j++], check); + } + fobj->shared_count = j; + RCU_INIT_POINTER(fobj->shared[fobj->shared_count], fence); + fobj->shared_count++; + +done: + preempt_disable(); + write_seqcount_begin(&obj->seq); + /* + * RCU_INIT_POINTER can be used here, + * seqcount provides the necessary barriers + */ + RCU_INIT_POINTER(obj->fence, fobj); + write_seqcount_end(&obj->seq); + preempt_enable(); + + if (!old) + return; + + /* Drop the references to the signaled fences */ + for (i = k; i < fobj->shared_max; ++i) { + struct dma_fence *f; + + f = rcu_dereference_protected(fobj->shared[i], + dma_resv_held(obj)); + dma_fence_put(f); + } + kfree_rcu(old, rcu); +} + +void _kcl_dma_resv_add_shared_fence(struct dma_resv *obj, struct dma_fence *fence) +{ + struct dma_resv_list *old, *fobj = obj->staged; + + old = dma_resv_get_list(obj); + obj->staged = NULL; + + if (!fobj) + reservation_object_add_shared_inplace(obj, old, fence); + else + reservation_object_add_shared_replace(obj, old, fobj, fence); +} +EXPORT_SYMBOL(_kcl_dma_resv_add_shared_fence); + +int _kcl_dma_resv_copy_fences(struct dma_resv *dst, struct dma_resv *src) +{ + int ret; + + ret = dma_resv_copy_fences(dst, src); + if (ret) + return ret; + + kfree(dst->staged); + dst->staged = NULL; + + return ret; +} +EXPORT_SYMBOL(_kcl_dma_resv_copy_fences); +#endif diff --git a/include/kcl/kcl_dma-resv.h b/include/kcl/kcl_dma-resv.h index be88ddb4c0d1b..5658e14dad4fe 100644 --- a/include/kcl/kcl_dma-resv.h +++ b/include/kcl/kcl_dma-resv.h @@ -51,13 +51,24 @@ struct dma_resv_list; +#if defined(HAVE_RESERVATION_OBJECT_STAGED) struct dma_resv { struct ww_mutex lock; seqcount_t seq; struct dma_fence __rcu *fence_excl; struct dma_resv_list __rcu *fence; + struct dma_resv_list *staged; }; +#else +struct dma_resv { + struct ww_mutex lock; + seqcount_t seq; + + struct dma_fence __rcu *fence_excl; + struct dma_resv_list __rcu *fence; +}; +#endif #if !defined(smp_store_mb) #define smp_store_mb set_mb diff --git a/include/kcl/reservation.h b/include/kcl/reservation.h index 8dcc5e3c18479..fbd036fdd650d 100644 --- a/include/kcl/reservation.h +++ b/include/kcl/reservation.h @@ -4,6 +4,23 @@ #ifndef HAVE_LINUX_DMA_RESV_H #include + +#if defined(HAVE_RESERVATION_OBJECT_STAGED) +static inline void +_kcl_reservation_object_fini(struct reservation_object *obj) +{ + dma_resv_fini(obj); + kfree(obj->staged); +} +#define amddma_resv_fini _kcl_reservation_object_fini + +void _kcl_dma_resv_add_shared_fence(struct dma_resv *obj, struct dma_fence *fence); +#define amddma_resv_add_shared_fence _kcl_dma_resv_add_shared_fence + +int _kcl_dma_resv_copy_fences(struct dma_resv *dst, struct dma_resv *src); +#define amddma_resv_copy_fences _kcl_dma_resv_copy_fences + +#endif /* HAVE_RESERVATION_OBJECT_STAGED */ #endif /* HAVE_LINUX_DMA_RESV_H */ #endif From 1f3cf7c962c74b61f063b00370014c884f81de0e Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 3 Sep 2020 16:13:29 +0800 Subject: [PATCH 0099/1868] drm/amdkcl: test seqcount_ww_mutex_init for dma_resv Signed-off-by: Flora Cui drm/amdkcl: include kcl_common.h in every .c Signed-off-by: Flora Cui Reviewed-by: Shiwu Zhang drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkcl/kcl_reservation.c | 5 ++- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 | 42 ++++++++++++++------ include/kcl/kcl_dma-resv.h | 11 ++++- include/kcl/kcl_seqlock.h | 30 ++++++++++++++ 5 files changed, 74 insertions(+), 15 deletions(-) create mode 100644 include/kcl/kcl_seqlock.h diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_reservation.c b/drivers/gpu/drm/amd/amdkcl/kcl_reservation.c index 16393735a2f43..5bb5b8b68e64e 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_reservation.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_reservation.c @@ -33,7 +33,6 @@ * Authors: Thomas Hellstrom */ #include -#include "kcl_common.h" void amdkcl_reservation_init(void) { @@ -41,6 +40,10 @@ void amdkcl_reservation_init(void) } #if defined(HAVE_RESERVATION_OBJECT_STAGED) +/* + * Copied from v4.19-rc6-1514-g27836b641c1b^:drivers/dma-buf/reservation.c + * and modified for KCL + */ static void reservation_object_add_shared_inplace(struct reservation_object *obj, struct reservation_object_list *fobj, diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 722e0b7c215e4..93bd18b4053db 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 index c1060c688a017..1ede56611c58d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 @@ -1,26 +1,42 @@ dnl # -dnl # v5.3-rc1-476-gb016cd6ed4b7 dma-buf: Restore seqlock around dma_resv updates -dnl # v5.3-rc1-449-g52791eeec1d9 dma-buf: rename reservation_object to dma_resv -dnl # v5.3-rc1-448-g5d344f58da76 dma-buf: nuke reservation_object seq number +dnl # v5.8-rc6-36-gcd29f22019ec dma-buf: Use sequence counter with associated wound/wait mutex +dnl # v5.8-rc6-35-g318ce71f3e3a dma-buf: Remove custom seqcount lockdep class key dnl # AC_DEFUN([AC_AMDGPU_DMA_RESV_SEQ], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_LINUX_DMA_RESV_H #include - #else - #include - #endif ], [ - #ifdef HAVE_LINUX_DMA_RESV_H - struct dma_resv *resv = NULL; - #else - struct reservation_object *resv = NULL; - #endif - write_seqcount_begin(&resv->seq); + struct dma_resv *obj = NULL; + seqcount_ww_mutex_init(&obj->seq, &obj->lock); ], [ + AC_DEFINE(HAVE_DMA_RESV_SEQCOUNT_WW_MUTEX_T, 1, + [dma_resv->seq is seqcount_ww_mutex_t]) AC_DEFINE(HAVE_DMA_RESV_SEQ, 1, [dma_resv->seq is available]) + ], [ + dnl # + dnl # v5.3-rc1-476-gb016cd6ed4b7 dma-buf: Restore seqlock around dma_resv updates + dnl # v5.3-rc1-449-g52791eeec1d9 dma-buf: rename reservation_object to dma_resv + dnl # v5.3-rc1-448-g5d344f58da76 dma-buf: nuke reservation_object seq number + dnl # + AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_LINUX_DMA_RESV_H + #include + #else + #include + #endif + ], [ + #ifdef HAVE_LINUX_DMA_RESV_H + struct dma_resv *resv = NULL; + #else + struct reservation_object *resv = NULL; + #endif + write_seqcount_begin(&resv->seq); + ], [ + AC_DEFINE(HAVE_DMA_RESV_SEQ, 1, + [dma_resv->seq is available]) + ]) ]) ]) ]) diff --git a/include/kcl/kcl_dma-resv.h b/include/kcl/kcl_dma-resv.h index 5658e14dad4fe..680f1fe9c1757 100644 --- a/include/kcl/kcl_dma-resv.h +++ b/include/kcl/kcl_dma-resv.h @@ -48,10 +48,19 @@ #include #include +#include struct dma_resv_list; -#if defined(HAVE_RESERVATION_OBJECT_STAGED) +#if defined(HAVE_DMA_RESV_SEQCOUNT_WW_MUTEX_T) +struct dma_resv { + struct ww_mutex lock; + seqcount_ww_mutex_t seq; + + struct dma_fence __rcu *fence_excl; + struct dma_resv_list __rcu *fence; +}; +#elif defined(HAVE_RESERVATION_OBJECT_STAGED) struct dma_resv { struct ww_mutex lock; seqcount_t seq; diff --git a/include/kcl/kcl_seqlock.h b/include/kcl/kcl_seqlock.h new file mode 100644 index 0000000000000..39f2aa7baa4e5 --- /dev/null +++ b/include/kcl/kcl_seqlock.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _KCL_KCL_SEQLOCK_H +#define _KCL_KCL_SEQLOCK_H + +#include + +#ifndef write_seqcount_begin +struct ww_mutex; +static __always_inline void +seqcount_ww_mutex_init(seqcount_t *s, struct ww_mutex *lock) +{ + seqcount_init(s); +} + +static inline void _kcl_write_seqcount_begin(seqcount_t *s) +{ + preempt_disable(); + write_seqcount_begin(s); +} +#define write_seqcount_begin _kcl_write_seqcount_begin + +static inline void _kcl_write_seqcount_end(seqcount_t *s) +{ + write_seqcount_end(s); + preempt_enable(); +} +#define write_seqcount_end _kcl_write_seqcount_end +#endif /* write_seqcount_begin */ + +#endif From 78f0f2e9bce7ef79b489abff88dae9c205ecbc20 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 22 Jun 2020 13:07:45 +0800 Subject: [PATCH 0100/1868] drm/amdkcl: test for ttm_sg_tt_init the pages array(drm_prime_sg_to_page_addr_arrays) is optional since v4.16-rc1-409-g186ca446aea1 the change history is: v4.16-rc1-1232-g75a57669cbc8 drm/ttm: add ttm_sg_tt_init v4.16-rc1-409-g186ca446aea1 drm/prime: make the pages array optional for drm_prime_sg_to_page_addr_arrays Signed-off-by: Flora Cui Reviewed-by: Yang Xiong drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/ttm_sg_tt_init.m4 | 11 +++++++++++ include/kcl/backport/kcl_ttm_tt_backport.h | 11 +++++++++++ 4 files changed, 24 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/ttm_sg_tt_init.m4 create mode 100644 include/kcl/backport/kcl_ttm_tt_backport.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 93bd18b4053db..64fa219edf63b 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -29,5 +29,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 26a8405a75aaa..9f9440a5aff5f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -29,6 +29,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_MM_RELEASE_PAGES AC_AMDGPU_DMA_FENCE_HEADERS AC_AMDGPU_DMA_RESV + AC_AMDGPU_TTM_SG_TT_INIT AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/ttm_sg_tt_init.m4 b/drivers/gpu/drm/amd/dkms/m4/ttm_sg_tt_init.m4 new file mode 100644 index 0000000000000..9bfcadc878e3c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/ttm_sg_tt_init.m4 @@ -0,0 +1,11 @@ +dnl # +dnl # v4.16-rc1-1232-g75a57669cbc8 +dnl # drm/ttm: add ttm_sg_tt_init +dnl # +AC_DEFUN([AC_AMDGPU_TTM_SG_TT_INIT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([ttm_sg_tt_init], [drivers/gpu/drm/ttm/ttm_tt.c], [ + AC_DEFINE(HAVE_TTM_SG_TT_INIT, 1, [ttm_sg_tt_init() is available]) + ]) + ]) +]) diff --git a/include/kcl/backport/kcl_ttm_tt_backport.h b/include/kcl/backport/kcl_ttm_tt_backport.h new file mode 100644 index 0000000000000..64f22b0fb609e --- /dev/null +++ b/include/kcl/backport/kcl_ttm_tt_backport.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_BACKPORT_KCL_TTM_TT_BACKPORT_H +#define AMDKCL_BACKPORT_KCL_TTM_TT_BACKPORT_H + +#include + +#ifndef HAVE_TTM_SG_TT_INIT +#define amdttm_sg_tt_init ttm_dma_tt_init +#endif + +#endif From 1242dfb3a76681040506296c5f8a39ef23a5a1f5 Mon Sep 17 00:00:00 2001 From: Adam Yang Date: Mon, 23 Sep 2019 16:44:20 +0800 Subject: [PATCH 0101/1868] drm/amdkcl: Test whether drm_need_swiotlb() is available Signed-off-by: Adam Yang Signed-off-by: Jack Gui Change-Id: I14e2af5f5522e3ab8398f137f9d4af1cb144498f drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_drm_cache.c | 66 ++++++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/drm-cache.m4 | 16 ++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_cache.h | 41 ++++++++++++++ 6 files changed, 126 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_cache.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-cache.m4 create mode 100644 include/kcl/kcl_drm_cache.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 6d61493a05b1a..96d530ef4231e 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -7,7 +7,7 @@ amdkcl-y += dma-buf/dma-resv.o amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_kthread.o kcl_io.o kcl_perf_event.o \ kcl_suspend.o kcl_pci.o kcl_mm.o \ - kcl_fence.o kcl_fence_array.o kcl_reservation.o + kcl_fence.o kcl_fence_array.o kcl_reservation.o kcl_drm_cache.o CFLAGS_kcl_fence.o := -I$(src) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_cache.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_cache.c new file mode 100644 index 0000000000000..85894bf3907c6 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_cache.c @@ -0,0 +1,66 @@ +/* + * \file drm_memory.c + * Memory management wrappers for DRM + * + * \author Rickard E. (Rik) Faith + * \author Gareth Hughes + */ + +/* + * Created: Thu Feb 4 14:00:34 1999 by faith@valinux.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include + +#include +#include + +/* Copied from drivers/gpu/drm/drm_memory.c */ +#if !defined(HAVE_DRM_NEED_SWIOTLB) +bool drm_need_swiotlb(int dma_bits) +{ + struct resource *tmp; + resource_size_t max_iomem = 0; + + /* + * Xen paravirtual hosts require swiotlb regardless of requested dma + * transfer size. + * + * NOTE: Really, what it requires is use of the dma_alloc_coherent + * allocator used in ttm_dma_populate() instead of + * ttm_populate_and_map_pages(), which bounce buffers so much in + * Xen it leads to swiotlb buffer exhaustion. + */ + if (xen_pv_domain()) + return true; + + for (tmp = iomem_resource.child; tmp; tmp = tmp->sibling) { + max_iomem = max(max_iomem, tmp->end); + } + + return max_iomem > ((u64)1 << dma_bits); +} +EXPORT_SYMBOL(drm_need_swiotlb); +#endif /* HAVE_DRM_NEED_SWIOTLB */ diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 64fa219edf63b..e13cadeacaad3 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -30,5 +30,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-cache.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-cache.m4 new file mode 100644 index 0000000000000..42911c2cc2131 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-cache.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit 913b2cb727b7a47ccf8842d54c89f1b873c6deed +dnl # drm: change func to better detect wether swiotlb is needed +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CACHE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_need_swiotlb(0); + ], [ + AC_DEFINE(HAVE_DRM_NEED_SWIOTLB, 1, + [drm_need_swiotlb() is availablea]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 9f9440a5aff5f..0dcda800bfca8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -30,6 +30,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DMA_FENCE_HEADERS AC_AMDGPU_DMA_RESV AC_AMDGPU_TTM_SG_TT_INIT + AC_AMDGPU_DRM_CACHE AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_cache.h b/include/kcl/kcl_drm_cache.h new file mode 100644 index 0000000000000..861205f2403bd --- /dev/null +++ b/include/kcl/kcl_drm_cache.h @@ -0,0 +1,41 @@ +/************************************************************************** + * + * Copyright 2009 Red Hat Inc. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * + **************************************************************************/ +/* + * Authors: + * Dave Airlie + */ +#ifndef AMDKCL_DRM_CACHE_H +#define AMDKCL_DRM_CACHE_H +#include +#include + +#if !defined(HAVE_DRM_NEED_SWIOTLB) +bool drm_need_swiotlb(int dma_bits); +#endif /* HAVE_DRM_NEED_SWIOTLB */ + +#endif /* AMDKCL_DRM_CACHE_H */ From 96165661b029646af15110da571010c70fb87c13 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Tue, 24 Mar 2020 19:14:53 -0400 Subject: [PATCH 0102/1868] amd/amdkcl: backport drm_arch_can_wc_memory() function Signed-off-by: Slava Grigorev Reviewed-by: Flora Cui Signed-off-by: Yifan Zhang --- drivers/gpu/drm/amd/backport/backport.h | 2 +- include/kcl/backport/kcl_drm_cache_backport.h | 10 ++++++ include/kcl/kcl_drm_cache.h | 35 +++++++++++++++++++ 3 files changed, 46 insertions(+), 1 deletion(-) create mode 100644 include/kcl/backport/kcl_drm_cache_backport.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index e13cadeacaad3..0e45a4affc45b 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -30,6 +30,6 @@ #include #include #include -#include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/backport/kcl_drm_cache_backport.h b/include/kcl/backport/kcl_drm_cache_backport.h new file mode 100644 index 0000000000000..bc936463073e5 --- /dev/null +++ b/include/kcl/backport/kcl_drm_cache_backport.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef AMDKCL_DRM_CACHE_BACKPORT_H +#define AMDKCL_DRM_CACHE_BACKPORT_H + +#include +#include + +#define drm_arch_can_wc_memory kcl_drm_arch_can_wc_memory + +#endif /* AMDKCL_DRM_CACHE_BACKPORT_H */ diff --git a/include/kcl/kcl_drm_cache.h b/include/kcl/kcl_drm_cache.h index 861205f2403bd..8350e1faa62b5 100644 --- a/include/kcl/kcl_drm_cache.h +++ b/include/kcl/kcl_drm_cache.h @@ -38,4 +38,39 @@ bool drm_need_swiotlb(int dma_bits); #endif /* HAVE_DRM_NEED_SWIOTLB */ +/* + * Copied from include/drm/drm_cache.h + * v5.4-rc2-80-g268a2d600130 MIPS: Loongson64: Rename CPU TYPES + */ +static inline bool kcl_drm_arch_can_wc_memory(void) +{ +#if defined(CONFIG_PPC) && !defined(CONFIG_NOT_COHERENT_CACHE) + return false; +#elif defined(CONFIG_MIPS) && \ + (defined(CONFIG_CPU_LOONGSON64) || defined(CPU_LOONGSON3)) + + return false; +#elif defined(CONFIG_ARM) || defined(CONFIG_ARM64) + /* + * The DRM driver stack is designed to work with cache coherent devices + * only, but permits an optimization to be enabled in some cases, where + * for some buffers, both the CPU and the GPU use uncached mappings, + * removing the need for DMA snooping and allocation in the CPU caches. + * + * The use of uncached GPU mappings relies on the correct implementation + * of the PCIe NoSnoop TLP attribute by the platform, otherwise the GPU + * will use cached mappings nonetheless. On x86 platforms, this does not + * seem to matter, as uncached CPU mappings will snoop the caches in any + * case. However, on ARM and arm64, enabling this optimization on a + * platform where NoSnoop is ignored results in loss of coherency, which + * breaks correct operation of the device. Since we have no way of + * detecting whether NoSnoop works or not, just disable this + * optimization entirely for ARM and arm64. + */ + return false; +#else + return true; +#endif +} + #endif /* AMDKCL_DRM_CACHE_H */ From 8356cd52ed9d65e0a4b84fd3b4fc9b027a0f072a Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 14 Apr 2020 22:41:34 +0800 Subject: [PATCH 0103/1868] drm/amdkcl: test whether drm_debug_enabled() is available Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/backport/backport.h | 1 + .../gpu/drm/amd/dkms/m4/drm_debug_enabled.m4 | 19 ++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_print.h | 38 +++++++++++++++++++ 4 files changed, 59 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_debug_enabled.m4 create mode 100644 include/kcl/kcl_drm_print.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 0e45a4affc45b..e01f33c789fe6 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -31,5 +31,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_debug_enabled.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_debug_enabled.m4 new file mode 100644 index 0000000000000..0baf031bd2e3d --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_debug_enabled.m4 @@ -0,0 +1,19 @@ +dnl # +dnl # commit v5.3-rc1-708-gf0a8f533adc2 +dnl # drm/print: add drm_debug_enabled() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DEBUG_ENABLED], [ + AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drm_print.h], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + drm_debug_enabled(0); + ],[ + AC_DEFINE(HAVE_DRM_DEBUG_ENABLED, + 1, + [drm_debug_enabled() is available]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 0dcda800bfca8..25256192d7137 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -31,6 +31,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DMA_RESV AC_AMDGPU_TTM_SG_TT_INIT AC_AMDGPU_DRM_CACHE + AC_AMDGPU_DRM_DEBUG_ENABLED AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h new file mode 100644 index 0000000000000..03dce456987d5 --- /dev/null +++ b/include/kcl/kcl_drm_print.h @@ -0,0 +1,38 @@ +/* + * Copyright (C) 2016 Red Hat + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Rob Clark + */ +#ifndef AMDKCL_DRM_PRINT_H +#define AMDKCL_DRM_PRINT_H + +#include +#include + +#ifndef HAVE_DRM_DEBUG_ENABLED +/* Copied from v5.3-rc1-708-gf0a8f533adc2 include/drm/drm_print.h */ +static inline bool drm_debug_enabled(unsigned int category) +{ + return unlikely(drm_debug & category); +} +#endif /* HAVE_DRM_DEBUG_ENABLED */ +#endif From b1a3274430ae17e8031ee030114f7e6c9ba0db7d Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Thu, 12 Jul 2018 14:38:53 -0400 Subject: [PATCH 0104/1868] drm/amdkcl: Test whether drm_fb_helper_remove_conflicting_pci_framebuffers() is available v1: drm/amdkcl: Test whether remove_conflicting_framebuffers() returns int v2: drm/amdkcl: Test whether drm_fb_helper_remove_conflicting_framebuffers() is available v3: drm/amdkcl: refactor drm_fb_helper_remove_conflicting_pci_framebuffers() check v4: drm/amdkcl: accommodate to drmP.h removal for drm-fb-helper-remove-conflicting-pci-framebuffers.m4 v5: for drm_fb_helper_remove_conflicting_pci_framebuffers v6: split to kcl_drm_fb.c v7: drm/amdkcl: fix license for kcl drm part v8: drm/amdkcl: split fbmem related stuff Signed-off-by: Slava Grigorev Signed-off-by: Yifan Zhang Reviewed-by: Feifei Xu Signed-off-by: Jack Gui Signed-off-by: Slava Grigorev Signed-off-by: Flora Cui Reviewed-by: Jack Gui Signed-off-by: Yifan Zhang Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling Change-Id: I0bfd8baf89e77660fe2d017610a3c997001e39a2 --- drivers/gpu/drm/amd/amdkcl/Makefile | 3 +- drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c | 43 ++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + ...per-remove-conflicting-pci-framebuffers.m4 | 57 +++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/backport/kcl_drm_fb.h | 31 +++++++ include/kcl/kcl_drm_fb.h | 80 +++++++++++++++++++ 7 files changed, 215 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-remove-conflicting-pci-framebuffers.m4 create mode 100644 include/kcl/backport/kcl_drm_fb.h create mode 100644 include/kcl/kcl_drm_fb.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 96d530ef4231e..704e31fc89a3d 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -7,7 +7,8 @@ amdkcl-y += dma-buf/dma-resv.o amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_kthread.o kcl_io.o kcl_perf_event.o \ kcl_suspend.o kcl_pci.o kcl_mm.o \ - kcl_fence.o kcl_fence_array.o kcl_reservation.o kcl_drm_cache.o + kcl_fence.o kcl_fence_array.o kcl_reservation.o kcl_drm_cache.o \ + kcl_drm_fb.o kcl_fbmem.o CFLAGS_kcl_fence.o := -I$(src) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c b/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c new file mode 100644 index 0000000000000..11a2fe7ab066e --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c @@ -0,0 +1,43 @@ +/* + * linux/drivers/video/fbmem.c + * + * Copyright (C) 1994 Martin Schaller + * + * 2001 - Documented with DocBook + * - Brad Douglas + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + */ + +#include + +/* Copied from drivers/video/fbdev/core/fbmem.c and modified for KCL */ +#if !defined(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS) +int remove_conflicting_pci_framebuffers(struct pci_dev *pdev, int res_id, const char *name) +{ + struct apertures_struct *ap; + bool primary = false; + int err = 0; + + ap = alloc_apertures(1); + if (!ap) + return -ENOMEM; + + ap->ranges[0].base = pci_resource_start(pdev, res_id); + ap->ranges[0].size = pci_resource_len(pdev, res_id); +#ifdef CONFIG_X86 + primary = pdev->resource[PCI_ROM_RESOURCE].flags & + IORESOURCE_ROM_SHADOW; +#endif +#ifdef HAVE_REMOVE_CONFLICTING_FRAMEBUFFERS_RETURNS_INT + err = remove_conflicting_framebuffers(ap, name, primary); +#else + remove_conflicting_framebuffers(ap, name, primary); +#endif + kfree(ap); + return err; +} +EXPORT_SYMBOL(remove_conflicting_pci_framebuffers); +#endif diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index e01f33c789fe6..05cff055dd4f0 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -32,5 +32,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-remove-conflicting-pci-framebuffers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-remove-conflicting-pci-framebuffers.m4 new file mode 100644 index 0000000000000..fe519aa4941d2 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-remove-conflicting-pci-framebuffers.m4 @@ -0,0 +1,57 @@ +dnl # +dnl # commit v5.3-rc1-541-g35616a4aa919 +dnl # fbdev: drop res_id parameter from remove_conflicting_pci_framebuffers +dnl # +AC_DEFUN([AC_AMDGPU_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drmP.h], [ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + drm_fb_helper_remove_conflicting_pci_framebuffers(NULL, NULL); + ], [ + AC_DEFINE(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP, 1, + [drm_fb_helper_remove_conflicting_pci_framebuffers() wants p,p args]) + AC_DEFINE(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS, 1, + [drm_fb_helper_remove_conflicting_pci_framebuffers() is available]) + ], [ + dnl # + dnl # commit v4.19-rc1-110-g4d18975c78f2 + dnl # Author: Michał Mirosław + dnl # Date: Sat Sep 1 16:08:45 2018 +0200 + dnl # fbdev: add remove_conflicting_pci_framebuffers() + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + drm_fb_helper_remove_conflicting_pci_framebuffers(NULL, 0, NULL); + ], [ + AC_DEFINE(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PIP, 1, + [drm_fb_helper_remove_conflicting_pci_framebuffers() wants p,i,p args]) + AC_DEFINE(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS, 1, + [drm_fb_helper_remove_conflicting_pci_framebuffers() is available]) + ], [ + dnl # + dnl # commit 46eeb2c144956e88197439b5ee5cf221a91b0a81 + dnl # video/fb: Propagate error code from failing to unregister conflicting fb + dnl # + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + int ret = remove_conflicting_framebuffers(NULL, NULL, false); + ], [remove_conflicting_framebuffers], [drivers/video/fbdev/core/fbmem.c], [ + AC_DEFINE(HAVE_REMOVE_CONFLICTING_FRAMEBUFFERS_RETURNS_INT, 1, + [remove_conflicting_framebuffers() returns int]) + ]) + ]) + ]) + ], [ + AC_DEFINE(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP, 1, + [drm_fb_helper_remove_conflicting_pci_framebuffers() wants p,p args]) + AC_DEFINE(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS, 1, + [drm_fb_helper_remove_conflicting_pci_framebuffers() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 25256192d7137..a9df4cd3d5d78 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -32,6 +32,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_TTM_SG_TT_INIT AC_AMDGPU_DRM_CACHE AC_AMDGPU_DRM_DEBUG_ENABLED + AC_AMDGPU_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/backport/kcl_drm_fb.h b/include/kcl/backport/kcl_drm_fb.h new file mode 100644 index 0000000000000..c83d4ffd135b4 --- /dev/null +++ b/include/kcl/backport/kcl_drm_fb.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2016 Intel Corporation + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE. + */ +#ifndef KCL_BACKPORT_KCL_DRM_FB_H +#define KCL_BACKPORT_KCL_DRM_FB_H + +#include +#include + +#if !defined(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP) +#define drm_fb_helper_remove_conflicting_pci_framebuffers _kcl_drm_fb_helper_remove_conflicting_pci_framebuffers +#endif +#endif diff --git a/include/kcl/kcl_drm_fb.h b/include/kcl/kcl_drm_fb.h new file mode 100644 index 0000000000000..b05eecd7ae2bf --- /dev/null +++ b/include/kcl/kcl_drm_fb.h @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2006-2009 Red Hat Inc. + * Copyright (c) 2006-2008 Intel Corporation + * Copyright (c) 2007 Dave Airlie + * + * DRM framebuffer helper functions + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE. + * + * Authors: + * Dave Airlie + * Jesse Barnes + */ +#ifndef KCL_KCL_DRM_FB_H +#define KCL_KCL_DRM_FB_H + +#include +#include +#include + +#if !defined(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS) +#if !defined(IS_REACHABLE) +/* Copied from include/linux/kconfig.h */ +#define __ARG_PLACEHOLDER_1 0, +#define __take_second_arg(__ignored, val, ...) val + +/* + * The use of "&&" / "||" is limited in certain expressions. + * The followings enable to calculate "and" / "or" with macro expansion only. + */ +#define __and(x, y) ___and(x, y) +#define ___and(x, y) ____and(__ARG_PLACEHOLDER_##x, y) +#define ____and(arg1_or_junk, y) __take_second_arg(arg1_or_junk y, 0) + +#define __or(x, y) ___or(x, y) +#define ___or(x, y) ____or(__ARG_PLACEHOLDER_##x, y) +#define ____or(arg1_or_junk, y) __take_second_arg(arg1_or_junk 1, y) + +#define IS_REACHABLE(option) __or(IS_BUILTIN(option), \ + __and(IS_MODULE(option), __is_defined(MODULE))) +#endif /*IS_REACHABLE*/ + +extern int remove_conflicting_pci_framebuffers(struct pci_dev *pdev, int res_id, + const char *name); +static inline int +_kcl_drm_fb_helper_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, + const char *name) +{ +#if IS_REACHABLE(CONFIG_FB) + return remove_conflicting_pci_framebuffers(pdev, 0, name); +#else + return 0; +#endif +} +#elif !defined(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP) +static inline int +_kcl_drm_fb_helper_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, + const char *name) +{ + return drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, 0, name); +} +#endif /* HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS */ + +#endif From ad5c61fb4fcb40e6be77b7732fff90e78c5c3aa3 Mon Sep 17 00:00:00 2001 From: Evan Quan Date: Wed, 26 Aug 2020 10:06:31 +0800 Subject: [PATCH 0105/1868] drm/amdkcl: add macro DRM_MODE_ROTATE_xxx v2: move to kcl_drm_crtc.h v3: fix license for kcl drm part Signed-off-by: Evan Quan Reviewed-by: Junwei Zhang Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- include/kcl/kcl_drm_crtc.h | 76 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 76 insertions(+) create mode 100644 include/kcl/kcl_drm_crtc.h diff --git a/include/kcl/kcl_drm_crtc.h b/include/kcl/kcl_drm_crtc.h new file mode 100644 index 0000000000000..f027ec142c74e --- /dev/null +++ b/include/kcl/kcl_drm_crtc.h @@ -0,0 +1,76 @@ +/* + * Copyright © 2006 Keith Packard + * Copyright © 2007-2008 Dave Airlie + * Copyright © 2007-2008 Intel Corporation + * Jesse Barnes + * For codes copied from include/drm/drm_crtc.h + * + * Copyright © 2006 Keith Packard + * Copyright © 2007-2008 Dave Airlie + * Copyright © 2007-2008 Intel Corporation + * Jesse Barnes + * For codes copied from include/drm/drm_crtc_helper.h + * + * Copyright (c) 2007 Dave Airlie + * Copyright (c) 2007 Jakob Bornecrantz + * Copyright (c) 2008 Red Hat Inc. + * Copyright (c) 2007-2008 Tungsten Graphics, Inc., Cedar Park, TX., USA + * Copyright (c) 2007-2008 Intel Corporation + * For codes copied from include/drm/drm_mode.h + * + * Copyright 2018 Intel Corporation + * For codes copied from include/drm/drm_util.h + * + * Copyright (c) 2016 Intel Corporation + * For codes copied from include/drm/drm_encoder.h + * + * Copyright (c) 2016 Intel Corporation + * For codes copied from include/drm/drm_framebuffer.h + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef KCL_KCL_DRM_CRTC_H +#define KCL_KCL_DRM_CRTC_H + +#include +#include + +/* Copied from include/drm/drm_mode.h */ +#ifndef DRM_MODE_ROTATE_0 +#define DRM_MODE_ROTATE_0 (1<<0) +#endif +#ifndef DRM_MODE_ROTATE_90 +#define DRM_MODE_ROTATE_90 (1<<1) +#endif +#ifndef DRM_MODE_ROTATE_180 +#define DRM_MODE_ROTATE_180 (1<<2) +#endif +#ifndef DRM_MODE_ROTATE_270 +#define DRM_MODE_ROTATE_270 (1<<3) +#endif + +#ifndef DRM_MODE_ROTATE_MASK +#define DRM_MODE_ROTATE_MASK (\ + DRM_MODE_ROTATE_0 | \ + DRM_MODE_ROTATE_90 | \ + DRM_MODE_ROTATE_180 | \ + DRM_MODE_ROTATE_270) +#endif + +#endif From 4d330ab4b6c7cfecefd37eadf50800f929bbe4bc Mon Sep 17 00:00:00 2001 From: Chengming Gui Date: Thu, 29 Aug 2019 16:50:23 +0800 Subject: [PATCH 0106/1868] drm/amdkcl: Test whether drm_connector_update_edid_property() is available Introduced by kernel v4.19-rc1~28^2~27^2~22 Signed-off-by: Chengming Gui Reviewed-by: Flora Cui Signed-off-by: Jack Gui drm/amdkcl: fix license for kcl drm part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/backport/backport.h | 1 + .../m4/drm-connector-update-edid-property.m4 | 16 ++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_connector.h | 32 +++++++++++++++++++ 4 files changed, 50 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-connector-update-edid-property.m4 create mode 100644 include/kcl/kcl_drm_connector.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 05cff055dd4f0..ea1f38e85da3d 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -33,5 +33,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-update-edid-property.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-update-edid-property.m4 new file mode 100644 index 0000000000000..eade2ed63d298 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector-update-edid-property.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit c555f02371c338b06752577aebf738dbdb6907bd +dnl # drm: drop _mode_ from update_edit_property() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_UPDATE_EDID_PROPERTY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + drm_connector_update_edid_property(NULL, NULL); + ],[drm_connector_update_edid_property],[drivers/gpu/drm/drm_connector.c],[ + AC_DEFINE(HAVE_DRM_CONNECTOR_UPDATE_EDID_PROPERTY, 1, + [drm_connector_update_edid_property() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index a9df4cd3d5d78..f6480c620e89e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -33,6 +33,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CACHE AC_AMDGPU_DRM_DEBUG_ENABLED AC_AMDGPU_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS + AC_AMDGPU_DRM_CONNECTOR_UPDATE_EDID_PROPERTY AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_connector.h b/include/kcl/kcl_drm_connector.h new file mode 100644 index 0000000000000..ce58a5236fbac --- /dev/null +++ b/include/kcl/kcl_drm_connector.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2016 Intel Corporation + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE. + */ +#ifndef AMDKCL_DRM_CONNECTOR_H +#define AMDKCL_DRM_CONNECTOR_H + +#include +#include + +#ifndef HAVE_DRM_CONNECTOR_UPDATE_EDID_PROPERTY +#define drm_connector_update_edid_property drm_mode_connector_update_edid_property +#endif + +#endif /* AMDKCL_DRM_CONNECTOR_H */ From 6164d37ac1757ac28aa6f01861a77e45fb02dfd3 Mon Sep 17 00:00:00 2001 From: Chengming Gui Date: Thu, 29 Aug 2019 16:58:01 +0800 Subject: [PATCH 0107/1868] drm/amdkcl: Test whether drm_connector_attach_encoder() is available Introduced by kernel v4.19-rc1~28^2~27^2~21 Signed-off-by: Chengming Gui Reviewed-by: Flora Cui Signed-off-by: Jack Gui --- .../amd/dkms/m4/drm-connector-attach-encoder.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_connector.h | 4 ++++ 3 files changed, 21 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-connector-attach-encoder.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-attach-encoder.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-attach-encoder.m4 new file mode 100644 index 0000000000000..9b4bd0e561b64 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector-attach-encoder.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit cde4c44d8769c1be16074c097592c46c7d64092b +dnl # drm: drop _mode_ from drm_mode_connector_attach_encode +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_ATTACH_ENCODER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + drm_connector_attach_encoder(NULL, NULL); + ],[drm_connector_attach_encoder],[drivers/gpu/drm/drm_connector.c],[ + AC_DEFINE(HAVE_DRM_CONNECTOR_ATTACH_ENCODER, 1, + [drm_connector_attach_encoder() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index f6480c620e89e..201d629dd6831 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -34,6 +34,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DEBUG_ENABLED AC_AMDGPU_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS AC_AMDGPU_DRM_CONNECTOR_UPDATE_EDID_PROPERTY + AC_AMDGPU_DRM_CONNECTOR_ATTACH_ENCODER AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_connector.h b/include/kcl/kcl_drm_connector.h index ce58a5236fbac..5e26174b89b97 100644 --- a/include/kcl/kcl_drm_connector.h +++ b/include/kcl/kcl_drm_connector.h @@ -29,4 +29,8 @@ #define drm_connector_update_edid_property drm_mode_connector_update_edid_property #endif +#ifndef HAVE_DRM_CONNECTOR_ATTACH_ENCODER +#define drm_connector_attach_encoder drm_mode_connector_attach_encoder +#endif + #endif /* AMDKCL_DRM_CONNECTOR_H */ From 593b978a3d70cf5b62b7e70af61d1dfff735da4e Mon Sep 17 00:00:00 2001 From: Chengming Gui Date: Thu, 29 Aug 2019 17:03:30 +0800 Subject: [PATCH 0108/1868] drm/amdkcl: Test whether drm_connector_set_path_property() is available Introduced by kernel v4.19-rc1~28^2~27^2~20 Signed-off-by: Chengming Gui Reviewed-by: Flora Cui Signed-off-by: Jack Gui --- .../dkms/m4/drm-connector-set-path-property.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_connector.h | 4 ++++ 3 files changed, 21 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-connector-set-path-property.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-set-path-property.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-set-path-property.m4 new file mode 100644 index 0000000000000..f872d0db19a2e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector-set-path-property.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit 97e14fbeb53fe060c5f6a7a07e37fd24c087ed0c +dnl # drm: drop _mode_ from remaining connector functions +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_SET_PATH_PROPERTY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + drm_connector_set_path_property(NULL, NULL); + ],[drm_connector_set_path_property],[drivers/gpu/drm/drm_connector.c],[ + AC_DEFINE(HAVE_DRM_CONNECTOR_SET_PATH_PROPERTY, 1, + [drm_connector_set_path_property() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 201d629dd6831..0df51593ebe56 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -35,6 +35,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS AC_AMDGPU_DRM_CONNECTOR_UPDATE_EDID_PROPERTY AC_AMDGPU_DRM_CONNECTOR_ATTACH_ENCODER + AC_AMDGPU_DRM_CONNECTOR_SET_PATH_PROPERTY AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_connector.h b/include/kcl/kcl_drm_connector.h index 5e26174b89b97..557629af9c283 100644 --- a/include/kcl/kcl_drm_connector.h +++ b/include/kcl/kcl_drm_connector.h @@ -33,4 +33,8 @@ #define drm_connector_attach_encoder drm_mode_connector_attach_encoder #endif +#ifndef HAVE_DRM_CONNECTOR_SET_PATH_PROPERTY +#define drm_connector_set_path_property drm_mode_connector_set_path_property +#endif + #endif /* AMDKCL_DRM_CONNECTOR_H */ From 1756f6f9268519562c3e7d06ffa297cd05b49016 Mon Sep 17 00:00:00 2001 From: tianci yin Date: Thu, 14 Feb 2019 10:08:11 +0800 Subject: [PATCH 0109/1868] drm/amdkcl: check whether drm_connector_for_each_possible_encoder is available drm_connector_for_each_possible_encoder was introduced by the below commit since 4.19-rc1, add kcl implement for older kernel. "drm: Add drm_connector_for_each_possible_encoder()" for_each_if is introduce from v4.5-rc1 . so it's not available on drm < 4.5 like rhel6.10 . v1: drm/amdkcl: [4.19] kcl for drm_connector_for_each_possible_encoder v2: drm/amdkcl: check whether drm_connector_for_each_possible_encoder is available v3: drm_connector_for_each_possible_encoder Reviewed-by: changzhu Signed-off-by: Tianci Yin Signed-off-by: Chengming Gui Signed-off-by: Flora Cui Signed-off-by: Jack Gui Reviewed-by: Flora Cui Signed-off-by: Yifan Zhang --- include/kcl/kcl_drm_connector.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/include/kcl/kcl_drm_connector.h b/include/kcl/kcl_drm_connector.h index 557629af9c283..313ab68fc65f5 100644 --- a/include/kcl/kcl_drm_connector.h +++ b/include/kcl/kcl_drm_connector.h @@ -24,6 +24,7 @@ #include #include +#include #ifndef HAVE_DRM_CONNECTOR_UPDATE_EDID_PROPERTY #define drm_connector_update_edid_property drm_mode_connector_update_edid_property @@ -37,4 +38,20 @@ #define drm_connector_set_path_property drm_mode_connector_set_path_property #endif +/** + * drm_connector_for_each_possible_encoder - iterate connector's possible encoders + * @connector: &struct drm_connector pointer + * @encoder: &struct drm_encoder pointer used as cursor + * @__i: int iteration cursor, for macro-internal use + */ +#ifndef drm_connector_for_each_possible_encoder +#define drm_connector_for_each_possible_encoder(connector, encoder, __i) \ + for ((__i) = 0; (__i) < ARRAY_SIZE((connector)->encoder_ids) && \ + (connector)->encoder_ids[(__i)] != 0; (__i)++) \ + for_each_if((encoder) = \ + drm_encoder_find((connector)->dev, NULL, \ + (connector)->encoder_ids[(__i)])) \ + +#endif + #endif /* AMDKCL_DRM_CONNECTOR_H */ From f4c944394974f41e08107d94898a0367d51326cd Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 5 Dec 2019 15:22:06 +0800 Subject: [PATCH 0110/1868] drm/amdkcl: Test whether drm_connector_init_with_ddc is available introduced by kernel v5.3-rc1-330-g100163df4203 v2: fix typo Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/Makefile | 3 ++- drivers/gpu/drm/amd/amdkcl/kcl_connector.c | 14 ++++++++++++++ .../amd/dkms/m4/drm-connector-init-with-ddc.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_connector.h | 17 +++++++++++++++++ 5 files changed, 50 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_connector.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-connector-init-with-ddc.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 704e31fc89a3d..e63bff1e7554b 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -8,7 +8,8 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_kthread.o kcl_io.o kcl_perf_event.o \ kcl_suspend.o kcl_pci.o kcl_mm.o \ kcl_fence.o kcl_fence_array.o kcl_reservation.o kcl_drm_cache.o \ - kcl_drm_fb.o kcl_fbmem.o + kcl_drm_fb.o kcl_fbmem.o \ + kcl_connector.o CFLAGS_kcl_fence.o := -I$(src) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_connector.c b/drivers/gpu/drm/amd/amdkcl/kcl_connector.c new file mode 100644 index 0000000000000..ff900e261cb43 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_connector.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: MIT */ +#include + +#ifndef HAVE_DRM_CONNECTOR_INIT_WITH_DDC +int _kcl_drm_connector_init_with_ddc(struct drm_device *dev, + struct drm_connector *connector, + const struct drm_connector_funcs *funcs, + int connector_type, + struct i2c_adapter *ddc) +{ + return drm_connector_init(dev, connector, funcs, connector_type); +} +EXPORT_SYMBOL(_kcl_drm_connector_init_with_ddc); +#endif diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-init-with-ddc.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-init-with-ddc.m4 new file mode 100644 index 0000000000000..9af2f9f8226b4 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector-init-with-ddc.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.3-rc1-330-g100163df4203 +dnl # drm: Add drm_connector_init() variant with ddc +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_INIT_WITH_DDC], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + drm_connector_init_with_ddc(NULL, NULL, NULL, 0, NULL); + ],[ + AC_DEFINE(HAVE_DRM_CONNECTOR_INIT_WITH_DDC, 1, + [drm_connector_init_with_ddc() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 0df51593ebe56..876fda15fdb41 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -36,6 +36,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_UPDATE_EDID_PROPERTY AC_AMDGPU_DRM_CONNECTOR_ATTACH_ENCODER AC_AMDGPU_DRM_CONNECTOR_SET_PATH_PROPERTY + AC_AMDGPU_DRM_CONNECTOR_INIT_WITH_DDC AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_connector.h b/include/kcl/kcl_drm_connector.h index 313ab68fc65f5..ac6c066aa3376 100644 --- a/include/kcl/kcl_drm_connector.h +++ b/include/kcl/kcl_drm_connector.h @@ -54,4 +54,21 @@ #endif +#ifndef HAVE_DRM_CONNECTOR_INIT_WITH_DDC +int _kcl_drm_connector_init_with_ddc(struct drm_device *dev, + struct drm_connector *connector, + const struct drm_connector_funcs *funcs, + int connector_type, + struct i2c_adapter *ddc); +static inline +int drm_connector_init_with_ddc(struct drm_device *dev, + struct drm_connector *connector, + const struct drm_connector_funcs *funcs, + int connector_type, + struct i2c_adapter *ddc) +{ + return _kcl_drm_connector_init_with_ddc(dev, connector, funcs, connector_type, ddc); +} +#endif + #endif /* AMDKCL_DRM_CONNECTOR_H */ From ad892554f99db5c9562cc4ec471bb3aeb6302a7d Mon Sep 17 00:00:00 2001 From: Prike Liang Date: Thu, 11 Oct 2018 13:46:20 +0800 Subject: [PATCH 0111/1868] drm/amdkcl: check whether ACPI_VIDEO_NOTIFY_PROBE is available Signed-off-by: Prike Liang Signed-off-by: Jack Gui drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_video.h | 11 +++++++++++ 2 files changed, 12 insertions(+) create mode 100644 include/kcl/kcl_video.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index ea1f38e85da3d..682284f3d2967 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include diff --git a/include/kcl/kcl_video.h b/include/kcl/kcl_video.h new file mode 100644 index 0000000000000..414cfdc2439a7 --- /dev/null +++ b/include/kcl/kcl_video.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_VIDEO_H +#define AMDKCL_VIDEO_H + +#include + +#ifndef ACPI_VIDEO_NOTIFY_PROBE +#define ACPI_VIDEO_NOTIFY_PROBE 0x81 +#endif + +#endif/*AMDKCL_VIDEO_H*/ From fbf152962046bbd1cca55fa94f4f40005700a941 Mon Sep 17 00:00:00 2001 From: Junwei Zhang Date: Mon, 18 Feb 2019 10:46:23 +0800 Subject: [PATCH 0112/1868] drm/amdkcl: Test whether ACPI_HANDLE is defined This is a squash of: drm/amdkcl: [RHEL 6] fix ACPI_HANDLE missing Signed-off-by: Junwei Zhang Reviewed-by: Qiang Yu Signed-off-by: Jack Gui drm/amdkcl: Test whether ACPI_HANDLE is defined Signed-off-by: Slava Grigorev Reviewed-by: Flora Cui Signed-off-by: Jack Gui drm/amdkcl: add comments for kcl_acpi.h Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_acpi.h | 26 +++++++++++++++++++++++++ 2 files changed, 27 insertions(+) create mode 100644 include/kcl/kcl_acpi.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 682284f3d2967..2df777a72095f 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include diff --git a/include/kcl/kcl_acpi.h b/include/kcl/kcl_acpi.h new file mode 100644 index 0000000000000..d6f499640f0b8 --- /dev/null +++ b/include/kcl/kcl_acpi.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * acpi.h - ACPI Interface + * + * Copyright (C) 2001 Paul Diefenbaugh + */ +#ifndef AMDKCL_ACPI_H +#define AMDKCL_ACPI_H + +/** + * interface change in mainline kernel 3.13 + * but only affect RHEL6 without backport + * v3.7-rc5-12-g95f8a082b9b1 ACPI / driver core: Introduce struct acpi_dev_node + * and related macros + * v3.12-8048-g7b1998116bbb ACPI / driver core: Store an ACPI device pointer in + * struct acpi_dev_node + */ + +#include + +/* Copied from include/linux/acpi.h> */ +#ifndef ACPI_HANDLE +#define ACPI_HANDLE(dev) DEVICE_ACPI_HANDLE(dev) +#endif + +#endif /* AMDKCL_ACPI_H */ From 8fe9a0e6be7948f7d964247a900984a132405f26 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 26 Aug 2020 15:35:29 +0800 Subject: [PATCH 0113/1868] drm/amdkcl: test kthread_{use,unuse}_mm() introduced in commit f5678e7f2ac3 ("kernel: better document the use_mm/unuse_mm API contract") Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/kthread_use_mm.m4 | 11 +++++++++++ include/kcl/kcl_kthread.h | 17 +++++++++++++++++ 3 files changed, 29 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/kthread_use_mm.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 876fda15fdb41..7f29ac453df37 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -37,6 +37,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_ATTACH_ENCODER AC_AMDGPU_DRM_CONNECTOR_SET_PATH_PROPERTY AC_AMDGPU_DRM_CONNECTOR_INIT_WITH_DDC + AC_AMDGPU_KTHREAD_USE_MM AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/kthread_use_mm.m4 b/drivers/gpu/drm/amd/dkms/m4/kthread_use_mm.m4 new file mode 100644 index 0000000000000..0b62fc9008c6b --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/kthread_use_mm.m4 @@ -0,0 +1,11 @@ +dnl # +dnl # f5678e7f2ac3 kernel: better document the use_mm/unuse_mm API contract +dnl # 9bf5b9eb232b kernel: move use_mm/unuse_mm to kthread.c +dnl # +AC_DEFUN([AC_AMDGPU_KTHREAD_USE_MM], [ + AC_KERNEL_CHECK_SYMBOL_EXPORT([kthread_use_mm kthread_unuse_mm], + [kernel/kthread.c], [ + AC_DEFINE(HAVE_KTHREAD_USE_MM, 1, + [kthread_{use,unuse}_mm() is available]) + ]) +]) diff --git a/include/kcl/kcl_kthread.h b/include/kcl/kcl_kthread.h index 66298a3726350..ecb650acee90e 100644 --- a/include/kcl/kcl_kthread.h +++ b/include/kcl/kcl_kthread.h @@ -4,6 +4,9 @@ #include #include +#ifndef HAVE_KTHREAD_USE_MM +#include +#endif #if !defined(HAVE___KTHREAD_SHOULD_PATK) extern bool __kcl_kthread_should_park(struct task_struct *k); @@ -15,4 +18,18 @@ extern void (*_kcl_kthread_unpark)(struct task_struct *k); extern int (*_kcl_kthread_park)(struct task_struct *k); extern bool (*_kcl_kthread_should_park)(void); #endif + +#ifndef HAVE_KTHREAD_USE_MM +static inline +void kthread_use_mm(struct mm_struct *mm) +{ + use_mm(mm); +} +static inline +void kthread_unuse_mm(struct mm_struct *mm) +{ + unuse_mm(mm); +} +#endif + #endif /* AMDKCL_KTHREAD_H */ From 14506d7606f17a11f8445e1bf381ac0f5ee78bec Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 27 Aug 2020 16:18:17 +0800 Subject: [PATCH 0114/1868] drm/amdkcl: test fault_flag_allow_retry_first() Signed-off-by: Flora Cui --- .../amd/dkms/m4/fault_flag_allow_retry_first.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_mm.h | 8 ++++++++ 3 files changed, 25 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/fault_flag_allow_retry_first.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/fault_flag_allow_retry_first.m4 b/drivers/gpu/drm/amd/dkms/m4/fault_flag_allow_retry_first.m4 new file mode 100644 index 0000000000000..ce4b655254f91 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/fault_flag_allow_retry_first.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.6-5709-g4064b9827063 +dnl # mm: allow VM_FAULT_RETRY for multiple times +dnl # +AC_DEFUN([AC_AMDGPU_FAULT_FLAG_ALLOW_RETRY_FIRST], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + fault_flag_allow_retry_first(0); + ], [ + AC_DEFINE(HAVE_FAULT_FLAG_ALLOW_RETRY_FIRST, 1, + [fault_flag_allow_retry_first() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 7f29ac453df37..5fdb1075e4658 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -38,6 +38,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_SET_PATH_PROPERTY AC_AMDGPU_DRM_CONNECTOR_INIT_WITH_DDC AC_AMDGPU_KTHREAD_USE_MM + AC_AMDGPU_FAULT_FLAG_ALLOW_RETRY_FIRST AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_mm.h b/include/kcl/kcl_mm.h index f300ba76bf794..f7616dde77031 100644 --- a/include/kcl/kcl_mm.h +++ b/include/kcl/kcl_mm.h @@ -14,4 +14,12 @@ #define untagged_addr(addr) (addr) #endif +#ifndef HAVE_FAULT_FLAG_ALLOW_RETRY_FIRST +static inline bool fault_flag_allow_retry_first(unsigned int flags) +{ + return (flags & FAULT_FLAG_ALLOW_RETRY) && + (!(flags & FAULT_FLAG_TRIED)); +} +#endif + #endif /* AMDKCL_MM_H */ From b1d65fd34c2a2b878e6a802855b445f2e63eaceb Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Wed, 12 Jun 2019 11:03:57 -0400 Subject: [PATCH 0115/1868] drm/amdkcl: Test whether drm_printf() function is available Signed-off-by: Slava Grigorev Signed-off-by: Yifan Zhang Signed-off-by: Jack Gui Signed-off-by: Flora Cui drm/amdkcl: split drm_print stuff to kcl_drm_print.[ch] Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c | 41 +++++++++++++++++++ drivers/gpu/drm/scheduler/backport/backport.h | 2 +- drivers/gpu/drm/ttm/backport/backport.h | 1 + include/kcl/kcl_drm_print.h | 15 ++++++- 5 files changed, 57 insertions(+), 4 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index e63bff1e7554b..dc2f9b9255877 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -8,7 +8,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_kthread.o kcl_io.o kcl_perf_event.o \ kcl_suspend.o kcl_pci.o kcl_mm.o \ kcl_fence.o kcl_fence_array.o kcl_reservation.o kcl_drm_cache.o \ - kcl_drm_fb.o kcl_fbmem.o \ + kcl_drm_fb.o kcl_drm_print.o kcl_fbmem.o \ kcl_connector.o CFLAGS_kcl_fence.o := -I$(src) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c new file mode 100644 index 0000000000000..47b68ba76db6f --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2016 Red Hat + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Rob Clark + */ +#include +#include + +#if !defined(HAVE_DRM_DRM_PRINT_H) +void drm_printf(struct drm_printer *p, const char *f, ...) +{ + struct va_format vaf; + va_list args; + + va_start(args, f); + vaf.fmt = f; + vaf.va = &args; + p->printfn(p, &vaf); + va_end(args); +} +EXPORT_SYMBOL(drm_printf); +#endif diff --git a/drivers/gpu/drm/scheduler/backport/backport.h b/drivers/gpu/drm/scheduler/backport/backport.h index 28b00db43738f..4a62c9677187a 100644 --- a/drivers/gpu/drm/scheduler/backport/backport.h +++ b/drivers/gpu/drm/scheduler/backport/backport.h @@ -5,5 +5,5 @@ #include #include #include - +#include #endif diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index 48f3f3bc56a71..9f3fbf350006e 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -7,4 +7,5 @@ #include #include #include +#include #endif diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index 03dce456987d5..4cdae9fe3968d 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -25,8 +25,19 @@ #ifndef AMDKCL_DRM_PRINT_H #define AMDKCL_DRM_PRINT_H -#include -#include +#include +#include + +#if !defined(HAVE_DRM_DRM_PRINT_H) +/* Copied from include/drm/drm_print.h */ +struct drm_printer { + void (*printfn)(struct drm_printer *p, struct va_format *vaf); + void *arg; + const char *prefix; +}; + +void drm_printf(struct drm_printer *p, const char *f, ...); +#endif #ifndef HAVE_DRM_DEBUG_ENABLED /* Copied from v5.3-rc1-708-gf0a8f533adc2 include/drm/drm_print.h */ From dd218a4875c12c98fc05dc5ba1020e4542473e83 Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Wed, 14 Aug 2019 12:58:05 +0800 Subject: [PATCH 0116/1868] drm/amdkcl: Test whether drm_debug_printer is available v1: drm/amdkcl: Test whether drm_debug_printer() function is available v2: drm/amdkcl: fix the struct drm_printer error. v3: drm/amdkcl: fix drm_printer related checks v4: drm/amdkcl: accommodate to drmP.h removal for drm-mm-print.m4 Signed-off-by: Yifan Zhang Reviewed-by: Flora Cui Reviewed-by: Feifei Xu Signed-off-by: Slava Grigorev Signed-off-by: Jack Gui Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang drm/amdkcl: split drm_print stuff to kcl_drm_print.[ch] Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c | 12 ++++++++++ .../gpu/drm/amd/dkms/m4/drm-debug-printer.m4 | 16 ++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_print.h | 22 +++++++++++++++++++ 4 files changed, 51 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-debug-printer.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c index 47b68ba76db6f..3b5945b8bee0a 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c @@ -39,3 +39,15 @@ void drm_printf(struct drm_printer *p, const char *f, ...) } EXPORT_SYMBOL(drm_printf); #endif + +#if !defined(HAVE_DRM_DEBUG_PRINTER) +void __drm_printfn_debug(struct drm_printer *p, struct va_format *vaf) +{ +#if !defined(HAVE_DRM_DRM_PRINT_H) + pr_debug("%s %pV", p->prefix, vaf); +#else + pr_debug("%s %pV", "no prefix < 4.11", vaf); +#endif +} +EXPORT_SYMBOL(__drm_printfn_debug); +#endif diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-debug-printer.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-debug-printer.m4 new file mode 100644 index 0000000000000..3fdcea368bf1e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-debug-printer.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit 3d387d923c18afbacef8f14ccaa2ace2a297df74 +dnl # drm/printer: add debug printer +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DEBUG_PRINTER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_debug_printer(NULL); + ], [ + AC_DEFINE(HAVE_DRM_DEBUG_PRINTER, 1, + [drm_debug_printer() function is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 5fdb1075e4658..7e2af6cbb3cd5 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -39,6 +39,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_INIT_WITH_DDC AC_AMDGPU_KTHREAD_USE_MM AC_AMDGPU_FAULT_FLAG_ALLOW_RETRY_FIRST + AC_AMDGPU_DRM_DEBUG_PRINTER AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index 4cdae9fe3968d..bd2996d38f602 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -39,6 +39,28 @@ struct drm_printer { void drm_printf(struct drm_printer *p, const char *f, ...); #endif +/** + * drm_debug_printer - construct a &drm_printer that outputs to pr_debug() + * @prefix: debug output prefix + * + * RETURNS: + * The &drm_printer object + */ +#if !defined(HAVE_DRM_DEBUG_PRINTER) +extern void __drm_printfn_debug(struct drm_printer *p, struct va_format *vaf); + +static inline struct drm_printer drm_debug_printer(const char *prefix) +{ + struct drm_printer p = { + .printfn = __drm_printfn_debug, +#if !defined(HAVE_DRM_DRM_PRINT_H) + .prefix = prefix +#endif + }; + return p; +} +#endif + #ifndef HAVE_DRM_DEBUG_ENABLED /* Copied from v5.3-rc1-708-gf0a8f533adc2 include/drm/drm_print.h */ static inline bool drm_debug_enabled(unsigned int category) From d007f5cc9a16791c8ee8519963200416ffcacfa7 Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Fri, 22 Nov 2019 13:09:50 +0800 Subject: [PATCH 0117/1868] drm/amdkcl: check whether DRM_DEV_{ERROR/DEBUG} are available v2: move DRM_DEV_ERROR to kcl_drm.h v3: drm/amdkcl: split drm_print stuff to kcl_drm_print.[ch] Signed-off-by: Yifan Zhang Signed-off-by: Flora Cui Reviewed-by: Flora Cui Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang Reviewed-by: Felix Kuehling --- include/kcl/kcl_drm_print.h | 52 +++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index bd2996d38f602..65db884854a3d 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -61,6 +61,58 @@ static inline struct drm_printer drm_debug_printer(const char *prefix) } #endif +#ifndef _DRM_PRINTK +#define _DRM_PRINTK(once, level, fmt, ...) \ + do { \ + printk##once(KERN_##level "[" DRM_NAME "] " fmt, \ + ##__VA_ARGS__); \ + } while (0) +#endif + +#ifndef DRM_WARN +#define DRM_WARN(fmt, ...) \ + _DRM_PRINTK(, WARNING, fmt, ##__VA_ARGS__) +#endif + +#ifndef DRM_WARN_ONCE +#define DRM_WARN_ONCE(fmt, ...) \ + _DRM_PRINTK(_once, WARNING, fmt, ##__VA_ARGS__) +#endif + +#ifndef DRM_NOTE +#define DRM_NOTE(fmt, ...) \ + _DRM_PRINTK(, NOTICE, fmt, ##__VA_ARGS__) +#endif + +#ifndef DRM_NOTE_ONCE +#define DRM_NOTE_ONCE(fmt, ...) \ + _DRM_PRINTK(_once, NOTICE, fmt, ##__VA_ARGS__) +#endif + +#ifndef DRM_ERROR +#define DRM_ERROR(fmt, ...) \ + drm_printk(KERN_ERR, DRM_UT_NONE, fmt, ##__VA_ARGS__) +#endif + +#if !defined(DRM_DEV_DEBUG) +#define DRM_DEV_DEBUG(dev, fmt, ...) \ + DRM_DEBUG(fmt, ##__VA_ARGS__) +#endif + +#if !defined(DRM_DEV_ERROR) +#define DRM_DEV_ERROR(dev, fmt, ...) \ + DRM_ERROR(fmt, ##__VA_ARGS__) +#endif + +#ifndef DRM_DEBUG_VBL +#define DRM_UT_VBL 0x20 +#define DRM_DEBUG_VBL(fmt, args...) \ + do { \ + if (unlikely(drm_debug & DRM_UT_VBL)) \ + drm_ut_debug_printk(__func__, fmt, ##args); \ + } while (0) +#endif + #ifndef HAVE_DRM_DEBUG_ENABLED /* Copied from v5.3-rc1-708-gf0a8f533adc2 include/drm/drm_print.h */ static inline bool drm_debug_enabled(unsigned int category) From 44c13350b4f24dd9d3f3495f13af4375742ae280 Mon Sep 17 00:00:00 2001 From: Anatoli Antonovitch Date: Mon, 24 Sep 2018 15:29:41 -0400 Subject: [PATCH 0118/1868] drm/amdkcl: Test whether drm_gem_object_put_unlocked() is available v2: drop kcl_drm_gem_object_put_unlocked v3: Add wrap for drm_gem_object_get v4: add wrap for drm_gem_object_put() v5: drm/amdkcl: split drm_gem related stuff Signed-off-by: Anatoli Antonovitch Signed-off-by: Yifan Zhang Signed-off-by: Jack Gui Signed-off-by: Flora Cui Acked-by: Feifei Xu / Signed-off-by: Jack Gui Signed-off-by: Flora Cui Signed-off-by: Chengming Gui Reviewed-by: Flora Cui Signed-off-by: Flora Cui Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/backport/backport.h | 1 + .../gpu/drm/amd/dkms/m4/drm-gem-object-ref.m4 | 28 +++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/backport/kcl_drm_gem.h | 45 ++++++++++++++ include/kcl/kcl_drm_gem.h | 60 +++++++++++++++++++ 5 files changed, 135 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-gem-object-ref.m4 create mode 100644 include/kcl/backport/kcl_drm_gem.h create mode 100644 include/kcl/kcl_drm_gem.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 2df777a72095f..ffe385190e8ee 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -34,6 +34,7 @@ #include #include #include +#include #include #include diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-gem-object-ref.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-gem-object-ref.m4 new file mode 100644 index 0000000000000..f73dc8440b756 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-gem-object-ref.m4 @@ -0,0 +1,28 @@ +dnl # +dnl # v5.7-rc1-518-gab15d56e27be drm: remove transient drm_gem_object_put_unlocked() +dnl # v5.7-rc1-491-geecd7fd8bf58 drm/gem: add _locked suffix to drm_gem_object_put +dnl # v5.7-rc1-490-gb5d250744ccc drm/gem: fold drm_gem_object_put_unlocked and __drm_gem_object_put() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_GEM_OBJECT_PUT_UNLOCKED], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT( + [drm_gem_object_put_locked], [drivers/gpu/drm/drm_gem.c], + [ + AC_DEFINE(HAVE_DRM_GEM_OBJECT_PUT_LOCKED, 1, + [drm_gem_object_put_locked() is available]) + ], [ + dnl # + dnl # commit v4.10-rc8-1302-ge6b62714e87c + dnl # drm: Introduce drm_gem_object_{get,put}() + dnl # + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_gem_object_put_unlocked(NULL); + ], [drm_gem_object_put_unlocked], [drivers/gpu/drm/drm_gem.c], [ + AC_DEFINE(HAVE_DRM_GEM_OBJECT_PUT_UNLOCKED, 1, + [drm_gem_object_put_unlocked() is available]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 7e2af6cbb3cd5..3067457e3882d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -32,6 +32,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_TTM_SG_TT_INIT AC_AMDGPU_DRM_CACHE AC_AMDGPU_DRM_DEBUG_ENABLED + AC_AMDGPU_DRM_GEM_OBJECT_PUT_UNLOCKED AC_AMDGPU_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS AC_AMDGPU_DRM_CONNECTOR_UPDATE_EDID_PROPERTY AC_AMDGPU_DRM_CONNECTOR_ATTACH_ENCODER diff --git a/include/kcl/backport/kcl_drm_gem.h b/include/kcl/backport/kcl_drm_gem.h new file mode 100644 index 0000000000000..373e3719b4c57 --- /dev/null +++ b/include/kcl/backport/kcl_drm_gem.h @@ -0,0 +1,45 @@ +/* + * GEM Graphics Execution Manager Driver Interfaces + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * Copyright (c) 2009-2010, Code Aurora Forum. + * All rights reserved. + * Copyright © 2014 Intel Corporation + * Daniel Vetter + * + * Author: Rickard E. (Rik) Faith + * Author: Gareth Hughes + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef __KCL_BACKPORT_KCL_DRM_GEM_H__ +#define __KCL_BACKPORT_KCL_DRM_GEM_H__ + +#include + +#if !defined(HAVE_DRM_GEM_OBJECT_PUT_LOCKED) +#if defined(HAVE_DRM_GEM_OBJECT_PUT_UNLOCKED) +#define drm_gem_object_put _kcl_drm_gem_object_put +#endif +#endif + +#endif diff --git a/include/kcl/kcl_drm_gem.h b/include/kcl/kcl_drm_gem.h new file mode 100644 index 0000000000000..a0f90deb18b06 --- /dev/null +++ b/include/kcl/kcl_drm_gem.h @@ -0,0 +1,60 @@ +/* + * GEM Graphics Execution Manager Driver Interfaces + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * Copyright (c) 2009-2010, Code Aurora Forum. + * All rights reserved. + * Copyright © 2014 Intel Corporation + * Daniel Vetter + * + * Author: Rickard E. (Rik) Faith + * Author: Gareth Hughes + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef __KCL_KCL_DRM_GEM_H__ +#define __KCL_KCL_DRM_GEM_H__ + +#include +#if !defined(HAVE_DRM_GEM_OBJECT_PUT_LOCKED) +#if defined(HAVE_DRM_GEM_OBJECT_PUT_UNLOCKED) +static inline void +_kcl_drm_gem_object_put(struct drm_gem_object *obj) +{ + return drm_gem_object_put_unlocked(obj); +} +#else +static inline void +drm_gem_object_put(struct drm_gem_object *obj) +{ + return drm_gem_object_unreference_unlocked(obj); +} + +static inline void +drm_gem_object_get(struct drm_gem_object *obj) +{ + kref_get(&obj->refcount); +} +#endif +#endif /* HAVE_DRM_GEM_OBJECT_PUT_LOCKED */ + +#endif From 714173a0764ce0bfd9a679244ca8dbf46f389a89 Mon Sep 17 00:00:00 2001 From: Chengming Gui Date: Thu, 19 Sep 2019 13:44:02 +0800 Subject: [PATCH 0119/1868] drm/amdkcl: Test whether drm_fb_helper_fill_info() is available Introduced by kernel v5.2-rc1~48^2~37^2~7 v2: implement drm_fb_helper_fill_info() for kernel don't have it. v3: drm/amdkcl: drop symbol check for drm_fb_helper_fill_info v4: drm/amdkcl: accommodate to drmP.h removal for drm-fb-helper-fill-info.m4 v5: move to kcl_drm_fb.h Signed-off-by: Chengming Gui Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang --- drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c | 30 +++++++++++++++++++ .../amd/dkms/m4/drm-fb-helper-fill-info.m4 | 22 ++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_fb.h | 6 ++++ 4 files changed, 59 insertions(+) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-fill-info.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c new file mode 100644 index 0000000000000..d803603612ab8 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: MIT */ +#include +#include +#include +#include +#include +#include + +#ifndef HAVE_DRM_FB_HELPER_FILL_INFO +void drm_fb_helper_fill_info(struct fb_info *info, + struct drm_fb_helper *fb_helper, + struct drm_fb_helper_surface_size *sizes) +{ + struct drm_framebuffer *fb = fb_helper->fb; + +#ifdef HAVE_DRM_FRAMEBUFFER_FORMAT + drm_fb_helper_fill_fix(info, fb->pitches[0], fb->format->depth); +#else + drm_fb_helper_fill_fix(info, fb->pitches[0], fb->depth); +#endif + drm_fb_helper_fill_var(info, fb_helper, + sizes->fb_width, sizes->fb_height); + + info->par = fb_helper; + snprintf(info->fix.id, sizeof(info->fix.id), "%sdrmfb", + fb_helper->dev->driver->name); + +} +EXPORT_SYMBOL(drm_fb_helper_fill_info); +#endif diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-fill-info.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-fill-info.m4 new file mode 100644 index 0000000000000..23832e30bd48e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-fill-info.m4 @@ -0,0 +1,22 @@ +dnl # +dnl # commit ec8bf1942567bf0736314da9723e93bcc73c131f +dnl # drm/fb-helper: Fixup fill_info cleanup +dnl # +AC_DEFUN([AC_AMDGPU_DRM_FB_HELPER_FILL_INFO], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drmP.h], [ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + drm_fb_helper_fill_info(NULL, NULL, NULL); + ], [ + AC_DEFINE(HAVE_DRM_FB_HELPER_FILL_INFO, 1, + [drm_fb_helper_fill_info() is available]) + ]) + ], [ + AC_DEFINE(HAVE_DRM_FB_HELPER_FILL_INFO, 1, + [drm_fb_helper_fill_info() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 3067457e3882d..30f36e74b2326 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -41,6 +41,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_KTHREAD_USE_MM AC_AMDGPU_FAULT_FLAG_ALLOW_RETRY_FIRST AC_AMDGPU_DRM_DEBUG_PRINTER + AC_AMDGPU_DRM_FB_HELPER_FILL_INFO AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_fb.h b/include/kcl/kcl_drm_fb.h index b05eecd7ae2bf..46fdedd66a9ca 100644 --- a/include/kcl/kcl_drm_fb.h +++ b/include/kcl/kcl_drm_fb.h @@ -77,4 +77,10 @@ _kcl_drm_fb_helper_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, } #endif /* HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS */ +#ifndef HAVE_DRM_FB_HELPER_FILL_INFO +void drm_fb_helper_fill_info(struct fb_info *info, + struct drm_fb_helper *fb_helper, + struct drm_fb_helper_surface_size *sizes); +#endif + #endif From ff13fc0a64275778a37404e21daac98018226c63 Mon Sep 17 00:00:00 2001 From: Chengming Gui Date: Thu, 22 Aug 2019 09:52:00 +0800 Subject: [PATCH 0120/1868] drm/amdkcl: Test whehter drm_fb_helper_set_suspend_unlocked() is available drm_fb_helper_set_suspend_unlocked() introduced and exported by kernel v4.9-rc1~41^2~39^2~4 v1: drm/amdkcl: drop kcl_drm_fb_helper_set_suspend_unlocked v2: drm/amdkcl: drop symbol check for drm_fb_helper_set_suspend_unlocked v3: drm/amdkcl: accommodate to drmP.h removal for drm-fb-helper-set-suspend-unlocked.m4 Signed-off-by: Chengming Gui Reviewed-by: Flora Cui Acked-by: Feifei Xu / Signed-off-by: Jack Gui Reviewed-by: Yifan Zhang Signed-off-by: Jiansong Chen Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c | 21 ++++++++++++++++++ .../m4/drm-fb-helper-set-suspend-unlocked.m4 | 22 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_fb.h | 11 ++++++++++ 4 files changed, 55 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-set-suspend-unlocked.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c index d803603612ab8..900629e0dc0ed 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: MIT */ #include #include +#include #include #include #include @@ -28,3 +29,23 @@ void drm_fb_helper_fill_info(struct fb_info *info, } EXPORT_SYMBOL(drm_fb_helper_fill_info); #endif + +#ifndef HAVE_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED +/** + * _kcl_drm_fb_helper_set_suspend_stub - wrapper around fb_set_suspend + * @fb_helper: driver-allocated fbdev helper + * @state: desired state, zero to resume, non-zero to suspend + * + * A wrapper around fb_set_suspend implemented by fbdev core + */ +void _kcl_drm_fb_helper_set_suspend_unlocked(struct drm_fb_helper *fb_helper, int state) +{ + if (!fb_helper || !fb_helper->fbdev) + return; + + console_lock(); + fb_set_suspend(fb_helper->fbdev, state); + console_unlock(); +} +EXPORT_SYMBOL(_kcl_drm_fb_helper_set_suspend_unlocked); +#endif diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-set-suspend-unlocked.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-set-suspend-unlocked.m4 new file mode 100644 index 0000000000000..cd00b4a9ac55c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-set-suspend-unlocked.m4 @@ -0,0 +1,22 @@ +dnl # +dnl # commit cfe63423d9be3e7020296c3dfb512768a83cd099 +dnl # drm/fb-helper: Add drm_fb_helper_set_suspend_unlocked() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drmP.h], [ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + drm_fb_helper_set_suspend_unlocked(NULL,0); + ], [ + AC_DEFINE(HAVE_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED, 1, + [drm_fb_helper_set_suspend_unlocked() is available]) + ]) + ], [ + AC_DEFINE(HAVE_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED, 1, + [drm_fb_helper_set_suspend_unlocked() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 30f36e74b2326..42eb904bcfbf9 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -42,6 +42,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_FAULT_FLAG_ALLOW_RETRY_FIRST AC_AMDGPU_DRM_DEBUG_PRINTER AC_AMDGPU_DRM_FB_HELPER_FILL_INFO + AC_AMDGPU_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_fb.h b/include/kcl/kcl_drm_fb.h index 46fdedd66a9ca..76b6ade463704 100644 --- a/include/kcl/kcl_drm_fb.h +++ b/include/kcl/kcl_drm_fb.h @@ -83,4 +83,15 @@ void drm_fb_helper_fill_info(struct fb_info *info, struct drm_fb_helper_surface_size *sizes); #endif +#ifndef HAVE_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED +extern void _kcl_drm_fb_helper_set_suspend_unlocked(struct drm_fb_helper *fb_helper, int state); +static inline +void drm_fb_helper_set_suspend_unlocked(struct drm_fb_helper *fb_helper, + bool suspend) + +{ + _kcl_drm_fb_helper_set_suspend_unlocked(fb_helper, suspend); +} +#endif + #endif From a7c61d2909804c624375c9ad7e9dc9b62bef6735 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Sat, 12 Oct 2019 10:26:05 +0800 Subject: [PATCH 0121/1868] drm/amdkcl: check whether dev_err_once() is available Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- include/kcl/kcl_device.h | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) create mode 100644 include/kcl/kcl_device.h diff --git a/include/kcl/kcl_device.h b/include/kcl/kcl_device.h new file mode 100644 index 0000000000000..41e786bc632fb --- /dev/null +++ b/include/kcl/kcl_device.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_DEVICE_H +#define AMDKCL_DEVICE_H + +/* Copied from include/linux/dev_printk.h */ +#if !defined(dev_err_once) +#ifdef CONFIG_PRINTK +#define dev_level_once(dev_level, dev, fmt, ...) \ +do { \ + static bool __print_once __read_mostly; \ + \ + if (!__print_once) { \ + __print_once = true; \ + dev_level(dev, fmt, ##__VA_ARGS__); \ + } \ +} while (0) +#else +#define dev_level_once(dev_level, dev, fmt, ...) \ +do { \ + if (0) \ + dev_level(dev, fmt, ##__VA_ARGS__); \ +} while (0) +#endif + +#define dev_err_once(dev, fmt, ...) \ + dev_level_once(dev_err, dev, fmt, ##__VA_ARGS__) +#endif +#endif /* AMDKCL_DEVICE_H */ From 1d83bf600038e7f58eb75880c2b7b8cda59b9d91 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Sat, 12 Oct 2019 10:34:57 +0800 Subject: [PATCH 0122/1868] drm/amdkcl: check whether dev_err_ratelimited() is available Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang Signed-off-by: Yifan Zhang --- include/kcl/kcl_device.h | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/include/kcl/kcl_device.h b/include/kcl/kcl_device.h index 41e786bc632fb..d8d3ee5263d06 100644 --- a/include/kcl/kcl_device.h +++ b/include/kcl/kcl_device.h @@ -2,7 +2,8 @@ #ifndef AMDKCL_DEVICE_H #define AMDKCL_DEVICE_H -/* Copied from include/linux/dev_printk.h */ +#include + #if !defined(dev_err_once) #ifdef CONFIG_PRINTK #define dev_level_once(dev_level, dev, fmt, ...) \ @@ -25,4 +26,18 @@ do { \ #define dev_err_once(dev, fmt, ...) \ dev_level_once(dev_err, dev, fmt, ##__VA_ARGS__) #endif + +#if !defined(dev_err_ratelimited) +#define dev_level_ratelimited(dev_level, dev, fmt, ...) \ +do { \ + static DEFINE_RATELIMIT_STATE(_rs, \ + DEFAULT_RATELIMIT_INTERVAL, \ + DEFAULT_RATELIMIT_BURST); \ + if (__ratelimit(&_rs)) \ + dev_level(dev, fmt, ##__VA_ARGS__); \ +} while (0) + +#define dev_err_ratelimited(dev, fmt, ...) \ + dev_level_ratelimited(dev_err, dev, fmt, ##__VA_ARGS__) +#endif #endif /* AMDKCL_DEVICE_H */ From 28473b6e831f113912eb7e665595e23a174cb872 Mon Sep 17 00:00:00 2001 From: chen gong Date: Thu, 6 Jun 2019 16:24:01 +0800 Subject: [PATCH 0123/1868] drm/amdkcl: Test whether dev_pm_set_driver_flags() is available v2: fake dev_pm_set_driver_flags() Signed-off-by: chen gong Reviewed-by: Slava Grigorev Signed-off-by: Yifan Zhang Signed-off-by: Jack Gui Signed-off-by: Flora Cui Reviewed-by: Jiansong Chen Signed-off-by: Yifan Zhang --- .../drm/amd/dkms/m4/dev-pm-set-driver-flags.m4 | 18 ++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_device.h | 15 +++++++++++++++ 3 files changed, 34 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/dev-pm-set-driver-flags.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/dev-pm-set-driver-flags.m4 b/drivers/gpu/drm/amd/dkms/m4/dev-pm-set-driver-flags.m4 new file mode 100644 index 0000000000000..d1fba526e26d1 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dev-pm-set-driver-flags.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit v4.14-rc4-21-g08810a4119aa +dnl # Author: Rafael J. Wysocki +dnl # Date: Wed Oct 25 14:12:29 2017 +0200 +dnl # PM / core: Add NEVER_SKIP and SMART_PREPARE driver flags +dnl # +AC_DEFUN([AC_AMDGPU_DEV_PM_SET_DRIVER_FLAGS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + dev_pm_set_driver_flags(NULL, 1); + ], [ + AC_DEFINE(HAVE_DEV_PM_SET_DRIVER_FLAGS, 1, + [dev_pm_set_driver_flags() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 42eb904bcfbf9..b431ffea2542b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -14,6 +14,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_I2C_NEW_CLIENT_DEVICE AC_AMDGPU_REQUEST_FIRMWARE_DIRECT AC_AMDGPU_BACKLIGHT_DEVICE_SET_BRIGHTNESS + AC_AMDGPU_DEV_PM_SET_DRIVER_FLAGS AC_AMDGPU_COMPAT_PTR_IOCTL AC_AMDGPU_KTHREAD_PARK_XX AC_AMDGPU___KTHREAD_SHOULD_PARK diff --git a/include/kcl/kcl_device.h b/include/kcl/kcl_device.h index d8d3ee5263d06..078622c69af21 100644 --- a/include/kcl/kcl_device.h +++ b/include/kcl/kcl_device.h @@ -3,6 +3,7 @@ #define AMDKCL_DEVICE_H #include +#include #if !defined(dev_err_once) #ifdef CONFIG_PRINTK @@ -40,4 +41,18 @@ do { \ #define dev_err_ratelimited(dev, fmt, ...) \ dev_level_ratelimited(dev_err, dev, fmt, ##__VA_ARGS__) #endif + +#if !defined(HAVE_DEV_PM_SET_DRIVER_FLAGS) +/* rhel7.7 wrap macro dev_pm_set_driver_flags in drm/drm_backport.h */ +#ifdef dev_pm_set_driver_flags +#undef dev_pm_set_driver_flags +#endif +#define DPM_FLAG_NEVER_SKIP BIT(0) +#define DPM_FLAG_SMART_PREPARE BIT(1) +static inline void dev_pm_set_driver_flags(struct device *dev, u32 flags) +{ + printk_once(KERN_WARNING "%s is not available\n", __func__); +} +#endif + #endif /* AMDKCL_DEVICE_H */ From e6c279c1622bef10bd5959cc8b77fd7b90387ca1 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 11 Oct 2019 13:02:02 +0800 Subject: [PATCH 0124/1868] drm/amdkcl: test whether in_compat_syscall exists in_compat_syscall() is introduced in v4.5-11126-g5180e3e24fd3("compat: add in_compat_syscall to ask whether we're in a compat syscall") macro in_compat_syscall in arch/x86 is introduced in v4.5-11141-gf970165beeaa("x86/compat: remove is_compat_task()") macro in_compat_syscall in include/linux/compat.h is introduced in v4.19-7730-ga846446b1914("x86/compat: Adjust in_compat_syscall() to generic code under !COMPAT") v1: 1c0e722ee1bf drm/amdkcl: [KFD] ALL in One KFD KCL Fix for 4.18 rebase v2: 1f0b1b8c91b5 drm/amd/autoconf: test whether in_compat_syscall exists v3: d37f1868c1b5 drm/amdkcl: refactor test for in_compat_syscall v4: c1f004d6344b drm/amdkcl: fix license for kcl part Signed-off-by: Kevin Wang Signed-off-by: Yifan Zhang Signed-off-by: Flora Cui Reviewed-by: Junwei Zhang Reviewed-by: Harish Kasiviswanathan Reviewed-by: Feifei Xu Signed-off-by: Yifan Zhang Signed-off-by: Flora Cui Acked-by: Feifei Xu Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/dkms/m4/in-compat-syscall.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_compat.h | 15 +++++++++++++++ 3 files changed, 32 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/in-compat-syscall.m4 create mode 100644 include/kcl/kcl_compat.h diff --git a/drivers/gpu/drm/amd/dkms/m4/in-compat-syscall.m4 b/drivers/gpu/drm/amd/dkms/m4/in-compat-syscall.m4 new file mode 100644 index 0000000000000..45f413011ba01 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/in-compat-syscall.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v4.5-11126-g5180e3e24fd3 +dnl # compat: add in_compat_syscall to ask whether we're in a compat syscall +dnl # +AC_DEFUN([AC_AMDGPU_IN_COMPAT_SYSCALL], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + in_compat_syscall(); + ],[ + AC_DEFINE(HAVE_IN_COMPAT_SYSCALL, 1, + [in_compat_syscall is defined]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index b431ffea2542b..bc63d79ad4b08 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -22,6 +22,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_LIST_IS_FIRST AC_AMDGPU_ARCH_IO_RESERVE_FREE_MEMTYPE_WC AC_AMDGPU_ACCESS_OK_WITH_TWO_ARGUMENTS + AC_AMDGPU_IN_COMPAT_SYSCALL AC_AMDGPU_PERF_EVENT_UPDATE_USERPAGE AC_AMDGPU_KSYS_SYNC_HELPER AC_AMDGPU_PCIE_GET_SPEED_AND_WIDTH_CAP diff --git a/include/kcl/kcl_compat.h b/include/kcl/kcl_compat.h new file mode 100644 index 0000000000000..80bcd236bd4de --- /dev/null +++ b/include/kcl/kcl_compat.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_COMPATE_H +#define AMDKCL_COMPATE_H + +#include + +#if !defined(HAVE_IN_COMPAT_SYSCALL) +#ifdef CONFIG_COMPAT +static inline bool in_compat_syscall(void) { return is_compat_task(); } +#else +static inline bool in_compat_syscall(void) { return false; } +#endif +#endif + +#endif /* AMDKCL_COMPATE_H */ From 765b15957894607bec873fb4900480035cd000ac Mon Sep 17 00:00:00 2001 From: Chengming Gui Date: Tue, 27 Aug 2019 14:37:02 +0800 Subject: [PATCH 0125/1868] drm/amdkcl: Test whether seq_hex_dump() is available (v2) seq_hex_dump() introduced by kernel v4.3-rc1~22^2~26 v2: fix typo, autconf --> autoconf v3: c1f004d6344b drm/amdkcl: fix license for kcl part Signed-off-by: Chengming Gui Reviewed-by: Flora Cui Signed-off-by: Jack Gui drm/amdkcl: add kcl copy of seq_hex_dump Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang Reviewed-by: Felix Kuehling Change-Id: I040b0b311b0fb9ab81ed32ef57f94407bdffa013 --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_seq_file.c | 57 +++++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/seq-hex-dump.m4 | 16 ++++++ include/kcl/kcl_seq_file.h | 17 +++++- 5 files changed, 91 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_seq_file.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/seq-hex-dump.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index dc2f9b9255877..fa37dcffda9fb 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -5,7 +5,7 @@ amdkcl-y += kcl_kernel_params.o amdkcl-y += dma-buf/dma-resv.o amdkcl-y += kcl_backlight.o kcl_ioctl.o \ - kcl_kthread.o kcl_io.o kcl_perf_event.o \ + kcl_kthread.o kcl_io.o kcl_perf_event.o kcl_seq_file.o\ kcl_suspend.o kcl_pci.o kcl_mm.o \ kcl_fence.o kcl_fence_array.o kcl_reservation.o kcl_drm_cache.o \ kcl_drm_fb.o kcl_drm_print.o kcl_fbmem.o \ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_seq_file.c b/drivers/gpu/drm/amd/amdkcl/kcl_seq_file.c new file mode 100644 index 0000000000000..725ca1cafbfc8 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_seq_file.c @@ -0,0 +1,57 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * linux/fs/seq_file.c + * + * helper functions for making synthetic files from sequences of records. + * initial implementation -- AV, Oct 2001. + */ +#include + +/* Copied from fs/seq_file.c */ +#ifndef HAVE_SEQ_HEX_DUMP +static void seq_set_overflow(struct seq_file *m) +{ + m->count = m->size; +} + +/* A complete analogue of print_hex_dump() */ +void _kcl_seq_hex_dump(struct seq_file *m, const char *prefix_str, int prefix_type, + int rowsize, int groupsize, const void *buf, size_t len, + bool ascii) +{ + const u8 *ptr = buf; + int i, linelen, remaining = len; + int ret; + + if (rowsize != 16 && rowsize != 32) + rowsize = 16; + + for (i = 0; i < len && !seq_has_overflowed(m); i += rowsize) { + linelen = min(remaining, rowsize); + remaining -= rowsize; + + switch (prefix_type) { + case DUMP_PREFIX_ADDRESS: + seq_printf(m, "%s%p: ", prefix_str, ptr + i); + break; + case DUMP_PREFIX_OFFSET: + seq_printf(m, "%s%.8x: ", prefix_str, i); + break; + default: + seq_printf(m, "%s", prefix_str); + break; + } + + ret = hex_dump_to_buffer(ptr + i, linelen, rowsize, groupsize, + m->buf + m->count, m->size - m->count, + ascii); + if (ret >= m->size - m->count) { + seq_set_overflow(m); + } else { + m->count += ret; + seq_putc(m, '\n'); + } + } +} +EXPORT_SYMBOL(_kcl_seq_hex_dump); +#endif diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index bc63d79ad4b08..9056ca9df5291 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -24,6 +24,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_ACCESS_OK_WITH_TWO_ARGUMENTS AC_AMDGPU_IN_COMPAT_SYSCALL AC_AMDGPU_PERF_EVENT_UPDATE_USERPAGE + AC_AMDGPU_SEQ_HEX_DUMP AC_AMDGPU_KSYS_SYNC_HELPER AC_AMDGPU_PCIE_GET_SPEED_AND_WIDTH_CAP AC_AMDGPU_KTIME_GET_BOOTTIME_NS diff --git a/drivers/gpu/drm/amd/dkms/m4/seq-hex-dump.m4 b/drivers/gpu/drm/amd/dkms/m4/seq-hex-dump.m4 new file mode 100644 index 0000000000000..5765baa40af2d --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/seq-hex-dump.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit 37607102c4426cf92aeb5da1b1d9a79ba6d95e3f +dnl # seq_file: provide an analogue of print_hex_dump() +dnl # +AC_DEFUN([AC_AMDGPU_SEQ_HEX_DUMP], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + seq_hex_dump(NULL,NULL,0,0,0,NULL,0,0); + ], [seq_hex_dump],[fs/seq_file.c], [ + AC_DEFINE(HAVE_SEQ_HEX_DUMP, 1, + [seq_hex_dump() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_seq_file.h b/include/kcl/kcl_seq_file.h index 4e7750f341705..b884645a14388 100644 --- a/include/kcl/kcl_seq_file.h +++ b/include/kcl/kcl_seq_file.h @@ -1,7 +1,10 @@ -/* SPDX-License-Identifier: MIT */ +/* SPDX-License-Identifier: GPL-2.0 */ #ifndef AMDKCL_SEQ_FILE_H #define AMDKCL_SEQ_FILE_H +#include + +/* Copied from linux/seq_file.h */ #ifndef DEFINE_SHOW_ATTRIBUTE #define DEFINE_SHOW_ATTRIBUTE(__name) \ static int __name ## _open(struct inode *inode, struct file *file) \ @@ -18,4 +21,16 @@ static const struct file_operations __name ## _fops = { \ } #endif +#ifndef HAVE_SEQ_HEX_DUMP +void _kcl_seq_hex_dump(struct seq_file *m, const char *prefix_str, int prefix_type, + int rowsize, int groupsize, const void *buf, size_t len, + bool ascii); + +static inline void seq_hex_dump(struct seq_file *m, const char *prefix_str, int prefix_type, + int rowsize, int groupsize, const void *buf, size_t len, + bool ascii) +{ + _kcl_seq_hex_dump(m, prefix_str, prefix_type, rowsize, groupsize, buf, len, ascii); +} +#endif #endif From bf367721a19299691809014d8c9d94210aaac330 Mon Sep 17 00:00:00 2001 From: Anatoli Antonovitch Date: Thu, 6 Jun 2019 15:58:38 -0400 Subject: [PATCH 0126/1868] drm/amdkcl: Test whether pci_enable_atomic_ops_to_root() is available Signed-off-by: Anatoli Antonovitch Reviewed-by: Flora Cui Signed-off-by: Jack Gui Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/kcl_pci.c | 87 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../dkms/m4/pcie-enable-atomic-ops-to-root.m4 | 18 ++++ include/kcl/kcl_pci.h | 9 ++ 4 files changed, 115 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/pcie-enable-atomic-ops-to-root.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_pci.c b/drivers/gpu/drm/amd/amdkcl/kcl_pci.c index 3068db5234542..ff2cfbce1e93d 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_pci.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_pci.c @@ -97,3 +97,90 @@ void amdkcl_pci_init(void) _kcl_pcie_get_width_cap = amdkcl_fp_setup("pcie_get_width_cap", pcie_get_width_cap); #endif } + +#if !defined(HAVE_PCIE_ENABLE_ATOMIC_OPS_TO_ROOT) +/** + * pci_enable_atomic_ops_to_root - enable AtomicOp requests to root port + * @dev: the PCI device + * @comp_caps: Caps required for atomic request completion + * + * Return 0 if all upstream bridges support AtomicOp routing, egress + * blocking is disabled on all upstream ports, and the root port + * supports the requested completion capabilities (32-bit, 64-bit + * and/or 128-bit AtomicOp completion), or negative otherwise. + * + */ +int _kcl_pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 comp_caps) +{ + struct pci_bus *bus = dev->bus; + + if (!pci_is_pcie(dev)) + return -EINVAL; + + switch (pci_pcie_type(dev)) { + /* + * PCIe 3.0, 6.15 specifies that endpoints and root ports are permitted + * to implement AtomicOp requester capabilities. + */ + case PCI_EXP_TYPE_ENDPOINT: + case PCI_EXP_TYPE_LEG_END: + case PCI_EXP_TYPE_RC_END: + break; + default: + return -EINVAL; + } + + while (bus->parent) { + struct pci_dev *bridge = bus->self; + u32 cap; + + pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap); + + switch (pci_pcie_type(bridge)) { + /* + * Upstream, downstream and root ports may implement AtomicOp + * routing capabilities. AtomicOp routing via a root port is + * not considered. + */ + case PCI_EXP_TYPE_UPSTREAM: + case PCI_EXP_TYPE_DOWNSTREAM: + if (!(cap & PCI_EXP_DEVCAP2_ATOMIC_ROUTE)) + return -EINVAL; + break; + + /* + * Root ports are permitted to implement AtomicOp completion + * capabilities. + */ + case PCI_EXP_TYPE_ROOT_PORT: + if ((cap & comp_caps) != comp_caps) + return -EINVAL; + break; + } + + /* + * Upstream ports may block AtomicOps on egress. + */ +#if defined(OS_NAME_RHEL_6) + if (pci_pcie_type(bridge) == PCI_EXP_TYPE_DOWNSTREAM) { +#else + if (!bridge->has_secondary_link) { +#endif + u32 ctl2; + + pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2, + &ctl2); + if (ctl2 & PCI_EXP_DEVCTL2_ATOMIC_BLOCK) + return -EINVAL; + } + + bus = bus->parent; + } + + pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, + PCI_EXP_DEVCTL2_ATOMIC_REQ); + + return 0; +} +EXPORT_SYMBOL(_kcl_pci_enable_atomic_ops_to_root); +#endif diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 9056ca9df5291..c5c1f79dbcaab 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -27,6 +27,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_SEQ_HEX_DUMP AC_AMDGPU_KSYS_SYNC_HELPER AC_AMDGPU_PCIE_GET_SPEED_AND_WIDTH_CAP + AC_AMDGPU_PCIE_ENABLE_ATOMIC_OPS_TO_ROOT AC_AMDGPU_KTIME_GET_BOOTTIME_NS AC_AMDGPU_MMU_NOTIFIER AC_AMDGPU_MM_RELEASE_PAGES diff --git a/drivers/gpu/drm/amd/dkms/m4/pcie-enable-atomic-ops-to-root.m4 b/drivers/gpu/drm/amd/dkms/m4/pcie-enable-atomic-ops-to-root.m4 new file mode 100644 index 0000000000000..fe1539a268b96 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pcie-enable-atomic-ops-to-root.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit 430a23689dea2e36ae5a0fc75a67301fd46b18bf +dnl # Author: Jay Cornwall +dnl # Date: Thu Jan 4 19:44:59 2018 -0500 +dnl # PCI: Add pci_enable_atomic_ops_to_root() +dnl # +AC_DEFUN([AC_AMDGPU_PCIE_ENABLE_ATOMIC_OPS_TO_ROOT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + pci_enable_atomic_ops_to_root(NULL, 0); + ], [pci_enable_atomic_ops_to_root], [drivers/pci/pci.c], [ + AC_DEFINE(HAVE_PCIE_ENABLE_ATOMIC_OPS_TO_ROOT, 1, + [pci_enable_atomic_ops_to_root() exist]) + ]) + ]) +]) diff --git a/include/kcl/kcl_pci.h b/include/kcl/kcl_pci.h index f6f8425cea3b6..f2d5f416c42cc 100644 --- a/include/kcl/kcl_pci.h +++ b/include/kcl/kcl_pci.h @@ -49,4 +49,13 @@ static inline enum pcie_link_width kcl_pcie_get_width_cap(struct pci_dev *dev) #endif } +#if !defined(HAVE_PCIE_ENABLE_ATOMIC_OPS_TO_ROOT) +int _kcl_pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 comp_caps); +static inline +int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask) +{ + return _kcl_pci_enable_atomic_ops_to_root(dev, cap_mask); +} +#endif + #endif /* AMDKCL_PCI_H */ From b3bf91ac575c1e03b2118b48c40e82f2a794de8c Mon Sep 17 00:00:00 2001 From: changzhu Date: Mon, 11 Feb 2019 18:10:17 +0800 Subject: [PATCH 0127/1868] drm/amdkcl: Test whether pci_upstream_bridge() is available drm/amdkcl: [3.13] fix implicit declaration of pci_upstream_bridge error [Why] pci_upstream_bridge is not defined before kernel_version(3,13,0). So there is build error when using pci_upstream_bridge in function amdgpu_device_get_min_pci_speed_width(amdgpu_device.c) on redhat 6.10. This kcl patch is for patch: drm/amdgpu: Fix pci platform speed and width [How] Define pci_upstream_bridge in kcl_pci.h when kernel_version<3,13,0. Besides,pci_upstream_bridge is defined on redhat 7.6,although the kernel_version of redha 7.6 is 3.10.0. So we need to use to complete the definition of pci_upstream_bridge. Change-Id: I686d3ad551159a23b28dfc02ed7a4781b053770a Signed-off-by: changzhu Reviewed-by: Rui Teng Signed-off-by: Jack Gui drm/amdkcl: Test whether pci_upstream_bridge() is available Change-Id: I7c0373d0151f6291a188096c299c7c1143c85eaf Signed-off-by: chen gong Reviewed-by: Anatoli Antonovitch Cherry-picked-by: Jack Gui Reviewed-by: Flora Cui Signed-off-by: Jack Gui --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../gpu/drm/amd/dkms/m4/pci-upstream-bridge.m4 | 18 ++++++++++++++++++ include/kcl/kcl_pci.h | 10 ++++++++++ 3 files changed, 29 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/pci-upstream-bridge.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index c5c1f79dbcaab..90063d75cf386 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -28,6 +28,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_KSYS_SYNC_HELPER AC_AMDGPU_PCIE_GET_SPEED_AND_WIDTH_CAP AC_AMDGPU_PCIE_ENABLE_ATOMIC_OPS_TO_ROOT + AC_AMDGPU_PCI_UPSTREAM_BRIDGE AC_AMDGPU_KTIME_GET_BOOTTIME_NS AC_AMDGPU_MMU_NOTIFIER AC_AMDGPU_MM_RELEASE_PAGES diff --git a/drivers/gpu/drm/amd/dkms/m4/pci-upstream-bridge.m4 b/drivers/gpu/drm/amd/dkms/m4/pci-upstream-bridge.m4 new file mode 100644 index 0000000000000..7d8e48fd14555 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pci-upstream-bridge.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit c6bde215acfd637708142ae671843b6f0eadbc6d +dnl # Author: Bjorn Helgaas +dnl # Date: Wed Nov 6 10:11:48 2013 -0700 +dnl # PCI: Add pci_upstream_bridge() +dnl # +AC_DEFUN([AC_AMDGPU_PCI_UPSTREAM_BRIDGE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + pci_upstream_bridge(NULL); + ], [ + AC_DEFINE(HAVE_PCI_UPSTREAM_BRIDGE, 1, + [pci_upstream_bridge() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_pci.h b/include/kcl/kcl_pci.h index f2d5f416c42cc..8f63e4d16c4f6 100644 --- a/include/kcl/kcl_pci.h +++ b/include/kcl/kcl_pci.h @@ -58,4 +58,14 @@ int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask) } #endif +#if !defined(HAVE_PCI_UPSTREAM_BRIDGE) +static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev) +{ + dev = pci_physfn(dev); + if (pci_is_root_bus(dev->bus)) + return NULL; + + return dev->bus->self; +} +#endif #endif /* AMDKCL_PCI_H */ From f55a00ec3b09346891b65d0ff134ad694e478507 Mon Sep 17 00:00:00 2001 From: Amber Lin Date: Mon, 13 May 2019 15:51:11 -0400 Subject: [PATCH 0128/1868] drm/amdkcl: Test whether pcie_bandwidth_available is available Add pcie_bandwidth_available() into autoconf test whether it's available in the kernel. Signed-off-by: Amber Lin Reviewed-by: Slava Grigorev Cherry-picked-by: Jack Gui Reviewed-by: Flora Cui Signed-off-by: Jack Gui drm/amdkcl: refactore check for pcie_link_speed Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang Signed-off-by: Jack Gui --- drivers/gpu/drm/amd/amdkcl/kcl_pci.c | 86 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../amd/dkms/m4/pcie-bandwidth-available.m4 | 16 ++++ include/kcl/kcl_pci.h | 14 +++ 4 files changed, 117 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/pcie-bandwidth-available.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_pci.c b/drivers/gpu/drm/amd/amdkcl/kcl_pci.c index ff2cfbce1e93d..96e4a0c859c83 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_pci.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_pci.c @@ -20,6 +20,87 @@ #include #include +#if !defined(HAVE_PCIE_BANDWIDTH_AVAILABLE) +const unsigned char *_kcl_pcie_link_speed; + +const unsigned char _kcl_pcie_link_speed_stub[] = { + PCI_SPEED_UNKNOWN, /* 0 */ + PCIE_SPEED_2_5GT, /* 1 */ + PCIE_SPEED_5_0GT, /* 2 */ + PCIE_SPEED_8_0GT, /* 3 */ + PCI_SPEED_UNKNOWN, /* 4 */ + PCI_SPEED_UNKNOWN, /* 5 */ + PCI_SPEED_UNKNOWN, /* 6 */ + PCI_SPEED_UNKNOWN, /* 7 */ + PCI_SPEED_UNKNOWN, /* 8 */ + PCI_SPEED_UNKNOWN, /* 9 */ + PCI_SPEED_UNKNOWN, /* A */ + PCI_SPEED_UNKNOWN, /* B */ + PCI_SPEED_UNKNOWN, /* C */ + PCI_SPEED_UNKNOWN, /* D */ + PCI_SPEED_UNKNOWN, /* E */ + PCI_SPEED_UNKNOWN /* F */ +}; + +/** + * pcie_bandwidth_available - determine minimum link settings of a PCIe + * device and its bandwidth limitation + * @dev: PCI device to query + * @limiting_dev: storage for device causing the bandwidth limitation + * @speed: storage for speed of limiting device + * @width: storage for width of limiting device + * + * Walk up the PCI device chain and find the point where the minimum + * bandwidth is available. Return the bandwidth available there and (if + * limiting_dev, speed, and width pointers are supplied) information about + * that point. The bandwidth returned is in Mb/s, i.e., megabits/second of + * raw bandwidth. + */ +u32 _kcl_pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, + enum pci_bus_speed *speed, + enum pcie_link_width *width) +{ + u16 lnksta; + enum pci_bus_speed next_speed; + enum pcie_link_width next_width; + u32 bw, next_bw; + + if (speed) + *speed = PCI_SPEED_UNKNOWN; + if (width) + *width = PCIE_LNK_WIDTH_UNKNOWN; + + bw = 0; + + while (dev) { + pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); + + next_speed = _kcl_pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS]; + next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >> + PCI_EXP_LNKSTA_NLW_SHIFT; + + next_bw = next_width * PCIE_SPEED2MBS_ENC(next_speed); + + /* Check if current device limits the total bandwidth */ + if (!bw || next_bw <= bw) { + bw = next_bw; + + if (limiting_dev) + *limiting_dev = dev; + if (speed) + *speed = next_speed; + if (width) + *width = next_width; + } + + dev = pci_upstream_bridge(dev); + } + + return bw; +} +EXPORT_SYMBOL(_kcl_pcie_bandwidth_available); +#endif /* HAVE_PCIE_BANDWIDTH_AVAILABLE */ + #if !defined(HAVE_PCIE_GET_SPEED_AND_WIDTH_CAP) /* * pcie_get_speed_cap - query for the PCI device's link speed capability @@ -96,6 +177,9 @@ void amdkcl_pci_init(void) _kcl_pcie_get_speed_cap = amdkcl_fp_setup("pcie_get_speed_cap", pcie_get_speed_cap); _kcl_pcie_get_width_cap = amdkcl_fp_setup("pcie_get_width_cap", pcie_get_width_cap); #endif +#if !defined(HAVE_PCIE_BANDWIDTH_AVAILABLE) + _kcl_pcie_link_speed = (const unsigned char *) amdkcl_fp_setup("pcie_link_speed", _kcl_pcie_link_speed_stub); +#endif } #if !defined(HAVE_PCIE_ENABLE_ATOMIC_OPS_TO_ROOT) @@ -184,3 +268,5 @@ int _kcl_pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 comp_caps) } EXPORT_SYMBOL(_kcl_pci_enable_atomic_ops_to_root); #endif + + diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 90063d75cf386..0de158e8179fa 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -29,6 +29,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_PCIE_GET_SPEED_AND_WIDTH_CAP AC_AMDGPU_PCIE_ENABLE_ATOMIC_OPS_TO_ROOT AC_AMDGPU_PCI_UPSTREAM_BRIDGE + AC_AMDGPU_PCIE_BANDWIDTH_AVAILABLE AC_AMDGPU_KTIME_GET_BOOTTIME_NS AC_AMDGPU_MMU_NOTIFIER AC_AMDGPU_MM_RELEASE_PAGES diff --git a/drivers/gpu/drm/amd/dkms/m4/pcie-bandwidth-available.m4 b/drivers/gpu/drm/amd/dkms/m4/pcie-bandwidth-available.m4 new file mode 100644 index 0000000000000..e733ecc72488c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pcie-bandwidth-available.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit 6db79a88c67e4679d9c1e4a3f05c6385e21f6e9a +dnl # PCI: Add pcie_bandwidth_available() to compute bandwidth available to device +dnl # +AC_DEFUN([AC_AMDGPU_PCIE_BANDWIDTH_AVAILABLE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + pcie_bandwidth_available(NULL, NULL, NULL, NULL); + ], [pcie_bandwidth_available], [drivers/pci/pci.c], [ + AC_DEFINE(HAVE_PCIE_BANDWIDTH_AVAILABLE, 1, + [pcie_bandwidth_available() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_pci.h b/include/kcl/kcl_pci.h index 8f63e4d16c4f6..7bf37b2644419 100644 --- a/include/kcl/kcl_pci.h +++ b/include/kcl/kcl_pci.h @@ -68,4 +68,18 @@ static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev) return dev->bus->self; } #endif + +#if !defined(HAVE_PCIE_BANDWIDTH_AVAILABLE) +u32 _kcl_pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, + enum pci_bus_speed *speed, + enum pcie_link_width *width); +static inline +u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, + enum pci_bus_speed *speed, + enum pcie_link_width *width) +{ + return _kcl_pcie_bandwidth_available(dev, limiting_dev, speed, width); +} +#endif + #endif /* AMDKCL_PCI_H */ From ef79d2ca6be60fac293f44935fc2d7ce0119585a Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 13 Sep 2018 15:01:36 +0800 Subject: [PATCH 0129/1868] drm/amdkcl: Enable PCIe Extended Tags if supported commit 60db3a4d8cc9 ("PCI: Enable PCIe Extended Tags if supported") fix rocm bandwidth test H2D case. add the change for kernel < 4.11 v2: export _kcl_pci_configure_extended_tags for dkms support. v3: amd/amdkcl: make sure to enable PCIe Extended Tags if supported Signed-off-by: Flora Cui Reviewed-by: Hawking Zhang Signed-off-by: Slava Grigorev Reviewed-by: Flora Cui Signed-off-by: Yifan Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 1 + drivers/gpu/drm/amd/amdkcl/kcl_pci.c | 27 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../dkms/m4/pci-configure-extended-tags.m4 | 17 ++++++++++++ include/kcl/kcl_pci.h | 11 ++++++++ 5 files changed, 57 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/pci-configure-extended-tags.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index b9bab30caa66a..053200a25fa24 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2305,6 +2305,7 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, if (!supports_atomic) ddev->driver_features &= ~DRIVER_ATOMIC; + kcl_pci_configure_extended_tags(pdev); ret = pci_enable_device(pdev); if (ret) return ret; diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_pci.c b/drivers/gpu/drm/amd/amdkcl/kcl_pci.c index 96e4a0c859c83..bf095e454ed06 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_pci.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_pci.c @@ -269,4 +269,31 @@ int _kcl_pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 comp_caps) EXPORT_SYMBOL(_kcl_pci_enable_atomic_ops_to_root); #endif +#if !defined(HAVE_PCI_CONFIGURE_EXTENDED_TAGS) +void _kcl_pci_configure_extended_tags(struct pci_dev *dev) +{ + u32 cap; + u16 ctl; + int ret; + + if (!pci_is_pcie(dev)) + return; + + ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap); + if (ret) + return; + + if (!(cap & PCI_EXP_DEVCAP_EXT_TAG)) + return; + ret = pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); + if (ret) + return; + + if (!(ctl & PCI_EXP_DEVCTL_EXT_TAG)) { + pcie_capability_set_word(dev, PCI_EXP_DEVCTL, + PCI_EXP_DEVCTL_EXT_TAG); + } +} +EXPORT_SYMBOL(_kcl_pci_configure_extended_tags); +#endif diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 0de158e8179fa..44686641e93b0 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -30,6 +30,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_PCIE_ENABLE_ATOMIC_OPS_TO_ROOT AC_AMDGPU_PCI_UPSTREAM_BRIDGE AC_AMDGPU_PCIE_BANDWIDTH_AVAILABLE + AC_AMDGPU_PCI_CONFIGURE_EXTENDED_TAGS AC_AMDGPU_KTIME_GET_BOOTTIME_NS AC_AMDGPU_MMU_NOTIFIER AC_AMDGPU_MM_RELEASE_PAGES diff --git a/drivers/gpu/drm/amd/dkms/m4/pci-configure-extended-tags.m4 b/drivers/gpu/drm/amd/dkms/m4/pci-configure-extended-tags.m4 new file mode 100644 index 0000000000000..c46dfedbf7a34 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pci-configure-extended-tags.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit 62ce94a7a5a54aac80975f5e6731707225d4077e +dnl # PCI: Mark Broadcom HT2100 Root Port Extended Tags as broken +dnl # +AC_DEFUN([AC_AMDGPU_PCI_CONFIGURE_EXTENDED_TAGS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct pci_host_bridge bridge; + bridge.no_ext_tags = 0; + ], [ + AC_DEFINE(HAVE_PCI_CONFIGURE_EXTENDED_TAGS, 1, + [PCI driver handles extended tags]) + ]) + ]) +]) diff --git a/include/kcl/kcl_pci.h b/include/kcl/kcl_pci.h index 7bf37b2644419..a8f30439b39a8 100644 --- a/include/kcl/kcl_pci.h +++ b/include/kcl/kcl_pci.h @@ -82,4 +82,15 @@ u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, } #endif +#if !defined(HAVE_PCI_CONFIGURE_EXTENDED_TAGS) +void _kcl_pci_configure_extended_tags(struct pci_dev *dev); +#endif + +static inline void kcl_pci_configure_extended_tags(struct pci_dev *dev) +{ +#if !defined(HAVE_PCI_CONFIGURE_EXTENDED_TAGS) + _kcl_pci_configure_extended_tags(dev); +#endif +} + #endif /* AMDKCL_PCI_H */ From 7a772e750ae73a615b58e2953b5ceb79620986f3 Mon Sep 17 00:00:00 2001 From: Adam Yang Date: Mon, 23 Sep 2019 17:10:03 +0800 Subject: [PATCH 0130/1868] drm/amdkcl: Test whether pci_dev_id() is available Signed-off-by: Adam Yang Signed-off-by: Jack Gui Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/pci-dev-id.m4 | 16 ++++++++++++++++ include/kcl/kcl_pci.h | 6 ++++++ 3 files changed, 23 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/pci-dev-id.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 44686641e93b0..2d9f1f12aa0f5 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -31,6 +31,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_PCI_UPSTREAM_BRIDGE AC_AMDGPU_PCIE_BANDWIDTH_AVAILABLE AC_AMDGPU_PCI_CONFIGURE_EXTENDED_TAGS + AC_AMDGPU_PCI_DEV_ID AC_AMDGPU_KTIME_GET_BOOTTIME_NS AC_AMDGPU_MMU_NOTIFIER AC_AMDGPU_MM_RELEASE_PAGES diff --git a/drivers/gpu/drm/amd/dkms/m4/pci-dev-id.m4 b/drivers/gpu/drm/amd/dkms/m4/pci-dev-id.m4 new file mode 100644 index 0000000000000..29c0928f6bd40 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pci-dev-id.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit 4e544bac8267f65a0bf06aed1bde9964da4812ed +dnl # PCI: Add pci_dev_id() helper +dnl # +AC_DEFUN([AC_AMDGPU_PCI_DEV_ID], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + pci_dev_id(NULL); + ], [ + AC_DEFINE(HAVE_PCI_DEV_ID, 1, + [pci_dev_id() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_pci.h b/include/kcl/kcl_pci.h index a8f30439b39a8..68246cdd08768 100644 --- a/include/kcl/kcl_pci.h +++ b/include/kcl/kcl_pci.h @@ -93,4 +93,10 @@ static inline void kcl_pci_configure_extended_tags(struct pci_dev *dev) #endif } +#if !defined(HAVE_PCI_DEV_ID) +static inline u16 pci_dev_id(struct pci_dev *dev) +{ + return PCI_DEVID(dev->bus->number, dev->devfn); +} +#endif /* HAVE_PCI_DEV_ID */ #endif /* AMDKCL_PCI_H */ From 4a4f16fe841d26a89e6a5fb831e22746a93a40be Mon Sep 17 00:00:00 2001 From: Chengming Gui Date: Mon, 24 Aug 2020 15:01:34 +0800 Subject: [PATCH 0131/1868] drm/amdkcl: Test whether ktime_get_raw_ns() is available ktime_get_raw_ns introduced by kernel v3.17-rc1~109^2~18 Signed-off-by: Chengming Gui Reviewed-by: Flora Cui Signed-off-by: Jack Gui Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../gpu/drm/amd/dkms/m4/ktime-get-raw-ns.m4 | 18 ++++++++++++++++++ include/kcl/kcl_timekeeping.h | 10 ++++++++++ 3 files changed, 29 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/ktime-get-raw-ns.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 2d9f1f12aa0f5..3eb2dadd86279 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -33,6 +33,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_PCI_CONFIGURE_EXTENDED_TAGS AC_AMDGPU_PCI_DEV_ID AC_AMDGPU_KTIME_GET_BOOTTIME_NS + AC_AMDGPU_KTIME_GET_RAW_NS AC_AMDGPU_MMU_NOTIFIER AC_AMDGPU_MM_RELEASE_PAGES AC_AMDGPU_DMA_FENCE_HEADERS diff --git a/drivers/gpu/drm/amd/dkms/m4/ktime-get-raw-ns.m4 b/drivers/gpu/drm/amd/dkms/m4/ktime-get-raw-ns.m4 new file mode 100644 index 0000000000000..e6ae5ff3a6fe0 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/ktime-get-raw-ns.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit v3.16-rc5-99-gf519b1a2e08c +dnl # timekeeping: Provide ktime_get_raw() +dnl # Provide a ktime_t based interface for raw monotonic time. +dnl # +AC_DEFUN([AC_AMDGPU_KTIME_GET_RAW_NS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + ktime_get_raw_ns(); + ], [ + AC_DEFINE(HAVE_KTIME_GET_RAW_NS, 1, + [ktime_get_raw_ns is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_timekeeping.h b/include/kcl/kcl_timekeeping.h index cddc7d78548af..add67d130b167 100644 --- a/include/kcl/kcl_timekeeping.h +++ b/include/kcl/kcl_timekeeping.h @@ -27,4 +27,14 @@ static inline u64 ktime_get_boottime_ns(void) #endif /* HAVE_KTIME_GET_NS */ #endif /* HAVE_KTIME_GET_BOOTTIME_NS */ +#if !defined(HAVE_KTIME_GET_RAW_NS) +static inline u64 ktime_get_raw_ns(void) +{ + struct timespec time; + + getrawmonotonic(&time); + return (u64)timespec_to_ns(&time); +} +#endif + #endif From 9ed2581e1e4656957f37e87416f349efcba5244d Mon Sep 17 00:00:00 2001 From: Chengming Gui Date: Thu, 19 Sep 2019 16:35:57 +0800 Subject: [PATCH 0132/1868] drm/amdkcl: Test whether ktime_get_real_seconds is available Introduced by kernel v3.19-rc1~153^2 Change-Id: I4fb478b1e84247fb839073fed4cce9ae1a91e06c Signed-off-by: Chengming Gui Reviewed-by: Flora Cui Signed-off-by: Flora Cui Reviewed-by: Feifei Xu Signed-off-by: Jack Gui --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../drm/amd/dkms/m4/ktime-get-real-seconds.m4 | 34 +++++++++++++++++++ include/kcl/kcl_timekeeping.h | 10 ++++++ 3 files changed, 45 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/ktime-get-real-seconds.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 3eb2dadd86279..9e93a78cdd592 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -34,6 +34,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_PCI_DEV_ID AC_AMDGPU_KTIME_GET_BOOTTIME_NS AC_AMDGPU_KTIME_GET_RAW_NS + AC_AMDGPU_KTIME_GET_REAL_SECONDS AC_AMDGPU_MMU_NOTIFIER AC_AMDGPU_MM_RELEASE_PAGES AC_AMDGPU_DMA_FENCE_HEADERS diff --git a/drivers/gpu/drm/amd/dkms/m4/ktime-get-real-seconds.m4 b/drivers/gpu/drm/amd/dkms/m4/ktime-get-real-seconds.m4 new file mode 100644 index 0000000000000..53fe6c0af4523 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/ktime-get-real-seconds.m4 @@ -0,0 +1,34 @@ +dnl # +dnl # commit dbe7aa622db96b5cd601f59d09c4f00b98b76079 +dnl # timekeeping: Provide y2038 safe accessor to the seconds portion of CLOCK_REALTIME +dnl # +AC_DEFUN([AC_AMDGPU_KTIME_GET_REAL_SECONDS_REAL], [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + #include + ],[ + ktime_get_real_seconds(); + ],[ktime_get_real_seconds],[kernel/time/timekeeping.c],[ + AC_DEFINE(HAVE_KTIME_GET_REAL_SECONDS, 1, + [ktime_get_real_seconds() is available]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_KTIME_GET_REAL_SECONDS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drm_backport.h], [ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + ktime_get_real_seconds(); + ], [ + AC_DEFINE(HAVE_KTIME_GET_REAL_SECONDS, 1, + [ktime_get_real_seconds() is available in drm_backport.h]) + ], [ + AC_AMDGPU_KTIME_GET_REAL_SECONDS_REAL + ]) + ], [ + AC_AMDGPU_KTIME_GET_REAL_SECONDS_REAL + ]) + ]) +]) diff --git a/include/kcl/kcl_timekeeping.h b/include/kcl/kcl_timekeeping.h index add67d130b167..95378dc3e862b 100644 --- a/include/kcl/kcl_timekeeping.h +++ b/include/kcl/kcl_timekeeping.h @@ -38,3 +38,13 @@ static inline u64 ktime_get_raw_ns(void) #endif #endif + +#ifndef HAVE_KTIME_GET_REAL_SECONDS +static inline time64_t ktime_get_real_seconds(void) +{ + struct timeval ts; + + do_gettimeofday(&ts); + return (time64_t)ts.tv_sec; +} +#endif From 3b6951a5e719838583ac375226d2e9ccd4659fb6 Mon Sep 17 00:00:00 2001 From: Jiansong Chen Date: Thu, 7 May 2020 18:00:20 +0800 Subject: [PATCH 0133/1868] drm/amdkcl: add kcl for ktime_get_mono_fast_ns It is introduced in v3.17-rc1, and not available for CentOS7.3 kernel. Now a compromised implementation is added to overcome build issue. Change-Id: Ie04c15f45aeb44a721b573303e1afcd368fe9c0b Signed-off-by: Jiansong Chen Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/ktime-get-fast-ns.m4 | 16 ++++++++++++++++ include/kcl/kcl_timekeeping.h | 11 +++++++++-- 3 files changed, 26 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/ktime-get-fast-ns.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 9e93a78cdd592..387246b62bfb3 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -35,6 +35,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_KTIME_GET_BOOTTIME_NS AC_AMDGPU_KTIME_GET_RAW_NS AC_AMDGPU_KTIME_GET_REAL_SECONDS + AC_AMDGPU_KTIME_GET_FAST_NS AC_AMDGPU_MMU_NOTIFIER AC_AMDGPU_MM_RELEASE_PAGES AC_AMDGPU_DMA_FENCE_HEADERS diff --git a/drivers/gpu/drm/amd/dkms/m4/ktime-get-fast-ns.m4 b/drivers/gpu/drm/amd/dkms/m4/ktime-get-fast-ns.m4 new file mode 100644 index 0000000000000..9e7158950fcbb --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/ktime-get-fast-ns.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v3.16-rc5-111-g4396e058c52e +dnl # timekeeping: Provide fast and NMI safe access to CLOCK_MONOTONIC +dnl # +AC_DEFUN([AC_AMDGPU_KTIME_GET_FAST_NS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + ktime_get_mono_fast_ns(); + ], [ + AC_DEFINE(HAVE_KTIME_GET_MONO_FAST_NS, 1, + [ktime_get_mono_fast_ns is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_timekeeping.h b/include/kcl/kcl_timekeeping.h index 95378dc3e862b..7c5bd5b28cb65 100644 --- a/include/kcl/kcl_timekeeping.h +++ b/include/kcl/kcl_timekeeping.h @@ -37,8 +37,6 @@ static inline u64 ktime_get_raw_ns(void) } #endif -#endif - #ifndef HAVE_KTIME_GET_REAL_SECONDS static inline time64_t ktime_get_real_seconds(void) { @@ -48,3 +46,12 @@ static inline time64_t ktime_get_real_seconds(void) return (time64_t)ts.tv_sec; } #endif + +#if !defined(HAVE_KTIME_GET_MONO_FAST_NS) +static inline u64 ktime_get_mono_fast_ns(void) +{ + return ktime_to_ns(ktime_get()); +} +#endif + +#endif From 02183013283744af034bc5862aa5d7442f5766fc Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 11 Oct 2023 16:43:38 +0800 Subject: [PATCH 0134/1868] drm/amdkcl: Test whether memalloc_nofs_{save/restore}() are available Signed-off-by: Slava Grigorev Signed-off-by: Yifan Zhang Signed-off-by: Jack Gui Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../gpu/drm/amd/dkms/m4/memalloc-nofs-save.m4 | 17 +++++++++++++++++ include/kcl/kcl_mm.h | 11 +++++++++++ 3 files changed, 29 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/memalloc-nofs-save.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 387246b62bfb3..ebcca8071fd0e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -36,6 +36,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_KTIME_GET_RAW_NS AC_AMDGPU_KTIME_GET_REAL_SECONDS AC_AMDGPU_KTIME_GET_FAST_NS + AC_AMDGPU_MEMALLOC_NOFS_SAVE AC_AMDGPU_MMU_NOTIFIER AC_AMDGPU_MM_RELEASE_PAGES AC_AMDGPU_DMA_FENCE_HEADERS diff --git a/drivers/gpu/drm/amd/dkms/m4/memalloc-nofs-save.m4 b/drivers/gpu/drm/amd/dkms/m4/memalloc-nofs-save.m4 new file mode 100644 index 0000000000000..64d78a728898d --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/memalloc-nofs-save.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit 7dea19f9ee636cb244109a4dba426bbb3e5304b7 +dnl # mm: introduce memalloc_nofs_{save,restore} API +dnl # +AC_DEFUN([AC_AMDGPU_MEMALLOC_NOFS_SAVE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + memalloc_nofs_save(); + memalloc_nofs_restore(0); + ], [ + AC_DEFINE(HAVE_MEMALLOC_NOFS_SAVE, 1, + [memalloc_nofs_{save,restore}() are available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_mm.h b/include/kcl/kcl_mm.h index f7616dde77031..cd1a3de986863 100644 --- a/include/kcl/kcl_mm.h +++ b/include/kcl/kcl_mm.h @@ -22,4 +22,15 @@ static inline bool fault_flag_allow_retry_first(unsigned int flags) } #endif +#if !defined(HAVE_MEMALLOC_NOFS_SAVE) +static inline unsigned int memalloc_nofs_save(void) +{ + return current->flags; +} + +static inline void memalloc_nofs_restore(unsigned int flags) +{ +} +#endif + #endif /* AMDKCL_MM_H */ From 64701b4579173f5779849cda0e180c9bf2d1adf9 Mon Sep 17 00:00:00 2001 From: chen gong Date: Tue, 4 Jun 2019 16:33:34 +0800 Subject: [PATCH 0135/1868] drm/amdkcl: Test whether zone_managed_pages() is available Signed-off-by: chen gong Reviewed-by: Slava Grigorev Signed-off-by: Yifan Zhang Signed-off-by: Jack Gui Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../gpu/drm/amd/dkms/m4/zone-managed-pages.m4 | 32 +++++++++++++++++++ include/kcl/kcl_mm.h | 13 ++++++++ 3 files changed, 46 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/zone-managed-pages.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index ebcca8071fd0e..238cf6ece6a42 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -37,6 +37,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_KTIME_GET_REAL_SECONDS AC_AMDGPU_KTIME_GET_FAST_NS AC_AMDGPU_MEMALLOC_NOFS_SAVE + AC_AMDGPU_ZONE_MANAGED_PAGES AC_AMDGPU_MMU_NOTIFIER AC_AMDGPU_MM_RELEASE_PAGES AC_AMDGPU_DMA_FENCE_HEADERS diff --git a/drivers/gpu/drm/amd/dkms/m4/zone-managed-pages.m4 b/drivers/gpu/drm/amd/dkms/m4/zone-managed-pages.m4 new file mode 100644 index 0000000000000..a1228bf4f67ac --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/zone-managed-pages.m4 @@ -0,0 +1,32 @@ +dnl # +dnl # commit v4.20-6505-g9705bea5f833 +dnl # Author: Arun KS +dnl # Date: Fri Dec 28 00:34:24 2018 -0800 +dnl # mm: convert zone->managed_pages to atomic variable +dnl # +AC_DEFUN([AC_AMDGPU_ZONE_MANAGED_PAGES], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + zone_managed_pages(NULL); + ],[ + AC_DEFINE(HAVE_ZONE_MANAGED_PAGES, 1, + [zone_managed_pages() is available]) + ],[ + dnl # + dnl # commit v3.7-4152-g9feedc9d831e + dnl # mm: introduce new field "managed_pages" to struct zone + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct zone *z = NULL; + z->managed_pages = 0; + ], [ + AC_DEFINE(HAVE_STRUCT_ZONE_MANAGED_PAGES, 1, + [zone->managed_pages is available]) + ]) + ]) + ]) +]) diff --git a/include/kcl/kcl_mm.h b/include/kcl/kcl_mm.h index cd1a3de986863..00c4b4edd62be 100644 --- a/include/kcl/kcl_mm.h +++ b/include/kcl/kcl_mm.h @@ -33,4 +33,17 @@ static inline void memalloc_nofs_restore(unsigned int flags) } #endif +#if !defined(HAVE_ZONE_MANAGED_PAGES) +static inline unsigned long zone_managed_pages(struct zone *zone) +{ +#if defined(HAVE_STRUCT_ZONE_MANAGED_PAGES) + return (unsigned long)zone->managed_pages; +#else + /* zone->managed_pages is introduced in v3.7-4152-g9feedc9d831e */ + WARN_ONCE(1, "struct zone->managed_pages don't exist. kernel is a bit old..."); + return 0; +#endif +} +#endif /* HAVE_ZONE_MANAGED_PAGES */ + #endif /* AMDKCL_MM_H */ From 75415495a58f2619393ba73a86e72203002ed5a6 Mon Sep 17 00:00:00 2001 From: Prike Liang Date: Tue, 26 Jun 2018 10:31:19 +0800 Subject: [PATCH 0136/1868] drm/amdkcl: Test whether vmf_insert_*() functions are available drm/amdkcl: [4.16] add kcl/kcl_mm_types.h file for ttm compatibility Signed-off-by: Prike Liang Reviewed-by: Tao Zhou Signed-off-by: Jack Gui drm/amdkcl: Test whether vmf_insert_*() functions are available Signed-off-by: Slava Grigorev Signed-off-by: Yifan Zhang Signed-off-by: Jack Gui drm/amd/autoconf: refactor kcl_mm_types.h Signed-off-by: Flora Cui Reviewed-by: Jack Gui drm/amdkcl: drop HAVE_PFN_T check outside of kcl Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang drm/amdkcl: move kcl copy of vmf_* to kcl_mm.h Reviewed-by: Yifan Zhang Signed-off-by: Flora Cui drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 3 +- drivers/gpu/drm/amd/dkms/m4/vmf-insert.m4 | 45 +++++++++++++++++++++++ drivers/gpu/drm/ttm/backport/backport.h | 1 + include/kcl/kcl_memory.h | 39 ++++++++++++++++++++ include/kcl/kcl_mm.h | 7 ++++ include/kcl/kcl_mm_types.h | 39 ++++++++++++++++++++ 6 files changed, 133 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/vmf-insert.m4 create mode 100644 include/kcl/kcl_memory.h create mode 100644 include/kcl/kcl_mm_types.h diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 238cf6ece6a42..95dfc6fcbd59b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -38,6 +38,8 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_KTIME_GET_FAST_NS AC_AMDGPU_MEMALLOC_NOFS_SAVE AC_AMDGPU_ZONE_MANAGED_PAGES + AC_AMDGPU_FAULT_FLAG_ALLOW_RETRY_FIRST + AC_AMDGPU_VMF_INSERT AC_AMDGPU_MMU_NOTIFIER AC_AMDGPU_MM_RELEASE_PAGES AC_AMDGPU_DMA_FENCE_HEADERS @@ -52,7 +54,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_SET_PATH_PROPERTY AC_AMDGPU_DRM_CONNECTOR_INIT_WITH_DDC AC_AMDGPU_KTHREAD_USE_MM - AC_AMDGPU_FAULT_FLAG_ALLOW_RETRY_FIRST AC_AMDGPU_DRM_DEBUG_PRINTER AC_AMDGPU_DRM_FB_HELPER_FILL_INFO AC_AMDGPU_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED diff --git a/drivers/gpu/drm/amd/dkms/m4/vmf-insert.m4 b/drivers/gpu/drm/amd/dkms/m4/vmf-insert.m4 new file mode 100644 index 0000000000000..89789fd059839 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/vmf-insert.m4 @@ -0,0 +1,45 @@ +dnl # +dnl # commit v4.4-6466-g34c0fd540e79 +dnl # mm, dax, pmem: introduce pfn_t +dnl # +AC_DEFUN([AC_AMDGPU_VMF_INSERT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + pfn_t pfn; + pfn.val = 0; + ], [ + dnl # + dnl # commit v4.16-7358-g1c8f422059ae + dnl # mm: change return type to vm_fault_t + dnl # + AC_DEFINE(HAVE_PFN_T, 1, [pfn_t is defined]) + + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + pfn_t pfn = {}; + vmf_insert_mixed(NULL, 0, pfn); + vmf_insert_pfn(NULL, 0, 0); + ], [ + AC_DEFINE(HAVE_VMF_INSERT, 1, + [vmf_insert_*() are available]) + ], [ + dnl # + dnl # commit v4.4-6475-g01c8f1c44b83 + dnl # mm, dax, gpu: convert vm_insert_mixed to pfn_t + dnl # + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + pfn_t pfn = {}; + vm_insert_mixed(NULL, 0, pfn); + ], [vm_insert_mixed], [mm/memory.c], [ + AC_DEFINE(HAVE_PFN_T_VM_INSERT_MIXED, 1, + [vm_insert_mixed() wants pfn_t arg]) + ]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index 9f3fbf350006e..659a7f1e254c4 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -8,4 +8,5 @@ #include #include #include +#include #endif diff --git a/include/kcl/kcl_memory.h b/include/kcl/kcl_memory.h new file mode 100644 index 0000000000000..f5ad19a510fe8 --- /dev/null +++ b/include/kcl/kcl_memory.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _KCL_KCL_MEMORY_H +#define _KCL_KCL_MEMORY_H + +#ifndef HAVE_VMF_INSERT +static inline vm_fault_t vmf_insert_mixed(struct vm_area_struct *vma, + unsigned long addr, + pfn_t pfn) +{ + int err; +#if !defined(HAVE_PFN_T_VM_INSERT_MIXED) + err = vm_insert_mixed(vma, addr, pfn_t_to_pfn(pfn)); +#else + err = vm_insert_mixed(vma, addr, pfn); +#endif + if (err == -ENOMEM) + return VM_FAULT_OOM; + if (err < 0 && err != -EBUSY) + return VM_FAULT_SIGBUS; + + return VM_FAULT_NOPAGE; +} + +static inline vm_fault_t vmf_insert_pfn(struct vm_area_struct *vma, + unsigned long addr, unsigned long pfn) +{ + int err = vm_insert_pfn(vma, addr, pfn); + + if (err == -ENOMEM) + return VM_FAULT_OOM; + if (err < 0 && err != -EBUSY) + return VM_FAULT_SIGBUS; + + return VM_FAULT_NOPAGE; +} + +#endif /* HAVE_VMF_INSERT */ + +#endif diff --git a/include/kcl/kcl_mm.h b/include/kcl/kcl_mm.h index 00c4b4edd62be..348b7570b6726 100644 --- a/include/kcl/kcl_mm.h +++ b/include/kcl/kcl_mm.h @@ -7,7 +7,14 @@ #ifndef AMDKCL_MM_H #define AMDKCL_MM_H +#include +#include +#include #include +#include +#include +#include +#include #ifndef untagged_addr /* Copied from include/linux/mm.h */ diff --git a/include/kcl/kcl_mm_types.h b/include/kcl/kcl_mm_types.h new file mode 100644 index 0000000000000..6cf223e559d02 --- /dev/null +++ b/include/kcl/kcl_mm_types.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_MM_TYPES_H +#define AMDKCL_MM_TYPES_H + +#include +#ifdef HAVE_PFN_T +#include +#else +/* Copied from include/linux/pfn_t.h */ +typedef struct { + u64 val; +} pfn_t; + +#define PFN_FLAGS_MASK (((unsigned long) ~PAGE_MASK) \ + << (BITS_PER_LONG - PAGE_SHIFT)) +#define PFN_SG_CHAIN (1UL << (BITS_PER_LONG - 1)) +#define PFN_SG_LAST (1UL << (BITS_PER_LONG - 2)) +#define PFN_DEV (1UL << (BITS_PER_LONG - 3)) +#define PFN_MAP (1UL << (BITS_PER_LONG - 4)) + +static inline pfn_t __pfn_to_pfn_t(unsigned long pfn, unsigned long flags) +{ + pfn_t pfn_t = { .val = pfn | (flags & PFN_FLAGS_MASK), }; + + return pfn_t; +} + +static inline unsigned long pfn_t_to_pfn(pfn_t pfn) +{ + return pfn.val & ~PFN_FLAGS_MASK; +} +#endif + +#ifndef HAVE_VMF_INSERT +typedef int vm_fault_t; +#endif + +#endif /* AMDKCL_MM_TYPES_H */ + From 2ff1612ec2471e0526ea5b3e6566dbe789587d3d Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 27 Aug 2020 16:31:58 +0800 Subject: [PATCH 0137/1868] drm/amdkcl: fake kcl copy of mmap_read_lock/unlock apis v2: c1f004d6344b drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- include/kcl/kcl_mm.h | 1 + include/kcl/kcl_mmap_lock.h | 48 +++++++++++++++++++++++++++++++++++++ 2 files changed, 49 insertions(+) create mode 100644 include/kcl/kcl_mmap_lock.h diff --git a/include/kcl/kcl_mm.h b/include/kcl/kcl_mm.h index 348b7570b6726..b4e18dfd764fe 100644 --- a/include/kcl/kcl_mm.h +++ b/include/kcl/kcl_mm.h @@ -13,6 +13,7 @@ #include #include #include +#include #include #include diff --git a/include/kcl/kcl_mmap_lock.h b/include/kcl/kcl_mmap_lock.h new file mode 100644 index 0000000000000..b677506d80cf1 --- /dev/null +++ b/include/kcl/kcl_mmap_lock.h @@ -0,0 +1,48 @@ +#ifndef KCL_KCL_MMAP_LOCK_H +#define KCL_KCL_MMAP_LOCK_H + +#ifdef HAVE_LINUX_MMAP_LOCK_H +#include +#else +/* Copied from include/linux/mmap_lock.h */ +static inline void mmap_init_lock(struct mm_struct *mm) +{ + init_rwsem(&mm->mmap_sem); +} + +static inline void mmap_write_lock(struct mm_struct *mm) +{ + down_write(&mm->mmap_sem); +} + +static inline bool mmap_write_trylock(struct mm_struct *mm) +{ + return down_write_trylock(&mm->mmap_sem) != 0; +} + +static inline void mmap_write_unlock(struct mm_struct *mm) +{ + up_write(&mm->mmap_sem); +} + +static inline void mmap_write_downgrade(struct mm_struct *mm) +{ + downgrade_write(&mm->mmap_sem); +} + +static inline void mmap_read_lock(struct mm_struct *mm) +{ + down_read(&mm->mmap_sem); +} + +static inline bool mmap_read_trylock(struct mm_struct *mm) +{ + return down_read_trylock(&mm->mmap_sem) != 0; +} + +static inline void mmap_read_unlock(struct mm_struct *mm) +{ + up_read(&mm->mmap_sem); +} +#endif +#endif /* KCL_KCL_MMAP_LOCK_H */ From e47419e9a093f17e1eab1a56c5f3a3ded11a2e1a Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 14 Apr 2020 18:18:15 +0800 Subject: [PATCH 0138/1868] drm/amdkcl: test whether vmf_insert_mixed_prot() is available Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_memory.c | 15 ++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../drm/amd/dkms/m4/vmf_insert_mixed_prot.m4 | 20 +++++++++++++++++++ include/kcl/kcl_memory.h | 11 ++++++++++ 5 files changed, 48 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_memory.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/vmf_insert_mixed_prot.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index fa37dcffda9fb..d2b9a7043ca89 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -6,7 +6,7 @@ amdkcl-y += dma-buf/dma-resv.o amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_kthread.o kcl_io.o kcl_perf_event.o kcl_seq_file.o\ - kcl_suspend.o kcl_pci.o kcl_mm.o \ + kcl_suspend.o kcl_pci.o kcl_mm.o kcl_memory.o\ kcl_fence.o kcl_fence_array.o kcl_reservation.o kcl_drm_cache.o \ kcl_drm_fb.o kcl_drm_print.o kcl_fbmem.o \ kcl_connector.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_memory.c b/drivers/gpu/drm/amd/amdkcl/kcl_memory.c new file mode 100644 index 0000000000000..fa13000906721 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_memory.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: MIT */ +#include + +#ifndef HAVE_VMF_INSERT_MIXED_PROT +vm_fault_t _kcl_vmf_insert_mixed_prot(struct vm_area_struct *vma, unsigned long addr, + pfn_t pfn, pgprot_t pgprot) +{ + struct vm_area_struct cvma = *vma; + + cvma.vm_page_prot = pgprot; + + return vmf_insert_mixed(&cvma, addr, pfn); +} +EXPORT_SYMBOL(_kcl_vmf_insert_mixed_prot); +#endif diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 95dfc6fcbd59b..71ddfb7706886 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -40,6 +40,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_ZONE_MANAGED_PAGES AC_AMDGPU_FAULT_FLAG_ALLOW_RETRY_FIRST AC_AMDGPU_VMF_INSERT + AC_AMDGPU_VMF_INSERT_MIXED_PROT AC_AMDGPU_MMU_NOTIFIER AC_AMDGPU_MM_RELEASE_PAGES AC_AMDGPU_DMA_FENCE_HEADERS diff --git a/drivers/gpu/drm/amd/dkms/m4/vmf_insert_mixed_prot.m4 b/drivers/gpu/drm/amd/dkms/m4/vmf_insert_mixed_prot.m4 new file mode 100644 index 0000000000000..53da9747196ea --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/vmf_insert_mixed_prot.m4 @@ -0,0 +1,20 @@ +dnl # +dnl # 5379e4dd3220 mm, drm/ttm: Fix vm page protection handling +dnl # 574c5b3d0e4c mm: Add a vmf_insert_mixed_prot() function +dnl # +AC_DEFUN([AC_AMDGPU_VMF_INSERT_MIXED_PROT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + #include + ],[ + pfn_t pfn; + pgprot_t prot; + vmf_insert_mixed_prot(NULL, 0, pfn, prot); + ],[vmf_insert_mixed_prot],[mm/memory.c],[ + AC_DEFINE(HAVE_VMF_INSERT_MIXED_PROT, + 1, + [vmf_insert_mixed_prot() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_memory.h b/include/kcl/kcl_memory.h index f5ad19a510fe8..5c7e4817d92f9 100644 --- a/include/kcl/kcl_memory.h +++ b/include/kcl/kcl_memory.h @@ -36,4 +36,15 @@ static inline vm_fault_t vmf_insert_pfn(struct vm_area_struct *vma, #endif /* HAVE_VMF_INSERT */ +#ifndef HAVE_VMF_INSERT_MIXED_PROT +vm_fault_t _kcl_vmf_insert_mixed_prot(struct vm_area_struct *vma, unsigned long addr, + pfn_t pfn, pgprot_t pgprot); +static inline +vm_fault_t vmf_insert_mixed_prot(struct vm_area_struct *vma, unsigned long addr, + pfn_t pfn, pgprot_t pgprot) +{ + return _kcl_vmf_insert_mixed_prot(vma, addr, pfn, pgprot); +} +#endif /* HAVE_VMF_INSERT_MIXED_PROT */ + #endif From 7250dfff7f40cc1eb4002444f384a269215588f1 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 15 Apr 2020 18:07:17 +0800 Subject: [PATCH 0139/1868] drm/amdkcl: fake a kcl copy of vmf_insert_pfn_prot() Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/kcl_memory.c | 28 +++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../drm/amd/dkms/m4/vmf_insert_pfn_prot.m4 | 35 +++++++++++++++++++ include/kcl/kcl_memory.h | 11 ++++++ 4 files changed, 75 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/vmf_insert_pfn_prot.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_memory.c b/drivers/gpu/drm/amd/amdkcl/kcl_memory.c index fa13000906721..9d5358ca93b48 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_memory.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_memory.c @@ -13,3 +13,31 @@ vm_fault_t _kcl_vmf_insert_mixed_prot(struct vm_area_struct *vma, unsigned long } EXPORT_SYMBOL(_kcl_vmf_insert_mixed_prot); #endif + +#ifndef HAVE_VMF_INSERT_PFN_PROT +#ifndef HAVE_VM_INSERT_PFN_PROT +int vm_insert_pfn_prot(struct vm_area_struct *vma, unsigned long addr, + unsigned long pfn, pgprot_t pgprot) +{ + struct vm_area_struct cvma = *vma; + + cvma.vm_page_prot = pgprot; + + return vm_insert_pfn(&cvma, addr, pfn); +} +#endif + +vm_fault_t _kcl_vmf_insert_pfn_prot(struct vm_area_struct *vma, unsigned long addr, + unsigned long pfn, pgprot_t pgprot) +{ + int err = vm_insert_pfn_prot(vma, addr, pfn, pgprot); + + if (err == -ENOMEM) + return VM_FAULT_OOM; + if (err < 0 && err != -EBUSY) + return VM_FAULT_SIGBUS; + + return VM_FAULT_NOPAGE; +} +EXPORT_SYMBOL(_kcl_vmf_insert_pfn_prot); +#endif diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 71ddfb7706886..86e431587638c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -41,6 +41,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_FAULT_FLAG_ALLOW_RETRY_FIRST AC_AMDGPU_VMF_INSERT AC_AMDGPU_VMF_INSERT_MIXED_PROT + AC_AMDGPU_VMF_INSERT_PFN_PROT AC_AMDGPU_MMU_NOTIFIER AC_AMDGPU_MM_RELEASE_PAGES AC_AMDGPU_DMA_FENCE_HEADERS diff --git a/drivers/gpu/drm/amd/dkms/m4/vmf_insert_pfn_prot.m4 b/drivers/gpu/drm/amd/dkms/m4/vmf_insert_pfn_prot.m4 new file mode 100644 index 0000000000000..d1f869507e4dd --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/vmf_insert_pfn_prot.m4 @@ -0,0 +1,35 @@ +dnl # +dnl # commit v4.19-6927-gf5e6d1d5f8f3 +dnl # mm: introduce vmf_insert_pfn_prot() +dnl # +AC_DEFUN([AC_AMDGPU_VMF_INSERT_PFN_PROT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ],[ + pgprot_t prot; + vmf_insert_pfn_prot(NULL, 0, 0, prot); + ],[ + AC_DEFINE(HAVE_VMF_INSERT_PFN_PROT, + 1, + [vmf_insert_pfn_prot() is available]) + ],[ + dnl # + dnl # commit v4.4-528-g1745cbc5d0de + dnl # mm: Add vm_insert_pfn_prot() + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + #include + ],[ + pgprot_t prot; + vm_insert_pfn_prot(NULL, 0, 0, prot); + ],[ + AC_DEFINE(HAVE_VM_INSERT_PFN_PROT, + 1, + [vm_insert_pfn_prot() is available]) + ]) + ]) + ]) +]) diff --git a/include/kcl/kcl_memory.h b/include/kcl/kcl_memory.h index 5c7e4817d92f9..e0dac3be04b47 100644 --- a/include/kcl/kcl_memory.h +++ b/include/kcl/kcl_memory.h @@ -47,4 +47,15 @@ vm_fault_t vmf_insert_mixed_prot(struct vm_area_struct *vma, unsigned long addr, } #endif /* HAVE_VMF_INSERT_MIXED_PROT */ +#ifndef HAVE_VMF_INSERT_PFN_PROT +vm_fault_t _kcl_vmf_insert_pfn_prot(struct vm_area_struct *vma, unsigned long addr, + unsigned long pfn, pgprot_t pgprot); +static inline +vm_fault_t vmf_insert_pfn_prot(struct vm_area_struct *vma, unsigned long addr, + unsigned long pfn, pgprot_t pgprot) +{ + return _kcl_vmf_insert_pfn_prot(vma, addr, pfn, pgprot); +} +#endif /* HAVE_VMF_INSERT_PFN_PROT */ + #endif From 4c3ee8078afcff2946cc0b1954588aa4e6425002 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 3 Sep 2020 17:40:25 +0800 Subject: [PATCH 0140/1868] drm/amdkcl: test sched_set_fifo_low() v2: c1f004d6344b drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkcl/Makefile | 4 +-- drivers/gpu/drm/amd/amdkcl/kcl_sched.c | 30 +++++++++++++++++++ drivers/gpu/drm/amd/amdkcl/main.c | 2 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../gpu/drm/amd/dkms/m4/sched_set_fifo_low.m4 | 13 ++++++++ drivers/gpu/drm/scheduler/backport/backport.h | 1 + include/kcl/kcl_sched.h | 12 ++++++++ 7 files changed, 61 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_sched.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/sched_set_fifo_low.m4 create mode 100644 include/kcl/kcl_sched.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index d2b9a7043ca89..893aca5bc08d2 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -5,8 +5,8 @@ amdkcl-y += kcl_kernel_params.o amdkcl-y += dma-buf/dma-resv.o amdkcl-y += kcl_backlight.o kcl_ioctl.o \ - kcl_kthread.o kcl_io.o kcl_perf_event.o kcl_seq_file.o\ - kcl_suspend.o kcl_pci.o kcl_mm.o kcl_memory.o\ + kcl_kthread.o kcl_io.o kcl_perf_event.o kcl_seq_file.o \ + kcl_suspend.o kcl_pci.o kcl_mm.o kcl_memory.o kcl_sched.o \ kcl_fence.o kcl_fence_array.o kcl_reservation.o kcl_drm_cache.o \ kcl_drm_fb.o kcl_drm_print.o kcl_fbmem.o \ kcl_connector.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_sched.c b/drivers/gpu/drm/amd/amdkcl/kcl_sched.c new file mode 100644 index 0000000000000..e57b29e7a7a73 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_sched.c @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * kernel/sched/core.c + * + * Core kernel scheduler code and related syscalls + * + * Copyright (C) 1991-2002 Linus Torvalds + */ + +#include + +/* Copied from kernel/sched/core.c and modified for KCL */ +#ifndef HAVE_SCHED_SET_FIFO_LOW +int (*_kcl_sched_setscheduler_nocheck)(struct task_struct *p, int policy, + const struct sched_param *param); +void sched_set_fifo_low(struct task_struct *p) +{ + struct sched_param sp = { .sched_priority = 1 }; + WARN_ON_ONCE(_kcl_sched_setscheduler_nocheck(p, SCHED_FIFO, &sp) != 0); +} +EXPORT_SYMBOL_GPL(sched_set_fifo_low); +#endif + +void amdkcl_sched_init(void) +{ +#ifndef HAVE_SCHED_SET_FIFO_LOW + _kcl_sched_setscheduler_nocheck = amdkcl_fp_setup("sched_setscheduler_nocheck", + NULL); +#endif +} diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c index 6dc78f4f4f851..b99b4ca0f9880 100644 --- a/drivers/gpu/drm/amd/amdkcl/main.c +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -11,6 +11,7 @@ extern void amdkcl_mm_init(void); extern void amdkcl_perf_event_init(void); extern void amdkcl_pci_init(void); extern void amdkcl_suspend_init(void); +extern void amdkcl_sched_init(void); int __init amdkcl_init(void) { @@ -23,6 +24,7 @@ int __init amdkcl_init(void) amdkcl_perf_event_init(); amdkcl_pci_init(); amdkcl_suspend_init(); + amdkcl_sched_init(); return 0; } diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 86e431587638c..014b74e5b590f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -44,6 +44,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_VMF_INSERT_PFN_PROT AC_AMDGPU_MMU_NOTIFIER AC_AMDGPU_MM_RELEASE_PAGES + AC_AMDGPU_SCHED_SET_FIFO_LOW AC_AMDGPU_DMA_FENCE_HEADERS AC_AMDGPU_DMA_RESV AC_AMDGPU_TTM_SG_TT_INIT diff --git a/drivers/gpu/drm/amd/dkms/m4/sched_set_fifo_low.m4 b/drivers/gpu/drm/amd/dkms/m4/sched_set_fifo_low.m4 new file mode 100644 index 0000000000000..422b5d833b653 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/sched_set_fifo_low.m4 @@ -0,0 +1,13 @@ +dnl # +dnl # v5.8-rc1-23-g7318d4cc14c8 +dnl # sched: Provide sched_set_fifo() +dnl # +AC_DEFUN([AC_AMDGPU_SCHED_SET_FIFO_LOW], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([sched_set_fifo_low], + [kernel/sched/core.c], [ + AC_DEFINE(HAVE_SCHED_SET_FIFO_LOW, 1, + [sched_set_fifo_low() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/scheduler/backport/backport.h b/drivers/gpu/drm/scheduler/backport/backport.h index 4a62c9677187a..46537c0094114 100644 --- a/drivers/gpu/drm/scheduler/backport/backport.h +++ b/drivers/gpu/drm/scheduler/backport/backport.h @@ -6,4 +6,5 @@ #include #include #include +#include #endif diff --git a/include/kcl/kcl_sched.h b/include/kcl/kcl_sched.h new file mode 100644 index 0000000000000..2ed8d6a01cd1f --- /dev/null +++ b/include/kcl/kcl_sched.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _KCL_KCL_SCHED_H +#define _KCL_KCL_SCHED_H + +#include +#include + +#ifndef HAVE_SCHED_SET_FIFO_LOW +void sched_set_fifo_low(struct task_struct *p); +#endif + +#endif From d5a4df25f3f999c880184deb71896ab172e5641f Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 17 Jun 2020 13:08:42 +0800 Subject: [PATCH 0141/1868] drm/amdkcl: fake drm_helper_mode_fill_fb_struct() drm_helper_mode_fill_fb_struct() prototype change in commit v4.9-rc8-1643-ga3f913ca9892 Signed-off-by: Flora Cui Reviewed-by: Yang Xiong --- drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c | 11 +++++++++++ .../dkms/m4/drm_helper_mode_fill_fb_struct.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/backport/kcl_drm_fb.h | 5 +++++ include/kcl/kcl_drm_fb.h | 7 +++++++ 5 files changed, 40 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_helper_mode_fill_fb_struct.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c index 900629e0dc0ed..c2203e2ede030 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c @@ -49,3 +49,14 @@ void _kcl_drm_fb_helper_set_suspend_unlocked(struct drm_fb_helper *fb_helper, in } EXPORT_SYMBOL(_kcl_drm_fb_helper_set_suspend_unlocked); #endif + +#ifndef HAVE_DRM_HELPER_MODE_FILL_FB_STRUCT_DEV +void _kcl_drm_helper_mode_fill_fb_struct(struct drm_device *dev, + struct drm_framebuffer *fb, + const struct drm_mode_fb_cmd2 *mode_cmd) +{ + fb->dev = dev; + drm_helper_mode_fill_fb_struct(fb, mode_cmd); +} +EXPORT_SYMBOL(_kcl_drm_helper_mode_fill_fb_struct); +#endif diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_helper_mode_fill_fb_struct.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_helper_mode_fill_fb_struct.m4 new file mode 100644 index 0000000000000..3d662319c8e11 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_helper_mode_fill_fb_struct.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v4.9-rc8-1647-g95bce7601581 drm: Populate fb->dev from drm_helper_mode_fill_fb_struct() +dnl # v4.9-rc8-1643-ga3f913ca9892 drm: Pass 'dev' to drm_helper_mode_fill_fb_struct() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_HELPER_MODE_FILL_FB_STRUCT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_helper_mode_fill_fb_struct(NULL, NULL, NULL); + ], [ + AC_DEFINE(HAVE_DRM_HELPER_MODE_FILL_FB_STRUCT_DEV, 1, + [drm_helper_mode_fill_fb_struct() wants dev arg]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 014b74e5b590f..e4d58dc65dc7b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -60,6 +60,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DEBUG_PRINTER AC_AMDGPU_DRM_FB_HELPER_FILL_INFO AC_AMDGPU_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED + AC_AMDGPU_DRM_HELPER_MODE_FILL_FB_STRUCT AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/backport/kcl_drm_fb.h b/include/kcl/backport/kcl_drm_fb.h index c83d4ffd135b4..85af1711c5a92 100644 --- a/include/kcl/backport/kcl_drm_fb.h +++ b/include/kcl/backport/kcl_drm_fb.h @@ -28,4 +28,9 @@ #if !defined(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP) #define drm_fb_helper_remove_conflicting_pci_framebuffers _kcl_drm_fb_helper_remove_conflicting_pci_framebuffers #endif + +#ifndef HAVE_DRM_HELPER_MODE_FILL_FB_STRUCT_DEV +#define drm_helper_mode_fill_fb_struct _kcl_drm_helper_mode_fill_fb_struct +#endif + #endif diff --git a/include/kcl/kcl_drm_fb.h b/include/kcl/kcl_drm_fb.h index 76b6ade463704..cd950f495e36b 100644 --- a/include/kcl/kcl_drm_fb.h +++ b/include/kcl/kcl_drm_fb.h @@ -32,6 +32,7 @@ #include #include +#include #include #if !defined(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS) @@ -94,4 +95,10 @@ void drm_fb_helper_set_suspend_unlocked(struct drm_fb_helper *fb_helper, } #endif +#ifndef HAVE_DRM_HELPER_MODE_FILL_FB_STRUCT_DEV +void _kcl_drm_helper_mode_fill_fb_struct(struct drm_device *dev, + struct drm_framebuffer *fb, + const struct drm_mode_fb_cmd2 *mode_cmd); +#endif + #endif From 5877cf85cc5c37b72682e92f7bfe4f89f055a41f Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 16 Dec 2020 16:41:10 +0800 Subject: [PATCH 0142/1868] drm/amdkcl: rework kcl faked drm_helper_mode_fill_fb_struct no need to add a _kcl_ symbol Signed-off-by: Flora Cui Reviewed-by: Shiwu Zhang --- drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c | 11 ----------- include/kcl/backport/kcl_drm_fb.h | 9 +++++++++ include/kcl/kcl_drm_fb.h | 7 ------- 3 files changed, 9 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c index c2203e2ede030..900629e0dc0ed 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c @@ -49,14 +49,3 @@ void _kcl_drm_fb_helper_set_suspend_unlocked(struct drm_fb_helper *fb_helper, in } EXPORT_SYMBOL(_kcl_drm_fb_helper_set_suspend_unlocked); #endif - -#ifndef HAVE_DRM_HELPER_MODE_FILL_FB_STRUCT_DEV -void _kcl_drm_helper_mode_fill_fb_struct(struct drm_device *dev, - struct drm_framebuffer *fb, - const struct drm_mode_fb_cmd2 *mode_cmd) -{ - fb->dev = dev; - drm_helper_mode_fill_fb_struct(fb, mode_cmd); -} -EXPORT_SYMBOL(_kcl_drm_helper_mode_fill_fb_struct); -#endif diff --git a/include/kcl/backport/kcl_drm_fb.h b/include/kcl/backport/kcl_drm_fb.h index 85af1711c5a92..fd7f828ca96fd 100644 --- a/include/kcl/backport/kcl_drm_fb.h +++ b/include/kcl/backport/kcl_drm_fb.h @@ -30,6 +30,15 @@ #endif #ifndef HAVE_DRM_HELPER_MODE_FILL_FB_STRUCT_DEV +static inline +void _kcl_drm_helper_mode_fill_fb_struct(struct drm_device *dev, + struct drm_framebuffer *fb, + const struct drm_mode_fb_cmd2 *mode_cmd) +{ + fb->dev = dev; + drm_helper_mode_fill_fb_struct(fb, mode_cmd); +} + #define drm_helper_mode_fill_fb_struct _kcl_drm_helper_mode_fill_fb_struct #endif diff --git a/include/kcl/kcl_drm_fb.h b/include/kcl/kcl_drm_fb.h index cd950f495e36b..0954d658644a8 100644 --- a/include/kcl/kcl_drm_fb.h +++ b/include/kcl/kcl_drm_fb.h @@ -94,11 +94,4 @@ void drm_fb_helper_set_suspend_unlocked(struct drm_fb_helper *fb_helper, _kcl_drm_fb_helper_set_suspend_unlocked(fb_helper, suspend); } #endif - -#ifndef HAVE_DRM_HELPER_MODE_FILL_FB_STRUCT_DEV -void _kcl_drm_helper_mode_fill_fb_struct(struct drm_device *dev, - struct drm_framebuffer *fb, - const struct drm_mode_fb_cmd2 *mode_cmd); -#endif - #endif From e7768bdc9833690a723975b65b9da43db141e821 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Tue, 10 Jul 2018 16:25:09 -0400 Subject: [PATCH 0143/1868] drm/amdkcl: Test whether drm_crtc_force_disable_all() is available v2: drm/amdkcl: fix drm_crtc_force_disable_all v3: drm/amdkcl: fix license for kcl drm part Signed-off-by: Slava Grigorev Signed-off-by: Yifan Zhang Reviewed-by: Flora Cui Signed-off-by: Flora Cui Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang Reviewed-by: Felix Kuehling Change-Id: Iceb48227e9cf51f819af21ceb5ba231e3750dd6b --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_drm_crtc.c | 79 +++++++++++++++++++ .../amd/dkms/m4/drm-crtc-force-disable-all.m4 | 16 ++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_crtc.h | 6 ++ 5 files changed, 103 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_crtc.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-crtc-force-disable-all.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 893aca5bc08d2..3de8b0d51ffcb 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -9,7 +9,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_suspend.o kcl_pci.o kcl_mm.o kcl_memory.o kcl_sched.o \ kcl_fence.o kcl_fence_array.o kcl_reservation.o kcl_drm_cache.o \ kcl_drm_fb.o kcl_drm_print.o kcl_fbmem.o \ - kcl_connector.o + kcl_drm_crtc.o kcl_connector.o CFLAGS_kcl_fence.o := -I$(src) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_crtc.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_crtc.c new file mode 100644 index 0000000000000..0dab372fcb93f --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_crtc.c @@ -0,0 +1,79 @@ +/* + * Copyright (c) 2006-2008 Intel Corporation + * Copyright (c) 2007 Dave Airlie + * Copyright (c) 2008 Red Hat Inc. + * + * DRM core CRTC related functions + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE. + * + * Authors: + * Keith Packard + * Eric Anholt + * Dave Airlie + * Jesse Barnes + */ +#include + +#if !defined(HAVE_DRM_CRTC_FORCE_DISABLE_ALL) +/** + * drm_crtc_force_disable - Forcibly turn off a CRTC + * @crtc: CRTC to turn off + * + * Returns: + * Zero on success, error code on failure. + */ +int drm_crtc_force_disable(struct drm_crtc *crtc) +{ + struct drm_mode_set set = { + .crtc = crtc, + }; + + return drm_mode_set_config_internal(&set); +} +EXPORT_SYMBOL(drm_crtc_force_disable); + +/** + * drm_crtc_force_disable_all - Forcibly turn off all enabled CRTCs + * @dev: DRM device whose CRTCs to turn off + * + * Drivers may want to call this on unload to ensure that all displays are + * unlit and the GPU is in a consistent, low power state. Takes modeset locks. + * + * Returns: + * Zero on success, error code on failure. + */ +int drm_crtc_force_disable_all(struct drm_device *dev) +{ + struct drm_crtc *crtc; + int ret = 0; + + drm_modeset_lock_all(dev); + drm_for_each_crtc(crtc, dev) + if (crtc->enabled) { + ret = drm_crtc_force_disable(crtc); + if (ret) + goto out; + } +out: + drm_modeset_unlock_all(dev); + return ret; +} +EXPORT_SYMBOL(drm_crtc_force_disable_all); +#endif diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-crtc-force-disable-all.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-crtc-force-disable-all.m4 new file mode 100644 index 0000000000000..68ccba497ae81 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-crtc-force-disable-all.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit 6a0d95285035c43361c72776b4c618f60c0f4ab4 +dnl # drm: Add helpers to turn off CRTCs +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CRTC_FORCE_DISABLE_ALL], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_crtc_force_disable_all(NULL); + ], [drm_crtc_force_disable_all], [drivers/gpu/drm/drm_crtc.c], [ + AC_DEFINE(HAVE_DRM_CRTC_FORCE_DISABLE_ALL, 1, + [drm_crtc_force_disable_all() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index e4d58dc65dc7b..1d23e06f8e2b4 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -61,6 +61,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_FB_HELPER_FILL_INFO AC_AMDGPU_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED AC_AMDGPU_DRM_HELPER_MODE_FILL_FB_STRUCT + AC_AMDGPU_DRM_CRTC_FORCE_DISABLE_ALL AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_crtc.h b/include/kcl/kcl_drm_crtc.h index f027ec142c74e..38861d70bd9bb 100644 --- a/include/kcl/kcl_drm_crtc.h +++ b/include/kcl/kcl_drm_crtc.h @@ -50,6 +50,7 @@ #include #include +#include /* Copied from include/drm/drm_mode.h */ #ifndef DRM_MODE_ROTATE_0 @@ -73,4 +74,9 @@ DRM_MODE_ROTATE_270) #endif +#if !defined(HAVE_DRM_CRTC_FORCE_DISABLE_ALL) +extern int drm_crtc_force_disable(struct drm_crtc *crtc); +extern int drm_crtc_force_disable_all(struct drm_device *dev); +#endif + #endif From 23eb22f11be23bc46ac2e990e96423b002f3fc6f Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 22 Oct 2019 14:16:22 +0800 Subject: [PATCH 0144/1868] drm/amdkcl: fix drm_add_edid_modes & drm_edid_to_eld drm_edid_to_eld() is moved to drm_add_edid_modes() in commit v4.14-rc3-592-gc945b8c14bb7 and is set to static in commit v4.14-rc3-594-g79436a1c9bcc HAVE_DRM_EDID_TO_ELD check could help to avoid duplicated drm_edid_to_eld() in most cases. Signed-off-by: Flora Cui Reviewed-by: Nicholas Kazlauskas Signed-off-by: Jiansong Chen Signed-off-by: Yifan Zhang Change-Id: Id7c442179d03f891274ecfa549ea26c16e68fa4e --- .../gpu/drm/amd/dkms/m4/drm-edid-to-eld.m4 | 19 +++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/backport/kcl_drm_encoder.h | 56 +++++++++++++++++++ 3 files changed, 76 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-edid-to-eld.m4 create mode 100644 include/kcl/backport/kcl_drm_encoder.h diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-edid-to-eld.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-edid-to-eld.m4 new file mode 100644 index 0000000000000..f0efb113db67b --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-edid-to-eld.m4 @@ -0,0 +1,19 @@ +dnl # +dnl # commit v4.14-rc3-594-g79436a1c9bcc +dnl # drm/edid: make drm_edid_to_eld() static +dnl # +dnl # commit v3.1-rc6-139-g76adaa34db40 +dnl # drm: support routines for HDMI/DP ELD +dnl # +AC_DEFUN([AC_AMDGPU_DRM_EDID_TO_ELD], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_edid_to_eld(NULL, NULL); + ], [drm_edid_to_eld], [drivers/gpu/drm/drm_edid.c], [ + AC_DEFINE(HAVE_DRM_EDID_TO_ELD, 1, + [drm_edid_to_eld() are available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 1d23e06f8e2b4..a7b5ccceb8d07 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -62,6 +62,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED AC_AMDGPU_DRM_HELPER_MODE_FILL_FB_STRUCT AC_AMDGPU_DRM_CRTC_FORCE_DISABLE_ALL + AC_AMDGPU_DRM_EDID_TO_ELD AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/backport/kcl_drm_encoder.h b/include/kcl/backport/kcl_drm_encoder.h new file mode 100644 index 0000000000000..07e3a75541b80 --- /dev/null +++ b/include/kcl/backport/kcl_drm_encoder.h @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2006 Luc Verhaegen (quirks list) + * Copyright (c) 2007-2008 Intel Corporation + * Jesse Barnes + * Copyright 2010 Red Hat, Inc. + * + * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from + * FB layer. + * Copyright (C) 2006 Dennis Munsie + * For codes copied from drivers/gpu/drm/drm_edid.c + * + * Copyright (c) 2016 Intel Corporation + * For codes copied from include/drm/drm_encoder.h + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sub license, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#ifndef KCL_BACKPORT_KCL_DRM_ENCODER_H +#define KCL_BACKPORT_KCL_DRM_ENCODER_H + +#include +#include + +#if defined(HAVE_DRM_EDID_TO_ELD) +static inline +int _kcl_drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) +{ + int ret; + + ret = drm_add_edid_modes(connector, edid); + + if (drm_edid_is_valid(edid)) + drm_edid_to_eld(connector, edid); + + return ret; +} +#define drm_add_edid_modes _kcl_drm_add_edid_modes +#endif + +#endif From 8dac5439a06cbafab8cc901800b43e235e45c5f0 Mon Sep 17 00:00:00 2001 From: "Stanley.Yang" Date: Tue, 7 Jan 2020 11:41:45 +0800 Subject: [PATCH 0145/1868] drm/amdkcl: Test whether drm_dp_atomic_find_vcpi_slots() wants five arguments it is a squash of: commit 60952ca580bfaa25cb57731bd7803bae5ec5293d Author: Stanley.Yang Date: Tue Jan 7 11:41:45 2020 +0800 drm/amdkcl: Test whether drm_dp_atomic_find_vcpi_slots() wants five arguments Signed-off-by: Stanley.Yang commit 6bbc6aadcb87e88d0f7976230b8292674b835785 Author: Slava Grigorev Date: Thu Jan 23 17:08:59 2020 -0500 drm/amdkcl: fix AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS test - a logical error in the test - compiler warning about ingnoring return value Signed-off-by: Slava Grigorev commit 655092d31b7e37020ef98bda5a0401f6a13f603c Author: Flora Cui Date: Mon Nov 16 16:34:47 2020 +0800 drm/amdkcl: move kcl copy for drm_dp_mst_helper into backport part the macros definition should be in backport to warn amdkcl to NOT include it. Reviewed-by: Shiwu Zhang Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/backport/backport.h | 1 + .../dkms/m4/drm-dp-atomic-find-vcpi-slots.m4 | 33 ++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../backport/kcl_drm_dp_mst_helper_backport.h | 54 +++++++++++++++++++ 4 files changed, 89 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-find-vcpi-slots.m4 create mode 100644 include/kcl/backport/kcl_drm_dp_mst_helper_backport.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index ffe385190e8ee..8ca380f5f6412 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -37,5 +37,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-find-vcpi-slots.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-find-vcpi-slots.m4 new file mode 100644 index 0000000000000..448c9066f274a --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-find-vcpi-slots.m4 @@ -0,0 +1,33 @@ +dnl # +dnl # commit edb1ed1ab7d314e114de84003f763da34c0f34c0 +dnl # drm/dp: Add DP MST helpers to atomically find and release vcpi slots +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + int retval; + retval = drm_dp_atomic_find_vcpi_slots(NULL, NULL, NULL, 0); + ], [drm_dp_atomic_find_vcpi_slots], [drivers/gpu/drm/drm_dp_mst_topology.c], [ + AC_DEFINE(HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS, 1, + [drm_dp_atomic_find_vcpi_slots() is available]) + ], [ + dnl # + dnl # commit dad1c2499a8f6d7ee01db8148f05ebba73cc41bd + dnl # drm/dp_mst: Manually overwrite PBN divider for calculating timeslots + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + int retval; + retval = drm_dp_atomic_find_vcpi_slots(NULL, NULL, NULL, 0, 0); + ], [ + AC_DEFINE(HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS_5ARGS, 1, + [drm_dp_atomic_find_vcpi_slots() wants 5args]) + AC_DEFINE(HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS, 1, + [drm_dp_atomic_find_vcpi_slots() is available]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index a7b5ccceb8d07..d1d9788795673 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -56,6 +56,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_ATTACH_ENCODER AC_AMDGPU_DRM_CONNECTOR_SET_PATH_PROPERTY AC_AMDGPU_DRM_CONNECTOR_INIT_WITH_DDC + AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS AC_AMDGPU_KTHREAD_USE_MM AC_AMDGPU_DRM_DEBUG_PRINTER AC_AMDGPU_DRM_FB_HELPER_FILL_INFO diff --git a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h new file mode 100644 index 0000000000000..500c939856d17 --- /dev/null +++ b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h @@ -0,0 +1,54 @@ +/* + * Copyright © 2014 Red Hat + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE. + */ +#ifndef _KCL_DRM_DP_MST_HELPER_BACKPORT_H_ +#define _KCL_DRM_DP_MST_HELPER_BACKPORT_H_ + +#include + +#if defined(HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS) +#if !defined(HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS_5ARGS) +static inline +int _kcl_drm_dp_atomic_find_vcpi_slots(struct drm_atomic_state *state, + struct drm_dp_mst_topology_mgr *mgr, + struct drm_dp_mst_port *port, int pbn, + int pbn_div) +{ + int pbn_backup; + int req_slots; + + if (pbn_div > 0) { + pbn_backup = mgr->pbn_div; + mgr->pbn_div = pbn_div; + } + + req_slots = drm_dp_atomic_find_vcpi_slots(state, mgr, port, pbn); + + if (pbn_div > 0) + mgr->pbn_div = pbn_backup; + + return req_slots; +} +#define drm_dp_atomic_find_vcpi_slots _kcl_drm_dp_atomic_find_vcpi_slots +#endif /* HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS_5ARGS */ +#endif /* HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS */ + +#endif From 88d7f65059b4346436a0d6dc16638442445797f3 Mon Sep 17 00:00:00 2001 From: tianci yin Date: Fri, 11 Jan 2019 15:39:47 +0800 Subject: [PATCH 0146/1868] drm/amdkcl: Test whether drm_dp_cec_xxx functions are available v1: drm/amdkcl: [4.19] kcl for drm_dp_cec_* functions v2: drm/amdkcl: Test whether drm_dp_cec_xxx functions are available v3: drm/amdkcl: fix kcl_drm_dp_cec_xxx v4: drm/amdkcl: fix drm_dp_cec_xxx check v5: drm_dp_cec_xxx are inlines with CONFIG_DRM_DP_CEC undefined. v6: drm/amdkcl: drop kcl_drm_dp_cec_xxx v7: drm/amdkcl: refactor kcl check for drm_dp_cec_irq v8: drm/amdkcl: split drm_dp_cec related stuff [why] commit "drm: add support for DisplayPort CEC-Tunneling-over-AUX" introduced drm_dp_cec_* functions. commit "drm/amdgpu: add DisplayPort CEC-Tunneling-over-AUX suppor" introduced the reference of drm_dp_cec_* functions. but for kernel < 4.19, drm_dp_cec_* functions are not available. [how] "DisplayPort CEC-Tunneling-over-AUX" is a new feature, for old kernel, we can just skip it, so we just define empty drm_dp_cec* functions like CONFIG_DRM_DP_CEC is not set. Reviewed-by: changzhu Signed-off-by: Tianci Yin Signed-off-by: chen gong Reviewed-by: Slava Grigorev Signed-off-by: Yifan Zhang Signed-off-by: Flora Cui Reviewed-by: Jack Gui Reviewed-by: Feifei Xu Signed-off-by: Jack Gui Signed-off-by: Flora Cui Reviewed-by: Shiwu Zhang --- drivers/gpu/drm/amd/backport/backport.h | 1 + .../m4/drm-dp-cec-correlation-functions.m4 | 31 +++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../kcl/backport/kcl_drm_dp_helper_backport.h | 21 +++++ include/kcl/kcl_drm_dp_cec.h | 86 +++++++++++++++++++ 5 files changed, 140 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dp-cec-correlation-functions.m4 create mode 100644 include/kcl/backport/kcl_drm_dp_helper_backport.h create mode 100644 include/kcl/kcl_drm_dp_cec.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 8ca380f5f6412..a581beee14b3d 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -37,6 +37,7 @@ #include #include #include +#include #include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-cec-correlation-functions.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-cec-correlation-functions.m4 new file mode 100644 index 0000000000000..52f51298caf4d --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-cec-correlation-functions.m4 @@ -0,0 +1,31 @@ +dnl # +dnl # commit v5.3-rc1-555-gae85b0df124f +dnl # drm_dp_cec: add connector info support. +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_CEC_CORRELATION_FUNCTIONS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_dp_cec_register_connector(NULL, NULL); + ], [ + AC_DEFINE(HAVE_DRM_DP_CEC_REGISTER_CONNECTOR_PP, 1, + [drm_dp_cec_register_connector() wants p,p interface]) + AC_DEFINE(HAVE_DRM_DP_CEC_CORRELATION_FUNCTIONS, 1, + [drm_dp_cec* correlation functions are available]) + ], [ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_dp_cec_irq(NULL); + drm_dp_cec_register_connector(NULL, NULL, NULL); + drm_dp_cec_unregister_connector(NULL); + drm_dp_cec_set_edid(NULL, NULL); + drm_dp_cec_unset_edid(NULL); + ], [ + AC_DEFINE(HAVE_DRM_DP_CEC_CORRELATION_FUNCTIONS, 1, + [drm_dp_cec* correlation functions are available]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index d1d9788795673..74f263a93aeee 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -57,6 +57,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_SET_PATH_PROPERTY AC_AMDGPU_DRM_CONNECTOR_INIT_WITH_DDC AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS + AC_AMDGPU_DRM_DP_CEC_CORRELATION_FUNCTIONS AC_AMDGPU_KTHREAD_USE_MM AC_AMDGPU_DRM_DEBUG_PRINTER AC_AMDGPU_DRM_FB_HELPER_FILL_INFO diff --git a/include/kcl/backport/kcl_drm_dp_helper_backport.h b/include/kcl/backport/kcl_drm_dp_helper_backport.h new file mode 100644 index 0000000000000..8a932361c9e0e --- /dev/null +++ b/include/kcl/backport/kcl_drm_dp_helper_backport.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_DRM_DP_HELPER_BACKPORT_H_ +#define _KCL_DRM_DP_HELPER_BACKPORT_H_ + +#include +#include + +/* + * commit v4.19-rc1-100-g5ce70c799ac2 + * drm_dp_cec: check that aux has a transfer function + */ +#if defined(AMDKCL_DRM_DP_CEC_XXX_CHECK_CB) +#define drm_dp_cec_irq _kcl_drm_dp_cec_irq +#define drm_dp_cec_set_edid _kcl_drm_dp_cec_set_edid +#define drm_dp_cec_unset_edid _kcl_drm_dp_cec_unset_edid +#endif + +#if !defined(HAVE_DRM_DP_CEC_REGISTER_CONNECTOR_PP) +#define drm_dp_cec_register_connector _kcl_drm_dp_cec_register_connector +#endif +#endif diff --git a/include/kcl/kcl_drm_dp_cec.h b/include/kcl/kcl_drm_dp_cec.h new file mode 100644 index 0000000000000..984b5d320f4fa --- /dev/null +++ b/include/kcl/kcl_drm_dp_cec.h @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * DisplayPort CEC-Tunneling-over-AUX support + * + * Copyright 2018 Cisco Systems, Inc. and/or its affiliates. All rights reserved. + */ + +#ifndef __KCL_KCL_DRM_DP_CEC_H__ +#define __KCL_KCL_DRM_DP_CEC_H__ + +#include + +/* + * commit v4.19-rc1-100-g5ce70c799ac2 + * drm_dp_cec: check that aux has a transfer function + */ +#if DRM_VERSION_CODE < DRM_VERSION(4, 20, 0) +#define AMDKCL_DRM_DP_CEC_XXX_CHECK_CB +#endif + +/* Copied from gpu/drm/drm_dp_cec.c and modified for KCL */ +#if defined(AMDKCL_DRM_DP_CEC_XXX_CHECK_CB) +static inline void _kcl_drm_dp_cec_irq(struct drm_dp_aux *aux) +{ +#if defined(HAVE_DRM_DP_CEC_CORRELATION_FUNCTIONS) +#ifdef CONFIG_DRM_DP_CEC + /* No transfer function was set, so not a DP connector */ + if (!aux->transfer) + return; +#endif + + drm_dp_cec_irq(aux); +#endif +} + +static inline void _kcl_drm_dp_cec_set_edid(struct drm_dp_aux *aux, + const struct edid *edid) +{ +#if defined(HAVE_DRM_DP_CEC_CORRELATION_FUNCTIONS) +#ifdef CONFIG_DRM_DP_CEC + /* No transfer function was set, so not a DP connector */ + if (!aux->transfer) + return; +#endif + + drm_dp_cec_set_edid(aux, edid); +#endif +} + +static inline void _kcl_drm_dp_cec_unset_edid(struct drm_dp_aux *aux) +{ +#if defined(HAVE_DRM_DP_CEC_CORRELATION_FUNCTIONS) +#ifdef CONFIG_DRM_DP_CEC + /* No transfer function was set, so not a DP connector */ + if (!aux->transfer) + return; +#endif + + drm_dp_cec_unset_edid(aux); +#endif +} +#endif + +#if !defined(HAVE_DRM_DP_CEC_CORRELATION_FUNCTIONS) +static inline void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux) +{ +} +#endif + +#if !defined(HAVE_DRM_DP_CEC_REGISTER_CONNECTOR_PP) +static inline void _kcl_drm_dp_cec_register_connector(struct drm_dp_aux *aux, + struct drm_connector *connector) +{ +#if defined(HAVE_DRM_DP_CEC_CORRELATION_FUNCTIONS) +#ifdef CONFIG_DRM_DP_CEC + if (WARN_ON(!aux->transfer)) + return; +#endif + + drm_dp_cec_register_connector(aux, connector->name, connector->dev->dev); +#endif +} +#endif + + +#endif From 581ed261a703a528058ea6830bac0928b7caa5e3 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 6 Dec 2019 15:29:49 +0800 Subject: [PATCH 0147/1868] drm/amdkcl: Test whether drm_dp_mst_topology_mgr_resume is available Signed-off-by: Flora Cui Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang --- .../dkms/m4/drm-dp-mst-topology-mgr-resume.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../backport/kcl_drm_dp_mst_helper_backport.h | 10 ++++++++++ 3 files changed, 28 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-mgr-resume.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-mgr-resume.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-mgr-resume.m4 new file mode 100644 index 0000000000000..3c491e182062e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-mgr-resume.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v5.4-rc4-759-g6f85f73821f6 +dnl # drm/dp_mst: Add basic topology reprobing when resuming +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_RESUME], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + int ret; + ret = drm_dp_mst_topology_mgr_resume(NULL, 0); + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_TOPOLOGY_MGR_RESUME_2ARGS, 1, + [drm_dp_mst_topology_mgr_resume() wants 2 args]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 74f263a93aeee..e5fcd0612b4b8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -58,6 +58,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_INIT_WITH_DDC AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS AC_AMDGPU_DRM_DP_CEC_CORRELATION_FUNCTIONS + AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_RESUME AC_AMDGPU_KTHREAD_USE_MM AC_AMDGPU_DRM_DEBUG_PRINTER AC_AMDGPU_DRM_FB_HELPER_FILL_INFO diff --git a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h index 500c939856d17..85fa328d0aa09 100644 --- a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h +++ b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h @@ -51,4 +51,14 @@ int _kcl_drm_dp_atomic_find_vcpi_slots(struct drm_atomic_state *state, #endif /* HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS_5ARGS */ #endif /* HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS */ +#ifndef HAVE_DRM_DP_MST_TOPOLOGY_MGR_RESUME_2ARGS +static inline int +_kcl_drm_dp_mst_topology_mgr_resume(struct drm_dp_mst_topology_mgr *mgr, + bool sync) +{ + return drm_dp_mst_topology_mgr_resume(mgr); +} +#define drm_dp_mst_topology_mgr_resume _kcl_drm_dp_mst_topology_mgr_resume +#endif + #endif From 91ca8ddc6517dbe004fc61482b37605cfd55e7c6 Mon Sep 17 00:00:00 2001 From: Prike Liang Date: Mon, 18 Feb 2019 10:56:56 +0800 Subject: [PATCH 0148/1868] drm/amdkcl: Test whether __devcgroup_check_permission() is available v1: drm/amdkcl: [4.15] Export __devcgroup_check_permission base on DKMS V2: EXport __devcgroup_check_permission by looking up the kallsys. v3: drm/amdkcl: Test whether __devcgroup_check_permission() is available v4: drm/amdkcl: fix devcgroup_check_permission() check v5: update for commit d16020d7429fffd47cfb2f3ab3b6b5b362108a6e : v6: drm/amdkcl: drop kcl_devcgroup_check_permission v7: drm/amdkcl: fix license for kcl part Signed-off-by: Prike Liang Reviewed-by: Junwei Zhang Signed-off-by: Flora Cui Reviewed-by: Jack Gui Reviewed-by: Rui Teng Acked-by: Feifei Xu Signed-off-by: Jack Gui Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkcl/Makefile | 3 +- .../gpu/drm/amd/amdkcl/kcl_device_cgroup.c | 35 +++++++++++++++ drivers/gpu/drm/amd/amdkcl/main.c | 2 + drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 4 +- drivers/gpu/drm/amd/backport/backport.h | 1 + .../amd/dkms/m4/devcgroup-check-permission.m4 | 15 +++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../kcl/backport/kcl_device_cgroup_backport.h | 10 +++++ include/kcl/kcl_device_cgroup.h | 45 +++++++++++++++++++ 9 files changed, 114 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_device_cgroup.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/devcgroup-check-permission.m4 create mode 100644 include/kcl/backport/kcl_device_cgroup_backport.h create mode 100644 include/kcl/kcl_device_cgroup.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 3de8b0d51ffcb..e0736cc39adb9 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -9,7 +9,8 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_suspend.o kcl_pci.o kcl_mm.o kcl_memory.o kcl_sched.o \ kcl_fence.o kcl_fence_array.o kcl_reservation.o kcl_drm_cache.o \ kcl_drm_fb.o kcl_drm_print.o kcl_fbmem.o \ - kcl_drm_crtc.o kcl_connector.o + kcl_drm_crtc.o kcl_connector.o \ + kcl_device_cgroup.o CFLAGS_kcl_fence.o := -I$(src) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_device_cgroup.c b/drivers/gpu/drm/amd/amdkcl/kcl_device_cgroup.c new file mode 100644 index 0000000000000..1fb1830aa5039 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_device_cgroup.c @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * device_cgroup.c - device cgroup subsystem + * + * Copyright 2007 IBM Corp + */ +#include +#include + +#if defined(CONFIG_CGROUP_DEVICE) && \ + !defined(HAVE_DEVCGROUP_CHECK_PERMISSION) +/* + * __devcgroup_check_permission is introduced in v3.6-6796-gad676077a2ae + * as: + * static int __devcgroup_check_permission(struct dev_cgroup *dev_cgroup, + * short type, u32 major, u32 minor, + * short access) + * + * prototype change in v3.7-rc2-147-g8c9506d16925 to: + * static int __devcgroup_check_permission(short type, u32 major, u32 minor, + * short access) + * + * the current amdkcl don't support kernel earilier than v3.7-rc2-147-g8c9506d16925 + */ +int (*__kcl_devcgroup_check_permission)(short type, u32 major, u32 minor, + short access); +EXPORT_SYMBOL(__kcl_devcgroup_check_permission); +#endif +void amdkcl_dev_cgroup_init(void) +{ +#if defined(CONFIG_CGROUP_DEVICE) && \ + !defined(HAVE_DEVCGROUP_CHECK_PERMISSION) + __kcl_devcgroup_check_permission = amdkcl_fp_setup("__devcgroup_check_permission", NULL); +#endif +} diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c index b99b4ca0f9880..aa767fa0aa014 100644 --- a/drivers/gpu/drm/amd/amdkcl/main.c +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -3,6 +3,7 @@ #include extern void amdkcl_symbol_init(void); +extern void amdkcl_dev_cgroup_init(void); extern void amdkcl_fence_init(void); extern void amdkcl_reservation_init(void); extern void amdkcl_io_init(void); @@ -16,6 +17,7 @@ extern void amdkcl_sched_init(void); int __init amdkcl_init(void) { amdkcl_symbol_init(); + amdkcl_dev_cgroup_init(); amdkcl_fence_init(); amdkcl_reservation_init(); amdkcl_io_init(); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index c60c0623287bf..70dc7b951de24 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -38,7 +38,9 @@ #include #include #include -#include +#include +/* amdkcl: this header file is included in kcl_device_cgroup.h +#include */ #include #include #include diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index a581beee14b3d..6ad8181770628 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -32,6 +32,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/gpu/drm/amd/dkms/m4/devcgroup-check-permission.m4 b/drivers/gpu/drm/amd/dkms/m4/devcgroup-check-permission.m4 new file mode 100644 index 0000000000000..0341249c5457b --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/devcgroup-check-permission.m4 @@ -0,0 +1,15 @@ +dnl # +dnl # commit v5.3-rc3-2427-g4b7d4d453fc4 +dnl # device_cgroup: Export devcgroup_check_permission +dnl # +AC_DEFUN([AC_AMDGPU_DEVCGROUP_CHECK_PERMISSION], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + devcgroup_check_permission(0, 0, 0, 0); + ], [devcgroup_check_permission], [security/device_cgroup.c], [ + AC_DEFINE(HAVE_DEVCGROUP_CHECK_PERMISSION, 1, [devcgroup_check_permission() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index e5fcd0612b4b8..6cfbed4fb46bb 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -48,6 +48,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DMA_FENCE_HEADERS AC_AMDGPU_DMA_RESV AC_AMDGPU_TTM_SG_TT_INIT + AC_AMDGPU_DEVCGROUP_CHECK_PERMISSION AC_AMDGPU_DRM_CACHE AC_AMDGPU_DRM_DEBUG_ENABLED AC_AMDGPU_DRM_GEM_OBJECT_PUT_UNLOCKED diff --git a/include/kcl/backport/kcl_device_cgroup_backport.h b/include/kcl/backport/kcl_device_cgroup_backport.h new file mode 100644 index 0000000000000..9bac47907e956 --- /dev/null +++ b/include/kcl/backport/kcl_device_cgroup_backport.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_DEVICE_CGROUP_BACKPORT_H +#define AMDKCL_DEVICE_CGROUP_BACKPORT_H + +#include + +#ifndef HAVE_DEVCGROUP_CHECK_PERMISSION +#define devcgroup_check_permission _kcl_devcgroup_check_permission +#endif /* HAVE_DEVCGROUP_CHECK_PERMISSION */ +#endif diff --git a/include/kcl/kcl_device_cgroup.h b/include/kcl/kcl_device_cgroup.h new file mode 100644 index 0000000000000..3eba9b4697856 --- /dev/null +++ b/include/kcl/kcl_device_cgroup.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_DEVICE_CGROUP_H +#define AMDKCL_DEVICE_CGROUP_H + +#include + +/* Copied from include/linux/device_cgroup.h */ +#ifndef DEVCG_DEV_CHAR +#define DEVCG_DEV_CHAR 2 +#endif +#ifndef DEVCG_ACC_READ +#define DEVCG_ACC_READ 2 +#endif +#ifndef DEVCG_ACC_WRITE +#define DEVCG_ACC_WRITE 4 +#endif + +/* Copied from security/device_cgroup.c and modified for KCL */ +#ifndef HAVE_DEVCGROUP_CHECK_PERMISSION +#if defined(CONFIG_CGROUP_DEVICE) +extern int (*__kcl_devcgroup_check_permission)(short type, u32 major, u32 minor, + short access); + +static inline int _kcl_devcgroup_check_permission(short type, u32 major, u32 minor, + short access) +{ +#ifdef BPF_CGROUP_RUN_PROG_DEVICE_CGROUP + int rc = BPF_CGROUP_RUN_PROG_DEVICE_CGROUP(type, major, minor, access); + + if (rc) + return -EPERM; +#endif + + return __kcl_devcgroup_check_permission(type, major, minor, access); +} +#else +static inline int _kcl_devcgroup_check_permission(short type, u32 major, u32 minor, + short access) +{ + return 0; +} +#endif /* CONFIG_CGROUP_DEVICE */ +#endif /* HAVE_DEVCGROUP_CHECK_PERMISSION */ + +#endif /* AMDKCL_DEVICE_CGROUP_H */ From 11d9ea02094979dfdb23026b5e85e74ba37ecdff Mon Sep 17 00:00:00 2001 From: Junwei Zhang Date: Mon, 18 Feb 2019 10:45:06 +0800 Subject: [PATCH 0149/1868] drm/amdkcl: Test whether mmu_notifier_call_srcu() is available It's a squash of 1d849edd9801 drm/amdkcl: Test whether mmu_notifier_call_srcu() is available fd62e7af6cd9 drm/amdkcl: refactor mmu_notifier_unregister_no_release() c1f004d6344b drm/amdkcl: fix license for kcl part Signed-off-by: Junwei Zhang Reviewed-by: Qiang Yu Signed-off-by: Jack Gui Signed-off-by: Anatoli Antonovitch Signed-off-by: Yifan Zhang Signed-off-by: Flora Cui Signed-off-by: Slava Grigorev Signed-off-by: Flora Cui Reviewed-by: Yang Xiong Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_mn.c | 43 +++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../drm/amd/dkms/m4/mmu-notifier-call-srcu.m4 | 18 ++++++++ include/kcl/kcl_mn.h | 16 +++++++ 6 files changed, 80 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_mn.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/mmu-notifier-call-srcu.m4 create mode 100644 include/kcl/kcl_mn.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index e0736cc39adb9..dd2587a0a67ee 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -10,7 +10,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_fence.o kcl_fence_array.o kcl_reservation.o kcl_drm_cache.o \ kcl_drm_fb.o kcl_drm_print.o kcl_fbmem.o \ kcl_drm_crtc.o kcl_connector.o \ - kcl_device_cgroup.o + kcl_device_cgroup.o kcl_mn.o CFLAGS_kcl_fence.o := -I$(src) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_mn.c b/drivers/gpu/drm/amd/amdkcl/kcl_mn.c new file mode 100644 index 0000000000000..20a0c2c5a9280 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_mn.c @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0 +#include +#include +#include +#include +#include + +/* Copied from v3.16-6588-gb972216e27d1 mm/mmu_notifier.c */ +#if !defined(HAVE_MMU_NOTIFIER_CALL_SRCU) && \ + !defined(HAVE_MMU_NOTIFIER_PUT) +/* + * Modifications [2017-03-14] (c) [2017] + */ + +/* + * This function allows mmu_notifier::release callback to delay a call to + * a function that will free appropriate resources. The function must be + * quick and must not block. + */ +void mmu_notifier_call_srcu(struct rcu_head *rcu, + void (*func)(struct rcu_head *rcu)) +{ + /* changed from call_srcu to call_rcu */ + call_rcu(rcu, func); +} +EXPORT_SYMBOL_GPL(mmu_notifier_call_srcu); + +void mmu_notifier_unregister_no_release(struct mmu_notifier *mn, + struct mm_struct *mm) +{ + spin_lock(&mm->mmu_notifier_mm->lock); + /* + * Can not use list_del_rcu() since __mmu_notifier_release + * can delete it before we hold the lock. + */ + hlist_del_init_rcu(&mn->hlist); + spin_unlock(&mm->mmu_notifier_mm->lock); + + BUG_ON(atomic_read(&mm->mm_count) <= 0); + mmdrop(mm); +} +EXPORT_SYMBOL_GPL(mmu_notifier_unregister_no_release); +#endif diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 6ad8181770628..499bef7ff56a2 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -33,6 +33,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 6cfbed4fb46bb..d02e92e074b9c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -43,6 +43,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_VMF_INSERT_MIXED_PROT AC_AMDGPU_VMF_INSERT_PFN_PROT AC_AMDGPU_MMU_NOTIFIER + AC_AMDGPU_MMU_NOTIFIER_CALL_SRCU AC_AMDGPU_MM_RELEASE_PAGES AC_AMDGPU_SCHED_SET_FIFO_LOW AC_AMDGPU_DMA_FENCE_HEADERS diff --git a/drivers/gpu/drm/amd/dkms/m4/mmu-notifier-call-srcu.m4 b/drivers/gpu/drm/amd/dkms/m4/mmu-notifier-call-srcu.m4 new file mode 100644 index 0000000000000..8b1aad73065f7 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/mmu-notifier-call-srcu.m4 @@ -0,0 +1,18 @@ +dnl # commit b972216e27d1c853eced33f8638926636c606341 +dnl # mmu_notifier: add call_srcu and sync function +dnl # for listener to delay call and sync +dnl # +dnl # commit v5.3-rc5-63-gc96245148c1e +dnl # mm/mmu_notifiers: remove unregister_no_release +dnl # +AC_DEFUN([AC_AMDGPU_MMU_NOTIFIER_CALL_SRCU], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + mmu_notifier_call_srcu(NULL, NULL); + ],[ + AC_DEFINE(HAVE_MMU_NOTIFIER_CALL_SRCU, 1, [mmu_notifier_call_srcu() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_mn.h b/include/kcl/kcl_mn.h new file mode 100644 index 0000000000000..02e80c3b4e386 --- /dev/null +++ b/include/kcl/kcl_mn.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_MN_H +#define AMDKCL_MN_H + +#include + +/* Copied from v3.16-6588-gb972216e27d1 include/linux/mmu_notifier.h */ +#if !defined(HAVE_MMU_NOTIFIER_CALL_SRCU) && \ + !defined(HAVE_MMU_NOTIFIER_PUT) +extern void mmu_notifier_call_srcu(struct rcu_head *rcu, + void (*func)(struct rcu_head *rcu)); +extern void mmu_notifier_unregister_no_release(struct mmu_notifier *mn, + struct mm_struct *mm); +#endif + +#endif /* AMDKCL_MN_H */ From 131274552e27ebb68f6ca9ae0bce059ffe500964 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 1 Jun 2020 12:48:26 +0800 Subject: [PATCH 0150/1868] drm/amdkcl: fake drm_atomic_helper_plane_reset to commit v4.19-rc1-206-ge267364a6e1b. v2: 69a65a9c531c drm/amdkcl: fix license for kcl drm part Signed-off-by: Flora Cui Acked-by: Rodrigo Siqueira Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- .../drm/amd/amdkcl/kcl_drm_atomic_helper.c | 48 +++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + .../backport/kcl_drm_atomic_helper_backport.h | 11 +++++ include/kcl/kcl_drm_atomic_helper.h | 47 ++++++++++++++++++ 5 files changed, 108 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c create mode 100644 include/kcl/backport/kcl_drm_atomic_helper_backport.h create mode 100644 include/kcl/kcl_drm_atomic_helper.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index dd2587a0a67ee..065f205b662a8 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -9,7 +9,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_suspend.o kcl_pci.o kcl_mm.o kcl_memory.o kcl_sched.o \ kcl_fence.o kcl_fence_array.o kcl_reservation.o kcl_drm_cache.o \ kcl_drm_fb.o kcl_drm_print.o kcl_fbmem.o \ - kcl_drm_crtc.o kcl_connector.o \ + kcl_drm_crtc.o kcl_connector.o kcl_drm_atomic_helper.o \ kcl_device_cgroup.o kcl_mn.o CFLAGS_kcl_fence.o := -I$(src) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c new file mode 100644 index 0000000000000..c6c37ceca85c8 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2018 Intel Corp. + * Copyright (C) 2014 Red Hat + * Copyright (C) 2014 Intel Corp. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Rob Clark + * Daniel Vetter + */ +#include +#include + +#ifdef AMDKCL__DRM_ATOMIC_HELPER_PLANE_RESET +void _kcl__drm_atomic_helper_plane_reset(struct drm_plane *plane, + struct drm_plane_state *state) +{ + state->plane = plane; + state->rotation = DRM_MODE_ROTATE_0; + +#ifdef DRM_BLEND_ALPHA_OPAQUE + state->alpha = DRM_BLEND_ALPHA_OPAQUE; +#endif +#ifdef DRM_MODE_BLEND_PREMULTI + state->pixel_blend_mode = DRM_MODE_BLEND_PREMULTI; +#endif + + plane->state = state; +} +EXPORT_SYMBOL(_kcl__drm_atomic_helper_plane_reset); +#endif diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 499bef7ff56a2..68d11a14a5029 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -41,5 +41,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/backport/kcl_drm_atomic_helper_backport.h b/include/kcl/backport/kcl_drm_atomic_helper_backport.h new file mode 100644 index 0000000000000..bcb45b685a034 --- /dev/null +++ b/include/kcl/backport/kcl_drm_atomic_helper_backport.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef AMDKCL_DRM_ATOMIC_HELPER_BACKPORT_H +#define AMDKCL_DRM_ATOMIC_HELPER_BACKPORT_H + +#include + +#ifdef AMDKCL__DRM_ATOMIC_HELPER_PLANE_RESET +#define __drm_atomic_helper_plane_reset _kcl__drm_atomic_helper_plane_reset +#endif /* AMDKCL__DRM_ATOMIC_HELPER_PLANE_RESET */ + +#endif diff --git a/include/kcl/kcl_drm_atomic_helper.h b/include/kcl/kcl_drm_atomic_helper.h new file mode 100644 index 0000000000000..661b8cd643ff2 --- /dev/null +++ b/include/kcl/kcl_drm_atomic_helper.h @@ -0,0 +1,47 @@ +/* + * Copyright (C) 2014 Red Hat + * Copyright (C) 2014 Intel Corp. + * Copyright (C) 2018 Intel Corp. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Rob Clark + * Daniel Vetter + */ +#ifndef AMDKCL_DRM_ATOMIC_HELPER_H +#define AMDKCL_DRM_ATOMIC_HELPER_H + +#include +#include +#include +#include +#include + +/* + * v4.19-rc1-206-ge267364a6e1b + * drm/atomic: Initialise planes with opaque alpha values + */ +#if DRM_VERSION_CODE < DRM_VERSION(4, 20, 0) +#define AMDKCL__DRM_ATOMIC_HELPER_PLANE_RESET +void _kcl__drm_atomic_helper_plane_reset(struct drm_plane *plane, + struct drm_plane_state *state); +#endif + +#endif From a3aa67e0ed68c7f41ccd5beb114d47b6a79cfbf0 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 22 Sep 2020 11:02:03 +0800 Subject: [PATCH 0151/1868] drm/amdkcl: test __drm_atomic_helper_crtc_reset() is available Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c | 13 +++++++++++++ .../amd/dkms/m4/__drm_atomic_helper_crtc_reset.m4 | 14 ++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_atomic_helper.h | 5 +++++ 4 files changed, 33 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/__drm_atomic_helper_crtc_reset.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c index c6c37ceca85c8..c11911f2dcbc8 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c @@ -46,3 +46,16 @@ void _kcl__drm_atomic_helper_plane_reset(struct drm_plane *plane, } EXPORT_SYMBOL(_kcl__drm_atomic_helper_plane_reset); #endif + +#ifndef HAVE___DRM_ATOMIC_HELPER_CRTC_RESET +void +__drm_atomic_helper_crtc_reset(struct drm_crtc *crtc, + struct drm_crtc_state *crtc_state) +{ + if (crtc_state) + crtc_state->crtc = crtc; + + crtc->state = crtc_state; +} +EXPORT_SYMBOL(__drm_atomic_helper_crtc_reset); +#endif diff --git a/drivers/gpu/drm/amd/dkms/m4/__drm_atomic_helper_crtc_reset.m4 b/drivers/gpu/drm/amd/dkms/m4/__drm_atomic_helper_crtc_reset.m4 new file mode 100644 index 0000000000000..637a0bc453cd7 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/__drm_atomic_helper_crtc_reset.m4 @@ -0,0 +1,14 @@ +dnl # +dnl # v5.1-rc2-1163-g7d26097b4beb +dnl # drm/atomic: Create __drm_atomic_helper_crtc_reset() for subclassing crtc_state. +dnl # +AC_DEFUN([AC_AMDGPU___DRM_ATOMIC_HELPER_CRTC_RESET], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([__drm_atomic_helper_crtc_reset], + [drivers/gpu/drm/drm_atomic_state_helper.c], + [ + AC_DEFINE(HAVE___DRM_ATOMIC_HELPER_CRTC_RESET, 1, + [__drm_atomic_helper_crtc_reset() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index d02e92e074b9c..5be2f1a8cbabb 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -61,6 +61,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS AC_AMDGPU_DRM_DP_CEC_CORRELATION_FUNCTIONS AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_RESUME + AC_AMDGPU___DRM_ATOMIC_HELPER_CRTC_RESET AC_AMDGPU_KTHREAD_USE_MM AC_AMDGPU_DRM_DEBUG_PRINTER AC_AMDGPU_DRM_FB_HELPER_FILL_INFO diff --git a/include/kcl/kcl_drm_atomic_helper.h b/include/kcl/kcl_drm_atomic_helper.h index 661b8cd643ff2..cb5c49c24cb94 100644 --- a/include/kcl/kcl_drm_atomic_helper.h +++ b/include/kcl/kcl_drm_atomic_helper.h @@ -44,4 +44,9 @@ void _kcl__drm_atomic_helper_plane_reset(struct drm_plane *plane, struct drm_plane_state *state); #endif +#ifndef HAVE___DRM_ATOMIC_HELPER_CRTC_RESET +void __drm_atomic_helper_crtc_reset(struct drm_crtc *crtc, + struct drm_crtc_state *crtc_state); +#endif + #endif From f934387ccc89ef2ed19455fd7b29f00002d2e899 Mon Sep 17 00:00:00 2001 From: Bhawanpreet Lakha Date: Fri, 31 Jul 2020 17:56:07 -0400 Subject: [PATCH 0152/1868] drm/amdkcl: Enable HDCP Build by default Add HDCP config flag to the makefile It's a squash of drm/amdkcl: test whether drm_hdcp_update_content_protection is available drm/amdkcl: add kcl/kcl_drm_hdcp.h drm/amdkcl: test drm_hdcp.h for enabling hdcp Signed-off-by: Yang Xiong Reviewed-by: Flora Cui Acked-by: Bhawanpreet Lakha drm/amdkcl: fix missing CONFIG_DRM_AMD_DC_HDCP check Signed-off-by: Rui Teng Reviewed-by: Jack Gui drm/amdkcl: move hdcp related stuff to kcl_drm_hdcp.c and fix license Reviewed-by: Shiwu Zhang Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling Signed-off-by: Bhawanpreet Lakha Signed-off-by: Yang Xiong Reviewed-by: Flora Cui Change-Id: Iecbc2d3cefce447cbb2a1cc10703fea226a469e5 --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 + drivers/gpu/drm/amd/amdkcl/kcl_drm_hdcp.c | 25 ++ drivers/gpu/drm/amd/backport/backport.h | 1 + .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 + drivers/gpu/drm/amd/dkms/Makefile | 4 + .../m4/drm-hdcp-update-content-protection.m4 | 16 + drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_hdcp.h | 316 ++++++++++++++++++ 8 files changed, 368 insertions(+) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_hdcp.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-hdcp-update-content-protection.m4 create mode 100644 include/kcl/kcl_drm_hdcp.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 065f205b662a8..b49fb6e31328d 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -12,6 +12,8 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_drm_crtc.o kcl_connector.o kcl_drm_atomic_helper.o \ kcl_device_cgroup.o kcl_mn.o +amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o + CFLAGS_kcl_fence.o := -I$(src) ccflags-y += \ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_hdcp.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_hdcp.c new file mode 100644 index 0000000000000..21686ff9a5950 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_hdcp.c @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Intel Corporation. + * + * Authors: + * Ramalingam C + */ +#include + +#ifndef HAVE_DRM_HDCP_UPDATE_CONTENT_PROTECTION +/* Copied from v5.3-rc1-380-gbb5a45d40d50 drivers/gpu/drm/drm_hdcp.c */ +void _kcl_drm_hdcp_update_content_protection(struct drm_connector *connector, + u64 val) +{ + struct drm_device *dev = connector->dev; + struct drm_connector_state *state = connector->state; + + WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); + if (state->content_protection == val) + return; + + state->content_protection = val; +} +EXPORT_SYMBOL(_kcl_drm_hdcp_update_content_protection); +#endif diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 68d11a14a5029..0af51f73cf470 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -42,5 +42,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 4916accf5ffbd..e632410ef3a56 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -96,6 +96,9 @@ #include #include #include +#ifdef CONFIG_DRM_AMD_DC_HDCP +#include +#endif #include diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index dbace6b3bc0ae..25f48546e8d01 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -156,6 +156,10 @@ subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_USERPTR subdir-ccflags-y += -DCONFIG_DRM_AMD_DC subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN1_0 +ifeq ($(shell grep "HAVE_DRM_DRM_HDCP_H" $(src)/amd/dkms/config/config.h | grep -q "define" && echo "y" || echo "n"),y) +export CONFIG_DRM_AMD_DC_HDCP=y +subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_HDCP +endif # Trying to enable DCN2/3 with core2 optimizations will result in # older versions of GCC hanging during building/installing. Check diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-hdcp-update-content-protection.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-hdcp-update-content-protection.m4 new file mode 100644 index 0000000000000..5b8c871002830 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-hdcp-update-content-protection.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.3-rc1-380-gbb5a45d40d50 +dnl # drm/hdcp: update content protection property with uevent +dnl # +AC_DEFUN([AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_hdcp_update_content_protection(NULL, 0); + ], [ + AC_DEFINE(HAVE_DRM_HDCP_UPDATE_CONTENT_PROTECTION, 1, + [drm_hdcp_update_content_protection is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 5be2f1a8cbabb..ab625eda42a47 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -62,6 +62,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_CEC_CORRELATION_FUNCTIONS AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_RESUME AC_AMDGPU___DRM_ATOMIC_HELPER_CRTC_RESET + AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION AC_AMDGPU_KTHREAD_USE_MM AC_AMDGPU_DRM_DEBUG_PRINTER AC_AMDGPU_DRM_FB_HELPER_FILL_INFO diff --git a/include/kcl/kcl_drm_hdcp.h b/include/kcl/kcl_drm_hdcp.h new file mode 100644 index 0000000000000..ba77fb5c0973a --- /dev/null +++ b/include/kcl/kcl_drm_hdcp.h @@ -0,0 +1,316 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright (C) 2017 Google, Inc. + * + * Authors: + * Sean Paul + */ +#ifndef AMDKCL_DRM_HDCP_H +#define AMDKCL_DRM_HDCP_H + +#ifdef CONFIG_DRM_AMD_DC_HDCP +#include +#include + +/* changed in v4.16-rc7-1717-gb8e47d87be65 + * drm: Fix HDCP downstream dev count read + */ +#ifdef DRM_HDCP_NUM_DOWNSTREAM +#undef DRM_HDCP_NUM_DOWNSTREAM +#define DRM_HDCP_NUM_DOWNSTREAM(x) (x & 0x7f) +#endif + +/* introduced in v5.3-rc1-377-g7672dbba85d3 + * drm: Add Content protection type property + */ +#ifndef DRM_MODE_HDCP_CONTENT_TYPE0 +#define DRM_MODE_HDCP_CONTENT_TYPE0 0 +#define DRM_MODE_HDCP_CONTENT_TYPE1 1 +#endif + +/* introduced in v4.19-rc2-1221-gaf5aad059885 + * drm: hdcp2.2 authentication msg definitions + */ +#ifndef DRM_HDCP_1_4_SRM_ID +#define DRM_HDCP_1_4_SRM_ID 0x8 +#define DRM_HDCP_1_4_VRL_LENGTH_SIZE 3 +#define DRM_HDCP_1_4_DCP_SIG_SIZE 40 + +/* Protocol message definition for HDCP2.2 specification */ +/* + * Protected content streams are classified into 2 types: + * - Type0: Can be transmitted with HDCP 1.4+ + * - Type1: Can be transmitted with HDCP 2.2+ + */ +#define HDCP_STREAM_TYPE0 0x00 +#define HDCP_STREAM_TYPE1 0x01 + +/* HDCP2.2 Msg IDs */ +#define HDCP_2_2_NULL_MSG 1 +#define HDCP_2_2_AKE_INIT 2 +#define HDCP_2_2_AKE_SEND_CERT 3 +#define HDCP_2_2_AKE_NO_STORED_KM 4 +#define HDCP_2_2_AKE_STORED_KM 5 +#define HDCP_2_2_AKE_SEND_HPRIME 7 +#define HDCP_2_2_AKE_SEND_PAIRING_INFO 8 +#define HDCP_2_2_LC_INIT 9 +#define HDCP_2_2_LC_SEND_LPRIME 10 +#define HDCP_2_2_SKE_SEND_EKS 11 +#define HDCP_2_2_REP_SEND_RECVID_LIST 12 +#define HDCP_2_2_REP_SEND_ACK 15 +#define HDCP_2_2_REP_STREAM_MANAGE 16 +#define HDCP_2_2_REP_STREAM_READY 17 +#define HDCP_2_2_ERRATA_DP_STREAM_TYPE 50 + +#define HDCP_2_2_RTX_LEN 8 +#define HDCP_2_2_RRX_LEN 8 + +#define HDCP_2_2_K_PUB_RX_MOD_N_LEN 128 +#define HDCP_2_2_K_PUB_RX_EXP_E_LEN 3 +#define HDCP_2_2_K_PUB_RX_LEN (HDCP_2_2_K_PUB_RX_MOD_N_LEN + \ + HDCP_2_2_K_PUB_RX_EXP_E_LEN) + +#define HDCP_2_2_DCP_LLC_SIG_LEN 384 + +#define HDCP_2_2_E_KPUB_KM_LEN 128 +#define HDCP_2_2_E_KH_KM_M_LEN (16 + 16) +#define HDCP_2_2_H_PRIME_LEN 32 +#define HDCP_2_2_E_KH_KM_LEN 16 +#define HDCP_2_2_RN_LEN 8 +#define HDCP_2_2_L_PRIME_LEN 32 +#define HDCP_2_2_E_DKEY_KS_LEN 16 +#define HDCP_2_2_RIV_LEN 8 +#define HDCP_2_2_SEQ_NUM_LEN 3 +#define HDCP_2_2_V_PRIME_HALF_LEN (HDCP_2_2_L_PRIME_LEN / 2) +#define HDCP_2_2_RECEIVER_ID_LEN DRM_HDCP_KSV_LEN +#define HDCP_2_2_MAX_DEVICE_COUNT 31 +#define HDCP_2_2_RECEIVER_IDS_MAX_LEN (HDCP_2_2_RECEIVER_ID_LEN * \ + HDCP_2_2_MAX_DEVICE_COUNT) +#define HDCP_2_2_MPRIME_LEN 32 + +/* Following Macros take a byte at a time for bit(s) masking */ +/* + * TODO: This has to be changed for DP MST, as multiple stream on + * same port is possible. + * For HDCP2.2 on HDMI and DP SST this value is always 1. + */ +#define HDCP_2_2_MAX_CONTENT_STREAMS_CNT 1 +#define HDCP_2_2_TXCAP_MASK_LEN 2 +#define HDCP_2_2_RXCAPS_LEN 3 +#define HDCP_2_2_RX_REPEATER(x) ((x) & BIT(0)) +#define HDCP_2_2_DP_HDCP_CAPABLE(x) ((x) & BIT(1)) +#define HDCP_2_2_RXINFO_LEN 2 + +/* HDCP1.x compliant device in downstream */ +#define HDCP_2_2_HDCP1_DEVICE_CONNECTED(x) ((x) & BIT(0)) + +/* HDCP2.0 Compliant repeater in downstream */ +#define HDCP_2_2_HDCP_2_0_REP_CONNECTED(x) ((x) & BIT(1)) +#define HDCP_2_2_MAX_CASCADE_EXCEEDED(x) ((x) & BIT(2)) +#define HDCP_2_2_MAX_DEVS_EXCEEDED(x) ((x) & BIT(3)) +#define HDCP_2_2_DEV_COUNT_LO(x) (((x) & (0xF << 4)) >> 4) +#define HDCP_2_2_DEV_COUNT_HI(x) ((x) & BIT(0)) +#define HDCP_2_2_DEPTH(x) (((x) & (0x7 << 1)) >> 1) + +struct hdcp2_cert_rx { + u8 receiver_id[HDCP_2_2_RECEIVER_ID_LEN]; + u8 kpub_rx[HDCP_2_2_K_PUB_RX_LEN]; + u8 reserved[2]; + u8 dcp_signature[HDCP_2_2_DCP_LLC_SIG_LEN]; +} __packed; + +struct hdcp2_streamid_type { + u8 stream_id; + u8 stream_type; +} __packed; + +/* + * The TxCaps field specified in the HDCP HDMI, DP specs + * This field is big endian as specified in the errata. + */ +struct hdcp2_tx_caps { + /* Transmitter must set this to 0x2 */ + u8 version; + + /* Reserved for HDCP and DP Spec. Read as Zero */ + u8 tx_cap_mask[HDCP_2_2_TXCAP_MASK_LEN]; +} __packed; + +/* Main structures for HDCP2.2 protocol communication */ +struct hdcp2_ake_init { + u8 msg_id; + u8 r_tx[HDCP_2_2_RTX_LEN]; + struct hdcp2_tx_caps tx_caps; +} __packed; + +struct hdcp2_ake_send_cert { + u8 msg_id; + struct hdcp2_cert_rx cert_rx; + u8 r_rx[HDCP_2_2_RRX_LEN]; + u8 rx_caps[HDCP_2_2_RXCAPS_LEN]; +} __packed; + +struct hdcp2_ake_no_stored_km { + u8 msg_id; + u8 e_kpub_km[HDCP_2_2_E_KPUB_KM_LEN]; +} __packed; + +struct hdcp2_ake_stored_km { + u8 msg_id; + u8 e_kh_km_m[HDCP_2_2_E_KH_KM_M_LEN]; +} __packed; + +struct hdcp2_ake_send_hprime { + u8 msg_id; + u8 h_prime[HDCP_2_2_H_PRIME_LEN]; +} __packed; + +struct hdcp2_ake_send_pairing_info { + u8 msg_id; + u8 e_kh_km[HDCP_2_2_E_KH_KM_LEN]; +} __packed; + +struct hdcp2_lc_init { + u8 msg_id; + u8 r_n[HDCP_2_2_RN_LEN]; +} __packed; + +struct hdcp2_lc_send_lprime { + u8 msg_id; + u8 l_prime[HDCP_2_2_L_PRIME_LEN]; +} __packed; + +struct hdcp2_ske_send_eks { + u8 msg_id; + u8 e_dkey_ks[HDCP_2_2_E_DKEY_KS_LEN]; + u8 riv[HDCP_2_2_RIV_LEN]; +} __packed; + +struct hdcp2_rep_send_receiverid_list { + u8 msg_id; + u8 rx_info[HDCP_2_2_RXINFO_LEN]; + u8 seq_num_v[HDCP_2_2_SEQ_NUM_LEN]; + u8 v_prime[HDCP_2_2_V_PRIME_HALF_LEN]; + u8 receiver_ids[HDCP_2_2_RECEIVER_IDS_MAX_LEN]; +} __packed; + +struct hdcp2_rep_send_ack { + u8 msg_id; + u8 v[HDCP_2_2_V_PRIME_HALF_LEN]; +} __packed; + +struct hdcp2_rep_stream_manage { + u8 msg_id; + u8 seq_num_m[HDCP_2_2_SEQ_NUM_LEN]; + __be16 k; + struct hdcp2_streamid_type streams[HDCP_2_2_MAX_CONTENT_STREAMS_CNT]; +} __packed; + +struct hdcp2_rep_stream_ready { + u8 msg_id; + u8 m_prime[HDCP_2_2_MPRIME_LEN]; +} __packed; + +struct hdcp2_dp_errata_stream_type { + u8 msg_id; + u8 stream_type; +} __packed; +#endif /* DRM_HDCP_1_4_SRM_ID */ + +/* introduced in v4.19-rc2-1222-g8b44fefee694 + * drm: HDMI and DP specific HDCP2.2 defines + */ +#ifndef HDCP_2_2_CERT_TIMEOUT_MS +/* HDCP2.2 TIMEOUTs in mSec */ +#define HDCP_2_2_CERT_TIMEOUT_MS 100 +#define HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS 1000 +#define HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS 200 +#define HDCP_2_2_PAIRING_TIMEOUT_MS 200 +#define HDCP_2_2_HDMI_LPRIME_TIMEOUT_MS 20 +#define HDCP_2_2_DP_LPRIME_TIMEOUT_MS 7 +#define HDCP_2_2_RECVID_LIST_TIMEOUT_MS 3000 +#define HDCP_2_2_STREAM_READY_TIMEOUT_MS 100 + +/* HDMI HDCP2.2 Register Offsets */ +#define HDCP_2_2_HDMI_REG_VER_OFFSET 0x50 +#define HDCP_2_2_HDMI_REG_WR_MSG_OFFSET 0x60 +#define HDCP_2_2_HDMI_REG_RXSTATUS_OFFSET 0x70 +#define HDCP_2_2_HDMI_REG_RD_MSG_OFFSET 0x80 +#define HDCP_2_2_HDMI_REG_DBG_OFFSET 0xC0 + +#define HDCP_2_2_HDMI_SUPPORT_MASK BIT(2) +#define HDCP_2_2_RX_CAPS_VERSION_VAL 0x02 +#define HDCP_2_2_SEQ_NUM_MAX 0xFFFFFF +#define HDCP_2_2_DELAY_BEFORE_ENCRYPTION_EN 200 + +/* Below macros take a byte at a time and mask the bit(s) */ +#define HDCP_2_2_HDMI_RXSTATUS_LEN 2 +#define HDCP_2_2_HDMI_RXSTATUS_MSG_SZ_HI(x) ((x) & 0x3) +#define HDCP_2_2_HDMI_RXSTATUS_READY(x) ((x) & BIT(2)) +#define HDCP_2_2_HDMI_RXSTATUS_REAUTH_REQ(x) ((x) & BIT(3)) +/* DP HDCP2.2 parameter offsets in DPCD address space */ +#define DP_HDCP_2_2_REG_RTX_OFFSET 0x69000 +#define DP_HDCP_2_2_REG_TXCAPS_OFFSET 0x69008 +#define DP_HDCP_2_2_REG_CERT_RX_OFFSET 0x6900B +#define DP_HDCP_2_2_REG_RRX_OFFSET 0x69215 +#define DP_HDCP_2_2_REG_RX_CAPS_OFFSET 0x6921D +#define DP_HDCP_2_2_REG_EKPUB_KM_OFFSET 0x69220 +#define DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET 0x692A0 +#define DP_HDCP_2_2_REG_M_OFFSET 0x692B0 +#define DP_HDCP_2_2_REG_HPRIME_OFFSET 0x692C0 +#define DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET 0x692E0 +#define DP_HDCP_2_2_REG_RN_OFFSET 0x692F0 +#define DP_HDCP_2_2_REG_LPRIME_OFFSET 0x692F8 +#define DP_HDCP_2_2_REG_EDKEY_KS_OFFSET 0x69318 +#define DP_HDCP_2_2_REG_RIV_OFFSET 0x69328 +#define DP_HDCP_2_2_REG_RXINFO_OFFSET 0x69330 +#define DP_HDCP_2_2_REG_SEQ_NUM_V_OFFSET 0x69332 +#define DP_HDCP_2_2_REG_VPRIME_OFFSET 0x69335 +#define DP_HDCP_2_2_REG_RECV_ID_LIST_OFFSET 0x69345 +#define DP_HDCP_2_2_REG_V_OFFSET 0x693E0 +#define DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET 0x693F0 +#define DP_HDCP_2_2_REG_K_OFFSET 0x693F3 +#define DP_HDCP_2_2_REG_STREAM_ID_TYPE_OFFSET 0x693F5 +#define DP_HDCP_2_2_REG_MPRIME_OFFSET 0x69473 +#define DP_HDCP_2_2_REG_RXSTATUS_OFFSET 0x69493 +#define DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET 0x69494 +#define DP_HDCP_2_2_REG_DBG_OFFSET 0x69518 + +/* DP HDCP message start offsets in DPCD address space */ +#define DP_HDCP_2_2_AKE_INIT_OFFSET DP_HDCP_2_2_REG_RTX_OFFSET +#define DP_HDCP_2_2_AKE_SEND_CERT_OFFSET DP_HDCP_2_2_REG_CERT_RX_OFFSET +#define DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET DP_HDCP_2_2_REG_EKPUB_KM_OFFSET +#define DP_HDCP_2_2_AKE_STORED_KM_OFFSET DP_HDCP_2_2_REG_EKH_KM_WR_OFFSET +#define DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET DP_HDCP_2_2_REG_HPRIME_OFFSET +#define DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET \ + DP_HDCP_2_2_REG_EKH_KM_RD_OFFSET +#define DP_HDCP_2_2_LC_INIT_OFFSET DP_HDCP_2_2_REG_RN_OFFSET +#define DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET DP_HDCP_2_2_REG_LPRIME_OFFSET +#define DP_HDCP_2_2_SKE_SEND_EKS_OFFSET DP_HDCP_2_2_REG_EDKEY_KS_OFFSET +#define DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET DP_HDCP_2_2_REG_RXINFO_OFFSET +#define DP_HDCP_2_2_REP_SEND_ACK_OFFSET DP_HDCP_2_2_REG_V_OFFSET +#define DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET DP_HDCP_2_2_REG_SEQ_NUM_M_OFFSET +#define DP_HDCP_2_2_REP_STREAM_READY_OFFSET DP_HDCP_2_2_REG_MPRIME_OFFSET + +#define HDCP_2_2_DP_RXSTATUS_LEN 1 +#define HDCP_2_2_DP_RXSTATUS_READY(x) ((x) & BIT(0)) +#define HDCP_2_2_DP_RXSTATUS_H_PRIME(x) ((x) & BIT(1)) +#define HDCP_2_2_DP_RXSTATUS_PAIRING(x) ((x) & BIT(2)) +#define HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(x) ((x) & BIT(3)) +#define HDCP_2_2_DP_RXSTATUS_LINK_FAILED(x) ((x) & BIT(4)) +#endif /* HDCP_2_2_CERT_TIMEOUT_MS */ + +#ifndef HAVE_DRM_HDCP_UPDATE_CONTENT_PROTECTION +void _kcl_drm_hdcp_update_content_protection(struct drm_connector *connector, + u64 val); +static inline +void drm_hdcp_update_content_protection(struct drm_connector *connector, + u64 val) +{ + _kcl_drm_hdcp_update_content_protection(connector, val); +} +#endif /* HAVE_DRM_HDCP_UPDATE_CONTENT_PROTECTION */ + +#endif /* CONFIG_DRM_AMD_DC_HDCP */ + +#endif /* AMDKCL_DRM_HDCP_H */ From c49f0b752ee8aa0f5581b89f5a19dc8a1024a546 Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Mon, 21 Sep 2020 19:13:19 +0800 Subject: [PATCH 0153/1868] drm/amdkcl: test mem_encrypt_active() is available fake a kcl copy if not available. mem_encrypt_active() is introduced in v4.14-rc8-89-gd8aa7eea78a1 This patch is introduced by v5.9-rc2-389-gc2bc2643976e 'drm/amdgpu/dc: Fail to load on RAVEN if SME is active' v2: c1f004d6344b drm/amdkcl: fix license for kcl part Signed-off-by: Shiwu Zhang Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling Change-Id: Ia5e4eab8c3362d76ca6a40e635271f3f4f4644e9 --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../gpu/drm/amd/dkms/m4/mem_encrypt_active.m4 | 16 ++++++++++++ include/kcl/kcl_dma_mapping.h | 1 + include/kcl/kcl_mem_encrypt.h | 26 +++++++++++++++++++ 4 files changed, 44 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/mem_encrypt_active.m4 create mode 100644 include/kcl/kcl_mem_encrypt.h diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index ab625eda42a47..f8049c2cee34e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -63,6 +63,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_RESUME AC_AMDGPU___DRM_ATOMIC_HELPER_CRTC_RESET AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION + AC_AMDGPU_MEM_ENCRYPT_ACTIVE AC_AMDGPU_KTHREAD_USE_MM AC_AMDGPU_DRM_DEBUG_PRINTER AC_AMDGPU_DRM_FB_HELPER_FILL_INFO diff --git a/drivers/gpu/drm/amd/dkms/m4/mem_encrypt_active.m4 b/drivers/gpu/drm/amd/dkms/m4/mem_encrypt_active.m4 new file mode 100644 index 0000000000000..ad484a873022a --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/mem_encrypt_active.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v4.14-rc8-89-gd8aa7eea78a1 +dnl # x86/mm: Add Secure Encrypted Virtualization (SEV) support +dnl # +AC_DEFUN([AC_AMDGPU_MEM_ENCRYPT_ACTIVE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + mem_encrypt_active(); + ], [ + AC_DEFINE(HAVE_MEM_ENCRYPT_ACTIVE, 1, + [mem_encrypt_active() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_dma_mapping.h b/include/kcl/kcl_dma_mapping.h index c7de48cd9aad7..1b7609d8ee876 100644 --- a/include/kcl/kcl_dma_mapping.h +++ b/include/kcl/kcl_dma_mapping.h @@ -3,6 +3,7 @@ #define AMDKCL_DMA_MAPPING_H #include +#include /* * commit v4.8-11962-ga9a62c938441 diff --git a/include/kcl/kcl_mem_encrypt.h b/include/kcl/kcl_mem_encrypt.h new file mode 100644 index 0000000000000..60d24e198587e --- /dev/null +++ b/include/kcl/kcl_mem_encrypt.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * AMD Memory Encryption Support + * + * Copyright (C) 2016 Advanced Micro Devices, Inc. + * + * Author: Tom Lendacky + */ +#ifndef KCL_KCL_MEM_ENCRYPT_H +#define KCL_KCL_MEM_ENCRYPT_H + +#ifdef HAVE_LINUX_MEM_ENCRYPT_H +#include +#ifndef HAVE_MEM_ENCRYPT_ACTIVE +static inline bool mem_encrypt_active(void) +{ + return sme_me_mask; +} +#endif +#else +static inline bool mem_encrypt_active(void) +{ + return false; +} +#endif +#endif From c4c21597deffc275934e4a67e733a61eaa5a7a0b Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 13 Oct 2020 08:54:27 +0800 Subject: [PATCH 0154/1868] drm/amdkcl: test jiffies64_to_msecs() fake a kcl copy for legacy kernel support. v2: c1f004d6344b drm/amdkcl: fix license for kcl part Signed-off-by: Flora Cui Reviewed-by: Guchun Chen Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_time.c | 40 +++++++++++++++++++ .../gpu/drm/amd/dkms/m4/jiffies64_to_msecs.m4 | 11 +++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_timekeeping.h | 4 ++ 5 files changed, 57 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_time.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/jiffies64_to_msecs.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index b49fb6e31328d..8089fe0c6b4f8 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -10,7 +10,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_fence.o kcl_fence_array.o kcl_reservation.o kcl_drm_cache.o \ kcl_drm_fb.o kcl_drm_print.o kcl_fbmem.o \ kcl_drm_crtc.o kcl_connector.o kcl_drm_atomic_helper.o \ - kcl_device_cgroup.o kcl_mn.o + kcl_device_cgroup.o kcl_mn.o kcl_time.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_time.c b/drivers/gpu/drm/amd/amdkcl/kcl_time.c new file mode 100644 index 0000000000000..a6394747da818 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_time.c @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 1991, 1992 Linus Torvalds + * + * This file contains the interface functions for the various time related + * system calls: time, stime, gettimeofday, settimeofday, adjtime + * + * Modification history: + * + * 1993-09-02 Philip Gladstone + * Created file with time related functions from sched/core.c and adjtimex() + * 1993-10-08 Torsten Duwe + * adjtime interface update and CMOS clock write code + * 1995-08-13 Torsten Duwe + * kernel PLL updated to 1994-12-13 specs (rfc-1589) + * 1999-01-16 Ulrich Windl + * Introduced error checking for many cases in adjtimex(). + * Updated NTP code according to technical memorandum Jan '96 + * "A Kernel Model for Precision Timekeeping" by Dave Mills + * Allow time_constant larger than MAXTC(6) for NTP v4 (MAXTC == 10) + * (Even though the technical memorandum forbids it) + * 2004-07-14 Christoph Lameter + * Added getnstimeofday to allow the posix timer functions to return + * with nanosecond accuracy + */ +#include +#include + +#ifndef HAVE_JIFFIES64_TO_MSECS +/* Copied from kernel/time/time.c */ +u64 jiffies64_to_msecs(const u64 j) +{ +#if HZ <= MSEC_PER_SEC && !(MSEC_PER_SEC % HZ) + return (MSEC_PER_SEC / HZ) * j; +#else + return div_u64(j * HZ_TO_MSEC_NUM, HZ_TO_MSEC_DEN); +#endif +} +EXPORT_SYMBOL(jiffies64_to_msecs); +#endif diff --git a/drivers/gpu/drm/amd/dkms/m4/jiffies64_to_msecs.m4 b/drivers/gpu/drm/amd/dkms/m4/jiffies64_to_msecs.m4 new file mode 100644 index 0000000000000..e44504998e830 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/jiffies64_to_msecs.m4 @@ -0,0 +1,11 @@ +dnl # +dnl # v5.1-rc3-699-g3b15d09f7e6d +dnl # time: Introduce jiffies64_to_msecs() +dnl # +AC_DEFUN([AC_AMDGPU_JIFFIES64_TO_MSECS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([jiffies64_to_msecs], [kernel/time/time.c], [ + AC_DEFINE(HAVE_JIFFIES64_TO_MSECS, 1, [jiffies64_to_msecs() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index f8049c2cee34e..5533f622938b9 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -64,6 +64,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU___DRM_ATOMIC_HELPER_CRTC_RESET AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION AC_AMDGPU_MEM_ENCRYPT_ACTIVE + AC_AMDGPU_JIFFIES64_TO_MSECS AC_AMDGPU_KTHREAD_USE_MM AC_AMDGPU_DRM_DEBUG_PRINTER AC_AMDGPU_DRM_FB_HELPER_FILL_INFO diff --git a/include/kcl/kcl_timekeeping.h b/include/kcl/kcl_timekeeping.h index 7c5bd5b28cb65..60b8c7fec82e5 100644 --- a/include/kcl/kcl_timekeeping.h +++ b/include/kcl/kcl_timekeeping.h @@ -54,4 +54,8 @@ static inline u64 ktime_get_mono_fast_ns(void) } #endif +#ifndef HAVE_JIFFIES64_TO_MSECS +extern u64 jiffies64_to_msecs(u64 j); +#endif + #endif From 14dcac7fd1ade348fbdabb8523ea33b96d50d520 Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Sun, 11 Oct 2020 20:22:47 +0800 Subject: [PATCH 0155/1868] drm/amdkcl: fake the __print_array macro for trace This is caused by "add new trace event for page table update" v5.9-rc2-514-g0fe7e2764d6f v2: calculate buf_len by count and el_size v3: use HAVE___PRINT_ARRAY instead of HAVE_FTRACE_PRINT_ARRAY_SEQ v4: fix license for kcl part Signed-off-by: Shiwu Zhang Reviewed-by: Flora Cui Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_ftrace.c | 56 +++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + .../drm/amd/dkms/m4/ftrace_print_array_seq.m4 | 23 ++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_ftrace.h | 17 ++++++ 6 files changed, 99 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_ftrace.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/ftrace_print_array_seq.m4 create mode 100644 include/kcl/kcl_ftrace.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 8089fe0c6b4f8..684f04edda134 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -10,7 +10,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_fence.o kcl_fence_array.o kcl_reservation.o kcl_drm_cache.o \ kcl_drm_fb.o kcl_drm_print.o kcl_fbmem.o \ kcl_drm_crtc.o kcl_connector.o kcl_drm_atomic_helper.o \ - kcl_device_cgroup.o kcl_mn.o kcl_time.o + kcl_device_cgroup.o kcl_mn.o kcl_time.o kcl_ftrace.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_ftrace.c b/drivers/gpu/drm/amd/amdkcl/kcl_ftrace.c new file mode 100644 index 0000000000000..115bdc26363a5 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_ftrace.c @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * trace_output.c + * + * Copyright (C) 2008 Red Hat Inc, Steven Rostedt + * + */ +#include + +/* Copied from v3.19-rc1-6-g6ea22486ba46 kernel/trace/trace_output.c */ +#if !defined(HAVE___PRINT_ARRAY) +const char * +ftrace_print_array_seq(struct trace_seq *p, const void *buf, int count, + size_t el_size) +{ + const char *ret = trace_seq_buffer_ptr(p); + const char *prefix = ""; + void *ptr = (void *)buf; + size_t buf_len = count * el_size; + + trace_seq_putc(p, '{'); + + while (ptr < buf + buf_len) { + switch (el_size) { + case 1: + trace_seq_printf(p, "%s0x%x", prefix, + *(u8 *)ptr); + break; + case 2: + trace_seq_printf(p, "%s0x%x", prefix, + *(u16 *)ptr); + break; + case 4: + trace_seq_printf(p, "%s0x%x", prefix, + *(u32 *)ptr); + break; + case 8: + trace_seq_printf(p, "%s0x%llx", prefix, + *(u64 *)ptr); + break; + default: + trace_seq_printf(p, "BAD SIZE:%zu 0x%x", el_size, + *(u8 *)ptr); + el_size = 1; + } + prefix = ","; + ptr += el_size; + } + + trace_seq_putc(p, '}'); + trace_seq_putc(p, 0); + + return ret; +} +EXPORT_SYMBOL(ftrace_print_array_seq); +#endif diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 0af51f73cf470..441239afe128f 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -43,5 +43,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/ftrace_print_array_seq.m4 b/drivers/gpu/drm/amd/dkms/m4/ftrace_print_array_seq.m4 new file mode 100644 index 0000000000000..ecc2aa76f18b1 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/ftrace_print_array_seq.m4 @@ -0,0 +1,23 @@ +dnl # +dnl # commit 0fe7e2764d6f +dnl # add new trace event for page table update +dnl # ftrace_print_array_seq() is exported in v3.19-rc1-6-g6ea22486ba46 +dnl # +AC_DEFUN([AC_AMDGPU___PRINT_ARRAY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([ftrace_print_array_seq], [kernel/trace/trace_output.c], [ + AC_DEFINE(HAVE___PRINT_ARRAY, 1, [__print_array is available]) + ], [ + dnl # + dnl # 645df987f7c + dnl # trace_print_array_seq() is exported in v4.1-rc3-8-g645df987f7c1 + dnl # + AC_KERNEL_CHECK_SYMBOL_EXPORT( + [trace_print_array_seq], + [kernel/trace/trace_output.c],[ + AC_DEFINE(HAVE___PRINT_ARRAY, 1, + [__print_array is available]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 5533f622938b9..9aa4b26097cae 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -65,6 +65,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION AC_AMDGPU_MEM_ENCRYPT_ACTIVE AC_AMDGPU_JIFFIES64_TO_MSECS + AC_AMDGPU___PRINT_ARRAY AC_AMDGPU_KTHREAD_USE_MM AC_AMDGPU_DRM_DEBUG_PRINTER AC_AMDGPU_DRM_FB_HELPER_FILL_INFO diff --git a/include/kcl/kcl_ftrace.h b/include/kcl/kcl_ftrace.h new file mode 100644 index 0000000000000..de98a0a5f345e --- /dev/null +++ b/include/kcl/kcl_ftrace.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_FTRACE_H +#define AMDKCL_FTRACE_H + +/* Copied from v3.19-rc1-6-g6ea22486ba46 include/trace/ftrace.h */ +#if !defined(HAVE___PRINT_ARRAY) +extern const char * ftrace_print_array_seq(struct trace_seq *p, const void *buf, int count, + size_t el_size); +#define __print_array(array, count, el_size) \ + ({ \ + BUILD_BUG_ON(el_size != 1 && el_size != 2 && \ + el_size != 4 && el_size != 8); \ + ftrace_print_array_seq(p, array, count, el_size); \ + }) +#endif + +#endif From 4cc066faf5b3e94f1e7e5c4467a12ca818e5ce6d Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Fri, 20 Nov 2020 14:53:01 +0800 Subject: [PATCH 0156/1868] drm/amdkcl: fake the acpi_put_table() This is caused by "Put ACPI table after using it" v5.9-rc5-1537-gc435d35df6c5 v2: c1f004d6344b drm/amdkcl: fix license for kcl part Signed-off-by: Shiwu Zhang Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkcl/Makefile | 3 ++- drivers/gpu/drm/amd/amdkcl/kcl_acpi_table.c | 15 +++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/acpi-put-table.m4 | 13 +++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_acpi_table.h | 18 ++++++++++++++++++ 6 files changed, 50 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_acpi_table.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/acpi-put-table.m4 create mode 100644 include/kcl/kcl_acpi_table.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 684f04edda134..fafb36606e287 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -10,7 +10,8 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_fence.o kcl_fence_array.o kcl_reservation.o kcl_drm_cache.o \ kcl_drm_fb.o kcl_drm_print.o kcl_fbmem.o \ kcl_drm_crtc.o kcl_connector.o kcl_drm_atomic_helper.o \ - kcl_device_cgroup.o kcl_mn.o kcl_time.o kcl_ftrace.o + kcl_device_cgroup.o kcl_mn.o kcl_time.o kcl_ftrace.o \ + kcl_acpi_table.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_acpi_table.c b/drivers/gpu/drm/amd/amdkcl/kcl_acpi_table.c new file mode 100644 index 0000000000000..554bebabd4adb --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_acpi_table.c @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 +/****************************************************************************** + * + * Module Name: tbxface - ACPI table-oriented external interfaces + * + * Copyright (C) 2000 - 2020, Intel Corp. + * + *****************************************************************************/ +#include +#include + +#ifndef HAVE_ACPI_PUT_TABLE +amdkcl_dummy_symbol(acpi_put_table, void, return, + struct acpi_table_header *table) +#endif diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 441239afe128f..a38fc43d61a54 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -44,5 +44,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/acpi-put-table.m4 b/drivers/gpu/drm/amd/dkms/m4/acpi-put-table.m4 new file mode 100644 index 0000000000000..27001acd98f95 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/acpi-put-table.m4 @@ -0,0 +1,13 @@ +dnl # +dnl # commit: v4.9-rc5-17-g174cc7187e6f +dnl # ACPICA: Tables: Back port acpi_get_table_with_size() and +dnl # early_acpi_os_unmap_memory() from Linux kernel +AC_DEFUN([AC_AMDGPU_ACPI_PUT_TABLE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([acpi_put_table], + [drivers/acpi/acpica/tbxface.c], [ + AC_DEFINE(HAVE_ACPI_PUT_TABLE, 1, + [acpi_put_table() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 9aa4b26097cae..ad80f9a980bfa 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -66,6 +66,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_MEM_ENCRYPT_ACTIVE AC_AMDGPU_JIFFIES64_TO_MSECS AC_AMDGPU___PRINT_ARRAY + AC_AMDGPU_ACPI_PUT_TABLE AC_AMDGPU_KTHREAD_USE_MM AC_AMDGPU_DRM_DEBUG_PRINTER AC_AMDGPU_DRM_FB_HELPER_FILL_INFO diff --git a/include/kcl/kcl_acpi_table.h b/include/kcl/kcl_acpi_table.h new file mode 100644 index 0000000000000..849e8a58a2dbd --- /dev/null +++ b/include/kcl/kcl_acpi_table.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */ +/****************************************************************************** + * + * Name: acpixf.h - External interfaces to the ACPI subsystem + * + * Copyright (C) 2000 - 2020, Intel Corp. + * + *****************************************************************************/ +#ifndef KCL_KCL_ACPI_TABLE_H +#define KCL_KCL_ACPI_TABLE_H + +#include + +#ifndef HAVE_ACPI_PUT_TABLE +void acpi_put_table(struct acpi_table_header *table); +#endif + +#endif From d13cfc3d897399307e5c0999a358fb2e84747db6 Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Tue, 8 Dec 2020 15:24:22 +0800 Subject: [PATCH 0157/1868] drm/amdkcl: fake drm_dbg_kms This is caused by "use drm_dbg_kms to log addfb2 failures" v5.9-rc5-1859-g16dba6910508 v2: copy the drm_dev_dbg implementation v3: add the autotest for drm_dev_dbg for sle sp2 support v4: drm/amdkcl: split drm_print stuff to kcl_drm_print.[ch] Signed-off-by: Shiwu Zhang Signed-off-by: Flora Cui Reviewed-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c | 26 ++++++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/drm_dev_dbg.m4 | 11 +++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_print.h | 9 ++++++++ 4 files changed, 47 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_dev_dbg.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c index 3b5945b8bee0a..3d690609edb8f 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c @@ -51,3 +51,29 @@ void __drm_printfn_debug(struct drm_printer *p, struct va_format *vaf) } EXPORT_SYMBOL(__drm_printfn_debug); #endif + +#if !defined(HAVE_DRM_DEV_DBG) +void drm_dev_dbg(const struct device *dev, int category, + const char *format, ...) +{ + struct va_format vaf; + va_list args; + + if (!drm_debug_enabled(category)) + return; + + va_start(args, format); + vaf.fmt = format; + vaf.va = &args; + + if (dev) + dev_printk(KERN_DEBUG, dev, "[" DRM_NAME ":%ps] %pV", + __builtin_return_address(0), &vaf); + else + printk(KERN_DEBUG "[" DRM_NAME ":%ps] %pV", + __builtin_return_address(0), &vaf); + + va_end(args); +} +EXPORT_SYMBOL(drm_dev_dbg); +#endif diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dev_dbg.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dev_dbg.m4 new file mode 100644 index 0000000000000..dfcc85e60e4bf --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dev_dbg.m4 @@ -0,0 +1,11 @@ +dnl # +dnl # v4.16-rc1-493-gdb8708649258 +dnl # drm: Reduce object size of DRM_DEV_ uses +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DEV_DBG], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([drm_dev_dbg], [drivers/gpu/drm/drm_print.c], [ + AC_DEFINE(HAVE_DRM_DEV_DBG, 1, [drm_dev_dbg() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index ad80f9a980bfa..911b9dce312b6 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -67,6 +67,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_JIFFIES64_TO_MSECS AC_AMDGPU___PRINT_ARRAY AC_AMDGPU_ACPI_PUT_TABLE + AC_AMDGPU_DRM_DEV_DBG AC_AMDGPU_KTHREAD_USE_MM AC_AMDGPU_DRM_DEBUG_PRINTER AC_AMDGPU_DRM_FB_HELPER_FILL_INFO diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index 65db884854a3d..3ead0ab2b367f 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -113,6 +113,15 @@ static inline struct drm_printer drm_debug_printer(const char *prefix) } while (0) #endif +#if !defined(HAVE_DRM_DEV_DBG) +void drm_dev_dbg(const struct device *dev, int category, const char *format, ...); +#endif + +#if !defined(drm_dbg_kms) +#define drm_dbg_kms(drm, fmt, ...) \ + drm_dev_dbg((drm)->dev, 0x04, fmt, ##__VA_ARGS__) +#endif + #ifndef HAVE_DRM_DEBUG_ENABLED /* Copied from v5.3-rc1-708-gf0a8f533adc2 include/drm/drm_print.h */ static inline bool drm_debug_enabled(unsigned int category) From 56ce4ffe84db06714e00409e1b882e6d1af4ed79 Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Thu, 17 Dec 2020 16:33:45 +0800 Subject: [PATCH 0158/1868] drm/amdkcl: fake pci_pr3_present This is caused by "add check for ACPI power resources" v5.9-rc5-1932-gad02c8dc25c1 v2: dummy the function if CONFIG_ACPI is not defined Signed-off-by: Shiwu Zhang Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/kcl_pci.c | 21 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../gpu/drm/amd/dkms/m4/pci_pr3_present.m4 | 11 ++++++++++ include/kcl/kcl_pci.h | 13 ++++++++++++ 4 files changed, 46 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/pci_pr3_present.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_pci.c b/drivers/gpu/drm/amd/amdkcl/kcl_pci.c index bf095e454ed06..171f3239eeb3a 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_pci.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_pci.c @@ -19,6 +19,7 @@ #include #include +#include #if !defined(HAVE_PCIE_BANDWIDTH_AVAILABLE) const unsigned char *_kcl_pcie_link_speed; @@ -297,3 +298,23 @@ void _kcl_pci_configure_extended_tags(struct pci_dev *dev) } EXPORT_SYMBOL(_kcl_pci_configure_extended_tags); #endif + +#ifndef HAVE_PCI_PR3_PRESENT +#ifdef CONFIG_ACPI +bool _kcl_pci_pr3_present(struct pci_dev *pdev) +{ + struct acpi_device *adev; + + if (acpi_disabled) + return false; + + adev = ACPI_COMPANION(&pdev->dev); + if (!adev) + return false; + + return adev->power.flags.power_resources && + acpi_has_method(adev->handle, "_PR3"); +} +EXPORT_SYMBOL_GPL(_kcl_pci_pr3_present); +#endif +#endif /* HAVE_PCI_PR3_PRESENT */ diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 911b9dce312b6..87b74110b702f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -68,6 +68,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU___PRINT_ARRAY AC_AMDGPU_ACPI_PUT_TABLE AC_AMDGPU_DRM_DEV_DBG + AC_AMDGPU_PCI_PR3_PRESENT AC_AMDGPU_KTHREAD_USE_MM AC_AMDGPU_DRM_DEBUG_PRINTER AC_AMDGPU_DRM_FB_HELPER_FILL_INFO diff --git a/drivers/gpu/drm/amd/dkms/m4/pci_pr3_present.m4 b/drivers/gpu/drm/amd/dkms/m4/pci_pr3_present.m4 new file mode 100644 index 0000000000000..38e50b2c0766f --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pci_pr3_present.m4 @@ -0,0 +1,11 @@ +dnl # +dnl # v5.4-rc2-37-g52525b7a3cf8 +dnl # PCI: Add a helper to check Power Resource Requirements _PR3 existence +dnl # +AC_DEFUN([AC_AMDGPU_PCI_PR3_PRESENT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([pci_pr3_present], [drivers/pci/pci.c], [ + AC_DEFINE(HAVE_PCI_PR3_PRESENT, 1, [pci_pr3_present() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_pci.h b/include/kcl/kcl_pci.h index 68246cdd08768..4eefafc20be1a 100644 --- a/include/kcl/kcl_pci.h +++ b/include/kcl/kcl_pci.h @@ -99,4 +99,17 @@ static inline u16 pci_dev_id(struct pci_dev *dev) return PCI_DEVID(dev->bus->number, dev->devfn); } #endif /* HAVE_PCI_DEV_ID */ + +#ifndef HAVE_PCI_PR3_PRESENT +#ifdef CONFIG_ACPI +bool _kcl_pci_pr3_present(struct pci_dev *pdev); +static inline bool pci_pr3_present(struct pci_dev *pdev) +{ + return _kcl_pci_pr3_present(pdev); +} +#else +static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; } +#endif +#endif /* HAVE_PCI_PR3_PRESENT */ + #endif /* AMDKCL_PCI_H */ From 9992da6762cbe7bcdd8a4ab98332068f5b370498 Mon Sep 17 00:00:00 2001 From: Adam Yang Date: Wed, 18 Sep 2019 21:55:54 +0800 Subject: [PATCH 0159/1868] drm/amdkcl: Test whether drm_helper_force_disable_all() is defined v2: drm/amdkcl: fix drm_helper_force_disable_all Signed-off-by: Adam Yang Signed-off-by: Flora Cui Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang --- .../gpu/drm/amd/dkms/m4/drm-crtc-helper.m4 | 20 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_crtc.h | 8 ++++++++ 3 files changed, 29 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-crtc-helper.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-crtc-helper.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-crtc-helper.m4 new file mode 100644 index 0000000000000..a0e32e7654867 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-crtc-helper.m4 @@ -0,0 +1,20 @@ +dnl # +dnl # commit f453ba0460742ad027ae0c4c7d61e62817b3e7ef +dnl # DRM: add mode setting support +dnl # +dnl # commit c2d88e06bcb98540bb83fac874574eaa4f320363 +dnl # drm: Move the legacy kms disable_all helper to crtc helpers +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CRTC_HELPER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_helper_force_disable_all(NULL); + ], [ + AC_DEFINE(HAVE_DRM_HELPER_FORCE_DISABLE_ALL, 1, + [drm_helper_force_disable_all() is available]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 87b74110b702f..a219e700c82a9 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -75,6 +75,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED AC_AMDGPU_DRM_HELPER_MODE_FILL_FB_STRUCT AC_AMDGPU_DRM_CRTC_FORCE_DISABLE_ALL + AC_AMDGPU_DRM_CRTC_HELPER AC_AMDGPU_DRM_EDID_TO_ELD AC_KERNEL_WAIT diff --git a/include/kcl/kcl_drm_crtc.h b/include/kcl/kcl_drm_crtc.h index 38861d70bd9bb..daca652324951 100644 --- a/include/kcl/kcl_drm_crtc.h +++ b/include/kcl/kcl_drm_crtc.h @@ -79,4 +79,12 @@ extern int drm_crtc_force_disable(struct drm_crtc *crtc); extern int drm_crtc_force_disable_all(struct drm_device *dev); #endif +#if !defined(HAVE_DRM_HELPER_FORCE_DISABLE_ALL) +static inline +int drm_helper_force_disable_all(struct drm_device *dev) +{ + return drm_crtc_force_disable_all(dev); +} +#endif + #endif From e542e3de2e621b70ca836cb0839dc413af5401fa Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 17 Dec 2020 16:30:35 +0800 Subject: [PATCH 0160/1868] drm/amdkcl: rework faked drm_helper_force_disable_all Signed-off-by: Flora Cui Reviewed-by: Shiwu Zhang --- drivers/gpu/drm/amd/amdkcl/kcl_drm_crtc.c | 57 ++++++------------- ...per.m4 => drm_helper_force_disable_all.m4} | 10 +--- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 3 +- include/kcl/kcl_drm_crtc.h | 8 +-- 4 files changed, 23 insertions(+), 55 deletions(-) rename drivers/gpu/drm/amd/dkms/m4/{drm-crtc-helper.m4 => drm_helper_force_disable_all.m4} (60%) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_crtc.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_crtc.c index 0dab372fcb93f..c4e079c49d8ab 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_crtc.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_crtc.c @@ -31,49 +31,26 @@ */ #include -#if !defined(HAVE_DRM_CRTC_FORCE_DISABLE_ALL) -/** - * drm_crtc_force_disable - Forcibly turn off a CRTC - * @crtc: CRTC to turn off - * - * Returns: - * Zero on success, error code on failure. - */ -int drm_crtc_force_disable(struct drm_crtc *crtc) +#ifndef HAVE_DRM_HELPER_FORCE_DISABLE_ALL +int _kcl_drm_helper_force_disable_all(struct drm_device *dev) { - struct drm_mode_set set = { - .crtc = crtc, - }; - - return drm_mode_set_config_internal(&set); -} -EXPORT_SYMBOL(drm_crtc_force_disable); + struct drm_crtc *crtc; + int ret = 0; -/** - * drm_crtc_force_disable_all - Forcibly turn off all enabled CRTCs - * @dev: DRM device whose CRTCs to turn off - * - * Drivers may want to call this on unload to ensure that all displays are - * unlit and the GPU is in a consistent, low power state. Takes modeset locks. - * - * Returns: - * Zero on success, error code on failure. - */ -int drm_crtc_force_disable_all(struct drm_device *dev) -{ - struct drm_crtc *crtc; - int ret = 0; + drm_modeset_lock_all(dev); + drm_for_each_crtc(crtc, dev) + if (crtc->enabled) { + struct drm_mode_set set = { + .crtc = crtc, + }; - drm_modeset_lock_all(dev); - drm_for_each_crtc(crtc, dev) - if (crtc->enabled) { - ret = drm_crtc_force_disable(crtc); - if (ret) - goto out; - } + ret = drm_mode_set_config_internal(&set); + if (ret) + goto out; + } out: - drm_modeset_unlock_all(dev); - return ret; + drm_modeset_unlock_all(dev); + return ret; } -EXPORT_SYMBOL(drm_crtc_force_disable_all); +EXPORT_SYMBOL(_kcl_drm_helper_force_disable_all); #endif diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-crtc-helper.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_helper_force_disable_all.m4 similarity index 60% rename from drivers/gpu/drm/amd/dkms/m4/drm-crtc-helper.m4 rename to drivers/gpu/drm/amd/dkms/m4/drm_helper_force_disable_all.m4 index a0e32e7654867..f52b3c10ccd43 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-crtc-helper.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_helper_force_disable_all.m4 @@ -2,16 +2,12 @@ dnl # dnl # commit f453ba0460742ad027ae0c4c7d61e62817b3e7ef dnl # DRM: add mode setting support dnl # -dnl # commit c2d88e06bcb98540bb83fac874574eaa4f320363 +dnl # commit v5.0-rc1-118-gc2d88e06bcb9 dnl # drm: Move the legacy kms disable_all helper to crtc helpers dnl # -AC_DEFUN([AC_AMDGPU_DRM_CRTC_HELPER], [ +AC_DEFUN([AC_AMDGPU_DRM_HELPER_FORCE_DISABLE_ALL], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - drm_helper_force_disable_all(NULL); - ], [ + AC_KERNEL_CHECK_SYMBOL_EXPORT([drm_helper_force_disable_all], [drivers/gpu/drm/drm_crtc_helper.c],[ AC_DEFINE(HAVE_DRM_HELPER_FORCE_DISABLE_ALL, 1, [drm_helper_force_disable_all() is available]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index a219e700c82a9..576f4fe44295a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -74,8 +74,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_FB_HELPER_FILL_INFO AC_AMDGPU_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED AC_AMDGPU_DRM_HELPER_MODE_FILL_FB_STRUCT - AC_AMDGPU_DRM_CRTC_FORCE_DISABLE_ALL - AC_AMDGPU_DRM_CRTC_HELPER + AC_AMDGPU_DRM_HELPER_FORCE_DISABLE_ALL AC_AMDGPU_DRM_EDID_TO_ELD AC_KERNEL_WAIT diff --git a/include/kcl/kcl_drm_crtc.h b/include/kcl/kcl_drm_crtc.h index daca652324951..e0eaa2ace66b1 100644 --- a/include/kcl/kcl_drm_crtc.h +++ b/include/kcl/kcl_drm_crtc.h @@ -74,16 +74,12 @@ DRM_MODE_ROTATE_270) #endif -#if !defined(HAVE_DRM_CRTC_FORCE_DISABLE_ALL) -extern int drm_crtc_force_disable(struct drm_crtc *crtc); -extern int drm_crtc_force_disable_all(struct drm_device *dev); -#endif - #if !defined(HAVE_DRM_HELPER_FORCE_DISABLE_ALL) +int _kcl_drm_helper_force_disable_all(struct drm_device *dev); static inline int drm_helper_force_disable_all(struct drm_device *dev) { - return drm_crtc_force_disable_all(dev); + return _kcl_drm_helper_force_disable_all(dev); } #endif From 96814d6bc46f0d6bbb98baee84a9c6f11dcdc6d4 Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Thu, 24 Dec 2020 11:43:48 +0800 Subject: [PATCH 0161/1868] drm/amdkcl: fix kthread_use_mm/kthread_unuse_mm redefinition error on sle sp2 server distro with kernel 5.3.18-24 define the kthread_use_mm for kcl only when it is neither defined in kthread.c nor in mmu_context.h Signed-off-by: Shiwu Zhang --- drivers/gpu/drm/amd/dkms/m4/kthread_use_mm.m4 | 20 +++++++++++++++---- include/kcl/kcl_kthread.h | 2 -- 2 files changed, 16 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kthread_use_mm.m4 b/drivers/gpu/drm/amd/dkms/m4/kthread_use_mm.m4 index 0b62fc9008c6b..6177b3b6fa49e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kthread_use_mm.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kthread_use_mm.m4 @@ -3,9 +3,21 @@ dnl # f5678e7f2ac3 kernel: better document the use_mm/unuse_mm API contract dnl # 9bf5b9eb232b kernel: move use_mm/unuse_mm to kthread.c dnl # AC_DEFUN([AC_AMDGPU_KTHREAD_USE_MM], [ - AC_KERNEL_CHECK_SYMBOL_EXPORT([kthread_use_mm kthread_unuse_mm], - [kernel/kthread.c], [ - AC_DEFINE(HAVE_KTHREAD_USE_MM, 1, - [kthread_{use,unuse}_mm() is available]) + AC_KERNEL_DO_BACKGROUND([ + dnl # + dnl # sle sp2 server distro inlines kthread_use_mm/kthread_unuse_mm + dnl # in mmu_context.h + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + #include + #include + ], [ + kthread_use_mm(NULL); + kthread_unuse_mm(NULL); + ], [ + AC_DEFINE(HAVE_KTHREAD_USE_MM, 1, + [kthread_{use,unuse}_mm() is available]) + ]) ]) ]) diff --git a/include/kcl/kcl_kthread.h b/include/kcl/kcl_kthread.h index ecb650acee90e..90893fd2590b1 100644 --- a/include/kcl/kcl_kthread.h +++ b/include/kcl/kcl_kthread.h @@ -4,9 +4,7 @@ #include #include -#ifndef HAVE_KTHREAD_USE_MM #include -#endif #if !defined(HAVE___KTHREAD_SHOULD_PATK) extern bool __kcl_kthread_should_park(struct task_struct *k); From 6cbdb0b34221773784b13e4b52aeacee4417365e Mon Sep 17 00:00:00 2001 From: "Le.Ma" Date: Wed, 20 Sep 2017 09:53:26 +0800 Subject: [PATCH 0162/1868] drm/amdkcl: check whether rcu_pointer_handoff is available Change-Id: Ie20100a6353d106bd3cad3e724f0157de6e6b902 Signed-off-by: Le.Ma Reviewed-by: Junwei Zhang Signed-off-by: Jack Gui Signed-off-by: Flora Cui --- include/kcl/kcl_rcupdate.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) create mode 100644 include/kcl/kcl_rcupdate.h diff --git a/include/kcl/kcl_rcupdate.h b/include/kcl/kcl_rcupdate.h new file mode 100644 index 0000000000000..ec31bae327ead --- /dev/null +++ b/include/kcl/kcl_rcupdate.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef AMDKCL_RCUPDATE_H +#define AMDKCL_RCUPDATE_H + +#include +#include + +#ifndef rcu_pointer_handoff +#define rcu_pointer_handoff(p) (p) +#endif + +#endif /* AMDKCL_RCUPDATE_H */ From a2f49393dfac3341e032908649c11f9bc5dbd294 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Wed, 13 May 2020 17:21:35 -0400 Subject: [PATCH 0163/1868] drm/amdkcl: optional devices ID for amdgpu driver Test for amdgpu-pciid.h header file Signed-off-by: Slava Grigorev Reviewed-by: Slava Abramov Reviewed-by: Tim Writer --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 053200a25fa24..c301a0ce7e25c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2137,6 +2137,10 @@ static const struct pci_device_id pciidlist[] = { .class_mask = 0xffffff, .driver_data = CHIP_IP_DISCOVERY }, +#ifdef HAVE_DRM_AMDGPU_PCIID_H +#include +#endif + {0, 0, 0} }; From 14a80c0017d115dd693b8b7c51c9045f8e881973 Mon Sep 17 00:00:00 2001 From: "Stanley.Yang" Date: Fri, 21 Aug 2020 12:44:47 +0800 Subject: [PATCH 0164/1868] drm/amdkcl: add kcl copy of drm/task_barrier.h This is a squash of: drm/amdkcl: rework drm/task_barrier.h handling Signed-off-by: Stanley.Yang Reviewed-by: Flora Cui Reviewed-by: Guchun Chen Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_task_barrier.h | 86 +++++++++++++++++++++++++ 2 files changed, 87 insertions(+) create mode 100644 include/kcl/kcl_task_barrier.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index a38fc43d61a54..a0a11812f299c 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -35,6 +35,7 @@ #include #include #include +#include #include #include #include diff --git a/include/kcl/kcl_task_barrier.h b/include/kcl/kcl_task_barrier.h new file mode 100644 index 0000000000000..341fe8e02a9d9 --- /dev/null +++ b/include/kcl/kcl_task_barrier.h @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef AMDKCL_DRM_TASK_BARRIER_H +#define AMDKCL_DRM_TASK_BARRIER_H + +#ifdef HAVE_DRM_TASK_BARRIER_H +#include +#else +/* + * Reusable 2 PHASE task barrier (randevouz point) implementation for N tasks. + * Based on the Little book of sempahores - https://greenteapress.com/wp/semaphores/ + */ +#include +#include + +/* + * Represents an instance of a task barrier. + */ +struct task_barrier { + unsigned int n; + atomic_t count; + struct semaphore enter_turnstile; + struct semaphore exit_turnstile; +}; + +static inline void task_barrier_signal_turnstile(struct semaphore *turnstile, + unsigned int n) +{ + int i; + + for (i = 0 ; i < n; i++) + up(turnstile); +} + +static inline void task_barrier_init(struct task_barrier *tb) +{ + tb->n = 0; + atomic_set(&tb->count, 0); + sema_init(&tb->enter_turnstile, 0); + sema_init(&tb->exit_turnstile, 0); +} + +static inline void task_barrier_add_task(struct task_barrier *tb) +{ + tb->n++; +} + +static inline void task_barrier_rem_task(struct task_barrier *tb) +{ + tb->n--; +} + +/* + * Lines up all the threads BEFORE the critical point. + * + * When all thread passed this code the entry barrier is back to locked state. + */ +static inline void task_barrier_enter(struct task_barrier *tb) +{ + if (atomic_inc_return(&tb->count) == tb->n) + task_barrier_signal_turnstile(&tb->enter_turnstile, tb->n); + + down(&tb->enter_turnstile); +} + +/* + * Lines up all the threads AFTER the critical point. + * + * This function is used to avoid any one thread running ahead if the barrier is + * used repeatedly . + */ +static inline void task_barrier_exit(struct task_barrier *tb) +{ + if (atomic_dec_return(&tb->count) == 0) + task_barrier_signal_turnstile(&tb->exit_turnstile, tb->n); + + down(&tb->exit_turnstile); +} + +/* Convinieince function when nothing to be done in between entry and exit */ +static inline void task_barrier_full(struct task_barrier *tb) +{ + task_barrier_enter(tb); + task_barrier_exit(tb); +} +#endif +#endif From 2d566f1b6b403ce5f5c366fc8412cc68cb51feda Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 7 Nov 2019 10:37:13 +0800 Subject: [PATCH 0165/1868] drm/amdkcl: increase drm vma offset size limit v2: increase drm vma offset size limit For 8 processes share 256GB system memory application case, 1T Bytes drm vma offset limit is not big enough. Increase the limit to 16TB, for max 44bits address space because the upper bit is encoded with gpu_id. Remove the 64GB size condition check to handle all kernels, 64GB is Ubuntu kernel default setting, CentOS, Redhat kernel default is 1TB. Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang Signed-off-by: Jack Gui Signed-off-by: Jiansong Chen Signed-off-by: Philip Yang Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 + drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/ttm/backport/backport.h | 1 + .../backport/kcl_drm_vma_manager_backport.h | 58 +++++++++++++++++++ 4 files changed, 62 insertions(+) create mode 100644 include/kcl/backport/kcl_drm_vma_manager_backport.h diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index c301a0ce7e25c..769a647262823 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2306,6 +2306,8 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, adev->pdev = pdev; ddev = adev_to_drm(adev); + kcl_drm_vma_offset_manager_init(ddev->vma_offset_manager); + if (!supports_atomic) ddev->driver_features &= ~DRIVER_ATOMIC; diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index a0a11812f299c..02f790b540220 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -38,6 +38,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index 659a7f1e254c4..acec38aa8d159 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #endif diff --git a/include/kcl/backport/kcl_drm_vma_manager_backport.h b/include/kcl/backport/kcl_drm_vma_manager_backport.h new file mode 100644 index 0000000000000..0a7e1bf34bd82 --- /dev/null +++ b/include/kcl/backport/kcl_drm_vma_manager_backport.h @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2013 David Herrmann + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef AMDKCL_DRM_VMA_MANAGER_H +#define AMDKCL_DRM_VMA_MANAGER_H + +/* We make up offsets for buffer objects so we can recognize them at + * mmap time. pgoff in mmap is an unsigned long, so we need to make sure + * that the faked up offset will fit + */ +#include +#include + +#if (BITS_PER_LONG == 64) +#ifdef DRM_FILE_PAGE_OFFSET_START +#undef DRM_FILE_PAGE_OFFSET_START +#endif +#ifdef DRM_FILE_PAGE_OFFSET_SIZE +#undef DRM_FILE_PAGE_OFFSET_SIZE +#endif + +#define DRM_FILE_PAGE_OFFSET_START ((0xFFFFFFFFULL >> PAGE_SHIFT) + 1) +#define DRM_FILE_PAGE_OFFSET_SIZE ((0xFFFFFFFFULL >> PAGE_SHIFT) * 4096) + +static inline void +kcl_drm_vma_offset_manager_init(struct drm_vma_offset_manager *mgr) +{ + drm_vma_offset_manager_destroy(mgr); + drm_vma_offset_manager_init(mgr, + DRM_FILE_PAGE_OFFSET_START, + DRM_FILE_PAGE_OFFSET_SIZE); +} +#else +static inline void +kcl_drm_vma_offset_manager_init(struct drm_vma_offset_manager *mgr) +{ +} +#endif + +#endif From 66398be50d7fd8f6d0e6b565c29dea709cdf7d36 Mon Sep 17 00:00:00 2001 From: Chengming Gui Date: Fri, 30 Aug 2019 15:30:41 +0800 Subject: [PATCH 0166/1868] drm/amdkcl: check whether DRM_FB_HELPER_DEFAULT_OPS is available DRM_FB_HELPER_DEFAULT_OPS introduced by kernel v4.9-rc1~41^2~3^2~2 - commit 74064893901ac5103cf101ecef5946e82b6ce9c6 - drm/fb-helper: add DRM_FB_HELPER_DEFAULT_OPS for fb_ops v1: drm/amdkcl: Test whether fb_ops->fb_debug_{enter/leave}() is available v2: drm/amdkcl: add DRM_FB_HELPER_DEFAULT_OPS v3: drm/amdkcl: accommodate to drmP.h removal for fb-ops-fb-debug-xx.m4 v4: drm/amd/autoconf: fix a drm kcl compiling error in CentOS 7.3 v5: drm/amdkcl: drop test for fb_ops->fb_debug_xx Signed-off-by: Chengming Gui Reviewed-by: Flora Cui Signed-off-by: Flora Cui Acked-by: Feifei Xu / Signed-off-by: Yifan Zhang Signed-off-by: Flora Cui Reviewed-by: Feifei Xu --- include/kcl/kcl_drm_fb.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/include/kcl/kcl_drm_fb.h b/include/kcl/kcl_drm_fb.h index 0954d658644a8..3a0d30273cf7a 100644 --- a/include/kcl/kcl_drm_fb.h +++ b/include/kcl/kcl_drm_fb.h @@ -35,6 +35,25 @@ #include #include +/* + * Don't add fb_debug_* since the legacy drm_fb_helper_debug_* has segfault + * history: + * v2.6.35-21-gd219adc1228a fb: add hooks to handle KDB enter/exit + * v2.6.35-22-g1a7aba7f4e45 drm: add KGDB/KDB support + * v4.8-rc8-1391-g74064893901a drm/fb-helper: add DRM_FB_HELPER_DEFAULT_OPS for fb_ops + * v4.9-rc4-808-g1e0089288b9b drm/fb-helper: add fb_debug_* to DRM_FB_HELPER_DEFAULT_OPS + * v4.9-rc4-807-g1b99b72489c6 drm/fb-helper: fix segfaults in drm_fb_helper_debug_* + * v4.10-rc8-1367-g0f3bbe074dd1 drm/fb-helper: implement ioctl FBIO_WAITFORVSYNC + */ +#ifndef DRM_FB_HELPER_DEFAULT_OPS +#define DRM_FB_HELPER_DEFAULT_OPS \ + .fb_check_var = drm_fb_helper_check_var, \ + .fb_set_par = drm_fb_helper_set_par, \ + .fb_setcmap = drm_fb_helper_setcmap, \ + .fb_blank = drm_fb_helper_blank, \ + .fb_pan_display = drm_fb_helper_pan_display +#endif + #if !defined(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS) #if !defined(IS_REACHABLE) /* Copied from include/linux/kconfig.h */ From effe85b76b9c95c144056a8b2f4769285671d2a1 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 26 Aug 2020 16:57:05 +0800 Subject: [PATCH 0167/1868] drm/amdkcl: fake kcl copy of drm_atomic_helper_resume Signed-off-by: Flora Cui --- .../backport/kcl_drm_atomic_helper_backport.h | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/include/kcl/backport/kcl_drm_atomic_helper_backport.h b/include/kcl/backport/kcl_drm_atomic_helper_backport.h index bcb45b685a034..1edfc203e12ce 100644 --- a/include/kcl/backport/kcl_drm_atomic_helper_backport.h +++ b/include/kcl/backport/kcl_drm_atomic_helper_backport.h @@ -4,6 +4,33 @@ #include +/* + * commit v4.14-rc4-1-g78279127253a + * drm/atomic: Unref duplicated drm_atomic_state in drm_atomic_helper_resume() + */ +#if DRM_VERSION_CODE < DRM_VERSION(4, 15, 0) +static inline +int _kcl_drm_atomic_helper_resume(struct drm_device *dev, + struct drm_atomic_state *state) +{ + unsigned int prev, after; + int ret; + + prev = kref_read(&state->ref); + + drm_atomic_state_get(state); + ret = drm_atomic_helper_resume(dev, state); + + after = kref_read(&state->ref); + drm_atomic_state_put(state); + if (prev != after) + drm_atomic_state_put(state); + + return ret; +} +#define drm_atomic_helper_resume _kcl_drm_atomic_helper_resume +#endif + #ifdef AMDKCL__DRM_ATOMIC_HELPER_PLANE_RESET #define __drm_atomic_helper_plane_reset _kcl__drm_atomic_helper_plane_reset #endif /* AMDKCL__DRM_ATOMIC_HELPER_PLANE_RESET */ From e01f2ea60388e344368e78705b10f454eb9efdd9 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 7 Sep 2020 14:04:55 +0800 Subject: [PATCH 0168/1868] drm/amdkcl: test dma_buf_ops->allow_peer2peer introduced in commit v5.6-rc5-1663-g09606b5446c2 ("dma-buf: add peer2peer flag") Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 6 ++++++ drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 | 18 ++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 25 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index 8e81a83d37d84..8970e8eec45b8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -57,8 +57,10 @@ static int amdgpu_dma_buf_attach(struct dma_buf *dmabuf, struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); +#ifdef HAVE_STRUCT_DMA_BUF_OPS_ALLOW_PEER2PEER if (pci_p2pdma_distance(adev->pdev, attach->dev, false) < 0) attach->peer2peer = false; +#endif return 0; } @@ -122,11 +124,13 @@ static struct sg_table *amdgpu_dma_buf_map(struct dma_buf_attachment *attach, struct ttm_operation_ctx ctx = { false, false }; unsigned int domains = AMDGPU_GEM_DOMAIN_GTT; +#ifdef HAVE_STRUCT_DMA_BUF_OPS_ALLOW_PEER2PEER if (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM && attach->peer2peer) { bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; domains |= AMDGPU_GEM_DOMAIN_VRAM; } +#endif amdgpu_bo_placement_from_domain(bo, domains); r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); if (r) @@ -393,7 +397,9 @@ amdgpu_dma_buf_move_notify(struct dma_buf_attachment *attach) } static const struct dma_buf_attach_ops amdgpu_dma_buf_attach_ops = { +#ifdef HAVE_STRUCT_DMA_BUF_OPS_ALLOW_PEER2PEER .allow_peer2peer = true, +#endif .move_notify = amdgpu_dma_buf_move_notify }; diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 new file mode 100644 index 0000000000000..f499b15204fa8 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # v5.6-rc5-1663-g09606b5446c2 +dnl # dma-buf: add peer2peer flag +dnl # +AC_DEFUN([AC_AMDGPU_DMA_BUF], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct dma_buf_ops *ptr = NULL; + ptr->allow_peer2peer = false; + ],[ + AC_DEFINE(HAVE_STRUCT_DMA_BUF_OPS_ALLOW_PEER2PEER, + 1, + [struct dma_buf_ops->allow_peer2peer is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 576f4fe44295a..62ecc02eb26be 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -50,6 +50,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DMA_RESV AC_AMDGPU_TTM_SG_TT_INIT AC_AMDGPU_DEVCGROUP_CHECK_PERMISSION + AC_AMDGPU_DMA_BUF AC_AMDGPU_DRM_CACHE AC_AMDGPU_DRM_DEBUG_ENABLED AC_AMDGPU_DRM_GEM_OBJECT_PUT_UNLOCKED From 6ed3c845c4772b729b3d6c515a9f7d17dd6a8e2a Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 15 Apr 2020 17:10:16 +0800 Subject: [PATCH 0169/1868] drm/amdkcl: for dma_buf_ops->pin/unpin Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 26 +++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 4 ++++ drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 | 20 ++++++++++++++++ 3 files changed, 50 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index 8970e8eec45b8..45b8a77524744 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -65,6 +65,7 @@ static int amdgpu_dma_buf_attach(struct dma_buf *dmabuf, return 0; } +#ifdef HAVE_STRUCT_DMA_BUF_OPS_PIN /** * amdgpu_dma_buf_pin - &dma_buf_ops.pin implementation * @@ -95,6 +96,7 @@ static void amdgpu_dma_buf_unpin(struct dma_buf_attachment *attach) amdgpu_bo_unpin(bo); } +#endif /** * amdgpu_dma_buf_map - &dma_buf_ops.map_dma_buf implementation @@ -119,6 +121,7 @@ static struct sg_table *amdgpu_dma_buf_map(struct dma_buf_attachment *attach, struct sg_table *sgt; long r; +#ifdef HAVE_STRUCT_DMA_BUF_OPS_PIN if (!bo->tbo.pin_count) { /* move buffer into GTT or VRAM */ struct ttm_operation_ctx ctx = { false, false }; @@ -139,6 +142,11 @@ static struct sg_table *amdgpu_dma_buf_map(struct dma_buf_attachment *attach, } else if (bo->tbo.resource->mem_type != TTM_PL_TT) { return ERR_PTR(-EBUSY); } +#else + r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT); + if (r) + return ERR_PTR(r); +#endif switch (bo->tbo.resource->mem_type) { case TTM_PL_TT: @@ -185,6 +193,12 @@ static void amdgpu_dma_buf_unmap(struct dma_buf_attachment *attach, struct sg_table *sgt, enum dma_data_direction dir) { +#ifndef HAVE_STRUCT_DMA_BUF_OPS_PIN + struct dma_buf *dma_buf = attach->dmabuf; + struct drm_gem_object *obj = dma_buf->priv; + struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); +#endif + if (sgt->sgl->page_link) { dma_unmap_sgtable(attach->dev, sgt, dir, 0); sg_free_table(sgt); @@ -192,6 +206,10 @@ static void amdgpu_dma_buf_unmap(struct dma_buf_attachment *attach, } else { amdgpu_vram_mgr_free_sgt(attach->dev, dir, sgt); } + +#ifndef HAVE_STRUCT_DMA_BUF_OPS_PIN + amdgpu_bo_unpin(bo); +#endif } /** @@ -237,8 +255,10 @@ static int amdgpu_dma_buf_begin_cpu_access(struct dma_buf *dma_buf, const struct dma_buf_ops amdgpu_dmabuf_ops = { .attach = amdgpu_dma_buf_attach, +#ifdef HAVE_STRUCT_DMA_BUF_OPS_PIN .pin = amdgpu_dma_buf_pin, .unpin = amdgpu_dma_buf_unpin, +#endif .map_dma_buf = amdgpu_dma_buf_map, .unmap_dma_buf = amdgpu_dma_buf_unmap, .release = drm_gem_dmabuf_release, @@ -326,6 +346,7 @@ amdgpu_dma_buf_create_obj(struct drm_device *dev, struct dma_buf *dma_buf) return ERR_PTR(ret); } +#ifdef HAVE_STRUCT_DMA_BUF_OPS_PIN /** * amdgpu_dma_buf_move_notify - &attach.move_notify implementation * @@ -402,6 +423,7 @@ static const struct dma_buf_attach_ops amdgpu_dma_buf_attach_ops = { #endif .move_notify = amdgpu_dma_buf_move_notify }; +#endif /** * amdgpu_gem_prime_import - &drm_driver.gem_prime_import implementation @@ -435,8 +457,12 @@ struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev, if (IS_ERR(obj)) return obj; +#ifdef HAVE_STRUCT_DMA_BUF_OPS_PIN attach = dma_buf_dynamic_attach(dma_buf, dev->dev, &amdgpu_dma_buf_attach_ops, obj); +#else + attach = dma_buf_dynamic_attach(dma_buf, dev->dev, true); +#endif if (IS_ERR(attach)) { drm_gem_object_put(obj); return ERR_CAST(attach); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index e32161f6b67a3..f436ed24b5c76 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -949,8 +949,10 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, */ domain = amdgpu_bo_get_preferred_domain(adev, domain); +#ifdef HAVE_STRUCT_DMA_BUF_OPS_PIN if (bo->tbo.base.import_attach) dma_buf_pin(bo->tbo.base.import_attach); +#endif /* force to pin into visible video ram */ if (!(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) @@ -1274,9 +1276,11 @@ void amdgpu_bo_move_notify(struct ttm_buffer_object *bo, amdgpu_bo_kunmap(abo); +#ifdef HAVE_STRUCT_DMA_BUF_OPS_PIN if (abo->tbo.base.dma_buf && !abo->tbo.base.import_attach && old_mem && old_mem->mem_type != TTM_PL_SYSTEM) dma_buf_move_notify(abo->tbo.base.dma_buf); +#endif /* move_notify is called before move happens */ trace_amdgpu_bo_move(abo, new_mem ? new_mem->mem_type : -1, diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 index f499b15204fa8..dc74e703be9bd 100644 --- a/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 @@ -13,6 +13,26 @@ AC_DEFUN([AC_AMDGPU_DMA_BUF], [ AC_DEFINE(HAVE_STRUCT_DMA_BUF_OPS_ALLOW_PEER2PEER, 1, [struct dma_buf_ops->allow_peer2peer is available]) + ],[ + dnl # + dnl # 4981cdb063e3 dma-buf: make move_notify mandatory if importer_ops are provided + dnl # bd2275eeed5b dma-buf: drop dynamic_mapping flag + dnl # a448cb003edc drm/amdgpu: implement amdgpu_gem_prime_move_notify v2 + dnl # 2d4dad2734e2 drm/amdgpu: add amdgpu_dma_buf_pin/unpin v2 + dnl # 4993ba02635f drm/amdgpu: use allowed_domains for exported DMA-bufs + dnl # d2588d2ded0f drm/ttm: remove the backing store if no placement is given + dnl # bb42df4662a4 dma-buf: add dynamic DMA-buf handling v15 + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct dma_buf_ops *ptr = NULL; + ptr->pin(NULL); + ],[ + AC_DEFINE(HAVE_STRUCT_DMA_BUF_OPS_PIN, + 1, + [struct dma_buf_ops->pin() is available]) + ]) ]) ]) ]) From 6c2262503a4bfa179258241141bf0e011f2fef38 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 4 Dec 2019 21:12:38 +0800 Subject: [PATCH 0170/1868] drm/amdkcl: Test whether drm_gem_object->resv is available It's a squash of b56463fa65e9 amd/amdkcl: drop BUILD_AS_DKMS compilation flag 65727463b0e9 drm/ttm,scheduler,amdgpu: properly define and initialize Makefile variables 5e00d69a73fb drm/amdkcl: introduce parallel autoconf tests execution de56d017a2d3 drm/amdkcl: Test whether drm_gem_object->resv is available Signed-off-by: Flora Cui Signed-off-by: Jack Gui Signed-off-by: Jiansong Chen Signed-off-by: Slava Grigorev Reviewed-by: Flora Cui Change-Id: Ibbd3ff2eb018141c783a2c6c0ebebac366f8ecc0 --- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 12 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 6 +- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 20 ++++- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 4 +- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 20 ++--- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 18 ++--- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../gpu/drm/amd/dkms/m4/ttm_buffer_object.m4 | 23 ++++++ drivers/gpu/drm/ttm/ttm_bo.c | 76 +++++++++---------- drivers/gpu/drm/ttm/ttm_bo_util.c | 16 ++-- drivers/gpu/drm/ttm/ttm_bo_vm.c | 16 ++-- drivers/gpu/drm/ttm/ttm_execbuf_util.c | 12 +-- drivers/gpu/drm/ttm/ttm_tt.c | 2 +- include/drm/ttm/ttm_bo.h | 29 +++++-- 19 files changed, 162 insertions(+), 103 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/ttm_buffer_object.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 6d5fd371d5ce8..e897d08c62ba4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -365,7 +365,7 @@ static int amdgpu_amdkfd_remove_eviction_fence(struct amdgpu_bo *bo, * table update and TLB flush here directly. */ replacement = dma_fence_get_stub(); - dma_resv_replace_fences(bo->tbo.base.resv, ef->base.context, + dma_resv_replace_fences(amdkcl_ttm_resvp(&bo->tbo), ef->base.context, replacement, DMA_RESV_USAGE_BOOKKEEP); dma_fence_put(replacement); return 0; @@ -399,9 +399,9 @@ int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo) ef = container_of(dma_fence_get(&info->eviction_fence->base), struct amdgpu_amdkfd_fence, base); - BUG_ON(!dma_resv_trylock(bo->tbo.base.resv)); + BUG_ON(!dma_resv_trylock(amdkcl_ttm_resvp(&bo->tbo))); ret = amdgpu_amdkfd_remove_eviction_fence(bo, ef); - dma_resv_unlock(bo->tbo.base.resv); + dma_resv_unlock(amdkcl_ttm_resvp(&bo->tbo)); dma_fence_put(&ef->base); return ret; @@ -1356,7 +1356,7 @@ static int process_sync_pds_resv(struct amdkfd_process_info *process_info, vm_list_node) { struct amdgpu_bo *pd = peer_vm->root.bo; - ret = amdgpu_sync_resv(NULL, sync, pd->tbo.base.resv, + ret = amdgpu_sync_resv(NULL, sync, amdkcl_ttm_resvp(&pd->tbo), AMDGPU_SYNC_NE_OWNER, AMDGPU_FENCE_OWNER_KFD); if (ret) @@ -1432,7 +1432,7 @@ static int init_kfd_vm(struct amdgpu_vm *vm, void **process_info, AMDGPU_FENCE_OWNER_KFD, false); if (ret) goto wait_pd_fail; - ret = dma_resv_reserve_fences(vm->root.bo->tbo.base.resv, 1); + ret = dma_resv_reserve_fences(amdkcl_ttm_resvp(&vm->root.bo->tbo), 1); if (ret) goto reserve_shared_fail; dma_resv_add_fence(vm->root.bo->tbo.base.resv, @@ -3138,7 +3138,7 @@ int amdgpu_amdkfd_add_gws_to_process(void *info, void *gws, struct kgd_mem **mem * Add process eviction fence to bo so they can * evict each other. */ - ret = dma_resv_reserve_fences(gws_bo->tbo.base.resv, 1); + ret = dma_resv_reserve_fences(amdkcl_ttm_resvp(&gws_bo->tbo), 1); if (ret) goto reserve_shared_fail; dma_resv_add_fence(gws_bo->tbo.base.resv, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 78b3c067fea7e..cb414a1c04dbb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -786,7 +786,7 @@ static int amdgpu_cs_bo_validate(void *param, struct amdgpu_bo *bo) struct ttm_operation_ctx ctx = { .interruptible = true, .no_wait_gpu = false, - .resv = bo->tbo.base.resv + .resv = amdkcl_ttm_resvp(&bo->tbo), }; uint32_t domain; int r; @@ -1215,7 +1215,7 @@ static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p) drm_exec_for_each_locked_object(&p->exec, index, obj) { struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); - struct dma_resv *resv = bo->tbo.base.resv; + struct dma_resv *resv = amdkcl_ttm_resvp(&bo->tbo); enum amdgpu_sync_mode sync_mode; sync_mode = amdgpu_bo_explicit_sync(bo) ? @@ -1797,7 +1797,7 @@ int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, *map = mapping; /* Double check that the BO is reserved by this CS */ - if (dma_resv_locking_ctx((*bo)->tbo.base.resv) != &parser->exec.ticket) + if (dma_resv_locking_ctx(amdkcl_ttm_resvp(&(*bo)->tbo)) != &parser->exec.ticket) return -EINVAL; (*bo)->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 092ec11258cdd..27cead4f33e2b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -247,7 +247,7 @@ int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc, goto unpin; } - r = dma_resv_get_fences(new_abo->tbo.base.resv, DMA_RESV_USAGE_WRITE, + r = dma_resv_get_fences(amdkcl_ttm_resvp(&new_abo->tbo), DMA_RESV_USAGE_WRITE, &work->shared_count, &work->shared); if (unlikely(r != 0)) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index 45b8a77524744..8794a82e08cce 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -62,6 +62,24 @@ static int amdgpu_dma_buf_attach(struct dma_buf *dmabuf, attach->peer2peer = false; #endif + r = amdgpu_bo_reserve(bo, false); + if (unlikely(r != 0)) + goto out; + + /* + * We only create shared fences for internal use, but importers + * of the dmabuf rely on exclusive fences for implicitly + * tracking write hazards. As any of the current fences may + * correspond to a write, we need to convert all existing + * fences on the reservation object into a single exclusive + * fence. + */ + r = __dma_resv_make_exclusive(amdkcl_ttm_resvp(&bo->tbo)); + if (r) + goto out; + + bo->prime_shared_count++; + amdgpu_bo_unreserve(bo); return 0; } @@ -382,7 +400,7 @@ amdgpu_dma_buf_move_notify(struct dma_buf_attachment *attach) for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) { struct amdgpu_vm *vm = bo_base->vm; - struct dma_resv *resv = vm->root.bo->tbo.base.resv; + struct dma_resv *resv = amdkcl_ttm_resvp(&vm->root.base.bo->tbo); if (ticket) { /* When we get an error here it means that somebody diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index aad2027e5c7cb..378546542f212 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -366,7 +366,7 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, if (r) return r; - resv = vm->root.bo->tbo.base.resv; + resv = amdkcl_ttm_resvp(&vm->root.bo->tbo); } initial_domain = (u32)(0xffffffff & args->in.domains); @@ -567,7 +567,7 @@ int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data, return -ENOENT; robj = gem_to_amdgpu_bo(gobj); - ret = dma_resv_wait_timeout(robj->tbo.base.resv, DMA_RESV_USAGE_READ, + ret = dma_resv_wait_timeout(amdkcl_ttm_resvp(&robj->tbo), DMA_RESV_USAGE_READ, true, timeout); /* ret == 0 means not signaled, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c index e36fede7f74c3..3c928bc9d48c0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c @@ -78,7 +78,7 @@ static bool amdgpu_hmm_invalidate_gfx(struct mmu_interval_notifier *mni, mmu_interval_set_seq(mni, cur_seq); - r = dma_resv_wait_timeout(bo->tbo.base.resv, DMA_RESV_USAGE_BOOKKEEP, + r = dma_resv_wait_timeout(amdkcl_ttm_resvp(&bo->tbo), DMA_RESV_USAGE_BOOKKEEP, false, MAX_SCHEDULE_TIMEOUT); mutex_unlock(&adev->notifier_lock); if (r <= 0) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index d9fde38f6ee27..24e0c7b812a9c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -1463,7 +1463,7 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev, amdgpu_vm_fini(adev, &fpriv->vm); if (pasid) - amdgpu_pasid_free_delayed(pd->tbo.base.resv, pasid); + amdgpu_pasid_free_delayed(amdkcl_ttm_resvp(&pd->tbo), pasid); amdgpu_bo_unref(&pd); idr_for_each_entry(&fpriv->bo_list_handles, list, handle) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index f436ed24b5c76..f48fefcf67241 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -657,7 +657,7 @@ int amdgpu_bo_create(struct amdgpu_device *adev, fail_unreserve: if (!bp->resv) - dma_resv_unlock(bo->tbo.base.resv); + dma_resv_unlock(amdkcl_ttm_resvp(&bo->tbo)); amdgpu_bo_unref(&bo); return r; } @@ -787,7 +787,7 @@ int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr) if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) return -EPERM; - r = dma_resv_wait_timeout(bo->tbo.base.resv, DMA_RESV_USAGE_KERNEL, + r = dma_resv_wait_timeout(amdkcl_ttm_resvp(&bo->tbo), DMA_RESV_USAGE_KERNEL, false, MAX_SCHEDULE_TIMEOUT); if (r < 0) return r; @@ -1155,7 +1155,7 @@ void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags) struct amdgpu_bo_user *ubo; BUG_ON(bo->tbo.type == ttm_bo_type_kernel); - dma_resv_assert_held(bo->tbo.base.resv); + dma_resv_assert_held(amdkcl_ttm_resvp(&bo->tbo)); ubo = to_amdgpu_bo_user(bo); if (tiling_flags) @@ -1365,8 +1365,8 @@ void amdgpu_bo_release_notify(struct ttm_buffer_object *bo) /* We only remove the fence if the resv has individualized. */ WARN_ON_ONCE(bo->type == ttm_bo_type_kernel - && bo->base.resv != &bo->base._resv); - if (bo->base.resv == &bo->base._resv) + && amdkcl_ttm_resvp(bo) != &amdkcl_ttm_resv(bo)); + if (amdkcl_ttm_resvp(bo) == &amdkcl_ttm_resv(bo)) amdgpu_amdkfd_remove_fence_on_pt_pd_bos(abo); if (!bo->resource || bo->resource->mem_type != TTM_PL_VRAM || @@ -1374,7 +1374,7 @@ void amdgpu_bo_release_notify(struct ttm_buffer_object *bo) adev->in_suspend || drm_dev_is_unplugged(adev_to_drm(adev))) return; - if (WARN_ON_ONCE(!dma_resv_trylock(bo->base.resv))) + if (WARN_ON_ONCE(!dma_resv_trylock(amdkcl_ttm_resvp(bo)))) return; r = amdgpu_fill_buffer(abo, 0, bo->base.resv, &fence, true); @@ -1384,7 +1384,7 @@ void amdgpu_bo_release_notify(struct ttm_buffer_object *bo) dma_fence_put(fence); } - dma_resv_unlock(bo->base.resv); + dma_resv_unlock(amdkcl_ttm_resvp(bo)); } /** @@ -1449,7 +1449,7 @@ vm_fault_t amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo) void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence, bool shared) { - struct dma_resv *resv = bo->tbo.base.resv; + struct dma_resv *resv = amdkcl_ttm_resvp(&bo->tbo); int r; r = dma_resv_reserve_fences(resv, 1); @@ -1505,7 +1505,7 @@ int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr) { struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); - return amdgpu_bo_sync_wait_resv(adev, bo->tbo.base.resv, + return amdgpu_bo_sync_wait_resv(adev, amdkcl_ttm_resvp(&bo->tbo), AMDGPU_SYNC_NE_OWNER, owner, intr); } @@ -1522,7 +1522,7 @@ int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr) u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo) { WARN_ON_ONCE(bo->tbo.resource->mem_type == TTM_PL_SYSTEM); - WARN_ON_ONCE(!dma_resv_is_locked(bo->tbo.base.resv) && + WARN_ON_ONCE(!dma_resv_is_locked(amdkcl_ttm_resvp(&bo->tbo)) && !bo->tbo.pin_count && bo->tbo.type != ttm_bo_type_kernel); WARN_ON_ONCE(bo->tbo.resource->start == AMDGPU_BO_INVALID_OFFSET); WARN_ON_ONCE(bo->tbo.resource->mem_type == TTM_PL_VRAM && diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index b8bc7fa8c3750..c229d58918a33 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -391,7 +391,7 @@ static int amdgpu_move_blit(struct ttm_buffer_object *bo, r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst, new_mem->size, amdgpu_bo_encrypted(abo), - bo->base.resv, &fence); + amdkcl_ttm_resvp(bo), &fence); if (r) goto error; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c index 31fd30dcd593b..bd5e71c3fdb0f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c @@ -1168,7 +1168,7 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo, goto err_free; } else { r = drm_sched_job_add_resv_dependencies(&job->base, - bo->tbo.base.resv, + amdkcl_ttm_resvp(&bo->tbo), DMA_RESV_USAGE_KERNEL); if (r) goto err_free; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index bcb729094521f..083e4ffa15794 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -1167,11 +1167,11 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va, if (clear || !bo) { mem = NULL; - resv = vm->root.bo->tbo.base.resv; + resv = amdkcl_ttm_resvp(&vm->root.base.bo->tbo); } else { struct drm_gem_object *obj = &bo->tbo.base; - resv = bo->tbo.base.resv; + resv = amdkcl_ttm_resvp(&bo->tbo); if (obj->import_attach && bo_va->is_xgmi) { struct dma_buf *dma_buf = obj->import_attach->dmabuf; struct drm_gem_object *gobj = dma_buf->priv; @@ -1414,7 +1414,7 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev, struct amdgpu_vm *vm, struct dma_fence **fence) { - struct dma_resv *resv = vm->root.bo->tbo.base.resv; + struct dma_resv *resv = amdkcl_ttm_resvp(&vm->root.base.bo->tbo); struct amdgpu_bo_va_mapping *mapping; uint64_t init_pte_value = 0; struct dma_fence *f = NULL; @@ -1486,7 +1486,7 @@ int amdgpu_vm_handle_moved(struct amdgpu_device *adev, while (!list_empty(&vm->invalidated)) { bo_va = list_first_entry(&vm->invalidated, struct amdgpu_bo_va, base.vm_status); - resv = bo_va->base.bo->tbo.base.resv; + resv = amdkcl_ttm_resvp(&bo_va->base.bo->tbo); spin_unlock(&vm->status_lock); /* Try to reserve the BO to avoid clearing its ptes */ @@ -2005,7 +2005,7 @@ void amdgpu_vm_bo_trace_cs(struct amdgpu_vm *vm, struct ww_acquire_ctx *ticket) struct amdgpu_bo *bo; bo = mapping->bo_va->base.bo; - if (dma_resv_locking_ctx(bo->tbo.base.resv) != + if (dma_resv_locking_ctx(amdkcl_ttm_resvp(&bo->tbo)) != ticket) continue; } @@ -2091,7 +2091,7 @@ bool amdgpu_vm_evictable(struct amdgpu_bo *bo) return true; /* Don't evict VM page tables while they are busy */ - if (!dma_resv_test_signaled(bo->tbo.base.resv, DMA_RESV_USAGE_BOOKKEEP)) + if (!dma_resv_test_signaled(amdkcl_ttm_resvp(&bo->tbo), DMA_RESV_USAGE_BOOKKEEP)) return false; /* Try to block ongoing updates */ @@ -2271,7 +2271,7 @@ void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size, */ long amdgpu_vm_wait_idle(struct amdgpu_vm *vm, long timeout) { - timeout = dma_resv_wait_timeout(vm->root.bo->tbo.base.resv, + timeout = dma_resv_wait_timeout(amdkcl_ttm_resvp(&vm->root.bo->tbo), DMA_RESV_USAGE_BOOKKEEP, true, timeout); if (timeout <= 0) @@ -2466,7 +2466,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, } amdgpu_vm_bo_base_init(&vm->root, vm, root_bo); - r = dma_resv_reserve_fences(root_bo->tbo.base.resv, 1); + r = dma_resv_reserve_fences(amdkcl_ttm_resvp(&root_bo->tbo), 1); if (r) goto error_free_root; @@ -3022,5 +3022,5 @@ void amdgpu_vm_update_fault_cache(struct amdgpu_device *adev, */ bool amdgpu_vm_is_bo_always_valid(struct amdgpu_vm *vm, struct amdgpu_bo *bo) { - return bo && bo->tbo.base.resv == vm->root.bo->tbo.base.resv; + return bo && amdkcl_ttm_resvp(&bo->tbo) == amdkcl_ttm_resvp(&vm->root.bo->tbo); } diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 62ecc02eb26be..308bd76a19a9a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -49,6 +49,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DMA_FENCE_HEADERS AC_AMDGPU_DMA_RESV AC_AMDGPU_TTM_SG_TT_INIT + AC_AMDGPU_TTM_BUFFER_OBJECT AC_AMDGPU_DEVCGROUP_CHECK_PERMISSION AC_AMDGPU_DMA_BUF AC_AMDGPU_DRM_CACHE diff --git a/drivers/gpu/drm/amd/dkms/m4/ttm_buffer_object.m4 b/drivers/gpu/drm/amd/dkms/m4/ttm_buffer_object.m4 new file mode 100644 index 0000000000000..6bf4a39e9679c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/ttm_buffer_object.m4 @@ -0,0 +1,23 @@ +dnl # +dnl # v5.3-rc1-374-ge7f0141a217f drm/ttm: drop ttm_buffer_object->resv +dnl # v5.3-rc1-370-g5a5011a72489 drm/amdgpu: switch driver from bo->resv to bo->base.resv +dnl # v5.3-rc1-367-ge532a135d704 drm/ttm: switch ttm core from bo->resv to bo->base.resv +dnl # v5.3-rc1-365-gb96f3e7c8069 drm/ttm: use gem vma_node +dnl # v5.3-rc1-364-g1e053b10ba60 drm/ttm: use gem reservation object +dnl # v5.3-rc1-362-gc105de2828e1 drm/amdgpu: use embedded gem object +dnl # v5.3-rc1-358-g8eb8833e7ed3 drm/ttm: add gem base object +dnl # v5.0-rc1-1004-g1ba627148ef5 drm: Add reservation_object to drm_gem_object +dnl # +AC_DEFUN([AC_AMDGPU_TTM_BUFFER_OBJECT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_gem_object *gem_obj = NULL; + gem_obj->resv = &gem_obj->_resv; + ], [ + AC_DEFINE(HAVE_DRM_GEM_OBJECT_RESV, 1, + [ttm_buffer_object->base is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index 2427be8bc97f0..260dc6425ead2 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -73,7 +73,7 @@ static void ttm_bo_mem_space_debug(struct ttm_buffer_object *bo, */ void ttm_bo_move_to_lru_tail(struct ttm_buffer_object *bo) { - dma_resv_assert_held(bo->base.resv); + dma_resv_assert_held(amdkcl_ttm_resvp(bo)); if (bo->resource) ttm_resource_move_to_lru_tail(bo->resource); @@ -97,7 +97,7 @@ EXPORT_SYMBOL(ttm_bo_move_to_lru_tail); void ttm_bo_set_bulk_move(struct ttm_buffer_object *bo, struct ttm_lru_bulk_move *bulk) { - dma_resv_assert_held(bo->base.resv); + dma_resv_assert_held(amdkcl_ttm_resvp(bo)); if (bo->bulk_move == bulk) return; @@ -187,13 +187,13 @@ static int ttm_bo_individualize_resv(struct ttm_buffer_object *bo) { int r; - if (bo->base.resv == &bo->base._resv) + if (amdkcl_ttm_resvp(bo) == &amdkcl_ttm_resv(bo)) return 0; - BUG_ON(!dma_resv_trylock(&bo->base._resv)); + BUG_ON(!dma_resv_trylock(&amdkcl_ttm_resv(bo))); - r = dma_resv_copy_fences(&bo->base._resv, bo->base.resv); - dma_resv_unlock(&bo->base._resv); + r = dma_resv_copy_fences(&amdkcl_ttm_resv(bo), amdkcl_ttm_resvp(bo)); + dma_resv_unlock(&amdkcl_ttm_resv(bo)); if (r) return r; @@ -203,7 +203,7 @@ static int ttm_bo_individualize_resv(struct ttm_buffer_object *bo) * the resv object while holding the lru_lock. */ spin_lock(&bo->bdev->lru_lock); - bo->base.resv = &bo->base._resv; + amdkcl_ttm_resvp(bo) = &amdkcl_ttm_resv(bo); spin_unlock(&bo->bdev->lru_lock); } @@ -212,7 +212,7 @@ static int ttm_bo_individualize_resv(struct ttm_buffer_object *bo) static void ttm_bo_flush_all_fences(struct ttm_buffer_object *bo) { - struct dma_resv *resv = &bo->base._resv; + struct dma_resv *resv = &amdkcl_ttm_resv(bo); struct dma_resv_iter cursor; struct dma_fence *fence; @@ -242,7 +242,7 @@ static int ttm_bo_cleanup_refs(struct ttm_buffer_object *bo, bool interruptible, bool no_wait_gpu, bool unlock_resv) { - struct dma_resv *resv = &bo->base._resv; + struct dma_resv *resv = &amdkcl_ttm_resv(bo); int ret; if (dma_resv_test_signaled(resv, DMA_RESV_USAGE_BOOKKEEP)) @@ -254,7 +254,7 @@ static int ttm_bo_cleanup_refs(struct ttm_buffer_object *bo, long lret; if (unlock_resv) - dma_resv_unlock(bo->base.resv); + dma_resv_unlock(amdkcl_ttm_resvp(bo)); spin_unlock(&bo->bdev->lru_lock); lret = dma_resv_wait_timeout(resv, DMA_RESV_USAGE_BOOKKEEP, @@ -267,7 +267,7 @@ static int ttm_bo_cleanup_refs(struct ttm_buffer_object *bo, return -EBUSY; spin_lock(&bo->bdev->lru_lock); - if (unlock_resv && !dma_resv_trylock(bo->base.resv)) { + if (unlock_resv && !dma_resv_trylock(amdkcl_ttm_resvp(bo))) { /* * We raced, and lost, someone else holds the reservation now, * and is probably busy in ttm_bo_cleanup_memtype_use. @@ -284,7 +284,7 @@ static int ttm_bo_cleanup_refs(struct ttm_buffer_object *bo, if (ret) { if (unlock_resv) - dma_resv_unlock(bo->base.resv); + dma_resv_unlock(amdkcl_ttm_resvp(bo)); spin_unlock(&bo->bdev->lru_lock); return ret; } @@ -293,7 +293,7 @@ static int ttm_bo_cleanup_refs(struct ttm_buffer_object *bo, ttm_bo_cleanup_memtype_use(bo); if (unlock_resv) - dma_resv_unlock(bo->base.resv); + dma_resv_unlock(amdkcl_ttm_resvp(bo)); return 0; } @@ -308,11 +308,11 @@ static void ttm_bo_delayed_delete(struct work_struct *work) bo = container_of(work, typeof(*bo), delayed_delete); - dma_resv_wait_timeout(bo->base.resv, DMA_RESV_USAGE_BOOKKEEP, false, + dma_resv_wait_timeout(amdkcl_ttm_resvp(bo), DMA_RESV_USAGE_BOOKKEEP, false, MAX_SCHEDULE_TIMEOUT); - dma_resv_lock(bo->base.resv, NULL); + dma_resv_lock(amdkcl_ttm_resvp(bo), NULL); ttm_bo_cleanup_memtype_use(bo); - dma_resv_unlock(bo->base.resv); + dma_resv_unlock(amdkcl_ttm_resvp(bo)); ttm_bo_put(bo); } @@ -332,7 +332,7 @@ static void ttm_bo_release(struct kref *kref) /* Last resort, if we fail to allocate memory for the * fences block for the BO to become idle */ - dma_resv_wait_timeout(bo->base.resv, + dma_resv_wait_timeout(amdkcl_ttm_resvp(bo), DMA_RESV_USAGE_BOOKKEEP, false, 30 * HZ); } @@ -343,11 +343,11 @@ static void ttm_bo_release(struct kref *kref) drm_vma_offset_remove(bdev->vma_manager, &bo->base.vma_node); ttm_mem_io_free(bdev, bo->resource); - if (!dma_resv_test_signaled(bo->base.resv, + if (!dma_resv_test_signaled(amdkcl_ttm_resvp(bo), DMA_RESV_USAGE_BOOKKEEP) || (want_init_on_free() && (bo->ttm != NULL)) || bo->type == ttm_bo_type_sg || - !dma_resv_trylock(bo->base.resv)) { + !dma_resv_trylock(amdkcl_ttm_resvp(bo))) { /* The BO is not idle, resurrect it for delayed destroy */ ttm_bo_flush_all_fences(bo); bo->deleted = true; @@ -382,7 +382,7 @@ static void ttm_bo_release(struct kref *kref) } ttm_bo_cleanup_memtype_use(bo); - dma_resv_unlock(bo->base.resv); + dma_resv_unlock(amdkcl_ttm_resvp(bo)); } atomic_dec(&ttm_glob.bo_count); @@ -437,7 +437,7 @@ static int ttm_bo_evict(struct ttm_buffer_object *bo, memset(&hop, 0, sizeof(hop)); - dma_resv_assert_held(bo->base.resv); + dma_resv_assert_held(amdkcl_ttm_resvp(bo)); placement.num_placement = 0; bdev->funcs->evict_flags(bo, &placement); @@ -530,15 +530,15 @@ static bool ttm_bo_evict_swapout_allowable(struct ttm_buffer_object *bo, return false; } - if (bo->base.resv == ctx->resv) { - dma_resv_assert_held(bo->base.resv); + if (amdkcl_ttm_resvp(bo) == ctx->resv) { + dma_resv_assert_held(amdkcl_ttm_resvp(bo)); if (ctx->allow_res_evict) ret = true; *locked = false; if (busy) *busy = false; } else { - ret = dma_resv_trylock(bo->base.resv); + ret = dma_resv_trylock(amdkcl_ttm_resvp(bo)); *locked = ret; if (busy) *busy = !ret; @@ -575,10 +575,10 @@ static int ttm_mem_evict_wait_busy(struct ttm_buffer_object *busy_bo, return -EBUSY; if (ctx->interruptible) - r = dma_resv_lock_interruptible(busy_bo->base.resv, + r = dma_resv_lock_interruptible(amdkcl_ttm_resvp(busy_bo), ticket); else - r = dma_resv_lock(busy_bo->base.resv, ticket); + r = dma_resv_lock(amdkcl_ttm_resvp(busy_bo), ticket); /* * TODO: It would be better to keep the BO locked until allocation is at @@ -586,7 +586,7 @@ static int ttm_mem_evict_wait_busy(struct ttm_buffer_object *busy_bo, * of TTM. */ if (!r) - dma_resv_unlock(busy_bo->base.resv); + dma_resv_unlock(amdkcl_ttm_resvp(busy_bo)); return r == -EDEADLK ? -EBUSY : r; } @@ -610,7 +610,7 @@ int ttm_mem_evict_first(struct ttm_device *bdev, if (!ttm_bo_evict_swapout_allowable(res->bo, ctx, place, &locked, &busy)) { if (busy && !busy_bo && ticket != - dma_resv_locking_ctx(res->bo->base.resv)) + dma_resv_locking_ctx(amdkcl_ttm_resvp(res->bo))) busy_bo = res->bo; continue; } @@ -716,7 +716,7 @@ static int ttm_bo_add_move_fence(struct ttm_buffer_object *bo, return ret; } - dma_resv_add_fence(bo->base.resv, fence, DMA_RESV_USAGE_KERNEL); + dma_resv_add_fence(amdkcl_ttm_resvp(bo), fence, DMA_RESV_USAGE_KERNEL); ret = dma_resv_reserve_fences(bo->base.resv, 1); dma_fence_put(fence); @@ -752,8 +752,8 @@ static int ttm_bo_alloc_resource(struct ttm_buffer_object *bo, struct ww_acquire_ctx *ticket; int i, ret; - ticket = dma_resv_locking_ctx(bo->base.resv); - ret = dma_resv_reserve_fences(bo->base.resv, 1); + ticket = dma_resv_locking_ctx(amdkcl_ttm_resvp(bo)); + ret = dma_resv_reserve_fences(amdkcl_ttm_resvp(bo), 1); if (unlikely(ret)) return ret; @@ -853,7 +853,7 @@ int ttm_bo_validate(struct ttm_buffer_object *bo, bool force_space; int ret; - dma_resv_assert_held(bo->base.resv); + dma_resv_assert_held(amdkcl_ttm_resvp(bo)); /* * Remove the backing store if no placement is given. @@ -971,9 +971,9 @@ int ttm_bo_init_reserved(struct ttm_device *bdev, struct ttm_buffer_object *bo, bo->sg = sg; bo->bulk_move = NULL; if (resv) - bo->base.resv = resv; + amdkcl_ttm_resvp(bo) = resv; else - bo->base.resv = &bo->base._resv; + amdkcl_ttm_resvp(bo) = &amdkcl_ttm_resv(bo); atomic_inc(&ttm_glob.bo_count); /* @@ -991,7 +991,7 @@ int ttm_bo_init_reserved(struct ttm_device *bdev, struct ttm_buffer_object *bo, * since otherwise lockdep will be angered in radeon. */ if (!resv) - WARN_ON(!dma_resv_trylock(bo->base.resv)); + WARN_ON(!dma_resv_trylock(amdkcl_ttm_resvp(bo))); else dma_resv_assert_held(resv); @@ -1101,14 +1101,14 @@ int ttm_bo_wait_ctx(struct ttm_buffer_object *bo, struct ttm_operation_ctx *ctx) long ret; if (ctx->no_wait_gpu) { - if (dma_resv_test_signaled(bo->base.resv, + if (dma_resv_test_signaled(amdkcl_ttm_resvp(bo), DMA_RESV_USAGE_BOOKKEEP)) return 0; else return -EBUSY; } - ret = dma_resv_wait_timeout(bo->base.resv, DMA_RESV_USAGE_BOOKKEEP, + ret = dma_resv_wait_timeout(amdkcl_ttm_resvp(bo), DMA_RESV_USAGE_BOOKKEEP, ctx->interruptible, 15 * HZ); if (unlikely(ret < 0)) return ret; @@ -1200,7 +1200,7 @@ int ttm_bo_swapout(struct ttm_buffer_object *bo, struct ttm_operation_ctx *ctx, * already swapped buffer. */ if (locked) - dma_resv_unlock(bo->base.resv); + dma_resv_unlock(amdkcl_ttm_resvp(bo)); ttm_bo_put(bo); return ret == -EBUSY ? -ENOSPC : ret; } diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c index 0b3f4267130c4..02a9574b0216a 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_util.c +++ b/drivers/gpu/drm/ttm/ttm_bo_util.c @@ -247,11 +247,11 @@ static int ttm_buffer_object_transfer(struct ttm_buffer_object *bo, fbo->base.destroy = &ttm_transfered_destroy; fbo->base.pin_count = 0; if (bo->type != ttm_bo_type_sg) - fbo->base.base.resv = &fbo->base.base._resv; + amdkcl_ttm_resvp(&fbo->base) = &amdkcl_ttm_resv(&fbo->base); - dma_resv_init(&fbo->base.base._resv); + dma_resv_init(&amdkcl_ttm_resv(&fbo->base)); fbo->base.base.dev = NULL; - ret = dma_resv_trylock(&fbo->base.base._resv); + ret = dma_resv_trylock(&amdkcl_ttm_resv(&fbo->base)); WARN_ON(!ret); if (fbo->base.resource) { @@ -591,7 +591,7 @@ static int ttm_bo_move_to_ghost(struct ttm_buffer_object *bo, if (ret) return ret; - dma_resv_add_fence(&ghost_obj->base._resv, fence, + dma_resv_add_fence(&amdkcl_ttm_resv(ghost_obj), fence, DMA_RESV_USAGE_KERNEL); /** @@ -605,7 +605,7 @@ static int ttm_bo_move_to_ghost(struct ttm_buffer_object *bo, else bo->ttm = NULL; - dma_resv_unlock(&ghost_obj->base._resv); + dma_resv_unlock(&amdkcl_ttm_resv(ghost_obj)); ttm_bo_put(ghost_obj); return 0; } @@ -659,7 +659,7 @@ int ttm_bo_move_accel_cleanup(struct ttm_buffer_object *bo, struct ttm_resource_manager *man = ttm_manager_type(bdev, new_mem->mem_type); int ret = 0; - dma_resv_add_fence(bo->base.resv, fence, DMA_RESV_USAGE_KERNEL); + dma_resv_add_fence(amdkcl_ttm_resvp(bo), fence, DMA_RESV_USAGE_KERNEL); if (!evict) ret = ttm_bo_move_to_ghost(bo, fence, man->use_tt); else if (!from->use_tt && pipeline) @@ -752,14 +752,14 @@ int ttm_bo_pipeline_gutting(struct ttm_buffer_object *bo) if (ret) goto error_destroy_tt; - ret = dma_resv_copy_fences(&ghost->base._resv, bo->base.resv); + ret = dma_resv_copy_fences(&amdkcl_ttm_resv(ghost), amdkcl_ttm_resvp(bo)); /* Last resort, wait for the BO to be idle when we are OOM */ if (ret) { dma_resv_wait_timeout(bo->base.resv, DMA_RESV_USAGE_BOOKKEEP, false, MAX_SCHEDULE_TIMEOUT); } - dma_resv_unlock(&ghost->base._resv); + dma_resv_unlock(&amdkcl_ttm_resv(ghost)); ttm_bo_put(ghost); bo->ttm = ttm; return 0; diff --git a/drivers/gpu/drm/ttm/ttm_bo_vm.c b/drivers/gpu/drm/ttm/ttm_bo_vm.c index 4212b8c91dd42..8f797d8d5d504 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_vm.c +++ b/drivers/gpu/drm/ttm/ttm_bo_vm.c @@ -60,10 +60,10 @@ static vm_fault_t ttm_bo_vm_fault_idle(struct ttm_buffer_object *bo, ttm_bo_get(bo); mmap_read_unlock(vmf->vma->vm_mm); - (void)dma_resv_wait_timeout(bo->base.resv, + (void)dma_resv_wait_timeout(amdkcl_ttm_resvp(bo), DMA_RESV_USAGE_KERNEL, true, MAX_SCHEDULE_TIMEOUT); - dma_resv_unlock(bo->base.resv); + dma_resv_unlock(amdkcl_ttm_resvp(bo)); ttm_bo_put(bo); return VM_FAULT_RETRY; } @@ -122,7 +122,7 @@ vm_fault_t ttm_bo_vm_reserve(struct ttm_buffer_object *bo, * for reserve, and if it fails, retry the fault after waiting * for the buffer to become unreserved. */ - if (unlikely(!dma_resv_trylock(bo->base.resv))) { + if (unlikely(!dma_resv_trylock(amdkcl_ttm_resvp(bo)))) { /* * If the fault allows retry and this is the first * fault attempt, we try to release the mmap_lock @@ -132,16 +132,16 @@ vm_fault_t ttm_bo_vm_reserve(struct ttm_buffer_object *bo, if (!(vmf->flags & FAULT_FLAG_RETRY_NOWAIT)) { ttm_bo_get(bo); mmap_read_unlock(vmf->vma->vm_mm); - if (!dma_resv_lock_interruptible(bo->base.resv, + if (!dma_resv_lock_interruptible(amdkcl_ttm_resvp(bo), NULL)) - dma_resv_unlock(bo->base.resv); + dma_resv_unlock(amdkcl_ttm_resvp(bo)); ttm_bo_put(bo); } return VM_FAULT_RETRY; } - if (dma_resv_lock_interruptible(bo->base.resv, NULL)) + if (dma_resv_lock_interruptible(amdkcl_ttm_resvp(bo), NULL)) return VM_FAULT_NOPAGE; } @@ -151,7 +151,7 @@ vm_fault_t ttm_bo_vm_reserve(struct ttm_buffer_object *bo, */ if (bo->ttm && (bo->ttm->page_flags & TTM_TT_FLAG_EXTERNAL)) { if (!(bo->ttm->page_flags & TTM_TT_FLAG_EXTERNAL_MAPPABLE)) { - dma_resv_unlock(bo->base.resv); + dma_resv_unlock(amdkcl_ttm_resvp(bo)); return VM_FAULT_SIGBUS; } } @@ -341,7 +341,7 @@ vm_fault_t ttm_bo_vm_fault(struct vm_fault *vmf) if (ret == VM_FAULT_RETRY && !(vmf->flags & FAULT_FLAG_RETRY_NOWAIT)) return ret; - dma_resv_unlock(bo->base.resv); + dma_resv_unlock(amdkcl_ttm_resvp(bo)); return ret; } diff --git a/drivers/gpu/drm/ttm/ttm_execbuf_util.c b/drivers/gpu/drm/ttm/ttm_execbuf_util.c index f1c60fa80c2d1..b7b085f3dd360 100644 --- a/drivers/gpu/drm/ttm/ttm_execbuf_util.c +++ b/drivers/gpu/drm/ttm/ttm_execbuf_util.c @@ -35,7 +35,7 @@ static void ttm_eu_backoff_reservation_reverse(struct list_head *list, list_for_each_entry_continue_reverse(entry, list, head) { struct ttm_buffer_object *bo = entry->bo; - dma_resv_unlock(bo->base.resv); + dma_resv_unlock(amdkcl_ttm_resvp(bo)); } } @@ -51,7 +51,7 @@ void ttm_eu_backoff_reservation(struct ww_acquire_ctx *ticket, struct ttm_buffer_object *bo = entry->bo; ttm_bo_move_to_lru_tail_unlocked(bo); - dma_resv_unlock(bo->base.resv); + dma_resv_unlock(amdkcl_ttm_resvp(bo)); } if (ticket) @@ -99,7 +99,7 @@ int ttm_eu_reserve_buffers(struct ww_acquire_ctx *ticket, num_fences = max(entry->num_shared, 1u); if (!ret) { - ret = dma_resv_reserve_fences(bo->base.resv, + ret = dma_resv_reserve_fences(amdkcl_ttm_resvp(bo), num_fences); if (!ret) continue; @@ -116,7 +116,7 @@ int ttm_eu_reserve_buffers(struct ww_acquire_ctx *ticket, } if (!ret) - ret = dma_resv_reserve_fences(bo->base.resv, + ret = dma_resv_reserve_fences(amdkcl_ttm_resvp(bo), num_fences); if (unlikely(ret != 0)) { @@ -150,10 +150,10 @@ void ttm_eu_fence_buffer_objects(struct ww_acquire_ctx *ticket, list_for_each_entry(entry, list, head) { struct ttm_buffer_object *bo = entry->bo; - dma_resv_add_fence(bo->base.resv, fence, entry->num_shared ? + dma_resv_add_fence(amdkcl_ttm_resvp(bo), fence, entry->num_shared ? DMA_RESV_USAGE_READ : DMA_RESV_USAGE_WRITE); ttm_bo_move_to_lru_tail_unlocked(bo); - dma_resv_unlock(bo->base.resv); + dma_resv_unlock(amdkcl_ttm_resvp(bo)); } if (ticket) ww_acquire_fini(ticket); diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c index 1c50cadd96e5e..550ead4d5b838 100644 --- a/drivers/gpu/drm/ttm/ttm_tt.c +++ b/drivers/gpu/drm/ttm/ttm_tt.c @@ -69,7 +69,7 @@ int ttm_tt_create(struct ttm_buffer_object *bo, bool zero_alloc) struct drm_device *ddev = bo->base.dev; uint32_t page_flags = 0; - dma_resv_assert_held(bo->base.resv); + dma_resv_assert_held(amdkcl_ttm_resvp(bo)); if (bo->ttm) return 0; diff --git a/include/drm/ttm/ttm_bo.h b/include/drm/ttm/ttm_bo.h index ef0f52f56ebc6..b0a046e7edeea 100644 --- a/include/drm/ttm/ttm_bo.h +++ b/include/drm/ttm/ttm_bo.h @@ -37,6 +37,9 @@ #include #include "ttm_device.h" +#ifndef HAVE_CONFIG_H +#define HAVE_DRM_GEM_OBJECT_RESV 1 +#endif /* Default number of pre-faulted pages in the TTM fault handler */ #if CONFIG_PGTABLE_LEVELS > 2 @@ -139,6 +142,11 @@ struct ttm_buffer_object { * reservation lock. */ struct sg_table *sg; + +#if !defined(HAVE_DRM_GEM_OBJECT_RESV) + struct dma_resv *resv; + struct dma_resv ttm_resv; +#endif }; #define TTM_BO_MAP_IOMEM_MASK 0x80 @@ -222,6 +230,14 @@ ttm_bo_get_unless_zero(struct ttm_buffer_object *bo) return bo; } +#if defined(HAVE_DRM_GEM_OBJECT_RESV) +#define amdkcl_ttm_resv(bo) ((bo)->base._resv) +#define amdkcl_ttm_resvp(bo) ((bo)->base.resv) +#else +#define amdkcl_ttm_resv(bo) ((bo)->ttm_resv) +#define amdkcl_ttm_resvp(bo) ((bo)->resv) +#endif + /** * ttm_bo_reserve: * @@ -256,14 +272,14 @@ static inline int ttm_bo_reserve(struct ttm_buffer_object *bo, if (WARN_ON(ticket)) return -EBUSY; - success = dma_resv_trylock(bo->base.resv); + success = dma_resv_trylock(amdkcl_ttm_resvp(bo)); return success ? 0 : -EBUSY; } if (interruptible) - ret = dma_resv_lock_interruptible(bo->base.resv, ticket); + ret = dma_resv_lock_interruptible(amdkcl_ttm_resvp(bo), ticket); else - ret = dma_resv_lock(bo->base.resv, ticket); + ret = dma_resv_lock(amdkcl_ttm_resvp(bo), ticket); if (ret == -EINTR) return -ERESTARTSYS; return ret; @@ -284,13 +300,13 @@ static inline int ttm_bo_reserve_slowpath(struct ttm_buffer_object *bo, struct ww_acquire_ctx *ticket) { if (interruptible) { - int ret = dma_resv_lock_slow_interruptible(bo->base.resv, + int ret = dma_resv_lock_slow_interruptible(amdkcl_ttm_resvp(bo), ticket); if (ret == -EINTR) ret = -ERESTARTSYS; return ret; } - dma_resv_lock_slow(bo->base.resv, ticket); + dma_resv_lock_slow(amdkcl_ttm_resvp(bo), ticket); return 0; } @@ -335,7 +351,7 @@ static inline void ttm_bo_move_null(struct ttm_buffer_object *bo, static inline void ttm_bo_unreserve(struct ttm_buffer_object *bo) { ttm_bo_move_to_lru_tail_unlocked(bo); - dma_resv_unlock(bo->base.resv); + dma_resv_unlock(amdkcl_ttm_resvp(bo)); } /** @@ -386,6 +402,7 @@ int ttm_bo_swapout(struct ttm_buffer_object *bo, struct ttm_operation_ctx *ctx, gfp_t gfp_flags); void ttm_bo_pin(struct ttm_buffer_object *bo); void ttm_bo_unpin(struct ttm_buffer_object *bo); + int ttm_mem_evict_first(struct ttm_device *bdev, struct ttm_resource_manager *man, const struct ttm_place *place, From 6a11cd81970a747e58f4bb2a4d530a5578f18a37 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 17 Apr 2020 11:36:17 +0800 Subject: [PATCH 0171/1868] drm/amdkcl: Test whether dma-buf dynamic locking is available It's a squash of 5e00d69a73fb drm/amdkcl: introduce parallel autoconf tests execution 57da2736175c drm/amdkcl: Test whether drm_gem_map_attach() wants 2 args a881ad26f08d drm/amdkcl: Test whether dma-buf dynamic locking is available Signed-off-by: Flora Cui Signed-off-by: Jack Gui Signed-off-by: Adam Yang Reviewed-by: Flora Cui Reviewed-by: Rui Teng Signed-off-by: Slava Grigorev --- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 254 ++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h | 9 + drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 | 16 ++ .../gpu/drm/amd/dkms/m4/drm-gem-map-attach.m4 | 14 + 4 files changed, 293 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-gem-map-attach.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index 8794a82e08cce..d0d6394394a08 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -42,6 +42,146 @@ #include #include +static int +__dma_resv_make_exclusive(struct dma_resv *obj) +{ + struct dma_fence **fences; + unsigned int count; + int r; + + if (!dma_resv_shared_list(obj)) /* no shared fences to convert */ + return 0; + + r = dma_resv_get_fences(obj, NULL, &count, &fences); + if (r) + return r; + + if (count == 0) { + /* Now that was unexpected. */ + } else if (count == 1) { + dma_resv_add_excl_fence(obj, fences[0]); + dma_fence_put(fences[0]); + kfree(fences); + } else { + struct dma_fence_array *array; + + array = dma_fence_array_create(count, fences, + dma_fence_context_alloc(1), 0, + false); + if (!array) + goto err_fences_put; + + dma_resv_add_excl_fence(obj, &array->base); + dma_fence_put(&array->base); + } + + return 0; + +err_fences_put: + while (count--) + dma_fence_put(fences[count]); + kfree(fences); + return -ENOMEM; +} + +#if !defined(HAVE_DMA_BUF_OPS_DYNAMIC_MAPPING) && \ + !defined(HAVE_STRUCT_DMA_BUF_OPS_PIN) +/** + * amdgpu_dma_buf_map_attach - &dma_buf_ops.attach implementation + * @dma_buf: Shared DMA buffer + * @attach: DMA-buf attachment + * + * Makes sure that the shared DMA buffer can be accessed by the target device. + * For now, simply pins it to the GTT domain, where it should be accessible by + * all DMA devices. + * + * Returns: + * 0 on success or a negative error code on failure. + */ +static int amdgpu_dma_buf_map_attach(struct dma_buf *dma_buf, +#ifndef HAVE_DRM_GEM_MAP_ATTACH_2ARGS + struct device *target_dev, +#endif + struct dma_buf_attachment *attach) +{ + struct drm_gem_object *obj = dma_buf->priv; + struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); + struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); + long r; + +#ifdef HAVE_DRM_GEM_MAP_ATTACH_2ARGS + r = drm_gem_map_attach(dma_buf, attach); +#else + r = drm_gem_map_attach(dma_buf, target_dev, attach); +#endif + if (r) + return r; + + r = amdgpu_bo_reserve(bo, false); + if (unlikely(r != 0)) + goto error_detach; + + + if (attach->dev->driver != adev->dev->driver) { + /* + * We only create shared fences for internal use, but importers + * of the dmabuf rely on exclusive fences for implicitly + * tracking write hazards. As any of the current fences may + * correspond to a write, we need to convert all existing + * fences on the reservation object into a single exclusive + * fence. + */ + r = __dma_resv_make_exclusive(amdkcl_ttm_resvp(&bo->tbo)); + if (r) + goto error_unreserve; + } + + /* pin buffer into GTT */ + r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT); + if (r) + goto error_unreserve; + + if (attach->dev->driver != adev->dev->driver) + bo->prime_shared_count++; + +error_unreserve: + amdgpu_bo_unreserve(bo); + +error_detach: + if (r) + drm_gem_map_detach(dma_buf, attach); + return r; +} + +/** + * amdgpu_dma_buf_map_detach - &dma_buf_ops.detach implementation + * @dma_buf: Shared DMA buffer + * @attach: DMA-buf attachment + * + * This is called when a shared DMA buffer no longer needs to be accessible by + * another device. For now, simply unpins the buffer from GTT. + */ +static void amdgpu_dma_buf_map_detach(struct dma_buf *dma_buf, + struct dma_buf_attachment *attach) +{ + struct drm_gem_object *obj = dma_buf->priv; + struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); + struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); + int ret = 0; + + ret = amdgpu_bo_reserve(bo, true); + if (unlikely(ret != 0)) + goto error; + + amdgpu_bo_unpin(bo); + if (attach->dev->driver != adev->dev->driver && bo->prime_shared_count) + bo->prime_shared_count--; + amdgpu_bo_unreserve(bo); + +error: + drm_gem_map_detach(dma_buf, attach); +} +#else /** * amdgpu_dma_buf_attach - &dma_buf_ops.attach implementation * @@ -229,6 +369,7 @@ static void amdgpu_dma_buf_unmap(struct dma_buf_attachment *attach, amdgpu_bo_unpin(bo); #endif } +#endif /** * amdgpu_dma_buf_begin_cpu_access - &dma_buf_ops.begin_cpu_access implementation @@ -272,6 +413,16 @@ static int amdgpu_dma_buf_begin_cpu_access(struct dma_buf *dma_buf, } const struct dma_buf_ops amdgpu_dmabuf_ops = { +#if !defined(HAVE_DMA_BUF_OPS_DYNAMIC_MAPPING) && \ + !defined(HAVE_STRUCT_DMA_BUF_OPS_PIN) + .attach = amdgpu_dma_buf_map_attach, + .detach = amdgpu_dma_buf_map_detach, + .map_dma_buf = drm_gem_map_dma_buf, + .unmap_dma_buf = drm_gem_unmap_dma_buf, +#else +#ifdef HAVE_DMA_BUF_OPS_DYNAMIC_MAPPING + .dynamic_mapping = true, +#endif .attach = amdgpu_dma_buf_attach, #ifdef HAVE_STRUCT_DMA_BUF_OPS_PIN .pin = amdgpu_dma_buf_pin, @@ -279,6 +430,7 @@ const struct dma_buf_ops amdgpu_dmabuf_ops = { #endif .map_dma_buf = amdgpu_dma_buf_map, .unmap_dma_buf = amdgpu_dma_buf_unmap, +#endif .release = drm_gem_dmabuf_release, .begin_cpu_access = amdgpu_dma_buf_begin_cpu_access, .mmap = drm_gem_dmabuf_mmap, @@ -313,6 +465,107 @@ struct dma_buf *amdgpu_gem_prime_export(struct drm_gem_object *gobj, return buf; } +#if !defined(HAVE_DMA_BUF_OPS_DYNAMIC_MAPPING) && \ + !defined(HAVE_STRUCT_DMA_BUF_OPS_PIN) +/** + * amdgpu_gem_prime_get_sg_table - &drm_driver.gem_prime_get_sg_table + * implementation + * @obj: GEM buffer object (BO) + * + * Returns: + * A scatter/gather table for the pinned pages of the BO's memory. + */ +struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj) +{ + struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); + int npages = bo->tbo.ttm->num_pages; + + return drm_prime_pages_to_sg(obj->dev, bo->tbo.ttm->pages, npages); +} + +/** + * amdgpu_gem_prime_import_sg_table - &drm_driver.gem_prime_import_sg_table + * implementation + * @dev: DRM device + * @attach: DMA-buf attachment + * @sg: Scatter/gather table + * + * Imports shared DMA buffer memory exported by another device. + * + * Returns: + * A new GEM BO of the given DRM device, representing the memory + * described by the given DMA-buf attachment and scatter/gather table. + */ +struct drm_gem_object * +amdgpu_gem_prime_import_sg_table(struct drm_device *dev, + struct dma_buf_attachment *attach, + struct sg_table *sg) +{ + struct dma_resv *resv = attach->dmabuf->resv; + struct amdgpu_device *adev = drm_to_adev(dev); + struct amdgpu_bo *bo; + struct amdgpu_bo_param bp; + int ret; + + memset(&bp, 0, sizeof(bp)); + bp.size = attach->dmabuf->size; + bp.byte_align = PAGE_SIZE; + bp.domain = AMDGPU_GEM_DOMAIN_CPU; + bp.flags = 0; + bp.type = ttm_bo_type_sg; + bp.resv = resv; + dma_resv_lock(resv, NULL); + ret = amdgpu_bo_create(adev, &bp, &bo); + if (ret) + goto error; + + bo->tbo.sg = sg; + bo->tbo.ttm->sg = sg; + bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT; + bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT; + bo->prime_shared_count = 1; + + dma_resv_unlock(resv); + return &bo->tbo.base; + +error: + dma_resv_unlock(resv); + return ERR_PTR(ret); +} + +/** + * amdgpu_gem_prime_import - &drm_driver.gem_prime_import implementation + * @dev: DRM device + * @dma_buf: Shared DMA buffer + * + * The main work is done by the &drm_gem_prime_import helper, which in turn + * uses &amdgpu_gem_prime_import_sg_table. + * + * Returns: + * GEM BO representing the shared DMA buffer for the given device. + */ +struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev, + struct dma_buf *dma_buf) +{ + struct drm_gem_object *obj; + + if (dma_buf->ops == &amdgpu_dmabuf_ops) { + obj = dma_buf->priv; + if (obj->dev == dev) { + /* + * Importing dmabuf exported from out own gem increases + * refcount on gem itself instead of f_count of dmabuf. + */ + drm_gem_object_get(obj); + return obj; + } + } + + return drm_gem_prime_import(dev, dma_buf); +} + +#else + /** * amdgpu_dma_buf_create_obj - create BO for DMA-buf import * @@ -490,6 +743,7 @@ struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev, obj->import_attach = attach; return obj; } +#endif /** * amdgpu_dmabuf_is_xgmi_accessible - Check if xgmi available for P2P transfer diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h index 3e93b9b407a97..dd7c8ffa41cf4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h @@ -25,6 +25,15 @@ #include +#if !defined(HAVE_DMA_BUF_OPS_DYNAMIC_MAPPING) && \ + !defined(HAVE_STRUCT_DMA_BUF_OPS_PIN) +struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj); +struct drm_gem_object * +amdgpu_gem_prime_import_sg_table(struct drm_device *dev, + struct dma_buf_attachment *attach, + struct sg_table *sg); +#endif + struct dma_buf *amdgpu_gem_prime_export(struct drm_gem_object *gobj, int flags); struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev, diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 index dc74e703be9bd..3f408896f437b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 @@ -32,6 +32,22 @@ AC_DEFUN([AC_AMDGPU_DMA_BUF], [ AC_DEFINE(HAVE_STRUCT_DMA_BUF_OPS_PIN, 1, [struct dma_buf_ops->pin() is available]) + ], [ + dnl # + dnl # commit v5.4-rc4-863-g15fd552d186c + dnl # dma-buf: change DMA-buf locking convention v3 + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct dma_buf_ops *dma_buf_ops = NULL; + dma_buf_ops->dynamic_mapping = true; + ],[ + AC_DEFINE(HAVE_DMA_BUF_OPS_DYNAMIC_MAPPING, 1, + [dma_buf dynamic_mapping is available]) + ],[ + AC_AMDGPU_DRM_GEM_MAP_ATTACH + ]) ]) ]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-gem-map-attach.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-gem-map-attach.m4 new file mode 100644 index 0000000000000..031d62f21740f --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-gem-map-attach.m4 @@ -0,0 +1,14 @@ +dnl # +dnl # commit v4.17-rc3-491-ga19741e5e5a9 +dnl # dma_buf: remove device parameter from attach callback v2 +dnl # +AC_DEFUN([AC_AMDGPU_DRM_GEM_MAP_ATTACH], [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_gem_map_attach(NULL, NULL); + ], [drm_gem_map_attach], [drivers/gpu/drm/drm_prime.c], [ + AC_DEFINE(HAVE_DRM_GEM_MAP_ATTACH_2ARGS, 1, + [drm_gem_map_attach() wants 2 arguments]) + ]) +]) From 65edc1b273ea3b3995f75ad861817484e5f5a164 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 9 Dec 2019 14:15:16 +0800 Subject: [PATCH 0172/1868] drm/amdkcl: Test whether drm_drv->gem_prime_res_obj() is available It's a squash of 5e00d69a73fb drm/amdkcl: introduce parallel autoconf tests execution 22887005a0ef drm/amdkcl: Test whether drm_drv->gem_prime_res_obj() is available Signed-off-by: Flora Cui Signed-off-by: Jack Gui Signed-off-by: Slava Grigorev Change-Id: I60c3bf6ef7409f636ecb9912cda0b35967e170ad --- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 16 ++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 8 +++++++ drivers/gpu/drm/amd/backport/backport.h | 3 +++ .../dkms/m4/drm-driver-gem-prime-res-obj.m4 | 22 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 5 files changed, 50 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-prime-res-obj.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index d0d6394394a08..ddfa482c9188d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -465,6 +465,22 @@ struct dma_buf *amdgpu_gem_prime_export(struct drm_gem_object *gobj, return buf; } +#ifdef HAVE_DRM_DRIVER_GEM_PRIME_RES_OBJ +/** + * amdgpu_gem_prime_res_obj - &drm_driver.gem_prime_res_obj implementation + * @obj: GEM BO + * + * Returns: + * The BO's reservation object. + */ +struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *obj) +{ + struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); + + return amdkcl_ttm_resvp(&bo->tbo); +} +#endif + #if !defined(HAVE_DMA_BUF_OPS_DYNAMIC_MAPPING) && \ !defined(HAVE_STRUCT_DMA_BUF_OPS_PIN) /** diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 769a647262823..ef4df69bfe0e9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2973,6 +2973,14 @@ static const struct drm_driver amdgpu_kms_driver = { #endif .gem_prime_import = amdgpu_gem_prime_import, +#ifdef HAVE_DRM_DRIVER_GEM_PRIME_RES_OBJ + .gem_prime_res_obj = amdgpu_gem_prime_res_obj, +#endif +#if !defined(HAVE_DMA_BUF_OPS_DYNAMIC_MAPPING) && \ + !defined(HAVE_STRUCT_DMA_BUF_OPS_PIN) + .gem_prime_get_sg_table = amdgpu_gem_prime_get_sg_table, + .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table, +#endif .name = DRIVER_NAME, .desc = DRIVER_DESC, diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 02f790b540220..bee3d491206e1 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -34,6 +34,9 @@ #include #include #include +#ifdef HAVE_DRM_DRIVER_GEM_PRIME_RES_OBJ +#include +#endif #include #include #include diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-prime-res-obj.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-prime-res-obj.m4 new file mode 100644 index 0000000000000..cf63fed2c4727 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-prime-res-obj.m4 @@ -0,0 +1,22 @@ +dnl # +dnl # commit v5.3-rc1-325-g51c98747113e +dnl # drm/amdgpu: Fill out gem_object->resv +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DRIVER_GEM_PRIME_RES_OBJ], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DRMP_H + struct vm_area_struct; + #include + #else + #include + #endif + ], [ + struct drm_driver *drv = NULL; + drv->gem_prime_res_obj(NULL); + ], [ + AC_DEFINE(HAVE_DRM_DRIVER_GEM_PRIME_RES_OBJ, 1, + [drm_driver->gem_prime_res_obj() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 308bd76a19a9a..cceaf0c361193 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -63,6 +63,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS AC_AMDGPU_DRM_DP_CEC_CORRELATION_FUNCTIONS AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_RESUME + AC_AMDGPU_DRM_DRIVER_GEM_PRIME_RES_OBJ AC_AMDGPU___DRM_ATOMIC_HELPER_CRTC_RESET AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION AC_AMDGPU_MEM_ENCRYPT_ACTIVE From 6d485259f72a6efdd173f997107fd54f45d805dc Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 6 Nov 2019 13:03:11 +0800 Subject: [PATCH 0173/1868] drm/amdkcl: add AMDKCL_AMDGPU_DMABUF_OPS v2:missing gem_prime_pin pointer Signed-off-by: Flora Cui Acked-by: Feifei Xu Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 63 +++++++++++++++++++-- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h | 8 +++ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 7 +++ drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/backport/kcl_drm_backport.h | 9 +++ 7 files changed, 90 insertions(+), 4 deletions(-) create mode 100644 include/kcl/backport/kcl_drm_backport.h diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index f3980b40f2cef..714da44aeabb6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -425,6 +425,10 @@ struct amdgpu_clock { uint32_t max_pixel_clock; }; +#if defined(AMDKCL_AMDGPU_DMABUF_OPS) +extern const struct dma_buf_ops amdgpu_dmabuf_ops; +#endif + /* sub-allocation manager, it has to be protected by another lock. * By conception this is an helper for other part of the driver * like the indirect buffer or semaphore, which both have their diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c index c272461d70a9a..7d004a7ee37a9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c @@ -515,9 +515,11 @@ int amdgpu_amdkfd_get_dmabuf_info(struct amdgpu_device *adev, int dma_buf_fd, if (IS_ERR(dma_buf)) return PTR_ERR(dma_buf); +#if defined(AMDKCL_AMDGPU_DMABUF_OPS) if (dma_buf->ops != &amdgpu_dmabuf_ops) /* Can't handle non-graphics buffers */ goto out_put; +#endif obj = dma_buf->priv; if (obj->dev->driver != adev_to_drm(adev)->driver) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index ddfa482c9188d..0656f0da465c6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -42,6 +42,7 @@ #include #include +#if defined(AMDKCL_AMDGPU_DMABUF_OPS) static int __dma_resv_make_exclusive(struct dma_resv *obj) { @@ -437,6 +438,7 @@ const struct dma_buf_ops amdgpu_dmabuf_ops = { .vmap = drm_gem_dmabuf_vmap, .vunmap = drm_gem_dmabuf_vunmap, }; +#endif /** * amdgpu_gem_prime_export - &drm_driver.gem_prime_export implementation @@ -459,8 +461,10 @@ struct dma_buf *amdgpu_gem_prime_export(struct drm_gem_object *gobj, return ERR_PTR(-EPERM); buf = drm_gem_prime_export(gobj, flags); +#if defined(AMDKCL_AMDGPU_DMABUF_OPS) if (!IS_ERR(buf)) buf->ops = &amdgpu_dmabuf_ops; +#endif return buf; } @@ -539,7 +543,10 @@ amdgpu_gem_prime_import_sg_table(struct drm_device *dev, bo->tbo.ttm->sg = sg; bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT; bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT; - bo->prime_shared_count = 1; +#if defined(AMDKCL_AMDGPU_DMABUF_OPS) + if (attach->dmabuf->ops != &amdgpu_dmabuf_ops) +#endif + bo->prime_shared_count = 1; dma_resv_unlock(resv); return &bo->tbo.base; @@ -549,6 +556,7 @@ amdgpu_gem_prime_import_sg_table(struct drm_device *dev, return ERR_PTR(ret); } +#ifdef AMDKCL_AMDGPU_DMABUF_OPS /** * amdgpu_gem_prime_import - &drm_driver.gem_prime_import implementation * @dev: DRM device @@ -579,9 +587,8 @@ struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev, return drm_gem_prime_import(dev, dma_buf); } - +#endif #else - /** * amdgpu_dma_buf_create_obj - create BO for DMA-buf import * @@ -711,7 +718,6 @@ static const struct dma_buf_attach_ops amdgpu_dma_buf_attach_ops = { .move_notify = amdgpu_dma_buf_move_notify }; #endif - /** * amdgpu_gem_prime_import - &drm_driver.gem_prime_import implementation * @dev: DRM device @@ -761,6 +767,53 @@ struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev, } #endif +#ifndef AMDKCL_AMDGPU_DMABUF_OPS +int amdgpu_gem_prime_pin(struct drm_gem_object *obj) +{ + struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); + long ret = 0; + + ret = amdgpu_bo_reserve(bo, false); + if (unlikely(ret != 0)) + return ret; + + /* + * Wait for all shared fences to complete before we switch to future + * use of exclusive fence on this prime shared bo. + */ + ret = dma_resv_wait_timeout_rcu(bo->tbo.resv, true, false, + MAX_SCHEDULE_TIMEOUT); + if (unlikely(ret < 0)) { + DRM_DEBUG_PRIME("Fence wait failed: %li\n", ret); + amdgpu_bo_unreserve(bo); + return ret; + } + + /* pin buffer into GTT */ + ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT); + if (likely(ret == 0)) + bo->prime_shared_count++; + + amdgpu_bo_unreserve(bo); + return ret; +} + +void amdgpu_gem_prime_unpin(struct drm_gem_object *obj) +{ + struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); + int ret = 0; + + ret = amdgpu_bo_reserve(bo, true); + if (unlikely(ret != 0)) + return; + + amdgpu_bo_unpin(bo); + if (bo->prime_shared_count) + bo->prime_shared_count--; + amdgpu_bo_unreserve(bo); +} +#endif + /** * amdgpu_dmabuf_is_xgmi_accessible - Check if xgmi available for P2P transfer * @@ -779,9 +832,11 @@ bool amdgpu_dmabuf_is_xgmi_accessible(struct amdgpu_device *adev, if (obj->import_attach) { struct dma_buf *dma_buf = obj->import_attach->dmabuf; +#if defined(AMDKCL_AMDGPU_DMABUF_OPS) if (dma_buf->ops != &amdgpu_dmabuf_ops) /* No XGMI with non AMD GPUs */ return false; +#endif gobj = dma_buf->priv; bo = gem_to_amdgpu_bo(gobj); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h index dd7c8ffa41cf4..db75327913c95 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h @@ -36,10 +36,18 @@ amdgpu_gem_prime_import_sg_table(struct drm_device *dev, struct dma_buf *amdgpu_gem_prime_export(struct drm_gem_object *gobj, int flags); +#if defined(AMDKCL_AMDGPU_DMABUF_OPS) struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev, struct dma_buf *dma_buf); +#else +int amdgpu_gem_prime_pin(struct drm_gem_object *obj); +void amdgpu_gem_prime_unpin(struct drm_gem_object *obj); +#endif bool amdgpu_dmabuf_is_xgmi_accessible(struct amdgpu_device *adev, struct amdgpu_bo *bo); +#ifdef HAVE_DRM_DRIVER_GEM_PRIME_RES_OBJ +struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *); +#endif extern const struct dma_buf_ops amdgpu_dmabuf_ops; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index ef4df69bfe0e9..1896902943c57 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2972,7 +2972,13 @@ static const struct drm_driver amdgpu_kms_driver = { .show_fdinfo = amdgpu_show_fdinfo, #endif +#if defined(AMDKCL_AMDGPU_DMABUF_OPS) .gem_prime_import = amdgpu_gem_prime_import, +#else + .gem_prime_import = drm_gem_prime_import, + .gem_prime_pin = amdgpu_gem_prime_pin, + .gem_prime_unpin = amdgpu_gem_prime_unpin, +#endif #ifdef HAVE_DRM_DRIVER_GEM_PRIME_RES_OBJ .gem_prime_res_obj = amdgpu_gem_prime_res_obj, #endif @@ -2982,6 +2988,7 @@ static const struct drm_driver amdgpu_kms_driver = { .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table, #endif + .gem_prime_mmap = drm_gem_prime_mmap, .name = DRIVER_NAME, .desc = DRIVER_DESC, .date = DRIVER_DATE, diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index bee3d491206e1..786b0e8246e62 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -40,6 +40,7 @@ #include #include #include +#include #include #include #include diff --git a/include/kcl/backport/kcl_drm_backport.h b/include/kcl/backport/kcl_drm_backport.h new file mode 100644 index 0000000000000..1450036960b9c --- /dev/null +++ b/include/kcl/backport/kcl_drm_backport.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef AMDKCL_DRM_BACKPORT_H +#define AMDKCL_DRM_BACKPORT_H + +#if DRM_VERSION_CODE >= DRM_VERSION(4, 17, 0) +#define AMDKCL_AMDGPU_DMABUF_OPS +#endif + +#endif/*AMDKCL_DRM_BACKPORT_H*/ From ef1c730222a6fffd4a272b708b15a1434294218f Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Sat, 10 Oct 2015 17:11:12 +0800 Subject: [PATCH 0174/1868] drm/amdgpu: [hybrid] add query for aperture va range Signed-off-by: Flora Cui Reviewed-by: Jammy Zhou Reviewed-by: Alex Deucher Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 18 +++++++++++++ include/uapi/drm/amdgpu_drm.h | 35 +++++++++++++++++++++++++ 2 files changed, 53 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index 24e0c7b812a9c..27e3b962e416e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -581,6 +581,24 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) return -EINVAL; switch (info->query) { + case AMDGPU_INFO_VIRTUAL_RANGE: { + struct drm_amdgpu_virtual_range range_info; + + switch (info->virtual_range.aperture) { + case AMDGPU_SUA_APERTURE_PRIVATE: + range_info.start = adev->gmc.private_aperture_start; + range_info.end = adev->gmc.private_aperture_end; + break; + case AMDGPU_SUA_APERTURE_SHARED: + range_info.start = adev->gmc.shared_aperture_start; + range_info.end = adev->gmc.shared_aperture_end; + break; + default: + return -EINVAL; + } + return copy_to_user(out, &range_info, + min((size_t)size, sizeof(range_info))) ? -EFAULT : 0; + } case AMDGPU_INFO_ACCEL_WORKING: ui32 = adev->accel_working; return copy_to_user(out, &ui32, min(size, 4u)) ? -EFAULT : 0; diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index da8f1afb16a72..d137704bb8670 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -934,6 +934,12 @@ struct drm_amdgpu_cs_chunk_cp_gfx_shadow { /* query last page fault info */ #define AMDGPU_INFO_GPUVM_FAULT 0x23 +/* Hybrid Stack Specific Defs*/ +/* gpu capability */ +#define AMDGPU_INFO_CAPABILITY 0x50 +/* virtual range */ +#define AMDGPU_INFO_VIRTUAL_RANGE 0x51 + #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff #define AMDGPU_INFO_MMR_SH_INDEX_SHIFT 8 @@ -990,6 +996,11 @@ struct drm_amdgpu_info { __u32 flags; } read_mmr_reg; + struct { + uint32_t aperture; + uint32_t _pad; + } virtual_range; + struct drm_amdgpu_query_fw query_fw; struct { @@ -1302,6 +1313,30 @@ struct drm_color_ctm_3x4 { __u64 matrix[12]; }; +/** + * Definition of System Unified Address (SUA) apertures + */ +#define AMDGPU_SUA_APERTURE_PRIVATE 1 +#define AMDGPU_SUA_APERTURE_SHARED 2 +struct drm_amdgpu_virtual_range { + uint64_t start; + uint64_t end; +}; + + +/* + * Definition of free sync enter and exit signals + * We may have more options in the future + */ +#define AMDGPU_FREESYNC_FULLSCREEN_ENTER 1 +#define AMDGPU_FREESYNC_FULLSCREEN_EXIT 2 + +struct drm_amdgpu_freesync { + __u32 op; /* AMDGPU_FREESYNC_FULLSCREEN_ENTER or */ + /* AMDGPU_FREESYNC_FULLSCREEN_ENTER */ + __u32 spare[7]; +}; + #if defined(__cplusplus) } #endif From 1a7ae1c32c1caea57524647d125fd23c2a68415d Mon Sep 17 00:00:00 2001 From: "Le.Ma" Date: Thu, 14 Sep 2017 15:53:13 +0800 Subject: [PATCH 0175/1868] drm/amdgpu: [hybrid] add AMDGPU VERSION Signed-off-by: Le.Ma --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 1896902943c57..87c15b3e2d1cf 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -123,6 +123,7 @@ #define KMS_DRIVER_MINOR 59 #define KMS_DRIVER_PATCHLEVEL 0 +#define AMDGPU_VERSION "19.10.9.418" /* * amdgpu.debug module options. Are all disabled by default */ @@ -3062,6 +3063,10 @@ static int __init amdgpu_init(void) goto error_fence; DRM_INFO("amdgpu kernel modesetting enabled.\n"); + + DRM_INFO("amdgpu version: %s\n", AMDGPU_VERSION); + DRM_INFO("OS DRM version: %d.%d.%d\n", DRM_VER, DRM_PATCH, DRM_SUB); + amdgpu_register_atpx_handler(); amdgpu_acpi_detect(); @@ -3096,3 +3101,4 @@ module_exit(amdgpu_exit); MODULE_AUTHOR(DRIVER_AUTHOR); MODULE_DESCRIPTION(DRIVER_DESC); MODULE_LICENSE("GPL and additional rights"); +MODULE_VERSION(AMDGPU_VERSION); From 61ff54df39b80ef0e46796acbd0d3b15dfd1004a Mon Sep 17 00:00:00 2001 From: Guchun Chen Date: Thu, 29 Apr 2021 18:05:44 +0800 Subject: [PATCH 0176/1868] drm/amdgpu:[hybrid] use DEFINE_SHOW_ATTRIBUTE to create amdgpu_gpu_recover node This will get rid of the limitation of DEFINE_DEBUGFS_ATTRIBUTE on old distros, otherwise amdgpu_gpu_recover is not exposed. Signed-off-by: Guchun Chen Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index 2f24a6aa13bf6..1e8afc0b7a62c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c @@ -940,9 +940,9 @@ static int amdgpu_debugfs_fence_info_show(struct seq_file *m, void *unused) * * Manually trigger a gpu reset at the next fence wait. */ -static int gpu_recover_get(void *data, u64 *val) +static int amdgpu_debugfs_gpu_recover_show(struct seq_file *m, void *unused) { - struct amdgpu_device *adev = (struct amdgpu_device *)data; + struct amdgpu_device *adev = (struct amdgpu_device *)m->private; struct drm_device *dev = adev_to_drm(adev); int r; @@ -955,7 +955,7 @@ static int gpu_recover_get(void *data, u64 *val) if (amdgpu_reset_domain_schedule(adev->reset_domain, &adev->reset_work)) flush_work(&adev->reset_work); - *val = atomic_read(&adev->reset_domain->reset_res); + // *val = atomic_read(&adev->reset_domain->reset_res); pm_runtime_mark_last_busy(dev->dev); pm_runtime_put_autosuspend(dev->dev); @@ -964,8 +964,7 @@ static int gpu_recover_get(void *data, u64 *val) } DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_fence_info); -DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_debugfs_gpu_recover_fops, gpu_recover_get, NULL, - "%lld\n"); +DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_gpu_recover); static void amdgpu_debugfs_reset_work(struct work_struct *work) { From 8be12d1f75f3d29980183ea9fff2a992bd85bdcc Mon Sep 17 00:00:00 2001 From: Jammy Zhou Date: Mon, 9 Nov 2015 13:39:37 +0800 Subject: [PATCH 0177/1868] drm/amdgpu: [hybrid] expose the pinning capability to user space The module option amdgpu.no_evict is added, and it is disabled by default now. Signed-off-by: Jammy Zhou Reviewed-by: Chunming Zhou Signed-off-by: Junwei Zhang Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 +++ drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 8 ++++++++ include/uapi/drm/amdgpu_drm.h | 4 ++++ 5 files changed, 17 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 714da44aeabb6..e5835f4060b17 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -189,6 +189,7 @@ extern int amdgpu_exp_hw_support; extern int amdgpu_dc; extern int amdgpu_sched_jobs; extern int amdgpu_sched_hw_submission; +extern int amdgpu_no_evict; extern uint amdgpu_pcie_gen_cap; extern uint amdgpu_pcie_lane_cap; extern u64 amdgpu_cg_mask; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 87c15b3e2d1cf..31092634bb6a8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -162,6 +162,7 @@ int amdgpu_exp_hw_support; int amdgpu_dc = -1; int amdgpu_sched_jobs = 32; int amdgpu_sched_hw_submission = 2; +int amdgpu_no_evict; uint amdgpu_pcie_gen_cap; uint amdgpu_pcie_lane_cap; u64 amdgpu_cg_mask = 0xffffffffffffffff; @@ -475,6 +476,8 @@ module_param_named(sched_hw_submission, amdgpu_sched_hw_submission, int, 0444); MODULE_PARM_DESC(ppfeaturemask, "all power features enabled (default))"); module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); +MODULE_PARM_DESC(no_evict, "Support pinning request from user space (1 = enable, 0 = disable (default))"); +module_param_named(no_evict, amdgpu_no_evict, int, 0444); /** * DOC: forcelongtraining (uint) * Force long memory training in resume. diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index 378546542f212..ef3c3f43b59d4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -336,6 +336,7 @@ int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data, AMDGPU_GEM_CREATE_EXPLICIT_SYNC | AMDGPU_GEM_CREATE_ENCRYPTED | AMDGPU_GEM_CREATE_GFX12_DCC | + AMDGPU_GEM_CREATE_NO_EVICT | AMDGPU_GEM_CREATE_DISCARDABLE)) return -EINVAL; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index f48fefcf67241..39fdd8b864588 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -653,6 +653,14 @@ int amdgpu_bo_create(struct amdgpu_device *adev, if (bp->type == ttm_bo_type_device) bo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; + if ((bp->flags & AMDGPU_GEM_CREATE_NO_EVICT) && amdgpu_no_evict) { + r = amdgpu_bo_reserve(bo, false); + if (unlikely(r != 0)) + return r; + r = amdgpu_bo_pin(bo, bp->domain); + amdgpu_bo_unreserve(bo); + } + return 0; fail_unreserve: diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index d137704bb8670..29bfcf7158740 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -174,6 +174,10 @@ extern "C" { /* Set PTE.D and recompress during GTT->VRAM moves according to TILING flags. */ #define AMDGPU_GEM_CREATE_GFX12_DCC (1 << 16) +/* hybrid specific */ +/* Flag that the memory allocation should be pinned */ +#define AMDGPU_GEM_CREATE_NO_EVICT (1ULL << 31) + struct drm_amdgpu_gem_create_in { /** the requested memory size */ __u64 bo_size; From 2620f6d2868c9e10249106443ecc6dc4195176f1 Mon Sep 17 00:00:00 2001 From: jimqu Date: Mon, 16 Nov 2015 14:03:15 +0800 Subject: [PATCH 0178/1868] drm/amdgpu: [hybrid] add query amdgpu capability function with this function, it could return capability to user space driver. Change-Id: Icad47e8d0621f9e8b8b9baedb751c11ded6c9449 Signed-off-by: JimQu Reviewed-by: Chunming Zhou Reviewed-by: Jammy Zhou Conflicts: drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c --- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 9 +++++++++ include/uapi/drm/amdgpu_drm.h | 5 +++++ 2 files changed, 14 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index 27e3b962e416e..95f30e16cdbc2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -1083,6 +1083,15 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) return -EINVAL; } } + case AMDGPU_INFO_CAPABILITY: { + struct drm_amdgpu_capability cap; + + memset(&cap, 0, sizeof(cap)); + if (amdgpu_no_evict) + cap.flag |= AMDGPU_CAPABILITY_PIN_MEM_FLAG; + return copy_to_user(out, &cap, + min((size_t)size, sizeof(cap))) ? -EFAULT : 0; + } case AMDGPU_INFO_SENSOR: { if (!adev->pm.dpm_enabled) return -ENOENT; diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index 29bfcf7158740..086d3bb912257 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -943,6 +943,8 @@ struct drm_amdgpu_cs_chunk_cp_gfx_shadow { #define AMDGPU_INFO_CAPABILITY 0x50 /* virtual range */ #define AMDGPU_INFO_VIRTUAL_RANGE 0x51 +/* query pin memory capability */ +#define AMDGPU_CAPABILITY_PIN_MEM_FLAG (1 << 0) #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff @@ -1327,6 +1329,9 @@ struct drm_amdgpu_virtual_range { uint64_t end; }; +struct drm_amdgpu_capability { + __u32 flag; +}; /* * Definition of free sync enter and exit signals From 47e4fe3c70ecf27981adaef1993c02b8e03be406 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 1 Sep 2016 12:33:01 +0800 Subject: [PATCH 0179/1868] drm/amdgpu: [hybrid] add AMDGPU_GEM_CREATE_TOP_DOWN flag so that the buffer could be allocated from the top of domain Change-Id: I7dc4ba02b78b18330c7fe00841970ab9cccbded5 Signed-off-by: Flora Cui Reviewed-by: Hawking Zhang Conflicts: drivers/gpu/drm/amd/amdgpu/amdgpu_object.c --- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 5 ++++- include/uapi/drm/amdgpu_drm.h | 2 ++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index 39fdd8b864588..1b69be22a6143 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -129,7 +129,7 @@ void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain) struct ttm_placement *placement = &abo->placement; struct ttm_place *places = abo->placements; u64 flags = abo->flags; - u32 c = 0; + u32 c = 0, i; if (domain & AMDGPU_GEM_DOMAIN_VRAM) { unsigned int visible_pfn = adev->gmc.visible_vram_size >> PAGE_SHIFT; @@ -227,6 +227,9 @@ void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain) BUG_ON(c > AMDGPU_BO_MAX_PLACEMENTS); + for (i = 0; i < c; i++) + if (flags & AMDGPU_GEM_CREATE_TOP_DOWN) + places[i].flags |= TTM_PL_FLAG_TOPDOWN; placement->num_placement = c; placement->placement = places; } diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index 086d3bb912257..8e16c5bfb0ed6 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -175,6 +175,8 @@ extern "C" { #define AMDGPU_GEM_CREATE_GFX12_DCC (1 << 16) /* hybrid specific */ +/* Flag that the memory allocation should be from top of domain */ +#define AMDGPU_GEM_CREATE_TOP_DOWN (1ULL << 30) /* Flag that the memory allocation should be pinned */ #define AMDGPU_GEM_CREATE_NO_EVICT (1ULL << 31) From e6d80c565c848164da110ec8cf02d59c42a47f3d Mon Sep 17 00:00:00 2001 From: Evan Quan Date: Thu, 6 Jul 2017 14:45:08 +0800 Subject: [PATCH 0180/1868] drm/amdgpu: [hybrid] always to use amdgpu to support CI/SI asics on hybrid - this patch is needed only by hybrid staging - we may update packing script to add cik_support system config in future. Then this commit will be not needed. Signed-off-by: Kent Russell Signed-off-by: Flora Cui Signed-off-by: Evan Quan Reviewed-by: Junwei Zhang Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/Kconfig | 8 ++++---- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 6 ++---- 2 files changed, 6 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/Kconfig b/drivers/gpu/drm/amd/amdgpu/Kconfig index 0051fb1b437fb..35c20e373b01b 100644 --- a/drivers/gpu/drm/amd/amdgpu/Kconfig +++ b/drivers/gpu/drm/amd/amdgpu/Kconfig @@ -55,11 +55,11 @@ config DRM_AMDGPU_CIK Choose this option if you want to enable support for CIK (Sea Islands) asics. - CIK is already supported in radeon. Support for CIK in amdgpu - will be disabled by default and is still provided by radeon. - Use module options to override this: + CIK is already supported in radeon. If you enable this option, + support for CIK will be provided by amdgpu and disabled in + radeon by default. Use module options to override this: - radeon.cik_support=0 amdgpu.cik_support=1 + radeon.cik_support=1 amdgpu.cik_support=0 config DRM_AMDGPU_USERPTR bool "Always enable userptr write support" diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 31092634bb6a8..9331c331ce3b4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -604,14 +604,13 @@ module_param_named(timeout_period, amdgpu_watchdog_timer.period, uint, 0644); */ #ifdef CONFIG_DRM_AMDGPU_SI -#if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE) +#if (0 && (IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE))) int amdgpu_si_support; MODULE_PARM_DESC(si_support, "SI support (1 = enabled, 0 = disabled (default))"); #else int amdgpu_si_support = 1; MODULE_PARM_DESC(si_support, "SI support (1 = enabled (default), 0 = disabled)"); #endif - module_param_named(si_support, amdgpu_si_support, int, 0444); #endif @@ -623,14 +622,13 @@ module_param_named(si_support, amdgpu_si_support, int, 0444); */ #ifdef CONFIG_DRM_AMDGPU_CIK -#if IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE) +#if (0 && (IS_ENABLED(CONFIG_DRM_RADEON) || IS_ENABLED(CONFIG_DRM_RADEON_MODULE))) int amdgpu_cik_support; MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled, 0 = disabled (default))"); #else int amdgpu_cik_support = 1; MODULE_PARM_DESC(cik_support, "CIK support (1 = enabled (default), 0 = disabled)"); #endif - module_param_named(cik_support, amdgpu_cik_support, int, 0444); #endif From 95f6116f68700e79c9fb56e6a0c949eb082b361f Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 23 Apr 2021 16:38:13 +0800 Subject: [PATCH 0181/1868] drm/amdgpu:[hybrid] unpin bo per exit Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index ef3c3f43b59d4..4253e98b56f30 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -90,6 +90,13 @@ static void amdgpu_gem_object_free(struct drm_gem_object *gobj) struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj); if (robj) { + if (robj->flags & AMDGPU_GEM_CREATE_NO_EVICT) { + if (!amdgpu_bo_reserve(robj, false)) { + amdgpu_bo_unpin(robj); + amdgpu_bo_unreserve(robj); + } + } + amdgpu_hmm_unregister(robj); amdgpu_bo_unref(&robj); } From 065d22ed3bf642291465eae088119d75b80f4906 Mon Sep 17 00:00:00 2001 From: Kevin Wang Date: Thu, 30 Aug 2018 12:14:28 +0800 Subject: [PATCH 0182/1868] drm/amdgpu: [hybrid] add semaphore object support Signed-off-by: Kevin Wang --- drivers/gpu/drm/amd/amdgpu/Makefile | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 + drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 5 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h | 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 8 + drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 7 + drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c | 462 ++++++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_sem.h | 64 ++++ include/uapi/drm/amdgpu_drm.h | 37 ++ 11 files changed, 590 insertions(+), 3 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_sem.h diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index 1c9429376f66b..05bdbf365fc4c 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -76,7 +76,7 @@ amdgpu-y += amdgpu_device.o amdgpu_doorbell_mgr.o amdgpu_kms.o \ amdgpu_gtt_mgr.o amdgpu_preempt_mgr.o amdgpu_vram_mgr.o amdgpu_virt.o \ amdgpu_atomfirmware.o amdgpu_vf_error.o amdgpu_sched.o \ amdgpu_debugfs.o amdgpu_ids.o amdgpu_gmc.o amdgpu_mmhub.o amdgpu_hdp.o \ - amdgpu_xgmi.o amdgpu_csa.o amdgpu_ras.o amdgpu_vm_cpu.o \ + amdgpu_xgmi.o amdgpu_csa.o amdgpu_ras.o amdgpu_vm_cpu.o amdgpu_sem.o amdgpu_gmc.o \ amdgpu_vm_sdma.o amdgpu_discovery.o amdgpu_ras_eeprom.o amdgpu_nbio.o \ amdgpu_umc.o smu_v11_0_i2c.o amdgpu_fru_eeprom.o amdgpu_rap.o \ amdgpu_fw_attestation.o amdgpu_securedisplay.o \ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index e5835f4060b17..b7e6a9acc8d8a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -73,6 +73,7 @@ #include "amdgpu_sync.h" #include "amdgpu_ring.h" #include "amdgpu_vm.h" +#include "amdgpu_sem.h" #include "amdgpu_dpm.h" #include "amdgpu_acp.h" #include "amdgpu_uvd.h" @@ -496,6 +497,8 @@ struct amdgpu_fpriv { struct mutex bo_list_lock; struct idr bo_list_handles; struct amdgpu_ctx_mgr ctx_mgr; + spinlock_t sem_handles_lock; + struct idr sem_handles; /** GPU partition selection */ uint32_t xcp_id; }; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index cb414a1c04dbb..f82cdb312846a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -40,6 +40,7 @@ #include "amdgpu_gmc.h" #include "amdgpu_gem.h" #include "amdgpu_ras.h" +#include "amdgpu_display.h" static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, struct amdgpu_device *adev, @@ -592,7 +593,7 @@ static int amdgpu_cs_p2_shadow(struct amdgpu_cs_parser *p, static int amdgpu_cs_pass2(struct amdgpu_cs_parser *p) { unsigned int ce_preempt = 0, de_preempt = 0; - int i, r; + int i, r = 0; for (i = 0; i < p->nchunks; ++i) { struct amdgpu_cs_chunk *chunk; @@ -639,7 +640,7 @@ static int amdgpu_cs_pass2(struct amdgpu_cs_parser *p) } } - return 0; + return amdgpu_sem_add_cs(p->ctx, p->entity, &p->job->sync); } /* Convert microseconds to bytes. */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c index c43d1b6e5d66b..178aa7c18dc2b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c @@ -216,6 +216,8 @@ static int amdgpu_ctx_init_entity(struct amdgpu_ctx *ctx, u32 hw_ip, GFP_KERNEL); if (!entity) return -ENOMEM; + INIT_LIST_HEAD(&entity->sem_dep_list); + mutex_init(&entity->sem_lock); ctx_prio = (ctx->override_priority == AMDGPU_CTX_PRIORITY_UNSET) ? ctx->init_priority : ctx->override_priority; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h index 85376baaa92f2..18b70d9239882 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.h @@ -39,6 +39,8 @@ struct amdgpu_ctx_entity { uint32_t hw_ip; uint64_t sequence; struct drm_sched_entity entity; + struct list_head sem_dep_list; + struct mutex sem_lock; struct dma_fence *fences[]; }; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 9331c331ce3b4..045598f0f94da 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2953,6 +2953,7 @@ const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(AMDGPU_SEM, amdgpu_sem_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW) }; static const struct drm_driver amdgpu_kms_driver = { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c index 8b512dc28df83..f57e97e6eed68 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c @@ -143,6 +143,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs, unsigned int i; int r = 0; + unsigned extra_nop = 0; if (num_ibs == 0) return -EINVAL; @@ -184,6 +185,11 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs, alloc_size = ring->funcs->emit_frame_size + num_ibs * ring->funcs->emit_ib_size; + if (job && !job->vm_needs_flush && ring->funcs->type == AMDGPU_RING_TYPE_GFX) { + extra_nop = 128; + alloc_size += extra_nop; + } + r = amdgpu_ring_alloc(ring, alloc_size); if (r) { dev_err(adev->dev, "scheduling IB failed (%d).\n", r); @@ -214,6 +220,8 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned int num_ibs, ring->funcs->insert_start(ring); if (job) { + amdgpu_ring_insert_nop(ring, extra_nop); /* prevent CE go too fast than DE */ + r = amdgpu_vm_flush(ring, job, need_pipe_sync); if (r) { amdgpu_ring_undo(ring); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index 95f30e16cdbc2..0f11987f307e9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -1416,6 +1416,8 @@ int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv) mutex_init(&fpriv->bo_list_lock); idr_init_base(&fpriv->bo_list_handles, 1); + spin_lock_init(&fpriv->sem_handles_lock); + idr_init(&fpriv->sem_handles); amdgpu_ctx_mgr_init(&fpriv->ctx_mgr, adev); @@ -1455,6 +1457,7 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev, struct amdgpu_device *adev = drm_to_adev(dev); struct amdgpu_fpriv *fpriv = file_priv->driver_priv; struct amdgpu_bo_list *list; + struct amdgpu_sem *sem; struct amdgpu_bo *pd; u32 pasid; int handle; @@ -1499,6 +1502,10 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev, idr_destroy(&fpriv->bo_list_handles); mutex_destroy(&fpriv->bo_list_lock); + idr_for_each_entry(&fpriv->sem_handles, sem, handle) + amdgpu_sem_destroy(fpriv, handle); + idr_destroy(&fpriv->sem_handles); + kfree(fpriv); file_priv->driver_priv = NULL; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c new file mode 100644 index 0000000000000..432072b28f5ae --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.c @@ -0,0 +1,462 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Chunming Zhou + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "amdgpu.h" +#include "amdgpu_sem.h" + +#define to_amdgpu_ctx_entity(e) \ + container_of((e), struct amdgpu_ctx_entity, entity) + +static int amdgpu_sem_entity_add(struct amdgpu_fpriv *fpriv, + struct drm_amdgpu_sem_in *in, + struct amdgpu_sem *sem); + +static void amdgpu_sem_core_free(struct kref *kref) +{ + struct amdgpu_sem_core *core = container_of( + kref, struct amdgpu_sem_core, kref); + + dma_fence_put(core->fence); + mutex_destroy(&core->lock); + kfree(core); +} + +static void amdgpu_sem_free(struct kref *kref) +{ + struct amdgpu_sem *sem = container_of( + kref, struct amdgpu_sem, kref); + + kref_put(&sem->base->kref, amdgpu_sem_core_free); + kfree(sem); +} + +static inline void amdgpu_sem_get(struct amdgpu_sem *sem) +{ + if (sem) + kref_get(&sem->kref); +} + +void amdgpu_sem_put(struct amdgpu_sem *sem) +{ + if (sem) + kref_put(&sem->kref, amdgpu_sem_free); +} + +static int amdgpu_sem_release(struct inode *inode, struct file *file) +{ + struct amdgpu_sem_core *core = file->private_data; + + /* set the core->file to null if file got released */ + mutex_lock(&core->lock); + core->file = NULL; + mutex_unlock(&core->lock); + + kref_put(&core->kref, amdgpu_sem_core_free); + return 0; +} + +static unsigned int amdgpu_sem_poll(struct file *file, poll_table *wait) +{ + return 0; +} + +static long amdgpu_sem_file_ioctl(struct file *file, unsigned int cmd, + unsigned long arg) +{ + return 0; +} + +static const struct file_operations amdgpu_sem_fops = { + .release = amdgpu_sem_release, + .poll = amdgpu_sem_poll, + .unlocked_ioctl = amdgpu_sem_file_ioctl, + .compat_ioctl = amdgpu_sem_file_ioctl, +}; + + +static inline struct amdgpu_sem *amdgpu_sem_lookup(struct amdgpu_fpriv *fpriv, u32 handle) +{ + struct amdgpu_sem *sem; + + spin_lock(&fpriv->sem_handles_lock); + + /* Check if we currently have a reference on the object */ + sem = idr_find(&fpriv->sem_handles, handle); + amdgpu_sem_get(sem); + + spin_unlock(&fpriv->sem_handles_lock); + + return sem; +} + +static struct amdgpu_sem_core *amdgpu_sem_core_alloc(void) +{ + struct amdgpu_sem_core *core; + + core = kzalloc(sizeof(*core), GFP_KERNEL); + if (!core) + return NULL; + + kref_init(&core->kref); + mutex_init(&core->lock); + return core; +} + +static struct amdgpu_sem *amdgpu_sem_alloc(void) +{ + struct amdgpu_sem *sem; + + sem = kzalloc(sizeof(*sem), GFP_KERNEL); + if (!sem) + return NULL; + + kref_init(&sem->kref); + INIT_LIST_HEAD(&sem->list); + + return sem; +} + +static int amdgpu_sem_create(struct amdgpu_fpriv *fpriv, u32 *handle) +{ + struct amdgpu_sem *sem; + struct amdgpu_sem_core *core; + int ret; + + sem = amdgpu_sem_alloc(); + core = amdgpu_sem_core_alloc(); + if (!sem || !core) { + kfree(sem); + kfree(core); + return -ENOMEM; + } + + sem->base = core; + + idr_preload(GFP_KERNEL); + spin_lock(&fpriv->sem_handles_lock); + + ret = idr_alloc(&fpriv->sem_handles, sem, 1, 0, GFP_NOWAIT); + + spin_unlock(&fpriv->sem_handles_lock); + idr_preload_end(); + + if (ret < 0) + return ret; + + *handle = ret; + return 0; +} + +static int amdgpu_sem_signal(struct amdgpu_fpriv *fpriv, + u32 handle, struct dma_fence *fence) +{ + struct amdgpu_sem *sem; + struct amdgpu_sem_core *core; + + sem = amdgpu_sem_lookup(fpriv, handle); + if (!sem) + return -EINVAL; + + core = sem->base; + mutex_lock(&core->lock); + dma_fence_put(core->fence); + core->fence = dma_fence_get(fence); + mutex_unlock(&core->lock); + + amdgpu_sem_put(sem); + return 0; +} + +static int amdgpu_sem_wait(struct amdgpu_fpriv *fpriv, + struct drm_amdgpu_sem_in *in) +{ + struct amdgpu_sem *sem; + int ret; + + sem = amdgpu_sem_lookup(fpriv, in->handle); + if (!sem) + return -EINVAL; + + ret = amdgpu_sem_entity_add(fpriv, in, sem); + amdgpu_sem_put(sem); + + return ret; +} + +static int amdgpu_sem_import(struct amdgpu_fpriv *fpriv, + int fd, u32 *handle) +{ + struct file *file = fget(fd); + struct amdgpu_sem *sem; + struct amdgpu_sem_core *core; + int ret; + + if (!file) + return -EINVAL; + + core = file->private_data; + if (!core) { + fput(file); + return -EINVAL; + } + + kref_get(&core->kref); + sem = amdgpu_sem_alloc(); + if (!sem) { + ret = -ENOMEM; + goto err_sem; + } + + sem->base = core; + + idr_preload(GFP_KERNEL); + spin_lock(&fpriv->sem_handles_lock); + + ret = idr_alloc(&fpriv->sem_handles, sem, 1, 0, GFP_NOWAIT); + + spin_unlock(&fpriv->sem_handles_lock); + idr_preload_end(); + + if (ret < 0) + goto err_out; + + *handle = ret; + fput(file); + return 0; +err_sem: + kref_put(&core->kref, amdgpu_sem_core_free); +err_out: + amdgpu_sem_put(sem); + fput(file); + return ret; + +} + +static int amdgpu_sem_export(struct amdgpu_fpriv *fpriv, + u32 handle, int *fd) +{ + struct amdgpu_sem *sem; + struct amdgpu_sem_core *core; + int ret; + + sem = amdgpu_sem_lookup(fpriv, handle); + if (!sem) + return -EINVAL; + + core = sem->base; + kref_get(&core->kref); + mutex_lock(&core->lock); + if (!core->file) { + core->file = anon_inode_getfile("sem_file", + &amdgpu_sem_fops, + core, 0); + if (IS_ERR(core->file)) { + mutex_unlock(&core->lock); + ret = -ENOMEM; + goto err_put_sem; + } + } else { + get_file(core->file); + } + mutex_unlock(&core->lock); + + ret = get_unused_fd_flags(O_CLOEXEC); + if (ret < 0) + goto err_put_file; + + fd_install(ret, core->file); + + *fd = ret; + amdgpu_sem_put(sem); + + return 0; + +err_put_file: + fput(core->file); +err_put_sem: + kref_put(&core->kref, amdgpu_sem_core_free); + amdgpu_sem_put(sem); + return ret; +} + +void amdgpu_sem_destroy(struct amdgpu_fpriv *fpriv, u32 handle) +{ + struct amdgpu_sem *sem = amdgpu_sem_lookup(fpriv, handle); + if (!sem) + return; + + spin_lock(&fpriv->sem_handles_lock); + idr_remove(&fpriv->sem_handles, handle); + spin_unlock(&fpriv->sem_handles_lock); + + kref_put(&sem->kref, amdgpu_sem_free); + kref_put(&sem->kref, amdgpu_sem_free); +} + +static struct dma_fence *amdgpu_sem_get_fence(struct amdgpu_fpriv *fpriv, + struct drm_amdgpu_sem_in *in) +{ + struct drm_sched_entity *entity; + struct amdgpu_ctx *ctx; + struct dma_fence *fence; + uint32_t ctx_id, ip_type, ip_instance, ring; + int r; + + ctx_id = in->ctx_id; + ip_type = in->ip_type; + ip_instance = in->ip_instance; + ring = in->ring; + ctx = amdgpu_ctx_get(fpriv, ctx_id); + if (!ctx) + return NULL; + r = amdgpu_ctx_get_entity(ctx, ip_type, + ip_instance, ring, &entity); + if (r) { + amdgpu_ctx_put(ctx); + return NULL; + } + /* get the last fence of this entity */ + fence = amdgpu_ctx_get_fence(ctx, entity, in->seq); + amdgpu_ctx_put(ctx); + + return fence; +} + +static int amdgpu_sem_entity_add(struct amdgpu_fpriv *fpriv, + struct drm_amdgpu_sem_in *in, + struct amdgpu_sem *sem) +{ + struct amdgpu_ctx *ctx; + struct amdgpu_sem_dep *dep; + struct drm_sched_entity *entity; + struct amdgpu_ctx_entity *centity; + uint32_t ctx_id, ip_type, ip_instance, ring; + int r; + + ctx_id = in->ctx_id; + ip_type = in->ip_type; + ip_instance = in->ip_instance; + ring = in->ring; + ctx = amdgpu_ctx_get(fpriv, ctx_id); + if (!ctx) + return -EINVAL; + r = amdgpu_ctx_get_entity(ctx, ip_type, + ip_instance, ring, &entity); + if (r) + goto err; + + dep = kzalloc(sizeof(*dep), GFP_KERNEL); + if (!dep) + goto err; + + INIT_LIST_HEAD(&dep->list); + dep->fence = dma_fence_get(sem->base->fence); + + centity = to_amdgpu_ctx_entity(entity); + mutex_lock(¢ity->sem_lock); + list_add(&dep->list, ¢ity->sem_dep_list); + mutex_unlock(¢ity->sem_lock); + +err: + amdgpu_ctx_put(ctx); + return r; +} + +int amdgpu_sem_add_cs(struct amdgpu_ctx *ctx, struct drm_sched_entity *entity, + struct amdgpu_sync *sync) +{ + struct amdgpu_sem_dep *dep, *tmp; + struct amdgpu_ctx_entity *centity = to_amdgpu_ctx_entity(entity); + int r = 0; + + if (list_empty(¢ity->sem_dep_list)) + return 0; + + mutex_lock(¢ity->sem_lock); + list_for_each_entry_safe(dep, tmp, ¢ity->sem_dep_list, + list) { + r = amdgpu_sync_fence(sync, dep->fence); + if (r) + goto err; + dma_fence_put(dep->fence); + list_del_init(&dep->list); + kfree(dep); + } +err: + mutex_unlock(¢ity->sem_lock); + return r; +} + +int amdgpu_sem_ioctl(struct drm_device *dev, void *data, + struct drm_file *filp) +{ + union drm_amdgpu_sem *args = data; + struct amdgpu_fpriv *fpriv = filp->driver_priv; + struct dma_fence *fence; + int r = 0; + + switch (args->in.op) { + case AMDGPU_SEM_OP_CREATE_SEM: + r = amdgpu_sem_create(fpriv, &args->out.handle); + break; + case AMDGPU_SEM_OP_WAIT_SEM: + r = amdgpu_sem_wait(fpriv, &args->in); + break; + case AMDGPU_SEM_OP_SIGNAL_SEM: + fence = amdgpu_sem_get_fence(fpriv, &args->in); + if (IS_ERR(fence)) { + r = PTR_ERR(fence); + return r; + } + r = amdgpu_sem_signal(fpriv, args->in.handle, fence); + dma_fence_put(fence); + break; + case AMDGPU_SEM_OP_IMPORT_SEM: + r = amdgpu_sem_import(fpriv, args->in.handle, &args->out.handle); + break; + case AMDGPU_SEM_OP_EXPORT_SEM: + r = amdgpu_sem_export(fpriv, args->in.handle, &args->out.fd); + break; + case AMDGPU_SEM_OP_DESTROY_SEM: + amdgpu_sem_destroy(fpriv, args->in.handle); + break; + default: + r = -EINVAL; + break; + } + + return r; +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.h new file mode 100644 index 0000000000000..dbbb9d4540233 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sem.h @@ -0,0 +1,64 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: Chunming Zhou + * + */ + + +#ifndef _LINUX_AMDGPU_SEM_H +#define _LINUX_AMDGPU_SEM_H + +#include +#include +#include +#include +#include + +struct amdgpu_sem_core { + struct file *file; + struct kref kref; + struct dma_fence *fence; + struct mutex lock; +}; + +struct amdgpu_sem_dep { + struct dma_fence *fence; + struct list_head list; +}; + +struct amdgpu_sem { + struct amdgpu_sem_core *base; + struct kref kref; + struct list_head list; +}; + +void amdgpu_sem_put(struct amdgpu_sem *sem); + +int amdgpu_sem_ioctl(struct drm_device *dev, void *data, + struct drm_file *filp); + +int amdgpu_sem_add_cs(struct amdgpu_ctx *ctx, struct drm_sched_entity *entity, + struct amdgpu_sync *sync); + +void amdgpu_sem_destroy(struct amdgpu_fpriv *fpriv, u32 handle); + +#endif /* _LINUX_AMDGPU_SEM_H */ diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index 8e16c5bfb0ed6..e08f5d4f8095c 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -55,6 +55,9 @@ extern "C" { #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14 #define DRM_AMDGPU_SCHED 0x15 +/* hybrid specific ioctls */ +#define DRM_AMDGPU_SEM 0x5b + #define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create) #define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap) #define DRM_IOCTL_AMDGPU_CTX DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_CTX, union drm_amdgpu_ctx) @@ -98,6 +101,9 @@ extern "C" { * %AMDGPU_GEM_DOMAIN_DOORBELL Doorbell. It is an MMIO region for * signalling user mode queues. */ +/* hybrid specific ioctls */ +#define DRM_IOCTL_AMDGPU_SEM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_SEM, union drm_amdgpu_sem) + #define AMDGPU_GEM_DOMAIN_CPU 0x1 #define AMDGPU_GEM_DOMAIN_GTT 0x2 #define AMDGPU_GEM_DOMAIN_VRAM 0x4 @@ -175,6 +181,8 @@ extern "C" { #define AMDGPU_GEM_CREATE_GFX12_DCC (1 << 16) /* hybrid specific */ +/* Flag that the memory should be in SPARSE resource */ +#define AMDGPU_GEM_CREATE_SPARSE (1ULL << 29) /* Flag that the memory allocation should be from top of domain */ #define AMDGPU_GEM_CREATE_TOP_DOWN (1ULL << 30) /* Flag that the memory allocation should be pinned */ @@ -325,6 +333,35 @@ union drm_amdgpu_ctx { union drm_amdgpu_ctx_out out; }; +/* sem related */ +#define AMDGPU_SEM_OP_CREATE_SEM 1 +#define AMDGPU_SEM_OP_WAIT_SEM 2 +#define AMDGPU_SEM_OP_SIGNAL_SEM 3 +#define AMDGPU_SEM_OP_DESTROY_SEM 4 +#define AMDGPU_SEM_OP_IMPORT_SEM 5 +#define AMDGPU_SEM_OP_EXPORT_SEM 6 + +struct drm_amdgpu_sem_in { + /** AMDGPU_SEM_OP_* */ + uint32_t op; + uint32_t handle; + uint32_t ctx_id; + uint32_t ip_type; + uint32_t ip_instance; + uint32_t ring; + uint64_t seq; +}; + +union drm_amdgpu_sem_out { + int32_t fd; + uint32_t handle; +}; + +union drm_amdgpu_sem { + struct drm_amdgpu_sem_in in; + union drm_amdgpu_sem_out out; +}; + /* vm ioctl */ #define AMDGPU_VM_OP_RESERVE_VMID 1 #define AMDGPU_VM_OP_UNRESERVE_VMID 2 From 4abfe7641e2847e04680c180da20c72588a252cf Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 21 Aug 2018 17:35:56 +0800 Subject: [PATCH 0183/1868] drm/amdgpu: [hybrid] add direct gma(dgma) support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit v2: rebase on linux 4.18 and cleanup v3: 3f8d459ca0f1("drm/amdgpu: [hybrid] fix DGMA buffer info loss issue (v2)") v4: 814cd038a6b5(drm/amdkcl: modify DGMA setting for new PL_DOORBELL support) Signed-off-by: Bob Zhou Reviewed-by: Flora Cui Reviewed-by: Guchun Chen Signed-off-by: Flora Cui Reviewed-by: Hawking Zhang Signed-off-by: Junwei Zhang (v2) Signed-off-by: Shiwu Zhang Reviewed-by: Flora Cui Signed-off-by: Tianci.Yin Acked-by: Christian König Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 15 + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 6 + drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 86 ++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 28 +- drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 9 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 325 ++++++++++++++++++++- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 10 + drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 3 + include/drm/ttm/ttm_resource.h | 2 +- include/uapi/drm/amdgpu_drm.h | 24 +- 11 files changed, 503 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index b7e6a9acc8d8a..4a9ce5c5eeba2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -191,6 +191,7 @@ extern int amdgpu_dc; extern int amdgpu_sched_jobs; extern int amdgpu_sched_hw_submission; extern int amdgpu_no_evict; +extern int amdgpu_direct_gma_size; extern uint amdgpu_pcie_gen_cap; extern uint amdgpu_pcie_lane_cap; extern u64 amdgpu_cg_mask; @@ -658,6 +659,9 @@ int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *fi int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); +int amdgpu_gem_dgma_ioctl(struct drm_device *dev, void *data, + struct drm_file *filp); + /* VRAM scratch page for HDP bug, default vram page */ struct amdgpu_mem_scratch { struct amdgpu_bo *robj; @@ -748,6 +752,14 @@ enum amd_hw_ip_block_type { #define IP_VERSION_SUBREV(ver) ((ver) & 0xF) #define IP_VERSION_MAJ_MIN_REV(ver) ((ver) >> 8) +struct amdgpu_direct_gma { + /* reserved in visible vram*/ + struct amdgpu_bo *dgma_bo; + atomic64_t vram_usage; + /* reserved in gart */ + atomic64_t gart_usage; +}; + struct amdgpu_ip_map_info { /* Map of logical to actual dev instances/mask */ uint32_t dev_inst[MAX_HWIP][HWIP_MAX_INSTANCE]; @@ -876,6 +888,9 @@ struct amdgpu_device { uint32_t bios_scratch_reg_offset; uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH]; + /* Direct GMA */ + struct amdgpu_direct_gma direct_gma; + /* Register/doorbell mmio */ resource_size_t rmmio_base; resource_size_t rmmio_size; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index bf2d266c2f21c..49d7e0807e3a4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -1970,6 +1970,7 @@ static int amdgpu_device_check_arguments(struct amdgpu_device *adev) amdgpu_device_check_block_size(adev); adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type); + amdgpu_direct_gma_size = min(amdgpu_direct_gma_size, 96); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 045598f0f94da..4f421fb94c616 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -163,6 +163,7 @@ int amdgpu_dc = -1; int amdgpu_sched_jobs = 32; int amdgpu_sched_hw_submission = 2; int amdgpu_no_evict; +int amdgpu_direct_gma_size; uint amdgpu_pcie_gen_cap; uint amdgpu_pcie_lane_cap; u64 amdgpu_cg_mask = 0xffffffffffffffff; @@ -478,6 +479,10 @@ module_param_named(ppfeaturemask, amdgpu_pp_feature_mask, hexint, 0444); MODULE_PARM_DESC(no_evict, "Support pinning request from user space (1 = enable, 0 = disable (default))"); module_param_named(no_evict, amdgpu_no_evict, int, 0444); + +MODULE_PARM_DESC(direct_gma_size, "Direct GMA size in megabytes (max 96MB)"); +module_param_named(direct_gma_size, amdgpu_direct_gma_size, int, 0444); + /** * DOC: forcelongtraining (uint) * Force long memory training in resume. @@ -2953,6 +2958,7 @@ const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { DRM_IOCTL_DEF_DRV(AMDGPU_GEM_VA, amdgpu_gem_va_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(AMDGPU_GEM_DGMA, amdgpu_gem_dgma_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(AMDGPU_SEM, amdgpu_sem_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW) }; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index 4253e98b56f30..5996bd0bddc79 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -88,6 +88,7 @@ static const struct vm_operations_struct amdgpu_gem_vm_ops = { static void amdgpu_gem_object_free(struct drm_gem_object *gobj) { struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj); + struct amdgpu_device *adev = amdgpu_ttm_adev(robj->tbo.bdev); if (robj) { if (robj->flags & AMDGPU_GEM_CREATE_NO_EVICT) { @@ -97,6 +98,13 @@ static void amdgpu_gem_object_free(struct drm_gem_object *gobj) } } + if (robj->tbo.resource->mem_type == AMDGPU_PL_DGMA) + atomic64_sub(amdgpu_bo_size(robj), + &adev->direct_gma.vram_usage); + else if (robj->tbo.resource->mem_type == AMDGPU_PL_DGMA_IMPORT) + atomic64_sub(amdgpu_bo_size(robj), + &adev->direct_gma.gart_usage); + amdgpu_hmm_unregister(robj); amdgpu_bo_unref(&robj); } @@ -111,12 +119,30 @@ int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, struct amdgpu_bo *bo; struct amdgpu_bo_user *ubo; struct amdgpu_bo_param bp; + unsigned long max_size; int r; memset(&bp, 0, sizeof(bp)); *obj = NULL; flags |= AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE; + if ((initial_domain & AMDGPU_GEM_DOMAIN_DGMA) || + (initial_domain & AMDGPU_GEM_DOMAIN_DGMA_IMPORT)) { + flags |= AMDGPU_GEM_CREATE_NO_EVICT; + max_size = (unsigned long)amdgpu_direct_gma_size << 20; + + if (initial_domain & AMDGPU_GEM_DOMAIN_DGMA) + max_size -= atomic64_read(&adev->direct_gma.vram_usage); + else if (initial_domain & AMDGPU_GEM_DOMAIN_DGMA_IMPORT) + max_size -= atomic64_read(&adev->direct_gma.gart_usage); + + if (size > max_size) { + DRM_DEBUG("Allocation size %ldMb bigger than %ldMb limit\n", + size >> 20, max_size >> 20); + return -ENOMEM; + } + } + bp.size = size; bp.byte_align = alignment; bp.type = type; @@ -135,6 +161,11 @@ int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, *obj = &bo->tbo.base; (*obj)->funcs = &amdgpu_gem_object_funcs; + if (initial_domain & AMDGPU_GEM_DOMAIN_DGMA) + atomic64_add(size, &adev->direct_gma.vram_usage); + else if (initial_domain & AMDGPU_GEM_DOMAIN_DGMA_IMPORT) + atomic64_add(size, &adev->direct_gma.gart_usage); + return 0; } @@ -499,6 +530,61 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, return r; } +int amdgpu_gem_dgma_ioctl(struct drm_device *dev, void *data, + struct drm_file *filp) +{ + struct amdgpu_device *adev = drm_to_adev(dev); + struct drm_amdgpu_gem_dgma *args = data; + struct drm_gem_object *gobj; + struct amdgpu_bo *abo; + dma_addr_t *dma_addr; + uint32_t handle; + int i, r = 0; + + switch (args->op) { + case AMDGPU_GEM_DGMA_IMPORT: + /* create a gem object to contain this object in */ + r = amdgpu_gem_object_create(adev, args->size, 0, + AMDGPU_GEM_DOMAIN_DGMA_IMPORT, 0, + 0, NULL, &gobj); + if (r) + return r; + + abo = gem_to_amdgpu_bo(gobj); + dma_addr = kmalloc_array(abo->tbo.resource->num_pages, sizeof(dma_addr_t), GFP_KERNEL); + if (unlikely(dma_addr == NULL)) + goto release_object; + + for (i = 0; i < abo->tbo.resource->num_pages; i++) + dma_addr[i] = args->addr + i * PAGE_SIZE; + abo->dgma_import_base = args->addr; + abo->dgma_addr = (void *)dma_addr; + r = drm_gem_handle_create(filp, gobj, &handle); + args->handle = handle; + break; + case AMDGPU_GEM_DGMA_QUERY_PHYS_ADDR: + gobj = drm_gem_object_lookup(filp, args->handle); + if (gobj == NULL) + return -ENOENT; + + abo = gem_to_amdgpu_bo(gobj); + if (abo->tbo.resource->mem_type != AMDGPU_PL_DGMA) { + r = -EINVAL; + goto release_object; + } + args->addr = amdgpu_bo_gpu_offset(abo) - + amdgpu_ttm_domain_start(adev, TTM_PL_VRAM) + + adev->gmc.aper_base; + break; + default: + return -EINVAL; + } + +release_object: + drm_gem_object_put(gobj); + return r; +} + int amdgpu_mode_dumb_mmap(struct drm_file *filp, struct drm_device *dev, uint32_t handle, uint64_t *offset_p) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index 1b69be22a6143..b39cc2dc47888 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -58,6 +58,8 @@ static void amdgpu_bo_destroy(struct ttm_buffer_object *tbo) { struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo); + kfree(bo->dgma_addr); + amdgpu_bo_kunmap(bo); if (bo->tbo.base.import_attach) @@ -131,6 +133,22 @@ void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain) u64 flags = abo->flags; u32 c = 0, i; + if ((domain & AMDGPU_GEM_DOMAIN_DGMA) && amdgpu_direct_gma_size) { + places[c].fpfn = 0; + places[c].lpfn = 0; + places[c].mem_type = AMDGPU_PL_DGMA; + places[c].flags = 0; + c++; + } + + if ((domain & AMDGPU_GEM_DOMAIN_DGMA_IMPORT) && amdgpu_direct_gma_size) { + places[c].fpfn = 0; + places[c].lpfn = 0; + places[c].mem_type = AMDGPU_PL_DGMA_IMPORT; + places[c].flags = 0; + c++; + } + if (domain & AMDGPU_GEM_DOMAIN_VRAM) { unsigned int visible_pfn = adev->gmc.visible_vram_size >> PAGE_SHIFT; int8_t mem_id = KFD_XCP_MEM_ID(adev, abo->xcp_id); @@ -656,7 +674,8 @@ int amdgpu_bo_create(struct amdgpu_device *adev, if (bp->type == ttm_bo_type_device) bo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; - if ((bp->flags & AMDGPU_GEM_CREATE_NO_EVICT) && amdgpu_no_evict) { + if (((bp->flags & AMDGPU_GEM_CREATE_NO_EVICT) && amdgpu_no_evict) || + bp->domain & (AMDGPU_GEM_DOMAIN_DGMA | AMDGPU_GEM_DOMAIN_DGMA_IMPORT)) { r = amdgpu_bo_reserve(bo, false); if (unlikely(r != 0)) return r; @@ -1538,6 +1557,7 @@ u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo) WARN_ON_ONCE(bo->tbo.resource->start == AMDGPU_BO_INVALID_OFFSET); WARN_ON_ONCE(bo->tbo.resource->mem_type == TTM_PL_VRAM && !(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)); + WARN_ON_ONCE(bo->tbo.resource->mem_type == AMDGPU_PL_DGMA_IMPORT); return amdgpu_bo_gpu_offset_no_check(bo); } @@ -1624,6 +1644,12 @@ u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo, struct seq_file *m) else placement = "VRAM"; break; + case AMDGPU_PL_DGMA: + placement = "DGMA"; + break; + case AMDGPU_PL_DGMA_IMPORT: + placement = "DGMA_IMPORT"; + break; case TTM_PL_TT: placement = "GTT"; break; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h index d7e27957013f3..cd327b9c1cca7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h @@ -117,6 +117,10 @@ struct amdgpu_bo { #endif struct kgd_mem *kfd_bo; + /* DGMA imported buffer info */ + void *dgma_addr; + phys_addr_t dgma_import_base; + /* * For GPUs with spatial partitioning, xcp partition number, -1 means * any partition. For other ASICs without spatial partition, always 0 @@ -131,7 +135,6 @@ struct amdgpu_bo_user { u64 metadata_flags; void *metadata; u32 metadata_size; - }; struct amdgpu_bo_vm { @@ -196,6 +199,10 @@ static inline unsigned amdgpu_mem_type_to_domain(u32 mem_type) return AMDGPU_GEM_DOMAIN_OA; case AMDGPU_PL_DOORBELL: return AMDGPU_GEM_DOMAIN_DOORBELL; + case AMDGPU_PL_DGMA: + return AMDGPU_GEM_DOMAIN_DGMA; + case AMDGPU_PL_DGMA_IMPORT: + return AMDGPU_GEM_DOMAIN_DGMA_IMPORT; default: break; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index c229d58918a33..eb4e4272179ff 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -65,6 +65,11 @@ MODULE_IMPORT_NS(DMA_BUF); #define AMDGPU_TTM_VRAM_MAX_DW_READ ((size_t)128) +struct amdgpu_dgma_node { + struct ttm_buffer_object *tbo; + struct ttm_range_mgr_node base; +}; + static int amdgpu_ttm_backend_bind(struct ttm_device *bdev, struct ttm_tt *ttm, struct ttm_resource *bo_mem); @@ -127,6 +132,7 @@ static void amdgpu_evict_flags(struct ttm_buffer_object *bo, return; case TTM_PL_VRAM: + case AMDGPU_PL_DGMA: if (!adev->mman.buffer_funcs_enabled) { /* Move to system memory */ amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU); @@ -153,6 +159,7 @@ static void amdgpu_evict_flags(struct ttm_buffer_object *bo, } break; case TTM_PL_TT: + case AMDGPU_PL_DGMA_IMPORT: case AMDGPU_PL_PREEMPT: default: amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_CPU); @@ -500,6 +507,11 @@ static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict, } abo = ttm_to_amdgpu_bo(bo); + + if (old_mem->mem_type == AMDGPU_GEM_DOMAIN_DGMA || + old_mem->mem_type == AMDGPU_GEM_DOMAIN_DGMA_IMPORT) + return -EINVAL; + adev = amdgpu_ttm_adev(bo->bdev); if (!old_mem || (old_mem->mem_type == TTM_PL_SYSTEM && @@ -608,7 +620,10 @@ static int amdgpu_ttm_io_mem_reserve(struct ttm_device *bdev, case AMDGPU_PL_PREEMPT: break; case TTM_PL_VRAM: - mem->bus.offset = mem->start << PAGE_SHIFT; + case AMDGPU_PL_DGMA: + mem->bus.offset = (mem->start << PAGE_SHIFT) + + amdgpu_ttm_domain_start(adev, mem->mem_type) - + amdgpu_ttm_domain_start(adev, TTM_PL_VRAM); if (adev->mman.aper_base_kaddr && mem->placement & TTM_PL_FLAG_CONTIGUOUS) @@ -624,6 +639,19 @@ static int amdgpu_ttm_io_mem_reserve(struct ttm_device *bdev, mem->bus.is_iomem = true; mem->bus.caching = ttm_uncached; break; + case AMDGPU_PL_DGMA_IMPORT: + { + struct amdgpu_dgma_node *node; + struct amdgpu_bo *abo; + + node = container_of(mem, struct amdgpu_dgma_node, base.base); + abo = ttm_to_amdgpu_bo(node->tbo); + mem->bus.addr = abo->dgma_addr; + mem->bus.offset = abo->dgma_import_base; + mem->bus.is_iomem = true; + mem->bus.caching = ttm_write_combined; + break; + } default: return -EINVAL; } @@ -636,6 +664,10 @@ static unsigned long amdgpu_ttm_io_mem_pfn(struct ttm_buffer_object *bo, struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev); struct amdgpu_res_cursor cursor; + if (bo->resource->mem_type == AMDGPU_PL_DGMA || + bo->resource->mem_type == AMDGPU_PL_DGMA_IMPORT) + return (bo->resource->bus.offset >> PAGE_SHIFT) + page_offset; + amdgpu_res_first(bo->resource, (u64)page_offset << PAGE_SHIFT, 0, &cursor); @@ -661,6 +693,12 @@ uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type) return adev->gmc.gart_start; case TTM_PL_VRAM: return adev->gmc.vram_start; + case AMDGPU_PL_DGMA: + if (adev->direct_gma.dgma_bo) + return amdgpu_bo_gpu_offset(adev->direct_gma.dgma_bo); + fallthrough; + case AMDGPU_PL_DGMA_IMPORT: + return 0; } return 0; @@ -1376,6 +1414,9 @@ uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, { uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem); + if (mem && mem->mem_type == AMDGPU_PL_DGMA_IMPORT) + flags |= AMDGPU_PTE_SYSTEM; + flags |= adev->gart.gart_pte_flags; flags |= AMDGPU_PTE_READABLE; @@ -1798,6 +1839,252 @@ static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev) return 0; } +static inline struct amdgpu_dgma_import_mgr *to_dgma_import_mgr(struct ttm_resource_manager *man) +{ + return container_of(man, struct amdgpu_dgma_import_mgr, manager); +} + +static const struct ttm_resource_manager_func amdgpu_dgma_import_mgr_func; +/** + * amdgpu_dgma_import_mgr_init - init DGMA_import manager and DRM MM + * + * @adev: amdgpu_device pointer + * @dgma_size: maximum size of DGMA + * + * Allocate and initialize the DGMA manager. + */ +static int amdgpu_dgma_import_mgr_init(struct amdgpu_device *adev, uint64_t p_size) +{ + struct amdgpu_dgma_import_mgr *mgr = &adev->mman.dgma_import_mgr; + struct ttm_resource_manager *man = &mgr->manager; + + man->func = &amdgpu_dgma_import_mgr_func; + + ttm_resource_manager_init(man, &adev->mman.bdev, p_size); + drm_mm_init(&mgr->mm, 0, p_size); + spin_lock_init(&mgr->lock); + atomic64_set(&mgr->available, p_size); + + ttm_set_driver_manager(&adev->mman.bdev, AMDGPU_PL_DGMA_IMPORT, man); + ttm_resource_manager_set_used(man, true); + return 0; +} + +/** + * amdgpu_dgma_import_mgr_fini - free and destroy DGMA import manager + * + * @adev: amdgpu_device pointer + * + * Destroy and free the DGMA import manager, returns -EBUSY if ranges are still + * allocated inside it. + */ +static void amdgpu_dgma_import_mgr_fini(struct amdgpu_device *adev) +{ + struct amdgpu_dgma_import_mgr *mgr = &adev->mman.dgma_import_mgr; + struct ttm_resource_manager *man = &mgr->manager; + int ret; + + ttm_resource_manager_set_used(man, false); + + ret = ttm_resource_manager_evict_all(&adev->mman.bdev, man); + if (ret) + return; + + spin_lock(&mgr->lock); + drm_mm_takedown(&mgr->mm); + spin_unlock(&mgr->lock); + ttm_resource_manager_cleanup(man); + ttm_set_driver_manager(&adev->mman.bdev, TTM_PL_TT, NULL); +} + +/** + * amdgpu_dgma_import_mgr_new - allocate a new node + * + * @man: TTM memory type manager + * @tbo: TTM BO we need this range for + * @place: placement flags and restrictions + * @mem: the resulting mem object + */ +static int amdgpu_dgma_import_mgr_new(struct ttm_resource_manager *man, + struct ttm_buffer_object *tbo, + const struct ttm_place *place, + struct ttm_resource **res) +{ + struct amdgpu_dgma_import_mgr *mgr = to_dgma_import_mgr(man); + uint32_t num_pages = PFN_UP(tbo->base.size); + struct amdgpu_dgma_node *node; + unsigned long lpfn; + int r; + + spin_lock(&mgr->lock); + if (atomic64_read(&mgr->available) < num_pages) { + spin_unlock(&mgr->lock); + return -ENOSPC; + } + atomic64_sub(num_pages, &mgr->available); + spin_unlock(&mgr->lock); + + lpfn = place->lpfn; + if (!lpfn) + lpfn = man->size; + + node = kzalloc(struct_size(node, base.mm_nodes, 1), GFP_KERNEL); + if (!node) { + r = -ENOMEM; + goto err_out; + } + + node->tbo = tbo; + ttm_resource_init(tbo, place, &node->base.base); + + spin_lock(&mgr->lock); + r = drm_mm_insert_node_in_range(&mgr->mm, &node->base.mm_nodes[0], num_pages, + tbo->page_alignment, 0, place->fpfn, + lpfn, DRM_MM_INSERT_BEST); + spin_unlock(&mgr->lock); + + if (unlikely(r)) + goto err_free; + + *res = &node->base.base; + (*res)->start = node->base.mm_nodes[0].start; + + return 0; + +err_free: + kfree(node); + +err_out: + atomic64_add(num_pages, &mgr->available); + + return r; +} + +/** + * amdgpu_dgma_import_mgr_del - free ranges + * + * @man: TTM memory type manager + * @mem: TTM memory object + * + * Free the allocated node. + */ +static void amdgpu_dgma_import_mgr_del(struct ttm_resource_manager *man, + struct ttm_resource *mem) +{ + struct amdgpu_dgma_import_mgr *mgr = to_dgma_import_mgr(man); + struct amdgpu_dgma_node *node = container_of(mem, struct amdgpu_dgma_node, base.base); + + if (node) { + spin_lock(&mgr->lock); + drm_mm_remove_node(&node->base.mm_nodes[0]); + spin_unlock(&mgr->lock); + kfree(node); + } + + atomic64_add(mem->num_pages, &mgr->available); +} + +static void amdgpu_dgma_import_mgr_debug(struct ttm_resource_manager *man, + struct drm_printer *printer) +{ + struct amdgpu_dgma_import_mgr *rman = to_dgma_import_mgr(man); + + spin_lock(&rman->lock); + drm_mm_print(&rman->mm, printer); + spin_unlock(&rman->lock); +} + +static const struct ttm_resource_manager_func amdgpu_dgma_import_mgr_func = { + .alloc = amdgpu_dgma_import_mgr_new, + .free = amdgpu_dgma_import_mgr_del, + .debug = amdgpu_dgma_import_mgr_debug +}; + +static int amdgpu_direct_gma_init(struct amdgpu_device *adev) +{ + struct amdgpu_bo *abo; + struct amdgpu_bo_param bp; + unsigned long size; + int r; + + if (amdgpu_direct_gma_size == 0) + return 0; + + size = (unsigned long)amdgpu_direct_gma_size << 20; + + memset(&bp, 0, sizeof(bp)); + bp.size = size; + bp.byte_align = PAGE_SIZE; + bp.domain = AMDGPU_GEM_DOMAIN_VRAM; + bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | + AMDGPU_GEM_CREATE_TOP_DOWN; + bp.type = ttm_bo_type_kernel; + bp.resv = NULL; + + /* reserve in visible vram */ + r = amdgpu_bo_create(adev, &bp, &abo); + if (unlikely(r)) + goto error_out; + + r = amdgpu_bo_reserve(abo, false); + if (unlikely(r)) + goto error_free; + + r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM); + amdgpu_bo_unreserve(abo); + if (unlikely(r)) + goto error_free; + + adev->direct_gma.dgma_bo = abo; + + /* reserve in gtt */ + atomic64_add(size, &adev->gart_pin_size); + r = ttm_range_man_init(&adev->mman.bdev, AMDGPU_PL_DGMA, + false, size >> PAGE_SHIFT); + if (unlikely(r)) + goto error_put_node; + + r = amdgpu_dgma_import_mgr_init(adev, size >> PAGE_SHIFT); + if (unlikely(r)) + goto error_release_mm; + + DRM_INFO("%dMB VRAM/GTT reserved for Direct GMA\n", amdgpu_direct_gma_size); + return 0; + +error_release_mm: + ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_DGMA); + +error_put_node: + atomic64_sub(size, &adev->gart_pin_size); +error_free: + amdgpu_bo_unref(&abo); + +error_out: + amdgpu_direct_gma_size = 0; + memset(&adev->direct_gma, 0, sizeof(adev->direct_gma)); + DRM_ERROR("Fail to enable Direct GMA\n"); + return r; +} + +static void amdgpu_direct_gma_fini(struct amdgpu_device *adev) +{ + int r; + + if (amdgpu_direct_gma_size == 0) + return; + + ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_DGMA); + amdgpu_dgma_import_mgr_fini(adev); + + r = amdgpu_bo_reserve(adev->direct_gma.dgma_bo, false); + if (r == 0) { + amdgpu_bo_unpin(adev->direct_gma.dgma_bo); + amdgpu_bo_unreserve(adev->direct_gma.dgma_bo); + } + amdgpu_bo_unref(&adev->direct_gma.dgma_bo); + atomic64_sub((u64)amdgpu_direct_gma_size << 20, &adev->gart_pin_size); +} + static int amdgpu_ttm_pools_init(struct amdgpu_device *adev) { int i; @@ -1960,6 +2247,8 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) gtt_size = ttm_tt_pages_limit() << PAGE_SHIFT; else gtt_size = (uint64_t)amdgpu_gtt_size << 20; + /* reserve for DGMA import domain */ + gtt_size -= (uint64_t)amdgpu_direct_gma_size << 20; /* Initialize GTT memory pool */ r = amdgpu_gtt_mgr_init(adev, gtt_size); @@ -1970,6 +2259,7 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) DRM_INFO("amdgpu: %uM of GTT memory ready.\n", (unsigned int)(gtt_size / (1024 * 1024))); + amdgpu_direct_gma_init(adev); /* Initiailize doorbell pool on PCI BAR */ r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_DOORBELL, adev->doorbell.size / PAGE_SIZE); if (r) { @@ -2056,6 +2346,7 @@ void amdgpu_ttm_fini(struct amdgpu_device *adev) drm_dev_exit(idx); } + amdgpu_direct_gma_fini(adev); amdgpu_vram_mgr_fini(adev); amdgpu_gtt_mgr_fini(adev); amdgpu_preempt_mgr_fini(adev); @@ -2407,7 +2698,32 @@ static int amdgpu_ttm_page_pool_show(struct seq_file *m, void *unused) return ttm_pool_debugfs(&adev->mman.bdev.pool, m); } +static int amdgpu_mm_dgma_table_show(struct seq_file *m, void *unused) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)m->private; + struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, + AMDGPU_PL_DGMA); + struct drm_printer p = drm_seq_file_printer(m); + + man->func->debug(man, &p); + return 0; +} + +static int amdgpu_mm_dgma_import_table_show(struct seq_file *m, void *unused) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)m->private; + struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, + AMDGPU_PL_DGMA_IMPORT); + struct drm_printer p = drm_seq_file_printer(m); + + man->func->debug(man, &p); + return 0; +} + DEFINE_SHOW_ATTRIBUTE(amdgpu_ttm_page_pool); +DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_dgma_table); +DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_dgma_import_table); + /* * amdgpu_ttm_vram_read - Linear read access to VRAM @@ -2618,6 +2934,7 @@ void amdgpu_ttm_debugfs_init(struct amdgpu_device *adev) &amdgpu_ttm_iomem_fops); debugfs_create_file("ttm_page_pool", 0444, root, adev, &amdgpu_ttm_page_pool_fops); + ttm_resource_manager_create_debugfs(ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM), root, "amdgpu_vram_mm"); @@ -2634,5 +2951,11 @@ void amdgpu_ttm_debugfs_init(struct amdgpu_device *adev) AMDGPU_PL_OA), root, "amdgpu_oa_mm"); + if (amdgpu_direct_gma_size) { + debugfs_create_file("amdgpu_dgma_mm", 0444, root, adev, + &amdgpu_mm_dgma_table_fops); + debugfs_create_file("amdgpu_dgma_import_mm", 0444, root, adev, + &amdgpu_mm_dgma_import_table_fops); + } #endif } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h index 138d80017f356..a3477ae7996b6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -34,6 +34,8 @@ #define AMDGPU_PL_OA (TTM_PL_PRIV + 2) #define AMDGPU_PL_PREEMPT (TTM_PL_PRIV + 3) #define AMDGPU_PL_DOORBELL (TTM_PL_PRIV + 4) +#define AMDGPU_PL_DGMA (TTM_PL_PRIV + 7) +#define AMDGPU_PL_DGMA_IMPORT (TTM_PL_PRIV + 8) #define AMDGPU_GTT_MAX_TRANSFER_SIZE 512 #define AMDGPU_GTT_NUM_TRANSFER_WINDOWS 2 @@ -49,6 +51,13 @@ struct amdgpu_gtt_mgr { spinlock_t lock; }; +struct amdgpu_dgma_import_mgr { + struct ttm_resource_manager manager; + struct drm_mm mm; + spinlock_t lock; + atomic64_t available; +}; + struct amdgpu_mman { struct ttm_device bdev; struct ttm_pool *ttm_pools; @@ -68,6 +77,7 @@ struct amdgpu_mman { struct amdgpu_vram_mgr vram_mgr; struct amdgpu_gtt_mgr gtt_mgr; + struct amdgpu_dgma_import_mgr dgma_import_mgr; struct ttm_resource_manager preempt_mgr; uint64_t stolen_vga_size; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 083e4ffa15794..fe069be8136d0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -1023,6 +1023,7 @@ int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm, uint64_t tmp, num_entries, addr; num_entries = cursor.size >> AMDGPU_GPU_PAGE_SHIFT; + if (pages_addr) { bool contiguous = true; @@ -1185,6 +1186,8 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va, if (mem && (mem->mem_type == TTM_PL_TT || mem->mem_type == AMDGPU_PL_PREEMPT)) pages_addr = bo->tbo.ttm->dma_address; + else if (mem->mem_type == AMDGPU_PL_DGMA_IMPORT) + pages_addr = (dma_addr_t *)bo->tbo.mem.bus.addr; } if (bo) { diff --git a/include/drm/ttm/ttm_resource.h b/include/drm/ttm/ttm_resource.h index 69769355139f2..e909fc0cba01c 100644 --- a/include/drm/ttm/ttm_resource.h +++ b/include/drm/ttm/ttm_resource.h @@ -36,7 +36,7 @@ #include #define TTM_MAX_BO_PRIORITY 4U -#define TTM_NUM_MEM_TYPES 8 +#define TTM_NUM_MEM_TYPES 12 struct ttm_device; struct ttm_resource_manager; diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index e08f5d4f8095c..d1f7ba9b31300 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -54,6 +54,8 @@ extern "C" { #define DRM_AMDGPU_VM 0x13 #define DRM_AMDGPU_FENCE_TO_HANDLE 0x14 #define DRM_AMDGPU_SCHED 0x15 +/* not upstream */ +#define DRM_AMDGPU_GEM_DGMA 0x5c /* hybrid specific ioctls */ #define DRM_AMDGPU_SEM 0x5b @@ -75,6 +77,8 @@ extern "C" { #define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle) #define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched) +#define DRM_IOCTL_AMDGPU_GEM_DGMA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_DGMA, struct drm_amdgpu_gem_dgma) + /** * DOC: memory domains * @@ -111,13 +115,17 @@ extern "C" { #define AMDGPU_GEM_DOMAIN_GWS 0x10 #define AMDGPU_GEM_DOMAIN_OA 0x20 #define AMDGPU_GEM_DOMAIN_DOORBELL 0x40 +#define AMDGPU_GEM_DOMAIN_DGMA 0x400 +#define AMDGPU_GEM_DOMAIN_DGMA_IMPORT 0x800 #define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \ AMDGPU_GEM_DOMAIN_GTT | \ AMDGPU_GEM_DOMAIN_VRAM | \ AMDGPU_GEM_DOMAIN_GDS | \ AMDGPU_GEM_DOMAIN_GWS | \ - AMDGPU_GEM_DOMAIN_OA | \ - AMDGPU_GEM_DOMAIN_DOORBELL) + AMDGPU_GEM_DOMAIN_OA |\ + AMDGPU_GEM_DOMAIN_DOORBELL |\ + AMDGPU_GEM_DOMAIN_DGMA |\ + AMDGPU_GEM_DOMAIN_DGMA_IMPORT) /* Flag that CPU access will be required for the case of VRAM domain */ #define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0) @@ -418,6 +426,15 @@ struct drm_amdgpu_gem_userptr { __u32 handle; }; +#define AMDGPU_GEM_DGMA_IMPORT 0 +#define AMDGPU_GEM_DGMA_QUERY_PHYS_ADDR 1 +struct drm_amdgpu_gem_dgma { + __u64 addr; + __u64 size; + __u32 op; + __u32 handle; +}; + /* SI-CI-VI: */ /* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */ #define AMDGPU_TILING_ARRAY_MODE_SHIFT 0 @@ -984,6 +1001,8 @@ struct drm_amdgpu_cs_chunk_cp_gfx_shadow { #define AMDGPU_INFO_VIRTUAL_RANGE 0x51 /* query pin memory capability */ #define AMDGPU_CAPABILITY_PIN_MEM_FLAG (1 << 0) +/* query direct gma capability */ +#define AMDGPU_CAPABILITY_DIRECT_GMA_FLAG (1 << 1) #define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0 #define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff @@ -1370,6 +1389,7 @@ struct drm_amdgpu_virtual_range { struct drm_amdgpu_capability { __u32 flag; + __u32 direct_gma_size; }; /* From 2b91806aaf931330ed4402d24f9ec7cbb257e8ee Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 16 Apr 2021 11:17:58 +0800 Subject: [PATCH 0184/1868] drm/amdgpu: [hybrid] fix bo_ptr_size for dgma Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index eb4e4272179ff..57a184ed1dbc0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -2020,6 +2020,7 @@ static int amdgpu_direct_gma_init(struct amdgpu_device *adev) AMDGPU_GEM_CREATE_TOP_DOWN; bp.type = ttm_bo_type_kernel; bp.resv = NULL; + bp.bo_ptr_size = sizeof(struct amdgpu_bo); /* reserve in visible vram */ r = amdgpu_bo_create(adev, &bp, &abo); From 1ec1e8f15438c86d68889c665be439224a6e4b98 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 16 Apr 2021 15:51:05 +0800 Subject: [PATCH 0185/1868] drm/amdgpu: [hybrid] fix gpu mapping for dgma Signed-off-by: Flora Cui Signed-off-by: xinhui pan Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index fe069be8136d0..20ed60d32c6b2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -1187,7 +1187,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va, mem->mem_type == AMDGPU_PL_PREEMPT)) pages_addr = bo->tbo.ttm->dma_address; else if (mem->mem_type == AMDGPU_PL_DGMA_IMPORT) - pages_addr = (dma_addr_t *)bo->tbo.mem.bus.addr; + pages_addr = (dma_addr_t *)bo->dgma_addr; } if (bo) { From d94aca602717c3c837cc1a579c89b00bdb8cc49e Mon Sep 17 00:00:00 2001 From: Guchun Chen Date: Fri, 17 Sep 2021 11:43:13 +0800 Subject: [PATCH 0186/1868] drm/amdgpu: [hybrid]enable dGMA path in page table mapping Signed-off-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 69 +++++++++++++++----------- 1 file changed, 41 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 20ed60d32c6b2..fd14cd652cb3a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -1024,45 +1024,58 @@ int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm, num_entries = cursor.size >> AMDGPU_GPU_PAGE_SHIFT; - if (pages_addr) { - bool contiguous = true; + if (res && (res->mem_type == AMDGPU_PL_DGMA_IMPORT || + res->mem_type == AMDGPU_PL_DGMA)) { + uint64_t pfn = offset >> PAGE_SHIFT; - if (num_entries > AMDGPU_GPU_PAGES_IN_CPU_PAGE) { - uint64_t pfn = cursor.start >> PAGE_SHIFT; - uint64_t count; + if (res->mem_type == AMDGPU_PL_DGMA_IMPORT) { + addr = 0; + } else { + addr = pfn << PAGE_SHIFT; + addr += vram_base + + cursor.start + amdgpu_ttm_domain_start(adev, res->mem_type) - + amdgpu_ttm_domain_start(adev, TTM_PL_VRAM); + params.pages_addr = NULL; + } + } else { + if (pages_addr) { + bool contiguous = true; - contiguous = pages_addr[pfn + 1] == - pages_addr[pfn] + PAGE_SIZE; + if (num_entries > AMDGPU_GPU_PAGES_IN_CPU_PAGE) { + uint64_t pfn = cursor.start >> PAGE_SHIFT; + uint64_t count; - tmp = num_entries / - AMDGPU_GPU_PAGES_IN_CPU_PAGE; - for (count = 2; count < tmp; ++count) { - uint64_t idx = pfn + count; + contiguous = pages_addr[pfn + 1] == + pages_addr[pfn] + PAGE_SIZE; + + tmp = num_entries / + AMDGPU_GPU_PAGES_IN_CPU_PAGE; + for (count = 2; count < tmp; ++count) { + uint64_t idx = pfn + count; if (contiguous != (pages_addr[idx] == - pages_addr[idx - 1] + PAGE_SIZE)) + pages_addr[idx - 1] + PAGE_SIZE)) break; - } - if (!contiguous) + } + if (!contiguous) count--; - num_entries = count * - AMDGPU_GPU_PAGES_IN_CPU_PAGE; - } + num_entries = count * + AMDGPU_GPU_PAGES_IN_CPU_PAGE; + } - if (!contiguous) { - addr = cursor.start; - params.pages_addr = pages_addr; + if (!contiguous) { + addr = cursor.start; + params.pages_addr = pages_addr; + } else { + addr = pages_addr[cursor.start >> PAGE_SHIFT]; + params.pages_addr = NULL; + } + } else if (flags & (AMDGPU_PTE_VALID | AMDGPU_PTE_PRT_FLAG(adev))) { + addr = vram_base + cursor.start; } else { - addr = pages_addr[cursor.start >> PAGE_SHIFT]; - params.pages_addr = NULL; + addr = 0; } - - } else if (flags & (AMDGPU_PTE_VALID | AMDGPU_PTE_PRT_FLAG(adev))) { - addr = vram_base + cursor.start; - } else { - addr = 0; } - tmp = start + num_entries; r = amdgpu_vm_ptes_update(¶ms, start, tmp, addr, flags); if (r) From 9bbcfdb0ccbc6c5d16c59761fbd41f9428db2438 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Wed, 22 Apr 2020 22:53:31 -0400 Subject: [PATCH 0187/1868] drm/amdgpu: Add PCIe P2P support Allow mapping remote GPU memory in GPUVM for large-BAR GPUs with the BAR within the GPU physical address range. Signed-off-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c index 7d004a7ee37a9..f79d404d10d61 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c @@ -42,6 +42,7 @@ */ uint64_t amdgpu_amdkfd_total_mem_size; +extern bool pcie_p2p; static bool kfd_initialized; int amdgpu_amdkfd_init(void) From d10211e77cea58620b36586a1c114d3a9d926951 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Thu, 23 Apr 2020 00:11:19 -0400 Subject: [PATCH 0188/1868] drm/amdkfd: Add IPC API This allows exporting and importing buffers. The API generates handles that can be used with the HIP IPC API, i.e. big numbers rather than file descriptors. Signed-off-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 3 + .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 32 ++- drivers/gpu/drm/amd/amdkfd/Makefile | 1 + drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 73 ++++- drivers/gpu/drm/amd/amdkfd/kfd_ipc.c | 270 ++++++++++++++++++ drivers/gpu/drm/amd/amdkfd/kfd_ipc.h | 51 ++++ drivers/gpu/drm/amd/amdkfd/kfd_module.c | 5 + drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 28 +- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 106 ++++++- include/uapi/linux/kfd_ioctl.h | 22 ++ 10 files changed, 566 insertions(+), 25 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_ipc.c create mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_ipc.h diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index 4ed49265c764f..8cb33d3e0dba2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -334,6 +334,9 @@ int amdgpu_amdkfd_gpuvm_import_dmabuf_fd(struct amdgpu_device *adev, int fd, uint64_t *mmap_offset); int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_mem *mem, struct dma_buf **dmabuf); +int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_dev *kgd, void *vm, + struct kgd_mem *mem, + struct dma_buf **dmabuf); void amdgpu_amdkfd_debug_mem_fence(struct amdgpu_device *adev); int amdgpu_amdkfd_get_tile_config(struct amdgpu_device *adev, struct tile_config *config); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index e897d08c62ba4..a39107a5fe9d5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -2408,12 +2408,14 @@ static int import_obj_create(struct amdgpu_device *adev, INIT_LIST_HEAD(&(*mem)->attachments); mutex_init(&(*mem)->lock); - - (*mem)->alloc_flags = - ((bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ? - KFD_IOC_ALLOC_MEM_FLAGS_VRAM : KFD_IOC_ALLOC_MEM_FLAGS_GTT) - | KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE - | KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE; + if (bo->kfd_bo) + (*mem)->alloc_flags = bo->kfd_bo->alloc_flags; + else + (*mem)->alloc_flags = + ((bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) ? + KFD_IOC_ALLOC_MEM_FLAGS_VRAM : KFD_IOC_ALLOC_MEM_FLAGS_GTT) + | KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE + | KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE; get_dma_buf(dma_buf); (*mem)->dmabuf = dma_buf; @@ -2500,6 +2502,24 @@ int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_mem *mem, return ret; } +int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_dev *kgd, void *vm, + struct kgd_mem *mem, + struct dma_buf **dmabuf) +{ + struct amdgpu_device *adev = NULL; + + if (!dmabuf || !kgd || !vm || !mem) + return -EINVAL; + + adev = get_amdgpu_device(kgd); + + *dmabuf = amdgpu_gem_prime_export(&mem->bo->tbo.base, 0); + if (IS_ERR(*dmabuf)) + return -EINVAL; + + return 0; +} + /* Evict a userptr BO by stopping the queues if necessary * * Runs in MMU notifier, may be in RECLAIM_FS context. This means it diff --git a/drivers/gpu/drm/amd/amdkfd/Makefile b/drivers/gpu/drm/amd/amdkfd/Makefile index 0d3d8972240da..008b847a2df5c 100644 --- a/drivers/gpu/drm/amd/amdkfd/Makefile +++ b/drivers/gpu/drm/amd/amdkfd/Makefile @@ -59,6 +59,7 @@ AMDKFD_FILES := $(AMDKFD_PATH)/kfd_module.o \ $(AMDKFD_PATH)/kfd_int_process_v11.o \ $(AMDKFD_PATH)/kfd_smi_events.o \ $(AMDKFD_PATH)/kfd_crat.o \ + $(AMDKFD_PATH)/kfd_ipc.o \ $(AMDKFD_PATH)/kfd_debug.o ifneq ($(CONFIG_DEBUG_FS),) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 00350eccd5714..717891582ea8d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -41,6 +41,7 @@ #include "kfd_priv.h" #include "kfd_device_queue_manager.h" #include "kfd_svm.h" +#include "kfd_ipc.h" #include "amdgpu_amdkfd.h" #include "kfd_smi_events.h" #include "amdgpu_dma_buf.h" @@ -1049,6 +1050,8 @@ static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep, long err; uint64_t offset = args->mmap_offset; uint32_t flags = args->flags; + uint64_t cpuva = 0; + unsigned int mem_type = 0; if (args->size == 0) return -EINVAL; @@ -1137,7 +1140,13 @@ static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep, if (err) goto err_unlock; - idr_handle = kfd_process_device_create_obj_handle(pdd, mem); + mem_type = flags & (KFD_IOC_ALLOC_MEM_FLAGS_VRAM | + KFD_IOC_ALLOC_MEM_FLAGS_GTT | + KFD_IOC_ALLOC_MEM_FLAGS_USERPTR | + KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL | + KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP); + idr_handle = kfd_process_device_create_obj_handle(pdd, mem, + args->va_addr, args->size, cpuva, mem_type, NULL); if (idr_handle < 0) { err = -EFAULT; goto err_free; @@ -1181,7 +1190,8 @@ static int kfd_ioctl_free_memory_of_gpu(struct file *filep, { struct kfd_ioctl_free_memory_of_gpu_args *args = data; struct kfd_process_device *pdd; - void *mem; + struct kfd_bo *buf_obj; + struct kfd_dev *dev; int ret; uint64_t size = 0; @@ -1203,15 +1213,15 @@ static int kfd_ioctl_free_memory_of_gpu(struct file *filep, goto err_pdd; } - mem = kfd_process_device_translate_handle( - pdd, GET_IDR_HANDLE(args->handle)); - if (!mem) { + buf_obj = kfd_process_device_find_bo(pdd, + GET_IDR_HANDLE(args->handle)); + if (!buf_obj) { ret = -EINVAL; goto err_unlock; } ret = amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, - (struct kgd_mem *)mem, pdd->drm_priv, &size); + buf_obj->mem, pdd->drm_priv, &size); /* If freeing the buffer failed, leave the handle in place for * clean-up during process tear-down. @@ -1575,7 +1585,8 @@ static int kfd_ioctl_import_dmabuf(struct file *filep, if (r) goto err_unlock; - idr_handle = kfd_process_device_create_obj_handle(pdd, mem); + idr_handle = kfd_process_device_create_obj_handle(pdd, mem, + args->va_addr, size, 0, 0, -1); if (idr_handle < 0) { r = -EFAULT; goto err_free; @@ -1589,12 +1600,52 @@ static int kfd_ioctl_import_dmabuf(struct file *filep, err_free: amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, (struct kgd_mem *)mem, - pdd->drm_priv, NULL); + pdd->drm_priv, NULL); err_unlock: mutex_unlock(&p->mutex); return r; } +static int kfd_ioctl_ipc_export_handle(struct file *filep, + struct kfd_process *p, + void *data) +{ + struct kfd_ioctl_ipc_export_handle_args *args = data; + struct kfd_dev *dev; + int r; + + dev = kfd_device_by_id(args->gpu_id); + if (!dev) + return -EINVAL; + + r = kfd_ipc_export_as_handle(dev, p, args->handle, args->share_handle); + if (r) + pr_err("Failed to export IPC handle\n"); + + return r; +} + +static int kfd_ioctl_ipc_import_handle(struct file *filep, + struct kfd_process *p, + void *data) +{ + struct kfd_ioctl_ipc_import_handle_args *args = data; + struct kfd_dev *dev = NULL; + int r; + + dev = kfd_device_by_id(args->gpu_id); + if (!dev) + return -EINVAL; + + r = kfd_ipc_import_handle(dev, p, args->gpu_id, args->share_handle, + args->va_addr, &args->handle, + &args->mmap_offset); + if (r) + pr_err("Failed to import IPC handle\n"); + + return r; +} + static int kfd_ioctl_export_dmabuf(struct file *filep, struct kfd_process *p, void *data) { @@ -3199,6 +3250,12 @@ static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = { AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_TRAP, kfd_ioctl_set_debug_trap, 0), + + AMDKFD_IOCTL_DEF(AMDKFD_IOC_IPC_IMPORT_HANDLE, + kfd_ioctl_ipc_import_handle, 0), + + AMDKFD_IOCTL_DEF(AMDKFD_IOC_IPC_EXPORT_HANDLE, + kfd_ioctl_ipc_export_handle, 0), }; #define AMDKFD_CORE_IOCTL_COUNT ARRAY_SIZE(amdkfd_ioctls) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c new file mode 100644 index 0000000000000..51395a88c12a8 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c @@ -0,0 +1,270 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include +#include + +#include "kfd_ipc.h" +#include "kfd_priv.h" +#include "amdgpu_amdkfd.h" + +#define KFD_IPC_HASH_TABLE_SIZE_SHIFT 4 +#define KFD_IPC_HASH_TABLE_SIZE_MASK ((1 << KFD_IPC_HASH_TABLE_SIZE_SHIFT) - 1) + +static struct kfd_ipc_handles { + DECLARE_HASHTABLE(handles, KFD_IPC_HASH_TABLE_SIZE_SHIFT); + struct mutex lock; +} kfd_ipc_handles; + +/* Since, handles are random numbers, it can be used directly as hashing key. + * The least 4 bits of the handle are used as key. However, during import all + * 128 bits of the handle are checked to prevent handle snooping. + */ +#define HANDLE_TO_KEY(sh) ((*(uint64_t *)sh) & KFD_IPC_HASH_TABLE_SIZE_MASK) + +static int ipc_store_insert(void *val, void *sh, struct kfd_ipc_obj **ipc_obj) +{ + struct kfd_ipc_obj *obj; + + obj = kmalloc(sizeof(*obj), GFP_KERNEL); + if (!obj) + return -ENOMEM; + + /* The initial ref belongs to the allocator process. + * The IPC object store itself does not hold a ref since + * there is no specific moment in time where that ref should + * be dropped, except "when there are no more userspace processes + * holding a ref to the object". Therefore the removal from IPC + * storage happens at ipc_obj release time. + */ + kref_init(&obj->ref); + obj->data = val; + get_random_bytes(obj->share_handle, sizeof(obj->share_handle)); + + memcpy(sh, obj->share_handle, sizeof(obj->share_handle)); + + mutex_lock(&kfd_ipc_handles.lock); + hlist_add_head(&obj->node, + &kfd_ipc_handles.handles[HANDLE_TO_KEY(obj->share_handle)]); + mutex_unlock(&kfd_ipc_handles.lock); + + if (ipc_obj) + *ipc_obj = obj; + + return 0; +} + +static void ipc_obj_release(struct kref *r) +{ + struct kfd_ipc_obj *obj; + + obj = container_of(r, struct kfd_ipc_obj, ref); + + mutex_lock(&kfd_ipc_handles.lock); + hash_del(&obj->node); + mutex_unlock(&kfd_ipc_handles.lock); + + dma_buf_put(obj->data); + kfree(obj); +} + +void ipc_obj_get(struct kfd_ipc_obj *obj) +{ + kref_get(&obj->ref); +} + +void ipc_obj_put(struct kfd_ipc_obj **obj) +{ + kref_put(&(*obj)->ref, ipc_obj_release); + *obj = NULL; +} + +int kfd_ipc_init(void) +{ + mutex_init(&kfd_ipc_handles.lock); + hash_init(kfd_ipc_handles.handles); + return 0; +} + +static int kfd_import_dmabuf_create_kfd_bo(struct kfd_dev *dev, + struct kfd_process *p, + uint32_t gpu_id, struct dma_buf *dmabuf, + uint64_t va_addr, uint64_t *handle, + uint64_t *mmap_offset, + struct kfd_ipc_obj *ipc_obj) +{ + int r; + void *mem; + uint64_t size; + int idr_handle; + struct kfd_process_device *pdd = NULL; + + if (!handle) + return -EINVAL; + + if (!dev) + return -EINVAL; + + mutex_lock(&p->mutex); + + pdd = kfd_bind_process_to_device(dev, p); + if (IS_ERR(pdd)) { + r = PTR_ERR(pdd); + goto err_unlock; + } + + r = amdgpu_amdkfd_gpuvm_import_dmabuf(dev->kgd, dmabuf, + va_addr, pdd->vm, + (struct kgd_mem **)&mem, &size, + mmap_offset); + if (r) + goto err_unlock; + + idr_handle = kfd_process_device_create_obj_handle(pdd, mem, + va_addr, size, 0, 0, + ipc_obj); + if (idr_handle < 0) { + r = -EFAULT; + goto err_free; + } + + mutex_unlock(&p->mutex); + + *handle = MAKE_HANDLE(gpu_id, idr_handle); + + return 0; + +err_free: + amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->kgd, (struct kgd_mem *)mem, NULL); +err_unlock: + mutex_unlock(&p->mutex); + return r; +} + +int kfd_ipc_import_dmabuf(struct kfd_dev *dev, + struct kfd_process *p, + uint32_t gpu_id, int dmabuf_fd, + uint64_t va_addr, uint64_t *handle, + uint64_t *mmap_offset) +{ + int r; + struct dma_buf *dmabuf = dma_buf_get(dmabuf_fd); + + if (!dmabuf) + return -EINVAL; + + r = kfd_import_dmabuf_create_kfd_bo(dev, p, gpu_id, dmabuf, + va_addr, handle, mmap_offset, + NULL); + dma_buf_put(dmabuf); + return r; +} + +int kfd_ipc_import_handle(struct kfd_dev *dev, struct kfd_process *p, + uint32_t gpu_id, uint32_t *share_handle, + uint64_t va_addr, uint64_t *handle, + uint64_t *mmap_offset) +{ + int r; + struct kfd_ipc_obj *entry, *found = NULL; + + mutex_lock(&kfd_ipc_handles.lock); + /* Convert the user provided handle to hash key and search only in that + * bucket + */ + hlist_for_each_entry(entry, + &kfd_ipc_handles.handles[HANDLE_TO_KEY(share_handle)], node) { + if (!memcmp(entry->share_handle, share_handle, + sizeof(entry->share_handle))) { + found = entry; + break; + } + } + mutex_unlock(&kfd_ipc_handles.lock); + + if (!found) + return -EINVAL; + ipc_obj_get(found); + + pr_debug("Found ipc_dma_buf: %p\n", found->data); + + r = kfd_import_dmabuf_create_kfd_bo(dev, p, gpu_id, found->data, + va_addr, handle, mmap_offset, + found); + if (r) + goto error_unref; + + return r; + +error_unref: + ipc_obj_put(&found); + return r; +} + +int kfd_ipc_export_as_handle(struct kfd_dev *dev, struct kfd_process *p, + uint64_t handle, uint32_t *ipc_handle) +{ + struct kfd_process_device *pdd = NULL; + struct kfd_ipc_obj *obj; + struct kfd_bo *kfd_bo = NULL; + struct dma_buf *dmabuf; + int r; + + if (!dev || !ipc_handle) + return -EINVAL; + + mutex_lock(&p->mutex); + pdd = kfd_bind_process_to_device(dev, p); + if (IS_ERR(pdd)) { + mutex_unlock(&p->mutex); + pr_err("Failed to get pdd\n"); + return PTR_ERR(pdd); + } + + kfd_bo = kfd_process_device_find_bo(pdd, GET_IDR_HANDLE(handle)); + mutex_unlock(&p->mutex); + + if (!kfd_bo) { + pr_err("Failed to get bo"); + return -EINVAL; + } + if (kfd_bo->kfd_ipc_obj) { + memcpy(ipc_handle, kfd_bo->kfd_ipc_obj->share_handle, + sizeof(kfd_bo->kfd_ipc_obj->share_handle)); + return 0; + } + + r = amdgpu_amdkfd_gpuvm_export_dmabuf(dev->kgd, pdd->vm, + (struct kgd_mem *)kfd_bo->mem, + &dmabuf); + if (r) + return r; + + r = ipc_store_insert(dmabuf, ipc_handle, &obj); + if (r) + return r; + + kfd_bo->kfd_ipc_obj = obj; + + return r; +} diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h new file mode 100644 index 0000000000000..9ee8627b88b08 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h @@ -0,0 +1,51 @@ +/* + * Copyright 2014 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef KFD_IPC_H_ +#define KFD_IPC_H_ + +#include +#include "kfd_priv.h" + +struct kfd_ipc_obj { + struct hlist_node node; + struct kref ref; + void *data; + uint32_t share_handle[4]; +}; + +int kfd_ipc_import_handle(struct kfd_dev *dev, struct kfd_process *p, + uint32_t gpu_id, uint32_t *share_handle, + uint64_t va_addr, uint64_t *handle, + uint64_t *mmap_offset); +int kfd_ipc_import_dmabuf(struct kfd_dev *kfd, struct kfd_process *p, + uint32_t gpu_id, int dmabuf_fd, + uint64_t va_addr, uint64_t *handle, + uint64_t *mmap_offset); +int kfd_ipc_export_as_handle(struct kfd_dev *dev, struct kfd_process *p, + uint64_t handle, uint32_t *ipc_handle); + +void ipc_obj_get(struct kfd_ipc_obj *obj); +void ipc_obj_put(struct kfd_ipc_obj **obj); + +#endif /* KFD_IPC_H_ */ diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_module.c b/drivers/gpu/drm/amd/amdkfd/kfd_module.c index aee2212e52f69..a4f3155d0a2b1 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_module.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_module.c @@ -53,6 +53,10 @@ static int kfd_init(void) if (err < 0) goto err_topology; + err = kfd_ipc_init(); + if (err < 0) + goto err_ipc; + err = kfd_process_create_wq(); if (err < 0) goto err_create_wq; @@ -67,6 +71,7 @@ static int kfd_init(void) return 0; err_create_wq: +err_ipc: kfd_topology_shutdown(); err_topology: kfd_chardev_exit(); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 70dc7b951de24..3e98b7c0f4563 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -376,6 +376,19 @@ struct kfd_dev { unsigned long *doorbell_bitmap; }; +struct kfd_ipc_obj; + +struct kfd_bo { + void *mem; + struct interval_tree_node it; + struct kfd_dev *dev; + struct list_head cb_data_head; + struct kfd_ipc_obj *kfd_ipc_obj; + /* page-aligned VA address */ + uint64_t cpuva; + unsigned int mem_type; +}; + enum kfd_mempool { KFD_MEMPOOL_SYSTEM_CACHEABLE = 1, KFD_MEMPOOL_SYSTEM_WRITECOMBINE = 2, @@ -928,6 +941,8 @@ struct kfd_process { size_t signal_event_count; bool signal_event_limit_reached; + struct rb_root_cached bo_interval_tree; + /* Information used for memory eviction */ void *kgd_process_info; /* Eviction fence that is attached to all the BOs of this process. The @@ -1071,9 +1086,17 @@ int kfd_reserved_mem_mmap(struct kfd_node *dev, struct kfd_process *process, /* KFD process API for creating and translating handles */ int kfd_process_device_create_obj_handle(struct kfd_process_device *pdd, - void *mem); + void *mem, uint64_t start, + uint64_t length, uint64_t cpuva, + unsigned int mem_type, + struct kfd_ipc_obj *ipc_obj); void *kfd_process_device_translate_handle(struct kfd_process_device *p, int handle); +struct kfd_bo *kfd_process_device_find_bo(struct kfd_process_device *pdd, + int handle); +void *kfd_process_find_bo_from_interval(struct kfd_process *p, + uint64_t start_addr, + uint64_t last_addr); void kfd_process_device_remove_obj_handle(struct kfd_process_device *pdd, int handle); struct kfd_process *kfd_lookup_process_by_pid(struct pid *pid); @@ -1510,6 +1533,9 @@ int kfd_send_exception_to_runtime(struct kfd_process *p, uint64_t error_reason); bool kfd_is_locked(void); +/* IPC Support */ +int kfd_ipc_init(void); + /* Compute profile */ void kfd_inc_compute_active(struct kfd_node *dev); void kfd_dec_compute_active(struct kfd_node *dev); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index a902950cc0601..aad0e2973cbfe 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -32,6 +32,7 @@ #include #include #include +#include "kfd_ipc.h" #include #include "amdgpu_amdkfd.h" #include "amdgpu.h" @@ -714,6 +715,7 @@ static int kfd_process_alloc_gpuvm(struct kfd_process_device *pdd, { struct kfd_node *kdev = pdd->dev; int err; + unsigned int mem_type; err = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(kdev->adev, gpu_va, size, pdd->drm_priv, mem, NULL, @@ -955,7 +957,7 @@ struct kfd_process *kfd_lookup_process_by_pid(struct pid *pid) static void kfd_process_device_free_bos(struct kfd_process_device *pdd) { struct kfd_process *p = pdd->process; - void *mem; + struct kfd_bo *buf_obj; int id; int i; @@ -963,7 +965,8 @@ static void kfd_process_device_free_bos(struct kfd_process_device *pdd) * Remove all handles from idr and release appropriate * local memory object */ - idr_for_each_entry(&pdd->alloc_idr, mem, id) { + idr_for_each_entry(&pdd->alloc_idr, buf_obj, id) { + struct kfd_process_device *peer_pdd; for (i = 0; i < p->n_pdds; i++) { struct kfd_process_device *peer_pdd = p->pdds[i]; @@ -971,11 +974,11 @@ static void kfd_process_device_free_bos(struct kfd_process_device *pdd) if (!peer_pdd->drm_priv) continue; amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu( - peer_pdd->dev->adev, mem, peer_pdd->drm_priv); + peer_pdd->dev->kgd, buf_obj->mem, peer_pdd->drm_priv); } amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, mem, - pdd->drm_priv, NULL); + buf_obj->mem, pdd->drm_priv, NULL); kfd_process_device_remove_obj_handle(pdd, id); } } @@ -1758,9 +1761,49 @@ struct kfd_process_device *kfd_bind_process_to_device(struct kfd_node *dev, * Assumes that the process lock is held. */ int kfd_process_device_create_obj_handle(struct kfd_process_device *pdd, - void *mem) + void *mem, uint64_t start, + uint64_t length, uint64_t cpuva, + unsigned int mem_type, + struct kfd_ipc_obj *ipc_obj) +{ + int handle; + struct kfd_bo *buf_obj; + struct kfd_process *p; + + p = pdd->process; + + buf_obj = kzalloc(sizeof(*buf_obj), GFP_KERNEL); + + if (!buf_obj) + return -ENOMEM; + + buf_obj->it.start = start; + buf_obj->it.last = start + length - 1; + interval_tree_insert(&buf_obj->it, &p->bo_interval_tree); + + buf_obj->mem = mem; + buf_obj->dev = pdd->dev; + buf_obj->kfd_ipc_obj = ipc_obj; + buf_obj->cpuva = cpuva; + buf_obj->mem_type = mem_type; + + INIT_LIST_HEAD(&buf_obj->cb_data_head); + + handle = idr_alloc(&pdd->alloc_idr, buf_obj, 0, 0, GFP_KERNEL); + + if (handle < 0) + kfree(buf_obj); + + return handle; +} + +struct kfd_bo *kfd_process_device_find_bo(struct kfd_process_device *pdd, + int handle) { - return idr_alloc(&pdd->alloc_idr, mem, 0, 0, GFP_KERNEL); + if (handle < 0) + return NULL; + + return (struct kfd_bo *)idr_find(&pdd->alloc_idr, handle); } /* Translate specific handle from process local memory idr @@ -1769,10 +1812,37 @@ int kfd_process_device_create_obj_handle(struct kfd_process_device *pdd, void *kfd_process_device_translate_handle(struct kfd_process_device *pdd, int handle) { - if (handle < 0) + struct kfd_bo *buf_obj; + + buf_obj = kfd_process_device_find_bo(pdd, handle); + + return buf_obj->mem; +} + +void *kfd_process_find_bo_from_interval(struct kfd_process *p, + uint64_t start_addr, + uint64_t last_addr) +{ + struct interval_tree_node *it_node; + struct kfd_bo *buf_obj; + + it_node = interval_tree_iter_first(&p->bo_interval_tree, + start_addr, last_addr); + if (!it_node) { + pr_err("0x%llx-0x%llx does not relate to an existing buffer\n", + start_addr, last_addr); return NULL; + } + + if (interval_tree_iter_next(it_node, start_addr, last_addr)) { + pr_err("0x%llx-0x%llx spans more than a single BO\n", + start_addr, last_addr); + return NULL; + } + + buf_obj = container_of(it_node, struct kfd_bo, it); - return idr_find(&pdd->alloc_idr, handle); + return buf_obj; } /* Remove specific handle from process local memory idr @@ -1781,8 +1851,24 @@ void *kfd_process_device_translate_handle(struct kfd_process_device *pdd, void kfd_process_device_remove_obj_handle(struct kfd_process_device *pdd, int handle) { - if (handle >= 0) - idr_remove(&pdd->alloc_idr, handle); + struct kfd_bo *buf_obj; + struct kfd_process *p; + + p = pdd->process; + + if (handle < 0) + return; + + buf_obj = kfd_process_device_find_bo(pdd, handle); + + if (buf_obj->kfd_ipc_obj) + ipc_obj_put(&buf_obj->kfd_ipc_obj); + + idr_remove(&pdd->alloc_idr, handle); + + interval_tree_remove(&buf_obj->it, &p->bo_interval_tree); + + kfree(buf_obj); } /* This increments the process->ref counter. */ diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h index 71a7ce5f2d4c0..229948cf3dd9c 100644 --- a/include/uapi/linux/kfd_ioctl.h +++ b/include/uapi/linux/kfd_ioctl.h @@ -653,6 +653,22 @@ enum kfd_mmio_remap { KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL = 4, }; +struct kfd_ioctl_ipc_export_handle_args { + __u64 handle; /* to KFD */ + __u32 share_handle[4]; /* from KFD */ + __u32 gpu_id; /* to KFD */ + __u32 pad; +}; + +struct kfd_ioctl_ipc_import_handle_args { + __u64 handle; /* from KFD */ + __u64 va_addr; /* to KFD */ + __u64 mmap_offset; /* from KFD */ + __u32 share_handle[4]; /* to KFD */ + __u32 gpu_id; /* to KFD */ + __u32 pad; +}; + /* Guarantee host access to memory */ #define KFD_IOCTL_SVM_FLAG_HOST_ACCESS 0x00000001 /* Fine grained coherency between all devices with access */ @@ -1585,6 +1601,12 @@ struct kfd_ioctl_dbg_trap_args { #define AMDKFD_IOC_DBG_TRAP \ AMDKFD_IOWR(0x26, struct kfd_ioctl_dbg_trap_args) +#define AMDKFD_IOC_IPC_IMPORT_HANDLE \ + AMDKFD_IOWR(0x80, struct kfd_ioctl_ipc_import_handle_args) + +#define AMDKFD_IOC_IPC_EXPORT_HANDLE \ + AMDKFD_IOWR(0x81, struct kfd_ioctl_ipc_export_handle_args) + #define AMDKFD_COMMAND_START 0x01 #define AMDKFD_COMMAND_END 0x27 From 452fe0f6ec82d9ca68da1faf74924073c15f72fb Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Thu, 23 Apr 2020 01:26:36 -0400 Subject: [PATCH 0189/1868] drm/amdkfd: Add new GPU debugging API This is a completely new debug API that allows a debugger in a separate process to control wave execution, receive asynchronous notifications of events and query queue status. Change-Id: I765b39ebbd4ceb8a75c64c8a1ee24ab043c40330 Signed-off-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 3 ++- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 8 ++++++++ .../drm/amd/include/asic_reg/gc/gc_10_1_0_default.h | 7 +++++++ drivers/gpu/drm/amd/include/kgd_kfd_interface.h | 5 +++++ include/uapi/linux/kfd_ioctl.h | 10 ++++++++++ 5 files changed, 32 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index f6e2110702997..5e95b03bb56d3 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include #include @@ -1667,6 +1668,7 @@ static int initialize_cpsch(struct device_queue_manager *dqm) dqm->active_cp_queue_count = 0; dqm->gws_queue_count = 0; dqm->active_runlist = false; + INIT_WORK(&dqm->hw_exception_work, kfd_process_hw_exception); dqm->trap_debug_vmid = 0; @@ -2154,7 +2156,6 @@ static int unmap_queues_cpsch(struct device_queue_manager *dqm, if (retval) goto out; } - retval = pm_send_unmap_queue(&dqm->packet_mgr, filter, filter_param, reset); if (retval) goto out; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 3e98b7c0f4563..974d7e82f5ebd 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -1101,6 +1101,14 @@ void kfd_process_device_remove_obj_handle(struct kfd_process_device *pdd, int handle); struct kfd_process *kfd_lookup_process_by_pid(struct pid *pid); +/* Process device data iterator */ +struct kfd_process_device *kfd_get_first_process_device_data( + struct kfd_process *p); +struct kfd_process_device *kfd_get_next_process_device_data( + struct kfd_process *p, + struct kfd_process_device *pdd); +bool kfd_has_process_device_data(struct kfd_process *p); + /* PASIDs */ int kfd_pasid_init(void); void kfd_pasid_exit(void); diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_default.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_default.h index 320e1ee5df1a9..2050888f7ec6d 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_default.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_default.h @@ -2616,6 +2616,13 @@ #define mmSPI_WCL_PIPE_PERCENT_CS5_DEFAULT 0x0000007f #define mmSPI_WCL_PIPE_PERCENT_CS6_DEFAULT 0x0000007f #define mmSPI_WCL_PIPE_PERCENT_CS7_DEFAULT 0x0000007f +#define mmSPI_GDBG_WAVE_CNTL_DEFAULT 0x00000000 +#define mmSPI_GDBG_TRAP_CONFIG_DEFAULT 0x00000000 +#define mmSPI_GDBG_TRAP_MASK_DEFAULT 0x00000000 +#define mmSPI_GDBG_WAVE_CNTL2_DEFAULT 0x00000000 +#define mmSPI_GDBG_WAVE_CNTL3_DEFAULT 0x00000000 +#define mmSPI_GDBG_TRAP_DATA0_DEFAULT 0x00000000 +#define mmSPI_GDBG_TRAP_DATA1_DEFAULT 0x00000000 #define mmSPI_COMPUTE_QUEUE_RESET_DEFAULT 0x00000000 #define mmSPI_RESOURCE_RESERVE_CU_0_DEFAULT 0x00000000 #define mmSPI_RESOURCE_RESERVE_CU_1_DEFAULT 0x00000000 diff --git a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h index 7744ca3ef4b19..1243d4e2dd5ce 100644 --- a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h +++ b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h @@ -199,6 +199,11 @@ struct tile_config { * IH ring entry. This function allows the KFD ISR to get the VMID * from the fault status register as early as possible. * + * @get_iq_wait_times: Returns the mmCP_IQ_WAIT_TIME1/2 values + * + * @build_grace_period_packet_info: build a IQ_WAUT_TIME2 reg value with an + * updated grace period value. + * * @get_cu_occupancy: Function pointer that returns to caller the number * of wave fronts that are in flight for all of the queues of a process * as identified by its pasid. It is important to note that the value diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h index 229948cf3dd9c..35a3d25973080 100644 --- a/include/uapi/linux/kfd_ioctl.h +++ b/include/uapi/linux/kfd_ioctl.h @@ -242,6 +242,16 @@ struct kfd_ioctl_dbg_wave_control_args { #define KFD_INVALID_FD 0xffffffff +struct kfd_ioctl_dbg_trap_args { + __u64 ptr; /* to KFD -- used for pointer arguments: queue arrays */ + __u32 pid; /* to KFD */ + __u32 gpu_id; /* to KFD */ + __u32 op; /* to KFD */ + __u32 data1; /* to KFD */ + __u32 data2; /* to KFD */ + __u32 data3; /* to KFD */ +}; + /* Matching HSA_EVENTTYPE */ #define KFD_IOC_EVENT_SIGNAL 0 #define KFD_IOC_EVENT_NODECHANGE 1 From efaf1e870b4393c3053f610e41b4c06a98aea296 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Thu, 23 Apr 2020 02:23:36 -0400 Subject: [PATCH 0190/1868] drm/amdkfd: Add RDMA and PeerDirect support Both are interfaces between kernel drivers for direct peer-memory access between different devices, e.g. NICs and GPUs. The PeerDirect API is defined by Mellanox and supported by their non-upstream NIC driver. RDMA is an AMD interface and provides the implementation underneath the PeerDirect wrapper. It currently has no external users. Signed-off-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 22 + .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 206 ++++- drivers/gpu/drm/amd/amdkfd/Makefile | 1 + drivers/gpu/drm/amd/amdkfd/kfd_module.c | 3 + drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c | 702 ++++++++++++++++++ drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 5 +- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 9 +- drivers/gpu/drm/amd/dkms/sources | 1 + include/drm/amd_rdma.h | 78 ++ 9 files changed, 1021 insertions(+), 6 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c create mode 100644 include/drm/amd_rdma.h diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index 8cb33d3e0dba2..1b5a9eca185c6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -328,6 +328,28 @@ int amdgpu_amdkfd_gpuvm_restore_process_bos(void *process_info, struct dma_fence __rcu **ef); int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct amdgpu_device *adev, struct kfd_vm_fault_info *info); + +struct amdgpu_bo *amdgpu_amdkfd_gpuvm_get_bo_ref(struct kgd_mem *mem, + uint32_t *flags); +void amdgpu_amdkfd_gpuvm_put_bo_ref(struct amdgpu_bo *bo); + +int amdgpu_amdkfd_gpuvm_pin_bo(struct amdgpu_bo *bo); +void amdgpu_amdkfd_gpuvm_unpin_bo(struct amdgpu_bo *bo); + +int amdgpu_amdkfd_gpuvm_get_sg_table(struct kgd_dev *kgd, + struct amdgpu_bo *bo, uint32_t flags, + uint64_t offset, uint64_t size, + struct device *dma_dev, enum dma_data_direction dir, + struct sg_table **ret_sg); +void amdgpu_amdkfd_gpuvm_put_sg_table(struct amdgpu_bo *bo, + struct device *dma_dev, enum dma_data_direction dir, + struct sg_table *sg); + +int amdgpu_amdkfd_gpuvm_import_dmabuf(struct kgd_dev *kgd, + struct dma_buf *dmabuf, + uint64_t va, void *drm_priv, + struct kgd_mem **mem, uint64_t *size, + uint64_t *mmap_offset); int amdgpu_amdkfd_gpuvm_import_dmabuf_fd(struct amdgpu_device *adev, int fd, uint64_t va, void *drm_priv, struct kgd_mem **mem, uint64_t *size, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index a39107a5fe9d5..530bc6e73b01b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -1480,7 +1480,7 @@ static int init_kfd_vm(struct amdgpu_vm *vm, void **process_info, * * Return: ZERO if successful in pinning, Non-Zero in case of error. */ -static int amdgpu_amdkfd_gpuvm_pin_bo(struct amdgpu_bo *bo, u32 domain) +int amdgpu_amdkfd_gpuvm_pin_bo(struct amdgpu_bo *bo, u32 domain) { int ret = 0; @@ -1523,7 +1523,7 @@ static int amdgpu_amdkfd_gpuvm_pin_bo(struct amdgpu_bo *bo, u32 domain) * - All other BO types (GTT, VRAM, MMIO and DOORBELL) will have their * PIN count decremented. Calls to UNPIN must balance calls to PIN */ -static void amdgpu_amdkfd_gpuvm_unpin_bo(struct amdgpu_bo *bo) +void amdgpu_amdkfd_gpuvm_unpin_bo(struct amdgpu_bo *bo) { int ret = 0; @@ -2375,6 +2375,208 @@ int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct amdgpu_device *adev, return 0; } +struct amdgpu_bo *amdgpu_amdkfd_gpuvm_get_bo_ref(struct kgd_mem *mem, + uint32_t *flags) +{ + struct amdgpu_bo *bo = mem->bo; + + if (flags) + *flags = mem->alloc_flags; + drm_gem_object_get(&bo->tbo.base); + return bo; +} + +void amdgpu_amdkfd_gpuvm_put_bo_ref(struct amdgpu_bo *bo) +{ + drm_gem_object_put(&bo->tbo.base); +} + +#define AMD_GPU_PAGE_SHIFT PAGE_SHIFT +#define AMD_GPU_PAGE_SIZE (_AC(1, UL) << AMD_GPU_PAGE_SHIFT) + +/** + * @get_sg_table_of_mmio_or_doorbel_bo - Builds and returns an instance + * of scatter gather table (sg_table) for BO's that represent MMIO or + * DOORBELL memory. An example of this is the MMIO BO that is used to + * surface HDP registers. + * + * @note: Per current design and implementation MMIO or DOORBELL BO's + * use only one scatterlist node in their sg_table. This is because + * the size of backing memory is relatively small (e.g. 4096 bytes + * for MMIO BO surfacing HDP registers). Implementation of this method + * relies on this design choice. + * + * The method does the following: + * Acquire address to use in building scatterlist nodes + * Acquire size of memory to use in building scatterlist nodes + * Invoke DMA Map service to obtain DMA'able address + * Access sg_table construction service with above parameters + * Return the handle of scatter gather table + * + * @adev: GPU device whose MMIO address needs to be exported + * @bo: Buffer object representing MMIO/DOORBELL memory e.g. HDP registers + * @dma_dev: Handle of peer PCIe device that wishes to access BO's memory + * @dir: Direction of data movement from peer PCIe devices perspective + * + * @sgt: Output parameter that is built and returned + * + * Return: zero if successful, non-zero otherwise + * + * @FIXME: This will only work as long as bo->tbo.sg->sgl->dma_address + * is not a DMA address but a physical BAR address. This will be reworked + * later when we add DMA mapping support for doorbell and MMIO BOs + */ +static int get_sg_table_of_mmio_or_doorbel_bo(struct amdgpu_bo *bo, + struct device *dma_dev, enum dma_data_direction dir, + struct sg_table **sgt) +{ + dma_addr_t dma_addr; + s32 size, ret; + u64 addr; + + /* Acquire the address of MMIO or DOORBELL BO being + * exported. By policy the entire backing memory is + * encapsulated in one scatterlist node + */ + size = bo->tbo.sg->sgl->length; + addr = bo->tbo.sg->sgl->dma_address; + pr_debug("MMIO/Doorbell address being exported: %llx\n", addr); + + /* DMA map the acquired address - MMIO or DOORBELL */ + dma_addr = dma_map_resource(dma_dev, addr, size, + dir, DMA_ATTR_SKIP_CPU_SYNC); + ret = dma_mapping_error(dma_dev, dma_addr); + if (ret) + return ret; + + /* Update output parameter with a new sg_table */ + pr_debug("MMIO/Doorbell BO size: %d\n", size); + pr_debug("MMIO/Doorbell's DMA Address: %llx\n", dma_addr); + *sgt = create_doorbell_sg(dma_addr, size); + return 0; +} + +int amdgpu_amdkfd_gpuvm_get_sg_table(struct kgd_dev *kgd, + struct amdgpu_bo *bo, uint32_t flags, + uint64_t offset, uint64_t size, + struct device *dma_dev, enum dma_data_direction dir, + struct sg_table **ret_sg) +{ + struct amdgpu_device *adev = get_amdgpu_device(kgd); + struct sg_table *sg = NULL; + struct scatterlist *s; + struct page **pages; + uint64_t offset_in_page; + unsigned int page_size; + unsigned int cur_page; + unsigned int chunks; + unsigned int idx; + int ret; + + /* Determine access does not cross memory boundary */ + if (size + offset > amdgpu_bo_size(bo)) + return -EFAULT; + + /* For GPU memory use VRAM Mgr to build SG Table */ + if (bo->preferred_domains == AMDGPU_GEM_DOMAIN_VRAM) { + ret = amdgpu_vram_mgr_alloc_sgt(adev, bo->tbo.resource, offset, + size, dma_dev, dir, &sg); + *ret_sg = (ret == 0) ? sg : NULL; + return ret; + } + + /* Handle BO (type: ttm_bo_type_sg) that is used to surface + * resources from MMIO address space. The allocation flag of + * BO fall in MMIO_REMAP / DOORBELL domain + */ + if (bo->tbo.type == ttm_bo_type_sg && + ((flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) || + (flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP))) { + ret = get_sg_table_of_mmio_or_doorbel_bo(bo, dma_dev, dir, &sg); + *ret_sg = (ret == 0) ? sg : NULL; + return ret; + } + + /* Handle BO (type: ttm_bo_type_device) that is used to surface + * memory resources from GPU's GART aperture. The allocation flag + * of BO falls in GTT domain i.e. the physical backing memory is + * part of system memory. Construction of SG Table proceeds + * as follows: + * + * Allocate memory for SG Table + * Determine number of Scatterlist node in table + * Logic uses one Scatterlist node per PAGE_SIZE + * Allocate memory for Scatterlist nodes + * Initialize Scatterlist nodes to zero length + * Walk down system memory pointed by BO while + * Updating Scatterlist nodes with system memory info + */ + sg = kmalloc(sizeof(*sg), GFP_KERNEL); + if (!sg) { + ret = -ENOMEM; + goto out; + } + + page_size = PAGE_SIZE; + offset_in_page = offset & (page_size - 1); + chunks = (size + offset_in_page + page_size - 1) + / page_size; + + ret = sg_alloc_table(sg, chunks, GFP_KERNEL); + if (unlikely(ret)) + goto out; + + for_each_sgtable_sg(sg, s, idx) + s->length = 0; + + pages = bo->tbo.ttm->pages; + cur_page = offset / page_size; + for_each_sg(sg->sgl, s, sg->orig_nents, idx) { + uint64_t chunk_size, length; + + chunk_size = page_size - offset_in_page; + length = min(size, chunk_size); + + sg_set_page(s, pages[cur_page], length, offset_in_page); + s->dma_address = page_to_phys(pages[cur_page]); + s->dma_length = length; + + size -= length; + offset_in_page = 0; + cur_page++; + } + + ret = dma_map_sgtable(dma_dev, sg, dir, DMA_ATTR_SKIP_CPU_SYNC); + if (ret) + goto out_of_range; + + *ret_sg = sg; + return 0; + +out_of_range: + sg_free_table(sg); +out: + kfree(sg); + *ret_sg = NULL; + return ret; +} + +void amdgpu_amdkfd_gpuvm_put_sg_table(struct amdgpu_bo *bo, + struct device *dma_dev, enum dma_data_direction dir, + struct sg_table *sgt) +{ + /* Unmap GPU device memory */ + if (bo->preferred_domains == AMDGPU_GEM_DOMAIN_VRAM) { + amdgpu_vram_mgr_free_sgt(dma_dev, dir, sgt); + return; + } + + /* Unmap system memory */ + dma_unmap_sgtable(dma_dev, sgt, dir, DMA_ATTR_SKIP_CPU_SYNC); + sg_free_table(sgt); + kfree(sgt); +} + static int import_obj_create(struct amdgpu_device *adev, struct dma_buf *dma_buf, struct drm_gem_object *obj, diff --git a/drivers/gpu/drm/amd/amdkfd/Makefile b/drivers/gpu/drm/amd/amdkfd/Makefile index 008b847a2df5c..188b500900dac 100644 --- a/drivers/gpu/drm/amd/amdkfd/Makefile +++ b/drivers/gpu/drm/amd/amdkfd/Makefile @@ -59,6 +59,7 @@ AMDKFD_FILES := $(AMDKFD_PATH)/kfd_module.o \ $(AMDKFD_PATH)/kfd_int_process_v11.o \ $(AMDKFD_PATH)/kfd_smi_events.o \ $(AMDKFD_PATH)/kfd_crat.o \ + $(AMDKFD_PATH)/kfd_peerdirect.o \ $(AMDKFD_PATH)/kfd_ipc.o \ $(AMDKFD_PATH)/kfd_debug.o diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_module.c b/drivers/gpu/drm/amd/amdkfd/kfd_module.c index a4f3155d0a2b1..5f8093e03d340 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_module.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_module.c @@ -61,6 +61,8 @@ static int kfd_init(void) if (err < 0) goto err_create_wq; + kfd_init_peer_direct(); + /* Ignore the return value, so that we can continue * to init the KFD, even if procfs isn't craated */ @@ -84,6 +86,7 @@ static void kfd_exit(void) { kfd_cleanup_processes(); kfd_debugfs_fini(); + kfd_close_peer_direct(); kfd_process_destroy_wq(); kfd_procfs_shutdown(); kfd_topology_shutdown(); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c b/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c new file mode 100644 index 0000000000000..27fe96b788de6 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c @@ -0,0 +1,702 @@ +/* + * Copyright 2016 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + + +/* NOTE: + * + * This file contains logic to dynamically detect and enable PeerDirect + * suppor. PeerDirect support is delivered e.g. as part of OFED + * from Mellanox. Because we are not able to rely on the fact that the + * corresponding OFED will be installed we should: + * - copy PeerDirect definitions locally to avoid dependency on + * corresponding header file + * - try dynamically detect address of PeerDirect function + * pointers. + * + * If dynamic detection failed then PeerDirect support should be + * enabled using the standard PeerDirect bridge driver from: + * https://github.com/RadeonOpenCompute/ROCnRDMA + * + * + * Logic to support PeerDirect relies only on official public API to be + * non-intrusive as much as possible. + * + **/ + +#include +#include +#include +#include +#include +#include + +#include "kfd_priv.h" + +/* ----------------------- PeerDirect interface ------------------------------*/ + +/* + * Copyright (c) 2013, Mellanox Technologies. All rights reserved. + * + * This software is available to you under a choice of one of two + * licenses. You may choose to be licensed under the terms of the GNU + * General Public License (GPL) Version 2, available from the file + * COPYING in the main directory of this source tree, or the + * OpenIB.org BSD license below: + * + * Redistribution and use in source and binary forms, with or + * without modification, are permitted provided that the following + * conditions are met: + * + * - Redistributions of source code must retain the above + * copyright notice, this list of conditions and the following + * disclaimer. + * + * - Redistributions in binary form must reproduce the above + * copyright notice, this list of conditions and the following + * disclaimer in the documentation and/or other materials + * provided with the distribution. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS + * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN + * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#define IB_PEER_MEMORY_NAME_MAX 64 +#define IB_PEER_MEMORY_VER_MAX 16 + +struct peer_memory_client { + char name[IB_PEER_MEMORY_NAME_MAX]; + char version[IB_PEER_MEMORY_VER_MAX]; + /* acquire return code: 1-mine, 0-not mine */ + int (*acquire)(unsigned long addr, size_t size, + void *peer_mem_private_data, + char *peer_mem_name, + void **client_context); + int (*get_pages)(unsigned long addr, + size_t size, int write, int force, + struct sg_table *sg_head, + void *client_context, void *core_context); + int (*dma_map)(struct sg_table *sg_head, void *client_context, + struct device *dma_device, int dmasync, int *nmap); + int (*dma_unmap)(struct sg_table *sg_head, void *client_context, + struct device *dma_device); + void (*put_pages)(struct sg_table *sg_head, void *client_context); + unsigned long (*get_page_size)(void *client_context); + void (*release)(void *client_context); + void* (*get_context_private_data)(u64 peer_id); + void (*put_context_private_data)(void *context); +}; + +typedef int (*invalidate_peer_memory)(void *reg_handle, + void *core_context); + +void *ib_register_peer_memory_client(struct peer_memory_client *peer_client, + invalidate_peer_memory *invalidate_callback); +void ib_unregister_peer_memory_client(void *reg_handle); + + +/*------------------- PeerDirect bridge driver ------------------------------*/ + +#define AMD_PEER_BRIDGE_DRIVER_VERSION "1.0" +#define AMD_PEER_BRIDGE_DRIVER_NAME "amdkfd" + +static char rdma_name[] = "AMD RDMA"; + + +static void* (*pfn_ib_register_peer_memory_client)(struct peer_memory_client + *peer_client, + invalidate_peer_memory + *invalidate_callback); + +static void (*pfn_ib_unregister_peer_memory_client)(void *reg_handle); + +static void *ib_reg_handle; + +struct amd_mem_context { + uint64_t va; + uint64_t size; + unsigned long offset; + struct amdgpu_bo *bo; + struct kfd_dev *dev; + + struct sg_table *pages; + struct device *dma_dev; + + + /* Context received from PeerDirect call */ + void *core_context; + + pid_t pid; + uint32_t flags; +}; + +/* Workaround: Mellanox peerdirect driver expects sg lists at + * page granularity. This causes failures when an application tries + * to register size < PAGE_SIZE or addr starts at some offset. Fix + * it by aligning the size to page size and addr to page boundary. + */ +static void align_addr_size(unsigned long *addr, size_t *size) +{ + unsigned long end = ALIGN(*addr + *size, PAGE_SIZE); + + *addr = ALIGN_DOWN(*addr, PAGE_SIZE); + *size = end - *addr; +} + +static int amd_acquire(unsigned long addr, size_t size, + void *peer_mem_private_data, + char *peer_mem_name, void **client_context) +{ + struct kfd_process *p; + struct kfd_bo *buf_obj; + struct amd_mem_context *mem_context; + + if (peer_mem_name == rdma_name) { + p = peer_mem_private_data; + } else { + p = kfd_get_process(current); + if (!p) { + pr_debug("Not a KFD process\n"); + return 0; + } + } + + align_addr_size(&addr, &size); + + mutex_lock(&p->mutex); + buf_obj = kfd_process_find_bo_from_interval(p, addr, + addr + size - 1); + if (!buf_obj) { + pr_debug("Cannot find a kfd_bo for the range\n"); + goto out_unlock; + } + + /* Initialize context used for operation with given address */ + mem_context = kzalloc(sizeof(*mem_context), GFP_KERNEL); + if (!mem_context) + goto out_unlock; + + mem_context->pid = p->lead_thread->pid; + + pr_debug("addr: %#lx, size: %#lx, pid: %d\n", + addr, size, mem_context->pid); + + mem_context->va = addr; + mem_context->size = size; + mem_context->offset = addr - buf_obj->it.start; + + mem_context->bo = amdgpu_amdkfd_gpuvm_get_bo_ref(buf_obj->mem, + &mem_context->flags); + mem_context->dev = buf_obj->dev; + + mutex_unlock(&p->mutex); + + pr_debug("Client context: 0x%p\n", mem_context); + + /* Return pointer to allocated context */ + *client_context = mem_context; + + /* Return 1 to inform that this address which will be handled + * by AMD GPU driver + */ + return 1; + +out_unlock: + mutex_unlock(&p->mutex); + return 0; +} + +static int amd_get_pages(unsigned long addr, size_t size, int write, int force, + struct sg_table *sg_head, + void *client_context, void *core_context) +{ + int ret; + struct amd_mem_context *mem_context = + (struct amd_mem_context *)client_context; + + align_addr_size(&addr, &size); + + pr_debug("addr: %#lx, size: %#lx, core_context: 0x%p\n", + addr, size, core_context); + + if (!mem_context || !mem_context->bo || !mem_context->dev) { + pr_warn("Invalid client context"); + return -EINVAL; + } + + pr_debug("pid: %d\n", mem_context->pid); + + if (addr != mem_context->va) { + pr_warn("Context address (%#llx) is not the same\n", + mem_context->va); + return -EINVAL; + } + + if (size != mem_context->size) { + pr_warn("Context size (%#llx) is not the same\n", + mem_context->size); + return -EINVAL; + } + + ret = amdgpu_amdkfd_gpuvm_pin_bo(mem_context->bo); + if (ret) { + pr_err("Pinning of buffer failed.\n"); + return ret; + } + + /* Mark the device as active */ + kfd_inc_compute_active(mem_context->dev); + + mem_context->core_context = core_context; + + return 0; +} + + +static int amd_dma_map(struct sg_table *sg_head, void *client_context, + struct device *dma_device, int dmasync, int *nmap) +{ + struct sg_table *sg_table_tmp; + int ret; + + /* + * NOTE/TODO: + * We could have potentially three cases for real memory + * location: + * - all memory in the local + * - all memory in the system (RAM) + * - memory is spread (s/g) between local and system. + * + * In the case of all memory in the system we could use + * iommu driver to build DMA addresses but not in the case + * of local memory because currently iommu driver doesn't + * deal with local/device memory addresses (it requires "struct + * page"). + * + * Accordingly returning assumes that iommu funcutionality + * should be disabled so we can assume that sg_table already + * contains DMA addresses. + * + */ + struct amd_mem_context *mem_context = + (struct amd_mem_context *)client_context; + + pr_debug("Client context: 0x%p, sg_head: 0x%p\n", + client_context, sg_head); + + if (!mem_context || !mem_context->bo || !mem_context->dev) { + pr_warn("Invalid client context"); + return -EINVAL; + } + + pr_debug("pid: %d, address: %#llx, size: %#llx\n", + mem_context->pid, + mem_context->va, + mem_context->size); + + /* Build sg_table for buffer being exported, including DMA mapping */ + ret = amdgpu_amdkfd_gpuvm_get_sg_table( + mem_context->dev->kgd, mem_context->bo, mem_context->flags, + mem_context->offset, mem_context->size, + dma_device, DMA_BIDIRECTIONAL, &sg_table_tmp); + if (ret) { + pr_err("Building of sg_table failed\n"); + return ret; + } + + /* Maintain a copy of the handle to sg_table */ + mem_context->pages = sg_table_tmp; + mem_context->dma_dev = dma_device; + + /* Copy information about previosly allocated sg_table */ + *sg_head = *mem_context->pages; + + /* Return number of pages */ + *nmap = mem_context->pages->nents; + + return ret; +} + +static int amd_dma_unmap(struct sg_table *sg_head, void *client_context, + struct device *dma_device) +{ + struct amd_mem_context *mem_context = + (struct amd_mem_context *)client_context; + + pr_debug("Client context: 0x%p, sg_table: 0x%p\n", + client_context, sg_head); + + if (!mem_context || !mem_context->bo || !mem_context->dma_dev) { + pr_warn("Invalid client context"); + return -EINVAL; + } + + pr_debug("pid: %d, address: %#llx, size: %#llx\n", + mem_context->pid, + mem_context->va, + mem_context->size); + + /* Release the mapped pages of buffer */ + amdgpu_amdkfd_gpuvm_put_sg_table(mem_context->bo, + mem_context->dma_dev, + DMA_BIDIRECTIONAL, + mem_context->pages); + mem_context->pages = NULL; + + return 0; +} + +static void amd_put_pages(struct sg_table *sg_head, void *client_context) +{ + struct amd_mem_context *mem_context = + (struct amd_mem_context *)client_context; + + pr_debug("Client context: 0x%p, sg_head: 0x%p\n", + client_context, sg_head); + pr_debug("pid: %d, address: %#llx, size: %#llx\n", + mem_context->pid, + mem_context->va, + mem_context->size); + + amdgpu_amdkfd_gpuvm_unpin_bo(mem_context->bo); + kfd_dec_compute_active(mem_context->dev); +} + +static unsigned long amd_get_page_size(void *client_context) +{ + return PAGE_SIZE; +} + +static void amd_release(void *client_context) +{ + struct amd_mem_context *mem_context = + (struct amd_mem_context *)client_context; + + pr_debug("Client context: 0x%p\n", client_context); + pr_debug("pid: %d, address: %#llx, size: %#llx\n", + mem_context->pid, + mem_context->va, + mem_context->size); + + amdgpu_amdkfd_gpuvm_put_bo_ref(mem_context->bo); + + kfree(mem_context); +} + + +static struct peer_memory_client amd_mem_client = { + .acquire = amd_acquire, + .get_pages = amd_get_pages, + .dma_map = amd_dma_map, + .dma_unmap = amd_dma_unmap, + .put_pages = amd_put_pages, + .get_page_size = amd_get_page_size, + .release = amd_release, + .get_context_private_data = NULL, + .put_context_private_data = NULL, +}; + +/** Initialize PeerDirect interface with RDMA Network stack. + * + * Because network stack could potentially be loaded later we check + * presence of PeerDirect when HSA process is created. If PeerDirect was + * already initialized we do nothing otherwise try to detect and register. + */ +void kfd_init_peer_direct(void) +{ + if (pfn_ib_unregister_peer_memory_client) { + pr_debug("PeerDirect support was already initialized\n"); + return; + } + + pr_debug("Try to initialize PeerDirect support\n"); + + pfn_ib_register_peer_memory_client = + (void *(*)(struct peer_memory_client *, + invalidate_peer_memory *)) + symbol_request(ib_register_peer_memory_client); + + pfn_ib_unregister_peer_memory_client = (void (*)(void *)) + symbol_request(ib_unregister_peer_memory_client); + + if (!pfn_ib_register_peer_memory_client || + !pfn_ib_unregister_peer_memory_client) { + pr_debug("PeerDirect interface was not detected\n"); + /* Do cleanup */ + kfd_close_peer_direct(); + return; + } + + strcpy(amd_mem_client.name, AMD_PEER_BRIDGE_DRIVER_NAME); + strcpy(amd_mem_client.version, AMD_PEER_BRIDGE_DRIVER_VERSION); + + ib_reg_handle = pfn_ib_register_peer_memory_client(&amd_mem_client, NULL); + + if (!ib_reg_handle) { + pr_err("Cannot register peer memory client\n"); + /* Do cleanup */ + kfd_close_peer_direct(); + return; + } + + pr_info("PeerDirect support was initialized successfully\n"); +} + +/** + * Close connection with PeerDirect interface with RDMA Network stack. + * + */ +void kfd_close_peer_direct(void) +{ + if (pfn_ib_unregister_peer_memory_client) { + if (ib_reg_handle) + pfn_ib_unregister_peer_memory_client(ib_reg_handle); + + symbol_put(ib_unregister_peer_memory_client); + } + + if (pfn_ib_register_peer_memory_client) + symbol_put(ib_register_peer_memory_client); + + + /* Reset pointers to be safe */ + pfn_ib_unregister_peer_memory_client = NULL; + pfn_ib_register_peer_memory_client = NULL; + ib_reg_handle = NULL; +} + +/* ------------------------- AMD RDMA wrapper --------------------------------*/ + +#include "drm/amd_rdma.h" + +struct rdma_p2p_data { + struct amd_p2p_info p2p_info; + void (*free_callback)(void *client_priv); + void *client_priv; +}; + +/** + * This function makes the pages underlying a range of GPU virtual memory + * accessible for DMA operations from another PCIe device + * + * \param address - The start address in the Unified Virtual Address + * space in the specified process + * \param length - The length of requested mapping + * \param pid - Pointer to structure pid to which address belongs. + * Could be NULL for current process address space. + * \param p2p_data - On return: Pointer to structure describing + * underlying pages/locations + * \param free_callback - Pointer to callback which will be called when access + * to such memory must be stopped immediately: Memory + * was freed, GECC events, etc. + * Client should immediately stop any transfer + * operations and returned as soon as possible. + * After return all resources associated with address + * will be release and no access will be allowed. + * \param client_priv - Pointer to be passed as parameter on + * 'free_callback; + * + * \return 0 if operation was successful + */ +static int rdma_get_pages(uint64_t address, uint64_t length, struct pid *pid, + struct device *dma_dev, + struct amd_p2p_info **amd_p2p_data, + void (*free_callback)(void *client_priv), + void *client_priv) +{ + struct rdma_p2p_data *p2p_data; + struct kfd_process *p; + struct sg_table sg_head; + struct amd_mem_context *mem_context; + int nmap; + int r; + + p2p_data = kzalloc(sizeof(*p2p_data), GFP_KERNEL); + if (!p2p_data) + return -ENOMEM; + + p = kfd_lookup_process_by_pid(pid); + if (!p) { + pr_debug("pid lookup failed\n"); + r = -ESRCH; + goto err_lookup_process; + } + + r = amd_acquire(address, length, p, rdma_name, (void **)&mem_context); + kfd_unref_process(p); + if (r == 0) { + pr_debug("acquire failed: %d\n", r); + goto err_acquire; + } + + r = amd_get_pages(address, length, 1, 0, &sg_head, + mem_context, p2p_data); + if (r) { + pr_debug("get_pages failed: %d\n", r); + goto err_get_pages; + } + + r = amd_dma_map(&sg_head, mem_context, dma_dev, 0, &nmap); + if (r) { + pr_debug("dma_map failed: %d\n", r); + goto err_dma_map; + } + + + p2p_data->free_callback = free_callback; + p2p_data->client_priv = client_priv; + p2p_data->p2p_info.va = address; + p2p_data->p2p_info.size = length; + p2p_data->p2p_info.pid = pid; + p2p_data->p2p_info.pages = mem_context->pages; + p2p_data->p2p_info.priv = mem_context; + + *amd_p2p_data = &p2p_data->p2p_info; + + return 0; + +err_dma_map: + amd_put_pages(&sg_head, mem_context); +err_get_pages: + amd_release(mem_context); +err_acquire: +err_lookup_process: + kfree(p2p_data); + + return r; +} + +/** + * + * This function release resources previously allocated by get_pages() call. + * + * \param p_p2p_data - A pointer to pointer to amd_p2p_info entries + * allocated by get_pages() call. + * + * \return 0 if operation was successful + */ +static int rdma_put_pages(struct amd_p2p_info **p_p2p_data) +{ + struct rdma_p2p_data *p2p_data = + container_of(*p_p2p_data, struct rdma_p2p_data, p2p_info); + int r; + + r = amd_dma_unmap(p2p_data->p2p_info.pages, + p2p_data->p2p_info.priv, + NULL); + if (r) + return r; + amd_put_pages(p2p_data->p2p_info.pages, + p2p_data->p2p_info.priv); + amd_release(p2p_data->p2p_info.priv); + kfree(p2p_data); + + *p_p2p_data = NULL; + + return 0; +} + +/** + * Check if given address belongs to GPU address space. + * + * \param address - Address to check + * \param pid - Process to which given address belongs. + * Could be NULL if current one. + * + * \return 0 - This is not GPU address managed by AMD driver + * 1 - This is GPU address managed by AMD driver + */ +static int rdma_is_gpu_address(uint64_t address, struct pid *pid) +{ + struct kfd_bo *buf_obj; + struct kfd_process *p; + + p = kfd_lookup_process_by_pid(pid); + if (!p) { + pr_debug("Could not find the process\n"); + return 0; + } + + buf_obj = kfd_process_find_bo_from_interval(p, address, address); + + kfd_unref_process(p); + if (!buf_obj) + return 0; + + return 1; +} + +/** + * Return the single page size to be used when building scatter/gather table + * for given range. + * + * \param address - Address + * \param length - Range length + * \param pid - Process id structure. Could be NULL if current one. + * \param page_size - On return: Page size + * + * \return 0 if operation was successful + */ +static int rdma_get_page_size(uint64_t address, uint64_t length, + struct pid *pid, unsigned long *page_size) +{ + /* + * As local memory is always consecutive, we can assume the local + * memory page size to be arbitrary. + * Currently we assume the local memory page size to be the same + * as system memory, which is 4KB. + */ + *page_size = PAGE_SIZE; + + return 0; +} + +/** + * Singleton object: rdma interface function pointers + */ +static const struct amd_rdma_interface rdma_ops = { + .get_pages = rdma_get_pages, + .put_pages = rdma_put_pages, + .is_gpu_address = rdma_is_gpu_address, + .get_page_size = rdma_get_page_size +}; + +/** + * amdkfd_query_rdma_interface - Return interface (function pointers table) for + * rdma interface + * + * + * \param interace - OUT: Pointer to interface + * + * \return 0 if operation was successful. + */ +int amdkfd_query_rdma_interface(const struct amd_rdma_interface **ops) +{ + *ops = &rdma_ops; + + return 0; +} +EXPORT_SYMBOL(amdkfd_query_rdma_interface); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 974d7e82f5ebd..c695d7ffa42ef 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -382,7 +382,6 @@ struct kfd_bo { void *mem; struct interval_tree_node it; struct kfd_dev *dev; - struct list_head cb_data_head; struct kfd_ipc_obj *kfd_ipc_obj; /* page-aligned VA address */ uint64_t cpuva; @@ -1541,6 +1540,10 @@ int kfd_send_exception_to_runtime(struct kfd_process *p, uint64_t error_reason); bool kfd_is_locked(void); +/* PeerDirect support */ +void kfd_init_peer_direct(void); +void kfd_close_peer_direct(void); + /* IPC Support */ int kfd_ipc_init(void); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index aad0e2973cbfe..315d68b73585d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -977,7 +977,8 @@ static void kfd_process_device_free_bos(struct kfd_process_device *pdd) peer_pdd->dev->kgd, buf_obj->mem, peer_pdd->drm_priv); } - amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, mem, + run_rdma_free_callback(buf_obj); + amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, buf_obj->mem, pdd->drm_priv, NULL); kfd_process_device_remove_obj_handle(pdd, id); } @@ -1544,6 +1545,10 @@ static struct kfd_process *create_process(const struct task_struct *thread) kfd_unref_process(process); get_task_struct(process->lead_thread); + /* If PeerDirect interface was not detected try to detect it again + * in case if network driver was loaded later. + */ + kfd_init_peer_direct(); INIT_WORK(&process->debug_event_workarea, debug_event_write_work_handler); return process; @@ -1787,8 +1792,6 @@ int kfd_process_device_create_obj_handle(struct kfd_process_device *pdd, buf_obj->cpuva = cpuva; buf_obj->mem_type = mem_type; - INIT_LIST_HEAD(&buf_obj->cb_data_head); - handle = idr_alloc(&pdd->alloc_idr, buf_obj, 0, 0, GFP_KERNEL); if (handle < 0) diff --git a/drivers/gpu/drm/amd/dkms/sources b/drivers/gpu/drm/amd/dkms/sources index 3470a58a43676..a1b74441203de 100644 --- a/drivers/gpu/drm/amd/dkms/sources +++ b/drivers/gpu/drm/amd/dkms/sources @@ -24,6 +24,7 @@ include/drm/gpu_scheduler.h include/drm/ include/drm/amd_asic_type.h include/drm/ include/drm/spsc_queue.h include/drm/ include/uapi/linux/kfd_ioctl.h include/uapi/linux/ +include/drm/amd_rdma.h include/drm/ drivers/dma-buf/dma-resv.c amd/amdkcl/dma-buf/ include/linux/dma-resv.h include/linux/ include/kcl/reservation.h include/linux/ diff --git a/include/drm/amd_rdma.h b/include/drm/amd_rdma.h new file mode 100644 index 0000000000000..99682afae6754 --- /dev/null +++ b/include/drm/amd_rdma.h @@ -0,0 +1,78 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* + * Copyright 2015-2021 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/* @file This file defined kernel interfaces to communicate with amdkfd */ + +#ifndef AMD_RDMA_H_ +#define AMD_RDMA_H_ + +/* API versions: + * 1.0 Original API until ROCm 4.1, AMD_RDMA_MAJOR/MINOR undefined + * 2.0 Added IOMMU (dma-mapping) support, removed p2p_info.kfd_proc + * Introduced AMD_RDMA_MAJOR/MINOR version definition + */ +#define AMD_RDMA_MAJOR 2 +#define AMD_RDMA_MINOR 0 + +/** + * Structure describing information needed to P2P access from another device + * to specific location of GPU memory + */ +struct amd_p2p_info { + uint64_t va; /**< Specify user virt. address + * which this page table + * described + */ + uint64_t size; /**< Specify total size of + * allocation + */ + struct pid *pid; /**< Specify process pid to which + * virtual address belongs + */ + struct sg_table *pages; /**< Specify DMA/Bus addresses */ + void *priv; /**< Pointer set by AMD kernel + * driver + */ +}; + +/** + * Structure providing function pointers to support rdma/p2p requirements. + * to specific location of GPU memory + */ +struct amd_rdma_interface { + int (*get_pages)(uint64_t address, uint64_t length, struct pid *pid, + struct device *dma_dev, + struct amd_p2p_info **amd_p2p_data, + void (*free_callback)(void *client_priv), + void *client_priv); + int (*put_pages)(struct amd_p2p_info **amd_p2p_data); + int (*is_gpu_address)(uint64_t address, struct pid *pid); + int (*get_page_size)(uint64_t address, uint64_t length, struct pid *pid, + unsigned long *page_size); +}; + + +int amdkfd_query_rdma_interface(const struct amd_rdma_interface **rdma); + + +#endif /* AMD_RDMA_H_ */ From 277011e9ec999ca501d1c5c62ae08209689f22ac Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Thu, 23 Apr 2020 02:34:11 -0400 Subject: [PATCH 0191/1868] drm/amdkfd: Add module param to enable privileged queues This is useful for profiler prototyping in user mode. Change-Id: Ibb3dfedc698fadb5164637642bdd2d540cc00bd0 Signed-off-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 8 ++++++++ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c | 4 ++++ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 3 +++ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c | 4 +++- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 5 +++++ 5 files changed, 23 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 4f421fb94c616..30e0a6ccb9448 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -835,6 +835,14 @@ MODULE_PARM_DESC(no_system_mem_limit, "disable system memory limit (false = defa int amdgpu_no_queue_eviction_on_vm_fault; MODULE_PARM_DESC(no_queue_eviction_on_vm_fault, "No queue eviction on VM fault (0 = queue eviction, 1 = no queue eviction)"); module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm_fault, int, 0444); + +/** + * DOC: priv_cp_queues (int) + * Enable privileged mode for CP queues. Default value: 0 (off) + */ +int priv_cp_queues; +module_param(priv_cp_queues, int, 0644); +MODULE_PARM_DESC(priv_cp_queues, "Enable privileged mode for CP queues (0 = off (default), 1 = on)"); #endif /** diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c index 05f3ac2eaef9e..457e8fdc46418 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c @@ -31,6 +31,7 @@ #include "cik_regs.h" #include "cik_structs.h" #include "oss/oss_2_4_sh_mask.h" +#include "gca/gfx_7_2_sh_mask.h" static inline struct cik_mqd *get_mqd(void *mqd) { @@ -199,6 +200,9 @@ static void __update_mqd(struct mqd_manager *mm, void *mqd, if (q->format == KFD_QUEUE_FORMAT_AQL) m->cp_hqd_pq_control |= NO_UPDATE_RPTR; + if (priv_cp_queues) + m->cp_hqd_pq_control |= + 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT; update_cu_mask(mm, mqd, minfo); set_priority(m, q); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c index 84e8ea3a8a0c9..c3716d8efc7b0 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c @@ -297,6 +297,9 @@ static void update_mqd(struct mqd_manager *mm, void *mqd, m->cp_hqd_pq_doorbell_control |= 1 << CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_BIF_DROP__SHIFT; } + if (priv_cp_queues) + m->cp_hqd_pq_control |= + 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT; if (mm->dev->kfd->cwsr_enabled && q->ctx_save_restore_area_address) m->cp_hqd_ctx_save_control = 0; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c index c1fafc5025158..55387793985f3 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c @@ -225,7 +225,9 @@ static void __update_mqd(struct mqd_manager *mm, void *mqd, m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK | 2 << CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT; } - + if (priv_cp_queues) + m->cp_hqd_pq_control |= + 1 << CP_HQD_PQ_CONTROL__PRIV_STATE__SHIFT; if (mm->dev->kfd->cwsr_enabled && q->ctx_save_restore_area_address) m->cp_hqd_ctx_save_control = atc_bit << CP_HQD_CTX_SAVE_CONTROL__ATC__SHIFT | diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index c695d7ffa42ef..28383360dc4ba 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -181,6 +181,11 @@ extern int debug_largebar; /* Set sh_mem_config.retry_disable on GFX v9 */ extern int amdgpu_noretry; +/* + * Enable privileged mode for all CP queues including user queues + */ +extern int priv_cp_queues; + /* Halt if HWS hang is detected */ extern int halt_if_hws_hang; From 0b53a2107a2b8764ec62b1e51fa9f30b42784e08 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Thu, 23 Apr 2020 02:48:26 -0400 Subject: [PATCH 0192/1868] drm/amdkfd: Leave idle processes evicted This feature allows leaving processes with idle user mode queues evicted. That way more memory can be used by other processes. This is contolled by a module parameter. It's disabled by default. It needs more rigorous testing before enabling it by default. See FIXMEs below. The basic idea is to detect idle user mode queues when a process is restored after eviction. It it's found to be idle, we unmap the doorbells so the next submission from the host causes a page fault. We catch the page fault and use that to restore the process memory and the doorbells at that time. FIXME: Add check_queue_idle functions in kfd_mqd_manager_v10.c FIXME: Use READ_ONCE/WRITE_ONCE for vma->vm_private_data Change-Id: I03969b82f8fa31ac0e8593f537cc5c45ff8bc16e Signed-off-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 8 + .../drm/amd/amdkfd/kfd_device_queue_manager.c | 25 +++ .../drm/amd/amdkfd/kfd_device_queue_manager.h | 2 + drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c | 145 +++++++++++++++++- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h | 3 +- .../gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c | 28 ++++ .../gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 47 ++++++ .../gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c | 43 ++++++ drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 22 +++ drivers/gpu/drm/amd/amdkfd/kfd_process.c | 93 +++++++++++ 10 files changed, 411 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 30e0a6ccb9448..9fb830208ce31 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -843,6 +843,14 @@ module_param_named(no_queue_eviction_on_vm_fault, amdgpu_no_queue_eviction_on_vm int priv_cp_queues; module_param(priv_cp_queues, int, 0644); MODULE_PARM_DESC(priv_cp_queues, "Enable privileged mode for CP queues (0 = off (default), 1 = on)"); + +/** + * DOC: keep_idle_process_evicted (bool) + * Keep an evicted process evicted if it is idle. Default value: false (off) + */ +bool keep_idle_process_evicted; +module_param(keep_idle_process_evicted, bool, 0444); +MODULE_PARM_DESC(keep_idle_process_evicted, "Restore evicted process only if queues are active (N = off(default), Y = on)"); #endif /** diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index 5e95b03bb56d3..2862eb6753f43 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -152,6 +152,31 @@ void program_sh_mem_settings(struct device_queue_manager *dqm, qpd->sh_mem_bases, xcc_id); } +bool check_if_queues_active(struct device_queue_manager *dqm, + struct qcm_process_device *qpd) +{ + bool busy = false; + struct queue *q; + + dqm_lock(dqm); + list_for_each_entry(q, &qpd->queues_list, list) { + struct mqd_manager *mqd_mgr; + enum KFD_MQD_TYPE type; + + type = get_mqd_type_from_queue_type(q->properties.type); + mqd_mgr = dqm->mqd_mgrs[type]; + if (!mqd_mgr || !mqd_mgr->check_queue_active) + continue; + + busy = mqd_mgr->check_queue_active(q); + if (busy) + break; + } + dqm_unlock(dqm); + + return busy; +} + static void kfd_hws_hang(struct device_queue_manager *dqm) { struct device_process_node *cur; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h index dfb36a2466370..e570abecb337a 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h @@ -297,6 +297,8 @@ unsigned int get_queues_per_pipe(struct device_queue_manager *dqm); unsigned int get_pipes_per_mec(struct device_queue_manager *dqm); unsigned int get_num_sdma_queues(struct device_queue_manager *dqm); unsigned int get_num_xgmi_sdma_queues(struct device_queue_manager *dqm); +bool check_if_queues_active(struct device_queue_manager *dqm, + struct qcm_process_device *qpd); int reserve_debug_trap_vmid(struct device_queue_manager *dqm, struct qcm_process_device *qpd); int release_debug_trap_vmid(struct device_queue_manager *dqm, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c b/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c index 05c74887fd6fd..cc97f392c90af 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c @@ -103,11 +103,121 @@ void kfd_doorbell_fini(struct kfd_dev *kfd) (void **)&kfd->doorbell_kernel_ptr); } +static void kfd_doorbell_open(struct vm_area_struct *vma) +{ + /* Don't track the parent's PDD in a child process. We do set + * VM_DONTCOPY, but that can be overridden from user mode. + */ + vma->vm_private_data = NULL; +} + +static void kfd_doorbell_close(struct vm_area_struct *vma) +{ + struct kfd_process_device *pdd = vma->vm_private_data; + + if (!pdd) + return; + + mutex_lock(&pdd->qpd.doorbell_lock); + pdd->qpd.doorbell_vma = NULL; + /* Remember if the process was evicted without doorbells + * mapped to user mode. + */ + if (pdd->qpd.doorbell_mapped == 0) + pdd->qpd.doorbell_mapped = -1; + mutex_unlock(&pdd->qpd.doorbell_lock); +} + +static vm_fault_t kfd_doorbell_vm_fault(struct vm_fault *vmf) +{ + struct kfd_process_device *pdd = vmf->vma->vm_private_data; + + if (!pdd) + return VM_FAULT_SIGBUS; + + pr_debug("Process %d doorbell vm page fault\n", pdd->process->pasid); + + kfd_process_remap_doorbells_locked(pdd->process); + + kfd_process_schedule_restore(pdd->process); + + return VM_FAULT_NOPAGE; +} + +static const struct vm_operations_struct kfd_doorbell_vm_ops = { + .open = kfd_doorbell_open, + .close = kfd_doorbell_close, + .fault = kfd_doorbell_vm_fault, +}; + +void kfd_doorbell_unmap_locked(struct kfd_process_device *pdd) +{ + struct kfd_process *process = pdd->process; + struct vm_area_struct *vma; + size_t size; + + vma = pdd->qpd.doorbell_vma; + /* Remember if the process was evicted without doorbells + * mapped to user mode. + */ + if (!vma) { + pdd->qpd.doorbell_mapped = -1; + return; + } + + pr_debug("Process %d unmapping doorbell 0x%lx\n", + process->pasid, vma->vm_start); + + size = kfd_doorbell_process_slice(pdd->dev); + zap_vma_ptes(vma, vma->vm_start, size); + pdd->qpd.doorbell_mapped = 0; +} + +void kfd_doorbell_unmap(struct kfd_process_device *pdd) +{ + mutex_lock(&pdd->qpd.doorbell_lock); + kfd_doorbell_unmap_locked(pdd); + mutex_unlock(&pdd->qpd.doorbell_lock); +} + +int kfd_doorbell_remap(struct kfd_process_device *pdd) +{ + struct kfd_process *process = pdd->process; + phys_addr_t address; + struct vm_area_struct *vma; + size_t size; + int ret = 0; + + mutex_lock(&pdd->qpd.doorbell_lock); + if (pdd->qpd.doorbell_mapped != 0) + goto out_unlock; + + /* Calculate physical address of doorbell */ + address = kfd_get_process_doorbells(pdd); + vma = pdd->qpd.doorbell_vma; + size = kfd_doorbell_process_slice(pdd->dev); + + pr_debug("Process %d remap doorbell 0x%lx\n", process->pasid, + vma->vm_start); + + ret = vm_iomap_memory(vma, address, size); + if (ret) + pr_err("Process %d failed to remap doorbell 0x%lx\n", + process->pasid, vma->vm_start); + +out_unlock: + pdd->qpd.doorbell_mapped = 1; + mutex_unlock(&pdd->qpd.doorbell_lock); + + return ret; +} + int kfd_doorbell_mmap(struct kfd_node *dev, struct kfd_process *process, struct vm_area_struct *vma) { phys_addr_t address; struct kfd_process_device *pdd; + int ret; /* * For simplicitly we only allow mapping of the entire doorbell @@ -129,20 +239,47 @@ int kfd_doorbell_mmap(struct kfd_node *dev, struct kfd_process *process, vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); - pr_debug("Mapping doorbell page\n" + pr_debug("Process %d mapping doorbell page\n" " target user address == 0x%08llX\n" " physical address == 0x%08llX\n" " vm_flags == 0x%04lX\n" " size == 0x%04lX\n", - (unsigned long long) vma->vm_start, address, vma->vm_flags, - kfd_doorbell_process_slice(dev->kfd)); + process->pasid, (unsigned long long) vma->vm_start, + address, vma->vm_flags, kfd_doorbell_process_slice(dev)); + pdd = kfd_get_process_device_data(dev, process); + if (WARN_ON_ONCE(!pdd)) + return 0; - return io_remap_pfn_range(vma, + mutex_lock(&pdd->qpd.doorbell_lock); + + ret = io_remap_pfn_range(vma, vma->vm_start, address >> PAGE_SHIFT, kfd_doorbell_process_slice(dev->kfd), vma->vm_page_prot); + + if (!ret && keep_idle_process_evicted) { + vma->vm_ops = &kfd_doorbell_vm_ops; + vma->vm_private_data = pdd; + pdd->qpd.doorbell_vma = vma; + + /* If process is evicted before the first queue is created, + * process will be restored by the page fault when the + * doorbell is accessed the first time + */ + if (pdd->qpd.doorbell_mapped == -1) { + pr_debug("Process %d evicted, unmapping doorbell\n", + process->pasid); + kfd_doorbell_unmap_locked(pdd); + } else { + pdd->qpd.doorbell_mapped = 1; + } + } + + mutex_unlock(&pdd->qpd.doorbell_lock); + + return ret; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h index 17cc1f25c8d08..876cc71473293 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager.h @@ -102,6 +102,8 @@ struct mqd_manager { u32 *ctl_stack_used_size, u32 *save_area_used_size); + bool (*check_queue_active)(struct queue *q); + void (*get_checkpoint_info)(struct mqd_manager *mm, void *mqd, uint32_t *ctl_stack_size); void (*checkpoint_mqd)(struct mqd_manager *mm, @@ -115,7 +117,6 @@ struct mqd_manager { const void *mqd_src, const void *ctl_stack_src, const u32 ctl_stack_size); - #if defined(CONFIG_DEBUG_FS) int (*debugfs_show_mqd)(struct seq_file *m, void *data); #endif diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c index 457e8fdc46418..64adbde8648af 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_cik.c @@ -43,6 +43,31 @@ static inline struct cik_sdma_rlc_registers *get_sdma_mqd(void *mqd) return (struct cik_sdma_rlc_registers *)mqd; } +static bool check_sdma_queue_active(struct queue *q) +{ + uint32_t rptr, wptr; + struct cik_sdma_rlc_registers *m = get_sdma_mqd(q->mqd); + + rptr = m->sdma_rlc_rb_rptr; + wptr = m->sdma_rlc_rb_wptr; + pr_debug("rptr=%d, wptr=%d\n", rptr, wptr); + + return (rptr != wptr); +} + +static bool check_queue_active(struct queue *q) +{ + uint32_t rptr, wptr; + struct cik_mqd *m = get_mqd(q->mqd); + + rptr = m->cp_hqd_pq_rptr; + wptr = m->cp_hqd_pq_wptr; + + pr_debug("rptr=%d, wptr=%d\n", rptr, wptr); + + return (rptr != wptr); +} + static void update_cu_mask(struct mqd_manager *mm, void *mqd, struct mqd_update_info *minfo) { @@ -407,6 +432,7 @@ struct mqd_manager *mqd_manager_init_cik(enum KFD_MQD_TYPE type, mqd->update_mqd = update_mqd; mqd->destroy_mqd = kfd_destroy_mqd_cp; mqd->is_occupied = kfd_is_occupied_cp; + mqd->check_queue_active = check_queue_active; mqd->checkpoint_mqd = checkpoint_mqd; mqd->restore_mqd = restore_mqd; mqd->mqd_size = sizeof(struct cik_mqd); @@ -422,6 +448,7 @@ struct mqd_manager *mqd_manager_init_cik(enum KFD_MQD_TYPE type, mqd->update_mqd = update_mqd_hiq; mqd->destroy_mqd = kfd_destroy_mqd_cp; mqd->is_occupied = kfd_is_occupied_cp; + mqd->check_queue_active = check_queue_active; mqd->mqd_size = sizeof(struct cik_mqd); mqd->mqd_stride = kfd_mqd_stride; #if defined(CONFIG_DEBUG_FS) @@ -451,6 +478,7 @@ struct mqd_manager *mqd_manager_init_cik(enum KFD_MQD_TYPE type, mqd->update_mqd = update_mqd_sdma; mqd->destroy_mqd = kfd_destroy_mqd_sdma; mqd->is_occupied = kfd_is_occupied_sdma; + mqd->check_queue_active = check_sdma_queue_active; mqd->checkpoint_mqd = checkpoint_mqd_sdma; mqd->restore_mqd = restore_mqd_sdma; mqd->mqd_size = sizeof(struct cik_sdma_rlc_registers); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c index c3716d8efc7b0..bfd2867b7ef49 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c @@ -59,6 +59,49 @@ static inline struct v9_sdma_mqd *get_sdma_mqd(void *mqd) return (struct v9_sdma_mqd *)mqd; } +static bool check_sdma_queue_active(struct queue *q) +{ + uint32_t rptr, wptr; + uint32_t rptr_hi, wptr_hi; + struct v9_sdma_mqd *m = get_sdma_mqd(q->mqd); + + rptr = m->sdmax_rlcx_rb_rptr; + wptr = m->sdmax_rlcx_rb_wptr; + rptr_hi = m->sdmax_rlcx_rb_rptr_hi; + wptr_hi = m->sdmax_rlcx_rb_wptr_hi; + pr_debug("rptr=%d, wptr=%d\n", rptr, wptr); + pr_debug("rptr_hi=%d, wptr_hi=%d\n", rptr_hi, wptr_hi); + + return (rptr != wptr || rptr_hi != wptr_hi); +} + +static bool check_queue_active(struct queue *q) +{ + uint32_t rptr, wptr; + uint32_t cntl_stack_offset, cntl_stack_size; + struct v9_mqd *m = get_mqd(q->mqd); + + rptr = m->cp_hqd_pq_rptr; + wptr = m->cp_hqd_pq_wptr_lo % q->properties.queue_size; + cntl_stack_offset = m->cp_hqd_cntl_stack_offset; + cntl_stack_size = m->cp_hqd_cntl_stack_size; + + pr_debug("rptr=%d, wptr=%d\n", rptr, wptr); + pr_debug("m->cp_hqd_cntl_stack_offset=0x%08x\n", cntl_stack_offset); + pr_debug("m->cp_hqd_cntl_stack_size=0x%08x\n", cntl_stack_size); + + if ((rptr == 0 && wptr == 0) || + cntl_stack_offset == 0xffffffff || + cntl_stack_size > 0x5000) + return false; + + /* Process is idle if both conditions are meet: + * queue's rptr equals to wptr + * control stack is empty, cntl_stack_offset = cntl_stack_size + */ + return (rptr != wptr || cntl_stack_offset != cntl_stack_size); +} + static void update_cu_mask(struct mqd_manager *mm, void *mqd, struct mqd_update_info *minfo, uint32_t inst) { @@ -879,6 +922,7 @@ struct mqd_manager *mqd_manager_init_v9(enum KFD_MQD_TYPE type, mqd->allocate_mqd = allocate_mqd; mqd->free_mqd = kfd_free_mqd_cp; mqd->is_occupied = kfd_is_occupied_cp; + mqd->check_queue_active = check_queue_active; mqd->get_checkpoint_info = get_checkpoint_info; mqd->checkpoint_mqd = checkpoint_mqd; mqd->restore_mqd = restore_mqd; @@ -907,6 +951,7 @@ struct mqd_manager *mqd_manager_init_v9(enum KFD_MQD_TYPE type, mqd->free_mqd = free_mqd_hiq_sdma; mqd->update_mqd = update_mqd; mqd->is_occupied = kfd_is_occupied_cp; + mqd->check_queue_active = check_queue_active; mqd->mqd_size = sizeof(struct v9_mqd); mqd->mqd_stride = kfd_mqd_stride; #if defined(CONFIG_DEBUG_FS) @@ -933,6 +978,7 @@ struct mqd_manager *mqd_manager_init_v9(enum KFD_MQD_TYPE type, mqd->update_mqd = update_mqd; mqd->destroy_mqd = kfd_destroy_mqd_cp; mqd->is_occupied = kfd_is_occupied_cp; + mqd->check_queue_active = check_queue_active; mqd->mqd_size = sizeof(struct v9_mqd); #if defined(CONFIG_DEBUG_FS) mqd->debugfs_show_mqd = debugfs_show_mqd; @@ -946,6 +992,7 @@ struct mqd_manager *mqd_manager_init_v9(enum KFD_MQD_TYPE type, mqd->update_mqd = update_mqd_sdma; mqd->destroy_mqd = kfd_destroy_mqd_sdma; mqd->is_occupied = kfd_is_occupied_sdma; + mqd->check_queue_active = check_sdma_queue_active; mqd->checkpoint_mqd = checkpoint_mqd_sdma; mqd->restore_mqd = restore_mqd_sdma; mqd->mqd_size = sizeof(struct v9_sdma_mqd); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c index 55387793985f3..23669e908d504 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_vi.c @@ -45,6 +45,45 @@ static inline struct vi_sdma_mqd *get_sdma_mqd(void *mqd) return (struct vi_sdma_mqd *)mqd; } +static bool check_sdma_queue_active(struct queue *q) +{ + uint32_t rptr, wptr; + struct vi_sdma_mqd *m = get_sdma_mqd(q->mqd); + + rptr = m->sdmax_rlcx_rb_rptr; + wptr = m->sdmax_rlcx_rb_wptr; + pr_debug("rptr=%d, wptr=%d\n", rptr, wptr); + + return (rptr != wptr); +} + +static bool check_queue_active(struct queue *q) +{ + uint32_t rptr, wptr; + uint32_t cntl_stack_offset, cntl_stack_size; + struct vi_mqd *m = get_mqd(q->mqd); + + rptr = m->cp_hqd_pq_rptr; + wptr = m->cp_hqd_pq_wptr; + cntl_stack_offset = m->cp_hqd_cntl_stack_offset; + cntl_stack_size = m->cp_hqd_cntl_stack_size; + + pr_debug("rptr=%d, wptr=%d\n", rptr, wptr); + pr_debug("m->cp_hqd_cntl_stack_offset=0x%08x\n", cntl_stack_offset); + pr_debug("m->cp_hqd_cntl_stack_size=0x%08x\n", cntl_stack_size); + + if ((rptr == 0 && wptr == 0) || + cntl_stack_offset == 0xffffffff || + cntl_stack_size > 0x5000) + return false; + + /* Process is idle if both conditions are meet: + * queue's rptr equals to wptr + * control stack is empty, cntl_stack_offset = cntl_stack_size + */ + return (rptr != wptr || cntl_stack_offset != cntl_stack_size); +} + static void update_cu_mask(struct mqd_manager *mm, void *mqd, struct mqd_update_info *minfo) { @@ -463,6 +502,7 @@ struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type, mqd->destroy_mqd = kfd_destroy_mqd_cp; mqd->is_occupied = kfd_is_occupied_cp; mqd->get_wave_state = get_wave_state; + mqd->check_queue_active = check_queue_active; mqd->get_checkpoint_info = get_checkpoint_info; mqd->checkpoint_mqd = checkpoint_mqd; mqd->restore_mqd = restore_mqd; @@ -479,6 +519,7 @@ struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type, mqd->update_mqd = update_mqd_hiq; mqd->destroy_mqd = kfd_destroy_mqd_cp; mqd->is_occupied = kfd_is_occupied_cp; + mqd->check_queue_active = check_queue_active; mqd->mqd_size = sizeof(struct vi_mqd); mqd->mqd_stride = kfd_mqd_stride; #if defined(CONFIG_DEBUG_FS) @@ -494,6 +535,7 @@ struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type, mqd->update_mqd = update_mqd_hiq; mqd->destroy_mqd = kfd_destroy_mqd_cp; mqd->is_occupied = kfd_is_occupied_cp; + mqd->check_queue_active = check_queue_active; mqd->mqd_size = sizeof(struct vi_mqd); mqd->mqd_stride = kfd_mqd_stride; #if defined(CONFIG_DEBUG_FS) @@ -508,6 +550,7 @@ struct mqd_manager *mqd_manager_init_vi(enum KFD_MQD_TYPE type, mqd->update_mqd = update_mqd_sdma; mqd->destroy_mqd = kfd_destroy_mqd_sdma; mqd->is_occupied = kfd_is_occupied_sdma; + mqd->check_queue_active = check_sdma_queue_active; mqd->checkpoint_mqd = checkpoint_mqd_sdma; mqd->restore_mqd = restore_mqd_sdma; mqd->mqd_size = sizeof(struct vi_sdma_mqd); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 28383360dc4ba..a1410128da7bf 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -200,6 +200,11 @@ extern int queue_preemption_timeout_ms; */ extern int amdgpu_no_queue_eviction_on_vm_fault; +/* + * Restore evicted process only if queues are active + */ +extern bool keep_idle_process_evicted; + /* Enable eviction debug messages */ extern bool debug_evictions; @@ -723,6 +728,17 @@ struct qcm_process_device { /* bitmap for dynamic doorbell allocation from the bo */ unsigned long *doorbell_bitmap; + /* doorbell user mmap vma */ + struct vm_area_struct *doorbell_vma; + /* lock to serialize doorbell unmap and remap */ + struct mutex doorbell_lock; + + /* Indicate if doorbell is mapped or unmapped + * -1 means doorbells need to be unmapped because queue is evicted + * 0 means doorbells are unmapped + * 1 means doorbells are mapped + */ + int doorbell_mapped; }; /* KFD Memory Eviction */ @@ -734,6 +750,9 @@ struct qcm_process_device { /* Approx. time before evicting the process again */ #define PROCESS_ACTIVE_TIME_MS 10 +void kfd_process_schedule_restore(struct kfd_process *p); +int kfd_process_remap_doorbells_locked(struct kfd_process *p); + /* 8 byte handle containing GPU ID in the most significant 4 bytes and * idr_handle in the least significant 4 bytes */ @@ -964,6 +983,7 @@ struct kfd_process { * restored after an eviction */ unsigned long last_restore_timestamp; + unsigned long last_evict_timestamp; /* Indicates device process is debug attached with reserved vmid. */ bool debug_trap_enabled; @@ -1127,6 +1147,8 @@ int kfd_doorbell_init(struct kfd_dev *kfd); void kfd_doorbell_fini(struct kfd_dev *kfd); int kfd_doorbell_mmap(struct kfd_node *dev, struct kfd_process *process, struct vm_area_struct *vma); +void kfd_doorbell_unmap(struct kfd_process_device *pdd); +int kfd_doorbell_remap(struct kfd_process_device *pdd); void __iomem *kfd_get_kernel_doorbell(struct kfd_dev *kfd, unsigned int *doorbell_off); void kfd_release_kernel_doorbell(struct kfd_dev *kfd, u32 __iomem *db_addr); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 315d68b73585d..59e32b16aa11a 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -1047,6 +1047,7 @@ static void kfd_process_destroy_pdds(struct kfd_process *p) get_order(KFD_CWSR_TBA_TMA_SIZE)); idr_destroy(&pdd->alloc_idr); + mutex_destroy(&pdd->qpd.doorbell_lock); kfd_free_process_doorbells(pdd->dev->kfd, pdd); @@ -1603,6 +1604,7 @@ struct kfd_process_device *kfd_create_process_device_data(struct kfd_node *dev, pdd->qpd.pqm = &p->pqm; pdd->qpd.evicted = 0; pdd->qpd.mapped_gws_queue = false; + mutex_init(&pdd->qpd.doorbell_lock); pdd->process = p; pdd->bound = PDD_UNBOUND; pdd->already_dequeued = false; @@ -2035,6 +2037,95 @@ static int signal_eviction_fence(struct kfd_process *p) return ret; } +void kfd_process_schedule_restore(struct kfd_process *p) +{ + int ret; + unsigned long evicted_jiffies; + unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_RESTORE_TIME_MS); + + /* wait at least PROCESS_RESTORE_TIME_MS before attempting to restore + */ + evicted_jiffies = get_jiffies_64() - p->last_evict_timestamp; + if (delay_jiffies > evicted_jiffies) + delay_jiffies -= evicted_jiffies; + else + delay_jiffies = 0; + + pr_debug("Process %d schedule restore work\n", p->pasid); + ret = queue_delayed_work(kfd_restore_wq, &p->restore_work, + delay_jiffies); + WARN(!ret, "Schedule restore work failed\n"); +} + +static void kfd_process_unmap_doorbells(struct kfd_process *p) +{ + struct kfd_process_device *pdd; + struct mm_struct *mm = p->mm; + + mmap_write_lock(mm); + + list_for_each_entry(pdd, &p->per_device_data, per_device_list) + kfd_doorbell_unmap(pdd); + + mmap_write_unlock(mm); +} + +int kfd_process_remap_doorbells_locked(struct kfd_process *p) +{ + struct kfd_process_device *pdd; + int ret = 0; + + list_for_each_entry(pdd, &p->per_device_data, per_device_list) + ret = kfd_doorbell_remap(pdd); + + return ret; +} + +static int kfd_process_remap_doorbells(struct kfd_process *p) +{ + struct mm_struct *mm = p->mm; + int ret = 0; + + mmap_write_lock(mm); + ret = kfd_process_remap_doorbells_locked(p); + mmap_write_unlock(mm); + + return ret; +} + +/** + * kfd_process_unmap_doorbells_if_idle - Check if queues are active + * + * Returns true if queues are idle, and unmap doorbells. + * Returns false if queues are active + */ +static bool kfd_process_unmap_doorbells_if_idle(struct kfd_process *p) +{ + struct kfd_process_device *pdd; + bool busy = false; + + if (!keep_idle_process_evicted) + return false; + + /* Unmap doorbell first to avoid race conditions. Otherwise while the + * second queue is checked, the first queue may get more work, but we + * won't detect that since it has been checked + */ + kfd_process_unmap_doorbells(p); + + list_for_each_entry(pdd, &p->per_device_data, per_device_list) { + busy = check_if_queues_active(pdd->qpd.dqm, &pdd->qpd); + if (busy) + break; + } + + /* Remap doorbell if process queue is not idle */ + if (busy) + kfd_process_remap_doorbells(p); + + return !busy; +} + static void evict_process_worker(struct work_struct *work) { int ret; @@ -2048,6 +2139,8 @@ static void evict_process_worker(struct work_struct *work) */ p = container_of(dwork, struct kfd_process, eviction_work); + p->last_evict_timestamp = get_jiffies_64(); + pr_debug("Started evicting pasid 0x%x\n", p->pasid); ret = kfd_process_evict_queues(p, KFD_QUEUE_EVICTION_TRIGGER_TTM); if (!ret) { From 5f1b4cc6b28767ebae27552994d26c8101d3d65b Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Thu, 23 Apr 2020 03:06:45 -0400 Subject: [PATCH 0193/1868] drm/amdgpu: Workaround incorrect VRAM width reported on Fiji Signed-off-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 5 +++++ include/uapi/drm/amdgpu_drm.h | 2 ++ 2 files changed, 7 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index 86488c052f822..380a6b5f8bdbb 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -544,6 +544,11 @@ static int gmc_v8_0_mc_init(struct amdgpu_device *adev) break; } adev->gmc.vram_width = numchan * chansize; + /* FIXME: The above calculation is outdated. + * For HBM provide a temporary fix + */ + if (adev->gmc.vram_type == AMDGPU_VRAM_TYPE_HBM) + adev->gmc.vram_width = AMDGPU_VRAM_TYPE_HBM_WIDTH; } /* size in MB on si */ tmp = RREG32(mmCONFIG_MEMSIZE); diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index d1f7ba9b31300..8376066a24e4b 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -1162,6 +1162,8 @@ struct drm_amdgpu_info_vbios { #define AMDGPU_VRAM_TYPE_LPDDR4 11 #define AMDGPU_VRAM_TYPE_LPDDR5 12 +#define AMDGPU_VRAM_TYPE_HBM_WIDTH 4096 + struct drm_amdgpu_info_device { /** PCI Device ID */ __u32 device_id; From e5abf16443ffd38d17ba3379b5e65e7b9c3ef503 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Thu, 23 Apr 2020 03:14:27 -0400 Subject: [PATCH 0194/1868] drm/amdkfd: Proof of concept for KFD traces Add tracing to a few KFD functions as a proof of concept. Signed-off-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/Makefile | 1 + drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 7 ++ drivers/gpu/drm/amd/amdkfd/kfd_process.c | 10 ++ drivers/gpu/drm/amd/amdkfd/kfd_trace.c | 26 ++++ drivers/gpu/drm/amd/amdkfd/kfd_trace.h | 151 +++++++++++++++++++++++ 5 files changed, 195 insertions(+) create mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_trace.c create mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_trace.h diff --git a/drivers/gpu/drm/amd/amdkfd/Makefile b/drivers/gpu/drm/amd/amdkfd/Makefile index 188b500900dac..40dae27e387cd 100644 --- a/drivers/gpu/drm/amd/amdkfd/Makefile +++ b/drivers/gpu/drm/amd/amdkfd/Makefile @@ -61,6 +61,7 @@ AMDKFD_FILES := $(AMDKFD_PATH)/kfd_module.o \ $(AMDKFD_PATH)/kfd_crat.o \ $(AMDKFD_PATH)/kfd_peerdirect.o \ $(AMDKFD_PATH)/kfd_ipc.o \ + $(AMDKFD_PATH)/kfd_trace.o \ $(AMDKFD_PATH)/kfd_debug.o ifneq ($(CONFIG_DEBUG_FS),) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 717891582ea8d..23bd15ee785d3 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -42,6 +42,8 @@ #include "kfd_device_queue_manager.h" #include "kfd_svm.h" #include "kfd_ipc.h" +#include "kfd_trace.h" + #include "amdgpu_amdkfd.h" #include "kfd_smi_events.h" #include "amdgpu_dma_buf.h" @@ -1249,6 +1251,7 @@ static int kfd_ioctl_map_memory_to_gpu(struct file *filep, int i; uint32_t *devices_arr = NULL; + trace_kfd_map_memory_to_gpu_start(p); if (!args->n_devices) { pr_debug("Device IDs array empty\n"); return -EINVAL; @@ -1342,6 +1345,8 @@ static int kfd_ioctl_map_memory_to_gpu(struct file *filep, } kfree(devices_arr); + trace_kfd_map_memory_to_gpu_end(p, + args->n_devices * sizeof(*devices_arr), "Success"); return err; get_process_device_data_failed: @@ -1352,6 +1357,8 @@ static int kfd_ioctl_map_memory_to_gpu(struct file *filep, mutex_unlock(&p->mutex); copy_from_user_failed: kfree(devices_arr); + trace_kfd_map_memory_to_gpu_end(p, + args->n_devices * sizeof(*devices_arr), "Failed"); return err; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 59e32b16aa11a..ba18dc80decfc 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -42,6 +42,7 @@ struct mm_struct; #include "kfd_priv.h" #include "kfd_device_queue_manager.h" #include "kfd_svm.h" +#include "kfd_trace.h" #include "kfd_smi_events.h" #include "kfd_debug.h" @@ -2138,6 +2139,7 @@ static void evict_process_worker(struct work_struct *work) * lifetime of this thread, kfd_process p will be valid */ p = container_of(dwork, struct kfd_process, eviction_work); + trace_kfd_evict_process_worker_start(p); p->last_evict_timestamp = get_jiffies_64(); @@ -2156,6 +2158,7 @@ static void evict_process_worker(struct work_struct *work) pr_debug("Finished evicting pasid 0x%x\n", p->pasid); } else pr_err("Failed to evict queues of pasid 0x%x\n", p->pasid); + trace_kfd_evict_process_worker_end(p, ret ? "Failed" : "Success"); } static int restore_process_helper(struct kfd_process *p) @@ -2171,6 +2174,7 @@ static int restore_process_helper(struct kfd_process *p) } ret = kfd_process_restore_queues(p); + trace_kfd_restore_process_worker_end(p, ret ? "Failed" : "Success"); if (!ret) pr_debug("Finished restoring pasid 0x%x\n", p->pasid); else @@ -2192,6 +2196,7 @@ static void restore_process_worker(struct work_struct *work) */ p = container_of(dwork, struct kfd_process, restore_work); pr_debug("Started restoring pasid 0x%x\n", p->pasid); + trace_kfd_restore_process_worker_start(p); /* Setting last_restore_timestamp before successful restoration. * Otherwise this would have to be set by KGD (restore_process_bos) @@ -2212,6 +2217,11 @@ static void restore_process_worker(struct work_struct *work) if (mod_delayed_work(kfd_restore_wq, &p->restore_work, msecs_to_jiffies(PROCESS_RESTORE_TIME_MS))) kfd_process_restore_queues(p); + trace_kfd_restore_process_worker_end(p, ret ? + "Rescheduled restore" : + "Failed to reschedule restore"); + } else { + trace_kfd_restore_process_worker_end(p, "Success"); } } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_trace.c b/drivers/gpu/drm/amd/amdkfd/kfd_trace.c new file mode 100644 index 0000000000000..805a1da90bb15 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkfd/kfd_trace.c @@ -0,0 +1,26 @@ +/* + * Copyright 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + + +#define CREATE_TRACE_POINTS +#include "kfd_trace.h" diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_trace.h b/drivers/gpu/drm/amd/amdkfd/kfd_trace.h new file mode 100644 index 0000000000000..5d27a98055377 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkfd/kfd_trace.h @@ -0,0 +1,151 @@ +/* + * Copyright 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#if !defined(_AMDKFD_TRACE_H) || defined(TRACE_HEADER_MULTI_READ) +#define _KFD_TRACE_H_ + + +#include +#include +#include + +#include "kfd_priv.h" +#include + +#undef TRACE_SYSTEM +#define TRACE_SYSTEM amdkfd +#define TRACE_INCLUDE_FILE kfd_trace + + +TRACE_EVENT(kfd_map_memory_to_gpu_start, + TP_PROTO(struct kfd_process *p), + TP_ARGS(p), + TP_STRUCT__entry( + __field(unsigned int, pasid) + ), + TP_fast_assign( + __entry->pasid = p->pasid; + ), + TP_printk("pasid =%u", __entry->pasid) +); + + +TRACE_EVENT(kfd_map_memory_to_gpu_end, + TP_PROTO(struct kfd_process *p, u32 array_size, char *pStatusMsg), + TP_ARGS(p, array_size, pStatusMsg), + TP_STRUCT__entry( + __field(unsigned int, pasid) + __field(unsigned int, array_size) + __string(pStatusMsg, pStatusMsg) + ), + TP_fast_assign( + __entry->pasid = p->pasid; + __entry->array_size = array_size; + __assign_str(pStatusMsg, pStatusMsg); + ), + TP_printk("pasid = %u, array_size = %u, StatusMsg=%s", + __entry->pasid, + __entry->array_size, + __get_str(pStatusMsg)) +); + + +TRACE_EVENT(kfd_kgd2kfd_schedule_evict_and_restore_process, + TP_PROTO(struct kfd_process *p, u32 delay_jiffies), + TP_ARGS(p, delay_jiffies), + TP_STRUCT__entry( + __field(unsigned int, pasid) + __field(unsigned int, delay_jiffies) + ), + TP_fast_assign( + __entry->pasid = p->pasid; + __entry->delay_jiffies = delay_jiffies; + ), + TP_printk("pasid = %u, delay_jiffies = %u", + __entry->pasid, + __entry->delay_jiffies) +); + + +TRACE_EVENT(kfd_evict_process_worker_start, + TP_PROTO(struct kfd_process *p), + TP_ARGS(p), + TP_STRUCT__entry( + __field(unsigned int, pasid) + ), + TP_fast_assign( + __entry->pasid = p->pasid; + ), + TP_printk("pasid=%u", __entry->pasid) +); + + +TRACE_EVENT(kfd_evict_process_worker_end, + TP_PROTO(struct kfd_process *p, char *pStatusMsg), + TP_ARGS(p, pStatusMsg), + TP_STRUCT__entry( + __field(unsigned int, pasid) + __string(pStatusMsg, pStatusMsg) + ), + TP_fast_assign( + __entry->pasid = p->pasid; + __assign_str(pStatusMsg, pStatusMsg); + ), + TP_printk("pasid=%u, StatusMsg=%s", + __entry->pasid, __get_str(pStatusMsg)) +); + + +TRACE_EVENT(kfd_restore_process_worker_start, + TP_PROTO(struct kfd_process *p), + TP_ARGS(p), + TP_STRUCT__entry( + __field(unsigned int, pasid) + ), + TP_fast_assign( + __entry->pasid = p->pasid; + ), + TP_printk("pasid=%u", __entry->pasid) +); + +TRACE_EVENT(kfd_restore_process_worker_end, + TP_PROTO(struct kfd_process *p, char *pStatusMsg), + TP_ARGS(p, pStatusMsg), + TP_STRUCT__entry( + __field(unsigned int, pasid) + __string(pStatusMsg, pStatusMsg) + ), + TP_fast_assign( + entry->pasid = p->pasid; + __assign_str(pStatusMsg, pStatusMsg); + ), + TP_printk("pasid=%u, StatusMsg=%s", + __entry->pasid, __get_str(pStatusMsg)) +); + +#endif + +/* This part must be outside protection */ +#undef TRACE_INCLUDE_PATH +#define TRACE_INCLUDE_PATH . +#include From 81cb5df59cd30a73477534a9fd66b736c25a6cd3 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Thu, 23 Apr 2020 03:53:39 -0400 Subject: [PATCH 0195/1868] drm/amdkfd: Mapping foreign device memory to GPUVM This adds the possibility to map foreign device memory as a userptr. This assumes that the foreign memory is pinned an cannot be evicted or migrated. This is generally true for doorbells. Signed-off-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 25 +++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 23bd15ee785d3..159d7c86da5b3 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1052,6 +1052,7 @@ static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep, long err; uint64_t offset = args->mmap_offset; uint32_t flags = args->flags; + struct vm_area_struct *vma; uint64_t cpuva = 0; unsigned int mem_type = 0; @@ -1112,7 +1113,29 @@ static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep, goto err_unlock; } - if (flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) { + if (flags & KFD_IOC_ALLOC_MEM_FLAGS_USERPTR) { + /* Check if the userptr corresponds to another (or third-party) + * device local memory. If so treat is as a doorbell. User + * space will be oblivious of this and will use this doorbell + * BO as a regular userptr BO + */ + vma = find_vma(current->mm, args->mmap_offset); + if (vma && (vma->vm_flags & VM_IO)) { + unsigned long pfn; + + follow_pfn(vma, args->mmap_offset, &pfn); + flags |= KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL; + flags &= ~KFD_IOC_ALLOC_MEM_FLAGS_USERPTR; + offset = (pfn << PAGE_SHIFT); + } else { + if (offset & (PAGE_SIZE - 1)) { + pr_debug("Unaligned userptr address:%llx\n", + offset); + return -EINVAL; + } + cpuva = offset; + } + } else if (flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) { if (args->size != kfd_doorbell_process_slice(dev->kfd)) { err = -EINVAL; goto err_unlock; From bd0a619e9b95ec7fdd8bc7c3f6bbc1b3a9394023 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Thu, 23 Apr 2020 04:00:12 -0400 Subject: [PATCH 0196/1868] drm/amdkfd: Experimental support for architectures w/o ACPI Signed-off-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c index cd7b81b7b939a..e391c7e4e49f4 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c @@ -1840,8 +1840,6 @@ static int kfd_fill_iolink_info_for_cpu(int numa_node_id, int *avail_size, static int kfd_create_vcrat_image_cpu(void *pcrat_image, size_t *size) { struct crat_header *crat_table = (struct crat_header *)pcrat_image; - struct acpi_table_header *acpi_table; - acpi_status status; struct crat_subtype_generic *sub_type_hdr; int avail_size = *size; int numa_node_id; @@ -1849,6 +1847,10 @@ static int kfd_create_vcrat_image_cpu(void *pcrat_image, size_t *size) uint32_t entries = 0; #endif int ret = 0; +#ifdef CONFIG_ACPI + struct acpi_table_header *acpi_table; + acpi_status status; +#endif if (!pcrat_image) return -EINVAL; @@ -1865,6 +1867,7 @@ static int kfd_create_vcrat_image_cpu(void *pcrat_image, size_t *size) sizeof(crat_table->signature)); crat_table->length = sizeof(struct crat_header); +#ifdef CONFIG_ACPI status = acpi_get_table("DSDT", 0, &acpi_table); if (status != AE_OK) pr_warn("DSDT table not found for OEM information\n"); @@ -1876,6 +1879,11 @@ static int kfd_create_vcrat_image_cpu(void *pcrat_image, size_t *size) CRAT_OEMTABLEID_LENGTH); acpi_put_table(acpi_table); } +#else + crat_table->oem_revision = 0; + memcpy(crat_table->oem_id, "INV", CRAT_OEMID_LENGTH); + memcpy(crat_table->oem_table_id, "UNAVAIL", CRAT_OEMTABLEID_LENGTH); +#endif crat_table->total_entries = 0; crat_table->num_domains = 0; From a34b4978fc1cabb7ca6ac94b3191c91529b49779 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Thu, 23 Apr 2020 04:03:23 -0400 Subject: [PATCH 0197/1868] drm/amdkfd: Make eviction messages noisier Use pr_info instead of pr_debug. This makes it easier to diagnose eviction problems and resulting performance degradation remotely. Signed-off-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index ba18dc80decfc..cf9c4b82761b3 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -2155,7 +2155,7 @@ static void evict_process_worker(struct work_struct *work) msecs_to_jiffies(PROCESS_RESTORE_TIME_MS))) kfd_process_restore_queues(p); - pr_debug("Finished evicting pasid 0x%x\n", p->pasid); + pr_info("Finished evicting pasid 0x%x\n", p->pasid); } else pr_err("Failed to evict queues of pasid 0x%x\n", p->pasid); trace_kfd_evict_process_worker_end(p, ret ? "Failed" : "Success"); @@ -2195,7 +2195,7 @@ static void restore_process_worker(struct work_struct *work) * lifetime of this thread, kfd_process p will be valid */ p = container_of(dwork, struct kfd_process, restore_work); - pr_debug("Started restoring pasid 0x%x\n", p->pasid); + pr_info("Started restoring pasid 0x%x\n", p->pasid); trace_kfd_restore_process_worker_start(p); /* Setting last_restore_timestamp before successful restoration. @@ -2212,7 +2212,7 @@ static void restore_process_worker(struct work_struct *work) ret = restore_process_helper(p); if (ret) { - pr_debug("Failed to restore BOs of pasid 0x%x, retry after %d ms\n", + pr_info("Failed to restore BOs of pasid 0x%x, retry after %d ms\n", p->pasid, PROCESS_BACK_OFF_TIME_MS); if (mod_delayed_work(kfd_restore_wq, &p->restore_work, msecs_to_jiffies(PROCESS_RESTORE_TIME_MS))) From 5fd0433ee5a1038ce7ae19ef7d96202ea46f8ded Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Thu, 23 Apr 2020 04:07:48 -0400 Subject: [PATCH 0198/1868] drm/amdkfd: Report used GPU memory This change has been rejected upstream. A better solution is needed. Used memory being dynamic doesn't belong in the topology tree, which contains otherwise static information. Signed-off-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 44 +++++++++++++++++++---- drivers/gpu/drm/amd/amdkfd/kfd_topology.h | 3 +- 2 files changed, 40 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index 3871591c9aec9..a5c8c761c6f9b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -224,6 +224,8 @@ struct kfd_topology_device *kfd_create_topology_device( sysfs_show_gen_prop(buffer, offs, "%s %llu\n", name, value) #define sysfs_show_32bit_val(buffer, offs, value) \ sysfs_show_gen_prop(buffer, offs, "%u\n", value) +#define sysfs_show_64bit_val(buffer, offs, value) \ + sysfs_show_gen_prop(buffer, offs, "%llu\n", value) #define sysfs_show_str_val(buffer, offs, value) \ sysfs_show_gen_prop(buffer, offs, "%s\n", value) @@ -313,11 +315,25 @@ static ssize_t mem_show(struct kobject *kobj, struct attribute *attr, { int offs = 0; struct kfd_mem_properties *mem; + uint64_t used_mem; /* Making sure that the buffer is an empty string */ buffer[0] = 0; - mem = container_of(attr, struct kfd_mem_properties, attr); + if (strcmp(attr->name, "used_memory") == 0) { + mem = container_of(attr, struct kfd_mem_properties, + attr_used); + if (mem->gpu) { + if (kfd_devcgroup_check_permission(mem->gpu)) + return -EPERM; + used_mem = amdgpu_amdkfd_get_vram_usage(mem->gpu->kgd); + return sysfs_show_64bit_val(buffer, offs, used_mem); + } + /* TODO: Report APU/CPU-allocated memory; For now return 0 */ + return 0; + } + + mem = container_of(attr, struct kfd_mem_properties, attr_props); if (mem->gpu && kfd_devcgroup_check_permission(mem->gpu)) return -EPERM; sysfs_show_32bit_prop(buffer, offs, "heap_type", mem->heap_type); @@ -614,7 +630,12 @@ static void kfd_remove_sysfs_node_entry(struct kfd_topology_device *dev) if (dev->kobj_mem) { list_for_each_entry(mem, &dev->mem_props, list) if (mem->kobj) { - kfd_remove_sysfs_file(mem->kobj, &mem->attr); + /* TODO: Remove when CPU/APU supported */ + if (dev->node_props.cpu_cores_count == 0) + sysfs_remove_file(mem->kobj, + &mem->attr_used); + kfd_remove_sysfs_file(mem->kobj, + &mem->attr_props); mem->kobj = NULL; } kobject_del(dev->kobj_mem); @@ -725,12 +746,23 @@ static int kfd_build_sysfs_node_entry(struct kfd_topology_device *dev, return ret; } - mem->attr.name = "properties"; - mem->attr.mode = KFD_SYSFS_FILE_MODE; - sysfs_attr_init(&mem->attr); - ret = sysfs_create_file(mem->kobj, &mem->attr); + mem->attr_props.name = "properties"; + mem->attr_props.mode = KFD_SYSFS_FILE_MODE; + sysfs_attr_init(&mem->attr_props); + ret = sysfs_create_file(mem->kobj, &mem->attr_props); if (ret < 0) return ret; + + /* TODO: Support APU/CPU memory usage */ + if (dev->node_props.cpu_cores_count == 0) { + mem->attr_used.name = "used_memory"; + mem->attr_used.mode = KFD_SYSFS_FILE_MODE; + sysfs_attr_init(&mem->attr_used); + ret = sysfs_create_file(mem->kobj, &mem->attr_used); + if (ret < 0) + return ret; + } + i++; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h index 155b5c410af16..22e4b2cca1fe4 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h @@ -90,7 +90,8 @@ struct kfd_mem_properties { uint32_t mem_clk_max; struct kfd_node *gpu; struct kobject *kobj; - struct attribute attr; + struct attribute attr_props; + struct attribute attr_used; }; #define CACHE_SIBLINGMAP_SIZE 128 From 8800513fb62a32f515c739848d989d380f57bb7c Mon Sep 17 00:00:00 2001 From: Arnd Bergmann Date: Wed, 2 Oct 2019 14:01:27 +0200 Subject: [PATCH 0199/1868] drm/amdgpu: work around llvm bug #42576 Code in the amdgpu driver triggers a bug when using clang to build an arm64 kernel: /tmp/sdma_v4_0-f95fd3.s: Assembler messages: /tmp/sdma_v4_0-f95fd3.s:44: Error: selected processor does not support `bfc w0,#1,#5' I expect this to be fixed in llvm soon, but we can also work around it by inserting a barrier() that prevents the optimization. Link: https://bugs.llvm.org/show_bug.cgi?id=42576 Signed-off-by: Arnd Bergmann Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index 23ef4eb36b407..2de5ebb7e00a7 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c @@ -1068,6 +1068,7 @@ static uint32_t sdma_v4_0_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl) /* Set ring buffer size in dwords */ uint32_t rb_bufsz = order_base_2(ring->ring_size / 4); + barrier(); /* work around https://bugs.llvm.org/show_bug.cgi?id=42576 */ rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); #ifdef __BIG_ENDIAN rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); From 463d856604e673fd505c7f206bfbe69ef6fdbaf4 Mon Sep 17 00:00:00 2001 From: changzhu Date: Fri, 12 Jul 2019 15:53:23 +0800 Subject: [PATCH 0200/1868] Revert "drm/amdgpu: don't invalidate caches in RELEASE_MEM, only do the writeback" Signed-off-by: changzhu --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 75a6ca6459642..e9c21ceb7d6f6 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -8610,7 +8610,11 @@ static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ | PACKET3_RELEASE_MEM_GCR_GL2_WB | - PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */ + PACKET3_RELEASE_MEM_GCR_GL2_INV | + PACKET3_RELEASE_MEM_GCR_GL2_US | + PACKET3_RELEASE_MEM_GCR_GL1_INV | + PACKET3_RELEASE_MEM_GCR_GLV_INV | + PACKET3_RELEASE_MEM_GCR_GLM_INV | PACKET3_RELEASE_MEM_GCR_GLM_WB | PACKET3_RELEASE_MEM_CACHE_POLICY(3) | PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | From e2681918678d794b80a1232de7bbbd5fe0c2efae Mon Sep 17 00:00:00 2001 From: Jonathan Kim Date: Tue, 24 Mar 2020 12:30:28 -0400 Subject: [PATCH 0201/1868] drm/amdkfd: block queue destroy on suspended queues When debugger is attached, queue destroy requests will be blocked until queues have resumed. Note: the debugger owns suspend_queues and resume_queues so there should be no harm blocking queue destroy until queue resume since gdb can halt CPU threads anyways. Debugger also doesn't wait on application threads since suspend is only briefly called to update_waves before resume so halting queue destroy calls shouldn't deadlock the debugger. Signed-off-by: Jonathan Kim Reviewed-by: Felix Kuehling Signed-off-by: Jonathan Kim --- drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c index 20ea745729ee3..e15da906b6d22 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c @@ -517,9 +517,13 @@ int pqm_destroy_queue(struct process_queue_manager *pqm, unsigned int qid) if (retval) goto err_destroy_queue; - kfd_procfs_del_queue(pqn->q); dqm = pqn->q->device->dqm; retval = dqm->ops.destroy_queue(dqm, &pdd->qpd, pqn->q); + + if (retval == -ERESTARTSYS) + return retval; + + kfd_procfs_del_queue(pqn->q); if (retval) { pr_err("Pasid 0x%x destroy queue %d failed, ret %d\n", pqm->process->pasid, From d89167e9bec5eaf296993b1fe3a15ee15beff305 Mon Sep 17 00:00:00 2001 From: Amber Lin Date: Fri, 24 Apr 2020 16:14:01 -0400 Subject: [PATCH 0202/1868] drm/amdkfd: Distance non-upstream ioctls Create a gap between upstream and non-upstream ioctls so when upstream adds an ioctl, we don't need to bump non-upstream ioctl command number. This can avoid the backwards compatibility in the future though it'll happen at this time. Signed-off-by: Amber Lin Reviewed-by: Felix Kuehling Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 8 ++------ include/uapi/linux/kfd_ioctl.h | 8 ++++++-- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 159d7c86da5b3..ff9d3d10623e2 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -3288,8 +3288,6 @@ static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = { kfd_ioctl_ipc_export_handle, 0), }; -#define AMDKFD_CORE_IOCTL_COUNT ARRAY_SIZE(amdkfd_ioctls) - static long kfd_ioctl(struct file *filep, unsigned int cmd, unsigned long arg) { struct kfd_process *process; @@ -3302,10 +3300,8 @@ static long kfd_ioctl(struct file *filep, unsigned int cmd, unsigned long arg) int retcode = -EINVAL; bool ptrace_attached = false; - if (nr >= AMDKFD_CORE_IOCTL_COUNT) - goto err_i1; - - if ((nr >= AMDKFD_COMMAND_START) && (nr < AMDKFD_COMMAND_END)) { + if (((nr >= AMDKFD_COMMAND_START) && (nr < AMDKFD_COMMAND_END)) || + ((nr >= AMDKFD_COMMAND_START_2) && (nr < AMDKFD_COMMAND_END_2))) { u32 amdkfd_size; ioctl = &amdkfd_ioctls[nr]; diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h index 35a3d25973080..04ba10ee1ad7b 100644 --- a/include/uapi/linux/kfd_ioctl.h +++ b/include/uapi/linux/kfd_ioctl.h @@ -1611,13 +1611,17 @@ struct kfd_ioctl_dbg_trap_args { #define AMDKFD_IOC_DBG_TRAP \ AMDKFD_IOWR(0x26, struct kfd_ioctl_dbg_trap_args) +#define AMDKFD_COMMAND_START 0x01 +#define AMDKFD_COMMAND_END 0x27 + +/* non-upstream ioctls */ #define AMDKFD_IOC_IPC_IMPORT_HANDLE \ AMDKFD_IOWR(0x80, struct kfd_ioctl_ipc_import_handle_args) #define AMDKFD_IOC_IPC_EXPORT_HANDLE \ AMDKFD_IOWR(0x81, struct kfd_ioctl_ipc_export_handle_args) -#define AMDKFD_COMMAND_START 0x01 -#define AMDKFD_COMMAND_END 0x27 +#define AMDKFD_COMMAND_START_2 0x80 +#define AMDKFD_COMMAND_END_2 0x84 #endif From dca87377ed9cf6325e5ecd7eaebf3cfe82a51772 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Fri, 1 May 2020 10:40:05 -0400 Subject: [PATCH 0203/1868] drm/amdkfd: Fix a race condition getting IPC obj handle reference If an IPC object is being released (zero refcount) don't try to take another reference to it. Signed-off-by: Felix Kuehling Tested-by: Alex Sierra Reviewed-by: Alex Sierra --- drivers/gpu/drm/amd/amdkfd/kfd_ipc.c | 9 +++++---- drivers/gpu/drm/amd/amdkfd/kfd_ipc.h | 2 +- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c index 51395a88c12a8..ab05edb3a652a 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c @@ -88,9 +88,11 @@ static void ipc_obj_release(struct kref *r) kfree(obj); } -void ipc_obj_get(struct kfd_ipc_obj *obj) +struct kfd_ipc_obj *ipc_obj_get(struct kfd_ipc_obj *obj) { - kref_get(&obj->ref); + if (kref_get_unless_zero(&obj->ref)) + return obj; + return NULL; } void ipc_obj_put(struct kfd_ipc_obj **obj) @@ -196,7 +198,7 @@ int kfd_ipc_import_handle(struct kfd_dev *dev, struct kfd_process *p, &kfd_ipc_handles.handles[HANDLE_TO_KEY(share_handle)], node) { if (!memcmp(entry->share_handle, share_handle, sizeof(entry->share_handle))) { - found = entry; + found = ipc_obj_get(entry); break; } } @@ -204,7 +206,6 @@ int kfd_ipc_import_handle(struct kfd_dev *dev, struct kfd_process *p, if (!found) return -EINVAL; - ipc_obj_get(found); pr_debug("Found ipc_dma_buf: %p\n", found->data); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h index 9ee8627b88b08..a6560eae9ff50 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h @@ -45,7 +45,7 @@ int kfd_ipc_import_dmabuf(struct kfd_dev *kfd, struct kfd_process *p, int kfd_ipc_export_as_handle(struct kfd_dev *dev, struct kfd_process *p, uint64_t handle, uint32_t *ipc_handle); -void ipc_obj_get(struct kfd_ipc_obj *obj); +struct kfd_ipc_obj *ipc_obj_get(struct kfd_ipc_obj *obj); void ipc_obj_put(struct kfd_ipc_obj **obj); #endif /* KFD_IPC_H_ */ From 980d929e5869c8d16fc83536e6af3400c771d860 Mon Sep 17 00:00:00 2001 From: "Philip.Cox@amd.com" Date: Wed, 1 Apr 2020 13:37:20 -0400 Subject: [PATCH 0204/1868] drm/amdkfd: Initial gfx9 debug address watch Code for new GFX9 kfd debugger address watch code. -- Adding support for: -- add address watch -- clear address watch Change-Id: I51d6494db6881c02b8fbb56c73cf970389c036fc Signed-off-by: Philip.Cox@amd.com Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index a1410128da7bf..dc971527450db 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -371,6 +371,15 @@ struct kfd_dev { /* Compute Profile ref. count */ atomic_t compute_profile; + /* + * A bitmask to indicate which watch points have been allocated. + * bit meaning: + * 0: unallocated/available + * 1: allocated/unavailable + */ + uint32_t allocated_debug_watch_points; + spinlock_t watch_points_lock; + struct ida doorbell_ida; unsigned int max_doorbell_slices; @@ -1578,6 +1587,16 @@ int kfd_ipc_init(void); void kfd_inc_compute_active(struct kfd_node *dev); void kfd_dec_compute_active(struct kfd_node *dev); +/* Allocate and free watch point IDs for debugger */ +int kfd_allocate_debug_watch_point(struct kfd_dev *kfd, + uint64_t watch_address, + uint32_t watch_address_mask, + uint32_t *watch_point, + uint32_t watch_mode, + uint32_t debug_vmid); +int kfd_release_debug_watch_points(struct kfd_dev *kfd, + uint32_t watch_point_bit_mask_to_free); + /* Cgroup Support */ /* Check with device cgroup if @kfd device is accessible */ static inline int kfd_devcgroup_check_permission(struct kfd_node *node) From 81216fd3b1434ee4fcb0fe8ba0088011552226a4 Mon Sep 17 00:00:00 2001 From: Joseph Greathouse Date: Tue, 30 Jun 2020 18:40:37 -0500 Subject: [PATCH 0205/1868] drm/amdkfd: Prevent GWS+debugger on buggy firmware Some versions of MEC2 firmware do not correctly handle simultaneously setting up debugging on a process while having a GWS-enabled queue in that process. This could lead to CWSR failure and crashing the kernel driver. Prevent this situation from happening when we are on an affected firmware version by preventing both debugging and GWS-enabled queue from both being enabled at the same time. If the process has a GWS enabled queue, attempting to turn on debugging will fail with -EBUSY. If debugging is already enabled, attempting to create a GWS-enabled queue will fail with -EBUSY. v2: Use qpd.num_gws to track GWS usage, even with suspended queues. Signed-off-by: Joseph Greathouse Reviewed-by: Rajneesh Bhardwaj Reviewed-by: Felix Kuehling Change-Id: Id4f1d12665fa6ac5d5402637cf9361bcb2dbfbc6 --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 6 ++++++ drivers/gpu/drm/amd/amdkfd/kfd_device.c | 9 +++++++++ 2 files changed, 15 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index ff9d3d10623e2..e504c0a6c2dde 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1505,6 +1505,12 @@ static int kfd_ioctl_alloc_queue_gws(struct file *filep, goto out_unlock; } + pdd = kfd_bind_process_to_device(dev, p); + if (IS_ERR(pdd)) { + retval = -ESRCH; + goto out_unlock; + } + if (!dev->gws) { retval = -ENODEV; goto out_unlock; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index c2d2598f776cd..302b6979e7d2a 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -572,6 +572,15 @@ static int kfd_gws_init(struct kfd_node *node) ret = amdgpu_amdkfd_alloc_gws(node->adev, node->adev->gds.gws_size, &node->gws); + if ((kfd->device_info->asic_family == CHIP_VEGA10 + && kfd->mec2_fw_version < 0x81b6) + || (kfd->device_info->asic_family >= CHIP_VEGA12 + && kfd->device_info->asic_family <= CHIP_RAVEN + && kfd->mec2_fw_version < 0x1b6) + || (kfd->device_info->asic_family == CHIP_ARCTURUS + && kfd->mec2_fw_version < 0x30)) + kfd->gws_debug_workaround = true; + return ret; } From b8325798e5ee33ae716b9ecb2afa9a9335818762 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Fri, 26 Jun 2020 22:32:01 -0400 Subject: [PATCH 0206/1868] drm/amdkfd: Move ipc_obj from kfd_bo to kgd_mem This should make IPC easier to upstream. struct kfd_bo does not exist upstream and its main purpose is to support RDMA, which is not upstreamable. struct kgd_mem exists upstream and is a KFD-specific buffer object structure that can be used to store a pointer to the ipc_obj. Adding another one layer of tracking in KFD just for IPC cannot be justified when upstreaming IPC. With this change, some of the IPC functionality moves into amdgpu_amdkfd_gpuvm.c with some calls back to kfd_ipc.c. Cleaned up and exported kfd_ipc_obj_put and kfd_ipc_store_insert. Signed-off-by: Felix Kuehling Acked-and-tested-by: Rajneesh Bhardwaj --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 8 ++- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 39 ++++++++--- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_ipc.c | 67 ++++++++----------- drivers/gpu/drm/amd/amdkfd/kfd_ipc.h | 12 ++-- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 4 +- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 8 +-- 7 files changed, 75 insertions(+), 65 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index 1b5a9eca185c6..f251df5bd380a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -69,6 +69,7 @@ struct kfd_mem_attachment { struct kgd_mem { struct mutex lock; struct amdgpu_bo *bo; + struct kfd_ipc_obj *ipc_obj; struct dma_buf *dmabuf; struct hmm_range *range; struct list_head attachments; @@ -347,6 +348,7 @@ void amdgpu_amdkfd_gpuvm_put_sg_table(struct amdgpu_bo *bo, int amdgpu_amdkfd_gpuvm_import_dmabuf(struct kgd_dev *kgd, struct dma_buf *dmabuf, + struct kfd_ipc_obj *ipc_obj, uint64_t va, void *drm_priv, struct kgd_mem **mem, uint64_t *size, uint64_t *mmap_offset); @@ -356,9 +358,9 @@ int amdgpu_amdkfd_gpuvm_import_dmabuf_fd(struct amdgpu_device *adev, int fd, uint64_t *mmap_offset); int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_mem *mem, struct dma_buf **dmabuf); -int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_dev *kgd, void *vm, - struct kgd_mem *mem, - struct dma_buf **dmabuf); +int amdgpu_amdkfd_gpuvm_export_ipc_obj(struct kgd_dev *kgd, void *vm, + struct kgd_mem *mem, + struct kfd_ipc_obj **ipc_obj); void amdgpu_amdkfd_debug_mem_fence(struct amdgpu_device *adev); int amdgpu_amdkfd_get_tile_config(struct amdgpu_device *adev, struct tile_config *config); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 530bc6e73b01b..30a21ce2da417 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -36,6 +36,7 @@ #include "amdgpu_hmm.h" #include "amdgpu_amdkfd.h" #include "amdgpu_dma_buf.h" +#include "kfd_ipc.h" #include #include "amdgpu_xgmi.h" #include "kfd_priv.h" @@ -2000,6 +2001,9 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu( *size = 0; } + /* Unreference the ipc_obj if applicable */ + kfd_ipc_obj_put(&mem->ipc_obj); + /* Free the BO*/ drm_vma_node_revoke(&mem->bo->tbo.base.vma_node, drm_priv); drm_gem_handle_delete(adev->kfd.client.file, mem->gem_handle); @@ -2622,6 +2626,7 @@ static int import_obj_create(struct amdgpu_device *adev, get_dma_buf(dma_buf); (*mem)->dmabuf = dma_buf; (*mem)->bo = bo; + (*mem)->ipc_obj = ipc_obj; (*mem)->va = va; (*mem)->domain = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) && !(adev->flags & AMD_IS_APU) ? @@ -2704,22 +2709,40 @@ int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_mem *mem, return ret; } -int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_dev *kgd, void *vm, - struct kgd_mem *mem, - struct dma_buf **dmabuf) +int amdgpu_amdkfd_gpuvm_export_ipc_obj(struct kgd_dev *kgd, void *vm, + struct kgd_mem *mem, + struct kfd_ipc_obj **ipc_obj) { struct amdgpu_device *adev = NULL; + struct dma_buf *dmabuf; + int r = 0; - if (!dmabuf || !kgd || !vm || !mem) + if (!kgd || !vm || !mem) return -EINVAL; adev = get_amdgpu_device(kgd); + mutex_lock(&mem->lock); - *dmabuf = amdgpu_gem_prime_export(&mem->bo->tbo.base, 0); - if (IS_ERR(*dmabuf)) - return -EINVAL; + if (mem->ipc_obj) { + *ipc_obj = mem->ipc_obj; + goto unlock_out; + } - return 0; + dmabuf = amdgpu_gem_prime_export(&mem->bo->tbo.base, 0); + if (IS_ERR(dmabuf)) { + r = PTR_ERR(dmabuf); + goto unlock_out; + } + + r = kfd_ipc_store_insert(dmabuf, &mem->ipc_obj); + if (r) + dma_buf_put(dmabuf); + else + *ipc_obj = mem->ipc_obj; + +unlock_out: + mutex_unlock(&mem->lock); + return r; } /* Evict a userptr BO by stopping the queues if necessary diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index e504c0a6c2dde..edeee8b3424a0 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1171,7 +1171,7 @@ static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep, KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL | KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP); idr_handle = kfd_process_device_create_obj_handle(pdd, mem, - args->va_addr, args->size, cpuva, mem_type, NULL); + args->va_addr, args->size, cpuva, mem_type); if (idr_handle < 0) { err = -EFAULT; goto err_free; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c index ab05edb3a652a..d52e0f38eef1c 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c @@ -20,7 +20,6 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -#include #include #include @@ -42,7 +41,7 @@ static struct kfd_ipc_handles { */ #define HANDLE_TO_KEY(sh) ((*(uint64_t *)sh) & KFD_IPC_HASH_TABLE_SIZE_MASK) -static int ipc_store_insert(void *val, void *sh, struct kfd_ipc_obj **ipc_obj) +int kfd_ipc_store_insert(struct dma_buf *dmabuf, struct kfd_ipc_obj **ipc_obj) { struct kfd_ipc_obj *obj; @@ -58,11 +57,9 @@ static int ipc_store_insert(void *val, void *sh, struct kfd_ipc_obj **ipc_obj) * storage happens at ipc_obj release time. */ kref_init(&obj->ref); - obj->data = val; + obj->dmabuf = dmabuf; get_random_bytes(obj->share_handle, sizeof(obj->share_handle)); - memcpy(sh, obj->share_handle, sizeof(obj->share_handle)); - mutex_lock(&kfd_ipc_handles.lock); hlist_add_head(&obj->node, &kfd_ipc_handles.handles[HANDLE_TO_KEY(obj->share_handle)]); @@ -84,21 +81,23 @@ static void ipc_obj_release(struct kref *r) hash_del(&obj->node); mutex_unlock(&kfd_ipc_handles.lock); - dma_buf_put(obj->data); + dma_buf_put(obj->dmabuf); kfree(obj); } -struct kfd_ipc_obj *ipc_obj_get(struct kfd_ipc_obj *obj) +static struct kfd_ipc_obj *ipc_obj_get(struct kfd_ipc_obj *obj) { if (kref_get_unless_zero(&obj->ref)) return obj; return NULL; } -void ipc_obj_put(struct kfd_ipc_obj **obj) +void kfd_ipc_obj_put(struct kfd_ipc_obj **obj) { - kref_put(&(*obj)->ref, ipc_obj_release); - *obj = NULL; + if (*obj) { + kref_put(&(*obj)->ref, ipc_obj_release); + *obj = NULL; + } } int kfd_ipc_init(void) @@ -110,10 +109,10 @@ int kfd_ipc_init(void) static int kfd_import_dmabuf_create_kfd_bo(struct kfd_dev *dev, struct kfd_process *p, - uint32_t gpu_id, struct dma_buf *dmabuf, + uint32_t gpu_id, + struct dma_buf *dmabuf, struct kfd_ipc_obj *ipc_obj, uint64_t va_addr, uint64_t *handle, - uint64_t *mmap_offset, - struct kfd_ipc_obj *ipc_obj) + uint64_t *mmap_offset) { int r; void *mem; @@ -135,7 +134,7 @@ static int kfd_import_dmabuf_create_kfd_bo(struct kfd_dev *dev, goto err_unlock; } - r = amdgpu_amdkfd_gpuvm_import_dmabuf(dev->kgd, dmabuf, + r = amdgpu_amdkfd_gpuvm_import_dmabuf(dev->kgd, dmabuf, ipc_obj, va_addr, pdd->vm, (struct kgd_mem **)&mem, &size, mmap_offset); @@ -143,8 +142,7 @@ static int kfd_import_dmabuf_create_kfd_bo(struct kfd_dev *dev, goto err_unlock; idr_handle = kfd_process_device_create_obj_handle(pdd, mem, - va_addr, size, 0, 0, - ipc_obj); + va_addr, size, 0, 0); if (idr_handle < 0) { r = -EFAULT; goto err_free; @@ -175,9 +173,8 @@ int kfd_ipc_import_dmabuf(struct kfd_dev *dev, if (!dmabuf) return -EINVAL; - r = kfd_import_dmabuf_create_kfd_bo(dev, p, gpu_id, dmabuf, - va_addr, handle, mmap_offset, - NULL); + r = kfd_import_dmabuf_create_kfd_bo(dev, p, gpu_id, dmabuf, NULL, + va_addr, handle, mmap_offset); dma_buf_put(dmabuf); return r; } @@ -207,18 +204,18 @@ int kfd_ipc_import_handle(struct kfd_dev *dev, struct kfd_process *p, if (!found) return -EINVAL; - pr_debug("Found ipc_dma_buf: %p\n", found->data); + pr_debug("Found ipc_dma_buf: %p\n", found->dmabuf); - r = kfd_import_dmabuf_create_kfd_bo(dev, p, gpu_id, found->data, - va_addr, handle, mmap_offset, - found); + r = kfd_import_dmabuf_create_kfd_bo(dev, p, gpu_id, + found->dmabuf, found, + va_addr, handle, mmap_offset); if (r) goto error_unref; return r; error_unref: - ipc_obj_put(&found); + kfd_ipc_obj_put(&found); return r; } @@ -226,9 +223,9 @@ int kfd_ipc_export_as_handle(struct kfd_dev *dev, struct kfd_process *p, uint64_t handle, uint32_t *ipc_handle) { struct kfd_process_device *pdd = NULL; - struct kfd_ipc_obj *obj; + struct kfd_ipc_obj *ipc_obj; struct kfd_bo *kfd_bo = NULL; - struct dma_buf *dmabuf; + struct kgd_mem *mem; int r; if (!dev || !ipc_handle) @@ -249,23 +246,15 @@ int kfd_ipc_export_as_handle(struct kfd_dev *dev, struct kfd_process *p, pr_err("Failed to get bo"); return -EINVAL; } - if (kfd_bo->kfd_ipc_obj) { - memcpy(ipc_handle, kfd_bo->kfd_ipc_obj->share_handle, - sizeof(kfd_bo->kfd_ipc_obj->share_handle)); - return 0; - } - - r = amdgpu_amdkfd_gpuvm_export_dmabuf(dev->kgd, pdd->vm, - (struct kgd_mem *)kfd_bo->mem, - &dmabuf); - if (r) - return r; + mem = (struct kgd_mem *)kfd_bo->mem; - r = ipc_store_insert(dmabuf, ipc_handle, &obj); + r = amdgpu_amdkfd_gpuvm_export_ipc_obj(dev->kgd, pdd->vm, mem, + &ipc_obj); if (r) return r; - kfd_bo->kfd_ipc_obj = obj; + memcpy(ipc_handle, ipc_obj->share_handle, + sizeof(ipc_obj->share_handle)); return r; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h index a6560eae9ff50..72fe8e4af2e5c 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h @@ -25,12 +25,16 @@ #define KFD_IPC_H_ #include -#include "kfd_priv.h" +#include + +/* avoid including kfd_priv.h */ +struct kfd_dev; +struct kfd_process; struct kfd_ipc_obj { struct hlist_node node; struct kref ref; - void *data; + struct dma_buf *dmabuf; uint32_t share_handle[4]; }; @@ -45,7 +49,7 @@ int kfd_ipc_import_dmabuf(struct kfd_dev *kfd, struct kfd_process *p, int kfd_ipc_export_as_handle(struct kfd_dev *dev, struct kfd_process *p, uint64_t handle, uint32_t *ipc_handle); -struct kfd_ipc_obj *ipc_obj_get(struct kfd_ipc_obj *obj); -void ipc_obj_put(struct kfd_ipc_obj **obj); +int kfd_ipc_store_insert(struct dma_buf *dmabuf, struct kfd_ipc_obj **ipc_obj); +void kfd_ipc_obj_put(struct kfd_ipc_obj **obj); #endif /* KFD_IPC_H_ */ diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index dc971527450db..8f01c69316dce 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -401,7 +401,6 @@ struct kfd_bo { void *mem; struct interval_tree_node it; struct kfd_dev *dev; - struct kfd_ipc_obj *kfd_ipc_obj; /* page-aligned VA address */ uint64_t cpuva; unsigned int mem_type; @@ -1121,8 +1120,7 @@ int kfd_reserved_mem_mmap(struct kfd_node *dev, struct kfd_process *process, int kfd_process_device_create_obj_handle(struct kfd_process_device *pdd, void *mem, uint64_t start, uint64_t length, uint64_t cpuva, - unsigned int mem_type, - struct kfd_ipc_obj *ipc_obj); + unsigned int mem_type); void *kfd_process_device_translate_handle(struct kfd_process_device *p, int handle); struct kfd_bo *kfd_process_device_find_bo(struct kfd_process_device *pdd, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index cf9c4b82761b3..d60c493fa1966 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -32,7 +32,6 @@ #include #include #include -#include "kfd_ipc.h" #include #include "amdgpu_amdkfd.h" #include "amdgpu.h" @@ -1771,8 +1770,7 @@ struct kfd_process_device *kfd_bind_process_to_device(struct kfd_node *dev, int kfd_process_device_create_obj_handle(struct kfd_process_device *pdd, void *mem, uint64_t start, uint64_t length, uint64_t cpuva, - unsigned int mem_type, - struct kfd_ipc_obj *ipc_obj) + unsigned int mem_type) { int handle; struct kfd_bo *buf_obj; @@ -1791,7 +1789,6 @@ int kfd_process_device_create_obj_handle(struct kfd_process_device *pdd, buf_obj->mem = mem; buf_obj->dev = pdd->dev; - buf_obj->kfd_ipc_obj = ipc_obj; buf_obj->cpuva = cpuva; buf_obj->mem_type = mem_type; @@ -1867,9 +1864,6 @@ void kfd_process_device_remove_obj_handle(struct kfd_process_device *pdd, buf_obj = kfd_process_device_find_bo(pdd, handle); - if (buf_obj->kfd_ipc_obj) - ipc_obj_put(&buf_obj->kfd_ipc_obj); - idr_remove(&pdd->alloc_idr, handle); interval_tree_remove(&buf_obj->it, &p->bo_interval_tree); From 597168cb7b25d847a26b223af3e6e05bbeaf2d96 Mon Sep 17 00:00:00 2001 From: Jack Xiao Date: Fri, 20 Mar 2020 17:07:06 +0800 Subject: [PATCH 0207/1868] drm/amdgpu: move csa to the lower gmc hole location Move csa to the lower gmc hole location as the cp firmware starting from Navi1x firmware can't well handle the address of upper gmc hole space. Signed-off-by: Jack Xiao Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c index cfdf558b48b64..7d906ddbb30ac 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_csa.c @@ -28,9 +28,13 @@ uint64_t amdgpu_csa_vaddr(struct amdgpu_device *adev) { - uint64_t addr = AMDGPU_VA_RESERVED_CSA_START(adev); - - addr = amdgpu_gmc_sign_extend(addr); + uint64_t addr; + if (adev->asic_type >= CHIP_NAVI10) { + addr = AMDGPU_VA_RESERVED_CSA_SIZE - AMDGPU_CSA_SIZE; + } else { + addr = AMDGPU_VA_RESERVED_CSA_START(adev); + addr = amdgpu_gmc_sign_extend(addr); + } return addr; } From 5eba18643469988b8a6240bb4dd0e3ac0b7d9585 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Wed, 7 Oct 2020 14:14:28 -0400 Subject: [PATCH 0208/1868] drm/amdkfd: Catch failures from follow_pfn This fixes uninitialized, out-of-range physical addresses being programmed into the GPUVM page table in some corner cases. Signed-off-by: Felix Kuehling Acked-by: Oak Zeng --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index edeee8b3424a0..ebdcc6b518b3c 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1123,7 +1123,11 @@ static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep, if (vma && (vma->vm_flags & VM_IO)) { unsigned long pfn; - follow_pfn(vma, args->mmap_offset, &pfn); + err = follow_pfn(vma, args->mmap_offset, &pfn); + if (err) { + pr_debug("Failed to get PFN: %ld\n", err); + return err; + } flags |= KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL; flags &= ~KFD_IOC_ALLOC_MEM_FLAGS_USERPTR; offset = (pfn << PAGE_SHIFT); From 8e85fc1ff13770146625a55a81003d29f430fd2d Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Mon, 26 Oct 2020 18:40:58 -0400 Subject: [PATCH 0209/1868] drm/amdkfd: correctly check find_vma success Check that find_vma actually found a VM that matches the address we're looking for. If there is no such VMA, don't try to create an IO mapping. Instead a regular userptr mapping will be created, and is expected to fail later in get_user_pages. Signed-off-by: Felix Kuehling Reviewed-by: Oak Zeng --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index ebdcc6b518b3c..93768a23ca6a3 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1120,7 +1120,8 @@ static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep, * BO as a regular userptr BO */ vma = find_vma(current->mm, args->mmap_offset); - if (vma && (vma->vm_flags & VM_IO)) { + if (vma && args->mmap_offset >= vma->vm_start && + (vma->vm_flags & VM_IO)) { unsigned long pfn; err = follow_pfn(vma, args->mmap_offset, &pfn); From e9abfef7537d0f2699c199160c3b282d2db4ef59 Mon Sep 17 00:00:00 2001 From: Gang Ba Date: Sat, 31 Oct 2020 20:43:28 -0400 Subject: [PATCH 0210/1868] drm/amdkfd: Create P2P links Create p2p links for peer accessible devices Change-Id: I6cd52e43cba99224bca0eac7b01f29311912185b Signed-off-by: Gang Ba --- drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index a5c8c761c6f9b..061d75c29fcb2 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -591,6 +591,18 @@ static void kfd_remove_sysfs_node_entry(struct kfd_topology_device *dev) struct kfd_mem_properties *mem; struct kfd_perf_properties *perf; + if (dev->kobj_p2plink) { + list_for_each_entry(p2plink, &dev->p2p_link_props, list) + if (p2plink->kobj) { + kfd_remove_sysfs_file(p2plink->kobj, + &p2plink->attr); + p2plink->kobj = NULL; + } + kobject_del(dev->kobj_p2plink); + kobject_put(dev->kobj_p2plink); + dev->kobj_p2plink = NULL; + } + if (dev->kobj_iolink) { list_for_each_entry(iolink, &dev->io_link_props, list) if (iolink->kobj) { From 15125e7f039de70a57eff0211b5262bb27aa26bb Mon Sep 17 00:00:00 2001 From: Gang Ba Date: Wed, 21 Oct 2020 16:00:55 -0400 Subject: [PATCH 0211/1868] drm/amdgpu: allow function to allocate normal GTT memory amdgpu_amdkfd_alloc_gtt_mem currently allocates USWC memory. It uses write-combining for CPU access, which is slow for reading. Add a new parameter to amdgpu_amdkfd_alloc_gtt_mem to allocate normal GTT memory. Signed-off-by: Gang Ba Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 7 +++++-- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_device.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c | 2 +- 5 files changed, 9 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c index f79d404d10d61..20702e6a4c892 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c @@ -295,7 +295,7 @@ void amdgpu_amdkfd_gpu_reset(struct amdgpu_device *adev) int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t size, void **mem_obj, uint64_t *gpu_addr, - void **cpu_ptr, bool cp_mqd_gfx9) + void **cpu_ptr, bool cp_mqd_gfx9, bool is_uswc_mode) { struct amdgpu_bo *bo = NULL; struct amdgpu_bo_param bp; @@ -306,7 +306,10 @@ int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t size, bp.size = size; bp.byte_align = PAGE_SIZE; bp.domain = AMDGPU_GEM_DOMAIN_GTT; - bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC; + if (is_uswc_mode) + bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC; + else + bp.flags = 0; bp.type = ttm_bo_type_kernel; bp.resv = NULL; bp.bo_ptr_size = sizeof(struct amdgpu_bo); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index f251df5bd380a..eedaa87e254d6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -235,7 +235,7 @@ int amdgpu_amdkfd_bo_validate_and_fence(struct amdgpu_bo *bo, /* Shared API */ int amdgpu_amdkfd_alloc_gtt_mem(struct amdgpu_device *adev, size_t size, void **mem_obj, uint64_t *gpu_addr, - void **cpu_ptr, bool mqd_gfx9); + void **cpu_ptr, bool mqd_gfx9, bool is_uswc_mode); void amdgpu_amdkfd_free_gtt_mem(struct amdgpu_device *adev, void **mem_obj); int amdgpu_amdkfd_alloc_gws(struct amdgpu_device *adev, size_t size, void **mem_obj); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index 302b6979e7d2a..cdd956b232a15 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -787,7 +787,7 @@ bool kgd2kfd_device_init(struct kfd_dev *kfd, if (amdgpu_amdkfd_alloc_gtt_mem( kfd->adev, size, &kfd->gtt_mem, &kfd->gtt_start_gpu_addr, &kfd->gtt_start_cpu_ptr, - false)) { + false, true)) { dev_err(kfd_device, "Could not allocate %d bytes\n", size); goto alloc_gtt_mem_failure; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index 2862eb6753f43..eae541b9b9deb 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -2713,7 +2713,7 @@ static int allocate_hiq_sdma_mqd(struct device_queue_manager *dqm) retval = amdgpu_amdkfd_alloc_gtt_mem(dev->adev, size, &(mem_obj->gtt_mem), &(mem_obj->gpu_addr), - (void *)&(mem_obj->cpu_ptr), false); + (void *)&(mem_obj->cpu_ptr), false, true); return retval; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c index bfd2867b7ef49..4061f36db1dc7 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v9.c @@ -183,7 +183,7 @@ static struct kfd_mem_obj *allocate_mqd(struct kfd_node *node, NUM_XCC(node->xcc_mask), &(mqd_mem_obj->gtt_mem), &(mqd_mem_obj->gpu_addr), - (void *)&(mqd_mem_obj->cpu_ptr), true); + (void *)&(mqd_mem_obj->cpu_ptr), true, true); if (retval) { kfree(mqd_mem_obj); From 045413dcf50411f3cadaf484f2543ee505d8558c Mon Sep 17 00:00:00 2001 From: Gang Ba Date: Wed, 21 Oct 2020 17:10:42 -0400 Subject: [PATCH 0212/1868] drm/amd: Add Stream Performance Counter Monitors Driver Add Driver code for user to control GPU Stream Performance Counter Monitor and dump the Sample data to measure the GPU performance. Change-Id: Id10682e05ec3fc7456bcd8b25241686e42353462 Signed-off-by: Gang Ba Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/Makefile | 3 +- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 9 + .../drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c | 104 ++++ drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 11 + drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 136 ++++++ drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 137 +++++- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 127 +++++ drivers/gpu/drm/amd/amdkfd/Makefile | 1 + drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 10 + drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 12 + drivers/gpu/drm/amd/amdkfd/kfd_spm.c | 462 ++++++++++++++++++ include/uapi/linux/kfd_ioctl.h | 81 ++- 12 files changed, 1089 insertions(+), 4 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c create mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_spm.c diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index 05bdbf365fc4c..359d2b7d8cbbd 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -282,7 +282,8 @@ amdgpu-y += \ amdgpu_amdkfd_gfx_v10.o \ amdgpu_amdkfd_gfx_v10_3.o \ amdgpu_amdkfd_gfx_v11.o \ - amdgpu_amdkfd_gfx_v12.o + amdgpu_amdkfd_gfx_v12.o \ + amdgpu_amdkfd_rlc_spm.o ifneq ($(CONFIG_DRM_AMDGPU_CIK),) amdgpu-y += amdgpu_amdkfd_gfx_v7.o diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index eedaa87e254d6..558406b16d7b8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -421,6 +421,14 @@ void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo) } #endif +void amdgpu_amdkfd_rlc_spm_cntl(struct kgd_dev *kgd, bool cntl); +int amdgpu_amdkfd_rlc_spm(struct kgd_dev *kgd, void *args); +int amdgpu_amdkfd_rlc_spm_acquire(struct kgd_dev *kgd, + struct amdgpu_vm *vm, u64 gpu_addr, u32 size); +void amdgpu_amdkfd_rlc_spm_release(struct kgd_dev *kgd, struct amdgpu_vm *vm); +void amdgpu_amdkfd_rlc_spm_set_rdptr(struct kgd_dev *kgd, u32 rptr); +void amdgpu_amdkfd_rlc_spm_interrupt(struct amdgpu_device *adev); + #if IS_ENABLED(CONFIG_HSA_AMD_SVM) int kgd2kfd_init_zone_device(struct amdgpu_device *adev); #else @@ -432,6 +440,7 @@ int kgd2kfd_init_zone_device(struct amdgpu_device *adev) #endif /* KGD2KFD callbacks */ +void kgd2kfd_spm_interrupt(struct kfd_dev *kfd); int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger); int kgd2kfd_resume_mm(struct mm_struct *mm); int kgd2kfd_schedule_evict_and_restore_process(struct mm_struct *mm, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c new file mode 100644 index 0000000000000..eeaca9d1e02b9 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c @@ -0,0 +1,104 @@ +/* + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "amdgpu_object.h" +#include "amdgpu_amdkfd.h" +#include +#include "amdgpu_ids.h" + +void amdgpu_amdkfd_rlc_spm_cntl(struct kgd_dev *kgd, bool cntl) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)kgd; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + + spin_lock(&adev->gfx.kiq.ring_lock); + amdgpu_ring_alloc(kiq_ring, adev->gfx.spmfuncs->set_spm_config_size); + if (cntl) + adev->gfx.spmfuncs->start(adev); + else + adev->gfx.spmfuncs->stop(adev); + amdgpu_ring_commit(kiq_ring); + spin_unlock(&adev->gfx.kiq.ring_lock); +} + +void amdgpu_amdkfd_rlc_spm_set_rdptr(struct kgd_dev *kgd, u32 rptr) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)kgd; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + + spin_lock(&adev->gfx.kiq.ring_lock); + amdgpu_ring_alloc(kiq_ring, adev->gfx.spmfuncs->set_spm_config_size); + adev->gfx.spmfuncs->set_rdptr(adev, rptr); + amdgpu_ring_commit(kiq_ring); + spin_unlock(&adev->gfx.kiq.ring_lock); +} + +int amdgpu_amdkfd_rlc_spm_acquire(struct kgd_dev *kgd, struct amdgpu_vm *vm, u64 gpu_addr, u32 size) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)kgd; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + int r; + + if (!adev->gfx.rlc.funcs->update_spm_vmid) + return -EINVAL; + + r = amdgpu_vmid_alloc_reserved(adev, vm, AMDGPU_GFXHUB_0); + if (r) + return r; + + /* init spm vmid with 0x0 */ + adev->gfx.rlc.funcs->update_spm_vmid(adev, 0); + + /* set spm ring registers */ + spin_lock(&adev->gfx.kiq.ring_lock); + amdgpu_ring_alloc(kiq_ring, adev->gfx.spmfuncs->set_spm_config_size); + adev->gfx.spmfuncs->set_spm_perfmon_ring_buf(adev, gpu_addr, size); + amdgpu_ring_commit(kiq_ring); + spin_unlock(&adev->gfx.kiq.ring_lock); + return r; +} + +void amdgpu_amdkfd_rlc_spm_release(struct kgd_dev *kgd, struct amdgpu_vm *vm) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)kgd; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + + /* stop spm stream and interrupt */ + spin_lock(&adev->gfx.kiq.ring_lock); + amdgpu_ring_alloc(kiq_ring, adev->gfx.spmfuncs->set_spm_config_size); + adev->gfx.spmfuncs->stop(adev); + amdgpu_ring_commit(kiq_ring); + spin_unlock(&adev->gfx.kiq.ring_lock); + + amdgpu_vmid_free_reserved(adev, vm, AMDGPU_GFXHUB_0); + + /* revert spm vmid with 0xf */ + if (adev->gfx.rlc.funcs->update_spm_vmid) + adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); +} + +void amdgpu_amdkfd_rlc_spm_interrupt(struct amdgpu_device *adev) +{ + if (adev->kfd.dev) + kgd2kfd_spm_interrupt(adev->kfd.dev); +} + diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h index 86d3fa7eef904..d35a095661329 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h @@ -156,6 +156,15 @@ struct amdgpu_kiq { void *mqd_backup; }; +struct spm_funcs { + void (*start)(struct amdgpu_device *adev); + void (*stop)(struct amdgpu_device *adev); + void (*set_rdptr)(struct amdgpu_device *adev, u32 rptr); + void (*set_spm_perfmon_ring_buf)(struct amdgpu_device *adev, u64 gpu_rptr, u32 size); + /* Packet sizes */ + int set_spm_config_size; +}; + /* * GFX configurations */ @@ -350,6 +359,7 @@ struct amdgpu_gfx { struct amdgpu_mec_bitmap mec_bitmap[AMDGPU_MAX_GC_INSTANCES]; struct amdgpu_kiq kiq[AMDGPU_MAX_GC_INSTANCES]; struct amdgpu_imu imu; + const struct spm_funcs *spmfuncs; bool rs64_enable; /* firmware format */ const struct firmware *me_fw; /* ME firmware */ uint32_t me_fw_version; @@ -393,6 +403,7 @@ struct amdgpu_gfx { struct amdgpu_irq_src priv_inst_irq; struct amdgpu_irq_src bad_op_irq; struct amdgpu_irq_src cp_ecc_error_irq; + struct amdgpu_irq_src spm_irq; struct amdgpu_irq_src sq_irq; struct amdgpu_irq_src rlc_gc_fed_irq; struct sq_work sq_work; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index e9c21ceb7d6f6..73abab6b4dde5 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -4733,6 +4733,13 @@ static int gfx_v10_0_sw_init(void *handle) if (r) return r; + /* SPM */ + r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_RLC, + GFX_10_1__SRCID__RLC_STRM_PERF_MONITOR_INTERRUPT, + &adev->gfx.spm_irq); + if (r) + return r; + /* EOP Event */ r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_EOP_INTERRUPT, @@ -7424,6 +7431,7 @@ static int gfx_v10_0_hw_fini(void *handle) amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); + amdgpu_irq_put(adev, &adev->gfx.spm_irq, 0); /* WA added for Vangogh asic fixing the SMU suspend failure * It needs to set power gating again during gfxoff control @@ -7677,6 +7685,95 @@ static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring, (1 << (oa_size + oa_base)) - (1 << oa_base)); } +static void gfx_v10_0_spm_start(struct amdgpu_device *adev) +{ + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + uint32_t data = 0; + + data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, 0); + data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1); + gfx_v10_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX), data); + + + data = RREG32_SOC15(GC, 0, mmRLC_SPM_PERFMON_CNTL); + data |= RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE_MASK; + gfx_v10_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_PERFMON_CNTL), data); + + data = REG_SET_FIELD(0, CP_PERFMON_CNTL, SPM_PERFMON_STATE, + CP_PERFMON_STATE_DISABLE_AND_RESET); + gfx_v10_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmCP_PERFMON_CNTL), data); + + data = REG_SET_FIELD(0, CP_PERFMON_CNTL, SPM_PERFMON_STATE, + STRM_PERFMON_STATE_START_COUNTING); + gfx_v10_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmCP_PERFMON_CNTL), data); + + gfx_v10_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_INT_CNTL), 1); +} + +static void gfx_v10_0_spm_stop(struct amdgpu_device *adev) +{ + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + uint32_t data = 0; + + data = REG_SET_FIELD(0, CP_PERFMON_CNTL, PERFMON_STATE, + CP_PERFMON_STATE_STOP_COUNTING); + gfx_v10_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmCP_PERFMON_CNTL), data); + + data = REG_SET_FIELD(0, CP_PERFMON_CNTL, SPM_PERFMON_STATE, + CP_PERFMON_STATE_DISABLE_AND_RESET); + gfx_v10_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmCP_PERFMON_CNTL), data); +} + +static void gfx_v10_0_spm_set_rdptr(struct amdgpu_device *adev, u32 rptr) +{ + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + + gfx_v10_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_RING_RDPTR), rptr); +} + +static void gfx_v10_0_set_spm_perfmon_ring_buf(struct amdgpu_device *adev, + u64 gpu_addr, u32 size) +{ + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + + gfx_v10_0_write_data_to_reg(kiq_ring, 0, false, SOC15_REG_OFFSET(GC, 0, + mmRLC_SPM_PERFMON_RING_BASE_LO), lower_32_bits(gpu_addr)); + + gfx_v10_0_write_data_to_reg(kiq_ring, 0, false, SOC15_REG_OFFSET(GC, + 0, mmRLC_SPM_PERFMON_RING_BASE_HI), upper_32_bits(gpu_addr)); + + gfx_v10_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_PERFMON_RING_SIZE), size); + + gfx_v10_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_SEGMENT_THRESHOLD), 0xff); + + gfx_v10_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmCP_PERFMON_CNTL), 0); +} + +static const struct spm_funcs gfx_v10_0_spm_funcs = { + .start = &gfx_v10_0_spm_start, + .stop = &gfx_v10_0_spm_stop, + .set_rdptr = &gfx_v10_0_spm_set_rdptr, + .set_spm_perfmon_ring_buf = &gfx_v10_0_set_spm_perfmon_ring_buf, + .set_spm_config_size = 30, +}; + +static void gfx_v10_0_set_spm_funcs(struct amdgpu_device *adev) +{ + adev->gfx.spmfuncs = &gfx_v10_0_spm_funcs; +} + + static int gfx_v10_0_early_init(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; @@ -7708,6 +7805,7 @@ static int gfx_v10_0_early_init(void *handle) adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), AMDGPU_MAX_COMPUTE_RINGS); + gfx_v10_0_set_spm_funcs(adev); gfx_v10_0_set_kiq_pm4_funcs(adev); gfx_v10_0_set_ring_funcs(adev); gfx_v10_0_set_irq_funcs(adev); @@ -7730,6 +7828,10 @@ static int gfx_v10_0_late_init(void *handle) if (r) return r; + r = amdgpu_irq_get(adev, &adev->gfx.spm_irq, 0); + if (r) + return r; + r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); if (r) return r; @@ -9550,6 +9652,32 @@ static void gfx_v10_ip_dump(void *handle) amdgpu_gfx_off_ctrl(adev, true); } +static int gfx_v10_0_spm_set_interrupt_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *src, + unsigned int type, + enum amdgpu_interrupt_state state) +{ + switch (state) { + case AMDGPU_IRQ_STATE_DISABLE: + WREG32_SOC15(GC, 0, mmRLC_SPM_INT_CNTL, 0); + break; + case AMDGPU_IRQ_STATE_ENABLE: + WREG32_SOC15(GC, 0, mmRLC_SPM_INT_CNTL, 1); + break; + default: + break; + } + return 0; +} + +static int gfx_v10_0_spm_irq(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + amdgpu_amdkfd_rlc_spm_interrupt(adev); + return 0; +} + static const struct amd_ip_funcs gfx_v10_0_ip_funcs = { .name = "gfx_v10_0", .early_init = gfx_v10_0_early_init, @@ -9727,6 +9855,11 @@ static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = { .process = gfx_v10_0_kiq_irq, }; +static const struct amdgpu_irq_src_funcs gfx_v10_0_spm_irq_funcs = { + .set = gfx_v10_0_spm_set_interrupt_state, + .process = gfx_v10_0_spm_irq, +}; + static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev) { adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; @@ -9735,6 +9868,9 @@ static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev) adev->gfx.kiq[0].irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST; adev->gfx.kiq[0].irq.funcs = &gfx_v10_0_kiq_irq_funcs; + adev->gfx.spm_irq.num_types = 1; + adev->gfx.spm_irq.funcs = &gfx_v10_0_spm_irq_funcs; + adev->gfx.priv_reg_irq.num_types = 1; adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index a1963e6c5cab1..e463628eddd87 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -1921,6 +1921,12 @@ static int gfx_v8_0_sw_init(void *handle) adev->gfx.mec.num_pipe_per_mec = 4; adev->gfx.mec.num_queue_per_pipe = 8; + /* SPM */ + r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, + VISLANDS30_IV_SRCID_RLC_STRM_PERF_MONITOR, &adev->gfx.spm_irq); + if (r) + return r; + /* EOP Event */ r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_END_OF_PIPE, &adev->gfx.eop_irq); if (r) @@ -4889,6 +4895,7 @@ static int gfx_v8_0_hw_fini(void *handle) amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0); amdgpu_irq_put(adev, &adev->gfx.sq_irq, 0); + amdgpu_irq_put(adev, &adev->gfx.spm_irq, 0); /* disable KCQ to avoid CPC touch memory not valid anymore */ gfx_v8_0_kcq_disable(adev); @@ -5254,6 +5261,97 @@ static const struct amdgpu_gfx_funcs gfx_v8_0_gfx_funcs = { .select_me_pipe_q = &gfx_v8_0_select_me_pipe_q }; +static void gfx_v8_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, + bool wc, uint32_t reg, uint32_t val) +{ + amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); + amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) | + WRITE_DATA_DST_SEL(0) | + (wc ? WR_CONFIRM : 0)); + amdgpu_ring_write(ring, reg); + amdgpu_ring_write(ring, 0); + amdgpu_ring_write(ring, val); +} + +static void gfx_v8_0_spm_start(struct amdgpu_device *adev) +{ + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + uint32_t data = 0; + + data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, 0); + data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1); + gfx_v8_0_write_data_to_reg(kiq_ring, 0, false, mmGRBM_GFX_INDEX, data); + + + data = RREG32(mmRLC_SPM_PERFMON_CNTL); + data |= RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE_MASK; + gfx_v8_0_write_data_to_reg(kiq_ring, 0, false, mmRLC_SPM_PERFMON_CNTL, data); + + data = REG_SET_FIELD(0, CP_PERFMON_CNTL, + SPM_PERFMON_STATE, CP_PERFMON_STATE_DISABLE_AND_RESET); + gfx_v8_0_write_data_to_reg(kiq_ring, 0, false, mmCP_PERFMON_CNTL, data); + + data = REG_SET_FIELD(0, CP_PERFMON_CNTL, + SPM_PERFMON_STATE, STRM_PERFMON_STATE_START_COUNTING); + gfx_v8_0_write_data_to_reg(kiq_ring, 0, false, mmCP_PERFMON_CNTL, data); + + gfx_v8_0_write_data_to_reg(kiq_ring, 0, false, mmRLC_SPM_INT_CNTL, 1); +} + +static void gfx_v8_0_spm_stop(struct amdgpu_device *adev) +{ + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + uint32_t data = 0; + + data = REG_SET_FIELD(0, CP_PERFMON_CNTL, + PERFMON_STATE, CP_PERFMON_STATE_STOP_COUNTING); + gfx_v8_0_write_data_to_reg(kiq_ring, 0, false, mmCP_PERFMON_CNTL, data); + + data = REG_SET_FIELD(0, CP_PERFMON_CNTL, + SPM_PERFMON_STATE, CP_PERFMON_STATE_DISABLE_AND_RESET); + gfx_v8_0_write_data_to_reg(kiq_ring, 0, false, mmCP_PERFMON_CNTL, data); +} + +static void gfx_v8_0_spm_set_rdptr(struct amdgpu_device *adev, u32 rptr) +{ + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + + gfx_v8_0_write_data_to_reg(kiq_ring, 0, false, mmRLC_SPM_RING_RDPTR, rptr); +} + +static void gfx_v8_0_set_spm_perfmon_ring_buf(struct amdgpu_device *adev, + u64 gpu_addr, u32 size) +{ + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + + gfx_v8_0_write_data_to_reg(kiq_ring, 0, false, + mmRLC_SPM_PERFMON_RING_BASE_LO, lower_32_bits(gpu_addr)); + + gfx_v8_0_write_data_to_reg(kiq_ring, 0, false, + mmRLC_SPM_PERFMON_RING_BASE_HI, upper_32_bits(gpu_addr)); + + gfx_v8_0_write_data_to_reg(kiq_ring, 0, false, + mmRLC_SPM_PERFMON_RING_SIZE, size); + + gfx_v8_0_write_data_to_reg(kiq_ring, 0, false, + mmRLC_SPM_SEGMENT_THRESHOLD, 0xff); + + gfx_v8_0_write_data_to_reg(kiq_ring, 0, false, mmCP_PERFMON_CNTL, 0); +} + +static const struct spm_funcs gfx_v8_0_spm_funcs = { + .start = &gfx_v8_0_spm_start, + .stop = &gfx_v8_0_spm_stop, + .set_rdptr = &gfx_v8_0_spm_set_rdptr, + .set_spm_perfmon_ring_buf = &gfx_v8_0_set_spm_perfmon_ring_buf, + .set_spm_config_size = 30, +}; + +static void gfx_v8_0_set_spm_funcs(struct amdgpu_device *adev) +{ + adev->gfx.spmfuncs = &gfx_v8_0_spm_funcs; +} + static int gfx_v8_0_early_init(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; @@ -5263,6 +5361,7 @@ static int gfx_v8_0_early_init(void *handle) adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), AMDGPU_MAX_COMPUTE_RINGS); adev->gfx.funcs = &gfx_v8_0_gfx_funcs; + gfx_v8_0_set_spm_funcs(adev); gfx_v8_0_set_ring_funcs(adev); gfx_v8_0_set_irq_funcs(adev); gfx_v8_0_set_gds_init(adev); @@ -5303,6 +5402,10 @@ static int gfx_v8_0_late_init(void *handle) return r; } + r = amdgpu_irq_get(adev, &adev->gfx.spm_irq, 0); + if (r) + return r; + return 0; } @@ -6796,6 +6899,31 @@ static void gfx_v8_0_emit_mem_sync_compute(struct amdgpu_ring *ring) amdgpu_ring_write(ring, 0x0000000A); /* poll interval */ } +static int gfx_v8_0_spm_set_interrupt_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *src, + unsigned int type, + enum amdgpu_interrupt_state state) +{ + switch (state) { + case AMDGPU_IRQ_STATE_DISABLE: + WREG32(mmRLC_SPM_INT_CNTL, 0); + break; + case AMDGPU_IRQ_STATE_ENABLE: + WREG32(mmRLC_SPM_INT_CNTL, 1); + break; + default: + break; + } + return 0; +} + +static int gfx_v8_0_spm_irq(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + amdgpu_amdkfd_rlc_spm_interrupt(adev); + return 0; +} /* mmSPI_WCL_PIPE_PERCENT_CS[0-7]_DEFAULT values are same */ #define mmSPI_WCL_PIPE_PERCENT_CS_DEFAULT 0x0000007f @@ -6853,7 +6981,6 @@ static void gfx_v8_0_emit_wave_limit(struct amdgpu_ring *ring, bool enable) gfx_v8_0_emit_wave_limit_cs(ring, i, enable); } - } static const struct amd_ip_funcs gfx_v8_0_ip_funcs = { @@ -7022,11 +7149,19 @@ static const struct amdgpu_irq_src_funcs gfx_v8_0_sq_irq_funcs = { .process = gfx_v8_0_sq_irq, }; +static const struct amdgpu_irq_src_funcs gfx_v8_0_spm_irq_funcs = { + .set = gfx_v8_0_spm_set_interrupt_state, + .process = gfx_v8_0_spm_irq, +}; + static void gfx_v8_0_set_irq_funcs(struct amdgpu_device *adev) { adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; adev->gfx.eop_irq.funcs = &gfx_v8_0_eop_irq_funcs; + adev->gfx.spm_irq.num_types = 1; + adev->gfx.spm_irq.funcs = &gfx_v8_0_spm_irq_funcs; + adev->gfx.priv_reg_irq.num_types = 1; adev->gfx.priv_reg_irq.funcs = &gfx_v8_0_priv_reg_irq_funcs; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index ab10a05c7885a..661df6aceccff 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -2177,6 +2177,13 @@ static int gfx_v9_0_sw_init(void *handle) adev->gfx.mec.num_pipe_per_mec = 4; adev->gfx.mec.num_queue_per_pipe = 8; + /* SPM */ + r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_RLC, + GFX_9_0__SRCID__RLC_STRM_PERF_MONITOR_INTERRUPT, + &adev->gfx.spm_irq); + if (r) + return r; + /* EOP Event */ r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq); if (r) @@ -3943,6 +3950,7 @@ static int gfx_v9_0_hw_fini(void *handle) if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0); amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); + amdgpu_irq_put(adev, &adev->gfx.spm_irq, 0); amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); amdgpu_irq_put(adev, &adev->gfx.bad_op_irq, 0); @@ -4682,6 +4690,87 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev) return r; } +static void gfx_v9_0_spm_start(struct amdgpu_device *adev) +{ + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + uint32_t data = 0; + + data = RREG32_SOC15(GC, 0, mmRLC_SPM_PERFMON_CNTL); + data |= RLC_SPM_PERFMON_CNTL__PERFMON_RING_MODE_MASK; + gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_PERFMON_CNTL), data); + + data = REG_SET_FIELD(0, CP_PERFMON_CNTL, SPM_PERFMON_STATE, + CP_PERFMON_STATE_DISABLE_AND_RESET); + gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmCP_PERFMON_CNTL), data); + + data = REG_SET_FIELD(0, CP_PERFMON_CNTL, SPM_PERFMON_STATE, + STRM_PERFMON_STATE_START_COUNTING); + gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmCP_PERFMON_CNTL), data); + + gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_INT_CNTL), 1); +} + +static void gfx_v9_0_spm_stop(struct amdgpu_device *adev) +{ + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + uint32_t data = 0; + + data = REG_SET_FIELD(0, CP_PERFMON_CNTL, SPM_PERFMON_STATE, + CP_PERFMON_STATE_STOP_COUNTING); + gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmCP_PERFMON_CNTL), data); + + data = REG_SET_FIELD(0, CP_PERFMON_CNTL, PERFMON_STATE, + CP_PERFMON_STATE_DISABLE_AND_RESET); + gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmCP_PERFMON_CNTL), data); +} + +static void gfx_v9_0_spm_set_rdptr(struct amdgpu_device *adev, u32 rptr) +{ + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + + gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_RING_RDPTR), rptr); +} + +static void gfx_v9_0_set_spm_perfmon_ring_buf(struct amdgpu_device *adev, u64 gpu_addr, u32 size) +{ + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + + gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, SOC15_REG_OFFSET(GC, 0, + mmRLC_SPM_PERFMON_RING_BASE_LO), lower_32_bits(gpu_addr)); + + gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, + mmRLC_SPM_PERFMON_RING_BASE_HI), upper_32_bits(gpu_addr)); + + gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_PERFMON_RING_SIZE), size); + gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_SEGMENT_THRESHOLD), 0xff); + + gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmCP_PERFMON_CNTL), 0); +} + +static const struct spm_funcs gfx_v9_0_spm_funcs = { + .start = &gfx_v9_0_spm_start, + .stop = &gfx_v9_0_spm_stop, + .set_rdptr = &gfx_v9_0_spm_set_rdptr, + .set_spm_perfmon_ring_buf = &gfx_v9_0_set_spm_perfmon_ring_buf, + .set_spm_config_size = 30, +}; + +static void gfx_v9_0_set_spm_funcs(struct amdgpu_device *adev) +{ + adev->gfx.spmfuncs = &gfx_v9_0_spm_funcs; +} + static int gfx_v9_0_early_init(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; @@ -4696,6 +4785,7 @@ static int gfx_v9_0_early_init(void *handle) adev->gfx.xcc_mask = 1; adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), AMDGPU_MAX_COMPUTE_RINGS); + gfx_v9_0_set_spm_funcs(adev); gfx_v9_0_set_kiq_pm4_funcs(adev); gfx_v9_0_set_ring_funcs(adev); gfx_v9_0_set_irq_funcs(adev); @@ -4751,6 +4841,10 @@ static int gfx_v9_0_late_init(void *handle) if (r) return r; + r = amdgpu_irq_get(adev, &adev->gfx.spm_irq, 0); + if (r) + return r; + r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); if (r) return r; @@ -7041,6 +7135,32 @@ static void gfx_v9_0_emit_mem_sync(struct amdgpu_ring *ring) amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ } +static int gfx_v9_0_spm_set_interrupt_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *src, + unsigned int type, + enum amdgpu_interrupt_state state) +{ + switch (state) { + case AMDGPU_IRQ_STATE_DISABLE: + WREG32(mmRLC_SPM_INT_CNTL, 0); + break; + case AMDGPU_IRQ_STATE_ENABLE: + WREG32(mmRLC_SPM_INT_CNTL, 1); + break; + default: + break; + } + return 0; +} + +static int gfx_v9_0_spm_irq(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + struct amdgpu_iv_entry *entry) +{ + amdgpu_amdkfd_rlc_spm_interrupt(adev); + return 0; +} + static void gfx_v9_0_emit_wave_limit_cs(struct amdgpu_ring *ring, uint32_t pipe, bool enable) { @@ -7436,12 +7556,19 @@ static const struct amdgpu_irq_src_funcs gfx_v9_0_cp_ecc_error_irq_funcs = { .process = amdgpu_gfx_cp_ecc_error_irq, }; +static const struct amdgpu_irq_src_funcs gfx_v9_0_spm_irq_funcs = { + .set = gfx_v9_0_spm_set_interrupt_state, + .process = gfx_v9_0_spm_irq, +}; static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev) { adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; adev->gfx.eop_irq.funcs = &gfx_v9_0_eop_irq_funcs; + adev->gfx.spm_irq.num_types = 1; + adev->gfx.spm_irq.funcs = &gfx_v9_0_spm_irq_funcs; + adev->gfx.priv_reg_irq.num_types = 1; adev->gfx.priv_reg_irq.funcs = &gfx_v9_0_priv_reg_irq_funcs; diff --git a/drivers/gpu/drm/amd/amdkfd/Makefile b/drivers/gpu/drm/amd/amdkfd/Makefile index 40dae27e387cd..e883770ade3f4 100644 --- a/drivers/gpu/drm/amd/amdkfd/Makefile +++ b/drivers/gpu/drm/amd/amdkfd/Makefile @@ -62,6 +62,7 @@ AMDKFD_FILES := $(AMDKFD_PATH)/kfd_module.o \ $(AMDKFD_PATH)/kfd_peerdirect.o \ $(AMDKFD_PATH)/kfd_ipc.o \ $(AMDKFD_PATH)/kfd_trace.o \ + $(AMDKFD_PATH)/kfd_spm.o \ $(AMDKFD_PATH)/kfd_debug.o ifneq ($(CONFIG_DEBUG_FS),) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 93768a23ca6a3..0ad01bf2b734f 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1821,6 +1821,12 @@ static int kfd_ioctl_svm(struct file *filep, struct kfd_process *p, void *data) } #endif +static int kfd_ioctl_rlc_spm(struct file *filep, + struct kfd_process *p, void *data) +{ + return kfd_rlc_spm(p, data); +} + static int criu_checkpoint_process(struct kfd_process *p, uint8_t __user *user_priv_data, uint64_t *priv_offset) @@ -3297,6 +3303,10 @@ static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = { AMDKFD_IOCTL_DEF(AMDKFD_IOC_IPC_EXPORT_HANDLE, kfd_ioctl_ipc_export_handle, 0), + + AMDKFD_IOCTL_DEF(AMDKFD_IOC_RLC_SPM, + kfd_ioctl_rlc_spm, 0), + }; static long kfd_ioctl(struct file *filep, unsigned int cmd, unsigned long arg) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 8f01c69316dce..ad74b18fb0e16 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -371,6 +371,9 @@ struct kfd_dev { /* Compute Profile ref. count */ atomic_t compute_profile; + /*spm process id */ + unsigned int spm_pasid; + /* * A bitmask to indicate which watch points have been allocated. * bit meaning: @@ -831,6 +834,12 @@ struct kfd_process_device { struct attribute attr_sdma; char sdma_filename[MAX_SYSFS_FILENAME_LEN]; + /* spm data */ + struct kfd_spm_cntr *spm_cntr; + struct mutex spm_mutex; + struct work_struct spm_work; + spinlock_t spm_irq_lock; + /* Eviction activity tracking */ uint64_t last_evict_timestamp; atomic64_t evict_duration_counter; @@ -1574,6 +1583,9 @@ int kfd_send_exception_to_runtime(struct kfd_process *p, uint64_t error_reason); bool kfd_is_locked(void); +void kfd_spm_init_process_device(struct kfd_process_device *pdd); +int kfd_rlc_spm(struct kfd_process *p, void __user *data); + /* PeerDirect support */ void kfd_init_peer_direct(void); void kfd_close_peer_direct(void); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c new file mode 100644 index 0000000000000..d9856191ab7eb --- /dev/null +++ b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c @@ -0,0 +1,462 @@ +/* + * Copyright 2020 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include +#include "kfd_priv.h" +#include "amdgpu_amdkfd.h" +#include "amdgpu_irq.h" +#include "ivsrcid/gfx/irqsrcs_gfx_9_0.h" +#include "ivsrcid/ivsrcid_vislands30.h" +#include // for use_mm() +#include + +struct user_buf { + uint64_t __user *user_addr; + u32 ubufsize; +}; + +struct kfd_spm_cntr { + struct user_buf ubuf; + struct mutex spm_worker_mutex; + u64 gpu_addr; + u32 ring_size; + u32 ring_mask; + u32 ring_rptr; + u32 size_copied; + u32 has_data_loss; + u32 *cpu_addr; + void *spm_obj; + wait_queue_head_t spm_buf_wq; + bool has_user_buf; + bool is_user_buf_filled; + bool is_spm_started; +}; + +static int kfd_spm_data_copy(struct kfd_process_device *pdd, u32 size_to_copy) +{ + struct kfd_spm_cntr *spm = pdd->spm_cntr; + uint64_t __user *user_address; + uint64_t *ring_buf; + u32 user_buf_space_left; + int ret = 0; + + if (spm->ubuf.user_addr == NULL) + return -EFAULT; + + user_address = (uint64_t *)((uint64_t)spm->ubuf.user_addr + spm->size_copied); + ring_buf = (uint64_t *)((uint64_t)spm->cpu_addr + spm->ring_rptr); + + if (user_address == NULL) + return -EFAULT; + + user_buf_space_left = spm->ubuf.ubufsize - spm->size_copied; + + if (size_to_copy < user_buf_space_left) { + ret = copy_to_user(user_address, ring_buf, size_to_copy); + if (ret) { + spm->has_data_loss = true; + return -EFAULT; + } + spm->size_copied += size_to_copy; + spm->ring_rptr += size_to_copy; + } else { + ret = copy_to_user(user_address, ring_buf, user_buf_space_left); + if (ret) { + spm->has_data_loss = true; + return -EFAULT; + } + + spm->size_copied = spm->ubuf.ubufsize; + spm->ring_rptr += user_buf_space_left; + WRITE_ONCE(spm->is_user_buf_filled, true); + wake_up(&pdd->spm_cntr->spm_buf_wq); + } + + return ret; +} + +static int kfd_spm_read_ring_buffer(struct kfd_process_device *pdd) +{ + struct kfd_spm_cntr *spm = pdd->spm_cntr; + u32 size_to_copy; + int ret = 0; + u32 ring_wptr; + + ring_wptr = READ_ONCE(spm->cpu_addr[0]) & spm->ring_mask; + + /* keep SPM ring buffer running */ + if (!spm->has_user_buf || spm->is_user_buf_filled) { + spm->ring_rptr = ring_wptr; + spm->has_data_loss = true; + /* set flag due to there is no flag setup + * when read ring buffer timeout. + */ + if (!spm->is_user_buf_filled) + spm->is_user_buf_filled = true; + goto exit; + } + + if (spm->ring_rptr == ring_wptr) + goto exit; + + if ((spm->ring_rptr >= 0) && (spm->ring_rptr < 0x20)) { + /* + * First 8DW, only use for WritePtr, it is not Counter data + */ + spm->ring_rptr = 0x20; + } + + if (ring_wptr > spm->ring_rptr) { + size_to_copy = ring_wptr - spm->ring_rptr; + ret = kfd_spm_data_copy(pdd, size_to_copy); + } else { + size_to_copy = spm->ring_size - spm->ring_rptr; + ret = kfd_spm_data_copy(pdd, size_to_copy); + + /* correct counter start point */ + if (spm->ring_size == spm->ring_rptr) { + if (ring_wptr == 0) { + /* reset rptr to start point of ring buffer */ + spm->ring_rptr = ring_wptr; + goto exit; + } + spm->ring_rptr = 0x20; + size_to_copy = ring_wptr - spm->ring_rptr; + if (!ret) + ret = kfd_spm_data_copy(pdd, size_to_copy); + } + } + +exit: + amdgpu_amdkfd_rlc_spm_set_rdptr(pdd->dev->kgd, spm->ring_rptr); + return ret; +} + +static void kfd_spm_work(struct work_struct *work) +{ + struct kfd_process_device *pdd = container_of(work, struct kfd_process_device, spm_work); + struct mm_struct *mm = NULL; // referenced + + mm = get_task_mm(pdd->process->lead_thread); + if (mm) { + kthread_use_mm(mm); + { /* attach mm */ + mutex_lock(&pdd->spm_cntr->spm_worker_mutex); + kfd_spm_read_ring_buffer(pdd); + mutex_unlock(&pdd->spm_cntr->spm_worker_mutex); + } /* detach mm */ + kthread_unuse_mm(mm); + /* release the mm structure */ + mmput(mm); + } +} + +void kfd_spm_init_process_device(struct kfd_process_device *pdd) +{ + mutex_init(&pdd->spm_mutex); + pdd->spm_cntr = NULL; +} + +static int kfd_acquire_spm(struct kfd_process_device *pdd, struct kgd_dev *kgd) +{ + int ret = 0; + + mutex_lock(&pdd->spm_mutex); + + if (pdd->spm_cntr) { + mutex_unlock(&pdd->spm_mutex); + return -EINVAL; + } + + pdd->spm_cntr = kzalloc(sizeof(struct kfd_spm_cntr), GFP_KERNEL); + if (!pdd->spm_cntr) { + mutex_unlock(&pdd->spm_mutex); + return -ENOMEM; + } + mutex_unlock(&pdd->spm_mutex); + + /* git spm ring buffer 4M */ + pdd->spm_cntr->ring_size = order_base_2(4 * 1024 * 1024/4); + pdd->spm_cntr->ring_size = (1 << pdd->spm_cntr->ring_size) * 4 - 0xff; + pdd->spm_cntr->ring_mask = pdd->spm_cntr->ring_size - 1; + pdd->spm_cntr->has_user_buf = false; + + ret = amdgpu_amdkfd_alloc_gtt_mem(kgd, + pdd->spm_cntr->ring_size, &pdd->spm_cntr->spm_obj, + &pdd->spm_cntr->gpu_addr, (void *)&pdd->spm_cntr->cpu_addr, + false, false); + + if (ret) + goto alloc_gtt_mem_failure; + + ret = amdgpu_amdkfd_rlc_spm_acquire(kgd, pdd->vm, + pdd->spm_cntr->gpu_addr, pdd->spm_cntr->ring_size); + + /* + * By definition, the last 8 DWs of the buffer are not part of the rings + * and are instead part of the Meta data area. + */ + pdd->spm_cntr->ring_size -= 0x20; + + if (ret) + goto acquire_spm_failure; + + mutex_init(&pdd->spm_cntr->spm_worker_mutex); + + init_waitqueue_head(&pdd->spm_cntr->spm_buf_wq); + INIT_WORK(&pdd->spm_work, kfd_spm_work); + + spin_lock_init(&pdd->spm_irq_lock); + + goto out; + +acquire_spm_failure: + amdgpu_amdkfd_free_gtt_mem(kgd, pdd->spm_cntr->spm_obj); + +alloc_gtt_mem_failure: + mutex_lock(&pdd->spm_mutex); + kfree(pdd->spm_cntr); + pdd->spm_cntr = NULL; + mutex_unlock(&pdd->spm_mutex); + +out: + return ret; +} + +static int kfd_release_spm(struct kfd_process_device *pdd, struct kgd_dev *kgd) +{ + unsigned long flags; + + mutex_lock(&pdd->spm_mutex); + if (!pdd->spm_cntr) { + mutex_unlock(&pdd->spm_mutex); + return -EINVAL; + } + + spin_lock_irqsave(&pdd->spm_irq_lock, flags); + pdd->spm_cntr->is_spm_started = false; + spin_unlock_irqrestore(&pdd->spm_irq_lock, flags); + + flush_work(&pdd->spm_work); + wake_up_all(&pdd->spm_cntr->spm_buf_wq); + + amdgpu_amdkfd_rlc_spm_release(kgd, pdd->vm); + amdgpu_amdkfd_free_gtt_mem(kgd, pdd->spm_cntr->spm_obj); + + spin_lock_irqsave(&pdd->spm_irq_lock, flags); + kfree(pdd->spm_cntr); + pdd->spm_cntr = NULL; + spin_unlock_irqrestore(&pdd->spm_irq_lock, flags); + + mutex_unlock(&pdd->spm_mutex); + return 0; +} + +static void spm_copy_data_to_usr(struct kfd_ioctl_spm_args *user_spm_data, + struct kfd_process_device *pdd) +{ + mutex_lock(&pdd->spm_cntr->spm_worker_mutex); + user_spm_data->bytes_copied = pdd->spm_cntr->size_copied; + user_spm_data->has_data_loss = pdd->spm_cntr->has_data_loss; + pdd->spm_cntr->has_user_buf = false; + mutex_unlock(&pdd->spm_cntr->spm_worker_mutex); +} + +static void spm_set_dest_info(struct kfd_process_device *pdd, + struct kfd_ioctl_spm_args *user_spm_data) +{ + mutex_lock(&pdd->spm_cntr->spm_worker_mutex); + pdd->spm_cntr->ubuf.user_addr = (uint64_t *)user_spm_data->dest_buf; + pdd->spm_cntr->ubuf.ubufsize = user_spm_data->buf_size; + pdd->spm_cntr->has_data_loss = false; + pdd->spm_cntr->size_copied = 0; + pdd->spm_cntr->is_user_buf_filled = false; + pdd->spm_cntr->has_user_buf = true; + mutex_unlock(&pdd->spm_cntr->spm_worker_mutex); +} + +static int spm_wait_for_fill_awake(struct kfd_spm_cntr *spm, + struct kfd_ioctl_spm_args *user_spm_data) +{ + int ret = 0; + + long timeout = msecs_to_jiffies(user_spm_data->timeout); + long start_jiffies = jiffies; + + ret = wait_event_interruptible_timeout(spm->spm_buf_wq, + (READ_ONCE(spm->is_user_buf_filled) == true), + timeout); + + switch (ret) { + case -ERESTARTSYS: + /* Subtract elapsed time from timeout so we wait that much + * less when the call gets restarted. + */ + timeout -= (jiffies - start_jiffies); + if (timeout <= 0) { + ret = -ETIME; + timeout = 0; + pr_debug("[%s] interrupted by signal\n", __func__); + } + break; + + case 0: + default: + timeout = ret; + ret = 0; + break; + } + user_spm_data->timeout = jiffies_to_msecs(timeout); + + return ret; +} + +static int kfd_set_dest_buffer(struct kfd_process_device *pdd, struct kgd_dev *kgd, void *data) +{ + struct kfd_ioctl_spm_args *user_spm_data; + struct kfd_spm_cntr *spm; + unsigned long flags; + int ret = 0; + + user_spm_data = (struct kfd_ioctl_spm_args *) data; + + mutex_lock(&pdd->spm_mutex); + spm = pdd->spm_cntr; + + if (spm == NULL) { + mutex_unlock(&pdd->spm_mutex); + return -EINVAL; + } + + if (user_spm_data->timeout && spm->has_user_buf && + !READ_ONCE(spm->is_user_buf_filled)) { + ret = spm_wait_for_fill_awake(spm, user_spm_data); + if (ret == -ETIME) { + /* Copy (partial) data to user buffer after a timeout */ + schedule_work(&pdd->spm_work); + flush_work(&pdd->spm_work); + /* This is not an error */ + ret = 0; + } else if (ret) { + /* handle other errors normally, including -ERESTARTSYS */ + mutex_unlock(&pdd->spm_mutex); + return ret; + } + } else if (!user_spm_data->timeout && spm->has_user_buf) { + /* Copy (partial) data to user buffer */ + schedule_work(&pdd->spm_work); + flush_work(&pdd->spm_work); + } + + if (spm->has_user_buf) { + /* get info about filled space in previous output buffer */ + spm_copy_data_to_usr(user_spm_data, pdd); + } + + if (user_spm_data->dest_buf) { + /* setup new dest buf, start streaming if necessary */ + spm_set_dest_info(pdd, user_spm_data); + + /* Start SPM */ + if (spm->is_spm_started == false) { + amdgpu_amdkfd_rlc_spm_cntl(kgd, 1); + spin_lock_irqsave(&pdd->spm_irq_lock, flags); + spm->is_spm_started = true; + spin_unlock_irqrestore(&pdd->spm_irq_lock, flags); + } else { + /* If SPM was already started, there may already + * be data in the ring-buffer that needs to be read. + */ + schedule_work(&pdd->spm_work); + } + } else { + amdgpu_amdkfd_rlc_spm_cntl(kgd, 0); + spin_lock_irqsave(&pdd->spm_irq_lock, flags); + spm->is_spm_started = false; + spin_unlock_irqrestore(&pdd->spm_irq_lock, flags); + } + + mutex_unlock(&pdd->spm_mutex); + + return ret; +} + +int kfd_rlc_spm(struct kfd_process *p, void *data) +{ + struct kfd_ioctl_spm_args *args = data; + struct kfd_dev *dev; + struct kfd_process_device *pdd; + + dev = kfd_device_by_id(args->gpu_id); + if (!dev) { + pr_debug("Could not find gpu id 0x%x\n", args->gpu_id); + return -EINVAL; + } + + pdd = kfd_get_process_device_data(dev, p); + if (!pdd) + return -EINVAL; + + switch (args->op) { + case KFD_IOCTL_SPM_OP_ACQUIRE: + dev->spm_pasid = p->pasid; + return kfd_acquire_spm(pdd, dev->kgd); + + case KFD_IOCTL_SPM_OP_RELEASE: + return kfd_release_spm(pdd, dev->kgd); + + case KFD_IOCTL_SPM_OP_SET_DEST_BUF: + return kfd_set_dest_buffer(pdd, dev->kgd, data); + + default: + return -EINVAL; + } + + return -EINVAL; +} + +void kgd2kfd_spm_interrupt(struct kfd_dev *dev) +{ + struct kfd_process_device *pdd; + uint16_t pasid = dev->spm_pasid; + + struct kfd_process *p = kfd_lookup_process_by_pasid(pasid); + unsigned long flags; + + if (!p) { + pr_debug("kfd_spm_interrupt p = %p\n", p); + return; /* Presumably process exited. */ + } + + pdd = kfd_get_process_device_data(dev, p); + if (!pdd) + return; + + spin_lock_irqsave(&pdd->spm_irq_lock, flags); + + if (pdd->spm_cntr && pdd->spm_cntr->is_spm_started) + schedule_work(&pdd->spm_work); + spin_unlock_irqrestore(&pdd->spm_irq_lock, flags); + + kfd_unref_process(p); +} + diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h index 04ba10ee1ad7b..03de8ab6dfe5c 100644 --- a/include/uapi/linux/kfd_ioctl.h +++ b/include/uapi/linux/kfd_ioctl.h @@ -580,6 +580,81 @@ struct kfd_ioctl_smi_events_args { __u32 anon_fd; /* from KFD */ }; +/** + * kfd_ioctl_spm_op - SPM ioctl operations + * + * @KFD_IOCTL_SPM_OP_ACQUIRE: acquire exclusive access to SPM + * @KFD_IOCTL_SPM_OP_RELEASE: release exclusive access to SPM + * @KFD_IOCTL_SPM_OP_SET_DEST_BUF: set or unset destination buffer for SPM streaming + */ +enum kfd_ioctl_spm_op { + KFD_IOCTL_SPM_OP_ACQUIRE, + KFD_IOCTL_SPM_OP_RELEASE, + KFD_IOCTL_SPM_OP_SET_DEST_BUF +}; + +/** + * kfd_ioctl_spm_args - Arguments for SPM ioctl + * + * @op[in]: specifies the operation to perform + * @gpu_id[in]: GPU ID of the GPU to profile + * @dst_buf[in]: used for the address of the destination buffer + * in @KFD_IOCTL_SPM_SET_DEST_BUFFER + * @buf_size[in]: size of the destination buffer + * @timeout[in/out]: [in]: timeout in milliseconds, [out]: amount of time left + * `in the timeout window + * @bytes_copied[out]: amount of data that was copied to the previous dest_buf + * @has_data_loss: boolean indicating whether data was lost + * (e.g. due to a ring-buffer overflow) + * + * This ioctl performs different functions depending on the @op parameter. + * + * KFD_IOCTL_SPM_OP_ACQUIRE + * ------------------------ + * + * Acquires exclusive access of SPM on the specified @gpu_id for the calling process. + * This must be called before using KFD_IOCTL_SPM_OP_SET_DEST_BUF. + * + * KFD_IOCTL_SPM_OP_RELEASE + * ------------------------ + * + * Releases exclusive access of SPM on the specified @gpu_id for the calling process, + * which allows another process to acquire it in the future. + * + * KFD_IOCTL_SPM_OP_SET_DEST_BUF + * ----------------------------- + * + * If @dst_buf is NULL, the destination buffer address is unset and copying of counters + * is stopped. + * + * If @dst_buf is not NULL, it specifies the pointer to a new destination buffer. + * @buf_size specifies the size of the buffer. + * + * If @timeout is non-0, the call will wait for up to @timeout ms for the previous + * buffer to be filled. If previous buffer to be filled before timeout, the @timeout + * will be updated value with the time remaining. If the timeout is exceeded, the function + * copies any partial data available into the previous user buffer and returns success. + * The amount of valid data in the previous user buffer is indicated by @bytes_copied. + * + * If @timeout is 0, the function immediately replaces the previous destination buffer + * without waiting for the previous buffer to be filled. That means the previous buffer + * may only be partially filled, and @bytes_copied will indicate how much data has been + * copied to it. + * + * If data was lost, e.g. due to a ring buffer overflow, @has_data_loss will be non-0. + * + * Returns negative error code on failure, 0 on success. + */ +struct kfd_ioctl_spm_args { + __u64 dest_buf; + __u32 buf_size; + __u32 op; + __u32 timeout; + __u32 gpu_id; + __u32 bytes_copied; + __u32 has_data_loss; +}; + /************************************************************************************************** * CRIU IOCTLs (Checkpoint Restore In Userspace) * @@ -655,7 +730,6 @@ struct kfd_criu_bo_bucket { /* CRIU IOCTLs - END */ /**************************************************************************************************/ - /* Register offset inside the remapped mmio page */ enum kfd_mmio_remap { @@ -1621,7 +1695,10 @@ struct kfd_ioctl_dbg_trap_args { #define AMDKFD_IOC_IPC_EXPORT_HANDLE \ AMDKFD_IOWR(0x81, struct kfd_ioctl_ipc_export_handle_args) +#define AMDKFD_IOC_RLC_SPM \ + AMDKFD_IOWR(0x84, struct kfd_ioctl_spm_args) + #define AMDKFD_COMMAND_START_2 0x80 -#define AMDKFD_COMMAND_END_2 0x84 +#define AMDKFD_COMMAND_END_2 0x85 #endif From 2abad11462833c981f3628f36169745fe5b128b8 Mon Sep 17 00:00:00 2001 From: Guchun Chen Date: Thu, 7 Jan 2021 13:54:26 +0800 Subject: [PATCH 0213/1868] Revert "drm/amd/pm: typo fix (CUSTOM -> COMPUTE)" This reverts commit 11a4d4b89bfd7981aeb765683e1c5f7222f645f5. It breaks one test. Root cause identifying is still on the way. Signed-off-by: Guchun Chen --- drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c index 9c3c48297cba0..727fed69fc38c 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c @@ -250,7 +250,7 @@ static struct cmn2asic_mapping sienna_cichlid_workload_map[PP_SMC_POWER_PROFILE_ WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT), WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT), WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT), - WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT), + WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_CUSTOM_BIT), WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT), }; From 17facde9bba1116270128bbe6204237119b7ad22 Mon Sep 17 00:00:00 2001 From: Gang Ba Date: Thu, 14 Jan 2021 22:54:39 -0500 Subject: [PATCH 0214/1868] drm/amdkfd: Create indirect links Create GPU<->CPU indirect IO links Signed-off-by: Gang Ba Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index 061d75c29fcb2..112174322c16c 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -1421,6 +1421,20 @@ static void kfd_fill_iolink_non_crat_info(struct kfd_topology_device *dev) kfd_set_iolink_non_coherent(peer_dev, link, inbound_link); } } + + /* Create CPU<->GPU indirect links so apply flags setting to all */ + list_for_each_entry(link, &dev->p2p_link_props, list) { + cpu_dev = kfd_topology_device_by_proximity_domain( + link->node_to); + if (cpu_dev && !cpu_dev->gpu) { + list_for_each_entry(cpu_link, + &cpu_dev->p2p_link_props, list) + if (cpu_link->node_to == link->node_from) { + link->flags = flag; + cpu_link->flags = cpu_flag; + } + } + } } static int kfd_build_p2p_node_entry(struct kfd_topology_device *dev, From e2f57390b7d2cb1e91b1a3655664e73b098cc78f Mon Sep 17 00:00:00 2001 From: Philip Cox Date: Tue, 17 Nov 2020 11:05:36 -0500 Subject: [PATCH 0215/1868] drm/amdkfd: Change kfd debugger to use PID. Rework the kfd debugger API to use PID rather than the device id. Debugging actions are now on all devices, rather than a single device. Change-Id: Ie2a18a0299176b6a68c23113da057c7f7746c3a6 Signed-off-by: Philip Cox Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 6 ------ drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 19 ------------------- include/uapi/linux/kfd_ioctl.h | 2 +- 3 files changed, 1 insertion(+), 26 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 0ad01bf2b734f..5e12b2786fcc8 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1510,12 +1510,6 @@ static int kfd_ioctl_alloc_queue_gws(struct file *filep, goto out_unlock; } - pdd = kfd_bind_process_to_device(dev, p); - if (IS_ERR(pdd)) { - retval = -ESRCH; - goto out_unlock; - } - if (!dev->gws) { retval = -ENODEV; goto out_unlock; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index ad74b18fb0e16..d36e91dd69fa5 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -374,15 +374,6 @@ struct kfd_dev { /*spm process id */ unsigned int spm_pasid; - /* - * A bitmask to indicate which watch points have been allocated. - * bit meaning: - * 0: unallocated/available - * 1: allocated/unavailable - */ - uint32_t allocated_debug_watch_points; - spinlock_t watch_points_lock; - struct ida doorbell_ida; unsigned int max_doorbell_slices; @@ -1597,16 +1588,6 @@ int kfd_ipc_init(void); void kfd_inc_compute_active(struct kfd_node *dev); void kfd_dec_compute_active(struct kfd_node *dev); -/* Allocate and free watch point IDs for debugger */ -int kfd_allocate_debug_watch_point(struct kfd_dev *kfd, - uint64_t watch_address, - uint32_t watch_address_mask, - uint32_t *watch_point, - uint32_t watch_mode, - uint32_t debug_vmid); -int kfd_release_debug_watch_points(struct kfd_dev *kfd, - uint32_t watch_point_bit_mask_to_free); - /* Cgroup Support */ /* Check with device cgroup if @kfd device is accessible */ static inline int kfd_devcgroup_check_permission(struct kfd_node *node) diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h index 03de8ab6dfe5c..f77bed0e59603 100644 --- a/include/uapi/linux/kfd_ioctl.h +++ b/include/uapi/linux/kfd_ioctl.h @@ -245,11 +245,11 @@ struct kfd_ioctl_dbg_wave_control_args { struct kfd_ioctl_dbg_trap_args { __u64 ptr; /* to KFD -- used for pointer arguments: queue arrays */ __u32 pid; /* to KFD */ - __u32 gpu_id; /* to KFD */ __u32 op; /* to KFD */ __u32 data1; /* to KFD */ __u32 data2; /* to KFD */ __u32 data3; /* to KFD */ + __u32 data4; /* to KFD */ }; /* Matching HSA_EVENTTYPE */ From ef0b7d41228b05dff4b5468e8ffa90bf69adbe8f Mon Sep 17 00:00:00 2001 From: Jonathan Kim Date: Tue, 19 Jan 2021 23:45:47 -0500 Subject: [PATCH 0216/1868] drm/amdkfd: enable exception code reporting to the debugger Report EC_TRAP_HANDLER (debug notifier only at the moment), EC_QUEUE_NEW, EC_QUEUE_DELETE and EC_MEMORY_VIOLATION to the debugger with the new exception code features. Signed-off-by: Jonathan Kim Reviewed-by: Felix Kuehling --- include/uapi/linux/kfd_ioctl.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h index f77bed0e59603..b879fa06f4a8a 100644 --- a/include/uapi/linux/kfd_ioctl.h +++ b/include/uapi/linux/kfd_ioctl.h @@ -243,6 +243,7 @@ struct kfd_ioctl_dbg_wave_control_args { #define KFD_INVALID_FD 0xffffffff struct kfd_ioctl_dbg_trap_args { + __u64 exception_mask; /* to KFD */ __u64 ptr; /* to KFD -- used for pointer arguments: queue arrays */ __u32 pid; /* to KFD */ __u32 op; /* to KFD */ From f032931671e32bbffa4dc283592cb9b7d462c269 Mon Sep 17 00:00:00 2001 From: Jonathan Kim Date: Fri, 5 Mar 2021 08:40:03 -0500 Subject: [PATCH 0217/1868] drm/amdkfd: change process evict/restore prints to pr_debug Revert the following: 'commit e1d6df2f7361e49e911ba97b337fe95cd779f13e ("drm/amdkfd: silence process restore on arcturus debug attach/detach")' Change pr_info to pr_debug for process eviction and restore print outs now that these events are being traced. Signed-off-by: Jonathan Kim Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index d60c493fa1966..c370395287b0d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -2149,7 +2149,7 @@ static void evict_process_worker(struct work_struct *work) msecs_to_jiffies(PROCESS_RESTORE_TIME_MS))) kfd_process_restore_queues(p); - pr_info("Finished evicting pasid 0x%x\n", p->pasid); + pr_debug("Finished evicting pasid 0x%x\n", p->pasid); } else pr_err("Failed to evict queues of pasid 0x%x\n", p->pasid); trace_kfd_evict_process_worker_end(p, ret ? "Failed" : "Success"); @@ -2189,7 +2189,7 @@ static void restore_process_worker(struct work_struct *work) * lifetime of this thread, kfd_process p will be valid */ p = container_of(dwork, struct kfd_process, restore_work); - pr_info("Started restoring pasid 0x%x\n", p->pasid); + pr_debug("Started restoring pasid 0x%x\n", p->pasid); trace_kfd_restore_process_worker_start(p); /* Setting last_restore_timestamp before successful restoration. @@ -2206,7 +2206,7 @@ static void restore_process_worker(struct work_struct *work) ret = restore_process_helper(p); if (ret) { - pr_info("Failed to restore BOs of pasid 0x%x, retry after %d ms\n", + pr_debug("Failed to restore BOs of pasid 0x%x, retry after %d ms\n", p->pasid, PROCESS_BACK_OFF_TIME_MS); if (mod_delayed_work(kfd_restore_wq, &p->restore_work, msecs_to_jiffies(PROCESS_RESTORE_TIME_MS))) From dfe69a8b1c174f211aeb6b66f0df335dcc638959 Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Wed, 22 Apr 2020 21:43:26 +0800 Subject: [PATCH 0218/1868] drm/amdkcl: test drm_driver->gem_prime_export() This is a squash of: drm/amdkcl: fix test for drm_gem_prime_export() Reviewed-by: Guchun Chen Signed-off-by: Flora Cui Signed-off-by: Yifan Zhang Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 10 ++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h | 5 +++++ .../drm/amd/dkms/m4/drm-drv-gem-prime-export.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 32 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-drv-gem-prime-export.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index 0656f0da465c6..16862e62dd3bf 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -450,7 +450,12 @@ const struct dma_buf_ops amdgpu_dmabuf_ops = { * Returns: * Shared DMA buffer representing the GEM BO from the given device. */ +#ifdef HAVE_DRM_DRV_GEM_PRIME_EXPORT_PI struct dma_buf *amdgpu_gem_prime_export(struct drm_gem_object *gobj, +#else +struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev, + struct drm_gem_object *gobj, +#endif int flags) { struct amdgpu_bo *bo = gem_to_amdgpu_bo(gobj); @@ -460,7 +465,12 @@ struct dma_buf *amdgpu_gem_prime_export(struct drm_gem_object *gobj, bo->flags & AMDGPU_GEM_CREATE_VM_ALWAYS_VALID) return ERR_PTR(-EPERM); +#ifdef HAVE_DRM_DRV_GEM_PRIME_EXPORT_PI buf = drm_gem_prime_export(gobj, flags); +#else + buf = drm_gem_prime_export(dev, gobj, flags); +#endif + #if defined(AMDKCL_AMDGPU_DMABUF_OPS) if (!IS_ERR(buf)) buf->ops = &amdgpu_dmabuf_ops; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h index db75327913c95..f7a7492b68f55 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h @@ -34,7 +34,12 @@ amdgpu_gem_prime_import_sg_table(struct drm_device *dev, struct sg_table *sg); #endif +#ifdef HAVE_DRM_DRV_GEM_PRIME_EXPORT_PI struct dma_buf *amdgpu_gem_prime_export(struct drm_gem_object *gobj, +#else +struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev, + struct drm_gem_object *gobj, +#endif int flags); #if defined(AMDKCL_AMDGPU_DMABUF_OPS) struct drm_gem_object *amdgpu_gem_prime_import(struct drm_device *dev, diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-drv-gem-prime-export.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-drv-gem-prime-export.m4 new file mode 100644 index 0000000000000..bac95ca04518c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-drv-gem-prime-export.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.2-rc5-870-ge4fa8457b219 +dnl # drm/prime: Align gem_prime_export with obj_funcs.export +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DRV_GEM_PRIME_EXPORT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + drm_gem_prime_export(NULL, 0); + ],[ + AC_DEFINE(HAVE_DRM_DRV_GEM_PRIME_EXPORT_PI, 1, + [drm_gem_prime_export() with p,i arg is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index cceaf0c361193..268ac6b8672e3 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -64,6 +64,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_CEC_CORRELATION_FUNCTIONS AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_RESUME AC_AMDGPU_DRM_DRIVER_GEM_PRIME_RES_OBJ + AC_AMDGPU_DRM_DRV_GEM_PRIME_EXPORT AC_AMDGPU___DRM_ATOMIC_HELPER_CRTC_RESET AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION AC_AMDGPU_MEM_ENCRYPT_ACTIVE From a47573351aeb5c283d569f31cb647bd08dea44ee Mon Sep 17 00:00:00 2001 From: Anatoli Antonovitch Date: Wed, 26 Jun 2019 15:20:19 -0400 Subject: [PATCH 0219/1868] drm/amdkcl: Test whether ttm_bo_vm_fault() wants 2 args v2: Test whether vm_fault->{address/vma} is available v3: fix intree failure due to vmf->vma kcl wrapper v4: refactor test for vm_operations_struct->fault() Signed-off-by: Anatoli Antonovitch Signed-off-by: Yifan Zhang Signed-off-by: Jack Gui Signed-off-by: Chengming Gui Reviewed-by: Flora Cui Signed-off-by: Jack Gui Signed-off-by: Flora Cui Reviewed-by: Jack Gui Signed-off-by: Jack Gui Reviewed-by: Jiansong Chen Signed-off-by: Flora Cui Reviewed-by: Feifei Xu Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c | 8 +++- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../drm/amd/dkms/m4/vm_operations_struct.m4 | 35 +++++++++++++++ drivers/gpu/drm/ttm/ttm_bo_vm.c | 45 ++++++++++++++++--- include/drm/ttm/ttm_bo.h | 19 ++++++++ 5 files changed, 102 insertions(+), 6 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/vm_operations_struct.m4 diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c b/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c index cc97f392c90af..cbd0d109ea883 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c @@ -128,9 +128,15 @@ static void kfd_doorbell_close(struct vm_area_struct *vma) mutex_unlock(&pdd->qpd.doorbell_lock); } +#ifdef HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG static vm_fault_t kfd_doorbell_vm_fault(struct vm_fault *vmf) { - struct kfd_process_device *pdd = vmf->vma->vm_private_data; + struct vm_area_struct *vma = vmf->vma; +#else +static int kfd_doorbell_vm_fault(struct vm_area_struct *vma, struct vm_fault *vmf) +{ +#endif + struct kfd_process_device *pdd = vma->vm_private_data; if (!pdd) return VM_FAULT_SIGBUS; diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 268ac6b8672e3..cb1731abd6d52 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -42,6 +42,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_VMF_INSERT AC_AMDGPU_VMF_INSERT_MIXED_PROT AC_AMDGPU_VMF_INSERT_PFN_PROT + AC_AMDGPU_VM_OPERATIONS_STRUCT_FAULT AC_AMDGPU_MMU_NOTIFIER AC_AMDGPU_MMU_NOTIFIER_CALL_SRCU AC_AMDGPU_MM_RELEASE_PAGES diff --git a/drivers/gpu/drm/amd/dkms/m4/vm_operations_struct.m4 b/drivers/gpu/drm/amd/dkms/m4/vm_operations_struct.m4 new file mode 100644 index 0000000000000..9e01b9fb9f36b --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/vm_operations_struct.m4 @@ -0,0 +1,35 @@ +dnl # +dnl # commit v4.10-9602-g11bac8000449 +dnl # mm, fs: reduce fault, page_mkwrite, and pfn_mkwrite to take only vmf +dnl # +AC_DEFUN([AC_AMDGPU_VM_OPERATIONS_STRUCT_FAULT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + int (*fault)(struct vm_area_struct *vma, struct vm_fault *vmf) = 0; + struct vm_operations_struct *vm_ops = NULL; + vm_ops->fault(NULL); + ], [ + AC_DEFINE(HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG, 1, + [vm_operations_struct->fault() wants 1 arg]) + AC_DEFINE(HAVE_VM_FAULT_ADDRESS_VMA, 1, + [vm_fault->{address/vam} is available]) + ], [ + dnl # + dnl # commit v4.9-7746-g82b0f8c39a38 + dnl # mm: join struct fault_env and vm_fault + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct vm_fault *ptest = NULL; + ptest->address = 0; + ptest->vma = NULL; + ], [ + AC_DEFINE(HAVE_VM_FAULT_ADDRESS_VMA, 1, + [vm_fault->{address/vam} is available]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/ttm/ttm_bo_vm.c b/drivers/gpu/drm/ttm/ttm_bo_vm.c index 8f797d8d5d504..909fb3ab75967 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_vm.c +++ b/drivers/gpu/drm/ttm/ttm_bo_vm.c @@ -39,7 +39,8 @@ #include static vm_fault_t ttm_bo_vm_fault_idle(struct ttm_buffer_object *bo, - struct vm_fault *vmf) + struct vm_fault *vmf, + struct vm_area_struct *vma) { long err = 0; @@ -59,7 +60,7 @@ static vm_fault_t ttm_bo_vm_fault_idle(struct ttm_buffer_object *bo, return VM_FAULT_RETRY; ttm_bo_get(bo); - mmap_read_unlock(vmf->vma->vm_mm); + mmap_read_unlock(vma->vm_mm); (void)dma_resv_wait_timeout(amdkcl_ttm_resvp(bo), DMA_RESV_USAGE_KERNEL, true, MAX_SCHEDULE_TIMEOUT); @@ -113,9 +114,17 @@ static unsigned long ttm_bo_io_mem_pfn(struct ttm_buffer_object *bo, * VM_FAULT_RETRY if blocking wait. * VM_FAULT_NOPAGE if blocking wait and retrying was not allowed. */ +#ifndef HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG vm_fault_t ttm_bo_vm_reserve(struct ttm_buffer_object *bo, - struct vm_fault *vmf) + struct vm_fault *vmf, + struct vm_area_struct *vma) { +#else +vm_fault_t ttm_bo_vm_reserve(struct ttm_buffer_object *bo, + struct vm_fault *vmf) +{ + struct vm_area_struct *vma = vmf->vma; +#endif /* * Work around locking order reversal in fault / nopfn * between mmap_lock and bo_reserve: Perform a trylock operation @@ -131,7 +140,7 @@ vm_fault_t ttm_bo_vm_reserve(struct ttm_buffer_object *bo, if (fault_flag_allow_retry_first(vmf->flags)) { if (!(vmf->flags & FAULT_FLAG_RETRY_NOWAIT)) { ttm_bo_get(bo); - mmap_read_unlock(vmf->vma->vm_mm); + mmap_read_unlock(vma->vm_mm); if (!dma_resv_lock_interruptible(amdkcl_ttm_resvp(bo), NULL)) dma_resv_unlock(amdkcl_ttm_resvp(bo)); @@ -178,11 +187,19 @@ EXPORT_SYMBOL(ttm_bo_vm_reserve); * VM_FAULT_OOM on out-of-memory * VM_FAULT_RETRY if retryable wait */ +#ifndef HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG +vm_fault_t ttm_bo_vm_fault_reserved(struct vm_fault *vmf, + struct vm_area_struct *vma, + pgprot_t prot, + pgoff_t num_prefault) +{ +#else vm_fault_t ttm_bo_vm_fault_reserved(struct vm_fault *vmf, pgprot_t prot, pgoff_t num_prefault) { struct vm_area_struct *vma = vmf->vma; +#endif struct ttm_buffer_object *bo = vma->vm_private_data; struct ttm_device *bdev = bo->bdev; unsigned long page_offset; @@ -193,13 +210,17 @@ vm_fault_t ttm_bo_vm_fault_reserved(struct vm_fault *vmf, int err; pgoff_t i; vm_fault_t ret = VM_FAULT_NOPAGE; +#ifndef HAVE_VM_FAULT_ADDRESS_VMA + unsigned long address = (unsigned long)vmf->virtual_address; +#else unsigned long address = vmf->address; +#endif /* * Wait for buffer data in transit, due to a pipelined * move. */ - ret = ttm_bo_vm_fault_idle(bo, vmf); + ret = ttm_bo_vm_fault_idle(bo, vmf, vma); if (unlikely(ret != 0)) return ret; @@ -318,22 +339,36 @@ vm_fault_t ttm_bo_vm_dummy_page(struct vm_fault *vmf, pgprot_t prot) } EXPORT_SYMBOL(ttm_bo_vm_dummy_page); +#ifndef HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG +vm_fault_t ttm_bo_vm_fault(struct vm_area_struct *vma, struct vm_fault *vmf) +{ +#else vm_fault_t ttm_bo_vm_fault(struct vm_fault *vmf) { struct vm_area_struct *vma = vmf->vma; +#endif pgprot_t prot; struct ttm_buffer_object *bo = vma->vm_private_data; struct drm_device *ddev = bo->base.dev; vm_fault_t ret; int idx; +#ifndef HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG + ret = ttm_bo_vm_reserve(bo, vmf, vma); +#else ret = ttm_bo_vm_reserve(bo, vmf); +#endif if (ret) return ret; prot = vma->vm_page_prot; if (drm_dev_enter(ddev, &idx)) { + +#ifndef HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG + ret = ttm_bo_vm_fault_reserved(vmf, vma, prot, TTM_BO_VM_NUM_PREFAULT); +#else ret = ttm_bo_vm_fault_reserved(vmf, prot, TTM_BO_VM_NUM_PREFAULT); +#endif drm_dev_exit(idx); } else { ret = ttm_bo_vm_dummy_page(vmf, prot); diff --git a/include/drm/ttm/ttm_bo.h b/include/drm/ttm/ttm_bo.h index b0a046e7edeea..0d3ef4deb8b1a 100644 --- a/include/drm/ttm/ttm_bo.h +++ b/include/drm/ttm/ttm_bo.h @@ -39,6 +39,7 @@ #include "ttm_device.h" #ifndef HAVE_CONFIG_H #define HAVE_DRM_GEM_OBJECT_RESV 1 +#define HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG 1 #endif /* Default number of pre-faulted pages in the TTM fault handler */ @@ -408,12 +409,30 @@ int ttm_mem_evict_first(struct ttm_device *bdev, const struct ttm_place *place, struct ttm_operation_ctx *ctx, struct ww_acquire_ctx *ticket); + +/* Default number of pre-faulted pages in the TTM fault handler */ +#define TTM_BO_VM_NUM_PREFAULT 16 + +#if defined(HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG) vm_fault_t ttm_bo_vm_reserve(struct ttm_buffer_object *bo, struct vm_fault *vmf); vm_fault_t ttm_bo_vm_fault_reserved(struct vm_fault *vmf, pgprot_t prot, pgoff_t num_prefault); vm_fault_t ttm_bo_vm_fault(struct vm_fault *vmf); +#else +vm_fault_t ttm_bo_vm_reserve(struct ttm_buffer_object *bo, + struct vm_fault *vmf, + struct vm_area_struct *vma); + +vm_fault_t ttm_bo_vm_fault_reserved(struct vm_fault *vmf, + struct vm_area_struct *vma, + pgprot_t prot, + pgoff_t num_prefault); + +vm_fault_t ttm_bo_vm_fault(struct vm_area_struct *vma, struct vm_fault *vmf); +#endif + void ttm_bo_vm_open(struct vm_area_struct *vma); void ttm_bo_vm_close(struct vm_area_struct *vma); int ttm_bo_vm_access(struct vm_area_struct *vma, unsigned long addr, From 7ac4d8650739d0df465b789a13c4bbb8cc77baae Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Wed, 14 Aug 2019 12:58:05 +0800 Subject: [PATCH 0220/1868] drm/amdkcl: Test whether drm_mm_print is available v1: drm/amdkcl: Test whether drm_debug_printer() function is available v2: drm/amdkcl: fix the struct drm_printer error. v3: drm/amdkcl: fix drm_printer related checks v4: drm/amdkcl: accommodate to drmP.h removal for drm-mm-print.m4 Signed-off-by: Yifan Zhang Reviewed-by: Flora Cui Reviewed-by: Feifei Xu Signed-off-by: Slava Grigorev Signed-off-by: Jack Gui Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang Change-Id: I66988af2c3ae0af9782f278edebaaafbccd3fa30 --- drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 8 ++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 1 - drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 4 ++++ drivers/gpu/drm/amd/dkms/m4/drm-mm-print.m4 | 15 +++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/drm/ttm/ttm_resource.h | 4 ++++ 6 files changed, 32 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-mm-print.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c index 0760e70402ec1..d72c5a9a85470 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c @@ -247,12 +247,20 @@ static bool amdgpu_gtt_mgr_compatible(struct ttm_resource_manager *man, * Dump the table content using printk. */ static void amdgpu_gtt_mgr_debug(struct ttm_resource_manager *man, +#if defined(HAVE_DRM_MM_PRINT) struct drm_printer *printer) +#else + const char *prefix) +#endif { struct amdgpu_gtt_mgr *mgr = to_gtt_mgr(man); spin_lock(&mgr->lock); +#if defined(HAVE_DRM_MM_PRINT) drm_mm_print(&mgr->mm, printer); +#else + drm_mm_debug_table(&mgr->mm, prefix); +#endif spin_unlock(&mgr->lock); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 57a184ed1dbc0..0224bd5e6ca24 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -2691,7 +2691,6 @@ int amdgpu_ttm_evict_resources(struct amdgpu_device *adev, int mem_type) } #if defined(CONFIG_DEBUG_FS) - static int amdgpu_ttm_page_pool_show(struct seq_file *m, void *unused) { struct amdgpu_device *adev = m->private; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c index 7d26a962f811c..c6bd73b8ca382 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c @@ -857,7 +857,11 @@ static bool amdgpu_vram_mgr_compatible(struct ttm_resource_manager *man, * Dump the table content using printk. */ static void amdgpu_vram_mgr_debug(struct ttm_resource_manager *man, +#if defined(HAVE_DRM_MM_PRINT) struct drm_printer *printer) +#else + const char *prefix) +#endif { struct amdgpu_vram_mgr *mgr = to_vram_mgr(man); struct drm_buddy *mm = &mgr->mm; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-mm-print.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-mm-print.m4 new file mode 100644 index 0000000000000..2d1d63b131ce7 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-mm-print.m4 @@ -0,0 +1,15 @@ +dnl # +dnl # commit b5c3714fe8789745521d8351d75049b9c6a0d26b +dnl # drm/mm: Convert to drm_printer +dnl # +AC_DEFUN([AC_AMDGPU_DRM_MM_PRINT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_mm_print(NULL, NULL); + ], [ + AC_DEFINE(HAVE_DRM_MM_PRINT, 1, [drm_mm_print() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index cb1731abd6d52..1befd32bc2b9e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -66,6 +66,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_RESUME AC_AMDGPU_DRM_DRIVER_GEM_PRIME_RES_OBJ AC_AMDGPU_DRM_DRV_GEM_PRIME_EXPORT + AC_AMDGPU_DRM_MM_PRINT AC_AMDGPU___DRM_ATOMIC_HELPER_CRTC_RESET AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION AC_AMDGPU_MEM_ENCRYPT_ACTIVE diff --git a/include/drm/ttm/ttm_resource.h b/include/drm/ttm/ttm_resource.h index e909fc0cba01c..51f907adae150 100644 --- a/include/drm/ttm/ttm_resource.h +++ b/include/drm/ttm/ttm_resource.h @@ -130,8 +130,12 @@ struct ttm_resource_manager_func { * type manager to aid debugging of out-of-memory conditions. * It may not be called from within atomic context. */ +#if defined(HAVE_DRM_MM_PRINT) void (*debug)(struct ttm_resource_manager *man, struct drm_printer *printer); +#else + void (*debug)(struct ttm_resource_manager *man, const char *prefix); +#endif }; /** From 8924ee30afcee475c90cddbd6a1ff62101840275 Mon Sep 17 00:00:00 2001 From: Chengming Gui Date: Mon, 5 Aug 2019 10:10:54 +0800 Subject: [PATCH 0221/1868] drm/amdkcl: Test whether drm_mm_insert_mode is available drm_mm_search_flags was replaced with drm_mm_insert_mode when kernel 4.11 introduced v1: drm/amdkcl: fix missing HAVE_DRM_MM_INSERT_MODE check (v2) v2: clean code v3: drm/amdkcl: accommodate to drmP.h removal for drm-mm-insert-mode.m4 Signed-off-by: Chengming Gui Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang Signed-off-by: Chengming Gui Reviewed-by: Flora Cui Signed-off-by: Jack Gui Change-Id: I26c8f257f9f86c8c66b8b3ed3ec11bfb217f1507 --- .../gpu/drm/amd/dkms/m4/drm-mm-insert-mode.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/ttm/ttm_range_manager.c | 7 +++++++ 3 files changed, 25 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-mm-insert-mode.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-mm-insert-mode.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-mm-insert-mode.m4 new file mode 100644 index 0000000000000..633f7925b0aec --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-mm-insert-mode.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit 4e64e5539d152e202ad6eea2b6f65f3ab58d9428 +dnl # Author: Chris Wilson +dnl # Date: Thu Feb 2 21:04:38 2017 +0000 +dnl # +AC_DEFUN([AC_AMDGPU_DRM_MM_INSERT_MODE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + enum drm_mm_insert_mode mode = DRM_MM_INSERT_BEST; + ],[ + AC_DEFINE(HAVE_DRM_MM_INSERT_MODE, 1, + [whether drm_mm_insert_mode is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 1befd32bc2b9e..e49321200a7c9 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -67,6 +67,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DRIVER_GEM_PRIME_RES_OBJ AC_AMDGPU_DRM_DRV_GEM_PRIME_EXPORT AC_AMDGPU_DRM_MM_PRINT + AC_AMDGPU_DRM_MM_INSERT_MODE AC_AMDGPU___DRM_ATOMIC_HELPER_CRTC_RESET AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION AC_AMDGPU_MEM_ENCRYPT_ACTIVE diff --git a/drivers/gpu/drm/ttm/ttm_range_manager.c b/drivers/gpu/drm/ttm/ttm_range_manager.c index ae11d07eb63a8..e06325e1ab6b9 100644 --- a/drivers/gpu/drm/ttm/ttm_range_manager.c +++ b/drivers/gpu/drm/ttm/ttm_range_manager.c @@ -75,9 +75,16 @@ static int ttm_range_man_alloc(struct ttm_resource_manager *man, if (!node) return -ENOMEM; +#ifndef HAVE_DRM_MM_INSERT_MODE + if (place->flags & TTM_PL_FLAG_TOPDOWN) { + sflags = DRM_MM_SEARCH_BELOW; + aflags = DRM_MM_CREATE_TOP; + } +#else mode = DRM_MM_INSERT_BEST; if (place->flags & TTM_PL_FLAG_TOPDOWN) mode = DRM_MM_INSERT_HIGH; +#endif ttm_resource_init(bo, place, &node->base); From 178bbbbfec78dbe3320b2dc9265310fd2c1288f7 Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Tue, 30 Jul 2019 08:58:34 +0800 Subject: [PATCH 0222/1868] drm/amdkcl: add sync obj macros clean amdgpu_cs.c code v1: drm/amdkcl: remove DRIVER_SYNCOBJ_TIMELINE in kms_driver v2: sync with mainline v3: drm/amdkcl: add HAVE_CHUNK_ID_SYNOBJ_IN_OUT in amdgpu_cs_post_dep v4: drm/amd/autoconf: fix CHUNK_ID_SCHEDULED_DEPENDENCIES check error v5: drm/amdkcl: drop kcl_drm_syncobj_find_fence Signed-off-by: Yifan Zhang Signed-off-by: Adam Yang Reviewed-by: Flora Cui Signed-off-by: Flora Cui Signed-off-by: Jack Gui Acked-by: Feifei Xu / --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 11 ++++++++++- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 8 ++++++-- .../dkms/m4/chunk-id-scheduled-dependencies.m4 | 16 ++++++++++++++++ .../m4/chunk-id-syncobj-timeline-wait-signal.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 ++ 5 files changed, 51 insertions(+), 3 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/chunk-id-scheduled-dependencies.m4 create mode 100644 drivers/gpu/drm/amd/dkms/m4/chunk-id-syncobj-timeline-wait-signal.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index f82cdb312846a..df9bf11f0cb2f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -276,12 +276,15 @@ static int amdgpu_cs_pass1(struct amdgpu_cs_parser *p, case AMDGPU_CHUNK_ID_DEPENDENCIES: case AMDGPU_CHUNK_ID_SYNCOBJ_IN: case AMDGPU_CHUNK_ID_SYNCOBJ_OUT: +#if defined(HAVE_AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES) case AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES: +#endif +#if defined(HAVE_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL) case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT: case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL: +#endif case AMDGPU_CHUNK_ID_CP_GFX_SHADOW: break; - default: goto free_partial_kdata; } @@ -569,6 +572,7 @@ static int amdgpu_cs_p2_syncobj_timeline_signal(struct amdgpu_cs_parser *p, return 0; } +#endif static int amdgpu_cs_p2_shadow(struct amdgpu_cs_parser *p, struct amdgpu_cs_chunk *chunk) @@ -1261,6 +1265,7 @@ static void amdgpu_cs_post_dependencies(struct amdgpu_cs_parser *p) int i; for (i = 0; i < p->num_post_deps; ++i) { +#if defined(HAVE_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL) if (p->post_deps[i].chain && p->post_deps[i].point) { drm_syncobj_add_point(p->post_deps[i].syncobj, p->post_deps[i].chain, @@ -1270,6 +1275,10 @@ static void amdgpu_cs_post_dependencies(struct amdgpu_cs_parser *p) drm_syncobj_replace_fence(p->post_deps[i].syncobj, p->fence); } +#else + drm_syncobj_replace_fence(p->post_deps[i].syncobj, + p->fence); +#endif } } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 9fb830208ce31..03e9208fdfbb6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2982,8 +2982,12 @@ static const struct drm_driver amdgpu_kms_driver = { .driver_features = DRIVER_ATOMIC | DRIVER_GEM | - DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ | - DRIVER_SYNCOBJ_TIMELINE, + DRIVER_RENDER | DRIVER_MODESET + | DRIVER_SYNCOBJ +#ifdef HAVE_DRM_DRV_DRIVER_SYNCOBJ_TIMELINE + | DRIVER_SYNCOBJ_TIMELINE +#endif /* HAVE_DRM_DRV_DRIVER_SYNCOBJ_TIMELINE */ + , .open = amdgpu_driver_open_kms, .postclose = amdgpu_driver_postclose_kms, .lastclose = amdgpu_driver_lastclose_kms, diff --git a/drivers/gpu/drm/amd/dkms/m4/chunk-id-scheduled-dependencies.m4 b/drivers/gpu/drm/amd/dkms/m4/chunk-id-scheduled-dependencies.m4 new file mode 100644 index 0000000000000..c1075f2a16d7f --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/chunk-id-scheduled-dependencies.m4 @@ -0,0 +1,16 @@ +dnl # commit 67dd1a36334ffce82bebeb2d633e152aa436d370 +dnl # drm/amdgpu: Add AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES +AC_DEFUN([AC_AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + #ifndef AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES + #error AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES not #defined + #endif + ], [ + AC_DEFINE(HAVE_AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES, 1, + [whether AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES is defined]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/chunk-id-syncobj-timeline-wait-signal.m4 b/drivers/gpu/drm/amd/dkms/m4/chunk-id-syncobj-timeline-wait-signal.m4 new file mode 100644 index 0000000000000..1ae2aee78530f --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/chunk-id-syncobj-timeline-wait-signal.m4 @@ -0,0 +1,17 @@ +dnl # commit 2624dd154bcc53ac2de16ecae9746ba867b6ca70 +dnl # drm/amdgpu: add timeline support in amdgpu CS v3 +AC_DEFUN([AC_AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + #if !defined(AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT) ||\ + !defined(AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL) + #error CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL not #defined + #endif + ], [ + AC_DEFINE(HAVE_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL, 1, + [whether CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL is defined]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index e49321200a7c9..a497aff232b48 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -68,6 +68,8 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DRV_GEM_PRIME_EXPORT AC_AMDGPU_DRM_MM_PRINT AC_AMDGPU_DRM_MM_INSERT_MODE + AC_AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES + AC_AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL AC_AMDGPU___DRM_ATOMIC_HELPER_CRTC_RESET AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION AC_AMDGPU_MEM_ENCRYPT_ACTIVE From b5eff0a84b53943ba742a86df8b22f0191cc861a Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 14 Apr 2020 20:31:21 +0800 Subject: [PATCH 0223/1868] drm/amdkcl: test drm_fb_helper_init() Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 400 ++++++++++++++++++ .../gpu/drm/amd/dkms/m4/drm_fb_helper_init.m4 | 35 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 436 insertions(+) create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_fb_helper_init.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c new file mode 100644 index 0000000000000..51c51f477d05c --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c @@ -0,0 +1,400 @@ +/* + * Copyright © 2007 David Airlie + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + * + * Authors: + * David Airlie + */ + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include "amdgpu.h" +#include "cikd.h" +#include "amdgpu_gem.h" + +#include "amdgpu_display.h" + +/* object hierarchy - + this contains a helper + a amdgpu fb + the helper contains a pointer to amdgpu framebuffer baseclass. +*/ + +static int +amdgpufb_open(struct fb_info *info, int user) +{ + struct drm_fb_helper *fb_helper = info->par; + int ret = pm_runtime_get_sync(fb_helper->dev->dev); + if (ret < 0 && ret != -EACCES) { + pm_runtime_mark_last_busy(fb_helper->dev->dev); + pm_runtime_put_autosuspend(fb_helper->dev->dev); + return ret; + } + return 0; +} + +static int +amdgpufb_release(struct fb_info *info, int user) +{ + struct drm_fb_helper *fb_helper = info->par; + + pm_runtime_mark_last_busy(fb_helper->dev->dev); + pm_runtime_put_autosuspend(fb_helper->dev->dev); + return 0; +} + +static const struct fb_ops amdgpufb_ops = { + .owner = THIS_MODULE, + DRM_FB_HELPER_DEFAULT_OPS, + .fb_open = amdgpufb_open, + .fb_release = amdgpufb_release, + .fb_fillrect = drm_fb_helper_cfb_fillrect, + .fb_copyarea = drm_fb_helper_cfb_copyarea, + .fb_imageblit = drm_fb_helper_cfb_imageblit, +}; + + +int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int cpp, bool tiled) +{ + int aligned = width; + int pitch_mask = 0; + + switch (cpp) { + case 1: + pitch_mask = 255; + break; + case 2: + pitch_mask = 127; + break; + case 3: + case 4: + pitch_mask = 63; + break; + } + + aligned += pitch_mask; + aligned &= ~pitch_mask; + return aligned * cpp; +} + +static void amdgpufb_destroy_pinned_object(struct drm_gem_object *gobj) +{ + struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj); + int ret; + + ret = amdgpu_bo_reserve(abo, true); + if (likely(ret == 0)) { + amdgpu_bo_kunmap(abo); + amdgpu_bo_unpin(abo); + amdgpu_bo_unreserve(abo); + } + drm_gem_object_put(gobj); +} + +static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev, + struct drm_mode_fb_cmd2 *mode_cmd, + struct drm_gem_object **gobj_p) +{ + const struct drm_format_info *info; + struct amdgpu_device *adev = rfbdev->adev; + struct drm_gem_object *gobj = NULL; + struct amdgpu_bo *abo = NULL; + bool fb_tiled = false; /* useful for testing */ + u32 tiling_flags = 0, domain; + int ret; + int aligned_size, size; + int height = mode_cmd->height; + u32 cpp; + u64 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | + AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | + AMDGPU_GEM_CREATE_VRAM_CLEARED; + + info = drm_get_format_info(adev_to_drm(adev), mode_cmd); + cpp = info->cpp[0]; + + /* need to align pitch with crtc limits */ + mode_cmd->pitches[0] = amdgpu_align_pitch(adev, mode_cmd->width, cpp, + fb_tiled); + domain = amdgpu_display_supported_domains(adev, flags); + height = ALIGN(mode_cmd->height, 8); + size = mode_cmd->pitches[0] * height; + aligned_size = ALIGN(size, PAGE_SIZE); + ret = amdgpu_gem_object_create(adev, aligned_size, 0, domain, flags, + ttm_bo_type_device, NULL, &gobj); + if (ret) { + pr_err("failed to allocate framebuffer (%d)\n", aligned_size); + return -ENOMEM; + } + abo = gem_to_amdgpu_bo(gobj); + + if (fb_tiled) + tiling_flags = AMDGPU_TILING_SET(ARRAY_MODE, GRPH_ARRAY_2D_TILED_THIN1); + + ret = amdgpu_bo_reserve(abo, false); + if (unlikely(ret != 0)) + goto out_unref; + + if (tiling_flags) { + ret = amdgpu_bo_set_tiling_flags(abo, + tiling_flags); + if (ret) + dev_err(adev->dev, "FB failed to set tiling flags\n"); + } + + ret = amdgpu_bo_pin(abo, domain); + if (ret) { + amdgpu_bo_unreserve(abo); + goto out_unref; + } + + ret = amdgpu_ttm_alloc_gart(&abo->tbo); + if (ret) { + amdgpu_bo_unreserve(abo); + dev_err(adev->dev, "%p bind failed\n", abo); + goto out_unref; + } + + ret = amdgpu_bo_kmap(abo, NULL); + amdgpu_bo_unreserve(abo); + if (ret) { + goto out_unref; + } + + *gobj_p = gobj; + return 0; +out_unref: + amdgpufb_destroy_pinned_object(gobj); + *gobj_p = NULL; + return ret; +} + +static int amdgpufb_create(struct drm_fb_helper *helper, + struct drm_fb_helper_surface_size *sizes) +{ + struct amdgpu_fbdev *rfbdev = (struct amdgpu_fbdev *)helper; + struct amdgpu_device *adev = rfbdev->adev; + struct fb_info *info; + struct drm_framebuffer *fb = NULL; + struct drm_mode_fb_cmd2 mode_cmd; + struct drm_gem_object *gobj = NULL; + struct amdgpu_bo *abo = NULL; + int ret; + + memset(&mode_cmd, 0, sizeof(mode_cmd)); + mode_cmd.width = sizes->surface_width; + mode_cmd.height = sizes->surface_height; + + if (sizes->surface_bpp == 24) + sizes->surface_bpp = 32; + + mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp, + sizes->surface_depth); + + ret = amdgpufb_create_pinned_object(rfbdev, &mode_cmd, &gobj); + if (ret) { + DRM_ERROR("failed to create fbcon object %d\n", ret); + return ret; + } + + abo = gem_to_amdgpu_bo(gobj); + + /* okay we have an object now allocate the framebuffer */ + info = drm_fb_helper_alloc_fbi(helper); + if (IS_ERR(info)) { + ret = PTR_ERR(info); + goto out; + } + + ret = amdgpu_display_gem_fb_init(adev_to_drm(adev), &rfbdev->rfb, + &mode_cmd, gobj); + if (ret) { + DRM_ERROR("failed to initialize framebuffer %d\n", ret); + goto out; + } + + fb = &rfbdev->rfb.base; + + /* setup helper */ + rfbdev->helper.fb = fb; + + info->fbops = &amdgpufb_ops; + + info->fix.smem_start = amdgpu_gmc_vram_cpu_pa(adev, abo); + info->fix.smem_len = amdgpu_bo_size(abo); + info->screen_base = amdgpu_bo_kptr(abo); + info->screen_size = amdgpu_bo_size(abo); + + drm_fb_helper_fill_info(info, &rfbdev->helper, sizes); + + /* setup aperture base/size for vesafb takeover */ + info->apertures->ranges[0].base = adev_to_drm(adev)->mode_config.fb_base; + info->apertures->ranges[0].size = adev->gmc.aper_size; + + /* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */ + + if (info->screen_base == NULL) { + ret = -ENOSPC; + goto out; + } + + DRM_INFO("fb mappable at 0x%lX\n", info->fix.smem_start); + DRM_INFO("vram apper at 0x%lX\n", (unsigned long)adev->gmc.aper_base); + DRM_INFO("size %lu\n", (unsigned long)amdgpu_bo_size(abo)); + DRM_INFO("fb depth is %d\n", fb->format->depth); + DRM_INFO(" pitch is %d\n", fb->pitches[0]); + + vga_switcheroo_client_fb_set(adev->pdev, info); + return 0; + +out: + if (abo) { + + } + if (fb && ret) { + drm_gem_object_put(gobj); + drm_framebuffer_unregister_private(fb); + drm_framebuffer_cleanup(fb); + kfree(fb); + } + return ret; +} + +static int amdgpu_fbdev_destroy(struct drm_device *dev, struct amdgpu_fbdev *rfbdev) +{ + struct amdgpu_framebuffer *rfb = &rfbdev->rfb; + int i; + + drm_fb_helper_unregister_fbi(&rfbdev->helper); + + if (rfb->base.obj[0]) { + for (i = 0; i < rfb->base.format->num_planes; i++) + drm_gem_object_put(rfb->base.obj[0]); + amdgpufb_destroy_pinned_object(rfb->base.obj[0]); + rfb->base.obj[0] = NULL; + drm_framebuffer_unregister_private(&rfb->base); + drm_framebuffer_cleanup(&rfb->base); + } + drm_fb_helper_fini(&rfbdev->helper); + + return 0; +} + +static const struct drm_fb_helper_funcs amdgpu_fb_helper_funcs = { + .fb_probe = amdgpufb_create, +}; + +int amdgpu_fbdev_init(struct amdgpu_device *adev) +{ + struct amdgpu_fbdev *rfbdev; + int bpp_sel = 32; + int ret; + + /* don't init fbdev on hw without DCE */ + if (!adev->mode_info.mode_config_initialized) + return 0; + + /* don't init fbdev if there are no connectors */ + if (list_empty(&adev_to_drm(adev)->mode_config.connector_list)) + return 0; + + /* select 8 bpp console on low vram cards */ + if (adev->gmc.real_vram_size <= (32*1024*1024)) + bpp_sel = 8; + + rfbdev = kzalloc(sizeof(struct amdgpu_fbdev), GFP_KERNEL); + if (!rfbdev) + return -ENOMEM; + + rfbdev->adev = adev; + adev->mode_info.rfbdev = rfbdev; + + drm_fb_helper_prepare(adev_to_drm(adev), &rfbdev->helper, + &amdgpu_fb_helper_funcs); + +#if defined(HAVE_DRM_FB_HELPER_INIT_2ARGS) + ret = drm_fb_helper_init(adev_to_drm(adev), &rfbdev->helper); +#elif defined(HAVE_DRM_FB_HELPER_INIT_3ARGS) + ret = drm_fb_helper_init(adev_to_drm(adev), &rfbdev->helper, + AMDGPUFB_CONN_LIMIT); +#else + ret = drm_fb_helper_init(adev_to_drm(adev), &rfbdev->helper, + adev->mode_info.num_crtc, AMDGPUFB_CONN_LIMIT); +#endif + + if (ret) { + kfree(rfbdev); + return ret; + } + + /* disable all the possible outputs/crtcs before entering KMS mode */ + if (!amdgpu_device_has_dc_support(adev)) + drm_helper_disable_unused_functions(adev_to_drm(adev)); + + drm_fb_helper_initial_config(&rfbdev->helper, bpp_sel); + return 0; +} + +void amdgpu_fbdev_fini(struct amdgpu_device *adev) +{ + if (!adev->mode_info.rfbdev) + return; + + amdgpu_fbdev_destroy(adev_to_drm(adev), adev->mode_info.rfbdev); + kfree(adev->mode_info.rfbdev); + adev->mode_info.rfbdev = NULL; +} + +void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state) +{ + if (adev->mode_info.rfbdev) + drm_fb_helper_set_suspend_unlocked(&adev->mode_info.rfbdev->helper, + state); +} + +int amdgpu_fbdev_total_size(struct amdgpu_device *adev) +{ + struct amdgpu_bo *robj; + int size = 0; + + if (!adev->mode_info.rfbdev) + return 0; + + robj = gem_to_amdgpu_bo(adev->mode_info.rfbdev->rfb.base.obj[0]); + size += amdgpu_bo_size(robj); + return size; +} + +bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj) +{ + if (!adev->mode_info.rfbdev) + return false; + if (robj == gem_to_amdgpu_bo(adev->mode_info.rfbdev->rfb.base.obj[0])) + return true; + return false; +} diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_fb_helper_init.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_fb_helper_init.m4 new file mode 100644 index 0000000000000..8c0d4b9e932ea --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_fb_helper_init.m4 @@ -0,0 +1,35 @@ +dnl # +dnl # commit v5.6-rc2-1021-g2dea2d118217 +dnl # drm: Remove unused arg from drm_fb_helper_init +dnl # +AC_DEFUN([AC_AMDGPU_DRM_FB_HELPER_INIT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #ifdef HAVE_DRM_DRMP_H + #include + #endif + #include + ], [ + drm_fb_helper_init(NULL, NULL); + ], [drm_fb_helper_init], [drivers/gpu/drm/drm_fb_helper.c], [ + AC_DEFINE(HAVE_DRM_FB_HELPER_INIT_2ARGS, 1, + [drm_fb_helper_init() has 2 args]) + ], [ + dnl # + dnl # commit v4.10-rc5-1046-ge4563f6ba717 + dnl # drm: Rely on mode_config data for fb_helper initialization + dnl # + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #ifdef HAVE_DRM_DRMP_H + #include + #endif + #include + ], [ + drm_fb_helper_init(NULL, NULL, 0); + ], [drm_fb_helper_init], [drivers/gpu/drm/drm_fb_helper.c], [ + AC_DEFINE(HAVE_DRM_FB_HELPER_INIT_3ARGS, 1, + [drm_fb_helper_init() has 3 args]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index a497aff232b48..781f0d97d3157 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -83,6 +83,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_FB_HELPER_FILL_INFO AC_AMDGPU_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED AC_AMDGPU_DRM_HELPER_MODE_FILL_FB_STRUCT + AC_AMDGPU_DRM_FB_HELPER_INIT AC_AMDGPU_DRM_HELPER_FORCE_DISABLE_ALL AC_AMDGPU_DRM_EDID_TO_ELD From 3f86701e9df32b12df4ffa299054c5489685b605 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Thu, 9 May 2019 17:20:26 -0400 Subject: [PATCH 0224/1868] drm/amdkcl: Test whether format in struct drm_framebuffer is available v1: drm/amdkcl: Test whether drm_framebuffer structure contains format v2: drm/amd/autoconf: test whether struct drm_framebuffer have format v3: drm/amdkcl: fix for HAVE_DRM_FRAMEBUFFER_FORMAT v4: drm/amdkcl: accommodate to drmP.h removal for drm-framebuffer-format.m4 v5: drm/amdkcl: fix pitch setting on leacy kernel (Flora Cui) update pitch register as is done by commit 965ebe3d5d641("drm/amdgpu: Update pitch on page flips without DC as well") Signed-off-by: Slava Grigorev Signed-off-by: Yifan Zhang Signed-off-by: chen gong Signed-off-by: Jack Gui Reviewed-by: Flora Cui Reviewed-by: Feifei Xu Signed-off-by: Flora Cui Signed-off-by: Flora Cui Reviewed-by: Yang Xiong --- drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 4 ++++ drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 17 ++++++++++++++ drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 17 ++++++++++++++ drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 17 ++++++++++++++ drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 18 ++++++++++++++- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++++ .../drm/amd/dkms/m4/drm-framebuffer-format.m4 | 23 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 8 files changed, 100 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-framebuffer-format.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c index 51c51f477d05c..7ff70856c88e1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c @@ -266,7 +266,11 @@ static int amdgpufb_create(struct drm_fb_helper *helper, DRM_INFO("fb mappable at 0x%lX\n", info->fix.smem_start); DRM_INFO("vram apper at 0x%lX\n", (unsigned long)adev->gmc.aper_base); DRM_INFO("size %lu\n", (unsigned long)amdgpu_bo_size(abo)); +#if !defined(HAVE_DRM_FRAMEBUFFER_FORMAT) + DRM_INFO("fb depth is %d\n", fb->depth); +#else DRM_INFO("fb depth is %d\n", fb->format->depth); +#endif DRM_INFO(" pitch is %d\n", fb->pitches[0]); vga_switcheroo_client_fb_set(adev->pdev, info); diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index 742adbc460c9d..3cc370c1dfdb0 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -244,8 +244,13 @@ static void dce_v10_0_page_flip(struct amdgpu_device *adev, GRPH_SURFACE_UPDATE_H_RETRACE_EN, async ? 1 : 0); WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); /* update pitch */ +#if defined(HAVE_DRM_FRAMEBUFFER_FORMAT) WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb->pitches[0] / fb->format->cpp[0]); +#else + WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, + fb->pitches[0] / (fb->bits_per_pixel / 8)); +#endif /* update the primary scanout address */ WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, upper_32_bits(crtc_base)); @@ -1894,7 +1899,11 @@ static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc, pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); +#if !defined(HAVE_DRM_FRAMEBUFFER_FORMAT) + switch (target_fb->pixel_format) { +#else switch (target_fb->format->format) { +#endif case DRM_FORMAT_C8: fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0); fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); @@ -1978,7 +1987,11 @@ static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc, break; default: DRM_ERROR("Unsupported screen format %p4cc\n", +#if defined(HAVE_DRM_FRAMEBUFFER_FORMAT) &target_fb->format->format); +#else + &target_fb->pixel_format); +#endif return -EINVAL; } @@ -2053,7 +2066,11 @@ static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc, WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); +#if !defined(HAVE_DRM_FRAMEBUFFER_FORMAT) + fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); +#else fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0]; +#endif WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); dce_v10_0_grph_enable(crtc, true); diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index 8d46ebadfa466..9882590e12cbe 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -268,8 +268,13 @@ static void dce_v11_0_page_flip(struct amdgpu_device *adev, GRPH_SURFACE_UPDATE_IMMEDIATE_EN, async ? 1 : 0); WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); /* update pitch */ +#if defined(HAVE_DRM_FRAMEBUFFER_FORMAT) WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb->pitches[0] / fb->format->cpp[0]); +#else + WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, + fb->pitches[0] / (fb->bits_per_pixel / 8)); +#endif /* update the scanout addresses */ WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, upper_32_bits(crtc_base)); @@ -1944,7 +1949,11 @@ static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc, pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); +#if !defined(HAVE_DRM_FRAMEBUFFER_FORMAT) + switch (target_fb->pixel_format) { +#else switch (target_fb->format->format) { +#endif case DRM_FORMAT_C8: fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0); fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); @@ -2028,7 +2037,11 @@ static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc, break; default: DRM_ERROR("Unsupported screen format %p4cc\n", +#if defined(HAVE_DRM_FRAMEBUFFER_FORMAT) &target_fb->format->format); +#else + &target_fb->pixel_format); +#endif return -EINVAL; } @@ -2103,7 +2116,11 @@ static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc, WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); +#if !defined(HAVE_DRM_FRAMEBUFFER_FORMAT) + fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); +#else fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0]; +#endif WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); dce_v11_0_grph_enable(crtc, true); diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c index f08dc6a3886f1..40ac8703fa33a 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c @@ -201,8 +201,13 @@ static void dce_v6_0_page_flip(struct amdgpu_device *adev, WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ? GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0); /* update pitch */ +#if defined(HAVE_DRM_FRAMEBUFFER_FORMAT) WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb->pitches[0] / fb->format->cpp[0]); +#else + WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, + fb->pitches[0] / (fb->bits_per_pixel / 8)); +#endif /* update the scanout addresses */ WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, upper_32_bits(crtc_base)); @@ -1872,7 +1877,11 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc, amdgpu_bo_get_tiling_flags(abo, &tiling_flags); amdgpu_bo_unreserve(abo); +#if !defined(HAVE_DRM_FRAMEBUFFER_FORMAT) + switch (target_fb->pixel_format) { +#else switch (target_fb->format->format) { +#endif case DRM_FORMAT_C8: fb_format = (GRPH_DEPTH(GRPH_DEPTH_8BPP) | GRPH_FORMAT(GRPH_FORMAT_INDEXED)); @@ -1948,7 +1957,11 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc, break; default: DRM_ERROR("Unsupported screen format %p4cc\n", +#if defined(HAVE_DRM_FRAMEBUFFER_FORMAT) &target_fb->format->format); +#else + &target_fb->pixel_format); +#endif return -EINVAL; } @@ -2011,7 +2024,11 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc, WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); +#if !defined(HAVE_DRM_FRAMEBUFFER_FORMAT) + fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); +#else fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0]; +#endif WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); dce_v6_0_grph_enable(crtc, true); diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index a6a3adf2ae134..d1546a207747f 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -191,9 +191,13 @@ static void dce_v8_0_page_flip(struct amdgpu_device *adev, /* flip at hsync for async, default is vsync */ WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ? GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0); - /* update pitch */ +#if defined(HAVE_DRM_FRAMEBUFFER_FORMAT) WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb->pitches[0] / fb->format->cpp[0]); +#else + WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, + fb->pitches[0] / (fb->bits_per_pixel / 8)); +#endif /* update the primary scanout addresses */ WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, upper_32_bits(crtc_base)); @@ -1841,7 +1845,11 @@ static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc, pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); +#if !defined(HAVE_DRM_FRAMEBUFFER_FORMAT) + switch (target_fb->pixel_format) { +#else switch (target_fb->format->format) { +#endif case DRM_FORMAT_C8: fb_format = ((GRPH_DEPTH_8BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | (GRPH_FORMAT_INDEXED << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); @@ -1917,7 +1925,11 @@ static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc, break; default: DRM_ERROR("Unsupported screen format %p4cc\n", +#if defined(HAVE_DRM_FRAMEBUFFER_FORMAT) &target_fb->format->format); +#else + &target_fb->pixel_format); +#endif return -EINVAL; } @@ -1980,7 +1992,11 @@ static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc, WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); +#if !defined(HAVE_DRM_FRAMEBUFFER_FORMAT) + fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); +#else fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0]; +#endif WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); dce_v8_0_grph_enable(crtc, true); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index e632410ef3a56..2a5634189112a 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -10596,7 +10596,11 @@ static bool should_reset_plane(struct drm_atomic_state *state, continue; /* Pixel format changes can require bandwidth updates. */ +#ifndef HAVE_DRM_FRAMEBUFFER_FORMAT + if (old_other_state->fb->pixel_format != new_other_state->fb->pixel_format) +#else if (old_other_state->fb->format != new_other_state->fb->format) +#endif return true; old_afb = (struct amdgpu_framebuffer *)old_other_state->fb; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-framebuffer-format.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-framebuffer-format.m4 new file mode 100644 index 0000000000000..977ed577e27c8 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-framebuffer-format.m4 @@ -0,0 +1,23 @@ +dnl # +dnl # commit e14c23c647abfc1fed96a55ba376cd9675a54098 +dnl # drm: Store a pointer to drm_format_info under drm_framebuffer +dnl # +AC_DEFUN([AC_AMDGPU_DRM_FRAMEBUFFER_FORMAT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drmP.h], [ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + struct drm_framebuffer *foo = NULL; + foo->format = NULL; + ], [ + AC_DEFINE(HAVE_DRM_FRAMEBUFFER_FORMAT, 1, + [whether struct drm_framebuffer have format]) + ]) + ], [ + AC_DEFINE(HAVE_DRM_FRAMEBUFFER_FORMAT, 1, + [whether struct drm_framebuffer have format]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 781f0d97d3157..a3030fc72c596 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -84,6 +84,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED AC_AMDGPU_DRM_HELPER_MODE_FILL_FB_STRUCT AC_AMDGPU_DRM_FB_HELPER_INIT + AC_AMDGPU_DRM_FRAMEBUFFER_FORMAT AC_AMDGPU_DRM_HELPER_FORCE_DISABLE_ALL AC_AMDGPU_DRM_EDID_TO_ELD From 2d18f1b4bd62dd02d1c153e2fe554e9fa860142d Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 11 Dec 2019 17:55:59 +0800 Subject: [PATCH 0225/1868] drm/amdkcl: check drm_get_format_info() is available Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 6 ++++++ drivers/gpu/drm/amd/dkms/m4/drm-get-format-info.m4 | 13 +++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 20 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-get-format-info.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c index 7ff70856c88e1..9db063a9e445c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c @@ -121,7 +121,9 @@ static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev, struct drm_mode_fb_cmd2 *mode_cmd, struct drm_gem_object **gobj_p) { +#ifdef HAVE_DRM_GET_FORMAT_INFO const struct drm_format_info *info; +#endif struct amdgpu_device *adev = rfbdev->adev; struct drm_gem_object *gobj = NULL; struct amdgpu_bo *abo = NULL; @@ -135,8 +137,12 @@ static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev, AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | AMDGPU_GEM_CREATE_VRAM_CLEARED; +#ifdef HAVE_DRM_GET_FORMAT_INFO info = drm_get_format_info(adev_to_drm(adev), mode_cmd); cpp = info->cpp[0]; +#else + cpp = drm_format_plane_cpp(mode_cmd->pixel_format, 0); +#endif /* need to align pitch with crtc limits */ mode_cmd->pitches[0] = amdgpu_align_pitch(adev, mode_cmd->width, cpp, diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-get-format-info.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-get-format-info.m4 new file mode 100644 index 0000000000000..5c797f77620f5 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-get-format-info.m4 @@ -0,0 +1,13 @@ +dnl # +dnl # commit v4.11-rc1-237-g6a0f9ebfc5e7 +dnl # drm: Add mode_config .get_format_info() hook +dnl # +AC_DEFUN([AC_AMDGPU_DRM_GET_FORMAT_INFO], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([drm_get_format_info], + [drivers/gpu/drm/drm_fourcc.c], [ + AC_DEFINE(HAVE_DRM_GET_FORMAT_INFO, 1, + [drm_get_format_info() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index a3030fc72c596..bf900dc220e7e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -85,6 +85,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_HELPER_MODE_FILL_FB_STRUCT AC_AMDGPU_DRM_FB_HELPER_INIT AC_AMDGPU_DRM_FRAMEBUFFER_FORMAT + AC_AMDGPU_DRM_GET_FORMAT_INFO AC_AMDGPU_DRM_HELPER_FORCE_DISABLE_ALL AC_AMDGPU_DRM_EDID_TO_ELD From 5677c4ae9548f7d8f9413cba551aa298a4852dfd Mon Sep 17 00:00:00 2001 From: changzhu Date: Mon, 13 Aug 2018 17:21:10 +0800 Subject: [PATCH 0226/1868] drm/amdkcl: [4.16] fix drm .last code, .output_poll_changed conflict .last_close and .output_poll_changed helpers are introduced in the same commit v4.14-rc3-576-g304a4f6accac drm_fb_helper_output_poll_changed & drm_fb_helper_lastclose can't be in amdkcl like other nonexistent symbols because there's no way to get fb_helper pointer from drm_device. amdgpu_device is required to get fb_helper pointer in this case. drm_device->fb_helper is introduced in v4.14-rc3-575-g29ad20b22c8f. and the 2 helper are introduced in v4.14-rc3-576-g304a4f6accac. Squash of 9d340fac6ea4 drm/amdkcl: add drm_fb_helper_output_poll_changed & drm_fb_helper_lastclose 686ea5e4ffe8 drm/amdkcl: refactor check for HAVE_DRM_FB_HELPER_LASTCLOSE 9c3af6d1cc70 drm/amdkcl: [4.16] fix drm .last code, .output_poll_changed conflict ae16f355fd44 drm/amdkcl: Test whether drm_fb_helper_lastclose is available 394828020901 drm/amdkcl: fix license for kcl backport part Signed-off-by: Yifan Zhang Signed-off-by: Slava Grigorev Signed-off-by: changzhu Reviewed-by: Rui Teng Signed-off-by: Flora Cui Signed-off-by: Jack Gui Signed-off-by: Flora Cui Acked-by: Feifei Xu Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/backport/backport.h | 1 + .../include/kcl/kcl_amdgpu_drm_fb_helper.h | 39 +++++++++++++++++++ 2 files changed, 40 insertions(+) create mode 100644 drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 786b0e8246e62..c75da3ec0fcb5 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -51,5 +51,6 @@ #include #include #include +#include "kcl/kcl_amdgpu_drm_fb_helper.h" #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h new file mode 100644 index 0000000000000..7b5938a2cd3ce --- /dev/null +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2006-2009 Red Hat Inc. + * Copyright (c) 2006-2008 Intel Corporation + * Copyright (c) 2007 Dave Airlie + * + * DRM framebuffer helper functions + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE. + * + * Authors: + * Dave Airlie + * Jesse Barnes + */ +#ifndef AMDGPU_BACKPORT_KCL_AMDGPU_DRM_FB_HELPER_H +#define AMDGPU_BACKPORT_KCL_AMDGPU_DRM_FB_HELPER_H + +#include + +#ifndef HAVE_DRM_FB_HELPER_LASTCLOSE +void drm_fb_helper_lastclose(struct drm_device *dev); +void drm_fb_helper_output_poll_changed(struct drm_device *dev); +#endif +#endif From ec2f7e047b0a5a885a245398d818bbde6867ec64 Mon Sep 17 00:00:00 2001 From: Kevin Wang Date: Wed, 15 Aug 2018 17:21:02 +0800 Subject: [PATCH 0227/1868] drm/amdkcl: fake drm_gem_fb_get_obj & kcl_drm_gem_fb_set_obj drm_gem_fb_get_obj() is introdued in v4.13-rc2-421-g4c3dbb2c312c. same with include/drm/drm_gem_framebuffer_helper.h fake a kcl copy for legacy kernel. Squash of e1357d7a01b8 drm/amdkcl: fake drm_gem_fb_get_obj & kcl_drm_gem_fb_set_obj c5ec212d2f24 drm/amdkcl: [4.14] fix drm_gem_object compile error Reviewed-by: Kevin Wang Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang Signed-off-by: Flora Cui Reviewed-by: Yang Xiong Change-Id: I2c087d77e289caabc6f5215f2bd54dc0e33e634e --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 8 ++++--- drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 3 +++ drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 6 +++--- .../include/kcl/kcl_amdgpu_drm_fb_helper.h | 21 +++++++++++++++++++ .../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 4 ++-- 9 files changed, 45 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 27cead4f33e2b..e744787b629e3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -216,13 +216,13 @@ int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc, work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0; /* schedule unpin of the old buffer */ - obj = crtc->primary->fb->obj[0]; + obj = drm_gem_fb_get_obj(crtc->primary->fb, 0); /* take a reference to the old object */ work->old_abo = gem_to_amdgpu_bo(obj); amdgpu_bo_ref(work->old_abo); - obj = fb->obj[0]; + obj = drm_gem_fb_get_obj(fb, 0); new_abo = gem_to_amdgpu_bo(obj); /* pin the new buffer */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c index 9db063a9e445c..8a71c31f394a4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c @@ -298,15 +298,17 @@ static int amdgpufb_create(struct drm_fb_helper *helper, static int amdgpu_fbdev_destroy(struct drm_device *dev, struct amdgpu_fbdev *rfbdev) { struct amdgpu_framebuffer *rfb = &rfbdev->rfb; + struct drm_gem_object *obj = NULL; int i; drm_fb_helper_unregister_fbi(&rfbdev->helper); + obj = drm_gem_fb_get_obj(&rfb->base, 0); if (rfb->base.obj[0]) { for (i = 0; i < rfb->base.format->num_planes; i++) drm_gem_object_put(rfb->base.obj[0]); amdgpufb_destroy_pinned_object(rfb->base.obj[0]); - rfb->base.obj[0] = NULL; + kcl_drm_gem_fb_set_obj(&rfb->base, 0, NULL); drm_framebuffer_unregister_private(&rfb->base); drm_framebuffer_cleanup(&rfb->base); } @@ -395,7 +397,7 @@ int amdgpu_fbdev_total_size(struct amdgpu_device *adev) if (!adev->mode_info.rfbdev) return 0; - robj = gem_to_amdgpu_bo(adev->mode_info.rfbdev->rfb.base.obj[0]); + robj = gem_to_amdgpu_bo(drm_gem_fb_get_obj(&adev->mode_info.rfbdev->rfb.base, 0)); size += amdgpu_bo_size(robj); return size; } @@ -404,7 +406,7 @@ bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj) { if (!adev->mode_info.rfbdev) return false; - if (robj == gem_to_amdgpu_bo(adev->mode_info.rfbdev->rfb.base.obj[0])) + if (robj == gem_to_amdgpu_bo(drm_gem_fb_get_obj(&adev->mode_info.rfbdev->rfb.base, 0))) return true; return false; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index 5e3faefc55109..3e175b1f54533 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -298,6 +298,9 @@ struct amdgpu_display_funcs { struct amdgpu_framebuffer { struct drm_framebuffer base; +#ifndef HAVE_DRM_DRM_GEM_FRAMEBUFFER_HELPER_H + struct drm_gem_object *obj; +#endif uint64_t tiling_flags; bool tmz_surface; diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index 3cc370c1dfdb0..36cda0ca61aac 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -1879,7 +1879,7 @@ static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc, /* If atomic, assume fb object is pinned & idle & fenced and * just update base pointers */ - obj = target_fb->obj[0]; + obj = drm_gem_fb_get_obj(target_fb, 0); abo = gem_to_amdgpu_bo(obj); r = amdgpu_bo_reserve(abo, false); if (unlikely(r != 0)) @@ -2091,7 +2091,7 @@ static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc, WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); if (!atomic && fb && fb != crtc->primary->fb) { - abo = gem_to_amdgpu_bo(fb->obj[0]); + abo = gem_to_amdgpu_bo(drm_gem_fb_get_obj(fb, 0)); r = amdgpu_bo_reserve(abo, true); if (unlikely(r != 0)) return r; @@ -2576,7 +2576,7 @@ static void dce_v10_0_crtc_disable(struct drm_crtc *crtc) int r; struct amdgpu_bo *abo; - abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]); + abo = gem_to_amdgpu_bo(drm_gem_fb_get_obj(crtc->primary->fb, 0)); r = amdgpu_bo_reserve(abo, true); if (unlikely(r)) DRM_ERROR("failed to reserve abo before unpin\n"); diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index 9882590e12cbe..c623e52263236 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -1929,7 +1929,7 @@ static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc, /* If atomic, assume fb object is pinned & idle & fenced and * just update base pointers */ - obj = target_fb->obj[0]; + obj = drm_gem_fb_get_obj(target_fb, 0); abo = gem_to_amdgpu_bo(obj); r = amdgpu_bo_reserve(abo, false); if (unlikely(r != 0)) @@ -2141,7 +2141,7 @@ static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc, WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); if (!atomic && fb && fb != crtc->primary->fb) { - abo = gem_to_amdgpu_bo(fb->obj[0]); + abo = gem_to_amdgpu_bo(drm_gem_fb_get_obj(fb, 0)); r = amdgpu_bo_reserve(abo, true); if (unlikely(r != 0)) return r; @@ -2660,7 +2660,7 @@ static void dce_v11_0_crtc_disable(struct drm_crtc *crtc) int r; struct amdgpu_bo *abo; - abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]); + abo = gem_to_amdgpu_bo(drm_gem_fb_get_obj(crtc->primary->fb, 0)); r = amdgpu_bo_reserve(abo, true); if (unlikely(r)) DRM_ERROR("failed to reserve abo before unpin\n"); diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c index 40ac8703fa33a..419480465d55f 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c @@ -1859,7 +1859,7 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc, /* If atomic, assume fb object is pinned & idle & fenced and * just update base pointers */ - obj = target_fb->obj[0]; + obj = drm_gem_fb_get_obj(target_fb, 0); abo = gem_to_amdgpu_bo(obj); r = amdgpu_bo_reserve(abo, false); if (unlikely(r != 0)) @@ -2049,7 +2049,7 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc, WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); if (!atomic && fb && fb != crtc->primary->fb) { - abo = gem_to_amdgpu_bo(fb->obj[0]); + abo = gem_to_amdgpu_bo(drm_gem_fb_get_obj(fb, 0)); r = amdgpu_bo_reserve(abo, true); if (unlikely(r != 0)) return r; @@ -2491,7 +2491,7 @@ static void dce_v6_0_crtc_disable(struct drm_crtc *crtc) int r; struct amdgpu_bo *abo; - abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]); + abo = gem_to_amdgpu_bo(drm_gem_fb_get_obj(crtc->primary->fb, 0)); r = amdgpu_bo_reserve(abo, true); if (unlikely(r)) DRM_ERROR("failed to reserve abo before unpin\n"); diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index d1546a207747f..4fde116498086 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -1825,7 +1825,7 @@ static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc, /* If atomic, assume fb object is pinned & idle & fenced and * just update base pointers */ - obj = target_fb->obj[0]; + obj = drm_gem_fb_get_obj(target_fb, 0); abo = gem_to_amdgpu_bo(obj); r = amdgpu_bo_reserve(abo, false); if (unlikely(r != 0)) @@ -2017,7 +2017,7 @@ static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc, WREG32(mmMASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0); if (!atomic && fb && fb != crtc->primary->fb) { - abo = gem_to_amdgpu_bo(fb->obj[0]); + abo = gem_to_amdgpu_bo(drm_gem_fb_get_obj(fb, 0)); r = amdgpu_bo_reserve(abo, true); if (unlikely(r != 0)) return r; @@ -2494,7 +2494,7 @@ static void dce_v8_0_crtc_disable(struct drm_crtc *crtc) int r; struct amdgpu_bo *abo; - abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]); + abo = gem_to_amdgpu_bo(drm_gem_fb_get_obj(crtc->primary->fb, 0)); r = amdgpu_bo_reserve(abo, true); if (unlikely(r)) DRM_ERROR("failed to reserve abo before unpin\n"); diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h index 7b5938a2cd3ce..7e316b60c45f9 100644 --- a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h @@ -31,9 +31,30 @@ #define AMDGPU_BACKPORT_KCL_AMDGPU_DRM_FB_HELPER_H #include +#include +#include "amdgpu.h" #ifndef HAVE_DRM_FB_HELPER_LASTCLOSE void drm_fb_helper_lastclose(struct drm_device *dev); void drm_fb_helper_output_poll_changed(struct drm_device *dev); #endif + +static inline +void kcl_drm_gem_fb_set_obj(struct drm_framebuffer *fb, int index, struct drm_gem_object *obj) +{ +#ifdef HAVE_DRM_DRM_GEM_FRAMEBUFFER_HELPER_H + if (fb) + fb->obj[index] = obj; +#else + struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb); + (void)index; /* for compile un-used warning */ + if (afb) + afb->obj = obj; +#endif +} +#ifndef HAVE_DRM_DRM_GEM_FRAMEBUFFER_HELPER_H +struct drm_gem_object *drm_gem_fb_get_obj(struct drm_framebuffer *fb, + unsigned int plane); +#endif + #endif diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 1ff469ef51af1..ed1a7d56e4d95 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -935,7 +935,7 @@ static int amdgpu_dm_plane_helper_prepare_fb(struct drm_plane *plane, } afb = to_amdgpu_framebuffer(new_state->fb); - obj = new_state->fb->obj[0]; + obj = drm_gem_fb_get_obj(new_state->fb, 0); rbo = gem_to_amdgpu_bo(obj); adev = amdgpu_ttm_adev(rbo->tbo.bdev); @@ -1023,7 +1023,7 @@ static void amdgpu_dm_plane_helper_cleanup_fb(struct drm_plane *plane, if (!old_state->fb) return; - rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]); + rbo = gem_to_amdgpu_bo(drm_gem_fb_get_obj(old_state->fb, 0)); r = amdgpu_bo_reserve(rbo, false); if (unlikely(r)) { DRM_ERROR("failed to reserve rbo before unpin\n"); From 779ed4a750e4f383512d4450efad323b26a008e8 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 15 Jun 2020 15:36:36 +0800 Subject: [PATCH 0228/1868] drm/amdkcl: fake drm_gem_fb_destroy & drm_gem_fb_create_handle the 2 api are introduced in commit v4.13-rc2-421-g4c3dbb2c312c, could leverage test for drm/drm_gem_framebuffer_helper.h Signed-off-by: Flora Cui Reviewed-by: Yang Xiong Change-Id: I55b7e056751e522ef827cadb905468675e342d96 --- .../drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h index 7e316b60c45f9..40a89aea46e78 100644 --- a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h @@ -55,6 +55,9 @@ void kcl_drm_gem_fb_set_obj(struct drm_framebuffer *fb, int index, struct drm_ge #ifndef HAVE_DRM_DRM_GEM_FRAMEBUFFER_HELPER_H struct drm_gem_object *drm_gem_fb_get_obj(struct drm_framebuffer *fb, unsigned int plane); +void drm_gem_fb_destroy(struct drm_framebuffer *fb); +int drm_gem_fb_create_handle(struct drm_framebuffer *fb, struct drm_file *file, + unsigned int *handle); #endif #endif From 43aacca80424c449d20f21a8ffccc64b965faca4 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 9 Jul 2024 10:29:27 +0800 Subject: [PATCH 0229/1868] drm/amdkcl: test drm_device->driver_features Signed-off-by: Yifan Zhang Signed-off-by: Flora Cui Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 18 +++++++++++++--- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../gpu/drm/amd/dkms/m4/struct_drm_device.m4 | 21 +++++++++++++++++++ 3 files changed, 37 insertions(+), 3 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/struct_drm_device.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 03e9208fdfbb6..658ab7b372b42 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2331,8 +2331,17 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, kcl_drm_vma_offset_manager_init(ddev->vma_offset_manager); +#ifdef HAVE_DRM_DEVICE_DRIVER_FEATURES if (!supports_atomic) ddev->driver_features &= ~DRIVER_ATOMIC; +#else + /* warn the user if they mix atomic and non-atomic capable GPUs */ + if ((kms_driver.driver_features & DRIVER_ATOMIC) && !supports_atomic) + DRM_ERROR("Mixing atomic and non-atomic capable GPUs!\n"); + /* support atomic early so the atomic debugfs stuff gets created */ + if (supports_atomic) + kms_driver.driver_features |= DRIVER_ATOMIC; +#endif kcl_pci_configure_extended_tags(pdev); ret = pci_enable_device(pdev); @@ -2980,9 +2989,12 @@ const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { static const struct drm_driver amdgpu_kms_driver = { .driver_features = - DRIVER_ATOMIC | - DRIVER_GEM | - DRIVER_RENDER | DRIVER_MODESET + 0 +#ifdef HAVE_DRM_DEVICE_DRIVER_FEATURES + | DRIVER_ATOMIC +#endif /* HAVE_DRM_DEVICE_DRIVER_FEATURES */ + | DRIVER_GEM + | DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ #ifdef HAVE_DRM_DRV_DRIVER_SYNCOBJ_TIMELINE | DRIVER_SYNCOBJ_TIMELINE diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index bf900dc220e7e..0f6e5d5e03484 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -70,6 +70,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_MM_INSERT_MODE AC_AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES AC_AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL + AC_AMDGPU_STRUCT_DRM_DEVICE AC_AMDGPU___DRM_ATOMIC_HELPER_CRTC_RESET AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION AC_AMDGPU_MEM_ENCRYPT_ACTIVE diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_device.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_device.m4 new file mode 100644 index 0000000000000..73fd46cf9315c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_device.m4 @@ -0,0 +1,21 @@ +dnl # +dnl # commit v4.19-rc1-194-g18ace11f87e6 +dnl # drm: Introduce per-device driver_features +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DEVICE_DRIVER_FEATURES], [ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_device *ddev = NULL; + ddev->driver_features = 0; + ],[ + AC_DEFINE(HAVE_DRM_DEVICE_DRIVER_FEATURES, 1, + [dev_device->driver_features is available]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_DEVICE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_AMDGPU_DRM_DEVICE_DRIVER_FEATURES + ]) +]) From 8702b33c64f5e5d3408b230e94235b695da5eda1 Mon Sep 17 00:00:00 2001 From: Adam Yang Date: Wed, 18 Sep 2019 16:37:51 +0800 Subject: [PATCH 0230/1868] drm/amdkcl: Test whether drm_driver->driver_features available test whether DRIVER_ATOMIC/DRIVER_SYNCOBJ_TIMELINE/DRIVER_IRQ_SHARED are available v1: drm/amdkcl: acommodate drmP.h drop for drm-driver-feature.m4 v2: drm/amdkcl: test DRIVER_PRIME is available Signed-off-by: Adam Yang Signed-off-by: Flora Cui Signed-off-by: Jack Gui --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 9 +++ .../gpu/drm/amd/dkms/m4/drm-driver-feature.m4 | 78 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 88 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-driver-feature.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 658ab7b372b42..dbb72622e7555 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2331,6 +2331,7 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, kcl_drm_vma_offset_manager_init(ddev->vma_offset_manager); +#ifdef HAVE_DRM_DRV_DRIVER_ATOMIC #ifdef HAVE_DRM_DEVICE_DRIVER_FEATURES if (!supports_atomic) ddev->driver_features &= ~DRIVER_ATOMIC; @@ -2341,6 +2342,7 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, /* support atomic early so the atomic debugfs stuff gets created */ if (supports_atomic) kms_driver.driver_features |= DRIVER_ATOMIC; +#endif #endif kcl_pci_configure_extended_tags(pdev); @@ -2993,6 +2995,13 @@ static const struct drm_driver amdgpu_kms_driver = { #ifdef HAVE_DRM_DEVICE_DRIVER_FEATURES | DRIVER_ATOMIC #endif /* HAVE_DRM_DEVICE_DRIVER_FEATURES */ + | DRIVER_HAVE_IRQ +#ifdef HAVE_DRM_DRV_DRIVER_IRQ_SHARED + | DRIVER_IRQ_SHARED +#endif /* HAVE_DRM_DRV_DRIVER_IRQ_SHARED */ +#ifdef HAVE_DRM_DRV_DRIVER_PRIME + | DRIVER_PRIME +#endif /* HAVE_DRM_DRV_DRIVER_PRIME */ | DRIVER_GEM | DRIVER_RENDER | DRIVER_MODESET | DRIVER_SYNCOBJ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-driver-feature.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-driver-feature.m4 new file mode 100644 index 0000000000000..3afe53a169b8c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-driver-feature.m4 @@ -0,0 +1,78 @@ +dnl # +dnl # commit 88a48e297b3a3bac6022c03babfb038f1a886cea +dnl # drm: add atomic properties +dnl # commit 0e2a933b02c972919f7478364177eb76cd4ae00d +dnl # drm: Switch DRIVER_ flags to an enum +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DRIVER_FEATURE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drmP.h], [ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + int _ = DRIVER_ATOMIC; + ], [ + AC_DEFINE(HAVE_DRM_DRV_DRIVER_ATOMIC, 1, [ + drm_driver_feature DRIVER_ATOMIC is available]) + ]) + ], [ + AC_DEFINE(HAVE_DRM_DRV_DRIVER_ATOMIC, 1, [ + drm_driver_feature DRIVER_ATOMIC is available]) + ]) + ]) + + dnl # + dnl # commit: 060cebb20cdbcd3185d593e7194fa7a738201817 + dnl # drm: introduce a capability flag for syncobj timeline support + dnl # + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drmP.h], [ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + int _ = DRIVER_SYNCOBJ_TIMELINE; + ],[ + AC_DEFINE(HAVE_DRM_DRV_DRIVER_SYNCOBJ_TIMELINE, 1, [ + drm_driver_feature DRIVER_SYNCOBJ_TIMELINE is available]) + ]) + ], [ + AC_DEFINE(HAVE_DRM_DRV_DRIVER_SYNCOBJ_TIMELINE, 1, [ + drm_driver_feature DRIVER_SYNCOBJ_TIMELINE is available]) + ]) + ]) + + dnl # + dnl # commit: 1ff494813bafa127ecba1160262ba39b2fdde7ba + dnl # drm/irq: Ditch DRIVER_IRQ_SHARED + dnl # + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drmP.h], [ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + int _ = DRIVER_IRQ_SHARED; + ],[ + AC_DEFINE(HAVE_DRM_DRV_DRIVER_IRQ_SHARED, 1, [ + drm_driver_feature DRIVER_IRQ_SHARED is available]) + ]) + ]) + ]) + + dnl # + dnl # commit: v5.2-rc5-867-g0424fdaf883a + dnl # drm/prime: Actually remove DRIVER_PRIME everywhere + dnl # + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drmP.h], [ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + int _ = DRIVER_PRIME; + ],[ + AC_DEFINE(HAVE_DRM_DRV_DRIVER_PRIME, 1, [ + drm_driver_feature DRIVER_PRIME is available]) + ]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 0f6e5d5e03484..e488c5030fad9 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -71,6 +71,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES AC_AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL AC_AMDGPU_STRUCT_DRM_DEVICE + AC_AMDGPU_DRM_DRIVER_FEATURE AC_AMDGPU___DRM_ATOMIC_HELPER_CRTC_RESET AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION AC_AMDGPU_MEM_ENCRYPT_ACTIVE From 356661044943f11c0c051d4b1b0e8cfba36766c4 Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Wed, 22 Apr 2020 21:26:01 +0800 Subject: [PATCH 0231/1868] drm/amdkcl: test drm_device->open_count squash of b6521032d361 drm/amdkcl: fix drm/drm_device.h in m4 578fa0c102a1 drm/amdkcl: add AC_AMDGPU_STRUCT_DRM_DEVICE Signed-off-by: Yifan Zhang Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++++ .../gpu/drm/amd/dkms/m4/struct_drm_device.m4 | 17 +++++++++++++++++ 2 files changed, 21 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 49d7e0807e3a4..7e522400e44dd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -2037,7 +2037,11 @@ static bool amdgpu_switcheroo_can_switch(struct pci_dev *pdev) * locking inversion with the driver load path. And the access here is * completely racy anyway. So don't bother with locking for now. */ +#ifdef HAVE_DRM_DEVICE_OPEN_COUNT_INT + return dev->open_count == 0; +#else return atomic_read(&dev->open_count) == 0; +#endif } static const struct vga_switcheroo_client_ops amdgpu_switcheroo_ops = { diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_device.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_device.m4 index 73fd46cf9315c..7016ff6694c88 100644 --- a/drivers/gpu/drm/amd/dkms/m4/struct_drm_device.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_device.m4 @@ -14,8 +14,25 @@ AC_DEFUN([AC_AMDGPU_DRM_DEVICE_DRIVER_FEATURES], [ ]) ]) +dnl # +dnl # commit v5.5-rc2-1419-g7e13ad896484 +dnl # drm: Avoid drm_global_mutex for simple inc/dec of dev->open_count +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DEVICE_OPEN_COUNT], [ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_device *ddev = NULL; + ddev->open_count = 0; + ],[ + AC_DEFINE(HAVE_DRM_DEVICE_OPEN_COUNT_INT, 1, + [drm_device->open_count is int]) + ]) +]) + AC_DEFUN([AC_AMDGPU_STRUCT_DRM_DEVICE], [ AC_KERNEL_DO_BACKGROUND([ AC_AMDGPU_DRM_DEVICE_DRIVER_FEATURES + AC_AMDGPU_DRM_DEVICE_OPEN_COUNT ]) ]) From c72ffc0ab86a78428d0e185c60a88e920c322770 Mon Sep 17 00:00:00 2001 From: Yintian Tao Date: Mon, 2 Mar 2020 17:09:57 +0800 Subject: [PATCH 0232/1868] drm/amdkcl: get drm_dev reference Before 4.18.0, drm_dev_unplug will confirm dev->open_count to detemine whether to call drm_dev_put(), it will raise the problem below. Therefore, to get drm_dev_reference ensure not release drm_device before amdgpu_driver_unload_kms(). [ 43.055735] ------------[ cut here ]------------ [ 43.055736] Memory manager not clean during takedown. [ 43.055777] WARNING: CPU: 1 PID: 2807 at /build/linux-hwe-9KJ07q/linux-hwe-4.18.0/drivers/gpu/drm/drm_mm.c:913 drm_mm_takedown+0x24/0x30 [drm] [ 43.055778] Modules linked in: amdgpu(OE-) amd_sched(OE) amdttm(OE) amdkcl(OE) amd_iommu_v2 drm_kms_helper drm i2c_algo_bit fb_sys_fops syscopyarea sysfillrect sysimgblt snd_hda_codec_generic nfit kvm_intel kvm irqbypass crct10dif_pclmul crc32_pclmul snd_hda_intel snd_hda_codec snd_hda_core snd_hwdep snd_pcm ghash_clmulni_intel snd_seq_midi snd_seq_midi_event pcbc snd_rawmidi snd_seq snd_seq_device aesni_intel snd_timer joydev aes_x86_64 crypto_simd cryptd glue_helper snd soundcore input_leds mac_hid serio_raw qemu_fw_cfg binfmt_misc sch_fq_codel nfsd auth_rpcgss nfs_acl lockd grace sunrpc parport_pc ppdev lp parport ip_tables x_tables autofs4 hid_generic floppy usbhid psmouse hid i2c_piix4 e1000 pata_acpi [ 43.055819] CPU: 1 PID: 2807 Comm: modprobe Tainted: G OE 4.18.0-15-generic #16~18.04.1-Ubuntu [ 43.055820] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 1.12.0-1 04/01/2014 [ 43.055830] RIP: 0010:drm_mm_takedown+0x24/0x30 [drm] [ 43.055831] Code: 84 00 00 00 00 00 0f 1f 44 00 00 48 8b 47 38 48 83 c7 38 48 39 c7 75 02 f3 c3 55 48 c7 c7 38 33 80 c0 48 89 e5 e8 1c 41 ec d0 <0f> 0b 5d c3 0f 1f 84 00 00 00 00 00 0f 1f 44 00 00 55 48 89 e5 41 [ 43.055857] RSP: 0018:ffffae33c1393d28 EFLAGS: 00010286 [ 43.055859] RAX: 0000000000000000 RBX: ffff9651b4a29800 RCX: 0000000000000006 [ 43.055860] RDX: 0000000000000007 RSI: 0000000000000096 RDI: ffff9651bfc964b0 [ 43.055861] RBP: ffffae33c1393d28 R08: 00000000000002a6 R09: 0000000000000004 [ 43.055861] R10: ffffae33c1393d20 R11: 0000000000000001 R12: ffff9651ba6cb000 [ 43.055863] R13: ffff9651b7f40000 R14: ffffffffc0de3a10 R15: ffff9651ba5c6460 [ 43.055864] FS: 00007f1d3c08d540(0000) GS:ffff9651bfc80000(0000) knlGS:0000000000000000 [ 43.055865] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 43.055866] CR2: 00005630a5831640 CR3: 000000012e274004 CR4: 00000000003606e0 [ 43.055870] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 [ 43.055871] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 [ 43.055871] Call Trace: [ 43.055885] drm_vma_offset_manager_destroy+0x1b/0x30 [drm] [ 43.055894] drm_gem_destroy+0x19/0x40 [drm] [ 43.055903] drm_dev_fini+0x7f/0x90 [drm] [ 43.055911] drm_dev_release+0x2b/0x40 [drm] [ 43.055919] drm_dev_unplug+0x64/0x80 [drm] [ 43.055994] amdgpu_pci_remove+0x39/0x70 [amdgpu] [ 43.055998] pci_device_remove+0x3e/0xc0 [ 43.056001] device_release_driver_internal+0x18a/0x260 [ 43.056003] driver_detach+0x3f/0x80 [ 43.056004] bus_remove_driver+0x59/0xd0 [ 43.056006] driver_unregister+0x2c/0x40 [ 43.056008] pci_unregister_driver+0x22/0xa0 [ 43.056087] amdgpu_exit+0x15/0x57c [amdgpu] [ 43.056090] __x64_sys_delete_module+0x146/0x280 [ 43.056094] do_syscall_64+0x5a/0x120 [ 43.056097] entry_SYSCALL_64_after_hwframe+0x44/0xa9 [ 43.056098] RIP: 0033:0x7f1d3bbb31b7 v2: use < 4.19.0 instead of <= 4.18.0 v3: move the version check into kcl v4: drm_dev_unplug() drop ref change in commit bd53280ef042 ("drm/drv: Fix incorrect resolution of merge conflict") rework kcl wrapper for the ref change Squash of 7109e9b49244 drm/amdkcl: rework kcl wrapper for drm_dev_unplug() e8364b615641 drm/amdkcl: add kcl wrapper for drm_dev_unplug 4e12efdfbcd4 drm/amdkcl: get drm_dev reference Signed-off-by: Yintian Tao Reviewed-by: Flora Cui Signed-off-by: Flora Cui Reviewed-by: Yang Xiong --- .../drm/amd/amdkcl/kcl_drm_atomic_helper.c | 2 +- include/kcl/backport/kcl_drm_drv.h | 52 +++++++++++++++++++ 2 files changed, 53 insertions(+), 1 deletion(-) create mode 100644 include/kcl/backport/kcl_drm_drv.h diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c index c11911f2dcbc8..4ef77c1846213 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c @@ -26,7 +26,7 @@ * Daniel Vetter */ #include -#include +#include #ifdef AMDKCL__DRM_ATOMIC_HELPER_PLANE_RESET void _kcl__drm_atomic_helper_plane_reset(struct drm_plane *plane, diff --git a/include/kcl/backport/kcl_drm_drv.h b/include/kcl/backport/kcl_drm_drv.h new file mode 100644 index 0000000000000..dcc5c195b2d08 --- /dev/null +++ b/include/kcl/backport/kcl_drm_drv.h @@ -0,0 +1,52 @@ +/* + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * Copyright (c) 2009-2010, Code Aurora Forum. + * Copyright 2016 Intel Corp. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef __KCL_BACKPORT_KCL_DRM_DRV_H__ +#define __KCL_BACKPORT_KCL_DRM_DRV_H__ + +/* + * v5.1-rc5-1150-gbd53280ef042 drm/drv: Fix incorrect resolution of merge conflict + * v5.1-rc2-5-g3f04e0a6cfeb drm: Fix drm_release() and device unplug + */ +#if DRM_VERSION_CODE < DRM_VERSION(5, 2, 0) +static inline +void _kcl_drm_dev_unplug(struct drm_device *dev) +{ + unsigned int prev, post; + + drm_dev_get(dev); + + prev = kref_read(&dev->ref); + drm_dev_unplug(dev); + post = kref_read(&dev->ref); + + if (prev == post) + drm_dev_put(dev); +} +#define drm_dev_unplug _kcl_drm_dev_unplug +#endif + +#endif From aa1b2a142ad713260b74865ec0be36e7126c0710 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 12 Oct 2023 14:38:11 +0800 Subject: [PATCH 0233/1868] drm/amdkcl: add AMDKCL_AMDGPU_DEBUGFS_CLEANUP for debugfs_cleanup. macro AMDKCL_AMDGPU_DEBUGFS_CLEANUP would be more friendly for hybrid branch maintaining. Signed-off-by: Flora Cui Acked-by: Feifei Xu Change-Id: I006ec85bf1e697d4fb5173023f4f4ee9e81bf286 Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 19 +++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h | 5 +++++ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 6 ++++++ include/kcl/backport/kcl_drm_backport.h | 8 ++++++++ 4 files changed, 38 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c index cbef720de7797..8743a112831b1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c @@ -42,6 +42,25 @@ #if defined(CONFIG_DEBUG_FS) +#if defined(AMDKCL_AMDGPU_DEBUGFS_CLEANUP) +void amdgpu_debugfs_cleanup(struct drm_minor *minor) +{ + struct drm_info_node *node, *tmp; + + if (!&minor->debugfs_root) + return; + + mutex_lock(&minor->debugfs_lock); + list_for_each_entry_safe(node, tmp, + &minor->debugfs_list, list) { + debugfs_remove(node->dent); + list_del(&node->list); + kfree(node); + } + mutex_unlock(&minor->debugfs_lock); +} +#endif + /** * amdgpu_debugfs_process_reg_op - Handle MMIO register reads/writes * diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h index 0425432d8659b..68e7aa9ed2725 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h @@ -26,6 +26,11 @@ * Debugfs */ +#if defined(CONFIG_DEBUG_FS) +#if defined(AMDKCL_AMDGPU_DEBUGFS_CLEANUP) +void amdgpu_debugfs_cleanup(struct drm_minor *minor); +#endif +#endif int amdgpu_debugfs_regs_init(struct amdgpu_device *adev); int amdgpu_debugfs_init(struct amdgpu_device *adev); void amdgpu_debugfs_fini(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index dbb72622e7555..0e7199c2dba92 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3012,6 +3012,12 @@ static const struct drm_driver amdgpu_kms_driver = { .open = amdgpu_driver_open_kms, .postclose = amdgpu_driver_postclose_kms, .lastclose = amdgpu_driver_lastclose_kms, +#if defined(CONFIG_DEBUG_FS) +#if defined(AMDKCL_AMDGPU_DEBUGFS_CLEANUP) + .debugfs_cleanup = amdgpu_debugfs_cleanup, +#endif +#endif + .irq_handler = amdgpu_irq_handler, .ioctls = amdgpu_ioctls_kms, .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), .dumb_create = amdgpu_mode_dumb_create, diff --git a/include/kcl/backport/kcl_drm_backport.h b/include/kcl/backport/kcl_drm_backport.h index 1450036960b9c..84ca7b867d62d 100644 --- a/include/kcl/backport/kcl_drm_backport.h +++ b/include/kcl/backport/kcl_drm_backport.h @@ -2,6 +2,14 @@ #ifndef AMDKCL_DRM_BACKPORT_H #define AMDKCL_DRM_BACKPORT_H +/* + * commit v4.10-rc3-539-g086f2e5cde74 + * drm: debugfs: Remove all files automatically on cleanup + */ +#if DRM_VERSION_CODE < DRM_VERSION(4, 11, 0) +#define AMDKCL_AMDGPU_DEBUGFS_CLEANUP +#endif + #if DRM_VERSION_CODE >= DRM_VERSION(4, 17, 0) #define AMDKCL_AMDGPU_DMABUF_OPS #endif From faeb9b6c9a6e0c3ccdbd4f2e2a1c4a352e46d305 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 15 Apr 2020 14:42:32 +0800 Subject: [PATCH 0234/1868] drm/amdkcl: for drm_crtc_funcs->get_vblank_timestamp() add vblank macros AC_AMDGPU_GET_SCANOUT_POSITION_IN_DRM_DRIVER AC_AMDGPU_GET_VBLANK_TIMESTAMP_IN_DRM_DRIVER AC_AMDGPU_DRM_CALC_VBLTIMESTAMP_FROM_SCANOUTPOS AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS it is a squash of: commit 56d1d766045efd0a35ec331be7f176482022ac58 Author: Yifan Zhang Date: Tue Aug 6 13:46:25 2019 +0800 drm/amdkcl: use unsigned pipe v1: drm/amdkcl: drop kcl_amdgpu.c v2: merge unsigned pipe check into get-scanout-position Change-Id: If81006bf54584b6aff68082e0f4be48d1758cd7c Signed-off-by: Yifan Zhang Signed-off-by: Flora Cui Reviewed-by: Adam Yang Signed-off-by: Jack Gui Signed-off-by: Flora Cui commit 5e00d69a73fb4c5c0f888dcdeaca25bd42add60b Author: Slava Grigorev Date: Fri Feb 7 16:13:47 2020 -0500 drm/amdkcl: introduce parallel autoconf tests execution Change-Id: Ifff3054a6cd9403a6a34135bf5fb942f5aa760f8 Signed-off-by: Slava Grigorev drm/amdkcl: Test whether get_scanout_position has flags v1: drm/amd/autoconf: add a missing GET_SCANOUT_POSITION_HAVE_FLAGS v2: drm/amd/autoconf: fix drm_driver->get_scanout_position v3: drm/amdkcl: fix drm_driver->get_vblank_timestamp v4: drm/amd/autoconf: fix kcl_amdgpu_get_vblank_timestamp_kms() v5: drm/amdkcl: fix missing amdgpu_get_vblank_timestamp_kms() v6: drm/amd/autoconf: test drm_calc_vbltimestamp_from_scanoutpos() v7: fix macro for amdgpu_get_vblank_timestamp_kms() v8: drm/amdkcl: fix check for drm_driver->get_vblank_timestamp v9: drm/amdkcl: accommodate to drmP.h removal for drm-calc-vbltimestamp-from-scanoutpos.m4 v10: drm/amdkcl: accommodate to drmP.h removal for get-vblank-timestamp-in-struct-drm-driver.m4 v11: drm/amdkcl: merge use-unsigned-pipe.m4 into get-scanout-position-in-struct-drm-driver.m4 v12: drm/amdkcl: accommodate to drmP.h removal for get-scanout-position-in-struct-drm-driver.m4 Signed-off-by: Yifan Zhang Signed-off-by: Yifan Zhang Reviewed-by: Flora Cui Signed-off-by: Jack Gui History-1: v2.6.37-rc3-1-g27641c3f003e int (*get_scanout_position) (struct drm_device *dev, int crtc, int *vpos, int *hpos); v3.12-rc3-485-g8f6fce03ddaf - int *vpos, int *hpos); + int *vpos, int *hpos, ktime_t *stime, + ktime_t *etime); v4.3-rc2-44-g3bb403bf421b - int *vpos, int *hpos, ktime_t *stime, - ktime_t *etime); + int *vpos, int *hpos, + ktime_t *stime, ktime_t *etime, + ` const struct drm_display_mode *mode); v4.3-rc3-73-g88e72717c2de - int crtc, + unsigned int pipe, v4.11-rc7-1902-g1bf6ad622b9b - int (*get_scanout_position) (struct drm_device *dev, unsigned int pipe, - unsigned int flags, int *vpos, int *hpos, + bool (*get_scanout_position) (struct drm_device *dev, unsigned int pipe, + bool in_vblank_irq, int *vpos, int *hpos, History-2: v2.6.37-rc3-1-g27641c3f003e introduce int (*get_vblank_timestamp) (struct drm_device *dev, int crtc, int *max_error, struct timeval *vblank_time, unsigned flags); v4.3-rc3-73-g88e72717c2de - int (*get_vblank_timestamp) (struct drm_device *dev, int crtc, + int (*get_vblank_timestamp) (struct drm_device *dev, unsigned int pipe, v4.11-rc7-1899-gd673c02c4bdb - int (*get_vblank_timestamp) (struct drm_device *dev, unsigned int pipe, + bool (*get_vblank_timestamp) (struct drm_device *dev, unsigned int pipe, v4.11-rc7-1900-g3fcdcb270936 - unsigned flags); + bool in_vblank_irq); v4.14-rc3-721-g67680d3c0464 - struct timeval *vblank_time, + ktime_t *vblank_time, History-3: v2.6.37-rc3-1-g27641c3f003e int drm_calc_vbltimestamp_from_scanoutpos(struct drm_device *dev, int crtc, int *max_error, struct timeval *vblank_time, unsigned flags, struct drm_crtc *refcrtc) v3.13-rc8-550-g7da903ef0485 - struct drm_crtc *refcrtc); + const struct drm_crtc *refcrtc, + const struct drm_display_mode *mode); v4.2-rc3-517-gcc1ef118fc09 - int crtc, + unsigned int pipe, v4.3-rc2-43-geba1f35dfe14 - const struct drm_crtc *refcrtc, History-4: v4.11-rc7-1899-gd673c02c4bdb -int drm_calc_vbltimestamp_from_scanoutpos(struct drm_device *dev, +bool drm_calc_vbltimestamp_from_scanoutpos(struct drm_device *dev, v4.11-rc7-1900-g3fcdcb270936 - unsigned flags, + bool in_vblank_irq, v4.11-rc7-1902-g1bf6ad622b9b - bool in_vblank_irq, - const struct drm_display_mode *mode) + bool in_vblank_irq) v4.14-rc3-721-g67680d3c0464 - struct timeval *vblank_time, + ktime_t *vblank_time, Signed-off-by: Yifan Zhang Change-Id: I61cb503c47518e6f11769ec4382ba7984c6faa48 Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 7 + drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 58 +++++++++ drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 4 + drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 4 + drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 4 + drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 4 + drivers/gpu/drm/amd/backport/backport.h | 1 + .../drm/amd/backport/include/kcl/kcl_amdgpu.h | 121 ++++++++++++++++++ .../amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 6 +- .../drm-calc-vbltimestamp-from-scanoutpos.m4 | 58 +++++++++ ...t-scanout-position-in-struct-drm-driver.m4 | 94 ++++++++++++++ ...t-vblank-timestamp-in-struct-drm-driver.m4 | 68 ++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 | 28 ++++ 15 files changed, 458 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-calc-vbltimestamp-from-scanoutpos.m4 create mode 100644 drivers/gpu/drm/amd/dkms/m4/get-scanout-position-in-struct-drm-driver.m4 create mode 100644 drivers/gpu/drm/amd/dkms/m4/get-vblank-timestamp-in-struct-drm-driver.m4 create mode 100644 drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 4a9ce5c5eeba2..72523eeeb6e0e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1507,6 +1507,7 @@ int amdgpu_device_resume(struct drm_device *dev, bool fbcon); u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc); int amdgpu_enable_vblank_kms(struct drm_crtc *crtc); void amdgpu_disable_vblank_kms(struct drm_crtc *crtc); + int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 0e7199c2dba92..06bc5edf13c2d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3016,6 +3016,13 @@ static const struct drm_driver amdgpu_kms_driver = { #if defined(AMDKCL_AMDGPU_DEBUGFS_CLEANUP) .debugfs_cleanup = amdgpu_debugfs_cleanup, #endif +#endif +#ifndef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP + .get_vblank_counter = kcl_amdgpu_get_vblank_counter_kms, + .enable_vblank = kcl_amdgpu_enable_vblank_kms, + .disable_vblank = kcl_amdgpu_disable_vblank_kms, + .get_vblank_timestamp = kcl_amdgpu_get_vblank_timestamp_kms, + .get_scanout_position = kcl_amdgpu_get_crtc_scanout_position, #endif .irq_handler = amdgpu_irq_handler, .ioctls = amdgpu_ioctls_kms, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index 0f11987f307e9..781bd839bdf46 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -1628,6 +1628,64 @@ void amdgpu_disable_vblank_kms(struct drm_crtc *crtc) amdgpu_irq_put(adev, &adev->crtc_irq, idx); } +#ifndef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP +#if !defined(HAVE_DRM_CALC_VBLTIMESTAMP_FROM_SCANOUTPOS_USE_KTIMER_T_ARG) +/** + * amdgpu_get_vblank_timestamp_kms - get vblank timestamp + * + * @dev: drm dev pointer + * @crtc: crtc to get the timestamp for + * @max_error: max error + * @vblank_time: time value + * @flags: flags passed to the driver + * + * Gets the timestamp on the requested crtc based on the + * scanout position. (all asics). + * Returns postive status flags on success, negative error on failure. + */ +int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, + int *max_error, + struct timeval *vblank_time, + unsigned flags) +{ + struct drm_crtc *crtc; + struct amdgpu_device *adev = drm_to_adev(dev); + + if (pipe >= dev->num_crtcs) { + DRM_ERROR("Invalid crtc %u\n", pipe); + return -EINVAL; + } + + /* Get associated drm_crtc: */ + crtc = &adev->mode_info.crtcs[pipe]->base; + if (!crtc) { + /* This can occur on driver load if some component fails to + * initialize completely and driver is unloaded */ + DRM_ERROR("Uninitialized crtc %d\n", pipe); + return -EINVAL; + } + + /* Helper routine in DRM core does all the work: */ +#if defined(HAVE_DRM_CALC_VBLTIMESTAMP_FROM_SCANOUTPOS_DROP_MOD_ARG) + return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, + vblank_time, flags); +#elif defined(HAVE_DRM_CALC_VBLTIMESTAMP_FROM_SCANOUTPOS_HAVE_MODE_ARG) + return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, + vblank_time, flags, + &crtc->hwmode); +#elif defined(HAVE_DRM_CALC_VBLTIMESTAMP_FROM_SCANOUTPOS_HAVE_CRTC_MODE_ARG) + return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, + vblank_time, flags, + crtc, &crtc->hwmode); +#else + return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, + vblank_time, flags, + crtc); +#endif +} +#endif +#endif + /* * Debugfs info */ diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index 36cda0ca61aac..250b7d3c5a992 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -2504,10 +2504,12 @@ static const struct drm_crtc_funcs dce_v10_0_crtc_funcs = { .set_config = amdgpu_display_crtc_set_config, .destroy = dce_v10_0_crtc_destroy, .page_flip_target = amdgpu_display_crtc_page_flip_target, +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP .get_vblank_counter = amdgpu_get_vblank_counter_kms, .enable_vblank = amdgpu_enable_vblank_kms, .disable_vblank = amdgpu_disable_vblank_kms, .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, +#endif }; static void dce_v10_0_crtc_dpms(struct drm_crtc *crtc, int mode) @@ -2699,7 +2701,9 @@ static const struct drm_crtc_helper_funcs dce_v10_0_crtc_helper_funcs = { .prepare = dce_v10_0_crtc_prepare, .commit = dce_v10_0_crtc_commit, .disable = dce_v10_0_crtc_disable, +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP .get_scanout_position = amdgpu_crtc_get_scanout_position, +#endif }; static int dce_v10_0_crtc_init(struct amdgpu_device *adev, int index) diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index c623e52263236..1a6477928fd5a 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -2588,10 +2588,12 @@ static const struct drm_crtc_funcs dce_v11_0_crtc_funcs = { .set_config = amdgpu_display_crtc_set_config, .destroy = dce_v11_0_crtc_destroy, .page_flip_target = amdgpu_display_crtc_page_flip_target, +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP .get_vblank_counter = amdgpu_get_vblank_counter_kms, .enable_vblank = amdgpu_enable_vblank_kms, .disable_vblank = amdgpu_disable_vblank_kms, .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, +#endif }; static void dce_v11_0_crtc_dpms(struct drm_crtc *crtc, int mode) @@ -2812,7 +2814,9 @@ static const struct drm_crtc_helper_funcs dce_v11_0_crtc_helper_funcs = { .prepare = dce_v11_0_crtc_prepare, .commit = dce_v11_0_crtc_commit, .disable = dce_v11_0_crtc_disable, +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP .get_scanout_position = amdgpu_crtc_get_scanout_position, +#endif }; static int dce_v11_0_crtc_init(struct amdgpu_device *adev, int index) diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c index 419480465d55f..eb08d2b06179b 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c @@ -2423,10 +2423,12 @@ static const struct drm_crtc_funcs dce_v6_0_crtc_funcs = { .set_config = amdgpu_display_crtc_set_config, .destroy = dce_v6_0_crtc_destroy, .page_flip_target = amdgpu_display_crtc_page_flip_target, +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP .get_vblank_counter = amdgpu_get_vblank_counter_kms, .enable_vblank = amdgpu_enable_vblank_kms, .disable_vblank = amdgpu_disable_vblank_kms, .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, +#endif }; static void dce_v6_0_crtc_dpms(struct drm_crtc *crtc, int mode) @@ -2614,7 +2616,9 @@ static const struct drm_crtc_helper_funcs dce_v6_0_crtc_helper_funcs = { .prepare = dce_v6_0_crtc_prepare, .commit = dce_v6_0_crtc_commit, .disable = dce_v6_0_crtc_disable, +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP .get_scanout_position = amdgpu_crtc_get_scanout_position, +#endif }; static int dce_v6_0_crtc_init(struct amdgpu_device *adev, int index) diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index 4fde116498086..2a4515abd257f 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -2422,10 +2422,12 @@ static const struct drm_crtc_funcs dce_v8_0_crtc_funcs = { .set_config = amdgpu_display_crtc_set_config, .destroy = dce_v8_0_crtc_destroy, .page_flip_target = amdgpu_display_crtc_page_flip_target, +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP .get_vblank_counter = amdgpu_get_vblank_counter_kms, .enable_vblank = amdgpu_enable_vblank_kms, .disable_vblank = amdgpu_disable_vblank_kms, .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, +#endif }; static void dce_v8_0_crtc_dpms(struct drm_crtc *crtc, int mode) @@ -2624,7 +2626,9 @@ static const struct drm_crtc_helper_funcs dce_v8_0_crtc_helper_funcs = { .prepare = dce_v8_0_crtc_prepare, .commit = dce_v8_0_crtc_commit, .disable = dce_v8_0_crtc_disable, +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP .get_scanout_position = amdgpu_crtc_get_scanout_position, +#endif }; static int dce_v8_0_crtc_init(struct amdgpu_device *adev, int index) diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index c75da3ec0fcb5..7e5e5fc3d3d02 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -52,5 +52,6 @@ #include #include #include "kcl/kcl_amdgpu_drm_fb_helper.h" +#include "kcl/kcl_amdgpu.h" #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h new file mode 100644 index 0000000000000..9c0291d459b42 --- /dev/null +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h @@ -0,0 +1,121 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef AMDGPU_BACKPORT_KCL_AMDGPU_H +#define AMDGPU_BACKPORT_KCL_AMDGPU_H + +#include +#include "amdgpu.h" + +#ifndef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP + +#if defined(HAVE_VGA_USE_UNSIGNED_INT_PIPE) +static inline u32 kcl_amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int crtc) +#else +static inline u32 kcl_amdgpu_get_vblank_counter_kms(struct drm_device *dev, int crtc) +#endif +{ + struct drm_crtc *drm_crtc = drm_crtc_from_index(dev, crtc); + + return amdgpu_get_vblank_counter_kms(drm_crtc); +} + +#if defined(HAVE_VGA_USE_UNSIGNED_INT_PIPE) +static inline int kcl_amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int crtc) +#else +static inline int kcl_amdgpu_enable_vblank_kms(struct drm_device *dev, int crtc) +#endif +{ + struct drm_crtc *drm_crtc = drm_crtc_from_index(dev, crtc); + + return amdgpu_enable_vblank_kms(drm_crtc); +} + +#if defined(HAVE_VGA_USE_UNSIGNED_INT_PIPE) +static inline void kcl_amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int crtc) +#else +static inline void kcl_amdgpu_disable_vblank_kms(struct drm_device *dev, int crtc) +#endif +{ + struct drm_crtc *drm_crtc = drm_crtc_from_index(dev, crtc); + + return amdgpu_disable_vblank_kms(drm_crtc); +} + +#if defined(HAVE_GET_SCANOUT_POSITION_RETURN_BOOL) +static inline bool kcl_amdgpu_get_crtc_scanout_position(struct drm_device *dev, unsigned int pipe, + bool in_vblank_irq, int *vpos, int *hpos, + ktime_t *stime, ktime_t *etime, + const struct drm_display_mode *mode) +{ + return !!amdgpu_display_get_crtc_scanoutpos(dev, pipe, in_vblank_irq, vpos, hpos, stime, etime, mode); +} +#elif defined(HAVE_VGA_USE_UNSIGNED_INT_PIPE) +static inline int kcl_amdgpu_get_crtc_scanout_position(struct drm_device *dev, unsigned int crtc, + unsigned int flags, int *vpos, int *hpos, + ktime_t *stime, ktime_t *etime, + const struct drm_display_mode *mode) +{ + return amdgpu_display_get_crtc_scanoutpos(dev, crtc, flags, vpos, hpos, stime, etime, mode); +} +#elif defined(HAVE_GET_SCANOUT_POSITION_HAS_DRM_DISPLAY_MODE_ARG) +static inline int kcl_amdgpu_get_crtc_scanout_position(struct drm_device *dev, int crtc, + unsigned int flags, + int *vpos, int *hpos, + ktime_t *stime, ktime_t *etime, + const struct drm_display_mode *mode) +{ + return amdgpu_display_get_crtc_scanoutpos(dev, crtc, flags, vpos, hpos, stime, etime, mode); +} +#elif defined(HAVE_GET_SCANOUT_POSITION_HAS_TIMESTAMP_ARG) +static inline int kcl_amdgpu_get_crtc_scanout_position(struct drm_device *dev, int crtc, + int *vpos, int *hpos, ktime_t *stime, + ktime_t *etime) +{ + return amdgpu_display_get_crtc_scanoutpos(dev, crtc, 0, vpos, hpos, stime, etime, NULL); +} +#else +static inline int kcl_amdgpu_get_crtc_scanout_position(struct drm_device *dev, int crtc, + int *vpos, int *hpos) +{ + return amdgpu_display_get_crtc_scanoutpos(dev, crtc, 0, vpos, hpos, NULL, NULL, NULL); +} +#endif + +#if defined(HAVE_GET_VBLANK_TIMESTAMP_IN_DRM_DRIVER_HAS_KTIME_T) +static inline bool kcl_amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, + int *max_error, ktime_t *vblank_time, + bool in_vblank_irq) +{ + return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, vblank_time, in_vblank_irq); +} +#elif defined(HAVE_GET_VBLANK_TIMESTAMP_IN_DRM_DRIVER_HAS_BOOL_IN_VBLANK_IRQ) +static inline bool kcl_amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, + int *max_error, struct timeval *vblank_time, + bool in_vblank_irq) +{ + return !!amdgpu_get_vblank_timestamp_kms(dev, pipe, max_error, vblank_time, in_vblank_irq); +} +#elif defined(HAVE_GET_VBLANK_TIMESTAMP_IN_DRM_DRIVER_RETURN_BOOL) +static inline bool kcl_amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, + int *max_error, struct timeval *vblank_time, + unsigned flags) +{ + return !!amdgpu_get_vblank_timestamp_kms(dev, pipe, max_error, vblank_time, flags); +} +#elif defined(HAVE_VGA_USE_UNSIGNED_INT_PIPE) +static inline int kcl_amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, + int *max_error, struct timeval *vblank_time, + unsigned flags) +{ + return amdgpu_get_vblank_timestamp_kms(dev, pipe, max_error, vblank_time, flags); +} +#else +static inline int kcl_amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, int crtc, + int *max_error, + struct timeval *vblank_time, + unsigned flags) +{ + return amdgpu_get_vblank_timestamp_kms(dev, crtc, max_error, vblank_time, flags); +} +#endif +#endif /* HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP */ +#endif /* AMDGPU_BACKPORT_KCL_AMDGPU_H */ diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c index a2cf2c066a76d..af7a5a721dbc0 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c @@ -549,10 +549,12 @@ static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = { .set_crc_source = amdgpu_dm_crtc_set_crc_source, .verify_crc_source = amdgpu_dm_crtc_verify_crc_source, .get_crc_sources = amdgpu_dm_crtc_get_crc_sources, - .get_vblank_counter = amdgpu_get_vblank_counter_kms, .enable_vblank = amdgpu_dm_crtc_enable_vblank, .disable_vblank = amdgpu_dm_crtc_disable_vblank, +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP + .get_vblank_counter = amdgpu_get_vblank_counter_kms, .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, +#endif #if defined(CONFIG_DEBUG_FS) .late_register = amdgpu_dm_crtc_late_register, #endif @@ -678,7 +680,9 @@ static const struct drm_crtc_helper_funcs amdgpu_dm_crtc_helper_funcs = { .disable = amdgpu_dm_crtc_helper_disable, .atomic_check = amdgpu_dm_crtc_helper_atomic_check, .mode_fixup = amdgpu_dm_crtc_helper_mode_fixup, +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP .get_scanout_position = amdgpu_crtc_get_scanout_position, +#endif }; int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm, diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-calc-vbltimestamp-from-scanoutpos.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-calc-vbltimestamp-from-scanoutpos.m4 new file mode 100644 index 0000000000000..c69de05235130 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-calc-vbltimestamp-from-scanoutpos.m4 @@ -0,0 +1,58 @@ +dnl # +dnl # commit 67680d3c0464 +dnl # drm: vblank: use ktime_t instead of timeval +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CALC_VBLTIMESTAMP_FROM_SCANOUTPOS], [ + AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drmP.h], [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_calc_vbltimestamp_from_scanoutpos(NULL, 0, NULL, (ktime_t *)NULL, 0); + ], [drm_calc_vbltimestamp_from_scanoutpos], [drivers/gpu/drm/drm_vblank.c], [ + AC_DEFINE(HAVE_DRM_CALC_VBLTIMESTAMP_FROM_SCANOUTPOS_USE_KTIMER_T_ARG, 1, + [drm_calc_vbltimestamp_from_scanoutpos() use ktime_t arg]) + ], [ + dnl # + dnl # commit 1bf6ad622b9be + dnl # drm/vblank: drop the mode argument from drm_calc_vbltimestamp_from_scanoutpos + dnl # + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_calc_vbltimestamp_from_scanoutpos(NULL, 0, NULL, (struct timeval *)NULL, 0); + ], [drm_calc_vbltimestamp_from_scanoutpos], [drivers/gpu/drm/drm_vblank.c drivers/gpu/drm/drm_irq.c], [ + AC_DEFINE(HAVE_DRM_CALC_VBLTIMESTAMP_FROM_SCANOUTPOS_DROP_MOD_ARG, 1, + [drm_calc_vbltimestamp_from_scanoutpos() drop mode arg]) + ], [ + dnl # + dnl # commit eba1f35dfe14 + dnl # drm: Move timestamping constants into drm_vblank_crtc + dnl # + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_calc_vbltimestamp_from_scanoutpos(NULL, 0, NULL, NULL, 0, (const struct drm_display_mode *)NULL); + ], [drm_calc_vbltimestamp_from_scanoutpos], [drivers/gpu/drm/drm_irq.c], [ + AC_DEFINE(HAVE_DRM_CALC_VBLTIMESTAMP_FROM_SCANOUTPOS_HAVE_MODE_ARG, 1, + [drm_calc_vbltimestamp_from_scanoutpos() remove crtc arg]) + ], [ + dnl # + dnl # commit 7da903ef0485 + dnl # drm: Pass the display mode to drm_calc_vbltimestamp_from_scanoutpos() + dnl # + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_calc_vbltimestamp_from_scanoutpos(NULL, 0, NULL, NULL, 0, (const struct drm_crtc *)NULL, (const struct drm_display_mode *)NULL); + ], [drm_calc_vbltimestamp_from_scanoutpos], [drivers/gpu/drm/drm_irq.c], [ + AC_DEFINE(HAVE_DRM_CALC_VBLTIMESTAMP_FROM_SCANOUTPOS_HAVE_CRTC_MODE_ARG, 1, + [drm_calc_vbltimestamp_from_scanoutpos() have the crtc & mode arg]) + ]) + ]) + ]) + ]) + ], [ + AC_DEFINE(HAVE_DRM_CALC_VBLTIMESTAMP_FROM_SCANOUTPOS_USE_KTIMER_T_ARG, 1, + [drm_calc_vbltimestamp_from_scanoutpos() use ktime_t arg]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/get-scanout-position-in-struct-drm-driver.m4 b/drivers/gpu/drm/amd/dkms/m4/get-scanout-position-in-struct-drm-driver.m4 new file mode 100644 index 0000000000000..6f0105f6f9890 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/get-scanout-position-in-struct-drm-driver.m4 @@ -0,0 +1,94 @@ +dnl # +dnl # commit v4.11-rc7-1902-g1bf6ad622b9b +dnl # drm/vblank: drop the mode argument from drm_calc_vbltimestamp_from_scanoutpos +dnl # +AC_DEFUN([AC_AMDGPU_GET_SCANOUT_POSITION_IN_DRM_DRIVER], [ + AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drmP.h], [ + AC_KERNEL_TRY_COMPILE([ + #include + bool foo(struct drm_device *dev, unsigned int pipe, + bool in_vblank_irq, int *vpos, int *hpos, + ktime_t *stime, ktime_t *etime, + const struct drm_display_mode *mode) + { + return false; + } + ], [ + struct drm_driver *bar = NULL; + bar->get_scanout_position = foo; + ], [ + AC_DEFINE(HAVE_GET_SCANOUT_POSITION_RETURN_BOOL, 1, + [get_scanout_position return bool]) + AC_DEFINE(HAVE_VGA_USE_UNSIGNED_INT_PIPE, 1, + [get_scanout_position use unsigned int pipe]) + ], [ + dnl # + dnl # commit v4.3-rc3-73-g88e72717c2de + dnl # drm/irq: Use unsigned int pipe in public API + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + int foo(struct drm_device *dev, unsigned int pipe, + unsigned int flags, int *vpos, int *hpos, + ktime_t *stime, ktime_t *etime, + const struct drm_display_mode *mode) + { + return 0; + } + ], [ + struct drm_driver *bar = NULL; + bar->get_scanout_position = foo; + ], [ + AC_DEFINE(HAVE_VGA_USE_UNSIGNED_INT_PIPE, 1, + [get_scanout_position use unsigned int pipe]) + ], [ + dnl # + dnl # commit v4.3-rc2-44-g3bb403bf421b + dnl # drm: Stop using linedur_ns and pixeldur_ns for vblank timestamps + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + int foo(struct drm_device *dev, int crtc, + unsigned int flags, + int *vpos, int *hpos, + ktime_t *stime, ktime_t *etime, + const struct drm_display_mode *mode) + { + return 0; + } + ], [ + struct drm_driver *bar = NULL; + bar->get_scanout_position = foo; + ], [ + AC_DEFINE(HAVE_GET_SCANOUT_POSITION_HAS_DRM_DISPLAY_MODE_ARG, 1, + [get_scanout_position has struct drm_display_mode arg]) + ], [ + dnl # + dnl # commit v3.12-rc3-485-g8f6fce03ddaf + dnl # drm: Push latency sensitive bits of vblank scanoutpos timestamping into kms drivers. + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + int foo(struct drm_device *dev, int crtc, + int *vpos, int *hpos, ktime_t *stime, + ktime_t *etime) + { + return 0; + } + ], [ + struct drm_driver *bar = NULL; + bar->get_scanout_position = foo; + ], [ + AC_DEFINE(HAVE_GET_SCANOUT_POSITION_HAS_TIMESTAMP_ARG, 1, + [get_scanout_position has timestamp arg]) + ]) + ]) + ]) + ]) + ], [ + AC_DEFINE(HAVE_GET_SCANOUT_POSITION_RETURN_BOOL, 1, + [get_scanout_position return bool]) + AC_DEFINE(HAVE_VGA_USE_UNSIGNED_INT_PIPE, 1, + [get_scanout_position use unsigned int pipe]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/get-vblank-timestamp-in-struct-drm-driver.m4 b/drivers/gpu/drm/amd/dkms/m4/get-vblank-timestamp-in-struct-drm-driver.m4 new file mode 100644 index 0000000000000..8037673d5aa39 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/get-vblank-timestamp-in-struct-drm-driver.m4 @@ -0,0 +1,68 @@ +dnl # commit v4.14-rc3-721-g67680d3c0464 +dnl # drm: vblank: use ktime_t instead of timeval +dnl # +AC_DEFUN([AC_AMDGPU_GET_VBLANK_TIMESTAMP_IN_DRM_DRIVER], [ + AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drmP.h], [ + AC_KERNEL_TRY_COMPILE([ + #include + bool foo(struct drm_device *dev, unsigned int pipe, + int *max_error, + ktime_t *vblank_time, + bool in_vblank_irq) + { + return false; + } + ], [ + struct drm_driver *bar = NULL; + bar->get_vblank_timestamp = foo; + ], [ + AC_DEFINE(HAVE_GET_VBLANK_TIMESTAMP_IN_DRM_DRIVER_HAS_KTIME_T, 1, + [get_vblank_timestamp has ktime_t arg]) + ], [ + dnl + dnl # commit v4.11-rc7-1900-g3fcdcb270936 + dnl # drm/vblank: Switch to bool in_vblank_irq in get_vblank_timestamp + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + bool foo(struct drm_device *dev, unsigned int pipe, + int *max_error, + struct timeval *vblank_time, + bool in_vblank_irq) + { + return false; + } + ], [ + struct drm_driver *bar = NULL; + bar->get_vblank_timestamp = foo; + ], [ + AC_DEFINE(HAVE_GET_VBLANK_TIMESTAMP_IN_DRM_DRIVER_HAS_BOOL_IN_VBLANK_IRQ, 1, + [get_vblank_timestamp has bool in_vblank_irq arg]) + ], [ + dnl # + dnl # commit id v4.11-rc7-1899-gd673c02c4bdb + dnl # drm/vblank: Switch drm_driver->get_vblank_timestamp to return a bool + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + bool foo(struct drm_device *dev, unsigned int pipe, + int *max_error, + struct timeval *vblank_time, + unsigned flags) + { + return false; + } + ], [ + struct drm_driver *bar = NULL; + bar->get_vblank_timestamp = foo; + ], [ + AC_DEFINE(HAVE_GET_VBLANK_TIMESTAMP_IN_DRM_DRIVER_RETURN_BOOL, 1, + [get_vblank_timestamp return bool]) + ]) + ]) + ]) + ], [ + AC_DEFINE(HAVE_GET_VBLANK_TIMESTAMP_IN_DRM_DRIVER_HAS_KTIME_T, 1, + [get_vblank_timestamp has ktime_t arg]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index e488c5030fad9..6d4e444051a97 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -90,6 +90,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_GET_FORMAT_INFO AC_AMDGPU_DRM_HELPER_FORCE_DISABLE_ALL AC_AMDGPU_DRM_EDID_TO_ELD + AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 new file mode 100644 index 0000000000000..f70303a508a0e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 @@ -0,0 +1,28 @@ +dnl # +dnl # v5.5-rc2-1557-ge3eff4b5d91e drm/amdgpu: Convert to CRTC VBLANK callbacks +dnl # v5.5-rc2-1556-gea702333e567 drm/amdgpu: Convert to struct drm_crtc_helper_funcs.get_scanout_position() +dnl # v5.5-rc2-1555-g7fe3f0d15aac drm: Add get_vblank_timestamp() to struct drm_crtc_funcs +dnl # v5.5-rc2-1554-gf1e2b6371c12 drm: Add get_scanout_position() to struct drm_crtc_helper_funcs +dnl # +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_crtc_funcs *ptr = NULL; + ptr->get_vblank_timestamp(NULL, NULL, NULL, 0); + ],[ + AC_DEFINE(HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP, + 1, + [struct drm_crtc_funcs->get_vblank_timestamp() is available]) + ],[ + AC_AMDGPU_GET_SCANOUT_POSITION_IN_DRM_DRIVER + AC_AMDGPU_GET_VBLANK_TIMESTAMP_IN_DRM_DRIVER + AC_AMDGPU_DRM_CALC_VBLTIMESTAMP_FROM_SCANOUTPOS + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS], [ + AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP +]) From 820c09a7e834be92c1738127cc46e4dcd781a53f Mon Sep 17 00:00:00 2001 From: Junwei Zhang Date: Mon, 26 Dec 2016 14:26:42 +0800 Subject: [PATCH 0235/1868] drm/amdkcl: test for drm_crtc_funcs->page_flip_target() drm_crtc_funcs->page_flip_target() is introduced in v4.8-rc1-112-gc229bfbbd04a the prototype change is introduced in v4.11-rc3-945-g41292b1fa13a Squash of cf36daa8cd0c drm/amdkcl: missing check with HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET aa624db31f13 drm/amdkcl: test for drm_crtc_funcs->page_flip_target() a2fc1ef061a5 drm/amdkcl: [4.9] fix amdgpu_crtc_page_flip_target() Signed-off-by: Junwei Zhang Reviewed-by: Qiang Yu Signed-off-by: Jack Gui Signed-off-by: Jiansong Chen Signed-off-by: Yifan Zhang Signed-off-by: Flora Cui Reviewed-by: Yang Xiong --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4 + drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 216 ++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 13 ++ drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 4 + drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 4 + drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 4 + drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 4 + .../drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 | 35 +++ 8 files changed, 284 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 72523eeeb6e0e..3a0239cfac171 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -471,7 +471,11 @@ void amdgpu_fence_slab_fini(void); */ struct amdgpu_flip_work { +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET struct delayed_work flip_work; +#else + struct work_struct flip_work; +#endif struct work_struct unpin_work; struct amdgpu_device *adev; int crtc_id; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index e744787b629e3..155f7e0bfbccf 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -94,7 +94,11 @@ static void amdgpu_display_flip_callback(struct dma_fence *f, container_of(cb, struct amdgpu_flip_work, cb); dma_fence_put(f); +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET schedule_work(&work->flip_work.work); +#else + schedule_work(&work->flip_work); +#endif } static bool amdgpu_display_flip_handle_fence(struct amdgpu_flip_work *work, @@ -115,6 +119,89 @@ static bool amdgpu_display_flip_handle_fence(struct amdgpu_flip_work *work, return false; } +#if !defined(HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET) +static void amdgpu_flip_work_func(struct work_struct *__work) +{ + struct amdgpu_flip_work *work = + container_of(__work, struct amdgpu_flip_work, flip_work); + struct amdgpu_device *adev = work->adev; + struct amdgpu_crtc *amdgpuCrtc = adev->mode_info.crtcs[work->crtc_id]; + + struct drm_crtc *crtc = &amdgpuCrtc->base; + unsigned long flags; + unsigned i, repcnt = 4; + int vpos, hpos, stat, min_udelay = 0; + struct drm_vblank_crtc *vblank = &crtc->dev->vblank[work->crtc_id]; + + if (amdgpu_display_flip_handle_fence(work, &work->excl)) + return; + + for (i = 0; i < work->shared_count; ++i) + if (amdgpu_display_flip_handle_fence(work, &work->shared[i])) + return; + + /* We borrow the event spin lock for protecting flip_status */ + spin_lock_irqsave(&crtc->dev->event_lock, flags); + + /* If this happens to execute within the "virtually extended" vblank + * interval before the start of the real vblank interval then it needs + * to delay programming the mmio flip until the real vblank is entered. + * This prevents completing a flip too early due to the way we fudge + * our vblank counter and vblank timestamps in order to work around the + * problem that the hw fires vblank interrupts before actual start of + * vblank (when line buffer refilling is done for a frame). It + * complements the fudging logic in amdgpu_display_get_crtc_scanoutpos() for + * timestamping and amdgpu_get_vblank_counter_kms() for vblank counts. + * + * In practice this won't execute very often unless on very fast + * machines because the time window for this to happen is very small. + */ + while (amdgpuCrtc->enabled && --repcnt) { + /* GET_DISTANCE_TO_VBLANKSTART returns distance to real vblank + * start in hpos, and to the "fudged earlier" vblank start in + * vpos. + */ + stat = amdgpu_display_get_crtc_scanoutpos(adev_to_drm(adev), work->crtc_id, + GET_DISTANCE_TO_VBLANKSTART, + &vpos, &hpos, NULL, NULL, + &crtc->hwmode); + + if ((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != + (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE) || + !(vpos >= 0 && hpos <= 0)) + break; + + /* Sleep at least until estimated real start of hw vblank */ + min_udelay = (-hpos + 1) * max(vblank->linedur_ns / 1000, 5); + if (min_udelay > vblank->framedur_ns / 2000) { + /* Don't wait ridiculously long - something is wrong */ + repcnt = 0; + break; + } + spin_unlock_irqrestore(&crtc->dev->event_lock, flags); + usleep_range(min_udelay, 2 * min_udelay); + spin_lock_irqsave(&crtc->dev->event_lock, flags); + } + + if (!repcnt) + DRM_DEBUG_DRIVER("Delay problem on crtc %d: min_udelay %d, " + "framedur %d, linedur %d, stat %d, vpos %d, " + "hpos %d\n", work->crtc_id, min_udelay, + vblank->framedur_ns / 1000, + vblank->linedur_ns / 1000, stat, vpos, hpos); + + /* Do the flip (mmio) */ + adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base, work->async); + + /* Set the flip status */ + amdgpuCrtc->pflip_status = AMDGPU_FLIP_SUBMITTED; + spin_unlock_irqrestore(&crtc->dev->event_lock, flags); + + + DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_SUBMITTED, work: %p,\n", + amdgpuCrtc->crtc_id, amdgpuCrtc, work); +} +#else static void amdgpu_display_flip_work_func(struct work_struct *__work) { struct delayed_work *delayed_work = @@ -164,6 +251,7 @@ static void amdgpu_display_flip_work_func(struct work_struct *__work) amdgpu_crtc->crtc_id, amdgpu_crtc, work); } +#endif /* * Handle unpin events outside the interrupt handler proper. @@ -187,11 +275,16 @@ static void amdgpu_display_unpin_work_func(struct work_struct *__work) kfree(work); } +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc, struct drm_framebuffer *fb, struct drm_pending_vblank_event *event, +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET_CTX uint32_t page_flip_flags, uint32_t target, struct drm_modeset_acquire_ctx *ctx) +#else + uint32_t page_flip_flags, uint32_t target) +#endif { struct drm_device *dev = crtc->dev; struct amdgpu_device *adev = drm_to_adev(dev); @@ -305,6 +398,129 @@ int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc, return r; } +#else +int amdgpu_crtc_page_flip(struct drm_crtc *crtc, + struct drm_framebuffer *fb, + struct drm_pending_vblank_event *event, + uint32_t page_flip_flags) +{ + struct drm_device *dev = crtc->dev; + struct amdgpu_device *adev = drm_to_adev(dev); + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + struct amdgpu_framebuffer *old_amdgpu_fb; + struct amdgpu_framebuffer *new_amdgpu_fb; + struct drm_gem_object *obj; + struct amdgpu_flip_work *work; + struct amdgpu_bo *new_abo; + unsigned long flags; + u64 tiling_flags; + u64 base; + int i, r; + + work = kzalloc(sizeof *work, GFP_KERNEL); + if (work == NULL) + return -ENOMEM; + + INIT_WORK(&work->flip_work, amdgpu_flip_work_func); + INIT_WORK(&work->unpin_work, amdgpu_display_unpin_work_func); + + work->event = event; + work->adev = adev; + work->crtc_id = amdgpu_crtc->crtc_id; + work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0; + + /* schedule unpin of the old buffer */ + old_amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); + obj = old_amdgpu_fb->obj; + + /* take a reference to the old object */ + work->old_abo = gem_to_amdgpu_bo(obj); + amdgpu_bo_ref(work->old_abo); + + new_amdgpu_fb = to_amdgpu_framebuffer(fb); + obj = new_amdgpu_fb->obj; + new_abo = gem_to_amdgpu_bo(obj); + + /* pin the new buffer */ + r = amdgpu_bo_reserve(new_abo, false); + if (unlikely(r != 0)) { + DRM_ERROR("failed to reserve new abo buffer before flip\n"); + goto cleanup; + } + + r = amdgpu_bo_pin(new_abo, AMDGPU_GEM_DOMAIN_VRAM); + if (unlikely(r != 0)) { + r = -EINVAL; + DRM_ERROR("failed to pin new abo buffer before flip\n"); + goto unreserve; + } + + r = dma_resv_get_fences_rcu(amdkcl_ttm_resvp(&new_abo->tbo), &work->excl, + &work->shared_count, + &work->shared); + if (unlikely(r != 0)) { + DRM_ERROR("failed to get fences for buffer\n"); + goto unpin; + } + + amdgpu_bo_get_tiling_flags(new_abo, &tiling_flags); + amdgpu_bo_unreserve(new_abo); + + work->base = base; + + r = drm_crtc_vblank_get(crtc); + if (r) { + DRM_ERROR("failed to get vblank before flip\n"); + goto pflip_cleanup; + } + + /* we borrow the event spin lock for protecting flip_wrok */ + spin_lock_irqsave(&crtc->dev->event_lock, flags); + if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_NONE) { + DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); + spin_unlock_irqrestore(&crtc->dev->event_lock, flags); + r = -EBUSY; + goto vblank_cleanup; + } + + amdgpu_crtc->pflip_status = AMDGPU_FLIP_PENDING; + amdgpu_crtc->pflip_works = work; + + + DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_PENDING, work: %p,\n", + amdgpu_crtc->crtc_id, amdgpu_crtc, work); + /* update crtc fb */ + crtc->primary->fb = fb; + spin_unlock_irqrestore(&crtc->dev->event_lock, flags); + amdgpu_flip_work_func(&work->flip_work); + return 0; + +vblank_cleanup: + drm_crtc_vblank_put(crtc); + +pflip_cleanup: + if (unlikely(amdgpu_bo_reserve(new_abo, false) != 0)) { + DRM_ERROR("failed to reserve new abo in error path\n"); + goto cleanup; + } +unpin: + if (unlikely(amdgpu_bo_unpin(new_abo) != 0)) { + DRM_ERROR("failed to unpin new abo in error path\n"); + } +unreserve: + amdgpu_bo_unreserve(new_abo); + +cleanup: + amdgpu_bo_unref(&work->old_abo); + fence_put(work->excl); + for (i = 0; i < work->shared_count; ++i) + fence_put(work->shared[i]); + kfree(work->shared); + kfree(work); + + return r; +} +#endif int amdgpu_display_crtc_set_config(struct drm_mode_set *set, struct drm_modeset_acquire_ctx *ctx) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index 3e175b1f54533..c6eaa6cf54895 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -705,11 +705,24 @@ void amdgpu_display_print_display_setup(struct drm_device *dev); int amdgpu_display_modeset_create_props(struct amdgpu_device *adev); int amdgpu_display_crtc_set_config(struct drm_mode_set *set, struct drm_modeset_acquire_ctx *ctx); + +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc, struct drm_framebuffer *fb, struct drm_pending_vblank_event *event, +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET_CTX uint32_t page_flip_flags, uint32_t target, struct drm_modeset_acquire_ctx *ctx); +#else + uint32_t page_flip_flags, uint32_t target); +#endif +#else +int amdgpu_crtc_page_flip(struct drm_crtc *crtc, + struct drm_framebuffer *fb, + struct drm_pending_vblank_event *event, + uint32_t page_flip_flags); +#endif + extern const struct drm_mode_config_funcs amdgpu_mode_funcs; #endif diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index 250b7d3c5a992..b66ae8eeab957 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -2503,7 +2503,11 @@ static const struct drm_crtc_funcs dce_v10_0_crtc_funcs = { .gamma_set = dce_v10_0_crtc_gamma_set, .set_config = amdgpu_display_crtc_set_config, .destroy = dce_v10_0_crtc_destroy, +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET .page_flip_target = amdgpu_display_crtc_page_flip_target, +#else + .page_flip = amdgpu_crtc_page_flip, +#endif #ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP .get_vblank_counter = amdgpu_get_vblank_counter_kms, .enable_vblank = amdgpu_enable_vblank_kms, diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index 1a6477928fd5a..10db3f4e68512 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -2587,7 +2587,11 @@ static const struct drm_crtc_funcs dce_v11_0_crtc_funcs = { .gamma_set = dce_v11_0_crtc_gamma_set, .set_config = amdgpu_display_crtc_set_config, .destroy = dce_v11_0_crtc_destroy, +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET .page_flip_target = amdgpu_display_crtc_page_flip_target, +#else + .page_flip = amdgpu_crtc_page_flip, +#endif #ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP .get_vblank_counter = amdgpu_get_vblank_counter_kms, .enable_vblank = amdgpu_enable_vblank_kms, diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c index eb08d2b06179b..e5c77f0104b94 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c @@ -2422,7 +2422,11 @@ static const struct drm_crtc_funcs dce_v6_0_crtc_funcs = { .gamma_set = dce_v6_0_crtc_gamma_set, .set_config = amdgpu_display_crtc_set_config, .destroy = dce_v6_0_crtc_destroy, +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET .page_flip_target = amdgpu_display_crtc_page_flip_target, +#else + .page_flip = amdgpu_crtc_page_flip, +#endif #ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP .get_vblank_counter = amdgpu_get_vblank_counter_kms, .enable_vblank = amdgpu_enable_vblank_kms, diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index 2a4515abd257f..48324a382b551 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -2421,7 +2421,11 @@ static const struct drm_crtc_funcs dce_v8_0_crtc_funcs = { .gamma_set = dce_v8_0_crtc_gamma_set, .set_config = amdgpu_display_crtc_set_config, .destroy = dce_v8_0_crtc_destroy, +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET .page_flip_target = amdgpu_display_crtc_page_flip_target, +#else + .page_flip = amdgpu_crtc_page_flip, +#endif #ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP .get_vblank_counter = amdgpu_get_vblank_counter_kms, .enable_vblank = amdgpu_enable_vblank_kms, diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 index f70303a508a0e..4cbefbc42c5e8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 @@ -23,6 +23,41 @@ AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP], [ ]) ]) +dnl # +dnl # v4.11-rc3-945-g41292b1fa13a +dnl # drm: Add acquire ctx parameter to ->page_flip(_target) +dnl # +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_crtc_funcs *funcs = NULL; + funcs->page_flip_target(NULL, NULL, NULL, 0, 0, NULL); + ], [ + AC_DEFINE(HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET_CTX, 1, + [drm_crtc_funcs->page_flip_target() wants ctx parameter]) + AC_DEFINE(HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET, 1, + [drm_crtc_funcs->page_flip_target() is available]) + ], [ + dnl # + dnl # v4.8-rc1-112-gc229bfbbd04a + dnl # drm: Add page_flip_target CRTC hook v2 + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_crtc_funcs *funcs = NULL; + funcs->page_flip_target(NULL, NULL, NULL, 0, 0); + ], [ + AC_DEFINE(HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET, 1, + [drm_crtc_funcs->page_flip_target() is available]) + ]) + ]) + ]) +]) + AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS], [ AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP + AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET ]) From b8dfc8c683eb872aba4065de0a83f32383784ed8 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 16 Jun 2020 13:44:08 +0800 Subject: [PATCH 0236/1868] drm/amdkcl: test for drm_crtc_funcs->set_config() the interface updated in commit v4.11-rc3-950-ga4eff9aa6db8("drm: Add acquire ctx parameter to ->set_config") Signed-off-by: Flora Cui Reviewed-by: Yang Xiong --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 8 ++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 4 ++++ .../drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 | 19 +++++++++++++++++++ 3 files changed, 31 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 155f7e0bfbccf..238cca75a2f51 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -522,8 +522,12 @@ int amdgpu_crtc_page_flip(struct drm_crtc *crtc, } #endif +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_SET_CONFIG_CTX int amdgpu_display_crtc_set_config(struct drm_mode_set *set, struct drm_modeset_acquire_ctx *ctx) +#else +int amdgpu_display_crtc_set_config(struct drm_mode_set *set) +#endif { struct drm_device *dev; struct amdgpu_device *adev; @@ -540,7 +544,11 @@ int amdgpu_display_crtc_set_config(struct drm_mode_set *set, if (ret < 0) goto out; +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_SET_CONFIG_CTX ret = drm_crtc_helper_set_config(set, ctx); +#else + ret = drm_crtc_helper_set_config(set); +#endif list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) if (crtc->enabled) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index c6eaa6cf54895..10bb7988efdbd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -703,8 +703,12 @@ bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc, /* amdgpu_display.c */ void amdgpu_display_print_display_setup(struct drm_device *dev); int amdgpu_display_modeset_create_props(struct amdgpu_device *adev); +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_SET_CONFIG_CTX int amdgpu_display_crtc_set_config(struct drm_mode_set *set, struct drm_modeset_acquire_ctx *ctx); +#else +int amdgpu_display_crtc_set_config(struct drm_mode_set *set); +#endif #ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc, diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 index 4cbefbc42c5e8..412f1d90ec93d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 @@ -23,6 +23,24 @@ AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP], [ ]) ]) +dnl # +dnl # v4.11-rc3-950-ga4eff9aa6db8 +dnl # drm: Add acquire ctx parameter to ->set_config +dnl # +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_SET_CONFIG], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_crtc_funcs *funcs = NULL; + funcs->set_config(NULL, NULL); + ], [ + AC_DEFINE(HAVE_STRUCT_DRM_CRTC_FUNCS_SET_CONFIG_CTX, 1, + [drm_crtc_funcs->set_config() wants ctx parameter]) + ]) + ]) +]) + dnl # dnl # v4.11-rc3-945-g41292b1fa13a dnl # drm: Add acquire ctx parameter to ->page_flip(_target) @@ -59,5 +77,6 @@ AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET], [ AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS], [ AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP + AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_SET_CONFIG AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET ]) From 0ba768064cf990f8a8a0774af21215e34b0c5f63 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 17 Jun 2020 10:39:21 +0800 Subject: [PATCH 0237/1868] drm/amdkcl: test drm_kms_helper_is_poll_worker() introduced in v4.15-rc8-13-g25c058ccaf2e Signed-off-by: Flora Cui Reviewed-by: Yang Xiong --- drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c | 7 +++++++ .../amd/dkms/m4/drm_kms_helper_is_poll_worker.m4 | 13 +++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 21 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_kms_helper_is_poll_worker.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c index 344e0a9ee08a9..77b8a438fa1ee 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c @@ -40,6 +40,13 @@ #include +#ifndef HAVE_DRM_KMS_HELPER_IS_POLL_WORKER +bool inline drm_kms_helper_is_poll_worker(void) +{ + return false; +} +#endif + void amdgpu_connector_hotplug(struct drm_connector *connector) { struct drm_device *dev = connector->dev; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_kms_helper_is_poll_worker.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_kms_helper_is_poll_worker.m4 new file mode 100644 index 0000000000000..dda9b0e2e2c79 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_kms_helper_is_poll_worker.m4 @@ -0,0 +1,13 @@ +dnl # +dnl # commit v4.15-rc8-13-g25c058ccaf2e +dnl # drm: Allow determining if current task is output poll worker +dnl # +AC_DEFUN([AC_AMDGPU_DRM_KMS_HELPER_IS_POLL_WORKER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([drm_kms_helper_is_poll_worker], + [drivers/gpu/drm/drm_probe_helper.c], [ + AC_DEFINE(HAVE_DRM_KMS_HELPER_IS_POLL_WORKER, 1, + [drm_kms_helper_is_poll_worker() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 6d4e444051a97..e421253c4bb36 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -91,6 +91,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_HELPER_FORCE_DISABLE_ALL AC_AMDGPU_DRM_EDID_TO_ELD AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS + AC_AMDGPU_DRM_KMS_HELPER_IS_POLL_WORKER AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 87401403e178a06b3d56ce9643dfd8264de12a9a Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 22 Sep 2020 11:02:03 +0800 Subject: [PATCH 0238/1868] drm/amdkcl: test __drm_atomic_helper_crtc_reset() is available Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index e421253c4bb36..45facbdeef08f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -64,6 +64,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS AC_AMDGPU_DRM_DP_CEC_CORRELATION_FUNCTIONS AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_RESUME + AC_AMDGPU___DRM_ATOMIC_HELPER_CRTC_RESET AC_AMDGPU_DRM_DRIVER_GEM_PRIME_RES_OBJ AC_AMDGPU_DRM_DRV_GEM_PRIME_EXPORT AC_AMDGPU_DRM_MM_PRINT From c60febe80a2c48ed6251691f411dcb71633d2514 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 19 Jun 2020 17:31:03 +0800 Subject: [PATCH 0239/1868] drm/amdkcl: check drm_connector_funcs->detect drm_connector_funcs->detect() is optional since commit v4.9-rc4-949-g949f08862d66 Signed-off-by: Flora Cui Reviewed-by: Yang Xiong --- include/kcl/kcl_drm_connector.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/kcl/kcl_drm_connector.h b/include/kcl/kcl_drm_connector.h index ac6c066aa3376..1da6773c7ee4b 100644 --- a/include/kcl/kcl_drm_connector.h +++ b/include/kcl/kcl_drm_connector.h @@ -26,6 +26,14 @@ #include #include +/* + * commit v4.9-rc4-949-g949f08862d66 + * drm: Make the connector .detect() callback optional + */ +#if DRM_VERSION_CODE < DRM_VERSION(4, 10, 0) +#define AMDKCL_AMDGPU_DRM_CONNECTOR_STATUS_DETECT_MANDATORY +#endif + #ifndef HAVE_DRM_CONNECTOR_UPDATE_EDID_PROPERTY #define drm_connector_update_edid_property drm_mode_connector_update_edid_property #endif From b8a0bc588b7da93d40d3659f55520aacf103aa44 Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Wed, 29 Apr 2020 15:30:15 +0800 Subject: [PATCH 0240/1868] drm/amdkcl: repalce crtc->index with drm_crtc_index Reviewed-by: Feifei Xu Reviewed-by: Flora Cui Signed-off-by: Yifan Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 238cca75a2f51..159a3b1739d4e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1896,7 +1896,7 @@ bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc, const struct drm_display_mode *mode) { struct drm_device *dev = crtc->dev; - unsigned int pipe = crtc->index; + unsigned int pipe = drm_crtc_index(crtc); return amdgpu_display_get_crtc_scanoutpos(dev, pipe, 0, vpos, hpos, stime, etime, mode); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index 781bd839bdf46..744b1fe63ee1e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -1536,7 +1536,7 @@ void amdgpu_driver_release_kms(struct drm_device *dev) u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc) { struct drm_device *dev = crtc->dev; - unsigned int pipe = crtc->index; + unsigned int pipe = drm_crtc_index(crtc); struct amdgpu_device *adev = drm_to_adev(dev); int vpos, hpos, stat; u32 count; @@ -1604,7 +1604,7 @@ u32 amdgpu_get_vblank_counter_kms(struct drm_crtc *crtc) int amdgpu_enable_vblank_kms(struct drm_crtc *crtc) { struct drm_device *dev = crtc->dev; - unsigned int pipe = crtc->index; + unsigned int pipe = drm_crtc_index(crtc); struct amdgpu_device *adev = drm_to_adev(dev); int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); @@ -1621,7 +1621,7 @@ int amdgpu_enable_vblank_kms(struct drm_crtc *crtc) void amdgpu_disable_vblank_kms(struct drm_crtc *crtc) { struct drm_device *dev = crtc->dev; - unsigned int pipe = crtc->index; + unsigned int pipe = drm_crtc_index(crtc); struct amdgpu_device *adev = drm_to_adev(dev); int idx = amdgpu_display_crtc_idx_to_irq_type(adev, pipe); From 5d72e8c4172f8f5d89c12ed12e9e4acae7093e5f Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 12 Oct 2023 14:41:17 +0800 Subject: [PATCH 0241/1868] drm/amdkcl: test whether drm_driver->release() is available introduced by v4.10-rc5-1045-gf30c92576af4 This patch is caused by 'drm/amdgpu: Embed drm_device into amdgpu_device (v2) Although v5.5-rc2-1531-ge62bf83aa1bb has removed checking on dev->dev_private, some distro with kernel v5.6+ (such as ubuntu20.04-oem) may still access dev->dev_private In case of accessing dev->dev_private in drm code, init dev->dev_private to amdgpu_device. Wrap this initialization with kcl inline function for easy tracking. Squash of 469aa26d1979 drm/amdkcl: fix reture val for faked __devm_drm_dev_alloc() af31a40bf581 drm/amdkcl: rework the faked __devm_drm_dev_alloc 312a6b63c4e9 drm/amdkcl: fake devm_drm_dev_alloc 2ec2a0da80d7 drm/amdkcl: always init drm_device.dev_private 22de9a4cefd6 drm/amdkcl: test whether drm_dev_fini() is available (v2) introduced by v5.5-rc2-1531-ge62bf83aa1bb f9896ea4089f drm/amdkcl: test whether drm checking on dev->dev_private d4300369d400 drm/amdkcl: test whether drm_dev_fini() is available Signed-off-by: Yang Xiong Reviewed-by: Flora Cui Acked-by: Guchun Chen Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling Reviewed-by: Shiwu Zhang Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 12 +++++ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 24 ++++++++- drivers/gpu/drm/amd/backport/Makefile | 2 +- drivers/gpu/drm/amd/backport/backport.h | 1 + .../drm/amd/backport/include/kcl/kcl_amdgpu.h | 2 + .../backport/include/kcl/kcl_amdgpu_drm_drv.h | 43 ++++++++++++++++ drivers/gpu/drm/amd/backport/kcl_drm_drv.c | 49 +++++++++++++++++++ .../gpu/drm/amd/dkms/m4/drm-driver-release.m4 | 21 ++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 9 files changed, 153 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_drv.h create mode 100644 drivers/gpu/drm/amd/backport/kcl_drm_drv.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-driver-release.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 3a0239cfac171..4180d9fcdaded 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -855,7 +855,11 @@ struct amdgpu_fru_info; struct amdgpu_device { struct device *dev; struct pci_dev *pdev; +#ifdef HAVE_DRM_DRIVER_RELEASE struct drm_device ddev; +#else + struct drm_device *ddev; +#endif #ifdef CONFIG_DRM_AMD_ACP struct amdgpu_acp acp; @@ -1209,12 +1213,20 @@ static inline uint32_t amdgpu_ip_version_full(const struct amdgpu_device *adev, static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev) { +#ifdef HAVE_DRM_DRIVER_RELEASE return container_of(ddev, struct amdgpu_device, ddev); +#else + return ddev->dev_private; +#endif } static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev) { +#ifdef HAVE_DRM_DRIVER_RELEASE return &adev->ddev; +#else + return adev->ddev; +#endif } static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 06bc5edf13c2d..f011190a0a007 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2348,7 +2348,11 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, kcl_pci_configure_extended_tags(pdev); ret = pci_enable_device(pdev); if (ret) +#ifndef AMDKCL_DEVM_DRM_DEV_ALLOC return ret; +#else + goto err_free; +#endif pci_set_drvdata(pdev, ddev); @@ -2442,6 +2446,10 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, err_pci: pci_disable_device(pdev); +#ifdef AMDKCL_DEVM_DRM_DEV_ALLOC +err_free: + amdkcl_drm_dev_release(ddev); +#endif return ret; } @@ -2453,7 +2461,6 @@ amdgpu_pci_remove(struct pci_dev *pdev) amdgpu_xcp_dev_unplug(adev); drm_dev_unplug(dev); - if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { pm_runtime_get_sync(dev->dev); pm_runtime_forbid(dev->dev); @@ -2470,6 +2477,18 @@ amdgpu_pci_remove(struct pci_dev *pdev) pci_wait_for_pending_transaction(pdev); } +#ifdef HAVE_DRM_DRIVER_RELEASE +#ifndef HAVE_DRM_DRM_MANAGED_H +static void amdgpu_driver_release(struct drm_device *ddev) +{ + struct amdgpu_device *adev = drm_to_adev(ddev); + + drm_dev_fini(ddev); + kfree(adev); +} +#endif +#endif + static void amdgpu_pci_shutdown(struct pci_dev *pdev) { @@ -3017,6 +3036,7 @@ static const struct drm_driver amdgpu_kms_driver = { .debugfs_cleanup = amdgpu_debugfs_cleanup, #endif #endif + #ifndef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP .get_vblank_counter = kcl_amdgpu_get_vblank_counter_kms, .enable_vblank = kcl_amdgpu_enable_vblank_kms, @@ -3030,7 +3050,9 @@ static const struct drm_driver amdgpu_kms_driver = { .dumb_create = amdgpu_mode_dumb_create, .dumb_map_offset = amdgpu_mode_dumb_mmap, .fops = &amdgpu_driver_kms_fops, +#ifdef HAVE_DRM_DRIVER_RELEASE .release = &amdgpu_driver_release_kms, +#endif #ifdef CONFIG_PROC_FS .show_fdinfo = amdgpu_show_fdinfo, #endif diff --git a/drivers/gpu/drm/amd/backport/Makefile b/drivers/gpu/drm/amd/backport/Makefile index 1ad8a02a4b19f..8880468d474a6 100644 --- a/drivers/gpu/drm/amd/backport/Makefile +++ b/drivers/gpu/drm/amd/backport/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: MIT -BACKPORT_OBJS := +BACKPORT_OBJS := kcl_drm_drv.o amdgpu-y += $(addprefix ../backport/,$(BACKPORT_OBJS)) diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 7e5e5fc3d3d02..e03d2fe1152ae 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -53,5 +53,6 @@ #include #include "kcl/kcl_amdgpu_drm_fb_helper.h" #include "kcl/kcl_amdgpu.h" +#include "kcl/kcl_amdgpu_drm_drv.h" #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h index 9c0291d459b42..5c6fe94ccd030 100644 --- a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h @@ -4,6 +4,7 @@ #include #include "amdgpu.h" +#include #ifndef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP @@ -118,4 +119,5 @@ static inline int kcl_amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, in } #endif #endif /* HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP */ + #endif /* AMDGPU_BACKPORT_KCL_AMDGPU_H */ diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_drv.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_drv.h new file mode 100644 index 0000000000000..926e4cd441519 --- /dev/null +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_drv.h @@ -0,0 +1,43 @@ +/* + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * Copyright (c) 2009-2010, Code Aurora Forum. + * Copyright 2016 Intel Corp. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef __AMDGPU_BACKPORT_KCL_AMDGPU_DRM_DRV_H__ +#define __AMDGPU_BACKPORT_KCL_AMDGPU_DRM_DRV_H__ + +#include + +/* Copied from v5.7-rc1-343-gb0b5849e0cc0 include/drm/drm_drv.h */ +#ifndef devm_drm_dev_alloc +#define AMDKCL_DEVM_DRM_DEV_ALLOC 1 +void *__devm_drm_dev_alloc(struct device *parent, struct drm_driver *driver, + size_t size, size_t offset); +#define devm_drm_dev_alloc(parent, driver, type, member) \ + ((type *) __devm_drm_dev_alloc(parent, driver, sizeof(type), \ + offsetof(type, member))) + +void amdkcl_drm_dev_release(struct drm_device *ddev); +#endif + +#endif diff --git a/drivers/gpu/drm/amd/backport/kcl_drm_drv.c b/drivers/gpu/drm/amd/backport/kcl_drm_drv.c new file mode 100644 index 0000000000000..d6b18e3a75f73 --- /dev/null +++ b/drivers/gpu/drm/amd/backport/kcl_drm_drv.c @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#include +#include "amdgpu.h" + +#ifdef AMDKCL_DEVM_DRM_DEV_ALLOC +/* Copied from v5.7-rc1-343-gb0b5849e0cc0 drivers/gpu/drm/drm_drv.c and modified for KCL */ +void *__devm_drm_dev_alloc(struct device *parent, struct drm_driver *driver, + size_t size, size_t offset) +{ + void *container; + struct drm_device *drm; + int ret; + + container = kzalloc(size, GFP_KERNEL); + if (!container) + return ERR_PTR(-ENOMEM); + +#ifdef HAVE_DRM_DRIVER_RELEASE + drm = container + offset; + ret = drm_dev_init(drm, driver, parent); + if (ret) { + drm_dev_put(drm); + return ERR_PTR(ret); + } +#ifdef HAVE_DRM_DRM_MANAGED_H + drmm_add_final_kfree(drm, container); +#endif +#else + drm = drm_dev_alloc(driver, parent); + if (IS_ERR(drm)) + return PTR_ERR(drm); + ((struct amdgpu_device*)container)->ddev = drm; +#endif + drm->dev_private = container; + return container; +} + +void amdkcl_drm_dev_release(struct drm_device *ddev) +{ +#ifndef HAVE_DRM_DRIVER_RELEASE + if (ddev) { + kfree(drm_to_adev(ddev)); + ddev->dev_private = NULL; + } +#endif + drm_dev_put(ddev); +} + +#endif diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-driver-release.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-driver-release.m4 new file mode 100644 index 0000000000000..05801784c5188 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-driver-release.m4 @@ -0,0 +1,21 @@ +dnl # +dnl # commit v4.10-rc5-1045-gf30c92576af4 +dnl # drm: Provide a driver hook for drm_dev_release() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DRIVER_RELEASE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DRM_DRV_H + #include + #else + #include + #endif + ],[ + struct drm_driver *ddrv = NULL; + ddrv->release = NULL; + ],[ + AC_DEFINE(HAVE_DRM_DRIVER_RELEASE, 1, + [drm_driver->release() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 45facbdeef08f..a76ad4e84223d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -93,6 +93,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_EDID_TO_ELD AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS AC_AMDGPU_DRM_KMS_HELPER_IS_POLL_WORKER + AC_AMDGPU_DRM_DRIVER_RELEASE AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 58cdf49fc46052a7c190404631a2b6d01754adfe Mon Sep 17 00:00:00 2001 From: tianci yin Date: Thu, 14 Feb 2019 10:08:11 +0800 Subject: [PATCH 0242/1868] drm/amdkcl: check whether drm_connector_for_each_possible_encoder is available drm_connector_for_each_possible_encoder was introduced by the below commit since 4.19-rc1, add kcl implement for older kernel. "drm: Add drm_connector_for_each_possible_encoder()" for_each_if is introduce from v4.5-rc1 . so it's not available on drm < 4.5 like rhel6.10 . v1: drm/amdkcl: [4.19] kcl for drm_connector_for_each_possible_encoder v2: drm/amdkcl: check whether drm_connector_for_each_possible_encoder is available v3: drm_connector_for_each_possible_encoder Reviewed-by: changzhu Signed-off-by: Tianci Yin Signed-off-by: Chengming Gui Signed-off-by: Flora Cui Signed-off-by: Jack Gui Reviewed-by: Flora Cui Signed-off-by: Yifan Zhang --- .../gpu/drm/amd/amdgpu/amdgpu_connectors.c | 39 +++++++++++++++++++ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++ ...drm-connector-for-each-possible-encoder.m4 | 20 ++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 64 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-connector-for-each-possible-encoder.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c index 77b8a438fa1ee..4b0a9394f2682 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c @@ -226,10 +226,15 @@ amdgpu_connector_update_scratch_regs(struct drm_connector *connector, struct drm_encoder *encoder; const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; bool connected; + int i; best_encoder = connector_funcs->best_encoder(connector); +#ifdef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS drm_connector_for_each_possible_encoder(connector, encoder) { +#else + drm_connector_for_each_possible_encoder(connector, encoder, i) { +#endif if ((encoder == best_encoder) && (status == connector_status_connected)) connected = true; else @@ -244,8 +249,13 @@ amdgpu_connector_find_encoder(struct drm_connector *connector, int encoder_type) { struct drm_encoder *encoder; + int i; +#ifdef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS drm_connector_for_each_possible_encoder(connector, encoder) { +#else + drm_connector_for_each_possible_encoder(connector, encoder, i) { +#endif if (encoder->encoder_type == encoder_type) return encoder; } @@ -330,9 +340,14 @@ static struct drm_encoder * amdgpu_connector_best_single_encoder(struct drm_connector *connector) { struct drm_encoder *encoder; + int i; /* pick the first one */ +#ifdef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS drm_connector_for_each_possible_encoder(connector, encoder) +#else + drm_connector_for_each_possible_encoder(connector, encoder, i) +#endif return encoder; return NULL; @@ -1118,8 +1133,13 @@ amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force) /* find analog encoder */ if (amdgpu_connector->dac_load_detect) { struct drm_encoder *encoder; + int i; +#ifdef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS drm_connector_for_each_possible_encoder(connector, encoder) { +#else + drm_connector_for_each_possible_encoder(connector, encoder, i) { +#endif if (encoder->encoder_type != DRM_MODE_ENCODER_DAC && encoder->encoder_type != DRM_MODE_ENCODER_TVDAC) continue; @@ -1170,8 +1190,13 @@ amdgpu_connector_dvi_encoder(struct drm_connector *connector) { struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); struct drm_encoder *encoder; + int i; +#ifdef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS drm_connector_for_each_possible_encoder(connector, encoder) { +#else + drm_connector_for_each_possible_encoder(connector, encoder, i) { +#endif if (amdgpu_connector->use_digital == true) { if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS) return encoder; @@ -1186,7 +1211,11 @@ amdgpu_connector_dvi_encoder(struct drm_connector *connector) /* then check use digitial */ /* pick the first one */ +#ifdef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS drm_connector_for_each_possible_encoder(connector, encoder) +#else + drm_connector_for_each_possible_encoder(connector, encoder, i) +#endif return encoder; return NULL; @@ -1324,8 +1353,13 @@ u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *conn { struct drm_encoder *encoder; struct amdgpu_encoder *amdgpu_encoder; + int i; +#ifdef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS drm_connector_for_each_possible_encoder(connector, encoder) { +#else + drm_connector_for_each_possible_encoder(connector, encoder, i) { +#endif amdgpu_encoder = to_amdgpu_encoder(encoder); switch (amdgpu_encoder->encoder_id) { @@ -1344,9 +1378,14 @@ static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector) { struct drm_encoder *encoder; struct amdgpu_encoder *amdgpu_encoder; + int i; bool found = false; +#ifdef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS drm_connector_for_each_possible_encoder(connector, encoder) { +#else + drm_connector_for_each_possible_encoder(connector, encoder, i) { +#endif amdgpu_encoder = to_amdgpu_encoder(encoder); if (amdgpu_encoder->caps & ATOM_ENCODER_CAP_RECORD_HBR2) found = true; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 2a5634189112a..92c3edc0aea06 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -7635,6 +7635,7 @@ static int to_drm_connector_type(enum signal_type st) static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector) { +#ifdef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS struct drm_encoder *encoder; /* There is only one encoder per connector */ @@ -7642,6 +7643,9 @@ static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector * return encoder; return NULL; +#else + return drm_encoder_find(connector->dev, NULL, connector->encoder_ids[0]); +#endif } static void amdgpu_dm_get_native_mode(struct drm_connector *connector) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-for-each-possible-encoder.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-for-each-possible-encoder.m4 new file mode 100644 index 0000000000000..0f57128fcf1a1 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector-for-each-possible-encoder.m4 @@ -0,0 +1,20 @@ +dnl # +dnl # commit v5.3-rc1-656-g62afb4ad425a +dnl # drm/connector: Allow max possible encoders to attach to a connector +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ],[ + struct drm_connector *connector = NULL; + struct drm_encoder *encoder = NULL; + drm_connector_for_each_possible_encoder(connector, encoder) + return 0; + ],[ + AC_DEFINE(HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS, 1, + [drm_connector_for_each_possible_encoder() wants 2 arguments]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index a76ad4e84223d..20d4f15a2eb7c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -94,6 +94,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS AC_AMDGPU_DRM_KMS_HELPER_IS_POLL_WORKER AC_AMDGPU_DRM_DRIVER_RELEASE + AC_AMDGPU_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From be1a92478423a34c1cb6ed13bb11ca55b1e6b6f2 Mon Sep 17 00:00:00 2001 From: Adam Yang Date: Fri, 20 Sep 2019 16:34:11 +0800 Subject: [PATCH 0243/1868] drm/amdkcl: Test drm_hdmi_avi_infoframe_from_display_mode() interface history v1: f6cdebf80917 Test whether drm_hdmi_avi_infoframe_from_display_mode() wants 2 args Signed-off-by: Adam Yang Signed-off-by: Anatoli Antonovitch Signed-off-by: Yifan Zhang Signed-off-by: Jack Gui drm/amdkcl: fix drm_hdmi_avi_infoframe_from_display_mode 1. fix compile waring 2. remove extra "," Signed-off-by: Flora Cui Signed-off-by: Jack Gui Change-Id: I0b32a9991abed7088f72652740aa71604fe40b10 --- drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 6 ++++ drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 6 ++++ drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 6 ++++ drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 6 ++++ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 ++++ drivers/gpu/drm/amd/dkms/m4/drm-edid.m4 | 35 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 7 files changed, 66 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-edid.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index b66ae8eeab957..435cf5e4ec8f2 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -1711,7 +1711,13 @@ static void dce_v10_0_afmt_setmode(struct drm_encoder *encoder, dce_v10_0_audio_write_sad_regs(encoder); dce_v10_0_audio_write_latency_fields(encoder, mode); +#if defined(HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_P) err = drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode); +#elif defined(HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_B) + err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, false); +#else + err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); +#endif /* HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_P */ if (err < 0) { DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); return; diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index 10db3f4e68512..7490ade2335fb 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -1760,7 +1760,13 @@ static void dce_v11_0_afmt_setmode(struct drm_encoder *encoder, dce_v11_0_audio_write_sad_regs(encoder); dce_v11_0_audio_write_latency_fields(encoder, mode); +#if defined(HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_P) err = drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode); +#elif defined(HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_B) + err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, false); +#else + err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); +#endif /* HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_P */ if (err < 0) { DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); return; diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c index e5c77f0104b94..7957c071b8e67 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c @@ -1481,7 +1481,13 @@ static void dce_v6_0_audio_set_avi_infoframe(struct drm_encoder *encoder, ssize_t err; u32 tmp; +#if defined(HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_P) err = drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode); +#elif defined(HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_B) + err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, false); +#else + err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); +#endif /* HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_P */ if (err < 0) { DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); return; diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index 48324a382b551..5803e0a0608cf 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -1662,7 +1662,13 @@ static void dce_v8_0_afmt_setmode(struct drm_encoder *encoder, dce_v8_0_audio_write_sad_regs(encoder); dce_v8_0_audio_write_latency_fields(encoder, mode); +#if defined(HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_P) err = drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode); +#elif defined(HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_B) + err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, false); +#else + err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); +#endif /* HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_P */ if (err < 0) { DRM_ERROR("failed to setup AVI infoframe: %zd\n", err); return; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 92c3edc0aea06..135bef05968f6 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -6004,7 +6004,13 @@ static void fill_stream_properties_from_drm_display_mode( } if (stream->signal == SIGNAL_TYPE_HDMI_TYPE_A) { +#if defined(HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_P) drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, (struct drm_connector *)connector, mode_in); +#elif defined(HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_B) + drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, mode_in, false); +#else + drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, mode_in); +#endif /* HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_P */ timing_out->vic = avi_frame.video_code; drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in); timing_out->hdmi_vic = hv_frame.vic; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-edid.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-edid.m4 new file mode 100644 index 0000000000000..02a5a8a2b5875 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-edid.m4 @@ -0,0 +1,35 @@ +dnl # +dnl # 13d0add333afea7b2fef77473232b10dea3627dd +dnl # drm/edid: Pass connector to AVI infoframe functions +dnl # +AC_DEFUN([AC_AMDGPU_DRM_EDID], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + struct hdmi_avi_infoframe *frame = NULL; + struct drm_connector *connector = NULL; + const struct drm_display_mode *mode = NULL; + drm_hdmi_avi_infoframe_from_display_mode(frame, connector, mode); + ], [drm_hdmi_avi_infoframe_from_display_mode], [drivers/gpu/drm/drm_edid.c], [ + AC_DEFINE(HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_P, 1, + [drm_hdmi_avi_infoframe_from_display_mode() has p,p,p interface]) + ], [ + dnl # + dnl # 10a8512008655d5ce62f8c56323a6b5bd221c920 + dnl # drm: Add HDMI infoframe helpers + dnl # + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + struct hdmi_avi_infoframe *frame = NULL; + const struct drm_display_mode *mode = NULL; + bool is_hdmi2_sink = false; + drm_hdmi_avi_infoframe_from_display_mode(frame, mode, is_hdmi2_sink); + ], [drm_hdmi_avi_infoframe_from_display_mode], [drivers/gpu/drm/drm_edid.c], [ + AC_DEFINE(HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_B, 1, + [drm_hdmi_avi_infoframe_from_display_mode() has p,p,b interface]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 20d4f15a2eb7c..ed11813a3944d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -92,6 +92,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_HELPER_FORCE_DISABLE_ALL AC_AMDGPU_DRM_EDID_TO_ELD AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS + AC_AMDGPU_DRM_EDID AC_AMDGPU_DRM_KMS_HELPER_IS_POLL_WORKER AC_AMDGPU_DRM_DRIVER_RELEASE AC_AMDGPU_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER From 805c5a4c0ebdce4ab17be97c6a3d752999cadcee Mon Sep 17 00:00:00 2001 From: changzhu Date: Fri, 12 Jul 2019 14:49:19 +0800 Subject: [PATCH 0244/1868] drm/amdkcl: add AC_AMDGPU_DRM_AUDIO_COMPONENT_HEADER it is a squash of: drm/amdkcl: test whether drm/drm_audio_component.h is available [why] drm_audio_component.h is not defined before drm version 4.19.0. So there will be build error when using them before drm version 4.19.0. [How] Use autoconf way to check drm_audio_component_ops, drm_audio_component_audio_ops,drm_audio_component in kernel. If they are not defined,avoid to use them in driver code. This autoconf patch is caused by patch: drm/amd/display: Add drm_audio_component support to amdgpu_dm Change-Id: Ic75928406a042a0e08f5b06cf64543555c62e476 Signed-off-by: changzhu Reviewed-by: Nicholas Kazlauskas Signed-off-by: Jack Gui drm/amdkcl: correct drm_audio_component_header.m4 patten Signed-off-by: Yifan Zhang Reviewed-by: Flora Cui Signed-off-by: Jack Gui drm/amdkcl: fix check for drm/drm_audio_component.h Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang Signed-off-by: Yifan Zhang Signed-off-by: Ma Jun Change-Id: I7717d2f117361cfa3fa7a0f941e88ac3d99327b8 --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 20 +++++++++++++++++++ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 4 ++++ .../amd/dkms/m4/drm-audio-component-header.m4 | 9 +++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 34 insertions(+) mode change 100644 => 100755 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c mode change 100644 => 100755 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-audio-component-header.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c old mode 100644 new mode 100755 index 135bef05968f6..3254e901224bf --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -79,7 +79,10 @@ #include #include #include + +#if defined(HAVE_DRM_AUDIO_COMPONENT_HEADER) #include +#endif #include #include @@ -94,7 +97,9 @@ #include #include #include +#if defined(HAVE_DRM_AUDIO_COMPONENT_HEADER) #include +#endif #include #ifdef CONFIG_DRM_AMD_DC_HDCP #include @@ -993,6 +998,7 @@ static void amdgpu_dm_fbc_init(struct drm_connector *connector) } +#if defined(HAVE_DRM_AUDIO_COMPONENT_HEADER) static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port, int pipe, bool *enabled, unsigned char *buf, int max_bytes) @@ -1128,6 +1134,7 @@ static void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin) pin, -1); } } +#endif static int dm_dmub_hw_init(struct amdgpu_device *adev) { @@ -1772,7 +1779,10 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) mutex_init(&adev->dm.dpia_aux_lock); mutex_init(&adev->dm.dc_lock); + +#if defined(HAVE_DRM_AUDIO_COMPONENT_HEADER) mutex_init(&adev->dm.audio_lock); +#endif if (amdgpu_dm_irq_init(adev)) { DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n"); @@ -2144,7 +2154,9 @@ static void amdgpu_dm_fini(struct amdgpu_device *adev) adev->dm.freesync_module = NULL; } +#if defined(HAVE_DRM_AUDIO_COMPONENT_HEADER) mutex_destroy(&adev->dm.audio_lock); +#endif mutex_destroy(&adev->dm.dc_lock); mutex_destroy(&adev->dm.dpia_aux_lock); } @@ -4409,12 +4421,14 @@ static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) } #endif +#if defined(HAVE_DRM_AUDIO_COMPONENT_HEADER) r = amdgpu_dm_audio_init(adev); if (r) { dc_state_release(state->context); kfree(state); return r; } +#endif return 0; } @@ -7993,7 +8007,9 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, aconnector->base.stereo_allowed = false; aconnector->base.dpms = DRM_MODE_DPMS_OFF; aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */ +#if defined(HAVE_DRM_AUDIO_COMPONENT_HEADER) aconnector->audio_inst = -1; +#endif aconnector->pack_sdp_v1_3 = false; aconnector->as_type = ADAPTIVE_SYNC_TYPE_NONE; memset(&aconnector->vsdb_info, 0, sizeof(aconnector->vsdb_info)); @@ -9166,6 +9182,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, kfree(bundle); } +#if defined(HAVE_DRM_AUDIO_COMPONENT_HEADER) static void amdgpu_dm_commit_audio(struct drm_device *dev, struct drm_atomic_state *state) { @@ -9246,6 +9263,7 @@ static void amdgpu_dm_commit_audio(struct drm_device *dev, amdgpu_dm_audio_eld_notify(adev, inst); } } +#endif /* * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC @@ -9906,8 +9924,10 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) acrtc->wb_enabled = true; } +#if defined(HAVE_DRM_AUDIO_COMPONENT_HEADER) /* Update audio instances for each connector. */ amdgpu_dm_commit_audio(dev, state); +#endif /* restore the backlight level */ for (i = 0; i < dm->num_of_edps; i++) { diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h old mode 100644 new mode 100755 index 2d7755e2b6c32..1b0414421ad58 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -396,6 +396,7 @@ struct amdgpu_display_manager { */ struct mutex dc_lock; +#if defined(HAVE_DRM_AUDIO_COMPONENT_HEADER) /** * @audio_lock: * @@ -417,6 +418,7 @@ struct amdgpu_display_manager { * successfully, false otherwise. */ bool audio_registered; +#endif /** * @irq_handler_list_low_tab: @@ -715,8 +717,10 @@ struct amdgpu_dm_connector { */ int max_vfreq ; +#if defined(HAVE_DRM_AUDIO_COMPONENT_HEADER) /* Audio instance - protected by audio_lock. */ int audio_inst; +#endif struct mutex hpd_lock; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-audio-component-header.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-audio-component-header.m4 new file mode 100644 index 0000000000000..520d72bebcb5c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-audio-component-header.m4 @@ -0,0 +1,9 @@ +AC_DEFUN([AC_AMDGPU_DRM_AUDIO_COMPONENT_HEADER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drm_audio_component.h], [ + AC_DEFINE(HAVE_DRM_AUDIO_COMPONENT_HEADER, 1, + [whether drm/drm_audio_component.h is defined]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index ed11813a3944d..00ac87837a73c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -48,6 +48,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_MM_RELEASE_PAGES AC_AMDGPU_SCHED_SET_FIFO_LOW AC_AMDGPU_DMA_FENCE_HEADERS + AC_AMDGPU_DRM_AUDIO_COMPONENT_HEADER AC_AMDGPU_DMA_RESV AC_AMDGPU_TTM_SG_TT_INIT AC_AMDGPU_TTM_BUFFER_OBJECT From 231921f13b5cb6239eff7779589d42b0cd30b289 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 24 Sep 2019 13:30:02 +0800 Subject: [PATCH 0245/1868] drm/amdkcl: Test whether drm_mode_is_420_xxx() is available v2: drm/amdkcl: refactor kcl copy rm_mode_is_420_xxx v3: fix license for kcl drm part Change-Id: I3b71e9df855e8996d76a040ac6b650fdb52702fa Signed-off-by: Flora Cui Reviewed-by: Feifei Xu Signed-off-by: Jack Gui Reviewed-by: Yifan Zhang Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling Change-Id: I2797279336841ff551df87ec663ec384b01022ca --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_drm_modes.c | 41 +++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 10 +++-- .../drm/amd/dkms/m4/drm_mode_is_420_xxx.m4 | 17 ++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_modes.h | 39 ++++++++++++++++++ 7 files changed, 106 insertions(+), 5 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_modes.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_mode_is_420_xxx.m4 create mode 100644 include/kcl/kcl_drm_modes.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index fafb36606e287..3f301283ce0de 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -10,7 +10,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_fence.o kcl_fence_array.o kcl_reservation.o kcl_drm_cache.o \ kcl_drm_fb.o kcl_drm_print.o kcl_fbmem.o \ kcl_drm_crtc.o kcl_connector.o kcl_drm_atomic_helper.o \ - kcl_device_cgroup.o kcl_mn.o kcl_time.o kcl_ftrace.o \ + kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o kcl_ftrace.o \ kcl_acpi_table.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_modes.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_modes.c new file mode 100644 index 0000000000000..bf57f999e4fc2 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_modes.c @@ -0,0 +1,41 @@ +/* + * Copyright © 1997-2003 by The XFree86 Project, Inc. + * Copyright © 2007 Dave Airlie + * Copyright © 2007-2008 Intel Corporation + * Jesse Barnes + * Copyright 2005-2006 Luc Verhaegen + * Copyright (c) 2001, Andy Ritger aritger@nvidia.com + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Except as contained in this notice, the name of the copyright holder(s) + * and author(s) shall not be used in advertising or otherwise to promote + * the sale, use or other dealings in this Software without prior written + * authorization from the copyright holder(s) and author(s). + */ +#include +#include +#include + +#ifndef HAVE_DRM_MODE_IS_420_XXX +amdkcl_dummy_symbol(drm_mode_is_420_only, bool, return false, + const struct drm_display_info *display, const struct drm_display_mode *mode) +amdkcl_dummy_symbol(drm_mode_is_420_also, bool, return false, + const struct drm_display_info *display, const struct drm_display_mode *mode) +#endif diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index e03d2fe1152ae..b12907b57f7c0 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -44,6 +44,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 3254e901224bf..40c634ca0ef2d 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -5784,6 +5784,11 @@ convert_color_depth_from_display_info(const struct drm_connector *connector, { u8 bpc; + bpc = (uint8_t)connector->display_info.bpc; + /* Assume 8 bpc by default if no bpc is specified. */ + bpc = bpc ? bpc : 8; + +#ifdef HAVE_DRM_MODE_IS_420_XXX if (is_y420) { bpc = 8; @@ -5794,11 +5799,8 @@ convert_color_depth_from_display_info(const struct drm_connector *connector, bpc = 12; else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30) bpc = 10; - } else { - bpc = (uint8_t)connector->display_info.bpc; - /* Assume 8 bpc by default if no bpc is specified. */ - bpc = bpc ? bpc : 8; } +#endif if (requested_bpc > 0) { /* diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_mode_is_420_xxx.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_mode_is_420_xxx.m4 new file mode 100644 index 0000000000000..65c9ec9268e1b --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_mode_is_420_xxx.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit 2570fe2586254ff174c2ba5a20dabbde707dbb9b +dnl # drm: add helper functions for YCBCR420 handling +dnl # +AC_DEFUN([AC_AMDGPU_DRM_MODE_IS_420_XXX], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_mode_is_420_only(NULL, NULL); + drm_mode_is_420_also(NULL, NULL); + ], [drm_mode_is_420_only drm_mode_is_420_also],[drivers/gpu/drm/drm_modes.c],[ + AC_DEFINE(HAVE_DRM_MODE_IS_420_XXX, 1, + [drm_mode_is_420_xxx() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 00ac87837a73c..d9d0406b6abc7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -97,6 +97,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_KMS_HELPER_IS_POLL_WORKER AC_AMDGPU_DRM_DRIVER_RELEASE AC_AMDGPU_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER + AC_AMDGPU_DRM_MODE_IS_420_XXX AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_modes.h b/include/kcl/kcl_drm_modes.h new file mode 100644 index 0000000000000..c47d691ca6e7a --- /dev/null +++ b/include/kcl/kcl_drm_modes.h @@ -0,0 +1,39 @@ +/* + * Copyright © 2006 Keith Packard + * Copyright © 2007-2008 Dave Airlie + * Copyright © 2007-2008 Intel Corporation + * Jesse Barnes + * Copyright © 2014 Intel Corporation + * Daniel Vetter + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef KCL_KCL_DRM_MODES_H +#define KCL_KCL_DRM_MODES_H + +#include + +#ifndef HAVE_DRM_MODE_IS_420_XXX +bool drm_mode_is_420_only(const struct drm_display_info *display, + const struct drm_display_mode *mode); +bool drm_mode_is_420_also(const struct drm_display_info *display, + const struct drm_display_mode *mode); +#endif + +#endif From 92af54546a15240b7f449b55b2f2c377948beb8c Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Thu, 9 May 2019 17:20:26 -0400 Subject: [PATCH 0246/1868] drm/amdkcl: Test whether format in struct drm_framebuffer is available v1: drm/amdkcl: Test whether drm_framebuffer structure contains format v2: drm/amd/autoconf: test whether struct drm_framebuffer have format v3: drm/amdkcl: fix for HAVE_DRM_FRAMEBUFFER_FORMAT v4: drm/amdkcl: accommodate to drmP.h removal for drm-framebuffer-format.m4 It's a squash of drm/amdkcl: fix pitch setting on leacy kernel drm/amdkcl: fix test for drm_framebuffer->format Signed-off-by: Flora Cui Reviewed-by: Yang Xiong drm/amdkcl: [4.11] fix for struct drm_framebuffer format build error v2 Signed-off-by: changzhu Reviewed-by: Nicholas Kazlauskas Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang Change-Id: I03e3c89fa4144a526e917c5fe671a8b60855258a Signed-off-by: Slava Grigorev Signed-off-by: Yifan Zhang Signed-off-by: chen gong Signed-off-by: Jack Gui Reviewed-by: Flora Cui Reviewed-by: Feifei Xu Signed-off-by: Flora Cui Signed-off-by: Yang Xiong Signed-off-by: Ma Jun --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 ++++++++ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 12 ++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 +- 3 files changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 40c634ca0ef2d..05597cd3b0122 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -5400,7 +5400,11 @@ fill_dc_plane_info_and_addr(struct amdgpu_device *adev, memset(plane_info, 0, sizeof(*plane_info)); +#ifndef HAVE_DRM_FRAMEBUFFER_FORMAT + switch (fb->pixel_format) { +#else switch (fb->format->format) { +#endif case DRM_FORMAT_C8: plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS; @@ -5452,7 +5456,11 @@ fill_dc_plane_info_and_addr(struct amdgpu_device *adev, default: DRM_ERROR( "Unsupported screen format %p4cc\n", +#ifdef HAVE_DRM_FRAMEBUFFER_FORMAT &fb->format->format); +#else + &fb->pixel_format); +#endif return -EINVAL; } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index ed1a7d56e4d95..aba6b2a3043bc 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -859,7 +859,11 @@ int amdgpu_dm_plane_fill_plane_buffer_attributes(struct amdgpu_device *adev, plane_size->surface_size.width = fb->width; plane_size->surface_size.height = fb->height; plane_size->surface_pitch = +#ifndef HAVE_DRM_FRAMEBUFFER_FORMAT + fb->pitches[0] / (fb->bits_per_pixel / 8); +#else fb->pitches[0] / fb->format->cpp[0]; +#endif address->type = PLN_ADDR_TYPE_GRAPHICS; address->grph.addr.low_part = lower_32_bits(addr); @@ -873,7 +877,11 @@ int amdgpu_dm_plane_fill_plane_buffer_attributes(struct amdgpu_device *adev, plane_size->surface_size.width = fb->width; plane_size->surface_size.height = fb->height; plane_size->surface_pitch = +#ifndef HAVE_DRM_FRAMEBUFFER_FORMAT + fb->pitches[0] / (fb->bits_per_pixel / 8); +#else fb->pitches[0] / fb->format->cpp[0]; +#endif plane_size->chroma_size.x = 0; plane_size->chroma_size.y = 0; @@ -882,7 +890,11 @@ int amdgpu_dm_plane_fill_plane_buffer_attributes(struct amdgpu_device *adev, plane_size->chroma_size.height = fb->height / 2; plane_size->chroma_pitch = +#ifndef HAVE_DRM_FRAMEBUFFER_FORMAT + fb->pitches[1] / (fb->bits_per_pixel / 8)/2; +#else fb->pitches[1] / fb->format->cpp[1]; +#endif address->type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE; address->video_progressive.luma_addr.low_part = diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index d9d0406b6abc7..f8984384a9f5d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -88,7 +88,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED AC_AMDGPU_DRM_HELPER_MODE_FILL_FB_STRUCT AC_AMDGPU_DRM_FB_HELPER_INIT - AC_AMDGPU_DRM_FRAMEBUFFER_FORMAT AC_AMDGPU_DRM_GET_FORMAT_INFO AC_AMDGPU_DRM_HELPER_FORCE_DISABLE_ALL AC_AMDGPU_DRM_EDID_TO_ELD @@ -98,6 +97,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DRIVER_RELEASE AC_AMDGPU_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER AC_AMDGPU_DRM_MODE_IS_420_XXX + AC_AMDGPU_DRM_FRAMEBUFFER_FORMAT AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 6d61ea3c978620b48f383a189bbc626b329d948c Mon Sep 17 00:00:00 2001 From: chen gong Date: Mon, 10 Jun 2019 10:52:24 +0800 Subject: [PATCH 0247/1868] drm/amdkcl: Test whether strscpy() is available Change-Id: Ieaf30809e752533ae30b493d7490ceb640476a6a Signed-off-by: chen gong Reviewed-by: Slava Grigorev Signed-off-by: Yifan Zhang Signed-off-by: Jack Gui Signed-off-by: Ma Jun --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 10 ++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/strscpy.m4 | 17 +++++++++++++++++ 3 files changed, 28 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/strscpy.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 05597cd3b0122..9b6dadb5a783c 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -6092,9 +6092,15 @@ static void fill_audio_info(struct audio_info *audio_info, cea_revision = drm_connector->display_info.cea_rev; +#if !defined(HAVE_STRSCPY) + strncpy(audio_info->display_name, + edid_caps->display_name, + AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS - 1); +#else strscpy(audio_info->display_name, edid_caps->display_name, AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS); +#endif if (cea_revision >= 3) { audio_info->mode_count = edid_caps->audio_mode_count; @@ -7725,7 +7731,11 @@ amdgpu_dm_create_common_mode(struct drm_encoder *encoder, mode->hdisplay = hdisplay; mode->vdisplay = vdisplay; mode->type &= ~DRM_MODE_TYPE_PREFERRED; +#if !defined(HAVE_STRSCPY) + strncpy(mode->name, name, DRM_DISPLAY_MODE_LEN); +#else strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN); +#endif return mode; diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index f8984384a9f5d..a195dee0dcd92 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -98,6 +98,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER AC_AMDGPU_DRM_MODE_IS_420_XXX AC_AMDGPU_DRM_FRAMEBUFFER_FORMAT + AC_AMDGPU_STRSCPY AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/strscpy.m4 b/drivers/gpu/drm/amd/dkms/m4/strscpy.m4 new file mode 100644 index 0000000000000..35ace5a7694c7 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/strscpy.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit 30035e45753b708e7d47a98398500ca005e02b86 +dnl # Author: Chris Metcalf +dnl # Date: Wed Apr 29 12:52:04 2015 -0400 +dnl # string: provide strscpy() +dnl # +AC_DEFUN([AC_AMDGPU_STRSCPY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + strscpy(NULL, NULL, 8); + ], [strscpy], [lib/string.c], [ + AC_DEFINE(HAVE_STRSCPY, 1, [strscpy() is available]) + ]) + ]) +]) From 02695b6bbc50a176e51a8b65041500d93c3883ae Mon Sep 17 00:00:00 2001 From: Rui Teng Date: Mon, 23 Sep 2019 19:29:57 +0800 Subject: [PATCH 0248/1868] drm/amdkcl: check whether DEFINE_DEBUGFS_ATTRIBUTE is available DEFINE_DEBUGFS_ATTRIBUTE and debugfs_create_file_unsafe is introduced by kernel 4.7 - commit c64688081490321f2d23a292ef24e60bb321f3f1 - Author: Nicolai Stange - debugfs: add support for self-protecting attribute file fops Change-Id: Ia4c9ddf96d50a5eea76a28c6e8f3a012332f1f69 Signed-off-by: Rui Teng Reviewed-by: Flora Cui Signed-off-by: Jack Gui drm/amdkcl: fix compile error if DEFINE_DEBUGFS_ATTRIBUTE not defined Change-Id: I23277d6b9c298fb4325cc54b1ca7379e45b68d99 Signed-off-by: Stanley.Yang --- .../drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index db56b0aa54545..6ddba57c50d62 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -3031,8 +3031,10 @@ static int force_yuv420_output_get(void *data, u64 *val) return 0; } +#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(force_yuv420_output_fops, force_yuv420_output_get, force_yuv420_output_set, "%llu\n"); +#endif /* * Read Replay state @@ -3265,6 +3267,7 @@ static int dmcub_trace_event_state_get(void *data, u64 *val) return 0; } +#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(dmcub_trace_event_state_fops, dmcub_trace_event_state_get, dmcub_trace_event_state_set, "%llu\n"); @@ -3281,6 +3284,7 @@ DEFINE_DEBUGFS_ATTRIBUTE(allow_edp_hotplug_detection_fops, DEFINE_DEBUGFS_ATTRIBUTE(disallow_edp_enter_psr_fops, disallow_edp_enter_psr_get, disallow_edp_enter_psr_set, "%llu\n"); +#endif DEFINE_SHOW_ATTRIBUTE(current_backlight); DEFINE_SHOW_ATTRIBUTE(target_backlight); @@ -3290,7 +3294,9 @@ static const struct { char *name; const struct file_operations *fops; } connector_debugfs_entries[] = { +#ifdef DEFINE_DEBUGFS_ATTRIBUTE {"force_yuv420_output", &force_yuv420_output_fops}, +#endif {"trigger_hotplug", &trigger_hotplug_debugfs_fops}, {"internal_display", &internal_display_fops}, {"odm_combine_segments", &odm_combine_segments_fops} @@ -3443,6 +3449,8 @@ void connector_debugfs_init(struct amdgpu_dm_connector *connector) dp_debugfs_entries[i].fops); } } + +#ifdef DEFINE_DEBUGFS_ATTRIBUTE if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP) { debugfs_create_file("replay_capability", 0444, dir, connector, &replay_capability_fops); @@ -3462,6 +3470,7 @@ void connector_debugfs_init(struct amdgpu_dm_connector *connector) debugfs_create_file("disallow_edp_enter_psr", 0644, dir, connector, &disallow_edp_enter_psr_fops); } +#endif for (i = 0; i < ARRAY_SIZE(connector_debugfs_entries); i++) { debugfs_create_file(connector_debugfs_entries[i].name, @@ -3884,8 +3893,10 @@ static int force_timing_sync_get(void *data, u64 *val) return 0; } +#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(force_timing_sync_ops, force_timing_sync_get, force_timing_sync_set, "%llu\n"); +#endif /* @@ -4023,8 +4034,10 @@ static int visual_confirm_get(void *data, u64 *val) } DEFINE_SHOW_ATTRIBUTE(mst_topo); +#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(visual_confirm_fops, visual_confirm_get, visual_confirm_set, "%llu\n"); +#endif /* @@ -4150,6 +4163,7 @@ void dtn_debugfs_init(struct amdgpu_device *adev) debugfs_create_file("amdgpu_dm_dp_ignore_cable_id", 0644, root, adev, &dp_ignore_cable_id_ops); +#ifdef DEFINE_DEBUGFS_ATTRIBUTE debugfs_create_file_unsafe("amdgpu_dm_visual_confirm", 0644, root, adev, &visual_confirm_fops); @@ -4183,4 +4197,5 @@ void dtn_debugfs_init(struct amdgpu_device *adev) if (adev->dm.dc->caps.ips_support) debugfs_create_file_unsafe("amdgpu_dm_ips_status", 0644, root, adev, &ips_status_fops); +#endif } From 8669adc9cb311e4f2310f3d0d07b42898186f654 Mon Sep 17 00:00:00 2001 From: chen gong Date: Thu, 16 May 2019 16:29:41 +0800 Subject: [PATCH 0249/1868] drm/amdkcl: check whether for_each_{old/new/oldnew}_{plane/connector/crtc}_in_state is available drm/amdkcl: Test whether for_each_oldnew_plane_in_state() is defined Change-Id: Iff20a648d390ab976a5d98443ee6037b10968561 Signed-off-by: chen gong Reviewed-by: Anatoli Antonovitch Signed-off-by: Yifan Zhang Signed-off-by: Jack Gui drm/amdkcl: Test whether for_each_oldnew_connector_in_state() is defined Change-Id: I7b2847ca6fc7e847ba9e06bc2e2e9173ef26e8cf Signed-off-by: chen gong Reviewed-by: Anatoli Antonovitch Signed-off-by: Yifan Zhang Signed-off-by: Jack Gui drm/amdkcl: Test whether for_each_new_crtc_in_state() is defined Change-Id: Iedac8a5691e7bec594db95096259ff260d05b684 Signed-off-by: chen gong Reviewed-by: Anatoli Antonovitch Signed-off-by: Yifan Zhang Signed-off-by: Jack Gui drm/amdkcl: add protection for for_each_new_crtc_in_state Signed-off-by: Yifan Zhang Reviewed-by: Feifei Xu Signed-off-by: Jack Gui drm/amdkcl: check whether for_each_{old/new/oldnew}_{plane/connector/crtc}_in_state is available drm/amdkcl: test for_each_new_crtc_in_state directly for_each_new_crtc_in_state is a macro which can be tested directly with #ifdef, save a m4 macro Change-Id: I747b753244b1b514ef4a2ad4c1e0cc8bd8fb1314 Signed-off-by: Yifan Zhang Signed-off-by: Jack Gui drm/amdkcl: test for_each_oldnew_plane_in_state directly Change-Id: Ia1a265e35b690ecbf2620a235191c0f269c84fbf Signed-off-by: Yifan Zhang Signed-off-by: Jack Gui drm/amdkcl: test for_each_oldnew_connector_in_state directly Change-Id: I054e2e8db8091d3aa63ebd38c350f2b219edae6c Signed-off-by: Yifan Zhang Signed-off-by: Jack Gui drm/amdkcl: check whether for_each_{old/new/oldnew}_{plane/connector/crtc}_in_state is available Related commit: v4.12~21^2~8^2~134 - commit 581e49fe6b411f407102a7f2377648849e0fa37f - drm/atomic: Add new iterators over all state, v3 v4.17-rc2~1^2~24^2~13 - commit 55de2923847c3318459758931ff175996facce69 - drm/atomic: Add new reverse iterator over all plane state (V2) Signed-off-by: Chengming Gui Reviewed-by: Flora Cui Signed-off-by: Jack Gui drm/amdkcl: rework for_each_oldnew_plane_in_state_reverse to fix install failure with ubuntu16.04.5 & phontom Signed-off-by: Flora Cui Reviewed-by: Feifei Xu Signed-off-by: Jack Gui Signed-off-by: Flora Cui Change-Id: Ib4bb484bd839ddd20881f0e0d8166e24877124ab Signed-off-by: chen gong --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 +-- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 31 +++++++++++++++++++ 2 files changed, 33 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 9b6dadb5a783c..0dafff022ca73 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -9348,7 +9348,7 @@ static void amdgpu_dm_commit_streams(struct drm_atomic_state *state, } for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, - new_crtc_state, i) { + new_crtc_state, i) { struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc); dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); @@ -11329,9 +11329,9 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, } } } + for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); - if (!drm_atomic_crtc_needs_modeset(new_crtc_state) && !new_crtc_state->color_mgmt_changed && old_crtc_state->vrr_enabled == new_crtc_state->vrr_enabled && diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index 1b0414421ad58..b935387fb6c1e 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -197,6 +197,31 @@ struct amdgpu_dm_backlight_caps { u8 dc_level; }; +/** + * for_each_oldnew_plane_in_state_reverse - iterate over all planes in an atomic + * update in reverse order + * @__state: &struct drm_atomic_state pointer + * @plane: &struct drm_plane iteration cursor + * @old_plane_state: &struct drm_plane_state iteration cursor for the old state + * @new_plane_state: &struct drm_plane_state iteration cursor for the new state + * @__i: int iteration cursor, for macro-internal use + * + * This iterates over all planes in an atomic update in reverse order, + * tracking both old and new state. This is useful in places where the + * state delta needs to be considered, for example in atomic check functions. + */ +#if !defined(for_each_oldnew_plane_in_state_reverse) && \ + defined(for_each_oldnew_plane_in_state) +#define for_each_oldnew_plane_in_state_reverse(__state, plane, old_plane_state, new_plane_state, __i) \ + for ((__i) = ((__state)->dev->mode_config.num_total_plane - 1); \ + (__i) >= 0; \ + (__i)--) \ + for_each_if ((__state)->planes[__i].ptr && \ + ((plane) = (__state)->planes[__i].ptr, \ + (old_plane_state) = (__state)->planes[__i].old_state,\ + (new_plane_state) = (__state)->planes[__i].new_state, 1)) +#endif + /** * struct dal_allocation - Tracks mapped FB memory for SMU communication * @list: list of dal allocations @@ -211,6 +236,7 @@ struct dal_allocation { u64 gpu_addr; }; + /** * struct hpd_rx_irq_offload_work_queue - Work queue to handle hpd_rx_irq * offload work @@ -999,7 +1025,12 @@ int dm_atomic_get_state(struct drm_atomic_state *state, struct drm_connector * amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state, +#ifndef for_each_new_connector_in_state + struct drm_crtc *crtc, + bool from_state_var); +#else struct drm_crtc *crtc); +#endif int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth); struct idle_workqueue *idle_create_workqueue(struct amdgpu_device *adev); From f70f914ce2d2a1e0715215478b89a1c10a253113 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Sat, 9 May 2020 17:46:12 +0800 Subject: [PATCH 0250/1868] drm/amdkcl: test struct drm_crtc_funcs->enable_vblank struct drm_crtc_funcs->enable_vblank is introduced in v4.10-rc5-1070-g84e354839b15 It's a squash of drm/amdkcl: drop macro check for dm_enable/disable_vblank Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang drm/amdkcl: [4.12] Fix drm_crtc_funcs - .{enable/disable}_vblank Signed-off-by: Yifan Zhang Signed-off-by: Flora Cui Acked-by: Rodrigo Siqueira Signed-off-by: Yang Xiong Change-Id: I23428ae35e3a7898e55608622d2fc9de3237270a Signed-off-by: Ma Jun --- .../amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 2 ++ .../drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 | 19 +++++++++++++++++++ 2 files changed, 21 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c index af7a5a721dbc0..02bd2415b9d9f 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c @@ -549,8 +549,10 @@ static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = { .set_crc_source = amdgpu_dm_crtc_set_crc_source, .verify_crc_source = amdgpu_dm_crtc_verify_crc_source, .get_crc_sources = amdgpu_dm_crtc_get_crc_sources, +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_ENABLE_VBLANK .enable_vblank = amdgpu_dm_crtc_enable_vblank, .disable_vblank = amdgpu_dm_crtc_disable_vblank, +#endif #ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP .get_vblank_counter = amdgpu_get_vblank_counter_kms, .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 index 412f1d90ec93d..ba4d038ec86f7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 @@ -75,8 +75,27 @@ AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET], [ ]) ]) +dnl # +dnl # commit v4.10-rc5-1070-g84e354839b15 +dnl # drm: add vblank hooks to struct drm_crtc_funcs +dnl # +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_ENABLE_VBLANK], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_crtc_funcs *crtc_funcs = NULL; + crtc_funcs->enable_vblank(NULL); + ], [ + AC_DEFINE(HAVE_STRUCT_DRM_CRTC_FUNCS_ENABLE_VBLANK, 1, [ + drm_crtc_funcs->enable_vblank() is available]) + ]) + ]) +]) + AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS], [ AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP + AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_ENABLE_VBLANK AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_SET_CONFIG AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET ]) From e8d3f301ca669c82131875fa36e1d2ca71ded03f Mon Sep 17 00:00:00 2001 From: changzhu Date: Wed, 30 Jan 2019 13:07:27 +0800 Subject: [PATCH 0251/1868] drm/amdkcl: adapt drm_crtc_funcs->set_crc_source change [Why] In drm_crtc.h,drm_crtc_funcs->set_crc_source is defined since DRM_VERSION(4,10,0).It has three parameters until DRM_VERSION(4,20,0).After DRM_VERSION(4,20,0),it has two parameters.The change is as below: From: int (*set_crc_source)(struct drm_crtc *crtc, const char *source, size_t *values_cnt); To: int (*set_crc_source)(struct drm_crtc *crtc, const char *source); In amdgpu_dm.c.we have code: .set_crc_source = amdgpu_dm_crtc_set_crc_source, and amdgpu_dm_crtc_set_crc_source(crtc, "auto"); So we will meet build error when use amdgpu_dm_crtc_set_crc_source because it has three parameters before DRM_VERSION(4,20,0) In drm_crtc.h,drm_crtc_funcs->verify_crc_source is not defined until DRM_VERSION(4,20,0).However,this member is used by patch: drm/crc: Cleanup crtc_crc_open function This patch is needed because we use newly defined function amdgpu_dm_crtc_set_crc_source To fix drm_crtc_funcs->verify_crc_source customer build error,we need to cherry-pick patch: drm/amdgpu_dm/crc: Implement verify_crc_source callback So it will meet build error when use amdgpu_dm_crtc_verify_crc_source before DRM_VERSION(4,20,0) [How] Keep parameter:size_t *values_cnt before DRM_VERSION(4,20,0) to fix .set_crc_source = amdgpu_dm_crtc_set_crc_source, build error. Use amdgpu_dm_crtc_set_crc_source(crtc, "auto", NULL); before DRM_VERSION(4,20,0) to fix amdgpu_dm_crtc_set_crc_source(crtc, "auto"); build error. Avoid using amdgpu_dm_crtc_verify_crc_source before DRM_VERSION(4,20,0) It's a squash of drm/amdkcl: refactor test for drm_crtc_funcs->set_crc_source Signed-off-by: Flora Cui Acked-by: Rodrigo Siqueira drm/amdkcl: [4.20] fix amdgpu_dm_crtc_set_crc_source few arguments error Signed-off-by: changzhu Reviewed-by: Rui Teng Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang drm/amdkcl: add guarding for amdgpu_dm_crtc_handle_crc_irq call Signed-off-by: Jiansong Chen Reviewed-by: Jack Gui Signed-off-by: Yifan Zhang drm/amdkcl: test struct drm_crtc_funcs->get/verify_crtc_source Signed-off-by: Flora Cui Acked-by: Rodrigo Siqueira Change-Id: Ie33bf644377ad146ce486a2f0957f400e4929e3a Signed-off-by: changzhu Reviewed-by: tianci yin Signed-off-by: Jack Gui Signed-off-by: Yang Xiong Signed-off-by: Ma Jun --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++ .../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c | 4 ++++ .../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h | 3 +++ .../amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 2 ++ .../drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 | 22 +++++++++++++++++++ 5 files changed, 33 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 0dafff022ca73..2e54e7ffca5b1 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -661,7 +661,9 @@ static void dm_crtc_high_irq(void *interrupt_params) * Following stuff must happen at start of vblank, for crc * computation and below-the-range btr support in vrr mode. */ +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VERIFY_CRC_SOURCES amdgpu_dm_crtc_handle_crc_irq(&acrtc->base); +#endif /* BTR updates need to happen before VUPDATE on Vega and above. */ if (adev->family < AMDGPU_FAMILY_AI) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c index f936a35fa9ebb..741e2526ec127 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c @@ -31,6 +31,7 @@ #include "dc.h" #include "amdgpu_securedisplay.h" +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VERIFY_CRC_SOURCES static const char *const pipe_crc_sources[] = { "none", "crtc", @@ -39,6 +40,7 @@ static const char *const pipe_crc_sources[] = { "dprx dither", "auto", }; +#endif static enum amdgpu_dm_pipe_crc_source dm_parse_crc_source(const char *source) { @@ -75,6 +77,7 @@ static bool dm_need_crc_dither(enum amdgpu_dm_pipe_crc_source src) (src == AMDGPU_DM_PIPE_CRC_SOURCE_NONE); } +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VERIFY_CRC_SOURCES const char *const *amdgpu_dm_crtc_get_crc_sources(struct drm_crtc *crtc, size_t *count) { @@ -208,6 +211,7 @@ amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc, const char *src_name, *values_cnt = 3; return 0; } +#endif int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc, struct dm_crtc_state *dm_crtc_state, diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h index 748e80ef40d0a..ce48316355cac 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h @@ -79,11 +79,14 @@ int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc, struct dm_crtc_state *dm_crtc_state, enum amdgpu_dm_pipe_crc_source source); int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name); + +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VERIFY_CRC_SOURCES int amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc, const char *src_name, size_t *values_cnt); const char *const *amdgpu_dm_crtc_get_crc_sources(struct drm_crtc *crtc, size_t *count); +#endif /* HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VERIFY_CRC_SOURCES */ void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc); #else #define amdgpu_dm_crtc_set_crc_source NULL diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c index 02bd2415b9d9f..2e2b7e0f5897e 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c @@ -547,8 +547,10 @@ static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = { .atomic_duplicate_state = amdgpu_dm_crtc_duplicate_state, .atomic_destroy_state = amdgpu_dm_crtc_destroy_state, .set_crc_source = amdgpu_dm_crtc_set_crc_source, +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VERIFY_CRC_SOURCES .verify_crc_source = amdgpu_dm_crtc_verify_crc_source, .get_crc_sources = amdgpu_dm_crtc_get_crc_sources, +#endif #ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_ENABLE_VBLANK .enable_vblank = amdgpu_dm_crtc_enable_vblank, .disable_vblank = amdgpu_dm_crtc_disable_vblank, diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 index ba4d038ec86f7..211d8df287f57 100644 --- a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 @@ -93,9 +93,31 @@ AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_ENABLE_VBLANK], [ ]) ]) +dnl # +dnl # v5.2-rc5-2034-g8fb843d179a6 drm/amd/display: add functionality to get pipe CRC source. +dnl # v4.18-rc3-759-g3b3b8448ebd1 drm/amdgpu_dm/crc: Implement verify_crc_source callback +dnl # v4.18-rc3-757-g4396551e9cf3 drm: crc: Introduce get_crc_sources callback +dnl # v4.18-rc3-756-gd5cc15a0c66e drm: crc: Introduce verify_crc_source callback +dnl # +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GET_VERIFY_CRC_SOURCES], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_crtc_funcs *crtc_funcs = NULL; + crtc_funcs->get_crc_sources(NULL, NULL); + crtc_funcs->verify_crc_source(NULL, NULL, NULL); + ], [ + AC_DEFINE(HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VERIFY_CRC_SOURCES, 1, [ + drm_crtc_funcs->{get,verify}_crc_sources() is available]) + ]) + ]) +]) + AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS], [ AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_ENABLE_VBLANK + AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GET_VERIFY_CRC_SOURCES AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_SET_CONFIG AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET ]) From 2b3ec781d92585c66dade6375a1f5911580035dc Mon Sep 17 00:00:00 2001 From: Adam Yang Date: Wed, 18 Sep 2019 23:25:40 +0800 Subject: [PATCH 0252/1868] drm/amdkcl: test whether drm_dp_mst_allocate_vcpi() has p,p,i,i interface It's a squash of drm/amdkcl: Test whether drm_dp_mst_{get,put}_port_malloc() is available Signed-off-by: Adam Yang Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang Change-Id: I99ef7484b72edf3266bed3cd7cb0cc1db117f05d Signed-off-by: Adam Yang Reviewed-by: Flora Cui Signed-off-by: Jack Gui Signed-off-by: Yang Xiong --- .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 4 ++ .../drm/amd/dkms/m4/drm-dp-mst-topology.m4 | 55 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 60 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 2e9f6da1acdca..6875c1d09b093 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -132,7 +132,9 @@ dm_dp_mst_connector_destroy(struct drm_connector *connector) kfree(aconnector->edid); drm_connector_cleanup(connector); +#if defined(HAVE_DRM_DP_MST_GET_PUT_PORT_MALLOC) drm_dp_mst_put_port_malloc(aconnector->mst_output_port); +#endif /* HAVE_DRM_DP_MST_GET_PUT_PORT_MALLOC */ kfree(aconnector); } @@ -634,7 +636,9 @@ dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr, */ amdgpu_dm_connector_funcs_reset(connector); +#if defined(HAVE_DRM_DP_MST_GET_PUT_PORT_MALLOC) drm_dp_mst_get_port_malloc(port); +#endif /* HAVE_DRM_DP_MST_GET_PUT_PORT_MALLOC */ return connector; } diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 new file mode 100644 index 0000000000000..5c6393f547854 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 @@ -0,0 +1,55 @@ +dnl # +dnl # commit 1e797f556c616a42f1e039b1ff1d3c58f61b6104 +dnl # drm/dp: Split drm_dp_mst_allocate_vcpi +dnl # +dnl # Note: This autoconf only works with compiler flag -Werror +dnl # The interface types are specified in Hungarian notation +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_dp_mst_allocate_vcpi(NULL, NULL, 1, 1); + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_ALLOCATE_VCPI_P_P_I_I, 1, [ + drm_dp_mst_allocate_vcpi() has p,p,i,i interface]) + ]) + ]) + dnl # + dnl # commit d25689760b747287c6ca03cfe0729da63e0717f4 + dnl # drm/amdgpu/display: Keep malloc ref to MST port + dnl # + dnl # commit ebcc0e6b509108b4a67daa4c55809a05ab7f4b77 + dnl # drm/dp_mst: Introduce new refcounting scheme for mstbs and ports + dnl # + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_dp_mst_get_port_malloc(NULL); + drm_dp_mst_put_port_malloc(NULL); + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_GET_PUT_PORT_MALLOC, 1, [ + drm_dp_mst_{get,put}_port_malloc() is available]) + ]) + ]) + dnl # + dnl # commit aad0eab4e8dd76d1ba5248f9278633829cbcec38 + dnl # drm/dp_mst: Enable registration of AUX devices for MST ports + dnl # + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_dp_mst_connector_early_unregister(NULL, NULL); + drm_dp_mst_connector_late_register(NULL, NULL); + ], [ + AC_DEFINE(HAVE_DP_MST_CONNECTOR_EARLY_UNREGISTER, 1, [ + drm_dp_mst_connector_early_unregister() is available]) + AC_DEFINE(HAVE_DP_MST_CONNECTOR_LATE_REGISTER, 1, [ + drm_dp_mst_connector_late_register() is available]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index a195dee0dcd92..ff2fe3a1f8016 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -99,6 +99,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_MODE_IS_420_XXX AC_AMDGPU_DRM_FRAMEBUFFER_FORMAT AC_AMDGPU_STRSCPY + AC_AMDGPU_DRM_DP_MST_TOPOLOGY AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From ee6f03d09262abbc303f920dad8e0b8f7830161b Mon Sep 17 00:00:00 2001 From: changzhu Date: Fri, 19 Apr 2019 13:58:42 +0800 Subject: [PATCH 0253/1868] drm/amdkcl: test whether struct drm_dp_mst_topology_cbs has hotplug drm/amdkcl: [5.1] Fix multiple MST daisy chain issues within DM [Why] This patch fixes the following issues: - Null pointer dereference was found with MST monitor attached - MST daisy chain hotplugging doesn't work [How] Until DRM Ver.5.0, we need a MST hotplug function to deal with MST hotplug operations. (this function is not needed since DRV Ver.5.1 rc1). Hence a MST hotplug function is added to avoid hotplug failure. (the old hotplug structure was replaced within DRV Ver.5.1) Signed-off-by: Zhan Liu Reviewed-by: Xiaojie Yuan Reviewed-by: Junwei Zhang drm/amdkcl: fix dm_dp_mst_hotplug custom kernel build error [Why] There is build error when using dm_dp_mst_hotplug to build custom kernel on dkms-5.0 branch [How] Avoid using dm_dp_mst_hotplug when building custom kernel on dkms-5.0 branch. This kcl patch is supplement for kcl patch: drm/amdkcl: [5.1] Fix multiple MST daisy chain issues within DM Change-Id: I827c06eee369f0b5468e8298376f8aea344c5533 Signed-off-by: changzhu Reviewed-by: Zhan Liu drm/amdkcl: test whether struct drm_dp_mst_topology_cbs has hotplug Signed-off-by: Flora Cui Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang --- .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 31 ++++++++++++++ .../amd/dkms/m4/drm-dp-mst-topology-cbs.m4 | 42 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 74 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 6875c1d09b093..1f3e7dc87b0e3 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -752,8 +752,39 @@ static void dm_handle_mst_down_rep_msg_ready(struct drm_dp_mst_topology_mgr *mgr dm_handle_mst_sideband_msg_ready_event(mgr, DOWN_REP_MSG_RDY_EVENT); } +#if defined(HAVE_DRM_DP_MST_TOPOLOGY_CBS_HOTPLUG) +static void dm_dp_mst_hotplug(struct drm_dp_mst_topology_mgr *mgr) +{ + struct amdgpu_dm_connector *master = container_of(mgr, struct amdgpu_dm_connector, mst_mgr); + struct drm_device *dev = master->base.dev; + + drm_kms_helper_hotplug_event(dev); +} +#endif + +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_CBS_REGISTER_CONNECTOR +static void dm_dp_mst_register_connector(struct drm_connector *connector) +{ + struct drm_device *dev = connector->dev; + struct amdgpu_device *adev = dev->dev_private; + + if (adev->mode_info.rfbdev) + drm_fb_helper_add_one_connector(&adev->mode_info.rfbdev->helper, connector); + else + DRM_ERROR("adev->mode_info.rfbdev is NULL\n"); + + drm_connector_register(connector); +} +#endif + static const struct drm_dp_mst_topology_cbs dm_mst_cbs = { .add_connector = dm_dp_add_mst_connector, +#if defined(HAVE_DRM_DP_MST_TOPOLOGY_CBS_HOTPLUG) + .hotplug = dm_dp_mst_hotplug, +#endif +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_CBS_REGISTER_CONNECTOR + .register_connector = dm_dp_mst_register_connector +#endif .poll_hpd_irq = dm_handle_mst_down_rep_msg_ready, }; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 new file mode 100644 index 0000000000000..5847b52020f9f --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 @@ -0,0 +1,42 @@ +dnl # +dnl # commit v4.20-rc4-941-g16bff572cc66 +dnl # drm/dp-mst-helper: Remove hotplug callback +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_HOTPLUG], [ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_dp_mst_topology_cbs *dp_mst_cbs = NULL; + dp_mst_cbs->hotplug(NULL); + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_TOPOLOGY_CBS_HOTPLUG, 1, + [struct drm_dp_mst_topology_cbs has hotplug member]) + ]) +]) + + +dnl # +dnl # commit v5.6-rc2-1065-ga5c4dc165957 +dnl # drm/dp_mst: Remove register_connector callback +dnl # +dnl # commit v4.3-rc3-39-gd9515c5ec1a2 +dnl # drm/dp/mst: split connector registration into two parts (v2) +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_REGISTER_CONNECTOR], [ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_dp_mst_topology_cbs *dp_mst_cbs = NULL; + dp_mst_cbs->register_connector(NULL); + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_TOPOLOGY_CBS_REGISTER_CONNECTOR, 1, + [struct drm_dp_mst_topology_cbs->register_connector is available]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_HOTPLUG + AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_REGISTER_CONNECTOR + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index ff2fe3a1f8016..f7d18acaf3e1e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -100,6 +100,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_FRAMEBUFFER_FORMAT AC_AMDGPU_STRSCPY AC_AMDGPU_DRM_DP_MST_TOPOLOGY + AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 0991da75e64f075317931ef5d510cf1fdbbe489d Mon Sep 17 00:00:00 2001 From: Adam Yang Date: Mon, 23 Sep 2019 20:31:53 +0800 Subject: [PATCH 0254/1868] drm/amdkcl: Test whether drm_atomic_private_obj_init() has p,p,p,p interface It's a squash of drm/amdkcl: drop drm version 4.2 support Signed-off-by: Flora Cui Reviewed-by: Yang Xiong drm/amdkcl: [4.2] fix drm_atomic_crtc_needs_modeset Signed-off-by: Chengming Gui Signed-off-by: Yifan Zhang drm/amdkcl: [4.2] fix drm_atomic_add_affected_planes Signed-off-by: changzhu Reviewed-by: Amber Lin Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang drm/amdkcl: refactor test for drm_atomic_private_obj_init Signed-off-by: Flora Cui Acked-by: Rodrigo Siqueira Signed-off-by: Flora Cui drm/amdkcl: add kcl for commit 7747415697139b1e3d57ba10572ce0298ca41996 Signed-off-by: Yifan Zhang Reviewed-by: Flora Cui Signed-off-by: Jack Gui drm/amdkcl: [4.14] fix amdgpu_display_manager lack memeber atomic_obj build error Signed-off-by: changzhu Reviewed-by: Nicholas Kazlauskas Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang drm/amdkcl: [4.14] add kcl for "drm/amd/display: Use private obj helpers for dm_atomic_state" Reviewed-by: Nicholas Kazlauskas Signed-off-by: Tianci Yin Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang drm/amdkcl: test for drm_mode_config_funcs->atomic_state_alloc drop DRM_VERSION_CODE check in commit 11675cd9ee1e007ab91c102e2dc8082618636f93("drm/amdkcl: [4.14] add kcl for "drm/amd/display: Use private obj helpers for dm_atomic_state") drm_mode_config_funcs->atomic_state_alloc() is introduced in v4.12-rc7-1381-ga4370c777406 the test guard is changed to DRM_VERSION 4.13 instead of 4.10 Signed-off-by: Flora Cui Acked-by: Rodrigo Siqueira Change-Id: Ib7f028dcaa01fd9d543879d95ec18fce6daa37a2 Signed-off-by: Adam Yang Signed-off-by: Jack Gui Signed-off-by: Yang Xiong --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 104 ++++++++++++++++-- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 8 ++ .../dkms/m4/drm_atomic_private_obj_init.m4 | 31 ++++++ .../drm/amd/dkms/m4/drm_mode_config_funcs.m4 | 18 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 + 5 files changed, 156 insertions(+), 7 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_atomic_private_obj_init.m4 create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_mode_config_funcs.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 2e54e7ffca5b1..d58cdee22ea2c 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3087,7 +3087,9 @@ static int dm_resume(void *handle) struct drm_plane *plane; struct drm_plane_state *new_plane_state; struct dm_plane_state *dm_new_plane_state; +#ifdef HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state); +#endif enum dc_connection_type new_connection_type = dc_connection_none; struct dc_state *dc_state; int i, r, j, ret; @@ -3160,10 +3162,12 @@ static int dm_resume(void *handle) return 0; } +#ifdef HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT /* Recreate dc_state - DC invalidates it when setting power state to S3. */ dc_state_release(dm_state->context); dm_state->context = dc_state_create(dm->dc, NULL); /* TODO: Remove dc_state->dccg, use dc->dccg directly. */ +#endif /* Before powering on DC we need to re-initialize DMUB. */ dm_dmub_hw_resume(adev); @@ -3339,6 +3343,48 @@ const struct amdgpu_ip_block_version dm_ip_block = { .funcs = &amdgpu_dm_funcs, }; +#ifndef HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT +#ifdef HAVE_DRM_MODE_CONFIG_FUNCS_ATOMIC_STATE_ALLOC +static struct drm_atomic_state * +dm_atomic_state_alloc(struct drm_device *dev) +{ + struct dm_atomic_state *state = kzalloc(sizeof(*state), GFP_KERNEL); + + if (!state) + return NULL; + + if (drm_atomic_state_init(dev, &state->base) < 0) + goto fail; + + return &state->base; +fail: + kfree(state); + return NULL; +} + +static void +dm_atomic_state_clear(struct drm_atomic_state *state) +{ + struct dm_atomic_state *dm_state = to_dm_atomic_state(state); + + if (dm_state->context) { + dc_release_state(dm_state->context); + dm_state->context = NULL; + } + + drm_atomic_state_default_clear(state); +} + +static void +dm_atomic_state_alloc_free(struct drm_atomic_state *state) +{ + struct dm_atomic_state *dm_state = to_dm_atomic_state(state); + + drm_atomic_state_default_release(state); + kfree(dm_state); +} +#endif +#endif /** * DOC: atomic @@ -3351,6 +3397,13 @@ static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = { .get_format_info = amdgpu_dm_plane_get_format_info, .atomic_check = amdgpu_dm_atomic_check, .atomic_commit = drm_atomic_helper_commit, +#ifndef HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT +#ifdef HAVE_DRM_MODE_CONFIG_FUNCS_ATOMIC_STATE_ALLOC + .atomic_state_alloc = dm_atomic_state_alloc, + .atomic_state_clear = dm_atomic_state_clear, + .atomic_state_free = dm_atomic_state_alloc_free +#endif +#endif }; static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = { @@ -4287,6 +4340,7 @@ static int register_outbox_irq_handlers(struct amdgpu_device *adev) return 0; } +#ifdef HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT /* * Acquires the lock for the atomic state object and returns * the new atomic state. @@ -4370,6 +4424,7 @@ static struct drm_private_state_funcs dm_atomic_state_funcs = { .atomic_duplicate_state = dm_atomic_duplicate_state, .atomic_destroy_state = dm_atomic_destroy_state, }; +#endif static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) { @@ -4393,20 +4448,30 @@ static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) /* indicates support for immediate flip */ adev_to_drm(adev)->mode_config.async_page_flip = true; + drm_modeset_lock_init(&adev->dm.atomic_obj_lock); + state = kzalloc(sizeof(*state), GFP_KERNEL); if (!state) return -ENOMEM; +#ifdef HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT state->context = dc_state_create_current_copy(adev->dm.dc); if (!state->context) { kfree(state); return -ENOMEM; } +#ifdef HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT_P_P_P_P drm_atomic_private_obj_init(adev_to_drm(adev), &adev->dm.atomic_obj, &state->base, &dm_atomic_state_funcs); +#else + drm_atomic_private_obj_init(&adev->dm.atomic_obj, + &state->base, + &dm_atomic_state_funcs); +#endif +#endif r = amdgpu_display_modeset_create_props(adev); if (r) { @@ -5056,7 +5121,10 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm) { + drm_mode_config_cleanup(dm->ddev); +#ifdef HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT drm_atomic_private_obj_fini(&dm->atomic_obj); +#endif } /****************************************************************************** @@ -10249,7 +10317,11 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm, bool enable, bool *lock_and_validation_needed) { +#ifdef HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT struct dm_atomic_state *dm_state = NULL; +#else + struct dm_atomic_state *dm_state = to_dm_atomic_state(state); +#endif struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; struct dc_stream_state *new_stream; int ret = 0; @@ -10397,11 +10469,11 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm, if (!drm_mode_equal(&new_crtc_state->mode, high_mode)) set_freesync_fixed_config(dm_new_crtc_state); } - +#ifdef HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT ret = dm_atomic_get_state(state, &dm_state); if (ret) goto fail; - +#endif DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n", crtc->base.id); @@ -10437,11 +10509,11 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm, dm_old_crtc_state->stream)) { WARN_ON(dm_new_crtc_state->stream); - +#ifdef HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT ret = dm_atomic_get_state(state, &dm_state); if (ret) goto fail; - +#endif dm_new_crtc_state->stream = new_stream; dc_stream_retain(new_stream); @@ -10802,8 +10874,11 @@ static int dm_update_plane_state(struct dc *dc, bool *lock_and_validation_needed, bool *is_top_most_overlay) { - +#ifdef HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT struct dm_atomic_state *dm_state = NULL; +#else + struct dm_atomic_state *dm_state = to_dm_atomic_state(state); +#endif struct drm_crtc *new_plane_crtc, *old_plane_crtc; struct drm_crtc_state *old_crtc_state, *new_crtc_state; struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state; @@ -10851,12 +10926,13 @@ static int dm_update_plane_state(struct dc *dc, DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n", plane->base.id, old_plane_crtc->base.id); - +#ifdef HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT ret = dm_atomic_get_state(state, &dm_state); if (ret) return ret; if (!dc_state_remove_plane( +#endif dc, dm_old_crtc_state->stream, dm_old_plane_state->dc_state, @@ -10915,12 +10991,13 @@ static int dm_update_plane_state(struct dc *dc, goto out; } +#ifdef HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT ret = dm_atomic_get_state(state, &dm_state); if (ret) { dc_plane_state_release(dc_new_plane_state); goto out; } - +#endif /* * Any atomic check errors that occur after this will * not need a release. The plane state will be attached @@ -11274,7 +11351,11 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, struct drm_atomic_state *state) { struct amdgpu_device *adev = drm_to_adev(dev); +#ifdef HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT struct dm_atomic_state *dm_state = NULL; +#else + struct dm_atomic_state *dm_state = to_dm_atomic_state(state); +#endif struct dc *dc = adev->dm.dc; struct drm_connector *connector; struct drm_connector_state *old_con_state, *new_con_state; @@ -11402,6 +11483,11 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, } } +#ifndef HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT + dm_state->context = dc_create_state(dc); + ASSERT(dm_state->context); + dc_resource_state_copy_construct_current(dc, dm_state->context); +#endif /* * DC consults the zpos (layer_index in DC terminology) to determine the * hw plane on which to enable the hw cursor (see @@ -11632,11 +11718,13 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, * TODO: Remove this stall and drop DM state private objects. */ if (lock_and_validation_needed) { +#ifdef HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT ret = dm_atomic_get_state(state, &dm_state); if (ret) { drm_dbg_atomic(dev, "dm_atomic_get_state() failed\n"); goto fail; } +#endif ret = do_aquire_global_lock(dev, state); if (ret) { @@ -11680,6 +11768,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, goto fail; } } else { +#ifdef HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT /* * The commit is a fast update. Fast updates shouldn't change * the DC context, affect global validation, and can have their @@ -11720,6 +11809,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, break; } } +#endif } /* Store the overall update type for use later in atomic check. */ diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index b935387fb6c1e..3149be16860e9 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -405,6 +405,7 @@ struct amdgpu_display_manager { struct drm_device *ddev; u16 display_indexes_num; +#ifdef HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT /** * @atomic_obj: * @@ -414,6 +415,9 @@ struct amdgpu_display_manager { */ struct drm_private_obj atomic_obj; + struct drm_modeset_lock atomic_obj_lock; +#endif + /** * @dc_lock: * @@ -929,7 +933,11 @@ struct dm_crtc_state { #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base) struct dm_atomic_state { +#ifdef HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT struct drm_private_state base; +#else + struct drm_atomic_state base; +#endif struct dc_state *context; }; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_atomic_private_obj_init.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_atomic_private_obj_init.m4 new file mode 100644 index 0000000000000..10d794c4ace79 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_atomic_private_obj_init.m4 @@ -0,0 +1,31 @@ +dnl # +dnl # commit v4.20-rc4-945-gb962a12050a3 +dnl # drm/atomic: integrate modeset lock with private objects +dnl # +AC_DEFUN([AC_AMDGPU_DRM_ATOMIC_PRIVATE_OBJ_INIT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_atomic_private_obj_init(NULL, NULL, NULL, NULL); + ], [ + AC_DEFINE(HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT_P_P_P_P, 1, + [drm_atomic_private_obj_init() has p,p,p,p interface]) + AC_DEFINE(HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT, 1, + [drm_atomic_private_obj_init() is available]) + ], [ + dnl # + dnl # commit v4.12-rc7-1381-ga4370c777406 + dnl # drm/atomic: Make private objs proper objects + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_atomic_private_obj_init(NULL, NULL, NULL); + ], [ + AC_DEFINE(HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT, 1, + [drm_atomic_private_obj_init() is available]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_mode_config_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_mode_config_funcs.m4 new file mode 100644 index 0000000000000..fad6cdc4bd81d --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_mode_config_funcs.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # v4.1-rc2-37-g036ef5733ba4 +dnl # drm/atomic: Allow drivers to subclass drm_atomic_state, v3 +dnl # +AC_DEFUN([AC_AMDGPU_DRM_MODE_CONFIG_FUNCS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + struct drm_mode_config_funcs *funcs = NULL; + funcs->atomic_state_alloc(NULL); + ], [ + AC_DEFINE(HAVE_DRM_MODE_CONFIG_FUNCS_ATOMIC_STATE_ALLOC, 1, + [drm_mode_config_funcs->atomic_state_alloc() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index f7d18acaf3e1e..0c92dfcad558b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -101,6 +101,8 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_STRSCPY AC_AMDGPU_DRM_DP_MST_TOPOLOGY AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS + AC_AMDGPU_DRM_ATOMIC_PRIVATE_OBJ_INIT + AC_AMDGPU_DRM_MODE_CONFIG_FUNCS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 0ddac192fcac3fbd6f3c535048b601376db7fa95 Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Wed, 14 Aug 2019 12:52:25 +0800 Subject: [PATCH 0255/1868] drm/amdkcl: whether struct drm_atomic_state have async_update Change-Id: Ic9a0e4c28255e46fae3af23c0a12d0fbf6fccbf5 Signed-off-by: Yifan Zhang Reviewed-by: Feifei Xu Signed-off-by: Jack Gui --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index d58cdee22ea2c..77501d3eaabd5 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -11642,6 +11642,11 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, } } + /* Perform validation of MST topology in the state*/ + ret = drm_dp_mst_atomic_check(state); + if (ret) + goto fail; + if (state->legacy_cursor_update) { /* * This is a fast cursor update coming from the plane update From c75ee72e0feec4fa0fb9f73a027cf43b01284e8b Mon Sep 17 00:00:00 2001 From: Chengming Gui Date: Fri, 20 Sep 2019 09:27:01 +0800 Subject: [PATCH 0256/1868] drm/amdkcl: Test whether drm_connector_list_iter_begin is available Introduced by kernel v4.11-rc1~83^2~48^2~54 It's a squash of drm/amdkcl: refactor guard for drm_modeset_{lock,unlock}_all Signed-off-by: Flora Cui Acked-by: Rodrigo Siqueira drm/amdkcl: [4.14] fix drm_modeset_lock_all Signed-off-by: Evan Quan Reviewed-by: Junwei Zhang Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang drm/amdkcl: rework kcl for amdgpu_pmops_runtime_idle Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang drm/amdkcl: add kcl for amdgpu_pmops_runtime_idle Signed-off-by: Yifan Zhang drm/amdkcl: fix drm_connector_list_iter Signed-off-by: Flora Cui Change-Id: Iacbf79c46b7be3146e0b318c67769e10ff5b73a4 Signed-off-by: Chengming Gui Reviewed-by: Flora Cui Reviewed-by: Feifei Xu Signed-off-by: Jack Gui Signed-off-by: Yang Xiong --- .../gpu/drm/amd/amdgpu/amdgpu_connectors.c | 10 ++++ drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 10 +++- drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c | 32 +++++++++++++ drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 40 ++++++++++++++++ drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 40 ++++++++++++++++ drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 48 +++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 40 ++++++++++++++++ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 37 ++++++++++++-- .../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c | 8 ++++ .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 8 ++++ .../drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c | 16 +++++++ .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 7 +++ .../dkms/m4/drm-connector-list-iter-begin.m4 | 16 +++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 14 files changed, 308 insertions(+), 5 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-connector-list-iter-begin.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c index 4b0a9394f2682..96820a0e87631 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c @@ -1616,7 +1616,9 @@ amdgpu_connector_add(struct amdgpu_device *adev, { struct drm_device *dev = adev_to_drm(adev); struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif struct amdgpu_connector *amdgpu_connector; struct amdgpu_connector_atom_dig *amdgpu_dig_connector; struct drm_encoder *encoder; @@ -1631,12 +1633,18 @@ amdgpu_connector_add(struct amdgpu_device *adev, return; /* see if we already added it */ +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { +#else + drm_for_each_connector(connector, dev) { +#endif amdgpu_connector = to_amdgpu_connector(connector); if (amdgpu_connector->connector_id == connector_id) { amdgpu_connector->devices |= supported_device; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif return; } if (amdgpu_connector->ddc_bus && i2c_bus->valid) { @@ -1651,7 +1659,9 @@ amdgpu_connector_add(struct amdgpu_device *adev, } } } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif /* check if it's a dp bridge */ list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 159a3b1739d4e..37303d65eb9ee 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -634,13 +634,19 @@ void amdgpu_display_print_display_setup(struct drm_device *dev) struct amdgpu_connector *amdgpu_connector; struct drm_encoder *encoder; struct amdgpu_encoder *amdgpu_encoder; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif uint32_t devices; int i = 0; - drm_connector_list_iter_begin(dev, &iter); DRM_INFO("AMDGPU Display Connectors\n"); +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN + drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { +#else + drm_for_each_connector(connector, dev) { +#endif amdgpu_connector = to_amdgpu_connector(connector); DRM_INFO("Connector %d:\n", i); DRM_INFO(" %s\n", connector->name); @@ -704,7 +710,9 @@ void amdgpu_display_print_display_setup(struct drm_device *dev) } i++; } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif } bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c index 3aaeed2d35620..cd4bf5460252b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c @@ -36,14 +36,20 @@ amdgpu_link_encoder_connector(struct drm_device *dev) { struct amdgpu_device *adev = drm_to_adev(dev); struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif struct amdgpu_connector *amdgpu_connector; struct drm_encoder *encoder; struct amdgpu_encoder *amdgpu_encoder; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); /* walk the list and link encoders to connectors */ drm_for_each_connector_iter(connector, &iter) { +#else + drm_for_each_connector(connector, dev) { +#endif amdgpu_connector = to_amdgpu_connector(connector); list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { amdgpu_encoder = to_amdgpu_encoder(encoder); @@ -56,7 +62,9 @@ amdgpu_link_encoder_connector(struct drm_device *dev) } } } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif } void amdgpu_encoder_set_active_device(struct drm_encoder *encoder) @@ -64,10 +72,15 @@ void amdgpu_encoder_set_active_device(struct drm_encoder *encoder) struct drm_device *dev = encoder->dev; struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { +#else + + drm_for_each_connector(connector, dev) { +#endif if (connector->encoder == encoder) { struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); @@ -77,7 +90,9 @@ void amdgpu_encoder_set_active_device(struct drm_encoder *encoder) amdgpu_connector->devices, encoder->encoder_type); } } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif } struct drm_connector * @@ -86,18 +101,27 @@ amdgpu_get_connector_for_encoder(struct drm_encoder *encoder) struct drm_device *dev = encoder->dev; struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct drm_connector *connector, *found = NULL; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif struct amdgpu_connector *amdgpu_connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { + +#else + drm_for_each_connector(connector, dev) { +#endif amdgpu_connector = to_amdgpu_connector(connector); if (amdgpu_encoder->active_device & amdgpu_connector->devices) { found = connector; break; } } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif return found; } @@ -107,18 +131,26 @@ amdgpu_get_connector_for_encoder_init(struct drm_encoder *encoder) struct drm_device *dev = encoder->dev; struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct drm_connector *connector, *found = NULL; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif struct amdgpu_connector *amdgpu_connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { +#else + drm_for_each_connector(connector, dev) { +#endif amdgpu_connector = to_amdgpu_connector(connector); if (amdgpu_encoder->devices & amdgpu_connector->devices) { found = connector; break; } } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif return found; } diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index 435cf5e4ec8f2..c87d4fbe3f46b 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -334,11 +334,17 @@ static void dce_v10_0_hpd_init(struct amdgpu_device *adev) { struct drm_device *dev = adev_to_drm(adev); struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif u32 tmp; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { +#else + drm_for_each_connector(connector, dev) { +#endif struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) @@ -375,7 +381,9 @@ static void dce_v10_0_hpd_init(struct amdgpu_device *adev) amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif } /** @@ -390,11 +398,17 @@ static void dce_v10_0_hpd_fini(struct amdgpu_device *adev) { struct drm_device *dev = adev_to_drm(adev); struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif u32 tmp; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { +#else + drm_for_each_connector(connector, dev) { +#endif struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) @@ -407,7 +421,9 @@ static void dce_v10_0_hpd_fini(struct amdgpu_device *adev) amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif } static u32 dce_v10_0_hpd_get_gpio_reg(struct amdgpu_device *adev) @@ -1235,7 +1251,9 @@ static void dce_v10_0_audio_write_latency_fields(struct drm_encoder *encoder, struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif struct amdgpu_connector *amdgpu_connector = NULL; u32 tmp; int interlace = 0; @@ -1243,14 +1261,20 @@ static void dce_v10_0_audio_write_latency_fields(struct drm_encoder *encoder, if (!dig || !dig->afmt || !dig->afmt->pin) return; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { +#else + drm_for_each_connector(connector, dev) { +#endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); break; } } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif if (!amdgpu_connector) { DRM_ERROR("Couldn't find encoder's connector\n"); @@ -1281,7 +1305,9 @@ static void dce_v10_0_audio_write_speaker_allocation(struct drm_encoder *encoder struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif struct amdgpu_connector *amdgpu_connector = NULL; u32 tmp; u8 *sadb = NULL; @@ -1290,14 +1316,20 @@ static void dce_v10_0_audio_write_speaker_allocation(struct drm_encoder *encoder if (!dig || !dig->afmt || !dig->afmt->pin) return; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { +#else + drm_for_each_connector(connector, dev) { +#endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); break; } } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif if (!amdgpu_connector) { DRM_ERROR("Couldn't find encoder's connector\n"); @@ -1337,7 +1369,9 @@ static void dce_v10_0_audio_write_sad_regs(struct drm_encoder *encoder) struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif struct amdgpu_connector *amdgpu_connector = NULL; struct cea_sad *sads; int i, sad_count; @@ -1360,14 +1394,20 @@ static void dce_v10_0_audio_write_sad_regs(struct drm_encoder *encoder) if (!dig || !dig->afmt || !dig->afmt->pin) return; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { +#else + drm_for_each_connector(connector, dev) { +#endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); break; } } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif if (!amdgpu_connector) { DRM_ERROR("Couldn't find encoder's connector\n"); diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index 7490ade2335fb..68b24df8aa3f9 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -358,11 +358,17 @@ static void dce_v11_0_hpd_init(struct amdgpu_device *adev) { struct drm_device *dev = adev_to_drm(adev); struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif u32 tmp; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { +#else + drm_for_each_connector(connector, dev) { +#endif struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) @@ -398,7 +404,9 @@ static void dce_v11_0_hpd_init(struct amdgpu_device *adev) dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif } /** @@ -413,11 +421,17 @@ static void dce_v11_0_hpd_fini(struct amdgpu_device *adev) { struct drm_device *dev = adev_to_drm(adev); struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif u32 tmp; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { +#else + drm_for_each_connector(connector, dev) { +#endif struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) @@ -429,7 +443,9 @@ static void dce_v11_0_hpd_fini(struct amdgpu_device *adev) amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif } static u32 dce_v11_0_hpd_get_gpio_reg(struct amdgpu_device *adev) @@ -1267,7 +1283,9 @@ static void dce_v11_0_audio_write_latency_fields(struct drm_encoder *encoder, struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif struct amdgpu_connector *amdgpu_connector = NULL; u32 tmp; int interlace = 0; @@ -1275,14 +1293,20 @@ static void dce_v11_0_audio_write_latency_fields(struct drm_encoder *encoder, if (!dig || !dig->afmt || !dig->afmt->pin) return; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { +#else + drm_for_each_connector(connector, dev) { +#endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); break; } } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif if (!amdgpu_connector) { DRM_ERROR("Couldn't find encoder's connector\n"); @@ -1313,7 +1337,9 @@ static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif struct amdgpu_connector *amdgpu_connector = NULL; u32 tmp; u8 *sadb = NULL; @@ -1322,14 +1348,20 @@ static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder if (!dig || !dig->afmt || !dig->afmt->pin) return; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { +#else + drm_for_each_connector(connector, dev) { +#endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); break; } } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif if (!amdgpu_connector) { DRM_ERROR("Couldn't find encoder's connector\n"); @@ -1369,7 +1401,9 @@ static void dce_v11_0_audio_write_sad_regs(struct drm_encoder *encoder) struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif struct amdgpu_connector *amdgpu_connector = NULL; struct cea_sad *sads; int i, sad_count; @@ -1392,14 +1426,20 @@ static void dce_v11_0_audio_write_sad_regs(struct drm_encoder *encoder) if (!dig || !dig->afmt || !dig->afmt->pin) return; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { +#else + drm_for_each_connector(connector, dev) { +#endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); break; } } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif if (!amdgpu_connector) { DRM_ERROR("Couldn't find encoder's connector\n"); diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c index 7957c071b8e67..19a4e46242564 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c @@ -305,11 +305,17 @@ static void dce_v6_0_hpd_init(struct amdgpu_device *adev) { struct drm_device *dev = adev_to_drm(adev); struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif u32 tmp; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { +#else + drm_for_each_connector(connector, dev) { +#endif struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) @@ -336,7 +342,9 @@ static void dce_v6_0_hpd_init(struct amdgpu_device *adev) dce_v6_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif } /** @@ -351,11 +359,17 @@ static void dce_v6_0_hpd_fini(struct amdgpu_device *adev) { struct drm_device *dev = adev_to_drm(adev); struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif u32 tmp; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { +#else + drm_for_each_connector(connector, dev) { +#endif struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) @@ -367,7 +381,9 @@ static void dce_v6_0_hpd_fini(struct amdgpu_device *adev) amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif } static u32 dce_v6_0_hpd_get_gpio_reg(struct amdgpu_device *adev) @@ -1158,19 +1174,27 @@ static void dce_v6_0_audio_write_latency_fields(struct drm_encoder *encoder, struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif struct amdgpu_connector *amdgpu_connector = NULL; int interlace = 0; u32 tmp; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { +#else + drm_for_each_connector(connector, dev) { +#endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); break; } } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif if (!amdgpu_connector) { DRM_ERROR("Couldn't find encoder's connector\n"); @@ -1202,20 +1226,28 @@ static void dce_v6_0_audio_write_speaker_allocation(struct drm_encoder *encoder) struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif struct amdgpu_connector *amdgpu_connector = NULL; u8 *sadb = NULL; int sad_count; u32 tmp; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { +#else + drm_for_each_connector(connector, dev) { +#endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); break; } } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif if (!amdgpu_connector) { DRM_ERROR("Couldn't find encoder's connector\n"); @@ -1263,7 +1295,9 @@ static void dce_v6_0_audio_write_sad_regs(struct drm_encoder *encoder) struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif struct amdgpu_connector *amdgpu_connector = NULL; struct cea_sad *sads; int i, sad_count; @@ -1283,14 +1317,20 @@ static void dce_v6_0_audio_write_sad_regs(struct drm_encoder *encoder) { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, }; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { +#else + drm_for_each_connector(connector, dev) { +#endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); break; } } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif if (!amdgpu_connector) { DRM_ERROR("Couldn't find encoder's connector\n"); @@ -1679,7 +1719,9 @@ static void dce_v6_0_afmt_setmode(struct drm_encoder *encoder, struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif struct amdgpu_connector *amdgpu_connector = NULL; int em = amdgpu_atombios_encoder_get_encoder_mode(encoder); int bpc = 8; @@ -1687,14 +1729,20 @@ static void dce_v6_0_afmt_setmode(struct drm_encoder *encoder, if (!dig || !dig->afmt) return; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { +#else + drm_for_each_connector(connector, dev) { +#endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); break; } } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif if (!amdgpu_connector) { DRM_ERROR("Couldn't find encoder's connector\n"); diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index 5803e0a0608cf..218a03570d63c 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -296,11 +296,17 @@ static void dce_v8_0_hpd_init(struct amdgpu_device *adev) { struct drm_device *dev = adev_to_drm(adev); struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif u32 tmp; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { +#else + drm_for_each_connector(connector, dev) { +#endif struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) @@ -327,7 +333,9 @@ static void dce_v8_0_hpd_init(struct amdgpu_device *adev) dce_v8_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif } /** @@ -342,11 +350,17 @@ static void dce_v8_0_hpd_fini(struct amdgpu_device *adev) { struct drm_device *dev = adev_to_drm(adev); struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif u32 tmp; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { +#else + drm_for_each_connector(connector, dev) { +#endif struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) @@ -358,7 +372,9 @@ static void dce_v8_0_hpd_fini(struct amdgpu_device *adev) amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif } static u32 dce_v8_0_hpd_get_gpio_reg(struct amdgpu_device *adev) @@ -1190,7 +1206,9 @@ static void dce_v8_0_audio_write_latency_fields(struct drm_encoder *encoder, struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif struct amdgpu_connector *amdgpu_connector = NULL; u32 tmp = 0, offset; @@ -1199,14 +1217,20 @@ static void dce_v8_0_audio_write_latency_fields(struct drm_encoder *encoder, offset = dig->afmt->pin->offset; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { +#else + drm_for_each_connector(connector, dev) { +#endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); break; } } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif if (!amdgpu_connector) { DRM_ERROR("Couldn't find encoder's connector\n"); @@ -1251,7 +1275,9 @@ static void dce_v8_0_audio_write_speaker_allocation(struct drm_encoder *encoder) struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif struct amdgpu_connector *amdgpu_connector = NULL; u32 offset, tmp; u8 *sadb = NULL; @@ -1262,14 +1288,20 @@ static void dce_v8_0_audio_write_speaker_allocation(struct drm_encoder *encoder) offset = dig->afmt->pin->offset; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { +#else + drm_for_each_connector(connector, dev) { +#endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); break; } } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif if (!amdgpu_connector) { DRM_ERROR("Couldn't find encoder's connector\n"); @@ -1305,7 +1337,9 @@ static void dce_v8_0_audio_write_sad_regs(struct drm_encoder *encoder) struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; u32 offset; struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif struct amdgpu_connector *amdgpu_connector = NULL; struct cea_sad *sads; int i, sad_count; @@ -1330,14 +1364,20 @@ static void dce_v8_0_audio_write_sad_regs(struct drm_encoder *encoder) offset = dig->afmt->pin->offset; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { +#else + drm_for_each_connector(connector, dev) { +#endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); break; } } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif if (!amdgpu_connector) { DRM_ERROR("Couldn't find encoder's connector\n"); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 77501d3eaabd5..4dac3e5d4a553 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1008,7 +1008,9 @@ static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port, struct drm_device *dev = dev_get_drvdata(kdev); struct amdgpu_device *adev = drm_to_adev(dev); struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter conn_iter; +#endif struct amdgpu_dm_connector *aconnector; int ret = 0; @@ -1016,9 +1018,12 @@ static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port, mutex_lock(&adev->dm.audio_lock); +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &conn_iter); drm_for_each_connector_iter(connector, &conn_iter) { - +#else + drm_for_each_connector(connector, dev) { +#endif if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) continue; @@ -1032,7 +1037,9 @@ static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port, break; } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&conn_iter); +#endif mutex_unlock(&adev->dm.audio_lock); @@ -2516,12 +2523,17 @@ static int detect_mst_link_for_all_connectors(struct drm_device *dev) { struct amdgpu_dm_connector *aconnector; struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif int ret = 0; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { - +#else + drm_for_each_connector(connector, dev) { +#endif if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) continue; @@ -2543,7 +2555,9 @@ static int detect_mst_link_for_all_connectors(struct drm_device *dev) } } } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif return ret; } @@ -2648,12 +2662,17 @@ static void s3_handle_mst(struct drm_device *dev, bool suspend) { struct amdgpu_dm_connector *aconnector; struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif struct drm_dp_mst_topology_mgr *mgr; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { - +#else + drm_for_each_connector(connector, dev) { +#endif if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) continue; @@ -2683,7 +2702,10 @@ static void s3_handle_mst(struct drm_device *dev, bool suspend) resume_mst_branch_status(mgr); } } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif + } static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev) @@ -3080,7 +3102,9 @@ static int dm_resume(void *handle) struct amdgpu_display_manager *dm = &adev->dm; struct amdgpu_dm_connector *aconnector; struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif struct drm_crtc *crtc; struct drm_crtc_state *new_crtc_state; struct dm_crtc_state *dm_new_crtc_state; @@ -3195,9 +3219,12 @@ static int dm_resume(void *handle) s3_handle_mst(ddev, false); /* Do detection*/ +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(ddev, &iter); drm_for_each_connector_iter(connector, &iter) { - +#else + drm_for_each_connector(connector, ddev) { +#endif if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) continue; @@ -3235,7 +3262,9 @@ static int dm_resume(void *handle) amdgpu_dm_update_connector_after_detect(aconnector); mutex_unlock(&aconnector->hpd_lock); } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif /* Force mode set in atomic commit */ for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) { diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c index 741e2526ec127..c043cf62e62ff 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c @@ -323,10 +323,16 @@ int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name) dm_is_crc_source_dprx(cur_crc_src))) { struct amdgpu_dm_connector *aconn = NULL; struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter conn_iter; +#endif +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(crtc->dev, &conn_iter); drm_for_each_connector_iter(connector, &conn_iter) { +#else + drm_for_each_connector(connector, crtc->dev) { +#endif if (!connector->state || connector->state->crtc != crtc) continue; @@ -336,7 +342,9 @@ int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name) aconn = to_amdgpu_dm_connector(connector); break; } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&conn_iter); +#endif if (!aconn) { DRM_DEBUG_DRIVER("No amd connector matching CRTC-%d\n", crtc->index); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index 6ddba57c50d62..9f1f498d17d38 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -3767,11 +3767,17 @@ static int mst_topo_show(struct seq_file *m, void *unused) struct amdgpu_device *adev = (struct amdgpu_device *)m->private; struct drm_device *dev = adev_to_drm(adev); struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter conn_iter; +#endif struct amdgpu_dm_connector *aconnector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &conn_iter); drm_for_each_connector_iter(connector, &conn_iter) { +#else + drm_for_each_connector(connector, dev) { +#endif if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) continue; @@ -3784,7 +3790,9 @@ static int mst_topo_show(struct seq_file *m, void *unused) seq_printf(m, "\nMST topology for connector %d\n", aconnector->connector_id); drm_dp_mst_dump_topology(m, &aconnector->mst_mgr); } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&conn_iter); +#endif return 0; } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c index 3390f0d8420a0..c276e0bbc6b00 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c @@ -893,10 +893,16 @@ void amdgpu_dm_hpd_init(struct amdgpu_device *adev) { struct drm_device *dev = adev_to_drm(adev); struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { +#else + drm_for_each_connector(connector, dev) { +#endif struct amdgpu_dm_connector *amdgpu_dm_connector; const struct dc_link *dc_link; @@ -919,7 +925,9 @@ void amdgpu_dm_hpd_init(struct amdgpu_device *adev) true); } } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif } /** @@ -934,10 +942,16 @@ void amdgpu_dm_hpd_fini(struct amdgpu_device *adev) { struct drm_device *dev = adev_to_drm(adev); struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { +#else + drm_for_each_connector(connector, dev) { +#endif struct amdgpu_dm_connector *amdgpu_dm_connector; const struct dc_link *dc_link; @@ -959,5 +973,7 @@ void amdgpu_dm_hpd_fini(struct amdgpu_device *adev) false); } } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 1f3e7dc87b0e3..58107033a6a87 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -768,11 +768,18 @@ static void dm_dp_mst_register_connector(struct drm_connector *connector) struct drm_device *dev = connector->dev; struct amdgpu_device *adev = dev->dev_private; +#ifndef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN + drm_modeset_lock_all(dev); +#endif if (adev->mode_info.rfbdev) drm_fb_helper_add_one_connector(&adev->mode_info.rfbdev->helper, connector); else DRM_ERROR("adev->mode_info.rfbdev is NULL\n"); +#ifndef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN + drm_modeset_unlock_all(dev); +#endif + drm_connector_register(connector); } #endif diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-list-iter-begin.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-list-iter-begin.m4 new file mode 100644 index 0000000000000..b9b18381ae244 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector-list-iter-begin.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit 613051dac40da1751ab269572766d3348d45a197 +dnl # drm: locking&new iterators for connector_list +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_LIST_ITER_BEGIN], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + drm_connector_list_iter_begin(NULL, NULL); + ],[ + AC_DEFINE(HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN, 1, + [drm_connector_list_iter_begin() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 0c92dfcad558b..921c2cfd6de11 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -103,6 +103,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS AC_AMDGPU_DRM_ATOMIC_PRIVATE_OBJ_INIT AC_AMDGPU_DRM_MODE_CONFIG_FUNCS + AC_AMDGPU_DRM_CONNECTOR_LIST_ITER_BEGIN AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 75ca5766264ca4c390a59ebb93a7bfdea7d2e524 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 16 Jun 2020 10:55:00 +0800 Subject: [PATCH 0257/1868] drm/amdkcl: add test for drm_plane_helper_funcs->atomic_async_check the 2 callbacks are introduced in commit v4.12-rc7-1335-gfef9df8b5945("drm/atomic: initial support for asynchronous plane update") It's a squash of drm/amdkcl: [4.14] add kcl for "add fast path for cursor plane updates" Reviewed-by: Prike Liang Signed-off-by: Tianci Yin Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang Signed-off-by: Flora Cui Reviewed-by: Yang Xiong Change-Id: Iec3f145247132537e016e6895ade88eedbfb0ec2 Signed-off-by: Ma Jun --- .../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 4 ++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../dkms/m4/struct_drm_plane_helper_funcs.m4 | 18 ++++++++++++++++++ 3 files changed, 23 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/struct_drm_plane_helper_funcs.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index aba6b2a3043bc..60b255fa5c9d1 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -1265,6 +1265,7 @@ static int amdgpu_dm_plane_atomic_check(struct drm_plane *plane, return -EINVAL; } +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_ASYNC_CHECK static int amdgpu_dm_plane_atomic_async_check(struct drm_plane *plane, struct drm_atomic_state *state) { @@ -1285,6 +1286,7 @@ static int amdgpu_dm_plane_atomic_async_check(struct drm_plane *plane, return 0; } +#endif int amdgpu_dm_plane_get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc, struct dc_cursor_position *position) @@ -1428,8 +1430,10 @@ static const struct drm_plane_helper_funcs dm_plane_helper_funcs = { .prepare_fb = amdgpu_dm_plane_helper_prepare_fb, .cleanup_fb = amdgpu_dm_plane_helper_cleanup_fb, .atomic_check = amdgpu_dm_plane_atomic_check, +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_ASYNC_CHECK .atomic_async_check = amdgpu_dm_plane_atomic_async_check, .atomic_async_update = amdgpu_dm_plane_atomic_async_update +#endif }; static void amdgpu_dm_plane_drm_plane_reset(struct drm_plane *plane) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 921c2cfd6de11..8e1c43d55b35c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -104,6 +104,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_ATOMIC_PRIVATE_OBJ_INIT AC_AMDGPU_DRM_MODE_CONFIG_FUNCS AC_AMDGPU_DRM_CONNECTOR_LIST_ITER_BEGIN + AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_plane_helper_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_plane_helper_funcs.m4 new file mode 100644 index 0000000000000..4dd6e4db74ff6 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_plane_helper_funcs.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # v4.12-rc7-1335-gfef9df8b5945 +dnl # drm/atomic: initial support for asynchronous plane update +dnl # +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_plane_helper_funcs *funcs = NULL; + funcs->atomic_async_check(NULL, NULL); + funcs->atomic_async_update(NULL, NULL); + ], [ + AC_DEFINE(HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_ASYNC_CHECK, 1, + [drm_plane_helper_funcs->atomic_async_check() is available]) + ]) + ]) +]) From 6ed6e6a995ca3b6162d8f0add0ee7997ad16d22f Mon Sep 17 00:00:00 2001 From: "Stanley.Yang" Date: Fri, 27 Dec 2019 14:29:23 +0800 Subject: [PATCH 0258/1868] drm/amdkcl: Test whether drm_dp_mst_atomic_check() is available Change-Id: I6d5801df6e80e208e07e3806a031b8672d55e4d1 Signed-off-by: Stanley.Yang Reviewed-by: Flora Cui Signed-off-by: Yifan Zhang --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++++ .../amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 4 ++++ .../drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 26 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 4dac3e5d4a553..041e547fb6565 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -11671,10 +11671,12 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, } } +#if defined(HAVE_STRUCT_NAME_CB_NAME_2ARGS) && defined(HAVE_DRM_DP_MST_ATOMIC_CHECK) /* Perform validation of MST topology in the state*/ ret = drm_dp_mst_atomic_check(state); if (ret) goto fail; +#endif if (state->legacy_cursor_update) { /* @@ -11789,11 +11791,13 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, * dc_validate_global_state(), or there is a chance * to get stuck in an infinite loop and hang eventually. */ +#ifdef HAVE_DRM_DP_MST_ATOMIC_CHECK ret = drm_dp_mst_atomic_check(state); if (ret) { drm_dbg_atomic(dev, "drm_dp_mst_atomic_check() failed\n"); goto fail; } +#endif status = dc_validate_global_state(dc, dm_state->context, true); if (status != DC_OK) { drm_dbg_atomic(dev, "DC global validation failure: %s (%d)", diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 58107033a6a87..d3e455b58a9aa 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -832,6 +832,8 @@ int dm_mst_get_pbn_divider(struct dc_link *link) dc_link_get_link_cap(link)) / (8 * 1000 * 54); } +#if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT) +#if defined(CONFIG_DRM_AMD_DC_DCN1_0) && defined(HAVE_DRM_DP_MST_ATOMIC_CHECK) struct dsc_mst_fairness_params { struct dc_crtc_timing *timing; struct dc_sink *sink; @@ -1658,6 +1660,7 @@ static bool is_dsc_common_config_possible(struct dc_stream_state *stream, return bw_range->max_target_bpp_x16 && bw_range->min_target_bpp_x16; } #endif +#endif /* HAVE_DRM_DP_MST_ATOMIC_CHECK */ #if defined(CONFIG_DRM_AMD_DC_FP) static bool dp_get_link_current_set_bw(struct drm_dp_aux *aux, uint32_t *cur_link_bw) @@ -1827,3 +1830,4 @@ enum dc_status dm_dp_mst_is_port_support_mode( #endif return DC_OK; } +#endif diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 new file mode 100644 index 0000000000000..dc4167e33a865 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit eceae147246749c6dbaeefda802b30f804a3c54c +dnl # drm/dp_mst: Start tracking per-port VCPI allocations +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_ATOMIC_CHECK], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + int ret; + ret = drm_dp_mst_atomic_check(NULL); + ], [drm_dp_mst_atomic_check], [drivers/gpu/drm/drm_dp_mst_topology.c], [ + AC_DEFINE(HAVE_DRM_DP_MST_ATOMIC_CHECK, 1, + [drm_dp_mst_atomic_check() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 8e1c43d55b35c..c4a003b852428 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -105,6 +105,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_MODE_CONFIG_FUNCS AC_AMDGPU_DRM_CONNECTOR_LIST_ITER_BEGIN AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS + AC_AMDGPU_DRM_DP_MST_ATOMIC_CHECK AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 1655468edb7f29e6c73ac63575c2fbe1a6fa1218 Mon Sep 17 00:00:00 2001 From: "Stanley.Yang" Date: Mon, 6 Jan 2020 14:59:32 +0800 Subject: [PATCH 0259/1868] drm/amdkcl: Test whether drm_dp_calc_pbn_mode() wants three arguments v2: drm/amdkcl: Test whether mul_u32_u32 is available v3: drm/amdkcl: move kcl copy for drm_dp_mst_helper into backport part the macros definition should be in backport to warn amdkcl to NOT include it. It is not necessary to wrap a mul_u32_u32() funcion, because function mul_u32_u32() is introdued into kernel before function drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc). Signed-off-by: Stanley.Yang Signed-off-by: Yifan Zhang Signed-off-by: Stanley.Yang Reviewed-by: Flora Cui Reviewed-by: Shiwu Zhang Signed-off-by: Flora Cui --- .../gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../backport/kcl_drm_dp_mst_helper_backport.h | 14 ++++++++++++++ 3 files changed, 31 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 new file mode 100644 index 0000000000000..d168a591bcd23 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit 9a7c0da823fd4e65098bd466a996503cc8309c0e +dnl # drm/dp_mst: Add PBN calculation for DSC modes +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_CALC_PBN_MODE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_dp_calc_pbn_mode(0, 0, 0); + ], [ + AC_DEFINE(HAVE_DRM_DP_CALC_PBN_MODE_3ARGS, 1, + [drm_dp_calc_pbn_mode() wants 3args]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index c4a003b852428..1826ae1e0ef6e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -62,6 +62,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_ATTACH_ENCODER AC_AMDGPU_DRM_CONNECTOR_SET_PATH_PROPERTY AC_AMDGPU_DRM_CONNECTOR_INIT_WITH_DDC + AC_AMDGPU_DRM_DP_CALC_PBN_MODE AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS AC_AMDGPU_DRM_DP_CEC_CORRELATION_FUNCTIONS AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_RESUME diff --git a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h index 85fa328d0aa09..183e49a5ba766 100644 --- a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h +++ b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h @@ -24,6 +24,20 @@ #include +/* Copied from drivers/gpu/drm/drm_dp_mst_topology.c and modified for KCL */ +#if !defined(HAVE_DRM_DP_CALC_PBN_MODE_3ARGS) +static inline +int _kcl_drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc) +{ + if (dsc) + return DIV_ROUND_UP_ULL(mul_u32_u32(clock * (bpp / 16), 64 * 1006), + 8 * 54 * 1000 * 1000); + + return drm_dp_calc_pbn_mode(clock, bpp); +} +#define drm_dp_calc_pbn_mode _kcl_drm_dp_calc_pbn_mode +#endif + #if defined(HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS) #if !defined(HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS_5ARGS) static inline From a318ed5788654e5c0e7a268bb17a9a12bd6a1cc6 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 21 Jan 2020 15:22:52 +0800 Subject: [PATCH 0260/1868] drm/amdkcl: refactor test for drm_connector_helper_funcs->atomic_check it is a squash of: commit ae74c678762b314212c82c0afcbc7b06f18f3c15 Author: Slava Grigorev Date: Thu Feb 13 12:43:57 2020 -0500 drm/amdkcl: properly define the root of the build directories Change-Id: I5064df48df8b742be9175b01ba9340378d674103 Signed-off-by: Slava Grigorev Change-Id: I32b0308637042a254d34dc5b1a7d0b01fee0190c Signed-off-by: Flora Cui Reviewed-by: Feifei Xu Signed-off-by: Yifan Zhang Signed-off-by: Slava Grigorev Signed-off-by: Ma Jun --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 12 +++++++----- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 2 ++ .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 4 ++++ .../amd/dkms/m4/drm-connector-helper-funcs.m4 | 18 ++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 5 files changed, 32 insertions(+), 5 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-connector-helper-funcs.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 041e547fb6565..29b267edb7aa1 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -6342,7 +6342,6 @@ static void dm_enable_per_frame_crtc_master_sync(struct dc_state *context) for (i = 0; i < context->stream_count ; i++) { stream = context->streams[i]; - if (!stream) continue; @@ -6413,7 +6412,6 @@ get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector, return NULL; } } - highest_refresh = drm_mode_vrefresh(m_pref); /* @@ -7023,7 +7021,6 @@ static void amdgpu_dm_connector_unregister(struct drm_connector *connector) drm_dp_aux_unregister(&amdgpu_dm_connector->dm_dp_aux.aux); } - static void amdgpu_dm_connector_destroy(struct drm_connector *connector) { struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); @@ -7057,7 +7054,6 @@ static void amdgpu_dm_connector_destroy(struct drm_connector *connector) kfree(aconnector->i2c); } kfree(aconnector->dm_dp_aux.aux.name); - kfree(connector); } @@ -7079,8 +7075,10 @@ void amdgpu_dm_connector_funcs_reset(struct drm_connector *connector) state->underscan_hborder = 0; state->underscan_vborder = 0; state->base.max_requested_bpc = 8; +#if defined(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE) state->vcpi_slots = 0; state->pbn = 0; +#endif if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) { if (amdgpu_dm_abm_level <= 0) @@ -7113,8 +7111,10 @@ amdgpu_dm_connector_atomic_duplicate_state(struct drm_connector *connector) new_state->underscan_enable = state->underscan_enable; new_state->underscan_hborder = state->underscan_hborder; new_state->underscan_vborder = state->underscan_vborder; +#if defined(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE) new_state->vcpi_slots = state->vcpi_slots; new_state->pbn = state->pbn; +#endif return &new_state->base; } @@ -7586,6 +7586,7 @@ static void dm_encoder_helper_disable(struct drm_encoder *encoder) } +#if defined(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE) int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth) { switch (display_color_depth) { @@ -7606,6 +7607,7 @@ int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth) } return 0; } +#endif static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, struct drm_crtc_state *crtc_state, @@ -11671,7 +11673,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, } } -#if defined(HAVE_STRUCT_NAME_CB_NAME_2ARGS) && defined(HAVE_DRM_DP_MST_ATOMIC_CHECK) +#if defined(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE) && defined(HAVE_DRM_DP_MST_ATOMIC_CHECK) /* Perform validation of MST topology in the state*/ ret = drm_dp_mst_atomic_check(state); if (ret) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index 3149be16860e9..834b7f4c7e31d 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -954,8 +954,10 @@ struct dm_connector_state { bool freesync_capable; bool update_hdcp; uint8_t abm_level; +#if defined(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE) int vcpi_slots; uint64_t pbn; +#endif }; #define to_dm_connector_state(x)\ diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index d3e455b58a9aa..5931fb4e49469 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -514,6 +514,7 @@ dm_dp_mst_detect(struct drm_connector *connector, return connection_status; } +#if defined(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE) static int dm_dp_mst_atomic_check(struct drm_connector *connector, struct drm_atomic_state *state) { @@ -523,13 +524,16 @@ static int dm_dp_mst_atomic_check(struct drm_connector *connector, return drm_dp_atomic_release_time_slots(state, mst_mgr, mst_port); } +#endif static const struct drm_connector_helper_funcs dm_dp_mst_connector_helper_funcs = { .get_modes = dm_dp_mst_get_modes, .mode_valid = amdgpu_dm_connector_mode_valid, .atomic_best_encoder = dm_mst_atomic_best_encoder, .detect_ctx = dm_dp_mst_detect, +#if defined(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE) .atomic_check = dm_dp_mst_atomic_check, +#endif }; static void amdgpu_dm_encoder_destroy(struct drm_encoder *encoder) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-helper-funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-helper-funcs.m4 new file mode 100644 index 0000000000000..148d0cc472804 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector-helper-funcs.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit v5.2-rc2-529-g6f3b62781bbd +dnl # drm: Convert connector_helper_funcs->atomic_check to accept drm_atomic_state +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + struct drm_connector_helper_funcs *p = NULL; + p->atomic_check(NULL, (struct drm_atomic_state*)NULL); + ], [ + AC_DEFINE(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE, 1, + [drm_connector_helper_funcs->atomic_check() wants struct drm_atomic_state arg]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 1826ae1e0ef6e..c6aee6618f472 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -107,6 +107,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_LIST_ITER_BEGIN AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS AC_AMDGPU_DRM_DP_MST_ATOMIC_CHECK + AC_AMDGPU_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From da3326bd4eb1ab2a376b26a55cb16adc1d31ceb0 Mon Sep 17 00:00:00 2001 From: "Stanley.Yang" Date: Wed, 8 Jan 2020 14:23:18 +0800 Subject: [PATCH 0261/1868] drm/amdkcl: Test whether drm_dp_mst_atomic_enable_dsc() is available Change-Id: If8f9e171797152ab6a10c4bc05b1e8cf014f0d98 Signed-off-by: Stanley.Yang Acked-by: Hawking Zhang Reviewed-by: Flora Cui Signed-off-by: Yifan Zhang --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 ++++++++ .../amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 25 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 29b267edb7aa1..df290988e7b62 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -7668,6 +7668,8 @@ const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = { .atomic_check = dm_encoder_helper_atomic_check }; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT +#if defined(HAVE_DRM_DP_MST_ATOMIC_ENABLE_DSC) static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state, struct dc_state *dc_state, struct dsc_mst_fairness_vars *vars) @@ -7744,6 +7746,8 @@ static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state, } return 0; } +#endif +#endif static int to_drm_connector_type(enum signal_type st) { @@ -11781,11 +11785,13 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, } #endif +#if defined(HAVE_DRM_DP_MST_ATOMIC_ENABLE_DSC) ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars); if (ret) { drm_dbg_atomic(dev, "dm_update_mst_vcpi_slots_for_dsc() failed\n"); goto fail; } +#endif /* * Perform validation of MST topology in the state: @@ -11794,11 +11800,13 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, * to get stuck in an infinite loop and hang eventually. */ #ifdef HAVE_DRM_DP_MST_ATOMIC_CHECK +#if defined(HAVE_DRM_DP_MST_ATOMIC_ENABLE_DSC) ret = drm_dp_mst_atomic_check(state); if (ret) { drm_dbg_atomic(dev, "drm_dp_mst_atomic_check() failed\n"); goto fail; } +#endif #endif status = dc_validate_global_state(dc, dm_state->context, true); if (status != DC_OK) { diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 new file mode 100644 index 0000000000000..17422c2217f46 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit 0529a1d385b9ce6cd7498d180f720eeb3f755980 +dnl # drm/dp_mst: Add DSC enablement helpers to DRM +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_ATOMIC_ENABLE_DSC], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_dp_mst_atomic_enable_dsc(NULL, NULL, 0, 0, false); + ], [drm_dp_mst_atomic_enable_dsc], [drivers/gpu/drm/drm_dp_mst_topology.c], [ + AC_DEFINE(HAVE_DRM_DP_MST_ATOMIC_ENABLE_DSC, 1, + [drm_dp_mst_atomic_enable_dsc() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index c6aee6618f472..a10280059cdc8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -107,6 +107,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_LIST_ITER_BEGIN AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS AC_AMDGPU_DRM_DP_MST_ATOMIC_CHECK + AC_AMDGPU_DRM_DP_MST_ATOMIC_ENABLE_DSC AC_AMDGPU_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK AC_KERNEL_WAIT From b7114c624fb2d055c0f8c8479d18fd4e1210808c Mon Sep 17 00:00:00 2001 From: Evan Quan Date: Fri, 12 May 2017 09:35:40 +0800 Subject: [PATCH 0262/1868] drm/amdkcl: [4.11] fix for drm_dp_mst_topology_mgr_init This is a squash of: drm/amdkcl: test drm_dp_mst_topology_mgr_init() the prototype change introduced in v4.10-rc3-517-g7b0a89a6db9a Change-Id: I288af7fc96335e1ae8d1aaf768f4f3f7bb6a8810 Signed-off-by: Evan Quan Reviewed-by: Junwei Zhang Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang Signed-off-by: Flora Cui Reviewed-by: Yang Xiong --- .../amd/dkms/m4/drm_dp_mst_topology_mgr_init.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 2 files changed, 18 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr_init.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr_init.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr_init.m4 new file mode 100644 index 0000000000000..98d2982594b7c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr_init.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # v4.10-rc3-517-g7b0a89a6db9a +dnl # drm/dp: Store drm_device in MST topology manager +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_INIT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_dp_mst_topology_mgr_init(NULL, (struct drm_device *)NULL, NULL, 0, 0, 0, 0, 0); + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_TOPOLOGY_MGR_INIT_MAX_LANE_COUNT, 1, + [drm_dp_mst_topology_mgr_init() has max_lane_count and max_link_rate]) + + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index a10280059cdc8..f5b4eebd3a4e4 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -109,6 +109,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_ATOMIC_CHECK AC_AMDGPU_DRM_DP_MST_ATOMIC_ENABLE_DSC AC_AMDGPU_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK + AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_INIT AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 1022ffa547388b4f9eeaebb280a0fd325728f0ee Mon Sep 17 00:00:00 2001 From: Chengming Gui Date: Mon, 25 Nov 2019 13:53:09 +0800 Subject: [PATCH 0263/1868] drm/amdkcl: [4.8] fix drm helper func - .atomic_commit_tail This is a squash of: drm/amdkcl: test drm_mode_config->helper_private Signed-off-by: Flora Cui Reviewed-by: Yang Xiong Change-Id: I6c9491d9985d0054887df89e76d007b202e703b5 Signed-off-by: Chengming Gui Signed-off-by: Yifan Zhang --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index df290988e7b62..297bd378caee8 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3435,10 +3435,12 @@ static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = { #endif }; +#ifdef HAVE_DRM_MODE_CONFIG_HELPER_PRIVATE static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = { .atomic_commit_tail = amdgpu_dm_atomic_commit_tail, .atomic_commit_setup = drm_dp_mst_atomic_setup_commit, }; +#endif static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector) { @@ -4463,7 +4465,9 @@ static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) adev->mode_info.mode_config_initialized = true; adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs; +#ifdef HAVE_DRM_MODE_CONFIG_HELPER_PRIVATE adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs; +#endif adev_to_drm(adev)->mode_config.max_width = 16384; adev_to_drm(adev)->mode_config.max_height = 16384; From 72336ca9a43e9661435b82b78fb3da88060f1d81 Mon Sep 17 00:00:00 2001 From: tianci yin Date: Mon, 21 Jan 2019 10:45:32 +0800 Subject: [PATCH 0264/1868] drm/amdkcl: [5.0] fix null pointer crash in drm_pick_crtcs It is a squash of: amd/amdkcl: drop AC_AMDGPU_DRM_ATOMIC_HELPER_BEST_ENCODER test [why] drm_pick_crtcs called the best_encoder function pointer directly without NULL checking on rhel6.10, and patch "drm/amdgpu: Remove default best_encoder hook from DC" remove the assignment for .best_encoder, this cause the null crash. [how] bring the assignment code back for these old kernel. Change-Id: I5e687b6c3c83ad3814204c6f7e9a9e8338e18fae Reviewed-by: changzhu Signed-off-by: Tianci Yin Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang Signed-off-by: Slava Grigorev Reviewed-by: Flora Cui Signed-off-by: Ma Jun Signed-off-by: tianci yin --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 31 ++++++++++--------- 1 file changed, 16 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 297bd378caee8..860fdada888e9 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -7572,6 +7572,21 @@ amdgpu_dm_connector_atomic_check(struct drm_connector *conn, return 0; } +static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector) +{ +#ifdef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS + struct drm_encoder *encoder; + + /* There is only one encoder per connector */ + drm_connector_for_each_possible_encoder(connector, encoder) + return encoder; + + return NULL; +#else + return drm_encoder_find(connector->dev, NULL, connector->encoder_ids[0]); +#endif +} + static const struct drm_connector_helper_funcs amdgpu_dm_connector_helper_funcs = { /* @@ -7583,6 +7598,7 @@ amdgpu_dm_connector_helper_funcs = { .get_modes = get_modes, .mode_valid = amdgpu_dm_connector_mode_valid, .atomic_check = amdgpu_dm_connector_atomic_check, + .best_encoder = amdgpu_dm_connector_to_encoder }; static void dm_encoder_helper_disable(struct drm_encoder *encoder) @@ -7778,21 +7794,6 @@ static int to_drm_connector_type(enum signal_type st) } } -static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector) -{ -#ifdef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS - struct drm_encoder *encoder; - - /* There is only one encoder per connector */ - drm_connector_for_each_possible_encoder(connector, encoder) - return encoder; - - return NULL; -#else - return drm_encoder_find(connector->dev, NULL, connector->encoder_ids[0]); -#endif -} - static void amdgpu_dm_get_native_mode(struct drm_connector *connector) { struct drm_encoder *encoder; From d982dea89d34dc6c820448656d0effc1e10ab80c Mon Sep 17 00:00:00 2001 From: changzhu Date: Mon, 4 Mar 2019 10:32:16 +0800 Subject: [PATCH 0265/1868] drm/amdkcl: [4.12] fix for Refactor pageflips plane commit This is a squash of: drm/amdkcl: [4.12] fix drm_crtc_state pageflip_flags build error in amdgpu_dm_atomic_commit_tail drm/amdkcl: Test whether drm_crtc_state->async_flip is available drm/amdkcl: [4.12] Reserve flip_flags for display usage drm/amdkcl: add test for drm_crtc_state->pageflip_flags drm/amdkcl: refactor test for pageflip flag in struct drm-crtc-state [Why] In patch:drm/amd/display: Refactor pageflips plane commit Pageflip code is moved from an if statement to after a continue. Because the new code lacks the kcl control,we need to implement it in the new code. [How] Use the old kcl control way in the new code. Change-Id: I82ada88f319ee7c0b9a33f798123ef01e0371b8d Signed-off-by: changzhu Reviewed-by: tianci yin Reviewed-by: Prike Liang Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang Change-Id: I8b738edde37ecee67d0aba0dcfaf49d4dd881413 Signed-off-by: changzhu Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang Change-Id: I922e6eefbe5ae01c8a69c4467ea3f22f8398a1e8 Signed-off-by: Flora Cui Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang Change-Id: Ia7396521f5e11468e83cf2cabac1b6cbbcda21cd Signed-off-by: Le.Ma Signed-off-by: Jack Gui Signed-off-by: Flora Cui Reviewed-by: Yang Xiong Change-Id: I2f78c678a412ba5945af3d584a525fed5714a6c0 --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 9 +++++++++ drivers/gpu/drm/amd/dkms/m4/drm-crtc-state.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 27 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-crtc-state.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 860fdada888e9..a92c2682a282d 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -9056,7 +9056,12 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, plane->base.id, plane->name); bundle->flip_addrs[planes_count].flip_immediate = +#if defined(HAVE_STRUCT_DRM_CRTC_STATE_ASYNC_FLIP) crtc->state->async_flip && +#else + (crtc->state->pageflip_flags & + DRM_MODE_PAGE_FLIP_ASYNC) != 0 && +#endif acrtc_state->update_type == UPDATE_TYPE_FAST && get_mem_type(old_plane_state->fb) == get_mem_type(fb); @@ -10018,7 +10023,11 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) } for_each_new_crtc_in_state(state, crtc, new_crtc_state, j) +#if defined(HAVE_STRUCT_DRM_CRTC_STATE_ASYNC_FLIP) if (new_crtc_state->async_flip) +#else + if (new_crtc_state->pageflip_flags & DRM_MODE_PAGE_FLIP_ASYNC) +#endif wait_for_vblank = false; /* update planes when needed per crtc*/ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-crtc-state.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-crtc-state.m4 new file mode 100644 index 0000000000000..cc6860f55c68e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-crtc-state.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v5.3-rc3-2032-g4d85f45c73a2 +dnl # drm/atomic: Rename crtc_state->pageflip_flags to async_flip +dnl # +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_STATE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_crtc_state *crtc_state = NULL; + crtc_state->async_flip = 0; + ],[ + AC_DEFINE(HAVE_STRUCT_DRM_CRTC_STATE_ASYNC_FLIP, 1, + [struct drm_crtc_state->async_flip is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index f5b4eebd3a4e4..07ded667ffa3b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -109,6 +109,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_ATOMIC_CHECK AC_AMDGPU_DRM_DP_MST_ATOMIC_ENABLE_DSC AC_AMDGPU_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK + AC_AMDGPU_STRUCT_DRM_CRTC_STATE AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_INIT AC_KERNEL_WAIT From 83bd132e8845c2af99310fc0b950700f00c156cb Mon Sep 17 00:00:00 2001 From: Nicholas Kazlauskas Date: Tue, 5 Mar 2019 09:14:17 -0500 Subject: [PATCH 0266/1868] drm/amdkcl: [display] Drop atomic_obj_lock for private obj [Why] New DRM versions manage locking for private objects for us, so this is no longer needed. This also prevents a WARN_ON from occurring when the private object is duplicated during the forced atomic commit that occurs from the HPD handler. The HPD handler calls drm_modeset_lock_all before the forced commit and if the private object is duplicated then the DEBUG_LOCKS_WARN_ON(ww_ctx->done_acquire) warning will be triggered since we're trying to lock something when everything should have already been locked. [How] Drop the lock and let DRM manage this. Change-Id: I4a5cc92f89ce61bf2e4c3af9f7fa67bd465155a2 Cc: Harry Wentland Signed-off-by: Nicholas Kazlauskas Reviewed-by: Leo Li Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 -- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 1 - 2 files changed, 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index a92c2682a282d..31d0e7cbdc4ee 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4481,8 +4481,6 @@ static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) /* indicates support for immediate flip */ adev_to_drm(adev)->mode_config.async_page_flip = true; - drm_modeset_lock_init(&adev->dm.atomic_obj_lock); - state = kzalloc(sizeof(*state), GFP_KERNEL); if (!state) return -ENOMEM; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index 834b7f4c7e31d..f26ea1aef3a27 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -415,7 +415,6 @@ struct amdgpu_display_manager { */ struct drm_private_obj atomic_obj; - struct drm_modeset_lock atomic_obj_lock; #endif /** From 6c25461c69efb6796c4e3751fc2682a736126242 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 6 Dec 2019 15:39:25 +0800 Subject: [PATCH 0267/1868] drm/amdkcl: [display] add missing linux/debugfs.h for amdgpu_dm_debugfs.c Signed-off-by: Flora Cui Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index 9f1f498d17d38..1bab7e411bb01 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -25,7 +25,7 @@ #include #include - +#include #include "dc.h" #include "amdgpu.h" #include "amdgpu_dm.h" From 2d6a077b92a94d4c55e085deb611d0120f37bf58 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 20 Mar 2024 16:35:34 +0800 Subject: [PATCH 0268/1868] drm/amdkcl: Test whether drm_dp_mst_detect_port() is available v2: drm/amdkcl: fix drm_dp_mst_detect_port() prototype change v2 Change-Id: I3c263f29db3827f340eb80aecd0d48335f8d53c7 Signed-off-by: Flora Cui Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang Signed-off-by: Asher Song --- .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 22 +++++++++++++++++++ .../drm/amd/dkms/m4/drm-dp-mst-detect-port.m4 | 17 ++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 40 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-detect-port.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 5931fb4e49469..c56b11f4534f2 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -116,7 +116,22 @@ static ssize_t dm_dp_aux_transfer(struct drm_dp_aux *aux, return result; } +#ifndef HAVE_DRM_DP_MST_DETECT_PORT_PPPP +static enum drm_connector_status +dm_dp_mst_detect(struct drm_connector *connector, bool force) +{ + struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); + struct amdgpu_dm_connector *master = aconnector->mst_port; + + enum drm_connector_status status = + drm_dp_mst_detect_port( + connector, + &master->mst_mgr, + aconnector->port); + return status; +} +#endif static void dm_dp_mst_connector_destroy(struct drm_connector *connector) { @@ -194,6 +209,9 @@ amdgpu_dm_mst_connector_early_unregister(struct drm_connector *connector) } static const struct drm_connector_funcs dm_dp_mst_connector_funcs = { +#ifndef HAVE_DRM_DP_MST_DETECT_PORT_PPPP + .detect = dm_dp_mst_detect, +#endif .fill_modes = drm_helper_probe_single_connector_modes, .destroy = dm_dp_mst_connector_destroy, .reset = amdgpu_dm_connector_funcs_reset, @@ -441,6 +459,7 @@ dm_mst_atomic_best_encoder(struct drm_connector *connector, return &adev->dm.mst_encoders[acrtc->crtc_id].base; } +#ifdef HAVE_DRM_DP_MST_DETECT_PORT_PPPP static int dm_dp_mst_detect(struct drm_connector *connector, struct drm_modeset_acquire_ctx *ctx, bool force) @@ -513,6 +532,7 @@ dm_dp_mst_detect(struct drm_connector *connector, return connection_status; } +#endif #if defined(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE) static int dm_dp_mst_atomic_check(struct drm_connector *connector, @@ -530,7 +550,9 @@ static const struct drm_connector_helper_funcs dm_dp_mst_connector_helper_funcs .get_modes = dm_dp_mst_get_modes, .mode_valid = amdgpu_dm_connector_mode_valid, .atomic_best_encoder = dm_mst_atomic_best_encoder, +#ifdef HAVE_DRM_DP_MST_DETECT_PORT_PPPP .detect_ctx = dm_dp_mst_detect, +#endif #if defined(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE) .atomic_check = dm_dp_mst_atomic_check, #endif diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-detect-port.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-detect-port.m4 new file mode 100644 index 0000000000000..4198140ed6a0e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-detect-port.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v5.4-rc4-752-g3f9b3f02dda5 +dnl # drm/dp_mst: Protect drm_dp_mst_port members with locking +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_DETECT_PORT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + int ret; + ret = drm_dp_mst_detect_port(NULL, NULL, NULL, NULL); + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_DETECT_PORT_PPPP, 1, + [drm_dp_mst_detect_port() wants p,p,p,p args]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 07ded667ffa3b..60076b9f0d9b3 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -109,6 +109,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_ATOMIC_CHECK AC_AMDGPU_DRM_DP_MST_ATOMIC_ENABLE_DSC AC_AMDGPU_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK + AC_AMDGPU_DRM_DP_MST_DETECT_PORT AC_AMDGPU_STRUCT_DRM_CRTC_STATE AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_INIT From a4650ee1047ff36d4b506c49904dc077562a5ad5 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 6 Dec 2019 16:31:52 +0800 Subject: [PATCH 0269/1868] drm/amdkcl: fix for commit "drm/amd/display: Expose HDR output metadata for supported connectors" Signed-off-by: Flora Cui Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang Change-Id: I03f5e07550343e269ef5cb7b0dba24249ad20adb --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 26 +++++++++++++++---- 1 file changed, 21 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 31d0e7cbdc4ee..cc0d881e71eea 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -6680,7 +6680,6 @@ create_stream_for_sink(struct drm_connector *connector, sink = aconnector->dc_sink; dc_sink_retain(sink); } - stream = dc_create_stream_for_sink(sink); if (stream == NULL) { @@ -7441,6 +7440,7 @@ enum drm_mode_status amdgpu_dm_connector_mode_valid(struct drm_connector *connec return result; } +#ifdef HDMI_DRM_INFOFRAME_SIZE static int fill_hdr_info_packet(const struct drm_connector_state *state, struct dc_info_packet *out) { @@ -7569,7 +7569,7 @@ amdgpu_dm_connector_atomic_check(struct drm_connector *conn, return 0; } - +#endif static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector) { #ifdef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS @@ -7595,7 +7595,9 @@ amdgpu_dm_connector_helper_funcs = { */ .get_modes = get_modes, .mode_valid = amdgpu_dm_connector_mode_valid, +#ifdef HDMI_DRM_INFOFRAME_SIZE .atomic_check = amdgpu_dm_connector_atomic_check, +#endif .best_encoder = amdgpu_dm_connector_to_encoder }; @@ -8206,6 +8208,7 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, if (connector_type == DRM_MODE_CONNECTOR_HDMIA || connector_type == DRM_MODE_CONNECTOR_DisplayPort || connector_type == DRM_MODE_CONNECTOR_eDP) { + drm_connector_attach_hdr_output_metadata_property(&aconnector->base); if (!aconnector->mst_root) @@ -9869,9 +9872,12 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) struct amdgpu_crtc *acrtc = to_amdgpu_crtc(dm_new_con_state->base.crtc); struct dc_surface_update *dummy_updates; struct dc_stream_update stream_update; - struct dc_info_packet hdr_packet; struct dc_stream_status *status = NULL; - bool abm_changed, hdr_changed, scaling_changed; +#ifdef HDMI_DRM_INFOFRAME_SIZE + struct dc_info_packet hdr_packet; + bool hdr_changed; +#endif + bool abm_changed, scaling_changed; memset(&stream_update, 0, sizeof(stream_update)); @@ -9893,10 +9899,16 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) abm_changed = dm_new_crtc_state->abm_level != dm_old_crtc_state->abm_level; +#ifdef HDMI_DRM_INFOFRAME_SIZE hdr_changed = !drm_connector_atomic_hdr_metadata_equal(old_con_state, new_con_state); +#endif - if (!scaling_changed && !abm_changed && !hdr_changed) + if (!scaling_changed && !abm_changed +#ifdef HDMI_DRM_INFOFRAME_SIZE + && !hdr_changed +#endif + ) continue; stream_update.stream = dm_new_crtc_state->stream; @@ -9914,10 +9926,12 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) stream_update.abm_level = &dm_new_crtc_state->abm_level; } +#ifdef HDMI_DRM_INFOFRAME_SIZE if (hdr_changed) { fill_hdr_info_packet(new_con_state, &hdr_packet); stream_update.hdr_static_metadata = &hdr_packet; } +#endif status = dc_stream_get_status(dm_new_crtc_state->stream); @@ -10439,10 +10453,12 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm, dm_new_crtc_state->abm_level = dm_new_conn_state->abm_level; +#ifdef HDMI_DRM_INFOFRAME_SIZE ret = fill_hdr_info_packet(drm_new_conn_state, &new_stream->hdr_static_metadata); if (ret) goto fail; +#endif /* * If we already removed the old stream from the context From 39a0d97d4a9e1fb672c6329a26a2965f49232274 Mon Sep 17 00:00:00 2001 From: Jiansong Chen Date: Thu, 19 Dec 2019 14:58:42 +0800 Subject: [PATCH 0270/1868] drm/amdkcl: fix implicit declaration of prepare_flip_isr dm_page_flip is activated for CentOS7.3 kernel(drm version 4.6.5). The funciton will call prepare_flip_isr and its definition is in front of prepare_flip_isr. Change-Id: I084653267001f327adb75f05b9b8f6608af1d9c1 Signed-off-by: Jiansong Chen Reviewed-by: Flora Cui Reviewed-by: Jack Gui Signed-off-by: Yifan Zhang --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index cc0d881e71eea..9887a7b2dd84d 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -247,7 +247,7 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state); static int amdgpu_dm_atomic_check(struct drm_device *dev, struct drm_atomic_state *state); - +static void prepare_flip_isr(struct amdgpu_crtc *acrtc); static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector); static void handle_hpd_rx_irq(void *param); From 01d54ab063570d63e3d0b8526434751b2dd97ab7 Mon Sep 17 00:00:00 2001 From: "Stanley.Yang" Date: Thu, 26 Dec 2019 17:15:39 +0800 Subject: [PATCH 0271/1868] drm/amdkcl: Test whether drm_dp_mst_dsc_aux_for_port is available Change-Id: If098c1c8474741511e7ae338be90c1a382e3f5cc Signed-off-by: Stanley.Yang Reviewed-by: Flora Cui Signed-off-by: Yifan Zhang --- .../amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 9 +++++++-- .../amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 24 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index c56b11f4534f2..0fbd2bdd2df45 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -257,8 +257,9 @@ static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnecto u8 dsc_branch_dec_caps_raw[3] = { 0 }; // DSC branch decoder caps 0xA0 ~ 0xA2 u8 *dsc_branch_dec_caps = NULL; +#if defined(HAVE_DRM_DP_MST_DSC_AUX_FOR_PORT) aconnector->dsc_aux = drm_dp_mst_dsc_aux_for_port(port); - +#endif /* * drm_dp_mst_dsc_aux_for_port() will return NULL for certain configs * because it only check the dsc/fec caps of the "port variable" and not the dock @@ -427,6 +428,8 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector) amdgpu_dm_update_freesync_caps( connector, aconnector->edid); +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT +#if defined(HAVE_DRM_DP_MST_DSC_AUX_FOR_PORT) #if defined(CONFIG_DRM_AMD_DC_FP) if (!validate_dsc_caps_on_connector(aconnector)) memset(&aconnector->dc_sink->dsc_caps, @@ -436,6 +439,8 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector) if (!retrieve_downstream_port_device(aconnector)) memset(&aconnector->mst_downstream_port_present, 0, sizeof(aconnector->mst_downstream_port_present)); +#endif +#endif } } @@ -859,7 +864,7 @@ int dm_mst_get_pbn_divider(struct dc_link *link) } #if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT) -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) && defined(HAVE_DRM_DP_MST_ATOMIC_CHECK) +#if defined(HAVE_DRM_DP_MST_ATOMIC_CHECK) struct dsc_mst_fairness_params { struct dc_crtc_timing *timing; struct dc_sink *sink; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 new file mode 100644 index 0000000000000..06d77b61ab828 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit d251c02a2b78245bb32d7909a66b06285f7922a2 +dnl # drm/dp_mst: Add helpers for MST DSC and virtual DPCD aux +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_DSC_AUX_FOR_PORT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_dp_mst_dsc_aux_for_port(NULL); + ], [drm_dp_mst_dsc_aux_for_port], [drivers/gpu/drm/drm_dp_mst_topology.c], [ + AC_DEFINE(HAVE_DRM_DP_MST_DSC_AUX_FOR_PORT, 1, + [drm_dp_mst_dsc_aux_for_port() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 60076b9f0d9b3..9a0376d17acec 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -111,6 +111,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK AC_AMDGPU_DRM_DP_MST_DETECT_PORT AC_AMDGPU_STRUCT_DRM_CRTC_STATE + AC_AMDGPU_DRM_DP_MST_DSC_AUX_FOR_PORT AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_INIT AC_KERNEL_WAIT From 595c5587a246a9f191c0e6715eadf23cfb809c0c Mon Sep 17 00:00:00 2001 From: "Stanley.Yang" Date: Fri, 27 Dec 2019 15:20:06 +0800 Subject: [PATCH 0272/1868] drm/amdkcl: Test whether drm_dp_mst_add_affected_dsc_crtcs() is available Change-Id: Icefa820b7602cfd943cbb4d49caac6fa71083263 Signed-off-by: Stanley.Yang Reviewed-by: Flora Cui Signed-off-by: Yifan Zhang --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++++ .../m4/drm-dp-mst-add-affected-dsc-crtcs.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 22 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 9887a7b2dd84d..252a98f1ac736 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -11192,6 +11192,7 @@ static inline struct __drm_planes_state *__get_next_zpos( (old_plane_state) = __i->old_state, \ (new_plane_state) = __i->new_state, 1)) +#if defined(HAVE_DRM_DP_MST_ADD_AFFECTED_DSC_CRTCS) static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm_crtc *crtc) { struct drm_connector *connector; @@ -11221,6 +11222,7 @@ static int add_affected_mst_dsc_crtcs(struct drm_atomic_state *state, struct drm return drm_dp_mst_add_affected_dsc_crtcs(state, &aconnector->mst_root->mst_mgr); } +#endif /** * DOC: Cursor Modes - Native vs Overlay @@ -11464,6 +11466,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, new_crtc_state->connectors_changed = true; } +#if defined(HAVE_DRM_DP_MST_ADD_AFFECTED_DSC_CRTCS) if (dc_resource_is_dsc_encoding_supported(dc)) { for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { if (drm_atomic_crtc_needs_modeset(new_crtc_state)) { @@ -11475,6 +11478,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, } } } +#endif for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) { dm_old_crtc_state = to_dm_crtc_state(old_crtc_state); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 new file mode 100644 index 0000000000000..1d4564270d065 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit 971fb192aaeb4b5086ac3f21d00943a5e1431176 +dnl # drm/dp_mst: Add helper to trigger modeset on affected DSC MST CRTCs +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_ADD_AFFECTED_DSC_CRTCS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + int ret; + ret = drm_dp_mst_add_affected_dsc_crtcs(NULL, NULL); + ], [drm_dp_mst_dsc_aux_for_port], [drivers/gpu/drm/drm_dp_mst_topology.c], [ + AC_DEFINE(HAVE_DRM_DP_MST_ADD_AFFECTED_DSC_CRTCS, 1, + [drm_dp_mst_add_affected_dsc_crtcs() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 9a0376d17acec..10616d390bd82 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -112,6 +112,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_DETECT_PORT AC_AMDGPU_STRUCT_DRM_CRTC_STATE AC_AMDGPU_DRM_DP_MST_DSC_AUX_FOR_PORT + AC_AMDGPU_DRM_DP_MST_ADD_AFFECTED_DSC_CRTCS AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_INIT AC_KERNEL_WAIT From 7d01bdd23d6fc06357b8a090be0d60c98a87f409 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 21 Jan 2020 15:35:48 +0800 Subject: [PATCH 0273/1868] drm/amdkcl: adapt for drm_connector_helper_funcs->atomic_check() prototype change prototype change is in v5.2-rc2-529-g6f3b62781bbd macro HDMI_DRM_INFOFRAME_SIZE is introduced in v5.1-rc5-1691-g2cdbfd66a829 thus there's no need to check atomic_check() availability. Signed-off-by: Flora Cui Reviewed-by: Feifei Xu Signed-off-by: Flora Cui Signed-off-by: Yifan Zhang Change-Id: I511b2784fc4d815f3425a58ecc1b64ae8e291444 --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 252a98f1ac736..fedf19967141d 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -7502,10 +7502,16 @@ static int fill_hdr_info_packet(const struct drm_connector_state *state, static int amdgpu_dm_connector_atomic_check(struct drm_connector *conn, +#ifdef HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE struct drm_atomic_state *state) { struct drm_connector_state *new_con_state = drm_atomic_get_new_connector_state(state, conn); +#else + struct drm_connector_state *new_con_state) +{ + struct drm_atomic_state *state = new_con_state->state; +#endif struct drm_connector_state *old_con_state = drm_atomic_get_old_connector_state(state, conn); struct drm_crtc *crtc = new_con_state->crtc; From b7ebe31f095f0c8fc1fed2c0d01e40aff763bf66 Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Wed, 4 Mar 2020 15:46:02 +0800 Subject: [PATCH 0274/1868] drm/amdkcl: add HAVE_HDR_SINK_METADATA macro v3 Change-Id: Ifbf6c42b1b46065c6e7836e80bb505e14dfdf76c Signed-off-by: Yifan Zhang Reviewed-by: Flora Cui --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 47 +++++++++++++++++++ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 4 ++ .../drm/amd/dkms/m4/drm-hdr-sink-metadata.m4 | 20 ++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 72 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-hdr-sink-metadata.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index fedf19967141d..f49ec0aa04d36 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3442,6 +3442,7 @@ static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = { }; #endif +#ifdef HAVE_HDR_SINK_METADATA static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector) { struct amdgpu_dm_backlight_caps *caps; @@ -3483,6 +3484,7 @@ static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector) caps->aux_max_input_signal = 512; } } +#endif void amdgpu_dm_update_connector_after_detect( struct amdgpu_dm_connector *aconnector) @@ -3610,7 +3612,9 @@ void amdgpu_dm_update_connector_after_detect( drm_connector_update_edid_property(connector, aconnector->edid); amdgpu_dm_update_freesync_caps(connector, aconnector->edid); +#ifdef HAVE_HDR_SINK_METADATA update_connector_ext_caps(aconnector); +#endif } else { drm_dp_cec_unset_edid(&aconnector->dm_dp_aux.aux); amdgpu_dm_update_freesync_caps(connector, NULL); @@ -4533,7 +4537,9 @@ static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255 +#ifdef HAVE_HDR_SINK_METADATA #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50 +#endif static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm, int bl_idx) @@ -4549,8 +4555,10 @@ static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm, amdgpu_acpi_get_backlight_caps(&caps); if (caps.caps_valid) { dm->backlight_caps[bl_idx].caps_valid = true; +#ifdef HAVE_HDR_SINK_METADATA if (caps.aux_support) return; +#endif dm->backlight_caps[bl_idx].min_input_signal = caps.min_input_signal; dm->backlight_caps[bl_idx].max_input_signal = caps.max_input_signal; } else { @@ -4560,14 +4568,17 @@ static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm, AMDGPU_DM_DEFAULT_MAX_BACKLIGHT; } #else +#ifdef HAVE_HDR_SINK_METADATA if (dm->backlight_caps[bl_idx].aux_support) return; +#endif dm->backlight_caps[bl_idx].min_input_signal = AMDGPU_DM_DEFAULT_MIN_BACKLIGHT; dm->backlight_caps[bl_idx].max_input_signal = AMDGPU_DM_DEFAULT_MAX_BACKLIGHT; #endif } +#ifdef HAVE_HDR_SINK_METADATA static int get_brightness_range(const struct amdgpu_dm_backlight_caps *caps, unsigned int *min, unsigned int *max) { @@ -4613,19 +4624,25 @@ static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *cap return DIV_ROUND_CLOSEST(AMDGPU_MAX_BL_LEVEL * (brightness - min), max - min); } +#endif static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm, int bl_idx, u32 user_brightness) { struct amdgpu_dm_backlight_caps caps; +#ifdef HAVE_HDR_SINK_METADATA struct dc_link *link; u32 brightness; +#else + uint32_t brightness = user_brightness; +#endif bool rc; amdgpu_dm_update_backlight_caps(dm, bl_idx); caps = dm->backlight_caps[bl_idx]; +#ifdef HAVE_HDR_SINK_METADATA dm->brightness[bl_idx] = user_brightness; /* update scratch register */ if (bl_idx == 0) @@ -4647,6 +4664,30 @@ static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm, if (rc) dm->actual_brightness[bl_idx] = user_brightness; +#else + /* + * The brightness input is in the range 0-255 + * It needs to be rescaled to be between the + * requested min and max input signal + * + * It also needs to be scaled up by 0x101 to + * match the DC interface which has a range of + * 0 to 0xffff + */ + brightness = + brightness + * 0x101 + * (caps.max_input_signal - caps.min_input_signal) + / AMDGPU_MAX_BL_LEVEL + + caps.min_input_signal * 0x101; + + rc = dc_link_set_backlight_level(dm->backlight_link[bl_idx], brightness, 0); + + if (!rc) + DRM_ERROR("DM: Failed to update backlight on eDP[%d]\n", bl_idx); + if (rc) + dm->actual_brightness[bl_idx] = user_brightness; +#endif } static int amdgpu_dm_backlight_update_status(struct backlight_device *bd) @@ -4675,6 +4716,7 @@ static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm, amdgpu_dm_update_backlight_caps(dm, bl_idx); caps = dm->backlight_caps[bl_idx]; +#ifdef HAVE_HDR_SINK_METADATA if (caps.aux_support) { u32 avg, peak; bool rc; @@ -4684,13 +4726,18 @@ static u32 amdgpu_dm_backlight_get_level(struct amdgpu_display_manager *dm, return dm->brightness[bl_idx]; return convert_brightness_to_user(&caps, avg); } +#endif ret = dc_link_get_backlight_level(link); if (ret == DC_ERROR_UNEXPECTED) return dm->brightness[bl_idx]; +#ifdef HAVE_HDR_SINK_METADATA return convert_brightness_to_user(&caps, ret); +#else + return ret; +#endif } static int amdgpu_dm_backlight_get_brightness(struct backlight_device *bd) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index f26ea1aef3a27..c501090d47551 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -157,6 +157,7 @@ struct idle_workqueue { * Describe the backlight support for ACPI or eDP AUX. */ struct amdgpu_dm_backlight_caps { +#ifdef HAVE_HDR_SINK_METADATA /** * @ext_caps: Keep the data struct with all the information about the * display support for HDR. @@ -171,6 +172,7 @@ struct amdgpu_dm_backlight_caps { * in nits. */ u32 aux_max_input_signal; +#endif /** * @min_input_signal: minimum possible input in range 0-255. */ @@ -186,7 +188,9 @@ struct amdgpu_dm_backlight_caps { /** * @aux_support: Describes if the display supports AUX backlight. */ +#ifdef HAVE_HDR_SINK_METADATA bool aux_support; +#endif /** * @ac_level: the default brightness if booted on AC */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-hdr-sink-metadata.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-hdr-sink-metadata.m4 new file mode 100644 index 0000000000000..31c75e5910a4e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-hdr-sink-metadata.m4 @@ -0,0 +1,20 @@ +dnl # +dnl # commit fbb5d0353c62d10c3699ec844d2d015a762952d7 +dnl # drm: Add HDR source metadata property +dnl # + +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_HAVE_HDR_SINK_METADATA], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_connector *dc = NULL; + struct hdr_sink_metadata *p = NULL; + + p = &dc->hdr_sink_metadata; + ],[ + AC_DEFINE(HAVE_HDR_SINK_METADATA, 1, + [drm_connector_hdr_sink_metadata() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 10616d390bd82..5d3efbad8fa5c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -113,6 +113,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_STRUCT_DRM_CRTC_STATE AC_AMDGPU_DRM_DP_MST_DSC_AUX_FOR_PORT AC_AMDGPU_DRM_DP_MST_ADD_AFFECTED_DSC_CRTCS + AC_AMDGPU_DRM_CONNECTOR_HAVE_HDR_SINK_METADATA AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_INIT AC_KERNEL_WAIT From f0b5e7d7df305f7770f7b4939ded9b5a67c4d3af Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Fri, 6 Mar 2020 11:44:27 +0800 Subject: [PATCH 0275/1868] drm/amdkcl: add protection for P010 pixel format Change-Id: Iebdf9ccdb876bba345ae49c06669518101fe35ee Signed-off-by: Yifan Zhang Signed-off-by: Ma Jun --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 2 ++ drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c | 2 ++ drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c | 2 ++ 4 files changed, 8 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index f49ec0aa04d36..6f8e5697a3c51 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -5582,9 +5582,11 @@ fill_dc_plane_info_and_addr(struct amdgpu_device *adev, case DRM_FORMAT_NV12: plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb; break; +#ifdef DRM_FORMAT_P010 case DRM_FORMAT_P010: plane_info->format = SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb; break; +#endif case DRM_FORMAT_XRGB16161616F: case DRM_FORMAT_ARGB16161616F: plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 60b255fa5c9d1..cee20078bb422 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -793,8 +793,10 @@ static int amdgpu_dm_plane_get_plane_formats(const struct drm_plane *plane, if (plane_cap && plane_cap->pixel_format_support.nv12) formats[num_formats++] = DRM_FORMAT_NV12; +#ifdef DRM_FORMAT_P010 if (plane_cap && plane_cap->pixel_format_support.p010) formats[num_formats++] = DRM_FORMAT_P010; +#endif if (plane_cap && plane_cap->pixel_format_support.fp16) { formats[num_formats++] = DRM_FORMAT_XRGB16161616F; formats[num_formats++] = DRM_FORMAT_ARGB16161616F; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c index 563c5eec83ff3..5e4daf97861fc 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c @@ -513,7 +513,9 @@ static const struct dc_plane_cap plane_cap = { .argb8888 = true, .nv12 = true, .fp16 = true, +#ifdef DRM_FORMAT_P010 .p010 = false +#endif }, .max_upscale_factor = { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c index 347e6aaea582f..ded328abd281e 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c @@ -589,7 +589,9 @@ static const struct dc_plane_cap plane_cap = { .argb8888 = true, .nv12 = true, .fp16 = true, +#ifdef DRM_FORMAT_P010 .p010 = true +#endif }, .max_upscale_factor = { From 98f969cf8a9e21c4930d0bfbde492ca9c624a564 Mon Sep 17 00:00:00 2001 From: Emily Deng Date: Thu, 2 Apr 2020 15:06:51 +0800 Subject: [PATCH 0276/1868] amd/amdkcl: Fix the assert report Signed-off-by: Emily Deng Reviewed-by: Flora Cui Change-Id: If2f264ccc7b2f0e73952fd88b45a23174d22ea61 Signed-off-by: Yifan Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c | 10 ++++------ drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 10 +++++----- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 10 +++++----- drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 12 ++++++------ drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 10 +++++----- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 ++++---- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c | 2 +- .../drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 2 +- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c | 4 ++-- 11 files changed, 35 insertions(+), 37 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c index 96820a0e87631..4131569c8ee15 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c @@ -1637,7 +1637,7 @@ amdgpu_connector_add(struct amdgpu_device *adev, drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { #else - drm_for_each_connector(connector, dev) { + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { #endif amdgpu_connector = to_amdgpu_connector(connector); if (amdgpu_connector->connector_id == connector_id) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 37303d65eb9ee..453aae4d35437 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -645,7 +645,7 @@ void amdgpu_display_print_display_setup(struct drm_device *dev) drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { #else - drm_for_each_connector(connector, dev) { + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { #endif amdgpu_connector = to_amdgpu_connector(connector); DRM_INFO("Connector %d:\n", i); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c index cd4bf5460252b..54913ae5148b6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c @@ -48,7 +48,7 @@ amdgpu_link_encoder_connector(struct drm_device *dev) /* walk the list and link encoders to connectors */ drm_for_each_connector_iter(connector, &iter) { #else - drm_for_each_connector(connector, dev) { + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { #endif amdgpu_connector = to_amdgpu_connector(connector); list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { @@ -78,8 +78,7 @@ void amdgpu_encoder_set_active_device(struct drm_encoder *encoder) drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { #else - - drm_for_each_connector(connector, dev) { + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { #endif if (connector->encoder == encoder) { struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); @@ -109,9 +108,8 @@ amdgpu_get_connector_for_encoder(struct drm_encoder *encoder) #ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { - #else - drm_for_each_connector(connector, dev) { + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { #endif amdgpu_connector = to_amdgpu_connector(connector); if (amdgpu_encoder->active_device & amdgpu_connector->devices) { @@ -140,7 +138,7 @@ amdgpu_get_connector_for_encoder_init(struct drm_encoder *encoder) drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { #else - drm_for_each_connector(connector, dev) { + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { #endif amdgpu_connector = to_amdgpu_connector(connector); if (amdgpu_encoder->devices & amdgpu_connector->devices) { diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index c87d4fbe3f46b..5d93201ac67da 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -343,7 +343,7 @@ static void dce_v10_0_hpd_init(struct amdgpu_device *adev) drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { #else - drm_for_each_connector(connector, dev) { + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { #endif struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); @@ -407,7 +407,7 @@ static void dce_v10_0_hpd_fini(struct amdgpu_device *adev) drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { #else - drm_for_each_connector(connector, dev) { + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { #endif struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); @@ -1265,7 +1265,7 @@ static void dce_v10_0_audio_write_latency_fields(struct drm_encoder *encoder, drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { #else - drm_for_each_connector(connector, dev) { + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { #endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); @@ -1320,7 +1320,7 @@ static void dce_v10_0_audio_write_speaker_allocation(struct drm_encoder *encoder drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { #else - drm_for_each_connector(connector, dev) { + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { #endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); @@ -1398,7 +1398,7 @@ static void dce_v10_0_audio_write_sad_regs(struct drm_encoder *encoder) drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { #else - drm_for_each_connector(connector, dev) { + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { #endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index 68b24df8aa3f9..710e822524309 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -367,7 +367,7 @@ static void dce_v11_0_hpd_init(struct amdgpu_device *adev) drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { #else - drm_for_each_connector(connector, dev) { + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { #endif struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); @@ -430,7 +430,7 @@ static void dce_v11_0_hpd_fini(struct amdgpu_device *adev) drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { #else - drm_for_each_connector(connector, dev) { + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { #endif struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); @@ -1297,7 +1297,7 @@ static void dce_v11_0_audio_write_latency_fields(struct drm_encoder *encoder, drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { #else - drm_for_each_connector(connector, dev) { + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { #endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); @@ -1352,7 +1352,7 @@ static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { #else - drm_for_each_connector(connector, dev) { + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { #endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); @@ -1430,7 +1430,7 @@ static void dce_v11_0_audio_write_sad_regs(struct drm_encoder *encoder) drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { #else - drm_for_each_connector(connector, dev) { + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { #endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c index 19a4e46242564..bc1155699dead 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c @@ -314,7 +314,7 @@ static void dce_v6_0_hpd_init(struct amdgpu_device *adev) drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { #else - drm_for_each_connector(connector, dev) { + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { #endif struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); @@ -368,7 +368,7 @@ static void dce_v6_0_hpd_fini(struct amdgpu_device *adev) drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { #else - drm_for_each_connector(connector, dev) { + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { #endif struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); @@ -1185,7 +1185,7 @@ static void dce_v6_0_audio_write_latency_fields(struct drm_encoder *encoder, drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { #else - drm_for_each_connector(connector, dev) { + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { #endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); @@ -1238,7 +1238,7 @@ static void dce_v6_0_audio_write_speaker_allocation(struct drm_encoder *encoder) drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { #else - drm_for_each_connector(connector, dev) { + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { #endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); @@ -1321,7 +1321,7 @@ static void dce_v6_0_audio_write_sad_regs(struct drm_encoder *encoder) drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { #else - drm_for_each_connector(connector, dev) { + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { #endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); @@ -1733,7 +1733,7 @@ static void dce_v6_0_afmt_setmode(struct drm_encoder *encoder, drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { #else - drm_for_each_connector(connector, dev) { + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { #endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index 218a03570d63c..26e464c18fea2 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -305,7 +305,7 @@ static void dce_v8_0_hpd_init(struct amdgpu_device *adev) drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { #else - drm_for_each_connector(connector, dev) { + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { #endif struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); @@ -359,7 +359,7 @@ static void dce_v8_0_hpd_fini(struct amdgpu_device *adev) drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { #else - drm_for_each_connector(connector, dev) { + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { #endif struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); @@ -1221,7 +1221,7 @@ static void dce_v8_0_audio_write_latency_fields(struct drm_encoder *encoder, drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { #else - drm_for_each_connector(connector, dev) { + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { #endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); @@ -1292,7 +1292,7 @@ static void dce_v8_0_audio_write_speaker_allocation(struct drm_encoder *encoder) drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { #else - drm_for_each_connector(connector, dev) { + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { #endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); @@ -1368,7 +1368,7 @@ static void dce_v8_0_audio_write_sad_regs(struct drm_encoder *encoder) drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { #else - drm_for_each_connector(connector, dev) { + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { #endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 6f8e5697a3c51..6ba0e7c61ecb5 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1022,7 +1022,7 @@ static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port, drm_connector_list_iter_begin(dev, &conn_iter); drm_for_each_connector_iter(connector, &conn_iter) { #else - drm_for_each_connector(connector, dev) { + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { #endif if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) continue; @@ -2532,7 +2532,7 @@ static int detect_mst_link_for_all_connectors(struct drm_device *dev) drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { #else - drm_for_each_connector(connector, dev) { + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { #endif if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) continue; @@ -2671,7 +2671,7 @@ static void s3_handle_mst(struct drm_device *dev, bool suspend) drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { #else - drm_for_each_connector(connector, dev) { + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { #endif if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) continue; @@ -3223,7 +3223,7 @@ static int dm_resume(void *handle) drm_connector_list_iter_begin(ddev, &iter); drm_for_each_connector_iter(connector, &iter) { #else - drm_for_each_connector(connector, ddev) { + list_for_each_entry(connector, &(ddev)->mode_config.connector_list, head) { #endif if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) continue; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c index c043cf62e62ff..07a09ccf813a6 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c @@ -331,7 +331,7 @@ int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name) drm_connector_list_iter_begin(crtc->dev, &conn_iter); drm_for_each_connector_iter(connector, &conn_iter) { #else - drm_for_each_connector(connector, crtc->dev) { + list_for_each_entry(connector, &(crtc->dev)->mode_config.connector_list, head) { #endif if (!connector->state || connector->state->crtc != crtc) continue; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index 1bab7e411bb01..7e3b648098d9f 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -3776,7 +3776,7 @@ static int mst_topo_show(struct seq_file *m, void *unused) drm_connector_list_iter_begin(dev, &conn_iter); drm_for_each_connector_iter(connector, &conn_iter) { #else - drm_for_each_connector(connector, dev) { + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { #endif if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) continue; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c index c276e0bbc6b00..155d6d7db7562 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c @@ -901,7 +901,7 @@ void amdgpu_dm_hpd_init(struct amdgpu_device *adev) drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { #else - drm_for_each_connector(connector, dev) { + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { #endif struct amdgpu_dm_connector *amdgpu_dm_connector; const struct dc_link *dc_link; @@ -950,7 +950,7 @@ void amdgpu_dm_hpd_fini(struct amdgpu_device *adev) drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { #else - drm_for_each_connector(connector, dev) { + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { #endif struct amdgpu_dm_connector *amdgpu_dm_connector; const struct dc_link *dc_link; From 83ee1e159690898e72e4053e782ce270db1fb955 Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Wed, 22 Apr 2020 21:29:31 +0800 Subject: [PATCH 0277/1868] drm/amdkcl: add AC_AMDGPU_DRM_HDMI_VENDOR_INFOFRAME_FROM_DISPLAY_MODE Change-Id: I66ddaedbb8f853bb9e40f10d96db003d0ccfedab Signed-off-by: Yifan Zhang Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++++ ...drm-hdmi-vendor-infoframe-from-display-mode.m4 | 15 +++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 20 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-hdmi-vendor-infoframe-from-display-mode.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 6ba0e7c61ecb5..e9acf33cf107b 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -6186,7 +6186,11 @@ static void fill_stream_properties_from_drm_display_mode( drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, mode_in); #endif /* HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_P */ timing_out->vic = avi_frame.video_code; +#if defined(HAVE_DRM_HDMI_VENDOR_INFOFRAME_FROM_DISPLAY_MODE_P_P_P) drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in); +#else + drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, mode_in); +#endif timing_out->hdmi_vic = hv_frame.vic; } diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-hdmi-vendor-infoframe-from-display-mode.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-hdmi-vendor-infoframe-from-display-mode.m4 new file mode 100644 index 0000000000000..c9f2c8a635e43 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-hdmi-vendor-infoframe-from-display-mode.m4 @@ -0,0 +1,15 @@ +dnl f1781e9bb2dd2305d8d7ffbede1888ae22119557 +dnl # drm/edid: Allow HDMI infoframe without VIC or S3D +dnl # +AC_DEFUN([AC_AMDGPU_DRM_HDMI_VENDOR_INFOFRAME_FROM_DISPLAY_MODE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_hdmi_vendor_infoframe_from_display_mode(NULL, NULL, NULL); + ], [drm_hdmi_vendor_infoframe_from_display_mode], [drivers/gpu/drm/drm_edid.c], [ + AC_DEFINE(HAVE_DRM_HDMI_VENDOR_INFOFRAME_FROM_DISPLAY_MODE_P_P_P, 1, + [drm_hdmi_vendor_infoframe_from_display_mode() has p,p,p interface]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 5d3efbad8fa5c..dbdfb17d99557 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -101,6 +101,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_FRAMEBUFFER_FORMAT AC_AMDGPU_STRSCPY AC_AMDGPU_DRM_DP_MST_TOPOLOGY + AC_AMDGPU_DRM_HDMI_VENDOR_INFOFRAME_FROM_DISPLAY_MODE AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS AC_AMDGPU_DRM_ATOMIC_PRIVATE_OBJ_INIT AC_AMDGPU_DRM_MODE_CONFIG_FUNCS From 7855c6eb97f66bf7192be39420e634cc979c634b Mon Sep 17 00:00:00 2001 From: Chengming Gui Date: Wed, 6 May 2020 15:38:49 +0800 Subject: [PATCH 0278/1868] drm/amdkcl: Test whether drm_dp_send_real_edid_checksum is available introduced by commit: e11f5bd8228fc3760c221f940b9f6365dbf3e7ed drm: Add support for DP 1.4 Compliance edid corruption test Signed-off-by: Chengming Gui Reviewed-by: Flora Cui --- .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 5 ++++- .../dkms/m4/drm-dp-send-real-edid-checksum.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 21 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index 165e010fe69c8..68a3a87b11348 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -893,7 +893,9 @@ enum dc_edid_status dm_helpers_read_local_edid( struct dc_sink *sink) { struct amdgpu_dm_connector *aconnector = link->priv; +#ifdef HAVE_DRM_DP_SEND_REAL_EDID_CHECKSUM struct drm_connector *connector = &aconnector->base; +#endif struct i2c_adapter *ddc; int retry = 3; enum dc_edid_status edid_status; @@ -911,6 +913,7 @@ enum dc_edid_status dm_helpers_read_local_edid( edid = drm_get_edid(&aconnector->base, ddc); +#ifdef HAVE_DRM_DP_SEND_REAL_EDID_CHECKSUM /* DP Compliance Test 4.2.2.6 */ if (link->aux_mode && connector->edid_corrupt) drm_dp_send_real_edid_checksum(&aconnector->dm_dp_aux.aux, connector->real_edid_checksum); @@ -919,6 +922,7 @@ enum dc_edid_status dm_helpers_read_local_edid( connector->edid_corrupt = false; return EDID_BAD_CHECKSUM; } +#endif if (!edid) return EDID_NO_RESPONSE; @@ -966,7 +970,6 @@ enum dc_edid_status dm_helpers_read_local_edid( DP_TEST_RESPONSE, &test_response.raw, sizeof(test_response)); - } return edid_status; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 new file mode 100644 index 0000000000000..c15c7d3d88eb9 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit e11f5bd8228fc3760c221f940b9f6365dbf3e7ed +dnl # drm: Add support for DP 1.4 Compliance edid corruption test +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_SEND_REAL_EDID_CHECKSUM], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_dp_send_real_edid_checksum(NULL, 0); + ], [drm_dp_send_real_edid_checksum], [drivers/gpu/drm/drm_dp_helper.c], [ + AC_DEFINE(HAVE_DRM_DP_SEND_REAL_EDID_CHECKSUM, 1, + [drm_dp_send_real_edid_checksum() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index dbdfb17d99557..7aaa3648dee84 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -64,6 +64,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_INIT_WITH_DDC AC_AMDGPU_DRM_DP_CALC_PBN_MODE AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS + AC_AMDGPU_DRM_DP_SEND_REAL_EDID_CHECKSUM AC_AMDGPU_DRM_DP_CEC_CORRELATION_FUNCTIONS AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_RESUME AC_AMDGPU___DRM_ATOMIC_HELPER_CRTC_RESET From 5ec572c1316b1ae43fc96693508f3a30f8b6e4fb Mon Sep 17 00:00:00 2001 From: Chengming Gui Date: Thu, 7 May 2020 13:59:32 +0800 Subject: [PATCH 0279/1868] drm/amdkcl: Check whether DRM_FORMAT_XRGB16161616F is defined DRM_FORMAT_XRGB16161616F introduced by commit: drm/fourcc: Add 64 bpp half float formats Signed-off-by: Chengming Gui Reviewed-by: Flora Cui Change-Id: I44c6d15e6f91c01377f59520e1d8a360c9796a1a --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index e9acf33cf107b..044ada3e6d044 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -5595,6 +5595,7 @@ fill_dc_plane_info_and_addr(struct amdgpu_device *adev, case DRM_FORMAT_ABGR16161616F: plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F; break; +#ifdef DRM_FORMAT_XRGB16161616 case DRM_FORMAT_XRGB16161616: case DRM_FORMAT_ARGB16161616: plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616; @@ -5603,6 +5604,7 @@ fill_dc_plane_info_and_addr(struct amdgpu_device *adev, case DRM_FORMAT_ABGR16161616: plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616; break; +#endif default: DRM_ERROR( "Unsupported screen format %p4cc\n", From c15d0efb1423d21e790147a2ca24c2a9e26b5d2a Mon Sep 17 00:00:00 2001 From: Yang Xiong Date: Mon, 6 Jul 2020 17:20:41 +0800 Subject: [PATCH 0280/1868] drm/amdkcl: fix build error of drm_atomic_get_new_crtc_state undefined This kcl patch is caused by patch: drm/amd/display: clip plane rects in DM before passing into DC Change-Id: I0932a38c7d28db411b721fcb6303cefed51d8674 Signed-off-by: Yang Xiong Reviewed-by: Flora Cui Signed-off-by: Ma Jun --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index cee20078bb422..5a2f4d6b5f81a 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -1247,9 +1247,9 @@ static int amdgpu_dm_plane_atomic_check(struct drm_plane *plane, if (!dm_plane_state->dc_state) return 0; - new_crtc_state = - drm_atomic_get_new_crtc_state(state, - new_plane_state->crtc); + new_crtc_state = kcl_drm_atomic_get_new_crtc_state_before_commit( + state, new_plane_state->crtc); + if (!new_crtc_state) return -EINVAL; From 4a11b51abe998dc5f3e2455a917571efc9745197 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 21 Mar 2024 11:24:49 +0800 Subject: [PATCH 0281/1868] drm/amdkcl: test whether struct drm_connector_state has hdcp_content_type This patch is caused by 'drm/amdkcl: Enable HDCP Build by default' Signed-off-by: Yang Xiong Reviewed-by: Flora Cui Acked-by: Bhawanpreet Lakha Change-Id: I4c9d082592f89270bcdc292b07cf9bdbfeb9f51b Signed-off-by: Asher Song --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 13 ++++++++++++- .../drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c | 4 ++++ .../m4/drm-connector-state-hdcp-content-type.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 34 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-connector-state-hdcp-content-type.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 044ada3e6d044..18672d394adff 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8276,7 +8276,11 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, drm_connector_attach_vrr_capable_property(&aconnector->base); if (adev->dm.hdcp_workqueue) +#ifdef HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE drm_connector_attach_content_protection_property(&aconnector->base, true); +#else + drm_connector_attach_content_protection_property(&aconnector->base); +#endif } } @@ -8539,6 +8543,7 @@ static bool is_content_protection_different(struct drm_crtc_state *new_crtc_stat new_crtc_state->active_changed, new_crtc_state->connectors_changed); +#ifdef HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE /* hdcp content type change */ if (old_conn_state->hdcp_content_type != new_conn_state->hdcp_content_type && new_conn_state->content_protection != DRM_MODE_CONTENT_PROTECTION_UNDESIRED) { @@ -8546,6 +8551,7 @@ static bool is_content_protection_different(struct drm_crtc_state *new_crtc_stat pr_debug("[HDCP_DM] Type0/1 change %s :true\n", __func__); return true; } +#endif /* CP is being re enabled, ignore this */ if (old_conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED && @@ -9922,7 +9928,12 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) if (aconnector->dc_link) hdcp_update_display( adev->dm.hdcp_workqueue, aconnector->dc_link->link_index, aconnector, - new_con_state->hdcp_content_type, enable_encryption); +#ifdef HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE + new_con_state->hdcp_content_type, +#else + DRM_MODE_HDCP_CONTENT_TYPE0, +#endif + enable_encryption); } } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c index e339c7a8d541c..59884dad8843b 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c @@ -336,6 +336,7 @@ static void event_property_update(struct work_struct *work) } if (hdcp_work->encryption_status[conn_index] != MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF) { +#ifdef HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE if (conn_state->hdcp_content_type == DRM_MODE_HDCP_CONTENT_TYPE0 && hdcp_work->encryption_status[conn_index] <= @@ -350,6 +351,9 @@ static void event_property_update(struct work_struct *work) drm_hdcp_update_content_protection(connector, DRM_MODE_CONTENT_PROTECTION_ENABLED); } +#else + drm_hdcp_update_content_protection(&aconnector->base, DRM_MODE_CONTENT_PROTECTION_ENABLED); +#endif } else { DRM_DEBUG_DRIVER("[HDCP_DM] DRM_MODE_CONTENT_PROTECTION_DESIRED\n"); drm_hdcp_update_content_protection(connector, diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-state-hdcp-content-type.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-state-hdcp-content-type.m4 new file mode 100644 index 0000000000000..6d852b75d9e05 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector-state-hdcp-content-type.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v5.3-rc1-377-g7672dbba85d3 +dnl # drm: Add Content protection type property +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_connector_state *state = NULL; + state->hdcp_content_type = 0; + ],[ + AC_DEFINE(HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE, 1, + [struct drm_connector_state has hdcp_content_type member]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 7aaa3648dee84..be33765bbfa57 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -117,6 +117,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_ADD_AFFECTED_DSC_CRTCS AC_AMDGPU_DRM_CONNECTOR_HAVE_HDR_SINK_METADATA AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_INIT + AC_AMDGPU_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 74e527cc53dada8454dfb68ccfd248af0daf0e7a Mon Sep 17 00:00:00 2001 From: Yang Xiong Date: Fri, 4 Sep 2020 21:45:09 +0800 Subject: [PATCH 0282/1868] drm/amdkcl: drm_device to amdgpu_device by inline-f This patch is caused by the following patche: drm/amdgpu: drm_device to amdgpu_device by inline-f (v2) Change-Id: If95bc03e61ac1f9431be788b7c3ab623e87db5a8 Signed-off-by: Yang Xiong Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 0fbd2bdd2df45..cc89cbbce1b6b 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -797,7 +797,7 @@ static void dm_dp_mst_hotplug(struct drm_dp_mst_topology_mgr *mgr) static void dm_dp_mst_register_connector(struct drm_connector *connector) { struct drm_device *dev = connector->dev; - struct amdgpu_device *adev = dev->dev_private; + struct amdgpu_device *adev = drm_to_adev(dev); #ifndef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_modeset_lock_all(dev); From 5e89c3b0ba8d8aedd6d416f0f6c2a56c1473b31d Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 12 May 2020 10:17:25 +0800 Subject: [PATCH 0283/1868] drm/amdkcl: test drm_crtc_funcs->gamma_set the history is: v4.11-rc5-1392-g6d124ff84533 drm: Add acquire ctx to ->gamma_set hook v4.7-rc1-260-g7ea772838782 drm/core: Change declaration for gamma_set. v4.5-rc3-706-g5488dc16fde7 drm: introduce pipe color correction propertie v2.6.35-260-g7203425a943e drm: expand gamma_set v2.6.28-8-gf453ba046074 DRM: add mode setting support It's a squash of drm/amdkcl: drop redundant test for drm_atomic_helper_legacy_gamma_set() Reviewed-by: Yang Xiong Signed-off-by: Flora Cui drm/amdkcl: [4.8] fix for drm_crtc_funcs->gamma_set Signed-off-by: Flora Cui Reviewed-by: Hawking Zhang Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang drm/amdkcl: TODO drop dead code in crtc->gamma_set Signed-off-by: Flora Cui Reviewed-by: Yang Xiong Signed-off-by: Flora Cui Acked-by: Rodrigo Siqueira Change-Id: I73df3ae59f010ff4431135aab5bd827af2f958d0 Signed-off-by: Yang Xiong --- drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 21 ++++++++ drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 21 ++++++++ drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 21 ++++++++ drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 21 ++++++++ .../drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 | 48 +++++++++++++++++++ 5 files changed, 132 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index 5d93201ac67da..88956fa3f2b8b 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -2526,6 +2526,12 @@ static void dce_v10_0_cursor_reset(struct drm_crtc *crtc) } } +/* + * TODO: drm_fb_helper_setcmap() prev commit v4.12-rc7-1385-g964c60063bff + * ("drm/fb-helper: separate the fb_setcmap helper into atomic and legacy paths") + * don't work as expected. + */ +#if defined(HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_6ARGS) static int dce_v10_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, u16 *blue, uint32_t size, struct drm_modeset_acquire_ctx *ctx) @@ -2534,6 +2540,21 @@ static int dce_v10_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, return 0; } +#elif defined(HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_5ARGS) +static int dce_v10_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, + u16 *blue, uint32_t size) +{ + dce_v10_0_crtc_load_lut(crtc); + + return 0; +} +#else +static void dce_v10_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, + u16 *blue, uint32_t start, uint32_t size) +{ + dce_v10_0_crtc_load_lut(crtc); +} +#endif static void dce_v10_0_crtc_destroy(struct drm_crtc *crtc) { diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index 710e822524309..c27a40f596c6e 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -2610,6 +2610,12 @@ static void dce_v11_0_cursor_reset(struct drm_crtc *crtc) } } +/* + * TODO: drm_fb_helper_setcmap() prev commit v4.12-rc7-1385-g964c60063bff + * ("drm/fb-helper: separate the fb_setcmap helper into atomic and legacy paths") + * don't work as expected. + */ +#if defined(HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_6ARGS) static int dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, u16 *blue, uint32_t size, struct drm_modeset_acquire_ctx *ctx) @@ -2618,6 +2624,21 @@ static int dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, return 0; } +#elif defined(HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_5ARGS) +static int dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, + u16 *blue, uint32_t size) +{ + dce_v11_0_crtc_load_lut(crtc); + + return 0; +} +#else +static void dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, + u16 *blue, uint32_t start, uint32_t size) +{ + dce_v11_0_crtc_load_lut(crtc); +} +#endif static void dce_v11_0_crtc_destroy(struct drm_crtc *crtc) { diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c index bc1155699dead..2c9be10e4f4c1 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c @@ -2453,6 +2453,12 @@ static void dce_v6_0_cursor_reset(struct drm_crtc *crtc) } } +/* + * TODO: drm_fb_helper_setcmap() prev commit v4.12-rc7-1385-g964c60063bff + * ("drm/fb-helper: separate the fb_setcmap helper into atomic and legacy paths") + * don't work as expected. + */ +#if defined(HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_6ARGS) static int dce_v6_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, u16 *blue, uint32_t size, struct drm_modeset_acquire_ctx *ctx) @@ -2461,6 +2467,21 @@ static int dce_v6_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, return 0; } +#elif defined(HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_5ARGS) +static int dce_v6_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, + u16 *blue, uint32_t size) +{ + dce_v6_0_crtc_load_lut(crtc); + + return 0; +} +#else +static void dce_v6_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, + u16 *blue, uint32_t start, uint32_t size) +{ + dce_v6_0_crtc_load_lut(crtc); +} +#endif static void dce_v6_0_crtc_destroy(struct drm_crtc *crtc) { diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index 26e464c18fea2..8ac78fc5e5dcb 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -2444,6 +2444,12 @@ static void dce_v8_0_cursor_reset(struct drm_crtc *crtc) } } +/* + * TODO: drm_fb_helper_setcmap() prev commit v4.12-rc7-1385-g964c60063bff + * ("drm/fb-helper: separate the fb_setcmap helper into atomic and legacy paths") + * don't work as expected. + */ +#if defined(HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_6ARGS) static int dce_v8_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, u16 *blue, uint32_t size, struct drm_modeset_acquire_ctx *ctx) @@ -2452,6 +2458,21 @@ static int dce_v8_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, return 0; } +#elif defined(HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_5ARGS) +static int dce_v8_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, + u16 *blue, uint32_t size) +{ + dce_v8_0_crtc_load_lut(crtc); + + return 0; +} +#else +static void dce_v8_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, + u16 *blue, uint32_t start, uint32_t size) +{ + dce_v8_0_crtc_load_lut(crtc); +} +#endif static void dce_v8_0_crtc_destroy(struct drm_crtc *crtc) { diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 index 211d8df287f57..ec6c920089ae1 100644 --- a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 @@ -114,10 +114,58 @@ AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GET_VERIFY_CRC_SOURCES], [ ]) ]) +dnl # +dnl # v4.11-rc5-1392-g6d124ff84533 drm: Add acquire ctx to ->gamma_set hook +dnl # int (*gamma_set)(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, +dnl # - uint32_t size); +dnl # + uint32_t size, +dnl # + struct drm_modeset_acquire_ctx *ctx); +dnl # v4.7-rc1-260-g7ea772838782 drm/core: Change declaration for gamma_set. +dnl # - void (*gamma_set)(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, +dnl # - uint32_t start, uint32_t size); +dnl # + int (*gamma_set)(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, +dnl # + uint32_t size); +dnl # v2.6.35-260-g7203425a943e drm: expand gamma_set +dnl # void (*gamma_set)(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, +dnl # - uint32_t size); +dnl # + uint32_t start, uint32_t size); +dnl # v2.6.28-8-gf453ba046074 DRM: add mode setting support +dnl # + void (*gamma_set)(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, +dnl # + uint32_t size); +dnl # +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_crtc *crtc = NULL; + int ret; + + ret = crtc->funcs->gamma_set(NULL, NULL, NULL, NULL, 0, NULL); + ], [ + AC_DEFINE(HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_6ARGS, 1, + [crtc->funcs->gamma_set() wants 6 args]) + ], [ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_crtc *crtc = NULL; + int ret; + + ret = crtc->funcs->gamma_set(NULL, NULL, NULL, NULL, 0); + ], [ + AC_DEFINE(HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_5ARGS, 1, + [crtc->funcs->gamma_set() wants 5 args]) + ]) + ]) + ]) +]) + AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS], [ AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_ENABLE_VBLANK AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GET_VERIFY_CRC_SOURCES AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_SET_CONFIG AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET + AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET ]) From 30f363a13e891f52a595b20bb441f4dacd7aeb59 Mon Sep 17 00:00:00 2001 From: changzhu Date: Fri, 9 Aug 2019 11:06:58 +0800 Subject: [PATCH 0284/1868] drm/amdkcl: Test whether whether drm_dp_mst_connector_{early_unregister,late_register} are available Rebase 5.3 squash: * 600691173f87 drm/amd/autoconf: Test whether drm_dp_mst_connector_late_register is available * 8baafc6b96b7 drm/amd/autoconf: Test whether whether drm_dp_mst_connector_early_unregister is available Change-Id: I8d5367bf7adf47083cb0c050a9b01b1b5145614f Signed-off-by: Adam Yang Signed-off-by: changzhu Reviewed-by: Leo Li Reviewed-by: Slava Grigorev Signed-off-by: Jack Gui --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index cc89cbbce1b6b..b36df52efae07 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -153,6 +153,7 @@ dm_dp_mst_connector_destroy(struct drm_connector *connector) kfree(aconnector); } +#if defined(HAVE_DRM_DP_MST_CONNECTOR_LATE_REGISTER) static int amdgpu_dm_mst_connector_late_register(struct drm_connector *connector) { @@ -171,7 +172,9 @@ amdgpu_dm_mst_connector_late_register(struct drm_connector *connector) return 0; } +#endif /* HAVE_DRM_DP_MST_CONNECTOR_LATE_REGISTER */ +#if defined(HAVE_DRM_DP_MST_CONNECTOR_EARLY_UNREGISTER) static void amdgpu_dm_mst_connector_early_unregister(struct drm_connector *connector) { @@ -207,6 +210,7 @@ amdgpu_dm_mst_connector_early_unregister(struct drm_connector *connector) aconnector->mst_status = MST_STATUS_DEFAULT; drm_modeset_unlock(&root->mst_mgr.base.lock); } +#endif /* HAVE_DRM_DP_MST_CONNECTOR_EARLY_UNREGISTER */ static const struct drm_connector_funcs dm_dp_mst_connector_funcs = { #ifndef HAVE_DRM_DP_MST_DETECT_PORT_PPPP @@ -219,8 +223,12 @@ static const struct drm_connector_funcs dm_dp_mst_connector_funcs = { .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, .atomic_set_property = amdgpu_dm_connector_atomic_set_property, .atomic_get_property = amdgpu_dm_connector_atomic_get_property, +#if defined(HAVE_DRM_DP_MST_CONNECTOR_LATE_REGISTER) .late_register = amdgpu_dm_mst_connector_late_register, +#endif /* HAVE_DRM_DP_MST_CONNECTOR_LATE_REGISTER */ +#if defined(HAVE_DRM_DP_MST_CONNECTOR_EARLY_UNREGISTER) .early_unregister = amdgpu_dm_mst_connector_early_unregister, +#endif /* HAVE_DRM_DP_MST_CONNECTOR_EARLY_UNREGISTER */ }; bool needs_dsc_aux_workaround(struct dc_link *link) From e2d0ff92f2fe9ee5f5a4af170f865f01130270ba Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Mon, 12 Oct 2020 15:02:05 +0800 Subject: [PATCH 0285/1868] drm/amdkcl: DCN301 backport for DC This is caused by "Add dcn3.01 support to DC" v5.9-rc2-568-g94e09bdc1c96 v1: enable DCN301 for DKMS build v2: guard the DSC related code under the macro CONFIG_DRM_AMD_DC_DSC_SUPPORT v3: fix the SSE build error for floating operation v4: remove the unnecessary depends for Kconfig Signed-off-by: Shiwu Zhang Reviewed-by: Yang Xiong --- .../display/dc/dio/dcn301/dcn301_dio_link_encoder.c | 2 ++ .../drm/amd/display/dc/hwss/dcn301/dcn301_init.c | 2 ++ .../display/dc/resource/dcn301/dcn301_resource.c | 13 ++++++++++++- 3 files changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.c index 1b39a6e8a1ac5..100953da7bc48 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.c @@ -48,7 +48,9 @@ (enc10->link_regs->index) static const struct link_encoder_funcs dcn301_link_enc_funcs = { +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .read_state = link_enc2_read_state, +#endif .validate_output_with_stream = dcn10_link_encoder_validate_output_with_stream, .hw_init = enc3_hw_init, .setup = dcn10_link_encoder_setup, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c index 93e49d87a67ce..723fff4b8ac0b 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c @@ -135,7 +135,9 @@ static const struct hwseq_private_funcs dcn301_private_funcs = { .hubp_pg_control = dcn20_hubp_pg_control, .program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree, .update_odm = dcn20_update_odm, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .dsc_pg_control = dcn20_dsc_pg_control, +#endif .set_hdr_multiplier = dcn10_set_hdr_multiplier, .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high, .wait_for_blank_complete = dcn20_wait_for_blank_complete, diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c index 7d04739c3ba14..c3653c6e878a4 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c @@ -47,7 +47,9 @@ #include "dcn30/dcn30_hwseq.h" #include "dce110/dce110_hwseq.h" #include "dcn30/dcn30_opp.h" +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include "dcn20/dcn20_dsc.h" +#endif #include "dcn30/dcn30_vpg.h" #include "dcn30/dcn30_afmt.h" #include "dce/dce_clock_source.h" @@ -489,6 +491,7 @@ static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) }; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #define dsc_regsDCN20(id)\ [id] = {\ DSC_REG_LIST_DCN20(id)\ @@ -507,6 +510,7 @@ static const struct dcn20_dsc_shift dsc_shift = { static const struct dcn20_dsc_mask dsc_mask = { DSC_REG_LIST_SH_MASK_DCN20(_MASK) }; +#endif static const struct dcn30_mpc_registers mpc_regs = { MPC_REG_LIST_DCN3_0(0), @@ -648,7 +652,9 @@ static struct resource_caps res_cap_dcn301 = { .num_ddc = 4, .num_vmid = 16, .num_mpc_3dlut = 2, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .num_dsc = 3, +#endif }; static const struct dc_plane_cap plane_cap = { @@ -1053,10 +1059,12 @@ static void dcn301_destruct(struct dcn301_resource_pool *pool) } } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } +#endif if (pool->base.mpc != NULL) { kfree(TO_DCN20_MPC(pool->base.mpc)); @@ -1223,6 +1231,7 @@ static bool dcn301_mmhubbub_create(struct dc_context *ctx, struct resource_pool return true; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static struct display_stream_compressor *dcn301_dsc_create( struct dc_context *ctx, uint32_t inst) { @@ -1237,7 +1246,7 @@ static struct display_stream_compressor *dcn301_dsc_create( dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); return &dsc->base; } - +#endif static void dcn301_destroy_resource_pool(struct resource_pool **pool) { @@ -1652,6 +1661,7 @@ static bool dcn301_resource_construct( goto create_fail; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { pool->base.dscs[i] = dcn301_dsc_create(ctx, i); if (pool->base.dscs[i] == NULL) { @@ -1660,6 +1670,7 @@ static bool dcn301_resource_construct( goto create_fail; } } +#endif /* DWB and MMHUBBUB */ if (!dcn301_dwbc_create(ctx, &pool->base)) { From f51b4797d9a2819e86a058b29940a413d7b7ac18 Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Mon, 19 Oct 2020 14:57:24 +0800 Subject: [PATCH 0286/1868] drm/amdkcl: DCN302 backport for DC This is caused by "Add support for DCN302 (v2)" v5.9-rc2-689-gbe0899b1f9f0 Signed-off-by: Shiwu Zhang Reviewed-by: Flora Cui --- .../drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c | 2 ++ .../drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.h | 2 ++ .../gpu/drm/amd/display/dc/hwss/dcn302/dcn302_init.c | 2 ++ .../amd/display/dc/resource/dcn302/dcn302_resource.c | 12 ++++++++++++ 4 files changed, 18 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c index 0a6d58dd8f6da..40fad52521647 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c @@ -156,6 +156,7 @@ void dcn302_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool } } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void dcn302_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on) { uint32_t power_gate = power_on ? 0 : 1; @@ -221,3 +222,4 @@ void dcn302_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool po if (org_ip_request_cntl == 0) REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); } +#endif diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.h index 1e5126a0e695d..6317b4a0f363e 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.h @@ -30,6 +30,8 @@ void dcn302_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on); void dcn302_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on); +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void dcn302_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on); +#endif #endif /* __DC_HWSS_DCN302_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_init.c index 637f9514d37b2..1602be017597a 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_init.c @@ -37,5 +37,7 @@ void dcn302_hw_sequencer_construct(struct dc *dc) dc->hwseq->funcs.dpp_pg_control = dcn302_dpp_pg_control; dc->hwseq->funcs.hubp_pg_control = dcn302_hubp_pg_control; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT dc->hwseq->funcs.dsc_pg_control = dcn302_dsc_pg_control; +#endif } diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c index 5791b5cc28752..00995cd380fe7 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c @@ -40,7 +40,9 @@ #include "dcn30/dcn30_optc.h" #include "dcn30/dcn30_resource.h" +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include "dcn20/dcn20_dsc.h" +#endif #include "dcn20/dcn20_resource.h" #include "dml/dcn30/dcn30_fpu.h" @@ -129,7 +131,9 @@ static const struct resource_caps res_cap_dcn302 = { .num_ddc = 5, .num_vmid = 16, .num_mpc_3dlut = 2, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .num_dsc = 5, +#endif }; static const struct dc_plane_cap plane_cap = { @@ -658,6 +662,7 @@ static struct mpc *dcn302_mpc_create(struct dc_context *ctx, int num_mpcc, int n return &mpc30->base; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #define dsc_regsDCN20(id)\ [id] = { DSC_REG_LIST_DCN20(id) } @@ -689,6 +694,7 @@ static struct display_stream_compressor *dcn302_dsc_create(struct dc_context *ct dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); return &dsc->base; } +#endif #define dwbc_regs_dcn3(id)\ [id] = { DWBC_COMMON_REG_LIST_DCN30(id) } @@ -1004,10 +1010,12 @@ static void dcn302_resource_destruct(struct resource_pool *pool) } } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->res_cap->num_dsc; i++) { if (pool->dscs[i] != NULL) dcn20_dsc_destroy(&pool->dscs[i]); } +#endif if (pool->mpc != NULL) { kfree(TO_DCN20_MPC(pool->mpc)); @@ -1142,7 +1150,9 @@ static struct resource_funcs dcn302_res_pool_funcs = { .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, .add_stream_to_ctx = dcn30_add_stream_to_ctx, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, +#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, .set_mcif_arb_params = dcn30_set_mcif_arb_params, @@ -1428,6 +1438,7 @@ static bool dcn302_resource_construct( goto create_fail; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->res_cap->num_dsc; i++) { pool->dscs[i] = dcn302_dsc_create(ctx, i); if (pool->dscs[i] == NULL) { @@ -1436,6 +1447,7 @@ static bool dcn302_resource_construct( goto create_fail; } } +#endif /* DWB and MMHUBBUB */ if (!dcn302_dwbc_create(ctx, pool)) { From 4cf354a146facff8a9791fa5a164e2ad42dc1b87 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 16 Oct 2020 13:55:40 +0800 Subject: [PATCH 0287/1868] drm/amdkcl: update config checks with _is_kcl_macro_defined Signed-off-by: Flora Cui Reviewed-by: shiwu.zhang --- drivers/gpu/drm/amd/dkms/Makefile | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 25f48546e8d01..26cce7ae2a0cb 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -12,7 +12,7 @@ endif _is_kcl_macro_defined=$(shell grep $1 $(src)/amd/dkms/config/config.h | grep -q "define" && echo "y" || echo "n") -ifeq ($(shell grep "HAVE_DMA_RESV_SEQ" $(src)/amd/dkms/config/config.h | grep -q "define" && echo "y" || echo "n"),n) +ifeq ($(call _is_kcl_macro_defined,HAVE_DMA_RESV_SEQ),n) $(error dma_resv->seq is missing., exit...) endif @@ -156,10 +156,8 @@ subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_USERPTR subdir-ccflags-y += -DCONFIG_DRM_AMD_DC subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN1_0 -ifeq ($(shell grep "HAVE_DRM_DRM_HDCP_H" $(src)/amd/dkms/config/config.h | grep -q "define" && echo "y" || echo "n"),y) export CONFIG_DRM_AMD_DC_HDCP=y subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_HDCP -endif # Trying to enable DCN2/3 with core2 optimizations will result in # older versions of GCC hanging during building/installing. Check From c88613798544c152229b06d85a3c1de8a4498b2e Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 2 Oct 2020 12:48:30 +0800 Subject: [PATCH 0288/1868] drm/amdkcl: drop test for DRIVER_ATOMIC DRIVER_ATOMIC is introduced in v3.18-1050-g88a48e297b3a Signed-off-by: Flora Cui Reviewed-by: Shiwu Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 -- .../gpu/drm/amd/dkms/m4/drm-driver-feature.m4 | 22 ++----------------- 2 files changed, 2 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index f011190a0a007..63a314daf81b8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2331,7 +2331,6 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, kcl_drm_vma_offset_manager_init(ddev->vma_offset_manager); -#ifdef HAVE_DRM_DRV_DRIVER_ATOMIC #ifdef HAVE_DRM_DEVICE_DRIVER_FEATURES if (!supports_atomic) ddev->driver_features &= ~DRIVER_ATOMIC; @@ -2342,7 +2341,6 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, /* support atomic early so the atomic debugfs stuff gets created */ if (supports_atomic) kms_driver.driver_features |= DRIVER_ATOMIC; -#endif #endif kcl_pci_configure_extended_tags(pdev); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-driver-feature.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-driver-feature.m4 index 3afe53a169b8c..0970897b2338a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-driver-feature.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-driver-feature.m4 @@ -1,28 +1,10 @@ dnl # -dnl # commit 88a48e297b3a3bac6022c03babfb038f1a886cea -dnl # drm: add atomic properties dnl # commit 0e2a933b02c972919f7478364177eb76cd4ae00d dnl # drm: Switch DRIVER_ flags to an enum dnl # AC_DEFUN([AC_AMDGPU_DRM_DRIVER_FEATURE], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drmP.h], [ - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - int _ = DRIVER_ATOMIC; - ], [ - AC_DEFINE(HAVE_DRM_DRV_DRIVER_ATOMIC, 1, [ - drm_driver_feature DRIVER_ATOMIC is available]) - ]) - ], [ - AC_DEFINE(HAVE_DRM_DRV_DRIVER_ATOMIC, 1, [ - drm_driver_feature DRIVER_ATOMIC is available]) - ]) - ]) - dnl # - dnl # commit: 060cebb20cdbcd3185d593e7194fa7a738201817 + dnl # commit: v5.1-rc5-1467-g060cebb20cdb dnl # drm: introduce a capability flag for syncobj timeline support dnl # AC_KERNEL_DO_BACKGROUND([ @@ -42,7 +24,7 @@ AC_DEFUN([AC_AMDGPU_DRM_DRIVER_FEATURE], [ ]) dnl # - dnl # commit: 1ff494813bafa127ecba1160262ba39b2fdde7ba + dnl # commit: v5.0-rc1-390-g1ff494813baf dnl # drm/irq: Ditch DRIVER_IRQ_SHARED dnl # AC_KERNEL_DO_BACKGROUND([ From 7971c1705062e844c2790245399ec28ff16d4251 Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Tue, 3 Nov 2020 15:47:44 +0800 Subject: [PATCH 0289/1868] drm/amdkcl: use the kcl wrapper for get/set gem object This is caused by "Store tiling_flags in the framebuffer" v5.9-rc5-1363-gdd3cc8e45355 Signed-off-by: Shiwu Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 453aae4d35437..dffe1f2dcf524 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1404,7 +1404,7 @@ static int amdgpu_display_get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb return 0; } - rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]); + rbo = gem_to_amdgpu_bo(drm_gem_fb_get_obj(&amdgpu_fb->base, 0)); r = amdgpu_bo_reserve(rbo, false); if (unlikely(r)) { From c182e247de8197d91e6a7d45e9d7b5a42ec1d2f7 Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Mon, 16 Nov 2020 21:08:17 +0800 Subject: [PATCH 0290/1868] drm/amdkcl: access drm_mm in ttm mem manager by memory type for centos7.3 and 7.4 backport This is caused by "drop priv pointer in memory manager" v5.8-rc2-636-g7ee6c95e05e9 v2: use the static inline function instead Signed-off-by: Shiwu Zhang Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/backport/backport.h | 1 + .../amd/backport/include/kcl/kcl_amdgpu_ttm.h | 26 +++++++++++++++++++ 2 files changed, 27 insertions(+) create mode 100644 drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_ttm.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index b12907b57f7c0..802029996d2ac 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -51,6 +51,7 @@ #include #include #include +#include "kcl/kcl_amdgpu_ttm.h" #include #include "kcl/kcl_amdgpu_drm_fb_helper.h" #include "kcl/kcl_amdgpu.h" diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_ttm.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_ttm.h new file mode 100644 index 0000000000000..1c4be1340422f --- /dev/null +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_ttm.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef AMDGPU_BACKPORT_KCL_AMDGPU_TTM_H +#define AMDGPU_BACKPORT_KCL_AMDGPU_TTM_H +#include +#include +#include +#include "amdgpu.h" +#include "amdgpu_ttm.h" + +#if !defined(HAVE_DRM_MM_PRINT) +extern struct drm_mm *kcl_ttm_range_res_manager_to_drm_mm(struct ttm_resource_manager *man); + +static inline struct drm_mm *kcl_ttm_get_drm_mm_by_mem_type(struct amdgpu_device *adev, unsigned char ttm_pl) +{ + if (ttm_pl == TTM_PL_TT) { + return &(adev->mman.gtt_mgr.mm); + } else if (ttm_pl == TTM_PL_VRAM) { + return &(adev->mman.vram_mgr.mm); + } else { + struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, ttm_pl); + return kcl_ttm_range_res_manager_to_drm_mm(man); + } +} +#endif + +#endif /* AMDGPU_BACKPORT_KCL_AMDGPU_TTM_H */ From d9aa0a80cafcd3dbd85dcf15300c64a7c0e50592 Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Tue, 24 Nov 2020 16:58:39 +0800 Subject: [PATCH 0291/1868] drm/amdkcl: fake the func of timestamping calculation This is caused by "Always get CRTC updated constant values inside commit tail" v5.9-rc5-1644-gea29955035a6 This is a squash of: drm/amdkcl: call legacy update only for backport This is caused by "Remove the timestamping constant update from drm_atomic_helper_update_legacy_modeset_state()" v5.9-rc5-1595-ge1ad957d45f7 Signed-off-by: Shiwu Zhang Reviewed-by: Flora Cui --- .../drm/amd/amdkcl/kcl_drm_atomic_helper.c | 28 +++++++++++++++++++ ...omic_helper_calc_timestamping_constants.m4 | 13 +++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_atomic_helper.h | 4 +++ 4 files changed, 46 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_atomic_helper_calc_timestamping_constants.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c index 4ef77c1846213..3e2cf46b8526c 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c @@ -27,6 +27,7 @@ */ #include #include +#include #ifdef AMDKCL__DRM_ATOMIC_HELPER_PLANE_RESET void _kcl__drm_atomic_helper_plane_reset(struct drm_plane *plane, @@ -59,3 +60,30 @@ __drm_atomic_helper_crtc_reset(struct drm_crtc *crtc, } EXPORT_SYMBOL(__drm_atomic_helper_crtc_reset); #endif + +#ifndef HAVE_DRM_ATOMIC_HELPER_CALC_TIMESTAMPING_CONSTANTS +/* + * This implementation is duplicated from v5.9-rc5-1595-ge1ad957d45f7 + * "Extract drm_atomic_helper_calc_timestamping_constants()" + * + */ +void drm_atomic_helper_calc_timestamping_constants(struct drm_atomic_state *state) +{ + struct drm_device *dev = state->dev; + struct drm_crtc_state *new_crtc_state; + struct drm_crtc *crtc; + int i; + +#if !defined(for_each_new_crtc_in_state) + list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { + new_crtc_state = crtc->state; +#else + for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { +#endif + if (new_crtc_state->enable) + drm_calc_timestamping_constants(crtc, + &new_crtc_state->adjusted_mode); + } +} +EXPORT_SYMBOL(drm_atomic_helper_calc_timestamping_constants); +#endif diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_atomic_helper_calc_timestamping_constants.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_atomic_helper_calc_timestamping_constants.m4 new file mode 100644 index 0000000000000..79ab39b5802f3 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_atomic_helper_calc_timestamping_constants.m4 @@ -0,0 +1,13 @@ +dnl # +dnl # v5.9-rc5-1595-ge1ad957d45f7 +dnl # Extract drm_atomic_helper_calc_timestamping_constants() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_ATOMIC_HELPER_CALC_TIMESTAMPING_CONSTANTS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([drm_atomic_helper_calc_timestamping_constants], + [drivers/gpu/drm/drm_atomic_helper.c], [ + AC_DEFINE(HAVE_DRM_ATOMIC_HELPER_CALC_TIMESTAMPING_CONSTANTS, 1, + [drm_atomic_helper_calc_timestamping_constants() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index be33765bbfa57..d7ffe4cc177c3 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -82,6 +82,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_JIFFIES64_TO_MSECS AC_AMDGPU___PRINT_ARRAY AC_AMDGPU_ACPI_PUT_TABLE + AC_AMDGPU_DRM_ATOMIC_HELPER_CALC_TIMESTAMPING_CONSTANTS AC_AMDGPU_DRM_DEV_DBG AC_AMDGPU_PCI_PR3_PRESENT AC_AMDGPU_KTHREAD_USE_MM diff --git a/include/kcl/kcl_drm_atomic_helper.h b/include/kcl/kcl_drm_atomic_helper.h index cb5c49c24cb94..208a5e9edf330 100644 --- a/include/kcl/kcl_drm_atomic_helper.h +++ b/include/kcl/kcl_drm_atomic_helper.h @@ -49,4 +49,8 @@ void __drm_atomic_helper_crtc_reset(struct drm_crtc *crtc, struct drm_crtc_state *crtc_state); #endif +#ifndef HAVE_DRM_ATOMIC_HELPER_CALC_TIMESTAMPING_CONSTANTS +void drm_atomic_helper_calc_timestamping_constants(struct drm_atomic_state *state); +#endif + #endif From 7dbac2b77501dcd46cb3a9129c26d679c6823a9c Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Tue, 17 Nov 2020 16:48:12 +0800 Subject: [PATCH 0292/1868] drm/amdkcl: disable modifier support for DRM before 5.0 This is caused by "Add formats for DCC with 2/3 planes" and "Expose modifiers" v5.9-rc5-1367-g564b9f4c7cf9 and v5.9-rc5-1368-g86ce3ed796ff This is a squash of: drm/amdkcl: fix license for kcl drm part Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling drm/amdkcl: guard the modifier code for backport This is caused by "Store gem objects for planes 1-3" v5.9-rc5-1565-gbf01c77ad320 Signed-off-by: Shiwu Zhang Reviewed-by: Bhawanpreet Lakha drm/amdkcl: update the AMD modifer macros This is caused by "Fix modifier field mask for AMD modifiers", "add table describing AMD modifiers bit layout", "fix AMD modifiers PACKERS field doc" v5.9-rc5-1563-g80363c69ca44, v5.9-rc5-1564-gbac8bece9c55 and v5.9-rc5-1594-g11e500d2892a Signed-off-by: Shiwu Zhang drm/amdkcl: fix the config.h mismatch for autotest and regenerate the config.h Signed-off-by: Shiwu Zhang drm/amdkcl: disable modifier feature if Floating point 64bpp RGB format is not defined This is to avoid warning printing during modprobe on the OS like rhel 7.9 Signed-off-by: Shiwu Zhang Signed-off-by: Shiwu Zhang Reviewed-by: Flora Cui Reviewed-by: Bhawanpreet Lakha Signed-off-by: Ma Jun Change-Id: If9ccae068c5b8cf3f475fa8c178b5d3135a9b84a --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 6 + drivers/gpu/drm/amd/backport/backport.h | 1 + .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 + .../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 10 + .../gpu/drm/amd/dkms/m4/drm_format_info.m4 | 20 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 13 +- include/kcl/kcl_drm_fourcc.h | 217 ++++++++++++++++++ 7 files changed, 263 insertions(+), 6 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_format_info.m4 create mode 100644 include/kcl/kcl_drm_fourcc.h diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index dffe1f2dcf524..74f6c3ba2320b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -978,6 +978,7 @@ static int convert_tiling_flags_to_modifier_gfx12(struct amdgpu_framebuffer *afb return 0; } +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb) { struct amdgpu_device *adev = drm_to_adev(afb->base.dev); @@ -1171,6 +1172,7 @@ static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb) afb->base.flags |= DRM_MODE_FB_MODIFIERS; return 0; } +#endif /* Mirrors the is_displayable check in radeonsi's gfx6_compute_surface */ static int check_tiling_flags_gfx6(struct amdgpu_framebuffer *afb) @@ -1476,6 +1478,7 @@ static int amdgpu_display_framebuffer_init(struct drm_device *dev, * This needs to happen before modifier conversion as that might change * the number of planes. */ +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED for (i = 1; i < rfb->base.format->num_planes; ++i) { if (mode_cmd->handles[i] != mode_cmd->handles[0]) { drm_dbg_kms(dev, "Plane 0 and %d have different BOs: %u vs. %u\n", @@ -1484,12 +1487,14 @@ static int amdgpu_display_framebuffer_init(struct drm_device *dev, return ret; } } +#endif ret = amdgpu_display_get_fb_info(rfb, &rfb->tiling_flags, &rfb->tmz_surface, &rfb->gfx12_dcc); if (ret) return ret; +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED if (dev->mode_config.fb_modifiers_not_supported && !adev->enable_virtual_display) { drm_WARN_ONCE(dev, adev->family >= AMDGPU_FAMILY_AI, "GFX9+ requires FB check based on format modifier\n"); @@ -1520,6 +1525,7 @@ static int amdgpu_display_framebuffer_init(struct drm_device *dev, drm_gem_object_get(rfb->base.obj[0]); rfb->base.obj[i] = rfb->base.obj[0]; } +#endif return 0; } diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 802029996d2ac..08d61f40a3eb4 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -53,6 +53,7 @@ #include #include "kcl/kcl_amdgpu_ttm.h" #include +#include #include "kcl/kcl_amdgpu_drm_fb_helper.h" #include "kcl/kcl_amdgpu.h" #include "kcl/kcl_amdgpu_drm_drv.h" diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 18672d394adff..7e603b155f8ce 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3423,7 +3423,9 @@ dm_atomic_state_alloc_free(struct drm_atomic_state *state) static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = { .fb_create = amdgpu_display_user_framebuffer_create, +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED .get_format_info = amdgpu_dm_plane_get_format_info, +#endif .atomic_check = amdgpu_dm_atomic_check, .atomic_commit = drm_atomic_helper_commit, #ifndef HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 5a2f4d6b5f81a..3a6ba5078d688 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -162,10 +162,12 @@ static void amdgpu_dm_plane_add_modifier(uint64_t **mods, uint64_t *size, uint64 *size += 1; } +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED static bool amdgpu_dm_plane_modifier_has_dcc(uint64_t modifier) { return IS_AMD_FMT_MOD(modifier) && AMD_FMT_MOD_GET(DCC, modifier); } +#endif static unsigned int amdgpu_dm_plane_modifier_gfx9_swizzle_mode(uint64_t modifier) { @@ -301,6 +303,7 @@ static int amdgpu_dm_plane_validate_dcc(struct amdgpu_device *adev, return 0; } +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED static int amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers(struct amdgpu_device *adev, const struct amdgpu_framebuffer *afb, const enum surface_pixel_format format, @@ -351,6 +354,7 @@ static int amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers(struct amdg return ret; } +#endif static int amdgpu_dm_plane_fill_gfx12_plane_attributes_from_modifiers(struct amdgpu_device *adev, const struct amdgpu_framebuffer *afb, @@ -918,6 +922,7 @@ int amdgpu_dm_plane_fill_plane_buffer_attributes(struct amdgpu_device *adev, if (ret) return ret; } else if (adev->family >= AMDGPU_FAMILY_AI) { +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED ret = amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers(adev, afb, format, rotation, plane_size, tiling_info, dcc, @@ -925,6 +930,7 @@ int amdgpu_dm_plane_fill_plane_buffer_attributes(struct amdgpu_device *adev, force_disable_dcc); if (ret) return ret; +#endif } else { amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags(tiling_info, tiling_flags); } @@ -1772,7 +1778,9 @@ static const struct drm_plane_funcs dm_plane_funcs = { .reset = amdgpu_dm_plane_drm_plane_reset, .atomic_duplicate_state = amdgpu_dm_plane_drm_plane_duplicate_state, .atomic_destroy_state = amdgpu_dm_plane_drm_plane_destroy_state, +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED .format_mod_supported = amdgpu_dm_plane_format_mod_supported, +#endif #ifdef AMD_PRIVATE_COLOR .atomic_set_property = dm_atomic_plane_set_property, .atomic_get_property = dm_atomic_plane_get_property, @@ -1794,9 +1802,11 @@ int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, num_formats = amdgpu_dm_plane_get_plane_formats(plane, plane_cap, formats, ARRAY_SIZE(formats)); +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED res = amdgpu_dm_plane_get_plane_modifiers(dm->adev, plane->type, &modifiers); if (res) return res; +#endif if (modifiers == NULL) adev_to_drm(dm->adev)->mode_config.fb_modifiers_not_supported = true; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_format_info.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_format_info.m4 new file mode 100644 index 0000000000000..95a45563d402e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_format_info.m4 @@ -0,0 +1,20 @@ +dnl # +dnl # v5.9-rc5-1367-g564b9f4c7cf9 +dnl # drm/amd/display: Add formats for DCC with 2/3 planes +dnl # +AC_DEFUN([AC_AMDGPU_DRM_FORMAT_INFO], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_format_info format = { + .format = DRM_FORMAT_XRGB16161616F, + .block_w = {0}, + .block_h = {0}, + }; + ], [ + AC_DEFINE(HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED, 1, + [drm_format_info.block_w and rm_format_info.block_h is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index d7ffe4cc177c3..493caf84cbfba 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -77,12 +77,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_STRUCT_DRM_DEVICE AC_AMDGPU_DRM_DRIVER_FEATURE AC_AMDGPU___DRM_ATOMIC_HELPER_CRTC_RESET - AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION - AC_AMDGPU_MEM_ENCRYPT_ACTIVE - AC_AMDGPU_JIFFIES64_TO_MSECS - AC_AMDGPU___PRINT_ARRAY - AC_AMDGPU_ACPI_PUT_TABLE - AC_AMDGPU_DRM_ATOMIC_HELPER_CALC_TIMESTAMPING_CONSTANTS AC_AMDGPU_DRM_DEV_DBG AC_AMDGPU_PCI_PR3_PRESENT AC_AMDGPU_KTHREAD_USE_MM @@ -119,6 +113,13 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_HAVE_HDR_SINK_METADATA AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_INIT AC_AMDGPU_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE + AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION + AC_AMDGPU_MEM_ENCRYPT_ACTIVE + AC_AMDGPU_JIFFIES64_TO_MSECS + AC_AMDGPU___PRINT_ARRAY + AC_AMDGPU_ACPI_PUT_TABLE + AC_AMDGPU_DRM_ATOMIC_HELPER_CALC_TIMESTAMPING_CONSTANTS + AC_AMDGPU_DRM_FORMAT_INFO AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_fourcc.h b/include/kcl/kcl_drm_fourcc.h new file mode 100644 index 0000000000000..25cf40f897b23 --- /dev/null +++ b/include/kcl/kcl_drm_fourcc.h @@ -0,0 +1,217 @@ +/* + * Copyright 2011 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef KCL_KCL_DRM_FOURCC_H +#define KCL_KCL_DRM_FOURCC_H + +#include + +/* Copied from include/uapi/drm/drm_fourcc.h */ +/* + * Linear Layout + * + * Just plain linear layout. Note that this is different from no specifying any + * modifier (e.g. not setting DRM_MODE_FB_MODIFIERS in the DRM_ADDFB2 ioctl), + * which tells the driver to also take driver-internal information into account + * and so might actually result in a tiled framebuffer. + */ +#if !defined(DRM_FORMAT_MOD_VENDOR_NONE) +#define DRM_FORMAT_MOD_VENDOR_NONE 0 +#endif + +#if !defined(DRM_FORMAT_MOD_LINEAR) +#define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0) +#endif + +#if !defined(DRM_FORMAT_RESERVED) +#define DRM_FORMAT_RESERVED ((1ULL << 56) - 1) +#endif +/* + * * Invalid Modifier + * * + * * This modifier can be used as a sentinel to terminate the format modifiers + * * list, or to initialize a variable with an invalid modifier. It might also be + * * used to report an error back to userspace for certain APIs. + * */ +#if !defined(DRM_FORMAT_MOD_INVALID) +#define DRM_FORMAT_MOD_INVALID fourcc_mod_code(NONE, DRM_FORMAT_RESERVED) +#endif + +/* + * AMD modifiers + * + * Memory layout: + * + * without DCC: + * - main surface + * + * with DCC & without DCC_RETILE: + * - main surface in plane 0 + * - DCC surface in plane 1 (RB-aligned, pipe-aligned if DCC_PIPE_ALIGN is set) + * + * with DCC & DCC_RETILE: + * - main surface in plane 0 + * - displayable DCC surface in plane 1 (not RB-aligned & not pipe-aligned) + * - pipe-aligned DCC surface in plane 2 (RB-aligned & pipe-aligned) + * + * For multi-plane formats the above surfaces get merged into one plane for + * each format plane, based on the required alignment only. + * + * Bits Parameter Notes + * ----- ------------------------ --------------------------------------------- + * + * 7:0 TILE_VERSION Values are AMD_FMT_MOD_TILE_VER_* + * 12:8 TILE Values are AMD_FMT_MOD_TILE__* + * 13 DCC + * 14 DCC_RETILE + * 15 DCC_PIPE_ALIGN + * 16 DCC_INDEPENDENT_64B + * 17 DCC_INDEPENDENT_128B + * 19:18 DCC_MAX_COMPRESSED_BLOCK Values are AMD_FMT_MOD_DCC_BLOCK_* + * 20 DCC_CONSTANT_ENCODE + * 23:21 PIPE_XOR_BITS Only for some chips + * 26:24 BANK_XOR_BITS Only for some chips + * 29:27 PACKERS Only for some chips + * 32:30 RB Only for some chips + * 35:33 PIPE Only for some chips + * 55:36 - Reserved for future use, must be zero + */ + +#if !defined(AMD_FMT_MOD) +#define AMD_FMT_MOD fourcc_mod_code(AMD, 0) + +#define IS_AMD_FMT_MOD(val) (((val) >> 56) == DRM_FORMAT_MOD_VENDOR_AMD) + +/* Reserve 0 for GFX8 and older */ +#define AMD_FMT_MOD_TILE_VER_GFX9 1 +#define AMD_FMT_MOD_TILE_VER_GFX10 2 +#define AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS 3 + +/* + * 64K_S is the same for GFX9/GFX10/GFX10_RBPLUS and hence has GFX9 as canonical + * version. + */ +#define AMD_FMT_MOD_TILE_GFX9_64K_S 9 + +/* + * 64K_D for non-32 bpp is the same for GFX9/GFX10/GFX10_RBPLUS and hence has + * GFX9 as canonical version. + */ +#define AMD_FMT_MOD_TILE_GFX9_64K_D 10 +#define AMD_FMT_MOD_TILE_GFX9_64K_S_X 25 +#define AMD_FMT_MOD_TILE_GFX9_64K_D_X 26 +#define AMD_FMT_MOD_TILE_GFX9_64K_R_X 27 + +#define AMD_FMT_MOD_DCC_BLOCK_64B 0 +#define AMD_FMT_MOD_DCC_BLOCK_128B 1 +#define AMD_FMT_MOD_DCC_BLOCK_256B 2 + +#define AMD_FMT_MOD_TILE_VERSION_SHIFT 0 +#define AMD_FMT_MOD_TILE_VERSION_MASK 0xFF +#define AMD_FMT_MOD_TILE_SHIFT 8 +#define AMD_FMT_MOD_TILE_MASK 0x1F + +/* Whether DCC compression is enabled. */ +#define AMD_FMT_MOD_DCC_SHIFT 13 +#define AMD_FMT_MOD_DCC_MASK 0x1 + +/* + * Whether to include two DCC surfaces, one which is rb & pipe aligned, and + * one which is not-aligned. + */ +#define AMD_FMT_MOD_DCC_RETILE_SHIFT 14 +#define AMD_FMT_MOD_DCC_RETILE_MASK 0x1 + +/* Only set if DCC_RETILE = false */ +#define AMD_FMT_MOD_DCC_PIPE_ALIGN_SHIFT 15 +#define AMD_FMT_MOD_DCC_PIPE_ALIGN_MASK 0x1 + +#define AMD_FMT_MOD_DCC_INDEPENDENT_64B_SHIFT 16 +#define AMD_FMT_MOD_DCC_INDEPENDENT_64B_MASK 0x1 +#define AMD_FMT_MOD_DCC_INDEPENDENT_128B_SHIFT 17 +#define AMD_FMT_MOD_DCC_INDEPENDENT_128B_MASK 0x1 +#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_SHIFT 18 +#define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3 + +/* + * DCC supports embedding some clear colors directly in the DCC surface. + * However, on older GPUs the rendering HW ignores the embedded clear color + * and prefers the driver provided color. This necessitates doing a fastclear + * eliminate operation before a process transfers control. + * + * If this bit is set that means the fastclear eliminate is not needed for these + * embeddable colors. + */ +#define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_SHIFT 20 +#define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_MASK 0x1 + +/* + * The below fields are for accounting for per GPU differences. These are only + * relevant for GFX9 and later and if the tile field is *_X/_T. + * + * PIPE_XOR_BITS = always needed + * BANK_XOR_BITS = only for TILE_VER_GFX9 + * PACKERS = only for TILE_VER_GFX10_RBPLUS + * RB = only for TILE_VER_GFX9 & DCC + * PIPE = only for TILE_VER_GFX9 & DCC & (DCC_RETILE | DCC_PIPE_ALIGN) + */ +#define AMD_FMT_MOD_PIPE_XOR_BITS_SHIFT 21 +#define AMD_FMT_MOD_PIPE_XOR_BITS_MASK 0x7 +#define AMD_FMT_MOD_BANK_XOR_BITS_SHIFT 24 +#define AMD_FMT_MOD_BANK_XOR_BITS_MASK 0x7 +#define AMD_FMT_MOD_PACKERS_SHIFT 27 +#define AMD_FMT_MOD_PACKERS_MASK 0x7 +#define AMD_FMT_MOD_RB_SHIFT 30 +#define AMD_FMT_MOD_RB_MASK 0x7 +#define AMD_FMT_MOD_PIPE_SHIFT 33 +#define AMD_FMT_MOD_PIPE_MASK 0x7 + +#define AMD_FMT_MOD_SET(field, value) \ + ((uint64_t)(value) << AMD_FMT_MOD_##field##_SHIFT) +#define AMD_FMT_MOD_GET(field, value) \ + (((value) >> AMD_FMT_MOD_##field##_SHIFT) & AMD_FMT_MOD_##field##_MASK) +#define AMD_FMT_MOD_CLEAR(field) \ + (~((uint64_t)AMD_FMT_MOD_##field##_MASK << AMD_FMT_MOD_##field##_SHIFT)) +#endif + +/* + * 2 plane YCbCr MSB aligned + * index 0 = Y plane, [15:0] Y:x [10:6] little endian + * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian + */ +#ifndef DRM_FORMAT_P010 +#define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel */ +#endif +/* + * Floating point 64bpp RGB + * IEEE 754-2008 binary16 half-precision float + * [15:0] sign:exponent:mantissa 1:5:10 + */ +#ifndef DRM_FORMAT_XRGB16161616F +#define DRM_FORMAT_XRGB16161616F fourcc_code('X', 'R', '4', 'H') /* [63:0] x:R:G:B 16:16:16:16 little endian */ +#define DRM_FORMAT_XBGR16161616F fourcc_code('X', 'B', '4', 'H') /* [63:0] x:B:G:R 16:16:16:16 little endian */ + +#define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */ +#define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */ +#endif + +#endif /* KCL_KCL_DRM_FOURCC_H */ From feb0cdec7529be888e2af35a8f2db50d055c7907 Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Tue, 15 Dec 2020 17:30:45 +0800 Subject: [PATCH 0293/1868] drm/amdkcl: dummy the amdgpu dm tracepoint for backport This is caused by "Add tracepoint for amdgpu_dm" v5.9-rc5-1254-gb694b19508a3 v2: more autotests to make the new tracepoints valid on the tier1 OS of rhel7.9 and above v3: fix indent and use the autotests already defined before Signed-off-by: Shiwu Zhang Reviewed-by: Flora Cui --- .../amd/display/amdgpu_dm/amdgpu_dm_trace.h | 88 ++++++++++++++++--- .../gpu/drm/amd/dkms/m4/drm-atomic-state.m4 | 18 ++++ .../drm/amd/dkms/m4/drm-connector-state.m4 | 26 ++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 + include/kcl/backport/kcl_dm_tracepoint.h | 21 +++++ 5 files changed, 143 insertions(+), 12 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-atomic-state.m4 create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-connector-state.m4 create mode 100644 include/kcl/backport/kcl_dm_tracepoint.h diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h index 4686d4b0cbad2..71ddae18f9b9d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h @@ -40,6 +40,7 @@ #include "dc/inc/hw/optc.h" #include "dc/inc/core_types.h" +#include DECLARE_EVENT_CLASS(amdgpu_dc_reg_template, TP_PROTO(unsigned long *count, uint32_t reg, uint32_t value), @@ -112,13 +113,19 @@ TRACE_EVENT(amdgpu_dm_connector_atomic_check, __field(uint32_t, crtc_id) __field(uint32_t, best_encoder_id) __field(enum drm_link_status, link_status) +#ifdef HAVE_STRUCT_DRM_CONNECTOR_STATE_SELF_REFRESH_AWARE __field(bool, self_refresh_aware) +#endif __field(enum hdmi_picture_aspect, picture_aspect_ratio) __field(unsigned int, content_type) +#ifdef HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE __field(unsigned int, hdcp_content_type) +#endif __field(unsigned int, content_protection) __field(unsigned int, scaling_mode) +#ifdef HAVE_STRUCT_DRM_CONNECTOR_STATE_COLORSPACE __field(u32, colorspace) +#endif __field(u8, max_requested_bpc) __field(u8, max_bpc) ), @@ -132,28 +139,52 @@ TRACE_EVENT(amdgpu_dm_connector_atomic_check, __entry->best_encoder_id = state->best_encoder ? state->best_encoder->base.id : 0; __entry->link_status = state->link_status; +#ifdef HAVE_STRUCT_DRM_CONNECTOR_STATE_SELF_REFRESH_AWARE __entry->self_refresh_aware = state->self_refresh_aware; +#endif __entry->picture_aspect_ratio = state->picture_aspect_ratio; __entry->content_type = state->content_type; +#ifdef HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE __entry->hdcp_content_type = state->hdcp_content_type; +#endif __entry->content_protection = state->content_protection; __entry->scaling_mode = state->scaling_mode; +#ifdef HAVE_STRUCT_DRM_CONNECTOR_STATE_COLORSPACE __entry->colorspace = state->colorspace; +#endif __entry->max_requested_bpc = state->max_requested_bpc; __entry->max_bpc = state->max_bpc; ), TP_printk("conn_id=%u conn_state=%p state=%p commit=%p crtc_id=%u " - "best_encoder_id=%u link_status=%d self_refresh_aware=%d " + "best_encoder_id=%u link_status=%d " +#ifdef HAVE_STRUCT_DRM_CONNECTOR_STATE_SELF_REFRESH_AWARE + "self_refresh_aware=%d " +#endif "picture_aspect_ratio=%d content_type=%u " - "hdcp_content_type=%u content_protection=%u scaling_mode=%u " - "colorspace=%u max_requested_bpc=%u max_bpc=%u", +#ifdef HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE + "hdcp_content_type=%u " +#endif + "content_protection=%u scaling_mode=%u " +#ifdef HAVE_STRUCT_DRM_CONNECTOR_STATE_COLORSPACE + "colorspace=%u " +#endif + "max_requested_bpc=%u max_bpc=%u", __entry->conn_id, __entry->conn_state, __entry->state, __entry->commit, __entry->crtc_id, __entry->best_encoder_id, - __entry->link_status, __entry->self_refresh_aware, + __entry->link_status, +#ifdef HAVE_STRUCT_DRM_CONNECTOR_STATE_SELF_REFRESH_AWARE + __entry->self_refresh_aware, +#endif __entry->picture_aspect_ratio, __entry->content_type, - __entry->hdcp_content_type, __entry->content_protection, - __entry->scaling_mode, __entry->colorspace, +#ifdef HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE + __entry->hdcp_content_type, +#endif + __entry->content_protection, + __entry->scaling_mode, +#ifdef HAVE_STRUCT_DRM_CONNECTOR_STATE_COLORSPACE + __entry->colorspace, +#endif __entry->max_requested_bpc, __entry->max_bpc) ); @@ -175,9 +206,13 @@ TRACE_EVENT(amdgpu_dm_crtc_atomic_check, __field(bool, zpos_changed) __field(bool, color_mgmt_changed) __field(bool, no_vblank) +#ifdef HAVE_STRUCT_DRM_CRTC_STATE_ASYNC_FLIP __field(bool, async_flip) +#endif __field(bool, vrr_enabled) +#ifdef HAVE_STRUCT_DRM_CONNECTOR_STATE_SELF_REFRESH_AWARE __field(bool, self_refresh_active) +#endif __field(u32, plane_mask) __field(u32, connector_mask) __field(u32, encoder_mask) @@ -197,9 +232,13 @@ TRACE_EVENT(amdgpu_dm_crtc_atomic_check, __entry->zpos_changed = state->zpos_changed; __entry->color_mgmt_changed = state->color_mgmt_changed; __entry->no_vblank = state->no_vblank; +#ifdef HAVE_STRUCT_DRM_CRTC_STATE_ASYNC_FLIP __entry->async_flip = state->async_flip; +#endif __entry->vrr_enabled = state->vrr_enabled; +#ifdef HAVE_STRUCT_DRM_CONNECTOR_STATE_SELF_REFRESH_AWARE __entry->self_refresh_active = state->self_refresh_active; +#endif __entry->plane_mask = state->plane_mask; __entry->connector_mask = state->connector_mask; __entry->encoder_mask = state->encoder_mask; @@ -207,16 +246,29 @@ TRACE_EVENT(amdgpu_dm_crtc_atomic_check, TP_printk("crtc_id=%u crtc_state=%p state=%p commit=%p changed(" "planes=%d mode=%d active=%d conn=%d zpos=%d color_mgmt=%d) " - "state(enable=%d active=%d async_flip=%d vrr_enabled=%d " - "self_refresh_active=%d no_vblank=%d) mask(plane=%x conn=%x " + "state(enable=%d active=%d " +#ifdef HAVE_STRUCT_DRM_CRTC_STATE_ASYNC_FLIP + "async_flip=%d " +#endif + "vrr_enabled=%d " +#ifdef HAVE_STRUCT_DRM_CONNECTOR_STATE_SELF_REFRESH_AWARE + "self_refresh_active=%d " +#endif + "no_vblank=%d) mask(plane=%x conn=%x " "enc=%x)", __entry->crtc_id, __entry->crtc_state, __entry->state, __entry->commit, __entry->planes_changed, __entry->mode_changed, __entry->active_changed, __entry->connectors_changed, __entry->zpos_changed, __entry->color_mgmt_changed, __entry->enable, __entry->active, - __entry->async_flip, __entry->vrr_enabled, - __entry->self_refresh_active, __entry->no_vblank, +#ifdef HAVE_STRUCT_DRM_CRTC_STATE_ASYNC_FLIP + __entry->async_flip, +#endif + __entry->vrr_enabled, +#ifdef HAVE_STRUCT_DRM_CONNECTOR_STATE_SELF_REFRESH_AWARE + __entry->self_refresh_active, +#endif + __entry->no_vblank, __entry->plane_mask, __entry->connector_mask, __entry->encoder_mask) ); @@ -322,7 +374,9 @@ TRACE_EVENT(amdgpu_dm_atomic_state_template, __field(bool, allow_modeset) __field(bool, legacy_cursor_update) __field(bool, async_update) +#ifdef HAVE_STRUCT_DRM_ATOMIC_STATE_DUPLICATED __field(bool, duplicated) +#endif __field(int, num_connector) __field(int, num_private_objs) ), @@ -332,16 +386,26 @@ TRACE_EVENT(amdgpu_dm_atomic_state_template, __entry->allow_modeset = state->allow_modeset; __entry->legacy_cursor_update = state->legacy_cursor_update; __entry->async_update = state->async_update; +#ifdef HAVE_STRUCT_DRM_ATOMIC_STATE_DUPLICATED __entry->duplicated = state->duplicated; +#endif __entry->num_connector = state->num_connector; __entry->num_private_objs = state->num_private_objs; ), TP_printk("state=%p allow_modeset=%d legacy_cursor_update=%d " - "async_update=%d duplicated=%d num_connector=%d " + "async_update=%d " +#ifdef HAVE_STRUCT_DRM_ATOMIC_STATE_DUPLICATED + "duplicated=%d " +#endif + "num_connector=%d " "num_private_objs=%d", __entry->state, __entry->allow_modeset, __entry->legacy_cursor_update, - __entry->async_update, __entry->duplicated, __entry->num_connector, + __entry->async_update, +#ifdef HAVE_STRUCT_DRM_ATOMIC_STATE_DUPLICATED + __entry->duplicated, +#endif + __entry->num_connector, __entry->num_private_objs) ); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-atomic-state.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-atomic-state.m4 new file mode 100644 index 0000000000000..cd7227d5c12eb --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-atomic-state.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # v5.0-rc1-415-g022debad063e +dnl # drm/atomic: Add drm_atomic_state->duplicated +dnl # +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_ATOMIC_STATE_DUPLICATED], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_atomic_state *state = NULL; + state->duplicated = 0; + ],[ + AC_DEFINE(HAVE_STRUCT_DRM_ATOMIC_STATE_DUPLICATED, 1, + [struct drm_connector_state->duplicated is available]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-state.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-state.m4 new file mode 100644 index 0000000000000..69753da371891 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector-state.m4 @@ -0,0 +1,26 @@ +dnl # +dnl # v4.20-rc3-425-g1398958cfd8d +dnl # drm: Add vrr_enabled property to drm CRTC +dnl # +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CONNECTOR_STATE_COLORSPACE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_connector_state *state = NULL; + state->colorspace = 0; + ],[ + AC_DEFINE(HAVE_STRUCT_DRM_CONNECTOR_STATE_COLORSPACE, 1, + [struct drm_connector_state->colorspace is available]) + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_connector_state *state = NULL; + state->self_refresh_aware = 0; + ],[ + AC_DEFINE(HAVE_STRUCT_DRM_CONNECTOR_STATE_SELF_REFRESH_AWARE, 1, + [struct drm_connector_state->self_refresh_aware is available]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 493caf84cbfba..d76fdbebea066 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -120,6 +120,8 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_ACPI_PUT_TABLE AC_AMDGPU_DRM_ATOMIC_HELPER_CALC_TIMESTAMPING_CONSTANTS AC_AMDGPU_DRM_FORMAT_INFO + AC_AMDGPU_STRUCT_DRM_CONNECTOR_STATE_COLORSPACE + AC_AMDGPU_STRUCT_DRM_ATOMIC_STATE_DUPLICATED AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/backport/kcl_dm_tracepoint.h b/include/kcl/backport/kcl_dm_tracepoint.h new file mode 100644 index 0000000000000..7d0e772c51ece --- /dev/null +++ b/include/kcl/backport/kcl_dm_tracepoint.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef KCL_BACKPORT_KCL_DM_TRACEPOINT_H +#define KCL_BACKPORT_KCL_DM_TRACEPOINT_H + +#ifndef DECLARE_EVENT_NOP +#define DECLARE_EVENT_NOP(name, proto, args) \ + static inline void trace_##name(proto) \ + { } \ + static inline bool trace_##name##_enabled(void) \ + { \ + return false; \ + } + +#define TRACE_EVENT_NOP(name, proto, args, struct, assign, print) \ + DECLARE_EVENT_NOP(name, PARAMS(proto), PARAMS(args)) + +#define DEFINE_EVENT_NOP(template, name, proto, args) \ + DECLARE_EVENT_NOP(name, PARAMS(proto), PARAMS(args)) +#endif + +#endif /* KCL_BACKPORT_KCL_DM_TRACEPOINT_H */ From 694af4d2422156072dc4a26f6049409ce18196d8 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 8 Jan 2020 17:12:58 +0800 Subject: [PATCH 0294/1868] drm/amdkcl: enable CONFIG_DRM_TTM_DMA_PAGE_POOL Signed-off-by: Flora Cui Reviewed-by: Kevin Wang --- drivers/gpu/drm/amd/dkms/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 26cce7ae2a0cb..cfe73b92bcad9 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -141,6 +141,7 @@ LINUXINCLUDE := \ export CONFIG_HSA_AMD=y export CONFIG_DRM_TTM=m +export CONFIG_DRM_TTM_DMA_PAGE_POOL=y export CONFIG_DRM_AMDGPU=m export CONFIG_DRM_SCHED=m export CONFIG_DRM_AMDGPU_CIK=y @@ -150,6 +151,7 @@ export CONFIG_DRM_AMD_DC=y export CONFIG_DRM_AMD_DC_DCN1_0=y subdir-ccflags-y += -DCONFIG_HSA_AMD +subdir-ccflags-y += -DCONFIG_DRM_TTM_DMA_PAGE_POOL subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_CIK subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_SI subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_USERPTR From d0f6f22319fd237f46778e09bf7ee3fba6eb2570 Mon Sep 17 00:00:00 2001 From: "Le.Ma" Date: Mon, 18 Feb 2019 10:40:35 +0800 Subject: [PATCH 0295/1868] drm/amdkcl: check whether u64_to_user_ptr is available v1: drm/amdkcl: [4.7] kcl for u64_to_user_ptr() v2: drm/amdkcl: drop kcl_u64_to_user_ptr Signed-off-by: Le.Ma Reviewed-by: Junwei Zhang Reviewed-by: Evan Quan Signed-off-by: Flora Cui Acked-by: Feifei Xu / Signed-off-by: Jack Gui --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_kernel.h | 17 +++++++++++++++++ 2 files changed, 18 insertions(+) create mode 100644 include/kcl/kcl_kernel.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 08d61f40a3eb4..a76e1bc850477 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include diff --git a/include/kcl/kcl_kernel.h b/include/kcl/kcl_kernel.h new file mode 100644 index 0000000000000..e1a0dfe11a386 --- /dev/null +++ b/include/kcl/kcl_kernel.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_KERNEL_H +#define AMDKCL_KERNEL_H + +#include + +/* Copied from include/linux/kernel.h */ +#ifndef u64_to_user_ptr +#define u64_to_user_ptr(x) ( \ +{ \ + typecheck(u64, x); \ + (void __user *)(uintptr_t)x; \ +} \ +) +#endif + +#endif /* AMDKCL_KERNEL_H */ From 1e53913dda3a277f89aa22e5695ceb95a6640d8c Mon Sep 17 00:00:00 2001 From: Kevin Wang Date: Tue, 23 Jan 2018 15:33:23 +0800 Subject: [PATCH 0296/1868] drm/amdkcl: check whether __GFP_RETRY_MAYFAIL is available kernel 4.13: rename __GFP_REPEAT to __GFP_RETRY_MAYFAIL Reviewed-by: Le Ma Reviewed-by: Roger He Signed-Off-by: Kevin Wang Signed-off-by: Jack Gui Signed-off-by: Flora Cui --- drivers/gpu/drm/ttm/backport/backport.h | 1 + include/kcl/kcl_kernel.h | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index acec38aa8d159..04bfefdaf001c 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -4,6 +4,7 @@ #include #include +#include #include #include #include diff --git a/include/kcl/kcl_kernel.h b/include/kcl/kcl_kernel.h index e1a0dfe11a386..6624b9a50f79a 100644 --- a/include/kcl/kcl_kernel.h +++ b/include/kcl/kcl_kernel.h @@ -3,6 +3,7 @@ #define AMDKCL_KERNEL_H #include +#include /* Copied from include/linux/kernel.h */ #ifndef u64_to_user_ptr @@ -14,4 +15,8 @@ ) #endif +#ifndef __GFP_RETRY_MAYFAIL +#define __GFP_RETRY_MAYFAIL __GFP_REPEAT +#endif + #endif /* AMDKCL_KERNEL_H */ From 429cc2a8055cf91c73d5272bcc16644af6d7dfae Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 12 Mar 2020 21:00:19 +0800 Subject: [PATCH 0297/1868] drm/amdkcl: add macro ALIGN_DOWN Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang Signed-off-by: Yifan Zhang --- include/kcl/kcl_kernel.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/kcl/kcl_kernel.h b/include/kcl/kcl_kernel.h index 6624b9a50f79a..f33fc452d8243 100644 --- a/include/kcl/kcl_kernel.h +++ b/include/kcl/kcl_kernel.h @@ -19,4 +19,8 @@ #define __GFP_RETRY_MAYFAIL __GFP_REPEAT #endif +#ifndef ALIGN_DOWN +#define ALIGN_DOWN(x, a) __ALIGN_KERNEL((x) - ((a) - 1), (a)) +#endif /* ALIGN_DOWN */ + #endif /* AMDKCL_KERNEL_H */ From 82d6086e1abeba22fedb25c35930844b29e17e91 Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Wed, 18 Mar 2020 17:09:57 +0800 Subject: [PATCH 0298/1868] drm/amdkcl: add kcl_compiler_attributes.h Signed-off-by: Yifan Zhang Reviewed-by: Flora Cui Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/scheduler/backport/backport.h | 2 ++ drivers/gpu/drm/ttm/backport/backport.h | 2 ++ include/kcl/kcl_compiler_attributes.h | 13 +++++++++++++ 4 files changed, 18 insertions(+) create mode 100644 include/kcl/kcl_compiler_attributes.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index a76e1bc850477..c2baa09d32bc3 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/gpu/drm/scheduler/backport/backport.h b/drivers/gpu/drm/scheduler/backport/backport.h index 46537c0094114..690cfe2fbe358 100644 --- a/drivers/gpu/drm/scheduler/backport/backport.h +++ b/drivers/gpu/drm/scheduler/backport/backport.h @@ -3,8 +3,10 @@ #define AMDSCHED_BACKPORT_H #include +#include #include #include #include #include + #endif diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index 04bfefdaf001c..a5c1c3c403ad7 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -5,10 +5,12 @@ #include #include #include +#include #include #include #include #include #include #include + #endif diff --git a/include/kcl/kcl_compiler_attributes.h b/include/kcl/kcl_compiler_attributes.h new file mode 100644 index 0000000000000..34d035352059c --- /dev/null +++ b/include/kcl/kcl_compiler_attributes.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_COMPILER_ATTRIBUTES_H +#define AMDKCL_COMPILER_ATTRIBUTES_H + +#ifdef HAVE_LINUX_COMPILER_ATTRIBUTES_H +#include +#endif + +#ifndef fallthrough +#define fallthrough do {} while (0) /* fallthrough */ +#endif + +#endif /* AMDKCL_COMPILER_ATTRIBUTES_H */ From d00f5cd6ea8fa1963eaf341ffb6a8ab0b5fe85d6 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 10 Sep 2020 13:32:43 +0800 Subject: [PATCH 0299/1868] drm/amdkcl: fake dma_alloc_attrs api for dma_attrs change Signed-off-by: Flora Cui Change-Id: If4dffb0b4f0d2a6d9a7067ab5e15c3d42e31e198 --- drivers/gpu/drm/ttm/ttm_pool.c | 4 ++-- include/kcl/kcl_dma_mapping.h | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 34 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/ttm/ttm_pool.c b/drivers/gpu/drm/ttm/ttm_pool.c index 8504dbe19c1a0..49ca26b933b60 100644 --- a/drivers/gpu/drm/ttm/ttm_pool.c +++ b/drivers/gpu/drm/ttm/ttm_pool.c @@ -107,7 +107,7 @@ static struct page *ttm_pool_alloc_page(struct ttm_pool *pool, gfp_t gfp_flags, if (order) attr |= DMA_ATTR_NO_WARN; - vaddr = dma_alloc_attrs(pool->dev, (1ULL << order) * PAGE_SIZE, + vaddr = kcl_dma_alloc_attrs(pool->dev, (1ULL << order) * PAGE_SIZE, &dma->addr, gfp_flags, attr); if (!vaddr) goto error_free; @@ -155,7 +155,7 @@ static void ttm_pool_free_page(struct ttm_pool *pool, enum ttm_caching caching, dma = (void *)p->private; vaddr = (void *)(dma->vaddr & PAGE_MASK); - dma_free_attrs(pool->dev, (1UL << order) * PAGE_SIZE, vaddr, dma->addr, + kcl_dma_free_attrs(pool->dev, (1UL << order) * PAGE_SIZE, vaddr, dma->addr, attr); kfree(dma); } diff --git a/include/kcl/kcl_dma_mapping.h b/include/kcl/kcl_dma_mapping.h index 1b7609d8ee876..0d58912e10533 100644 --- a/include/kcl/kcl_dma_mapping.h +++ b/include/kcl/kcl_dma_mapping.h @@ -27,6 +27,38 @@ void _kcl_convert_long_to_dma_attrs(struct dma_attrs *dma_attrs, dma_set_attr(i, dma_attrs); } } + +static inline +void *kcl_dma_alloc_attrs(struct device *dev, size_t size, dma_addr_t *dma_handle, + gfp_t flag, unsigned long attrs) +{ + struct dma_attrs dma_attrs; + + _kcl_convert_long_to_dma_attrs(&dma_attrs, attrs); + return dma_alloc_attrs(dev, size, dma_handle, flag, &dma_attrs); +} + +static inline +void kcl_dma_free_attrs(struct device *dev, size_t size, void *cpu_addr, + dma_addr_t dma_handle, unsigned long attrs) +{ + struct dma_attrs dma_attrs; + + _kcl_convert_long_to_dma_attrs(&dma_attrs, attrs); + dma_free_attrs(dev, size, cpu_addr, dma_handle, &dma_attrs); +} +#else +static inline void *kcl_dma_alloc_attrs(struct device *dev, size_t size, + dma_addr_t *dma_handle, gfp_t flag, + unsigned long attrs) +{ + return dma_alloc_attrs(dev, size, dma_handle, flag, attrs); +} +static inline void kcl_dma_free_attrs(struct device *dev, size_t size, void *cpu_addr, + dma_addr_t dma_handle, unsigned long attrs) +{ + return dma_free_attrs(dev, size, cpu_addr, dma_handle, attrs); +} #endif #ifndef HAVE_DMA_MAP_SGTABLE From da980d857c6447273329fd050b0d277bd40340a2 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 7 Sep 2020 13:36:31 +0800 Subject: [PATCH 0300/1868] drm/amdkcl: test for_each_sgtable_sg() Signed-off-by: Flora Cui --- include/kcl/kcl_dma_mapping.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/include/kcl/kcl_dma_mapping.h b/include/kcl/kcl_dma_mapping.h index 0d58912e10533..c65a83d51b953 100644 --- a/include/kcl/kcl_dma_mapping.h +++ b/include/kcl/kcl_dma_mapping.h @@ -120,4 +120,13 @@ static inline void dma_unmap_sgtable(struct device *dev, struct sg_table *sgt, } #endif +/* + * v5.8-rc3-2-g68d237056e00 ("scatterlist: protect parameters of the sg_table related macros") + * v5.7-rc5-33-g709d6d73c756 ("scatterlist: add generic wrappers for iterating over sgtable objects") + */ +#ifndef for_each_sgtable_sg +#define for_each_sgtable_sg(sgt, sg, i) \ + for_each_sg((sgt)->sgl, sg, (sgt)->orig_nents, i) +#endif + #endif From 74449d92211898d2e002d29c0bec6d16c975d2ac Mon Sep 17 00:00:00 2001 From: Yang Xiong Date: Fri, 10 Jul 2020 16:04:02 +0800 Subject: [PATCH 0301/1868] drm/amdkcl: add kcl copy of epoll event masks macro introduced in v4.11-rc2-2-g7e040726850a This kcl patch is caused by patch: drm/amdkfd: sparse: fix incorrect type in assignment Signed-off-by: Yang Xiong Reviewed-by: Flora Cui Change-Id: I2ab2c440728cfa1a38c1cd8a0e230fb3ee7327ae --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_eventpoll.h | 33 +++++++++++++++++++++++++ 2 files changed, 34 insertions(+) create mode 100644 include/kcl/kcl_eventpoll.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index c2baa09d32bc3..020a1c6516280 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include diff --git a/include/kcl/kcl_eventpoll.h b/include/kcl/kcl_eventpoll.h new file mode 100644 index 0000000000000..5f23d49a7e46f --- /dev/null +++ b/include/kcl/kcl_eventpoll.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */ +/* + * include/linux/eventpoll.h ( Efficient event polling implementation ) + * Copyright (C) 2001,...,2006 Davide Libenzi + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * Davide Libenzi + * + */ +#ifndef AMDKCL_EVENTPOLL_H +#define AMDKCL_EVENTPOLL_H + +#include + +/* Copied from include/uapi/linux/eventpoll.h */ +#ifndef EPOLLIN +#define EPOLLIN 0x00000001 +#define EPOLLPRI 0x00000002 +#define EPOLLOUT 0x00000004 +#define EPOLLERR 0x00000008 +#define EPOLLHUP 0x00000010 +#define EPOLLRDNORM 0x00000040 +#define EPOLLRDBAND 0x00000080 +#define EPOLLWRNORM 0x00000100 +#define EPOLLWRBAND 0x00000200 +#define EPOLLMSG 0x00000400 +#define EPOLLRDHUP 0x00002000 +#endif +#endif From 5be2eaa7663586239a712b0408d1455df781c942 Mon Sep 17 00:00:00 2001 From: tianci yin Date: Mon, 18 Feb 2019 10:59:12 +0800 Subject: [PATCH 0302/1868] drm/amdkcl: Test whether system_highpri_wq is available This is a squash of: drm/amdkcl: [3.16] add system_highpri_wq support Reviewed-by: Prike Liang Signed-off-by: Tianci Yin Signed-off-by: Jack Gui drm/amdkcl: Test whether system_highpri_wq is available system_highpri_wq is exported in kernel 3.6 and declared in kernel 3.15 Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang Signed-off-by: Jack Gui drm/amd/autoconf: fix system_highpri_wq unexported issue Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang drm/amdkcl: drop test for system_highpri_wq Signed-off-by: Flora Cui Reviewed-by: Shiwu Zhang --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_workqueue.h | 19 +++++++++++++++++++ 2 files changed, 20 insertions(+) create mode 100644 include/kcl/kcl_workqueue.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 020a1c6516280..60e80984d0d19 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include diff --git a/include/kcl/kcl_workqueue.h b/include/kcl/kcl_workqueue.h new file mode 100644 index 0000000000000..345bd0f2cc384 --- /dev/null +++ b/include/kcl/kcl_workqueue.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef KCL_LINUX_WORKQUEUE_H +#define KCL_LINUX_WORKQUEUE_H + +#include + +/* + * System-wide workqueues which are always present. + * + * system_highpri_wq is similar to system_wq but for work items which + * require WQ_HIGHPRI. + * + * v3.15-rc1-18-g73e4354444ee workqueue: declare system_highpri_wq + * v3.6-rc1-20-g1aabe902ca36 workqueue: introduce system_highpri_wq + */ +extern struct workqueue_struct *system_highpri_wq; + +#endif From 677880eb2dab10c04f2292346e24fee8e16cb505 Mon Sep 17 00:00:00 2001 From: Prike Liang Date: Mon, 22 Oct 2018 17:08:04 +0800 Subject: [PATCH 0303/1868] drm/amdkcl: [4.13] Add sysfs node max_link_speed/width, current_link_speed/width For SWDEV-165476 require and implement the feature inquire node. KCL originally implemented as commit 02805f8d0d76 to add sysfs node for max_link_speed, max_link_width, current_link_speed, current_link_width proposed in commit 56c1af4606f0. Since most of the attributes introduced in the commit 56c1af4606f0 are static and only visible within the PCI compile unit, we cannot use autoconf to check if they are defined. In this commit, we use the macro PCI_EXP_LNKCAP_SLS_8_0GB checked-in along with these attributes as a workaround and further check the return value after calling device_create_file() by deliberately ignoring the -EEXIST error code to make sure the error log is not mis-reported. v1: drm/amdkcl: Add sysfs node max_link_speed/width, current_link_speed/width v2: drm/amdkcl: add macros in kcl_pci.h if checked undefinded v3: add macro undefined check for remove BUILD_AS_DKMS macro v4: drm/amdkcl: remove sysfs entry on exit Signed-off-by: Prike Liang Reviewed-by: xinhui pan Reviewed-by: Junwei Zhang Signed-off-by: Adam Yang Signed-off-by: Chengming Gui Reviewed-by: Flora Cui Signed-off-by: Jack Gui Signed-off-by: Flora Cui Reviewed-by: Feifei Xu Signed-off-by: Yifan Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 + drivers/gpu/drm/amd/amdkcl/kcl_pci.c | 122 ++++++++++++++++++++++++ include/kcl/kcl_pci.h | 75 +++++++++++++++ 3 files changed, 199 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 63a314daf81b8..962e632101a0f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2343,6 +2343,7 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, kms_driver.driver_features |= DRIVER_ATOMIC; #endif + kcl_pci_create_measure_file(pdev); kcl_pci_configure_extended_tags(pdev); ret = pci_enable_device(pdev); if (ret) @@ -2471,6 +2472,7 @@ amdgpu_pci_remove(struct pci_dev *pdev) * Clear the Bus Master Enable bit and then wait on the PCIe Device * StatusTransactions Pending bit. */ + kcl_pci_remove_measure_file(pdev); pci_disable_device(pdev); pci_wait_for_pending_transaction(pdev); } diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_pci.c b/drivers/gpu/drm/amd/amdkcl/kcl_pci.c index 171f3239eeb3a..13b6180f6b3ed 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_pci.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_pci.c @@ -318,3 +318,125 @@ bool _kcl_pci_pr3_present(struct pci_dev *pdev) EXPORT_SYMBOL_GPL(_kcl_pci_pr3_present); #endif #endif /* HAVE_PCI_PR3_PRESENT */ + +#ifdef AMDKCL_CREATE_MEASURE_FILE +static ssize_t max_link_speed_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct pci_dev *pdev = to_pci_dev(dev); + + return sprintf(buf, "%s\n", PCIE_SPEED2STR(kcl_pcie_get_speed_cap(pdev))); +} +static DEVICE_ATTR_RO(max_link_speed); + +static ssize_t max_link_width_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct pci_dev *pdev = to_pci_dev(dev); + + return sprintf(buf, "%u\n", kcl_pcie_get_width_cap(pdev)); +} +static DEVICE_ATTR_RO(max_link_width); + +static ssize_t current_link_speed_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct pci_dev *pci_dev = to_pci_dev(dev); + u16 linkstat; + int err; + const char *speed; + + err = pcie_capability_read_word(pci_dev, PCI_EXP_LNKSTA, &linkstat); + if (err) + return -EINVAL; + + switch (linkstat & PCI_EXP_LNKSTA_CLS) { + case PCI_EXP_LNKSTA_CLS_16_0GB: + speed = "16 GT/s"; + break; + case PCI_EXP_LNKSTA_CLS_8_0GB: + speed = "8 GT/s"; + break; + case PCI_EXP_LNKSTA_CLS_5_0GB: + speed = "5 GT/s"; + break; + case PCI_EXP_LNKSTA_CLS_2_5GB: + speed = "2.5 GT/s"; + break; + default: + speed = "Unknown speed"; + } + + return sprintf(buf, "%s\n", speed); +} +static DEVICE_ATTR_RO(current_link_speed); + +static ssize_t current_link_width_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + struct pci_dev *pci_dev = to_pci_dev(dev); + u16 linkstat; + int err; + + err = pcie_capability_read_word(pci_dev, PCI_EXP_LNKSTA, &linkstat); + if (err) + return -EINVAL; + + return sprintf(buf, "%u\n", + (linkstat & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT); +} +static DEVICE_ATTR_RO(current_link_width); + +static struct attribute *pcie_dev_attrs[] = { + &dev_attr_current_link_speed.attr, + &dev_attr_current_link_width.attr, + &dev_attr_max_link_width.attr, + &dev_attr_max_link_speed.attr, + NULL, +}; + +int _kcl_pci_create_measure_file(struct pci_dev *pdev) +{ + int ret = 0; + + ret = device_create_file(&pdev->dev, &dev_attr_current_link_speed); + if (ret) { + dev_err(&pdev->dev, + "Failed to create current_link_speed sysfs files: %d\n", ret); + return ret; + } + + ret = device_create_file(&pdev->dev, &dev_attr_current_link_width); + if (ret) { + dev_err(&pdev->dev, + "Failed to create current_link_width sysfs files: %d\n", ret); + return ret; + } + + ret = device_create_file(&pdev->dev, &dev_attr_max_link_width); + if (ret) { + dev_err(&pdev->dev, + "Failed to create max_link_width sysfs files: %d\n", ret); + return ret; + } + + ret = device_create_file(&pdev->dev, &dev_attr_max_link_speed); + if (ret) { + dev_err(&pdev->dev, + "Failed to create max_link_speed sysfs files: %d\n", ret); + return ret; + } + + return ret; +} +EXPORT_SYMBOL(_kcl_pci_create_measure_file); + +void _kcl_pci_remove_measure_file(struct pci_dev *pdev) +{ + device_remove_file(&pdev->dev, &dev_attr_current_link_speed); + device_remove_file(&pdev->dev, &dev_attr_current_link_width); + device_remove_file(&pdev->dev, &dev_attr_max_link_width); + device_remove_file(&pdev->dev, &dev_attr_max_link_speed); +} +EXPORT_SYMBOL(_kcl_pci_remove_measure_file); +#endif /* AMDKCL_CREATE_MEASURE_FILE */ diff --git a/include/kcl/kcl_pci.h b/include/kcl/kcl_pci.h index 4eefafc20be1a..fe3c471def696 100644 --- a/include/kcl/kcl_pci.h +++ b/include/kcl/kcl_pci.h @@ -26,6 +26,58 @@ #include #include +#ifndef PCI_EXP_DEVCAP2_ATOMIC_ROUTE +#define PCI_EXP_DEVCAP2_ATOMIC_ROUTE 0x00000040 /* Atomic Op routing */ +#endif +#ifndef PCI_EXP_DEVCAP2_ATOMIC_COMP32 +#define PCI_EXP_DEVCAP2_ATOMIC_COMP32 0x00000080 /* 32b AtomicOp completion */ +#endif +#ifndef PCI_EXP_DEVCAP2_ATOMIC_COMP64 +#define PCI_EXP_DEVCAP2_ATOMIC_COMP64 0x00000100 /* 64b AtomicOp completion*/ +#endif +#ifndef PCI_EXP_DEVCAP2_ATOMIC_COMP128 +#define PCI_EXP_DEVCAP2_ATOMIC_COMP128 0x00000200 /* 128b AtomicOp completion*/ +#endif +#ifndef PCI_EXP_DEVCTL2_ATOMIC_REQ +#define PCI_EXP_DEVCTL2_ATOMIC_REQ 0x0040 /* Set Atomic requests */ +#endif +#ifndef PCI_EXP_DEVCTL2_ATOMIC_BLOCK +#define PCI_EXP_DEVCTL2_ATOMIC_BLOCK 0x0040 /* Block AtomicOp on egress */ +#endif + +#ifndef PCIE_SPEED_16_0GT +#define PCIE_SPEED_16_0GT 0x17 +#endif +#ifndef PCI_EXP_LNKCAP2_SLS_16_0GB +#define PCI_EXP_LNKCAP2_SLS_16_0GB 0x00000010 /* Supported Speed 16GT/s */ +#endif +#ifndef PCI_EXP_LNKCAP_SLS_16_0GB +#define PCI_EXP_LNKCAP_SLS_16_0GB 0x00000004 /* LNKCAP2 SLS Vector bit 3 */ +#endif +#ifndef PCI_EXP_LNKSTA_CLS_16_0GB +#define PCI_EXP_LNKSTA_CLS_16_0GB 0x0004 /* Current Link Speed 16.0GT/s */ +#endif + +/* PCIe link information */ +#ifndef PCIE_SPEED2STR +#define PCIE_SPEED2STR(speed) \ + ((speed) == PCIE_SPEED_16_0GT ? "16 GT/s" : \ + (speed) == PCIE_SPEED_8_0GT ? "8 GT/s" : \ + (speed) == PCIE_SPEED_5_0GT ? "5 GT/s" : \ + (speed) == PCIE_SPEED_2_5GT ? "2.5 GT/s" : \ + "Unknown speed") +#endif + +/* PCIe speed to Mb/s reduced by encoding overhead */ +#ifndef PCIE_SPEED2MBS_ENC +#define PCIE_SPEED2MBS_ENC(speed) \ + ((speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \ + (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \ + (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \ + (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \ + 0) +#endif + #if !defined(HAVE_PCIE_GET_SPEED_AND_WIDTH_CAP) extern enum pci_bus_speed (*_kcl_pcie_get_speed_cap)(struct pci_dev *dev); extern enum pcie_link_width (*_kcl_pcie_get_width_cap)(struct pci_dev *dev); @@ -112,4 +164,27 @@ static inline bool pci_pr3_present(struct pci_dev *pdev) { return false; } #endif #endif /* HAVE_PCI_PR3_PRESENT */ +#ifndef PCI_EXP_LNKCAP_SLS_8_0GB +#define AMDKCL_CREATE_MEASURE_FILE +#define PCI_EXP_LNKCAP_SLS_8_0GB 0x00000003 /* LNKCAP2 SLS Vector bit 2 */ +int _kcl_pci_create_measure_file(struct pci_dev *pdev); +void _kcl_pci_remove_measure_file(struct pci_dev *pdev); +#endif + +static inline int kcl_pci_create_measure_file(struct pci_dev *pdev) +{ +#ifdef AMDKCL_CREATE_MEASURE_FILE + return _kcl_pci_create_measure_file(pdev); +#else + return 0; +#endif +} + +static inline void kcl_pci_remove_measure_file(struct pci_dev *pdev) +{ +#ifdef AMDKCL_CREATE_MEASURE_FILE + _kcl_pci_remove_measure_file(pdev); +#endif +} + #endif /* AMDKCL_PCI_H */ From f863881740d6ebc02238e739904dd3016268d8e0 Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Wed, 22 Apr 2020 22:15:29 +0800 Subject: [PATCH 0304/1868] drm/amdkcl: add PCI_EXP macro in kcl Change-Id: I16e3b99df53731bc3f8f836aeb1ac41763443810 Signed-off-by: Yifan Zhang --- include/kcl/kcl_pci.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/include/kcl/kcl_pci.h b/include/kcl/kcl_pci.h index fe3c471def696..596f37906499c 100644 --- a/include/kcl/kcl_pci.h +++ b/include/kcl/kcl_pci.h @@ -44,6 +44,25 @@ #ifndef PCI_EXP_DEVCTL2_ATOMIC_BLOCK #define PCI_EXP_DEVCTL2_ATOMIC_BLOCK 0x0040 /* Block AtomicOp on egress */ #endif +#ifndef PCI_EXP_LNKCTL2_ENTER_COMP +#define PCI_EXP_LNKCTL2_ENTER_COMP 0x0010 /* Enter Compliance */ +#endif +#ifndef PCI_EXP_LNKCTL2_TX_MARGIN +#define PCI_EXP_LNKCTL2_TX_MARGIN 0x0380 /* Transmit Margin */ +#endif + +#ifndef PCI_EXP_LNKCTL2_TLS +#define PCI_EXP_LNKCTL2_TLS 0x000f +#endif +#ifndef PCI_EXP_LNKCTL2_TLS_2_5GT +#define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */ +#endif +#ifndef PCI_EXP_LNKCTL2_TLS_5_0GT +#define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */ +#endif +#ifndef PCI_EXP_LNKCTL2_TLS_8_0GT +#define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ +#endif #ifndef PCIE_SPEED_16_0GT #define PCIE_SPEED_16_0GT 0x17 From 472d03bd33f2460b19b17a35438974c012635453 Mon Sep 17 00:00:00 2001 From: tianci yin Date: Fri, 28 Aug 2020 16:25:15 +0800 Subject: [PATCH 0305/1868] drm/amdkcl: add macro for_each_if Signed-off-by: Tianci Yin Signed-off-by: tianci yin --- include/kcl/kcl_drm_crtc.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/kcl/kcl_drm_crtc.h b/include/kcl/kcl_drm_crtc.h index e0eaa2ace66b1..8b8b027aefbf9 100644 --- a/include/kcl/kcl_drm_crtc.h +++ b/include/kcl/kcl_drm_crtc.h @@ -74,6 +74,12 @@ DRM_MODE_ROTATE_270) #endif +/* Copied from include/drm/drm_util.h */ +/* helper for handling conditionals in various for_each macros */ +#ifndef for_each_if +#define for_each_if(condition) if (!(condition)) {} else +#endif + #if !defined(HAVE_DRM_HELPER_FORCE_DISABLE_ALL) int _kcl_drm_helper_force_disable_all(struct drm_device *dev); static inline From ca58f08c6615b11cf2dccbcf4a4d35bc63804abd Mon Sep 17 00:00:00 2001 From: changzhu Date: Wed, 26 Aug 2020 10:08:03 +0800 Subject: [PATCH 0306/1868] drm/amdkcl: check whether drm_for_each_xxx macros are available This is a squahs of: drm/amdkcl: drop redundant macro Signed-off-by: Flora Cui Reviewed-by: Shiwu Zhang This commit is used to fix bug in kcl_drm.h in redhat 7.2 v2: 57e9a478b988 - Clean up KCL macros. v3: drm/amdkcl: remove kcl_drm_for_each_ macro v4: move to kcl_drm_crtc.h Signed-off-by: changzhu Reviewed-by: Amber Lin Signed-off-by: Flora Cui --- include/kcl/kcl_drm_crtc.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/include/kcl/kcl_drm_crtc.h b/include/kcl/kcl_drm_crtc.h index 8b8b027aefbf9..2f01179d0c2b1 100644 --- a/include/kcl/kcl_drm_crtc.h +++ b/include/kcl/kcl_drm_crtc.h @@ -80,6 +80,21 @@ #define for_each_if(condition) if (!(condition)) {} else #endif +#ifndef drm_for_each_crtc +#define drm_for_each_crtc(crtc, dev) \ + list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head) +#endif + +#ifndef drm_for_each_encoder +#define drm_for_each_encoder(encoder, dev) \ + list_for_each_entry(encoder, &(dev)->mode_config.encoder_list, head) +#endif + +#ifndef drm_for_each_fb +#define drm_for_each_fb(fb, dev) \ + list_for_each_entry(fb, &(dev)->mode_config.fb_list, head) +#endif + #if !defined(HAVE_DRM_HELPER_FORCE_DISABLE_ALL) int _kcl_drm_helper_force_disable_all(struct drm_device *dev); static inline @@ -89,4 +104,5 @@ int drm_helper_force_disable_all(struct drm_device *dev) } #endif + #endif From 573c77eb3314f8776d7ca07c7617d8b8da7c330c Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Mon, 29 Jul 2019 11:14:34 +0800 Subject: [PATCH 0307/1868] drm/amdkcl: check whether DP_DPRX_FEATURE_ENUMERATION_LIST is available This is a squash of: drm/amdkcl: test DP_TRAINING_PATTERN_SET_PHY_REPEATER1 directly Change-Id: I883c0612c232e08039518f40a794fdb9b148cd16 Signed-off-by: Stanley.Yang Reviewed-by: Rui Teng Signed-off-by: Yifan Zhang drm/amdkcl: test DP_TEST_AUDIO_MODE directory Change-Id: I1b903fc00c3710f88d9db5bd5f72bd60e88d7373 Signed-off-by: Stanley.Yang Reviewed-by: Flora Cui Signed-off-by: Yifan Zhang drm/amdkcl: fake macro DP_DSC_SUPPORT Signed-off-by: Stanley.Yang Reviewed-by: Flora Cui Signed-off-by: Yifan Zhang drm/amdkcl: move DP_DSC_THROUGHPUT_MODE_0_UPSUPPORTED check to kcl_drm_dp_helper.h Signed-off-by: Chengming Gui Reviewed-by: Flora Cui drm/amdkcl: refactor dp related macros Signed-off-by: Flora Cui Reviewed-by: Yang Xiong drm/amdkcl: fake kcl copy of DP_PHY_TEST_PATTERN Signed-off-by: Flora Cui Change-Id: I351a01e5881df067a68f0128ec48aba922e42790 Signed-off-by: Yifan Zhang Signed-off-by: Jack Gui --- include/kcl/kcl_drm_dp_helper.h | 165 ++++++++++++++++++++++++++++++++ 1 file changed, 165 insertions(+) create mode 100644 include/kcl/kcl_drm_dp_helper.h diff --git a/include/kcl/kcl_drm_dp_helper.h b/include/kcl/kcl_drm_dp_helper.h new file mode 100644 index 0000000000000..edb6b4202915b --- /dev/null +++ b/include/kcl/kcl_drm_dp_helper.h @@ -0,0 +1,165 @@ +/* + * Copyright © 2008 Keith Packard + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE. + */ + + +#ifndef _KCL_DRM_DP_HELPER_H_ +#define _KCL_DRM_DP_HELPER_H_ + +#include +#include +#include + +#include +#include +#include +#include + +/* + * v4.13-rc5-840-gc673fe7f0cd5 + * drm/dp: DPCD register defines for link status within ESI field + */ +#ifndef DP_LANE0_1_STATUS_ESI +#define DP_LANE0_1_STATUS_ESI 0x200c /* status same as 0x202 */ +#define DP_LANE2_3_STATUS_ESI 0x200d /* status same as 0x203 */ +#define DP_LANE_ALIGN_STATUS_UPDATED_ESI 0x200e /* status same as 0x204 */ +#define DP_SINK_STATUS_ESI 0x200f /* status same as 0x205 */ +#endif + +/* + * v4.13-rc5-1383-gac58fff15516 + * drm/dp-helper: add missing defines needed by AMD display core. + */ +#ifndef DP_ADJUST_REQUEST_POST_CURSOR2 +#define DP_ADJUST_REQUEST_POST_CURSOR2 0x20c + +#define DP_TEST_MISC0 0x232 + +#define DP_TEST_PHY_PATTERN 0x248 +#define DP_TEST_80BIT_CUSTOM_PATTERN_7_0 0x250 +#define DP_TEST_80BIT_CUSTOM_PATTERN_15_8 0x251 +#define DP_TEST_80BIT_CUSTOM_PATTERN_23_16 0x252 +#define DP_TEST_80BIT_CUSTOM_PATTERN_31_24 0x253 +#define DP_TEST_80BIT_CUSTOM_PATTERN_39_32 0x254 +#define DP_TEST_80BIT_CUSTOM_PATTERN_47_40 0x255 +#define DP_TEST_80BIT_CUSTOM_PATTERN_55_48 0x256 +#define DP_TEST_80BIT_CUSTOM_PATTERN_63_56 0x257 +#define DP_TEST_80BIT_CUSTOM_PATTERN_71_64 0x258 +#define DP_TEST_80BIT_CUSTOM_PATTERN_79_72 0x259 + +#define DP_BRANCH_REVISION_START 0x509 + +#define DP_DP13_DPCD_REV 0x2200 +#define DP_DP13_MAX_LINK_RATE 0x2201 +#endif + + +#if !defined(DP_DPRX_FEATURE_ENUMERATION_LIST) +#define DP_DPRX_FEATURE_ENUMERATION_LIST 0x2210 /* DP 1.3 */ +#endif + +#if !defined(DP_TRAINING_PATTERN_SET_PHY_REPEATER1) +#define DP_TRAINING_PATTERN_SET_PHY_REPEATER1 0xf0010 /* 1.3 */ +#endif + +#if !defined(DP_LANE0_1_STATUS_PHY_REPEATER1) +#define DP_LANE0_1_STATUS_PHY_REPEATER1 0xf0030 /* 1.3 */ +#endif + +#if !defined(DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1) +#define DP_ADJUST_REQUEST_LANE0_1_PHY_REPEATER1 0xf0033 /* 1.3 */ +#endif + +#if !defined(DP_TRAINING_LANE0_SET_PHY_REPEATER1) +#define DP_TRAINING_LANE0_SET_PHY_REPEATER1 0xf0011 /* 1.3 */ +#endif + +#if !defined(DP_PHY_REPEATER_MODE_TRANSPARENT) +#define DP_PHY_REPEATER_MODE_TRANSPARENT 0x55 /* 1.3 */ +#endif + +#if !defined(DP_PHY_REPEATER_MODE) +#define DP_PHY_REPEATER_MODE 0xf0003 /* 1.3 */ +#endif + +#if !defined(DP_PHY_REPEATER_MODE_NON_TRANSPARENT) +#define DP_PHY_REPEATER_MODE_NON_TRANSPARENT 0xaa /* 1.3 */ +#endif + +#if !defined(DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1) +#define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xf0020 /* 1.4a */ +#endif + +#if !defined(DP_TRAINING_PATTERN_SET_PHY_REPEATER1) +#define DP_TRAINING_PATTERN_SET_PHY_REPEATER1 0xf0010 /* 1.3 */ +#endif + +#if !defined(DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT) +#define DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT 0xf0005 /* 1.4a */ +#endif + +#if !defined(DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV) +#define DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV 0xf0000 /* 1.3 */ +#endif + +#if !defined(DP_MAX_LINK_RATE_PHY_REPEATER) +#define DP_MAX_LINK_RATE_PHY_REPEATER 0xf0001 /* 1.4a */ +#endif + +#if !defined(DP_PHY_REPEATER_CNT) +#define DP_PHY_REPEATER_CNT 0xf0002 /* 1.3 */ +#endif + +#if !defined(DP_MAX_LANE_COUNT_PHY_REPEATER) +#define DP_MAX_LANE_COUNT_PHY_REPEATER 0xf0004 /* 1.4a */ +#endif + +#if !defined(DP_TEST_AUDIO_MODE) +#define DP_TEST_AUDIO_MODE 0x271 +#endif + +#if !defined(DP_TEST_AUDIO_PATTERN_TYPE) +#define DP_TEST_AUDIO_PATTERN_TYPE 0x272 +#endif + +#if !defined(DP_TEST_AUDIO_PERIOD_CH1) +#define DP_TEST_AUDIO_PERIOD_CH1 0x273 +#endif + +#if !defined(DP_DSC_SUPPORT) +#define DP_DSC_SUPPORT 0x060 /* DP 1.4 */ +#endif + +/* + * v5.6-1624-g8811d9eb4dfa + * drm/amd/display: Align macro name as per DP spec + */ +#ifdef DP_TEST_PHY_PATTERN +#define DP_PHY_TEST_PATTERN DP_TEST_PHY_PATTERN +#endif + +/* commit fc1424c2ec813080aa1eaa2948070902b1a0e507 + * drm: Correct DP DSC macro typo */ +#ifdef DP_DSC_THROUGHPUT_MODE_0_UPSUPPORTED +#define DP_DSC_THROUGHPUT_MODE_0_UNSUPPORTED DP_DSC_THROUGHPUT_MODE_0_UPSUPPORTED +#endif + +#endif /* _KCL_DRM_DP_HELPER_H_ */ From d9c86b9d898d9b4568babc5fa00095f032a018f9 Mon Sep 17 00:00:00 2001 From: Junwei Zhang Date: Fri, 23 Dec 2016 18:24:00 +0800 Subject: [PATCH 0308/1868] drm/amdkcl: add AMDKCL_DMA_FENCE_OPS_WAIT_OPTIONAL && AMDKCL_DMA_FENCE_OPS_ENABLE_SIGNALING_OPTIONAL dma_fence_get_rcu_safe() history: v4.8-rc8-1410-g4be0542073a3 introduce +static inline struct fence *fence_get_rcu_safe(struct fence * __rcu *fencep) v4.9-rc2-299-gf54d1867005c dma-buf: Rename struct fence to dma_fence v4.14-rc3-486-gf8e0731db4a0 dma-fence: fix dma_fence_get_rcu_safe v2 - if (!fence || !dma_fence_get_rcu(fence)) + if (!fence) return NULL; + if (!dma_fence_get_rcu(fence)) + continue; + v4.14-rc3-601-g5f72db59160c dma-buf/fence: Sparse wants __rcu on the object itself -dma_fence_get_rcu_safe(struct dma_fence * __rcu *fencep) +dma_fence_get_rcu_safe(struct dma_fence __rcu **fencep) v1: drm/amdkcl: [4.8] add fence array support v2: drm/amdkcl: Test whether dma_fence header is available v3: drm/amdkcl: refactor kcl copy dma_fence_is_later() v4: drm/amdkcl: add AMDKCL_DMA_FENCE_OPS_WAIT_OPTIONAL v5: drm/amdkcl: add AMDKCL_DMA_FENCE_OPS_ENABLE_SIGNALING_OPTIONAL v6: drm/amdkcl: refactor check for dma_fence_wait_any_timeout v7: drm/amdkcl: refactor check for fence_default_wait, fence_wait_timeout v8: drm/amdkcl: refactor check for fence_get_rcu_safe v9: drm/amdkcl: include kcl_fence.h for dkms build v10: drm/amdkcl: drop kcl_fence_context_alloc & kcl_fence_init v11: drm/amdkcl: fix kcl_fence_get_rcu_safe() v12: drm/amdkcl: fix kcl_fence_default_wait v13: drm/amdkcl: drop test for linux/dma-fence.h outside of kcl v14: drm/amdkcl: drop test for linux/dma-fence-array.h outside of kcl Signed-off-by: Junwei Zhang Reviewed-by: Qiang Yu Signed-off-by: Anatoli Antonovitch Signed-off-by: Yifan Zhang Signed-off-by: Flora Cui Reviewed-by: Feifei Xu Acked-by: Feifei Xu Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 1 + drivers/gpu/drm/scheduler/sched_fence.c | 4 ++++ 3 files changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c index 1ef758ac5076e..85e560df7f6b8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.c @@ -184,5 +184,6 @@ static const struct dma_fence_ops amdkfd_fence_ops = { .get_driver_name = amdkfd_fence_get_driver_name, .get_timeline_name = amdkfd_fence_get_timeline_name, .enable_signaling = amdkfd_fence_enable_signaling, + AMDKCL_DMA_FENCE_OPS_WAIT_OPTIONAL .release = amdkfd_fence_release, }; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index 1e8afc0b7a62c..837ae142d6778 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c @@ -878,6 +878,7 @@ static const struct dma_fence_ops amdgpu_fence_ops = { .get_driver_name = amdgpu_fence_get_driver_name, .get_timeline_name = amdgpu_fence_get_timeline_name, .enable_signaling = amdgpu_fence_enable_signaling, + AMDKCL_DMA_FENCE_OPS_WAIT_OPTIONAL .release = amdgpu_fence_release, }; diff --git a/drivers/gpu/drm/scheduler/sched_fence.c b/drivers/gpu/drm/scheduler/sched_fence.c index 0f35f009b9d37..59aa91e73d733 100644 --- a/drivers/gpu/drm/scheduler/sched_fence.c +++ b/drivers/gpu/drm/scheduler/sched_fence.c @@ -181,12 +181,16 @@ static void drm_sched_fence_set_deadline_finished(struct dma_fence *f, static const struct dma_fence_ops drm_sched_fence_ops_scheduled = { .get_driver_name = drm_sched_fence_get_driver_name, .get_timeline_name = drm_sched_fence_get_timeline_name, + AMDKCL_DMA_FENCE_OPS_ENABLE_SIGNALING_OPTIONAL + AMDKCL_DMA_FENCE_OPS_WAIT_OPTIONAL .release = drm_sched_fence_release_scheduled, }; static const struct dma_fence_ops drm_sched_fence_ops_finished = { .get_driver_name = drm_sched_fence_get_driver_name, .get_timeline_name = drm_sched_fence_get_timeline_name, + AMDKCL_DMA_FENCE_OPS_ENABLE_SIGNALING_OPTIONAL + AMDKCL_DMA_FENCE_OPS_WAIT_OPTIONAL .release = drm_sched_fence_release_finished, .set_deadline = drm_sched_fence_set_deadline_finished, }; From 905541790d0be3e4fcdd01d90e8355bb6223e8ca Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 13 Jul 2020 14:39:08 +0800 Subject: [PATCH 0309/1868] drm/amdkcl: dkms support for hmm Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling Change-Id: I261b55baa69cc111cde879705b8950573af0d6d3 --- drivers/gpu/drm/amd/amdgpu/Makefile | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 3 + .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 95 +++- drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h | 4 + drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 111 ++++ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 14 + drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c | 480 +++++++++++++++++- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h | 36 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 5 + drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 230 ++++++++- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 7 +- drivers/gpu/drm/amd/dkms/m4/hmm.m4 | 35 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 15 files changed, 1022 insertions(+), 5 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/hmm.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index 359d2b7d8cbbd..37347b2d30374 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -310,7 +310,7 @@ endif amdgpu-$(CONFIG_COMPAT) += amdgpu_ioc32.o amdgpu-$(CONFIG_VGA_SWITCHEROO) += amdgpu_atpx_handler.o amdgpu-$(CONFIG_ACPI) += amdgpu_acpi.o -amdgpu-$(CONFIG_HMM_MIRROR) += amdgpu_hmm.o +amdgpu-$(CONFIG_MMU_NOTIFIER) += amdgpu_hmm.o include $(FULL_AMD_PATH)/pm/Makefile diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 4180d9fcdaded..98b2ec5887032 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1130,7 +1130,9 @@ struct amdgpu_device { enum pp_mp1_state mp1_state; struct amdgpu_doorbell_index doorbell_index; +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED struct mutex notifier_lock; +#endif int asic_reset_res; struct work_struct xgmi_reset_work; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index 558406b16d7b8..da2764c3aae93 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -83,6 +83,9 @@ struct kgd_mem { uint32_t invalid; struct amdkfd_process_info *process_info; +#ifndef HAVE_AMDKCL_HMM_MIRROR_ENABLED + struct page **user_pages; +#endif struct amdgpu_sync sync; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 30a21ce2da417..2d16fec2fb322 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -1093,6 +1093,7 @@ static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr, return 0; } +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED ret = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages, &range); if (ret) { if (ret == -EAGAIN) @@ -1101,6 +1102,29 @@ static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr, pr_err("%s: Failed to get user pages: %d\n", __func__, ret); goto unregister_out; } +#else + /* If no restore worker is running concurrently, user_pages + * should not be allocated + */ + WARN(mem->user_pages, "Leaking user_pages array"); + + mem->user_pages = kvmalloc_array(bo->tbo.ttm->num_pages, + sizeof(struct page *), + GFP_KERNEL | __GFP_ZERO); + if (!mem->user_pages) { + pr_err("%s: Failed to allocate pages array\n", __func__); + ret = -ENOMEM; + goto unregister_out; + } + + ret = amdgpu_ttm_tt_get_user_pages(bo, mem->user_pages); + if (ret) { + pr_err("%s: Failed to get user pages: %d\n", __func__, ret); + goto free_out; + } + + amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm, mem->user_pages); +#endif ret = amdgpu_bo_reserve(bo, true); if (ret) { @@ -1114,7 +1138,15 @@ static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr, amdgpu_bo_unreserve(bo); release_out: +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm, range); +#else + if (ret) + release_pages(mem->user_pages, bo->tbo.ttm->num_pages); +free_out: + kvfree(mem->user_pages); + mem->user_pages = NULL; +#endif unregister_out: if (ret) amdgpu_hmm_unregister(bo); @@ -1959,6 +1991,17 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu( mutex_unlock(&process_info->notifier_lock); } +#ifndef HAVE_AMDKCL_HMM_MIRROR_ENABLED + /* Free user pages if necessary */ + if (mem->user_pages) { + pr_debug("%s: Freeing user_pages array\n", __func__); + if (mem->user_pages[0]) + release_pages(mem->user_pages, + mem->bo->tbo.ttm->num_pages); + kvfree(mem->user_pages); + } +#endif + ret = reserve_bo_and_cond_vms(mem, NULL, BO_VM_ALL, &ctx); if (unlikely(ret)) return ret; @@ -2847,6 +2890,7 @@ static int update_invalid_user_pages(struct amdkfd_process_info *process_info, } } +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED /* Get updated user pages */ ret = amdgpu_ttm_tt_get_user_pages(bo, bo->tbo.ttm->pages, &mem->range); @@ -2865,9 +2909,35 @@ static int update_invalid_user_pages(struct amdkfd_process_info *process_info, ret = 0; } +#else + if (!mem->user_pages) { + mem->user_pages = + kvmalloc_array(bo->tbo.ttm->num_pages, + sizeof(struct page *), + GFP_KERNEL | __GFP_ZERO); + if (!mem->user_pages) { + pr_err("%s: Failed to allocate pages array\n", + __func__); + return -ENOMEM; + } + } else if (mem->user_pages[0]) { + release_pages(mem->user_pages, bo->tbo.ttm->num_pages); + } + /* Get updated user pages */ + ret = amdgpu_ttm_tt_get_user_pages(bo, mem->user_pages); + if (ret) { + mem->user_pages[0] = NULL; + pr_info("%s: Failed to get user pages: %d\n", + __func__, ret); + /* Pretend it succeeded. It will fail later + * with a VM fault if the GPU tries to access + * it. Better than hanging indefinitely with + * stalled user mode queues. + */ + } +#endif mutex_lock(&process_info->notifier_lock); - /* Mark the BO as valid unless it was invalidated * again concurrently. */ @@ -2941,6 +3011,7 @@ static int validate_invalid_user_pages(struct amdkfd_process_info *process_info) bo = mem->bo; +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED /* Validate the BO if we got user pages */ if (bo->tbo.ttm->pages[0]) { amdgpu_bo_placement_from_domain(bo, mem->domain); @@ -2951,6 +3022,28 @@ static int validate_invalid_user_pages(struct amdkfd_process_info *process_info) } } +#else + /* Copy pages array and validate the BO if we got user pages */ + if (mem->user_pages[0]) { + amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm, + mem->user_pages); + amdgpu_bo_placement_from_domain(bo, mem->domain); + ret = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); + if (ret) { + pr_err("%s: failed to validate BO\n", __func__); + goto unreserve_out; + } + } + + /* Validate succeeded, now the BO owns the pages, free + * our copy of the pointer array. Put this BO back on + * the userptr_valid_list. If we need to revalidate + * it, we need to start from scratch. + */ + kvfree(mem->user_pages); + mem->user_pages = NULL; +#endif + /* Update mapping. If the BO was not validated * (because we couldn't get user pages), this will * clear the page table entries, which will result in diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h index 555cd6d877c30..204bee0e32562 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h @@ -40,7 +40,11 @@ struct amdgpu_bo_list_entry { uint32_t priority; struct page **user_pages; struct hmm_range *range; +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED bool user_invalidated; +#else + int user_invalidated; +#endif }; struct amdgpu_bo_list { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index df9bf11f0cb2f..d5c2b19caebd2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -848,6 +848,9 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, struct amdgpu_bo_list_entry *e; struct drm_gem_object *obj; unsigned long index; +#ifndef HAVE_AMDKCL_HMM_MIRROR_ENABLED + unsigned tries = 10; +#endif unsigned int i; int r; @@ -870,6 +873,8 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, mutex_lock(&p->bo_list->bo_list_mutex); + +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED /* Get userptr backing pages. If pages are updated after registered * in amdgpu_gem_userptr_ioctl(), amdgpu_cs_list_validate() will do * amdgpu_ttm_backend_bind() to flush and invalidate new pages @@ -929,6 +934,82 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, goto out_free_user_pages; } } +#else + while (1) { + struct list_head need_pages; + + r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true, + &duplicates); + if (unlikely(r != 0)) { + if (r != -ERESTARTSYS) + DRM_ERROR("ttm_eu_reserve_buffers failed.\n"); + goto error_free_pages; + } + + INIT_LIST_HEAD(&need_pages); + amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) { + struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo); + + if (amdgpu_ttm_tt_userptr_invalidated(bo->tbo.ttm, + &e->user_invalidated) && e->user_pages) { + + /* We acquired a page array, but somebody + * invalidated it. Free it and try again + */ + release_pages(e->user_pages, + bo->tbo.ttm->num_pages); + kvfree(e->user_pages); + e->user_pages = NULL; + } + + if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm) && + !e->user_pages) { + list_del(&e->tv.head); + list_add(&e->tv.head, &need_pages); + + amdgpu_bo_unreserve(bo); + } + } + + if (list_empty(&need_pages)) + break; + + /* Unreserve everything again. */ + ttm_eu_backoff_reservation(&p->ticket, &p->validated); + + /* We tried too many times, just abort */ + if (!--tries) { + r = -EDEADLK; + DRM_ERROR("deadlock in %s\n", __func__); + goto error_free_pages; + } + + /* Fill the page arrays for all userptrs. */ + list_for_each_entry(e, &need_pages, tv.head) { + struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo); + + e->user_pages = kvmalloc_array(bo->tbo.ttm->num_pages, + sizeof(struct page*), + GFP_KERNEL | __GFP_ZERO); + if (!e->user_pages) { + r = -ENOMEM; + DRM_ERROR("calloc failure in %s\n", __func__); + goto error_free_pages; + } + + r = amdgpu_ttm_tt_get_user_pages(bo, e->user_pages); + if (r) { + DRM_ERROR("amdgpu_ttm_tt_get_user_pages failed.\n"); + kvfree(e->user_pages); + e->user_pages = NULL; + goto error_free_pages; + } + } + + /* And try again. */ + list_splice(&need_pages, &p->validated); + } +#endif amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) { struct mm_struct *usermm; @@ -991,6 +1072,8 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, p->bo_list->oa_obj); return 0; + +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED out_free_user_pages: amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) { struct amdgpu_bo *bo = e->bo; @@ -1002,6 +1085,17 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, e->user_pages = NULL; e->range = NULL; } +#else +error_free_pages: + + amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) { + if (!e->user_pages) + continue; + + release_pages(e->user_pages, e->tv.bo->ttm->num_pages); + kvfree(e->user_pages); + } +#endif mutex_unlock(&p->bo_list->bo_list_mutex); return r; } @@ -1317,6 +1411,7 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, amdgpu_job_set_gang_leader(p->jobs[i], leader); } +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED /* No memory allocation is allowed while holding the notifier lock. * The lock is held until amdgpu_cs_submit is finished and fence is * added to BOs. @@ -1337,6 +1432,18 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, mutex_unlock(&p->adev->notifier_lock); return r; } +#else + /* No memory allocation is allowed while holding the mn lock */ + amdgpu_mn_lock(p->mn); + amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) { + struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo); + + if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm)) { + r = -ERESTARTSYS; + goto error_abort; + } + } +#endif p->fence = dma_fence_get(&leader->base.s_fence->finished); drm_exec_for_each_locked_object(&p->exec, index, gobj) { @@ -1380,7 +1487,11 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, amdgpu_vm_move_to_lru_tail(p->adev, &fpriv->vm); +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED mutex_unlock(&p->adev->notifier_lock); +#else + amdgpu_mn_unlock(p->mn); +#endif mutex_unlock(&p->bo_list->bo_list_mutex); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 7e522400e44dd..08e0333553952 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -4062,7 +4062,9 @@ int amdgpu_device_init(struct amdgpu_device *adev, mutex_init(&adev->virt.rlcg_reg_lock); hash_init(adev->mn_hash); mutex_init(&adev->psp.mutex); +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED mutex_init(&adev->notifier_lock); +#endif mutex_init(&adev->pm.stable_pstate_ctx_lock); mutex_init(&adev->benchmark_mutex); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index 5996bd0bddc79..906bc0282355b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -515,14 +515,28 @@ int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, } r = drm_gem_handle_create(filp, gobj, &handle); +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED if (r) goto user_pages_done; args->handle = handle; +#else + /* drop reference from allocate - handle holds it now */ + drm_gem_object_put(gobj); + if (r) + return r; + + args->handle = handle; + return 0; +#endif user_pages_done: +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm, range); +#else + release_pages(bo->tbo.ttm->pages, bo->tbo.ttm->num_pages); +#endif release_object: drm_gem_object_put(gobj); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c index 3c928bc9d48c0..fa888fbcb17ba 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c @@ -51,8 +51,485 @@ #include "amdgpu_amdkfd.h" #include "amdgpu_hmm.h" -#define MAX_WALK_BYTE (2UL << 30) +#ifndef HAVE_AMDKCL_HMM_MIRROR_ENABLED +/** + * struct amdgpu_mn + * + * @adev: amdgpu device pointer + * @mm: process address space + * @mn: MMU notifier structure + * @type: type of MMU notifier + * @work: destruction work item + * @node: hash table node to find structure by adev and mn + * @lock: rw semaphore protecting the notifier nodes + * @objects: interval tree containing amdgpu_mn_nodes + * @read_lock: mutex for recursive locking of @lock + * @recursion: depth of recursion + * + * Data for each amdgpu device and process address space. + */ +struct amdgpu_mn { + /* constant after initialisation */ + struct amdgpu_device *adev; + struct mm_struct *mm; + struct mmu_notifier mn; + enum amdgpu_mn_type type; + + /* only used on destruction */ + struct work_struct work; + + /* protected by adev->mn_lock */ + struct hlist_node node; + + /* objects protected by lock */ + struct rw_semaphore lock; + struct rb_root_cached objects; + struct mutex read_lock; + atomic_t recursion; +}; + +/** + * struct amdgpu_mn_node + * + * @it: interval node defining start-last of the affected address range + * @bos: list of all BOs in the affected address range + * + * Manages all BOs which are affected of a certain range of address space. + */ +struct amdgpu_mn_node { + struct interval_tree_node it; + struct list_head bos; +}; + +/** + * amdgpu_mn_destroy - destroy the MMU notifier + * + * @work: previously sheduled work item + * + * Lazy destroys the notifier from a work item + */ +static void amdgpu_mn_destroy(struct work_struct *work) +{ + struct amdgpu_mn *amn = container_of(work, struct amdgpu_mn, work); + struct amdgpu_device *adev = amn->adev; + struct amdgpu_mn_node *node, *next_node; + struct amdgpu_bo *bo, *next_bo; + + mutex_lock(&adev->mn_lock); + down_write(&amn->lock); + hash_del(&amn->node); + rbtree_postorder_for_each_entry_safe(node, next_node, + &amn->objects.rb_root, it.rb) { + list_for_each_entry_safe(bo, next_bo, &node->bos, mn_list) { + bo->mn = NULL; + list_del_init(&bo->mn_list); + } + kfree(node); + } + up_write(&amn->lock); + mutex_unlock(&adev->mn_lock); + mmu_notifier_unregister_no_release(&amn->mn, amn->mm); + kfree(amn); +} + +/** + * amdgpu_mn_release - callback to notify about mm destruction + * + * @mn: our notifier + * @mm: the mm this callback is about + * + * Shedule a work item to lazy destroy our notifier. + */ +static void amdgpu_mn_release(struct mmu_notifier *mn, + struct mm_struct *mm) +{ + struct amdgpu_mn *amn = container_of(mn, struct amdgpu_mn, mn); + + INIT_WORK(&amn->work, amdgpu_mn_destroy); + schedule_work(&amn->work); +} + + +/** + * amdgpu_mn_lock - take the write side lock for this notifier + * + * @mn: our notifier + */ +void amdgpu_mn_lock(struct amdgpu_mn *mn) +{ + if (mn) + down_write(&mn->lock); +} + +/** + * amdgpu_mn_unlock - drop the write side lock for this notifier + * + * @mn: our notifier + */ +void amdgpu_mn_unlock(struct amdgpu_mn *mn) +{ + if (mn) + up_write(&mn->lock); +} + +/** + * amdgpu_mn_read_lock - take the read side lock for this notifier + * + * @amn: our notifier + */ +static int amdgpu_mn_read_lock(struct amdgpu_mn *amn, bool blockable) +{ + if (blockable) + mutex_lock(&amn->read_lock); + else if (!mutex_trylock(&amn->read_lock)) + return -EAGAIN; + + if (atomic_inc_return(&amn->recursion) == 1) + down_read_non_owner(&amn->lock); + mutex_unlock(&amn->read_lock); + + return 0; +} + +/** + * amdgpu_mn_read_unlock - drop the read side lock for this notifier + * + * @amn: our notifier + */ +static void amdgpu_mn_read_unlock(struct amdgpu_mn *amn) +{ + if (atomic_dec_return(&amn->recursion) == 0) + up_read_non_owner(&amn->lock); +} + +/** + * amdgpu_mn_invalidate_node - unmap all BOs of a node + * + * @node: the node with the BOs to unmap + * @start: start of address range affected + * @end: end of address range affected + * + * Block for operations on BOs to finish and mark pages as accessed and + * potentially dirty. + */ +static void amdgpu_mn_invalidate_node(struct amdgpu_mn_node *node, + unsigned long start, + unsigned long end) +{ + struct amdgpu_bo *bo; + long r; + + list_for_each_entry(bo, &node->bos, mn_list) { + + if (!amdgpu_ttm_tt_affect_userptr(bo->tbo.ttm, start, end)) + continue; + + r = dma_resv_wait_timeout(amdkcl_ttm_resvp(&bo->tbo), + true, false, MAX_SCHEDULE_TIMEOUT); + if (r <= 0) + DRM_ERROR("(%ld) failed to wait for user bo\n", r); + + amdgpu_ttm_tt_mark_user_pages(bo->tbo.ttm); + } +} + +/** + * amdgpu_mn_invalidate_range_start_gfx - callback to notify about mm change + * + * @mn: our notifier + * @range: mmu notifier context + * + * Block for operations on BOs to finish and mark pages as accessed and + * potentially dirty. + */ +static int amdgpu_mn_invalidate_range_start_gfx(struct mmu_notifier *mn, + const struct mmu_notifier_range *range) +{ + struct amdgpu_mn *amn = container_of(mn, struct amdgpu_mn, mn); + struct interval_tree_node *it; + unsigned long end; + + /* notification is exclusive, but interval is inclusive */ + end = range->end - 1; + + /* TODO we should be able to split locking for interval tree and + * amdgpu_mn_invalidate_node + */ + if (amdgpu_mn_read_lock(amn, mmu_notifier_range_blockable(range))) + return -EAGAIN; + + it = interval_tree_iter_first(&amn->objects, range->start, end); + while (it) { + struct amdgpu_mn_node *node; + + if (!mmu_notifier_range_blockable(range)) { + amdgpu_mn_read_unlock(amn); + return -EAGAIN; + } + + node = container_of(it, struct amdgpu_mn_node, it); + it = interval_tree_iter_next(it, range->start, end); + + amdgpu_mn_invalidate_node(node, range->start, end); + } + + return 0; +} + +/** + * amdgpu_mn_invalidate_range_start_hsa - callback to notify about mm change + * + * @mn: our notifier + * @mm: the mm this callback is about + * @start: start of updated range + * @end: end of updated range + * + * We temporarily evict all BOs between start and end. This + * necessitates evicting all user-mode queues of the process. The BOs + * are restorted in amdgpu_mn_invalidate_range_end_hsa. + */ +static int amdgpu_mn_invalidate_range_start_hsa(struct mmu_notifier *mn, + const struct mmu_notifier_range *range) +{ + struct amdgpu_mn *amn = container_of(mn, struct amdgpu_mn, mn); + struct interval_tree_node *it; + unsigned long end; + + /* notification is exclusive, but interval is inclusive */ + end = range->end - 1; + + if (amdgpu_mn_read_lock(amn, mmu_notifier_range_blockable(range))) + return -EAGAIN; + + it = interval_tree_iter_first(&amn->objects, range->start, end); + while (it) { + struct amdgpu_mn_node *node; + struct amdgpu_bo *bo; + + if (!mmu_notifier_range_blockable(range)) { + amdgpu_mn_read_unlock(amn); + return -EAGAIN; + } + + node = container_of(it, struct amdgpu_mn_node, it); + it = interval_tree_iter_next(it, range->start, end); + + list_for_each_entry(bo, &node->bos, mn_list) { + struct kgd_mem *mem = bo->kfd_bo; + + if (amdgpu_ttm_tt_affect_userptr(bo->tbo.ttm, + range->start, + end)) + amdgpu_amdkfd_evict_userptr(mem, range->mm); + } + } + + return 0; +} + +/** + * amdgpu_mn_invalidate_range_end - callback to notify about mm change + * + * @mn: our notifier + * @mm: the mm this callback is about + * @start: start of updated range + * @end: end of updated range + * + * Release the lock again to allow new command submissions. + */ +static void amdgpu_mn_invalidate_range_end(struct mmu_notifier *mn, + const struct mmu_notifier_range *range) +{ + struct amdgpu_mn *amn = container_of(mn, struct amdgpu_mn, mn); + + amdgpu_mn_read_unlock(amn); +} + +static const struct mmu_notifier_ops amdgpu_mn_ops[] = { + [AMDGPU_MN_TYPE_GFX] = { + .release = amdgpu_mn_release, + .invalidate_range_start = amdgpu_mn_invalidate_range_start_gfx, + .invalidate_range_end = amdgpu_mn_invalidate_range_end, + }, + [AMDGPU_MN_TYPE_HSA] = { + .release = amdgpu_mn_release, + .invalidate_range_start = amdgpu_mn_invalidate_range_start_hsa, + .invalidate_range_end = amdgpu_mn_invalidate_range_end, + }, +}; + +/* Low bits of any reasonable mm pointer will be unused due to struct + * alignment. Use these bits to make a unique key from the mm pointer + * and notifier type. + */ +#define AMDGPU_MN_KEY(mm, type) ((unsigned long)(mm) + (type)) + +/** + * amdgpu_mn_get - create notifier context + * + * @adev: amdgpu device pointer + * @type: type of MMU notifier context + * + * Creates a notifier context for current->mm. + */ +struct amdgpu_mn *amdgpu_mn_get(struct amdgpu_device *adev, + enum amdgpu_mn_type type) +{ + struct mm_struct *mm = current->mm; + struct amdgpu_mn *amn; + unsigned long key = AMDGPU_MN_KEY(mm, type); + int r; + + mutex_lock(&adev->mn_lock); + if (down_write_killable(&mm->mmap_sem)) { + mutex_unlock(&adev->mn_lock); + return ERR_PTR(-EINTR); + } + + hash_for_each_possible(adev->mn_hash, amn, node, key) + if (AMDGPU_MN_KEY(amn->mm, amn->type) == key) + goto release_locks; + + amn = kzalloc(sizeof(*amn), GFP_KERNEL); + if (!amn) { + amn = ERR_PTR(-ENOMEM); + goto release_locks; + } + + amn->adev = adev; + amn->mm = mm; + init_rwsem(&amn->lock); + amn->type = type; + amn->mn.ops = &amdgpu_mn_ops[type]; + amn->objects = RB_ROOT_CACHED; + mutex_init(&amn->read_lock); + atomic_set(&amn->recursion, 0); + + r = __mmu_notifier_register(&amn->mn, mm); + if (r) + goto free_amn; + + hash_add(adev->mn_hash, &amn->node, AMDGPU_MN_KEY(mm, type)); + +release_locks: + up_write(&mm->mmap_sem); + mutex_unlock(&adev->mn_lock); + + return amn; + +free_amn: + up_write(&mm->mmap_sem); + mutex_unlock(&adev->mn_lock); + kfree(amn); + + return ERR_PTR(r); +} + +/** + * amdgpu_mn_register - register a BO for notifier updates + * + * @bo: amdgpu buffer object + * @addr: userptr addr we should monitor + * + * Registers an MMU notifier for the given BO at the specified address. + * Returns 0 on success, -ERRNO if anything goes wrong. + */ +int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr) +{ + unsigned long end = addr + amdgpu_bo_size(bo) - 1; + struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); + enum amdgpu_mn_type type = + bo->kfd_bo ? AMDGPU_MN_TYPE_HSA : AMDGPU_MN_TYPE_GFX; + struct amdgpu_mn *amn; + struct amdgpu_mn_node *node = NULL, *new_node; + struct list_head bos; + struct interval_tree_node *it; + + amn = amdgpu_mn_get(adev, type); + if (IS_ERR(amn)) + return PTR_ERR(amn); + + new_node = kmalloc(sizeof(*new_node), GFP_KERNEL); + if (!new_node) + return -ENOMEM; + + INIT_LIST_HEAD(&bos); + + down_write(&amn->lock); + + while ((it = interval_tree_iter_first(&amn->objects, addr, end))) { + kfree(node); + node = container_of(it, struct amdgpu_mn_node, it); + interval_tree_remove(&node->it, &amn->objects); + addr = min(it->start, addr); + end = max(it->last, end); + list_splice(&node->bos, &bos); + } + + if (!node) + node = new_node; + else + kfree(new_node); + + bo->mn = amn; + + node->it.start = addr; + node->it.last = end; + INIT_LIST_HEAD(&node->bos); + list_splice(&bos, &node->bos); + list_add(&bo->mn_list, &node->bos); + + interval_tree_insert(&node->it, &amn->objects); + + up_write(&amn->lock); + + return 0; +} + +/** + * amdgpu_mn_unregister - unregister a BO for notifier updates + * + * @bo: amdgpu buffer object + * + * Remove any registration of MMU notifier updates from the buffer object. + */ +void amdgpu_mn_unregister(struct amdgpu_bo *bo) +{ + struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); + struct amdgpu_mn *amn; + struct list_head *head; + + mutex_lock(&adev->mn_lock); + + amn = bo->mn; + if (amn == NULL) { + mutex_unlock(&adev->mn_lock); + return; + } + + down_write(&amn->lock); + + /* save the next list entry for later */ + head = bo->mn_list.next; + + bo->mn = NULL; + list_del_init(&bo->mn_list); + + if (list_empty(head)) { + struct amdgpu_mn_node *node; + + node = container_of(head, struct amdgpu_mn_node, bos); + interval_tree_remove(&node->it, &amn->objects); + kfree(node); + } + + up_write(&amn->lock); + mutex_unlock(&adev->mn_lock); +} + +#else /* HAVE_AMDKCL_HMM_MIRROR_ENABLED */ +#define MAX_WALK_BYTE (2UL << 30) /** * amdgpu_hmm_invalidate_gfx - callback to notify about mm change * @@ -255,3 +732,4 @@ bool amdgpu_hmm_range_get_pages_done(struct hmm_range *hmm_range) return r; } +#endif /* HAVE_AMDKCL_HMM_MIRROR_ENABLED */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h index e2edcd010cccb..7d7a087899125 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h @@ -24,6 +24,41 @@ #ifndef __AMDGPU_MN_H__ #define __AMDGPU_MN_H__ +#ifndef HAVE_AMDKCL_HMM_MIRROR_ENABLED +#include +#include +/* + * MMU Notifier + */ +struct amdgpu_mn; + +enum amdgpu_mn_type { + AMDGPU_MN_TYPE_GFX, + AMDGPU_MN_TYPE_HSA, +}; + +#if defined(CONFIG_MMU_NOTIFIER) +void amdgpu_mn_lock(struct amdgpu_mn *mn); +void amdgpu_mn_unlock(struct amdgpu_mn *mn); +struct amdgpu_mn *amdgpu_mn_get(struct amdgpu_device *adev, + enum amdgpu_mn_type type); +int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr); +void amdgpu_mn_unregister(struct amdgpu_bo *bo); +#else /* !CONFIG_MMU_NOTIFIER */ +static inline void amdgpu_mn_lock(struct amdgpu_mn *mn) {} +static inline void amdgpu_mn_unlock(struct amdgpu_mn *mn) {} +static inline struct amdgpu_mn *amdgpu_mn_get(struct amdgpu_device *adev, + enum amdgpu_mn_type type) +{ + return NULL; +} +static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr) +{ + return -ENODEV; +} +static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {} +#endif /* CONFIG_MMU_NOTIFIER */ +#else /* HAVE_AMDKCL_HMM_MIRROR_ENABLED */ #include #include #include @@ -49,5 +84,6 @@ static inline int amdgpu_hmm_register(struct amdgpu_bo *bo, unsigned long addr) } static inline void amdgpu_hmm_unregister(struct amdgpu_bo *bo) {} #endif +#endif /* HAVE_AMDKCL_HMM_MIRROR_ENABLED */ #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h index cd327b9c1cca7..2775791d2761f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h @@ -112,9 +112,14 @@ struct amdgpu_bo { /* Constant after initialization */ struct amdgpu_bo *parent; +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED #ifdef CONFIG_MMU_NOTIFIER struct mmu_interval_notifier notifier; #endif +#else + struct list_head mn_list; +#endif + struct kgd_mem *kfd_bo; /* DGMA imported buffer info */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 0224bd5e6ca24..33b6c425596bd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -32,6 +32,9 @@ #include #include +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED +#include +#endif #include #include #include @@ -707,6 +710,13 @@ uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type) /* * TTM backend functions. */ +#ifndef HAVE_AMDKCL_HMM_MIRROR_ENABLED +struct amdgpu_ttm_gup_task_list { + struct list_head list; + struct task_struct *task; +}; +#endif + struct amdgpu_ttm_tt { struct ttm_tt ttm; struct drm_gem_object *gobj; @@ -715,12 +725,19 @@ struct amdgpu_ttm_tt { struct task_struct *usertask; uint32_t userflags; bool bound; +#ifndef HAVE_AMDKCL_HMM_MIRROR_ENABLED + spinlock_t guptasklock; + struct list_head guptasks; + atomic_t mmu_invalidations; + uint32_t last_set_pages; +#endif /* HAVE_AMDKCL_HMM_MIRROR_ENABLED */ int32_t pool_id; }; #define ttm_to_amdgpu_ttm_tt(ptr) container_of(ptr, struct amdgpu_ttm_tt, ttm) #ifdef CONFIG_DRM_AMDGPU_USERPTR +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED /* * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user * memory and start HMM tracking CPU page table update @@ -808,8 +825,89 @@ bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm, return !amdgpu_hmm_range_get_pages_done(range); } -#endif +#else +/* + * amdgpu_ttm_tt_get_user_pages - Pin pages of memory pointed to by a USERPTR + * pointer to memory + * + * Called by amdgpu_gem_userptr_ioctl() and amdgpu_cs_parser_bos(). + * This provides a wrapper around the get_user_pages() call to provide + * device accessible pages that back user memory. + */ +int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages) +{ + struct ttm_tt *ttm = bo->tbo.ttm; + struct amdgpu_ttm_tt *gtt = (void *)ttm; + struct mm_struct *mm = gtt->usertask->mm; + unsigned int flags = 0; + unsigned pinned = 0; + int r; + + if (!mm) /* Happens during process shutdown */ + return -ESRCH; + + if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY)) + flags |= FOLL_WRITE; + + down_read(&mm->mmap_sem); + + if (gtt->userflags & AMDGPU_GEM_USERPTR_ANONONLY) { + /* + * check that we only use anonymous memory to prevent problems + * with writeback + */ + unsigned long end = gtt->userptr + ttm->num_pages * PAGE_SIZE; + struct vm_area_struct *vma; + + vma = find_vma(mm, gtt->userptr); + if (!vma || vma->vm_file || vma->vm_end < end) { + up_read(&mm->mmap_sem); + return -EPERM; + } + } + + /* loop enough times using contiguous pages of memory */ + do { + unsigned num_pages = ttm->num_pages - pinned; + uint64_t userptr = gtt->userptr + pinned * PAGE_SIZE; + struct page **p = pages + pinned; + struct amdgpu_ttm_gup_task_list guptask; + + guptask.task = current; + spin_lock(>t->guptasklock); + list_add(&guptask.list, >t->guptasks); + spin_unlock(>t->guptasklock); + + if (mm == current->mm) + r = get_user_pages(userptr, num_pages, flags, p, NULL); + else + r = get_user_pages_remote(mm, userptr, num_pages, + flags, p, NULL, NULL); + + spin_lock(>t->guptasklock); + list_del(&guptask.list); + spin_unlock(>t->guptasklock); + + if (r < 0) + goto release_pages; + + pinned += r; + + } while (pinned < ttm->num_pages); + + up_read(&mm->mmap_sem); + return 0; + +release_pages: + release_pages(pages, pinned); + up_read(&mm->mmap_sem); + return r; +} +#endif /* HAVE_AMDKCL_HMM_MIRROR_ENABLED */ +#endif /* CONFIG_DRM_AMDGPU_USERPTR */ + +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED /* * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary. * @@ -825,6 +923,52 @@ void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages) ttm->pages[i] = pages ? pages[i] : NULL; } +#else +/** + * amdgpu_ttm_tt_set_user_pages - Copy pages in, putting old pages as necessary. + * + * Called by amdgpu_cs_list_validate(). This creates the page list + * that backs user memory and will ultimately be mapped into the device + * address space. + */ +void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages) +{ + struct amdgpu_ttm_tt *gtt = (void *)ttm; + unsigned i; + + gtt->last_set_pages = atomic_read(>t->mmu_invalidations); + for (i = 0; i < ttm->num_pages; ++i) { + if (ttm->pages[i]) + put_page(ttm->pages[i]); + + ttm->pages[i] = pages ? pages[i] : NULL; + } +} + +/** + * amdgpu_ttm_tt_mark_user_page - Mark pages as dirty + * + * Called while unpinning userptr pages + */ +void amdgpu_ttm_tt_mark_user_pages(struct ttm_tt *ttm) +{ + struct amdgpu_ttm_tt *gtt = (void *)ttm; + unsigned i; + + for (i = 0; i < ttm->num_pages; ++i) { + struct page *page = ttm->pages[i]; + + if (!page) + continue; + + if (!(gtt->userflags & AMDGPU_GEM_USERPTR_READONLY)) + set_page_dirty(page); + + mark_page_accessed(page); + } +} +#endif + /* * amdgpu_ttm_tt_pin_userptr - prepare the sg table with the user pages * @@ -882,7 +1026,15 @@ static void amdgpu_ttm_tt_unpin_userptr(struct ttm_device *bdev, /* unmap the pages mapped to the device */ dma_unmap_sgtable(adev->dev, ttm->sg, direction, 0); + +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED sg_free_table(ttm->sg); +#else + /* mark the pages as dirty */ + amdgpu_ttm_tt_mark_user_pages(ttm); + + sg_free_table(ttm->sg); +#endif } /* @@ -1298,6 +1450,13 @@ int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo, gtt->usertask = current->group_leader; get_task_struct(gtt->usertask); +#ifndef HAVE_AMDKCL_HMM_MIRROR_ENABLED + spin_lock_init(>t->guptasklock); + INIT_LIST_HEAD(>t->guptasks); + atomic_set(>t->mmu_invalidations, 0); + gtt->last_set_pages = 0; +#endif + return 0; } @@ -1317,6 +1476,7 @@ struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm) return gtt->usertask->mm; } +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED /* * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an * address range for the current task. @@ -1356,6 +1516,74 @@ bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm) return true; } +#else +/* + * amdgpu_ttm_tt_affect_userptr - Determine if a ttm_tt object lays inside an + * address range for the current task. + * + */ +bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, + unsigned long end) +{ + struct amdgpu_ttm_tt *gtt = (void *)ttm; + struct amdgpu_ttm_gup_task_list *entry; + unsigned long size; + + if (gtt == NULL || !gtt->userptr) + return false; + + /* Return false if no part of the ttm_tt object lies within + * the range + */ + size = (unsigned long)gtt->ttm.num_pages * PAGE_SIZE; + if (gtt->userptr > end || gtt->userptr + size <= start) + return false; + + /* Search the lists of tasks that hold this mapping and see + * if current is one of them. If it is return false. + */ + spin_lock(>t->guptasklock); + list_for_each_entry(entry, >t->guptasks, list) { + if (entry->task == current) { + spin_unlock(>t->guptasklock); + return false; + } + } + spin_unlock(>t->guptasklock); + + atomic_inc(>t->mmu_invalidations); + + return true; +} + +/** + * amdgpu_ttm_tt_userptr_invalidated - Has the ttm_tt object been invalidated? + */ +bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm, + int *last_invalidated) +{ + struct amdgpu_ttm_tt *gtt = (void *)ttm; + int prev_invalidated = *last_invalidated; + + *last_invalidated = atomic_read(>t->mmu_invalidations); + return prev_invalidated != *last_invalidated; +} + +/** + * amdgpu_ttm_tt_userptr_needs_pages - Have the pages backing this ttm_tt object + * been invalidated since the last time they've been set? + */ +bool amdgpu_ttm_tt_userptr_needs_pages(struct ttm_tt *ttm) +{ + struct amdgpu_ttm_tt *gtt = (void *)ttm; + + if (gtt == NULL || !gtt->userptr) + return false; + + return atomic_read(>t->mmu_invalidations) != gtt->last_set_pages; +} +#endif /* HAVE_AMDKCL_HMM_MIRROR_ENABLED */ + /* * amdgpu_ttm_tt_is_readonly - Is the ttm_tt object read only? */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h index a3477ae7996b6..a49d8718d6432 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -227,9 +227,14 @@ bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm); struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm); bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, unsigned long end, unsigned long *userptr); +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED +bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm); +#else bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm, int *last_invalidated); -bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm); +void amdgpu_ttm_tt_mark_user_pages(struct ttm_tt *ttm); +bool amdgpu_ttm_tt_userptr_needs_pages(struct ttm_tt *ttm); +#endif bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm); uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem); uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm, diff --git a/drivers/gpu/drm/amd/dkms/m4/hmm.m4 b/drivers/gpu/drm/amd/dkms/m4/hmm.m4 new file mode 100644 index 0000000000000..5cda4aed70d25 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/hmm.m4 @@ -0,0 +1,35 @@ +dnl # +dnl # 93f4e735b6d9 - mm/hmm: remove hmm_range_dma_map and hmm_range_dma_unmap 2019-11-23 19:56:45 -0400 +dnl # d28c2c9a4877 - mm/hmm: make full use of walk_page_range() 2019-11-23 19:56:45 -0400 +dnl # d3eeb1d77c5d - xen/gntdev: use mmu_interval_notifier_insert 2019-11-23 19:56:45 -0400 +dnl # a22dd506400d - mm/hmm: remove hmm_mirror and related 2019-11-23 19:56:45 -0400 +dnl # 81fa1af31b5d - drm/amdgpu: Use mmu_interval_notifier instead of hmm_mirror 2019-11-23 19:56:45 -0400 +dnl # 62914a99dee5 - drm/amdgpu: Use mmu_interval_insert instead of hmm_mirror 2019-11-23 19:56:45 -0400 +dnl # a9ae8731e6e5 - drm/amdgpu: Call find_vma under mmap_sem 2019-11-23 19:56:44 -0400 +dnl # 20fef4ef84bf - nouveau: use mmu_interval_notifier instead of hmm_mirror 2019-11-23 19:56:44 -0400 +dnl # c625c274ee00 - nouveau: use mmu_notifier directly for invalidate_range_start 2019-11-23 19:56:44 -0400 +dnl # 3506ff69c3ec - drm/radeon: use mmu_interval_notifier_insert 2019-11-23 19:56:44 -0400 +dnl # 3889551db212 - RDMA/hfi1: Use mmu_interval_notifier_insert for user_exp_rcv 2019-11-23 19:56:44 -0400 +dnl # f25a546e6529 - RDMA/odp: Use mmu_interval_notifier_insert() 2019-11-23 19:56:44 -0400 +dnl # 107e899874e9 - mm/hmm: define the pre-processor related parts of hmm.h even if disabled 2019-11-23 19:56:44 -0400 +dnl # v5.4-rc5-20-g04ec32fbc2b2 - mm/hmm: allow hmm_range to be used with a mmu_interval_notifier or hmm_mirror 2019-11-23 19:56:44 -0400 +dnl # 99cb252f5e68 - mm/mmu_notifier: add an interval tree notifier 2019-11-23 19:56:44 -0400 +dnl # 56f434f40f05 - mm/mmu_notifier: define the header pre-processor parts even if disabled 2019-11-12 20:18:27 -0400 +dnl # +AC_DEFUN([AC_AMDGPU_HMM], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + #ifdef CONFIG_HMM_MIRROR + struct hmm_range *range = NULL; + range->notifier = NULL; + #else + #error CONFIG_HMM_MIRROR not enabled + #endif + ], [ + AC_DEFINE(HAVE_AMDKCL_HMM_MIRROR_ENABLED, 1, + [hmm support is enabled]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index d76fdbebea066..4792ec8fcf5c3 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -53,6 +53,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_TTM_SG_TT_INIT AC_AMDGPU_TTM_BUFFER_OBJECT AC_AMDGPU_DEVCGROUP_CHECK_PERMISSION + AC_AMDGPU_HMM AC_AMDGPU_DMA_BUF AC_AMDGPU_DRM_CACHE AC_AMDGPU_DRM_DEBUG_ENABLED From 0219fae6d977fd43e08756857c48d093d46a6160 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 31 Aug 2020 15:42:28 +0800 Subject: [PATCH 0310/1868] drm/amdkcl: fake hmm_range_fault() protocol changed in v5.6-rc3-21-g6bfef2f91945("mm/hmm: remove HMM_FAULT_SNAPSHOT") Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/hmm.m4 | 16 ++++++++++++++++ include/kcl/backport/kcl_hmm.h | 18 ++++++++++++++++++ 3 files changed, 35 insertions(+) create mode 100644 include/kcl/backport/kcl_hmm.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 60e80984d0d19..2cb3aae626abb 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -37,6 +37,7 @@ #include #include #include +#include #include #ifdef HAVE_DRM_DRIVER_GEM_PRIME_RES_OBJ #include diff --git a/drivers/gpu/drm/amd/dkms/m4/hmm.m4 b/drivers/gpu/drm/amd/dkms/m4/hmm.m4 index 5cda4aed70d25..1e351ff9c3b3f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/hmm.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/hmm.m4 @@ -1,3 +1,18 @@ +dnl # +dnl # v5.6-rc3-21-g6bfef2f91945 +dnl # mm/hmm: remove HMM_FAULT_SNAPSHOT +dnl # +AC_DEFUN([AC_AMDGPU_HMM_RANGE_FAULT], [ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + hmm_range_fault(NULL); + ], [ + AC_DEFINE(HAVE_HMM_RANGE_FAULT_1ARG, 1, + [hmm_range_fault() wants 1 arg]) + ]) +]) + dnl # dnl # 93f4e735b6d9 - mm/hmm: remove hmm_range_dma_map and hmm_range_dma_unmap 2019-11-23 19:56:45 -0400 dnl # d28c2c9a4877 - mm/hmm: make full use of walk_page_range() 2019-11-23 19:56:45 -0400 @@ -30,6 +45,7 @@ AC_DEFUN([AC_AMDGPU_HMM], [ ], [ AC_DEFINE(HAVE_AMDKCL_HMM_MIRROR_ENABLED, 1, [hmm support is enabled]) + AC_AMDGPU_HMM_RANGE_FAULT ]) ]) ]) diff --git a/include/kcl/backport/kcl_hmm.h b/include/kcl/backport/kcl_hmm.h new file mode 100644 index 0000000000000..233b0cbda947a --- /dev/null +++ b/include/kcl/backport/kcl_hmm.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_BACKPORT_KCL_HMM_H +#define _KCL_BACKPORT_KCL_HMM_H + +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED +#include + +#ifndef HAVE_HMM_RANGE_FAULT_1ARG +static inline +int _kcl_hmm_range_fault(struct hmm_range *range) +{ + return hmm_range_fault(range, 0); +} +#define hmm_range_fault _kcl_hmm_range_fault +#endif /* HAVE_HMM_RANGE_FAULT_1ARG */ + +#endif /* HAVE_AMDKCL_HMM_MIRROR_ENABLED */ +#endif From 71c533c7887b6c7d28508770962fac821b8eab7a Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 31 Aug 2020 16:06:54 +0800 Subject: [PATCH 0311/1868] drm/amdkcl: test whether hmm remove the customizable pfn format Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 21 +++++++++++++++++++- drivers/gpu/drm/amd/dkms/m4/hmm.m4 | 26 +++++++++++++++++++++---- 2 files changed, 42 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 33b6c425596bd..92c755aa0a46b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -738,6 +738,20 @@ struct amdgpu_ttm_tt { #ifdef CONFIG_DRM_AMDGPU_USERPTR #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED +#ifndef HAVE_HMM_DROP_CUSTOMIZABLE_PFN_FORMAT +/* flags used by HMM internal, not related to CPU/GPU PTE flags */ +static const uint64_t hmm_range_flags[HMM_PFN_FLAG_MAX] = { + (1 << 0), /* HMM_PFN_VALID */ + (1 << 1), /* HMM_PFN_WRITE */ + 0 /* HMM_PFN_DEVICE_PRIVATE */ +}; + +static const uint64_t hmm_range_values[HMM_PFN_VALUE_MAX] = { + 0xfffffffffffffffeUL, /* HMM_PFN_ERROR */ + 0, /* HMM_PFN_NONE */ + 0xfffffffffffffffcUL /* HMM_PFN_SPECIAL */ +}; +#endif /* * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user * memory and start HMM tracking CPU page table update @@ -821,7 +835,12 @@ bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm, DRM_DEBUG_DRIVER("user_pages_done 0x%llx pages 0x%x\n", gtt->userptr, ttm->num_pages); - WARN_ONCE(!range->hmm_pfns, "No user pages to check\n"); +#ifndef HAVE_HMM_DROP_CUSTOMIZABLE_PFN_FORMAT + WARN_ONCE(!range->pfns, +#else + WARN_ONCE(!range->hmm_pfns, +#endif + "No user pages to check\n"); return !amdgpu_hmm_range_get_pages_done(range); } diff --git a/drivers/gpu/drm/amd/dkms/m4/hmm.m4 b/drivers/gpu/drm/amd/dkms/m4/hmm.m4 index 1e351ff9c3b3f..228e66022b959 100644 --- a/drivers/gpu/drm/amd/dkms/m4/hmm.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/hmm.m4 @@ -1,15 +1,33 @@ dnl # -dnl # v5.6-rc3-21-g6bfef2f91945 -dnl # mm/hmm: remove HMM_FAULT_SNAPSHOT +dnl # v5.7-rc4-4-g2733ea144dcc mm/hmm: remove the customizable pfn format from hmm_range_fault +dnl # v5.7-rc4-3-g5c8f3c4cf18a mm/hmm: remove HMM_PFN_SPECIAL +dnl # v5.7-rc4-2-g4e2490843d55 drm/amdgpu: remove dead code after hmm_range_fault() +dnl # v5.7-rc4-1-gbe957c886d92 mm/hmm: make hmm_range_fault return 0 or -1 dnl # AC_DEFUN([AC_AMDGPU_HMM_RANGE_FAULT], [ AC_KERNEL_TRY_COMPILE([ #include ], [ - hmm_range_fault(NULL); + enum hmm_pfn_flags flag; + flag = HMM_PFN_REQ_FAULT; ], [ + AC_DEFINE(HAVE_HMM_DROP_CUSTOMIZABLE_PFN_FORMAT, 1, + [hmm remove the customizable pfn format]) AC_DEFINE(HAVE_HMM_RANGE_FAULT_1ARG, 1, - [hmm_range_fault() wants 1 arg]) + [hmm_range_fault() wants 1 arg]) + ], [ + dnl # + dnl # v5.6-rc3-21-g6bfef2f91945 + dnl # mm/hmm: remove HMM_FAULT_SNAPSHOT + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + hmm_range_fault(NULL);; + ], [ + AC_DEFINE(HAVE_HMM_RANGE_FAULT_1ARG, 1, + [hmm_range_fault() wants 1 arg]) + ]) ]) ]) From f09efc5f9a7ec9c3484233fb49f7ef9253366239 Mon Sep 17 00:00:00 2001 From: chen gong Date: Fri, 3 May 2019 11:53:41 +0800 Subject: [PATCH 0312/1868] drm/amdkcl: Test whether invalidate_range_start() wants 2 args or 5 args Signed-off-by: chen gong Reviewed-by: Anatoli Antonovitch Signed-off-by: Yifan Zhang Signed-off-by: Jack Gui drm/amdkcl: fix invalidate_range_end() leverage HAVE_2ARGS_INVALIDATE_RANGE_START for invalidate_range_end() check Signed-off-by: Flora Cui Reviewed-by: Feifei Xu Signed-off-by: Jack Gui --- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c | 145 ++++++++++++++++++ .../drm/amd/dkms/m4/invalidate-range-start.m4 | 36 +++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 182 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/invalidate-range-start.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c index fa888fbcb17ba..e75b0846faf94 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c @@ -172,6 +172,20 @@ void amdgpu_mn_unlock(struct amdgpu_mn *mn) up_write(&mn->lock); } +#if !defined(HAVE_5ARGS_INVALIDATE_RANGE_START) && !defined(HAVE_2ARGS_INVALIDATE_RANGE_START) +/** + * amdgpu_mn_read_lock - take the read side lock for this notifier + * + * @amn: our notifier + */ +static void amdgpu_mn_read_lock(struct amdgpu_mn *amn) +{ + mutex_lock(&amn->read_lock); + if (atomic_inc_return(&amn->recursion) == 1) + down_read_non_owner(&amn->lock); + mutex_unlock(&amn->read_lock); +} +#else /** * amdgpu_mn_read_lock - take the read side lock for this notifier * @@ -190,6 +204,7 @@ static int amdgpu_mn_read_lock(struct amdgpu_mn *amn, bool blockable) return 0; } +#endif /** * amdgpu_mn_read_unlock - drop the read side lock for this notifier @@ -233,6 +248,7 @@ static void amdgpu_mn_invalidate_node(struct amdgpu_mn_node *node, } } +#if defined(HAVE_2ARGS_INVALIDATE_RANGE_START) /** * amdgpu_mn_invalidate_range_start_gfx - callback to notify about mm change * @@ -327,6 +343,129 @@ static int amdgpu_mn_invalidate_range_start_hsa(struct mmu_notifier *mn, return 0; } +#else + +/** + * amdgpu_mn_invalidate_range_start_gfx - callback to notify about mm change + * + * @mn: our notifier + * @mm: the mm this callback is about + * @start: start of updated range + * @end: end of updated range + * + * Block for operations on BOs to finish and mark pages as accessed and + * potentially dirty. + */ +#if defined(HAVE_5ARGS_INVALIDATE_RANGE_START) +static int amdgpu_mn_invalidate_range_start_gfx(struct mmu_notifier *mn, + struct mm_struct *mm, + unsigned long start, + unsigned long end, + bool blockable) +#else +static void amdgpu_mn_invalidate_range_start_gfx(struct mmu_notifier *mn, + struct mm_struct *mm, + unsigned long start, + unsigned long end) +#endif +{ + struct amdgpu_mn *amn = container_of(mn, struct amdgpu_mn, mn); + struct interval_tree_node *it; + + /* notification is exclusive, but interval is inclusive */ + end -= 1; + +#if defined(HAVE_5ARGS_INVALIDATE_RANGE_START) + if (amdgpu_mn_read_lock(amn, blockable)) + return -EAGAIN; +#else + amdgpu_mn_read_lock(amn); +#endif + + it = interval_tree_iter_first(&amn->objects, start, end); + while (it) { + struct amdgpu_mn_node *node; + +#if defined(HAVE_5ARGS_INVALIDATE_RANGE_START) + if (!blockable) { + amdgpu_mn_read_unlock(amn); + return -EAGAIN; + } +#endif + + node = container_of(it, struct amdgpu_mn_node, it); + it = interval_tree_iter_next(it, start, end); + + amdgpu_mn_invalidate_node(node, start, end); + } +} + + +/** + * amdgpu_mn_invalidate_range_start_hsa - callback to notify about mm change + * + * @mn: our notifier + * @mm: the mm this callback is about + * @start: start of updated range + * @end: end of updated range + * + * We temporarily evict all BOs between start and end. This + * necessitates evicting all user-mode queues of the process. The BOs + * are restorted in amdgpu_mn_invalidate_range_end_hsa. + */ +#if defined(HAVE_5ARGS_INVALIDATE_RANGE_START) +static int amdgpu_mn_invalidate_range_start_hsa(struct mmu_notifier *mn, + struct mm_struct *mm, + unsigned long start, + unsigned long end, + bool blockable) +#else +static void amdgpu_mn_invalidate_range_start_hsa(struct mmu_notifier *mn, + struct mm_struct *mm, + unsigned long start, + unsigned long end) +#endif +{ + struct amdgpu_mn *amn = container_of(mn, struct amdgpu_mn, mn); + struct interval_tree_node *it; + + /* notification is exclusive, but interval is inclusive */ + end -= 1; + +#if defined(HAVE_5ARGS_INVALIDATE_RANGE_START) + if (amdgpu_mn_read_lock(amn, blockable)) + return -EAGAIN; +#else + amdgpu_mn_read_lock(amn); +#endif + + it = interval_tree_iter_first(&amn->objects, start, end); + while (it) { + struct amdgpu_mn_node *node; + struct amdgpu_bo *bo; + +#if defined(HAVE_5ARGS_INVALIDATE_RANGE_START) + if (!blockable) { + amdgpu_mn_read_unlock(amn); + return -EAGAIN; + } +#endif + + node = container_of(it, struct amdgpu_mn_node, it); + it = interval_tree_iter_next(it, start, end); + + list_for_each_entry(bo, &node->bos, mn_list) { + struct kgd_mem *mem = bo->kfd_bo; + + if (amdgpu_ttm_tt_affect_userptr(bo->tbo.ttm, + start, end)) + amdgpu_amdkfd_evict_userptr(mem, mm); + } + } +} + +#endif + /** * amdgpu_mn_invalidate_range_end - callback to notify about mm change * @@ -338,7 +477,13 @@ static int amdgpu_mn_invalidate_range_start_hsa(struct mmu_notifier *mn, * Release the lock again to allow new command submissions. */ static void amdgpu_mn_invalidate_range_end(struct mmu_notifier *mn, +#ifdef HAVE_2ARGS_INVALIDATE_RANGE_START const struct mmu_notifier_range *range) +#else + struct mm_struct *mm, + unsigned long start, + unsigned long end) +#endif { struct amdgpu_mn *amn = container_of(mn, struct amdgpu_mn, mn); diff --git a/drivers/gpu/drm/amd/dkms/m4/invalidate-range-start.m4 b/drivers/gpu/drm/amd/dkms/m4/invalidate-range-start.m4 new file mode 100644 index 0000000000000..d9edaefbebdcf --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/invalidate-range-start.m4 @@ -0,0 +1,36 @@ +dnl # +dnl # commit 5d6527a784f7a6d247961e046e830de8d71b47d1 +dnl # Author: Jérôme Glisse +dnl # Date: Fri Dec 28 00:38:05 2018 -0800 +dnl # mm/mmu_notifier: use structure for invalidate_range_start/end callback +dnl # Patch series "mmu notifier contextual informations", v2. +dnl # +AC_DEFUN([AC_AMDGPU_INVALIDATE_RANGE_START], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct mmu_notifier_ops *ops = NULL; + ops->invalidate_range_start(NULL, NULL); + ], [ + AC_DEFINE(HAVE_2ARGS_INVALIDATE_RANGE_START, 1, + whether invalidate_range_start() wants 2 args) + ], [ + dnl # + dnl # commit 93065ac753e4443840a057bfef4be71ec766fde9 + dnl # Author: Michal Hocko + dnl # Date: Tue Aug 21 21:52:33 2018 -0700 + dnl # mm, oom: distinguish blockable mode for mmu notifiers + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct mmu_notifier_ops *ops = NULL; + ops->invalidate_range_start(NULL, NULL, 1, 1, 1); + ], [ + AC_DEFINE(HAVE_5ARGS_INVALIDATE_RANGE_START, 1, + whether invalidate_range_start() wants 5 args) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 4792ec8fcf5c3..611b37e27b6fc 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -54,6 +54,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_TTM_BUFFER_OBJECT AC_AMDGPU_DEVCGROUP_CHECK_PERMISSION AC_AMDGPU_HMM + AC_AMDGPU_INVALIDATE_RANGE_START AC_AMDGPU_DMA_BUF AC_AMDGPU_DRM_CACHE AC_AMDGPU_DRM_DEBUG_ENABLED From cf9665a27faa723d67d167b21576d127051bdf43 Mon Sep 17 00:00:00 2001 From: Chengming Gui Date: Wed, 28 Aug 2019 11:21:44 +0800 Subject: [PATCH 0313/1868] drm/amdkcl: Test whether down_write_killable() is available (v2) down_write_killable() introduced by kernel v4.7-rc1~192^2~3 v2: typo fixed, locking/rwsem.h --> locking/rwsem.c Signed-off-by: Chengming Gui Reviewed-by: Flora Cui Signed-off-by: Jack Gui --- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c | 4 ++++ .../gpu/drm/amd/dkms/m4/down-write-killable.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 22 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/down-write-killable.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c index e75b0846faf94..9af6fd2c51641 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c @@ -526,10 +526,14 @@ struct amdgpu_mn *amdgpu_mn_get(struct amdgpu_device *adev, int r; mutex_lock(&adev->mn_lock); +#ifndef HAVE_DOWN_WRITE_KILLABLE + down_write(&mm->mmap_sem); +#else if (down_write_killable(&mm->mmap_sem)) { mutex_unlock(&adev->mn_lock); return ERR_PTR(-EINTR); } +#endif hash_for_each_possible(adev->mn_hash, amn, node, key) if (AMDGPU_MN_KEY(amn->mm, amn->type) == key) diff --git a/drivers/gpu/drm/amd/dkms/m4/down-write-killable.m4 b/drivers/gpu/drm/amd/dkms/m4/down-write-killable.m4 new file mode 100644 index 0000000000000..c048731800f48 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/down-write-killable.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit 916633a403702549d37ea353e63a68e5b0dc27ad +dnl # locking/rwsem: Provide down_write_killable() +dnl # +AC_DEFUN([AC_AMDGPU_DOWN_WRITE_KILLABLE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + int ret; + ret = down_write_killable(NULL); + ], [down_write_killable],[kernel/locking/rwsem.c],[ + AC_DEFINE(HAVE_DOWN_WRITE_KILLABLE, 1, + [down_write_killable() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 611b37e27b6fc..62de650b61d4b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -55,6 +55,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DEVCGROUP_CHECK_PERMISSION AC_AMDGPU_HMM AC_AMDGPU_INVALIDATE_RANGE_START + AC_AMDGPU_DOWN_WRITE_KILLABLE AC_AMDGPU_DMA_BUF AC_AMDGPU_DRM_CACHE AC_AMDGPU_DRM_DEBUG_ENABLED From b763a465fce0ea72f8110c2481357da12b200ef2 Mon Sep 17 00:00:00 2001 From: Philip Yang Date: Thu, 12 Dec 2019 10:04:29 -0500 Subject: [PATCH 0314/1868] drm/amdkcl: add return value for amdgpu_mn_invalidate_range_start_gfx Otherwise it returns random value and generates below kernel warning. The return value is ignored by the calling function, this will just remove the warnings, no function change. v2: add return value for amdgpu_mn_invalidate_range_start_hsa Dec 9 10:08:33 debian-rocm kernel: [ 883.795760] amdgpu_mn_invalidate_range_start_hsa+0x0/0x100 [amdgpu] callback failed with 226470832 in blockable context. Dec 9 10:08:33 debian-rocm kernel: [ 883.805443] amdgpu_mn_invalidate_range_start_hsa+0x0/0x100 [amdgpu] callback failed with 226470832 in blockable context. Change-Id: I2ad1c8703c4d4ec615ccdd5d402dd2ccdf08136b Signed-off-by: Philip Yang Reviewed-by: Eric Huang Signed-off-by: Yifan Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c index 9af6fd2c51641..41fc2d09d7b0f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c @@ -398,6 +398,10 @@ static void amdgpu_mn_invalidate_range_start_gfx(struct mmu_notifier *mn, amdgpu_mn_invalidate_node(node, start, end); } + +#if defined(HAVE_5ARGS_INVALIDATE_RANGE_START) + return 0; +#endif } @@ -462,6 +466,10 @@ static void amdgpu_mn_invalidate_range_start_hsa(struct mmu_notifier *mn, amdgpu_amdkfd_evict_userptr(mem, mm); } } + +#if defined(HAVE_5ARGS_INVALIDATE_RANGE_START) + return 0; +#endif } #endif From 74269d36e1c56e851da4010e491a61c078b595cc Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 6 Aug 2019 20:15:47 -0300 Subject: [PATCH 0315/1868] drm/amdkcl: Test whether mmu_notifier_synchronize is available introduced by kernel v5.3-rc1-29-g2c7933f53f6b Signed-off-by: Flora Cui Signed-off-by: Jack Gui Signed-off-by: Yifan Zhang Change-Id: I0a46e15c16ec5d3e79687a1a33e50069ba956244 --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 ++ drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 4 +++ drivers/gpu/drm/amd/amdkfd/kfd_process.c | 21 +++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../amd/dkms/m4/mmu-notifier-synchronize.m4 | 31 +++++++++++++++++++ 5 files changed, 59 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/mmu-notifier-synchronize.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 962e632101a0f..eb436b991b43f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3175,7 +3175,9 @@ static void __exit amdgpu_exit(void) amdgpu_acpi_release(); amdgpu_sync_fini(); amdgpu_fence_slab_fini(); +#ifdef HAVE_MMU_NOTIFIER_SYNCHRONIZE mmu_notifier_synchronize(); +#endif amdgpu_xcp_drv_release(); } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index d36e91dd69fa5..367f4f7460481 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -947,6 +947,10 @@ struct kfd_process { /* We want to receive a notification when the mm_struct is destroyed */ struct mmu_notifier mmu_notifier; +#ifndef HAVE_MMU_NOTIFIER_SYNCHRONIZE + /* Use for delayed freeing of kfd_process structure */ + struct rcu_head rcu; +#endif u32 pasid; /* diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index c370395287b0d..f513878b00f70 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -1163,6 +1163,7 @@ static void kfd_process_ref_release(struct kref *ref) queue_work(kfd_process_wq, &p->release_work); } +#ifdef HAVE_MMU_NOTIFIER_SYNCHRONIZE static struct mmu_notifier *kfd_process_alloc_notifier(struct mm_struct *mm) { int idx = srcu_read_lock(&kfd_processes_srcu); @@ -1177,6 +1178,14 @@ static void kfd_process_free_notifier(struct mmu_notifier *mn) { kfd_unref_process(container_of(mn, struct kfd_process, mmu_notifier)); } +#else +static void kfd_process_destroy_delayed(struct rcu_head *rcu) +{ + struct kfd_process *p = container_of(rcu, struct kfd_process, rcu); + + kfd_unref_process(p); +} +#endif static void kfd_process_notifier_release_internal(struct kfd_process *p) { @@ -1252,8 +1261,10 @@ static void kfd_process_notifier_release(struct mmu_notifier *mn, static const struct mmu_notifier_ops kfd_process_mmu_notifier_ops = { .release = kfd_process_notifier_release, +#ifdef HAVE_MMU_NOTIFIER_SYNCHRONIZE .alloc_notifier = kfd_process_alloc_notifier, .free_notifier = kfd_process_free_notifier, +#endif }; /* @@ -1474,7 +1485,9 @@ void kfd_process_set_trap_debug_flag(struct qcm_process_device *qpd, static struct kfd_process *create_process(const struct task_struct *thread) { struct kfd_process *process; +#ifdef HAVE_MMU_NOTIFIER_PUT struct mmu_notifier *mn; +#endif int err = -ENOMEM; process = kzalloc(sizeof(*process), GFP_KERNEL); @@ -1531,6 +1544,7 @@ static struct kfd_process *create_process(const struct task_struct *thread) */ kref_get(&process->ref); +#ifdef HAVE_MMU_NOTIFIER_PUT /* MMU notifier registration must be the last call that can fail * because after this point we cannot unwind the process creation. * After this point, mmu_notifier_put will trigger the cleanup by @@ -1542,6 +1556,13 @@ static struct kfd_process *create_process(const struct task_struct *thread) goto err_register_notifier; } BUG_ON(mn != &process->mmu_notifier); +#else + /* Must be last, have to use release destruction after this */ + process->mmu_notifier.ops = &kfd_process_mmu_notifier_ops; + err = mmu_notifier_register(&process->mmu_notifier, process->mm); + if (err) + goto err_register_notifier; +#endif kfd_unref_process(process); get_task_struct(process->lead_thread); diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 62de650b61d4b..573afb7356203 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -44,6 +44,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_VMF_INSERT_PFN_PROT AC_AMDGPU_VM_OPERATIONS_STRUCT_FAULT AC_AMDGPU_MMU_NOTIFIER + AC_AMDGPU_MMU_NOTIFIER_SYNCHRONIZE AC_AMDGPU_MMU_NOTIFIER_CALL_SRCU AC_AMDGPU_MM_RELEASE_PAGES AC_AMDGPU_SCHED_SET_FIFO_LOW diff --git a/drivers/gpu/drm/amd/dkms/m4/mmu-notifier-synchronize.m4 b/drivers/gpu/drm/amd/dkms/m4/mmu-notifier-synchronize.m4 new file mode 100644 index 0000000000000..a5e8dcde897ff --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/mmu-notifier-synchronize.m4 @@ -0,0 +1,31 @@ +dnl # +dnl # commit v5.3-rc1-29-g2c7933f53f6b +dnl # mm/mmu_notifiers: add a get/put scheme for the registration +dnl # +dnl # amdkcl: mmu_notifier_put() & mmu_notifier_synchronize() is +dnl # introduced in the same commit, yet rhel7.7 has different behavior +dnl # +AC_DEFUN([AC_AMDGPU_MMU_NOTIFIER_PUT], [ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + mmu_notifier_put(NULL); + ],[ + AC_DEFINE(HAVE_MMU_NOTIFIER_PUT, 1, + [mmu_notifier_put() is available]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_MMU_NOTIFIER_SYNCHRONIZE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + mmu_notifier_synchronize(); + ],[ + AC_DEFINE(HAVE_MMU_NOTIFIER_SYNCHRONIZE, 1, + [mmu_notifier_synchronize() is available]) + ]) + AC_AMDGPU_MMU_NOTIFIER_PUT + ]) +]) From 2b5240b9685172eba3ff34fb8123ae6b5511c7a1 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 6 Dec 2019 22:15:18 +0800 Subject: [PATCH 0316/1868] drm/amdkcl: Test whether mmu_notifier_put is available Change-Id: I6a1119a60093799f5560d72ea00b8bf44bc2b773 Signed-off-by: Flora Cui Signed-off-by: Jack.Gui Signed-off-by: Yifan Zhang --- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 367f4f7460481..e6ebc46cf66d1 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -947,7 +947,7 @@ struct kfd_process { /* We want to receive a notification when the mm_struct is destroyed */ struct mmu_notifier mmu_notifier; -#ifndef HAVE_MMU_NOTIFIER_SYNCHRONIZE +#ifndef HAVE_MMU_NOTIFIER_PUT /* Use for delayed freeing of kfd_process structure */ struct rcu_head rcu; #endif diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index f513878b00f70..369ceabaae472 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -1163,7 +1163,7 @@ static void kfd_process_ref_release(struct kref *ref) queue_work(kfd_process_wq, &p->release_work); } -#ifdef HAVE_MMU_NOTIFIER_SYNCHRONIZE +#ifdef HAVE_MMU_NOTIFIER_PUT static struct mmu_notifier *kfd_process_alloc_notifier(struct mm_struct *mm) { int idx = srcu_read_lock(&kfd_processes_srcu); @@ -1261,7 +1261,7 @@ static void kfd_process_notifier_release(struct mmu_notifier *mn, static const struct mmu_notifier_ops kfd_process_mmu_notifier_ops = { .release = kfd_process_notifier_release, -#ifdef HAVE_MMU_NOTIFIER_SYNCHRONIZE +#ifdef HAVE_MMU_NOTIFIER_PUT .alloc_notifier = kfd_process_alloc_notifier, .free_notifier = kfd_process_free_notifier, #endif From 0bb0d23ccad6a87466dd9a8d59d21b712e9a2b77 Mon Sep 17 00:00:00 2001 From: changzhu Date: Sun, 18 Aug 2019 19:17:39 +0800 Subject: [PATCH 0317/1868] drm/amdkcl: Test whether struct rb_root_cached is defined Signed-off-by: changzhu Reviewed-by: Flora Cui Signed-off-by: Jack Gui drm/amdkcl: fix the dkms install failure in SLED15.1 use interval_tree_insert to judge rb_root_cached Signed-off-by: Yifan Zhang Reviewed-by: Flora Cui Signed-off-by: Jack Gui --- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c | 12 ++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 12 ++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 4 ++++ drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 4 ++++ .../drm/amd/dkms/m4/interval-tree-insert.m4 | 18 ++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 6 files changed, 51 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/interval-tree-insert.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c index 41fc2d09d7b0f..78a5f32697202 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c @@ -83,7 +83,11 @@ struct amdgpu_mn { /* objects protected by lock */ struct rw_semaphore lock; +#ifndef HAVE_TREE_INSERT_HAVE_RB_ROOT_CACHED + struct rb_root objects; +#else struct rb_root_cached objects; +#endif struct mutex read_lock; atomic_t recursion; }; @@ -119,7 +123,11 @@ static void amdgpu_mn_destroy(struct work_struct *work) down_write(&amn->lock); hash_del(&amn->node); rbtree_postorder_for_each_entry_safe(node, next_node, +#ifndef HAVE_TREE_INSERT_HAVE_RB_ROOT_CACHED + &amn->objects, it.rb) { +#else &amn->objects.rb_root, it.rb) { +#endif list_for_each_entry_safe(bo, next_bo, &node->bos, mn_list) { bo->mn = NULL; list_del_init(&bo->mn_list); @@ -558,7 +566,11 @@ struct amdgpu_mn *amdgpu_mn_get(struct amdgpu_device *adev, init_rwsem(&amn->lock); amn->type = type; amn->mn.ops = &amdgpu_mn_ops[type]; +#ifndef HAVE_TREE_INSERT_HAVE_RB_ROOT_CACHED + amn->objects = RB_ROOT; +#else amn->objects = RB_ROOT_CACHED; +#endif mutex_init(&amn->read_lock); atomic_set(&amn->recursion, 0); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index fd14cd652cb3a..e38b83da24a4d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -2418,7 +2418,11 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, struct amdgpu_bo_vm *root; int r, i; +#ifndef HAVE_TREE_INSERT_HAVE_RB_ROOT_CACHED + vm->va = RB_ROOT; +#else vm->va = RB_ROOT_CACHED; +#endif for (i = 0; i < AMDGPU_MAX_VMHUBS; i++) vm->reserved_vmid[i] = NULL; INIT_LIST_HEAD(&vm->evicted); @@ -2642,11 +2646,19 @@ void amdgpu_vm_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) amdgpu_vm_fini_entities(vm); +#ifndef HAVE_TREE_INSERT_HAVE_RB_ROOT_CACHED + if (!RB_EMPTY_ROOT(&vm->va)) { +#else if (!RB_EMPTY_ROOT(&vm->va.rb_root)) { +#endif dev_err(adev->dev, "still active bo inside vm\n"); } rbtree_postorder_for_each_entry_safe(mapping, tmp, +#ifndef HAVE_TREE_INSERT_HAVE_RB_ROOT_CACHED + &vm->va, rb) { +#else &vm->va.rb_root, rb) { +#endif /* Don't remove the mapping here, we don't want to trigger a * rebalance and the tree is about to be destroyed anyway. */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h index 046949c4b6959..bb1a31fe1d3be 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h @@ -324,7 +324,11 @@ struct amdgpu_vm_fault_info { struct amdgpu_vm { /* tree of virtual addresses mapped */ +#ifndef HAVE_TREE_INSERT_HAVE_RB_ROOT_CACHED + struct rb_root va; +#else struct rb_root_cached va; +#endif /* Lock to prevent eviction while we are updating page tables * use vm_eviction_lock/unlock(vm) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index e6ebc46cf66d1..c778f1309b5a0 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -976,7 +976,11 @@ struct kfd_process { size_t signal_event_count; bool signal_event_limit_reached; +#ifndef HAVE_TREE_INSERT_HAVE_RB_ROOT_CACHED + struct rb_root bo_interval_tree; +#else struct rb_root_cached bo_interval_tree; +#endif /* Information used for memory eviction */ void *kgd_process_info; diff --git a/drivers/gpu/drm/amd/dkms/m4/interval-tree-insert.m4 b/drivers/gpu/drm/amd/dkms/m4/interval-tree-insert.m4 new file mode 100644 index 0000000000000..52baac13d3460 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/interval-tree-insert.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit f808c13fd3738948e10196496959871130612b61 +dnl # lib/interval_tree: fast overlap detection +dnl # +AC_DEFUN([AC_AMDGPU_INTERVAL_TREE_INSERT_HAVE_RB_ROOT_CACHED], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct rb_root_cached *r = NULL; + interval_tree_insert(NULL, r); + ],[ + AC_DEFINE(HAVE_TREE_INSERT_HAVE_RB_ROOT_CACHED, 1, + [interval_tree_insert have struct rb_root_cached]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 573afb7356203..8d0ecbd20aaff 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -57,6 +57,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_HMM AC_AMDGPU_INVALIDATE_RANGE_START AC_AMDGPU_DOWN_WRITE_KILLABLE + AC_AMDGPU_INTERVAL_TREE_INSERT_HAVE_RB_ROOT_CACHED AC_AMDGPU_DMA_BUF AC_AMDGPU_DRM_CACHE AC_AMDGPU_DRM_DEBUG_ENABLED From 98024597477c6b4cd8138e1e257cad19e0ee6f54 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Tue, 1 Sep 2020 11:19:53 +0800 Subject: [PATCH 0318/1868] drm/amdkcl: Test whether get_user_{pages/pages_remote}() wants {5/6,8} args v2: rework get_user_pages() & get_user_pages_remote() test v3: adapt to get_user_pages_remote() prototype change (drop task_struct) Signed-off-by: Slava Grigorev Signed-off-by: Yifan Zhang Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang Reviewed-by: Jack Gui Reviewed-by: Feifei Xu Signed-off-by: Jack Gui Signed-off-by: Flora Cui Reviewed-by: Yang Xiong --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 3 +- .../drm/amd/dkms/m4/get-user-pages-remote.m4 | 53 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/get-user-pages.m4 | 30 +++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 + include/kcl/backport/kcl_mm_backport.h | 45 ++++++++++++++++ 5 files changed, 132 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/get-user-pages-remote.m4 create mode 100644 drivers/gpu/drm/amd/dkms/m4/get-user-pages.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 92c755aa0a46b..a50213c55220b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -901,7 +901,8 @@ int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages) if (mm == current->mm) r = get_user_pages(userptr, num_pages, flags, p, NULL); else - r = get_user_pages_remote(mm, userptr, num_pages, + r = kcl_get_user_pages_remote(gtt->usertask, + mm, userptr, num_pages, flags, p, NULL, NULL); spin_lock(>t->guptasklock); diff --git a/drivers/gpu/drm/amd/dkms/m4/get-user-pages-remote.m4 b/drivers/gpu/drm/amd/dkms/m4/get-user-pages-remote.m4 new file mode 100644 index 0000000000000..8f70124da00f0 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/get-user-pages-remote.m4 @@ -0,0 +1,53 @@ +AC_DEFUN([AC_AMDGPU_GET_USER_PAGES_REMOTE], [ + AC_KERNEL_DO_BACKGROUND([ + dnl # + dnl # v4.5-rc4-71-g1e9877902dc7 + dnl # mm/gup: Introduce get_user_pages_remote() + dnl # + AC_KERNEL_CHECK_SYMBOL_EXPORT([get_user_pages_remote],[mm/gup.c], + [ + dnl # + dnl # v5.8-12463-g64019a2e467a + dnl # mm/gup: remove task_struct pointer for all gup code + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + get_user_pages_remote(NULL, 0, 0, 0, NULL, NULL, NULL); + ], [ + AC_DEFINE(HAVE_GET_USER_PAGES_REMOTE_REMOVE_TASK_STRUCT, 1, + [get_user_pages_remote() remove task_struct pointer]) + ], [ + dnl # + dnl # commit v4.9-7744-g5b56d49fc31d + dnl # mm: add locked parameter to get_user_pages_remote() + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + get_user_pages_remote(NULL, NULL, 0, 0, 0, NULL, NULL, NULL); + ], [ + AC_DEFINE(HAVE_GET_USER_PAGES_REMOTE_LOCKED, 1, + [get_user_pages_remote() wants locked parameter]) + ], [ + dnl # + dnl # commit v4.8-14096-g9beae1ea8930 + dnl # mm: replace get_user_pages_remote() write/force parameters + dnl # with gup_flags + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + get_user_pages_remote(NULL, NULL, 0, 0, 0, NULL, NULL); + ], [ + AC_DEFINE(HAVE_GET_USER_PAGES_REMOTE_GUP_FLAGS, 1, + [get_user_pages_remote() wants gup_flags parameter]) + ],[ + AC_DEFINE(HAVE_GET_USER_PAGES_REMOTE_INTRODUCED, 1, + [get_user_pages_remote() is introduced with initial prototype]) + ]) + ]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/get-user-pages.m4 b/drivers/gpu/drm/amd/dkms/m4/get-user-pages.m4 new file mode 100644 index 0000000000000..7f9931fdf453f --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/get-user-pages.m4 @@ -0,0 +1,30 @@ +dnl # +dnl # commit v4.8-14095-g768ae309a961 +dnl # mm: replace get_user_pages() write/force parameters with gup_flags +dnl # +AC_DEFUN([AC_AMDGPU_GET_USER_PAGES], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + get_user_pages(0, 0, 0, NULL, NULL); + ], [get_user_pages], [mm/gup.c], [ + AC_DEFINE(HAVE_GET_USER_PAGES_GUP_FLAGS, 1, + [get_user_pages() wants gup_flags parameter]) + ], [ + dnl # + dnl # commit v4.6-rc2-1-gc12d2da56d0e + dnl # mm/gup: Remove the macro overload API migration helpers + dnl # from the get_user*() APIs + dnl # + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + get_user_pages(0, 0, 0, 0, NULL, NULL); + ], [get_user_pages], [mm/gup.c], [ + AC_DEFINE(HAVE_GET_USER_PAGES_6ARGS, 1, + [get_user_pages() wants 6 args]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 8d0ecbd20aaff..417ec7e084caa 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -58,6 +58,8 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_INVALIDATE_RANGE_START AC_AMDGPU_DOWN_WRITE_KILLABLE AC_AMDGPU_INTERVAL_TREE_INSERT_HAVE_RB_ROOT_CACHED + AC_AMDGPU_GET_USER_PAGES_REMOTE + AC_AMDGPU_GET_USER_PAGES AC_AMDGPU_DMA_BUF AC_AMDGPU_DRM_CACHE AC_AMDGPU_DRM_DEBUG_ENABLED diff --git a/include/kcl/backport/kcl_mm_backport.h b/include/kcl/backport/kcl_mm_backport.h index 055945c8728ef..3fc317a922a8d 100644 --- a/include/kcl/backport/kcl_mm_backport.h +++ b/include/kcl/backport/kcl_mm_backport.h @@ -5,4 +5,49 @@ #include #include +#ifdef get_user_pages_remote +#undef get_user_pages_remote +#endif +#ifdef get_user_pages +#undef get_user_pages +#endif + +static inline +long kcl_get_user_pages_remote(struct task_struct *tsk, struct mm_struct *mm, + unsigned long start, unsigned long nr_pages, + unsigned int gup_flags, struct page **pages, + struct vm_area_struct **vmas, int *locked) +{ +#if defined(HAVE_GET_USER_PAGES_REMOTE_REMOVE_TASK_STRUCT) + return get_user_pages_remote(mm, start, nr_pages, gup_flags, pages, vmas, locked); +#elif defined(HAVE_GET_USER_PAGES_REMOTE_LOCKED) + return get_user_pages_remote(tsk, mm, start, nr_pages, gup_flags, pages, vmas, locked); +#elif defined(HAVE_GET_USER_PAGES_REMOTE_GUP_FLAGS) + return get_user_pages_remote(tsk, mm, start, nr_pages, gup_flags, pages, vmas); +#elif defined(HAVE_GET_USER_PAGES_REMOTE_INTRODUCED) + return get_user_pages_remote(tsk, mm, start, nr_pages, !!(gup_flags & FOLL_WRITE), + !!(gup_flags & FOLL_FORCE), pages, vmas); +#else + return get_user_pages(tsk, mm, start, nr_pages, !!(gup_flags & FOLL_WRITE), + !!(gup_flags & FOLL_FORCE), pages, vmas); +#endif +} + +#ifndef HAVE_GET_USER_PAGES_GUP_FLAGS +static inline +long _kcl_get_user_pages(unsigned long start, unsigned long nr_pages, + unsigned int gup_flags, struct page **pages, + struct vm_area_struct **vmas) +{ +#if defined(HAVE_GET_USER_PAGES_6ARGS) + return get_user_pages(start, nr_pages, !!(gup_flags & FOLL_WRITE), + !!(gup_flags & FOLL_FORCE), pages, vmas); +#else + return get_user_pages(current, current->mm, start, nr_pages, !!(gup_flags & FOLL_WRITE), + !!(gup_flags & FOLL_FORCE), pages, vmas); +#endif +} +#define get_user_pages _kcl_get_user_pages +#endif /* HAVE_GET_USER_PAGES_GUP_FLAGS */ + #endif From a931424d8038d30dcba804c5a94bd4f9b16d474d Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Sat, 18 Apr 2020 19:46:03 +0800 Subject: [PATCH 0319/1868] drm/amdkcl: workaroud for shared address space with dma bufs Signed-off-by: Flora Cui Signed-off-by: Yifan Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 6 +++++- include/kcl/backport/kcl_drm_backport.h | 8 ++++++++ 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index 16862e62dd3bf..998c0c0ff8f8b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -471,10 +471,14 @@ struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev, buf = drm_gem_prime_export(dev, gobj, flags); #endif + if (!IS_ERR(buf)) { +#ifdef AMDKCL_DMA_BUF_SHARE_ADDR_SPACE + buf->file->f_mapping = gobj->dev->anon_inode->i_mapping; +#endif #if defined(AMDKCL_AMDGPU_DMABUF_OPS) - if (!IS_ERR(buf)) buf->ops = &amdgpu_dmabuf_ops; #endif + } return buf; } diff --git a/include/kcl/backport/kcl_drm_backport.h b/include/kcl/backport/kcl_drm_backport.h index 84ca7b867d62d..668fa168e20bd 100644 --- a/include/kcl/backport/kcl_drm_backport.h +++ b/include/kcl/backport/kcl_drm_backport.h @@ -14,4 +14,12 @@ #define AMDKCL_AMDGPU_DMABUF_OPS #endif +/* + * commit v5.4-rc4-1120-gb3fac52c5193 + * drm: share address space for dma bufs + */ +#if DRM_VERSION_CODE < DRM_VERSION(5, 5, 0) +#define AMDKCL_DMA_BUF_SHARE_ADDR_SPACE +#endif + #endif/*AMDKCL_DRM_BACKPORT_H*/ From 5389d2e9bcb0c60396029d8fc7f39a0a7a9dd96d Mon Sep 17 00:00:00 2001 From: Adam Yang Date: Wed, 18 Sep 2019 16:50:24 +0800 Subject: [PATCH 0320/1868] drm/amdkcl: fix pr_fmt() macro is redefined warning Signed-off-by: Adam Yang Signed-off-by: Yifan Zhang --- drivers/gpu/drm/ttm/ttm_agp_backend.c | 3 +++ drivers/gpu/drm/ttm/ttm_bo.c | 3 +++ drivers/gpu/drm/ttm/ttm_bo_vm.c | 3 +++ drivers/gpu/drm/ttm/ttm_tt.c | 3 +++ 4 files changed, 12 insertions(+) diff --git a/drivers/gpu/drm/ttm/ttm_agp_backend.c b/drivers/gpu/drm/ttm/ttm_agp_backend.c index d27691f2e4518..e3121e5d44100 100644 --- a/drivers/gpu/drm/ttm/ttm_agp_backend.c +++ b/drivers/gpu/drm/ttm/ttm_agp_backend.c @@ -30,6 +30,9 @@ * Keith Packard. */ +#ifdef pr_fmt +#undef pr_fmt +#endif /* pr_fmt */ #define pr_fmt(fmt) "[TTM] " fmt #include diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index 260dc6425ead2..7aff1bdd01526 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -29,6 +29,9 @@ * Authors: Thomas Hellstrom */ +#ifdef pr_fmt +#undef pr_fmt +#endif /* pr_fmt */ #define pr_fmt(fmt) "[TTM] " fmt #include diff --git a/drivers/gpu/drm/ttm/ttm_bo_vm.c b/drivers/gpu/drm/ttm/ttm_bo_vm.c index 909fb3ab75967..00de8c8290dbc 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_vm.c +++ b/drivers/gpu/drm/ttm/ttm_bo_vm.c @@ -29,6 +29,9 @@ * Authors: Thomas Hellstrom */ +#ifdef pr_fmt +#undef pr_fmt +#endif /* pr_fmt */ #define pr_fmt(fmt) "[TTM] " fmt #include diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c index 550ead4d5b838..412b0004842bd 100644 --- a/drivers/gpu/drm/ttm/ttm_tt.c +++ b/drivers/gpu/drm/ttm/ttm_tt.c @@ -29,6 +29,9 @@ * Authors: Thomas Hellstrom */ +#ifdef pr_fmt +#undef pr_fmt +#endif /* pr_fmt */ #define pr_fmt(fmt) "[TTM] " fmt #include From 100b1978fbf3088459269555a73afda6570f615c Mon Sep 17 00:00:00 2001 From: Anatoli Antonovitch Date: Fri, 28 Jun 2019 15:41:36 -0400 Subject: [PATCH 0321/1868] drm/amdkcl: check whether pgprot_decrypted is available Change-Id: I55f9dd3b5b7bf756dd48f74810028c67855bec02 Signed-off-by: Anatoli Antonovitch Signed-off-by: Yifan Zhang Signed-off-by: Jack Gui --- drivers/gpu/drm/ttm/ttm_bo_vm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/ttm/ttm_bo_vm.c b/drivers/gpu/drm/ttm/ttm_bo_vm.c index 00de8c8290dbc..19ea3c3cbf461 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_vm.c +++ b/drivers/gpu/drm/ttm/ttm_bo_vm.c @@ -258,8 +258,10 @@ vm_fault_t ttm_bo_vm_fault_reserved(struct vm_fault *vmf, return VM_FAULT_SIGBUS; } } else { +#ifdef pgprot_decrypted /* Iomem should not be marked encrypted */ prot = pgprot_decrypted(prot); +#endif } /* From c10c37921b9409df7c3d572ebf4003b0a0d21998 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 8 Sep 2020 12:45:50 +0800 Subject: [PATCH 0322/1868] drm/amdkcl: use wait_queue_head_t for backward compatibility Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h index 68e7aa9ed2725..f6d0ac99a42d1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.h @@ -25,7 +25,6 @@ /* * Debugfs */ - #if defined(CONFIG_DEBUG_FS) #if defined(AMDKCL_AMDGPU_DEBUGFS_CLEANUP) void amdgpu_debugfs_cleanup(struct drm_minor *minor); From d429e0c9ffd0c74470818c37aaf002db1a0d4772 Mon Sep 17 00:00:00 2001 From: Anatoli Antonovitch Date: Mon, 28 Jan 2019 14:16:44 -0500 Subject: [PATCH 0323/1868] drm/amdkcl: Test whether wait_queue_entry_t exists v2: drm/amdkcl: drop kcl_wait.h Signed-off-by: Anatoli Antonovitch Signed-off-by: Yifan Zhang Signed-off-by: Jack Gui Signed-off-by: Flora Cui Reviewed-by: Jiansong Chen Signed-off-by: Yifan Zhang --- drivers/gpu/drm/amd/amdkfd/kfd_events.c | 12 +++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../amd/dkms/m4/sched-list-for-each-entry.m4 | 21 +++++++++++++++++++ 3 files changed, 34 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/sched-list-for-each-entry.m4 diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_events.c b/drivers/gpu/drm/amd/amdkfd/kfd_events.c index ea37922492093..cd07a9ca76125 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_events.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_events.c @@ -38,7 +38,11 @@ * Wrapper around wait_queue_entry_t */ struct kfd_event_waiter { +#if defined(HAVE_WAIT_QUEUE_ENTRY) wait_queue_entry_t wait; +#else + wait_queue_t wait; +#endif struct kfd_event *event; /* Event to wait for */ bool activated; /* Becomes true when event is signaled */ bool event_age_enabled; /* set to true when last_event_age is non-zero */ @@ -265,7 +269,11 @@ static void destroy_event(struct kfd_process *p, struct kfd_event *ev) /* Wake up pending waiters. They will return failure */ spin_lock(&ev->lock); +#if !defined(HAVE_WAIT_QUEUE_ENTRY) + list_for_each_entry(waiter, &ev->wq.task_list, wait.task_list) +#else list_for_each_entry(waiter, &ev->wq.head, wait.entry) +#endif WRITE_ONCE(waiter->event, NULL); wake_up_all(&ev->wq); spin_unlock(&ev->lock); @@ -637,7 +645,11 @@ static void set_event(struct kfd_event *ev) WARN_ONCE(1, "event_age wrap back!"); } +#if !defined(HAVE_WAIT_QUEUE_ENTRY) + list_for_each_entry(waiter, &ev->wq.task_list, wait.task_list) +#else list_for_each_entry(waiter, &ev->wq.head, wait.entry) +#endif WRITE_ONCE(waiter->activated, true); wake_up_all(&ev->wq); diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 417ec7e084caa..ead7859cc9432 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -61,6 +61,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_GET_USER_PAGES_REMOTE AC_AMDGPU_GET_USER_PAGES AC_AMDGPU_DMA_BUF + AC_AMDGPU_LIST_FOR_EACH_ENTRY AC_AMDGPU_DRM_CACHE AC_AMDGPU_DRM_DEBUG_ENABLED AC_AMDGPU_DRM_GEM_OBJECT_PUT_UNLOCKED diff --git a/drivers/gpu/drm/amd/dkms/m4/sched-list-for-each-entry.m4 b/drivers/gpu/drm/amd/dkms/m4/sched-list-for-each-entry.m4 new file mode 100644 index 0000000000000..4f993d9da6fa3 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/sched-list-for-each-entry.m4 @@ -0,0 +1,21 @@ +dnl # +dnl # 4.13 API change +dnl # commit ac6424b981bce1c4bc55675c6ce11bfe1bbfa64f +dnl # Renamed wait_queue_head::task_list -> wait_queue_head::head +dnl # Renamed wait_queue_entry::task_list -> wait_queue_entry::entry +dnl # +AC_DEFUN([AC_AMDGPU_LIST_FOR_EACH_ENTRY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + wait_queue_entry_t *wq_entry = NULL; + wait_queue_head_t *wq_head = NULL; + + __add_wait_queue(wq_head, wq_entry); + ], [ + AC_DEFINE(HAVE_WAIT_QUEUE_ENTRY, 1, + [wait_queue_entry_t exists]) + ]) + ]) +]) From 79b8e5a7b9187431eeb5748286eefe048653f423 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 13 Apr 2020 06:37:24 +0800 Subject: [PATCH 0324/1868] drm/amdkcl: Test whether struct i2c_lock_operations is defined void (*lock_bus)(struct i2c_adapter *, unsigned int flags); int (*trylock_bus)(struct i2c_adapter *, unsigned int flags); void (*unlock_bus)(struct i2c_adapter *, unsigned int flags); are not defined in struct i2c_adapter until the following patch: commit 8320f495cf441d593f7cd4f30e6b63455be71a2c Author: Peter Rosin Date: Wed May 4 22:15:27 2016 +0200 i2c: allow adapter drivers to override the adapter locking It's not defined until kernel version 4.7.0. So it's hard to support lock_bus,trylock_bus and unlock_bus on redhat 7.7 whose kernel version is 3.10.0. v2: 31fbd646eca3 drm/amdgpu: add lock for i2c bus (andrey.grodzovsky@amd.com) Signed-off-by: changzhu Reviewed-by: Adam Yang Signed-off-by: Jack Gui Signed-off-by: Slava Grigorev Signed-off-by: Andrey Grodzovsky Reviewed-by: Rui Teng --- drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c | 12 ++++++++++++ .../amd/dkms/m4/i2c-lock-operations-struct.m4 | 19 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 32 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/i2c-lock-operations-struct.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c b/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c index dd2d66090d237..2de46087444c7 100644 --- a/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c +++ b/drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.c @@ -636,17 +636,23 @@ static void unlock_bus(struct i2c_adapter *i2c, unsigned int flags) mutex_unlock(&smu_i2c->mutex); } +#if defined(HAVE_I2C_LOCK_OPERATIONS_STRUCT) static const struct i2c_lock_operations smu_v11_0_i2c_i2c_lock_ops = { .lock_bus = lock_bus, .trylock_bus = trylock_bus, .unlock_bus = unlock_bus, }; +#endif static int smu_v11_0_i2c_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msg, int num) { int i, ret; u16 addr, dir; +#if !defined(HAVE_I2C_LOCK_OPERATIONS_STRUCT) + lock_bus(i2c_adap, 0); +#endif + smu_v11_0_i2c_init(i2c_adap); @@ -705,6 +711,10 @@ static int smu_v11_0_i2c_xfer(struct i2c_adapter *i2c_adap, } smu_v11_0_i2c_fini(i2c_adap); + +#if !defined(HAVE_I2C_LOCK_OPERATIONS_STRUCT) + unlock_bus(i2c_adap, 0); +#endif return num; } @@ -736,7 +746,9 @@ int smu_v11_0_i2c_control_init(struct amdgpu_device *adev) control->dev.parent = &adev->pdev->dev; control->algo = &smu_v11_0_i2c_algo; snprintf(control->name, sizeof(control->name), "AMDGPU SMU 0"); +#if defined(HAVE_I2C_LOCK_OPERATIONS_STRUCT) control->lock_ops = &smu_v11_0_i2c_i2c_lock_ops; +#endif control->quirks = &smu_v11_0_i2c_control_quirks; i2c_set_adapdata(control, smu_i2c); diff --git a/drivers/gpu/drm/amd/dkms/m4/i2c-lock-operations-struct.m4 b/drivers/gpu/drm/amd/dkms/m4/i2c-lock-operations-struct.m4 new file mode 100644 index 0000000000000..c8655f6c15d91 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/i2c-lock-operations-struct.m4 @@ -0,0 +1,19 @@ +dnl # +dnl # commit d1ed7985b9a6b85ea38a330108c51ec83381c01b +dnl # Author: Peter Rosin +dnl # Date: Thu Aug 25 23:07:01 2016 +0200 +dnl # i2c: move locking operations to their own structure +dnl # +AC_DEFUN([AC_AMDGPU_I2C_LOCK_OPERATIONS_STRUCT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct i2c_lock_operations drm_dp_i2c_lock_ops; + drm_dp_i2c_lock_ops.lock_bus = NULL; + ], [ + AC_DEFINE(HAVE_I2C_LOCK_OPERATIONS_STRUCT, 1, + [struct i2c_lock_operations is defined]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index ead7859cc9432..a563e99fda0ac 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -12,6 +12,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_TYPE__POLL_T AC_AMDGPU_DMA_MAP_SGTABLE AC_AMDGPU_I2C_NEW_CLIENT_DEVICE + AC_AMDGPU_I2C_LOCK_OPERATIONS_STRUCT AC_AMDGPU_REQUEST_FIRMWARE_DIRECT AC_AMDGPU_BACKLIGHT_DEVICE_SET_BRIGHTNESS AC_AMDGPU_DEV_PM_SET_DRIVER_FLAGS From 24267bdef125e07ea7ae4de533022015815f1d67 Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Mon, 22 Jul 2019 10:13:39 +0800 Subject: [PATCH 0325/1868] drm/amdkcl: Test whether timer_setup() is available test if timer_setup() is defined Signed-off-by: Anatoli Antonovitch Signed-off-by: Yifan Zhang Signed-off-by: Jack Gui --- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 14 ++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/timer-setup.m4 | 16 ++++++++++++++++ 3 files changed, 31 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/timer-setup.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index 837ae142d6778..0285bc1c26673 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c @@ -320,6 +320,7 @@ bool amdgpu_fence_process(struct amdgpu_ring *ring) * * Checks for fence activity. */ +#if defined(HAVE_TIMER_SETUP) static void amdgpu_fence_fallback(struct timer_list *t) { struct amdgpu_ring *ring = from_timer(ring, t, @@ -328,6 +329,14 @@ static void amdgpu_fence_fallback(struct timer_list *t) if (amdgpu_fence_process(ring)) DRM_WARN("Fence fallback timer expired on ring %s\n", ring->name); } +#else +static void amdgpu_fence_fallback(unsigned long arg) +{ + struct amdgpu_ring *ring = (void *)arg; + + amdgpu_fence_process(ring); +} +#endif /** * amdgpu_fence_wait_empty - wait for all fences to signal @@ -519,7 +528,12 @@ int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring) atomic_set(&ring->fence_drv.last_seq, 0); ring->fence_drv.initialized = false; +#if defined(HAVE_TIMER_SETUP) timer_setup(&ring->fence_drv.fallback_timer, amdgpu_fence_fallback, 0); +#else + setup_timer(&ring->fence_drv.fallback_timer, amdgpu_fence_fallback, + (unsigned long)ring); +#endif ring->fence_drv.num_fences_mask = ring->num_hw_submission * 2 - 1; spin_lock_init(&ring->fence_drv.lock); diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index a563e99fda0ac..ce38baf3a06a9 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -63,6 +63,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_GET_USER_PAGES AC_AMDGPU_DMA_BUF AC_AMDGPU_LIST_FOR_EACH_ENTRY + AC_AMDGPU_TIMER_SETUP AC_AMDGPU_DRM_CACHE AC_AMDGPU_DRM_DEBUG_ENABLED AC_AMDGPU_DRM_GEM_OBJECT_PUT_UNLOCKED diff --git a/drivers/gpu/drm/amd/dkms/m4/timer-setup.m4 b/drivers/gpu/drm/amd/dkms/m4/timer-setup.m4 new file mode 100644 index 0000000000000..63a4498b7476a --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/timer-setup.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # timer_setup is available +dnl # +dnl # +AC_DEFUN([AC_AMDGPU_TIMER_SETUP], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + timer_setup(NULL, NULL, 0); + ],[ + AC_DEFINE(HAVE_TIMER_SETUP, 1, + [timer_setup() is available]) + ]) + ]) +]) From 52e23a4740561e2cdaee2ab6fd608b31832f5ea8 Mon Sep 17 00:00:00 2001 From: Chengming Gui Date: Fri, 9 Aug 2019 14:29:29 +0800 Subject: [PATCH 0326/1868] drm/amdkcl: Test whether amd_iommu_pc_supported is available (v2) amd_iommu_pc_xxx introduced by kernel v3.11-rc1~144^2~20 v2: fix typo and correct header file included Signed-off-by: Chengming Gui Reviewed-by: Flora Cui Signed-off-by: Jack Gui drm/amd/autoconf: fix missing HAVE_AMD_IOMMU_PC_SUPPORTED Signed-off-by: Flora Cui Reviewed-by: Jack Gui drm/amd/autoconf: fix missing HAVE_AMD_IOMMU_PC_SUPPORTED this break rhel7.6 Signed-off-by: Flora Cui Reviewed-by: Yifan Zhang drm/amd/autoconf: check CONFIG_AMD_IOMMU enabled for amd_iommu_pc_* or else the symbols are missing. This is for in-tree build. Signed-off-by: Flora Cui Reviewed-by: Feifei Xu Signed-off-by: Jack Gui drm/amdkcl: Fix kfd_iommu dkms install error Issue introduced by commit: 4b38b7a521e3aa401f986483722154b3ba701538 Fix RHEL7.6 with 3.10 kernel kfd_iommu dkms install error some legacy kcl path miss replaced with autoconf macro Signed-off-by: Chengming Gui Reviewed-by: Feifei Xu Signed-off-by: Jack Gui --- drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 25 +++++++++++++++++-- drivers/gpu/drm/amd/amdkfd/kfd_topology.h | 12 +++++++++ .../drm/amd/dkms/m4/amd-iommu-pc-supported.m4 | 18 +++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 54 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/amd-iommu-pc-supported.m4 diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index 112174322c16c..9c445538adbd7 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -133,7 +133,9 @@ static void kfd_release_topology_device(struct kfd_topology_device *dev) struct kfd_cache_properties *cache; struct kfd_iolink_properties *iolink; struct kfd_iolink_properties *p2plink; +#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED struct kfd_perf_properties *perf; +#endif list_del(&dev->list); @@ -165,12 +167,14 @@ static void kfd_release_topology_device(struct kfd_topology_device *dev) kfree(p2plink); } +#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED while (dev->perf_props.next != &dev->perf_props) { perf = container_of(dev->perf_props.next, struct kfd_perf_properties, list); list_del(&perf->list); kfree(perf); } +#endif kfree(dev); } @@ -207,7 +211,9 @@ struct kfd_topology_device *kfd_create_topology_device( INIT_LIST_HEAD(&dev->cache_props); INIT_LIST_HEAD(&dev->io_link_props); INIT_LIST_HEAD(&dev->p2p_link_props); +#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED INIT_LIST_HEAD(&dev->perf_props); +#endif list_add_tail(&dev->list, device_list); @@ -401,6 +407,7 @@ static const struct kobj_type cache_type = { .sysfs_ops = &cache_ops, }; +#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED /****** Sysfs of Performance Counters ******/ struct kfd_perf_attr { @@ -434,6 +441,7 @@ static struct kfd_perf_attr perf_attr_iommu[] = { KFD_PERF_DESC(counter_ids, 0), }; /****************************************/ +#endif static ssize_t node_show(struct kobject *kobj, struct attribute *attr, char *buffer) @@ -589,7 +597,9 @@ static void kfd_remove_sysfs_node_entry(struct kfd_topology_device *dev) struct kfd_iolink_properties *iolink; struct kfd_cache_properties *cache; struct kfd_mem_properties *mem; +#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED struct kfd_perf_properties *perf; +#endif if (dev->kobj_p2plink) { list_for_each_entry(p2plink, &dev->p2p_link_props, list) @@ -655,6 +665,7 @@ static void kfd_remove_sysfs_node_entry(struct kfd_topology_device *dev) dev->kobj_mem = NULL; } +#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED if (dev->kobj_perf) { list_for_each_entry(perf, &dev->perf_props, list) { kfree(perf->attr_group); @@ -664,6 +675,7 @@ static void kfd_remove_sysfs_node_entry(struct kfd_topology_device *dev) kobject_put(dev->kobj_perf); dev->kobj_perf = NULL; } +#endif if (dev->kobj_node) { sysfs_remove_file(dev->kobj_node, &dev->attr_gpuid); @@ -682,10 +694,13 @@ static int kfd_build_sysfs_node_entry(struct kfd_topology_device *dev, struct kfd_iolink_properties *iolink; struct kfd_cache_properties *cache; struct kfd_mem_properties *mem; +#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED struct kfd_perf_properties *perf; - int ret; - uint32_t i, num_attrs; + uint32_t num_attrs; struct attribute **attrs; +#endif + int ret; + uint32_t i; if (WARN_ON(dev->kobj_node)) return -EEXIST; @@ -720,9 +735,11 @@ static int kfd_build_sysfs_node_entry(struct kfd_topology_device *dev, if (!dev->kobj_p2plink) return -ENOMEM; +#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED dev->kobj_perf = kobject_create_and_add("perf", dev->kobj_node); if (!dev->kobj_perf) return -ENOMEM; +#endif /* * Creating sysfs files for node properties @@ -841,6 +858,7 @@ static int kfd_build_sysfs_node_entry(struct kfd_topology_device *dev, i++; } +#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED /* All hardware blocks have the same number of attributes. */ num_attrs = ARRAY_SIZE(perf_attr_iommu); list_for_each_entry(perf, &dev->perf_props, list) { @@ -866,6 +884,7 @@ static int kfd_build_sysfs_node_entry(struct kfd_topology_device *dev, if (ret < 0) return ret; } +#endif return 0; } @@ -1094,8 +1113,10 @@ int kfd_topology_init(void) goto err; } +#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED kdev = list_first_entry(&temp_topology_device_list, struct kfd_topology_device, list); +#endif down_write(&topology_lock); kfd_topology_update_device_list(&temp_topology_device_list, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h index 22e4b2cca1fe4..924534289b0a2 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h @@ -133,12 +133,14 @@ struct kfd_iolink_properties { struct attribute attr; }; +#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED struct kfd_perf_properties { struct list_head list; char block_name[16]; uint32_t max_concurrent; struct attribute_group *attr_group; }; +#endif struct kfd_topology_device { struct list_head list; @@ -149,14 +151,18 @@ struct kfd_topology_device { struct list_head cache_props; struct list_head io_link_props; struct list_head p2p_link_props; +#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED struct list_head perf_props; +#endif struct kfd_node *gpu; struct kobject *kobj_node; struct kobject *kobj_mem; struct kobject *kobj_cache; struct kobject *kobj_iolink; struct kobject *kobj_p2plink; +#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED struct kobject *kobj_perf; +#endif struct attribute attr_gpuid; struct attribute attr_name; struct attribute attr_props; @@ -184,4 +190,10 @@ struct kfd_topology_device *kfd_create_topology_device( struct list_head *device_list); void kfd_release_topology_device_list(struct list_head *device_list); +#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED +extern bool amd_iommu_pc_supported(void); +extern u8 amd_iommu_pc_get_max_banks(u16 devid); +extern u8 amd_iommu_pc_get_max_counters(u16 devid); +#endif + #endif /* __KFD_TOPOLOGY_H__ */ diff --git a/drivers/gpu/drm/amd/dkms/m4/amd-iommu-pc-supported.m4 b/drivers/gpu/drm/amd/dkms/m4/amd-iommu-pc-supported.m4 new file mode 100644 index 0000000000000..27bed9e6beb3b --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/amd-iommu-pc-supported.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit 30861ddc9cca479a7fc6a5efef4e5c69d6b274f4 +dnl # perf/x86/amd: Add IOMMU Performance Counter resource management +dnl # +AC_DEFUN([AC_AMDGPU_AMD_IOMMU_PC_SUPPORTED], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + #ifndef CONFIG_AMD_IOMMU + #error CONFIG_AMD_IOMMU not enabled + #endif + ], [amd_iommu_pc_supported], [drivers/iommu/amd_iommu_init.c], [ + AC_DEFINE(HAVE_AMD_IOMMU_PC_SUPPORTED, 1, + [amd_iommu_pc_supported() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index ce38baf3a06a9..84f3625085d6f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -64,6 +64,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DMA_BUF AC_AMDGPU_LIST_FOR_EACH_ENTRY AC_AMDGPU_TIMER_SETUP + AC_AMDGPU_AMD_IOMMU_PC_SUPPORTED AC_AMDGPU_DRM_CACHE AC_AMDGPU_DRM_DEBUG_ENABLED AC_AMDGPU_DRM_GEM_OBJECT_PUT_UNLOCKED From 98962c67f4277435a817c50fd6cb9175834b2989 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 6 Nov 2019 15:53:10 +0800 Subject: [PATCH 0327/1868] drm/amdkcl: fix bridge_pm_usable v2: drm/amdkcl: add AMDKCL_PCIE_BRIDGE_PM_USABLE to be friendly for hybrid branch maintainer Signed-off-by: Junwei Zhang Reviewed-by: Qiang Yu Signed-off-by: Flora Cui Acked-by: Feifei Xu Signed-off-by: Jack Gui --- .../gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c | 17 +++++++++++++++++ include/kcl/backport/kcl_pci_backport.h | 4 ++++ 2 files changed, 21 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c index 375f020025797..fda8bf2751513 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c @@ -44,7 +44,9 @@ struct amdgpu_atpx { static struct amdgpu_atpx_priv { bool atpx_detected; +#ifdef AMDKCL_PCIE_BRIDGE_PM_USABLE bool bridge_pm_usable; +#endif unsigned int quirks; /* handle for device - and atpx */ acpi_handle dhandle; @@ -233,11 +235,18 @@ static int amdgpu_atpx_validate(struct amdgpu_atpx *atpx) atpx->is_hybrid = false; } else { pr_notice("ATPX Hybrid Graphics\n"); +#ifdef AMDKCL_PCIE_BRIDGE_PM_USABLE /* * Disable legacy PM methods only when pcie port PM is usable, * otherwise the device might fail to power off or power on. */ atpx->functions.power_cntl = !amdgpu_atpx_priv.bridge_pm_usable; +#else + /* + * This is a temporary hack for the kernel doesn't support D3. + */ + atpx->functions.power_cntl = true; +#endif atpx->is_hybrid = true; } } @@ -616,16 +625,20 @@ static bool amdgpu_atpx_detect(void) struct pci_dev *pdev = NULL; bool has_atpx = false; int vga_count = 0; +#ifdef AMDKCL_PCIE_BRIDGE_PM_USABLE bool d3_supported = false; struct pci_dev *parent_pdev; +#endif while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) { vga_count++; has_atpx |= amdgpu_atpx_pci_probe_handle(pdev); +#ifdef AMDKCL_PCIE_BRIDGE_PM_USABLE parent_pdev = pci_upstream_bridge(pdev); d3_supported |= parent_pdev && parent_pdev->bridge_d3; +#endif amdgpu_atpx_get_quirks(pdev); } @@ -634,8 +647,10 @@ static bool amdgpu_atpx_detect(void) has_atpx |= amdgpu_atpx_pci_probe_handle(pdev); +#ifdef AMDKCL_PCIE_BRIDGE_PM_USABLE parent_pdev = pci_upstream_bridge(pdev); d3_supported |= parent_pdev && parent_pdev->bridge_d3; +#endif amdgpu_atpx_get_quirks(pdev); } @@ -644,7 +659,9 @@ static bool amdgpu_atpx_detect(void) pr_info("vga_switcheroo: detected switching method %s handle\n", acpi_method_name); amdgpu_atpx_priv.atpx_detected = true; +#ifdef AMDKCL_PCIE_BRIDGE_PM_USABLE amdgpu_atpx_priv.bridge_pm_usable = d3_supported; +#endif amdgpu_atpx_init(); return true; } diff --git a/include/kcl/backport/kcl_pci_backport.h b/include/kcl/backport/kcl_pci_backport.h index cc2af255e21b5..29bdd6c628b28 100644 --- a/include/kcl/backport/kcl_pci_backport.h +++ b/include/kcl/backport/kcl_pci_backport.h @@ -9,4 +9,8 @@ #if !defined(HAVE_PCIE_GET_SPEED_AND_WIDTH_CAP) #define pcie_get_speed_cap _kcl_pcie_get_speed_cap #endif + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 9, 0) +#define AMDKCL_PCIE_BRIDGE_PM_USABLE +#endif #endif From d0bb5e660b8d68fce8e17b83b34c634e7beddafd Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 6 Nov 2019 10:07:49 +0800 Subject: [PATCH 0328/1868] drm/amdkcl: add AMDKCL_ENABLE_RESIZE_FB_BAR for resize BAR enable This is a squash of: drm/amdkcl: move AMDKCL_ENABLE_RESIZE_FB_BAR to kcl_pci part no actual change. Reviewed-by: Guchun Chen Signed-off-by: Flora Cui drm/amdkcl: rework pci resize dependency. Reviewed-by: Guchun Chen Signed-off-by: Flora Cui drm/amdkcl: move pci resize macro to kcl_pci.h Signed-off-by: Flora Cui Signed-off-by: Flora Cui Acked-by: Feifei Xu --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 7 +++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 ++ include/kcl/backport/kcl_pci_backport.h | 1 + include/kcl/kcl_pci.h | 10 ++++++++++ 4 files changed, 20 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 98b2ec5887032..6f91ae1a44e65 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1449,7 +1449,14 @@ bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev); void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes, u64 num_vis_bytes); +#ifdef AMDKCL_ENABLE_RESIZE_FB_BAR int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); +#else +static inline int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev) +{ + return 0; +} +#endif void amdgpu_device_program_register_sequence(struct amdgpu_device *adev, const u32 *registers, const u32 array_size); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 08e0333553952..eb203118262fe 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -1518,6 +1518,7 @@ void amdgpu_device_wb_free(struct amdgpu_device *adev, u32 wb) spin_unlock_irqrestore(&adev->wb.lock, flags); } +#ifdef AMDKCL_ENABLE_RESIZE_FB_BAR /** * amdgpu_device_resize_fb_bar - try to resize FB BAR * @@ -1602,6 +1603,7 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev) return 0; } +#endif static bool amdgpu_device_read_bios(struct amdgpu_device *adev) { diff --git a/include/kcl/backport/kcl_pci_backport.h b/include/kcl/backport/kcl_pci_backport.h index 29bdd6c628b28..21799422a6abd 100644 --- a/include/kcl/backport/kcl_pci_backport.h +++ b/include/kcl/backport/kcl_pci_backport.h @@ -13,4 +13,5 @@ #if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 9, 0) #define AMDKCL_PCIE_BRIDGE_PM_USABLE #endif + #endif diff --git a/include/kcl/kcl_pci.h b/include/kcl/kcl_pci.h index 596f37906499c..2fa2ef4a09bdf 100644 --- a/include/kcl/kcl_pci.h +++ b/include/kcl/kcl_pci.h @@ -206,4 +206,14 @@ static inline void kcl_pci_remove_measure_file(struct pci_dev *pdev) #endif } +/* + * v4.18-rc1-3-gb1277a226d8c PCI: Cleanup PCI_REBAR_CTRL_BAR_SHIFT handling + * v4.18-rc1-2-gd3252ace0bc6 PCI: Restore resized BAR state on resume + * v4.14-rc3-3-g8bb705e3e79d PCI: Add pci_resize_resource() for resizing BARs + * v4.14-rc3-2-g276b738deb5b PCI: Add resizable BAR infrastructure + */ +#ifdef PCI_REBAR_CTRL_BAR_SHIFT +#define AMDKCL_ENABLE_RESIZE_FB_BAR +#endif /* PCI_REBAR_CTRL_BAR_SHIFT */ + #endif /* AMDKCL_PCI_H */ From 705b6d0f27c51d3d5d4f42d620b38ecc27f797d6 Mon Sep 17 00:00:00 2001 From: Yang Xiong Date: Mon, 1 Jun 2020 15:23:39 +0800 Subject: [PATCH 0329/1868] drm/amdkcl: test for RATELIMIT_MSG_ON_RELEASE The macro RATELIMIT_MSG_ON_RELEASE is introduced by the patch: 6b1d174b0c27 ratelimit: extend to print suppressed messages on release. Drop the RATELIMIT_MSG_ON_RELEASE related code if RATELIMIT_MSG_ON_RELEASE is not defined. The only side effect is that some warning messages on ratelimit release will be left over. This kcl patch is caused by patch: drm/amdgpu: added a sysfs interface for thermal throttling related V4 Signed-off-by: Yang Xiong Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index eb203118262fe..d59361ea63589 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -4117,7 +4117,9 @@ int amdgpu_device_init(struct amdgpu_device *adev, * for throttling interrupt) = 60 seconds. */ ratelimit_state_init(&adev->throttling_logging_rs, (60 - 1) * HZ, 1); +#ifdef RATELIMIT_MSG_ON_RELEASE ratelimit_set_flags(&adev->throttling_logging_rs, RATELIMIT_MSG_ON_RELEASE); +#endif /* Registers mapping */ /* TODO: block userspace mapping of io register */ From 78dad7acdfb317b78eb7544fa41d448005e22b62 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 25 Dec 2019 18:05:04 +0800 Subject: [PATCH 0330/1868] drm/amdkcl: fix dma_addressing_limited() not work correctly It will cause KFDEvictTest failure on ubuntu16.04. Signed-off-by: Flora Cui Reviewed-by: Le Ma Signed-off-by: Yifan Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 15 ++++++++++++++- include/kcl/kcl_dma_mapping.h | 8 ++++++++ 2 files changed, 22 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index a50213c55220b..3e68812420f00 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -2382,6 +2382,19 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) { uint64_t gtt_size; int r; + bool need_dma32; + +#ifdef AMDKCL_DMA_ADDRESSING_LIMITED_WORKAROUND + /* + * set DMA mask + need_dma32 flags. + * PCIE - can handle 44-bits. + * IGP - can handle 44-bits + * PCI - dma32 for legacy pci gart + */ + need_dma32 = !!pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(44)); +#else + need_dma32 = dma_addressing_limited(adev->dev); +#endif mutex_init(&adev->mman.gtt_window_lock); @@ -2390,7 +2403,7 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) adev_to_drm(adev)->anon_inode->i_mapping, adev_to_drm(adev)->vma_offset_manager, adev->need_swiotlb, - dma_addressing_limited(adev->dev)); + need_dma32); if (r) { DRM_ERROR("failed initializing buffer object driver(%d).\n", r); return r; diff --git a/include/kcl/kcl_dma_mapping.h b/include/kcl/kcl_dma_mapping.h index c65a83d51b953..24d18c3a7bf27 100644 --- a/include/kcl/kcl_dma_mapping.h +++ b/include/kcl/kcl_dma_mapping.h @@ -13,6 +13,14 @@ #define DMA_ATTR_NO_WARN (0UL) #endif +/* +* commit v5.3-rc1-57-g06532750010e +* dma-mapping: use dma_get_mask in dma_addressing_limited + */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0) +#define AMDKCL_DMA_ADDRESSING_LIMITED_WORKAROUND +#endif + #ifdef HAVE_LINUX_DMA_ATTRS_H static inline void _kcl_convert_long_to_dma_attrs(struct dma_attrs *dma_attrs, From 0d33d5035fdfd0572289b005065afceb4748f80d Mon Sep 17 00:00:00 2001 From: Chengming Gui Date: Thu, 15 Aug 2019 16:11:59 +0800 Subject: [PATCH 0331/1868] drm/amdkcl: check whether DEFINE_SRCU is available (v2) DEFINE_SRCU introduced by kernel v3.8-rc1~173^2^2~4^4~1 v2: replace autoconf test with macro name check Signed-off-by: Chengming Gui Reviewed-by: Flora Cui Signed-off-by: Jack Gui --- drivers/gpu/drm/amd/amdkfd/kfd_module.c | 9 +++++++++ drivers/gpu/drm/amd/amdkfd/kfd_process.c | 13 +++++++++++++ 2 files changed, 22 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_module.c b/drivers/gpu/drm/amd/amdkfd/kfd_module.c index 5f8093e03d340..ea7aca6d9d874 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_module.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_module.c @@ -26,6 +26,11 @@ #include "kfd_priv.h" #include "amdgpu_amdkfd.h" +#ifndef DEFINE_SRCU +void kfd_init_processes_srcu(void); +void kfd_cleanup_processes_srcu(void); +#endif + static int kfd_init(void) { int err; @@ -70,6 +75,10 @@ static int kfd_init(void) kfd_debugfs_init(); +#ifndef DEFINE_SRCU + kfd_init_processes_srcu(); +#endif + return 0; err_create_wq: diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 369ceabaae472..0bdeba89be480 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -52,7 +52,20 @@ struct mm_struct; DEFINE_HASHTABLE(kfd_processes_table, KFD_PROCESS_TABLE_SIZE); DEFINE_MUTEX(kfd_processes_mutex); +#ifndef DEFINE_SRCU +struct srcu_struct kfd_processes_srcu; +void kfd_init_processes_srcu(void) +{ + init_srcu_struct(&kfd_processes_srcu); +} + +void kfd_cleanup_processes_srcu(void) +{ + cleanup_srcu_struct(&kfd_processes_srcu); +} +#else DEFINE_SRCU(kfd_processes_srcu); +#endif /* For process termination handling */ static struct workqueue_struct *kfd_process_wq; From e8e93a4addb7611696e8afba5395d8c41f061fef Mon Sep 17 00:00:00 2001 From: changzhu Date: Sun, 18 Aug 2019 21:38:39 +0800 Subject: [PATCH 0332/1868] drm/amdkcl: Test whether DW_I2S_QUIRK_16BIT_IDX_OVERRIDE is available [Why] DW_I2S_QUIRK_16BIT_IDX_OVERRIDE is not defined until patch: ASoC: dwc: Added a quirk DW_I2S_QUIRK_16BIT_IDX_OVERRIDE to dwc driver So there will be build when it's not defined. [How] Define DW_I2S_QUIRK_16BIT_IDX_OVERRIDE if it's not defined. Change-Id: I92c4695c24cb7fd7aed80659a53ac57ca8064cef Signed-off-by: changzhu Reviewed-by: Flora Cui Signed-off-by: Jack Gui --- drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c index bf6c4a0d05252..8ef2018fbff6b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c @@ -87,9 +87,12 @@ #define ACP_TIMEOUT_LOOP 0x000000FF #define ACP_DEVS 4 #define ACP_SRC_ID 162 - static unsigned long acp_machine_id; +#ifndef DW_I2S_QUIRK_16BIT_IDX_OVERRIDE +#define DW_I2S_QUIRK_16BIT_IDX_OVERRIDE (1 << 2) +#endif + enum { ACP_TILE_P1 = 0, ACP_TILE_P2, From 0461dfb3395efab4e177cf807ed302a7f6bb337c Mon Sep 17 00:00:00 2001 From: Yang Xiong Date: Tue, 25 Aug 2020 12:24:13 +0800 Subject: [PATCH 0333/1868] drm/amdkcl: test whether down_read_killable is available introduced by v4.14-rc4-65-g76f8507f7a64 This patch is caused by 'drm/amdgpu: change reset lock from mutex to rw_semaphore' v2:change reset_sem to reset_domain->sem, it's caused by "drm/amdgpu: Move reset sem into reset_domain" Signed-off-by: Yang Xiong Reviewed-by: Dennis Li --- drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 4 ++++ drivers/gpu/drm/amd/dkms/m4/down-read-killable.m4 | 14 ++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 19 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/down-read-killable.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c index 8743a112831b1..4ae8fa6bc47f0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c @@ -1954,9 +1954,13 @@ static int amdgpu_debugfs_ib_preempt(void *data, u64 val) return -ENOMEM; /* Avoid accidently unparking the sched thread during GPU reset */ +#ifdef HAVE_DOWN_READ_KILLABLE r = down_read_killable(&adev->reset_domain->sem); if (r) goto pro_end; +#else + down_read(&adev->reset_domain->sem); +#endif /* stop the scheduler */ drm_sched_wqueue_stop(&ring->sched); diff --git a/drivers/gpu/drm/amd/dkms/m4/down-read-killable.m4 b/drivers/gpu/drm/amd/dkms/m4/down-read-killable.m4 new file mode 100644 index 0000000000000..6de71b3c0a40d --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/down-read-killable.m4 @@ -0,0 +1,14 @@ +#dnl +#dnl commit v4.14-rc4-65-g76f8507f7a64 +#dnl locking/rwsem: Add down_read_killable() +#dnl +AC_DEFUN([AC_AMDGPU_DOWN_READ_KILLABLE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT( + [down_read_killable], + [kernel/locking/rwsem.c], + [AC_DEFINE(HAVE_DOWN_READ_KILLABLE, 1, + [down_read_killable() is available])] + ) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 84f3625085d6f..ef49aabbfe3c3 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -65,6 +65,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_LIST_FOR_EACH_ENTRY AC_AMDGPU_TIMER_SETUP AC_AMDGPU_AMD_IOMMU_PC_SUPPORTED + AC_AMDGPU_DOWN_READ_KILLABLE AC_AMDGPU_DRM_CACHE AC_AMDGPU_DRM_DEBUG_ENABLED AC_AMDGPU_DRM_GEM_OBJECT_PUT_UNLOCKED From 1e08e810314db0c20098eb3eebeb8c2a6346c29a Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 15 Oct 2020 14:01:05 +0800 Subject: [PATCH 0334/1868] drm/amdkcl: include kcl_mn with CONFIG_MMU_NOTIFIER enabled Signed-off-by: Flora Cui Reviewed-by: Shiwu Zhang --- drivers/gpu/drm/amd/amdkcl/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 3f301283ce0de..798e54671fd8c 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -14,6 +14,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_acpi_table.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o +amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o CFLAGS_kcl_fence.o := -I$(src) From 86d55fa65615427fc41de242af3efd7da3689318 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 16 Nov 2020 10:56:56 +0800 Subject: [PATCH 0335/1868] drm/amdkcl: rename kcl_connector.c to kcl_drm_connector.c Signed-off-by: Flora Cui Reviewed-by: Shiwu Zhang --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- .../gpu/drm/amd/amdkcl/{kcl_connector.c => kcl_drm_connector.c} | 0 2 files changed, 1 insertion(+), 1 deletion(-) rename drivers/gpu/drm/amd/amdkcl/{kcl_connector.c => kcl_drm_connector.c} (100%) diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 798e54671fd8c..52104abef5fe1 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -9,7 +9,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_suspend.o kcl_pci.o kcl_mm.o kcl_memory.o kcl_sched.o \ kcl_fence.o kcl_fence_array.o kcl_reservation.o kcl_drm_cache.o \ kcl_drm_fb.o kcl_drm_print.o kcl_fbmem.o \ - kcl_drm_crtc.o kcl_connector.o kcl_drm_atomic_helper.o \ + kcl_drm_crtc.o kcl_drm_connector.o kcl_drm_atomic_helper.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o kcl_ftrace.o \ kcl_acpi_table.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_connector.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c similarity index 100% rename from drivers/gpu/drm/amd/amdkcl/kcl_connector.c rename to drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c From 0d24922f361d49740f8ae622b0111c3dca17aa17 Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Fri, 25 Dec 2020 16:52:50 +0800 Subject: [PATCH 0336/1868] drm/amdkcl: dummy the dp subconnector property This is caused by "utilize subconnector property for DP through atombios" and "utilize subconnector property for DP through DisplayManager" v5.8-rc2-673-g65bf2cf95d3a and v5.8-rc2-673-g65bf2cf95d3a Signed-off-by: Shiwu Zhang Reviewed-by: Flora Cui --- .../gpu/drm/amd/amdkcl/kcl_drm_connector.c | 8 +++++ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +- .../drm/amd/dkms/m4/drm_dp_subconnector.m4 | 26 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_connector.h | 29 +++++++++++++++++++ 5 files changed, 66 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_dp_subconnector.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c index ff900e261cb43..a467ebb08a8f3 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c @@ -12,3 +12,11 @@ int _kcl_drm_connector_init_with_ddc(struct drm_device *dev, } EXPORT_SYMBOL(_kcl_drm_connector_init_with_ddc); #endif + +#ifndef HAVE_DRM_MODE_CONFIG_DP_SUBCONNECTOR_PROPERTY +amdkcl_dummy_symbol(drm_connector_attach_dp_subconnector_property, void, return, + struct drm_connector *connector) +amdkcl_dummy_symbol(drm_dp_set_subconnector_property, void, return, + struct drm_connector *connector, enum drm_connector_status status, + const u8 *dpcd, const u8 prot_cap[4]) +#endif diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 7e603b155f8ce..3b624a38e61b6 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -216,10 +216,11 @@ static void update_subconnector_property(struct amdgpu_dm_connector *aconnector) if (aconnector->dc_sink) subconnector = get_subconnector_type(link); - +#ifdef HAVE_DRM_MODE_CONFIG_DP_SUBCONNECTOR_PROPERTY drm_object_property_set_value(&connector->base, connector->dev->mode_config.dp_subconnector_property, subconnector); +#endif } /* diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dp_subconnector.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dp_subconnector.m4 new file mode 100644 index 0000000000000..a6c7c75f41f9e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dp_subconnector.m4 @@ -0,0 +1,26 @@ +dnl # +dnl # v5.8-rc2-671-ge5b92773287c drm: report dp downstream port type as a subconnector property +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_SUBCONNECTOR], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + struct drm_mode_config *mode_config = NULL; + mode_config->dp_subconnector_property = NULL; + ], [ + AC_DEFINE(HAVE_DRM_MODE_CONFIG_DP_SUBCONNECTOR_PROPERTY, 1, + [drm_mode_config->dp_subconnector_property is available]) + ], [ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + enum drm_mode_subconnector sub = 0; + ], [ + AC_DEFINE(HAVE_DRM_MODE_SUBCONNECTOR_ENUM, 1, + [enum drm_mode_subconnector is available]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index ef49aabbfe3c3..2d9c08270341c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -134,6 +134,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_FORMAT_INFO AC_AMDGPU_STRUCT_DRM_CONNECTOR_STATE_COLORSPACE AC_AMDGPU_STRUCT_DRM_ATOMIC_STATE_DUPLICATED + AC_AMDGPU_DRM_DP_SUBCONNECTOR AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_connector.h b/include/kcl/kcl_drm_connector.h index 1da6773c7ee4b..8eb2f3e647417 100644 --- a/include/kcl/kcl_drm_connector.h +++ b/include/kcl/kcl_drm_connector.h @@ -79,4 +79,33 @@ int drm_connector_init_with_ddc(struct drm_device *dev, } #endif +#ifndef DP_MAX_DOWNSTREAM_PORTS +#define DP_MAX_DOWNSTREAM_PORTS 0x10 +#endif + +#ifndef HAVE_DRM_MODE_CONFIG_DP_SUBCONNECTOR_PROPERTY +void drm_connector_attach_dp_subconnector_property(struct drm_connector *connector); +void drm_dp_set_subconnector_property(struct drm_connector *connector, enum drm_connector_status status, + const u8 *dpcd, const u8 prot_cap[4]); + +#ifdef HAVE_DRM_MODE_SUBCONNECTOR_ENUM +#define DRM_MODE_SUBCONNECTOR_VGA 1 +#define DRM_MODE_SUBCONNECTOR_DisplayPort 10 +#define DRM_MODE_SUBCONNECTOR_HDMIA 11 +#define DRM_MODE_SUBCONNECTOR_Native 15 +#define DRM_MODE_SUBCONNECTOR_Wireless 18 +#else +/* Copied from include/uapi/drm/drm_mode.h */ +/* This is for connectors with multiple signal types. */ +/* Try to match DRM_MODE_CONNECTOR_X as closely as possible. */ +enum drm_mode_subconnector { + DRM_MODE_SUBCONNECTOR_VGA = 1, /* DP */ + DRM_MODE_SUBCONNECTOR_DisplayPort = 10, /* DP */ + DRM_MODE_SUBCONNECTOR_HDMIA = 11, /* DP */ + DRM_MODE_SUBCONNECTOR_Native = 15, /* DP */ + DRM_MODE_SUBCONNECTOR_Wireless = 18, /* DP */ +}; +#endif /* HAVE_DRM_MODE_SUBCONNECTOR_ENUM */ +#endif /* HAVE_DRM_MODE_CONFIG_DP_SUBCONNECTOR_PROPERTY */ + #endif /* AMDKCL_DRM_CONNECTOR_H */ From e1bd89c742cf189be32a6723255eceea3e34cd55 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 9 Mar 2021 11:52:01 +0800 Subject: [PATCH 0337/1868] drm/amdkcl: fake hexint support for module_param Change-Id: Ic6b3fd5e2ca1e6e645c658924cc051b6119297b6 Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/backport/backport.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 2cb3aae626abb..4cfaaadbf3d8c 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -56,9 +56,10 @@ #include #include #include -#include "kcl/kcl_amdgpu_ttm.h" +#include #include #include +#include "kcl/kcl_amdgpu_ttm.h" #include "kcl/kcl_amdgpu_drm_fb_helper.h" #include "kcl/kcl_amdgpu.h" #include "kcl/kcl_amdgpu_drm_drv.h" From c45cc86fccf90d261e7c56e5ca28ccf746fe7f03 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 3 Feb 2021 11:54:35 +0800 Subject: [PATCH 0338/1868] drm/amdkcl: add kcl/kcl_dma-buf-map.h Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/ttm/backport/backport.h | 1 + include/kcl/kcl_dma-buf-map.h | 141 ++++++++++++++++++++++++ 3 files changed, 143 insertions(+) create mode 100644 include/kcl/kcl_dma-buf-map.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 4cfaaadbf3d8c..5145ab0dc038a 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index a5c1c3c403ad7..2964bb26cea9e 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include diff --git a/include/kcl/kcl_dma-buf-map.h b/include/kcl/kcl_dma-buf-map.h new file mode 100644 index 0000000000000..5bcaad09cabd8 --- /dev/null +++ b/include/kcl/kcl_dma-buf-map.h @@ -0,0 +1,141 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Pointer to dma-buf-mapped memory, plus helpers. + * Copied from include/kcl/dma-buf-map.h + */ + +#ifndef _KCL_KCL__DMA_BUF_MAP_H__H__ +#define _KCL_KCL__DMA_BUF_MAP_H__H__ + +#include + +#ifndef HAVE_LINUX_DMA_BUF_MAP_H +#include + +/** + * struct dma_buf_map - Pointer to vmap'ed dma-buf memory. + * @vaddr_iomem: The buffer's address if in I/O memory + * @vaddr: The buffer's address if in system memory + * @is_iomem: True if the dma-buf memory is located in I/O + * memory, or false otherwise. + */ +struct dma_buf_map { + union { + void __iomem *vaddr_iomem; + void *vaddr; + }; + bool is_iomem; +}; + +/** + * DMA_BUF_MAP_INIT_VADDR - Initializes struct dma_buf_map to an address in system memory + * @vaddr: A system-memory address + */ +#define DMA_BUF_MAP_INIT_VADDR(vaddr_) \ + { \ + .vaddr = (vaddr_), \ + .is_iomem = false, \ + } + +/** + * dma_buf_map_set_vaddr - Sets a dma-buf mapping structure to an address in system memory + * @map: The dma-buf mapping structure + * @vaddr: A system-memory address + * + * Sets the address and clears the I/O-memory flag. + */ +static inline void dma_buf_map_set_vaddr(struct dma_buf_map *map, void *vaddr) +{ + map->vaddr = vaddr; + map->is_iomem = false; +} + +/** + * dma_buf_map_set_vaddr_iomem - Sets a dma-buf mapping structure to an address in I/O memory + * @map: The dma-buf mapping structure + * @vaddr_iomem: An I/O-memory address + * + * Sets the address and the I/O-memory flag. + */ +static inline void dma_buf_map_set_vaddr_iomem(struct dma_buf_map *map, + void __iomem *vaddr_iomem) +{ + map->vaddr_iomem = vaddr_iomem; + map->is_iomem = true; +} + + +/** + * dma_buf_map_is_equal - Compares two dma-buf mapping structures for equality + * @lhs: The dma-buf mapping structure + * @rhs: A dma-buf mapping structure to compare with + * + * Two dma-buf mapping structures are equal if they both refer to the same type of memory + * and to the same address within that memory. + * + * Returns: + * True is both structures are equal, or false otherwise. + */ +static inline bool dma_buf_map_is_equal(const struct dma_buf_map *lhs, + const struct dma_buf_map *rhs) +{ + if (lhs->is_iomem != rhs->is_iomem) + return false; + else if (lhs->is_iomem) + return lhs->vaddr_iomem == rhs->vaddr_iomem; + else + return lhs->vaddr == rhs->vaddr; +} + +/** + * dma_buf_map_is_null - Tests for a dma-buf mapping to be NULL + * @map: The dma-buf mapping structure + * + * Depending on the state of struct dma_buf_map.is_iomem, tests if the + * mapping is NULL. + * + * Returns: + * True if the mapping is NULL, or false otherwise. + */ +static inline bool dma_buf_map_is_null(const struct dma_buf_map *map) +{ + if (map->is_iomem) + return !map->vaddr_iomem; + return !map->vaddr; +} + +/** + * dma_buf_map_is_set - Tests is the dma-buf mapping has been set + * @map: The dma-buf mapping structure + * + * Depending on the state of struct dma_buf_map.is_iomem, tests if the + * mapping has been set. + * + * Returns: + * True if the mapping is been set, or false otherwise. + */ +static inline bool dma_buf_map_is_set(const struct dma_buf_map *map) +{ + return !dma_buf_map_is_null(map); +} + +/** + * dma_buf_map_clear - Clears a dma-buf mapping structure + * @map: The dma-buf mapping structure + * + * Clears all fields to zero; including struct dma_buf_map.is_iomem. So + * mapping structures that were set to point to I/O memory are reset for + * system memory. Pointers are cleared to NULL. This is the default. + */ +static inline void dma_buf_map_clear(struct dma_buf_map *map) +{ + if (map->is_iomem) { + map->vaddr_iomem = NULL; + map->is_iomem = false; + } else { + map->vaddr = NULL; + } +} +#endif /* HAVE_LINUX_DMA_BUF_MAP_H */ + +#endif From 1b8ca1dd394f87fb14e8da39f8875f7ac3218888 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 4 Aug 2021 11:05:33 +0800 Subject: [PATCH 0339/1868] drm/amdkcl: Test whether drm_memcpy_from_wc() is available This is caused by 053c57696cb9 "drm/ttm: Use drm_memcpy_from_wc for TTM bo moves" v5.13-rc3-862-g053c57696cb9 Signed-off-by: Leslie Shi --- .../gpu/drm/amd/dkms/m4/drm-memcpy-from-wc.m4 | 16 +++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/ttm/ttm_bo_util.c | 19 ++++++++++ include/kcl/kcl_dma-buf-map.h | 35 +++++++++++++++++++ 4 files changed, 71 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-memcpy-from-wc.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-memcpy-from-wc.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-memcpy-from-wc.m4 new file mode 100644 index 0000000000000..491ada31c112a --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-memcpy-from-wc.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit b7e32bef4ae5f9149276203564b7911fac466588 +dnl # drm: Add a prefetching memcpy_from_wc +dnl # +AC_DEFUN([AC_AMDGPU_DRM_MEMCPY_FROM_WC], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_memcpy_from_wc(NULL, NULL, 0); + ], [ + AC_DEFINE(HAVE_DRM_MEMCPY_FROM_WC, 1, + [drm_memcpy_from_wc() is availablea]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 2d9c08270341c..4d1ebd5dde096 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -135,6 +135,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_STRUCT_DRM_CONNECTOR_STATE_COLORSPACE AC_AMDGPU_STRUCT_DRM_ATOMIC_STATE_DUPLICATED AC_AMDGPU_DRM_DP_SUBCONNECTOR + AC_AMDGPU_DRM_MEMCPY_FROM_WC AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c index 02a9574b0216a..09af9bc43ebad 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_util.c +++ b/drivers/gpu/drm/ttm/ttm_bo_util.c @@ -113,7 +113,26 @@ void ttm_move_memcpy(bool clear, dst_ops->map_local(dst_iter, &dst_map, i); src_ops->map_local(src_iter, &src_map, i); +#ifdef HAVE_DRM_MEMCPY_FROM_WC drm_memcpy_from_wc(&dst_map, &src_map, PAGE_SIZE); +#else + if (!src_map.is_iomem && !dst_map.is_iomem) { + memcpy(dst_map.vaddr, src_map.vaddr, PAGE_SIZE); + } else if (!src_map.is_iomem) { + dma_buf_map_memcpy_to(&dst_map, src_map.vaddr, + PAGE_SIZE); + } else if (!dst_map.is_iomem) { + memcpy_fromio(dst_map.vaddr, src_map.vaddr_iomem, + PAGE_SIZE); + } else { + int j; + u32 __iomem *src = src_map.vaddr_iomem; + u32 __iomem *dst = dst_map.vaddr_iomem; + + for (j = 0; j < (PAGE_SIZE / sizeof(u32)); ++j) + iowrite32(ioread32(src++), dst++); + } +#endif if (src_ops->unmap_local) src_ops->unmap_local(src_iter, &src_map); diff --git a/include/kcl/kcl_dma-buf-map.h b/include/kcl/kcl_dma-buf-map.h index 5bcaad09cabd8..4ce925f647ec5 100644 --- a/include/kcl/kcl_dma-buf-map.h +++ b/include/kcl/kcl_dma-buf-map.h @@ -136,6 +136,41 @@ static inline void dma_buf_map_clear(struct dma_buf_map *map) map->vaddr = NULL; } } + +/** + * dma_buf_map_memcpy_to - Memcpy into dma-buf mapping + * @dst: The dma-buf mapping structure + * @src: The source buffer + * @len: The number of byte in src + * + * Copies data into a dma-buf mapping. The source buffer is in system + * memory. Depending on the buffer's location, the helper picks the correct + * method of accessing the memory. + */ +static inline void dma_buf_map_memcpy_to(struct dma_buf_map *dst, const void *src, size_t len) +{ + if (dst->is_iomem) + memcpy_toio(dst->vaddr_iomem, src, len); + else + memcpy(dst->vaddr, src, len); +} + +/** + * dma_buf_map_incr - Increments the address stored in a dma-buf mapping + * @map: The dma-buf mapping structure + * @incr: The number of bytes to increment + * + * Increments the address stored in a dma-buf mapping. Depending on the + * buffer's location, the correct value will be updated. + */ +static inline void dma_buf_map_incr(struct dma_buf_map *map, size_t incr) +{ + if (map->is_iomem) + map->vaddr_iomem += incr; + else + map->vaddr += incr; +} + #endif /* HAVE_LINUX_DMA_BUF_MAP_H */ #endif From ac71ef88444dfb71f5222deb12814b78d7982735 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 4 Aug 2021 11:27:39 +0800 Subject: [PATCH 0340/1868] drm/amdkcl: Test whether is_cow_mapping() is available This is caused by f91142c62161 "drm/ttm: nuke VM_MIXEDMAP on BO mappings v3" v5.13-rc3-873-gf91142c62161 Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/m4/is_cow_mapping.m4 | 15 +++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_mm.h | 7 +++++++ 3 files changed, 23 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/is_cow_mapping.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/is_cow_mapping.m4 b/drivers/gpu/drm/amd/dkms/m4/is_cow_mapping.m4 new file mode 100644 index 0000000000000..c0bf84f081f2a --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/is_cow_mapping.m4 @@ -0,0 +1,15 @@ +dnl # +dnl # commit 97a7e4733b9b221d012ae68fcd3b3251febf6341 +dnl # mm: introduce page_needs_cow_for_dma() for deciding whether cow +dnl # +AC_DEFUN([AC_AMDGPU_IS_COW_MAPPING], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + is_cow_mapping(VM_SHARED); + ], [ + AC_DEFINE(HAVE_IS_COW_MAPPING, 1, [is_cow_mapping() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 4d1ebd5dde096..40371f56993d5 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -136,6 +136,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_STRUCT_DRM_ATOMIC_STATE_DUPLICATED AC_AMDGPU_DRM_DP_SUBCONNECTOR AC_AMDGPU_DRM_MEMCPY_FROM_WC + AC_AMDGPU_IS_COW_MAPPING AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_mm.h b/include/kcl/kcl_mm.h index b4e18dfd764fe..402a28df45f0e 100644 --- a/include/kcl/kcl_mm.h +++ b/include/kcl/kcl_mm.h @@ -54,4 +54,11 @@ static inline unsigned long zone_managed_pages(struct zone *zone) } #endif /* HAVE_ZONE_MANAGED_PAGES */ +#ifndef HAVE_IS_COW_MAPPING +static inline bool is_cow_mapping(vm_flags_t flags) +{ + return (flags & (VM_SHARED | VM_MAYWRITE)) == VM_MAYWRITE; +} +#endif /* HAVE_IS_COW_MAPPING */ + #endif /* AMDKCL_MM_H */ From c589c235899edc89c023de6217898e76cfb9cc5b Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 4 Aug 2021 15:13:38 +0800 Subject: [PATCH 0341/1868] drm/amdkcl: Test whether drm_aperture_* is available This is caused by 6848c291a54f "drm/aperture: Convert drivers to aperture interfaces" v5.12-rc3-331-g6848c291a54f Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c | 139 ++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/drm-aperture.m4 | 16 ++ drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 6 + drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 4 +- .../gpu/drm/amd/dkms/m4/vga_remove_vgacon.m4 | 16 ++ include/kcl/kcl_drm_aperture.h | 25 ++++ 8 files changed, 207 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-aperture.m4 create mode 100644 drivers/gpu/drm/amd/dkms/m4/vga_remove_vgacon.m4 create mode 100644 include/kcl/kcl_drm_aperture.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 52104abef5fe1..0791290ae716b 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -11,7 +11,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_drm_fb.o kcl_drm_print.o kcl_fbmem.o \ kcl_drm_crtc.o kcl_drm_connector.o kcl_drm_atomic_helper.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o kcl_ftrace.o \ - kcl_acpi_table.o + kcl_acpi_table.o kcl_drm_aperture.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c new file mode 100644 index 0000000000000..b3fa22920b7f2 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c @@ -0,0 +1,139 @@ +// SPDX-License-Identifier: MIT + +#ifndef HAVE_DRM_APERTURE +#include +#include +#include +#include +#include +#include + +struct drm_aperture { + struct drm_device *dev; + resource_size_t base; + resource_size_t size; + struct list_head lh; + void (*detach)(struct drm_device *dev); +}; + +static LIST_HEAD(drm_apertures); +static DEFINE_MUTEX(drm_apertures_lock); + +static bool overlap(resource_size_t base1, resource_size_t end1, + resource_size_t base2, resource_size_t end2) +{ + return (base1 < end2) && (end1 > base2); +} + + +static void drm_aperture_detach_drivers(resource_size_t base, resource_size_t size) +{ + resource_size_t end = base + size; + struct list_head *pos, *n; + + mutex_lock(&drm_apertures_lock); + + list_for_each_safe(pos, n, &drm_apertures) { + struct drm_aperture *ap = + container_of(pos, struct drm_aperture, lh); + struct drm_device *dev = ap->dev; + + if (WARN_ON_ONCE(!dev)) + continue; + + if (!overlap(base, end, ap->base, ap->base + ap->size)) + continue; + + ap->dev = NULL; /* detach from device */ + list_del(&ap->lh); + + ap->detach(dev); + } + + mutex_unlock(&drm_apertures_lock); +} + + +/** + * drm_aperture_remove_conflicting_framebuffers - remove existing framebuffers in the given range + * @base: the aperture's base address in physical memory + * @size: aperture size in bytes + * @primary: also kick vga16fb if present + * @name: requesting driver name + * + * This function removes graphics device drivers which use memory range described by + * @base and @size. + * + * Returns: + * 0 on success, or a negative errno code otherwise + */ +int drm_aperture_remove_conflicting_framebuffers(resource_size_t base, resource_size_t size, + bool primary, const char *name) +{ +#if IS_REACHABLE(CONFIG_FB) + struct apertures_struct *a; + int ret; + + a = alloc_apertures(1); + if (!a) + return -ENOMEM; + + a->ranges[0].base = base; + a->ranges[0].size = size; + + ret = remove_conflicting_framebuffers(a, name, primary); + kfree(a); + + if (ret) + return ret; +#endif + + drm_aperture_detach_drivers(base, size); + + return 0; +} +EXPORT_SYMBOL(drm_aperture_remove_conflicting_framebuffers); + +/** + * drm_aperture_remove_conflicting_pci_framebuffers - remove existing framebuffers for PCI devices + * @pdev: PCI device + * @name: requesting driver name + * + * This function removes graphics device drivers using memory range configured + * for any of @pdev's memory bars. The function assumes that PCI device with + * shadowed ROM drives a primary display and so kicks out vga16fb. + * + * Returns: + * 0 on success, or a negative errno code otherwise + */ +int drm_aperture_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, const char *name) +{ + resource_size_t base, size; + int bar, ret = 0; + + for (bar = 0; bar < PCI_STD_NUM_BARS; ++bar) { + if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) + continue; + base = pci_resource_start(pdev, bar); + size = pci_resource_len(pdev, bar); + drm_aperture_detach_drivers(base, size); + } + + /* + * WARNING: Apparently we must kick fbdev drivers before vgacon, + * otherwise the vga fbdev driver falls over. + */ + +#ifdef HAVE_VGA_REMOVE_VGACON +#if IS_REACHABLE(CONFIG_FB) + ret = remove_conflicting_pci_framebuffers(pdev, name); +#endif + if (ret == 0) + ret = vga_remove_vgacon(pdev); +#endif + + return ret; +} +EXPORT_SYMBOL(drm_aperture_remove_conflicting_pci_framebuffers); + +#endif /* HAVE_DRM_APERTURE */ diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 5145ab0dc038a..6d1d8f4d0a66e 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -64,5 +64,6 @@ #include "kcl/kcl_amdgpu_drm_fb_helper.h" #include "kcl/kcl_amdgpu.h" #include "kcl/kcl_amdgpu_drm_drv.h" +#include "kcl/kcl_drm_aperture.h" #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-aperture.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-aperture.m4 new file mode 100644 index 0000000000000..532e9149653c9 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-aperture.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit 2916059147ea38f76787d7b38dee883da2e9def2 +dnl # drm/aperture: Add infrastructure for aperture ownership +dnl # +AC_DEFUN([AC_AMDGPU_DRM_APERTURE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_aperture_remove_conflicting_pci_framebuffers(NULL, NULL); + ], [ + AC_DEFINE(HAVE_DRM_APERTURE, 1, + [drm_aperture_remove_* is availablea]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index 5db23c22d9fe3..16ebd93fc3ea8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -38,4 +38,10 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # drm: add managed resources tied to drm_device dnl # AC_KERNEL_CHECK_HEADERS([drm/drm_managed.h]) + + dnl # + dnl # v5.12-rc3-330-g2916059147ea + dnl # drm/aperture: Add infrastructure for aperture ownership + dnl # + AC_KERNEL_CHECK_HEADERS([drm/drm_aperture.h]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 40371f56993d5..984902235fd9c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -137,7 +137,9 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_SUBCONNECTOR AC_AMDGPU_DRM_MEMCPY_FROM_WC AC_AMDGPU_IS_COW_MAPPING - + AC_AMDGPU_VGA_REMOVE_VGACON + AC_AMDGPU_DRM_APERTURE + AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ KERNEL_MAKE="$KERNEL_MAKE O=$LINUX_OBJ" diff --git a/drivers/gpu/drm/amd/dkms/m4/vga_remove_vgacon.m4 b/drivers/gpu/drm/amd/dkms/m4/vga_remove_vgacon.m4 new file mode 100644 index 0000000000000..f95a903f3143b --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/vga_remove_vgacon.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v5.0-rc1-998-gc6b38fbbde91 +dnl # drm: move i915_kick_out_vgacon to vgaarb +dnl # +AC_DEFUN([AC_AMDGPU_VGA_REMOVE_VGACON], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + vga_remove_vgacon(NULL); + ], [ + AC_DEFINE(HAVE_VGA_REMOVE_VGACON, 1, + [vga_remove_vgacon() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_drm_aperture.h b/include/kcl/kcl_drm_aperture.h new file mode 100644 index 0000000000000..5c402e251a5d9 --- /dev/null +++ b/include/kcl/kcl_drm_aperture.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef KCL_KCL_DRM_APERTURE_H +#define KCL_KCL_DRM_APERTURE_H + +#ifndef HAVE_DRM_APERTURE + +#include + +/* Copied from uapi/linux/pci_regs.h */ +#ifndef PCI_STD_NUM_BARS +#define PCI_STD_NUM_BARS 6 +#endif + +/* Copied from drm/drm_aperture.h */ +struct drm_device; +struct pci_dev; + +int drm_aperture_remove_conflicting_framebuffers(resource_size_t base, resource_size_t size, + bool primary, const char *name); + +int drm_aperture_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, const char *name); + +#endif /* HAVE_DRM_APERTURE */ + +#endif From 278e7e77204f490d6dc8fb56e0cd77ff66e58b52 Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Mon, 8 Mar 2021 11:52:50 +0800 Subject: [PATCH 0342/1868] drm/amdkcl: fix the warning of struct ttm_bo_devic invisible Signed-off-by: Shiwu Zhang --- include/kcl/backport/kcl_ttm_tt_backport.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/kcl/backport/kcl_ttm_tt_backport.h b/include/kcl/backport/kcl_ttm_tt_backport.h index 64f22b0fb609e..3641f2408b0f3 100644 --- a/include/kcl/backport/kcl_ttm_tt_backport.h +++ b/include/kcl/backport/kcl_ttm_tt_backport.h @@ -2,6 +2,7 @@ #ifndef AMDKCL_BACKPORT_KCL_TTM_TT_BACKPORT_H #define AMDKCL_BACKPORT_KCL_TTM_TT_BACKPORT_H +#include #include #ifndef HAVE_TTM_SG_TT_INIT From ddcf54ca053a1a0bb63a421a64d1f7d5da0ace3e Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 4 Aug 2021 15:43:10 +0800 Subject: [PATCH 0343/1868] drm/amdkcl: Test whether struct pci_driver has field dev_groups This is caused by 35bba8313b95 "drm/amdgpu: Convert driver sysfs attributes to static attributes" v5.13-rc1-237-g35bba8313b95 Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../gpu/drm/amd/dkms/m4/pci-driver-dev-groups.m4 | 16 ++++++++++++++++ 3 files changed, 19 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/pci-driver-dev-groups.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index eb436b991b43f..d331bd145790d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3128,7 +3128,9 @@ static struct pci_driver amdgpu_kms_pci_driver = { .shutdown = amdgpu_pci_shutdown, .driver.pm = &amdgpu_pm_ops, .err_handler = &amdgpu_pci_err_handler, +#ifdef HAVE_PCI_DRIVER_DEV_GROUPS .dev_groups = amdgpu_sysfs_groups, +#endif }; static int __init amdgpu_init(void) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 984902235fd9c..fafda1c1b1c0d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -139,6 +139,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_IS_COW_MAPPING AC_AMDGPU_VGA_REMOVE_VGACON AC_AMDGPU_DRM_APERTURE + AC_AMDGPU_PCI_DRIVER_DEV_GROUPS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/pci-driver-dev-groups.m4 b/drivers/gpu/drm/amd/dkms/m4/pci-driver-dev-groups.m4 new file mode 100644 index 0000000000000..7a673c73d6b1c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pci-driver-dev-groups.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit ded13b9cfd595adb478a1e371d2282048bba1df5 +dnl # PCI: Add support for dev_groups to struct pci_driver +dnl # +AC_DEFUN([AC_AMDGPU_PCI_DRIVER_DEV_GROUPS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + struct pci_driver pd; + pd.dev_groups = NULL; + ], [], [], [ + AC_DEFINE(HAVE_PCI_DRIVER_DEV_GROUPS, 1, [struct pci_driver has field dev_groups]) + ]) + ]) +]) From 5bb5a03beea1abbae20557d82385dbb7dee19557 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 3 Feb 2021 11:38:10 +0800 Subject: [PATCH 0344/1868] drm/amdkcl: add faked pci_rebar_bytes_to_size() Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../drm/amd/dkms/m4/pci_rebar_bytes_to_size.m4 | 16 ++++++++++++++++ include/kcl/kcl_pci.h | 11 +++++++++++ 3 files changed, 28 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/pci_rebar_bytes_to_size.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index fafda1c1b1c0d..b439fe9d39fe3 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -33,6 +33,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_PCIE_BANDWIDTH_AVAILABLE AC_AMDGPU_PCI_CONFIGURE_EXTENDED_TAGS AC_AMDGPU_PCI_DEV_ID + AC_AMDGPU_PCI_REBAR_BYTES_TO_SIZE AC_AMDGPU_KTIME_GET_BOOTTIME_NS AC_AMDGPU_KTIME_GET_RAW_NS AC_AMDGPU_KTIME_GET_REAL_SECONDS diff --git a/drivers/gpu/drm/amd/dkms/m4/pci_rebar_bytes_to_size.m4 b/drivers/gpu/drm/amd/dkms/m4/pci_rebar_bytes_to_size.m4 new file mode 100644 index 0000000000000..01d066282244a --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pci_rebar_bytes_to_size.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit 192f1bf7559e895d51f81c3976c5892c8b1e0601 +dnl # PCI: Add pci_rebar_bytes_to_size() +dnl # +AC_DEFUN([AC_AMDGPU_PCI_REBAR_BYTES_TO_SIZE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + pci_rebar_bytes_to_size(0); + ], [ + AC_DEFINE(HAVE_PCI_REBAR_BYTES_TO_SIZE, 1, + [pci_rebar_bytes_to_size() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_pci.h b/include/kcl/kcl_pci.h index 2fa2ef4a09bdf..a75ef23e8bf46 100644 --- a/include/kcl/kcl_pci.h +++ b/include/kcl/kcl_pci.h @@ -214,6 +214,17 @@ static inline void kcl_pci_remove_measure_file(struct pci_dev *pdev) */ #ifdef PCI_REBAR_CTRL_BAR_SHIFT #define AMDKCL_ENABLE_RESIZE_FB_BAR + +/* Copied from 192f1bf7559e895d51f81c3976c5892c8b1e0601 include/linux/pci.h */ +#ifndef HAVE_PCI_REBAR_BYTES_TO_SIZE +static inline int pci_rebar_bytes_to_size(u64 bytes) +{ + bytes = roundup_pow_of_two(bytes); + + /* Return BAR size as defined in the resizable BAR specification */ + return max(ilog2(bytes), 20) - 20; +} +#endif #endif /* PCI_REBAR_CTRL_BAR_SHIFT */ #endif /* AMDKCL_PCI_H */ From 88cca8dbc0539108551b45078733cb77373369a4 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 3 Feb 2021 11:46:01 +0800 Subject: [PATCH 0345/1868] drm/amdkcl: add faked pci_rebar_get_possible_sizes() Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/kcl_pci.c | 51 ++++++++++++++++++++++++++++ include/kcl/kcl_pci.h | 12 +++++++ 2 files changed, 63 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_pci.c b/drivers/gpu/drm/amd/amdkcl/kcl_pci.c index 13b6180f6b3ed..6cc6a80b921e4 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_pci.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_pci.c @@ -440,3 +440,54 @@ void _kcl_pci_remove_measure_file(struct pci_dev *pdev) } EXPORT_SYMBOL(_kcl_pci_remove_measure_file); #endif /* AMDKCL_CREATE_MEASURE_FILE */ + +#ifdef AMDKCL_ENABLE_RESIZE_FB_BAR +/* Copied from drivers/pci/pci.c */ +#ifndef HAVE_PCI_REBAR_BYTES_TO_SIZE +static int _kcl_pci_rebar_find_pos(struct pci_dev *pdev, int bar) +{ + unsigned int pos, nbars, i; + u32 ctrl; + + pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR); + if (!pos) + return -ENOTSUPP; + + pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); + nbars = (ctrl & PCI_REBAR_CTRL_NBAR_MASK) >> + PCI_REBAR_CTRL_NBAR_SHIFT; + + for (i = 0; i < nbars; i++, pos += 8) { + int bar_idx; + + pci_read_config_dword(pdev, pos + PCI_REBAR_CTRL, &ctrl); + bar_idx = ctrl & PCI_REBAR_CTRL_BAR_IDX; + if (bar_idx == bar) + return pos; + } + + return -ENOENT; +} + +u32 _kcl_pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar) +{ + int pos; + u32 cap; + + pos = _kcl_pci_rebar_find_pos(pdev, bar); + if (pos < 0) + return 0; + + pci_read_config_dword(pdev, pos + PCI_REBAR_CAP, &cap); + cap &= PCI_REBAR_CAP_SIZES; + + /* Sapphire RX 5600 XT Pulse has an invalid cap dword for BAR 0 */ + if (pdev->vendor == PCI_VENDOR_ID_ATI && pdev->device == 0x731f && + bar == 0 && cap == 0x7000) + cap = 0x3f000; + + return cap >> 4; +} +EXPORT_SYMBOL(_kcl_pci_rebar_get_possible_sizes); +#endif /* HAVE_PCI_REBAR_BYTES_TO_SIZE */ +#endif /* AMDKCL_ENABLE_RESIZE_FB_BAR */ diff --git a/include/kcl/kcl_pci.h b/include/kcl/kcl_pci.h index a75ef23e8bf46..7289493f142b2 100644 --- a/include/kcl/kcl_pci.h +++ b/include/kcl/kcl_pci.h @@ -224,7 +224,19 @@ static inline int pci_rebar_bytes_to_size(u64 bytes) /* Return BAR size as defined in the resizable BAR specification */ return max(ilog2(bytes), 20) - 20; } + +/* + * 907830b0fc9e PCI: Add a REBAR size quirk for Sapphire RX 5600 XT Pulse + * 8fbdbb66f8c1 PCI: Export pci_rebar_get_possible_sizes() + */ +u32 _kcl_pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar); +static inline +u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar) +{ + return _kcl_pci_rebar_get_possible_sizes(pdev, bar); +} #endif + #endif /* PCI_REBAR_CTRL_BAR_SHIFT */ #endif /* AMDKCL_PCI_H */ From e997ee36d4e16e827a10e652f978175c8aa85064 Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Mon, 8 Mar 2021 14:15:32 +0800 Subject: [PATCH 0346/1868] drm/amdkcl: fake the drm_prime_sg_to_dma_addr_array This is caused by "drm/prime: split array import functions v4" v5.10-rc3-1140-gc67e62790f5c Signed-off-by: Shiwu Zhang --- drivers/block/umem.c | 1130 ++++++++++ drivers/block/umem.h | 132 ++ drivers/block/xsysace.c | 1273 ++++++++++++ drivers/extcon/extcon-arizona.c | 1816 +++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/drm_prime.m4 | 11 + .../gpu/drm/amd/dkms/m4/highmem-internal.m4 | 16 + drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 3 +- include/kcl/kcl_drm_prime.h | 19 + 9 files changed, 4400 insertions(+), 1 deletion(-) create mode 100644 drivers/block/umem.c create mode 100644 drivers/block/umem.h create mode 100644 drivers/block/xsysace.c create mode 100644 drivers/extcon/extcon-arizona.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_prime.m4 create mode 100644 drivers/gpu/drm/amd/dkms/m4/highmem-internal.m4 create mode 100644 include/kcl/kcl_drm_prime.h diff --git a/drivers/block/umem.c b/drivers/block/umem.c new file mode 100644 index 0000000000000..664280f23bee1 --- /dev/null +++ b/drivers/block/umem.c @@ -0,0 +1,1130 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * mm.c - Micro Memory(tm) PCI memory board block device driver - v2.3 + * + * (C) 2001 San Mehat + * (C) 2001 Johannes Erdfelt + * (C) 2001 NeilBrown + * + * This driver for the Micro Memory PCI Memory Module with Battery Backup + * is Copyright Micro Memory Inc 2001-2002. All rights reserved. + * + * This driver provides a standard block device interface for Micro Memory(tm) + * PCI based RAM boards. + * 10/05/01: Phap Nguyen - Rebuilt the driver + * 10/22/01: Phap Nguyen - v2.1 Added disk partitioning + * 29oct2001:NeilBrown - Use make_request_fn instead of request_fn + * - use stand disk partitioning (so fdisk works). + * 08nov2001:NeilBrown - change driver name from "mm" to "umem" + * - incorporate into main kernel + * 08apr2002:NeilBrown - Move some of interrupt handle to tasklet + * - use spin_lock_bh instead of _irq + * - Never block on make_request. queue + * bh's instead. + * - unregister umem from devfs at mod unload + * - Change version to 2.3 + * 07Nov2001:Phap Nguyen - Select pci read command: 06, 12, 15 (Decimal) + * 07Jan2002: P. Nguyen - Used PCI Memory Write & Invalidate for DMA + * 15May2002:NeilBrown - convert to bio for 2.5 + * 17May2002:NeilBrown - remove init_mem initialisation. Instead detect + * - a sequence of writes that cover the card, and + * - set initialised bit then. + */ + +#undef DEBUG /* #define DEBUG if you want debugging info (pr_debug) */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include /* O_ACCMODE */ +#include /* HDIO_GETGEO */ + +#include "umem.h" + +#include +#include + +#define MM_MAXCARDS 4 +#define MM_RAHEAD 2 /* two sectors */ +#define MM_BLKSIZE 1024 /* 1k blocks */ +#define MM_HARDSECT 512 /* 512-byte hardware sectors */ +#define MM_SHIFT 6 /* max 64 partitions on 4 cards */ + +/* + * Version Information + */ + +#define DRIVER_NAME "umem" +#define DRIVER_VERSION "v2.3" +#define DRIVER_AUTHOR "San Mehat, Johannes Erdfelt, NeilBrown" +#define DRIVER_DESC "Micro Memory(tm) PCI memory board block driver" + +static int debug; +/* #define HW_TRACE(x) writeb(x,cards[0].csr_remap + MEMCTRLSTATUS_MAGIC) */ +#define HW_TRACE(x) + +#define DEBUG_LED_ON_TRANSFER 0x01 +#define DEBUG_BATTERY_POLLING 0x02 + +module_param(debug, int, 0644); +MODULE_PARM_DESC(debug, "Debug bitmask"); + +static int pci_read_cmd = 0x0C; /* Read Multiple */ +module_param(pci_read_cmd, int, 0); +MODULE_PARM_DESC(pci_read_cmd, "PCI read command"); + +static int pci_write_cmd = 0x0F; /* Write and Invalidate */ +module_param(pci_write_cmd, int, 0); +MODULE_PARM_DESC(pci_write_cmd, "PCI write command"); + +static int pci_cmds; + +static int major_nr; + +#include +#include + +struct cardinfo { + struct pci_dev *dev; + + unsigned char __iomem *csr_remap; + unsigned int mm_size; /* size in kbytes */ + + unsigned int init_size; /* initial segment, in sectors, + * that we know to + * have been written + */ + struct bio *bio, *currentbio, **biotail; + struct bvec_iter current_iter; + + struct request_queue *queue; + + struct mm_page { + dma_addr_t page_dma; + struct mm_dma_desc *desc; + int cnt, headcnt; + struct bio *bio, **biotail; + struct bvec_iter iter; + } mm_pages[2]; +#define DESC_PER_PAGE ((PAGE_SIZE*2)/sizeof(struct mm_dma_desc)) + + int Active, Ready; + + struct tasklet_struct tasklet; + unsigned int dma_status; + + struct { + int good; + int warned; + unsigned long last_change; + } battery[2]; + + spinlock_t lock; + int check_batteries; + + int flags; +}; + +static struct cardinfo cards[MM_MAXCARDS]; +static struct timer_list battery_timer; + +static int num_cards; + +static struct gendisk *mm_gendisk[MM_MAXCARDS]; + +static void check_batteries(struct cardinfo *card); + +static int get_userbit(struct cardinfo *card, int bit) +{ + unsigned char led; + + led = readb(card->csr_remap + MEMCTRLCMD_LEDCTRL); + return led & bit; +} + +static int set_userbit(struct cardinfo *card, int bit, unsigned char state) +{ + unsigned char led; + + led = readb(card->csr_remap + MEMCTRLCMD_LEDCTRL); + if (state) + led |= bit; + else + led &= ~bit; + writeb(led, card->csr_remap + MEMCTRLCMD_LEDCTRL); + + return 0; +} + +/* + * NOTE: For the power LED, use the LED_POWER_* macros since they differ + */ +static void set_led(struct cardinfo *card, int shift, unsigned char state) +{ + unsigned char led; + + led = readb(card->csr_remap + MEMCTRLCMD_LEDCTRL); + if (state == LED_FLIP) + led ^= (1<csr_remap + MEMCTRLCMD_LEDCTRL); + +} + +#ifdef MM_DIAG +static void dump_regs(struct cardinfo *card) +{ + unsigned char *p; + int i, i1; + + p = card->csr_remap; + for (i = 0; i < 8; i++) { + printk(KERN_DEBUG "%p ", p); + + for (i1 = 0; i1 < 16; i1++) + printk("%02x ", *p++); + + printk("\n"); + } +} +#endif + +static void dump_dmastat(struct cardinfo *card, unsigned int dmastat) +{ + dev_printk(KERN_DEBUG, &card->dev->dev, "DMAstat - "); + if (dmastat & DMASCR_ANY_ERR) + printk(KERN_CONT "ANY_ERR "); + if (dmastat & DMASCR_MBE_ERR) + printk(KERN_CONT "MBE_ERR "); + if (dmastat & DMASCR_PARITY_ERR_REP) + printk(KERN_CONT "PARITY_ERR_REP "); + if (dmastat & DMASCR_PARITY_ERR_DET) + printk(KERN_CONT "PARITY_ERR_DET "); + if (dmastat & DMASCR_SYSTEM_ERR_SIG) + printk(KERN_CONT "SYSTEM_ERR_SIG "); + if (dmastat & DMASCR_TARGET_ABT) + printk(KERN_CONT "TARGET_ABT "); + if (dmastat & DMASCR_MASTER_ABT) + printk(KERN_CONT "MASTER_ABT "); + if (dmastat & DMASCR_CHAIN_COMPLETE) + printk(KERN_CONT "CHAIN_COMPLETE "); + if (dmastat & DMASCR_DMA_COMPLETE) + printk(KERN_CONT "DMA_COMPLETE "); + printk("\n"); +} + +/* + * Theory of request handling + * + * Each bio is assigned to one mm_dma_desc - which may not be enough FIXME + * We have two pages of mm_dma_desc, holding about 64 descriptors + * each. These are allocated at init time. + * One page is "Ready" and is either full, or can have request added. + * The other page might be "Active", which DMA is happening on it. + * + * Whenever IO on the active page completes, the Ready page is activated + * and the ex-Active page is clean out and made Ready. + * Otherwise the Ready page is only activated when it becomes full. + * + * If a request arrives while both pages a full, it is queued, and b_rdev is + * overloaded to record whether it was a read or a write. + * + * The interrupt handler only polls the device to clear the interrupt. + * The processing of the result is done in a tasklet. + */ + +static void mm_start_io(struct cardinfo *card) +{ + /* we have the lock, we know there is + * no IO active, and we know that card->Active + * is set + */ + struct mm_dma_desc *desc; + struct mm_page *page; + int offset; + + /* make the last descriptor end the chain */ + page = &card->mm_pages[card->Active]; + pr_debug("start_io: %d %d->%d\n", + card->Active, page->headcnt, page->cnt - 1); + desc = &page->desc[page->cnt-1]; + + desc->control_bits |= cpu_to_le32(DMASCR_CHAIN_COMP_EN); + desc->control_bits &= ~cpu_to_le32(DMASCR_CHAIN_EN); + desc->sem_control_bits = desc->control_bits; + + + if (debug & DEBUG_LED_ON_TRANSFER) + set_led(card, LED_REMOVE, LED_ON); + + desc = &page->desc[page->headcnt]; + writel(0, card->csr_remap + DMA_PCI_ADDR); + writel(0, card->csr_remap + DMA_PCI_ADDR + 4); + + writel(0, card->csr_remap + DMA_LOCAL_ADDR); + writel(0, card->csr_remap + DMA_LOCAL_ADDR + 4); + + writel(0, card->csr_remap + DMA_TRANSFER_SIZE); + writel(0, card->csr_remap + DMA_TRANSFER_SIZE + 4); + + writel(0, card->csr_remap + DMA_SEMAPHORE_ADDR); + writel(0, card->csr_remap + DMA_SEMAPHORE_ADDR + 4); + + offset = ((char *)desc) - ((char *)page->desc); + writel(cpu_to_le32((page->page_dma+offset) & 0xffffffff), + card->csr_remap + DMA_DESCRIPTOR_ADDR); + /* Force the value to u64 before shifting otherwise >> 32 is undefined C + * and on some ports will do nothing ! */ + writel(cpu_to_le32(((u64)page->page_dma)>>32), + card->csr_remap + DMA_DESCRIPTOR_ADDR + 4); + + /* Go, go, go */ + writel(cpu_to_le32(DMASCR_GO | DMASCR_CHAIN_EN | pci_cmds), + card->csr_remap + DMA_STATUS_CTRL); +} + +static int add_bio(struct cardinfo *card); + +static void activate(struct cardinfo *card) +{ + /* if No page is Active, and Ready is + * not empty, then switch Ready page + * to active and start IO. + * Then add any bh's that are available to Ready + */ + + do { + while (add_bio(card)) + ; + + if (card->Active == -1 && + card->mm_pages[card->Ready].cnt > 0) { + card->Active = card->Ready; + card->Ready = 1-card->Ready; + mm_start_io(card); + } + + } while (card->Active == -1 && add_bio(card)); +} + +static inline void reset_page(struct mm_page *page) +{ + page->cnt = 0; + page->headcnt = 0; + page->bio = NULL; + page->biotail = &page->bio; +} + +/* + * If there is room on Ready page, take + * one bh off list and add it. + * return 1 if there was room, else 0. + */ +static int add_bio(struct cardinfo *card) +{ + struct mm_page *p; + struct mm_dma_desc *desc; + dma_addr_t dma_handle; + int offset; + struct bio *bio; + struct bio_vec vec; + + bio = card->currentbio; + if (!bio && card->bio) { + card->currentbio = card->bio; + card->current_iter = card->bio->bi_iter; + card->bio = card->bio->bi_next; + if (card->bio == NULL) + card->biotail = &card->bio; + card->currentbio->bi_next = NULL; + return 1; + } + if (!bio) + return 0; + + if (card->mm_pages[card->Ready].cnt >= DESC_PER_PAGE) + return 0; + + vec = bio_iter_iovec(bio, card->current_iter); + + dma_handle = dma_map_page(&card->dev->dev, + vec.bv_page, + vec.bv_offset, + vec.bv_len, + bio_op(bio) == REQ_OP_READ ? + DMA_FROM_DEVICE : DMA_TO_DEVICE); + + p = &card->mm_pages[card->Ready]; + desc = &p->desc[p->cnt]; + p->cnt++; + if (p->bio == NULL) + p->iter = card->current_iter; + if ((p->biotail) != &bio->bi_next) { + *(p->biotail) = bio; + p->biotail = &(bio->bi_next); + bio->bi_next = NULL; + } + + desc->data_dma_handle = dma_handle; + + desc->pci_addr = cpu_to_le64((u64)desc->data_dma_handle); + desc->local_addr = cpu_to_le64(card->current_iter.bi_sector << 9); + desc->transfer_size = cpu_to_le32(vec.bv_len); + offset = (((char *)&desc->sem_control_bits) - ((char *)p->desc)); + desc->sem_addr = cpu_to_le64((u64)(p->page_dma+offset)); + desc->zero1 = desc->zero2 = 0; + offset = (((char *)(desc+1)) - ((char *)p->desc)); + desc->next_desc_addr = cpu_to_le64(p->page_dma+offset); + desc->control_bits = cpu_to_le32(DMASCR_GO|DMASCR_ERR_INT_EN| + DMASCR_PARITY_INT_EN| + DMASCR_CHAIN_EN | + DMASCR_SEM_EN | + pci_cmds); + if (bio_op(bio) == REQ_OP_WRITE) + desc->control_bits |= cpu_to_le32(DMASCR_TRANSFER_READ); + desc->sem_control_bits = desc->control_bits; + + + bio_advance_iter(bio, &card->current_iter, vec.bv_len); + if (!card->current_iter.bi_size) + card->currentbio = NULL; + + return 1; +} + +static void process_page(unsigned long data) +{ + /* check if any of the requests in the page are DMA_COMPLETE, + * and deal with them appropriately. + * If we find a descriptor without DMA_COMPLETE in the semaphore, then + * dma must have hit an error on that descriptor, so use dma_status + * instead and assume that all following descriptors must be re-tried. + */ + struct mm_page *page; + struct bio *return_bio = NULL; + struct cardinfo *card = (struct cardinfo *)data; + unsigned int dma_status = card->dma_status; + + spin_lock(&card->lock); + if (card->Active < 0) + goto out_unlock; + page = &card->mm_pages[card->Active]; + + while (page->headcnt < page->cnt) { + struct bio *bio = page->bio; + struct mm_dma_desc *desc = &page->desc[page->headcnt]; + int control = le32_to_cpu(desc->sem_control_bits); + int last = 0; + struct bio_vec vec; + + if (!(control & DMASCR_DMA_COMPLETE)) { + control = dma_status; + last = 1; + } + + page->headcnt++; + vec = bio_iter_iovec(bio, page->iter); + bio_advance_iter(bio, &page->iter, vec.bv_len); + + if (!page->iter.bi_size) { + page->bio = bio->bi_next; + if (page->bio) + page->iter = page->bio->bi_iter; + } + + dma_unmap_page(&card->dev->dev, desc->data_dma_handle, + vec.bv_len, + (control & DMASCR_TRANSFER_READ) ? + DMA_TO_DEVICE : DMA_FROM_DEVICE); + if (control & DMASCR_HARD_ERROR) { + /* error */ + bio->bi_status = BLK_STS_IOERR; + dev_printk(KERN_WARNING, &card->dev->dev, + "I/O error on sector %d/%d\n", + le32_to_cpu(desc->local_addr)>>9, + le32_to_cpu(desc->transfer_size)); + dump_dmastat(card, control); + } else if (op_is_write(bio_op(bio)) && + le32_to_cpu(desc->local_addr) >> 9 == + card->init_size) { + card->init_size += le32_to_cpu(desc->transfer_size) >> 9; + if (card->init_size >> 1 >= card->mm_size) { + dev_printk(KERN_INFO, &card->dev->dev, + "memory now initialised\n"); + set_userbit(card, MEMORY_INITIALIZED, 1); + } + } + if (bio != page->bio) { + bio->bi_next = return_bio; + return_bio = bio; + } + + if (last) + break; + } + + if (debug & DEBUG_LED_ON_TRANSFER) + set_led(card, LED_REMOVE, LED_OFF); + + if (card->check_batteries) { + card->check_batteries = 0; + check_batteries(card); + } + if (page->headcnt >= page->cnt) { + reset_page(page); + card->Active = -1; + activate(card); + } else { + /* haven't finished with this one yet */ + pr_debug("do some more\n"); + mm_start_io(card); + } + out_unlock: + spin_unlock(&card->lock); + + while (return_bio) { + struct bio *bio = return_bio; + + return_bio = bio->bi_next; + bio->bi_next = NULL; + bio_endio(bio); + } +} + +static void mm_unplug(struct blk_plug_cb *cb, bool from_schedule) +{ + struct cardinfo *card = cb->data; + + spin_lock_irq(&card->lock); + activate(card); + spin_unlock_irq(&card->lock); + kfree(cb); +} + +static int mm_check_plugged(struct cardinfo *card) +{ + return !!blk_check_plugged(mm_unplug, card, sizeof(struct blk_plug_cb)); +} + +static blk_qc_t mm_submit_bio(struct bio *bio) +{ + struct cardinfo *card = bio->bi_bdev->bd_disk->private_data; + + pr_debug("mm_make_request %llu %u\n", + (unsigned long long)bio->bi_iter.bi_sector, + bio->bi_iter.bi_size); + + blk_queue_split(&bio); + + spin_lock_irq(&card->lock); + *card->biotail = bio; + bio->bi_next = NULL; + card->biotail = &bio->bi_next; + if (op_is_sync(bio->bi_opf) || !mm_check_plugged(card)) + activate(card); + spin_unlock_irq(&card->lock); + + return BLK_QC_T_NONE; +} + +static irqreturn_t mm_interrupt(int irq, void *__card) +{ + struct cardinfo *card = (struct cardinfo *) __card; + unsigned int dma_status; + unsigned short cfg_status; + +HW_TRACE(0x30); + + dma_status = le32_to_cpu(readl(card->csr_remap + DMA_STATUS_CTRL)); + + if (!(dma_status & (DMASCR_ERROR_MASK | DMASCR_CHAIN_COMPLETE))) { + /* interrupt wasn't for me ... */ + return IRQ_NONE; + } + + /* clear COMPLETION interrupts */ + if (card->flags & UM_FLAG_NO_BYTE_STATUS) + writel(cpu_to_le32(DMASCR_DMA_COMPLETE|DMASCR_CHAIN_COMPLETE), + card->csr_remap + DMA_STATUS_CTRL); + else + writeb((DMASCR_DMA_COMPLETE|DMASCR_CHAIN_COMPLETE) >> 16, + card->csr_remap + DMA_STATUS_CTRL + 2); + + /* log errors and clear interrupt status */ + if (dma_status & DMASCR_ANY_ERR) { + unsigned int data_log1, data_log2; + unsigned int addr_log1, addr_log2; + unsigned char stat, count, syndrome, check; + + stat = readb(card->csr_remap + MEMCTRLCMD_ERRSTATUS); + + data_log1 = le32_to_cpu(readl(card->csr_remap + + ERROR_DATA_LOG)); + data_log2 = le32_to_cpu(readl(card->csr_remap + + ERROR_DATA_LOG + 4)); + addr_log1 = le32_to_cpu(readl(card->csr_remap + + ERROR_ADDR_LOG)); + addr_log2 = readb(card->csr_remap + ERROR_ADDR_LOG + 4); + + count = readb(card->csr_remap + ERROR_COUNT); + syndrome = readb(card->csr_remap + ERROR_SYNDROME); + check = readb(card->csr_remap + ERROR_CHECK); + + dump_dmastat(card, dma_status); + + if (stat & 0x01) + dev_printk(KERN_ERR, &card->dev->dev, + "Memory access error detected (err count %d)\n", + count); + if (stat & 0x02) + dev_printk(KERN_ERR, &card->dev->dev, + "Multi-bit EDC error\n"); + + dev_printk(KERN_ERR, &card->dev->dev, + "Fault Address 0x%02x%08x, Fault Data 0x%08x%08x\n", + addr_log2, addr_log1, data_log2, data_log1); + dev_printk(KERN_ERR, &card->dev->dev, + "Fault Check 0x%02x, Fault Syndrome 0x%02x\n", + check, syndrome); + + writeb(0, card->csr_remap + ERROR_COUNT); + } + + if (dma_status & DMASCR_PARITY_ERR_REP) { + dev_printk(KERN_ERR, &card->dev->dev, + "PARITY ERROR REPORTED\n"); + pci_read_config_word(card->dev, PCI_STATUS, &cfg_status); + pci_write_config_word(card->dev, PCI_STATUS, cfg_status); + } + + if (dma_status & DMASCR_PARITY_ERR_DET) { + dev_printk(KERN_ERR, &card->dev->dev, + "PARITY ERROR DETECTED\n"); + pci_read_config_word(card->dev, PCI_STATUS, &cfg_status); + pci_write_config_word(card->dev, PCI_STATUS, cfg_status); + } + + if (dma_status & DMASCR_SYSTEM_ERR_SIG) { + dev_printk(KERN_ERR, &card->dev->dev, "SYSTEM ERROR\n"); + pci_read_config_word(card->dev, PCI_STATUS, &cfg_status); + pci_write_config_word(card->dev, PCI_STATUS, cfg_status); + } + + if (dma_status & DMASCR_TARGET_ABT) { + dev_printk(KERN_ERR, &card->dev->dev, "TARGET ABORT\n"); + pci_read_config_word(card->dev, PCI_STATUS, &cfg_status); + pci_write_config_word(card->dev, PCI_STATUS, cfg_status); + } + + if (dma_status & DMASCR_MASTER_ABT) { + dev_printk(KERN_ERR, &card->dev->dev, "MASTER ABORT\n"); + pci_read_config_word(card->dev, PCI_STATUS, &cfg_status); + pci_write_config_word(card->dev, PCI_STATUS, cfg_status); + } + + /* and process the DMA descriptors */ + card->dma_status = dma_status; + tasklet_schedule(&card->tasklet); + +HW_TRACE(0x36); + + return IRQ_HANDLED; +} + +/* + * If both batteries are good, no LED + * If either battery has been warned, solid LED + * If both batteries are bad, flash the LED quickly + * If either battery is bad, flash the LED semi quickly + */ +static void set_fault_to_battery_status(struct cardinfo *card) +{ + if (card->battery[0].good && card->battery[1].good) + set_led(card, LED_FAULT, LED_OFF); + else if (card->battery[0].warned || card->battery[1].warned) + set_led(card, LED_FAULT, LED_ON); + else if (!card->battery[0].good && !card->battery[1].good) + set_led(card, LED_FAULT, LED_FLASH_7_0); + else + set_led(card, LED_FAULT, LED_FLASH_3_5); +} + +static void init_battery_timer(void); + +static int check_battery(struct cardinfo *card, int battery, int status) +{ + if (status != card->battery[battery].good) { + card->battery[battery].good = !card->battery[battery].good; + card->battery[battery].last_change = jiffies; + + if (card->battery[battery].good) { + dev_printk(KERN_ERR, &card->dev->dev, + "Battery %d now good\n", battery + 1); + card->battery[battery].warned = 0; + } else + dev_printk(KERN_ERR, &card->dev->dev, + "Battery %d now FAILED\n", battery + 1); + + return 1; + } else if (!card->battery[battery].good && + !card->battery[battery].warned && + time_after_eq(jiffies, card->battery[battery].last_change + + (HZ * 60 * 60 * 5))) { + dev_printk(KERN_ERR, &card->dev->dev, + "Battery %d still FAILED after 5 hours\n", battery + 1); + card->battery[battery].warned = 1; + + return 1; + } + + return 0; +} + +static void check_batteries(struct cardinfo *card) +{ + /* NOTE: this must *never* be called while the card + * is doing (bus-to-card) DMA, or you will need the + * reset switch + */ + unsigned char status; + int ret1, ret2; + + status = readb(card->csr_remap + MEMCTRLSTATUS_BATTERY); + if (debug & DEBUG_BATTERY_POLLING) + dev_printk(KERN_DEBUG, &card->dev->dev, + "checking battery status, 1 = %s, 2 = %s\n", + (status & BATTERY_1_FAILURE) ? "FAILURE" : "OK", + (status & BATTERY_2_FAILURE) ? "FAILURE" : "OK"); + + ret1 = check_battery(card, 0, !(status & BATTERY_1_FAILURE)); + ret2 = check_battery(card, 1, !(status & BATTERY_2_FAILURE)); + + if (ret1 || ret2) + set_fault_to_battery_status(card); +} + +static void check_all_batteries(struct timer_list *unused) +{ + int i; + + for (i = 0; i < num_cards; i++) + if (!(cards[i].flags & UM_FLAG_NO_BATT)) { + struct cardinfo *card = &cards[i]; + spin_lock_bh(&card->lock); + if (card->Active >= 0) + card->check_batteries = 1; + else + check_batteries(card); + spin_unlock_bh(&card->lock); + } + + init_battery_timer(); +} + +static void init_battery_timer(void) +{ + timer_setup(&battery_timer, check_all_batteries, 0); + battery_timer.expires = jiffies + (HZ * 60); + add_timer(&battery_timer); +} + +static void del_battery_timer(void) +{ + del_timer(&battery_timer); +} + +/* + * Note no locks taken out here. In a worst case scenario, we could drop + * a chunk of system memory. But that should never happen, since validation + * happens at open or mount time, when locks are held. + * + * That's crap, since doing that while some partitions are opened + * or mounted will give you really nasty results. + */ +static int mm_revalidate(struct gendisk *disk) +{ + struct cardinfo *card = disk->private_data; + set_capacity(disk, card->mm_size << 1); + return 0; +} + +static int mm_getgeo(struct block_device *bdev, struct hd_geometry *geo) +{ + struct cardinfo *card = bdev->bd_disk->private_data; + int size = card->mm_size * (1024 / MM_HARDSECT); + + /* + * get geometry: we have to fake one... trim the size to a + * multiple of 2048 (1M): tell we have 32 sectors, 64 heads, + * whatever cylinders. + */ + geo->heads = 64; + geo->sectors = 32; + geo->cylinders = size / (geo->heads * geo->sectors); + return 0; +} + +static const struct block_device_operations mm_fops = { + .owner = THIS_MODULE, + .submit_bio = mm_submit_bio, + .getgeo = mm_getgeo, + .revalidate_disk = mm_revalidate, +}; + +static int mm_pci_probe(struct pci_dev *dev, const struct pci_device_id *id) +{ + int ret; + struct cardinfo *card = &cards[num_cards]; + unsigned char mem_present; + unsigned char batt_status; + unsigned int saved_bar, data; + unsigned long csr_base; + unsigned long csr_len; + int magic_number; + static int printed_version; + + if (!printed_version++) + printk(KERN_INFO DRIVER_VERSION " : " DRIVER_DESC "\n"); + + ret = pci_enable_device(dev); + if (ret) + return ret; + + pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xF8); + pci_set_master(dev); + + card->dev = dev; + + csr_base = pci_resource_start(dev, 0); + csr_len = pci_resource_len(dev, 0); + if (!csr_base || !csr_len) + return -ENODEV; + + dev_printk(KERN_INFO, &dev->dev, + "Micro Memory(tm) controller found (PCI Mem Module (Battery Backup))\n"); + + if (dma_set_mask(&dev->dev, DMA_BIT_MASK(64)) && + dma_set_mask(&dev->dev, DMA_BIT_MASK(32))) { + dev_printk(KERN_WARNING, &dev->dev, "NO suitable DMA found\n"); + return -ENOMEM; + } + + ret = pci_request_regions(dev, DRIVER_NAME); + if (ret) { + dev_printk(KERN_ERR, &card->dev->dev, + "Unable to request memory region\n"); + goto failed_req_csr; + } + + card->csr_remap = ioremap(csr_base, csr_len); + if (!card->csr_remap) { + dev_printk(KERN_ERR, &card->dev->dev, + "Unable to remap memory region\n"); + ret = -ENOMEM; + + goto failed_remap_csr; + } + + dev_printk(KERN_INFO, &card->dev->dev, + "CSR 0x%08lx -> 0x%p (0x%lx)\n", + csr_base, card->csr_remap, csr_len); + + switch (card->dev->device) { + case 0x5415: + card->flags |= UM_FLAG_NO_BYTE_STATUS | UM_FLAG_NO_BATTREG; + magic_number = 0x59; + break; + + case 0x5425: + card->flags |= UM_FLAG_NO_BYTE_STATUS; + magic_number = 0x5C; + break; + + case 0x6155: + card->flags |= UM_FLAG_NO_BYTE_STATUS | + UM_FLAG_NO_BATTREG | UM_FLAG_NO_BATT; + magic_number = 0x99; + break; + + default: + magic_number = 0x100; + break; + } + + if (readb(card->csr_remap + MEMCTRLSTATUS_MAGIC) != magic_number) { + dev_printk(KERN_ERR, &card->dev->dev, "Magic number invalid\n"); + ret = -ENOMEM; + goto failed_magic; + } + + card->mm_pages[0].desc = dma_alloc_coherent(&card->dev->dev, + PAGE_SIZE * 2, &card->mm_pages[0].page_dma, GFP_KERNEL); + card->mm_pages[1].desc = dma_alloc_coherent(&card->dev->dev, + PAGE_SIZE * 2, &card->mm_pages[1].page_dma, GFP_KERNEL); + if (card->mm_pages[0].desc == NULL || + card->mm_pages[1].desc == NULL) { + dev_printk(KERN_ERR, &card->dev->dev, "alloc failed\n"); + ret = -ENOMEM; + goto failed_alloc; + } + reset_page(&card->mm_pages[0]); + reset_page(&card->mm_pages[1]); + card->Ready = 0; /* page 0 is ready */ + card->Active = -1; /* no page is active */ + card->bio = NULL; + card->biotail = &card->bio; + spin_lock_init(&card->lock); + + card->queue = blk_alloc_queue(NUMA_NO_NODE); + if (!card->queue) { + ret = -ENOMEM; + goto failed_alloc; + } + + tasklet_init(&card->tasklet, process_page, (unsigned long)card); + + card->check_batteries = 0; + + mem_present = readb(card->csr_remap + MEMCTRLSTATUS_MEMORY); + switch (mem_present) { + case MEM_128_MB: + card->mm_size = 1024 * 128; + break; + case MEM_256_MB: + card->mm_size = 1024 * 256; + break; + case MEM_512_MB: + card->mm_size = 1024 * 512; + break; + case MEM_1_GB: + card->mm_size = 1024 * 1024; + break; + case MEM_2_GB: + card->mm_size = 1024 * 2048; + break; + default: + card->mm_size = 0; + break; + } + + /* Clear the LED's we control */ + set_led(card, LED_REMOVE, LED_OFF); + set_led(card, LED_FAULT, LED_OFF); + + batt_status = readb(card->csr_remap + MEMCTRLSTATUS_BATTERY); + + card->battery[0].good = !(batt_status & BATTERY_1_FAILURE); + card->battery[1].good = !(batt_status & BATTERY_2_FAILURE); + card->battery[0].last_change = card->battery[1].last_change = jiffies; + + if (card->flags & UM_FLAG_NO_BATT) + dev_printk(KERN_INFO, &card->dev->dev, + "Size %d KB\n", card->mm_size); + else { + dev_printk(KERN_INFO, &card->dev->dev, + "Size %d KB, Battery 1 %s (%s), Battery 2 %s (%s)\n", + card->mm_size, + batt_status & BATTERY_1_DISABLED ? "Disabled" : "Enabled", + card->battery[0].good ? "OK" : "FAILURE", + batt_status & BATTERY_2_DISABLED ? "Disabled" : "Enabled", + card->battery[1].good ? "OK" : "FAILURE"); + + set_fault_to_battery_status(card); + } + + pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, &saved_bar); + data = 0xffffffff; + pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, data); + pci_read_config_dword(dev, PCI_BASE_ADDRESS_1, &data); + pci_write_config_dword(dev, PCI_BASE_ADDRESS_1, saved_bar); + data &= 0xfffffff0; + data = ~data; + data += 1; + + if (request_irq(dev->irq, mm_interrupt, IRQF_SHARED, DRIVER_NAME, + card)) { + dev_printk(KERN_ERR, &card->dev->dev, + "Unable to allocate IRQ\n"); + ret = -ENODEV; + goto failed_req_irq; + } + + dev_printk(KERN_INFO, &card->dev->dev, + "Window size %d bytes, IRQ %d\n", data, dev->irq); + + pci_set_drvdata(dev, card); + + if (pci_write_cmd != 0x0F) /* If not Memory Write & Invalidate */ + pci_write_cmd = 0x07; /* then Memory Write command */ + + if (pci_write_cmd & 0x08) { /* use Memory Write and Invalidate */ + unsigned short cfg_command; + pci_read_config_word(dev, PCI_COMMAND, &cfg_command); + cfg_command |= 0x10; /* Memory Write & Invalidate Enable */ + pci_write_config_word(dev, PCI_COMMAND, cfg_command); + } + pci_cmds = (pci_read_cmd << 28) | (pci_write_cmd << 24); + + num_cards++; + + if (!get_userbit(card, MEMORY_INITIALIZED)) { + dev_printk(KERN_INFO, &card->dev->dev, + "memory NOT initialized. Consider over-writing whole device.\n"); + card->init_size = 0; + } else { + dev_printk(KERN_INFO, &card->dev->dev, + "memory already initialized\n"); + card->init_size = card->mm_size; + } + + /* Enable ECC */ + writeb(EDC_STORE_CORRECT, card->csr_remap + MEMCTRLCMD_ERRCTRL); + + return 0; + + failed_req_irq: + failed_alloc: + if (card->mm_pages[0].desc) + dma_free_coherent(&card->dev->dev, PAGE_SIZE * 2, + card->mm_pages[0].desc, + card->mm_pages[0].page_dma); + if (card->mm_pages[1].desc) + dma_free_coherent(&card->dev->dev, PAGE_SIZE * 2, + card->mm_pages[1].desc, + card->mm_pages[1].page_dma); + failed_magic: + iounmap(card->csr_remap); + failed_remap_csr: + pci_release_regions(dev); + failed_req_csr: + + return ret; +} + +static void mm_pci_remove(struct pci_dev *dev) +{ + struct cardinfo *card = pci_get_drvdata(dev); + + tasklet_kill(&card->tasklet); + free_irq(dev->irq, card); + iounmap(card->csr_remap); + + if (card->mm_pages[0].desc) + dma_free_coherent(&card->dev->dev, PAGE_SIZE * 2, + card->mm_pages[0].desc, + card->mm_pages[0].page_dma); + if (card->mm_pages[1].desc) + dma_free_coherent(&card->dev->dev, PAGE_SIZE * 2, + card->mm_pages[1].desc, + card->mm_pages[1].page_dma); + blk_cleanup_queue(card->queue); + + pci_release_regions(dev); + pci_disable_device(dev); +} + +static const struct pci_device_id mm_pci_ids[] = { + {PCI_DEVICE(PCI_VENDOR_ID_MICRO_MEMORY, PCI_DEVICE_ID_MICRO_MEMORY_5415CN)}, + {PCI_DEVICE(PCI_VENDOR_ID_MICRO_MEMORY, PCI_DEVICE_ID_MICRO_MEMORY_5425CN)}, + {PCI_DEVICE(PCI_VENDOR_ID_MICRO_MEMORY, PCI_DEVICE_ID_MICRO_MEMORY_6155)}, + { + .vendor = 0x8086, + .device = 0xB555, + .subvendor = 0x1332, + .subdevice = 0x5460, + .class = 0x050000, + .class_mask = 0, + }, { /* end: all zeroes */ } +}; + +MODULE_DEVICE_TABLE(pci, mm_pci_ids); + +static struct pci_driver mm_pci_driver = { + .name = DRIVER_NAME, + .id_table = mm_pci_ids, + .probe = mm_pci_probe, + .remove = mm_pci_remove, +}; + +static int __init mm_init(void) +{ + int retval, i; + int err; + + retval = pci_register_driver(&mm_pci_driver); + if (retval) + return -ENOMEM; + + err = major_nr = register_blkdev(0, DRIVER_NAME); + if (err < 0) { + pci_unregister_driver(&mm_pci_driver); + return -EIO; + } + + for (i = 0; i < num_cards; i++) { + mm_gendisk[i] = alloc_disk(1 << MM_SHIFT); + if (!mm_gendisk[i]) + goto out; + } + + for (i = 0; i < num_cards; i++) { + struct gendisk *disk = mm_gendisk[i]; + sprintf(disk->disk_name, "umem%c", 'a'+i); + spin_lock_init(&cards[i].lock); + disk->major = major_nr; + disk->first_minor = i << MM_SHIFT; + disk->fops = &mm_fops; + disk->private_data = &cards[i]; + disk->queue = cards[i].queue; + set_capacity(disk, cards[i].mm_size << 1); + add_disk(disk); + } + + init_battery_timer(); + printk(KERN_INFO "MM: desc_per_page = %ld\n", DESC_PER_PAGE); +/* printk("mm_init: Done. 10-19-01 9:00\n"); */ + return 0; + +out: + pci_unregister_driver(&mm_pci_driver); + unregister_blkdev(major_nr, DRIVER_NAME); + while (i--) + put_disk(mm_gendisk[i]); + return -ENOMEM; +} + +static void __exit mm_cleanup(void) +{ + int i; + + del_battery_timer(); + + for (i = 0; i < num_cards ; i++) { + del_gendisk(mm_gendisk[i]); + put_disk(mm_gendisk[i]); + } + + pci_unregister_driver(&mm_pci_driver); + + unregister_blkdev(major_nr, DRIVER_NAME); +} + +module_init(mm_init); +module_exit(mm_cleanup); + +MODULE_AUTHOR(DRIVER_AUTHOR); +MODULE_DESCRIPTION(DRIVER_DESC); +MODULE_LICENSE("GPL"); diff --git a/drivers/block/umem.h b/drivers/block/umem.h new file mode 100644 index 0000000000000..58384978ff054 --- /dev/null +++ b/drivers/block/umem.h @@ -0,0 +1,132 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * This file contains defines for the + * Micro Memory MM5415 + * family PCI Memory Module with Battery Backup. + * + * Copyright Micro Memory INC 2001. All rights reserved. + */ + +#ifndef _DRIVERS_BLOCK_MM_H +#define _DRIVERS_BLOCK_MM_H + + +#define IRQ_TIMEOUT (1 * HZ) + +/* CSR register definition */ +#define MEMCTRLSTATUS_MAGIC 0x00 +#define MM_MAGIC_VALUE (unsigned char)0x59 + +#define MEMCTRLSTATUS_BATTERY 0x04 +#define BATTERY_1_DISABLED 0x01 +#define BATTERY_1_FAILURE 0x02 +#define BATTERY_2_DISABLED 0x04 +#define BATTERY_2_FAILURE 0x08 + +#define MEMCTRLSTATUS_MEMORY 0x07 +#define MEM_128_MB 0xfe +#define MEM_256_MB 0xfc +#define MEM_512_MB 0xf8 +#define MEM_1_GB 0xf0 +#define MEM_2_GB 0xe0 + +#define MEMCTRLCMD_LEDCTRL 0x08 +#define LED_REMOVE 2 +#define LED_FAULT 4 +#define LED_POWER 6 +#define LED_FLIP 255 +#define LED_OFF 0x00 +#define LED_ON 0x01 +#define LED_FLASH_3_5 0x02 +#define LED_FLASH_7_0 0x03 +#define LED_POWER_ON 0x00 +#define LED_POWER_OFF 0x01 +#define USER_BIT1 0x01 +#define USER_BIT2 0x02 + +#define MEMORY_INITIALIZED USER_BIT1 + +#define MEMCTRLCMD_ERRCTRL 0x0C +#define EDC_NONE_DEFAULT 0x00 +#define EDC_NONE 0x01 +#define EDC_STORE_READ 0x02 +#define EDC_STORE_CORRECT 0x03 + +#define MEMCTRLCMD_ERRCNT 0x0D +#define MEMCTRLCMD_ERRSTATUS 0x0E + +#define ERROR_DATA_LOG 0x20 +#define ERROR_ADDR_LOG 0x28 +#define ERROR_COUNT 0x3D +#define ERROR_SYNDROME 0x3E +#define ERROR_CHECK 0x3F + +#define DMA_PCI_ADDR 0x40 +#define DMA_LOCAL_ADDR 0x48 +#define DMA_TRANSFER_SIZE 0x50 +#define DMA_DESCRIPTOR_ADDR 0x58 +#define DMA_SEMAPHORE_ADDR 0x60 +#define DMA_STATUS_CTRL 0x68 +#define DMASCR_GO 0x00001 +#define DMASCR_TRANSFER_READ 0x00002 +#define DMASCR_CHAIN_EN 0x00004 +#define DMASCR_SEM_EN 0x00010 +#define DMASCR_DMA_COMP_EN 0x00020 +#define DMASCR_CHAIN_COMP_EN 0x00040 +#define DMASCR_ERR_INT_EN 0x00080 +#define DMASCR_PARITY_INT_EN 0x00100 +#define DMASCR_ANY_ERR 0x00800 +#define DMASCR_MBE_ERR 0x01000 +#define DMASCR_PARITY_ERR_REP 0x02000 +#define DMASCR_PARITY_ERR_DET 0x04000 +#define DMASCR_SYSTEM_ERR_SIG 0x08000 +#define DMASCR_TARGET_ABT 0x10000 +#define DMASCR_MASTER_ABT 0x20000 +#define DMASCR_DMA_COMPLETE 0x40000 +#define DMASCR_CHAIN_COMPLETE 0x80000 + +/* +3.SOME PCs HAVE HOST BRIDGES WHICH APPARENTLY DO NOT CORRECTLY HANDLE +READ-LINE (0xE) OR READ-MULTIPLE (0xC) PCI COMMAND CODES DURING DMA +TRANSFERS. IN OTHER SYSTEMS THESE COMMAND CODES WILL CAUSE THE HOST BRIDGE +TO ALLOW LONGER BURSTS DURING DMA READ OPERATIONS. THE UPPER FOUR BITS +(31..28) OF THE DMA CSR HAVE BEEN MADE PROGRAMMABLE, SO THAT EITHER A 0x6, +AN 0xE OR A 0xC CAN BE WRITTEN TO THEM TO SET THE COMMAND CODE USED DURING +DMA READ OPERATIONS. +*/ +#define DMASCR_READ 0x60000000 +#define DMASCR_READLINE 0xE0000000 +#define DMASCR_READMULTI 0xC0000000 + + +#define DMASCR_ERROR_MASK (DMASCR_MASTER_ABT | DMASCR_TARGET_ABT | DMASCR_SYSTEM_ERR_SIG | DMASCR_PARITY_ERR_DET | DMASCR_MBE_ERR | DMASCR_ANY_ERR) +#define DMASCR_HARD_ERROR (DMASCR_MASTER_ABT | DMASCR_TARGET_ABT | DMASCR_SYSTEM_ERR_SIG | DMASCR_PARITY_ERR_DET | DMASCR_MBE_ERR) + +#define WINDOWMAP_WINNUM 0x7B + +#define DMA_READ_FROM_HOST 0 +#define DMA_WRITE_TO_HOST 1 + +struct mm_dma_desc { + __le64 pci_addr; + __le64 local_addr; + __le32 transfer_size; + u32 zero1; + __le64 next_desc_addr; + __le64 sem_addr; + __le32 control_bits; + u32 zero2; + + dma_addr_t data_dma_handle; + + /* Copy of the bits */ + __le64 sem_control_bits; +} __attribute__((aligned(8))); + +/* bits for card->flags */ +#define UM_FLAG_DMA_IN_REGS 1 +#define UM_FLAG_NO_BYTE_STATUS 2 +#define UM_FLAG_NO_BATTREG 4 +#define UM_FLAG_NO_BATT 8 +#endif diff --git a/drivers/block/xsysace.c b/drivers/block/xsysace.c new file mode 100644 index 0000000000000..eb8ef65778c35 --- /dev/null +++ b/drivers/block/xsysace.c @@ -0,0 +1,1273 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Xilinx SystemACE device driver + * + * Copyright 2007 Secret Lab Technologies Ltd. + */ + +/* + * The SystemACE chip is designed to configure FPGAs by loading an FPGA + * bitstream from a file on a CF card and squirting it into FPGAs connected + * to the SystemACE JTAG chain. It also has the advantage of providing an + * MPU interface which can be used to control the FPGA configuration process + * and to use the attached CF card for general purpose storage. + * + * This driver is a block device driver for the SystemACE. + * + * Initialization: + * The driver registers itself as a platform_device driver at module + * load time. The platform bus will take care of calling the + * ace_probe() method for all SystemACE instances in the system. Any + * number of SystemACE instances are supported. ace_probe() calls + * ace_setup() which initialized all data structures, reads the CF + * id structure and registers the device. + * + * Processing: + * Just about all of the heavy lifting in this driver is performed by + * a Finite State Machine (FSM). The driver needs to wait on a number + * of events; some raised by interrupts, some which need to be polled + * for. Describing all of the behaviour in a FSM seems to be the + * easiest way to keep the complexity low and make it easy to + * understand what the driver is doing. If the block ops or the + * request function need to interact with the hardware, then they + * simply need to flag the request and kick of FSM processing. + * + * The FSM itself is atomic-safe code which can be run from any + * context. The general process flow is: + * 1. obtain the ace->lock spinlock. + * 2. loop on ace_fsm_dostate() until the ace->fsm_continue flag is + * cleared. + * 3. release the lock. + * + * Individual states do not sleep in any way. If a condition needs to + * be waited for then the state much clear the fsm_continue flag and + * either schedule the FSM to be run again at a later time, or expect + * an interrupt to call the FSM when the desired condition is met. + * + * In normal operation, the FSM is processed at interrupt context + * either when the driver's tasklet is scheduled, or when an irq is + * raised by the hardware. The tasklet can be scheduled at any time. + * The request method in particular schedules the tasklet when a new + * request has been indicated by the block layer. Once started, the + * FSM proceeds as far as it can processing the request until it + * needs on a hardware event. At this point, it must yield execution. + * + * A state has two options when yielding execution: + * 1. ace_fsm_yield() + * - Call if need to poll for event. + * - clears the fsm_continue flag to exit the processing loop + * - reschedules the tasklet to run again as soon as possible + * 2. ace_fsm_yieldirq() + * - Call if an irq is expected from the HW + * - clears the fsm_continue flag to exit the processing loop + * - does not reschedule the tasklet so the FSM will not be processed + * again until an irq is received. + * After calling a yield function, the state must return control back + * to the FSM main loop. + * + * Additionally, the driver maintains a kernel timer which can process + * the FSM. If the FSM gets stalled, typically due to a missed + * interrupt, then the kernel timer will expire and the driver can + * continue where it left off. + * + * To Do: + * - Add FPGA configuration control interface. + * - Request major number from lanana + */ + +#undef DEBUG + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#if defined(CONFIG_OF) +#include +#include +#include +#endif + +MODULE_AUTHOR("Grant Likely "); +MODULE_DESCRIPTION("Xilinx SystemACE device driver"); +MODULE_LICENSE("GPL"); + +/* SystemACE register definitions */ +#define ACE_BUSMODE (0x00) + +#define ACE_STATUS (0x04) +#define ACE_STATUS_CFGLOCK (0x00000001) +#define ACE_STATUS_MPULOCK (0x00000002) +#define ACE_STATUS_CFGERROR (0x00000004) /* config controller error */ +#define ACE_STATUS_CFCERROR (0x00000008) /* CF controller error */ +#define ACE_STATUS_CFDETECT (0x00000010) +#define ACE_STATUS_DATABUFRDY (0x00000020) +#define ACE_STATUS_DATABUFMODE (0x00000040) +#define ACE_STATUS_CFGDONE (0x00000080) +#define ACE_STATUS_RDYFORCFCMD (0x00000100) +#define ACE_STATUS_CFGMODEPIN (0x00000200) +#define ACE_STATUS_CFGADDR_MASK (0x0000e000) +#define ACE_STATUS_CFBSY (0x00020000) +#define ACE_STATUS_CFRDY (0x00040000) +#define ACE_STATUS_CFDWF (0x00080000) +#define ACE_STATUS_CFDSC (0x00100000) +#define ACE_STATUS_CFDRQ (0x00200000) +#define ACE_STATUS_CFCORR (0x00400000) +#define ACE_STATUS_CFERR (0x00800000) + +#define ACE_ERROR (0x08) +#define ACE_CFGLBA (0x0c) +#define ACE_MPULBA (0x10) + +#define ACE_SECCNTCMD (0x14) +#define ACE_SECCNTCMD_RESET (0x0100) +#define ACE_SECCNTCMD_IDENTIFY (0x0200) +#define ACE_SECCNTCMD_READ_DATA (0x0300) +#define ACE_SECCNTCMD_WRITE_DATA (0x0400) +#define ACE_SECCNTCMD_ABORT (0x0600) + +#define ACE_VERSION (0x16) +#define ACE_VERSION_REVISION_MASK (0x00FF) +#define ACE_VERSION_MINOR_MASK (0x0F00) +#define ACE_VERSION_MAJOR_MASK (0xF000) + +#define ACE_CTRL (0x18) +#define ACE_CTRL_FORCELOCKREQ (0x0001) +#define ACE_CTRL_LOCKREQ (0x0002) +#define ACE_CTRL_FORCECFGADDR (0x0004) +#define ACE_CTRL_FORCECFGMODE (0x0008) +#define ACE_CTRL_CFGMODE (0x0010) +#define ACE_CTRL_CFGSTART (0x0020) +#define ACE_CTRL_CFGSEL (0x0040) +#define ACE_CTRL_CFGRESET (0x0080) +#define ACE_CTRL_DATABUFRDYIRQ (0x0100) +#define ACE_CTRL_ERRORIRQ (0x0200) +#define ACE_CTRL_CFGDONEIRQ (0x0400) +#define ACE_CTRL_RESETIRQ (0x0800) +#define ACE_CTRL_CFGPROG (0x1000) +#define ACE_CTRL_CFGADDR_MASK (0xe000) + +#define ACE_FATSTAT (0x1c) + +#define ACE_NUM_MINORS 16 +#define ACE_SECTOR_SIZE (512) +#define ACE_FIFO_SIZE (32) +#define ACE_BUF_PER_SECTOR (ACE_SECTOR_SIZE / ACE_FIFO_SIZE) + +#define ACE_BUS_WIDTH_8 0 +#define ACE_BUS_WIDTH_16 1 + +struct ace_reg_ops; + +struct ace_device { + /* driver state data */ + int id; + int media_change; + int users; + struct list_head list; + + /* finite state machine data */ + struct tasklet_struct fsm_tasklet; + uint fsm_task; /* Current activity (ACE_TASK_*) */ + uint fsm_state; /* Current state (ACE_FSM_STATE_*) */ + uint fsm_continue_flag; /* cleared to exit FSM mainloop */ + uint fsm_iter_num; + struct timer_list stall_timer; + + /* Transfer state/result, use for both id and block request */ + struct request *req; /* request being processed */ + void *data_ptr; /* pointer to I/O buffer */ + int data_count; /* number of buffers remaining */ + int data_result; /* Result of transfer; 0 := success */ + + int id_req_count; /* count of id requests */ + int id_result; + struct completion id_completion; /* used when id req finishes */ + int in_irq; + + /* Details of hardware device */ + resource_size_t physaddr; + void __iomem *baseaddr; + int irq; + int bus_width; /* 0 := 8 bit; 1 := 16 bit */ + struct ace_reg_ops *reg_ops; + int lock_count; + + /* Block device data structures */ + spinlock_t lock; + struct device *dev; + struct request_queue *queue; + struct gendisk *gd; + struct blk_mq_tag_set tag_set; + struct list_head rq_list; + + /* Inserted CF card parameters */ + u16 cf_id[ATA_ID_WORDS]; +}; + +static DEFINE_MUTEX(xsysace_mutex); +static int ace_major; + +/* --------------------------------------------------------------------- + * Low level register access + */ + +struct ace_reg_ops { + u16(*in) (struct ace_device * ace, int reg); + void (*out) (struct ace_device * ace, int reg, u16 val); + void (*datain) (struct ace_device * ace); + void (*dataout) (struct ace_device * ace); +}; + +/* 8 Bit bus width */ +static u16 ace_in_8(struct ace_device *ace, int reg) +{ + void __iomem *r = ace->baseaddr + reg; + return in_8(r) | (in_8(r + 1) << 8); +} + +static void ace_out_8(struct ace_device *ace, int reg, u16 val) +{ + void __iomem *r = ace->baseaddr + reg; + out_8(r, val); + out_8(r + 1, val >> 8); +} + +static void ace_datain_8(struct ace_device *ace) +{ + void __iomem *r = ace->baseaddr + 0x40; + u8 *dst = ace->data_ptr; + int i = ACE_FIFO_SIZE; + while (i--) + *dst++ = in_8(r++); + ace->data_ptr = dst; +} + +static void ace_dataout_8(struct ace_device *ace) +{ + void __iomem *r = ace->baseaddr + 0x40; + u8 *src = ace->data_ptr; + int i = ACE_FIFO_SIZE; + while (i--) + out_8(r++, *src++); + ace->data_ptr = src; +} + +static struct ace_reg_ops ace_reg_8_ops = { + .in = ace_in_8, + .out = ace_out_8, + .datain = ace_datain_8, + .dataout = ace_dataout_8, +}; + +/* 16 bit big endian bus attachment */ +static u16 ace_in_be16(struct ace_device *ace, int reg) +{ + return in_be16(ace->baseaddr + reg); +} + +static void ace_out_be16(struct ace_device *ace, int reg, u16 val) +{ + out_be16(ace->baseaddr + reg, val); +} + +static void ace_datain_be16(struct ace_device *ace) +{ + int i = ACE_FIFO_SIZE / 2; + u16 *dst = ace->data_ptr; + while (i--) + *dst++ = in_le16(ace->baseaddr + 0x40); + ace->data_ptr = dst; +} + +static void ace_dataout_be16(struct ace_device *ace) +{ + int i = ACE_FIFO_SIZE / 2; + u16 *src = ace->data_ptr; + while (i--) + out_le16(ace->baseaddr + 0x40, *src++); + ace->data_ptr = src; +} + +/* 16 bit little endian bus attachment */ +static u16 ace_in_le16(struct ace_device *ace, int reg) +{ + return in_le16(ace->baseaddr + reg); +} + +static void ace_out_le16(struct ace_device *ace, int reg, u16 val) +{ + out_le16(ace->baseaddr + reg, val); +} + +static void ace_datain_le16(struct ace_device *ace) +{ + int i = ACE_FIFO_SIZE / 2; + u16 *dst = ace->data_ptr; + while (i--) + *dst++ = in_be16(ace->baseaddr + 0x40); + ace->data_ptr = dst; +} + +static void ace_dataout_le16(struct ace_device *ace) +{ + int i = ACE_FIFO_SIZE / 2; + u16 *src = ace->data_ptr; + while (i--) + out_be16(ace->baseaddr + 0x40, *src++); + ace->data_ptr = src; +} + +static struct ace_reg_ops ace_reg_be16_ops = { + .in = ace_in_be16, + .out = ace_out_be16, + .datain = ace_datain_be16, + .dataout = ace_dataout_be16, +}; + +static struct ace_reg_ops ace_reg_le16_ops = { + .in = ace_in_le16, + .out = ace_out_le16, + .datain = ace_datain_le16, + .dataout = ace_dataout_le16, +}; + +static inline u16 ace_in(struct ace_device *ace, int reg) +{ + return ace->reg_ops->in(ace, reg); +} + +static inline u32 ace_in32(struct ace_device *ace, int reg) +{ + return ace_in(ace, reg) | (ace_in(ace, reg + 2) << 16); +} + +static inline void ace_out(struct ace_device *ace, int reg, u16 val) +{ + ace->reg_ops->out(ace, reg, val); +} + +static inline void ace_out32(struct ace_device *ace, int reg, u32 val) +{ + ace_out(ace, reg, val); + ace_out(ace, reg + 2, val >> 16); +} + +/* --------------------------------------------------------------------- + * Debug support functions + */ + +#if defined(DEBUG) +static void ace_dump_mem(void *base, int len) +{ + const char *ptr = base; + int i, j; + + for (i = 0; i < len; i += 16) { + printk(KERN_INFO "%.8x:", i); + for (j = 0; j < 16; j++) { + if (!(j % 4)) + printk(" "); + printk("%.2x", ptr[i + j]); + } + printk(" "); + for (j = 0; j < 16; j++) + printk("%c", isprint(ptr[i + j]) ? ptr[i + j] : '.'); + printk("\n"); + } +} +#else +static inline void ace_dump_mem(void *base, int len) +{ +} +#endif + +static void ace_dump_regs(struct ace_device *ace) +{ + dev_info(ace->dev, + " ctrl: %.8x seccnt/cmd: %.4x ver:%.4x\n" + " status:%.8x mpu_lba:%.8x busmode:%4x\n" + " error: %.8x cfg_lba:%.8x fatstat:%.4x\n", + ace_in32(ace, ACE_CTRL), + ace_in(ace, ACE_SECCNTCMD), + ace_in(ace, ACE_VERSION), + ace_in32(ace, ACE_STATUS), + ace_in32(ace, ACE_MPULBA), + ace_in(ace, ACE_BUSMODE), + ace_in32(ace, ACE_ERROR), + ace_in32(ace, ACE_CFGLBA), ace_in(ace, ACE_FATSTAT)); +} + +static void ace_fix_driveid(u16 *id) +{ +#if defined(__BIG_ENDIAN) + int i; + + /* All half words have wrong byte order; swap the bytes */ + for (i = 0; i < ATA_ID_WORDS; i++, id++) + *id = le16_to_cpu(*id); +#endif +} + +/* --------------------------------------------------------------------- + * Finite State Machine (FSM) implementation + */ + +/* FSM tasks; used to direct state transitions */ +#define ACE_TASK_IDLE 0 +#define ACE_TASK_IDENTIFY 1 +#define ACE_TASK_READ 2 +#define ACE_TASK_WRITE 3 +#define ACE_FSM_NUM_TASKS 4 + +/* FSM state definitions */ +#define ACE_FSM_STATE_IDLE 0 +#define ACE_FSM_STATE_REQ_LOCK 1 +#define ACE_FSM_STATE_WAIT_LOCK 2 +#define ACE_FSM_STATE_WAIT_CFREADY 3 +#define ACE_FSM_STATE_IDENTIFY_PREPARE 4 +#define ACE_FSM_STATE_IDENTIFY_TRANSFER 5 +#define ACE_FSM_STATE_IDENTIFY_COMPLETE 6 +#define ACE_FSM_STATE_REQ_PREPARE 7 +#define ACE_FSM_STATE_REQ_TRANSFER 8 +#define ACE_FSM_STATE_REQ_COMPLETE 9 +#define ACE_FSM_STATE_ERROR 10 +#define ACE_FSM_NUM_STATES 11 + +/* Set flag to exit FSM loop and reschedule tasklet */ +static inline void ace_fsm_yieldpoll(struct ace_device *ace) +{ + tasklet_schedule(&ace->fsm_tasklet); + ace->fsm_continue_flag = 0; +} + +static inline void ace_fsm_yield(struct ace_device *ace) +{ + dev_dbg(ace->dev, "%s()\n", __func__); + ace_fsm_yieldpoll(ace); +} + +/* Set flag to exit FSM loop and wait for IRQ to reschedule tasklet */ +static inline void ace_fsm_yieldirq(struct ace_device *ace) +{ + dev_dbg(ace->dev, "ace_fsm_yieldirq()\n"); + + if (ace->irq > 0) + ace->fsm_continue_flag = 0; + else + ace_fsm_yieldpoll(ace); +} + +static bool ace_has_next_request(struct request_queue *q) +{ + struct ace_device *ace = q->queuedata; + + return !list_empty(&ace->rq_list); +} + +/* Get the next read/write request; ending requests that we don't handle */ +static struct request *ace_get_next_request(struct request_queue *q) +{ + struct ace_device *ace = q->queuedata; + struct request *rq; + + rq = list_first_entry_or_null(&ace->rq_list, struct request, queuelist); + if (rq) { + list_del_init(&rq->queuelist); + blk_mq_start_request(rq); + } + + return NULL; +} + +static void ace_fsm_dostate(struct ace_device *ace) +{ + struct request *req; + u32 status; + u16 val; + int count; + +#if defined(DEBUG) + dev_dbg(ace->dev, "fsm_state=%i, id_req_count=%i\n", + ace->fsm_state, ace->id_req_count); +#endif + + /* Verify that there is actually a CF in the slot. If not, then + * bail out back to the idle state and wake up all the waiters */ + status = ace_in32(ace, ACE_STATUS); + if ((status & ACE_STATUS_CFDETECT) == 0) { + ace->fsm_state = ACE_FSM_STATE_IDLE; + ace->media_change = 1; + set_capacity(ace->gd, 0); + dev_info(ace->dev, "No CF in slot\n"); + + /* Drop all in-flight and pending requests */ + if (ace->req) { + blk_mq_end_request(ace->req, BLK_STS_IOERR); + ace->req = NULL; + } + while ((req = ace_get_next_request(ace->queue)) != NULL) + blk_mq_end_request(req, BLK_STS_IOERR); + + /* Drop back to IDLE state and notify waiters */ + ace->fsm_state = ACE_FSM_STATE_IDLE; + ace->id_result = -EIO; + while (ace->id_req_count) { + complete(&ace->id_completion); + ace->id_req_count--; + } + } + + switch (ace->fsm_state) { + case ACE_FSM_STATE_IDLE: + /* See if there is anything to do */ + if (ace->id_req_count || ace_has_next_request(ace->queue)) { + ace->fsm_iter_num++; + ace->fsm_state = ACE_FSM_STATE_REQ_LOCK; + mod_timer(&ace->stall_timer, jiffies + HZ); + if (!timer_pending(&ace->stall_timer)) + add_timer(&ace->stall_timer); + break; + } + del_timer(&ace->stall_timer); + ace->fsm_continue_flag = 0; + break; + + case ACE_FSM_STATE_REQ_LOCK: + if (ace_in(ace, ACE_STATUS) & ACE_STATUS_MPULOCK) { + /* Already have the lock, jump to next state */ + ace->fsm_state = ACE_FSM_STATE_WAIT_CFREADY; + break; + } + + /* Request the lock */ + val = ace_in(ace, ACE_CTRL); + ace_out(ace, ACE_CTRL, val | ACE_CTRL_LOCKREQ); + ace->fsm_state = ACE_FSM_STATE_WAIT_LOCK; + break; + + case ACE_FSM_STATE_WAIT_LOCK: + if (ace_in(ace, ACE_STATUS) & ACE_STATUS_MPULOCK) { + /* got the lock; move to next state */ + ace->fsm_state = ACE_FSM_STATE_WAIT_CFREADY; + break; + } + + /* wait a bit for the lock */ + ace_fsm_yield(ace); + break; + + case ACE_FSM_STATE_WAIT_CFREADY: + status = ace_in32(ace, ACE_STATUS); + if (!(status & ACE_STATUS_RDYFORCFCMD) || + (status & ACE_STATUS_CFBSY)) { + /* CF card isn't ready; it needs to be polled */ + ace_fsm_yield(ace); + break; + } + + /* Device is ready for command; determine what to do next */ + if (ace->id_req_count) + ace->fsm_state = ACE_FSM_STATE_IDENTIFY_PREPARE; + else + ace->fsm_state = ACE_FSM_STATE_REQ_PREPARE; + break; + + case ACE_FSM_STATE_IDENTIFY_PREPARE: + /* Send identify command */ + ace->fsm_task = ACE_TASK_IDENTIFY; + ace->data_ptr = ace->cf_id; + ace->data_count = ACE_BUF_PER_SECTOR; + ace_out(ace, ACE_SECCNTCMD, ACE_SECCNTCMD_IDENTIFY); + + /* As per datasheet, put config controller in reset */ + val = ace_in(ace, ACE_CTRL); + ace_out(ace, ACE_CTRL, val | ACE_CTRL_CFGRESET); + + /* irq handler takes over from this point; wait for the + * transfer to complete */ + ace->fsm_state = ACE_FSM_STATE_IDENTIFY_TRANSFER; + ace_fsm_yieldirq(ace); + break; + + case ACE_FSM_STATE_IDENTIFY_TRANSFER: + /* Check that the sysace is ready to receive data */ + status = ace_in32(ace, ACE_STATUS); + if (status & ACE_STATUS_CFBSY) { + dev_dbg(ace->dev, "CFBSY set; t=%i iter=%i dc=%i\n", + ace->fsm_task, ace->fsm_iter_num, + ace->data_count); + ace_fsm_yield(ace); + break; + } + if (!(status & ACE_STATUS_DATABUFRDY)) { + ace_fsm_yield(ace); + break; + } + + /* Transfer the next buffer */ + ace->reg_ops->datain(ace); + ace->data_count--; + + /* If there are still buffers to be transfers; jump out here */ + if (ace->data_count != 0) { + ace_fsm_yieldirq(ace); + break; + } + + /* transfer finished; kick state machine */ + dev_dbg(ace->dev, "identify finished\n"); + ace->fsm_state = ACE_FSM_STATE_IDENTIFY_COMPLETE; + break; + + case ACE_FSM_STATE_IDENTIFY_COMPLETE: + ace_fix_driveid(ace->cf_id); + ace_dump_mem(ace->cf_id, 512); /* Debug: Dump out disk ID */ + + if (ace->data_result) { + /* Error occurred, disable the disk */ + ace->media_change = 1; + set_capacity(ace->gd, 0); + dev_err(ace->dev, "error fetching CF id (%i)\n", + ace->data_result); + } else { + ace->media_change = 0; + + /* Record disk parameters */ + set_capacity(ace->gd, + ata_id_u32(ace->cf_id, ATA_ID_LBA_CAPACITY)); + dev_info(ace->dev, "capacity: %i sectors\n", + ata_id_u32(ace->cf_id, ATA_ID_LBA_CAPACITY)); + } + + /* We're done, drop to IDLE state and notify waiters */ + ace->fsm_state = ACE_FSM_STATE_IDLE; + ace->id_result = ace->data_result; + while (ace->id_req_count) { + complete(&ace->id_completion); + ace->id_req_count--; + } + break; + + case ACE_FSM_STATE_REQ_PREPARE: + req = ace_get_next_request(ace->queue); + if (!req) { + ace->fsm_state = ACE_FSM_STATE_IDLE; + break; + } + + /* Okay, it's a data request, set it up for transfer */ + dev_dbg(ace->dev, + "request: sec=%llx hcnt=%x, ccnt=%x, dir=%i\n", + (unsigned long long)blk_rq_pos(req), + blk_rq_sectors(req), blk_rq_cur_sectors(req), + rq_data_dir(req)); + + ace->req = req; + ace->data_ptr = bio_data(req->bio); + ace->data_count = blk_rq_cur_sectors(req) * ACE_BUF_PER_SECTOR; + ace_out32(ace, ACE_MPULBA, blk_rq_pos(req) & 0x0FFFFFFF); + + count = blk_rq_sectors(req); + if (rq_data_dir(req)) { + /* Kick off write request */ + dev_dbg(ace->dev, "write data\n"); + ace->fsm_task = ACE_TASK_WRITE; + ace_out(ace, ACE_SECCNTCMD, + count | ACE_SECCNTCMD_WRITE_DATA); + } else { + /* Kick off read request */ + dev_dbg(ace->dev, "read data\n"); + ace->fsm_task = ACE_TASK_READ; + ace_out(ace, ACE_SECCNTCMD, + count | ACE_SECCNTCMD_READ_DATA); + } + + /* As per datasheet, put config controller in reset */ + val = ace_in(ace, ACE_CTRL); + ace_out(ace, ACE_CTRL, val | ACE_CTRL_CFGRESET); + + /* Move to the transfer state. The systemace will raise + * an interrupt once there is something to do + */ + ace->fsm_state = ACE_FSM_STATE_REQ_TRANSFER; + if (ace->fsm_task == ACE_TASK_READ) + ace_fsm_yieldirq(ace); /* wait for data ready */ + break; + + case ACE_FSM_STATE_REQ_TRANSFER: + /* Check that the sysace is ready to receive data */ + status = ace_in32(ace, ACE_STATUS); + if (status & ACE_STATUS_CFBSY) { + dev_dbg(ace->dev, + "CFBSY set; t=%i iter=%i c=%i dc=%i irq=%i\n", + ace->fsm_task, ace->fsm_iter_num, + blk_rq_cur_sectors(ace->req) * 16, + ace->data_count, ace->in_irq); + ace_fsm_yield(ace); /* need to poll CFBSY bit */ + break; + } + if (!(status & ACE_STATUS_DATABUFRDY)) { + dev_dbg(ace->dev, + "DATABUF not set; t=%i iter=%i c=%i dc=%i irq=%i\n", + ace->fsm_task, ace->fsm_iter_num, + blk_rq_cur_sectors(ace->req) * 16, + ace->data_count, ace->in_irq); + ace_fsm_yieldirq(ace); + break; + } + + /* Transfer the next buffer */ + if (ace->fsm_task == ACE_TASK_WRITE) + ace->reg_ops->dataout(ace); + else + ace->reg_ops->datain(ace); + ace->data_count--; + + /* If there are still buffers to be transfers; jump out here */ + if (ace->data_count != 0) { + ace_fsm_yieldirq(ace); + break; + } + + /* bio finished; is there another one? */ + if (blk_update_request(ace->req, BLK_STS_OK, + blk_rq_cur_bytes(ace->req))) { + /* dev_dbg(ace->dev, "next block; h=%u c=%u\n", + * blk_rq_sectors(ace->req), + * blk_rq_cur_sectors(ace->req)); + */ + ace->data_ptr = bio_data(ace->req->bio); + ace->data_count = blk_rq_cur_sectors(ace->req) * 16; + ace_fsm_yieldirq(ace); + break; + } + + ace->fsm_state = ACE_FSM_STATE_REQ_COMPLETE; + break; + + case ACE_FSM_STATE_REQ_COMPLETE: + ace->req = NULL; + + /* Finished request; go to idle state */ + ace->fsm_state = ACE_FSM_STATE_IDLE; + break; + + default: + ace->fsm_state = ACE_FSM_STATE_IDLE; + break; + } +} + +static void ace_fsm_tasklet(unsigned long data) +{ + struct ace_device *ace = (void *)data; + unsigned long flags; + + spin_lock_irqsave(&ace->lock, flags); + + /* Loop over state machine until told to stop */ + ace->fsm_continue_flag = 1; + while (ace->fsm_continue_flag) + ace_fsm_dostate(ace); + + spin_unlock_irqrestore(&ace->lock, flags); +} + +static void ace_stall_timer(struct timer_list *t) +{ + struct ace_device *ace = from_timer(ace, t, stall_timer); + unsigned long flags; + + dev_warn(ace->dev, + "kicking stalled fsm; state=%i task=%i iter=%i dc=%i\n", + ace->fsm_state, ace->fsm_task, ace->fsm_iter_num, + ace->data_count); + spin_lock_irqsave(&ace->lock, flags); + + /* Rearm the stall timer *before* entering FSM (which may then + * delete the timer) */ + mod_timer(&ace->stall_timer, jiffies + HZ); + + /* Loop over state machine until told to stop */ + ace->fsm_continue_flag = 1; + while (ace->fsm_continue_flag) + ace_fsm_dostate(ace); + + spin_unlock_irqrestore(&ace->lock, flags); +} + +/* --------------------------------------------------------------------- + * Interrupt handling routines + */ +static int ace_interrupt_checkstate(struct ace_device *ace) +{ + u32 sreg = ace_in32(ace, ACE_STATUS); + u16 creg = ace_in(ace, ACE_CTRL); + + /* Check for error occurrence */ + if ((sreg & (ACE_STATUS_CFGERROR | ACE_STATUS_CFCERROR)) && + (creg & ACE_CTRL_ERRORIRQ)) { + dev_err(ace->dev, "transfer failure\n"); + ace_dump_regs(ace); + return -EIO; + } + + return 0; +} + +static irqreturn_t ace_interrupt(int irq, void *dev_id) +{ + u16 creg; + struct ace_device *ace = dev_id; + + /* be safe and get the lock */ + spin_lock(&ace->lock); + ace->in_irq = 1; + + /* clear the interrupt */ + creg = ace_in(ace, ACE_CTRL); + ace_out(ace, ACE_CTRL, creg | ACE_CTRL_RESETIRQ); + ace_out(ace, ACE_CTRL, creg); + + /* check for IO failures */ + if (ace_interrupt_checkstate(ace)) + ace->data_result = -EIO; + + if (ace->fsm_task == 0) { + dev_err(ace->dev, + "spurious irq; stat=%.8x ctrl=%.8x cmd=%.4x\n", + ace_in32(ace, ACE_STATUS), ace_in32(ace, ACE_CTRL), + ace_in(ace, ACE_SECCNTCMD)); + dev_err(ace->dev, "fsm_task=%i fsm_state=%i data_count=%i\n", + ace->fsm_task, ace->fsm_state, ace->data_count); + } + + /* Loop over state machine until told to stop */ + ace->fsm_continue_flag = 1; + while (ace->fsm_continue_flag) + ace_fsm_dostate(ace); + + /* done with interrupt; drop the lock */ + ace->in_irq = 0; + spin_unlock(&ace->lock); + + return IRQ_HANDLED; +} + +/* --------------------------------------------------------------------- + * Block ops + */ +static blk_status_t ace_queue_rq(struct blk_mq_hw_ctx *hctx, + const struct blk_mq_queue_data *bd) +{ + struct ace_device *ace = hctx->queue->queuedata; + struct request *req = bd->rq; + + if (blk_rq_is_passthrough(req)) { + blk_mq_start_request(req); + return BLK_STS_IOERR; + } + + spin_lock_irq(&ace->lock); + list_add_tail(&req->queuelist, &ace->rq_list); + spin_unlock_irq(&ace->lock); + + tasklet_schedule(&ace->fsm_tasklet); + return BLK_STS_OK; +} + +static unsigned int ace_check_events(struct gendisk *gd, unsigned int clearing) +{ + struct ace_device *ace = gd->private_data; + dev_dbg(ace->dev, "ace_check_events(): %i\n", ace->media_change); + + return ace->media_change ? DISK_EVENT_MEDIA_CHANGE : 0; +} + +static void ace_media_changed(struct ace_device *ace) +{ + unsigned long flags; + + dev_dbg(ace->dev, "requesting cf id and scheduling tasklet\n"); + + spin_lock_irqsave(&ace->lock, flags); + ace->id_req_count++; + spin_unlock_irqrestore(&ace->lock, flags); + + tasklet_schedule(&ace->fsm_tasklet); + wait_for_completion(&ace->id_completion); + + dev_dbg(ace->dev, "revalidate complete\n"); +} + +static int ace_open(struct block_device *bdev, fmode_t mode) +{ + struct ace_device *ace = bdev->bd_disk->private_data; + unsigned long flags; + + dev_dbg(ace->dev, "ace_open() users=%i\n", ace->users + 1); + + mutex_lock(&xsysace_mutex); + spin_lock_irqsave(&ace->lock, flags); + ace->users++; + spin_unlock_irqrestore(&ace->lock, flags); + + if (bdev_check_media_change(bdev) && ace->media_change) + ace_media_changed(ace); + mutex_unlock(&xsysace_mutex); + + return 0; +} + +static void ace_release(struct gendisk *disk, fmode_t mode) +{ + struct ace_device *ace = disk->private_data; + unsigned long flags; + u16 val; + + dev_dbg(ace->dev, "ace_release() users=%i\n", ace->users - 1); + + mutex_lock(&xsysace_mutex); + spin_lock_irqsave(&ace->lock, flags); + ace->users--; + if (ace->users == 0) { + val = ace_in(ace, ACE_CTRL); + ace_out(ace, ACE_CTRL, val & ~ACE_CTRL_LOCKREQ); + } + spin_unlock_irqrestore(&ace->lock, flags); + mutex_unlock(&xsysace_mutex); +} + +static int ace_getgeo(struct block_device *bdev, struct hd_geometry *geo) +{ + struct ace_device *ace = bdev->bd_disk->private_data; + u16 *cf_id = ace->cf_id; + + dev_dbg(ace->dev, "ace_getgeo()\n"); + + geo->heads = cf_id[ATA_ID_HEADS]; + geo->sectors = cf_id[ATA_ID_SECTORS]; + geo->cylinders = cf_id[ATA_ID_CYLS]; + + return 0; +} + +static const struct block_device_operations ace_fops = { + .owner = THIS_MODULE, + .open = ace_open, + .release = ace_release, + .check_events = ace_check_events, + .getgeo = ace_getgeo, +}; + +static const struct blk_mq_ops ace_mq_ops = { + .queue_rq = ace_queue_rq, +}; + +/* -------------------------------------------------------------------- + * SystemACE device setup/teardown code + */ +static int ace_setup(struct ace_device *ace) +{ + u16 version; + u16 val; + int rc; + + dev_dbg(ace->dev, "ace_setup(ace=0x%p)\n", ace); + dev_dbg(ace->dev, "physaddr=0x%llx irq=%i\n", + (unsigned long long)ace->physaddr, ace->irq); + + spin_lock_init(&ace->lock); + init_completion(&ace->id_completion); + INIT_LIST_HEAD(&ace->rq_list); + + /* + * Map the device + */ + ace->baseaddr = ioremap(ace->physaddr, 0x80); + if (!ace->baseaddr) + goto err_ioremap; + + /* + * Initialize the state machine tasklet and stall timer + */ + tasklet_init(&ace->fsm_tasklet, ace_fsm_tasklet, (unsigned long)ace); + timer_setup(&ace->stall_timer, ace_stall_timer, 0); + + /* + * Initialize the request queue + */ + ace->queue = blk_mq_init_sq_queue(&ace->tag_set, &ace_mq_ops, 2, + BLK_MQ_F_SHOULD_MERGE); + if (IS_ERR(ace->queue)) { + rc = PTR_ERR(ace->queue); + ace->queue = NULL; + goto err_blk_initq; + } + ace->queue->queuedata = ace; + + blk_queue_logical_block_size(ace->queue, 512); + blk_queue_bounce_limit(ace->queue, BLK_BOUNCE_HIGH); + + /* + * Allocate and initialize GD structure + */ + ace->gd = alloc_disk(ACE_NUM_MINORS); + if (!ace->gd) + goto err_alloc_disk; + + ace->gd->major = ace_major; + ace->gd->first_minor = ace->id * ACE_NUM_MINORS; + ace->gd->fops = &ace_fops; + ace->gd->events = DISK_EVENT_MEDIA_CHANGE; + ace->gd->queue = ace->queue; + ace->gd->private_data = ace; + snprintf(ace->gd->disk_name, 32, "xs%c", ace->id + 'a'); + + /* set bus width */ + if (ace->bus_width == ACE_BUS_WIDTH_16) { + /* 0x0101 should work regardless of endianess */ + ace_out_le16(ace, ACE_BUSMODE, 0x0101); + + /* read it back to determine endianess */ + if (ace_in_le16(ace, ACE_BUSMODE) == 0x0001) + ace->reg_ops = &ace_reg_le16_ops; + else + ace->reg_ops = &ace_reg_be16_ops; + } else { + ace_out_8(ace, ACE_BUSMODE, 0x00); + ace->reg_ops = &ace_reg_8_ops; + } + + /* Make sure version register is sane */ + version = ace_in(ace, ACE_VERSION); + if ((version == 0) || (version == 0xFFFF)) + goto err_read; + + /* Put sysace in a sane state by clearing most control reg bits */ + ace_out(ace, ACE_CTRL, ACE_CTRL_FORCECFGMODE | + ACE_CTRL_DATABUFRDYIRQ | ACE_CTRL_ERRORIRQ); + + /* Now we can hook up the irq handler */ + if (ace->irq > 0) { + rc = request_irq(ace->irq, ace_interrupt, 0, "systemace", ace); + if (rc) { + /* Failure - fall back to polled mode */ + dev_err(ace->dev, "request_irq failed\n"); + ace->irq = rc; + } + } + + /* Enable interrupts */ + val = ace_in(ace, ACE_CTRL); + val |= ACE_CTRL_DATABUFRDYIRQ | ACE_CTRL_ERRORIRQ; + ace_out(ace, ACE_CTRL, val); + + /* Print the identification */ + dev_info(ace->dev, "Xilinx SystemACE revision %i.%i.%i\n", + (version >> 12) & 0xf, (version >> 8) & 0x0f, version & 0xff); + dev_dbg(ace->dev, "physaddr 0x%llx, mapped to 0x%p, irq=%i\n", + (unsigned long long) ace->physaddr, ace->baseaddr, ace->irq); + + ace->media_change = 1; + ace_media_changed(ace); + + /* Make the sysace device 'live' */ + add_disk(ace->gd); + + return 0; + +err_read: + /* prevent double queue cleanup */ + ace->gd->queue = NULL; + put_disk(ace->gd); +err_alloc_disk: + blk_cleanup_queue(ace->queue); + blk_mq_free_tag_set(&ace->tag_set); +err_blk_initq: + iounmap(ace->baseaddr); +err_ioremap: + dev_info(ace->dev, "xsysace: error initializing device at 0x%llx\n", + (unsigned long long) ace->physaddr); + return -ENOMEM; +} + +static void ace_teardown(struct ace_device *ace) +{ + if (ace->gd) { + del_gendisk(ace->gd); + put_disk(ace->gd); + } + + if (ace->queue) { + blk_cleanup_queue(ace->queue); + blk_mq_free_tag_set(&ace->tag_set); + } + + tasklet_kill(&ace->fsm_tasklet); + + if (ace->irq > 0) + free_irq(ace->irq, ace); + + iounmap(ace->baseaddr); +} + +static int ace_alloc(struct device *dev, int id, resource_size_t physaddr, + int irq, int bus_width) +{ + struct ace_device *ace; + int rc; + dev_dbg(dev, "ace_alloc(%p)\n", dev); + + /* Allocate and initialize the ace device structure */ + ace = kzalloc(sizeof(struct ace_device), GFP_KERNEL); + if (!ace) { + rc = -ENOMEM; + goto err_alloc; + } + + ace->dev = dev; + ace->id = id; + ace->physaddr = physaddr; + ace->irq = irq; + ace->bus_width = bus_width; + + /* Call the setup code */ + rc = ace_setup(ace); + if (rc) + goto err_setup; + + dev_set_drvdata(dev, ace); + return 0; + +err_setup: + dev_set_drvdata(dev, NULL); + kfree(ace); +err_alloc: + dev_err(dev, "could not initialize device, err=%i\n", rc); + return rc; +} + +static void ace_free(struct device *dev) +{ + struct ace_device *ace = dev_get_drvdata(dev); + dev_dbg(dev, "ace_free(%p)\n", dev); + + if (ace) { + ace_teardown(ace); + dev_set_drvdata(dev, NULL); + kfree(ace); + } +} + +/* --------------------------------------------------------------------- + * Platform Bus Support + */ + +static int ace_probe(struct platform_device *dev) +{ + int bus_width = ACE_BUS_WIDTH_16; /* FIXME: should not be hard coded */ + resource_size_t physaddr; + struct resource *res; + u32 id = dev->id; + int irq; + int i; + + dev_dbg(&dev->dev, "ace_probe(%p)\n", dev); + + /* device id and bus width */ + if (of_property_read_u32(dev->dev.of_node, "port-number", &id)) + id = 0; + if (of_find_property(dev->dev.of_node, "8-bit", NULL)) + bus_width = ACE_BUS_WIDTH_8; + + res = platform_get_resource(dev, IORESOURCE_MEM, 0); + if (!res) + return -EINVAL; + + physaddr = res->start; + if (!physaddr) + return -ENODEV; + + irq = platform_get_irq_optional(dev, 0); + + /* Call the bus-independent setup code */ + return ace_alloc(&dev->dev, id, physaddr, irq, bus_width); +} + +/* + * Platform bus remove() method + */ +static int ace_remove(struct platform_device *dev) +{ + ace_free(&dev->dev); + return 0; +} + +#if defined(CONFIG_OF) +/* Match table for of_platform binding */ +static const struct of_device_id ace_of_match[] = { + { .compatible = "xlnx,opb-sysace-1.00.b", }, + { .compatible = "xlnx,opb-sysace-1.00.c", }, + { .compatible = "xlnx,xps-sysace-1.00.a", }, + { .compatible = "xlnx,sysace", }, + {}, +}; +MODULE_DEVICE_TABLE(of, ace_of_match); +#else /* CONFIG_OF */ +#define ace_of_match NULL +#endif /* CONFIG_OF */ + +static struct platform_driver ace_platform_driver = { + .probe = ace_probe, + .remove = ace_remove, + .driver = { + .name = "xsysace", + .of_match_table = ace_of_match, + }, +}; + +/* --------------------------------------------------------------------- + * Module init/exit routines + */ +static int __init ace_init(void) +{ + int rc; + + ace_major = register_blkdev(ace_major, "xsysace"); + if (ace_major <= 0) { + rc = -ENOMEM; + goto err_blk; + } + + rc = platform_driver_register(&ace_platform_driver); + if (rc) + goto err_plat; + + pr_info("Xilinx SystemACE device driver, major=%i\n", ace_major); + return 0; + +err_plat: + unregister_blkdev(ace_major, "xsysace"); +err_blk: + printk(KERN_ERR "xsysace: registration failed; err=%i\n", rc); + return rc; +} +module_init(ace_init); + +static void __exit ace_exit(void) +{ + pr_debug("Unregistering Xilinx SystemACE driver\n"); + platform_driver_unregister(&ace_platform_driver); + unregister_blkdev(ace_major, "xsysace"); +} +module_exit(ace_exit); diff --git a/drivers/extcon/extcon-arizona.c b/drivers/extcon/extcon-arizona.c new file mode 100644 index 0000000000000..aae82db542a5e --- /dev/null +++ b/drivers/extcon/extcon-arizona.c @@ -0,0 +1,1816 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * extcon-arizona.c - Extcon driver Wolfson Arizona devices + * + * Copyright (C) 2012-2014 Wolfson Microelectronics plc + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include + +#define ARIZONA_MAX_MICD_RANGE 8 + +#define ARIZONA_MICD_CLAMP_MODE_JDL 0x4 +#define ARIZONA_MICD_CLAMP_MODE_JDH 0x5 +#define ARIZONA_MICD_CLAMP_MODE_JDL_GP5H 0x9 +#define ARIZONA_MICD_CLAMP_MODE_JDH_GP5H 0xb + +#define ARIZONA_TST_CAP_DEFAULT 0x3 +#define ARIZONA_TST_CAP_CLAMP 0x1 + +#define ARIZONA_HPDET_MAX 10000 + +#define HPDET_DEBOUNCE 500 +#define DEFAULT_MICD_TIMEOUT 2000 + +#define ARIZONA_HPDET_WAIT_COUNT 15 +#define ARIZONA_HPDET_WAIT_DELAY_MS 20 + +#define QUICK_HEADPHONE_MAX_OHM 3 +#define MICROPHONE_MIN_OHM 1257 +#define MICROPHONE_MAX_OHM 30000 + +#define MICD_DBTIME_TWO_READINGS 2 +#define MICD_DBTIME_FOUR_READINGS 4 + +#define MICD_LVL_1_TO_7 (ARIZONA_MICD_LVL_1 | ARIZONA_MICD_LVL_2 | \ + ARIZONA_MICD_LVL_3 | ARIZONA_MICD_LVL_4 | \ + ARIZONA_MICD_LVL_5 | ARIZONA_MICD_LVL_6 | \ + ARIZONA_MICD_LVL_7) + +#define MICD_LVL_0_TO_7 (ARIZONA_MICD_LVL_0 | MICD_LVL_1_TO_7) + +#define MICD_LVL_0_TO_8 (MICD_LVL_0_TO_7 | ARIZONA_MICD_LVL_8) + +struct arizona_extcon_info { + struct device *dev; + struct arizona *arizona; + struct mutex lock; + struct regulator *micvdd; + struct input_dev *input; + + u16 last_jackdet; + + int micd_mode; + const struct arizona_micd_config *micd_modes; + int micd_num_modes; + + const struct arizona_micd_range *micd_ranges; + int num_micd_ranges; + + bool micd_reva; + bool micd_clamp; + + struct delayed_work hpdet_work; + struct delayed_work micd_detect_work; + struct delayed_work micd_timeout_work; + + bool hpdet_active; + bool hpdet_done; + bool hpdet_retried; + + int num_hpdet_res; + unsigned int hpdet_res[3]; + + bool mic; + bool detecting; + int jack_flips; + + int hpdet_ip_version; + + struct extcon_dev *edev; + + struct gpio_desc *micd_pol_gpio; +}; + +static const struct arizona_micd_config micd_default_modes[] = { + { ARIZONA_ACCDET_SRC, 1, 0 }, + { 0, 2, 1 }, +}; + +static const struct arizona_micd_range micd_default_ranges[] = { + { .max = 11, .key = BTN_0 }, + { .max = 28, .key = BTN_1 }, + { .max = 54, .key = BTN_2 }, + { .max = 100, .key = BTN_3 }, + { .max = 186, .key = BTN_4 }, + { .max = 430, .key = BTN_5 }, +}; + +/* The number of levels in arizona_micd_levels valid for button thresholds */ +#define ARIZONA_NUM_MICD_BUTTON_LEVELS 64 + +static const int arizona_micd_levels[] = { + 3, 6, 8, 11, 13, 16, 18, 21, 23, 26, 28, 31, 34, 36, 39, 41, 44, 46, + 49, 52, 54, 57, 60, 62, 65, 67, 70, 73, 75, 78, 81, 83, 89, 94, 100, + 105, 111, 116, 122, 127, 139, 150, 161, 173, 186, 196, 209, 220, 245, + 270, 295, 321, 348, 375, 402, 430, 489, 550, 614, 681, 752, 903, 1071, + 1257, 30000, +}; + +static const unsigned int arizona_cable[] = { + EXTCON_MECHANICAL, + EXTCON_JACK_MICROPHONE, + EXTCON_JACK_HEADPHONE, + EXTCON_JACK_LINE_OUT, + EXTCON_NONE, +}; + +static void arizona_start_hpdet_acc_id(struct arizona_extcon_info *info); + +static void arizona_extcon_hp_clamp(struct arizona_extcon_info *info, + bool clamp) +{ + struct arizona *arizona = info->arizona; + unsigned int mask = 0, val = 0; + unsigned int cap_sel = 0; + int ret; + + switch (arizona->type) { + case WM8998: + case WM1814: + mask = 0; + break; + case WM5110: + case WM8280: + mask = ARIZONA_HP1L_SHRTO | ARIZONA_HP1L_FLWR | + ARIZONA_HP1L_SHRTI; + if (clamp) { + val = ARIZONA_HP1L_SHRTO; + cap_sel = ARIZONA_TST_CAP_CLAMP; + } else { + val = ARIZONA_HP1L_FLWR | ARIZONA_HP1L_SHRTI; + cap_sel = ARIZONA_TST_CAP_DEFAULT; + } + + ret = regmap_update_bits(arizona->regmap, + ARIZONA_HP_TEST_CTRL_1, + ARIZONA_HP1_TST_CAP_SEL_MASK, + cap_sel); + if (ret != 0) + dev_warn(arizona->dev, + "Failed to set TST_CAP_SEL: %d\n", ret); + break; + default: + mask = ARIZONA_RMV_SHRT_HP1L; + if (clamp) + val = ARIZONA_RMV_SHRT_HP1L; + break; + } + + snd_soc_dapm_mutex_lock(arizona->dapm); + + arizona->hpdet_clamp = clamp; + + /* Keep the HP output stages disabled while doing the clamp */ + if (clamp) { + ret = regmap_update_bits(arizona->regmap, + ARIZONA_OUTPUT_ENABLES_1, + ARIZONA_OUT1L_ENA | + ARIZONA_OUT1R_ENA, 0); + if (ret != 0) + dev_warn(arizona->dev, + "Failed to disable headphone outputs: %d\n", + ret); + } + + if (mask) { + ret = regmap_update_bits(arizona->regmap, ARIZONA_HP_CTRL_1L, + mask, val); + if (ret != 0) + dev_warn(arizona->dev, "Failed to do clamp: %d\n", + ret); + + ret = regmap_update_bits(arizona->regmap, ARIZONA_HP_CTRL_1R, + mask, val); + if (ret != 0) + dev_warn(arizona->dev, "Failed to do clamp: %d\n", + ret); + } + + /* Restore the desired state while not doing the clamp */ + if (!clamp) { + ret = regmap_update_bits(arizona->regmap, + ARIZONA_OUTPUT_ENABLES_1, + ARIZONA_OUT1L_ENA | + ARIZONA_OUT1R_ENA, arizona->hp_ena); + if (ret != 0) + dev_warn(arizona->dev, + "Failed to restore headphone outputs: %d\n", + ret); + } + + snd_soc_dapm_mutex_unlock(arizona->dapm); +} + +static void arizona_extcon_set_mode(struct arizona_extcon_info *info, int mode) +{ + struct arizona *arizona = info->arizona; + + mode %= info->micd_num_modes; + + gpiod_set_value_cansleep(info->micd_pol_gpio, + info->micd_modes[mode].gpio); + + regmap_update_bits(arizona->regmap, ARIZONA_MIC_DETECT_1, + ARIZONA_MICD_BIAS_SRC_MASK, + info->micd_modes[mode].bias << + ARIZONA_MICD_BIAS_SRC_SHIFT); + regmap_update_bits(arizona->regmap, ARIZONA_ACCESSORY_DETECT_MODE_1, + ARIZONA_ACCDET_SRC, info->micd_modes[mode].src); + + info->micd_mode = mode; + + dev_dbg(arizona->dev, "Set jack polarity to %d\n", mode); +} + +static const char *arizona_extcon_get_micbias(struct arizona_extcon_info *info) +{ + switch (info->micd_modes[0].bias) { + case 1: + return "MICBIAS1"; + case 2: + return "MICBIAS2"; + case 3: + return "MICBIAS3"; + default: + return "MICVDD"; + } +} + +static void arizona_extcon_pulse_micbias(struct arizona_extcon_info *info) +{ + struct arizona *arizona = info->arizona; + const char *widget = arizona_extcon_get_micbias(info); + struct snd_soc_dapm_context *dapm = arizona->dapm; + struct snd_soc_component *component = snd_soc_dapm_to_component(dapm); + int ret; + + ret = snd_soc_component_force_enable_pin(component, widget); + if (ret != 0) + dev_warn(arizona->dev, "Failed to enable %s: %d\n", + widget, ret); + + snd_soc_dapm_sync(dapm); + + if (!arizona->pdata.micd_force_micbias) { + ret = snd_soc_component_disable_pin(component, widget); + if (ret != 0) + dev_warn(arizona->dev, "Failed to disable %s: %d\n", + widget, ret); + + snd_soc_dapm_sync(dapm); + } +} + +static void arizona_start_mic(struct arizona_extcon_info *info) +{ + struct arizona *arizona = info->arizona; + bool change; + int ret; + unsigned int mode; + + /* Microphone detection can't use idle mode */ + pm_runtime_get(info->dev); + + if (info->detecting) { + ret = regulator_allow_bypass(info->micvdd, false); + if (ret != 0) { + dev_err(arizona->dev, + "Failed to regulate MICVDD: %d\n", + ret); + } + } + + ret = regulator_enable(info->micvdd); + if (ret != 0) { + dev_err(arizona->dev, "Failed to enable MICVDD: %d\n", + ret); + } + + if (info->micd_reva) { + const struct reg_sequence reva[] = { + { 0x80, 0x3 }, + { 0x294, 0x0 }, + { 0x80, 0x0 }, + }; + + regmap_multi_reg_write(arizona->regmap, reva, ARRAY_SIZE(reva)); + } + + if (info->detecting && arizona->pdata.micd_software_compare) + mode = ARIZONA_ACCDET_MODE_ADC; + else + mode = ARIZONA_ACCDET_MODE_MIC; + + regmap_update_bits(arizona->regmap, + ARIZONA_ACCESSORY_DETECT_MODE_1, + ARIZONA_ACCDET_MODE_MASK, mode); + + arizona_extcon_pulse_micbias(info); + + ret = regmap_update_bits_check(arizona->regmap, ARIZONA_MIC_DETECT_1, + ARIZONA_MICD_ENA, ARIZONA_MICD_ENA, + &change); + if (ret < 0) { + dev_err(arizona->dev, "Failed to enable micd: %d\n", ret); + } else if (!change) { + regulator_disable(info->micvdd); + pm_runtime_put_autosuspend(info->dev); + } +} + +static void arizona_stop_mic(struct arizona_extcon_info *info) +{ + struct arizona *arizona = info->arizona; + const char *widget = arizona_extcon_get_micbias(info); + struct snd_soc_dapm_context *dapm = arizona->dapm; + struct snd_soc_component *component = snd_soc_dapm_to_component(dapm); + bool change = false; + int ret; + + ret = regmap_update_bits_check(arizona->regmap, ARIZONA_MIC_DETECT_1, + ARIZONA_MICD_ENA, 0, + &change); + if (ret < 0) + dev_err(arizona->dev, "Failed to disable micd: %d\n", ret); + + ret = snd_soc_component_disable_pin(component, widget); + if (ret != 0) + dev_warn(arizona->dev, + "Failed to disable %s: %d\n", + widget, ret); + + snd_soc_dapm_sync(dapm); + + if (info->micd_reva) { + const struct reg_sequence reva[] = { + { 0x80, 0x3 }, + { 0x294, 0x2 }, + { 0x80, 0x0 }, + }; + + regmap_multi_reg_write(arizona->regmap, reva, ARRAY_SIZE(reva)); + } + + ret = regulator_allow_bypass(info->micvdd, true); + if (ret != 0) { + dev_err(arizona->dev, "Failed to bypass MICVDD: %d\n", + ret); + } + + if (change) { + regulator_disable(info->micvdd); + pm_runtime_mark_last_busy(info->dev); + pm_runtime_put_autosuspend(info->dev); + } +} + +static struct { + unsigned int threshold; + unsigned int factor_a; + unsigned int factor_b; +} arizona_hpdet_b_ranges[] = { + { 100, 5528, 362464 }, + { 169, 11084, 6186851 }, + { 169, 11065, 65460395 }, +}; + +#define ARIZONA_HPDET_B_RANGE_MAX 0x3fb + +static struct { + int min; + int max; +} arizona_hpdet_c_ranges[] = { + { 0, 30 }, + { 8, 100 }, + { 100, 1000 }, + { 1000, 10000 }, +}; + +static int arizona_hpdet_read(struct arizona_extcon_info *info) +{ + struct arizona *arizona = info->arizona; + unsigned int val, range; + int ret; + + ret = regmap_read(arizona->regmap, ARIZONA_HEADPHONE_DETECT_2, &val); + if (ret != 0) { + dev_err(arizona->dev, "Failed to read HPDET status: %d\n", + ret); + return ret; + } + + switch (info->hpdet_ip_version) { + case 0: + if (!(val & ARIZONA_HP_DONE)) { + dev_err(arizona->dev, "HPDET did not complete: %x\n", + val); + return -EAGAIN; + } + + val &= ARIZONA_HP_LVL_MASK; + break; + + case 1: + if (!(val & ARIZONA_HP_DONE_B)) { + dev_err(arizona->dev, "HPDET did not complete: %x\n", + val); + return -EAGAIN; + } + + ret = regmap_read(arizona->regmap, ARIZONA_HP_DACVAL, &val); + if (ret != 0) { + dev_err(arizona->dev, "Failed to read HP value: %d\n", + ret); + return -EAGAIN; + } + + regmap_read(arizona->regmap, ARIZONA_HEADPHONE_DETECT_1, + &range); + range = (range & ARIZONA_HP_IMPEDANCE_RANGE_MASK) + >> ARIZONA_HP_IMPEDANCE_RANGE_SHIFT; + + if (range < ARRAY_SIZE(arizona_hpdet_b_ranges) - 1 && + (val < arizona_hpdet_b_ranges[range].threshold || + val >= ARIZONA_HPDET_B_RANGE_MAX)) { + range++; + dev_dbg(arizona->dev, "Moving to HPDET range %d\n", + range); + regmap_update_bits(arizona->regmap, + ARIZONA_HEADPHONE_DETECT_1, + ARIZONA_HP_IMPEDANCE_RANGE_MASK, + range << + ARIZONA_HP_IMPEDANCE_RANGE_SHIFT); + return -EAGAIN; + } + + /* If we go out of range report top of range */ + if (val < arizona_hpdet_b_ranges[range].threshold || + val >= ARIZONA_HPDET_B_RANGE_MAX) { + dev_dbg(arizona->dev, "Measurement out of range\n"); + return ARIZONA_HPDET_MAX; + } + + dev_dbg(arizona->dev, "HPDET read %d in range %d\n", + val, range); + + val = arizona_hpdet_b_ranges[range].factor_b + / ((val * 100) - + arizona_hpdet_b_ranges[range].factor_a); + break; + + case 2: + if (!(val & ARIZONA_HP_DONE_B)) { + dev_err(arizona->dev, "HPDET did not complete: %x\n", + val); + return -EAGAIN; + } + + val &= ARIZONA_HP_LVL_B_MASK; + /* Convert to ohms, the value is in 0.5 ohm increments */ + val /= 2; + + regmap_read(arizona->regmap, ARIZONA_HEADPHONE_DETECT_1, + &range); + range = (range & ARIZONA_HP_IMPEDANCE_RANGE_MASK) + >> ARIZONA_HP_IMPEDANCE_RANGE_SHIFT; + + /* Skip up a range, or report? */ + if (range < ARRAY_SIZE(arizona_hpdet_c_ranges) - 1 && + (val >= arizona_hpdet_c_ranges[range].max)) { + range++; + dev_dbg(arizona->dev, "Moving to HPDET range %d-%d\n", + arizona_hpdet_c_ranges[range].min, + arizona_hpdet_c_ranges[range].max); + regmap_update_bits(arizona->regmap, + ARIZONA_HEADPHONE_DETECT_1, + ARIZONA_HP_IMPEDANCE_RANGE_MASK, + range << + ARIZONA_HP_IMPEDANCE_RANGE_SHIFT); + return -EAGAIN; + } + + if (range && (val < arizona_hpdet_c_ranges[range].min)) { + dev_dbg(arizona->dev, "Reporting range boundary %d\n", + arizona_hpdet_c_ranges[range].min); + val = arizona_hpdet_c_ranges[range].min; + } + break; + + default: + dev_warn(arizona->dev, "Unknown HPDET IP revision %d\n", + info->hpdet_ip_version); + return -EINVAL; + } + + dev_dbg(arizona->dev, "HP impedance %d ohms\n", val); + return val; +} + +static int arizona_hpdet_do_id(struct arizona_extcon_info *info, int *reading, + bool *mic) +{ + struct arizona *arizona = info->arizona; + int id_gpio = arizona->pdata.hpdet_id_gpio; + + if (!arizona->pdata.hpdet_acc_id) + return 0; + + /* + * If we're using HPDET for accessory identification we need + * to take multiple measurements, step through them in sequence. + */ + info->hpdet_res[info->num_hpdet_res++] = *reading; + + /* Only check the mic directly if we didn't already ID it */ + if (id_gpio && info->num_hpdet_res == 1) { + dev_dbg(arizona->dev, "Measuring mic\n"); + + regmap_update_bits(arizona->regmap, + ARIZONA_ACCESSORY_DETECT_MODE_1, + ARIZONA_ACCDET_MODE_MASK | + ARIZONA_ACCDET_SRC, + ARIZONA_ACCDET_MODE_HPR | + info->micd_modes[0].src); + + gpio_set_value_cansleep(id_gpio, 1); + + regmap_update_bits(arizona->regmap, ARIZONA_HEADPHONE_DETECT_1, + ARIZONA_HP_POLL, ARIZONA_HP_POLL); + return -EAGAIN; + } + + /* OK, got both. Now, compare... */ + dev_dbg(arizona->dev, "HPDET measured %d %d\n", + info->hpdet_res[0], info->hpdet_res[1]); + + /* Take the headphone impedance for the main report */ + *reading = info->hpdet_res[0]; + + /* Sometimes we get false readings due to slow insert */ + if (*reading >= ARIZONA_HPDET_MAX && !info->hpdet_retried) { + dev_dbg(arizona->dev, "Retrying high impedance\n"); + info->num_hpdet_res = 0; + info->hpdet_retried = true; + arizona_start_hpdet_acc_id(info); + pm_runtime_put(info->dev); + return -EAGAIN; + } + + /* + * If we measure the mic as high impedance + */ + if (!id_gpio || info->hpdet_res[1] > 50) { + dev_dbg(arizona->dev, "Detected mic\n"); + *mic = true; + info->detecting = true; + } else { + dev_dbg(arizona->dev, "Detected headphone\n"); + } + + /* Make sure everything is reset back to the real polarity */ + regmap_update_bits(arizona->regmap, ARIZONA_ACCESSORY_DETECT_MODE_1, + ARIZONA_ACCDET_SRC, info->micd_modes[0].src); + + return 0; +} + +static irqreturn_t arizona_hpdet_irq(int irq, void *data) +{ + struct arizona_extcon_info *info = data; + struct arizona *arizona = info->arizona; + int id_gpio = arizona->pdata.hpdet_id_gpio; + unsigned int report = EXTCON_JACK_HEADPHONE; + int ret, reading; + bool mic = false; + + mutex_lock(&info->lock); + + /* If we got a spurious IRQ for some reason then ignore it */ + if (!info->hpdet_active) { + dev_warn(arizona->dev, "Spurious HPDET IRQ\n"); + mutex_unlock(&info->lock); + return IRQ_NONE; + } + + /* If the cable was removed while measuring ignore the result */ + ret = extcon_get_state(info->edev, EXTCON_MECHANICAL); + if (ret < 0) { + dev_err(arizona->dev, "Failed to check cable state: %d\n", + ret); + goto out; + } else if (!ret) { + dev_dbg(arizona->dev, "Ignoring HPDET for removed cable\n"); + goto done; + } + + ret = arizona_hpdet_read(info); + if (ret == -EAGAIN) + goto out; + else if (ret < 0) + goto done; + reading = ret; + + /* Reset back to starting range */ + regmap_update_bits(arizona->regmap, + ARIZONA_HEADPHONE_DETECT_1, + ARIZONA_HP_IMPEDANCE_RANGE_MASK | ARIZONA_HP_POLL, + 0); + + ret = arizona_hpdet_do_id(info, &reading, &mic); + if (ret == -EAGAIN) + goto out; + else if (ret < 0) + goto done; + + /* Report high impedence cables as line outputs */ + if (reading >= 5000) + report = EXTCON_JACK_LINE_OUT; + else + report = EXTCON_JACK_HEADPHONE; + + ret = extcon_set_state_sync(info->edev, report, true); + if (ret != 0) + dev_err(arizona->dev, "Failed to report HP/line: %d\n", + ret); + +done: + /* Reset back to starting range */ + regmap_update_bits(arizona->regmap, + ARIZONA_HEADPHONE_DETECT_1, + ARIZONA_HP_IMPEDANCE_RANGE_MASK | ARIZONA_HP_POLL, + 0); + + arizona_extcon_hp_clamp(info, false); + + if (id_gpio) + gpio_set_value_cansleep(id_gpio, 0); + + /* If we have a mic then reenable MICDET */ + if (mic || info->mic) + arizona_start_mic(info); + + if (info->hpdet_active) { + pm_runtime_put_autosuspend(info->dev); + info->hpdet_active = false; + } + + info->hpdet_done = true; + +out: + mutex_unlock(&info->lock); + + return IRQ_HANDLED; +} + +static void arizona_identify_headphone(struct arizona_extcon_info *info) +{ + struct arizona *arizona = info->arizona; + int ret; + + if (info->hpdet_done) + return; + + dev_dbg(arizona->dev, "Starting HPDET\n"); + + /* Make sure we keep the device enabled during the measurement */ + pm_runtime_get(info->dev); + + info->hpdet_active = true; + + arizona_stop_mic(info); + + arizona_extcon_hp_clamp(info, true); + + ret = regmap_update_bits(arizona->regmap, + ARIZONA_ACCESSORY_DETECT_MODE_1, + ARIZONA_ACCDET_MODE_MASK, + arizona->pdata.hpdet_channel); + if (ret != 0) { + dev_err(arizona->dev, "Failed to set HPDET mode: %d\n", ret); + goto err; + } + + ret = regmap_update_bits(arizona->regmap, ARIZONA_HEADPHONE_DETECT_1, + ARIZONA_HP_POLL, ARIZONA_HP_POLL); + if (ret != 0) { + dev_err(arizona->dev, "Can't start HPDETL measurement: %d\n", + ret); + goto err; + } + + return; + +err: + arizona_extcon_hp_clamp(info, false); + pm_runtime_put_autosuspend(info->dev); + + /* Just report headphone */ + ret = extcon_set_state_sync(info->edev, EXTCON_JACK_HEADPHONE, true); + if (ret != 0) + dev_err(arizona->dev, "Failed to report headphone: %d\n", ret); + + if (info->mic) + arizona_start_mic(info); + + info->hpdet_active = false; +} + +static void arizona_start_hpdet_acc_id(struct arizona_extcon_info *info) +{ + struct arizona *arizona = info->arizona; + int hp_reading = 32; + bool mic; + int ret; + + dev_dbg(arizona->dev, "Starting identification via HPDET\n"); + + /* Make sure we keep the device enabled during the measurement */ + pm_runtime_get_sync(info->dev); + + info->hpdet_active = true; + + arizona_extcon_hp_clamp(info, true); + + ret = regmap_update_bits(arizona->regmap, + ARIZONA_ACCESSORY_DETECT_MODE_1, + ARIZONA_ACCDET_SRC | ARIZONA_ACCDET_MODE_MASK, + info->micd_modes[0].src | + arizona->pdata.hpdet_channel); + if (ret != 0) { + dev_err(arizona->dev, "Failed to set HPDET mode: %d\n", ret); + goto err; + } + + if (arizona->pdata.hpdet_acc_id_line) { + ret = regmap_update_bits(arizona->regmap, + ARIZONA_HEADPHONE_DETECT_1, + ARIZONA_HP_POLL, ARIZONA_HP_POLL); + if (ret != 0) { + dev_err(arizona->dev, + "Can't start HPDETL measurement: %d\n", + ret); + goto err; + } + } else { + arizona_hpdet_do_id(info, &hp_reading, &mic); + } + + return; + +err: + /* Just report headphone */ + ret = extcon_set_state_sync(info->edev, EXTCON_JACK_HEADPHONE, true); + if (ret != 0) + dev_err(arizona->dev, "Failed to report headphone: %d\n", ret); + + info->hpdet_active = false; +} + +static void arizona_micd_timeout_work(struct work_struct *work) +{ + struct arizona_extcon_info *info = container_of(work, + struct arizona_extcon_info, + micd_timeout_work.work); + + mutex_lock(&info->lock); + + dev_dbg(info->arizona->dev, "MICD timed out, reporting HP\n"); + + info->detecting = false; + + arizona_identify_headphone(info); + + mutex_unlock(&info->lock); +} + +static int arizona_micd_adc_read(struct arizona_extcon_info *info) +{ + struct arizona *arizona = info->arizona; + unsigned int val; + int ret; + + /* Must disable MICD before we read the ADCVAL */ + regmap_update_bits(arizona->regmap, ARIZONA_MIC_DETECT_1, + ARIZONA_MICD_ENA, 0); + + ret = regmap_read(arizona->regmap, ARIZONA_MIC_DETECT_4, &val); + if (ret != 0) { + dev_err(arizona->dev, + "Failed to read MICDET_ADCVAL: %d\n", ret); + return ret; + } + + dev_dbg(arizona->dev, "MICDET_ADCVAL: %x\n", val); + + val &= ARIZONA_MICDET_ADCVAL_MASK; + if (val < ARRAY_SIZE(arizona_micd_levels)) + val = arizona_micd_levels[val]; + else + val = INT_MAX; + + if (val <= QUICK_HEADPHONE_MAX_OHM) + val = ARIZONA_MICD_STS | ARIZONA_MICD_LVL_0; + else if (val <= MICROPHONE_MIN_OHM) + val = ARIZONA_MICD_STS | ARIZONA_MICD_LVL_1; + else if (val <= MICROPHONE_MAX_OHM) + val = ARIZONA_MICD_STS | ARIZONA_MICD_LVL_8; + else + val = ARIZONA_MICD_LVL_8; + + return val; +} + +static int arizona_micd_read(struct arizona_extcon_info *info) +{ + struct arizona *arizona = info->arizona; + unsigned int val = 0; + int ret, i; + + for (i = 0; i < 10 && !(val & MICD_LVL_0_TO_8); i++) { + ret = regmap_read(arizona->regmap, ARIZONA_MIC_DETECT_3, &val); + if (ret != 0) { + dev_err(arizona->dev, + "Failed to read MICDET: %d\n", ret); + return ret; + } + + dev_dbg(arizona->dev, "MICDET: %x\n", val); + + if (!(val & ARIZONA_MICD_VALID)) { + dev_warn(arizona->dev, + "Microphone detection state invalid\n"); + return -EINVAL; + } + } + + if (i == 10 && !(val & MICD_LVL_0_TO_8)) { + dev_err(arizona->dev, "Failed to get valid MICDET value\n"); + return -EINVAL; + } + + return val; +} + +static int arizona_micdet_reading(void *priv) +{ + struct arizona_extcon_info *info = priv; + struct arizona *arizona = info->arizona; + int ret, val; + + if (info->detecting && arizona->pdata.micd_software_compare) + ret = arizona_micd_adc_read(info); + else + ret = arizona_micd_read(info); + if (ret < 0) + return ret; + + val = ret; + + /* Due to jack detect this should never happen */ + if (!(val & ARIZONA_MICD_STS)) { + dev_warn(arizona->dev, "Detected open circuit\n"); + info->mic = false; + info->detecting = false; + arizona_identify_headphone(info); + return 0; + } + + /* If we got a high impedence we should have a headset, report it. */ + if (val & ARIZONA_MICD_LVL_8) { + info->mic = true; + info->detecting = false; + + arizona_identify_headphone(info); + + ret = extcon_set_state_sync(info->edev, + EXTCON_JACK_MICROPHONE, true); + if (ret != 0) + dev_err(arizona->dev, "Headset report failed: %d\n", + ret); + + /* Don't need to regulate for button detection */ + ret = regulator_allow_bypass(info->micvdd, true); + if (ret != 0) { + dev_err(arizona->dev, "Failed to bypass MICVDD: %d\n", + ret); + } + + return 0; + } + + /* If we detected a lower impedence during initial startup + * then we probably have the wrong polarity, flip it. Don't + * do this for the lowest impedences to speed up detection of + * plain headphones. If both polarities report a low + * impedence then give up and report headphones. + */ + if (val & MICD_LVL_1_TO_7) { + if (info->jack_flips >= info->micd_num_modes * 10) { + dev_dbg(arizona->dev, "Detected HP/line\n"); + + info->detecting = false; + + arizona_identify_headphone(info); + } else { + info->micd_mode++; + if (info->micd_mode == info->micd_num_modes) + info->micd_mode = 0; + arizona_extcon_set_mode(info, info->micd_mode); + + info->jack_flips++; + + if (arizona->pdata.micd_software_compare) + regmap_update_bits(arizona->regmap, + ARIZONA_MIC_DETECT_1, + ARIZONA_MICD_ENA, + ARIZONA_MICD_ENA); + + queue_delayed_work(system_power_efficient_wq, + &info->micd_timeout_work, + msecs_to_jiffies(arizona->pdata.micd_timeout)); + } + + return 0; + } + + /* + * If we're still detecting and we detect a short then we've + * got a headphone. + */ + dev_dbg(arizona->dev, "Headphone detected\n"); + info->detecting = false; + + arizona_identify_headphone(info); + + return 0; +} + +static int arizona_button_reading(void *priv) +{ + struct arizona_extcon_info *info = priv; + struct arizona *arizona = info->arizona; + int val, key, lvl, i; + + val = arizona_micd_read(info); + if (val < 0) + return val; + + /* + * If we're still detecting and we detect a short then we've + * got a headphone. Otherwise it's a button press. + */ + if (val & MICD_LVL_0_TO_7) { + if (info->mic) { + dev_dbg(arizona->dev, "Mic button detected\n"); + + lvl = val & ARIZONA_MICD_LVL_MASK; + lvl >>= ARIZONA_MICD_LVL_SHIFT; + + for (i = 0; i < info->num_micd_ranges; i++) + input_report_key(info->input, + info->micd_ranges[i].key, 0); + + if (lvl && ffs(lvl) - 1 < info->num_micd_ranges) { + key = info->micd_ranges[ffs(lvl) - 1].key; + input_report_key(info->input, key, 1); + input_sync(info->input); + } else { + dev_err(arizona->dev, "Button out of range\n"); + } + } else { + dev_warn(arizona->dev, "Button with no mic: %x\n", + val); + } + } else { + dev_dbg(arizona->dev, "Mic button released\n"); + for (i = 0; i < info->num_micd_ranges; i++) + input_report_key(info->input, + info->micd_ranges[i].key, 0); + input_sync(info->input); + arizona_extcon_pulse_micbias(info); + } + + return 0; +} + +static void arizona_micd_detect(struct work_struct *work) +{ + struct arizona_extcon_info *info = container_of(work, + struct arizona_extcon_info, + micd_detect_work.work); + struct arizona *arizona = info->arizona; + int ret; + + cancel_delayed_work_sync(&info->micd_timeout_work); + + mutex_lock(&info->lock); + + /* If the cable was removed while measuring ignore the result */ + ret = extcon_get_state(info->edev, EXTCON_MECHANICAL); + if (ret < 0) { + dev_err(arizona->dev, "Failed to check cable state: %d\n", + ret); + mutex_unlock(&info->lock); + return; + } else if (!ret) { + dev_dbg(arizona->dev, "Ignoring MICDET for removed cable\n"); + mutex_unlock(&info->lock); + return; + } + + if (info->detecting) + arizona_micdet_reading(info); + else + arizona_button_reading(info); + + pm_runtime_mark_last_busy(info->dev); + mutex_unlock(&info->lock); +} + +static irqreturn_t arizona_micdet(int irq, void *data) +{ + struct arizona_extcon_info *info = data; + struct arizona *arizona = info->arizona; + int debounce = arizona->pdata.micd_detect_debounce; + + cancel_delayed_work_sync(&info->micd_detect_work); + cancel_delayed_work_sync(&info->micd_timeout_work); + + mutex_lock(&info->lock); + if (!info->detecting) + debounce = 0; + mutex_unlock(&info->lock); + + if (debounce) + queue_delayed_work(system_power_efficient_wq, + &info->micd_detect_work, + msecs_to_jiffies(debounce)); + else + arizona_micd_detect(&info->micd_detect_work.work); + + return IRQ_HANDLED; +} + +static void arizona_hpdet_work(struct work_struct *work) +{ + struct arizona_extcon_info *info = container_of(work, + struct arizona_extcon_info, + hpdet_work.work); + + mutex_lock(&info->lock); + arizona_start_hpdet_acc_id(info); + mutex_unlock(&info->lock); +} + +static int arizona_hpdet_wait(struct arizona_extcon_info *info) +{ + struct arizona *arizona = info->arizona; + unsigned int val; + int i, ret; + + for (i = 0; i < ARIZONA_HPDET_WAIT_COUNT; i++) { + ret = regmap_read(arizona->regmap, ARIZONA_HEADPHONE_DETECT_2, + &val); + if (ret) { + dev_err(arizona->dev, + "Failed to read HPDET state: %d\n", ret); + return ret; + } + + switch (info->hpdet_ip_version) { + case 0: + if (val & ARIZONA_HP_DONE) + return 0; + break; + default: + if (val & ARIZONA_HP_DONE_B) + return 0; + break; + } + + msleep(ARIZONA_HPDET_WAIT_DELAY_MS); + } + + dev_warn(arizona->dev, "HPDET did not appear to complete\n"); + + return -ETIMEDOUT; +} + +static irqreturn_t arizona_jackdet(int irq, void *data) +{ + struct arizona_extcon_info *info = data; + struct arizona *arizona = info->arizona; + unsigned int val, present, mask; + bool cancelled_hp, cancelled_mic; + int ret, i; + + cancelled_hp = cancel_delayed_work_sync(&info->hpdet_work); + cancelled_mic = cancel_delayed_work_sync(&info->micd_timeout_work); + + pm_runtime_get_sync(info->dev); + + mutex_lock(&info->lock); + + if (info->micd_clamp) { + mask = ARIZONA_MICD_CLAMP_STS; + present = 0; + } else { + mask = ARIZONA_JD1_STS; + if (arizona->pdata.jd_invert) + present = 0; + else + present = ARIZONA_JD1_STS; + } + + ret = regmap_read(arizona->regmap, ARIZONA_AOD_IRQ_RAW_STATUS, &val); + if (ret != 0) { + dev_err(arizona->dev, "Failed to read jackdet status: %d\n", + ret); + mutex_unlock(&info->lock); + pm_runtime_put_autosuspend(info->dev); + return IRQ_NONE; + } + + val &= mask; + if (val == info->last_jackdet) { + dev_dbg(arizona->dev, "Suppressing duplicate JACKDET\n"); + if (cancelled_hp) + queue_delayed_work(system_power_efficient_wq, + &info->hpdet_work, + msecs_to_jiffies(HPDET_DEBOUNCE)); + + if (cancelled_mic) { + int micd_timeout = arizona->pdata.micd_timeout; + + queue_delayed_work(system_power_efficient_wq, + &info->micd_timeout_work, + msecs_to_jiffies(micd_timeout)); + } + + goto out; + } + info->last_jackdet = val; + + if (info->last_jackdet == present) { + dev_dbg(arizona->dev, "Detected jack\n"); + ret = extcon_set_state_sync(info->edev, + EXTCON_MECHANICAL, true); + + if (ret != 0) + dev_err(arizona->dev, "Mechanical report failed: %d\n", + ret); + + info->detecting = true; + info->mic = false; + info->jack_flips = 0; + + if (!arizona->pdata.hpdet_acc_id) { + arizona_start_mic(info); + } else { + queue_delayed_work(system_power_efficient_wq, + &info->hpdet_work, + msecs_to_jiffies(HPDET_DEBOUNCE)); + } + + if (info->micd_clamp || !arizona->pdata.jd_invert) + regmap_update_bits(arizona->regmap, + ARIZONA_JACK_DETECT_DEBOUNCE, + ARIZONA_MICD_CLAMP_DB | + ARIZONA_JD1_DB, 0); + } else { + dev_dbg(arizona->dev, "Detected jack removal\n"); + + arizona_stop_mic(info); + + info->num_hpdet_res = 0; + for (i = 0; i < ARRAY_SIZE(info->hpdet_res); i++) + info->hpdet_res[i] = 0; + info->mic = false; + info->hpdet_done = false; + info->hpdet_retried = false; + + for (i = 0; i < info->num_micd_ranges; i++) + input_report_key(info->input, + info->micd_ranges[i].key, 0); + input_sync(info->input); + + for (i = 0; i < ARRAY_SIZE(arizona_cable) - 1; i++) { + ret = extcon_set_state_sync(info->edev, + arizona_cable[i], false); + if (ret != 0) + dev_err(arizona->dev, + "Removal report failed: %d\n", ret); + } + + /* + * If the jack was removed during a headphone detection we + * need to wait for the headphone detection to finish, as + * it can not be aborted. We don't want to be able to start + * a new headphone detection from a fresh insert until this + * one is finished. + */ + arizona_hpdet_wait(info); + + regmap_update_bits(arizona->regmap, + ARIZONA_JACK_DETECT_DEBOUNCE, + ARIZONA_MICD_CLAMP_DB | ARIZONA_JD1_DB, + ARIZONA_MICD_CLAMP_DB | ARIZONA_JD1_DB); + } + +out: + /* Clear trig_sts to make sure DCVDD is not forced up */ + regmap_write(arizona->regmap, ARIZONA_AOD_WKUP_AND_TRIG, + ARIZONA_MICD_CLAMP_FALL_TRIG_STS | + ARIZONA_MICD_CLAMP_RISE_TRIG_STS | + ARIZONA_JD1_FALL_TRIG_STS | + ARIZONA_JD1_RISE_TRIG_STS); + + mutex_unlock(&info->lock); + + pm_runtime_mark_last_busy(info->dev); + pm_runtime_put_autosuspend(info->dev); + + return IRQ_HANDLED; +} + +/* Map a level onto a slot in the register bank */ +static void arizona_micd_set_level(struct arizona *arizona, int index, + unsigned int level) +{ + int reg; + unsigned int mask; + + reg = ARIZONA_MIC_DETECT_LEVEL_4 - (index / 2); + + if (!(index % 2)) { + mask = 0x3f00; + level <<= 8; + } else { + mask = 0x3f; + } + + /* Program the level itself */ + regmap_update_bits(arizona->regmap, reg, mask, level); +} + +static int arizona_extcon_get_micd_configs(struct device *dev, + struct arizona *arizona) +{ + const char * const prop = "wlf,micd-configs"; + const int entries_per_config = 3; + struct arizona_micd_config *micd_configs; + int nconfs, ret; + int i, j; + u32 *vals; + + nconfs = device_property_count_u32(arizona->dev, prop); + if (nconfs <= 0) + return 0; + + vals = kcalloc(nconfs, sizeof(u32), GFP_KERNEL); + if (!vals) + return -ENOMEM; + + ret = device_property_read_u32_array(arizona->dev, prop, vals, nconfs); + if (ret < 0) + goto out; + + nconfs /= entries_per_config; + micd_configs = devm_kcalloc(dev, nconfs, sizeof(*micd_configs), + GFP_KERNEL); + if (!micd_configs) { + ret = -ENOMEM; + goto out; + } + + for (i = 0, j = 0; i < nconfs; ++i) { + micd_configs[i].src = vals[j++] ? ARIZONA_ACCDET_SRC : 0; + micd_configs[i].bias = vals[j++]; + micd_configs[i].gpio = vals[j++]; + } + + arizona->pdata.micd_configs = micd_configs; + arizona->pdata.num_micd_configs = nconfs; + +out: + kfree(vals); + return ret; +} + +static int arizona_extcon_device_get_pdata(struct device *dev, + struct arizona *arizona) +{ + struct arizona_pdata *pdata = &arizona->pdata; + unsigned int val = ARIZONA_ACCDET_MODE_HPL; + int ret; + + device_property_read_u32(arizona->dev, "wlf,hpdet-channel", &val); + switch (val) { + case ARIZONA_ACCDET_MODE_HPL: + case ARIZONA_ACCDET_MODE_HPR: + pdata->hpdet_channel = val; + break; + default: + dev_err(arizona->dev, + "Wrong wlf,hpdet-channel DT value %d\n", val); + pdata->hpdet_channel = ARIZONA_ACCDET_MODE_HPL; + } + + device_property_read_u32(arizona->dev, "wlf,micd-detect-debounce", + &pdata->micd_detect_debounce); + + device_property_read_u32(arizona->dev, "wlf,micd-bias-start-time", + &pdata->micd_bias_start_time); + + device_property_read_u32(arizona->dev, "wlf,micd-rate", + &pdata->micd_rate); + + device_property_read_u32(arizona->dev, "wlf,micd-dbtime", + &pdata->micd_dbtime); + + device_property_read_u32(arizona->dev, "wlf,micd-timeout-ms", + &pdata->micd_timeout); + + pdata->micd_force_micbias = device_property_read_bool(arizona->dev, + "wlf,micd-force-micbias"); + + pdata->micd_software_compare = device_property_read_bool(arizona->dev, + "wlf,micd-software-compare"); + + pdata->jd_invert = device_property_read_bool(arizona->dev, + "wlf,jd-invert"); + + device_property_read_u32(arizona->dev, "wlf,gpsw", &pdata->gpsw); + + pdata->jd_gpio5 = device_property_read_bool(arizona->dev, + "wlf,use-jd2"); + pdata->jd_gpio5_nopull = device_property_read_bool(arizona->dev, + "wlf,use-jd2-nopull"); + + ret = arizona_extcon_get_micd_configs(dev, arizona); + if (ret < 0) + dev_err(arizona->dev, "Failed to read micd configs: %d\n", ret); + + return 0; +} + +static int arizona_extcon_probe(struct platform_device *pdev) +{ + struct arizona *arizona = dev_get_drvdata(pdev->dev.parent); + struct arizona_pdata *pdata = &arizona->pdata; + struct arizona_extcon_info *info; + unsigned int val; + unsigned int clamp_mode; + int jack_irq_fall, jack_irq_rise; + int ret, mode, i, j; + + if (!arizona->dapm || !arizona->dapm->card) + return -EPROBE_DEFER; + + info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL); + if (!info) + return -ENOMEM; + + if (!dev_get_platdata(arizona->dev)) + arizona_extcon_device_get_pdata(&pdev->dev, arizona); + + info->micvdd = devm_regulator_get(&pdev->dev, "MICVDD"); + if (IS_ERR(info->micvdd)) { + ret = PTR_ERR(info->micvdd); + dev_err(arizona->dev, "Failed to get MICVDD: %d\n", ret); + return ret; + } + + mutex_init(&info->lock); + info->arizona = arizona; + info->dev = &pdev->dev; + info->last_jackdet = ~(ARIZONA_MICD_CLAMP_STS | ARIZONA_JD1_STS); + INIT_DELAYED_WORK(&info->hpdet_work, arizona_hpdet_work); + INIT_DELAYED_WORK(&info->micd_detect_work, arizona_micd_detect); + INIT_DELAYED_WORK(&info->micd_timeout_work, arizona_micd_timeout_work); + platform_set_drvdata(pdev, info); + + switch (arizona->type) { + case WM5102: + switch (arizona->rev) { + case 0: + info->micd_reva = true; + break; + default: + info->micd_clamp = true; + info->hpdet_ip_version = 1; + break; + } + break; + case WM5110: + case WM8280: + switch (arizona->rev) { + case 0 ... 2: + break; + default: + info->micd_clamp = true; + info->hpdet_ip_version = 2; + break; + } + break; + case WM8998: + case WM1814: + info->micd_clamp = true; + info->hpdet_ip_version = 2; + break; + default: + break; + } + + info->edev = devm_extcon_dev_allocate(&pdev->dev, arizona_cable); + if (IS_ERR(info->edev)) { + dev_err(&pdev->dev, "failed to allocate extcon device\n"); + return -ENOMEM; + } + + ret = devm_extcon_dev_register(&pdev->dev, info->edev); + if (ret < 0) { + dev_err(arizona->dev, "extcon_dev_register() failed: %d\n", + ret); + return ret; + } + + info->input = devm_input_allocate_device(&pdev->dev); + if (!info->input) { + dev_err(arizona->dev, "Can't allocate input dev\n"); + ret = -ENOMEM; + return ret; + } + + info->input->name = "Headset"; + info->input->phys = "arizona/extcon"; + + if (!pdata->micd_timeout) + pdata->micd_timeout = DEFAULT_MICD_TIMEOUT; + + if (pdata->num_micd_configs) { + info->micd_modes = pdata->micd_configs; + info->micd_num_modes = pdata->num_micd_configs; + } else { + info->micd_modes = micd_default_modes; + info->micd_num_modes = ARRAY_SIZE(micd_default_modes); + } + + if (arizona->pdata.gpsw > 0) + regmap_update_bits(arizona->regmap, ARIZONA_GP_SWITCH_1, + ARIZONA_SW1_MODE_MASK, arizona->pdata.gpsw); + + if (pdata->micd_pol_gpio > 0) { + if (info->micd_modes[0].gpio) + mode = GPIOF_OUT_INIT_HIGH; + else + mode = GPIOF_OUT_INIT_LOW; + + ret = devm_gpio_request_one(&pdev->dev, pdata->micd_pol_gpio, + mode, "MICD polarity"); + if (ret != 0) { + dev_err(arizona->dev, "Failed to request GPIO%d: %d\n", + pdata->micd_pol_gpio, ret); + return ret; + } + + info->micd_pol_gpio = gpio_to_desc(pdata->micd_pol_gpio); + } else { + if (info->micd_modes[0].gpio) + mode = GPIOD_OUT_HIGH; + else + mode = GPIOD_OUT_LOW; + + /* We can't use devm here because we need to do the get + * against the MFD device, as that is where the of_node + * will reside, but if we devm against that the GPIO + * will not be freed if the extcon driver is unloaded. + */ + info->micd_pol_gpio = gpiod_get_optional(arizona->dev, + "wlf,micd-pol", + GPIOD_OUT_LOW); + if (IS_ERR(info->micd_pol_gpio)) { + ret = PTR_ERR(info->micd_pol_gpio); + dev_err(arizona->dev, + "Failed to get microphone polarity GPIO: %d\n", + ret); + return ret; + } + } + + if (arizona->pdata.hpdet_id_gpio > 0) { + ret = devm_gpio_request_one(&pdev->dev, + arizona->pdata.hpdet_id_gpio, + GPIOF_OUT_INIT_LOW, + "HPDET"); + if (ret != 0) { + dev_err(arizona->dev, "Failed to request GPIO%d: %d\n", + arizona->pdata.hpdet_id_gpio, ret); + goto err_gpio; + } + } + + if (arizona->pdata.micd_bias_start_time) + regmap_update_bits(arizona->regmap, ARIZONA_MIC_DETECT_1, + ARIZONA_MICD_BIAS_STARTTIME_MASK, + arizona->pdata.micd_bias_start_time + << ARIZONA_MICD_BIAS_STARTTIME_SHIFT); + + if (arizona->pdata.micd_rate) + regmap_update_bits(arizona->regmap, ARIZONA_MIC_DETECT_1, + ARIZONA_MICD_RATE_MASK, + arizona->pdata.micd_rate + << ARIZONA_MICD_RATE_SHIFT); + + switch (arizona->pdata.micd_dbtime) { + case MICD_DBTIME_FOUR_READINGS: + regmap_update_bits(arizona->regmap, ARIZONA_MIC_DETECT_1, + ARIZONA_MICD_DBTIME_MASK, + ARIZONA_MICD_DBTIME); + break; + case MICD_DBTIME_TWO_READINGS: + regmap_update_bits(arizona->regmap, ARIZONA_MIC_DETECT_1, + ARIZONA_MICD_DBTIME_MASK, 0); + break; + default: + break; + } + + BUILD_BUG_ON(ARRAY_SIZE(arizona_micd_levels) < + ARIZONA_NUM_MICD_BUTTON_LEVELS); + + if (arizona->pdata.num_micd_ranges) { + info->micd_ranges = pdata->micd_ranges; + info->num_micd_ranges = pdata->num_micd_ranges; + } else { + info->micd_ranges = micd_default_ranges; + info->num_micd_ranges = ARRAY_SIZE(micd_default_ranges); + } + + if (arizona->pdata.num_micd_ranges > ARIZONA_MAX_MICD_RANGE) { + dev_err(arizona->dev, "Too many MICD ranges: %d\n", + arizona->pdata.num_micd_ranges); + } + + if (info->num_micd_ranges > 1) { + for (i = 1; i < info->num_micd_ranges; i++) { + if (info->micd_ranges[i - 1].max > + info->micd_ranges[i].max) { + dev_err(arizona->dev, + "MICD ranges must be sorted\n"); + ret = -EINVAL; + goto err_gpio; + } + } + } + + /* Disable all buttons by default */ + regmap_update_bits(arizona->regmap, ARIZONA_MIC_DETECT_2, + ARIZONA_MICD_LVL_SEL_MASK, 0x81); + + /* Set up all the buttons the user specified */ + for (i = 0; i < info->num_micd_ranges; i++) { + for (j = 0; j < ARIZONA_NUM_MICD_BUTTON_LEVELS; j++) + if (arizona_micd_levels[j] >= info->micd_ranges[i].max) + break; + + if (j == ARIZONA_NUM_MICD_BUTTON_LEVELS) { + dev_err(arizona->dev, "Unsupported MICD level %d\n", + info->micd_ranges[i].max); + ret = -EINVAL; + goto err_gpio; + } + + dev_dbg(arizona->dev, "%d ohms for MICD threshold %d\n", + arizona_micd_levels[j], i); + + arizona_micd_set_level(arizona, i, j); + input_set_capability(info->input, EV_KEY, + info->micd_ranges[i].key); + + /* Enable reporting of that range */ + regmap_update_bits(arizona->regmap, ARIZONA_MIC_DETECT_2, + 1 << i, 1 << i); + } + + /* Set all the remaining keys to a maximum */ + for (; i < ARIZONA_MAX_MICD_RANGE; i++) + arizona_micd_set_level(arizona, i, 0x3f); + + /* + * If we have a clamp use it, activating in conjunction with + * GPIO5 if that is connected for jack detect operation. + */ + if (info->micd_clamp) { + if (arizona->pdata.jd_gpio5) { + /* Put the GPIO into input mode with optional pull */ + val = 0xc101; + if (arizona->pdata.jd_gpio5_nopull) + val &= ~ARIZONA_GPN_PU; + + regmap_write(arizona->regmap, ARIZONA_GPIO5_CTRL, + val); + + if (arizona->pdata.jd_invert) + clamp_mode = ARIZONA_MICD_CLAMP_MODE_JDH_GP5H; + else + clamp_mode = ARIZONA_MICD_CLAMP_MODE_JDL_GP5H; + } else { + if (arizona->pdata.jd_invert) + clamp_mode = ARIZONA_MICD_CLAMP_MODE_JDH; + else + clamp_mode = ARIZONA_MICD_CLAMP_MODE_JDL; + } + + regmap_update_bits(arizona->regmap, + ARIZONA_MICD_CLAMP_CONTROL, + ARIZONA_MICD_CLAMP_MODE_MASK, clamp_mode); + + regmap_update_bits(arizona->regmap, + ARIZONA_JACK_DETECT_DEBOUNCE, + ARIZONA_MICD_CLAMP_DB, + ARIZONA_MICD_CLAMP_DB); + } + + arizona_extcon_set_mode(info, 0); + + pm_runtime_enable(&pdev->dev); + pm_runtime_idle(&pdev->dev); + pm_runtime_get_sync(&pdev->dev); + + if (info->micd_clamp) { + jack_irq_rise = ARIZONA_IRQ_MICD_CLAMP_RISE; + jack_irq_fall = ARIZONA_IRQ_MICD_CLAMP_FALL; + } else { + jack_irq_rise = ARIZONA_IRQ_JD_RISE; + jack_irq_fall = ARIZONA_IRQ_JD_FALL; + } + + ret = arizona_request_irq(arizona, jack_irq_rise, + "JACKDET rise", arizona_jackdet, info); + if (ret != 0) { + dev_err(&pdev->dev, "Failed to get JACKDET rise IRQ: %d\n", + ret); + goto err_pm; + } + + ret = arizona_set_irq_wake(arizona, jack_irq_rise, 1); + if (ret != 0) { + dev_err(&pdev->dev, "Failed to set JD rise IRQ wake: %d\n", + ret); + goto err_rise; + } + + ret = arizona_request_irq(arizona, jack_irq_fall, + "JACKDET fall", arizona_jackdet, info); + if (ret != 0) { + dev_err(&pdev->dev, "Failed to get JD fall IRQ: %d\n", ret); + goto err_rise_wake; + } + + ret = arizona_set_irq_wake(arizona, jack_irq_fall, 1); + if (ret != 0) { + dev_err(&pdev->dev, "Failed to set JD fall IRQ wake: %d\n", + ret); + goto err_fall; + } + + ret = arizona_request_irq(arizona, ARIZONA_IRQ_MICDET, + "MICDET", arizona_micdet, info); + if (ret != 0) { + dev_err(&pdev->dev, "Failed to get MICDET IRQ: %d\n", ret); + goto err_fall_wake; + } + + ret = arizona_request_irq(arizona, ARIZONA_IRQ_HPDET, + "HPDET", arizona_hpdet_irq, info); + if (ret != 0) { + dev_err(&pdev->dev, "Failed to get HPDET IRQ: %d\n", ret); + goto err_micdet; + } + + arizona_clk32k_enable(arizona); + regmap_update_bits(arizona->regmap, ARIZONA_JACK_DETECT_DEBOUNCE, + ARIZONA_JD1_DB, ARIZONA_JD1_DB); + regmap_update_bits(arizona->regmap, ARIZONA_JACK_DETECT_ANALOGUE, + ARIZONA_JD1_ENA, ARIZONA_JD1_ENA); + + ret = regulator_allow_bypass(info->micvdd, true); + if (ret != 0) + dev_warn(arizona->dev, "Failed to set MICVDD to bypass: %d\n", + ret); + + ret = input_register_device(info->input); + if (ret) { + dev_err(&pdev->dev, "Can't register input device: %d\n", ret); + goto err_hpdet; + } + + pm_runtime_put(&pdev->dev); + + return 0; + +err_hpdet: + arizona_free_irq(arizona, ARIZONA_IRQ_HPDET, info); +err_micdet: + arizona_free_irq(arizona, ARIZONA_IRQ_MICDET, info); +err_fall_wake: + arizona_set_irq_wake(arizona, jack_irq_fall, 0); +err_fall: + arizona_free_irq(arizona, jack_irq_fall, info); +err_rise_wake: + arizona_set_irq_wake(arizona, jack_irq_rise, 0); +err_rise: + arizona_free_irq(arizona, jack_irq_rise, info); +err_pm: + pm_runtime_put(&pdev->dev); + pm_runtime_disable(&pdev->dev); +err_gpio: + gpiod_put(info->micd_pol_gpio); + return ret; +} + +static int arizona_extcon_remove(struct platform_device *pdev) +{ + struct arizona_extcon_info *info = platform_get_drvdata(pdev); + struct arizona *arizona = info->arizona; + int jack_irq_rise, jack_irq_fall; + bool change; + int ret; + + ret = regmap_update_bits_check(arizona->regmap, ARIZONA_MIC_DETECT_1, + ARIZONA_MICD_ENA, 0, + &change); + if (ret < 0) { + dev_err(&pdev->dev, "Failed to disable micd on remove: %d\n", + ret); + } else if (change) { + regulator_disable(info->micvdd); + pm_runtime_put(info->dev); + } + + gpiod_put(info->micd_pol_gpio); + + pm_runtime_disable(&pdev->dev); + + regmap_update_bits(arizona->regmap, + ARIZONA_MICD_CLAMP_CONTROL, + ARIZONA_MICD_CLAMP_MODE_MASK, 0); + + if (info->micd_clamp) { + jack_irq_rise = ARIZONA_IRQ_MICD_CLAMP_RISE; + jack_irq_fall = ARIZONA_IRQ_MICD_CLAMP_FALL; + } else { + jack_irq_rise = ARIZONA_IRQ_JD_RISE; + jack_irq_fall = ARIZONA_IRQ_JD_FALL; + } + + arizona_set_irq_wake(arizona, jack_irq_rise, 0); + arizona_set_irq_wake(arizona, jack_irq_fall, 0); + arizona_free_irq(arizona, ARIZONA_IRQ_HPDET, info); + arizona_free_irq(arizona, ARIZONA_IRQ_MICDET, info); + arizona_free_irq(arizona, jack_irq_rise, info); + arizona_free_irq(arizona, jack_irq_fall, info); + cancel_delayed_work_sync(&info->hpdet_work); + regmap_update_bits(arizona->regmap, ARIZONA_JACK_DETECT_ANALOGUE, + ARIZONA_JD1_ENA, 0); + arizona_clk32k_disable(arizona); + + return 0; +} + +static struct platform_driver arizona_extcon_driver = { + .driver = { + .name = "arizona-extcon", + }, + .probe = arizona_extcon_probe, + .remove = arizona_extcon_remove, +}; + +module_platform_driver(arizona_extcon_driver); + +MODULE_DESCRIPTION("Arizona Extcon driver"); +MODULE_AUTHOR("Mark Brown "); +MODULE_LICENSE("GPL"); +MODULE_ALIAS("platform:extcon-arizona"); diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 6d1d8f4d0a66e..9d1ea737eebea 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -58,6 +58,7 @@ #include #include #include +#include #include #include #include "kcl/kcl_amdgpu_ttm.h" diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_prime.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_prime.m4 new file mode 100644 index 0000000000000..4a1160753c960 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_prime.m4 @@ -0,0 +1,11 @@ +dnl # +dnl # commit v5.10-rc3-1140-gc67e62790f5c +dnl # drm/prime: split array import functions v4 +dnl # +AC_DEFUN([AC_AMDGPU_DRM_PRIME_SG_TO_DMA_ADDR_ARRAY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([drm_prime_sg_to_dma_addr_array], [drivers/gpu/drm/drm_prime.c], [ + AC_DEFINE(HAVE_DRM_PRIME_SG_TO_DMA_ADDR_ARRAY, 1, [drm_prime_sg_to_dma_addr_array() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/highmem-internal.m4 b/drivers/gpu/drm/amd/dkms/m4/highmem-internal.m4 new file mode 100644 index 0000000000000..b2614eabab932 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/highmem-internal.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit f3ba3c710ac5a30cd058615a9eb62d2ad95bb782 +dnl # mm/highmem: Provide kmap_local* +dnl # +AC_DEFUN([AC_AMDGPU_KMAP_LOCAL], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + pgprot_t prot; + kmap_local_page_prot(NULL, prot); + ], [], [], [ + AC_DEFINE(HAVE_KMAP_LOCAL, 1, [kmap_local_* is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index b439fe9d39fe3..e82b760d04929 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -136,12 +136,13 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_STRUCT_DRM_CONNECTOR_STATE_COLORSPACE AC_AMDGPU_STRUCT_DRM_ATOMIC_STATE_DUPLICATED AC_AMDGPU_DRM_DP_SUBCONNECTOR + AC_AMDGPU_DRM_PRIME_SG_TO_DMA_ADDR_ARRAY AC_AMDGPU_DRM_MEMCPY_FROM_WC AC_AMDGPU_IS_COW_MAPPING AC_AMDGPU_VGA_REMOVE_VGACON AC_AMDGPU_DRM_APERTURE AC_AMDGPU_PCI_DRIVER_DEV_GROUPS - + AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ KERNEL_MAKE="$KERNEL_MAKE O=$LINUX_OBJ" diff --git a/include/kcl/kcl_drm_prime.h b/include/kcl/kcl_drm_prime.h new file mode 100644 index 0000000000000..7f02b6c95d10c --- /dev/null +++ b/include/kcl/kcl_drm_prime.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __KCL_DRM_PRIME_H__ +#define __KCL_DRM_PRIME_H__ + +#include +#include +#include + +#ifndef HAVE_DRM_PRIME_SG_TO_DMA_ADDR_ARRAY +static inline +int drm_prime_sg_to_dma_addr_array(struct sg_table *sgt, dma_addr_t *addrs, + int max_entries) +{ + return drm_prime_sg_to_page_addr_arrays(sgt, NULL, addrs, max_entries); + +} +#endif +#endif From 38720d2af31bbade9ed6661773446e2de475a644 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Wed, 3 Feb 2021 18:07:54 +0800 Subject: [PATCH 0347/1868] drm/amdkcl: test drm_prime_pages_to_sg() Test whether drm_prime_pages_to_sg() takes 3 arguments Signed-off-by: Slava Grigorev Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/dev-pagemap.m4 | 21 ++++++++ .../drm/amd/dkms/m4/drm-prime-pages-to-sg.m4 | 14 ++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 + include/kcl/backport/kcl_drm_prime.h | 49 +++++++++++++++++++ 5 files changed, 87 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/dev-pagemap.m4 create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-prime-pages-to-sg.m4 create mode 100644 include/kcl/backport/kcl_drm_prime.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 9d1ea737eebea..8bf382ab0c388 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -48,6 +48,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/gpu/drm/amd/dkms/m4/dev-pagemap.m4 b/drivers/gpu/drm/amd/dkms/m4/dev-pagemap.m4 new file mode 100644 index 0000000000000..b33ceb61643ce --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dev-pagemap.m4 @@ -0,0 +1,21 @@ +dnl # +dnl # commit a4574f63edc6f76fb46dcd65d3eb4d5a8e23ba38 +dnl # mm/memremap_pages: convert to 'struct range' +dnl # +AC_DEFUN([AC_AMDGPU_DEV_PAGEMAP_RANGE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct dev_pagemap *pm = NULL; + pm->range.start = 0; + ], [ + AC_DEFINE(HAVE_DEV_PAGEMAP_RANGE, 1, + [there is 'range' field within dev_pagemap structure]) + ]) + ]) +]) +AC_DEFUN([AC_AMDGPU_DEV_PAGEMAP], [ + AC_AMDGPU_DEV_PAGEMAP_RANGE +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-prime-pages-to-sg.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-prime-pages-to-sg.m4 new file mode 100644 index 0000000000000..5854aa864fd2e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-prime-pages-to-sg.m4 @@ -0,0 +1,14 @@ +dnl # +dnl # commit 707d561f77b5e2a6f90c9786bee44ee7a8dedc7e +dnl # drm: allow limiting the scatter list size. +dnl # +AC_DEFUN([AC_AMDGPU_DRM_PRIME_PAGES_TO_SG], [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_prime_pages_to_sg(NULL, NULL, 0); + ], [drm_prime_pages_to_sg], [drivers/gpu/drm/drm_prime.c], [ + AC_DEFINE(HAVE_DRM_PRIME_PAGES_TO_SG_3ARGS, 1, + [drm_prime_pages_to_sg() wants 3 arguments]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index e82b760d04929..61a4cadcc4fd7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -66,6 +66,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_LIST_FOR_EACH_ENTRY AC_AMDGPU_TIMER_SETUP AC_AMDGPU_AMD_IOMMU_PC_SUPPORTED + AC_AMDGPU_DEV_PAGEMAP AC_AMDGPU_DOWN_READ_KILLABLE AC_AMDGPU_DRM_CACHE AC_AMDGPU_DRM_DEBUG_ENABLED @@ -137,6 +138,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_STRUCT_DRM_ATOMIC_STATE_DUPLICATED AC_AMDGPU_DRM_DP_SUBCONNECTOR AC_AMDGPU_DRM_PRIME_SG_TO_DMA_ADDR_ARRAY + AC_AMDGPU_DRM_PRIME_PAGES_TO_SG AC_AMDGPU_DRM_MEMCPY_FROM_WC AC_AMDGPU_IS_COW_MAPPING AC_AMDGPU_VGA_REMOVE_VGACON diff --git a/include/kcl/backport/kcl_drm_prime.h b/include/kcl/backport/kcl_drm_prime.h new file mode 100644 index 0000000000000..1c3895f60823d --- /dev/null +++ b/include/kcl/backport/kcl_drm_prime.h @@ -0,0 +1,49 @@ +/* + * Copyright © 2012 Red Hat + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * Copyright (c) 2009-2010, Code Aurora Forum. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Dave Airlie + * Rob Clark + * + */ + +// Copied from include/drm/drm_prime.h +#ifndef _KCL_BACKPORT_KCL__DRM_PRIME_H__H_ +#define _KCL_BACKPORT_KCL__DRM_PRIME_H__H_ + +#include + +#ifndef HAVE_DRM_PRIME_PAGES_TO_SG_3ARGS +static inline +struct sg_table *_kcl_drm_prime_pages_to_sg(struct drm_device *dev, + struct page **pages, unsigned int nr_pages) +{ + pr_warn_once("legacy kernel with drm_prime_pages_to_sg() ignore segment size limits, which is buggy\n"); + return drm_prime_pages_to_sg(pages, nr_pages); +} +#define drm_prime_pages_to_sg _kcl_drm_prime_pages_to_sg +#endif + +#endif From e13ba40add1c0d41afd79d3a3fd641a2310799e7 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Wed, 3 Feb 2021 16:33:18 +0800 Subject: [PATCH 0348/1868] drm/amdkcl: test amd_iommu_invalidate_ctx protocol Test whether type of pasid is u32 Reviewed-by: Guchun Chen Signed-off-by: Slava Grigorev Signed-off-by: Flora Cui --- .../drm/amd/dkms/m4/amd_iommu_invalidate_ctx.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 2 files changed, 18 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/amd_iommu_invalidate_ctx.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/amd_iommu_invalidate_ctx.m4 b/drivers/gpu/drm/amd/dkms/m4/amd_iommu_invalidate_ctx.m4 new file mode 100644 index 0000000000000..ff2bf9c8949ad --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/amd_iommu_invalidate_ctx.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit c7b6bac9c72c5fcbd6e9e12545bd3022c7f21860 +dnl # drm, iommu: Change type of pasid to u32 +dnl # +AC_DEFUN([AC_AMDGPU_AMD_IOMMU_INVALIDATE_CTX], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + void (*f)(struct pci_dev *pdev, u32 pasid); + amd_iommu_invalidate_ctx callback = f; + ], [ + AC_DEFINE(HAVE_AMD_IOMMU_INVALIDATE_CTX_PASID_U32, 1, + [amd_iommu_invalidate_ctx take arg type of pasid as u32]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 61a4cadcc4fd7..b66ac0b8eaa38 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -66,6 +66,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_LIST_FOR_EACH_ENTRY AC_AMDGPU_TIMER_SETUP AC_AMDGPU_AMD_IOMMU_PC_SUPPORTED + AC_AMDGPU_AMD_IOMMU_INVALIDATE_CTX AC_AMDGPU_DEV_PAGEMAP AC_AMDGPU_DOWN_READ_KILLABLE AC_AMDGPU_DRM_CACHE From e13dd95c61974ffae76272f25b3fb367768e7d81 Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Mon, 8 Mar 2021 20:20:27 +0800 Subject: [PATCH 0349/1868] drm/amdkcl: check the callback prototype of atomic_best_encoder This is caused by "drm: Pass the full state to connectors atomic functions" v5.10-rc3-1075-geca22edb37d2 Signed-off-by: Shiwu Zhang --- .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 5 ++++ .../amd/dkms/m4/drm-connector-helper-funcs.m4 | 24 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 +- 3 files changed, 30 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index b36df52efae07..9323ee8a2bb45 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -462,10 +462,15 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector) static struct drm_encoder * dm_mst_atomic_best_encoder(struct drm_connector *connector, +#ifdef HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_BEST_ENCODER_ARG_DRM_ATOMIC_STATE struct drm_atomic_state *state) { struct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state, connector); +#else + struct drm_connector_state *connector_state) +{ +#endif struct amdgpu_device *adev = drm_to_adev(connector->dev); struct amdgpu_crtc *acrtc = to_amdgpu_crtc(connector_state->crtc); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-helper-funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-helper-funcs.m4 index 148d0cc472804..c31a4f9b86b56 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-connector-helper-funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector-helper-funcs.m4 @@ -16,3 +16,27 @@ AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK], [ ]) ]) ]) + +dnl # +dnl # v5.10-rc3-1075-geca22edb37d2 +dnl # drm: Pass the full state to connectors atomic functions +dnl # +AC_DEFUN([AC_AMDGPU_CONNECTOR_HELPER_FUNCTS_ATOMIC_BEST_ENCODER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + struct drm_connector_helper_funcs *p = NULL; + p->atomic_best_encoder(NULL, (struct drm_atomic_state*)NULL); + ], [ + AC_DEFINE(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_BEST_ENCODER_ARG_DRM_ATOMIC_STATE, 1, + [atomic_best_encoder take 2nd arg type of state as struct drm_atomic_state]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_HELPER_FUNCS], [ + AC_AMDGPU_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK + AC_AMDGPU_CONNECTOR_HELPER_FUNCTS_ATOMIC_BEST_ENCODER +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index b66ac0b8eaa38..f8e43f2d8b6d1 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -120,7 +120,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS AC_AMDGPU_DRM_DP_MST_ATOMIC_CHECK AC_AMDGPU_DRM_DP_MST_ATOMIC_ENABLE_DSC - AC_AMDGPU_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK + AC_AMDGPU_DRM_CONNECTOR_HELPER_FUNCS AC_AMDGPU_DRM_DP_MST_DETECT_PORT AC_AMDGPU_STRUCT_DRM_CRTC_STATE AC_AMDGPU_DRM_DP_MST_DSC_AUX_FOR_PORT From 09fd308784a7d2e5cd5f73be4dbd0af75babb23f Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Mon, 8 Mar 2021 20:54:21 +0800 Subject: [PATCH 0350/1868] drm/amdkcl: check the callback prototype of atomic_check in drm_crtc_helper_funcs Signed-off-by: Shiwu Zhang Signed-off-by: Ma Jun Change-Id: Ie6eb721917f480b955f6187de194d4426ae0392b --- .../drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 5 +++++ .../drm/amd/dkms/m4/drm-crtc-helper-funcs.m4 | 18 ++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 24 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-crtc-helper-funcs.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c index 2e2b7e0f5897e..02880bf440741 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c @@ -627,10 +627,15 @@ static bool amdgpu_dm_crtc_helper_mode_fixup(struct drm_crtc *crtc, } static int amdgpu_dm_crtc_helper_atomic_check(struct drm_crtc *crtc, +#ifdef HAVE_DRM_CRTC_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE struct drm_atomic_state *state) { struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc); +#else + struct drm_crtc_state *crtc_state) +{ +#endif struct amdgpu_device *adev = drm_to_adev(crtc->dev); struct dc *dc = adev->dm.dc; struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-crtc-helper-funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-crtc-helper-funcs.m4 new file mode 100644 index 0000000000000..7f43ce7a2f5e2 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-crtc-helper-funcs.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit v5.2-rc2-529-g6f3b62781bbd +dnl # drm: Convert connector_helper_funcs->atomic_check to accept drm_atomic_state +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CRTC_HELPER_FUNCS_ATOMIC_CHECK], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + struct drm_crtc_helper_funcs *p = NULL; + p->atomic_check(NULL, (struct drm_atomic_state*)NULL); + ], [ + AC_DEFINE(HAVE_DRM_CRTC_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE, 1, + [drm_crtc_helper_funcs->atomic_check() wants struct drm_atomic_state arg]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index f8e43f2d8b6d1..767a572dc2b86 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -140,6 +140,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_SUBCONNECTOR AC_AMDGPU_DRM_PRIME_SG_TO_DMA_ADDR_ARRAY AC_AMDGPU_DRM_PRIME_PAGES_TO_SG + AC_AMDGPU_DRM_CRTC_HELPER_FUNCS_ATOMIC_CHECK AC_AMDGPU_DRM_MEMCPY_FROM_WC AC_AMDGPU_IS_COW_MAPPING AC_AMDGPU_VGA_REMOVE_VGACON From 7531c7d087371baa7d95923bddcb35c4c448f895 Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Wed, 24 Feb 2021 16:09:01 +0800 Subject: [PATCH 0351/1868] drm/amdkcl: wrapper the code for hmm dkms support and monitor_range related code under DISPLAY_INFO_MONITOR_RANGE This is caused by "remove unused variable from struct amdgpu_bo" and "Add Freesync HDMI support to DM" v5.9-rc5-2435-g3e6c7e19c2a5 and v5.9-rc5-2419-g1556b0c185e3 Signed-off-by: Shiwu Zhang Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 4 ++++ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++ 2 files changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h index 2775791d2761f..74cfaf0fb8fe1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h @@ -112,6 +112,10 @@ struct amdgpu_bo { /* Constant after initialization */ struct amdgpu_bo *parent; +#ifndef HAVE_AMDKCL_HMM_MIRROR_ENABLED + struct amdgpu_mn *mn; +#endif + #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED #ifdef CONFIG_MMU_NOTIFIER struct mmu_interval_notifier notifier; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 3b624a38e61b6..6f97337b2b8be 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -12409,8 +12409,10 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) freesync_capable = true; +#ifdef HAVE_DRM_DISPLAY_INFO_MONITOR_RANGE connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz; connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz; +#endif } } From b6f7a8e771847cc53d27c1bd23b8a91c0aa70dd0 Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Mon, 22 Feb 2021 18:36:34 +0800 Subject: [PATCH 0352/1868] drm/amdkcl: do not use drm middle layer for dgma debugfs This is a squash of: drm/amdkcl: simplify kcl handling of drm_mm_print() Reviewed-by: Shiwu Zhang Signed-off-by: Flora Cui drm/amdkcl: restore prev handling of drm_debug_printer() Signed-off-by: Flora Cui This is caused by "do not use drm middle layer for debugfs" v5.9-rc5-2401-g80453ffefd61 Signed-off-by: Shiwu Zhang Reviewed-by: Flora Cui Signed-off-by: Ma Jun Change-Id: Ie651234201ff972b9a49dc77d592bed663a08987 --- drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 8 +++-- drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 8 ----- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 1 - drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 4 --- drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c | 14 +++++--- drivers/gpu/drm/amd/backport/backport.h | 1 - .../amd/backport/include/kcl/kcl_amdgpu_ttm.h | 26 --------------- .../gpu/drm/amd/dkms/m4/drm-debug-printer.m4 | 16 --------- drivers/gpu/drm/amd/dkms/m4/drm-mm-print.m4 | 15 --------- drivers/gpu/drm/amd/dkms/m4/drm_print.m4 | 21 ++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 3 +- include/drm/ttm/ttm_resource.h | 4 --- include/kcl/kcl_drm_print.h | 33 +++++++++++++------ 13 files changed, 61 insertions(+), 93 deletions(-) delete mode 100644 drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_ttm.h delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-debug-printer.m4 delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-mm-print.m4 create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_print.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c index 4ae8fa6bc47f0..b9dfbfef2bc19 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c @@ -1823,12 +1823,14 @@ static int amdgpu_debugfs_vm_info_show(struct seq_file *m, void *unused) DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_test_ib); DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_vm_info); +#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_evict_vram_fops, amdgpu_debugfs_evict_vram, NULL, "%lld\n"); DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_evict_gtt_fops, amdgpu_debugfs_evict_gtt, NULL, "%lld\n"); DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_benchmark_fops, NULL, amdgpu_debugfs_benchmark, "%lld\n"); +#endif static void amdgpu_ib_preempt_fences_swap(struct amdgpu_ring *ring, struct dma_fence **fences) @@ -2123,16 +2125,18 @@ int amdgpu_debugfs_init(struct amdgpu_device *adev) amdgpu_securedisplay_debugfs_init(adev); amdgpu_fw_attestation_debugfs_init(adev); +#ifdef DEFINE_DEBUGFS_ATTRIBUTE debugfs_create_file("amdgpu_evict_vram", 0444, root, adev, &amdgpu_evict_vram_fops); debugfs_create_file("amdgpu_evict_gtt", 0444, root, adev, &amdgpu_evict_gtt_fops); + debugfs_create_file("amdgpu_benchmark", 0200, root, adev, + &amdgpu_benchmark_fops); +#endif debugfs_create_file("amdgpu_test_ib", 0444, root, adev, &amdgpu_debugfs_test_ib_fops); debugfs_create_file("amdgpu_vm_info", 0444, root, adev, &amdgpu_debugfs_vm_info_fops); - debugfs_create_file("amdgpu_benchmark", 0200, root, adev, - &amdgpu_benchmark_fops); adev->debugfs_vbios_blob.data = adev->bios; adev->debugfs_vbios_blob.size = adev->bios_size; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c index d72c5a9a85470..0760e70402ec1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c @@ -247,20 +247,12 @@ static bool amdgpu_gtt_mgr_compatible(struct ttm_resource_manager *man, * Dump the table content using printk. */ static void amdgpu_gtt_mgr_debug(struct ttm_resource_manager *man, -#if defined(HAVE_DRM_MM_PRINT) struct drm_printer *printer) -#else - const char *prefix) -#endif { struct amdgpu_gtt_mgr *mgr = to_gtt_mgr(man); spin_lock(&mgr->lock); -#if defined(HAVE_DRM_MM_PRINT) drm_mm_print(&mgr->mm, printer); -#else - drm_mm_debug_table(&mgr->mm, prefix); -#endif spin_unlock(&mgr->lock); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 3e68812420f00..60c7f12962014 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -2985,7 +2985,6 @@ DEFINE_SHOW_ATTRIBUTE(amdgpu_ttm_page_pool); DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_dgma_table); DEFINE_SHOW_ATTRIBUTE(amdgpu_mm_dgma_import_table); - /* * amdgpu_ttm_vram_read - Linear read access to VRAM * diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c index c6bd73b8ca382..7d26a962f811c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c @@ -857,11 +857,7 @@ static bool amdgpu_vram_mgr_compatible(struct ttm_resource_manager *man, * Dump the table content using printk. */ static void amdgpu_vram_mgr_debug(struct ttm_resource_manager *man, -#if defined(HAVE_DRM_MM_PRINT) struct drm_printer *printer) -#else - const char *prefix) -#endif { struct amdgpu_vram_mgr *mgr = to_vram_mgr(man); struct drm_buddy *mm = &mgr->mm; diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c index 3d690609edb8f..0c47443e0f189 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c @@ -38,15 +38,21 @@ void drm_printf(struct drm_printer *p, const char *f, ...) va_end(args); } EXPORT_SYMBOL(drm_printf); + +void __drm_printfn_seq_file(struct drm_printer *p, struct va_format *vaf) +{ + seq_printf(p->arg, "%pV", vaf); +} +EXPORT_SYMBOL(__drm_printfn_seq_file); #endif -#if !defined(HAVE_DRM_DEBUG_PRINTER) +#if !defined(HAVE_DRM_PRINTER_PREFIX) void __drm_printfn_debug(struct drm_printer *p, struct va_format *vaf) { -#if !defined(HAVE_DRM_DRM_PRINT_H) - pr_debug("%s %pV", p->prefix, vaf); +#ifndef HAVE_DRM_DRM_PRINT_H + printk(KERN_DEBUG "[" DRM_NAME ":]" "%s %pV", p->prefix, vaf); #else - pr_debug("%s %pV", "no prefix < 4.11", vaf); + printk(KERN_DEBUG "[" DRM_NAME ":]" "%s %pV", "no prefix", vaf); #endif } EXPORT_SYMBOL(__drm_printfn_debug); diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 8bf382ab0c388..a26805941e1a0 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -62,7 +62,6 @@ #include #include #include -#include "kcl/kcl_amdgpu_ttm.h" #include "kcl/kcl_amdgpu_drm_fb_helper.h" #include "kcl/kcl_amdgpu.h" #include "kcl/kcl_amdgpu_drm_drv.h" diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_ttm.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_ttm.h deleted file mode 100644 index 1c4be1340422f..0000000000000 --- a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_ttm.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -#ifndef AMDGPU_BACKPORT_KCL_AMDGPU_TTM_H -#define AMDGPU_BACKPORT_KCL_AMDGPU_TTM_H -#include -#include -#include -#include "amdgpu.h" -#include "amdgpu_ttm.h" - -#if !defined(HAVE_DRM_MM_PRINT) -extern struct drm_mm *kcl_ttm_range_res_manager_to_drm_mm(struct ttm_resource_manager *man); - -static inline struct drm_mm *kcl_ttm_get_drm_mm_by_mem_type(struct amdgpu_device *adev, unsigned char ttm_pl) -{ - if (ttm_pl == TTM_PL_TT) { - return &(adev->mman.gtt_mgr.mm); - } else if (ttm_pl == TTM_PL_VRAM) { - return &(adev->mman.vram_mgr.mm); - } else { - struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, ttm_pl); - return kcl_ttm_range_res_manager_to_drm_mm(man); - } -} -#endif - -#endif /* AMDGPU_BACKPORT_KCL_AMDGPU_TTM_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-debug-printer.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-debug-printer.m4 deleted file mode 100644 index 3fdcea368bf1e..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm-debug-printer.m4 +++ /dev/null @@ -1,16 +0,0 @@ -dnl # -dnl # commit 3d387d923c18afbacef8f14ccaa2ace2a297df74 -dnl # drm/printer: add debug printer -dnl # -AC_DEFUN([AC_AMDGPU_DRM_DEBUG_PRINTER], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - drm_debug_printer(NULL); - ], [ - AC_DEFINE(HAVE_DRM_DEBUG_PRINTER, 1, - [drm_debug_printer() function is available]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-mm-print.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-mm-print.m4 deleted file mode 100644 index 2d1d63b131ce7..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm-mm-print.m4 +++ /dev/null @@ -1,15 +0,0 @@ -dnl # -dnl # commit b5c3714fe8789745521d8351d75049b9c6a0d26b -dnl # drm/mm: Convert to drm_printer -dnl # -AC_DEFUN([AC_AMDGPU_DRM_MM_PRINT], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - drm_mm_print(NULL, NULL); - ], [ - AC_DEFINE(HAVE_DRM_MM_PRINT, 1, [drm_mm_print() is available]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_print.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_print.m4 new file mode 100644 index 0000000000000..3c4a306d53cd3 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_print.m4 @@ -0,0 +1,21 @@ +dnl # +dnl # v4.9-rc2-477-gd8187177b0b1 drm: add helper for printing to log or seq_file +dnl # +AC_DEFUN([AC_AMDGPU_DRM_PRINTER], [ + AC_KERNEL_DO_BACKGROUND([ + AS_IF([test $HAVE_DRM_DRM_PRINT_H], [ + dnl # + dnl # v4.9-rc8-1738-gb5c3714fe878 drm/mm: Convert to drm_printer + dnl # v4.9-rc8-1737-g3d387d923c18 drm/printer: add debug printer + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_printer *p = NULL; + p->prefix = NULL; + ], [ + AC_DEFINE(HAVE_DRM_PRINTER_PREFIX, 1, [drm_printer->prefix is available]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 767a572dc2b86..9793bf2fc25bf 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -85,7 +85,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU___DRM_ATOMIC_HELPER_CRTC_RESET AC_AMDGPU_DRM_DRIVER_GEM_PRIME_RES_OBJ AC_AMDGPU_DRM_DRV_GEM_PRIME_EXPORT - AC_AMDGPU_DRM_MM_PRINT + AC_AMDGPU_DRM_PRINTER AC_AMDGPU_DRM_MM_INSERT_MODE AC_AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES AC_AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL @@ -95,7 +95,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DEV_DBG AC_AMDGPU_PCI_PR3_PRESENT AC_AMDGPU_KTHREAD_USE_MM - AC_AMDGPU_DRM_DEBUG_PRINTER AC_AMDGPU_DRM_FB_HELPER_FILL_INFO AC_AMDGPU_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED AC_AMDGPU_DRM_HELPER_MODE_FILL_FB_STRUCT diff --git a/include/drm/ttm/ttm_resource.h b/include/drm/ttm/ttm_resource.h index 51f907adae150..e909fc0cba01c 100644 --- a/include/drm/ttm/ttm_resource.h +++ b/include/drm/ttm/ttm_resource.h @@ -130,12 +130,8 @@ struct ttm_resource_manager_func { * type manager to aid debugging of out-of-memory conditions. * It may not be called from within atomic context. */ -#if defined(HAVE_DRM_MM_PRINT) void (*debug)(struct ttm_resource_manager *man, struct drm_printer *printer); -#else - void (*debug)(struct ttm_resource_manager *man, const char *prefix); -#endif }; /** diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index 3ead0ab2b367f..10ba443b49303 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -29,7 +29,7 @@ #include #if !defined(HAVE_DRM_DRM_PRINT_H) -/* Copied from include/drm/drm_print.h */ +/* Copied from d8187177b0b1 include/drm/drm_print.h */ struct drm_printer { void (*printfn)(struct drm_printer *p, struct va_format *vaf); void *arg; @@ -37,28 +37,41 @@ struct drm_printer { }; void drm_printf(struct drm_printer *p, const char *f, ...); +void __drm_printfn_seq_file(struct drm_printer *p, struct va_format *vaf); +static inline struct drm_printer drm_seq_file_printer(struct seq_file *f) +{ + struct drm_printer p = { + .printfn = __drm_printfn_seq_file, + .arg = f, + }; + return p; +} #endif -/** - * drm_debug_printer - construct a &drm_printer that outputs to pr_debug() - * @prefix: debug output prefix - * - * RETURNS: - * The &drm_printer object - */ -#if !defined(HAVE_DRM_DEBUG_PRINTER) +/* Copied from 3d387d923c18 include/drm/drm_print.h */ +#if !defined(HAVE_DRM_PRINTER_PREFIX) extern void __drm_printfn_debug(struct drm_printer *p, struct va_format *vaf); static inline struct drm_printer drm_debug_printer(const char *prefix) { struct drm_printer p = { .printfn = __drm_printfn_debug, -#if !defined(HAVE_DRM_DRM_PRINT_H) +#ifndef HAVE_DRM_DRM_PRINT_H .prefix = prefix #endif }; return p; } + +static inline +void drm_mm_print(const struct drm_mm *mm, struct drm_printer *p) +{ +#ifndef HAVE_DRM_DRM_PRINT_H + drm_mm_debug_table(mm, p->prefix); +#else + drm_mm_debug_table(mm, "no prefix"); +#endif +} #endif #ifndef _DRM_PRINTK From c10c47613606deb7e9f78eb3d10a92fd887f48ca Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Tue, 23 Feb 2021 16:01:29 +0800 Subject: [PATCH 0353/1868] drm/amdkcl: fake the debugfs_create_file_size This is caused by "do not use drm middle layer for debugfs" v5.9-rc5-2401-g80453ffefd61 Signed-off-by: Shiwu Zhang Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/Makefile | 1 + .../gpu/drm/amd/amdkcl/kcl_debugfs_inode.c | 29 +++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/debugfs_inode.m4 | 13 +++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_debugfs_inode.h | 27 +++++++++++++++++ 6 files changed, 72 insertions(+) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_debugfs_inode.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/debugfs_inode.m4 create mode 100644 include/kcl/kcl_debugfs_inode.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 0791290ae716b..3a98d624be313 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -15,6 +15,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o +amdkcl-$(CONFIG_DEBUG_FS) += kcl_debugfs_inode.o CFLAGS_kcl_fence.o := -I$(src) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_debugfs_inode.c b/drivers/gpu/drm/amd/amdkcl/kcl_debugfs_inode.c new file mode 100644 index 0000000000000..5d41d1e609712 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_debugfs_inode.c @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * inode.c - part of debugfs, a tiny little debug file system + * + * Copyright (C) 2004,2019 Greg Kroah-Hartman + * Copyright (C) 2004 IBM Inc. + * Copyright (C) 2019 Linux Foundation + * + * debugfs is for people to use instead of /proc or /sys. + * See ./Documentation/core-api/kernel-api.rst for more details. + */ + +#include +#include + +/* Copied from fs/debugfs/inode.c */ +#ifndef HAVE_DEBUGFS_CREATE_FILE_SIZE +void debugfs_create_file_size(const char *name, umode_t mode, + struct dentry *parent, void *data, + const struct file_operations *fops, + loff_t file_size) +{ + struct dentry *de = debugfs_create_file(name, mode, parent, data, fops); + + if (de) + d_inode(de)->i_size = file_size; +} +EXPORT_SYMBOL_GPL(debugfs_create_file_size); +#endif diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index a26805941e1a0..2b8a6cea3b4b7 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -62,6 +62,7 @@ #include #include #include +#include #include "kcl/kcl_amdgpu_drm_fb_helper.h" #include "kcl/kcl_amdgpu.h" #include "kcl/kcl_amdgpu_drm_drv.h" diff --git a/drivers/gpu/drm/amd/dkms/m4/debugfs_inode.m4 b/drivers/gpu/drm/amd/dkms/m4/debugfs_inode.m4 new file mode 100644 index 0000000000000..3f4be7129b920 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/debugfs_inode.m4 @@ -0,0 +1,13 @@ +dnl # +dnl # commit: v3.19-rc5-12-ge59b4e9187bd +dnl # debugfs: Provide a file creation function +dnl # that also takes an initial size +AC_DEFUN([AC_AMDGPU_DEBUGFS_CREATE_FILE_SIZE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([debugfs_create_file_size], + [fs/debugfs/inode.c], [ + AC_DEFINE(HAVE_DEBUGFS_CREATE_FILE_SIZE, 1, + [debugfs_create_file_size() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 9793bf2fc25bf..6d799037c6960 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -140,6 +140,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_PRIME_SG_TO_DMA_ADDR_ARRAY AC_AMDGPU_DRM_PRIME_PAGES_TO_SG AC_AMDGPU_DRM_CRTC_HELPER_FUNCS_ATOMIC_CHECK + AC_AMDGPU_DEBUGFS_CREATE_FILE_SIZE AC_AMDGPU_DRM_MEMCPY_FROM_WC AC_AMDGPU_IS_COW_MAPPING AC_AMDGPU_VGA_REMOVE_VGACON diff --git a/include/kcl/kcl_debugfs_inode.h b/include/kcl/kcl_debugfs_inode.h new file mode 100644 index 0000000000000..a21af633d09d6 --- /dev/null +++ b/include/kcl/kcl_debugfs_inode.h @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * debugfs.h - a tiny little debug file system + * + * Copyright (C) 2004 Greg Kroah-Hartman + * Copyright (C) 2004 IBM Inc. + * + * debugfs is for people to use instead of /proc or /sys. + * See Documentation/filesystems/ for more details. + */ +#include +#include + +#ifndef HAVE_DEBUGFS_CREATE_FILE_SIZE +#ifdef CONFIG_DEBUG_FS +void debugfs_create_file_size(const char *name, umode_t mode, + struct dentry *parent, void *data, + const struct file_operations *fops, + loff_t file_size); +#else +static inline void debugfs_create_file_size(const char *name, umode_t mode, + struct dentry *parent, void *data, + const struct file_operations *fops, + loff_t file_size) +{ } +#endif +#endif From 30fe5018ada3626d60fbccf0cf32023608170a7d Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Thu, 21 Jan 2021 20:25:47 +0800 Subject: [PATCH 0354/1868] drm/amdkcl: check whether drm_display_info have monitor_range This is caused by "Report Freesync to vrr_range debugfs entry in DRM" v5.9-rc5-2241-ga5df71e584c0 squrash: 1aaf7981408b231b5125a59cdd198824af316025 drm/amdkcl: wrap code under macro HAVE_DRM_DISPLAY_INFO_MONITOR_RANGE Signed-off-by: Bob Zhou Signed-off-by: Shiwu Zhang --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 7 ++++++ .../gpu/drm/amd/dkms/m4/drm-display-info.m4 | 22 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 30 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-display-info.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 6f97337b2b8be..e2d411af962b7 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -12345,9 +12345,12 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, if (range->flags != 1) continue; + +#ifdef HAVE_DRM_DISPLAY_INFO_MONITOR_RANGE connector->display_info.monitor_range.min_vfreq = range->min_vfreq; connector->display_info.monitor_range.max_vfreq = range->max_vfreq; + if (edid->revision >= 4) { if (data->pad2 & DRM_EDID_RANGE_OFFSET_MIN_VFREQ) connector->display_info.monitor_range.min_vfreq += 255; @@ -12359,6 +12362,10 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, connector->display_info.monitor_range.min_vfreq; amdgpu_dm_connector->max_vfreq = connector->display_info.monitor_range.max_vfreq; +#else + amdgpu_dm_connector->min_vfreq = range->min_vfreq; + amdgpu_dm_connector->max_vfreq = range->max_vfreq; +#endif break; } diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-display-info.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-display-info.m4 new file mode 100644 index 0000000000000..61eef3b454776 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-display-info.m4 @@ -0,0 +1,22 @@ +dnl # +dnl # commit v5.6-rc2-1062-ga1d11d1efe4d +dnl # drm/edid: Add function to parse EDID descriptors for monitor range +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DISPLAY_INFO_MONITOR_RANGE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_display_info *info = NULL; + info->monitor_range.min_vfreq=0; + info->monitor_range.max_vfreq=0; + ],[ + AC_DEFINE(HAVE_DRM_DISPLAY_INFO_MONITOR_RANGE, 1, + [struct drm_display_info has monitor_range member]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_DRM_DISPLAY_INFO], [ + AC_AMDGPU_DRM_DISPLAY_INFO_MONITOR_RANGE +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 6d799037c6960..2fbd4125bf2dd 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -146,6 +146,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_VGA_REMOVE_VGACON AC_AMDGPU_DRM_APERTURE AC_AMDGPU_PCI_DRIVER_DEV_GROUPS + AC_AMDGPU_DRM_DISPLAY_INFO AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From d7ee97fcaf519a059117bff9281efc5204032e98 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 1 Mar 2021 15:43:59 +0800 Subject: [PATCH 0355/1868] drm/amdkcl: adapt for drm_mm_insert_node prototype change This is caused "drm/amdgpu: reserve backup pages for bad page retirment" v5.9-rc5-2461-g3a5cce0da738 Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/backport/kcl_drm_mm_backport.h | 23 ++++++++++++++++++++++ 2 files changed, 24 insertions(+) create mode 100644 include/kcl/backport/kcl_drm_mm_backport.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 2b8a6cea3b4b7..5de75456b50fb 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -63,6 +63,7 @@ #include #include #include +#include #include "kcl/kcl_amdgpu_drm_fb_helper.h" #include "kcl/kcl_amdgpu.h" #include "kcl/kcl_amdgpu_drm_drv.h" diff --git a/include/kcl/backport/kcl_drm_mm_backport.h b/include/kcl/backport/kcl_drm_mm_backport.h new file mode 100644 index 0000000000000..8c20d53ed7f4f --- /dev/null +++ b/include/kcl/backport/kcl_drm_mm_backport.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef AMDKCL_DRM_MM_H +#define AMDKCL_DRM_MM_H + +/** + * interface change in mainline kernel 4.10 + * v4.10-rc5-1060-g4e64e5539d15 drm: Improve drm_mm search (and fix topdown allocation) + * with rbtrees + */ + +#include + +#ifndef HAVE_DRM_MM_INSERT_NODE_THREE_PARAMETERS +static inline int _kcl_drm_mm_insert_node(struct drm_mm *mm, + struct drm_mm_node *node, + u64 size) +{ + return drm_mm_insert_node(mm, node, size, 0, DRM_MM_SEARCH_DEFAULT); +} +#define drm_mm_insert_node _kcl_drm_mm_insert_node +#endif /* HAVE_DRM_MM_INSERT_NODE_THREE_PARAMETERS */ + +#endif /* AMDKCL_DRM_MM_H */ From ba648b8052d2086d63a325a7bf594b9aa5a3c400 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 2 Mar 2021 15:22:04 +0800 Subject: [PATCH 0356/1868] drm/amdkcl: Replace DEFINE_SIMPLE_ATTRIBUTE with DEFINE_DEBUGFS_ATTRIBUTE This is caused by "drm/amdgpu: Replace DEFINE_SIMPLE_ATTRIBUTE with DEFINE_DEBUGFS_ATTRIBUTE" v5.9-rc5-2487-gd7ce9ec795fb Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c index b9dfbfef2bc19..c44a3e2b03625 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c @@ -2045,11 +2045,13 @@ static int amdgpu_debugfs_sclk_set(void *data, u64 val) return ret; } +#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(fops_ib_preempt, NULL, amdgpu_debugfs_ib_preempt, "%llu\n"); DEFINE_DEBUGFS_ATTRIBUTE(fops_sclk_set, NULL, amdgpu_debugfs_sclk_set, "%llu\n"); +#endif int amdgpu_debugfs_init(struct amdgpu_device *adev) { @@ -2060,6 +2062,7 @@ int amdgpu_debugfs_init(struct amdgpu_device *adev) if (!debugfs_initialized()) return 0; +#ifdef DEFINE_DEBUGFS_ATTRIBUTE debugfs_create_x32("amdgpu_smu_debug", 0600, root, &adev->pm.smu_debug_mask); @@ -2076,6 +2079,7 @@ int amdgpu_debugfs_init(struct amdgpu_device *adev) DRM_ERROR("unable to create amdgpu_set_sclk debugsfs file\n"); return PTR_ERR(ent); } +#endif /* Register debugfs entries for amdgpu_ttm */ amdgpu_ttm_debugfs_init(adev); From 2f89ee55ef1725c759c8cd7d3a996f1e0d54902c Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Tue, 5 Jan 2021 14:45:43 +0800 Subject: [PATCH 0357/1868] drm/amdkcl: add pixel format definitions for backport This is caused by "Check plane scaling against format specific hw plane caps" v5.9-rc5-2058-g9302b36fd9a0 Signed-off-by: Shiwu Zhang Reviewed-by: Flora Cui Signed-off-by: Ma Jun Change-Id: I1170bb9d453ab4b4536b1a2cf2cc4a0144a67490 --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 8 ++++++-- .../drm/amd/display/dc/resource/dcn10/dcn10_resource.c | 2 -- .../drm/amd/display/dc/resource/dcn21/dcn21_resource.c | 2 -- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 3a6ba5078d688..9cf79ad8887bf 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -797,10 +797,10 @@ static int amdgpu_dm_plane_get_plane_formats(const struct drm_plane *plane, if (plane_cap && plane_cap->pixel_format_support.nv12) formats[num_formats++] = DRM_FORMAT_NV12; -#ifdef DRM_FORMAT_P010 + if (plane_cap && plane_cap->pixel_format_support.p010) formats[num_formats++] = DRM_FORMAT_P010; -#endif + if (plane_cap && plane_cap->pixel_format_support.fp16) { formats[num_formats++] = DRM_FORMAT_XRGB16161616F; formats[num_formats++] = DRM_FORMAT_ARGB16161616F; @@ -1064,7 +1064,11 @@ static void amdgpu_dm_plane_get_min_max_dc_plane_scaling(struct drm_device *dev, /* Caps for all supported planes are the same on DCE and DCN 1 - 3 */ struct dc_plane_cap *plane_cap = &dc->caps.planes[0]; +#ifndef HAVE_DRM_FRAMEBUFFER_FORMAT + switch (fb->pixel_format) { +#else switch (fb->format->format) { +#endif case DRM_FORMAT_P010: case DRM_FORMAT_NV12: case DRM_FORMAT_NV21: diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c index 5e4daf97861fc..563c5eec83ff3 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c @@ -513,9 +513,7 @@ static const struct dc_plane_cap plane_cap = { .argb8888 = true, .nv12 = true, .fp16 = true, -#ifdef DRM_FORMAT_P010 .p010 = false -#endif }, .max_upscale_factor = { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c index ded328abd281e..347e6aaea582f 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c @@ -589,9 +589,7 @@ static const struct dc_plane_cap plane_cap = { .argb8888 = true, .nv12 = true, .fp16 = true, -#ifdef DRM_FORMAT_P010 .p010 = true -#endif }, .max_upscale_factor = { From ac8f1630c814924f9c7fc90f627f919b5cc37aeb Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Fri, 22 Jan 2021 13:04:18 +0800 Subject: [PATCH 0358/1868] drm/amdkcl: fake the PCIe 5.0 speed enum by using macro This is caused by "Add pcie gen5 support in pcie capability" v5.9-rc5-2265-g14769c60e22e Signed-off-by: Shiwu Zhang Reviewed-by: Flora Cui --- include/kcl/kcl_pci.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/kcl/kcl_pci.h b/include/kcl/kcl_pci.h index 7289493f142b2..b93c8b9e91ff0 100644 --- a/include/kcl/kcl_pci.h +++ b/include/kcl/kcl_pci.h @@ -64,9 +64,9 @@ #define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */ #endif -#ifndef PCIE_SPEED_16_0GT #define PCIE_SPEED_16_0GT 0x17 -#endif +#define PCIE_SPEED_32_0GT 0x18 + #ifndef PCI_EXP_LNKCAP2_SLS_16_0GB #define PCI_EXP_LNKCAP2_SLS_16_0GB 0x00000010 /* Supported Speed 16GT/s */ #endif From 753f69e03c6d34dc650462467ec4dee0f3059f6c Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 21 Dec 2020 13:50:14 +0800 Subject: [PATCH 0359/1868] drm/amdkcl: test drm_dp_mst_topology_cbs->destroy_connector drm_dp_mst_topology_cbs->destroy_connector() is a must before commit d29333cf5cd7 ("drm/dp_mst: Remove PDT teardown in drm_dp_destroy_port() and refactor"). otherwise kernel NULL pointer dereference jump out. Reviewed-by: Guchun Chen Reviewed-by: Aurabindo Pillai Signed-off-by: Flora Cui --- .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 37 +++++++++++++++++++ .../amd/dkms/m4/drm-dp-mst-topology-cbs.m4 | 17 +++++++++ 2 files changed, 54 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 9323ee8a2bb45..ef745d6abdfc7 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -138,11 +138,13 @@ dm_dp_mst_connector_destroy(struct drm_connector *connector) struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); +#ifndef HAVE_DRM_DP_MST_TOPOLOGY_CBS_DESTROY_CONNECTOR if (aconnector->dc_sink) { dc_link_remove_remote_sink(aconnector->dc_link, aconnector->dc_sink); dc_sink_release(aconnector->dc_sink); } +#endif kfree(aconnector->edid); @@ -796,6 +798,38 @@ static void dm_handle_mst_down_rep_msg_ready(struct drm_dp_mst_topology_mgr *mgr dm_handle_mst_sideband_msg_ready_event(mgr, DOWN_REP_MSG_RDY_EVENT); } +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_CBS_DESTROY_CONNECTOR +static void dm_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr, + struct drm_connector *connector) +{ + struct amdgpu_dm_connector *master = container_of(mgr, struct amdgpu_dm_connector, mst_mgr); + struct drm_device *dev = master->base.dev; + struct amdgpu_device *adev = drm_to_adev(dev); + struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); + + DRM_INFO("DM_MST: Disabling connector: %p [id: %d] [master: %p]\n", + aconnector, connector->base.id, aconnector->mst_port); + + if (aconnector->dc_sink) { + amdgpu_dm_update_freesync_caps(connector, NULL); + dc_link_remove_remote_sink(aconnector->dc_link, + aconnector->dc_sink); + dc_sink_release(aconnector->dc_sink); + aconnector->dc_sink = NULL; + mutex_lock(&mgr->lock); + if (!mgr->mst_state) + aconnector->dc_link->cur_link_settings.lane_count = 0; + mutex_unlock(&mgr->lock); + } + drm_connector_unregister(connector); +#ifdef HAVE_DRM_FB_HELPER_ADD_REMOVE_CONNECTORS + if (adev->mode_info.rfbdev) + drm_fb_helper_remove_one_connector(&adev->mode_info.rfbdev->helper, connector); +#endif + drm_connector_put(connector); +} +#endif + #if defined(HAVE_DRM_DP_MST_TOPOLOGY_CBS_HOTPLUG) static void dm_dp_mst_hotplug(struct drm_dp_mst_topology_mgr *mgr) { @@ -830,6 +864,9 @@ static void dm_dp_mst_register_connector(struct drm_connector *connector) static const struct drm_dp_mst_topology_cbs dm_mst_cbs = { .add_connector = dm_dp_add_mst_connector, +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_CBS_DESTROY_CONNECTOR + .destroy_connector = dm_dp_destroy_mst_connector, +#endif #if defined(HAVE_DRM_DP_MST_TOPOLOGY_CBS_HOTPLUG) .hotplug = dm_dp_mst_hotplug, #endif diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 index 5847b52020f9f..f08316600fcbd 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 @@ -34,9 +34,26 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_REGISTER_CONNECTOR], [ ]) ]) +dnl # +dnl # commit v5.6-rc5-1703-g72dc0f515913 +dnl # drm/dp_mst: Remove drm_dp_mst_topology_cbs.destroy_connector +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_DESTROY_CONNECTOR], [ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_dp_mst_topology_cbs *dp_mst_cbs = NULL; + dp_mst_cbs->destroy_connector(NULL, NULL); + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_TOPOLOGY_CBS_DESTROY_CONNECTOR, 1, + [struct drm_dp_mst_topology_cbs->destroy_connector is available]) + ]) +]) + AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS], [ AC_KERNEL_DO_BACKGROUND([ AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_HOTPLUG AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_REGISTER_CONNECTOR + AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_DESTROY_CONNECTOR ]) ]) From 1a1d61d227abc02c5a448eaa2ae8ab6284ceb000 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Wed, 20 Jan 2021 14:29:34 +0800 Subject: [PATCH 0360/1868] drm/amdkcl: Work around mmu_notifier_put issue on RHEL 8.3 The DRM backport from kernel 5.6 includes some MMU notifier changes that cause problems with the mmu_notifier_put function. The free_notifier never gets called. This leads to a leak of kfd_process structures and their doorbells. Work around this by falling back to the old method of releasing the MMU notifier and destryoing the process structure. Signed-off-by: Felix Kuehling Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- include/kcl/kcl_mn.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/kcl/kcl_mn.h b/include/kcl/kcl_mn.h index 02e80c3b4e386..f828b5dedec49 100644 --- a/include/kcl/kcl_mn.h +++ b/include/kcl/kcl_mn.h @@ -4,6 +4,12 @@ #include +/* mmu_notifier_put in the RH DRM backport from 5.6 is broken */ +#if DRM_VER == 5 && DRM_PATCH == 6 && \ + LINUX_VERSION_CODE == KERNEL_VERSION(4, 18, 0) +#undef HAVE_MMU_NOTIFIER_PUT +#endif + /* Copied from v3.16-6588-gb972216e27d1 include/linux/mmu_notifier.h */ #if !defined(HAVE_MMU_NOTIFIER_CALL_SRCU) && \ !defined(HAVE_MMU_NOTIFIER_PUT) From a5ff8e82c0ecb1314cdd2164c36942a838e06294 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 3 Feb 2021 16:22:49 +0800 Subject: [PATCH 0361/1868] drm/amdkcl: fake drm_gem_ttm_{vmap,vunmap} Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 14 +++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 18 +++++++++ drivers/gpu/drm/amd/backport/Makefile | 2 +- drivers/gpu/drm/amd/backport/backport.h | 1 + .../include/kcl/kcl_drm_gem_ttm_helper.h | 37 +++++++++++++++++ .../drm/amd/backport/kcl_drm_gem_ttm_helper.c | 40 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 7 ++++ .../drm/amd/dkms/m4/drm_gem_object_funcs.m4 | 28 +++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/header/drm/drm_gem_ttm_helper.h | 9 +++++ 10 files changed, 156 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_gem_ttm_helper.h create mode 100644 drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_gem_object_funcs.m4 create mode 100644 include/kcl/header/drm/drm_gem_ttm_helper.h diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index d331bd145790d..f06c7aea80e8c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3046,6 +3046,11 @@ static const struct drm_driver amdgpu_kms_driver = { #endif .irq_handler = amdgpu_irq_handler, .ioctls = amdgpu_ioctls_kms, +#ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK + .gem_free_object_unlocked = amdgpu_gem_object_free, + .gem_open_object = amdgpu_gem_object_open, + .gem_close_object = amdgpu_gem_object_close, +#endif .num_ioctls = ARRAY_SIZE(amdgpu_ioctls_kms), .dumb_create = amdgpu_mode_dumb_create, .dumb_map_offset = amdgpu_mode_dumb_mmap, @@ -3057,6 +3062,10 @@ static const struct drm_driver amdgpu_kms_driver = { .show_fdinfo = amdgpu_show_fdinfo, #endif +#ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK + .gem_prime_export = amdgpu_gem_prime_export, +#endif + #if defined(AMDKCL_AMDGPU_DMABUF_OPS) .gem_prime_import = amdgpu_gem_prime_import, #else @@ -3073,6 +3082,11 @@ static const struct drm_driver amdgpu_kms_driver = { .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table, #endif +#ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK + .gem_prime_vmap = drm_gem_ttm_vmap, + .gem_prime_vunmap = drm_gem_ttm_vunmap, +#endif + .gem_prime_mmap = drm_gem_prime_mmap, .name = DRIVER_NAME, .desc = DRIVER_DESC, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index 906bc0282355b..5cf5133d793a7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -43,6 +43,9 @@ #include "amdgpu_hmm.h" #include "amdgpu_xgmi.h" +#ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK +void amdgpu_gem_object_free(struct drm_gem_object *gobj) +#else static const struct drm_gem_object_funcs amdgpu_gem_object_funcs; static vm_fault_t amdgpu_gem_fault(struct vm_fault *vmf) @@ -86,6 +89,7 @@ static const struct vm_operations_struct amdgpu_gem_vm_ops = { }; static void amdgpu_gem_object_free(struct drm_gem_object *gobj) +#endif { struct amdgpu_bo *robj = gem_to_amdgpu_bo(gobj); struct amdgpu_device *adev = amdgpu_ttm_adev(robj->tbo.bdev); @@ -159,7 +163,9 @@ int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size, bo = &ubo->bo; *obj = &bo->tbo.base; +#ifndef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK (*obj)->funcs = &amdgpu_gem_object_funcs; +#endif if (initial_domain & AMDGPU_GEM_DOMAIN_DGMA) atomic64_add(size, &adev->direct_gma.vram_usage); @@ -197,8 +203,13 @@ void amdgpu_gem_force_release(struct amdgpu_device *adev) * Call from drm_gem_handle_create which appear in both new and open ioctl * case. */ +#ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK +int amdgpu_gem_object_open(struct drm_gem_object *obj, + struct drm_file *file_priv) +#else static int amdgpu_gem_object_open(struct drm_gem_object *obj, struct drm_file *file_priv) +#endif { struct amdgpu_bo *abo = gem_to_amdgpu_bo(obj); struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev); @@ -262,8 +273,13 @@ static int amdgpu_gem_object_open(struct drm_gem_object *obj, return r; } +#ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK +void amdgpu_gem_object_close(struct drm_gem_object *obj, + struct drm_file *file_priv) +#else static void amdgpu_gem_object_close(struct drm_gem_object *obj, struct drm_file *file_priv) +#endif { struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); @@ -333,6 +349,7 @@ static int amdgpu_gem_object_mmap(struct drm_gem_object *obj, struct vm_area_str return drm_gem_ttm_mmap(obj, vma); } +#ifndef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK static const struct drm_gem_object_funcs amdgpu_gem_object_funcs = { .free = amdgpu_gem_object_free, .open = amdgpu_gem_object_open, @@ -343,6 +360,7 @@ static const struct drm_gem_object_funcs amdgpu_gem_object_funcs = { .mmap = amdgpu_gem_object_mmap, .vm_ops = &amdgpu_gem_vm_ops, }; +#endif /* * GEM ioctls. diff --git a/drivers/gpu/drm/amd/backport/Makefile b/drivers/gpu/drm/amd/backport/Makefile index 8880468d474a6..115fc89f8204f 100644 --- a/drivers/gpu/drm/amd/backport/Makefile +++ b/drivers/gpu/drm/amd/backport/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: MIT -BACKPORT_OBJS := kcl_drm_drv.o +BACKPORT_OBJS := kcl_drm_drv.o kcl_drm_gem_ttm_helper.o amdgpu-y += $(addprefix ../backport/,$(BACKPORT_OBJS)) diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 5de75456b50fb..c9f88d77262d6 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -67,6 +67,7 @@ #include "kcl/kcl_amdgpu_drm_fb_helper.h" #include "kcl/kcl_amdgpu.h" #include "kcl/kcl_amdgpu_drm_drv.h" +#include "kcl/kcl_drm_gem_ttm_helper.h" #include "kcl/kcl_drm_aperture.h" #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_gem_ttm_helper.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_gem_ttm_helper.h new file mode 100644 index 0000000000000..10d002f55b191 --- /dev/null +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_gem_ttm_helper.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* Copied from include/drm/drm_gem_ttm_helper.h */ + +#ifndef _KCL_KCL_DRM_GEM_TTM_HELPER_H_H +#define _KCL_KCL_DRM_GEM_TTM_HELPER_H_H + +#include + +#ifndef HAVE_DRM_GEM_TTM_VMAP +void _kcl_drm_gem_ttm_vunmap(struct drm_gem_object *gem, + void *vaddr); + +void *_kcl_drm_gem_ttm_vmap(struct drm_gem_object *obj); + +static inline +void drm_gem_ttm_vunmap(struct drm_gem_object *gem, + void *vaddr) +{ + _kcl_drm_gem_ttm_vunmap(gem, vaddr); +} + +static inline +void *drm_gem_ttm_vmap(struct drm_gem_object *obj) +{ + return _kcl_drm_gem_ttm_vmap(obj); +} +#endif + +#ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK +void amdgpu_gem_object_free(struct drm_gem_object *obj); +int amdgpu_gem_object_open(struct drm_gem_object *obj, + struct drm_file *file_priv); +void amdgpu_gem_object_close(struct drm_gem_object *obj, + struct drm_file *file_priv); +#endif + +#endif diff --git a/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c b/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c new file mode 100644 index 0000000000000..ef1c82463f8e0 --- /dev/null +++ b/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +#include + +#include +#include +#include +#include +#include +#include + +#ifndef drm_gem_ttm_of_gem +#define drm_gem_ttm_of_gem(gem_obj) \ + container_of(gem_obj, struct ttm_buffer_object, base) +#endif + +#ifndef HAVE_DRM_GEM_TTM_VMAP +void *_kcl_drm_gem_ttm_vmap(struct drm_gem_object *obj) +{ + struct ttm_buffer_object *bo = drm_gem_ttm_of_gem(obj); + struct dma_buf_map map; + + ttm_bo_vmap(bo, &map); + return map.vaddr; +} +EXPORT_SYMBOL(_kcl_drm_gem_ttm_vmap); + +void _kcl_drm_gem_ttm_vunmap(struct drm_gem_object *gem, + void *vaddr) +{ + struct ttm_buffer_object *bo = drm_gem_ttm_of_gem(gem); + struct dma_buf_map map; + + map.vaddr = vaddr; + map.is_iomem = bo->mem.bus.is_iomem; + + ttm_bo_vunmap(bo, &map); +} +EXPORT_SYMBOL(_kcl_drm_gem_ttm_vunmap); +#endif diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index 16ebd93fc3ea8..1f21aec4ff2ee 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -39,6 +39,13 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # AC_KERNEL_CHECK_HEADERS([drm/drm_managed.h]) + dnl # + dnl # v5.3-rc1-623-gff540b76f14a + dnl # drm/ttm: add drm gem ttm helpers, + dnl # starting with drm_gem_ttm_print_info() + dnl # + AC_KERNEL_CHECK_HEADERS([drm/drm_gem_ttm_helper.h]) + dnl # dnl # v5.12-rc3-330-g2916059147ea dnl # drm/aperture: Add infrastructure for aperture ownership diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_gem_object_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_gem_object_funcs.m4 new file mode 100644 index 0000000000000..353a678db52d7 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_gem_object_funcs.m4 @@ -0,0 +1,28 @@ +dnl # +dnl # commit v4.9-rc8-1739-g6d1b81d8e25d +dnl # drm: add crtc helper drm_crtc_from_index() +dnl # commit v5.9-rc5-1077-gd693def4fd1c +dnl # drm: Remove obsolete GEM and PRIME callbacks from struct drm_driver +dnl # +AC_DEFUN([AC_AMDGPU_DRM_GEM_TTM_VMAP], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([drm_gem_ttm_vmap], [drivers/gpu/drm/drm_gem_ttm_helper.c], [ + AC_DEFINE(HAVE_DRM_GEM_TTM_VMAP, 1, [drm_gem_ttm_vmap() is available]) + ],[ + AC_KERNEL_TRY_COMPILE([ + struct vm_area_struct; + #ifdef HAVE_DRM_DRMP_H + #include + #else + #include + #endif + ],[ + struct drm_driver *drv = NULL; + drv->gem_open_object = NULL; + ],[ + AC_DEFINE(HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK, 1, + [drm_gem_open_object is defined in struct drm_drv]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 2fbd4125bf2dd..e8a9e41f1efb7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -141,6 +141,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_PRIME_PAGES_TO_SG AC_AMDGPU_DRM_CRTC_HELPER_FUNCS_ATOMIC_CHECK AC_AMDGPU_DEBUGFS_CREATE_FILE_SIZE + AC_AMDGPU_DRM_GEM_TTM_VMAP AC_AMDGPU_DRM_MEMCPY_FROM_WC AC_AMDGPU_IS_COW_MAPPING AC_AMDGPU_VGA_REMOVE_VGACON diff --git a/include/kcl/header/drm/drm_gem_ttm_helper.h b/include/kcl/header/drm/drm_gem_ttm_helper.h new file mode 100644 index 0000000000000..1f4610148dd07 --- /dev/null +++ b/include/kcl/header/drm/drm_gem_ttm_helper.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DRM_VBLANK_H_H_ +#define _KCL_HEADER_DRM_VBLANK_H_H_ + +#ifdef HAVE_DRM_DRM_DRM_GEM_TTM_HELPER_H +#include_next +#endif + +#endif From ef88da4452cc07d607902f889a3da57e73285ff2 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 4 Feb 2021 15:18:44 +0800 Subject: [PATCH 0362/1868] drm/amdkcl: refactor test for ktime_get_real_seconds Reviewed-by: Guchun Chen Signed-off-by: Flora Cui --- .../drm/amd/dkms/m4/ktime-get-real-seconds.m4 | 42 +++++++------------ 1 file changed, 14 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/ktime-get-real-seconds.m4 b/drivers/gpu/drm/amd/dkms/m4/ktime-get-real-seconds.m4 index 53fe6c0af4523..6ba2dff0aca08 100644 --- a/drivers/gpu/drm/amd/dkms/m4/ktime-get-real-seconds.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/ktime-get-real-seconds.m4 @@ -1,34 +1,20 @@ -dnl # -dnl # commit dbe7aa622db96b5cd601f59d09c4f00b98b76079 -dnl # timekeeping: Provide y2038 safe accessor to the seconds portion of CLOCK_REALTIME -dnl # -AC_DEFUN([AC_AMDGPU_KTIME_GET_REAL_SECONDS_REAL], [ - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include - #include - ],[ - ktime_get_real_seconds(); - ],[ktime_get_real_seconds],[kernel/time/timekeeping.c],[ - AC_DEFINE(HAVE_KTIME_GET_REAL_SECONDS, 1, - [ktime_get_real_seconds() is available]) - ]) -]) - AC_DEFUN([AC_AMDGPU_KTIME_GET_REAL_SECONDS], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drm_backport.h], [ - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - ktime_get_real_seconds(); - ], [ - AC_DEFINE(HAVE_KTIME_GET_REAL_SECONDS, 1, - [ktime_get_real_seconds() is available in drm_backport.h]) - ], [ - AC_AMDGPU_KTIME_GET_REAL_SECONDS_REAL - ]) + dnl # + dnl # commit dbe7aa622db96b5cd601f59d09c4f00b98b76079 + dnl # timekeeping: Provide y2038 safe accessor to the seconds portion of CLOCK_REALTIME + dnl # + AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DRM_BACKPORT_H + #include + #endif + #include + #include + ], [ + ktime_get_real_seconds(); ], [ - AC_AMDGPU_KTIME_GET_REAL_SECONDS_REAL + AC_DEFINE(HAVE_KTIME_GET_REAL_SECONDS, 1, + [ktime_get_real_seconds() is available]) ]) ]) ]) From 177c595759f8c523220632d8c6297a0c7a9c92b6 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 5 Feb 2021 10:57:32 +0800 Subject: [PATCH 0363/1868] drm/amdkcl: refactor test for drm_driver_feature Reviewed-by: Shiwu Zhang Signed-off-by: Flora Cui --- .../gpu/drm/amd/dkms/m4/drm-driver-feature.m4 | 59 ++++++++++--------- 1 file changed, 31 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-driver-feature.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-driver-feature.m4 index 0970897b2338a..d10e0fcde3942 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-driver-feature.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-driver-feature.m4 @@ -8,16 +8,15 @@ AC_DEFUN([AC_AMDGPU_DRM_DRIVER_FEATURE], [ dnl # drm: introduce a capability flag for syncobj timeline support dnl # AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drmP.h], [ - AC_KERNEL_TRY_COMPILE([ - #include - ],[ - int _ = DRIVER_SYNCOBJ_TIMELINE; - ],[ - AC_DEFINE(HAVE_DRM_DRV_DRIVER_SYNCOBJ_TIMELINE, 1, [ - drm_driver_feature DRIVER_SYNCOBJ_TIMELINE is available]) - ]) - ], [ + AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DRMP_H + struct vm_area_struct; + #include + #endif + #include + ],[ + int _ = DRIVER_SYNCOBJ_TIMELINE; + ],[ AC_DEFINE(HAVE_DRM_DRV_DRIVER_SYNCOBJ_TIMELINE, 1, [ drm_driver_feature DRIVER_SYNCOBJ_TIMELINE is available]) ]) @@ -28,15 +27,17 @@ AC_DEFUN([AC_AMDGPU_DRM_DRIVER_FEATURE], [ dnl # drm/irq: Ditch DRIVER_IRQ_SHARED dnl # AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drmP.h], [ - AC_KERNEL_TRY_COMPILE([ - #include - ],[ - int _ = DRIVER_IRQ_SHARED; - ],[ - AC_DEFINE(HAVE_DRM_DRV_DRIVER_IRQ_SHARED, 1, [ - drm_driver_feature DRIVER_IRQ_SHARED is available]) - ]) + AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DRMP_H + struct vm_area_struct; + #include + #endif + #include + ],[ + int _ = DRIVER_IRQ_SHARED; + ],[ + AC_DEFINE(HAVE_DRM_DRV_DRIVER_IRQ_SHARED, 1, [ + drm_driver_feature DRIVER_IRQ_SHARED is available]) ]) ]) @@ -45,15 +46,17 @@ AC_DEFUN([AC_AMDGPU_DRM_DRIVER_FEATURE], [ dnl # drm/prime: Actually remove DRIVER_PRIME everywhere dnl # AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drmP.h], [ - AC_KERNEL_TRY_COMPILE([ - #include - ],[ - int _ = DRIVER_PRIME; - ],[ - AC_DEFINE(HAVE_DRM_DRV_DRIVER_PRIME, 1, [ - drm_driver_feature DRIVER_PRIME is available]) - ]) + AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DRMP_H + struct vm_area_struct; + #include + #endif + #include + ],[ + int _ = DRIVER_PRIME; + ],[ + AC_DEFINE(HAVE_DRM_DRV_DRIVER_PRIME, 1, [ + drm_driver_feature DRIVER_PRIME is available]) ]) ]) ]) From a4ee67fb59ceb03def2500b1ffd2b15756b36293 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 5 Feb 2021 11:20:01 +0800 Subject: [PATCH 0364/1868] drm/amdkcl: refactor test for drm_device Reviewed-by: Shiwu Zhang Signed-off-by: Flora Cui --- .../gpu/drm/amd/dkms/m4/struct_drm_device.m4 | 26 ++++++++++--------- 1 file changed, 14 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_device.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_device.m4 index 7016ff6694c88..7ea0061caa47e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/struct_drm_device.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_device.m4 @@ -3,14 +3,16 @@ dnl # commit v4.19-rc1-194-g18ace11f87e6 dnl # drm: Introduce per-device driver_features dnl # AC_DEFUN([AC_AMDGPU_DRM_DEVICE_DRIVER_FEATURES], [ - AC_KERNEL_TRY_COMPILE([ - #include - ],[ - struct drm_device *ddev = NULL; - ddev->driver_features = 0; - ],[ - AC_DEFINE(HAVE_DRM_DEVICE_DRIVER_FEATURES, 1, - [dev_device->driver_features is available]) + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_device *ddev = NULL; + ddev->driver_features = 0; + ],[ + AC_DEFINE(HAVE_DRM_DEVICE_DRIVER_FEATURES, 1, + [dev_device->driver_features is available]) + ]) ]) ]) @@ -19,6 +21,7 @@ dnl # commit v5.5-rc2-1419-g7e13ad896484 dnl # drm: Avoid drm_global_mutex for simple inc/dec of dev->open_count dnl # AC_DEFUN([AC_AMDGPU_DRM_DEVICE_OPEN_COUNT], [ + AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ #include ],[ @@ -28,11 +31,10 @@ AC_DEFUN([AC_AMDGPU_DRM_DEVICE_OPEN_COUNT], [ AC_DEFINE(HAVE_DRM_DEVICE_OPEN_COUNT_INT, 1, [drm_device->open_count is int]) ]) + ]) ]) AC_DEFUN([AC_AMDGPU_STRUCT_DRM_DEVICE], [ - AC_KERNEL_DO_BACKGROUND([ - AC_AMDGPU_DRM_DEVICE_DRIVER_FEATURES - AC_AMDGPU_DRM_DEVICE_OPEN_COUNT - ]) + AC_AMDGPU_DRM_DEVICE_DRIVER_FEATURES + AC_AMDGPU_DRM_DEVICE_OPEN_COUNT ]) From 246d4f67598835c79448c355f5acd95eb44f134e Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 5 Feb 2021 11:24:09 +0800 Subject: [PATCH 0365/1868] drm/amdkcl: refactor test for drm_framebuffer Reviewed-by: Shiwu Zhang Signed-off-by: Flora Cui --- .../drm/amd/dkms/m4/drm-framebuffer-format.m4 | 20 +++++++++---------- 1 file changed, 9 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-framebuffer-format.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-framebuffer-format.m4 index 977ed577e27c8..5a219b26d81bb 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-framebuffer-format.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-framebuffer-format.m4 @@ -4,17 +4,15 @@ dnl # drm: Store a pointer to drm_format_info under drm_framebuffer dnl # AC_DEFUN([AC_AMDGPU_DRM_FRAMEBUFFER_FORMAT], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drmP.h], [ - AC_KERNEL_TRY_COMPILE([ - #include - #include - ], [ - struct drm_framebuffer *foo = NULL; - foo->format = NULL; - ], [ - AC_DEFINE(HAVE_DRM_FRAMEBUFFER_FORMAT, 1, - [whether struct drm_framebuffer have format]) - ]) + AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DRMP_H + struct vm_area_struct; + #include + #endif + #include + ], [ + struct drm_framebuffer *foo = NULL; + foo->format = NULL; ], [ AC_DEFINE(HAVE_DRM_FRAMEBUFFER_FORMAT, 1, [whether struct drm_framebuffer have format]) From a8abb5021eeec7e237e60f75c905e30f7b15508e Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Sun, 7 Feb 2021 11:34:46 +0800 Subject: [PATCH 0366/1868] drm/amdkcl: refactor test for drm/drm_audio_component.h Reviewed-by: Shiwu Zhang Signed-off-by: Flora Cui --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 18 ------------------ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 4 ---- .../amd/dkms/m4/drm-audio-component-header.m4 | 9 --------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - 4 files changed, 32 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-audio-component-header.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index e2d411af962b7..4ac3517b21b68 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -80,9 +80,7 @@ #include #include -#if defined(HAVE_DRM_AUDIO_COMPONENT_HEADER) #include -#endif #include #include @@ -97,9 +95,7 @@ #include #include #include -#if defined(HAVE_DRM_AUDIO_COMPONENT_HEADER) #include -#endif #include #ifdef CONFIG_DRM_AMD_DC_HDCP #include @@ -1001,7 +997,6 @@ static void amdgpu_dm_fbc_init(struct drm_connector *connector) } -#if defined(HAVE_DRM_AUDIO_COMPONENT_HEADER) static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port, int pipe, bool *enabled, unsigned char *buf, int max_bytes) @@ -1144,7 +1139,6 @@ static void amdgpu_dm_audio_eld_notify(struct amdgpu_device *adev, int pin) pin, -1); } } -#endif static int dm_dmub_hw_init(struct amdgpu_device *adev) { @@ -1790,9 +1784,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) mutex_init(&adev->dm.dpia_aux_lock); mutex_init(&adev->dm.dc_lock); -#if defined(HAVE_DRM_AUDIO_COMPONENT_HEADER) mutex_init(&adev->dm.audio_lock); -#endif if (amdgpu_dm_irq_init(adev)) { DRM_ERROR("amdgpu: failed to initialize DM IRQ support.\n"); @@ -2164,9 +2156,7 @@ static void amdgpu_dm_fini(struct amdgpu_device *adev) adev->dm.freesync_module = NULL; } -#if defined(HAVE_DRM_AUDIO_COMPONENT_HEADER) mutex_destroy(&adev->dm.audio_lock); -#endif mutex_destroy(&adev->dm.dc_lock); mutex_destroy(&adev->dm.dpia_aux_lock); } @@ -4526,14 +4516,12 @@ static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) } #endif -#if defined(HAVE_DRM_AUDIO_COMPONENT_HEADER) r = amdgpu_dm_audio_init(adev); if (r) { dc_state_release(state->context); kfree(state); return r; } -#endif return 0; } @@ -8201,9 +8189,7 @@ void amdgpu_dm_connector_init_helper(struct amdgpu_display_manager *dm, aconnector->base.stereo_allowed = false; aconnector->base.dpms = DRM_MODE_DPMS_OFF; aconnector->hpd.hpd = AMDGPU_HPD_NONE; /* not used */ -#if defined(HAVE_DRM_AUDIO_COMPONENT_HEADER) aconnector->audio_inst = -1; -#endif aconnector->pack_sdp_v1_3 = false; aconnector->as_type = ADAPTIVE_SYNC_TYPE_NONE; memset(&aconnector->vsdb_info, 0, sizeof(aconnector->vsdb_info)); @@ -9388,7 +9374,6 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, kfree(bundle); } -#if defined(HAVE_DRM_AUDIO_COMPONENT_HEADER) static void amdgpu_dm_commit_audio(struct drm_device *dev, struct drm_atomic_state *state) { @@ -9469,7 +9454,6 @@ static void amdgpu_dm_commit_audio(struct drm_device *dev, amdgpu_dm_audio_eld_notify(adev, inst); } } -#endif /* * amdgpu_dm_crtc_copy_transient_flags - copy mirrored flags from DRM to DC @@ -10150,10 +10134,8 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) acrtc->wb_enabled = true; } -#if defined(HAVE_DRM_AUDIO_COMPONENT_HEADER) /* Update audio instances for each connector. */ amdgpu_dm_commit_audio(dev, state); -#endif /* restore the backlight level */ for (i = 0; i < dm->num_of_edps; i++) { diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index c501090d47551..d360ef5618df3 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -429,7 +429,6 @@ struct amdgpu_display_manager { */ struct mutex dc_lock; -#if defined(HAVE_DRM_AUDIO_COMPONENT_HEADER) /** * @audio_lock: * @@ -451,7 +450,6 @@ struct amdgpu_display_manager { * successfully, false otherwise. */ bool audio_registered; -#endif /** * @irq_handler_list_low_tab: @@ -750,10 +748,8 @@ struct amdgpu_dm_connector { */ int max_vfreq ; -#if defined(HAVE_DRM_AUDIO_COMPONENT_HEADER) /* Audio instance - protected by audio_lock. */ int audio_inst; -#endif struct mutex hpd_lock; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-audio-component-header.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-audio-component-header.m4 deleted file mode 100644 index 520d72bebcb5c..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm-audio-component-header.m4 +++ /dev/null @@ -1,9 +0,0 @@ -AC_DEFUN([AC_AMDGPU_DRM_AUDIO_COMPONENT_HEADER], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drm_audio_component.h], [ - AC_DEFINE(HAVE_DRM_AUDIO_COMPONENT_HEADER, 1, - [whether drm/drm_audio_component.h is defined]) - ]) - ]) -]) - diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index e8a9e41f1efb7..ef394c8b0e3cb 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -51,7 +51,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_MM_RELEASE_PAGES AC_AMDGPU_SCHED_SET_FIFO_LOW AC_AMDGPU_DMA_FENCE_HEADERS - AC_AMDGPU_DRM_AUDIO_COMPONENT_HEADER AC_AMDGPU_DMA_RESV AC_AMDGPU_TTM_SG_TT_INIT AC_AMDGPU_TTM_BUFFER_OBJECT From 3cecd77d3492369a6a6540695907b31abdca3879 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Sun, 7 Feb 2021 11:41:06 +0800 Subject: [PATCH 0367/1868] drm/amdkcl: refactor test for drm_debug_enabled Reviewed-by: Shiwu Zhang Signed-off-by: Flora Cui --- .../gpu/drm/amd/dkms/m4/drm_debug_enabled.m4 | 20 +++++++++---------- 1 file changed, 9 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_debug_enabled.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_debug_enabled.m4 index 0baf031bd2e3d..0250d30115d15 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_debug_enabled.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_debug_enabled.m4 @@ -3,17 +3,15 @@ dnl # commit v5.3-rc1-708-gf0a8f533adc2 dnl # drm/print: add drm_debug_enabled() dnl # AC_DEFUN([AC_AMDGPU_DRM_DEBUG_ENABLED], [ - AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drm_print.h], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ],[ - drm_debug_enabled(0); - ],[ - AC_DEFINE(HAVE_DRM_DEBUG_ENABLED, - 1, - [drm_debug_enabled() is available]) - ]) + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + drm_debug_enabled(0); + ],[ + AC_DEFINE(HAVE_DRM_DEBUG_ENABLED, + 1, + [drm_debug_enabled() is available]) ]) ]) ]) From 0e72578cb54c01fd2ed6de8ce651ef9fc198de59 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Sun, 7 Feb 2021 13:50:01 +0800 Subject: [PATCH 0368/1868] drm/amdkcl: refactor drm-fb-helper-xxx Reviewed-by: Shiwu Zhang Signed-off-by: Flora Cui --- .../amd/dkms/m4/drm-fb-helper-fill-info.m4 | 18 +++-- ...per-remove-conflicting-pci-framebuffers.m4 | 69 +++++++++---------- .../m4/drm-fb-helper-set-suspend-unlocked.m4 | 18 +++-- 3 files changed, 50 insertions(+), 55 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-fill-info.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-fill-info.m4 index 23832e30bd48e..bf7fcc83d14df 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-fill-info.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-fill-info.m4 @@ -4,16 +4,14 @@ dnl # drm/fb-helper: Fixup fill_info cleanup dnl # AC_DEFUN([AC_AMDGPU_DRM_FB_HELPER_FILL_INFO], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drmP.h], [ - AC_KERNEL_TRY_COMPILE([ - #include - #include - ], [ - drm_fb_helper_fill_info(NULL, NULL, NULL); - ], [ - AC_DEFINE(HAVE_DRM_FB_HELPER_FILL_INFO, 1, - [drm_fb_helper_fill_info() is available]) - ]) + AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DRMP_H + struct vm_area_struct; + #include + #endif + #include + ], [ + drm_fb_helper_fill_info(NULL, NULL, NULL); ], [ AC_DEFINE(HAVE_DRM_FB_HELPER_FILL_INFO, 1, [drm_fb_helper_fill_info() is available]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-remove-conflicting-pci-framebuffers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-remove-conflicting-pci-framebuffers.m4 index fe519aa4941d2..ec30c7ffa874c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-remove-conflicting-pci-framebuffers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-remove-conflicting-pci-framebuffers.m4 @@ -4,54 +4,53 @@ dnl # fbdev: drop res_id parameter from remove_conflicting_pci_framebuffers dnl # AC_DEFUN([AC_AMDGPU_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drmP.h], [ + AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DRMP_H + struct vm_area_struct; + #include + #endif + #include + ], [ + drm_fb_helper_remove_conflicting_pci_framebuffers(NULL, NULL); + ], [ + AC_DEFINE(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP, 1, + [drm_fb_helper_remove_conflicting_pci_framebuffers() wants p,p args]) + AC_DEFINE(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS, 1, + [drm_fb_helper_remove_conflicting_pci_framebuffers() is available]) + ], [ + dnl # + dnl # commit v4.19-rc1-110-g4d18975c78f2 + dnl # Author: Michał Mirosław + dnl # Date: Sat Sep 1 16:08:45 2018 +0200 + dnl # fbdev: add remove_conflicting_pci_framebuffers() + dnl # AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DRMP_H + struct vm_area_struct; #include + #endif #include ], [ - drm_fb_helper_remove_conflicting_pci_framebuffers(NULL, NULL); + drm_fb_helper_remove_conflicting_pci_framebuffers(NULL, 0, NULL); ], [ - AC_DEFINE(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP, 1, - [drm_fb_helper_remove_conflicting_pci_framebuffers() wants p,p args]) + AC_DEFINE(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PIP, 1, + [drm_fb_helper_remove_conflicting_pci_framebuffers() wants p,i,p args]) AC_DEFINE(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS, 1, [drm_fb_helper_remove_conflicting_pci_framebuffers() is available]) ], [ dnl # - dnl # commit v4.19-rc1-110-g4d18975c78f2 - dnl # Author: Michał Mirosław - dnl # Date: Sat Sep 1 16:08:45 2018 +0200 - dnl # fbdev: add remove_conflicting_pci_framebuffers() + dnl # commit 46eeb2c144956e88197439b5ee5cf221a91b0a81 + dnl # video/fb: Propagate error code from failing to unregister conflicting fb dnl # - AC_KERNEL_TRY_COMPILE([ - #include - #include + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include ], [ - drm_fb_helper_remove_conflicting_pci_framebuffers(NULL, 0, NULL); - ], [ - AC_DEFINE(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PIP, 1, - [drm_fb_helper_remove_conflicting_pci_framebuffers() wants p,i,p args]) - AC_DEFINE(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS, 1, - [drm_fb_helper_remove_conflicting_pci_framebuffers() is available]) - ], [ - dnl # - dnl # commit 46eeb2c144956e88197439b5ee5cf221a91b0a81 - dnl # video/fb: Propagate error code from failing to unregister conflicting fb - dnl # - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include - ], [ - int ret = remove_conflicting_framebuffers(NULL, NULL, false); - ], [remove_conflicting_framebuffers], [drivers/video/fbdev/core/fbmem.c], [ - AC_DEFINE(HAVE_REMOVE_CONFLICTING_FRAMEBUFFERS_RETURNS_INT, 1, - [remove_conflicting_framebuffers() returns int]) - ]) + int ret = remove_conflicting_framebuffers(NULL, NULL, false); + ], [remove_conflicting_framebuffers], [drivers/video/fbdev/core/fbmem.c], [ + AC_DEFINE(HAVE_REMOVE_CONFLICTING_FRAMEBUFFERS_RETURNS_INT, 1, + [remove_conflicting_framebuffers() returns int]) ]) ]) - ], [ - AC_DEFINE(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP, 1, - [drm_fb_helper_remove_conflicting_pci_framebuffers() wants p,p args]) - AC_DEFINE(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS, 1, - [drm_fb_helper_remove_conflicting_pci_framebuffers() is available]) ]) ]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-set-suspend-unlocked.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-set-suspend-unlocked.m4 index cd00b4a9ac55c..c2502e2f914da 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-set-suspend-unlocked.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-set-suspend-unlocked.m4 @@ -4,16 +4,14 @@ dnl # drm/fb-helper: Add drm_fb_helper_set_suspend_unlocked() dnl # AC_DEFUN([AC_AMDGPU_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drmP.h], [ - AC_KERNEL_TRY_COMPILE([ - #include - #include - ], [ - drm_fb_helper_set_suspend_unlocked(NULL,0); - ], [ - AC_DEFINE(HAVE_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED, 1, - [drm_fb_helper_set_suspend_unlocked() is available]) - ]) + AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DRMP_H + struct vm_area_struct; + #include + #endif + #include + ], [ + drm_fb_helper_set_suspend_unlocked(NULL,0); ], [ AC_DEFINE(HAVE_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED, 1, [drm_fb_helper_set_suspend_unlocked() is available]) From bfb213a9a1bcc9e1a7af3d752650062dff713a26 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Sun, 7 Feb 2021 17:20:33 +0800 Subject: [PATCH 0369/1868] drm/amdkcl: rework test for drm_calc_vbltimestamp_from_scanoutpos Reviewed-by: Guchun Chen Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 58 ------------ .../drm/amd/backport/include/kcl/kcl_amdgpu.h | 89 ++++++------------ .../drm-calc-vbltimestamp-from-scanoutpos.m4 | 58 ------------ .../drm_calc_vbltimestamp_from_scanoutpos.m4 | 58 ++++++++++++ ...t-scanout-position-in-struct-drm-driver.m4 | 94 ------------------- ...t-vblank-timestamp-in-struct-drm-driver.m4 | 68 -------------- .../drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 | 2 - 7 files changed, 87 insertions(+), 340 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-calc-vbltimestamp-from-scanoutpos.m4 create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_calc_vbltimestamp_from_scanoutpos.m4 delete mode 100644 drivers/gpu/drm/amd/dkms/m4/get-scanout-position-in-struct-drm-driver.m4 delete mode 100644 drivers/gpu/drm/amd/dkms/m4/get-vblank-timestamp-in-struct-drm-driver.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index 744b1fe63ee1e..3d8aab004d934 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -1628,64 +1628,6 @@ void amdgpu_disable_vblank_kms(struct drm_crtc *crtc) amdgpu_irq_put(adev, &adev->crtc_irq, idx); } -#ifndef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP -#if !defined(HAVE_DRM_CALC_VBLTIMESTAMP_FROM_SCANOUTPOS_USE_KTIMER_T_ARG) -/** - * amdgpu_get_vblank_timestamp_kms - get vblank timestamp - * - * @dev: drm dev pointer - * @crtc: crtc to get the timestamp for - * @max_error: max error - * @vblank_time: time value - * @flags: flags passed to the driver - * - * Gets the timestamp on the requested crtc based on the - * scanout position. (all asics). - * Returns postive status flags on success, negative error on failure. - */ -int amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, - int *max_error, - struct timeval *vblank_time, - unsigned flags) -{ - struct drm_crtc *crtc; - struct amdgpu_device *adev = drm_to_adev(dev); - - if (pipe >= dev->num_crtcs) { - DRM_ERROR("Invalid crtc %u\n", pipe); - return -EINVAL; - } - - /* Get associated drm_crtc: */ - crtc = &adev->mode_info.crtcs[pipe]->base; - if (!crtc) { - /* This can occur on driver load if some component fails to - * initialize completely and driver is unloaded */ - DRM_ERROR("Uninitialized crtc %d\n", pipe); - return -EINVAL; - } - - /* Helper routine in DRM core does all the work: */ -#if defined(HAVE_DRM_CALC_VBLTIMESTAMP_FROM_SCANOUTPOS_DROP_MOD_ARG) - return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, - vblank_time, flags); -#elif defined(HAVE_DRM_CALC_VBLTIMESTAMP_FROM_SCANOUTPOS_HAVE_MODE_ARG) - return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, - vblank_time, flags, - &crtc->hwmode); -#elif defined(HAVE_DRM_CALC_VBLTIMESTAMP_FROM_SCANOUTPOS_HAVE_CRTC_MODE_ARG) - return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, - vblank_time, flags, - crtc, &crtc->hwmode); -#else - return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, - vblank_time, flags, - crtc); -#endif -} -#endif -#endif - /* * Debugfs info */ diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h index 5c6fe94ccd030..383d7ec209af1 100644 --- a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h @@ -7,41 +7,28 @@ #include #ifndef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP - -#if defined(HAVE_VGA_USE_UNSIGNED_INT_PIPE) static inline u32 kcl_amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int crtc) -#else -static inline u32 kcl_amdgpu_get_vblank_counter_kms(struct drm_device *dev, int crtc) -#endif { struct drm_crtc *drm_crtc = drm_crtc_from_index(dev, crtc); return amdgpu_get_vblank_counter_kms(drm_crtc); } -#if defined(HAVE_VGA_USE_UNSIGNED_INT_PIPE) static inline int kcl_amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int crtc) -#else -static inline int kcl_amdgpu_enable_vblank_kms(struct drm_device *dev, int crtc) -#endif { struct drm_crtc *drm_crtc = drm_crtc_from_index(dev, crtc); return amdgpu_enable_vblank_kms(drm_crtc); } -#if defined(HAVE_VGA_USE_UNSIGNED_INT_PIPE) static inline void kcl_amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int crtc) -#else -static inline void kcl_amdgpu_disable_vblank_kms(struct drm_device *dev, int crtc) -#endif { struct drm_crtc *drm_crtc = drm_crtc_from_index(dev, crtc); return amdgpu_disable_vblank_kms(drm_crtc); } -#if defined(HAVE_GET_SCANOUT_POSITION_RETURN_BOOL) +#if defined(HAVE_DRM_DRIVER_GET_SCANOUT_POSITION_RETURN_BOOL) static inline bool kcl_amdgpu_get_crtc_scanout_position(struct drm_device *dev, unsigned int pipe, bool in_vblank_irq, int *vpos, int *hpos, ktime_t *stime, ktime_t *etime, @@ -49,75 +36,57 @@ static inline bool kcl_amdgpu_get_crtc_scanout_position(struct drm_device *dev, { return !!amdgpu_display_get_crtc_scanoutpos(dev, pipe, in_vblank_irq, vpos, hpos, stime, etime, mode); } -#elif defined(HAVE_VGA_USE_UNSIGNED_INT_PIPE) -static inline int kcl_amdgpu_get_crtc_scanout_position(struct drm_device *dev, unsigned int crtc, +#else +static inline int kcl_amdgpu_get_crtc_scanout_position(struct drm_device *dev, unsigned int pipe, unsigned int flags, int *vpos, int *hpos, ktime_t *stime, ktime_t *etime, const struct drm_display_mode *mode) { - return amdgpu_display_get_crtc_scanoutpos(dev, crtc, flags, vpos, hpos, stime, etime, mode); -} -#elif defined(HAVE_GET_SCANOUT_POSITION_HAS_DRM_DISPLAY_MODE_ARG) -static inline int kcl_amdgpu_get_crtc_scanout_position(struct drm_device *dev, int crtc, - unsigned int flags, - int *vpos, int *hpos, - ktime_t *stime, ktime_t *etime, - const struct drm_display_mode *mode) -{ - return amdgpu_display_get_crtc_scanoutpos(dev, crtc, flags, vpos, hpos, stime, etime, mode); -} -#elif defined(HAVE_GET_SCANOUT_POSITION_HAS_TIMESTAMP_ARG) -static inline int kcl_amdgpu_get_crtc_scanout_position(struct drm_device *dev, int crtc, - int *vpos, int *hpos, ktime_t *stime, - ktime_t *etime) -{ - return amdgpu_display_get_crtc_scanoutpos(dev, crtc, 0, vpos, hpos, stime, etime, NULL); -} -#else -static inline int kcl_amdgpu_get_crtc_scanout_position(struct drm_device *dev, int crtc, - int *vpos, int *hpos) -{ - return amdgpu_display_get_crtc_scanoutpos(dev, crtc, 0, vpos, hpos, NULL, NULL, NULL); + return amdgpu_display_get_crtc_scanoutpos(dev, pipe, flags, vpos, hpos, stime, etime, mode); } #endif -#if defined(HAVE_GET_VBLANK_TIMESTAMP_IN_DRM_DRIVER_HAS_KTIME_T) +#if defined(HAVE_DRM_DRIVER_GET_VBLANK_TIMESTAMP_USE_KTIMER_T_ARG) static inline bool kcl_amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, int *max_error, ktime_t *vblank_time, bool in_vblank_irq) { return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, vblank_time, in_vblank_irq); } -#elif defined(HAVE_GET_VBLANK_TIMESTAMP_IN_DRM_DRIVER_HAS_BOOL_IN_VBLANK_IRQ) +#elif defined(HAVE_DRM_DRIVER_GET_VBLANK_TIMESTAMP_RETURN_BOOL) static inline bool kcl_amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, int *max_error, struct timeval *vblank_time, bool in_vblank_irq) { - return !!amdgpu_get_vblank_timestamp_kms(dev, pipe, max_error, vblank_time, in_vblank_irq); -} -#elif defined(HAVE_GET_VBLANK_TIMESTAMP_IN_DRM_DRIVER_RETURN_BOOL) -static inline bool kcl_amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, - int *max_error, struct timeval *vblank_time, - unsigned flags) -{ - return !!amdgpu_get_vblank_timestamp_kms(dev, pipe, max_error, vblank_time, flags); + return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, vblank_time, in_vblank_irq); } -#elif defined(HAVE_VGA_USE_UNSIGNED_INT_PIPE) +#else static inline int kcl_amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, int *max_error, struct timeval *vblank_time, unsigned flags) { - return amdgpu_get_vblank_timestamp_kms(dev, pipe, max_error, vblank_time, flags); -} -#else -static inline int kcl_amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, int crtc, - int *max_error, - struct timeval *vblank_time, - unsigned flags) -{ - return amdgpu_get_vblank_timestamp_kms(dev, crtc, max_error, vblank_time, flags); + struct drm_crtc *crtc; + struct amdgpu_device *adev = drm_to_adev(dev); + + if (pipe >= dev->num_crtcs) { + DRM_ERROR("Invalid crtc %u\n", pipe); + return -EINVAL; + } + + /* Get associated drm_crtc: */ + crtc = &adev->mode_info.crtcs[pipe]->base; + if (!crtc) { + /* This can occur on driver load if some component fails to + * initialize completely and driver is unloaded */ + DRM_ERROR("Uninitialized crtc %d\n", pipe); + return -EINVAL; + } + + return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, + vblank_time, flags, + &crtc->hwmode); } -#endif +#endif /* HAVE_DRM_DRIVER_GET_VBLANK_TIMESTAMP_USE_KTIMER_T_ARG */ #endif /* HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP */ #endif /* AMDGPU_BACKPORT_KCL_AMDGPU_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-calc-vbltimestamp-from-scanoutpos.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-calc-vbltimestamp-from-scanoutpos.m4 deleted file mode 100644 index c69de05235130..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm-calc-vbltimestamp-from-scanoutpos.m4 +++ /dev/null @@ -1,58 +0,0 @@ -dnl # -dnl # commit 67680d3c0464 -dnl # drm: vblank: use ktime_t instead of timeval -dnl # -AC_DEFUN([AC_AMDGPU_DRM_CALC_VBLTIMESTAMP_FROM_SCANOUTPOS], [ - AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drmP.h], [ - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include - ], [ - drm_calc_vbltimestamp_from_scanoutpos(NULL, 0, NULL, (ktime_t *)NULL, 0); - ], [drm_calc_vbltimestamp_from_scanoutpos], [drivers/gpu/drm/drm_vblank.c], [ - AC_DEFINE(HAVE_DRM_CALC_VBLTIMESTAMP_FROM_SCANOUTPOS_USE_KTIMER_T_ARG, 1, - [drm_calc_vbltimestamp_from_scanoutpos() use ktime_t arg]) - ], [ - dnl # - dnl # commit 1bf6ad622b9be - dnl # drm/vblank: drop the mode argument from drm_calc_vbltimestamp_from_scanoutpos - dnl # - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include - ], [ - drm_calc_vbltimestamp_from_scanoutpos(NULL, 0, NULL, (struct timeval *)NULL, 0); - ], [drm_calc_vbltimestamp_from_scanoutpos], [drivers/gpu/drm/drm_vblank.c drivers/gpu/drm/drm_irq.c], [ - AC_DEFINE(HAVE_DRM_CALC_VBLTIMESTAMP_FROM_SCANOUTPOS_DROP_MOD_ARG, 1, - [drm_calc_vbltimestamp_from_scanoutpos() drop mode arg]) - ], [ - dnl # - dnl # commit eba1f35dfe14 - dnl # drm: Move timestamping constants into drm_vblank_crtc - dnl # - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include - ], [ - drm_calc_vbltimestamp_from_scanoutpos(NULL, 0, NULL, NULL, 0, (const struct drm_display_mode *)NULL); - ], [drm_calc_vbltimestamp_from_scanoutpos], [drivers/gpu/drm/drm_irq.c], [ - AC_DEFINE(HAVE_DRM_CALC_VBLTIMESTAMP_FROM_SCANOUTPOS_HAVE_MODE_ARG, 1, - [drm_calc_vbltimestamp_from_scanoutpos() remove crtc arg]) - ], [ - dnl # - dnl # commit 7da903ef0485 - dnl # drm: Pass the display mode to drm_calc_vbltimestamp_from_scanoutpos() - dnl # - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include - ], [ - drm_calc_vbltimestamp_from_scanoutpos(NULL, 0, NULL, NULL, 0, (const struct drm_crtc *)NULL, (const struct drm_display_mode *)NULL); - ], [drm_calc_vbltimestamp_from_scanoutpos], [drivers/gpu/drm/drm_irq.c], [ - AC_DEFINE(HAVE_DRM_CALC_VBLTIMESTAMP_FROM_SCANOUTPOS_HAVE_CRTC_MODE_ARG, 1, - [drm_calc_vbltimestamp_from_scanoutpos() have the crtc & mode arg]) - ]) - ]) - ]) - ]) - ], [ - AC_DEFINE(HAVE_DRM_CALC_VBLTIMESTAMP_FROM_SCANOUTPOS_USE_KTIMER_T_ARG, 1, - [drm_calc_vbltimestamp_from_scanoutpos() use ktime_t arg]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_calc_vbltimestamp_from_scanoutpos.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_calc_vbltimestamp_from_scanoutpos.m4 new file mode 100644 index 0000000000000..35e273468a27f --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_calc_vbltimestamp_from_scanoutpos.m4 @@ -0,0 +1,58 @@ +dnl # +dnl # commit v4.14-rc3-721-g67680d3c0464 +dnl # drm: vblank: use ktime_t instead of timeval +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CALC_VBLTIMESTAMP_FROM_SCANOUTPOS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DRMP_H + struct vm_area_struct; + #include + #else + #include + #include + #endif + ], [ + struct drm_driver *kms_driver = NULL; + bool (*get_vblank_timestamp) (struct drm_device *dev, unsigned int pipe, + int *max_error, + ktime_t *vblank_time, + bool in_vblank_irq); + drm_calc_vbltimestamp_from_scanoutpos(NULL, 0, NULL, (ktime_t *)NULL, 0); + kms_driver->get_vblank_timestamp = get_vblank_timestamp; + ], [ + AC_DEFINE(HAVE_DRM_DRIVER_GET_VBLANK_TIMESTAMP_USE_KTIMER_T_ARG, 1, + [drm_calc_vbltimestamp_from_scanoutpos() use ktime_t arg]) + AC_DEFINE(HAVE_DRM_DRIVER_GET_SCANOUT_POSITION_RETURN_BOOL, 1, + [drm_driver->get_scanout_position() return bool]) + ], [ + dnl # + dnl # v4.11-rc7-1902-g1bf6ad622b9b drm/vblank: drop the mode argument from drm_calc_vbltimestamp_from_scanoutpos + dnl # v4.11-rc7-1900-g3fcdcb270936 drm/vblank: Switch to bool in_vblank_irq in get_vblank_timestamp + dnl # v4.11-rc7-1899-gd673c02c4bdb drm/vblank: Switch drm_driver->get_vblank_timestamp to return a bool + dnl # + AC_KERNEL_TRY_COMPILE([ + struct vm_area_struct; + #include + ], [ + struct drm_driver *kms_driver = NULL; + bool (*get_scanout_position) (struct drm_device *dev, unsigned int pipe, + bool in_vblank_irq, int *vpos, int *hpos, + ktime_t *stime, ktime_t *etime, + const struct drm_display_mode *mode); + bool (*get_vblank_timestamp) (struct drm_device *dev, unsigned int pipe, + int *max_error, + struct timeval *vblank_time, + bool in_vblank_irq); + kms_driver->get_scanout_position = get_scanout_position; + kms_driver->get_vblank_timestamp = get_vblank_timestamp; + drm_calc_vbltimestamp_from_scanoutpos(NULL, 0, NULL, (struct timeval *)NULL, 0); + ], [ + AC_DEFINE(HAVE_DRM_DRIVER_GET_SCANOUT_POSITION_RETURN_BOOL, 1, + [drm_driver->get_scanout_position() return bool]) + AC_DEFINE(HAVE_DRM_DRIVER_GET_VBLANK_TIMESTAMP_RETURN_BOOL, 1, + [drm_driver->get_vblank_timestamp() return bool]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/get-scanout-position-in-struct-drm-driver.m4 b/drivers/gpu/drm/amd/dkms/m4/get-scanout-position-in-struct-drm-driver.m4 deleted file mode 100644 index 6f0105f6f9890..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/get-scanout-position-in-struct-drm-driver.m4 +++ /dev/null @@ -1,94 +0,0 @@ -dnl # -dnl # commit v4.11-rc7-1902-g1bf6ad622b9b -dnl # drm/vblank: drop the mode argument from drm_calc_vbltimestamp_from_scanoutpos -dnl # -AC_DEFUN([AC_AMDGPU_GET_SCANOUT_POSITION_IN_DRM_DRIVER], [ - AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drmP.h], [ - AC_KERNEL_TRY_COMPILE([ - #include - bool foo(struct drm_device *dev, unsigned int pipe, - bool in_vblank_irq, int *vpos, int *hpos, - ktime_t *stime, ktime_t *etime, - const struct drm_display_mode *mode) - { - return false; - } - ], [ - struct drm_driver *bar = NULL; - bar->get_scanout_position = foo; - ], [ - AC_DEFINE(HAVE_GET_SCANOUT_POSITION_RETURN_BOOL, 1, - [get_scanout_position return bool]) - AC_DEFINE(HAVE_VGA_USE_UNSIGNED_INT_PIPE, 1, - [get_scanout_position use unsigned int pipe]) - ], [ - dnl # - dnl # commit v4.3-rc3-73-g88e72717c2de - dnl # drm/irq: Use unsigned int pipe in public API - dnl # - AC_KERNEL_TRY_COMPILE([ - #include - int foo(struct drm_device *dev, unsigned int pipe, - unsigned int flags, int *vpos, int *hpos, - ktime_t *stime, ktime_t *etime, - const struct drm_display_mode *mode) - { - return 0; - } - ], [ - struct drm_driver *bar = NULL; - bar->get_scanout_position = foo; - ], [ - AC_DEFINE(HAVE_VGA_USE_UNSIGNED_INT_PIPE, 1, - [get_scanout_position use unsigned int pipe]) - ], [ - dnl # - dnl # commit v4.3-rc2-44-g3bb403bf421b - dnl # drm: Stop using linedur_ns and pixeldur_ns for vblank timestamps - dnl # - AC_KERNEL_TRY_COMPILE([ - #include - int foo(struct drm_device *dev, int crtc, - unsigned int flags, - int *vpos, int *hpos, - ktime_t *stime, ktime_t *etime, - const struct drm_display_mode *mode) - { - return 0; - } - ], [ - struct drm_driver *bar = NULL; - bar->get_scanout_position = foo; - ], [ - AC_DEFINE(HAVE_GET_SCANOUT_POSITION_HAS_DRM_DISPLAY_MODE_ARG, 1, - [get_scanout_position has struct drm_display_mode arg]) - ], [ - dnl # - dnl # commit v3.12-rc3-485-g8f6fce03ddaf - dnl # drm: Push latency sensitive bits of vblank scanoutpos timestamping into kms drivers. - dnl # - AC_KERNEL_TRY_COMPILE([ - #include - int foo(struct drm_device *dev, int crtc, - int *vpos, int *hpos, ktime_t *stime, - ktime_t *etime) - { - return 0; - } - ], [ - struct drm_driver *bar = NULL; - bar->get_scanout_position = foo; - ], [ - AC_DEFINE(HAVE_GET_SCANOUT_POSITION_HAS_TIMESTAMP_ARG, 1, - [get_scanout_position has timestamp arg]) - ]) - ]) - ]) - ]) - ], [ - AC_DEFINE(HAVE_GET_SCANOUT_POSITION_RETURN_BOOL, 1, - [get_scanout_position return bool]) - AC_DEFINE(HAVE_VGA_USE_UNSIGNED_INT_PIPE, 1, - [get_scanout_position use unsigned int pipe]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/get-vblank-timestamp-in-struct-drm-driver.m4 b/drivers/gpu/drm/amd/dkms/m4/get-vblank-timestamp-in-struct-drm-driver.m4 deleted file mode 100644 index 8037673d5aa39..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/get-vblank-timestamp-in-struct-drm-driver.m4 +++ /dev/null @@ -1,68 +0,0 @@ -dnl # commit v4.14-rc3-721-g67680d3c0464 -dnl # drm: vblank: use ktime_t instead of timeval -dnl # -AC_DEFUN([AC_AMDGPU_GET_VBLANK_TIMESTAMP_IN_DRM_DRIVER], [ - AC_KERNEL_TEST_HEADER_FILE_EXIST([drm/drmP.h], [ - AC_KERNEL_TRY_COMPILE([ - #include - bool foo(struct drm_device *dev, unsigned int pipe, - int *max_error, - ktime_t *vblank_time, - bool in_vblank_irq) - { - return false; - } - ], [ - struct drm_driver *bar = NULL; - bar->get_vblank_timestamp = foo; - ], [ - AC_DEFINE(HAVE_GET_VBLANK_TIMESTAMP_IN_DRM_DRIVER_HAS_KTIME_T, 1, - [get_vblank_timestamp has ktime_t arg]) - ], [ - dnl - dnl # commit v4.11-rc7-1900-g3fcdcb270936 - dnl # drm/vblank: Switch to bool in_vblank_irq in get_vblank_timestamp - dnl # - AC_KERNEL_TRY_COMPILE([ - #include - bool foo(struct drm_device *dev, unsigned int pipe, - int *max_error, - struct timeval *vblank_time, - bool in_vblank_irq) - { - return false; - } - ], [ - struct drm_driver *bar = NULL; - bar->get_vblank_timestamp = foo; - ], [ - AC_DEFINE(HAVE_GET_VBLANK_TIMESTAMP_IN_DRM_DRIVER_HAS_BOOL_IN_VBLANK_IRQ, 1, - [get_vblank_timestamp has bool in_vblank_irq arg]) - ], [ - dnl # - dnl # commit id v4.11-rc7-1899-gd673c02c4bdb - dnl # drm/vblank: Switch drm_driver->get_vblank_timestamp to return a bool - dnl # - AC_KERNEL_TRY_COMPILE([ - #include - bool foo(struct drm_device *dev, unsigned int pipe, - int *max_error, - struct timeval *vblank_time, - unsigned flags) - { - return false; - } - ], [ - struct drm_driver *bar = NULL; - bar->get_vblank_timestamp = foo; - ], [ - AC_DEFINE(HAVE_GET_VBLANK_TIMESTAMP_IN_DRM_DRIVER_RETURN_BOOL, 1, - [get_vblank_timestamp return bool]) - ]) - ]) - ]) - ], [ - AC_DEFINE(HAVE_GET_VBLANK_TIMESTAMP_IN_DRM_DRIVER_HAS_KTIME_T, 1, - [get_vblank_timestamp has ktime_t arg]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 index ec6c920089ae1..2820aaa74c3b0 100644 --- a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 @@ -16,8 +16,6 @@ AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP], [ 1, [struct drm_crtc_funcs->get_vblank_timestamp() is available]) ],[ - AC_AMDGPU_GET_SCANOUT_POSITION_IN_DRM_DRIVER - AC_AMDGPU_GET_VBLANK_TIMESTAMP_IN_DRM_DRIVER AC_AMDGPU_DRM_CALC_VBLTIMESTAMP_FROM_SCANOUTPOS ]) ]) From 31aa095dfa9b9a87506e704e7252b47ee12a7c59 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 19 Feb 2021 14:21:21 +0800 Subject: [PATCH 0370/1868] drm/amdkcl: simplify test for drm_connector_xxx the prototype change is introduced in a series of patch. no need to test for each api. Reviewed-by: Guchun Chen Signed-off-by: Flora Cui --- .../amd/dkms/m4/drm-connector-attach-encoder.m4 | 16 ---------------- .../dkms/m4/drm-connector-set-path-property.m4 | 16 ---------------- .../m4/drm-connector-update-edid-property.m4 | 16 ---------------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 3 --- include/kcl/kcl_drm_connector.h | 12 ------------ 5 files changed, 63 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-connector-attach-encoder.m4 delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-connector-set-path-property.m4 delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-connector-update-edid-property.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-attach-encoder.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-attach-encoder.m4 deleted file mode 100644 index 9b4bd0e561b64..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm-connector-attach-encoder.m4 +++ /dev/null @@ -1,16 +0,0 @@ -dnl # -dnl # commit cde4c44d8769c1be16074c097592c46c7d64092b -dnl # drm: drop _mode_ from drm_mode_connector_attach_encode -dnl # -AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_ATTACH_ENCODER], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include - ],[ - drm_connector_attach_encoder(NULL, NULL); - ],[drm_connector_attach_encoder],[drivers/gpu/drm/drm_connector.c],[ - AC_DEFINE(HAVE_DRM_CONNECTOR_ATTACH_ENCODER, 1, - [drm_connector_attach_encoder() is available]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-set-path-property.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-set-path-property.m4 deleted file mode 100644 index f872d0db19a2e..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm-connector-set-path-property.m4 +++ /dev/null @@ -1,16 +0,0 @@ -dnl # -dnl # commit 97e14fbeb53fe060c5f6a7a07e37fd24c087ed0c -dnl # drm: drop _mode_ from remaining connector functions -dnl # -AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_SET_PATH_PROPERTY], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include - ],[ - drm_connector_set_path_property(NULL, NULL); - ],[drm_connector_set_path_property],[drivers/gpu/drm/drm_connector.c],[ - AC_DEFINE(HAVE_DRM_CONNECTOR_SET_PATH_PROPERTY, 1, - [drm_connector_set_path_property() is available]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-update-edid-property.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-update-edid-property.m4 deleted file mode 100644 index eade2ed63d298..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm-connector-update-edid-property.m4 +++ /dev/null @@ -1,16 +0,0 @@ -dnl # -dnl # commit c555f02371c338b06752577aebf738dbdb6907bd -dnl # drm: drop _mode_ from update_edit_property() -dnl # -AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_UPDATE_EDID_PROPERTY], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include - ],[ - drm_connector_update_edid_property(NULL, NULL); - ],[drm_connector_update_edid_property],[drivers/gpu/drm/drm_connector.c],[ - AC_DEFINE(HAVE_DRM_CONNECTOR_UPDATE_EDID_PROPERTY, 1, - [drm_connector_update_edid_property() is available]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index ef394c8b0e3cb..0ccf8398c3bff 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -72,9 +72,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DEBUG_ENABLED AC_AMDGPU_DRM_GEM_OBJECT_PUT_UNLOCKED AC_AMDGPU_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS - AC_AMDGPU_DRM_CONNECTOR_UPDATE_EDID_PROPERTY - AC_AMDGPU_DRM_CONNECTOR_ATTACH_ENCODER - AC_AMDGPU_DRM_CONNECTOR_SET_PATH_PROPERTY AC_AMDGPU_DRM_CONNECTOR_INIT_WITH_DDC AC_AMDGPU_DRM_DP_CALC_PBN_MODE AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS diff --git a/include/kcl/kcl_drm_connector.h b/include/kcl/kcl_drm_connector.h index 8eb2f3e647417..9074a56cce9fd 100644 --- a/include/kcl/kcl_drm_connector.h +++ b/include/kcl/kcl_drm_connector.h @@ -34,18 +34,6 @@ #define AMDKCL_AMDGPU_DRM_CONNECTOR_STATUS_DETECT_MANDATORY #endif -#ifndef HAVE_DRM_CONNECTOR_UPDATE_EDID_PROPERTY -#define drm_connector_update_edid_property drm_mode_connector_update_edid_property -#endif - -#ifndef HAVE_DRM_CONNECTOR_ATTACH_ENCODER -#define drm_connector_attach_encoder drm_mode_connector_attach_encoder -#endif - -#ifndef HAVE_DRM_CONNECTOR_SET_PATH_PROPERTY -#define drm_connector_set_path_property drm_mode_connector_set_path_property -#endif - /** * drm_connector_for_each_possible_encoder - iterate connector's possible encoders * @connector: &struct drm_connector pointer From 99137594aeb439358788ff99b0dd413ebe7df6dc Mon Sep 17 00:00:00 2001 From: xinhui pan Date: Wed, 18 Mar 2020 16:50:45 +0800 Subject: [PATCH 0371/1868] drm/amdgpu: fix OOM panic and deadlock In mmu release, we schedule a work to free amn. however there is race between exit_mmap and oom_reap_task_mm. exit_mmap -> mmu_notifier_release oom_reap_task_mm -> __oom_reap_task_mm -> mmu_notifier_invalidate_range_start_nonblock So the amn might have been freed. sync rcu in destroy to wait for ongoing range invalidate. calltrace: [ 4407.908455] BUG: kernel NULL pointer dereference, address: 0000000000000050 [ 4407.915591] #PF: supervisor read access in kernel mode [ 4407.920827] #PF: error_code(0x0000) - not-present page [ 4407.926079] PGD 0 P4D 0 [ 4407.928662] Oops: 0000 [#1] SMP PTI [ 4407.932216] CPU: 3 PID: 55 Comm: oom_reaper Tainted: G W O 5.4.0-rc7+ #1 [ 4407.940206] Hardware name: System manufacturer System Product Name/Z170-A, BIOS 1702 01/28/2016 [ 4407.949080] RIP: 0010:mark_lock+0xc9/0x540 [ 4407.953282] Code: 31 c0 eb 12 48 8d 14 80 48 8d 04 50 48 c1 e0 04 48 05 00 dd 01 9c 41 bc 01 00 00 00 89 d9 41 bf 01 00 00 00 41 d3 e4 4d 63 e4 <4c> 85 60 50 0f 85 50 ff ff ff e8 18 bb ff ff 85 c0 0f 84 40 ff ff [ 4407.972385] RSP: 0018:ffffab4440253ab0 EFLAGS: 00010006 [ 4407.977723] RAX: 0000000000000000 RBX: 0000000000000008 RCX: 0000000000000008 [ 4407.984977] RDX: ffff9df1d9fd8040 RSI: 0000000000000001 RDI: ffffffff9a318d0a [ 4407.992222] RBP: ffffab4440253af0 R08: 0000000000000000 R09: 000000000003b540 [ 4407.999493] R10: 0000000000000000 R11: 0000000000000037 R12: 0000000000000100 [ 4408.006774] R13: ffff9df1d9fd8040 R14: ffff9df1d9fd8c88 R15: 0000000000000001 [ 4408.014062] FS: 0000000000000000(0000) GS:ffff9df1de180000(0000) knlGS:0000000000000000 [ 4408.022295] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 4408.028154] CR2: 0000000000000050 CR3: 0000000393410001 CR4: 00000000003606e0 [ 4408.035427] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 [ 4408.042689] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 [ 4408.049968] Call Trace: [ 4408.052467] __lock_acquire+0x261/0x1600 [ 4408.056486] ? __lock_acquire+0x43a/0x1600 [ 4408.060628] ? __lock_acquire+0x43a/0x1600 [ 4408.064816] lock_acquire+0xb8/0x1c0 [ 4408.068482] ? rwsem_down_read_slowpath+0x1e8/0x5f0 [ 4408.073509] _raw_spin_lock_irq+0x3b/0x50 [ 4408.077624] ? rwsem_down_read_slowpath+0x1e8/0x5f0 [ 4408.082582] rwsem_down_read_slowpath+0x1e8/0x5f0 [ 4408.087401] ? finish_task_switch+0x63/0x230 [ 4408.091759] ? __schedule+0x2b3/0x860 [ 4408.095487] down_read_non_owner+0x86/0x160 [ 4408.099767] ? down_read_non_owner+0x86/0x160 [ 4408.104295] amdgpu_mn_read_lock+0x9f/0xb0 [amdgpu] [ 4408.109364] amdgpu_mn_invalidate_range_start_gfx+0x3f/0x1e0 [amdgpu] [ 4408.115941] __mmu_notifier_invalidate_range_start+0x9e/0x190 [ 4408.121816] ? __oom_reap_task_mm+0x6d/0x220 [ 4408.126166] __oom_reap_task_mm+0x1b5/0x220 [ 4408.130450] oom_reaper+0x4d0/0x650 [ 4408.133991] ? __kthread_parkme+0x2f/0x90 [ 4408.138083] ? finish_wait+0x90/0x90 [ 4408.141715] kthread+0x12c/0x150 [ 4408.145043] ? __oom_reap_task_mm+0x220/0x220 [ 4408.149461] ? kthread_park+0x90/0x90 [ 4408.153208] ret_from_fork+0x3a/0x50 There is another deadlock. calltrace: [ 1635.072660] BUG: sleeping function called from invalid context at ../kernel/locking/rwsem.c:1621 [ 1635.081870] in_atomic(): 0, irqs_disabled(): 0, non_block: 1, pid: 55, name: oom_reaper [ 1635.090106] 4 locks held by oom_reaper/55: [ 1635.091485] init_user_pages: Failed to get user pages: -512 [ 1635.094302] #0: ffff9ca48e94b5d8 (&mm->mmap_sem#2){++++}, at: oom_reaper+0xa4/0x650 [ 1635.108116] #1: ffffffff82750fc0 (mmu_notifier_invalidate_range_start){+.+.}, at: __oom_reap_task_mm+0x6d/0x220 [ 1635.118558] #2: ffffffff827637f0 (srcu){....}, at: __mmu_notifier_invalidate_range_start+0x5/0x190 [ 1635.127879] #3: ffff9ca4f7c605f0 (&amn->read_lock){+.+.}, at: amdgpu_mn_read_lock+0x75/0xb0 [amdgpu] [ 1635.137614] CPU: 3 PID: 55 Comm: oom_reaper Tainted: G W O 5.4.0-rc7+ #1 [ 1635.145787] Hardware name: System manufacturer System Product Name/Z170-A, BIOS 1702 01/28/2016 [ 1635.154744] Call Trace: [ 1635.157264] dump_stack+0x98/0xd5 [ 1635.160688] ___might_sleep+0x175/0x260 [ 1635.164675] __might_sleep+0x4a/0x80 [ 1635.168340] down_read_non_owner+0x20/0x160 [ 1635.172748] amdgpu_mn_read_lock+0x9f/0xb0 [amdgpu] [ 1635.177884] amdgpu_mn_invalidate_range_start_hsa+0x3f/0x180 [amdgpu] [ 1635.184477] __mmu_notifier_invalidate_range_start+0x9e/0x190 [ 1635.190337] ? __oom_reap_task_mm+0x6d/0x220 [ 1635.194725] __oom_reap_task_mm+0x1b5/0x220 [ 1635.199069] oom_reaper+0x4d0/0x650 [ 1635.202611] ? __kthread_parkme+0x2f/0x90 [ 1635.206740] ? finish_wait+0x90/0x90 [ 1635.210425] kthread+0x12c/0x150 [ 1635.213714] ? __oom_reap_task_mm+0x220/0x220 [ 1635.218215] ? kthread_park+0x90/0x90 [ 1635.221976] ret_from_fork+0x3a/0x50 [ 1815.108088] "echo 0 > /proc/sys/kernel/hung_task_timeout_secs" disables this message. [ 1815.116065] kworker/1:1 D 0 9357 2 0x80004000 [ 1815.121873] Workqueue: events amdgpu_mn_destroy [amdgpu] [ 1815.127264] Call Trace: [ 1815.129765] __schedule+0x2ab/0x860 [ 1815.133299] ? rwsem_down_write_slowpath+0x329/0x660 [ 1815.138382] schedule+0x3a/0xc0 [ 1815.141613] rwsem_down_write_slowpath+0x32e/0x660 [ 1815.146523] down_write+0x74/0x80 [ 1815.149921] ? down_write+0x40/0x80 [ 1815.153490] ? down_write+0x74/0x80 [ 1815.157285] amdgpu_mn_destroy+0x6e/0x240 [amdgpu] [ 1815.162176] process_one_work+0x231/0x5c0 [ 1815.166313] worker_thread+0x3f/0x3b0 [ 1815.170100] ? __kthread_parkme+0x61/0x90 [ 1815.174204] kthread+0x12c/0x150 [ 1815.177573] ? process_one_work+0x5c0/0x5c0 [ 1815.181857] ? kthread_park+0x90/0x90 [ 1815.185591] ret_from_fork+0x3a/0x50 oom killer want to invalidate range in nonblock context. But the amdgpu_mn_read_lock might sleep, and casue deadlock then. Reviewed-by: Flora Cui Signed-off-by: xinhui pan Signed-off-by: Yifan Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c | 63 ++++++++++++++----------- 1 file changed, 35 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c index 78a5f32697202..6621f0447d559 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c @@ -90,6 +90,9 @@ struct amdgpu_mn { #endif struct mutex read_lock; atomic_t recursion; +#if !defined(HAVE_MMU_NOTIFIER_PUT) + struct rcu_head rcu; +#endif }; /** @@ -105,6 +108,18 @@ struct amdgpu_mn_node { struct list_head bos; }; +#ifdef HAVE_MMU_NOTIFIER_PUT +static void amdgpu_mn_free(struct mmu_notifier *mn) +{ + kfree(container_of(mn, struct amdgpu_mn, mn)); +} +#else +static void amdgpu_mn_free(struct rcu_head *rcu) +{ + kfree(container_of(rcu, struct amdgpu_mn, rcu)); +} +#endif + /** * amdgpu_mn_destroy - destroy the MMU notifier * @@ -136,8 +151,12 @@ static void amdgpu_mn_destroy(struct work_struct *work) } up_write(&amn->lock); mutex_unlock(&adev->mn_lock); +#ifdef HAVE_MMU_NOTIFIER_PUT + mmu_notifier_put(&amn->mn); +#else mmu_notifier_unregister_no_release(&amn->mn, amn->mm); - kfree(amn); + mmu_notifier_call_srcu(&amn->rcu, amdgpu_mn_free); +#endif } /** @@ -188,6 +207,9 @@ void amdgpu_mn_unlock(struct amdgpu_mn *mn) */ static void amdgpu_mn_read_lock(struct amdgpu_mn *amn) { + /* FIXME: Need figure out one way to detect + * if we are in oom reaper context. + */ mutex_lock(&amn->read_lock); if (atomic_inc_return(&amn->recursion) == 1) down_read_non_owner(&amn->lock); @@ -201,11 +223,14 @@ static void amdgpu_mn_read_lock(struct amdgpu_mn *amn) */ static int amdgpu_mn_read_lock(struct amdgpu_mn *amn, bool blockable) { - if (blockable) - mutex_lock(&amn->read_lock); - else if (!mutex_trylock(&amn->read_lock)) + /* Non blockable occurs only in oom reaper context. + * In this case, process is going to be killed anyway. + * Let oom reaper fail at this stage. + */ + if (!blockable) return -EAGAIN; + mutex_lock(&amn->read_lock); if (atomic_inc_return(&amn->recursion) == 1) down_read_non_owner(&amn->lock); mutex_unlock(&amn->read_lock); @@ -286,11 +311,6 @@ static int amdgpu_mn_invalidate_range_start_gfx(struct mmu_notifier *mn, while (it) { struct amdgpu_mn_node *node; - if (!mmu_notifier_range_blockable(range)) { - amdgpu_mn_read_unlock(amn); - return -EAGAIN; - } - node = container_of(it, struct amdgpu_mn_node, it); it = interval_tree_iter_next(it, range->start, end); @@ -330,11 +350,6 @@ static int amdgpu_mn_invalidate_range_start_hsa(struct mmu_notifier *mn, struct amdgpu_mn_node *node; struct amdgpu_bo *bo; - if (!mmu_notifier_range_blockable(range)) { - amdgpu_mn_read_unlock(amn); - return -EAGAIN; - } - node = container_of(it, struct amdgpu_mn_node, it); it = interval_tree_iter_next(it, range->start, end); @@ -394,13 +409,6 @@ static void amdgpu_mn_invalidate_range_start_gfx(struct mmu_notifier *mn, while (it) { struct amdgpu_mn_node *node; -#if defined(HAVE_5ARGS_INVALIDATE_RANGE_START) - if (!blockable) { - amdgpu_mn_read_unlock(amn); - return -EAGAIN; - } -#endif - node = container_of(it, struct amdgpu_mn_node, it); it = interval_tree_iter_next(it, start, end); @@ -456,13 +464,6 @@ static void amdgpu_mn_invalidate_range_start_hsa(struct mmu_notifier *mn, struct amdgpu_mn_node *node; struct amdgpu_bo *bo; -#if defined(HAVE_5ARGS_INVALIDATE_RANGE_START) - if (!blockable) { - amdgpu_mn_read_unlock(amn); - return -EAGAIN; - } -#endif - node = container_of(it, struct amdgpu_mn_node, it); it = interval_tree_iter_next(it, start, end); @@ -508,11 +509,17 @@ static void amdgpu_mn_invalidate_range_end(struct mmu_notifier *mn, static const struct mmu_notifier_ops amdgpu_mn_ops[] = { [AMDGPU_MN_TYPE_GFX] = { +#ifdef HAVE_MMU_NOTIFIER_PUT + .free_notifier = amdgpu_mn_free, +#endif .release = amdgpu_mn_release, .invalidate_range_start = amdgpu_mn_invalidate_range_start_gfx, .invalidate_range_end = amdgpu_mn_invalidate_range_end, }, [AMDGPU_MN_TYPE_HSA] = { +#ifdef HAVE_MMU_NOTIFIER_PUT + .free_notifier = amdgpu_mn_free, +#endif .release = amdgpu_mn_release, .invalidate_range_start = amdgpu_mn_invalidate_range_start_hsa, .invalidate_range_end = amdgpu_mn_invalidate_range_end, From 3b28ea39a5f82946b3990fce2394f27e9541b7a0 Mon Sep 17 00:00:00 2001 From: Philip Yang Date: Tue, 15 Sep 2020 17:25:54 -0400 Subject: [PATCH 0372/1868] drm/amdgpu: prevent double release ttm->pages If ttm_bo_validate failed, pages are released, but ttm->pages is not cleared, this causes below backtrace. This issue happens on DELL machine with Ubuntu 18.04 kernel 4.15. put pages and set ttm->pages to NULL if ttm_bo_validate failed under memory pressure. [ 5400.077763] 0000:23:00.0: IOMMU mapping error in map_sg (io-pages: 32981732) [ 5400.097080] [drm:amdgpu_ttm_backend_bind [amdgpu]] *ERROR* failed to pin userptr [ 5400.097104] amdgpu: init_user_pages: failed to validate BO [ 5400.285482] BUG: Bad page state in process kfdtest pfn:1f6eac9 [ 5400.285533] page:ffffe07f7dbab240 count:0 mapcount:1 mapping:0000000000000000 index:0x1 [ 5400.285578] flags: 0x17ffffc0000000() [ 5400.285602] raw: 0017ffffc0000000 0000000000000000 0000000000000001 0000000000000000 [ 5400.285643] raw: dead000000000100 dead000000000200 0000000000000000 0000000000000000 [ 5400.285684] page dumped because: nonzero mapcount [ 5400.285710] Modules linked in: xt_conntrack ipt_MASQUERADE 4.15.0-117-generic #118-Ubuntu [ 5400.285779] Hardware name: Dell Inc. PowerEdge R7525/0PYVT1, BIOS 1.5.4 07/09/2020 [ 5400.285780] Call Trace: [ 5400.285793] dump_stack+0x6d/0x8e [ 5400.285798] bad_page+0xcb/0x120 [ 5400.285801] free_pages_check_bad+0x5f/0x70 [ 5400.285803] free_pcppages_bulk+0x44a/0x4e0 [ 5400.285808] ? mem_cgroup_uncharge+0x64/0x70 [ 5400.285810] free_unref_page_commit+0xb1/0xf0 [ 5400.285813] free_unref_page+0x59/0x70 [ 5400.285815] __put_page+0x40/0x80 [ 5400.285906] amdgpu_ttm_tt_set_user_pages+0x64/0xc0 [amdgpu] [ 5400.285983] amdgpu_ttm_tt_unpopulate+0x55/0x80 [amdgpu] [ 5400.285988] ttm_tt_unpopulate.part.10+0x53/0x60 [amdttm] [ 5400.285992] ttm_tt_destroy.part.11+0x4f/0x60 [amdttm] [ 5400.285996] ttm_tt_destroy+0x13/0x20 [amdttm] [ 5400.286000] ttm_bo_cleanup_memtype_use+0x36/0x80 [amdttm] [ 5400.286004] ttm_bo_release+0x1c9/0x360 [amdttm] [ 5400.286008] amdttm_bo_put+0x24/0x30 [amdttm] [ 5400.286083] amdgpu_bo_unref+0x1e/0x30 [amdgpu] [ 5400.286192] amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu+0x9ca/0xb10 [amdgpu] [ 5400.286293] kfd_ioctl_alloc_memory_of_gpu+0xef/0x2c0 [amdgpu] Change-Id: Ide1cac32300e4195257a4faf125f4d85e1fc3d64 Signed-off-by: Philip Yang Reviewed-by: Felix Kuehling Reviewed-by: Oak Zeng --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 2d16fec2fb322..d666e63230354 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -1142,7 +1142,7 @@ static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr, amdgpu_ttm_tt_get_user_pages_done(bo->tbo.ttm, range); #else if (ret) - release_pages(mem->user_pages, bo->tbo.ttm->num_pages); + amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm, NULL); free_out: kvfree(mem->user_pages); mem->user_pages = NULL; From 62eb12e4feaccd39cdcd74bd6f07675878904dc0 Mon Sep 17 00:00:00 2001 From: xinhui pan Date: Wed, 4 Nov 2020 11:43:39 +0800 Subject: [PATCH 0373/1868] drm/amdkcl: define __GFP_RETRY_MAYFAIL as __GFP_NORETRY In old kernel, __GFP_NORETRY would not invoke OOM killer. TTM prefers that usage when TTM_PAGE_FLAG_NO_RETRY is set. Signed-off-by: xinhui pan Reviewed-by: Kevin Wang --- include/kcl/kcl_kernel.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/kcl/kcl_kernel.h b/include/kcl/kcl_kernel.h index f33fc452d8243..f93febef548d8 100644 --- a/include/kcl/kcl_kernel.h +++ b/include/kcl/kcl_kernel.h @@ -16,7 +16,7 @@ #endif #ifndef __GFP_RETRY_MAYFAIL -#define __GFP_RETRY_MAYFAIL __GFP_REPEAT +#define __GFP_RETRY_MAYFAIL __GFP_NORETRY #endif #ifndef ALIGN_DOWN From 9be2c80b341eb6f3df2fa8b6412fdf6a71a5131c Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Mon, 15 Mar 2021 13:28:34 +0800 Subject: [PATCH 0374/1868] drm/amdkcl: fake the fs_reclaim_acquire{release} Signed-off-by: Shiwu Zhang --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_page_alloc.c | 143 ++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + .../gpu/drm/amd/dkms/m4/fs_reclaim_acquire.m4 | 15 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/ttm/backport/backport.h | 1 + include/kcl/kcl_sched_mm.h | 35 +++++ 7 files changed, 197 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_page_alloc.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/fs_reclaim_acquire.m4 create mode 100644 include/kcl/kcl_sched_mm.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 3a98d624be313..4ea595282d7d1 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -11,7 +11,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_drm_fb.o kcl_drm_print.o kcl_fbmem.o \ kcl_drm_crtc.o kcl_drm_connector.o kcl_drm_atomic_helper.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o kcl_ftrace.o \ - kcl_acpi_table.o kcl_drm_aperture.o + kcl_acpi_table.o kcl_page_alloc.o kcl_drm_aperture.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_page_alloc.c b/drivers/gpu/drm/amd/amdkcl/kcl_page_alloc.c new file mode 100644 index 0000000000000..d56b220384800 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_page_alloc.c @@ -0,0 +1,143 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * linux/mm/page_alloc.c + * + * Manages the free list, the system allocates free pages here. + * Note that kmalloc() lives in slab.c + * + * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds + * Swap reorganised 29.12.95, Stephen Tweedie + * Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999 + * Reshaped it to be a zoned allocator, Ingo Molnar, Red Hat, 1999 + * Discontiguous memory support, Kanoj Sarcar, SGI, Nov 1999 + * Zone balancing, Kanoj Sarcar, SGI, Jan 2000 + * Per cpu hot/cold page lists, bulk allocation, Martin J. Bligh, Sept 2002 + * (lots of bits borrowed from Ingo Molnar & Andrew Morton) + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +//#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +//#include +#include +#include +#include + +#include +#include +#include +//#include "internal.h" +//#include "shuffle.h" +//#include "page_reporting.h" + +/* Copied from mm/page_allo.c */ +#ifndef HAVE_FS_RECLAIM_ACQUIRE +#ifdef CONFIG_LOCKDEP +static struct lockdep_map __fs_reclaim_map = + STATIC_LOCKDEP_MAP_INIT("fs_reclaim", &__fs_reclaim_map); + +static bool __need_reclaim(gfp_t gfp_mask) +{ + /* no reclaim without waiting on it */ + if (!(gfp_mask & __GFP_DIRECT_RECLAIM)) + return false; + + /* this guy won't enter reclaim */ + if (current->flags & PF_MEMALLOC) + return false; + + if (gfp_mask & __GFP_NOLOCKDEP) + return false; + + return true; +} + +void __fs_reclaim_acquire(void) +{ + lock_map_acquire(&__fs_reclaim_map); +} + +void __fs_reclaim_release(void) +{ + lock_map_release(&__fs_reclaim_map); +} + +void _kcl_fs_reclaim_acquire(gfp_t gfp_mask) +{ + gfp_mask = current_gfp_context(gfp_mask); + + if (__need_reclaim(gfp_mask)) { + if (gfp_mask & __GFP_FS) + __fs_reclaim_acquire(); + +#ifdef CONFIG_MMU_NOTIFIER + lock_map_acquire(&__mmu_notifier_invalidate_range_start_map); + lock_map_release(&__mmu_notifier_invalidate_range_start_map); +#endif + + } +} +EXPORT_SYMBOL_GPL(_kcl_fs_reclaim_acquire); + +void _kcl_fs_reclaim_release(gfp_t gfp_mask) +{ + gfp_mask = current_gfp_context(gfp_mask); + + if (__need_reclaim(gfp_mask)) { + if (gfp_mask & __GFP_FS) + __fs_reclaim_release(); + } +} +EXPORT_SYMBOL_GPL(_kcl_fs_reclaim_release); +#endif +#endif /* HAVE_FS_RECLAIM_ACQUIRE */ diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index c9f88d77262d6..b9e45108b818c 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -64,6 +64,7 @@ #include #include #include +#include #include "kcl/kcl_amdgpu_drm_fb_helper.h" #include "kcl/kcl_amdgpu.h" #include "kcl/kcl_amdgpu_drm_drv.h" diff --git a/drivers/gpu/drm/amd/dkms/m4/fs_reclaim_acquire.m4 b/drivers/gpu/drm/amd/dkms/m4/fs_reclaim_acquire.m4 new file mode 100644 index 0000000000000..be2f5c9928ae2 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/fs_reclaim_acquire.m4 @@ -0,0 +1,15 @@ +dnl # +dnl # v4.13-rc4-164-gd92a8cfcb37e +dnl # locking/lockdep: Rework FS_RECLAIM annotation +dnl # +AC_DEFUN([AC_AMDGPU_FS_RECLAIM_ACQUIRE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + fs_reclaim_acquire(0); + ],[ + AC_DEFINE(HAVE_FS_RECLAIM_ACQUIRE, 1, [fs_reclaim_acquire() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 0ccf8398c3bff..b716a297c45a5 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -138,6 +138,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CRTC_HELPER_FUNCS_ATOMIC_CHECK AC_AMDGPU_DEBUGFS_CREATE_FILE_SIZE AC_AMDGPU_DRM_GEM_TTM_VMAP + AC_AMDGPU_FS_RECLAIM_ACQUIRE AC_AMDGPU_DRM_MEMCPY_FROM_WC AC_AMDGPU_IS_COW_MAPPING AC_AMDGPU_VGA_REMOVE_VGACON diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index 2964bb26cea9e..aa26d4d279a22 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -13,5 +13,6 @@ #include #include #include +#include #endif diff --git a/include/kcl/kcl_sched_mm.h b/include/kcl/kcl_sched_mm.h new file mode 100644 index 0000000000000..3458dc2617c6a --- /dev/null +++ b/include/kcl/kcl_sched_mm.h @@ -0,0 +1,35 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _KCL_KCL_SCHED_MM_H +#define _KCL_KCL_SCHED_MM_H + +#include +#include +#include +#include +#include +#include + +#ifndef SHRINK_EMPTY +#define SHRINK_EMPTY (~0UL - 1) +#define SHRINK_STOP (~0UL) +#endif + +#ifndef HAVE_FS_RECLAIM_ACQUIRE +#ifdef CONFIG_LOCKDEP +extern void __fs_reclaim_acquire(void); +extern void __fs_reclaim_release(void); +static inline void fs_reclaim_acquire(gfp_t gfp_mask) { + return _kcl_fs_reclaim_acquire(gfp_mask); +} +static inline void fs_reclaim_release(gfp_t gfp_mask) { + return _kcl_fs_reclaim_release(gfp_mask); +} +#else +static inline void __fs_reclaim_acquire(void) { } +static inline void __fs_reclaim_release(void) { } +static inline void fs_reclaim_acquire(gfp_t gfp_mask) { } +static inline void fs_reclaim_release(gfp_t gfp_mask) { } +#endif +#endif + +#endif From 9167d0f4abd3639b4e78cc7a90e3620b4bcb6676 Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Mon, 15 Mar 2021 15:23:24 +0800 Subject: [PATCH 0375/1868] drm/amdkcl: fake memalloc_noreclaim_save() Signed-off-by: Shiwu Zhang --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../drm/amd/dkms/m4/memalloc_noreclaim_save.m4 | 16 ++++++++++++++++ include/kcl/kcl_sched_mm.h | 18 ++++++++++++++++-- 3 files changed, 33 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/memalloc_noreclaim_save.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index b716a297c45a5..9739c68a6f562 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -139,6 +139,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DEBUGFS_CREATE_FILE_SIZE AC_AMDGPU_DRM_GEM_TTM_VMAP AC_AMDGPU_FS_RECLAIM_ACQUIRE + AC_AMDGPU_MEMALLOC_NORECLAIM_SAVE AC_AMDGPU_DRM_MEMCPY_FROM_WC AC_AMDGPU_IS_COW_MAPPING AC_AMDGPU_VGA_REMOVE_VGACON diff --git a/drivers/gpu/drm/amd/dkms/m4/memalloc_noreclaim_save.m4 b/drivers/gpu/drm/amd/dkms/m4/memalloc_noreclaim_save.m4 new file mode 100644 index 0000000000000..f9d0ba9a842cf --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/memalloc_noreclaim_save.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit 4e544bac8267f65a0bf06aed1bde9964da4812ed +dnl # PCI: Add pci_dev_id() helper +dnl # +AC_DEFUN([AC_AMDGPU_MEMALLOC_NORECLAIM_SAVE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + memalloc_noreclaim_save(); + ], [ + AC_DEFINE(HAVE_MEMALLOC_NORECLAIM_SAVE, 1, + [memalloc_noreclaim_save() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_sched_mm.h b/include/kcl/kcl_sched_mm.h index 3458dc2617c6a..be8915e298c62 100644 --- a/include/kcl/kcl_sched_mm.h +++ b/include/kcl/kcl_sched_mm.h @@ -29,7 +29,21 @@ static inline void __fs_reclaim_acquire(void) { } static inline void __fs_reclaim_release(void) { } static inline void fs_reclaim_acquire(gfp_t gfp_mask) { } static inline void fs_reclaim_release(gfp_t gfp_mask) { } -#endif -#endif +#endif /* CONFIG_LOCKDEP */ +#endif /* HAVE_FS_RECLAIM_ACQUIRE */ + +#ifndef HAVE_MEMALLOC_NORECLAIM_SAVE +static inline unsigned int memalloc_noreclaim_save(void) +{ + unsigned int flags = current->flags & PF_MEMALLOC; + current->flags |= PF_MEMALLOC; + return flags; +} + +static inline void memalloc_noreclaim_restore(unsigned int flags) +{ + current->flags = (current->flags & ~PF_MEMALLOC) | flags; +} +#endif /* HAVE_MEMALLOC_NORECLAIM_SAVE */ #endif From caf13146e8e3c56a132755cea4cffceab007d1ef Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Mon, 15 Mar 2021 20:10:01 +0800 Subject: [PATCH 0376/1868] drm/amdkcl: fake the macro of __GFP_KSWAPD_RECLAIM Signed-off-by: Shiwu Zhang --- include/kcl/kcl_kernel.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/kcl/kcl_kernel.h b/include/kcl/kcl_kernel.h index f93febef548d8..ef5bdee50ee36 100644 --- a/include/kcl/kcl_kernel.h +++ b/include/kcl/kcl_kernel.h @@ -23,4 +23,9 @@ #define ALIGN_DOWN(x, a) __ALIGN_KERNEL((x) - ((a) - 1), (a)) #endif /* ALIGN_DOWN */ +#ifndef ___GFP_KSWAPD_RECLAIM +#define ___GFP_KSWAPD_RECLAIM 0x00u +#define __GFP_KSWAPD_RECLAIM ((__force gfp_t)___GFP_KSWAPD_RECLAIM) /* kswapd can wake */ +#endif /* ___GFP_KSWAPD_RECLAIM */ + #endif /* AMDKCL_KERNEL_H */ From adba414aa3e3b3714f45504d1261f72bfb13fafd Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Wed, 17 Mar 2021 17:36:05 +0800 Subject: [PATCH 0377/1868] drm/amdkcl: init the ddev->pdev for legacy os This is caused by "Upcast struct drm_device.dev to struct pci_device; replace pdev" v5.11-rc2-514-g36b73b051c41 Otherwise, NULL pointer dereference will be reported for drm_pci_set_busid: [ 55.850413] BUG: kernel NULL pointer dereference, address: 0000000000000038 [ 55.850456] #PF: supervisor read access in kernel mode [ 55.850482] #PF: error_code(0x0000) - not-present page [ 55.850507] PGD 0 P4D 0 [ 55.850524] Oops: 0000 [#1] SMP NOPTI [ 55.850545] CPU: 7 PID: 1687 Comm: Xorg Tainted: G OE 5.8.0-45-generic #51~20.04.1-Ubuntu [ 55.850587] Hardware name: System manufacturer System Product Name/PRIME Z390-A, BIOS 1201 07/29/2019 [ 55.850655] RIP: 0010:drm_pci_set_busid+0x16/0x80 [drm] [ 55.850681] Code: 8b 85 80 01 00 00 eb 86 c3 66 2e 0f 1f 84 00 00 00 00 00 90 0f 1f 44 00 00 55 31 d2 48 89 e5 53 48 8b 87 88 01 00 00 48 89 f3 <44> 8b 40 38 48 8b 40 10 45 89 c1 41 c1 e8 03 0f b6 88 e0 00 00 00 [ 55.850762] RSP: 0018:ffffb768c0fabd20 EFLAGS: 00010246 [ 55.850788] RAX: 0000000000000000 RBX: ffffa0745070a840 RCX: 0000000000000002 [ 55.850820] RDX: 0000000000000000 RSI: ffffa0745070a840 RDI: ffffa0742dbe0010 [ 55.850853] RBP: ffffb768c0fabd28 R08: 0000000000000000 R09: ffffffffc046e5d9 [ 55.850886] R10: 0000000000000000 R11: 0000000000000000 R12: ffffa0742dbe0010 [ 55.850918] R13: ffffa0742d2abe00 R14: ffffa0742dbe00b8 R15: ffffa0745070a840 [ 55.850952] FS: 00007f6673a15a40(0000) GS:ffffa0745ddc0000(0000) knlGS:0000000000000000 [ 55.850989] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 55.851016] CR2: 0000000000000038 CR3: 00000004506da006 CR4: 00000000003606e0 [ 55.851049] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 [ 55.851082] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 [ 55.851114] Call Trace: [ 55.851149] drm_setversion+0x14e/0x190 [drm] [ 55.851188] ? drm_ioctl_permit+0x80/0x80 [drm] [ 55.851227] drm_ioctl_kernel+0xae/0xf0 [drm] [ 55.851266] drm_ioctl+0x234/0x3d0 [drm] [ 55.851302] ? drm_ioctl_permit+0x80/0x80 [drm] [ 55.851449] amdgpu_drm_ioctl+0x4e/0x80 [amdgpu] [ 55.851478] ksys_ioctl+0x9d/0xd0 [ 55.851496] __x64_sys_ioctl+0x1a/0x20 [ 55.851519] do_syscall_64+0x49/0xc0 [ 55.851539] entry_SYSCALL_64_after_hwframe+0x44/0xa9 [ 55.851565] RIP: 0033:0x7f6673d7550b Signed-off-by: Shiwu Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index f06c7aea80e8c..f79a7a493848b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2353,6 +2353,7 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, goto err_free; #endif + ddev->pdev = pdev; pci_set_drvdata(pdev, ddev); amdgpu_init_debug_options(adev); From 77991ecb740c4aaeffc26c599b2aa94dccdad0af Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 11 Mar 2021 13:11:31 +0800 Subject: [PATCH 0378/1868] drm/amdkcl: add BIT_PER_TYPE macro This patch is caused by 'drm/amdkfd: Fix UBSAN shift-out-of-bounds warning' v5.11-2606-g9f3ada6b3e86 Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_bitops.h | 11 +++++++++++ 2 files changed, 12 insertions(+) create mode 100644 include/kcl/kcl_bitops.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index b9e45108b818c..d6fc929d16b12 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -63,6 +63,7 @@ #include #include #include +#include #include #include #include "kcl/kcl_amdgpu_drm_fb_helper.h" diff --git a/include/kcl/kcl_bitops.h b/include/kcl/kcl_bitops.h new file mode 100644 index 0000000000000..f022f59a6a772 --- /dev/null +++ b/include/kcl/kcl_bitops.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_BITOPS_BACKPORT_H +#define AMDKCL_BITOPS_BACKPORT_H + +#include +/* Copied froma include/linux/bitops.h */ +#ifndef BITS_PER_TYPE +#define BITS_PER_TYPE(type) (sizeof(type) * BITS_PER_BYTE) +#endif + +#endif From f9197e7830e4ec65e284a0a3fca64fcc2f745af7 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 11 Mar 2021 16:14:09 +0800 Subject: [PATCH 0379/1868] drm/amdkcl: change drm_framebuffer field access code to kcl_drm_gem_fb_set_obj This patch is caused by 'drm/amdgpu: Verify bo size can fit framebuffer size on init.' v5.11-2639-g9e429bf5aabb Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 28 +++++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 74f6c3ba2320b..5a2f4ecec0ef1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1425,6 +1425,30 @@ static int amdgpu_display_get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb return r; } +int amdgpu_display_gem_fb_init(struct drm_device *dev, + struct amdgpu_framebuffer *rfb, + const struct drm_mode_fb_cmd2 *mode_cmd, + struct drm_gem_object *obj) +{ + int ret; + kcl_drm_gem_fb_set_obj(&rfb->base, 0, obj); + drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd); + + ret = amdgpu_display_framebuffer_init(dev, rfb, mode_cmd, obj); + if (ret) + goto err; + + ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs); + if (ret) + goto err; + + return 0; +err: + drm_dbg_kms(dev, "Failed to init gem fb: %d\n", ret); + kcl_drm_gem_fb_set_obj(&rfb->base, 0, NULL); + return ret; +} + static int amdgpu_display_gem_fb_verify_and_init(struct drm_device *dev, struct amdgpu_framebuffer *rfb, struct drm_file *file_priv, @@ -1433,7 +1457,7 @@ static int amdgpu_display_gem_fb_verify_and_init(struct drm_device *dev, { int ret; - rfb->base.obj[0] = obj; + kcl_drm_gem_fb_set_obj(&rfb->base, 0, obj); drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd); /* Verify that the modifier is supported. */ if (!drm_any_plane_has_format(dev, mode_cmd->pixel_format, @@ -1462,7 +1486,7 @@ static int amdgpu_display_gem_fb_verify_and_init(struct drm_device *dev, return 0; err: drm_dbg_kms(dev, "Failed to verify and init gem fb: %d\n", ret); - rfb->base.obj[0] = NULL; + kcl_drm_gem_fb_set_obj(&rfb->base, 0, NULL); return ret; } From 078d0e1c7f2a680d3238f3ea290a297901b7cebe Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 15 Mar 2021 16:58:47 +0800 Subject: [PATCH 0380/1868] drm/amdkcl: fake drm_err macro This patch is caused by 'drm/amdgpu: Verify bo size can fit framebuffer size on init.' v5.11-2639-g9e429bf5aabb Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c | 19 +++++++++++++++++++ include/kcl/kcl_drm_print.h | 20 ++++++++++++++++---- 2 files changed, 35 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c index 0c47443e0f189..b5d9e1a9113a3 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c @@ -83,3 +83,22 @@ void drm_dev_dbg(const struct device *dev, int category, } EXPORT_SYMBOL(drm_dev_dbg); #endif + +#if !defined(HAVE_DRM_ERR_MACRO) +void kcl_drm_err(const char *format, ...) +{ + struct va_format vaf; + va_list args; + + va_start(args, format); + vaf.fmt = format; + vaf.va = &args; + + printk(KERN_ERR "[" DRM_NAME ":%ps] *ERROR* %pV", + __builtin_return_address(0), &vaf); + + va_end(args); +} +EXPORT_SYMBOL(kcl_drm_err); + +#endif diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index 10ba443b49303..c51497dc79f3e 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -27,6 +27,7 @@ #include #include +#include #if !defined(HAVE_DRM_DRM_PRINT_H) /* Copied from d8187177b0b1 include/drm/drm_print.h */ @@ -102,10 +103,20 @@ void drm_mm_print(const struct drm_mm *mm, struct drm_printer *p) _DRM_PRINTK(_once, NOTICE, fmt, ##__VA_ARGS__) #endif -#ifndef DRM_ERROR -#define DRM_ERROR(fmt, ...) \ - drm_printk(KERN_ERR, DRM_UT_NONE, fmt, ##__VA_ARGS__) -#endif +#ifndef drm_err +#define drm_err(drm, fmt, ...) \ + dev_err((drm)->dev, "[drm] " fmt, ##__VA_ARGS__) + +__printf(1, 2) +void kcl_drm_err(const char *format, ...); + +#undef DRM_ERROR +#define DRM_ERROR(fmt, ...) \ + kcl_drm_err(fmt, ##__VA_ARGS__) + +#else +#define HAVE_DRM_ERR_MACRO +#endif /* drm_err */ #if !defined(DRM_DEV_DEBUG) #define DRM_DEV_DEBUG(dev, fmt, ...) \ @@ -142,4 +153,5 @@ static inline bool drm_debug_enabled(unsigned int category) return unlikely(drm_debug & category); } #endif /* HAVE_DRM_DEBUG_ENABLED */ + #endif From 498c4727bedb4b5d75c274966df359ac1677283a Mon Sep 17 00:00:00 2001 From: charles sun Date: Sun, 14 Mar 2021 19:19:10 +0800 Subject: [PATCH 0381/1868] the dcn301_calculate_wm_and_dl() calculation exposed a issue - switch to dcn30 version for now. still need to follow up with dcn301 watermark updates version. Signed-off-by: Charles Sun Reviewed-by: Nikola Cornij Acked-by: Charles Sun --- .../gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c index c3653c6e878a4..045c008335866 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c @@ -1396,7 +1396,7 @@ static struct resource_funcs dcn301_res_pool_funcs = { .link_enc_create = dcn301_link_encoder_create, .panel_cntl_create = dcn301_panel_cntl_create, .validate_bandwidth = dcn30_validate_bandwidth, - .calculate_wm_and_dlg = dcn301_calculate_wm_and_dlg, + .calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg, .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, .populate_dml_pipes = dcn30_populate_dml_pipes_from_context, .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, From b3a4745025be8ccefd767fc07bf721e39a48e625 Mon Sep 17 00:00:00 2001 From: Dennis Li Date: Fri, 5 Mar 2021 11:16:29 +0800 Subject: [PATCH 0382/1868] drm/amdgpu: remove reset lock from low level functions It is easy to cause performance drop issue when using lock in low level functions. Signed-off-by: Dennis Li Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index d59361ea63589..17c33193d645f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -614,13 +614,10 @@ uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, if ((reg * 4) < adev->rmmio_size) { if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && - amdgpu_sriov_runtime(adev) && - down_read_trylock(&adev->reset_domain->sem)) { + amdgpu_sriov_runtime(adev)) ret = amdgpu_kiq_rreg(adev, reg, 0); - up_read(&adev->reset_domain->sem); - } else { + else ret = readl(((void __iomem *)adev->rmmio) + (reg * 4)); - } } else { ret = adev->pcie_rreg(adev, reg * 4); } @@ -741,13 +738,10 @@ void amdgpu_device_wreg(struct amdgpu_device *adev, if ((reg * 4) < adev->rmmio_size) { if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && - amdgpu_sriov_runtime(adev) && - down_read_trylock(&adev->reset_domain->sem)) { + amdgpu_sriov_runtime(adev)) amdgpu_kiq_wreg(adev, reg, v, 0); - up_read(&adev->reset_domain->sem); - } else { + else writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); - } } else { adev->pcie_wreg(adev, reg * 4, v); } From 16894a57304fbd61a404c273542d1150ef065623 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 17 Mar 2021 15:07:31 +0800 Subject: [PATCH 0383/1868] drm/amdkcl: cleanup HAVE_DRM_MM_INSERT_MODE Reviewed-by: Guchun Chen Signed-off-by: Flora Cui --- drivers/gpu/drm/ttm/backport/backport.h | 1 + drivers/gpu/drm/ttm/ttm_range_manager.c | 7 --- include/kcl/backport/kcl_drm_mm_backport.h | 6 +- include/kcl/kcl_drm_mm.h | 68 ++++++++++++++++++++++ 4 files changed, 74 insertions(+), 8 deletions(-) create mode 100644 include/kcl/kcl_drm_mm.h diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index aa26d4d279a22..6d784a77a1906 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/gpu/drm/ttm/ttm_range_manager.c b/drivers/gpu/drm/ttm/ttm_range_manager.c index e06325e1ab6b9..ae11d07eb63a8 100644 --- a/drivers/gpu/drm/ttm/ttm_range_manager.c +++ b/drivers/gpu/drm/ttm/ttm_range_manager.c @@ -75,16 +75,9 @@ static int ttm_range_man_alloc(struct ttm_resource_manager *man, if (!node) return -ENOMEM; -#ifndef HAVE_DRM_MM_INSERT_MODE - if (place->flags & TTM_PL_FLAG_TOPDOWN) { - sflags = DRM_MM_SEARCH_BELOW; - aflags = DRM_MM_CREATE_TOP; - } -#else mode = DRM_MM_INSERT_BEST; if (place->flags & TTM_PL_FLAG_TOPDOWN) mode = DRM_MM_INSERT_HIGH; -#endif ttm_resource_init(bo, place, &node->base); diff --git a/include/kcl/backport/kcl_drm_mm_backport.h b/include/kcl/backport/kcl_drm_mm_backport.h index 8c20d53ed7f4f..1a2614d47ab59 100644 --- a/include/kcl/backport/kcl_drm_mm_backport.h +++ b/include/kcl/backport/kcl_drm_mm_backport.h @@ -8,7 +8,7 @@ * with rbtrees */ -#include +#include #ifndef HAVE_DRM_MM_INSERT_NODE_THREE_PARAMETERS static inline int _kcl_drm_mm_insert_node(struct drm_mm *mm, @@ -20,4 +20,8 @@ static inline int _kcl_drm_mm_insert_node(struct drm_mm *mm, #define drm_mm_insert_node _kcl_drm_mm_insert_node #endif /* HAVE_DRM_MM_INSERT_NODE_THREE_PARAMETERS */ +#ifndef HAVE_DRM_MM_INSERT_MODE +#define drm_mm_insert_node_in_range _kcl_drm_mm_insert_node_in_range +#endif + #endif /* AMDKCL_DRM_MM_H */ diff --git a/include/kcl/kcl_drm_mm.h b/include/kcl/kcl_drm_mm.h new file mode 100644 index 0000000000000..5387e6c05bc65 --- /dev/null +++ b/include/kcl/kcl_drm_mm.h @@ -0,0 +1,68 @@ +/************************************************************************** + * + * Copyright 2006-2008 Tungsten Graphics, Inc., Cedar Park, TX. USA. + * Copyright 2016 Intel Corporation + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * + **************************************************************************/ +/* + * Authors: + * Thomas Hellstrom + */ +#ifndef _KCL_KCL_DRM_MM_H_H_ +#define _KCL_KCL_DRM_MM_H_H_ +#include + +#ifndef HAVE_DRM_MM_INSERT_MODE +/* Copied from 4e64e5539d15 include/drm/drm_mm.h */ +enum drm_mm_insert_mode { + DRM_MM_INSERT_BEST = 0, + DRM_MM_INSERT_LOW, + DRM_MM_INSERT_HIGH, + DRM_MM_INSERT_EVICT, +}; + +static inline +int _kcl_drm_mm_insert_node_in_range(struct drm_mm * const mm, + struct drm_mm_node * const node, + u64 size, u64 alignment, + unsigned long color, + u64 range_start, u64 range_end, + enum drm_mm_insert_mode mode) +{ + enum drm_mm_search_flags sflags = DRM_MM_SEARCH_BEST; + enum drm_mm_allocator_flags aflags = DRM_MM_CREATE_DEFAULT; + + if (mode == DRM_MM_INSERT_HIGH) { + sflags = DRM_MM_SEARCH_BELOW; + aflags = DRM_MM_CREATE_TOP; + } + + return drm_mm_insert_node_in_range_generic(mm, node, size, + alignment, color, range_start, range_end, + sflags, aflags); +} +#endif /* HAVE_DRM_MM_INSERT_MODE */ + +#endif From feef350402a196566ec9430873d393ac9450c78d Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Thu, 25 Mar 2021 16:03:17 +0800 Subject: [PATCH 0384/1868] drm/amdkcl: add Centos7.3, 7.4 and 7.6 phantom support clear the compiling errors like lacking header files Signed-off-by: Shiwu Zhang Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 5 ++--- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 8 ++++---- drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 4 ++++ drivers/gpu/drm/amd/amdkcl/kcl_page_alloc.c | 1 - drivers/gpu/drm/amd/backport/backport.h | 2 +- drivers/gpu/drm/ttm/backport/backport.h | 1 + drivers/gpu/drm/ttm/ttm_tt.c | 4 ++++ include/kcl/backport/kcl_drm_prime.h | 4 ++++ include/kcl/backport/kcl_ttm_tt_backport.h | 12 ------------ include/kcl/kcl_drm_hdcp.h | 7 +++++++ include/kcl/kcl_sched_mm.h | 1 - 11 files changed, 27 insertions(+), 22 deletions(-) delete mode 100644 include/kcl/backport/kcl_ttm_tt_backport.h diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 5a2f4ecec0ef1..902b562438e91 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -504,9 +504,8 @@ int amdgpu_crtc_page_flip(struct drm_crtc *crtc, goto cleanup; } unpin: - if (unlikely(amdgpu_bo_unpin(new_abo) != 0)) { - DRM_ERROR("failed to unpin new abo in error path\n"); - } + amdgpu_bo_unpin(new_abo); + unreserve: amdgpu_bo_unreserve(new_abo); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index f79a7a493848b..58b8561ddba5c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2177,7 +2177,7 @@ static const struct amdgpu_asic_type_quirk asic_type_quirks[] = { {0x67FF, 0xF7, CHIP_POLARIS10}, }; -static const struct drm_driver amdgpu_kms_driver; +static struct drm_driver amdgpu_kms_driver; static void amdgpu_get_secondary_funcs(struct amdgpu_device *adev) { @@ -2336,11 +2336,11 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, ddev->driver_features &= ~DRIVER_ATOMIC; #else /* warn the user if they mix atomic and non-atomic capable GPUs */ - if ((kms_driver.driver_features & DRIVER_ATOMIC) && !supports_atomic) + if ((amdgpu_kms_driver.driver_features & DRIVER_ATOMIC) && !supports_atomic) DRM_ERROR("Mixing atomic and non-atomic capable GPUs!\n"); /* support atomic early so the atomic debugfs stuff gets created */ if (supports_atomic) - kms_driver.driver_features |= DRIVER_ATOMIC; + amdgpu_kms_driver.driver_features |= DRIVER_ATOMIC; #endif kcl_pci_create_measure_file(pdev); @@ -3009,7 +3009,7 @@ const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { DRM_IOCTL_DEF_DRV(AMDGPU_SEM, amdgpu_sem_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW) }; -static const struct drm_driver amdgpu_kms_driver = { +static struct drm_driver amdgpu_kms_driver = { .driver_features = 0 #ifdef HAVE_DRM_DEVICE_DRIVER_FEATURES diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c index b6397d3229e1b..cf43d436e5f5d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c @@ -64,7 +64,11 @@ void amdgpu_virt_init_setting(struct amdgpu_device *adev) adev->mode_info.num_crtc = 1; adev->enable_virtual_display = true; } +#ifdef HAVE_DRM_DEVICE_DRIVER_FEATURES ddev->driver_features &= ~DRIVER_ATOMIC; +#else + ddev->driver->driver_features &= ~DRIVER_ATOMIC; +#endif adev->cg_flags = 0; adev->pg_flags = 0; diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_page_alloc.c b/drivers/gpu/drm/amd/amdkcl/kcl_page_alloc.c index d56b220384800..4b6735959d945 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_page_alloc.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_page_alloc.c @@ -62,7 +62,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index d6fc929d16b12..15f2db83d31cd 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -19,6 +19,7 @@ #include #include #include +#include #include #include #include @@ -36,7 +37,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index 6d784a77a1906..f8fb0af23aa40 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -15,5 +15,6 @@ #include #include #include +#include #endif diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c index 412b0004842bd..63646d0ebfaed 100644 --- a/drivers/gpu/drm/ttm/ttm_tt.c +++ b/drivers/gpu/drm/ttm/ttm_tt.c @@ -203,10 +203,14 @@ int ttm_sg_tt_init(struct ttm_tt *ttm, struct ttm_buffer_object *bo, ttm_tt_init_fields(ttm, bo, page_flags, caching, 0); +#ifndef HAVE_TTM_SG_TT_INIT + ret = ttm_dma_tt_alloc_page_directory(ttm); +#else if (page_flags & TTM_TT_FLAG_EXTERNAL) ret = ttm_sg_tt_alloc_page_directory(ttm); else ret = ttm_dma_tt_alloc_page_directory(ttm); +#endif if (ret) { pr_err("Failed allocating page table\n"); return -ENOMEM; diff --git a/include/kcl/backport/kcl_drm_prime.h b/include/kcl/backport/kcl_drm_prime.h index 1c3895f60823d..33187c1891d71 100644 --- a/include/kcl/backport/kcl_drm_prime.h +++ b/include/kcl/backport/kcl_drm_prime.h @@ -33,7 +33,11 @@ #ifndef _KCL_BACKPORT_KCL__DRM_PRIME_H__H_ #define _KCL_BACKPORT_KCL__DRM_PRIME_H__H_ +#ifdef HAVE_DRM_DRMP_H +#include +#else #include +#endif #ifndef HAVE_DRM_PRIME_PAGES_TO_SG_3ARGS static inline diff --git a/include/kcl/backport/kcl_ttm_tt_backport.h b/include/kcl/backport/kcl_ttm_tt_backport.h deleted file mode 100644 index 3641f2408b0f3..0000000000000 --- a/include/kcl/backport/kcl_ttm_tt_backport.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef AMDKCL_BACKPORT_KCL_TTM_TT_BACKPORT_H -#define AMDKCL_BACKPORT_KCL_TTM_TT_BACKPORT_H - -#include -#include - -#ifndef HAVE_TTM_SG_TT_INIT -#define amdttm_sg_tt_init ttm_dma_tt_init -#endif - -#endif diff --git a/include/kcl/kcl_drm_hdcp.h b/include/kcl/kcl_drm_hdcp.h index ba77fb5c0973a..b3f6318e1f652 100644 --- a/include/kcl/kcl_drm_hdcp.h +++ b/include/kcl/kcl_drm_hdcp.h @@ -45,6 +45,13 @@ #define HDCP_STREAM_TYPE0 0x00 #define HDCP_STREAM_TYPE1 0x01 +/* introduced in v4.15-rc4-1351-g495eb7f877ab + * drm: Add some HDCP related #defines + */ +#ifndef DRM_HDCP_KSV_LEN +#define DRM_HDCP_KSV_LEN 5 +#endif + /* HDCP2.2 Msg IDs */ #define HDCP_2_2_NULL_MSG 1 #define HDCP_2_2_AKE_INIT 2 diff --git a/include/kcl/kcl_sched_mm.h b/include/kcl/kcl_sched_mm.h index be8915e298c62..31e59278e4b5d 100644 --- a/include/kcl/kcl_sched_mm.h +++ b/include/kcl/kcl_sched_mm.h @@ -7,7 +7,6 @@ #include #include #include -#include #ifndef SHRINK_EMPTY #define SHRINK_EMPTY (~0UL - 1) From ec1b0d16ea5e1cb6fdd4edca8e7dfa318bc7f495 Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Mon, 22 Mar 2021 17:08:28 +0800 Subject: [PATCH 0385/1868] drm/amdkcl: update the config.h Signed-off-by: Shiwu Zhang --- drivers/gpu/drm/amd/dkms/config/config.h | 829 +++++++++++++++++++++++ 1 file changed, 829 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 5c604c53ed971..1159d273a7753 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1,18 +1,317 @@ /* config/config.h. Generated from config.h.in by configure. */ /* config/config.h.in. Generated from configure.ac by autoheader. */ +/* whether invalidate_range_start() wants 2 args */ +#define HAVE_2ARGS_INVALIDATE_RANGE_START 1 + +/* whether invalidate_range_start() wants 5 args */ +/* #undef HAVE_5ARGS_INVALIDATE_RANGE_START */ + +/* whether access_ok(x, x) is available */ +#define HAVE_ACCESS_OK_WITH_TWO_ARGUMENTS 1 + +/* acpi_put_table() is available */ +/* #undef HAVE_ACPI_PUT_TABLE */ + +/* whether AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES is defined */ +#define HAVE_AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 1 + /* *FLAGS_.o support to take the path relative to $(obj) */ #define HAVE_AMDKCL_FLAGS_TAKE_PATH 1 +/* hmm support is enabled */ +#define HAVE_AMDKCL_HMM_MIRROR_ENABLED 1 + +/* amd_iommu_invalidate_ctx take arg type of pasid as u32 */ +#define HAVE_AMD_IOMMU_INVALIDATE_CTX_PASID_U32 1 + +/* amd_iommu_pc_supported() is available */ +/* #undef HAVE_AMD_IOMMU_PC_SUPPORTED */ + +/* arch_io_{reserve/free}_memtype_wc() are available */ +#define HAVE_ARCH_IO_RESERVE_FREE_MEMTYPE_WC 1 + /* Define to 1 if you have the header file. */ #define HAVE_ASM_FPU_API_H 1 /* Define to 1 if you have the header file. */ #define HAVE_ASM_SET_MEMORY_H 1 +/* backlight_device_set_brightness() is available */ +#define HAVE_BACKLIGHT_DEVICE_SET_BRIGHTNESS 1 + +/* whether CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL is defined */ +#define HAVE_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL 1 + +/* whether CHUNK_ID_SYNOBJ_IN_OUT is defined */ +#define HAVE_CHUNK_ID_SYNOBJ_IN_OUT 1 + +/* compat_ptr_ioctl() is available */ +#define HAVE_COMPAT_PTR_IOCTL 1 + +/* debugfs_create_file_size() is available */ +#define HAVE_DEBUGFS_CREATE_FILE_SIZE 1 + +/* devcgroup_check_permission() is available */ +#define HAVE_DEVCGROUP_CHECK_PERMISSION 1 + +/* devm_memremap_pages() wants struct dev_pagemap */ +#define HAVE_DEVM_MEMREMAP_PAGES_DEV_PAGEMAP 1 + +/* devm_memremap_pages() wants p,p,p,p interface */ +/* #undef HAVE_DEVM_MEMREMAP_PAGES_P_P_P_P */ + +/* there is 'range' field within dev_pagemap structure */ +#define HAVE_DEV_PAGEMAP_RANGE 1 + +/* dev_pm_set_driver_flags() is available */ +#define HAVE_DEV_PM_SET_DRIVER_FLAGS 1 + +/* dma_buf dynamic_mapping is available */ +/* #undef HAVE_DMA_BUF_OPS_DYNAMIC_MAPPING */ + +/* whether dma_fence_get_stub exits */ +#define HAVE_DMA_FENCE_GET_STUB 1 + +/* dma_fence_set_error() is available */ +#define HAVE_DMA_FENCE_SET_ERROR 1 + +/* dma_map_resource() is enabled */ +#define HAVE_DMA_MAP_RESOURCE 1 + +/* dma_map_sgtable() is enabled */ +#define HAVE_DMA_MAP_SGTABLE 1 + +/* dma_resv->seq is available */ +#define HAVE_DMA_RESV_SEQ 1 + +/* dma_resv->seq is seqcount_ww_mutex_t */ +#define HAVE_DMA_RESV_SEQCOUNT_WW_MUTEX_T 1 + +/* down_read_killable() is available */ +#define HAVE_DOWN_READ_KILLABLE 1 + +/* down_write_killable() is available */ +#define HAVE_DOWN_WRITE_KILLABLE 1 + +/* drm_dp_mst_connector_early_unregister() is available */ +#define HAVE_DP_MST_CONNECTOR_EARLY_UNREGISTER 1 + +/* drm_dp_mst_connector_late_register() is available */ +#define HAVE_DP_MST_CONNECTOR_LATE_REGISTER 1 + +/* drm_accurate_vblank_count() is available */ +/* #undef HAVE_DRM_ACCURATE_VBLANK_COUNT */ + +/* DRM_AMDGPU_FENCE_TO_HANDLE is defined */ +#define HAVE_DRM_AMDGPU_FENCE_TO_HANDLE 1 + /* Define to 1 if you have the header file. */ /* #undef HAVE_DRM_AMDGPU_PCIID_H */ +/* drm_atomic_get_old_crtc_state() and drm_atomic_get_new_crtc_state() are + available */ +#define HAVE_DRM_ATOMIC_GET_CRTC_STATE 1 + +/* drm_atomic_get_new_plane_state() is available */ +#define HAVE_DRM_ATOMIC_GET_NEW_PLANE_STATE 1 + +/* drm_atomic_helper_calc_timestamping_constants() is available */ +#define HAVE_DRM_ATOMIC_HELPER_CALC_TIMESTAMPING_CONSTANTS 1 + +/* drm_atomic_helper_check_plane_state() is available */ +#define HAVE_DRM_ATOMIC_HELPER_CHECK_PLANE_STATE 1 + +/* drm_atomic_helper_shutdown() is available */ +#define HAVE_DRM_ATOMIC_HELPER_SHUTDOWN 1 + +/* drm_atomic_helper_wait_for_flip_done() is available */ +#define HAVE_DRM_ATOMIC_HELPER_WAIT_FOR_FLIP_DONE 1 + +/* {drm_atomic_helper_crtc_set_property, drm_atomic_helper_plane_set_property, + drm_atomic_helper_connector_set_property, drm_atomic_helper_connector_dpms} + is available */ +/* #undef HAVE_DRM_ATOMIC_HELPER_XXX_SET_PROPERTY */ + +/* drm_atomic_nonblocking_commit() is available */ +#define HAVE_DRM_ATOMIC_NONBLOCKING_COMMIT 1 + +/* drm_atomic_plane_disabling() wants drm_plane_state * arg */ +#define HAVE_DRM_ATOMIC_PLANE_DISABLING_DRM_PLANE_STATE 1 + +/* drm_atomic_private_obj_init() is available */ +#define HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT 1 + +/* drm_atomic_private_obj_init() has p,p,p,p interface */ +#define HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT_P_P_P_P 1 + +/* whether struct drm_atomic_state have async_update */ +#define HAVE_DRM_ATOMIC_STATE_ASYNC_UPDATE 1 + +/* drm_atomic_state_put() is available */ +#define HAVE_DRM_ATOMIC_STATE_PUT 1 + +/* drm_color_lut_size() is available */ +#define HAVE_DRM_COLOR_LUT_SIZE 1 + +/* drm_connector_for_each_possible_encoder() wants 2 arguments */ +#define HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS 1 + +/* struct drm_connector_funcs has register members */ +#define HAVE_DRM_CONNECTOR_FUNCS_REGISTER 1 + +/* atomic_best_encoder take 2nd arg type of state as struct drm_atomic_state + */ +#define HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_BEST_ENCODER_ARG_DRM_ATOMIC_STATE 1 + +/* drm_connector_helper_funcs->atomic_check() wants struct drm_atomic_state + arg */ +#define HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE 1 + +/* drm_connector_init_with_ddc() is available */ +#define HAVE_DRM_CONNECTOR_INIT_WITH_DDC 1 + +/* drm_connector_list_iter_begin() is available */ +#define HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN 1 + +/* connector property "max bpc" is available */ +#define HAVE_DRM_CONNECTOR_PROPERTY_MAX_BPC 1 + +/* drm_connector_put() is available */ +#define HAVE_DRM_CONNECTOR_PUT 1 + +/* connector reference counting is available */ +#define HAVE_DRM_CONNECTOR_REFERENCE_COUNTING_SUPPORTED 1 + +/* struct drm_connector_state has hdcp_content_type member */ +#define HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE 1 + +/* drm_connector_unreference() is available */ +/* #undef HAVE_DRM_CONNECTOR_UNREFERENCE */ + +/* drm_connector_xxx() drop _mode_ */ +#define HAVE_DRM_CONNECTOR_XXX_DROP_MODE 1 + +/* ddrm_atomic_stat has __drm_crtcs_state */ +/* #undef HAVE_DRM_CRTCS_STATE_MEMBER */ + +/* drm_crtc_accurate_vblank_count() is available */ +#define HAVE_DRM_CRTC_ACCURATE_VBLANK_COUNT 1 + +/* drm_crtc_enable_color_mgmt() is available */ +#define HAVE_DRM_CRTC_ENABLE_COLOR_MGMT 1 + +/* drm_crtc_from_index() is available */ +#define HAVE_DRM_CRTC_FROM_INDEX 1 + +/* drm_crtc_helper_funcs->atomic_check() wants struct drm_atomic_state arg */ +#define HAVE_DRM_CRTC_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE 1 + +/* drm_crtc_init_with_planes() wants name */ +#define HAVE_DRM_CRTC_INIT_WITH_PLANES_VALID_WITH_NAME 1 + +/* drm_debug_enabled() is available */ +#define HAVE_DRM_DEBUG_ENABLED 1 + +/* dev_device->driver_features is available */ +#define HAVE_DRM_DEVICE_DRIVER_FEATURES 1 + +/* drm_device->filelist_mutex is available */ +#define HAVE_DRM_DEVICE_FILELIST_MUTEX 1 + +/* drm_device->open_count is int */ +/* #undef HAVE_DRM_DEVICE_OPEN_COUNT_INT */ + +/* drm_dev_dbg() is available */ +#define HAVE_DRM_DEV_DBG 1 + +/* drm_dev_put() is available */ +#define HAVE_DRM_DEV_PUT 1 + +/* drm_dev_unplug() is available */ +#define HAVE_DRM_DEV_UNPLUG 1 + +/* display_info->hdmi.scdc.scrambling are available */ +#define HAVE_DRM_DISPLAY_INFO_HDMI_SCDC_SCRAMBLING 1 + +/* display_info->max_tmds_clock is available */ +#define HAVE_DRM_DISPLAY_INFO_MAX_TMDS_CLOCK 1 + +/* struct drm_display_info has monitor_range member */ +#define HAVE_DRM_DISPLAY_INFO_MONITOR_RANGE 1 + +/* drm_dp_atomic_find_vcpi_slots() is available */ +#define HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS 1 + +/* drm_dp_atomic_find_vcpi_slots() wants 5args */ +#define HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS_5ARGS 1 + +/* drm_dp_calc_pbn_mode() wants 3args */ +#define HAVE_DRM_DP_CALC_PBN_MODE_3ARGS 1 + +/* drm_dp_cec* correlation functions are available */ +#define HAVE_DRM_DP_CEC_CORRELATION_FUNCTIONS 1 + +/* drm_dp_cec_register_connector() wants p,p interface */ +#define HAVE_DRM_DP_CEC_REGISTER_CONNECTOR_PP 1 + +/* drm_dp_mst_add_affected_dsc_crtcs() is available */ +#define HAVE_DRM_DP_MST_ADD_AFFECTED_DSC_CRTCS 1 + +/* drm_dp_mst_allocate_vcpi() has p,p,i,i interface */ +#define HAVE_DRM_DP_MST_ALLOCATE_VCPI_P_P_I_I 1 + +/* drm_dp_mst_atomic_check() is available */ +#define HAVE_DRM_DP_MST_ATOMIC_CHECK 1 + +/* drm_dp_mst_atomic_enable_dsc() is available */ +#define HAVE_DRM_DP_MST_ATOMIC_ENABLE_DSC 1 + +/* drm_dp_mst_detect_port() wants p,p,p,p args */ +#define HAVE_DRM_DP_MST_DETECT_PORT_PPPP 1 + +/* drm_dp_mst_dsc_aux_for_port() is available */ +#define HAVE_DRM_DP_MST_DSC_AUX_FOR_PORT 1 + +/* drm_dp_mst_{get,put}_port_malloc() is available */ +#define HAVE_DRM_DP_MST_GET_PUT_PORT_MALLOC 1 + +/* struct drm_dp_mst_topology_cbs->destroy_connector is available */ +/* #undef HAVE_DRM_DP_MST_TOPOLOGY_CBS_DESTROY_CONNECTOR */ + +/* struct drm_dp_mst_topology_cbs has hotplug member */ +/* #undef HAVE_DRM_DP_MST_TOPOLOGY_CBS_HOTPLUG */ + +/* struct drm_dp_mst_topology_cbs->register_connector is available */ +/* #undef HAVE_DRM_DP_MST_TOPOLOGY_CBS_REGISTER_CONNECTOR */ + +/* drm_dp_mst_topology_mgr_init() wants drm_device arg */ +#define HAVE_DRM_DP_MST_TOPOLOGY_MGR_INIT_DRM_DEV 1 + +/* drm_dp_mst_topology_mgr_resume() wants 2 args */ +#define HAVE_DRM_DP_MST_TOPOLOGY_MGR_RESUME_2ARGS 1 + +/* drm_dp_send_real_edid_checksum() is available */ +#define HAVE_DRM_DP_SEND_REAL_EDID_CHECKSUM 1 + +/* drm_dp_start_crc() is available */ +#define HAVE_DRM_DP_START_CRC 1 + +/* drm_driver->gem_prime_res_obj() is available */ +/* #undef HAVE_DRM_DRIVER_GEM_PRIME_RES_OBJ */ + +/* drm_driver->get_scanout_position() return bool */ +/* #undef HAVE_DRM_DRIVER_GET_SCANOUT_POSITION_RETURN_BOOL */ + +/* drm_driver->get_vblank_timestamp() return bool */ +/* #undef HAVE_DRM_DRIVER_GET_VBLANK_TIMESTAMP_RETURN_BOOL */ + +/* drm_calc_vbltimestamp_from_scanoutpos() use ktime_t arg */ +/* #undef HAVE_DRM_DRIVER_GET_VBLANK_TIMESTAMP_USE_KTIMER_T_ARG */ + +/* drm_driver->release() is available */ +#define HAVE_DRM_DRIVER_RELEASE 1 + /* Define to 1 if you have the header file. */ /* #undef HAVE_DRM_DRMP_H */ @@ -50,6 +349,9 @@ */ #define HAVE_DRM_DRM_GEM_FRAMEBUFFER_HELPER_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_GEM_TTM_HELPER_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_HDCP_H 1 @@ -77,12 +379,290 @@ /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_VBLANK_H 1 +/* drm_driver_feature DRIVER_IRQ_SHARED is available */ +/* #undef HAVE_DRM_DRV_DRIVER_IRQ_SHARED */ + +/* drm_driver_feature DRIVER_PRIME is available */ +/* #undef HAVE_DRM_DRV_DRIVER_PRIME */ + +/* drm_driver_feature DRIVER_SYNCOBJ_TIMELINE is available */ +#define HAVE_DRM_DRV_DRIVER_SYNCOBJ_TIMELINE 1 + +/* drm_gem_prime_export() with p,i arg is available */ +#define HAVE_DRM_DRV_GEM_PRIME_EXPORT_PI 1 + +/* drm_edid_to_eld() are available */ +/* #undef HAVE_DRM_EDID_TO_ELD */ + +/* drm_encoder_find() wants file_priv */ +#define HAVE_DRM_ENCODER_FIND_VALID_WITH_FILE 1 + +/* drm_fb_helper_single_add_all_connectors() && + drm_fb_helper_remove_one_connector() are symbol */ +/* #undef HAVE_DRM_FB_HELPER_ADD_REMOVE_CONNECTORS */ + +/* drm_fb_helper_fill_info() is available */ +#define HAVE_DRM_FB_HELPER_FILL_INFO 1 + +/* drm_fb_helper_init() has 2 args */ +#define HAVE_DRM_FB_HELPER_INIT_2ARGS 1 + +/* drm_fb_helper_init() has 3 args */ +/* #undef HAVE_DRM_FB_HELPER_INIT_3ARGS */ + +/* whether drm_fb_helper_lastclose() is available */ +#define HAVE_DRM_FB_HELPER_LASTCLOSE 1 + +/* drm_fb_helper_remove_conflicting_pci_framebuffers() is available */ +#define HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS 1 + +/* drm_fb_helper_remove_conflicting_pci_framebuffers() wants p,i,p args */ +/* #undef HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PIP */ + +/* drm_fb_helper_remove_conflicting_pci_framebuffers() wants p,p args */ +#define HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP 1 + +/* drm_fb_helper_set_suspend_unlocked() is available */ +#define HAVE_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED 1 + +/* drm_format_info.block_w and rm_format_info.block_h is available */ +#define HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED 1 + +/* whether struct drm_framebuffer have format */ +#define HAVE_DRM_FRAMEBUFFER_FORMAT 1 + +/* drm_gem_map_attach() wants 2 arguments */ +/* #undef HAVE_DRM_GEM_MAP_ATTACH_2ARGS */ + +/* drm_gem_object_lookup() wants 2 args */ +#define HAVE_DRM_GEM_OBJECT_LOOKUP_2ARGS 1 + +/* drm_gem_object_put_locked() is available */ +#define HAVE_DRM_GEM_OBJECT_PUT_LOCKED 1 + +/* drm_gem_object_put_unlocked() is available */ +/* #undef HAVE_DRM_GEM_OBJECT_PUT_UNLOCKED */ + +/* ttm_buffer_object->base is available */ +#define HAVE_DRM_GEM_OBJECT_RESV 1 + +/* drm_gem_ttm_vmap() is available */ +#define HAVE_DRM_GEM_TTM_VMAP 1 + +/* drm_get_format_info() is available */ +#define HAVE_DRM_GET_FORMAT_INFO 1 + +/* drm_get_format_name() has i,p interface */ +#define HAVE_DRM_GET_FORMAT_NAME_I_P 1 + +/* drm_hdcp_update_content_protection is available */ +#define HAVE_DRM_HDCP_UPDATE_CONTENT_PROTECTION 1 + +/* drm_hdmi_avi_infoframe_from_display_mode() has p,p,b interface */ +/* #undef HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_B */ + +/* drm_hdmi_avi_infoframe_from_display_mode() has p,p,p interface */ +#define HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_P 1 + +/* drm_hdmi_vendor_infoframe_from_display_mode() has p,p,p interface */ +#define HAVE_DRM_HDMI_VENDOR_INFOFRAME_FROM_DISPLAY_MODE_P_P_P 1 + +/* drm_helper_force_disable_all() is available */ +#define HAVE_DRM_HELPER_FORCE_DISABLE_ALL 1 + +/* drm_helper_mode_fill_fb_struct() wants dev arg */ +#define HAVE_DRM_HELPER_MODE_FILL_FB_STRUCT_DEV 1 + +/* drm_is_current_master() is available */ +#define HAVE_DRM_IS_CURRENT_MASTER 1 + +/* drm_kms_helper_is_poll_worker() is available */ +#define HAVE_DRM_KMS_HELPER_IS_POLL_WORKER 1 + +/* whether drm_mm_insert_mode is available */ +#define HAVE_DRM_MM_INSERT_MODE 1 + +/* drm_mm_insert_node has three parameters */ +#define HAVE_DRM_MM_INSERT_NODE_THREE_PARAMETERS 1 + +/* drm_mode_config->dp_subconnector_property is available */ +#define HAVE_DRM_MODE_CONFIG_DP_SUBCONNECTOR_PROPERTY 1 + +/* drm_mode_config_funcs->atomic_state_alloc() is available */ +#define HAVE_DRM_MODE_CONFIG_FUNCS_ATOMIC_STATE_ALLOC 1 + +/* drm_mode_config->helper_private is available */ +#define HAVE_DRM_MODE_CONFIG_HELPER_PRIVATE 1 + +/* drm_mode_get_hv_timing is available */ +#define HAVE_DRM_MODE_GET_HV_TIMING 1 + +/* drm_mode_is_420_xxx() is available */ +#define HAVE_DRM_MODE_IS_420_XXX 1 + +/* enum drm_mode_subconnector is available */ +/* #undef HAVE_DRM_MODE_SUBCONNECTOR_ENUM */ + +/* drm_need_swiotlb() is availablea */ +#define HAVE_DRM_NEED_SWIOTLB 1 + +/* drm atomic nonblocking commit support is available */ +#define HAVE_DRM_NONBLOCKING_COMMIT_SUPPORT 1 + +/* drm_plane_helper_check_state is available */ +/* #undef HAVE_DRM_PLANE_HELPER_CHECK_STATE */ + +/* drm_plane_mask is available */ +#define HAVE_DRM_PLANE_MASK 1 + +/* drm_plane_create_alpha_property, drm_plane_create_blend_mode_property are + available */ +#define HAVE_DRM_PLANE_PROPERTY_ALPHA_BLEND_MODE 1 + +/* drm_plane_create_color_properties is available */ +#define HAVE_DRM_PLANE_PROPERTY_COLOR_ENCODING_RANGE 1 + +/* drm_plane_create_rotation_property is available */ +#define HAVE_DRM_PLANE_PROPERTY_ROTATION 1 + +/* drm_prime_pages_to_sg() wants 3 arguments */ +#define HAVE_DRM_PRIME_PAGES_TO_SG_3ARGS 1 + +/* drm_prime_sg_to_dma_addr_array() is available */ +#define HAVE_DRM_PRIME_SG_TO_DMA_ADDR_ARRAY 1 + +/* drm_printer->prefix is available */ +#define HAVE_DRM_PRINTER_PREFIX 1 + +/* drm_syncobj_fence_get() is available */ +/* #undef HAVE_DRM_SYNCOBJ_FENCE_GET */ + +/* drm_syncobj_find_fence() is available */ +#define HAVE_DRM_SYNCOBJ_FIND_FENCE 1 + +/* whether drm_syncobj_find_fence() wants 3 args */ +/* #undef HAVE_DRM_SYNCOBJ_FIND_FENCE_3ARGS */ + +/* whether drm_syncobj_find_fence() wants 4 args */ +/* #undef HAVE_DRM_SYNCOBJ_FIND_FENCE_4ARGS */ + +/* whether drm_syncobj_find_fence() wants 5 args */ +#define HAVE_DRM_SYNCOBJ_FIND_FENCE_5ARGS 1 + /* Define to 1 if you have the header file. */ #define HAVE_DRM_TASK_BARRIER_H 1 +/* drm_universal_plane_init() wants 7 args */ +/* #undef HAVE_DRM_UNIVERSAL_PLANE_INIT_7ARGS */ + +/* drm_universal_plane_init() wants 8 args */ +/* #undef HAVE_DRM_UNIVERSAL_PLANE_INIT_8ARGS */ + +/* drm_universal_plane_init() wants 9 args */ +#define HAVE_DRM_UNIVERSAL_PLANE_INIT_9ARGS 1 + +/* drm_vma_node_verify_access() 2nd argument is drm_file */ +#define HAVE_DRM_VMA_NODE_VERIFY_ACCESS_HAS_DRM_FILE 1 + +/* Variable refresh rate(vrr) is supported */ +#define HAVE_DRM_VRR_SUPPORTED 1 + +/* fault_flag_allow_retry_first() is available */ +#define HAVE_FAULT_FLAG_ALLOW_RETRY_FIRST 1 + +/* drm_mode_object->free_cb is available */ +/* #undef HAVE_FREE_CB_IN_STRUCT_DRM_MODE_OBJECT */ + +/* fs_reclaim_acquire() is available */ +#define HAVE_FS_RECLAIM_ACQUIRE 1 + +/* drm_driver->gem_free_object_unlocked() is available */ +/* #undef HAVE_GEM_FREE_OBJECT_UNLOCKED_IN_DRM_DRIVER */ + +/* get_user_pages() wants 6 args */ +/* #undef HAVE_GET_USER_PAGES_6ARGS */ + +/* get_user_pages() wants gup_flags parameter */ +#define HAVE_GET_USER_PAGES_GUP_FLAGS 1 + +/* get_user_pages_remote() wants gup_flags parameter */ +/* #undef HAVE_GET_USER_PAGES_REMOTE_GUP_FLAGS */ + +/* get_user_pages_remote() is introduced with initial prototype */ +/* #undef HAVE_GET_USER_PAGES_REMOTE_INTRODUCED */ + +/* get_user_pages_remote() wants locked parameter */ +/* #undef HAVE_GET_USER_PAGES_REMOTE_LOCKED */ + +/* get_user_pages_remote() remove task_struct pointer */ +#define HAVE_GET_USER_PAGES_REMOTE_REMOVE_TASK_STRUCT 1 + +/* drm_connector_hdr_sink_metadata() is available */ +#define HAVE_HDR_SINK_METADATA 1 + +/* hmm remove the customizable pfn format */ +#define HAVE_HMM_DROP_CUSTOMIZABLE_PFN_FORMAT 1 + +/* hmm_range_fault() wants 1 arg */ +#define HAVE_HMM_RANGE_FAULT_1ARG 1 + +/* struct i2c_lock_operations is defined */ +#define HAVE_I2C_LOCK_OPERATIONS_STRUCT 1 + +/* i2c_new_client_device() is enabled */ +#define HAVE_I2C_NEW_CLIENT_DEVICE 1 + +/* idr_remove return void pointer */ +#define HAVE_IDR_REMOVE_RETURN_VOID_POINTER 1 + +/* in_compat_syscall is defined */ +#define HAVE_IN_COMPAT_SYSCALL 1 + +/* jiffies64_to_msecs() is available */ +#define HAVE_JIFFIES64_TO_MSECS 1 + /* kallsyms_lookup_name is available */ /* #undef HAVE_KALLSYMS_LOOKUP_NAME */ +/* kref_read() function is available */ +#define HAVE_KREF_READ 1 + +/* ksys_sync_helper() is available */ +#define HAVE_KSYS_SYNC_HELPER 1 + +/* kthread_{park/unpark/parkme/should_park}() is available */ +#define HAVE_KTHREAD_PARK_XX 1 + +/* kthread_{use,unuse}_mm() is available */ +#define HAVE_KTHREAD_USE_MM 1 + +/* ktime_get_boottime_ns() is available */ +#define HAVE_KTIME_GET_BOOTTIME_NS 1 + +/* ktime_get_mono_fast_ns is available */ +#define HAVE_KTIME_GET_MONO_FAST_NS 1 + +/* ktime_get_ns is available */ +#define HAVE_KTIME_GET_NS 1 + +/* ktime_get_raw_ns is available */ +#define HAVE_KTIME_GET_RAW_NS 1 + +/* ktime_get_real_seconds() is available */ +#define HAVE_KTIME_GET_REAL_SECONDS 1 + +/* kvcalloc() is available */ +#define HAVE_KVCALLOC 1 + +/* kvfree() is available */ +#define HAVE_KVFREE 1 + +/* kvmalloc_array() is available */ +#define HAVE_KVMALLOC_ARRAY 1 + +/* kv[mz]alloc() are available */ +#define HAVE_KVZALLOC_KVMALLOC 1 + /* Define to 1 if you have the header file. */ #define HAVE_LINUX_BITS_H 1 @@ -92,12 +672,18 @@ /* Define to 1 if you have the header file. */ /* #undef HAVE_LINUX_DMA_ATTRS_H */ +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_DMA_BUF_MAP_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_LINUX_DMA_FENCE_H 1 /* Define to 1 if you have the header file. */ #define HAVE_LINUX_DMA_RESV_H 1 +/* Define to 1 if you have the header file. */ +/* #undef HAVE_LINUX_FENCE_ARRAY_H */ + /* Define to 1 if you have the header file. */ #define HAVE_LINUX_IO_64_NONATOMIC_LO_HI_H 1 @@ -125,9 +711,252 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_SCHED_TASK_H 1 +/* list_bulk_move_tail() is available */ +#define HAVE_LIST_BULK_MOVE_TAIL 1 + +/* list_is_first() is available */ +#define HAVE_LIST_IS_FIRST 1 + +/* list_rotate_to_front() is available */ +#define HAVE_LIST_ROTATE_TO_FRONT 1 + +/* memalloc_nofs_{save,restore}() are available */ +#define HAVE_MEMALLOC_NOFS_SAVE 1 + +/* memalloc_noreclaim_save() is available */ +#define HAVE_MEMALLOC_NORECLAIM_SAVE 1 + +/* mem_encrypt_active() is available */ +#define HAVE_MEM_ENCRYPT_ACTIVE 1 + +/* mmgrab() is available */ +#define HAVE_MMGRAB 1 + +/* mmu_notifier_call_srcu() is available */ +/* #undef HAVE_MMU_NOTIFIER_CALL_SRCU */ + +/* mmu_notifier_put() is available */ +#define HAVE_MMU_NOTIFIER_PUT 1 + +/* mmu_notifier_range_blockable() is available */ +#define HAVE_MMU_NOTIFIER_RANGE_BLOCKABLE 1 + +/* mmu_notifier_synchronize() is available */ +#define HAVE_MMU_NOTIFIER_SYNCHRONIZE 1 + +/* mm_access() is available */ +#define HAVE_MM_ACCESS 1 + +/* release_pages() wants 2 args */ +#define HAVE_MM_RELEASE_PAGES_2ARGS 1 + +/* num_u32_u32 is available */ +#define HAVE_MUL_U32_U32 1 + +/* pcie_bandwidth_available() is available */ +#define HAVE_PCIE_BANDWIDTH_AVAILABLE 1 + +/* pci_enable_atomic_ops_to_root() exist */ +#define HAVE_PCIE_ENABLE_ATOMIC_OPS_TO_ROOT 1 + +/* pcie_get_speed_cap() and pcie_get_width_cap() exist */ +#define HAVE_PCIE_GET_SPEED_AND_WIDTH_CAP 1 + +/* PCI driver handles extended tags */ +#define HAVE_PCI_CONFIGURE_EXTENDED_TAGS 1 + +/* pci_dev_id() is available */ +#define HAVE_PCI_DEV_ID 1 + +/* pci_is_thunderbolt_attached() is available */ +#define HAVE_PCI_IS_THUNDERBOLD_ATTACHED 1 + +/* pci_pr3_present() is available */ +#define HAVE_PCI_PR3_PRESENT 1 + +/* pci_rebar_bytes_to_size() is available */ +#define HAVE_PCI_REBAR_BYTES_TO_SIZE 1 + +/* pci_upstream_bridge() is available */ +#define HAVE_PCI_UPSTREAM_BRIDGE 1 + +/* perf_event_update_userpage() is exported */ +#define HAVE_PERF_EVENT_UPDATE_USERPAGE 1 + +/* pfn_t is defined */ +#define HAVE_PFN_T 1 + +/* vm_insert_mixed() wants pfn_t arg */ +/* #undef HAVE_PFN_T_VM_INSERT_MIXED */ + +/* pm_genpd_remove_device() wants 2 arguments */ +/* #undef HAVE_PM_GENPD_REMOVE_DEVICE_2ARGS */ + +/* remove_conflicting_framebuffers() returns int */ +/* #undef HAVE_REMOVE_CONFLICTING_FRAMEBUFFERS_RETURNS_INT */ + +/* request_firmware_direct() is available */ +#define HAVE_REQUEST_FIRMWARE_DIRECT 1 + +/* reservation_object->staged is available */ +/* #undef HAVE_RESERVATION_OBJECT_STAGED */ + +/* sched_set_fifo_low() is available */ +#define HAVE_SCHED_SET_FIFO_LOW 1 + +/* seq_hex_dump() is available */ +#define HAVE_SEQ_HEX_DUMP 1 + +/* drm_driver->set_busid is available */ +/* #undef HAVE_SET_BUSID_IN_STRUCT_DRM_DRIVER */ + +/* whether si_mem_available() is available */ +#define HAVE_SI_MEM_AVAILABLE 1 + +/* strscpy() is available */ +#define HAVE_STRSCPY 1 + +/* struct dma_buf_ops->allow_peer2peer is available */ +/* #undef HAVE_STRUCT_DMA_BUF_OPS_ALLOW_PEER2PEER */ + +/* struct dma_buf_ops->pin() is available */ +#define HAVE_STRUCT_DMA_BUF_OPS_PIN 1 + +/* struct drm_connector_state->duplicated is available */ +#define HAVE_STRUCT_DRM_ATOMIC_STATE_DUPLICATED 1 + +/* struct drm_connector_state->colorspace is available */ +#define HAVE_STRUCT_DRM_CONNECTOR_STATE_COLORSPACE 1 + +/* struct drm_connector_state->self_refresh_aware is available */ +#define HAVE_STRUCT_DRM_CONNECTOR_STATE_SELF_REFRESH_AWARE 1 + +/* drm_connector->ycbcr_420_allowed is available */ +#define HAVE_STRUCT_DRM_CONNECTOR_YCBCR_420_ALLOWED 1 + +/* drm_crtc_funcs->enable_vblank() is available */ +#define HAVE_STRUCT_DRM_CRTC_FUNCS_ENABLE_VBLANK 1 + +/* crtc->funcs->gamma_set() wants 5 args */ +/* #undef HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_5ARGS */ + +/* crtc->funcs->gamma_set() wants 6 args */ +#define HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_6ARGS 1 + +/* struct drm_crtc_funcs->get_vblank_timestamp() is available */ +#define HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP 1 + +/* drm_crtc_funcs->{get,verify}_crc_sources() is available */ +#define HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VERIFY_CRC_SOURCES 1 + +/* drm_crtc_funcs->page_flip_target() is available */ +#define HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET 1 + +/* drm_crtc_funcs->page_flip_target() wants ctx parameter */ +#define HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET_CTX 1 + +/* drm_crtc_funcs->set_config() wants ctx parameter */ +#define HAVE_STRUCT_DRM_CRTC_FUNCS_SET_CONFIG_CTX 1 + +/* crtc->funcs->set_crc_source() is available */ +#define HAVE_STRUCT_DRM_CRTC_FUNCS_SET_CRC_SOURCE 1 + +/* crtc->funcs->set_crc_source() wants 2 args */ +#define HAVE_STRUCT_DRM_CRTC_FUNCS_SET_CRC_SOURCE_2ARGS 1 + +/* struct drm_crtc_state->async_flip is available */ +#define HAVE_STRUCT_DRM_CRTC_STATE_ASYNC_FLIP 1 + +/* struct drm_crtc_state has flag for flip */ +#define HAVE_STRUCT_DRM_CRTC_STATE_FLIP_FLAG 1 + +/* struct drm_crtc_state->pageflip_flags is available */ +/* #undef HAVE_STRUCT_DRM_CRTC_STATE_PAGEFLIP_FLAGS */ + +/* drm_gem_open_object is defined in struct drm_drv */ +/* #undef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK */ + +/* drm_pending_vblank_event->sequence is available */ +#define HAVE_STRUCT_DRM_PENDING_VBLANK_EVENT_SEQUENCE 1 + +/* drm_plane_helper_funcs->atomic_async_check() is available */ +#define HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_ASYNC_CHECK 1 + +/* drm_plane_helper_funcs->prepare_fb() wants const p arg */ +/* #undef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_PREPARE_FB_CONST */ + +/* drm_plane_helper_funcs->prepare_fb() wants p,p arg */ +#define HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_PREPARE_FB_PP 1 + +/* zone->managed_pages is available */ +/* #undef HAVE_STRUCT_ZONE_MANAGED_PAGES */ + +/* timer_setup() is available */ +#define HAVE_TIMER_SETUP 1 + +/* interval_tree_insert have struct rb_root_cached */ +#define HAVE_TREE_INSERT_HAVE_RB_ROOT_CACHED 1 + +/* ttm_sg_tt_init() is available */ +#define HAVE_TTM_SG_TT_INIT 1 + +/* __poll_t is available */ +#define HAVE_TYPE__POLL_T 1 + /* Define to 1 if you have the header file. */ #define HAVE_UAPI_LINUX_SCHED_TYPES_H 1 +/* vga_switcheroo_set_dynamic_switch() exist */ +/* #undef HAVE_VGA_SWITCHEROO_SET_DYNAMIC_SWITCH */ + +/* vmf_insert_*() are available */ +#define HAVE_VMF_INSERT 1 + +/* vmf_insert_mixed_prot() is available */ +#define HAVE_VMF_INSERT_MIXED_PROT 1 + +/* vmf_insert_pfn_{pmd,pud}() wants 3 args */ +/* #undef HAVE_VMF_INSERT_PFN_PMD_3ARGS */ + +/* vmf_insert_pfn_{pmd,pud}_prot() is available */ +#define HAVE_VMF_INSERT_PFN_PMD_PROT 1 + +/* vmf_insert_pfn_prot() is available */ +#define HAVE_VMF_INSERT_PFN_PROT 1 + +/* vmf_insert_pfn_pud() is available */ +/* #undef HAVE_VMF_INSERT_PFN_PUD */ + +/* vm_fault->{address/vam} is available */ +#define HAVE_VM_FAULT_ADDRESS_VMA 1 + +/* vm_insert_pfn_prot() is available */ +/* #undef HAVE_VM_INSERT_PFN_PROT */ + +/* vm_operations_struct->fault() wants 1 arg */ +#define HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG 1 + +/* wait_queue_entry_t exists */ +#define HAVE_WAIT_QUEUE_ENTRY 1 + +/* zone_managed_pages() is available */ +#define HAVE_ZONE_MANAGED_PAGES 1 + +/* __drm_atomic_helper_connector_destroy_state() wants 1 arg */ +#define HAVE___DRM_ATOMIC_HELPER_CONNECTOR_DESTROY_STATE_P 1 + +/* __drm_atomic_helper_crtc_destroy_state() wants 1 arg */ +#define HAVE___DRM_ATOMIC_HELPER_CRTC_DESTROY_STATE_P 1 + +/* __drm_atomic_helper_crtc_reset() is available */ +#define HAVE___DRM_ATOMIC_HELPER_CRTC_RESET 1 + +/* __kthread_should_park() is available */ +#define HAVE___KTHREAD_SHOULD_PARK 1 + +/* __print_array is available */ +#define HAVE___PRINT_ARRAY 1 + /* Define to the address where bug reports for this package should be sent. */ #define PACKAGE_BUGREPORT "" From bc8e2411582ec3e549ec95699977ee7e79f06f05 Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Wed, 24 Mar 2021 17:30:18 +0800 Subject: [PATCH 0386/1868] drm/amdkcl: re-generate the config.h Signed-off-by: Shiwu Zhang --- drivers/gpu/drm/amd/dkms/config/config.h | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 1159d273a7753..deeb11aad8f2a 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -11,7 +11,7 @@ #define HAVE_ACCESS_OK_WITH_TWO_ARGUMENTS 1 /* acpi_put_table() is available */ -/* #undef HAVE_ACPI_PUT_TABLE */ +#define HAVE_ACPI_PUT_TABLE 1 /* whether AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES is defined */ #define HAVE_AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 1 @@ -26,7 +26,7 @@ #define HAVE_AMD_IOMMU_INVALIDATE_CTX_PASID_U32 1 /* amd_iommu_pc_supported() is available */ -/* #undef HAVE_AMD_IOMMU_PC_SUPPORTED */ +#define HAVE_AMD_IOMMU_PC_SUPPORTED 1 /* arch_io_{reserve/free}_memtype_wc() are available */ #define HAVE_ARCH_IO_RESERVE_FREE_MEMTYPE_WC 1 @@ -449,6 +449,9 @@ /* drm_gem_ttm_vmap() is available */ #define HAVE_DRM_GEM_TTM_VMAP 1 +/* drm_gen_fb_init_with_funcs() is available */ +#define HAVE_DRM_GEN_FB_INIT_WITH_FUNCS 1 + /* drm_get_format_info() is available */ #define HAVE_DRM_GET_FORMAT_INFO 1 From e39d883f61e07b0eefe51c9131b1d22bd13dc702 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 21 Jan 2021 15:02:48 +0800 Subject: [PATCH 0387/1868] drm/amdkcl: rework dma-fence header file handling Reviewed-by: Guchun Chen Signed-off-by: Flora Cui --- include/kcl/header/linux/dma-fence-array.h | 11 +++++++++++ include/kcl/header/linux/dma-fence.h | 11 +++++++++++ include/kcl/kcl_fence.h | 7 +------ include/kcl/kcl_fence_array.h | 6 +++--- 4 files changed, 26 insertions(+), 9 deletions(-) create mode 100644 include/kcl/header/linux/dma-fence-array.h create mode 100644 include/kcl/header/linux/dma-fence.h diff --git a/include/kcl/header/linux/dma-fence-array.h b/include/kcl/header/linux/dma-fence-array.h new file mode 100644 index 0000000000000..49bb1fcd2a798 --- /dev/null +++ b/include/kcl/header/linux/dma-fence-array.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER__LINUX_DMA_FENCE_ARRAY_H_H_ +#define _KCL_HEADER__LINUX_DMA_FENCE_ARRAY_H_H_ + +#if defined(HAVE_LINUX_DMA_FENCE_H) +#include_next +#elif defined(HAVE_LINUX_FENCE_ARRAY_H) +#include +#endif + +#endif diff --git a/include/kcl/header/linux/dma-fence.h b/include/kcl/header/linux/dma-fence.h new file mode 100644 index 0000000000000..d4bb6177302a3 --- /dev/null +++ b/include/kcl/header/linux/dma-fence.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER__LINUX_DMA_FENCE_H_H_ +#define _KCL_HEADER__LINUX_DMA_FENCE_H_H_ + +#if defined(HAVE_LINUX_DMA_FENCE_H) +#include_next +#else +#include +#endif + +#endif diff --git a/include/kcl/kcl_fence.h b/include/kcl/kcl_fence.h index 7a869acf02b93..947efbf7e38aa 100644 --- a/include/kcl/kcl_fence.h +++ b/include/kcl/kcl_fence.h @@ -14,13 +14,8 @@ #include #include -#if !defined(HAVE_LINUX_DMA_FENCE_H) -#include -#include -#else #include -#include -#endif +#include #if !defined(HAVE_LINUX_DMA_FENCE_H) #define dma_fence_cb fence_cb diff --git a/include/kcl/kcl_fence_array.h b/include/kcl/kcl_fence_array.h index 8bce1cf8ff00c..1e8f37c5864d3 100644 --- a/include/kcl/kcl_fence_array.h +++ b/include/kcl/kcl_fence_array.h @@ -23,10 +23,10 @@ #ifndef AMDKCL_FENCE_ARRAY_H #define AMDKCL_FENCE_ARRAY_H +#include + #if !defined(HAVE_LINUX_DMA_FENCE_H) -#if defined(HAVE_LINUX_FENCE_ARRAY_H) -#include -#else +#if !defined(HAVE_LINUX_FENCE_ARRAY_H) #include /** From c4c9853cb3422df1130442ea05c09d6cb6e977ae Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Mon, 29 Mar 2021 20:24:42 +0800 Subject: [PATCH 0388/1868] drm/amdkcl: fix the autotest of drm_gem_ttm_helper.h Signed-off-by: Shiwu Zhang --- include/kcl/header/drm/drm_gem_ttm_helper.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/kcl/header/drm/drm_gem_ttm_helper.h b/include/kcl/header/drm/drm_gem_ttm_helper.h index 1f4610148dd07..5612902e4958d 100644 --- a/include/kcl/header/drm/drm_gem_ttm_helper.h +++ b/include/kcl/header/drm/drm_gem_ttm_helper.h @@ -1,8 +1,8 @@ /* SPDX-License-Identifier: MIT */ -#ifndef _KCL_HEADER_DRM_VBLANK_H_H_ -#define _KCL_HEADER_DRM_VBLANK_H_H_ +#ifndef _KCL_HEADER_DRM_GEM_TTM_HELPER_H_H_ +#define _KCL_HEADER_DRM_GEM_TTM_HELPER_H_H_ -#ifdef HAVE_DRM_DRM_DRM_GEM_TTM_HELPER_H +#ifdef HAVE_DRM_DRM_GEM_TTM_HELPER_H #include_next #endif From ee3d284a004057c61cde0f4f13d58ddae6c364e4 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 11 Oct 2023 16:46:45 +0800 Subject: [PATCH 0389/1868] drm/amdkcl: clear up the license left out during rebase Signed-off-by: Shiwu Zhang Signed-off-by: Asher Song --- .../drm/amd/amdkcl/kcl_drm_atomic_helper.c | 2 + .../gpu/drm/amd/amdkcl/kcl_drm_connector.c | 22 +++++++++- drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c | 31 +++++++++++++- drivers/gpu/drm/amd/amdkcl/kcl_memory.c | 32 ++++++++++++++- drivers/gpu/drm/amd/amdkcl/kcl_pci.c | 3 ++ drivers/gpu/drm/amd/backport/Makefile | 3 +- drivers/gpu/drm/amd/backport/backport.h | 1 + .../include/kcl/kcl_amdgpu_drm_fb_helper.h | 21 ---------- .../kcl_amdgpu_drm_gem_framebuffer_helper.h | 30 ++++++++++++++ drivers/gpu/drm/amd/backport/kcl_drm_drv.c | 28 ++++++++++++- .../backport/kcl_drm_gem_framebuffer_helper.c | 40 +++++++++++++++++++ .../backport/kcl_drm_atomic_helper_backport.h | 28 ++++++++++++- include/kcl/backport/kcl_drm_encoder.h | 1 + .../backport/kcl_drm_vma_manager_backport.h | 1 + include/kcl/backport/kcl_hmm.h | 9 ++++- include/kcl/backport/kcl_pci_backport.h | 2 +- include/kcl/kcl_device.h | 7 +++- include/kcl/kcl_dma_mapping.h | 1 + include/kcl/kcl_drm_fb.h | 1 + include/kcl/kcl_kernel.h | 1 + include/kcl/kcl_kthread.h | 1 + include/kcl/kcl_mm.h | 1 + include/kcl/kcl_pci.h | 2 + include/kcl/kcl_preempt.h | 2 +- include/kcl/kcl_rcupdate.h | 19 ++++++++- include/kcl/kcl_task_barrier.h | 24 ++++++++++- include/kcl/kcl_version.h | 2 +- 27 files changed, 281 insertions(+), 34 deletions(-) create mode 100644 drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_gem_framebuffer_helper.h create mode 100644 drivers/gpu/drm/amd/backport/kcl_drm_gem_framebuffer_helper.c diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c index 3e2cf46b8526c..58beb9fcedf38 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c @@ -30,6 +30,7 @@ #include #ifdef AMDKCL__DRM_ATOMIC_HELPER_PLANE_RESET +/* Copied from drivers/gpu/drm/drm_atomic_state_helper.c and modified for KCL */ void _kcl__drm_atomic_helper_plane_reset(struct drm_plane *plane, struct drm_plane_state *state) { @@ -49,6 +50,7 @@ EXPORT_SYMBOL(_kcl__drm_atomic_helper_plane_reset); #endif #ifndef HAVE___DRM_ATOMIC_HELPER_CRTC_RESET +/* Copied from drivers/gpu/drm/drm_atomic_state_helper.c */ void __drm_atomic_helper_crtc_reset(struct drm_crtc *crtc, struct drm_crtc_state *crtc_state) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c index a467ebb08a8f3..ebcb2ae541c33 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c @@ -1,4 +1,24 @@ -/* SPDX-License-Identifier: MIT */ +/* + * Copyright (c) 2016 Intel Corporation + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE. + */ #include #ifndef HAVE_DRM_CONNECTOR_INIT_WITH_DDC diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c index 900629e0dc0ed..139e955f225eb 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c @@ -1,4 +1,32 @@ -/* SPDX-License-Identifier: MIT */ +/* + * Copyright (c) 2006-2009 Red Hat Inc. + * Copyright (c) 2006-2008 Intel Corporation + * Copyright (c) 2007 Dave Airlie + * + * DRM framebuffer helper functions + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE. + * + * Authors: + * Dave Airlie + * Jesse Barnes + */ #include #include #include @@ -32,6 +60,7 @@ EXPORT_SYMBOL(drm_fb_helper_fill_info); #ifndef HAVE_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED /** + * Copied from drivers/gpu/drm/drm_fb_helper.c and modified for KCL. * _kcl_drm_fb_helper_set_suspend_stub - wrapper around fb_set_suspend * @fb_helper: driver-allocated fbdev helper * @state: desired state, zero to resume, non-zero to suspend diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_memory.c b/drivers/gpu/drm/amd/amdkcl/kcl_memory.c index 9d5358ca93b48..f5d947730e628 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_memory.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_memory.c @@ -1,6 +1,36 @@ -/* SPDX-License-Identifier: MIT */ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/************************************************************************** + * + * Copyright (c) 2006-2009 VMware, Inc., Palo Alto, CA., USA + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + **************************************************************************/ +/* + * Authors: Thomas Hellstrom + */ #include +/* Copied from drivers/gpu/drm/ttm/ttm_bo_vm.c and modified for KCL */ #ifndef HAVE_VMF_INSERT_MIXED_PROT vm_fault_t _kcl_vmf_insert_mixed_prot(struct vm_area_struct *vma, unsigned long addr, pfn_t pfn, pgprot_t pgprot) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_pci.c b/drivers/gpu/drm/amd/amdkcl/kcl_pci.c index 6cc6a80b921e4..42ca0b4a36945 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_pci.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_pci.c @@ -22,6 +22,7 @@ #include #if !defined(HAVE_PCIE_BANDWIDTH_AVAILABLE) +/* Copied from drivers/pci/probe.c and modified for KCL */ const unsigned char *_kcl_pcie_link_speed; const unsigned char _kcl_pcie_link_speed_stub[] = { @@ -43,6 +44,7 @@ const unsigned char _kcl_pcie_link_speed_stub[] = { PCI_SPEED_UNKNOWN /* F */ }; +/* Copied from drivers/pci/pci.c */ /** * pcie_bandwidth_available - determine minimum link settings of a PCIe * device and its bandwidth limitation @@ -320,6 +322,7 @@ EXPORT_SYMBOL_GPL(_kcl_pci_pr3_present); #endif /* HAVE_PCI_PR3_PRESENT */ #ifdef AMDKCL_CREATE_MEASURE_FILE +/* Copied from drivers/pci/pci-sysfs.c */ static ssize_t max_link_speed_show(struct device *dev, struct device_attribute *attr, char *buf) { diff --git a/drivers/gpu/drm/amd/backport/Makefile b/drivers/gpu/drm/amd/backport/Makefile index 115fc89f8204f..ba3805d29cbc3 100644 --- a/drivers/gpu/drm/amd/backport/Makefile +++ b/drivers/gpu/drm/amd/backport/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: MIT -BACKPORT_OBJS := kcl_drm_drv.o kcl_drm_gem_ttm_helper.o +BACKPORT_OBJS := kcl_drm_drv.o kcl_drm_gem_ttm_helper.o \ + kcl_drm_gem_framebuffer_helper.o amdgpu-y += $(addprefix ../backport/,$(BACKPORT_OBJS)) diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 15f2db83d31cd..7c48927ff0bd7 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -67,6 +67,7 @@ #include #include #include "kcl/kcl_amdgpu_drm_fb_helper.h" +#include "kcl/kcl_amdgpu_drm_gem_framebuffer_helper.h" #include "kcl/kcl_amdgpu.h" #include "kcl/kcl_amdgpu_drm_drv.h" #include "kcl/kcl_drm_gem_ttm_helper.h" diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h index 40a89aea46e78..b67bfda700d77 100644 --- a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h @@ -39,25 +39,4 @@ void drm_fb_helper_lastclose(struct drm_device *dev); void drm_fb_helper_output_poll_changed(struct drm_device *dev); #endif -static inline -void kcl_drm_gem_fb_set_obj(struct drm_framebuffer *fb, int index, struct drm_gem_object *obj) -{ -#ifdef HAVE_DRM_DRM_GEM_FRAMEBUFFER_HELPER_H - if (fb) - fb->obj[index] = obj; -#else - struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb); - (void)index; /* for compile un-used warning */ - if (afb) - afb->obj = obj; -#endif -} -#ifndef HAVE_DRM_DRM_GEM_FRAMEBUFFER_HELPER_H -struct drm_gem_object *drm_gem_fb_get_obj(struct drm_framebuffer *fb, - unsigned int plane); -void drm_gem_fb_destroy(struct drm_framebuffer *fb); -int drm_gem_fb_create_handle(struct drm_framebuffer *fb, struct drm_file *file, - unsigned int *handle); -#endif - #endif diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_gem_framebuffer_helper.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_gem_framebuffer_helper.h new file mode 100644 index 0000000000000..bbd3326b824bf --- /dev/null +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_gem_framebuffer_helper.h @@ -0,0 +1,30 @@ +#ifndef __AMDGPU_BACKPORT_KCL_AMDGPU_DRM_GEM_FRAMEBUFFER_HELPER_H__ +#define __AMDGPU_BACKPORT_KCL_AMDGPU_DRM_GEM_FRAMEBUFFER_HELPER_H__ + +#include +#include "amdgpu.h" + +static inline +void kcl_drm_gem_fb_set_obj(struct drm_framebuffer *fb, int index, struct drm_gem_object *obj) +{ +#ifdef HAVE_DRM_DRM_GEM_FRAMEBUFFER_HELPER_H + if (fb) + fb->obj[index] = obj; +#else + struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb); + (void)index; /* for compile un-used warning */ + if (afb) + afb->obj = obj; +#endif +} + +#ifndef HAVE_DRM_DRM_GEM_FRAMEBUFFER_HELPER_H +/* Copied from include/drm/drm_gem_framebuffer_helper.h */ +struct drm_gem_object *drm_gem_fb_get_obj(struct drm_framebuffer *fb, + unsigned int plane); +void drm_gem_fb_destroy(struct drm_framebuffer *fb); +int drm_gem_fb_create_handle(struct drm_framebuffer *fb, struct drm_file *file, + unsigned int *handle); +#endif + +#endif diff --git a/drivers/gpu/drm/amd/backport/kcl_drm_drv.c b/drivers/gpu/drm/amd/backport/kcl_drm_drv.c index d6b18e3a75f73..9783e852192a5 100644 --- a/drivers/gpu/drm/amd/backport/kcl_drm_drv.c +++ b/drivers/gpu/drm/amd/backport/kcl_drm_drv.c @@ -1,4 +1,30 @@ -/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Created: Fri Jan 19 10:48:35 2001 by faith@acm.org + * + * Copyright 2001 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Author Rickard E. (Rik) Faith + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ #include #include "amdgpu.h" diff --git a/drivers/gpu/drm/amd/backport/kcl_drm_gem_framebuffer_helper.c b/drivers/gpu/drm/amd/backport/kcl_drm_gem_framebuffer_helper.c new file mode 100644 index 0000000000000..1f68cf8bbe2b3 --- /dev/null +++ b/drivers/gpu/drm/amd/backport/kcl_drm_gem_framebuffer_helper.c @@ -0,0 +1,40 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * drm gem framebuffer helper functions + * + * Copyright (C) 2017 Noralf Trønnes + */ + +#include + +/* Copied from drivers/gpu/drm/drm_gem_framebuffer_helper.c and modified for KCL */ +#ifndef HAVE_DRM_DRM_GEM_FRAMEBUFFER_HELPER_H +struct drm_gem_object *drm_gem_fb_get_obj(struct drm_framebuffer *fb, + unsigned int plane) +{ + struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb); + (void)plane; /* for compile un-used warning */ + if (afb) + return afb->obj; + else + return NULL; +} + +void drm_gem_fb_destroy(struct drm_framebuffer *fb) +{ + struct amdgpu_framebuffer *amdgpu_fb = to_amdgpu_framebuffer(fb); + + drm_gem_object_put(amdgpu_fb->obj); + + drm_framebuffer_cleanup(fb); + kfree(fb); +} + +int drm_gem_fb_create_handle(struct drm_framebuffer *fb, struct drm_file *file, + unsigned int *handle) +{ + struct amdgpu_framebuffer *amdgpu_fb = to_amdgpu_framebuffer(fb); + + return drm_gem_handle_create(file, amdgpu_fb->obj, handle); +} +#endif diff --git a/include/kcl/backport/kcl_drm_atomic_helper_backport.h b/include/kcl/backport/kcl_drm_atomic_helper_backport.h index 1edfc203e12ce..eaa2464b77353 100644 --- a/include/kcl/backport/kcl_drm_atomic_helper_backport.h +++ b/include/kcl/backport/kcl_drm_atomic_helper_backport.h @@ -1,4 +1,30 @@ -/* SPDX-License-Identifier: MIT */ +/* + * Copyright (C) 2014 Red Hat + * Copyright (C) 2014 Intel Corp. + * Copyright (C) 2018 Intel Corp. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Rob Clark + * Daniel Vetter + */ #ifndef AMDKCL_DRM_ATOMIC_HELPER_BACKPORT_H #define AMDKCL_DRM_ATOMIC_HELPER_BACKPORT_H diff --git a/include/kcl/backport/kcl_drm_encoder.h b/include/kcl/backport/kcl_drm_encoder.h index 07e3a75541b80..0efc8f747defd 100644 --- a/include/kcl/backport/kcl_drm_encoder.h +++ b/include/kcl/backport/kcl_drm_encoder.h @@ -37,6 +37,7 @@ #include #include +/* Copied from drivers/gpu/drm/drm_edid.c and modified for KCL */ #if defined(HAVE_DRM_EDID_TO_ELD) static inline int _kcl_drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) diff --git a/include/kcl/backport/kcl_drm_vma_manager_backport.h b/include/kcl/backport/kcl_drm_vma_manager_backport.h index 0a7e1bf34bd82..9893688f6fac2 100644 --- a/include/kcl/backport/kcl_drm_vma_manager_backport.h +++ b/include/kcl/backport/kcl_drm_vma_manager_backport.h @@ -29,6 +29,7 @@ #include #include +/* Copied from include/drm/drm_vma_manager.h */ #if (BITS_PER_LONG == 64) #ifdef DRM_FILE_PAGE_OFFSET_START #undef DRM_FILE_PAGE_OFFSET_START diff --git a/include/kcl/backport/kcl_hmm.h b/include/kcl/backport/kcl_hmm.h index 233b0cbda947a..7dad7453aaa89 100644 --- a/include/kcl/backport/kcl_hmm.h +++ b/include/kcl/backport/kcl_hmm.h @@ -1,4 +1,11 @@ -/* SPDX-License-Identifier: MIT */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright 2013 Red Hat Inc. + * + * Authors: Jérôme Glisse + * + * See Documentation/vm/hmm.rst for reasons and overview of what HMM is. + */ #ifndef _KCL_BACKPORT_KCL_HMM_H #define _KCL_BACKPORT_KCL_HMM_H diff --git a/include/kcl/backport/kcl_pci_backport.h b/include/kcl/backport/kcl_pci_backport.h index 21799422a6abd..2cf66ef4aa69f 100644 --- a/include/kcl/backport/kcl_pci_backport.h +++ b/include/kcl/backport/kcl_pci_backport.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: MIT */ +/* SPDX-License-Identifier: GPL-2.0 */ #ifndef AMDKCL_PCI_BACKPORT_H #define AMDKCL_PCI_BACKPORT_H diff --git a/include/kcl/kcl_device.h b/include/kcl/kcl_device.h index 078622c69af21..a4d0dfbb334bc 100644 --- a/include/kcl/kcl_device.h +++ b/include/kcl/kcl_device.h @@ -1,10 +1,15 @@ /* SPDX-License-Identifier: GPL-2.0 */ +/* + * Definitions for the NVM Express interface + * Copyright (c) 2011-2014, Intel Corporation. + */ #ifndef AMDKCL_DEVICE_H #define AMDKCL_DEVICE_H #include #include +/* Copied from include/linux/dev_printk.h */ #if !defined(dev_err_once) #ifdef CONFIG_PRINTK #define dev_level_once(dev_level, dev, fmt, ...) \ @@ -51,7 +56,7 @@ do { \ #define DPM_FLAG_SMART_PREPARE BIT(1) static inline void dev_pm_set_driver_flags(struct device *dev, u32 flags) { - printk_once(KERN_WARNING "%s is not available\n", __func__); + pr_warn_once("%s is not available\n", __func__); } #endif diff --git a/include/kcl/kcl_dma_mapping.h b/include/kcl/kcl_dma_mapping.h index 24d18c3a7bf27..ba248dc82f298 100644 --- a/include/kcl/kcl_dma_mapping.h +++ b/include/kcl/kcl_dma_mapping.h @@ -131,6 +131,7 @@ static inline void dma_unmap_sgtable(struct device *dev, struct sg_table *sgt, /* * v5.8-rc3-2-g68d237056e00 ("scatterlist: protect parameters of the sg_table related macros") * v5.7-rc5-33-g709d6d73c756 ("scatterlist: add generic wrappers for iterating over sgtable objects") + * Copied from include/linux/scatterlist.h */ #ifndef for_each_sgtable_sg #define for_each_sgtable_sg(sgt, sg, i) \ diff --git a/include/kcl/kcl_drm_fb.h b/include/kcl/kcl_drm_fb.h index 3a0d30273cf7a..2b90f5bcd8682 100644 --- a/include/kcl/kcl_drm_fb.h +++ b/include/kcl/kcl_drm_fb.h @@ -35,6 +35,7 @@ #include #include +/* Copied from include/drm/drm_fb_helper.h */ /* * Don't add fb_debug_* since the legacy drm_fb_helper_debug_* has segfault * history: diff --git a/include/kcl/kcl_kernel.h b/include/kcl/kcl_kernel.h index ef5bdee50ee36..d055fad138c19 100644 --- a/include/kcl/kcl_kernel.h +++ b/include/kcl/kcl_kernel.h @@ -16,6 +16,7 @@ #endif #ifndef __GFP_RETRY_MAYFAIL +/* Copied from include/linux/gfp.h and modified for KCL */ #define __GFP_RETRY_MAYFAIL __GFP_NORETRY #endif diff --git a/include/kcl/kcl_kthread.h b/include/kcl/kcl_kthread.h index 90893fd2590b1..f9cca65e1ea6c 100644 --- a/include/kcl/kcl_kthread.h +++ b/include/kcl/kcl_kthread.h @@ -17,6 +17,7 @@ extern int (*_kcl_kthread_park)(struct task_struct *k); extern bool (*_kcl_kthread_should_park)(void); #endif +/* Copied from v5.7-13665-g9bf5b9eb232b kernel/kthread.c */ #ifndef HAVE_KTHREAD_USE_MM static inline void kthread_use_mm(struct mm_struct *mm) diff --git a/include/kcl/kcl_mm.h b/include/kcl/kcl_mm.h index 402a28df45f0e..be023c0b95edd 100644 --- a/include/kcl/kcl_mm.h +++ b/include/kcl/kcl_mm.h @@ -42,6 +42,7 @@ static inline void memalloc_nofs_restore(unsigned int flags) #endif #if !defined(HAVE_ZONE_MANAGED_PAGES) +/* Copied from v4.20-6505-g9705bea5f833 include/linux/mmzone.h and modified for KCL */ static inline unsigned long zone_managed_pages(struct zone *zone) { #if defined(HAVE_STRUCT_ZONE_MANAGED_PAGES) diff --git a/include/kcl/kcl_pci.h b/include/kcl/kcl_pci.h index b93c8b9e91ff0..f10e5e5c84106 100644 --- a/include/kcl/kcl_pci.h +++ b/include/kcl/kcl_pci.h @@ -129,6 +129,7 @@ int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask) } #endif +/* Copied from v3.12-rc2-29-gc6bde215acfd include/linux/pci.h */ #if !defined(HAVE_PCI_UPSTREAM_BRIDGE) static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev) { @@ -164,6 +165,7 @@ static inline void kcl_pci_configure_extended_tags(struct pci_dev *dev) #endif } +/* Copied from v5.1-rc1-5-g4e544bac8267 include/linux/pci.h */ #if !defined(HAVE_PCI_DEV_ID) static inline u16 pci_dev_id(struct pci_dev *dev) { diff --git a/include/kcl/kcl_preempt.h b/include/kcl/kcl_preempt.h index d76961463a6e3..1e59cbca1bf73 100644 --- a/include/kcl/kcl_preempt.h +++ b/include/kcl/kcl_preempt.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: MIT */ +/* SPDX-License-Identifier: GPL-2.0 */ #ifndef AMDKCL_PREEMPT_H #define AMDKCL_PREEMPT_H #include diff --git a/include/kcl/kcl_rcupdate.h b/include/kcl/kcl_rcupdate.h index ec31bae327ead..da63bf6d4f9e0 100644 --- a/include/kcl/kcl_rcupdate.h +++ b/include/kcl/kcl_rcupdate.h @@ -1,4 +1,21 @@ -/* SPDX-License-Identifier: MIT */ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Read-Copy Update mechanism for mutual exclusion + * + * Copyright IBM Corporation, 2001 + * + * Author: Dipankar Sarma + * + * Based on the original work by Paul McKenney + * and inputs from Rusty Russell, Andrea Arcangeli and Andi Kleen. + * Papers: + * http://www.rdrop.com/users/paulmck/paper/rclockpdcsproof.pdf + * http://lse.sourceforge.net/locking/rclock_OLS.2001.05.01c.sc.pdf (OLS2001) + * + * For detailed explanation of Read-Copy Update mechanism see - + * http://lse.sourceforge.net/locking/rcupdate.html + * + */ #ifndef AMDKCL_RCUPDATE_H #define AMDKCL_RCUPDATE_H diff --git a/include/kcl/kcl_task_barrier.h b/include/kcl/kcl_task_barrier.h index 341fe8e02a9d9..315bff4402dbc 100644 --- a/include/kcl/kcl_task_barrier.h +++ b/include/kcl/kcl_task_barrier.h @@ -1,10 +1,32 @@ -/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2019 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ #ifndef AMDKCL_DRM_TASK_BARRIER_H #define AMDKCL_DRM_TASK_BARRIER_H #ifdef HAVE_DRM_TASK_BARRIER_H #include #else +/* Copied from include/drm/task_barrier.h */ /* * Reusable 2 PHASE task barrier (randevouz point) implementation for N tasks. * Based on the Little book of sempahores - https://greenteapress.com/wp/semaphores/ diff --git a/include/kcl/kcl_version.h b/include/kcl/kcl_version.h index 4a470ef6dbbc7..59a859a26a540 100644 --- a/include/kcl/kcl_version.h +++ b/include/kcl/kcl_version.h @@ -1,4 +1,4 @@ -/* SPDX-License-Identifier: MIT */ +/* SPDX-License-Identifier: GPL-2.0 */ #ifndef AMDKCL_VERSION_H #define AMDKCL_VERSION_H From 2a20d910bb3cc6df78b61f8458327d51d733ef80 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 22 Mar 2021 14:32:02 +0800 Subject: [PATCH 0390/1868] drm/amdkcl: test whether pm_suspend_via_firmware is available This patch is caused by following commit 'drm/amdgpu: add a dev_pm_ops prepare callback (v2)' v5.11-2759-ga2839ac3fd80 Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../drm/amd/dkms/m4/pm-suspend-via-firmware.m4 | 17 +++++++++++++++++ include/kcl/kcl_suspend.h | 5 +++++ 4 files changed, 26 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/pm-suspend-via-firmware.m4 diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index deeb11aad8f2a..9be686177182d 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -795,6 +795,9 @@ /* pm_genpd_remove_device() wants 2 arguments */ /* #undef HAVE_PM_GENPD_REMOVE_DEVICE_2ARGS */ +/* pm_suspend_via_firmware() is available */ +#define HAVE_PM_SUSPEND_VIA_FIRMWARE 1 + /* remove_conflicting_framebuffers() returns int */ /* #undef HAVE_REMOVE_CONFLICTING_FRAMEBUFFERS_RETURNS_INT */ diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 9739c68a6f562..5b2fac65bb279 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -140,6 +140,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_GEM_TTM_VMAP AC_AMDGPU_FS_RECLAIM_ACQUIRE AC_AMDGPU_MEMALLOC_NORECLAIM_SAVE + AC_AMDGPU_PM_SUSPEND_VIA_FIRMWARE AC_AMDGPU_DRM_MEMCPY_FROM_WC AC_AMDGPU_IS_COW_MAPPING AC_AMDGPU_VGA_REMOVE_VGACON diff --git a/drivers/gpu/drm/amd/dkms/m4/pm-suspend-via-firmware.m4 b/drivers/gpu/drm/amd/dkms/m4/pm-suspend-via-firmware.m4 new file mode 100644 index 0000000000000..d5bcda40a4d71 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pm-suspend-via-firmware.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v4.3-rc5-6-gef25ba047601 +dnl # PM / sleep: Add flags to indicate platform firmware involvement +dnl # +AC_DEFUN([AC_AMDGPU_PM_SUSPEND_VIA_FIRMWARE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + pm_suspend_via_firmware(); + ],[ + AC_DEFINE(HAVE_PM_SUSPEND_VIA_FIRMWARE, + 1, + [pm_suspend_via_firmware() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_suspend.h b/include/kcl/kcl_suspend.h index 37a3cab923aa5..fb2c02994f763 100644 --- a/include/kcl/kcl_suspend.h +++ b/include/kcl/kcl_suspend.h @@ -14,4 +14,9 @@ static inline void ksys_sync_helper(void) static inline void ksys_sync_helper(void) {} #endif /* CONFIG_PM_SLEEP */ #endif /* HAVE_KSYS_SYNC_HELPER */ + +#ifndef HAVE_PM_SUSPEND_VIA_FIRMWARE +static inline bool pm_suspend_via_firmware(void) { return false; } +#endif /* HAVE_PM_SUSPEND_VIA_FIRMWARE */ + #endif /* AMDKCL_SUSPEND_H */ From 9408624af78c11da23d8ada31f88ef51abdb8d82 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 22 Mar 2021 14:47:46 +0800 Subject: [PATCH 0391/1868] drm/amdkcl: add DPM_FLAG_SMART_SUSPEND and DPM_FLAG_MAY_SKIP_RESUME macro This patch is caused by following commit 'drm/amdgpu: enable DPM_FLAG_MAY_SKIP_RESUME and DPM_FLAG_SMART_SUSPEND flags (v2)' v5.11-2760-g3d6ae23c0594 Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- include/kcl/kcl_pm.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/include/kcl/kcl_pm.h b/include/kcl/kcl_pm.h index 157fc65f14708..37c761718589e 100644 --- a/include/kcl/kcl_pm.h +++ b/include/kcl/kcl_pm.h @@ -7,6 +7,7 @@ #ifndef KCL_KCL_PM_H #define KCL_KCL_PM_H +#include #include /* @@ -17,4 +18,21 @@ #define DPM_FLAG_NO_DIRECT_COMPLETE DPM_FLAG_NEVER_SKIP #endif + +/* + * v4.15-rc1-1-g0d4b54c6fee8 + * PM / core: Add LEAVE_SUSPENDED driver flag + */ +#ifndef DPM_FLAG_SMART_SUSPEND +#define DPM_FLAG_SMART_SUSPEND BIT(2) +#endif + +/* + * v5.7-rc2-8-g2a3f34750b8b + * PM: sleep: core: Rename DPM_FLAG_LEAVE_SUSPENDED + */ +#ifndef DPM_FLAG_MAY_SKIP_RESUME +#define DPM_FLAG_MAY_SKIP_RESUME BIT(3) +#endif + #endif From 66fe300f92cbdd5290c411046bf8d3f70e22dc28 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 22 Mar 2021 15:28:30 +0800 Subject: [PATCH 0392/1868] drm/amdkcl: adapt code using list_for_each_entry for legacy os This patch is caused by following commit 'drm/amdgpu: clean up non-DC suspend/resume handling' v5.11-2764-ga7c22df2fd07 Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 902b562438e91..2d618c64f0ed3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1959,18 +1959,28 @@ int amdgpu_display_suspend_helper(struct amdgpu_device *adev) struct drm_device *dev = adev_to_drm(adev); struct drm_crtc *crtc; struct drm_connector *connector; + +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif int r; drm_kms_helper_poll_disable(dev); /* turn off display hw */ drm_modeset_lock_all(dev); +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) +#else + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) +#endif drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); + +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif drm_modeset_unlock_all(dev); /* unpin the front buffers and cursors */ list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { @@ -2007,7 +2017,9 @@ int amdgpu_display_resume_helper(struct amdgpu_device *adev) { struct drm_device *dev = adev_to_drm(adev); struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif struct drm_crtc *crtc; int r; @@ -2034,12 +2046,18 @@ int amdgpu_display_resume_helper(struct amdgpu_device *adev) /* turn on display hw */ drm_modeset_lock_all(dev); +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) +#else + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) +#endif drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif drm_modeset_unlock_all(dev); drm_kms_helper_poll_enable(dev); From fb504855b5659039f5712bc3d436b240f3a4d434 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 23 Mar 2021 15:41:51 +0800 Subject: [PATCH 0393/1868] drm/amdkcl: adapt code using drm_gem_fb_get_obj for legacy os This patch is caused by following commit 'drm/amdgpu: clean up non-DC suspend/resume handling' v5.11-2764-ga7c22df2fd07 Signed-off-by: Leslie Shi Reviewed-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 2d618c64f0ed3..d035c72750634 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1998,10 +1998,10 @@ int amdgpu_display_suspend_helper(struct amdgpu_device *adev) } } - if (!fb || !fb->obj[0]) + if (!fb || !drm_gem_fb_get_obj(fb, 0)) continue; - robj = gem_to_amdgpu_bo(fb->obj[0]); + robj = gem_to_amdgpu_bo(drm_gem_fb_get_obj(fb, 0)); if (!amdgpu_display_robj_is_fb(adev, robj)) { r = amdgpu_bo_reserve(robj, true); if (r == 0) { From e8b17fe22500011bbc6c233a0e8e43589cad75d7 Mon Sep 17 00:00:00 2001 From: Jonathan Kim Date: Tue, 8 Sep 2020 17:25:51 +0800 Subject: [PATCH 0394/1868] drm/amdkfd: add debug support for aldebaran The following commits have been squashed/touched up from npi and will go into dkms-staging: 'commit 156affb5f5d7 ("drm/amdkfd: update per-vmid registers for debug attach/detach")' 'commit 656b84994342 ("drm/amdgpu: fix lock scheme on aldebaran debug functions")' 'commit a376539fcd40 ("drm/amdkfd: add precise memory operations enable for aldebaran")' 'commit 32548be937a8 ("drm/amdgpu: unify debug setting fixes in aldebaran")' 'commit fc209adaf7ce ("drm/amdgpu: add new address watch functions to aldebaran")' The following has been omitted: References to anything emulation related Experimental host trap commands Signed-off-by: Jonathan Kim Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c index 8dfdb18197c49..ff1ac35561ff4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c @@ -26,6 +26,7 @@ #include "amdgpu_amdkfd_aldebaran.h" #include "gc/gc_9_4_2_offset.h" #include "gc/gc_9_4_2_sh_mask.h" +#include "soc15.h" #include /* From 39e36892a207baa5747162b3fc3277b4eb35ada2 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 31 Mar 2021 11:03:09 +0800 Subject: [PATCH 0395/1868] drm/amdkcl: fake the sysfs_emit This is caused by "Convert sysfs sprintf/snprintf family to sysfs_emit" v5.11-2844-g5f7dd9b5c2d3 Signed-off-by: Leslie Shi Reviewed by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/Makefile | 1 + drivers/gpu/drm/amd/amdkcl/kcl_sysfs_emit.c | 32 +++++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/sysfs_emit.m4 | 13 +++++++++ include/kcl/kcl_sysfs_emit.h | 25 ++++++++++++++++ 7 files changed, 76 insertions(+) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_sysfs_emit.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/sysfs_emit.m4 create mode 100644 include/kcl/kcl_sysfs_emit.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 4ea595282d7d1..a22c482f8b7b5 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -16,6 +16,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o amdkcl-$(CONFIG_DEBUG_FS) += kcl_debugfs_inode.o +amdkcl-$(CONFIG_SYSFS) += kcl_sysfs_emit.o CFLAGS_kcl_fence.o := -I$(src) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_sysfs_emit.c b/drivers/gpu/drm/amd/amdkcl/kcl_sysfs_emit.c new file mode 100644 index 0000000000000..798745cbfff91 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_sysfs_emit.c @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * fs/sysfs/file.c - sysfs regular (text) file implementation + * + * Copyright (c) 2001-3 Patrick Mochel + * Copyright (c) 2007 SUSE Linux Products GmbH + * Copyright (c) 2007 Tejun Heo + * + * Please see Documentation/filesystems/sysfs.rst for more information. + */ +#include +#include + +/* Copied from fs/sysfs/file.c */ +#ifndef HAVE_SYSFS_EMIT +int sysfs_emit(char *buf, const char *fmt, ...) +{ + va_list args; + int len; + + if (WARN(!buf || offset_in_page(buf), + "invalid sysfs_emit: buf:%p\n", buf)) + return 0; + + va_start(args, fmt); + len = vscnprintf(buf, PAGE_SIZE, fmt, args); + va_end(args); + + return len; +} +EXPORT_SYMBOL_GPL(sysfs_emit); +#endif diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 7c48927ff0bd7..2e0f765e1c88d 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -63,6 +63,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 9be686177182d..416b9a4042b0e 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -897,6 +897,9 @@ /* zone->managed_pages is available */ /* #undef HAVE_STRUCT_ZONE_MANAGED_PAGES */ +/* sysfs_emit() is available */ +#define HAVE_SYSFS_EMIT 1 + /* timer_setup() is available */ #define HAVE_TIMER_SETUP 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 5b2fac65bb279..8638a8af998ab 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -141,6 +141,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_FS_RECLAIM_ACQUIRE AC_AMDGPU_MEMALLOC_NORECLAIM_SAVE AC_AMDGPU_PM_SUSPEND_VIA_FIRMWARE + AC_AMDGPU_SYSFS_EMIT AC_AMDGPU_DRM_MEMCPY_FROM_WC AC_AMDGPU_IS_COW_MAPPING AC_AMDGPU_VGA_REMOVE_VGACON diff --git a/drivers/gpu/drm/amd/dkms/m4/sysfs_emit.m4 b/drivers/gpu/drm/amd/dkms/m4/sysfs_emit.m4 new file mode 100644 index 0000000000000..e9f403134af83 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/sysfs_emit.m4 @@ -0,0 +1,13 @@ +dnl # +dnl # commit: v5.9-rc5-23-g2efc459d06f1 +dnl # sysfs: Add sysfs_emit and sysfs_emit_at +dnl # to format sysfs output +AC_DEFUN([AC_AMDGPU_SYSFS_EMIT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([sysfs_emit], + [fs/sysfs/file.c], [ + AC_DEFINE(HAVE_SYSFS_EMIT, 1, + [sysfs_emit() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_sysfs_emit.h b/include/kcl/kcl_sysfs_emit.h new file mode 100644 index 0000000000000..ab87e74f817ff --- /dev/null +++ b/include/kcl/kcl_sysfs_emit.h @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * sysfs.h - definitions for the device driver filesystem + * + * Copyright (c) 2001,2002 Patrick Mochel + * Copyright (c) 2004 Silicon Graphics, Inc. + * Copyright (c) 2007 SUSE Linux Products GmbH + * Copyright (c) 2007 Tejun Heo + * + * Please see Documentation/filesystems/sysfs.rst for more information. + */ +#include + +#ifndef HAVE_SYSFS_EMIT +#ifdef CONFIG_SYSFS +__printf(2, 3) +int sysfs_emit(char *buf, const char *fmt, ...); +#else +__printf(2, 3) +static inline int sysfs_emit(char *buf, const char *fmt, ...) +{ + return 0; +} +#endif +#endif From 2b13224bff7d148d1d901502bd04095cd2111212 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 5 Aug 2021 10:40:27 +0800 Subject: [PATCH 0396/1868] drm/amdkcl: Test whether io_mapping_unmap_local() is available This is caused by 3bf3710e3718 "drm/ttm: Add a generic TTM memcpy move for page-based iomem" v5.13-rc3-860-g3bf3710e3718 Signed-off-by: Leslie Shi --- .../amd/dkms/m4/io-mapping-map-local-wc.m4 | 15 +++++++++++ .../drm/amd/dkms/m4/io-mapping-unmap-local.m4 | 15 +++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 ++ drivers/gpu/drm/ttm/backport/backport.h | 1 + include/kcl/kcl_io-mapping.h | 26 +++++++++++++++++++ 5 files changed, 59 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/io-mapping-map-local-wc.m4 create mode 100644 drivers/gpu/drm/amd/dkms/m4/io-mapping-unmap-local.m4 create mode 100644 include/kcl/kcl_io-mapping.h diff --git a/drivers/gpu/drm/amd/dkms/m4/io-mapping-map-local-wc.m4 b/drivers/gpu/drm/amd/dkms/m4/io-mapping-map-local-wc.m4 new file mode 100644 index 0000000000000..72ba661169b58 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/io-mapping-map-local-wc.m4 @@ -0,0 +1,15 @@ +dnl # +dnl # commit e66f6e095486f0210fcf3c5eb3ecf13fa348be4c +dnl # io-mapping: Provide iomap_local variant +dnl # +AC_DEFUN([AC_AMDGPU_IO_MAPPING_MAP_LOCAL_WC], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + io_mapping_map_local_wc(NULL, 0); + ], [ + AC_DEFINE(HAVE_IO_MAPPING_MAP_LOCAL_WC, 1, [io_mapping_map_local_wc() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/io-mapping-unmap-local.m4 b/drivers/gpu/drm/amd/dkms/m4/io-mapping-unmap-local.m4 new file mode 100644 index 0000000000000..282b77e11e1c5 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/io-mapping-unmap-local.m4 @@ -0,0 +1,15 @@ +dnl # +dnl # commit e66f6e095486f0210fcf3c5eb3ecf13fa348be4c +dnl # io-mapping: Provide iomap_local variant +dnl # +AC_DEFUN([AC_AMDGPU_IO_MAPPING_UNMAP_LOCAL], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + io_mapping_unmap_local(NULL); + ], [ + AC_DEFINE(HAVE_IO_MAPPING_UNMAP_LOCAL, 1, [io_mapping_unmap_local() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 8638a8af998ab..fd3ffebfae5f1 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -148,6 +148,8 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_APERTURE AC_AMDGPU_PCI_DRIVER_DEV_GROUPS AC_AMDGPU_DRM_DISPLAY_INFO + AC_AMDGPU_IO_MAPPING_UNMAP_LOCAL + AC_AMDGPU_IO_MAPPING_MAP_LOCAL_WC AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index f8fb0af23aa40..603819a994f54 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -16,5 +16,6 @@ #include #include #include +#include #endif diff --git a/include/kcl/kcl_io-mapping.h b/include/kcl/kcl_io-mapping.h new file mode 100644 index 0000000000000..6551e94cf3551 --- /dev/null +++ b/include/kcl/kcl_io-mapping.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright © 2008 Keith Packard + */ + +#ifndef KCL_KCL_IO_MAPPING_H +#define KCL_KCL_IO_MAPPING_H + +#include + +#ifndef HAVE_IO_MAPPING_UNMAP_LOCAL +static inline void io_mapping_unmap_local(void __iomem *vaddr) +{ + io_mapping_unmap(vaddr); +} +#endif + +#ifndef HAVE_IO_MAPPING_MAP_LOCAL_WC +static inline void __iomem * +io_mapping_map_local_wc(struct io_mapping *mapping, unsigned long offset) +{ + return io_mapping_map_wc(mapping, offset, PAGE_SIZE); +} +#endif + +#endif /* KCL_KCL_IO_MAPPING_H */ From fe2ef2a47d67b0b46774ba152ecf4bd0cd0a3b03 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 5 Aug 2021 14:01:12 +0800 Subject: [PATCH 0397/1868] drm/amdkcl: Test whether kmap_local_* is available This is caused by 3bf3710e3718 "drm/ttm: Add a generic TTM memcpy move for page-based iomem" v5.13-rc3-860-g3bf3710e3718 Signed-off-by: Leslie Shi --- .../gpu/drm/amd/dkms/m4/highmem-internal.m4 | 6 +-- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/ttm/backport/backport.h | 1 + include/kcl/kcl_highmem-internal.h | 41 +++++++++++++++++++ 4 files changed, 46 insertions(+), 3 deletions(-) create mode 100644 include/kcl/kcl_highmem-internal.h diff --git a/drivers/gpu/drm/amd/dkms/m4/highmem-internal.m4 b/drivers/gpu/drm/amd/dkms/m4/highmem-internal.m4 index b2614eabab932..326a3fc8e64c4 100644 --- a/drivers/gpu/drm/amd/dkms/m4/highmem-internal.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/highmem-internal.m4 @@ -4,12 +4,12 @@ dnl # mm/highmem: Provide kmap_local* dnl # AC_DEFUN([AC_AMDGPU_KMAP_LOCAL], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include + AC_KERNEL_TRY_COMPILE([ + #include ], [ pgprot_t prot; kmap_local_page_prot(NULL, prot); - ], [], [], [ + ], [ AC_DEFINE(HAVE_KMAP_LOCAL, 1, [kmap_local_* is available]) ]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index fd3ffebfae5f1..a00baf624dd92 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -150,6 +150,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DISPLAY_INFO AC_AMDGPU_IO_MAPPING_UNMAP_LOCAL AC_AMDGPU_IO_MAPPING_MAP_LOCAL_WC + AC_AMDGPU_KMAP_LOCAL AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index 603819a994f54..e6763a9dfb224 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -17,5 +17,6 @@ #include #include #include +#include #endif diff --git a/include/kcl/kcl_highmem-internal.h b/include/kcl/kcl_highmem-internal.h new file mode 100644 index 0000000000000..7304f188d7c2d --- /dev/null +++ b/include/kcl/kcl_highmem-internal.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef KCL_KCL_HIGHMEM_INTERNAL_H +#define KCL_KCL_HIGHMEM_INTERNAL_H + +#include +#include + +#ifndef HAVE_KMAP_LOCAL + +static inline void *kmap_local_page(struct page *page) +{ + return page_address(page); +} + +static inline void *kmap_local_page_prot(struct page *page, pgprot_t prot) +{ + return kmap_local_page(page); +} + +#endif + +#ifndef kunmap_local + +static inline void __kunmap_local(void *addr) +{ +#ifdef ARCH_HAS_FLUSH_ON_KUNMAP + kunmap_flush_on_unmap(addr); +#endif +} + +#define kunmap_local(__addr) \ +do { \ + BUILD_BUG_ON(__same_type((__addr), struct page *)); \ + __kunmap_local(__addr); \ +} while (0) +#endif /* kunmap_local */ + + + +#endif From 440fe77c443d9c8d4ffa6e2489658a38311bc644 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 5 Aug 2021 16:01:03 +0800 Subject: [PATCH 0398/1868] drm/amdkcl: fix build error of amdkcl_ttm_resvp Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index 998c0c0ff8f8b..41b27f6b802b8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -690,7 +690,7 @@ amdgpu_dma_buf_move_notify(struct dma_buf_attachment *attach) for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) { struct amdgpu_vm *vm = bo_base->vm; - struct dma_resv *resv = amdkcl_ttm_resvp(&vm->root.base.bo->tbo); + struct dma_resv *resv = amdkcl_ttm_resvp(&vm->root.bo->tbo); if (ticket) { /* When we get an error here it means that somebody diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index e38b83da24a4d..e2b45a7c1d9df 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -1181,7 +1181,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va, if (clear || !bo) { mem = NULL; - resv = amdkcl_ttm_resvp(&vm->root.base.bo->tbo); + resv = amdkcl_ttm_resvp(&vm->root.bo->tbo); } else { struct drm_gem_object *obj = &bo->tbo.base; @@ -1400,7 +1400,7 @@ static void amdgpu_vm_free_mapping(struct amdgpu_device *adev, */ static void amdgpu_vm_prt_fini(struct amdgpu_device *adev, struct amdgpu_vm *vm) { - struct dma_resv *resv = vm->root.bo->tbo.base.resv; + struct dma_resv *resv = amdkcl_ttm_resvp(&vm->root.bo->tbo); struct dma_resv_iter cursor; struct dma_fence *fence; @@ -1430,7 +1430,7 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev, struct amdgpu_vm *vm, struct dma_fence **fence) { - struct dma_resv *resv = amdkcl_ttm_resvp(&vm->root.base.bo->tbo); + struct dma_resv *resv = amdkcl_ttm_resvp(&vm->root.bo->tbo); struct amdgpu_bo_va_mapping *mapping; uint64_t init_pte_value = 0; struct dma_fence *f = NULL; From 97a2af8253bad8ca6e4be9f1441892b1c5c6821e Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Fri, 6 Aug 2021 10:25:47 +0800 Subject: [PATCH 0399/1868] drm/amdkcl: Test whether struct drm_dp_aux has member drm_dev This is caused by 6cba3fe43341 "drm/dp: Add backpointer to drm_device in drm_dp_aux" v5.12-rc7-1495-g6cba3fe43341 Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/atombios_dp.c | 3 +++ .../gpu/drm/amd/dkms/m4/drm-dp-aux-drm-dev.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 21 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dp-aux-drm-dev.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c index 622634c08c7b5..42f56fac03785 100644 --- a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c +++ b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c @@ -189,7 +189,10 @@ void amdgpu_atombios_dp_aux_init(struct amdgpu_connector *amdgpu_connector) { amdgpu_connector->ddc_bus->rec.hpd = amdgpu_connector->hpd.hpd; amdgpu_connector->ddc_bus->aux.transfer = amdgpu_atombios_dp_aux_transfer; + +#ifdef HAVE_DRM_DP_AUX_DRM_DEV amdgpu_connector->ddc_bus->aux.drm_dev = amdgpu_connector->base.dev; +#endif drm_dp_aux_init(&amdgpu_connector->ddc_bus->aux); amdgpu_connector->ddc_bus->has_aux = true; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-aux-drm-dev.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-aux-drm-dev.m4 new file mode 100644 index 0000000000000..d851ad71eab97 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-aux-drm-dev.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v5.12-rc7-1495-g6cba3fe43341 +dnl # drm/dp: Add backpointer to drm_device in drm_dp_aux +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_AUX_DRM_DEV], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + struct drm_dp_aux dda; + dda.drm_dev = NULL; + ], [],[],[ + AC_DEFINE(HAVE_DRM_DP_AUX_DRM_DEV, 1, + [struct drm_dp_aux has member named 'drm_dev']) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index a00baf624dd92..7c1d36508c4e8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -151,6 +151,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_IO_MAPPING_UNMAP_LOCAL AC_AMDGPU_IO_MAPPING_MAP_LOCAL_WC AC_AMDGPU_KMAP_LOCAL + AC_AMDGPU_DRM_DP_AUX_DRM_DEV AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From c765620b59ff2829a9d7370ff4aa2949a8add685 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Fri, 6 Aug 2021 10:39:04 +0800 Subject: [PATCH 0400/1868] drm/amdkcl: Test whether drm_dp_link_train_clock_recovery_delay() has 2 args This is caused by 9e9866664456 "drm/dp: Pass drm_dp_aux to drm_dp_link_train_clock_recovery_delay()" v5.12-rc7-1497-g9e9866664456 Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/atombios_dp.c | 4 ++++ .../drm-dp-link-train-clock-recovery-delay.m4 | 18 ++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 23 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c index 42f56fac03785..37cf0bbc71ac3 100644 --- a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c +++ b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c @@ -616,7 +616,11 @@ amdgpu_atombios_dp_link_train_cr(struct amdgpu_atombios_dp_link_train_info *dp_i dp_info->tries = 0; voltage = 0xff; while (1) { +#ifdef HAVE_DRM_DP_LINK_TRAIN_CLOCK_RECOVERY_DELAY_2ARGS drm_dp_link_train_clock_recovery_delay(dp_info->aux, dp_info->dpcd); +#else + drm_dp_link_train_clock_recovery_delay(dp_info->dpcd); +#endif if (drm_dp_dpcd_read_link_status(dp_info->aux, dp_info->link_status) <= 0) { diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 new file mode 100644 index 0000000000000..4d8e0f733eb7e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit v5.12-rc7-1497-g9e9866664456 +dnl # drm/dp: Pass drm_dp_aux to drm_dp_link_train_clock_recovery_delay() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_LINK_TRAIN_CLOCK_RECOVERY_DELAY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + struct drm_dp_aux *aux = NULL; + const u8 dpcd[DP_RECEIVER_CAP_SIZE]; + drm_dp_link_train_clock_recovery_delay(aux, dpcd); + ], [drm_dp_link_train_clock_recovery_delay],[drm/drm_dp_helper.c],[ + AC_DEFINE(HAVE_DRM_DP_LINK_TRAIN_CLOCK_RECOVERY_DELAY_2ARGS, 1, + [drm_dp_link_train_clock_recovery_delay() has 2 args]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 7c1d36508c4e8..4092bde235770 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -152,6 +152,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_IO_MAPPING_MAP_LOCAL_WC AC_AMDGPU_KMAP_LOCAL AC_AMDGPU_DRM_DP_AUX_DRM_DEV + AC_AMDGPU_DRM_DP_LINK_TRAIN_CLOCK_RECOVERY_DELAY AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From d221a966bd95920f3739bee12dffcac9a6a8d4d6 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Fri, 6 Aug 2021 13:27:27 +0800 Subject: [PATCH 0401/1868] drm/amdkcl: Test whether drm_dp_link_train_channel_eq_delay() has 2 args This is caused by 0c4fada608c1 "drm/dp: Pass drm_dp_aux to drm_dp*_link_train_channel_eq_delay()" v5.12-rc7-1498-g0c4fada608c1 Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/atombios_dp.c | 4 ++++ .../m4/drm-dp-link-train-channel-eq-delay.m4 | 18 ++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 23 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c index 37cf0bbc71ac3..abb18df7b0797 100644 --- a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c +++ b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c @@ -685,7 +685,11 @@ amdgpu_atombios_dp_link_train_ce(struct amdgpu_atombios_dp_link_train_info *dp_i dp_info->tries = 0; channel_eq = false; while (1) { +#ifdef HAVE_DRM_DP_LINK_TRAIN_CHANNEL_EQ_DELAY_2ARGS drm_dp_link_train_channel_eq_delay(dp_info->aux, dp_info->dpcd); +#else + drm_dp_link_train_channel_eq_delay(dp_info->dpcd); +#endif if (drm_dp_dpcd_read_link_status(dp_info->aux, dp_info->link_status) <= 0) { diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 new file mode 100644 index 0000000000000..664b63498814e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit v5.12-rc7-1498-g0c4fada608c1 +dnl # drm/dp: Pass drm_dp_aux to drm_dp*_link_train_channel_eq_delay() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_LINK_TRAIN_CHANNEL_EQ_DELAY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + struct drm_dp_aux *aux = NULL; + const u8 dpcd[DP_RECEIVER_CAP_SIZE]; + drm_dp_link_train_channel_eq_delay(aux, dpcd); + ], [drm_dp_link_train_channel_eq_delay],[drm/drm_dp_helper.c],[ + AC_DEFINE(HAVE_DRM_DP_LINK_TRAIN_CHANNEL_EQ_DELAY_2ARGS, 1, + [drm_dp_link_train_channel_eq_delay() has 2 args]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 4092bde235770..30cadfee467b1 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -153,6 +153,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_KMAP_LOCAL AC_AMDGPU_DRM_DP_AUX_DRM_DEV AC_AMDGPU_DRM_DP_LINK_TRAIN_CLOCK_RECOVERY_DELAY + AC_AMDGPU_DRM_DP_LINK_TRAIN_CHANNEL_EQ_DELAY AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 7b43645c9f85ca584f6f9785172348f46af8671d Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 31 Mar 2021 15:17:23 +0800 Subject: [PATCH 0402/1868] drm/amdkcl: access drm_plane index field using drm_plane_index This is caused by "drm/amd/display: Use appropriate DRM_DEBUG_... level" v5.11-2836-g27f1f74cc17e Signed-off-by: Leslie Shi Reviewed by: Flora Cui --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 4ac3517b21b68..02b513a40717d 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -9061,7 +9061,7 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, afb->tmz_surface, false); drm_dbg_state(state->dev, "plane: id=%d dcc_en=%d\n", - new_plane_state->plane->index, + drm_plane_index(new_plane_state->plane), bundle->plane_infos[planes_count].dcc.enable); bundle->surface_updates[planes_count].plane_info = From 59a8be4ecffb2534e77334c93ee6d7a097b2f201 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 1 Apr 2021 16:59:38 +0800 Subject: [PATCH 0403/1868] drm/amdkcl: wrap the code under HAVE_KTIME_IS_UNION This is caused by "drm/amd/display: Add refresh rate trace" v5.11-2869-g3b8fa2a4ed4c Signed-off-by: Leslie Shi --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++++ .../drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h | 2 ++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/ktime-is-union.m4 | 17 +++++++++++++++++ 5 files changed, 27 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/ktime-is-union.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 02b513a40717d..1f31388c105c1 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -537,9 +537,11 @@ static void dm_vupdate_high_irq(void *interrupt_params) struct common_irq_params *irq_params = interrupt_params; struct amdgpu_device *adev = irq_params->adev; struct amdgpu_crtc *acrtc; +#ifndef HAVE_KTIME_IS_UNION struct drm_device *drm_dev; struct drm_vblank_crtc *vblank; ktime_t frame_duration_ns, previous_timestamp; +#endif unsigned long flags; int vrr_active; @@ -547,6 +549,7 @@ static void dm_vupdate_high_irq(void *interrupt_params) if (acrtc) { vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc); +#ifndef HAVE_KTIME_IS_UNION drm_dev = acrtc->base.dev; vblank = drm_crtc_vblank_crtc(&acrtc->base); previous_timestamp = atomic64_read(&irq_params->previous_timestamp); @@ -558,6 +561,7 @@ static void dm_vupdate_high_irq(void *interrupt_params) ktime_divns(NSEC_PER_SEC, frame_duration_ns)); atomic64_set(&irq_params->previous_timestamp, vblank->time); } +#endif drm_dbg_vbl(drm_dev, "crtc:%d, vupdate-vrr:%d\n", acrtc->crtc_id, diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h index 71ddae18f9b9d..e487f8c68f97a 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h @@ -684,6 +684,7 @@ TRACE_EVENT(amdgpu_dmub_trace_high_irq, __entry->param0, __entry->param1) ); +#ifndef HAVE_KTIME_IS_UNION TRACE_EVENT(amdgpu_refresh_rate_track, TP_PROTO(int crtc_index, ktime_t refresh_rate_ns, uint32_t refresh_rate_hz), TP_ARGS(crtc_index, refresh_rate_ns, refresh_rate_hz), @@ -702,6 +703,7 @@ TRACE_EVENT(amdgpu_refresh_rate_track, __entry->refresh_rate_hz, __entry->refresh_rate_ns) ); +#endif TRACE_EVENT(dcn_fpu, TP_PROTO(bool begin, const char *function, const int line, const int recursion_depth), diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 416b9a4042b0e..c4c39ba20b734 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -654,6 +654,9 @@ /* ktime_get_real_seconds() is available */ #define HAVE_KTIME_GET_REAL_SECONDS 1 +/* ktime_t is union */ +/* #undef HAVE_KTIME_IS_UNION */ + /* kvcalloc() is available */ #define HAVE_KVCALLOC 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 30cadfee467b1..fe8c833ebfa0b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -142,6 +142,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_MEMALLOC_NORECLAIM_SAVE AC_AMDGPU_PM_SUSPEND_VIA_FIRMWARE AC_AMDGPU_SYSFS_EMIT + AC_AMDGPU_KTIME_IS_UNION AC_AMDGPU_DRM_MEMCPY_FROM_WC AC_AMDGPU_IS_COW_MAPPING AC_AMDGPU_VGA_REMOVE_VGACON diff --git a/drivers/gpu/drm/amd/dkms/m4/ktime-is-union.m4 b/drivers/gpu/drm/amd/dkms/m4/ktime-is-union.m4 new file mode 100644 index 0000000000000..0bd3f631e535f --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/ktime-is-union.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v4.18-rc1-35-ga8802d97e733 +dnl # ktime: Get rid of the union +dnl # +AC_DEFUN([AC_AMDGPU_KTIME_IS_UNION], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + ktime_t t; + t.tv64 = 0; + ], [ + AC_DEFINE(HAVE_KTIME_IS_UNION, 1, + [ktime_t is union]) + ]) + ]) +]) From 011c4947fed39ed79754884f5d78442bc6a3dbb8 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 6 Apr 2021 16:26:22 +0800 Subject: [PATCH 0404/1868] drm/amdkcl: access resv field using amdkcl_ttm_resvp This is caused by "drm/amdgpu: reserve fence slot to update page table" v5.11-2904-gf63da9ae7584 Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index e2b45a7c1d9df..25ab594b1a004 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -2862,7 +2862,7 @@ bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid, value = 0; } - r = dma_resv_reserve_fences(root->tbo.base.resv, 1); + r = dma_resv_reserve_fences(amdkcl_ttm_resvp(&root->tbo), 1); if (r) { pr_debug("failed %d to reserve fence slot\n", r); goto error_unlock; From 49912b45e363025f842a25fff9137de0aefebffd Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 7 Apr 2021 14:56:34 +0800 Subject: [PATCH 0405/1868] drm/amdkcl: wrap the code under DEFINE_DEBUGFS_ATTRIBUTE This is caused by "drm/amd/display: Add MST capability to trigger_hotplug interface" v5.11-2937-gd39b43894f55 Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index 7e3b648098d9f..58be9d5d98413 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -3797,6 +3797,7 @@ static int mst_topo_show(struct seq_file *m, void *unused) return 0; } +#ifdef DEFINE_DEBUGFS_ATTRIBUTE /* * Sets trigger hpd for MST topologies. * All connected connectors will be rediscovered and re started as needed if val of 1 is sent. @@ -3870,7 +3871,7 @@ static int trigger_hpd_mst_get(void *data, u64 *val) DEFINE_DEBUGFS_ATTRIBUTE(trigger_hpd_mst_ops, trigger_hpd_mst_get, trigger_hpd_mst_set, "%llu\n"); - +#endif /* * Sets the force_timing_sync debug option from the given string. From 975f77f348924afa04423bb2dffbd9bbf08178c3 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 7 Apr 2021 16:15:49 +0800 Subject: [PATCH 0406/1868] drm/amdkcl: wrap the code under DEFINE_DEBUGFS_ATTRIBUTE This is caused by "drm/amd/display: Add debugfs entry for LTTPR register status" v5.11-2928-g4721d0678f7c Signed-off-by: Leslie Shi Reviewed-by: Flora Cui Change-Id: I84809cf9dabb0b697c76bb8bd24e9e043e532b65 --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index 58be9d5d98413..686016d642602 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -568,6 +568,7 @@ static ssize_t dp_phy_settings_read(struct file *f, char __user *buf, return result; } +#ifdef DEFINE_DEBUGFS_ATTRIBUTE static int dp_lttpr_status_show(struct seq_file *m, void *unused) { struct drm_connector *connector = m->private; @@ -602,6 +603,7 @@ static int dp_lttpr_status_show(struct seq_file *m, void *unused) seq_puts(m, "\n"); return 0; } +#endif static ssize_t dp_phy_settings_write(struct file *f, const char __user *buf, size_t size, loff_t *pos) @@ -2860,7 +2862,9 @@ static int is_dpia_link_show(struct seq_file *m, void *data) DEFINE_SHOW_ATTRIBUTE(dp_dsc_fec_support); DEFINE_SHOW_ATTRIBUTE(dmub_fw_state); DEFINE_SHOW_ATTRIBUTE(dmub_tracebuffer); +#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_SHOW_ATTRIBUTE(dp_lttpr_status); +#endif DEFINE_SHOW_ATTRIBUTE(hdcp_sink_capability); DEFINE_SHOW_ATTRIBUTE(internal_display); DEFINE_SHOW_ATTRIBUTE(odm_combine_segments); @@ -2979,7 +2983,9 @@ static const struct { } dp_debugfs_entries[] = { {"link_settings", &dp_link_settings_debugfs_fops}, {"phy_settings", &dp_phy_settings_debugfs_fop}, +#ifdef DEFINE_DEBUGFS_ATTRIBUTE {"lttpr_status", &dp_lttpr_status_fops}, +#endif {"test_pattern", &dp_phy_test_pattern_fops}, {"hdcp_sink_capability", &hdcp_sink_capability_fops}, {"sdp_message", &sdp_message_fops}, From 96e4b4edfc0289ef66e3139b7c21b740bf98481a Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Fri, 9 Apr 2021 11:01:14 +0800 Subject: [PATCH 0407/1868] drm/amdkcl: fix pytorch test memory page fault Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 25ab594b1a004..20ff637055e85 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -1178,6 +1178,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va, uint64_t vram_base; uint64_t flags; int r; + struct amdgpu_device *bo_adev; if (clear || !bo) { mem = NULL; @@ -1204,8 +1205,6 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va, } if (bo) { - struct amdgpu_device *bo_adev; - flags = amdgpu_ttm_tt_pte_flags(adev, bo->tbo.ttm, mem); if (amdgpu_bo_encrypted(bo)) @@ -1247,6 +1246,18 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va, /* Apply ASIC specific mapping flags */ amdgpu_gmc_get_vm_pte(adev, mapping, &update_flags); + if (adev != bo_adev && + !(update_flags & AMDGPU_PTE_SYSTEM) && + !mapping->bo_va->is_xgmi) { + if (amdgpu_device_is_peer_accessible(bo_adev, adev)) { + update_flags |= AMDGPU_PTE_SYSTEM; + vram_base = bo_adev->gmc.aper_base; + } else { + DRM_DEBUG_DRIVER("Failed to map the VRAM for peer device access.\n"); + return -EINVAL; + } + } + trace_amdgpu_vm_bo_update(mapping); r = amdgpu_vm_update_range(adev, vm, false, false, flush_tlb, From d9cfdc0011c229f4d35b1f5f5b2f4bdeee812e58 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 13 Apr 2021 13:10:01 +0800 Subject: [PATCH 0408/1868] drm/amdkcl: wrap the code under DEFINE_DEBUGFS_ATTRIBUTE This is caused by "drm/amd/display: Add debugfs to repress HPD and HPR_RX IRQs" v5.11-2975-g14bc8d04dd21 Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index 686016d642602..b925151f8fc0d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -3914,6 +3914,7 @@ DEFINE_DEBUGFS_ATTRIBUTE(force_timing_sync_ops, force_timing_sync_get, #endif +#ifdef DEFINE_DEBUGFS_ATTRIBUTE /* * Disables all HPD and HPD RX interrupt handling in the * driver when set to 1. Default is 0. @@ -3943,6 +3944,7 @@ static int disable_hpd_get(void *data, u64 *val) DEFINE_DEBUGFS_ATTRIBUTE(disable_hpd_ops, disable_hpd_get, disable_hpd_set, "%llu\n"); +#endif /* * Prints hardware capabilities. These are used for IGT testing. From 770bc73764519fa6c7e7ab17f2aa4940ad614ee1 Mon Sep 17 00:00:00 2001 From: Feifei Xu Date: Thu, 15 Apr 2021 14:03:09 +0800 Subject: [PATCH 0409/1868] drm/amdgpu: use ratelimited print in sdma4 interrupt dev_*_ratelimited printing will avoid dmesg flush. Signed-off-by: Feifei Xu Acked-by: Kent Russell --- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index 2de5ebb7e00a7..b2ea1ae5b737b 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c @@ -2171,7 +2171,7 @@ static int sdma_v4_0_print_iv_entry(struct amdgpu_device *adev, instance = sdma_v4_0_irq_id_to_seq(entry->client_id); if (instance < 0 || instance >= adev->sdma.num_instances) { - dev_err(adev->dev, "sdma instance invalid %d\n", instance); + dev_err_ratelimited(adev->dev, "sdma instance invalid %d\n", instance); return -EINVAL; } From e7f01746209a2c1670915bf8b1b3a5abd95886bc Mon Sep 17 00:00:00 2001 From: Chengming Gui Date: Tue, 20 Apr 2021 15:53:54 +0800 Subject: [PATCH 0410/1868] drm/amd/amdgpu: Add missing bo size setting for bo_create MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add missing bp.bo_ptr_size setting in amdgpu_gem_prime_import_sg_table Signed-off-by: Chengming Gui Reviewed-by: Christian König Reviewed-by: Guchun Chen Change-Id: Ibe8ed71e797c12587684b2604c76e513adf98803 --- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index 41b27f6b802b8..790ce0671b43d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -548,6 +548,7 @@ amdgpu_gem_prime_import_sg_table(struct drm_device *dev, bp.flags = 0; bp.type = ttm_bo_type_sg; bp.resv = resv; + bp.bo_ptr_size = sizeof(struct amdgpu_bo); dma_resv_lock(resv, NULL); ret = amdgpu_bo_create(adev, &bp, &bo); if (ret) From ac53209ead05adb90a63cf2fa87d00e0a5d3b320 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Fri, 16 Apr 2021 15:53:12 +0800 Subject: [PATCH 0411/1868] drm/amdkcl: replace vm parameter with drm_priv This is caused by "drm/amdkfd: Use drm_priv to pass VM from KFD to amdgpu" v5.11-3019-g9be47f808bf7 Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkfd/kfd_ipc.c | 4 ++-- drivers/gpu/drm/amd/amdkfd/kfd_spm.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c index d52e0f38eef1c..88ab20909ce39 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c @@ -135,7 +135,7 @@ static int kfd_import_dmabuf_create_kfd_bo(struct kfd_dev *dev, } r = amdgpu_amdkfd_gpuvm_import_dmabuf(dev->kgd, dmabuf, ipc_obj, - va_addr, pdd->vm, + va_addr, pdd->drm_priv, (struct kgd_mem **)&mem, &size, mmap_offset); if (r) @@ -248,7 +248,7 @@ int kfd_ipc_export_as_handle(struct kfd_dev *dev, struct kfd_process *p, } mem = (struct kgd_mem *)kfd_bo->mem; - r = amdgpu_amdkfd_gpuvm_export_ipc_obj(dev->kgd, pdd->vm, mem, + r = amdgpu_amdkfd_gpuvm_export_ipc_obj(dev->kgd, pdd->drm_priv, mem, &ipc_obj); if (r) return r; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c index d9856191ab7eb..ceabdb3680a64 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c @@ -208,7 +208,7 @@ static int kfd_acquire_spm(struct kfd_process_device *pdd, struct kgd_dev *kgd) if (ret) goto alloc_gtt_mem_failure; - ret = amdgpu_amdkfd_rlc_spm_acquire(kgd, pdd->vm, + ret = amdgpu_amdkfd_rlc_spm_acquire(kgd, pdd->drm_priv, pdd->spm_cntr->gpu_addr, pdd->spm_cntr->ring_size); /* @@ -259,7 +259,7 @@ static int kfd_release_spm(struct kfd_process_device *pdd, struct kgd_dev *kgd) flush_work(&pdd->spm_work); wake_up_all(&pdd->spm_cntr->spm_buf_wq); - amdgpu_amdkfd_rlc_spm_release(kgd, pdd->vm); + amdgpu_amdkfd_rlc_spm_release(kgd, pdd->drm_priv); amdgpu_amdkfd_free_gtt_mem(kgd, pdd->spm_cntr->spm_obj); spin_lock_irqsave(&pdd->spm_irq_lock, flags); From 77f60c6f198e2a6f14aaec950cea62f947275359 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 24 Feb 2020 21:17:30 -0500 Subject: [PATCH 0412/1868] drm/amdkcl: move kcl part for hmm into amdgpu_mn Signed-off-by: Flora Cui Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c | 49 +++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c index 6621f0447d559..62856f6e3d949 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c @@ -818,6 +818,21 @@ void amdgpu_hmm_unregister(struct amdgpu_bo *bo) bo->notifier.mm = NULL; } +#ifndef HAVE_HMM_DROP_CUSTOMIZABLE_PFN_FORMAT +/* flags used by HMM internal, not related to CPU/GPU PTE flags */ +static const uint64_t hmm_range_flags[HMM_PFN_FLAG_MAX] = { + (1 << 0), /* HMM_PFN_VALID */ + (1 << 1), /* HMM_PFN_WRITE */ + 0 /* HMM_PFN_DEVICE_PRIVATE */ +}; + +static const uint64_t hmm_range_values[HMM_PFN_VALUE_MAX] = { + 0xfffffffffffffffeUL, /* HMM_PFN_ERROR */ + 0, /* HMM_PFN_NONE */ + 0xfffffffffffffffcUL /* HMM_PFN_SPECIAL */ +}; +#endif + int amdgpu_hmm_range_get_pages(struct mmu_interval_notifier *notifier, uint64_t start, uint64_t npages, bool readonly, void *owner, struct page **pages, @@ -841,10 +856,20 @@ int amdgpu_hmm_range_get_pages(struct mmu_interval_notifier *notifier, } hmm_range->notifier = notifier; +#ifndef HAVE_HMM_DROP_CUSTOMIZABLE_PFN_FORMAT + hmm_range->flags = hmm_range_flags; + hmm_range->values = hmm_range_values; + hmm_range->pfn_shift = PAGE_SHIFT; + hmm_range->default_flags = hmm_range_flags[HMM_PFN_VALID]; + if (!readonly) + hmm_range->default_flags |= hmm_range->flags[HMM_PFN_WRITE]; + hmm_range->pfns = (uint64_t *)pfns; +#else hmm_range->default_flags = HMM_PFN_REQ_FAULT; if (!readonly) hmm_range->default_flags |= HMM_PFN_REQ_WRITE; hmm_range->hmm_pfns = pfns; +#endif hmm_range->start = start; end = start + npages * PAGE_SIZE; hmm_range->dev_private_owner = owner; @@ -860,8 +885,16 @@ int amdgpu_hmm_range_get_pages(struct mmu_interval_notifier *notifier, retry: hmm_range->notifier_seq = mmu_interval_read_begin(notifier); r = hmm_range_fault(hmm_range); +#ifndef HAVE_HMM_DROP_CUSTOMIZABLE_PFN_FORMAT + if (unlikely(r <= 0)) { +#else if (unlikely(r)) { +#endif +#ifndef HAVE_HMM_DROP_CUSTOMIZABLE_PFN_FORMAT + if ((r == 0 || r == -EBUSY) && !time_after(jiffies, timeout)) +#else if (r == -EBUSY && !time_after(jiffies, timeout)) +#endif goto retry; goto out_free_pfns; } @@ -881,7 +914,19 @@ int amdgpu_hmm_range_get_pages(struct mmu_interval_notifier *notifier, * the notifier_lock, and mmu_interval_read_retry() must be done first. */ for (i = 0; pages && i < npages; i++) +#ifndef HAVE_HMM_DROP_CUSTOMIZABLE_PFN_FORMAT + pages[i] = hmm_device_entry_to_page(hmm_range, hmm_range->pfns[i]); + if (unlikely(!pages[i])) { + pr_err("Page fault failed for pfn[%lu] = 0x%llx\n", + i, hmm_range->pfns[i]); + r = -ENOMEM; + + goto out_free_pfns; + } + +#else pages[i] = hmm_pfn_to_page(pfns[i]); +#endif *phmm_range = hmm_range; @@ -903,7 +948,11 @@ bool amdgpu_hmm_range_get_pages_done(struct hmm_range *hmm_range) r = mmu_interval_read_retry(hmm_range->notifier, hmm_range->notifier_seq); +#ifndef HAVE_HMM_DROP_CUSTOMIZABLE_PFN_FORMAT + kvfree(hmm_range->pfns); +#else kvfree(hmm_range->hmm_pfns); +#endif kfree(hmm_range); return r; From 9ccdde849438bde28559a05fae769bbb02c00856 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 6 Apr 2021 11:42:37 +0800 Subject: [PATCH 0413/1868] drm/amdkcl: adapt to dev_pagemap->range update Signed-off-by: Flora Cui Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 27 ++++++++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c index 8ee3d07ffbdfa..8a9701d43f923 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@ -206,7 +206,11 @@ svm_migrate_copy_done(struct amdgpu_device *adev, struct dma_fence *mfence) unsigned long svm_migrate_addr_to_pfn(struct amdgpu_device *adev, unsigned long addr) { +#ifdef HAVE_DEV_PAGEMAP_RANGE return (addr + adev->kfd.pgmap.range.start) >> PAGE_SHIFT; +#else + return (addr + adev->kfd.dev->pgmap.res.start) >> PAGE_SHIFT; +#endif } static void @@ -236,7 +240,12 @@ svm_migrate_addr(struct amdgpu_device *adev, struct page *page) unsigned long addr; addr = page_to_pfn(page) << PAGE_SHIFT; +#ifdef HAVE_DEV_PAGEMAP_RANGE return (addr - adev->kfd.pgmap.range.start); +#else + return (addr - adev->kfd.dev->pgmap.res.start); +#endif + } static struct page * @@ -1033,20 +1042,34 @@ int kgd2kfd_init_zone_device(struct amdgpu_device *adev) * should remove reserved size */ size = ALIGN(adev->gmc.real_vram_size, 2ULL << 20); +#ifdef HAVE_DEVICE_COHERENT if (adev->gmc.xgmi.connected_to_cpu) { +#ifdef HAVE_DEV_PAGEMAP_RANGE + pgmap->nr_range = 1; pgmap->range.start = adev->gmc.aper_base; pgmap->range.end = adev->gmc.aper_base + adev->gmc.aper_size - 1; +#else + pgmap->res.start = adev->gmc.aper_base; + pgmap->res.end = adev->gmc.aper_base + adev->gmc.aper_size - 1; +#endif pgmap->type = MEMORY_DEVICE_COHERENT; - } else { + } else +#endif + { res = devm_request_free_mem_region(adev->dev, &iomem_resource, size); if (IS_ERR(res)) return PTR_ERR(res); +#ifdef HAVE_DEV_PAGEMAP_RANGE + pgmap->nr_range = 1; pgmap->range.start = res->start; pgmap->range.end = res->end; +#else + pgmap->res.start = res->start; + pgmap->res.end = res->end; +#endif pgmap->type = MEMORY_DEVICE_PRIVATE; } - pgmap->nr_range = 1; pgmap->ops = &svm_migrate_pgmap_ops; pgmap->owner = SVM_ADEV_PGMAP_OWNER(adev); pgmap->flags = 0; From 6707214f5657e04065639334bb6b33d847fb97c3 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 6 Apr 2021 11:46:35 +0800 Subject: [PATCH 0414/1868] drm/amdkcl: enable HSA_AMD_SVM in dkms package Signed-off-by: Flora Cui Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Makefile | 5 +++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/svm.m4 | 21 +++++++++++++++++++++ 4 files changed, 30 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/svm.m4 diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index cfe73b92bcad9..4fc3b8e5ba5a4 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -158,6 +158,11 @@ subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_USERPTR subdir-ccflags-y += -DCONFIG_DRM_AMD_DC subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN1_0 +ifeq ($(call _is_kcl_macro_defined,HAVE_HSA_AMD_SVM_ENABLED),y) +export CONFIG_HSA_AMD_SVM=y +subdir-ccflags-y += -DCONFIG_HSA_AMD_SVM +endif + export CONFIG_DRM_AMD_DC_HDCP=y subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_HDCP diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index c4c39ba20b734..703e254dacb0e 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -609,6 +609,9 @@ /* hmm_range_fault() wants 1 arg */ #define HAVE_HMM_RANGE_FAULT_1ARG 1 +/* dev_pagemap->owner is available */ +#define HAVE_HSA_AMD_SVM_ENABLED 1 + /* struct i2c_lock_operations is defined */ #define HAVE_I2C_LOCK_OPERATIONS_STRUCT 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index fe8c833ebfa0b..13b92df1691cc 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -67,6 +67,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_AMD_IOMMU_PC_SUPPORTED AC_AMDGPU_AMD_IOMMU_INVALIDATE_CTX AC_AMDGPU_DEV_PAGEMAP + AC_AMDGPU_HSA_AMD_SVM AC_AMDGPU_DOWN_READ_KILLABLE AC_AMDGPU_DRM_CACHE AC_AMDGPU_DRM_DEBUG_ENABLED diff --git a/drivers/gpu/drm/amd/dkms/m4/svm.m4 b/drivers/gpu/drm/amd/dkms/m4/svm.m4 new file mode 100644 index 0000000000000..ef2c930e21391 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/svm.m4 @@ -0,0 +1,21 @@ +dnl # +dnl # v5.6-rc3-15-g800bb1c8dc80 mm: handle multiple owners of device private pages in migrate_vma +dnl # v5.6-rc3-14-gf894ddd5ff01 memremap: add an owner field to struct dev_pagemap +dnl # +AC_DEFUN([AC_AMDGPU_HSA_AMD_SVM], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #if !IS_ENABLED(CONFIG_DEVICE_PRIVATE) + #error "DEVICE_PRIVATE is a must for svm support" + #endif + ], [ + struct dev_pagemap *pm = NULL; + pm->owner = NULL; + ], [ + AC_DEFINE(HAVE_HSA_AMD_SVM_ENABLED, 1, + [dev_pagemap->owner is available]) + ]) + ]) +]) + From 4e4ea016c207c86e3394593ecc823936a430fc43 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 6 Apr 2021 14:10:59 +0800 Subject: [PATCH 0415/1868] drm/amdkcl: test for migrate_vma->pgmap_owner kernel 5.8 doesnot have migrate_vma.pgmap_owner, it uses migrate_vma.src_owner=NULL for system memory and migrate_vma.src_ovner=adev for device memory. Kernel 5.9 and 5.11 add migrate_vma.pgmap_owner, and migrate_vma.flags to distinguish system memory or device memory. Signed-off-by: Flora Cui Signed-off-by: Philip Yang Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 9 +++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/svm.m4 | 17 +++++++++++++++++ 3 files changed, 29 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c index 8a9701d43f923..c7b5f704417c4 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@ -407,8 +407,12 @@ svm_migrate_vma_to_vram(struct kfd_node *node, struct svm_range *prange, migrate.vma = vma; migrate.start = start; migrate.end = end; +#ifdef HAVE_MIGRATE_VMA_PGMAP_OWNER migrate.flags = MIGRATE_VMA_SELECT_SYSTEM; migrate.pgmap_owner = SVM_ADEV_PGMAP_OWNER(adev); +#else + migrate.src_owner = NULL; +#endif buf = kvcalloc(npages, 2 * sizeof(*migrate.src) + sizeof(uint64_t) + sizeof(dma_addr_t), @@ -707,11 +711,15 @@ svm_migrate_vma_to_ram(struct kfd_node *node, struct svm_range *prange, migrate.vma = vma; migrate.start = start; migrate.end = end; +#ifdef HAVE_MIGRATE_VMA_PGMAP_OWNER migrate.pgmap_owner = SVM_ADEV_PGMAP_OWNER(adev); if (adev->gmc.xgmi.connected_to_cpu) migrate.flags = MIGRATE_VMA_SELECT_DEVICE_COHERENT; else migrate.flags = MIGRATE_VMA_SELECT_DEVICE_PRIVATE; +#else + migrate.src_owner = SVM_ADEV_PGMAP_OWNER(adev); +#endif buf = kvcalloc(npages, 2 * sizeof(*migrate.src) + sizeof(uint64_t) + sizeof(dma_addr_t), @@ -1073,6 +1081,7 @@ int kgd2kfd_init_zone_device(struct amdgpu_device *adev) pgmap->ops = &svm_migrate_pgmap_ops; pgmap->owner = SVM_ADEV_PGMAP_OWNER(adev); pgmap->flags = 0; + /* Device manager releases device-specific resources, memory region and * pgmap when driver disconnects from device. */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 703e254dacb0e..50c03bd2ddcbd 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -738,6 +738,9 @@ /* mem_encrypt_active() is available */ #define HAVE_MEM_ENCRYPT_ACTIVE 1 +/* migrate_vma->pgmap_owner is available */ +#define HAVE_MIGRATE_VMA_PGMAP_OWNER 1 + /* mmgrab() is available */ #define HAVE_MMGRAB 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/svm.m4 b/drivers/gpu/drm/amd/dkms/m4/svm.m4 index ef2c930e21391..0deabfae97260 100644 --- a/drivers/gpu/drm/amd/dkms/m4/svm.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/svm.m4 @@ -1,3 +1,18 @@ +dnl # +dnl # v5.8-rc4-7-g5143192cd410 mm/migrate: add a flags parameter to migrate_vma +dnl # +AC_DEFUN([AC_AMDGPU_MIGRATE_VMA_PGMAP_OWNER], [ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct migrate_vma *migrate = NULL; + migrate->pgmap_owner = NULL; + ], [ + AC_DEFINE(HAVE_MIGRATE_VMA_PGMAP_OWNER, 1, + [migrate_vma->pgmap_owner is available]) + ]) +]) + dnl # dnl # v5.6-rc3-15-g800bb1c8dc80 mm: handle multiple owners of device private pages in migrate_vma dnl # v5.6-rc3-14-gf894ddd5ff01 memremap: add an owner field to struct dev_pagemap @@ -15,6 +30,8 @@ AC_DEFUN([AC_AMDGPU_HSA_AMD_SVM], [ ], [ AC_DEFINE(HAVE_HSA_AMD_SVM_ENABLED, 1, [dev_pagemap->owner is available]) + + AC_AMDGPU_MIGRATE_VMA_PGMAP_OWNER ]) ]) ]) From c5b81e6e6ecf26f216f45e060b4d10f7c948f42e Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 19 Apr 2021 13:12:39 +0800 Subject: [PATCH 0416/1868] drm/amdkcl: direct include memremap.h for legacy os This is caused by "drm/amdkfd: register HMM device private zone" v5.11-3037-g2f833caf32eb Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index c778f1309b5a0..c3f7125464eed 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -47,6 +47,7 @@ #include #include #include +#include #include "amdgpu_amdkfd.h" #include "amd_shared.h" From c0e31e3c6d5cd96e0acb7a56d3b9a7a35be045e8 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 19 Apr 2021 13:52:15 +0800 Subject: [PATCH 0417/1868] drm/amdkcl: wrap the code under HAVE_TREE_INSERT_HAVE_RB_ROOT_CACHED This is caused by "drm/amdkfd: register svm range" v5.11-3025-gcdc3d25724fd Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index c3f7125464eed..1af4c8e670acf 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -903,7 +903,9 @@ struct kfd_process_device { struct svm_range_list { struct mutex lock; +#ifdef HAVE_TREE_INSERT_HAVE_RB_ROOT_CACHED struct rb_root_cached objects; +#endif struct list_head list; struct work_struct deferred_list_work; struct list_head deferred_range_list; From 8bfb240ef955f91b18b56b285622a45a9c305ca9 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 20 Apr 2021 10:21:04 +0800 Subject: [PATCH 0418/1868] drm/amdkcl: fix autoconf test for svm config Signed-off-by: Flora Cui Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/m4/hmm.m4 | 2 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - drivers/gpu/drm/amd/dkms/m4/svm.m4 | 30 +++++++++++++-------------- 3 files changed, 16 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/hmm.m4 b/drivers/gpu/drm/amd/dkms/m4/hmm.m4 index 228e66022b959..5137132996950 100644 --- a/drivers/gpu/drm/amd/dkms/m4/hmm.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/hmm.m4 @@ -15,6 +15,8 @@ AC_DEFUN([AC_AMDGPU_HMM_RANGE_FAULT], [ [hmm remove the customizable pfn format]) AC_DEFINE(HAVE_HMM_RANGE_FAULT_1ARG, 1, [hmm_range_fault() wants 1 arg]) + + AC_AMDGPU_HSA_AMD_SVM ], [ dnl # dnl # v5.6-rc3-21-g6bfef2f91945 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 13b92df1691cc..fe8c833ebfa0b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -67,7 +67,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_AMD_IOMMU_PC_SUPPORTED AC_AMDGPU_AMD_IOMMU_INVALIDATE_CTX AC_AMDGPU_DEV_PAGEMAP - AC_AMDGPU_HSA_AMD_SVM AC_AMDGPU_DOWN_READ_KILLABLE AC_AMDGPU_DRM_CACHE AC_AMDGPU_DRM_DEBUG_ENABLED diff --git a/drivers/gpu/drm/amd/dkms/m4/svm.m4 b/drivers/gpu/drm/amd/dkms/m4/svm.m4 index 0deabfae97260..dbcd257ba1662 100644 --- a/drivers/gpu/drm/amd/dkms/m4/svm.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/svm.m4 @@ -18,21 +18,19 @@ dnl # v5.6-rc3-15-g800bb1c8dc80 mm: handle multiple owners of device private pag dnl # v5.6-rc3-14-gf894ddd5ff01 memremap: add an owner field to struct dev_pagemap dnl # AC_DEFUN([AC_AMDGPU_HSA_AMD_SVM], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - #if !IS_ENABLED(CONFIG_DEVICE_PRIVATE) - #error "DEVICE_PRIVATE is a must for svm support" - #endif - ], [ - struct dev_pagemap *pm = NULL; - pm->owner = NULL; - ], [ - AC_DEFINE(HAVE_HSA_AMD_SVM_ENABLED, 1, - [dev_pagemap->owner is available]) - - AC_AMDGPU_MIGRATE_VMA_PGMAP_OWNER - ]) - ]) + AC_KERNEL_TRY_COMPILE([ + #include + #if !IS_ENABLED(CONFIG_DEVICE_PRIVATE) + #error "DEVICE_PRIVATE is a must for svm support" + #endif + ], [ + struct dev_pagemap *pm = NULL; + pm->owner = NULL; + ], [ + AC_DEFINE(HAVE_HSA_AMD_SVM_ENABLED, 1, + [dev_pagemap->owner is available]) + + AC_AMDGPU_MIGRATE_VMA_PGMAP_OWNER + ]) ]) From eded93d66887de6934e7193d6e1b26eca55cfae7 Mon Sep 17 00:00:00 2001 From: Ramesh Errabolu Date: Wed, 14 Apr 2021 12:19:39 -0500 Subject: [PATCH 0419/1868] drm/amdgpu: Use VRAM Mgr api's to export SG Tables Use api's exported by VRAM Mgr (amdgpu_vram_mgr.c) to build and export SG Tables for access by peer PCIe devices. These api's allow a VRAM buffer object to be partitioned into multiple non-overlapping segments. For example one could partition a VRAM buffer into two segments, one serving as SRC buffer while the other serves as DST buffer. Signed-off-by: Ramesh Errabolu Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index d666e63230354..337b81af7438f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -2558,6 +2558,7 @@ int amdgpu_amdkfd_gpuvm_get_sg_table(struct kgd_dev *kgd, * Walk down system memory pointed by BO while * Updating Scatterlist nodes with system memory info */ + sg = kmalloc(sizeof(*sg), GFP_KERNEL); if (!sg) { ret = -ENOMEM; From 5360a745610807af6b121c411c30e410e3d738c4 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 21 Apr 2021 13:19:15 +0800 Subject: [PATCH 0420/1868] drm/amdkcl: fix missing {} in amdgpu_hmm_range_get_pages Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c index 62856f6e3d949..9a68c36d7df98 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c @@ -913,7 +913,7 @@ int amdgpu_hmm_range_get_pages(struct mmu_interval_notifier *notifier, * hmm_range_fault() fails. FIXME: The pages cannot be touched outside * the notifier_lock, and mmu_interval_read_retry() must be done first. */ - for (i = 0; pages && i < npages; i++) + for (i = 0; pages && i < npages; i++) { #ifndef HAVE_HMM_DROP_CUSTOMIZABLE_PFN_FORMAT pages[i] = hmm_device_entry_to_page(hmm_range, hmm_range->pfns[i]); if (unlikely(!pages[i])) { @@ -927,6 +927,7 @@ int amdgpu_hmm_range_get_pages(struct mmu_interval_notifier *notifier, #else pages[i] = hmm_pfn_to_page(pfns[i]); #endif + } *phmm_range = hmm_range; From 17d810d6ed5cf3e01496022b0c946b4f05d67630 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 21 Apr 2021 10:57:09 +0800 Subject: [PATCH 0421/1868] drm/amdkcl: wrap the code under HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE This is caused by "drm/amd/display: update hdcp display using correct CP type." v5.11-3068-g2b39a66dfe7b Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen Signed-off-by: Ma Jun Change-Id: I8c6650ceb98679c6e708d7b8d8380634a279fb99 --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c index 59884dad8843b..c5a66857a5516 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c @@ -554,6 +554,7 @@ static void update_config(void *handle, struct cp_psp_stream_config *config) link->adjust.hdcp1.disable = 0; hdcp_w->encryption_status[display->index] = MOD_HDCP_ENCRYPTION_STATUS_HDCP_OFF; +#ifdef HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE DRM_DEBUG_DRIVER("[HDCP_DM] display %d, CP %d, type %d\n", aconnector->base.index, (!!aconnector->base.state) ? aconnector->base.state->content_protection : -1, @@ -566,7 +567,7 @@ static void update_config(void *handle, struct cp_psp_stream_config *config) process_output(hdcp_w); mutex_unlock(&hdcp_w->mutex); - +#endif } /** From fecbbe1bb26044772084da32a8d9c2e732642d42 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Sun, 25 Apr 2021 11:10:48 +0800 Subject: [PATCH 0422/1868] drm/amdkcl: adapt code to access format field of struct drm_framebuffer This is caused by "drm/amd/display: Reject non-zero src_y and src_x for video planes" v5.11-3116-g7af71c0752f0 Signed-off-by: Leslie Shi Reviewed-by: Flora Cui Signed-off-by: Ma Jun Change-Id: Ic7b7718302c27d2bf2193760407933401c923f48 --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 - drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 9 +++++++-- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 1f31388c105c1..3665279d0d23b 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -5629,7 +5629,6 @@ fill_dc_plane_info_and_addr(struct amdgpu_device *adev, break; } - plane_info->visible = true; plane_info->stereo_format = PLANE_STEREO_FORMAT_NONE; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 9cf79ad8887bf..4f76c5a0e46b1 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -1181,8 +1181,13 @@ int amdgpu_dm_plane_fill_dc_scaling_info(struct amdgpu_device *adev, */ if (((amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 0)) || (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 1))) && - (state->fb && state->fb->format->format == DRM_FORMAT_NV12 && - (scaling_info->src_rect.x != 0 || scaling_info->src_rect.y != 0))) + (state->fb && +#ifndef HAVE_DRM_FRAMEBUFFER_FORMAT + state->fb->pixel_format == DRM_FORMAT_NV12 && +#else + state->fb->format->format == DRM_FORMAT_NV12 && +#endif + (scaling_info->src_rect.x != 0 || scaling_info->src_rect.y != 0))) return -EINVAL; scaling_info->src_rect.width = state->src_w >> 16; From dd47c1d4b618d3f83060f7b923f332fc40ebdbf3 Mon Sep 17 00:00:00 2001 From: Mukul Joshi Date: Wed, 21 Apr 2021 13:34:01 -0400 Subject: [PATCH 0423/1868] drm/amdkcl: test for is_smca_umc_v2 symbol Test if is_smca_umc_v2 symbol is available or not. This symbol is needed for page retirement handling on Aldebaran. Signed-off-by: Mukul Joshi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/m4/check_smca_umc_v2.m4 | 13 +++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 2 files changed, 14 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/check_smca_umc_v2.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/check_smca_umc_v2.m4 b/drivers/gpu/drm/amd/dkms/m4/check_smca_umc_v2.m4 new file mode 100644 index 0000000000000..28eda1decdae2 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/check_smca_umc_v2.m4 @@ -0,0 +1,13 @@ +dnl # +dnl # +dnl # is_smca_umc_v2() +dnl # +AC_DEFUN([AC_AMDGPU_CHECK_SMCA_UMC_V2], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([is_smca_umc_v2], + [arch/x86/kernel/cpu/mce/amd.c], [ + AC_DEFINE(HAVE_SMCA_UMC_V2, 1, + [is_smca_umc_v2() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index fe8c833ebfa0b..ce2f2b08b7dca 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -143,6 +143,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_PM_SUSPEND_VIA_FIRMWARE AC_AMDGPU_SYSFS_EMIT AC_AMDGPU_KTIME_IS_UNION + AC_AMDGPU_CHECK_SMCA_UMC_V2 AC_AMDGPU_DRM_MEMCPY_FROM_WC AC_AMDGPU_IS_COW_MAPPING AC_AMDGPU_VGA_REMOVE_VGACON From d34a1bd786542ff213fa58ef6e056e1a9eb8454a Mon Sep 17 00:00:00 2001 From: Mukul Joshi Date: Wed, 21 Apr 2021 13:37:06 -0400 Subject: [PATCH 0424/1868] drm/amdgpu: Register bad page handler for Aldebaran On Aldebaran, GPU driver will handle bad page retirement even though UMC is host managed. As a result, register a bad page retirement handler on the mce notifier chain to retire bad pages on Aldebaran. Signed-off-by: Mukul Joshi Reviewed-By: John Clements Acked-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 61a2f386d9fbe..49a5bc2ab9992 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -126,6 +126,16 @@ const char *get_ras_block_str(struct ras_common_if *ras_block) #define MAX_FLUSH_RETIRE_DWORK_TIMES 100 +#ifdef HAVE_SMCA_UMC_V2 +#define GET_MCA_IPID_GPUID(m) (((m) >> 44) & 0xF) +#define GET_UMC_INST_NIBBLE(m) (((m) >> 20) & 0xF) +#define GET_CHAN_INDEX_NIBBLE(m) (((m) >> 12) & 0xF) +#define GPU_ID_OFFSET 8 + +static bool notifier_registered = false; +static void amdgpu_register_bad_pages_mca_notifier(void); +#endif + enum amdgpu_ras_retire_page_reservation { AMDGPU_RAS_RETIRE_PAGE_RESERVED, AMDGPU_RAS_RETIRE_PAGE_PENDING, @@ -3224,10 +3234,13 @@ int amdgpu_ras_recovery_init(struct amdgpu_device *adev) INIT_DELAYED_WORK(&con->page_retirement_dwork, amdgpu_ras_do_page_retirement); amdgpu_ras_ecc_log_init(&con->umc_ecc_log); #ifdef CONFIG_X86_MCE_AMD +#ifdef HAVE_SMCA_UMC_V2 if ((adev->asic_type == CHIP_ALDEBARAN) && (adev->gmc.xgmi.connected_to_cpu)) amdgpu_register_bad_pages_mca_notifier(adev); #endif +#endif + return 0; free: @@ -4130,6 +4143,7 @@ void amdgpu_release_ras_context(struct amdgpu_device *adev) } #ifdef CONFIG_X86_MCE_AMD +#ifdef HAVE_SMCA_UMC_V2 static struct amdgpu_device *find_adev(uint32_t node_id) { int i; @@ -4230,6 +4244,7 @@ static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev) } } #endif +#endif struct amdgpu_ras *amdgpu_ras_get_context(struct amdgpu_device *adev) { From 698808abccfe26302cd43531be16aa8cd20b751d Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 27 Apr 2021 11:06:29 +0800 Subject: [PATCH 0425/1868] drm/amdkcl: update config.h Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 50c03bd2ddcbd..81c902cba8bce 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -828,6 +828,9 @@ /* whether si_mem_available() is available */ #define HAVE_SI_MEM_AVAILABLE 1 +/* is_smca_umc_v2() is available */ +/* #undef HAVE_SMCA_UMC_V2 */ + /* strscpy() is available */ #define HAVE_STRSCPY 1 From fc5de11213c4b8e783420c45f8af62fd0d84a7cb Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Thu, 29 Apr 2021 16:58:17 +0800 Subject: [PATCH 0426/1868] drm/amdkcl: fix sg to page arrays callback for legacy OS To call the legacy drm_prime_sg_to_page_addr_arrays, the 2nd parameter should be page array instead of NULL pointer Otherwise, the page fault will be triggered Signed-off-by: Shiwu Zhang Reviewed-by: Flora Cui --- include/kcl/kcl_drm_prime.h | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/include/kcl/kcl_drm_prime.h b/include/kcl/kcl_drm_prime.h index 7f02b6c95d10c..8f207f1f44b91 100644 --- a/include/kcl/kcl_drm_prime.h +++ b/include/kcl/kcl_drm_prime.h @@ -12,8 +12,19 @@ static inline int drm_prime_sg_to_dma_addr_array(struct sg_table *sgt, dma_addr_t *addrs, int max_entries) { +#ifdef HAVE_TTM_SG_TT_INIT return drm_prime_sg_to_page_addr_arrays(sgt, NULL, addrs, max_entries); - -} +#else + /* + * the page array stands right next to dma address array, + * so get the page array pointer directly by max_entries offset + * refer to ttm_sg_tt_init() for initial array allocation and + * c67e62790f5c drm/prime: split array import functions v4 for + * the change to drm_prime_sg_to_page_addr_arrays() + */ + struct page **pages = (void*)addrs - max_entries; + return drm_prime_sg_to_page_addr_arrays(sgt, pages, addrs, max_entries); #endif +} +#endif /* HAVE_DRM_PRIME_SG_TO_DMA_ADDR_ARRAY */ #endif From 4d04e3ed5e0240958ef7fce55c4de4492efcb479 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 30 Apr 2021 14:56:46 +0800 Subject: [PATCH 0427/1868] drm/amdkcl: fake hmm_pfn_to_page() Suggested-by: Felix Kuehling Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c | 9 ++++----- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h | 17 +++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 14 -------------- 3 files changed, 21 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c index 9a68c36d7df98..1fada0f022dc0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c @@ -820,13 +820,13 @@ void amdgpu_hmm_unregister(struct amdgpu_bo *bo) #ifndef HAVE_HMM_DROP_CUSTOMIZABLE_PFN_FORMAT /* flags used by HMM internal, not related to CPU/GPU PTE flags */ -static const uint64_t hmm_range_flags[HMM_PFN_FLAG_MAX] = { +const uint64_t hmm_range_flags[HMM_PFN_FLAG_MAX] = { (1 << 0), /* HMM_PFN_VALID */ (1 << 1), /* HMM_PFN_WRITE */ 0 /* HMM_PFN_DEVICE_PRIVATE */ }; -static const uint64_t hmm_range_values[HMM_PFN_VALUE_MAX] = { +const uint64_t hmm_range_values[HMM_PFN_VALUE_MAX] = { 0xfffffffffffffffeUL, /* HMM_PFN_ERROR */ 0, /* HMM_PFN_NONE */ 0xfffffffffffffffcUL /* HMM_PFN_SPECIAL */ @@ -915,15 +915,14 @@ int amdgpu_hmm_range_get_pages(struct mmu_interval_notifier *notifier, */ for (i = 0; pages && i < npages; i++) { #ifndef HAVE_HMM_DROP_CUSTOMIZABLE_PFN_FORMAT - pages[i] = hmm_device_entry_to_page(hmm_range, hmm_range->pfns[i]); + pages[i] = hmm_device_entry_to_page(hmm_range, pfns[i]); if (unlikely(!pages[i])) { pr_err("Page fault failed for pfn[%lu] = 0x%llx\n", - i, hmm_range->pfns[i]); + i, pfns[i]); r = -ENOMEM; goto out_free_pfns; } - #else pages[i] = hmm_pfn_to_page(pfns[i]); #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h index 7d7a087899125..b70e93444fabb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h @@ -66,6 +66,23 @@ static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {} #include #include +#ifndef HAVE_HMM_DROP_CUSTOMIZABLE_PFN_FORMAT +/* flags used by HMM internal, not related to CPU/GPU PTE flags */ +extern const uint64_t hmm_range_flags[HMM_PFN_FLAG_MAX]; +extern const uint64_t hmm_range_values[HMM_PFN_VALUE_MAX]; + +static inline struct page *hmm_pfn_to_page(unsigned long hmm_pfn) +{ + struct hmm_range hmm_range = { + .flags = hmm_range_flags, + .values = hmm_range_values, + .pfn_shift = PAGE_SHIFT, + }; + + return hmm_device_entry_to_page(&hmm_range, hmm_pfn); +} +#endif + int amdgpu_hmm_range_get_pages(struct mmu_interval_notifier *notifier, uint64_t start, uint64_t npages, bool readonly, void *owner, struct page **pages, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 60c7f12962014..9441c2612b517 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -738,20 +738,6 @@ struct amdgpu_ttm_tt { #ifdef CONFIG_DRM_AMDGPU_USERPTR #ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED -#ifndef HAVE_HMM_DROP_CUSTOMIZABLE_PFN_FORMAT -/* flags used by HMM internal, not related to CPU/GPU PTE flags */ -static const uint64_t hmm_range_flags[HMM_PFN_FLAG_MAX] = { - (1 << 0), /* HMM_PFN_VALID */ - (1 << 1), /* HMM_PFN_WRITE */ - 0 /* HMM_PFN_DEVICE_PRIVATE */ -}; - -static const uint64_t hmm_range_values[HMM_PFN_VALUE_MAX] = { - 0xfffffffffffffffeUL, /* HMM_PFN_ERROR */ - 0, /* HMM_PFN_NONE */ - 0xfffffffffffffffcUL /* HMM_PFN_SPECIAL */ -}; -#endif /* * amdgpu_ttm_tt_get_user_pages - get device accessible pages that back user * memory and start HMM tracking CPU page table update From 89b9abb977ae1a06cea768664728bd366060e850 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 30 Apr 2021 13:58:54 +0800 Subject: [PATCH 0428/1868] drm/amdkcl: rework svm enabled dependency Signed-off-by: Flora Cui Acked-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 6 ++++-- drivers/gpu/drm/amd/dkms/Makefile | 2 +- drivers/gpu/drm/amd/dkms/config/config.h | 6 +++--- drivers/gpu/drm/amd/dkms/m4/hmm.m4 | 3 +-- drivers/gpu/drm/amd/dkms/m4/svm.m4 | 2 +- 5 files changed, 10 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c index c7b5f704417c4..5e3547dfc01f4 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@ -410,7 +410,7 @@ svm_migrate_vma_to_vram(struct kfd_node *node, struct svm_range *prange, #ifdef HAVE_MIGRATE_VMA_PGMAP_OWNER migrate.flags = MIGRATE_VMA_SELECT_SYSTEM; migrate.pgmap_owner = SVM_ADEV_PGMAP_OWNER(adev); -#else +#elif defined(HAVE_DEV_PAGEMAP_OWNER) migrate.src_owner = NULL; #endif @@ -717,7 +717,7 @@ svm_migrate_vma_to_ram(struct kfd_node *node, struct svm_range *prange, migrate.flags = MIGRATE_VMA_SELECT_DEVICE_COHERENT; else migrate.flags = MIGRATE_VMA_SELECT_DEVICE_PRIVATE; -#else +#elif defined(HAVE_DEV_PAGEMAP_OWNER) migrate.src_owner = SVM_ADEV_PGMAP_OWNER(adev); #endif @@ -1079,7 +1079,9 @@ int kgd2kfd_init_zone_device(struct amdgpu_device *adev) } pgmap->ops = &svm_migrate_pgmap_ops; +#ifdef HAVE_DEV_PAGEMAP_OWNER pgmap->owner = SVM_ADEV_PGMAP_OWNER(adev); +#endif pgmap->flags = 0; /* Device manager releases device-specific resources, memory region and diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 4fc3b8e5ba5a4..b1eecc92ebfb3 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -158,7 +158,7 @@ subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_USERPTR subdir-ccflags-y += -DCONFIG_DRM_AMD_DC subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN1_0 -ifeq ($(call _is_kcl_macro_defined,HAVE_HSA_AMD_SVM_ENABLED),y) +ifeq ($(call _is_kcl_macro_defined,HAVE_AMDKCL_HMM_MIRROR_ENABLED),y) export CONFIG_HSA_AMD_SVM=y subdir-ccflags-y += -DCONFIG_HSA_AMD_SVM endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 81c902cba8bce..69b0de5a9f633 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -61,6 +61,9 @@ /* devm_memremap_pages() wants p,p,p,p interface */ /* #undef HAVE_DEVM_MEMREMAP_PAGES_P_P_P_P */ +/* dev_pagemap->owner is available */ +#define HAVE_DEV_PAGEMAP_OWNER 1 + /* there is 'range' field within dev_pagemap structure */ #define HAVE_DEV_PAGEMAP_RANGE 1 @@ -609,9 +612,6 @@ /* hmm_range_fault() wants 1 arg */ #define HAVE_HMM_RANGE_FAULT_1ARG 1 -/* dev_pagemap->owner is available */ -#define HAVE_HSA_AMD_SVM_ENABLED 1 - /* struct i2c_lock_operations is defined */ #define HAVE_I2C_LOCK_OPERATIONS_STRUCT 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/hmm.m4 b/drivers/gpu/drm/amd/dkms/m4/hmm.m4 index 5137132996950..c175fd6289702 100644 --- a/drivers/gpu/drm/amd/dkms/m4/hmm.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/hmm.m4 @@ -15,8 +15,6 @@ AC_DEFUN([AC_AMDGPU_HMM_RANGE_FAULT], [ [hmm remove the customizable pfn format]) AC_DEFINE(HAVE_HMM_RANGE_FAULT_1ARG, 1, [hmm_range_fault() wants 1 arg]) - - AC_AMDGPU_HSA_AMD_SVM ], [ dnl # dnl # v5.6-rc3-21-g6bfef2f91945 @@ -66,6 +64,7 @@ AC_DEFUN([AC_AMDGPU_HMM], [ AC_DEFINE(HAVE_AMDKCL_HMM_MIRROR_ENABLED, 1, [hmm support is enabled]) AC_AMDGPU_HMM_RANGE_FAULT + AC_AMDGPU_HSA_AMD_SVM ]) ]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/svm.m4 b/drivers/gpu/drm/amd/dkms/m4/svm.m4 index dbcd257ba1662..17657770988f5 100644 --- a/drivers/gpu/drm/amd/dkms/m4/svm.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/svm.m4 @@ -27,7 +27,7 @@ AC_DEFUN([AC_AMDGPU_HSA_AMD_SVM], [ struct dev_pagemap *pm = NULL; pm->owner = NULL; ], [ - AC_DEFINE(HAVE_HSA_AMD_SVM_ENABLED, 1, + AC_DEFINE(HAVE_DEV_PAGEMAP_OWNER, 1, [dev_pagemap->owner is available]) AC_AMDGPU_MIGRATE_VMA_PGMAP_OWNER From 4ae574a2d2fc4f368e769be653aed37cf37cdda0 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Fri, 7 May 2021 13:59:37 +0800 Subject: [PATCH 0429/1868] drm/amdkcl: wrap the code under HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED This is caused by "drm/amdgpu: Use device specific BO size & stride check." v5.11-3225-gdf0c606a6ced Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index d035c72750634..a0756e23ac83d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1194,6 +1194,7 @@ static int check_tiling_flags_gfx6(struct amdgpu_framebuffer *afb) } } +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED static void get_block_dimensions(unsigned int block_log2, unsigned int cpp, unsigned int *width, unsigned int *height) { @@ -1276,17 +1277,16 @@ static int amdgpu_display_verify_plane(struct amdgpu_framebuffer *rfb, int plane (uint64_t)rfb->base.pitches[plane] / block_pitch * block_size * DIV_ROUND_UP(height, block_height); - if (rfb->base.obj[0]->size < size) { + if (drm_gem_fb_get_obj(&rfb->base, 0)->size < size) { drm_dbg_kms(rfb->base.dev, "BO size 0x%zx is less than 0x%llx required for plane %d\n", - rfb->base.obj[0]->size, size, plane); + drm_gem_fb_get_obj(&rfb->base, 0)->size, size, plane); return -EINVAL; } return 0; } - static int amdgpu_display_verify_sizes(struct amdgpu_framebuffer *rfb) { const struct drm_format_info *format_info = drm_format_info(rfb->base.format->format); @@ -1390,6 +1390,7 @@ static int amdgpu_display_verify_sizes(struct amdgpu_framebuffer *rfb) return 0; } +#endif static int amdgpu_display_get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb, uint64_t *tiling_flags, bool *tmz_surface, @@ -1458,6 +1459,8 @@ static int amdgpu_display_gem_fb_verify_and_init(struct drm_device *dev, kcl_drm_gem_fb_set_obj(&rfb->base, 0, obj); drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd); + +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED /* Verify that the modifier is supported. */ if (!drm_any_plane_has_format(dev, mode_cmd->pixel_format, mode_cmd->modifier[0])) { @@ -1468,6 +1471,7 @@ static int amdgpu_display_gem_fb_verify_and_init(struct drm_device *dev, ret = -EINVAL; goto err; } +#endif ret = amdgpu_display_framebuffer_init(dev, rfb, mode_cmd, obj); if (ret) @@ -1578,13 +1582,17 @@ amdgpu_display_user_framebuffer_create(struct drm_device *dev, domains = amdgpu_display_supported_domains(drm_to_adev(dev), bo->flags); if (obj->import_attach && !(domains & AMDGPU_GEM_DOMAIN_GTT)) { drm_dbg_kms(dev, "Cannot create framebuffer from imported dma_buf\n"); +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED drm_gem_object_put(obj); +#endif return ERR_PTR(-EINVAL); } amdgpu_fb = kzalloc(sizeof(*amdgpu_fb), GFP_KERNEL); if (amdgpu_fb == NULL) { +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED drm_gem_object_put(obj); +#endif return ERR_PTR(-ENOMEM); } @@ -1592,11 +1600,16 @@ amdgpu_display_user_framebuffer_create(struct drm_device *dev, mode_cmd, obj); if (ret) { kfree(amdgpu_fb); +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED drm_gem_object_put(obj); +#endif return ERR_PTR(ret); } +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED drm_gem_object_put(obj); +#endif + return &amdgpu_fb->base; } From 94f0c5a058088177c85c4d90f03a676392022127 Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Fri, 7 May 2021 18:07:00 +0800 Subject: [PATCH 0430/1868] drm/amdkcl: export the symbol of pxm_to_node This is caused by "add ACPI SRAT parsing for topology" v2: dummy pxm_to_node() in case the symbol cannot be found by kallsyms_lookup_name() Signed-off-by: Shiwu Zhang Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_numa.c | 20 ++++++++++++++++++++ drivers/gpu/drm/amd/amdkcl/main.c | 2 ++ drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/pxm_to_node.m4 | 13 +++++++++++++ include/kcl/backport/kcl_numa_backport.h | 10 ++++++++++ 8 files changed, 51 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_numa.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/pxm_to_node.m4 create mode 100644 include/kcl/backport/kcl_numa_backport.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index a22c482f8b7b5..f95c0c73adb27 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -11,7 +11,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_drm_fb.o kcl_drm_print.o kcl_fbmem.o \ kcl_drm_crtc.o kcl_drm_connector.o kcl_drm_atomic_helper.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o kcl_ftrace.o \ - kcl_acpi_table.o kcl_page_alloc.o kcl_drm_aperture.o + kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_drm_aperture.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_numa.c b/drivers/gpu/drm/amd/amdkcl/kcl_numa.c new file mode 100644 index 0000000000000..92605529089d1 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_numa.c @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0-only +#include + +#ifndef HAVE_PXM_TO_NODE +int (*_kcl_pxm_to_node)(int pxm); +EXPORT_SYMBOL(_kcl_pxm_to_node); + +/* Copied from include/acpi/acpi_numa.h */ +static int __kcl_pxm_to_node_stub(int pxm) +{ + return 0; +} +#endif + +void amdkcl_numa_init(void) +{ +#ifndef HAVE_PXM_TO_NODE + _kcl_pxm_to_node = amdkcl_fp_setup("pxm_to_node", __kcl_pxm_to_node_stub); +#endif +} diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c index aa767fa0aa014..feb2d6548f323 100644 --- a/drivers/gpu/drm/amd/amdkcl/main.c +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -13,6 +13,7 @@ extern void amdkcl_perf_event_init(void); extern void amdkcl_pci_init(void); extern void amdkcl_suspend_init(void); extern void amdkcl_sched_init(void); +extern void amdkcl_numa_init(void); int __init amdkcl_init(void) { @@ -27,6 +28,7 @@ int __init amdkcl_init(void) amdkcl_pci_init(); amdkcl_suspend_init(); amdkcl_sched_init(); + amdkcl_numa_init(); return 0; } diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 2e0f765e1c88d..9e7bee1e97075 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -67,6 +67,7 @@ #include #include #include +#include #include "kcl/kcl_amdgpu_drm_fb_helper.h" #include "kcl/kcl_amdgpu_drm_gem_framebuffer_helper.h" #include "kcl/kcl_amdgpu.h" diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 69b0de5a9f633..5f53c6094f4c6 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -807,6 +807,9 @@ /* pm_suspend_via_firmware() is available */ #define HAVE_PM_SUSPEND_VIA_FIRMWARE 1 +/* pxm_to_node() is available */ +#define HAVE_PXM_TO_NODE 1 + /* remove_conflicting_framebuffers() returns int */ /* #undef HAVE_REMOVE_CONFLICTING_FRAMEBUFFERS_RETURNS_INT */ diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index ce2f2b08b7dca..6caeec79b63ba 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -144,6 +144,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_SYSFS_EMIT AC_AMDGPU_KTIME_IS_UNION AC_AMDGPU_CHECK_SMCA_UMC_V2 + AC_AMDGPU_PXM_TO_NODE AC_AMDGPU_DRM_MEMCPY_FROM_WC AC_AMDGPU_IS_COW_MAPPING AC_AMDGPU_VGA_REMOVE_VGACON diff --git a/drivers/gpu/drm/amd/dkms/m4/pxm_to_node.m4 b/drivers/gpu/drm/amd/dkms/m4/pxm_to_node.m4 new file mode 100644 index 0000000000000..35651096f8e2a --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pxm_to_node.m4 @@ -0,0 +1,13 @@ +dnl # +dnl # v5.7-20-gf2af6d3978d7 +dnl # virtio-mem: Allow to specify an ACPI PXM as nid +dnl # +AC_DEFUN([AC_AMDGPU_PXM_TO_NODE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([pxm_to_node], + [drivers/acpi/numa/srat.c], [ + AC_DEFINE(HAVE_PXM_TO_NODE, 1, + [pxm_to_node() is available]) + ]) + ]) +]) diff --git a/include/kcl/backport/kcl_numa_backport.h b/include/kcl/backport/kcl_numa_backport.h new file mode 100644 index 0000000000000..ef190c784cdbf --- /dev/null +++ b/include/kcl/backport/kcl_numa_backport.h @@ -0,0 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +#ifndef AMDKCL_NUMA_BACKPORT_H +#define AMDKCL_NUMA_BACKPORT_H + +#if !defined(HAVE_PXM_TO_NODE) +extern int _kcl_pxm_to_node(int pxm); +#define pxm_to_node _kcl_pxm_to_node +#endif + +#endif From a6fda17e48899b41dc9e6ae6468f656eeb615528 Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Sat, 8 May 2021 11:48:26 +0800 Subject: [PATCH 0431/1868] drm/amdkcl: wrap the code of GENERIC_AFFINITY processing Disable the GENERIC_AFFINITY related code for legacy OS where ACPI 6.x is NOT supported. This is caused by "add ACPI SRAT parsing for topology" Signed-off-by: Shiwu Zhang Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 2 ++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/acpi_srat.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 22 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/acpi_srat.m4 diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c index e391c7e4e49f4..6e1e8e4625221 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c @@ -2035,6 +2035,7 @@ static void kfd_find_numa_node_in_srat(struct kfd_node *kdev) if (pxm > max_pxm) max_pxm = pxm; break; +#ifdef HAVE_ACPI_SRAT_GENERIC_AFFINITY case ACPI_SRAT_TYPE_GENERIC_AFFINITY: gpu = (struct acpi_srat_generic_affinity *)sub_header; bdf = *((u16 *)(&gpu->device_handle[0])) << 16 | @@ -2044,6 +2045,7 @@ static void kfd_find_numa_node_in_srat(struct kfd_node *kdev) numa_node = pxm_to_node(gpu->proximity_domain); } break; +#endif default: break; } diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 5f53c6094f4c6..d48a7edc72c7d 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -13,6 +13,9 @@ /* acpi_put_table() is available */ #define HAVE_ACPI_PUT_TABLE 1 +/* struct acpi_srat_generic_affinity is available */ +#define HAVE_ACPI_SRAT_GENERIC_AFFINITY 1 + /* whether AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES is defined */ #define HAVE_AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/acpi_srat.m4 b/drivers/gpu/drm/amd/dkms/m4/acpi_srat.m4 new file mode 100644 index 0000000000000..16493b5e8d995 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/acpi_srat.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit aa475a59fff172ec858093fbc8471c0993081481 +dnl # ACPICA: ACPI 6.3: SRAT: add Generic Affinity Structure subtable +dnl # +AC_DEFUN([AC_AMDGPU_ACPI_SRAT_GENERIC_AFFINITY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct acpi_srat_generic_affinity *p = NULL; + p->reserved = 0; + ], [ + AC_DEFINE(HAVE_ACPI_SRAT_GENERIC_AFFINITY, 1, [struct acpi_srat_generic_affinity is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 6caeec79b63ba..d1b4b3076d7f2 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -145,6 +145,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_KTIME_IS_UNION AC_AMDGPU_CHECK_SMCA_UMC_V2 AC_AMDGPU_PXM_TO_NODE + AC_AMDGPU_ACPI_SRAT_GENERIC_AFFINITY AC_AMDGPU_DRM_MEMCPY_FROM_WC AC_AMDGPU_IS_COW_MAPPING AC_AMDGPU_VGA_REMOVE_VGACON From 0db3809e832a76e93072cf17277e9aa656e51168 Mon Sep 17 00:00:00 2001 From: Matt Ezell Date: Wed, 12 May 2021 12:38:14 -0400 Subject: [PATCH 0432/1868] drm/amdkfd: Unlock mutex in error path of kfd_ioctl_alloc_memory_of_gpu Signed-off-by: Matt Ezell Reviewed-by: Felix Kuehling Signed-off-by: Felix Kuehling Reviewed-by: Kent Russell --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 5e12b2786fcc8..1b4b393f8e521 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1127,7 +1127,7 @@ static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep, err = follow_pfn(vma, args->mmap_offset, &pfn); if (err) { pr_debug("Failed to get PFN: %ld\n", err); - return err; + goto err_unlock; } flags |= KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL; flags &= ~KFD_IOC_ALLOC_MEM_FLAGS_USERPTR; @@ -1136,7 +1136,8 @@ static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep, if (offset & (PAGE_SIZE - 1)) { pr_debug("Unaligned userptr address:%llx\n", offset); - return -EINVAL; + err = -EINVAL; + goto err_unlock; } cpuva = offset; } From 01f81e88347a053df924e3b95ae573d6333ae6d6 Mon Sep 17 00:00:00 2001 From: Hawking Zhang Date: Mon, 17 May 2021 13:07:54 +0800 Subject: [PATCH 0433/1868] drm/amdgpu: disable GFX RAS on A + A platform this is a regression introduced by 0c15d459a359ff3e02e0556248fc0af17e11b178 GFX RAS should be disabled by default on A + A platform Signed-off-by: Hawking Zhang Reviewed-by: Dennis Li --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 49a5bc2ab9992..54c1ad918a3ec 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -3461,9 +3461,8 @@ static void amdgpu_ras_check_supported(struct amdgpu_device *adev) } else { /* driver only manages a few IP blocks RAS feature * when GPU is connected cpu through XGMI */ - adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX | - 1 << AMDGPU_RAS_BLOCK__SDMA | - 1 << AMDGPU_RAS_BLOCK__MMHUB); + adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__SDMA | + 1 << AMDGPU_RAS_BLOCK__MMHUB); } /* apply asic specific settings (vega20 only for now) */ From c561d5f949001b18a3a7a1bc5c08d498329aedf5 Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Fri, 23 Apr 2021 14:20:47 +0800 Subject: [PATCH 0434/1868] drm/amdkcl: fix the resv reference in bo struct Signed-off-by: Shiwu Zhang Reviewed-by: Guchun Chen --- drivers/gpu/drm/ttm/ttm_bo.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index 7aff1bdd01526..b1696c3911983 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -1144,7 +1144,7 @@ int ttm_bo_swapout(struct ttm_buffer_object *bo, struct ttm_operation_ctx *ctx, bo->ttm->page_flags & TTM_TT_FLAG_SWAPPED || !ttm_bo_get_unless_zero(bo)) { if (locked) - dma_resv_unlock(bo->base.resv); + dma_resv_unlock(amdkcl_ttm_resvp(bo)); return -EBUSY; } From 144d6f8c04dcdc4093324a482dc90cd05b4c0f0e Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 12 Oct 2023 10:18:24 +0800 Subject: [PATCH 0435/1868] drm/amdkcl: fix IGT gamma test failure [why] Patch "drm: automatic legacy gamma support" removes the assignment of amdgpu_dm_crtc_funcs.gamma_set, it's ok on new kernel that drm core handled the gamma setting, but on old kernel, it results drm_mode_gamma_set_ioctl() exit with ENOSYS, then the IGT gamma test failed. [how] Bring the assignment code back to fix the failure. Change-Id: Iebdf4752e5a06fa551df18810e3da1ba52c9fba0 Reviewed-by: Flora Cui Signed-off-by: Tianci.Yin Signed-off-by: Ma Jun Signed-off-by: Asher Song --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 3 +++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 | 13 +++++++++++++ 3 files changed, 19 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c index 02880bf440741..ff25b4b928ee6 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c @@ -542,6 +542,9 @@ amdgpu_dm_atomic_crtc_get_property(struct drm_crtc *crtc, static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = { .reset = amdgpu_dm_crtc_reset_state, .destroy = amdgpu_dm_crtc_destroy, +#ifndef HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL + .gamma_set = drm_atomic_helper_legacy_gamma_set, +#endif .set_config = drm_atomic_helper_set_config, .page_flip = drm_atomic_helper_page_flip, .atomic_duplicate_state = amdgpu_dm_crtc_duplicate_state, diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index d48a7edc72c7d..848d2f2e56b40 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -128,6 +128,9 @@ /* drm_atomic_helper_check_plane_state() is available */ #define HAVE_DRM_ATOMIC_HELPER_CHECK_PLANE_STATE 1 +/* HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL is available */ +#define HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL 1 + /* drm_atomic_helper_shutdown() is available */ #define HAVE_DRM_ATOMIC_HELPER_SHUTDOWN 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 index 2820aaa74c3b0..e92c34e468d65 100644 --- a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 @@ -159,6 +159,18 @@ AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET], [ ]) ]) +dnl # +dnl # v5.10-1961-g6ca2ab8086af drm: automatic legacy gamma support +dnl # +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL], [ + AC_KERNEL_CHECK_SYMBOL_EXPORT( + [drm_atomic_helper_legacy_gamma_set], [drivers/gpu/drm/drm_atomic_helper.c], [], + [ + AC_DEFINE(HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL, 1, + [HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL is available]) + ]) +]) + AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS], [ AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_ENABLE_VBLANK @@ -166,4 +178,5 @@ AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS], [ AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_SET_CONFIG AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET + AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL ]) From 35389b6d39cef5b16961f255d8338d2e86eaf00c Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Tue, 18 May 2021 17:14:05 +0800 Subject: [PATCH 0436/1868] drm/amdkcl: fix the calculation of pages array based on dma array Signed-off-by: Shiwu Zhang Reviewed-by: Flora Cui --- include/kcl/kcl_drm_prime.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/kcl/kcl_drm_prime.h b/include/kcl/kcl_drm_prime.h index 8f207f1f44b91..2c5e972520576 100644 --- a/include/kcl/kcl_drm_prime.h +++ b/include/kcl/kcl_drm_prime.h @@ -22,7 +22,7 @@ int drm_prime_sg_to_dma_addr_array(struct sg_table *sgt, dma_addr_t *addrs, * c67e62790f5c drm/prime: split array import functions v4 for * the change to drm_prime_sg_to_page_addr_arrays() */ - struct page **pages = (void*)addrs - max_entries; + struct page **pages = (void*)((unsigned long)addrs - max_entries*sizeof(dma_addr_t)); return drm_prime_sg_to_page_addr_arrays(sgt, pages, addrs, max_entries); #endif } From 5e645e456309daa171f904fe7be6572b98297387 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 18 May 2021 13:25:00 +0800 Subject: [PATCH 0437/1868] drm/amdkcl: wrap the code under CONFIG_DRM_AMD_DC_DSC_SUPPORT This is caused by "drm/amd/display: Initial DC support for Beige Goby" v5.11-3391-g54f910c6372e Signed-off-by: Leslie Shi --- .../amd/display/dc/resource/dcn303/dcn303_resource.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c index 63f0f882c8610..38053ce302cd4 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c @@ -127,7 +127,9 @@ static const struct resource_caps res_cap_dcn303 = { .num_ddc = 2, .num_vmid = 16, .num_mpc_3dlut = 1, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .num_dsc = 2, +#endif }; static const struct dc_plane_cap plane_cap = { @@ -623,6 +625,7 @@ static struct mpc *dcn303_mpc_create(struct dc_context *ctx, int num_mpcc, int n return &mpc30->base; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #define dsc_regsDCN20(id)\ [id] = { DSC_REG_LIST_DCN20(id) } @@ -651,6 +654,7 @@ static struct display_stream_compressor *dcn303_dsc_create(struct dc_context *ct dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); return &dsc->base; } +#endif #define dwbc_regs_dcn3(id)\ [id] = { DWBC_COMMON_REG_LIST_DCN30(id) } @@ -949,10 +953,12 @@ static void dcn303_resource_destruct(struct resource_pool *pool) } } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->res_cap->num_dsc; i++) { if (pool->dscs[i] != NULL) dcn20_dsc_destroy(&pool->dscs[i]); } +#endif if (pool->mpc != NULL) { kfree(TO_DCN20_MPC(pool->mpc)); @@ -1087,7 +1093,9 @@ static struct resource_funcs dcn303_res_pool_funcs = { .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, .add_stream_to_ctx = dcn30_add_stream_to_ctx, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, +#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, .set_mcif_arb_params = dcn30_set_mcif_arb_params, @@ -1361,6 +1369,7 @@ static bool dcn303_resource_construct( goto create_fail; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->res_cap->num_dsc; i++) { pool->dscs[i] = dcn303_dsc_create(ctx, i); if (pool->dscs[i] == NULL) { @@ -1369,6 +1378,7 @@ static bool dcn303_resource_construct( goto create_fail; } } +#endif /* DWB and MMHUBBUB */ if (!dcn303_dwbc_create(ctx, pool)) { From de32ad0ee55ac8ede1db909cae263e507a631cde Mon Sep 17 00:00:00 2001 From: Jonathan Kim Date: Wed, 19 May 2021 09:29:00 -0400 Subject: [PATCH 0438/1868] drm/amdkfd: complete indirect peer no-atomics support checks When setting no-atomics flags for a target GPU, the target should self check atomic support over root and check the source GPU's atomic endpoint support to complete the flag check and set. Signed-off-by: Jonathan Kim Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 35 ++++++++++++++++------- 1 file changed, 25 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index 9c445538adbd7..3472cd061838a 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -1290,7 +1290,16 @@ static void kfd_set_iolink_no_atomics(struct kfd_topology_device *dev, if (link->iolink_type == CRAT_IOLINK_TYPE_XGMI) return; - /* check pcie support to set cpu(dev) flags for target_gpu_dev link. */ + /* checkout source dev has atomics support on root. */ + if (dev->gpu && (!dev->gpu->pci_atomic_requested || + dev->gpu->device_info->asic_family == + CHIP_HAWAII)) { + link->flags |= CRAT_IOLINK_FLAGS_NO_ATOMICS_32_BIT | + CRAT_IOLINK_FLAGS_NO_ATOMICS_64_BIT; + return; + } + + /* check target_gpu_dev is atomics capable. */ if (target_gpu_dev) { uint32_t cap; @@ -1443,17 +1452,23 @@ static void kfd_fill_iolink_non_crat_info(struct kfd_topology_device *dev) } } - /* Create CPU<->GPU indirect links so apply flags setting to all */ + /* Create indirect links so apply flags setting to all */ list_for_each_entry(link, &dev->p2p_link_props, list) { - cpu_dev = kfd_topology_device_by_proximity_domain( + link->flags = CRAT_IOLINK_FLAGS_ENABLED; + kfd_set_iolink_no_atomics(dev, NULL, link); + peer_dev = kfd_topology_device_by_proximity_domain( link->node_to); - if (cpu_dev && !cpu_dev->gpu) { - list_for_each_entry(cpu_link, - &cpu_dev->p2p_link_props, list) - if (cpu_link->node_to == link->node_from) { - link->flags = flag; - cpu_link->flags = cpu_flag; - } + + if (!peer_dev) + continue; + + list_for_each_entry(inbound_link, &peer_dev->p2p_link_props, + list) { + if (inbound_link->node_to != link->node_from) + continue; + + inbound_link->flags = CRAT_IOLINK_FLAGS_ENABLED; + kfd_set_iolink_no_atomics(peer_dev, dev, inbound_link); } } } From 775ee6ebcc830c02db14ba2aa334f1839a0aa6db Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 18 May 2021 15:53:33 +0800 Subject: [PATCH 0439/1868] drm/amdkcl: adapt code for legacy os This is caused by following commits: d9e1c5963c97 drm/amd/amdgpu: fix refcount leak 9faf262c32d3 drm/amdgpu: Add DMA mapping of GTT BOs ac89ed0789f8 drm/amdgpu: Move kfd_mem_attach outside reservation Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 6 +++++- drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 8 +++++--- 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 337b81af7438f..c238ca60f1503 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -824,7 +824,7 @@ static int kfd_mem_export_dmabuf(struct kgd_mem *mem) bo_adev = amdgpu_ttm_adev(mem->bo->tbo.bdev); r = drm_gem_prime_handle_to_fd(&bo_adev->ddev, bo_adev->kfd.client.file, mem->gem_handle, - mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ? + mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ? DRM_RDWR : 0, &fd); if (r) return r; @@ -838,6 +838,7 @@ static int kfd_mem_export_dmabuf(struct kgd_mem *mem) return 0; } +#ifdef AMDKCL_AMDGPU_DMABUF_OPS static int kfd_mem_attach_dmabuf(struct amdgpu_device *adev, struct kgd_mem *mem, struct amdgpu_bo **bo) @@ -858,6 +859,7 @@ kfd_mem_attach_dmabuf(struct amdgpu_device *adev, struct kgd_mem *mem, return 0; } +#endif /* kfd_mem_attach - Add a BO to a VM * @@ -948,6 +950,7 @@ static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem, ret = create_dmamap_sg_bo(adev, mem, &bo[i]); if (ret) goto unwind; +#ifdef AMDKCL_AMDGPU_DMABUF_OPS /* Enable acces to GTT and VRAM BOs of peer devices */ } else if (mem->domain == AMDGPU_GEM_DOMAIN_GTT || mem->domain == AMDGPU_GEM_DOMAIN_VRAM) { @@ -956,6 +959,7 @@ static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem, if (ret) goto unwind; pr_debug("Employ DMABUF mechanism to enable peer GPU access\n"); +#endif } else { WARN_ONCE(true, "Handling invalid ATTACH request"); ret = -EINVAL; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c index 8a71c31f394a4..2367c391e6f33 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c @@ -304,10 +304,12 @@ static int amdgpu_fbdev_destroy(struct drm_device *dev, struct amdgpu_fbdev *rfb drm_fb_helper_unregister_fbi(&rfbdev->helper); obj = drm_gem_fb_get_obj(&rfb->base, 0); - if (rfb->base.obj[0]) { + if (obj) { +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED for (i = 0; i < rfb->base.format->num_planes; i++) - drm_gem_object_put(rfb->base.obj[0]); - amdgpufb_destroy_pinned_object(rfb->base.obj[0]); + drm_gem_object_put(obj); +#endif + amdgpufb_destroy_pinned_object(obj); kcl_drm_gem_fb_set_obj(&rfb->base, 0, NULL); drm_framebuffer_unregister_private(&rfb->base); drm_framebuffer_cleanup(&rfb->base); From 0c60d06af13f7358f4bbc4a8accb47528c27b033 Mon Sep 17 00:00:00 2001 From: Hawking Zhang Date: Fri, 21 May 2021 16:14:38 +0800 Subject: [PATCH 0440/1868] drm/amdgpu: allow force enable gfx ras on A + A platform This is temporary solution to allow enable gfx ras on A + A platform by setting kernel module parameter ras_mask to 0xe. It should be removed when gfx ras is enabled by default on A + A platform Signed-off-by: Hawking Zhang Reviewed-by: John Clements Reviewed-by: Dennis Li --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 54c1ad918a3ec..e1ea61eb4a9e1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -3463,6 +3463,12 @@ static void amdgpu_ras_check_supported(struct amdgpu_device *adev) * when GPU is connected cpu through XGMI */ adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__SDMA | 1 << AMDGPU_RAS_BLOCK__MMHUB); + /* This is temporary workaround to leverage ras_mask + * to allow nable GFX RAS manually. Should be removed later + */ + if (amdgpu_ras_enable && + (amdgpu_ras_mask == 0xe)) + adev->ras_hw_enabled |= 1 << AMDGPU_RAS_BLOCK__GFX; } /* apply asic specific settings (vega20 only for now) */ From 94fe68b30eda5c0abb65acde992cbf81d414d1c8 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 26 May 2021 14:59:49 +0800 Subject: [PATCH 0441/1868] drm/amdkcl: wrap code under macro for legacy os This is caused by "drm/amdgpu: Move dmabuf attach/detach to backend_(un)bind" v5.11-3411-g6c6210ae18ba Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 9441c2612b517..1565c4f4cae41 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -1128,6 +1128,8 @@ static int amdgpu_ttm_backend_bind(struct ttm_device *bdev, return r; } } else if (ttm->page_flags & TTM_TT_FLAG_EXTERNAL) { +#if defined(HAVE_DMA_BUF_OPS_DYNAMIC_MAPPING) || \ + defined(HAVE_STRUCT_DMA_BUF_OPS_PIN) if (!ttm->sg) { struct dma_buf_attachment *attach; struct sg_table *sgt; @@ -1139,6 +1141,7 @@ static int amdgpu_ttm_backend_bind(struct ttm_device *bdev, ttm->sg = sgt; } +#endif drm_prime_sg_to_dma_addr_array(ttm->sg, gtt->ttm.dma_address, ttm->num_pages); @@ -1251,11 +1254,14 @@ static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev, if (gtt->userptr) { amdgpu_ttm_tt_unpin_userptr(bdev, ttm); } else if (ttm->sg && gtt->gobj->import_attach) { +#ifdef defined(HAVE_DMA_BUF_OPS_DYNAMIC_MAPPING) || \ + defined(HAVE_STRUCT_DMA_BUF_OPS_PIN) struct dma_buf_attachment *attach; attach = gtt->gobj->import_attach; dma_buf_unmap_attachment(attach, ttm->sg, DMA_BIDIRECTIONAL); ttm->sg = NULL; +#endif } if (!gtt->bound) From ea147092ce427f37324c4b3a753aba4eccdb9309 Mon Sep 17 00:00:00 2001 From: Philip Yang Date: Tue, 8 Dec 2020 11:43:29 -0500 Subject: [PATCH 0442/1868] drm/amdgpu: fix mmu notifier release callback race exit_mmap calls MMU notifier release callback first, which schedule kfd_process_wq_release work and amdgpu_mn_destroy work, then calls unmap_vmas to unmap userptr, which calls amdgpu_mn_invalidate_range_start_hsa. kfd_process_wq_release work calls free_outstanding_kfd_bos -> amdgpu_mn_unregister to remove bo from amn->objects. amdgpu_mn_destroy work free bo nodes from amn->objects. amdgpu_mn_invalidate_range_start_hsa scans amn->objects tree to find bo. amdgpu_mn_destroy free bo nodes on the interval tree, but not free the tree. amdgpu_mn_invalidate_range_start_hsa scan the amn->objects to lookup bo node, this causes kernel BUG or NULL pointer access because bo node maybe freed. Fix: Set amn->objects tree to NULL, and remove amn from MMU notifier in amdgpu_mn_destroy before releasing adev->mn_lock. Kernel BUG backtrace: [849938.299554] BUG: unable to handle kernel paging request at [849938.314382] Call Trace: [849938.315637] amdgpu_mn_invalidate_range_start_hsa+0x55/0xc0 [amdgpu] [849938.316778] __mmu_notifier_invalidate_range_start+0x52/0x80 [849938.317627] try_to_unmap_one+0x101/0xa70 [849938.318545] ? entry_SYSCALL_64_after_hwframe+0xb9/0xca [849938.319590] ? __switch_to_asm+0x41/0x70 [849938.320434] ? __switch_to_asm+0x35/0x70 [849938.321525] ? __switch_to_asm+0x41/0x70 [849938.322676] rmap_walk_file+0xf7/0x260 [849938.323822] try_to_munlock+0x4d/0x70 [849938.324939] ? page_remove_rmap+0x350/0x350 [849938.326031] ? anon_vma_ctor+0x40/0x40 [849938.327089] ? page_get_anon_vma+0x80/0x80 [849938.328143] __munlock_isolated_page+0x26/0x60 [849938.329217] munlock_vma_page+0xff/0x110 [849938.330289] munlock_vma_pages_range+0x8d/0x3d0 [849938.331381] ? enqueue_entity+0x108/0x640 [849938.332466] ? select_idle_sibling+0x22/0x430 [849938.333560] ? enqueue_task_fair+0x7d/0x460 [849938.334671] exit_mmap+0x132/0x190 [849938.335750] ? __delayacct_add_tsk+0x183/0x1b0 [849938.336794] ? kmem_cache_free+0x18c/0x1b0 [849938.337816] mmput+0x54/0x130 [849938.338823] do_exit+0x353/0xb40 [849938.339821] do_group_exit+0x3a/0xa0 [849938.340814] get_signal+0x147/0x850 [849938.341825] do_signal+0x36/0x660 [849938.342835] ? ktime_get_ts64+0x40/0xe0 [849938.343839] exit_to_usermode_loop+0x89/0xf0 [849938.344605] do_syscall_64+0x198/0x1a0 BUG: SWDEV-262212 Signed-off-by: Philip Yang Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c index 1fada0f022dc0..d8ca2619f97cb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c @@ -149,14 +149,23 @@ static void amdgpu_mn_destroy(struct work_struct *work) } kfree(node); } + +#ifndef HAVE_TREE_INSERT_HAVE_RB_ROOT_CACHED + amn->objects = RB_ROOT; +#else + amn->objects = RB_ROOT_CACHED; +#endif + up_write(&amn->lock); - mutex_unlock(&adev->mn_lock); + #ifdef HAVE_MMU_NOTIFIER_PUT mmu_notifier_put(&amn->mn); #else mmu_notifier_unregister_no_release(&amn->mn, amn->mm); mmu_notifier_call_srcu(&amn->rcu, amdgpu_mn_free); #endif + + mutex_unlock(&adev->mn_lock); } /** From 962ed77c24903ff572bcfa5ddaead90cb9aa4701 Mon Sep 17 00:00:00 2001 From: Philip Yang Date: Sun, 30 May 2021 22:52:03 -0400 Subject: [PATCH 0443/1868] drm/amdgpu: unregister MMU notifier in release callback Schedule work to unregister MMU notifier in MMU release callback, if the work remove MMU notifier between invalidate_range_start and invalidate_range_end, amdgpu_mn_invalidate_range_end will not be called because the notifier is gone. This causes amn->lock is not unlocked, then amdgpu_mn_unregister hold adev->mn_lock, wait for amn->lock forever, and new process amdgpu_mn_register wait for adev->mn_lock, it is deadklock. Fix: Unregister MMU notifier in MMU notifier release callback, remove amn->work, it is not needed anymore. As a result, exit_mmap unmap outstanding userptr will not cause unnecessary queue evction and restore because MMU notifier is already removed before unmap userptr. BUG: SWDEV-262212 Signed-off-by: Philip Yang Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c index d8ca2619f97cb..128f079102013 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c @@ -75,9 +75,6 @@ struct amdgpu_mn { struct mmu_notifier mn; enum amdgpu_mn_type type; - /* only used on destruction */ - struct work_struct work; - /* protected by adev->mn_lock */ struct hlist_node node; @@ -123,13 +120,12 @@ static void amdgpu_mn_free(struct rcu_head *rcu) /** * amdgpu_mn_destroy - destroy the MMU notifier * - * @work: previously sheduled work item + * @amn: our notifier * - * Lazy destroys the notifier from a work item + * Destroy the notifier */ -static void amdgpu_mn_destroy(struct work_struct *work) +static void amdgpu_mn_destroy(struct amdgpu_mn *amn) { - struct amdgpu_mn *amn = container_of(work, struct amdgpu_mn, work); struct amdgpu_device *adev = amn->adev; struct amdgpu_mn_node *node, *next_node; struct amdgpu_bo *bo, *next_bo; @@ -174,15 +170,14 @@ static void amdgpu_mn_destroy(struct work_struct *work) * @mn: our notifier * @mm: the mm this callback is about * - * Shedule a work item to lazy destroy our notifier. + * Destroy our notifier. */ static void amdgpu_mn_release(struct mmu_notifier *mn, struct mm_struct *mm) { struct amdgpu_mn *amn = container_of(mn, struct amdgpu_mn, mn); - INIT_WORK(&amn->work, amdgpu_mn_destroy); - schedule_work(&amn->work); + amdgpu_mn_destroy(amn); } From eff68b821327ba1042997af6d7a5152ee38df294 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 2 Jun 2021 10:13:34 +0800 Subject: [PATCH 0444/1868] drm/amdkcl: define macro DRM_FORMAT_{XRGB/XBGR/ARGB/ABGR}16161616 for legacy os This is caused by bcd05bd9251f "drm/amd/display: Enable support for 16 bpc fixed-point framebuffers." Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- include/kcl/kcl_drm_fourcc.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/include/kcl/kcl_drm_fourcc.h b/include/kcl/kcl_drm_fourcc.h index 25cf40f897b23..d40688cb6422d 100644 --- a/include/kcl/kcl_drm_fourcc.h +++ b/include/kcl/kcl_drm_fourcc.h @@ -214,4 +214,17 @@ #define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */ #endif + +/* 64 bpp RGB */ +#ifndef DRM_FORMAT_XRGB16161616 +/* Copied from v5.11-3544-ga2fe23ecdbb7 */ +#define DRM_FORMAT_XRGB16161616 fourcc_code('X', 'R', '4', '8') /* [63:0] x:R:G:B 16:16:16:16 little endian */ +#define DRM_FORMAT_XBGR16161616 fourcc_code('X', 'B', '4', '8') /* [63:0] x:B:G:R 16:16:16:16 little endian */ +#endif + +#ifndef DRM_FORMAT_ARGB16161616 +#define DRM_FORMAT_ARGB16161616 fourcc_code('A', 'R', '4', '8') /* [63:0] A:R:G:B 16:16:16:16 little endian */ +#define DRM_FORMAT_ABGR16161616 fourcc_code('A', 'B', '4', '8') /* [63:0] A:B:G:R 16:16:16:16 little endian */ +#endif + #endif /* KCL_KCL_DRM_FOURCC_H */ From dbc06f99ef667ab1b2808ee3a182a76336f447bf Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 2 Jun 2021 15:54:34 +0800 Subject: [PATCH 0445/1868] drm/amdkcl: add macro drm_dbg_atomic This is caused by 216502b1e930 "amd/display: convert DRM_DEBUG_ATOMIC to drm_dbg_atomic" v5.11-3568-g216502b1e930 Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- include/kcl/kcl_drm_print.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index c51497dc79f3e..c2dac790ba1c8 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -141,6 +141,11 @@ void kcl_drm_err(const char *format, ...); void drm_dev_dbg(const struct device *dev, int category, const char *format, ...); #endif +#if !defined(drm_dbg_atomic) +#define drm_dbg_atomic(drm, fmt, ...) \ + drm_dev_dbg((drm)->dev, DRM_UT_ATOMIC, fmt, ##__VA_ARGS__) +#endif + #if !defined(drm_dbg_kms) #define drm_dbg_kms(drm, fmt, ...) \ drm_dev_dbg((drm)->dev, 0x04, fmt, ##__VA_ARGS__) From 351eaabf6346082eea541da4157243b15636e416 Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Fri, 4 Jun 2021 17:17:18 +0800 Subject: [PATCH 0446/1868] drm/amdkcl: fix the _kcl_pxm_to_node func declaration As _kcl_pxm_to_node is defined as func pointer the same for the declaration format. Otherwise the page fault will happen since the address of the pointer var itself is used for calling the func. [ 284.537683] kernel tried to execute NX-protected page - exploit attempt? (uid: 0) Signed-off-by: Shiwu Zhang Reviewed-by: Flora Cui --- include/kcl/backport/kcl_numa_backport.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/kcl/backport/kcl_numa_backport.h b/include/kcl/backport/kcl_numa_backport.h index ef190c784cdbf..99251097a9e76 100644 --- a/include/kcl/backport/kcl_numa_backport.h +++ b/include/kcl/backport/kcl_numa_backport.h @@ -3,7 +3,7 @@ #define AMDKCL_NUMA_BACKPORT_H #if !defined(HAVE_PXM_TO_NODE) -extern int _kcl_pxm_to_node(int pxm); +extern int (*_kcl_pxm_to_node)(int pxm); #define pxm_to_node _kcl_pxm_to_node #endif From 46024fc2ec42ea5420be490e6c2902c3a7c1da7a Mon Sep 17 00:00:00 2001 From: Ramesh Errabolu Date: Fri, 4 Jun 2021 12:51:31 -0500 Subject: [PATCH 0447/1868] drm/amdgpu: Access peer GPU VRAM BO's as DMABUF objects Current design enabling access to peer GPU's VRAM BO requires that system run with IOMMU disabled. Enabling the use of DMABUF objects relaxes this constraint i.e. access is not affected by IOMMU being ON or OFF. However, the use of DMABUF objects requires config option DMABUF_MOVE_NOTIFY to be enabled. When this config option is not SET access requests are valid only if IOMMU is OFF. Signed-off-by: Ramesh Errabolu Reviewed-by: Felix Kuehling --- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 39 +++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index c238ca60f1503..57873d77d8a4d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -861,6 +861,38 @@ kfd_mem_attach_dmabuf(struct amdgpu_device *adev, struct kgd_mem *mem, } #endif +/** + * @kfd_mem_attach_vram_bo: Acquires the handle of a VRAM BO that could + * be used to enable a peer GPU access it + * + * Implementation determines if access to VRAM BO would employ DMABUF + * or Shared BO mechanism. Employ DMABUF mechanism if kernel has config + * option DMABUF_MOVE_NOTIFY enabled. Employ Shared BO mechanism if above + * config option is not set. It is important to note that a Shared BO + * cannot be used to enable peer acces if system has IOMMU enabled + * + * @TODO: ADD Check to ensure IOMMU is not enabled. Should this check + * be somewhere as this is information could be useful in other places + */ +static int kfd_mem_attach_vram_bo(struct amdgpu_device *adev, + struct kgd_mem *mem, struct amdgpu_bo **bo, + struct kfd_mem_attachment *attachment) +{ + int ret = 0; + +#ifdef CONFIG_DMABUF_MOVE_NOTIFY + attachment->type = KFD_MEM_ATT_DMABUF; + ret = kfd_mem_attach_dmabuf(adev, mem, bo); + pr_debug("Employ DMABUF mechanim to enable peer GPU access\n"); +#else + *bo = mem->bo; + attachment->type = KFD_MEM_ATT_SHARED; + drm_gem_object_get(&(*bo)->tbo.base); + pr_debug("Employ Shared BO mechanim to enable peer GPU access\n"); +#endif + return ret; +} + /* kfd_mem_attach - Add a BO to a VM * * Everything that needs to bo done only once when a BO is first added @@ -960,6 +992,13 @@ static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem, goto unwind; pr_debug("Employ DMABUF mechanism to enable peer GPU access\n"); #endif + /* Enable peer acces to VRAM BO's */ + } else if (mem->domain == AMDGPU_GEM_DOMAIN_VRAM && + mem->bo->tbo.type == ttm_bo_type_device) { + ret = kfd_mem_attach_vram_bo(adev, mem, + &bo[i], attachment[i]); + if (ret) + goto unwind; } else { WARN_ONCE(true, "Handling invalid ATTACH request"); ret = -EINVAL; From cc4574127d263e03ce89b820a5dd6f6e701cc838 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Tue, 8 Jun 2021 12:13:06 -0400 Subject: [PATCH 0448/1868] drm/amdkcl: get list of supported ASIC The patch ensures that DKMS build succeeds against kernels that don't support all chips defined in amdgpu_pciid.h Change-Id: Id00ed13b2d8210965bd9de6759da1f1e776a3d4f Signed-off-by: Slava Grigorev Reviewed-by: Tim Writer Reviewed-by: Slava Abramov --- .../drm/amd/dkms/config/config-amd-chips.h | 3 ++ drivers/gpu/drm/amd/dkms/config/config.h | 2 ++ drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 5 ++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 29 +++++++++++++++++++ 4 files changed, 39 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/config/config-amd-chips.h diff --git a/drivers/gpu/drm/amd/dkms/config/config-amd-chips.h b/drivers/gpu/drm/amd/dkms/config/config-amd-chips.h new file mode 100644 index 0000000000000..9ff8bd1cb6a04 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/config/config-amd-chips.h @@ -0,0 +1,3 @@ +/* + * This file is managed by DKMS build. Do not edit. + */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 848d2f2e56b40..020d10ba36675 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1004,3 +1004,5 @@ /* Define to the version of this package. */ #define PACKAGE_VERSION "19.40" + +#include "config-amd-chips.h" diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index 1f21aec4ff2ee..5c9cf41e67120 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -46,6 +46,11 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # AC_KERNEL_CHECK_HEADERS([drm/drm_gem_ttm_helper.h]) + dnl # + dnl # Required by AC_KERNEL_SUPPORTED_AMD_CHIPS macro + dnl # + AC_KERNEL_CHECK_HEADERS([drm/amd_asic_type.h]) + dnl # dnl # v5.12-rc3-330-g2916059147ea dnl # drm/aperture: Add infrastructure for aperture ownership diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index d1b4b3076d7f2..d5c9005a84637 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -7,6 +7,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_LINUX_HEADERS AC_AMDGPU_DRM_HEADERS AC_AMDGPU_KALLSYMS_LOOKUP_NAME + AC_KERNEL_SUPPORTED_AMD_CHIPS AC_AMDGPU_IDR_REMOVE AC_AMDGPU_KREF_READ AC_AMDGPU_TYPE__POLL_T @@ -165,6 +166,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ ]) AC_SUBST(KERNEL_MAKE) + AH_BOTTOM([#include "config-amd-chips.h"]) ]) dnl # @@ -567,3 +569,30 @@ AC_DEFUN([AC_KERNEL_WAIT], [ AC_MSG_RESULT([failed]) ]) ]) + +dnl # +dnl # AC_KERNEL_SUPPORTED_AMD_CHIPS +dnl # get list of graphics chips supported by the amdgpu kernel driver +dnl # +AC_DEFUN([AC_KERNEL_SUPPORTED_AMD_CHIPS], [ + AC_MSG_CHECKING([for supported chips]) + AS_IF([test $HAVE_DRM_AMD_ASIC_TYPE_H], [ + chips=$(awk 'BEGIN {enum = 0} { + if ($[0] ~ "^enum amd_asic_type") + enum = 1; + if (enum && $[1] ~ "CHIP_") { + gsub(",", ""); + if ($[1] == "CHIP_LAST") + exit; + print $[1]; + } + }' $LINUX/include/drm/amd_asic_type.h) + + for i in $chips; do + $as_echo "#define HAVE_$i" >>config/config-amd-chips.h + done + AC_MSG_RESULT([done]) + ], [ + AC_MSG_RESULT([failed]) + ]) +]) From 1a62e22fb5c657d819cad52ada91241e6fa8fdae Mon Sep 17 00:00:00 2001 From: Guchun Chen Date: Wed, 9 Jun 2021 22:39:53 +0800 Subject: [PATCH 0449/1868] drm/amdkcl: fix a define typo Signed-off-by: Guchun Chen Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 1565c4f4cae41..db8f39c48ea11 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -1254,7 +1254,7 @@ static void amdgpu_ttm_backend_unbind(struct ttm_device *bdev, if (gtt->userptr) { amdgpu_ttm_tt_unpin_userptr(bdev, ttm); } else if (ttm->sg && gtt->gobj->import_attach) { -#ifdef defined(HAVE_DMA_BUF_OPS_DYNAMIC_MAPPING) || \ +#if defined(HAVE_DMA_BUF_OPS_DYNAMIC_MAPPING) || \ defined(HAVE_STRUCT_DMA_BUF_OPS_PIN) struct dma_buf_attachment *attach; From d58b14c27004381dc9009e857f2b9b408cd15040 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 9 Jun 2021 12:42:06 +0800 Subject: [PATCH 0450/1868] drm/amdkcl: wrap the coder under HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE This is caused by 4238367e9de8 "drm/amd/display: force CP to DESIRED when removing display" v5.11-3747-g084150ff1151 Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c index c5a66857a5516..f0bc72614588e 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_hdcp.c @@ -231,9 +231,11 @@ static void hdcp_remove_display(struct hdcp_workqueue *hdcp_work, if (conn_state && conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) { conn_state->content_protection = DRM_MODE_CONTENT_PROTECTION_DESIRED; +#ifdef HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE DRM_DEBUG_DRIVER("[HDCP_DM] display %d, CP 2 -> 1, type %u, DPMS %u\n", aconnector->base.index, conn_state->hdcp_content_type, aconnector->base.dpms); +#endif } mod_hdcp_remove_display(&hdcp_w->hdcp, aconnector->base.index, &hdcp_w->output); From 4c53831c187fffc70a16b908f0c524803e842a5e Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 10 Jun 2021 15:30:18 +0800 Subject: [PATCH 0451/1868] drm/amdkcl: disable support for 16 bpc fixed-point framebuffers in legacy os This is caused by 0c53c5194ddf "drm/amd/display: Enable support for 16 bpc fixed-point framebuffers." v5.11-3548-g0c53c5194ddf Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen Signed-off-by: Ma Jun Change-Id: I20f72b0bd90888520cb4e47453b94ffb1a75c157 --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 2 ++ include/kcl/kcl_drm_fourcc.h | 13 ------------- 2 files changed, 2 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 4f76c5a0e46b1..3e900ecfd3405 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -52,10 +52,12 @@ static const uint32_t rgb_formats[] = { DRM_FORMAT_XBGR2101010, DRM_FORMAT_ARGB2101010, DRM_FORMAT_ABGR2101010, +#ifdef DRM_FORMAT_XRGB16161616 DRM_FORMAT_XRGB16161616, DRM_FORMAT_XBGR16161616, DRM_FORMAT_ARGB16161616, DRM_FORMAT_ABGR16161616, +#endif DRM_FORMAT_XBGR8888, DRM_FORMAT_ABGR8888, DRM_FORMAT_RGB565, diff --git a/include/kcl/kcl_drm_fourcc.h b/include/kcl/kcl_drm_fourcc.h index d40688cb6422d..25cf40f897b23 100644 --- a/include/kcl/kcl_drm_fourcc.h +++ b/include/kcl/kcl_drm_fourcc.h @@ -214,17 +214,4 @@ #define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */ #endif - -/* 64 bpp RGB */ -#ifndef DRM_FORMAT_XRGB16161616 -/* Copied from v5.11-3544-ga2fe23ecdbb7 */ -#define DRM_FORMAT_XRGB16161616 fourcc_code('X', 'R', '4', '8') /* [63:0] x:R:G:B 16:16:16:16 little endian */ -#define DRM_FORMAT_XBGR16161616 fourcc_code('X', 'B', '4', '8') /* [63:0] x:B:G:R 16:16:16:16 little endian */ -#endif - -#ifndef DRM_FORMAT_ARGB16161616 -#define DRM_FORMAT_ARGB16161616 fourcc_code('A', 'R', '4', '8') /* [63:0] A:R:G:B 16:16:16:16 little endian */ -#define DRM_FORMAT_ABGR16161616 fourcc_code('A', 'B', '4', '8') /* [63:0] A:B:G:R 16:16:16:16 little endian */ -#endif - #endif /* KCL_KCL_DRM_FOURCC_H */ From 012ecd713a28e16681a719f777bcc5442a72e33d Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 15 Jun 2021 13:45:38 +0800 Subject: [PATCH 0452/1868] drm/amdkcl: add DP_* macro for legacy os This is caused by f50245219f8c "drm/amd/display: Partition DPCD address space and break up transactions" v5.11-3817-gf50245219f8c Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- include/kcl/kcl_drm_dp_helper.h | 53 ++++++++++++++++++++++++++++++--- 1 file changed, 49 insertions(+), 4 deletions(-) diff --git a/include/kcl/kcl_drm_dp_helper.h b/include/kcl/kcl_drm_dp_helper.h index edb6b4202915b..7fb0da12e569b 100644 --- a/include/kcl/kcl_drm_dp_helper.h +++ b/include/kcl/kcl_drm_dp_helper.h @@ -108,10 +108,6 @@ #define DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1 0xf0020 /* 1.4a */ #endif -#if !defined(DP_TRAINING_PATTERN_SET_PHY_REPEATER1) -#define DP_TRAINING_PATTERN_SET_PHY_REPEATER1 0xf0010 /* 1.3 */ -#endif - #if !defined(DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT) #define DP_PHY_REPEATER_EXTENDED_WAIT_TIMEOUT 0xf0005 /* 1.4a */ #endif @@ -162,4 +158,53 @@ #define DP_DSC_THROUGHPUT_MODE_0_UNSUPPORTED DP_DSC_THROUGHPUT_MODE_0_UPSUPPORTED #endif +/* v5.9-rc4-979-g9782f52ab5d6 + * drm/dp: Add LTTPR helpers + */ +#ifndef DP_TRAINING_PATTERN_SET_PHY_REPEATER + +enum drm_dp_phy { + DP_PHY_DPRX, + + DP_PHY_LTTPR1, + DP_PHY_LTTPR2, + DP_PHY_LTTPR3, + DP_PHY_LTTPR4, + DP_PHY_LTTPR5, + DP_PHY_LTTPR6, + DP_PHY_LTTPR7, + DP_PHY_LTTPR8, + + DP_MAX_LTTPR_COUNT = DP_PHY_LTTPR8, +}; + +#define DP_PHY_LTTPR(i) (DP_PHY_LTTPR1 + (i)) +#define __DP_LTTPR1_BASE 0xf0010 /* 1.3 */ +#define __DP_LTTPR2_BASE 0xf0060 /* 1.3 */ +#define DP_LTTPR_BASE(dp_phy) \ + (__DP_LTTPR1_BASE + (__DP_LTTPR2_BASE - __DP_LTTPR1_BASE) * \ + ((dp_phy) - DP_PHY_LTTPR1)) +#define DP_LTTPR_REG(dp_phy, lttpr1_reg) \ + (DP_LTTPR_BASE(dp_phy) - DP_LTTPR_BASE(DP_PHY_LTTPR1) + (lttpr1_reg)) +#define DP_TRAINING_PATTERN_SET_PHY_REPEATER(dp_phy) \ + DP_LTTPR_REG(dp_phy, DP_TRAINING_PATTERN_SET_PHY_REPEATER1) +#endif + +#ifndef DP_FEC_STATUS_PHY_REPEATER + +#define __DP_FEC1_BASE 0xf0290 /* 1.4 */ +#define __DP_FEC2_BASE 0xf0298 /* 1.4 */ +#define DP_FEC_BASE(dp_phy) \ + (__DP_FEC1_BASE + ((__DP_FEC2_BASE - __DP_FEC1_BASE) * \ + ((dp_phy) - DP_PHY_LTTPR1))) +#define DP_FEC_REG(dp_phy, fec1_reg) \ + (DP_FEC_BASE(dp_phy) - DP_FEC_BASE(DP_PHY_LTTPR1) + fec1_reg) +#define DP_FEC_STATUS_PHY_REPEATER1 0xf0290 /* 1.4 */ +#define DP_FEC_STATUS_PHY_REPEATER(dp_phy) \ + DP_FEC_REG(dp_phy, DP_FEC_STATUS_PHY_REPEATER1) +#define DP_LTTPR_MAX_ADD 0xf02ff /* 1.4 */ +#define DP_DPCD_MAX_ADD 0xfffff /* 1.4 */ + +#endif + #endif /* _KCL_DRM_DP_HELPER_H_ */ From 60a3cd2287701347de17c37b0be8eb6ea97de0a9 Mon Sep 17 00:00:00 2001 From: Eric Huang Date: Thu, 17 Jun 2021 10:15:18 -0400 Subject: [PATCH 0453/1868] drm/amdkfd: Set p2plink non-coherent in topology Fix non-coherent bit of p2plink properties flag which always is 0. Signed-off-by: Eric Huang Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index 3472cd061838a..420ec88344ffa 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -1469,6 +1469,7 @@ static void kfd_fill_iolink_non_crat_info(struct kfd_topology_device *dev) inbound_link->flags = CRAT_IOLINK_FLAGS_ENABLED; kfd_set_iolink_no_atomics(peer_dev, dev, inbound_link); + kfd_set_iolink_non_coherent(peer_dev, link, inbound_link); } } } From c96fd97c13341630141ecf9c3942622953c0ad9b Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 18 Jun 2021 14:02:34 +0800 Subject: [PATCH 0454/1868] drm/amdkcl: fix kgd2kfd_resume() prototype in dkms branch Signed-off-by: Flora Cui Reported-by: chen gong Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index da2764c3aae93..971cfc89db018 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -496,7 +496,7 @@ static inline void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm) { } -static inline int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm) +static inline int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm, bool sync) { return 0; } From 27f0d10363ac9aaeaab532f7585ac094c2cdeb1f Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Fri, 18 Jun 2021 13:14:46 +0800 Subject: [PATCH 0455/1868] drm/amdkcl: fake the sysfs_emit_at This is caused by d0d2e18213f7 "amdgpu/pm: replaced snprintf usage in amdgpu_pm.c with sysfs_emit" v5.11-3838-gd0d2e18213f7 Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/kcl_sysfs_emit.c | 29 +++++++++++++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 2 +- drivers/gpu/drm/amd/dkms/m4/sysfs_emit.m4 | 9 ++++--- include/kcl/kcl_sysfs_emit.h | 10 +++++++ 4 files changed, 46 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_sysfs_emit.c b/drivers/gpu/drm/amd/amdkcl/kcl_sysfs_emit.c index 798745cbfff91..0b23918cc8486 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_sysfs_emit.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_sysfs_emit.c @@ -29,4 +29,33 @@ int sysfs_emit(char *buf, const char *fmt, ...) return len; } EXPORT_SYMBOL_GPL(sysfs_emit); + +/** + * sysfs_emit_at - scnprintf equivalent, aware of PAGE_SIZE buffer. + * @buf: start of PAGE_SIZE buffer. + * @at: offset in @buf to start write in bytes + * @at must be >= 0 && < PAGE_SIZE + * @fmt: format + * @...: optional arguments to @fmt + * + * + * Returns number of characters written starting at &@buf[@at]. + */ +int sysfs_emit_at(char *buf, int at, const char *fmt, ...) +{ + va_list args; + int len; + + if (WARN(!buf || offset_in_page(buf) || at < 0 || at >= PAGE_SIZE, + "invalid sysfs_emit_at: buf:%p at:%d\n", buf, at)) + return 0; + + va_start(args, fmt); + len = vscnprintf(buf + at, PAGE_SIZE - at, fmt, args); + va_end(args); + + return len; +} +EXPORT_SYMBOL_GPL(sysfs_emit_at); + #endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 020d10ba36675..92e367643dc75 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -918,7 +918,7 @@ /* zone->managed_pages is available */ /* #undef HAVE_STRUCT_ZONE_MANAGED_PAGES */ -/* sysfs_emit() is available */ +/* sysfs_emit() and sysfs_emit_at are available */ #define HAVE_SYSFS_EMIT 1 /* timer_setup() is available */ diff --git a/drivers/gpu/drm/amd/dkms/m4/sysfs_emit.m4 b/drivers/gpu/drm/amd/dkms/m4/sysfs_emit.m4 index e9f403134af83..c1dc1717cc324 100644 --- a/drivers/gpu/drm/amd/dkms/m4/sysfs_emit.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/sysfs_emit.m4 @@ -1,13 +1,16 @@ dnl # dnl # commit: v5.9-rc5-23-g2efc459d06f1 -dnl # sysfs: Add sysfs_emit and sysfs_emit_at +dnl # sysfs: Add sysfs_emit and sysfs_emit_at dnl # to format sysfs output AC_DEFUN([AC_AMDGPU_SYSFS_EMIT], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([sysfs_emit], + AC_KERNEL_CHECK_SYMBOL_EXPORT([sysfs_emit sysfs_emit_at], [fs/sysfs/file.c], [ AC_DEFINE(HAVE_SYSFS_EMIT, 1, - [sysfs_emit() is available]) + [sysfs_emit() and sysfs_emit_at() are available]) ]) ]) ]) + + +) diff --git a/include/kcl/kcl_sysfs_emit.h b/include/kcl/kcl_sysfs_emit.h index ab87e74f817ff..381265a29b7e1 100644 --- a/include/kcl/kcl_sysfs_emit.h +++ b/include/kcl/kcl_sysfs_emit.h @@ -15,11 +15,21 @@ #ifdef CONFIG_SYSFS __printf(2, 3) int sysfs_emit(char *buf, const char *fmt, ...); + +__printf(3, 4) +int sysfs_emit_at(char *buf, int at, const char *fmt, ...); + #else __printf(2, 3) static inline int sysfs_emit(char *buf, const char *fmt, ...) { return 0; } + +__printf(3, 4) +static inline int sysfs_emit_at(char *buf, int at, const char *fmt, ...) +{ + return 0; +} #endif #endif From 6fc154cbd5503ecf8684467d8f8dd70e8479d49c Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 21 Jun 2021 14:38:26 +0800 Subject: [PATCH 0456/1868] drm/amdkcl: update test for ttm_sg_tt_init for kernel with CONFIG_DRM_TTM disabled Signed-off-by: Flora Cui Reviewed-by: Shiwu Zhang --- drivers/gpu/drm/amd/dkms/m4/ttm_sg_tt_init.m4 | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/ttm_sg_tt_init.m4 b/drivers/gpu/drm/amd/dkms/m4/ttm_sg_tt_init.m4 index 9bfcadc878e3c..5cbf835eaf401 100644 --- a/drivers/gpu/drm/amd/dkms/m4/ttm_sg_tt_init.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/ttm_sg_tt_init.m4 @@ -1,10 +1,10 @@ dnl # -dnl # v4.16-rc1-1232-g75a57669cbc8 -dnl # drm/ttm: add ttm_sg_tt_init +dnl # v4.16-rc1-1232-g75a57669cbc8 drm/ttm: add ttm_sg_tt_init +dnl # v4.16-rc1-409-g186ca446aea1 drm/prime: make the pages array optional for drm_prime_sg_to_page_addr_arrays dnl # AC_DEFUN([AC_AMDGPU_TTM_SG_TT_INIT], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([ttm_sg_tt_init], [drivers/gpu/drm/ttm/ttm_tt.c], [ + AS_IF([grep -q ttm_sg_tt_init $LINUX/include/drm/ttm/ttm_tt.h > /dev/null 2>&1], [ AC_DEFINE(HAVE_TTM_SG_TT_INIT, 1, [ttm_sg_tt_init() is available]) ]) ]) From 5e760b96264bcfe92e74de9db204ab47922d91fa Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 25 Jun 2021 13:00:25 +0800 Subject: [PATCH 0457/1868] drm/amdkcl: fix for kernel_write() prototype change Signed-off-by: Flora Cui Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- .../gpu/drm/amd/amdkcl/kcl_fs_read_write.c | 27 +++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 2 +- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/kernel_write.m4 | 16 +++++++++++ include/kcl/backport/kcl_fs.h | 12 +++++++++ include/kcl/kcl_fs.h | 6 +++++ 8 files changed, 67 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_fs_read_write.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/kernel_write.m4 create mode 100644 include/kcl/backport/kcl_fs.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index f95c0c73adb27..662dbafdd44d2 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -11,7 +11,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_drm_fb.o kcl_drm_print.o kcl_fbmem.o \ kcl_drm_crtc.o kcl_drm_connector.o kcl_drm_atomic_helper.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o kcl_ftrace.o \ - kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_drm_aperture.o + kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_fs_read_write.o kcl_drm_aperture.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fs_read_write.c b/drivers/gpu/drm/amd/amdkcl/kcl_fs_read_write.c new file mode 100644 index 0000000000000..e45c10eabc006 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fs_read_write.c @@ -0,0 +1,27 @@ +/* + * linux/fs/read_write.c + * + * Copyright (C) 1991, 1992 Linus Torvalds + */ +#include +#include + +/* Copied from v4.13-rc7-6-ge13ec939e96b:fs/read_write.c */ +#ifndef HAVE_KERNEL_WRITE_PPOS +ssize_t _kcl_kernel_write(struct file *file, const void *buf, size_t count, + loff_t *pos) +{ + mm_segment_t old_fs; + ssize_t res; + + old_fs = get_fs(); + set_fs(get_ds()); + /* The cast to a user pointer is valid due to the set_fs() */ + res = vfs_write(file, (__force const char __user *)buf, count, pos); + set_fs(old_fs); + + return res; +} +EXPORT_SYMBOL(_kcl_kernel_write); +#endif + diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 9e7bee1e97075..810a40bc1d1d6 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -20,7 +20,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 92e367643dc75..ff3331748b748 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -636,6 +636,9 @@ /* kallsyms_lookup_name is available */ /* #undef HAVE_KALLSYMS_LOOKUP_NAME */ +/* kernel_write() take arg type of position as pointer */ +#define HAVE_KERNEL_WRITE_PPOS 1 + /* kref_read() function is available */ #define HAVE_KREF_READ 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index d5c9005a84637..61fe97c920c80 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -147,6 +147,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_CHECK_SMCA_UMC_V2 AC_AMDGPU_PXM_TO_NODE AC_AMDGPU_ACPI_SRAT_GENERIC_AFFINITY + AC_AMDGPU_KERNEL_WRITE AC_AMDGPU_DRM_MEMCPY_FROM_WC AC_AMDGPU_IS_COW_MAPPING AC_AMDGPU_VGA_REMOVE_VGACON diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel_write.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel_write.m4 new file mode 100644 index 0000000000000..3fdd8e902d61e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/kernel_write.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v4.13-rc7-6-ge13ec939e96b +dnl # fs: fix kernel_write prototype +dnl # +AC_DEFUN([AC_AMDGPU_KERNEL_WRITE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + kernel_write(NULL, NULL, 0, NULL); + ], [ + AC_DEFINE(HAVE_KERNEL_WRITE_PPOS, 1, + [kernel_write() take arg type of position as pointer]) + ]) + ]) +]) diff --git a/include/kcl/backport/kcl_fs.h b/include/kcl/backport/kcl_fs.h new file mode 100644 index 0000000000000..200c92cd0f82f --- /dev/null +++ b/include/kcl/backport/kcl_fs.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _KCL_BACKPORT_KCL_FS_H +#define _KCL_BACKPORT_KCL_FS_H + +#include +#include + +#ifndef HAVE_KERNEL_WRITE_PPOS +#define kernel_write _kcl_kernel_write +#endif + +#endif diff --git a/include/kcl/kcl_fs.h b/include/kcl/kcl_fs.h index 4a4c208d833e0..633a6edfd8f17 100644 --- a/include/kcl/kcl_fs.h +++ b/include/kcl/kcl_fs.h @@ -19,4 +19,10 @@ static inline long compat_ptr_ioctl(struct file *file, unsigned int cmd, #define compat_ptr_ioctl NULL #endif /* CONFIG_COMPAT */ #endif /* HAVE_COMPAT_PTR_IOCTL */ + +#ifndef HAVE_KERNEL_WRITE_PPOS +ssize_t _kcl_kernel_write(struct file *file, const void *buf, size_t count, + loff_t *pos); +#endif + #endif From ce646ed826b200af0c67e3a6b793657e3d3d74ce Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 6 Jul 2021 15:33:05 +0800 Subject: [PATCH 0458/1868] drm/amdkcl: not use xarray for storing pasid in legacy os This is caused by 9538d0fc5286 "drm/amdgpu: use xarray for storing pasid in vm" v5.11-3985-g9538d0fc5286 Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 45 +++++++++++++++++++++++- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 5 +++ drivers/gpu/drm/amd/dkms/config/config.h | 3 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/xarray.m4 | 17 +++++++++ 5 files changed, 70 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/xarray.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 20ff637055e85..227418abede5f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -140,8 +140,9 @@ struct amdgpu_vm_tlb_seq_struct { int amdgpu_vm_set_pasid(struct amdgpu_device *adev, struct amdgpu_vm *vm, u32 pasid) { - int r; + int r = 0; +#ifdef HAVE_STRUCT_XARRAY if (vm->pasid == pasid) return 0; @@ -161,7 +162,21 @@ int amdgpu_vm_set_pasid(struct amdgpu_device *adev, struct amdgpu_vm *vm, vm->pasid = pasid; } +#else + unsigned long flags; + spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); + if (pasid) { + r = idr_alloc(&adev->vm_manager.pasid_idr, vm, pasid, pasid + 1, + GFP_ATOMIC); + } else if (vm->pasid) { + idr_remove(&adev->vm_manager.pasid_idr, vm->pasid); + } + spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); + if (r < 0) + return r; + vm->pasid = pasid; +#endif return 0; } @@ -2735,7 +2750,12 @@ void amdgpu_vm_manager_init(struct amdgpu_device *adev) adev->vm_manager.vm_update_mode = 0; #endif +#ifdef HAVE_STRUCT_XARRAY xa_init_flags(&adev->vm_manager.pasids, XA_FLAGS_LOCK_IRQ); +#else + idr_init(&adev->vm_manager.pasid_idr); + spin_lock_init(&adev->vm_manager.pasid_lock); +#endif } /** @@ -2747,8 +2767,13 @@ void amdgpu_vm_manager_init(struct amdgpu_device *adev) */ void amdgpu_vm_manager_fini(struct amdgpu_device *adev) { +#ifdef HAVE_STRUCT_XARRAY WARN_ON(!xa_empty(&adev->vm_manager.pasids)); xa_destroy(&adev->vm_manager.pasids); +#else + WARN_ON(!idr_is_empty(&adev->vm_manager.pasid_idr)); + idr_destroy(&adev->vm_manager.pasid_idr); +#endif amdgpu_vmid_mgr_fini(adev); } @@ -2819,15 +2844,24 @@ bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid, struct amdgpu_vm *vm; int r; +#ifdef HAVE_STRUCT_XARRAY xa_lock_irqsave(&adev->vm_manager.pasids, irqflags); vm = xa_load(&adev->vm_manager.pasids, pasid); +#else + spin_lock_irqsave(&adev->vm_manager.pasid_lock, irqflags); + vm = idr_find(&adev->vm_manager.pasid_idr, pasid); +#endif if (vm) { root = amdgpu_bo_ref(vm->root.bo); is_compute_context = vm->is_compute_context; } else { root = NULL; } +#ifdef HAVE_STRUCT_XARRAY xa_unlock_irqrestore(&adev->vm_manager.pasids, irqflags); +#else + spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, irqflags); +#endif if (!root) return false; @@ -2845,11 +2879,20 @@ bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid, goto error_unref; /* Double check that the VM still exists */ +#ifdef HAVE_STRUCT_XARRAY xa_lock_irqsave(&adev->vm_manager.pasids, irqflags); vm = xa_load(&adev->vm_manager.pasids, pasid); +#else + spin_lock_irqsave(&adev->vm_manager.pasid_lock, irqflags); + vm = idr_find(&adev->vm_manager.pasid_idr, pasid); +#endif if (vm && vm->root.bo != root) vm = NULL; +#ifdef HAVE_STRUCT_XARRAY xa_unlock_irqrestore(&adev->vm_manager.pasids, irqflags); +#else + spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, irqflags); +#endif if (!vm) goto error_unlock; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h index bb1a31fe1d3be..082db0f3fbaf9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h @@ -460,7 +460,12 @@ struct amdgpu_vm_manager { /* PASID to VM mapping, will be used in interrupt context to * look up VM of a page fault */ +#ifdef HAVE_STRUCT_XARRAY struct xarray pasids; +#else + struct idr pasid_idr; + spinlock_t pasid_lock; +#endif /* Global registration of recent page fault information */ struct amdgpu_vm_fault_info fault_info; }; diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index ff3331748b748..bce21674fb244 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -918,6 +918,9 @@ /* drm_plane_helper_funcs->prepare_fb() wants p,p arg */ #define HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_PREPARE_FB_PP 1 +/* struct xarray is available */ +#define HAVE_STRUCT_XARRAY 1 + /* zone->managed_pages is available */ /* #undef HAVE_STRUCT_ZONE_MANAGED_PAGES */ diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 61fe97c920c80..e639bda13d0bb 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -148,6 +148,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_PXM_TO_NODE AC_AMDGPU_ACPI_SRAT_GENERIC_AFFINITY AC_AMDGPU_KERNEL_WRITE + AC_AMDGPU_STRUCT_XARRAY AC_AMDGPU_DRM_MEMCPY_FROM_WC AC_AMDGPU_IS_COW_MAPPING AC_AMDGPU_VGA_REMOVE_VGACON diff --git a/drivers/gpu/drm/amd/dkms/m4/xarray.m4 b/drivers/gpu/drm/amd/dkms/m4/xarray.m4 new file mode 100644 index 0000000000000..bfe64c548f1c1 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/xarray.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # v4.19-rc5-244-gf8d5d0cc145c +dnl # xarray: Add definition of struct xarray +dnl # +AC_DEFUN([AC_AMDGPU_STRUCT_XARRAY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct xarray x; + xa_init(&x); + ], [ + AC_DEFINE(HAVE_STRUCT_XARRAY, 1, + [struct xarray is available]) + ]) + ]) +]) From cbdee207be8f9572ce66be0229f1e8fe8cb029c9 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 6 Jul 2021 15:44:07 +0800 Subject: [PATCH 0459/1868] drm/amdkcl: add I2C_AQ_NO_ZERO_LEN macro This is caused by b79271766c50 "drm/amdgpu: The I2C IP doesn't support 0 writes/reads" v5.11-3990-gb79271766c50 Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- include/kcl/kcl_i2c.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/include/kcl/kcl_i2c.h b/include/kcl/kcl_i2c.h index 66b3195eff49d..2e7f36acdeadc 100644 --- a/include/kcl/kcl_i2c.h +++ b/include/kcl/kcl_i2c.h @@ -23,4 +23,11 @@ i2c_new_client_device(struct i2c_adapter *adap, struct i2c_board_info const *inf } #endif +#ifndef I2C_AQ_NO_ZERO_LEN +#define I2C_AQ_NO_ZERO_LEN_READ BIT(5) +#define I2C_AQ_NO_ZERO_LEN_WRITE BIT(6) +#define I2C_AQ_NO_ZERO_LEN (I2C_AQ_NO_ZERO_LEN_READ | I2C_AQ_NO_ZERO_LEN_WRITE) +#endif + + #endif From c9cac95af86a91f98a059cb62ebdb575e46c90d2 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Fri, 25 Jun 2021 16:50:03 +0800 Subject: [PATCH 0460/1868] drm/amdkcl: wrap the coder under CONFIG_DRM_AMD_DC_DSC_SUPPORT This is caused by b37360fb390e "drm/amdgpu/display: fold DRM_AMD_DC_DCN3_1 into DRM_AMD_DC_DCN" v5.11-3882-gb37360fb390e Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- .../display/dc/dio/dcn31/dcn31_dio_link_encoder.c | 2 ++ .../gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c | 4 ++++ .../gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c | 2 ++ .../gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c | 2 ++ .../amd/display/dc/resource/dcn31/dcn31_resource.c | 12 ++++++++++++ 5 files changed, 22 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c index b2cea59ba5d49..994b5ab885bb7 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c @@ -247,7 +247,9 @@ void enc31_hw_init(struct link_encoder *enc) } static const struct link_encoder_funcs dcn31_link_enc_funcs = { +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .read_state = link_enc2_read_state, +#endif .validate_output_with_stream = dcn30_link_encoder_validate_output_with_stream, .hw_init = enc31_hw_init, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c index 3d4b31bd99469..a4dcf7d95c5b6 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c @@ -276,6 +276,7 @@ void dcn31_init_hw(struct dc *dc) dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void dcn31_dsc_pg_control( struct dce_hwseq *hws, unsigned int dsc_inst, @@ -338,6 +339,7 @@ void dcn31_dsc_pg_control( } } +#endif void dcn31_enable_power_gating_plane( @@ -517,9 +519,11 @@ static void dcn31_reset_back_end_for_pipe( dc->hwss.set_abm_immediate_disable(pipe_ctx); +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT pipe_ctx->stream_res.tg->funcs->set_dsc_config( pipe_ctx->stream_res.tg, OPTC_DSC_DISABLED, 0, 0); +#endif pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg); pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false); if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c index b57dd45611f23..cb208e2405bca 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c @@ -138,7 +138,9 @@ static const struct hwseq_private_funcs dcn31_private_funcs = { .hubp_pg_control = dcn31_hubp_pg_control, .program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree, .update_odm = dcn20_update_odm, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .dsc_pg_control = dcn31_dsc_pg_control, +#endif .set_hdr_multiplier = dcn10_set_hdr_multiplier, .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high, .wait_for_blank_complete = dcn20_wait_for_blank_complete, diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c index 4b6446ed4ce47..5822ceff727ab 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c @@ -289,7 +289,9 @@ static struct timing_generator_funcs dcn31_tg_funcs = { .setup_global_swap_lock = NULL, .get_crc = optc1_get_crc, .configure_crc = optc2_configure_crc, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .set_dsc_config = optc3_set_dsc_config, +#endif .get_dsc_status = optc2_get_dsc_status, .set_dwb_source = NULL, .set_odm_bypass = optc3_set_odm_bypass, diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c index ac8cb20e2e3b6..bd452d8d5f4aa 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c @@ -563,6 +563,7 @@ static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) }; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #define dsc_regsDCN20(id)\ [id] = {\ DSC_REG_LIST_DCN20(id)\ @@ -581,6 +582,7 @@ static const struct dcn20_dsc_shift dsc_shift = { static const struct dcn20_dsc_mask dsc_mask = { DSC_REG_LIST_SH_MASK_DCN20(_MASK) }; +#endif static const struct dcn30_mpc_registers mpc_regs = { MPC_REG_LIST_DCN3_0(0), @@ -824,7 +826,9 @@ static const struct resource_caps res_cap_dcn31 = { .num_ddc = 5, .num_vmid = 16, .num_mpc_3dlut = 2, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .num_dsc = 3, +#endif }; static const struct dc_plane_cap plane_cap = { @@ -1383,10 +1387,12 @@ static void dcn31_resource_destruct(struct dcn31_resource_pool *pool) } } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } +#endif if (pool->base.mpc != NULL) { kfree(TO_DCN20_MPC(pool->base.mpc)); @@ -1561,6 +1567,7 @@ static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool * return true; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static struct display_stream_compressor *dcn31_dsc_create( struct dc_context *ctx, uint32_t inst) { @@ -1575,6 +1582,7 @@ static struct display_stream_compressor *dcn31_dsc_create( dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); return &dsc->base; } +#endif static void dcn31_destroy_resource_pool(struct resource_pool **pool) { @@ -1833,7 +1841,9 @@ static struct resource_funcs dcn31_res_pool_funcs = { .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, .add_stream_to_ctx = dcn30_add_stream_to_ctx, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, +#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .populate_dml_writeback_from_context = dcn31_populate_dml_writeback_from_context, .set_mcif_arb_params = dcn31_set_mcif_arb_params, @@ -2127,6 +2137,7 @@ static bool dcn31_resource_construct( goto create_fail; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { pool->base.dscs[i] = dcn31_dsc_create(ctx, i); if (pool->base.dscs[i] == NULL) { @@ -2135,6 +2146,7 @@ static bool dcn31_resource_construct( goto create_fail; } } +#endif /* DWB and MMHUBBUB */ if (!dcn31_dwbc_create(ctx, &pool->base)) { From 488a8cb53999fa3b04b492ea7b06ab913cd16871 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Thu, 15 Jul 2021 10:11:26 -0400 Subject: [PATCH 0461/1868] drm/amdkcl: fix get list of supported ASIC Use amd_asic_type.h header in DKMS tree instead of system kernel tree to search for supported ASIC. Change-Id: Ie20e9670cecdea28616c325d983f99fb0155b616 Signed-off-by: Slava Grigorev --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index e639bda13d0bb..acdb4cb610885 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -588,7 +588,7 @@ AC_DEFUN([AC_KERNEL_SUPPORTED_AMD_CHIPS], [ exit; print $[1]; } - }' $LINUX/include/drm/amd_asic_type.h) + }' ../../include/drm/amd_asic_type.h) for i in $chips; do $as_echo "#define HAVE_$i" >>config/config-amd-chips.h From 53825aa240a7a1b7ffc892b46b6e6cdb2770e34d Mon Sep 17 00:00:00 2001 From: Jonathan Kim Date: Mon, 17 May 2021 19:48:51 -0400 Subject: [PATCH 0462/1868] drm/amdkfd: synchronize runtime enable with the debugger If the debugger is attached, raise an EC_PROCESS_RUNTIME_ENABLE/DISABLE event on runtime enable/disable and block until the debugger sends the process event to unblock. Signed-off-by: Jonathan Kim Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 1af4c8e670acf..6e39058b90539 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -39,6 +39,7 @@ #include #include #include +#include /* amdkcl: this header file is included in kcl_device_cgroup.h #include */ #include From e25b8422cc525b8f25724ba1efb0974413ba0adb Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 28 Jun 2021 12:16:21 +0800 Subject: [PATCH 0463/1868] drm/amdkcl: Fix compile warning by include header file Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- include/kcl/kcl_ftrace.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/kcl/kcl_ftrace.h b/include/kcl/kcl_ftrace.h index de98a0a5f345e..ae106eff452b0 100644 --- a/include/kcl/kcl_ftrace.h +++ b/include/kcl/kcl_ftrace.h @@ -2,6 +2,7 @@ #ifndef AMDKCL_FTRACE_H #define AMDKCL_FTRACE_H +#include /* Copied from v3.19-rc1-6-g6ea22486ba46 include/trace/ftrace.h */ #if !defined(HAVE___PRINT_ARRAY) extern const char * ftrace_print_array_seq(struct trace_seq *p, const void *buf, int count, From 6ac1aeb26b20862ef14a32f997f5347c00fef756 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 28 Jun 2021 12:28:49 +0800 Subject: [PATCH 0464/1868] drm/amdkcl: Add const cast to adapt function prototype and Fix compile warning Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- include/kcl/kcl_drm_print.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index c2dac790ba1c8..6dea17070b5de 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -68,9 +68,9 @@ static inline void drm_mm_print(const struct drm_mm *mm, struct drm_printer *p) { #ifndef HAVE_DRM_DRM_PRINT_H - drm_mm_debug_table(mm, p->prefix); + drm_mm_debug_table((struct drm_mm *)mm, p->prefix); #else - drm_mm_debug_table(mm, "no prefix"); + drm_mm_debug_table((struct drm_mm *)mm, "no prefix"); #endif } #endif From a26ebfc94679ca9bf6d731e0545077c7d9086678 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 28 Jun 2021 13:47:37 +0800 Subject: [PATCH 0465/1868] amd/drmkcl: Fix redefined dma_fence_default_wait macro Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- include/kcl/backport/kcl_fence_backport.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/kcl/backport/kcl_fence_backport.h b/include/kcl/backport/kcl_fence_backport.h index 022951286bb7d..7e3e1ab42138b 100644 --- a/include/kcl/backport/kcl_fence_backport.h +++ b/include/kcl/backport/kcl_fence_backport.h @@ -19,6 +19,11 @@ * dma-buf/fence: revert "don't wait when specified timeout is zero" (v2) */ #ifdef AMDKCL_FENCE_DEFAULT_WAIT_TIMEOUT + +#ifdef dma_fence_default_wait +#undef dma_fence_default_wait +#endif + #define dma_fence_default_wait _kcl_fence_default_wait #define dma_fence_wait_timeout _kcl_fence_wait_timeout #endif From be96f2981bcb6582e55d8725f526f5ccbb5e6d0e Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 28 Jun 2021 13:47:19 +0800 Subject: [PATCH 0466/1868] drm/amdkcl: Remove unused local variable Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c index 58beb9fcedf38..c0f145df309d3 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_atomic_helper.c @@ -71,15 +71,15 @@ EXPORT_SYMBOL(__drm_atomic_helper_crtc_reset); */ void drm_atomic_helper_calc_timestamping_constants(struct drm_atomic_state *state) { - struct drm_device *dev = state->dev; struct drm_crtc_state *new_crtc_state; struct drm_crtc *crtc; - int i; #if !defined(for_each_new_crtc_in_state) + struct drm_device *dev = state->dev; list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { new_crtc_state = crtc->state; #else + int i; for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { #endif if (new_crtc_state->enable) From 05c720fc3b09230ef20552ab0a41c6fa4d3fb0af Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 28 Jun 2021 16:02:19 +0800 Subject: [PATCH 0467/1868] drm/amdkcl: wrap function dma_fence_test_signaled_any under the macro Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/kcl_fence.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fence.c b/drivers/gpu/drm/amd/amdkcl/kcl_fence.c index ed889c91b8dd4..1376705d31822 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_fence.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fence.c @@ -26,6 +26,7 @@ #include "kcl_fence_trace.h" /* Copied from drivers/dma-buf/dma-fence.c */ +#if defined(AMDKCL_FENCE_DEFAULT_WAIT_TIMEOUT) || defined(AMDKCL_FENCE_WAIT_ANY_TIMEOUT) static bool dma_fence_test_signaled_any(struct dma_fence **fences, uint32_t count, uint32_t *idx) @@ -42,6 +43,7 @@ dma_fence_test_signaled_any(struct dma_fence **fences, uint32_t count, } return false; } +#endif struct default_wait_cb { struct dma_fence_cb base; From 2f52ec3bf724ddf75f2df24e1b285cbc9dbc8028 Mon Sep 17 00:00:00 2001 From: Solomon Chiu Date: Mon, 19 Jul 2021 17:34:52 +0800 Subject: [PATCH 0468/1868] drm/amd/display: Add common rates of vide mode matching for freesync_video_mode [Why] The condition checking of is_freesync_video_mode() is not enuough to tell whether freesync video mode or not. [How] Add common rates of video mode matching after origin condition matching. Signed-off-by: Solomon Chiu Change-Id: I0cf53fdf54ca8290d71f7f470e9a39ff43379850 --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 49 ++++++++++++++++--- 1 file changed, 41 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 3665279d0d23b..b234d5a5724dd 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -6485,31 +6485,64 @@ get_highest_refresh_rate_mode(struct amdgpu_dm_connector *aconnector, return m_pref; } +/* Standard FPS values + * + * 23.976 - TV/NTSC + * 24 - Cinema + * 25 - TV/PAL + * 29.97 - TV/NTSC + * 30 - TV/NTSC + * 48 - Cinema HFR + * 50 - TV/PAL + * 60 - Commonly used + * 48,72,96 - Multiples of 24 + */ +const uint32_t common_rates[] = { 23976, 24000, 25000, 29970, 30000, + 48000, 50000, 60000, 72000, 96000 }; + + static bool is_freesync_video_mode(const struct drm_display_mode *mode, struct amdgpu_dm_connector *aconnector) { struct drm_display_mode *high_mode; int timing_diff; + int i; high_mode = get_highest_refresh_rate_mode(aconnector, false); if (!high_mode || !mode) return false; - timing_diff = high_mode->vtotal - mode->vtotal; - if (high_mode->clock == 0 || high_mode->clock != mode->clock || - high_mode->hdisplay != mode->hdisplay || - high_mode->vdisplay != mode->vdisplay || - high_mode->hsync_start != mode->hsync_start || - high_mode->hsync_end != mode->hsync_end || + high_mode->hdisplay != mode->hdisplay || + high_mode->vdisplay != mode->vdisplay || + high_mode->hsync_start != mode->hsync_start || + high_mode->hsync_end != mode->hsync_end || high_mode->htotal != mode->htotal || high_mode->hskew != mode->hskew || high_mode->vscan != mode->vscan || high_mode->vsync_start - mode->vsync_start != timing_diff || high_mode->vsync_end - mode->vsync_end != timing_diff) return false; - else - return true; + + for (i = 0; i < ARRAY_SIZE(common_rates); i++) { + uint64_t target_vtotal, target_vtotal_diff; + uint64_t num, den; + + if (drm_mode_vrefresh(high_mode) * 1000 < common_rates[i]) + continue; + if (common_rates[i] < aconnector->min_vfreq * 1000 || + common_rates[i] > aconnector->max_vfreq * 1000) + continue; + num = (unsigned long long)high_mode->clock * 1000 * 1000; + den = common_rates[i] * (unsigned long long)high_mode->htotal; + target_vtotal = div_u64(num, den); + target_vtotal_diff = target_vtotal - high_mode->vtotal; + + if ((mode->vtotal - target_vtotal_diff) == high_mode->vtotal) + return true; + } + + return false; } #if defined(CONFIG_DRM_AMD_DC_FP) From 760a893b290a85ebe8661e846cf785c759e30a9c Mon Sep 17 00:00:00 2001 From: Philip Yang Date: Tue, 20 Jul 2021 22:10:49 -0400 Subject: [PATCH 0469/1868] drm/amdkfd: IPC export and import memory alloc flags Support query pointer info memory alloc flags, ex CoarseGrain, for shared memory by IPC. App pass memory alloc flags to export handle ioctl, to save memory alloc flags to ipc object, import handle ioctl get ipc object and pass memory alloc flags back to app which could be different process. Keep import export handle ioctl interface, rename unused _u32 pad field to flags. Signed-off-by: Philip Yang Reviewed-by: Harish Kasiviswanathan --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 3 ++- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 5 +++-- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 5 +++-- drivers/gpu/drm/amd/amdkfd/kfd_ipc.c | 12 ++++++++---- drivers/gpu/drm/amd/amdkfd/kfd_ipc.h | 9 ++++++--- include/uapi/linux/kfd_ioctl.h | 6 +++--- 6 files changed, 25 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index 971cfc89db018..3c30ac61323e5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -363,7 +363,8 @@ int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_mem *mem, struct dma_buf **dmabuf); int amdgpu_amdkfd_gpuvm_export_ipc_obj(struct kgd_dev *kgd, void *vm, struct kgd_mem *mem, - struct kfd_ipc_obj **ipc_obj); + struct kfd_ipc_obj **ipc_obj, + uint32_t flags); void amdgpu_amdkfd_debug_mem_fence(struct amdgpu_device *adev); int amdgpu_amdkfd_get_tile_config(struct amdgpu_device *adev, struct tile_config *config); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 57873d77d8a4d..a4b50a5210b49 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -2798,7 +2798,8 @@ int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_mem *mem, int amdgpu_amdkfd_gpuvm_export_ipc_obj(struct kgd_dev *kgd, void *vm, struct kgd_mem *mem, - struct kfd_ipc_obj **ipc_obj) + struct kfd_ipc_obj **ipc_obj, + uint32_t flags) { struct amdgpu_device *adev = NULL; struct dma_buf *dmabuf; @@ -2821,7 +2822,7 @@ int amdgpu_amdkfd_gpuvm_export_ipc_obj(struct kgd_dev *kgd, void *vm, goto unlock_out; } - r = kfd_ipc_store_insert(dmabuf, &mem->ipc_obj); + r = kfd_ipc_store_insert(dmabuf, &mem->ipc_obj, flags); if (r) dma_buf_put(dmabuf); else diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 1b4b393f8e521..01e4bbb539f57 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1654,7 +1654,8 @@ static int kfd_ioctl_ipc_export_handle(struct file *filep, if (!dev) return -EINVAL; - r = kfd_ipc_export_as_handle(dev, p, args->handle, args->share_handle); + r = kfd_ipc_export_as_handle(dev, p, args->handle, args->share_handle, + args->flags); if (r) pr_err("Failed to export IPC handle\n"); @@ -1675,7 +1676,7 @@ static int kfd_ioctl_ipc_import_handle(struct file *filep, r = kfd_ipc_import_handle(dev, p, args->gpu_id, args->share_handle, args->va_addr, &args->handle, - &args->mmap_offset); + &args->mmap_offset, &args->flags); if (r) pr_err("Failed to import IPC handle\n"); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c index 88ab20909ce39..b5d89265d3c2d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c @@ -41,7 +41,8 @@ static struct kfd_ipc_handles { */ #define HANDLE_TO_KEY(sh) ((*(uint64_t *)sh) & KFD_IPC_HASH_TABLE_SIZE_MASK) -int kfd_ipc_store_insert(struct dma_buf *dmabuf, struct kfd_ipc_obj **ipc_obj) +int kfd_ipc_store_insert(struct dma_buf *dmabuf, struct kfd_ipc_obj **ipc_obj, + uint32_t flags) { struct kfd_ipc_obj *obj; @@ -59,6 +60,7 @@ int kfd_ipc_store_insert(struct dma_buf *dmabuf, struct kfd_ipc_obj **ipc_obj) kref_init(&obj->ref); obj->dmabuf = dmabuf; get_random_bytes(obj->share_handle, sizeof(obj->share_handle)); + obj->flags = flags; mutex_lock(&kfd_ipc_handles.lock); hlist_add_head(&obj->node, @@ -182,7 +184,7 @@ int kfd_ipc_import_dmabuf(struct kfd_dev *dev, int kfd_ipc_import_handle(struct kfd_dev *dev, struct kfd_process *p, uint32_t gpu_id, uint32_t *share_handle, uint64_t va_addr, uint64_t *handle, - uint64_t *mmap_offset) + uint64_t *mmap_offset, uint32_t *pflags) { int r; struct kfd_ipc_obj *entry, *found = NULL; @@ -212,6 +214,7 @@ int kfd_ipc_import_handle(struct kfd_dev *dev, struct kfd_process *p, if (r) goto error_unref; + *pflags = found->flags; return r; error_unref: @@ -220,7 +223,8 @@ int kfd_ipc_import_handle(struct kfd_dev *dev, struct kfd_process *p, } int kfd_ipc_export_as_handle(struct kfd_dev *dev, struct kfd_process *p, - uint64_t handle, uint32_t *ipc_handle) + uint64_t handle, uint32_t *ipc_handle, + uint32_t flags) { struct kfd_process_device *pdd = NULL; struct kfd_ipc_obj *ipc_obj; @@ -249,7 +253,7 @@ int kfd_ipc_export_as_handle(struct kfd_dev *dev, struct kfd_process *p, mem = (struct kgd_mem *)kfd_bo->mem; r = amdgpu_amdkfd_gpuvm_export_ipc_obj(dev->kgd, pdd->drm_priv, mem, - &ipc_obj); + &ipc_obj, flags); if (r) return r; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h index 72fe8e4af2e5c..7915b8cad13db 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h @@ -36,20 +36,23 @@ struct kfd_ipc_obj { struct kref ref; struct dma_buf *dmabuf; uint32_t share_handle[4]; + uint32_t flags; }; int kfd_ipc_import_handle(struct kfd_dev *dev, struct kfd_process *p, uint32_t gpu_id, uint32_t *share_handle, uint64_t va_addr, uint64_t *handle, - uint64_t *mmap_offset); + uint64_t *mmap_offset, uint32_t *pflags); int kfd_ipc_import_dmabuf(struct kfd_dev *kfd, struct kfd_process *p, uint32_t gpu_id, int dmabuf_fd, uint64_t va_addr, uint64_t *handle, uint64_t *mmap_offset); int kfd_ipc_export_as_handle(struct kfd_dev *dev, struct kfd_process *p, - uint64_t handle, uint32_t *ipc_handle); + uint64_t handle, uint32_t *ipc_handle, + uint32_t flags); -int kfd_ipc_store_insert(struct dma_buf *dmabuf, struct kfd_ipc_obj **ipc_obj); +int kfd_ipc_store_insert(struct dma_buf *dmabuf, struct kfd_ipc_obj **ipc_obj, + uint32_t flags); void kfd_ipc_obj_put(struct kfd_ipc_obj **obj); #endif /* KFD_IPC_H_ */ diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h index b879fa06f4a8a..4522660ee4003 100644 --- a/include/uapi/linux/kfd_ioctl.h +++ b/include/uapi/linux/kfd_ioctl.h @@ -742,16 +742,16 @@ struct kfd_ioctl_ipc_export_handle_args { __u64 handle; /* to KFD */ __u32 share_handle[4]; /* from KFD */ __u32 gpu_id; /* to KFD */ - __u32 pad; + __u32 flags; /* to KFD */ }; struct kfd_ioctl_ipc_import_handle_args { __u64 handle; /* from KFD */ __u64 va_addr; /* to KFD */ - __u64 mmap_offset; /* from KFD */ + __u64 mmap_offset; /* from KFD */ __u32 share_handle[4]; /* to KFD */ __u32 gpu_id; /* to KFD */ - __u32 pad; + __u32 flags; /* from KFD */ }; /* Guarantee host access to memory */ From 53fc68afd44a290551a1aa47ad973daab988e90d Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 10 Aug 2021 14:14:34 +0800 Subject: [PATCH 0470/1868] drm/amdkcl: Test whether struct dev_pagemap has member range This is caused by 1d5dbfe6c06a "drm/amdkfd: classify and map mixed svm range pages in GPU" v5.13-rc7-1639-g1d5dbfe6c06a Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c index 2339bbdf452fb..229da4a0283d0 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c @@ -184,7 +184,11 @@ svm_range_dma_map_dev(struct amdgpu_device *adev, struct svm_range *prange, addr[i] = (hmm_pfns[i] << PAGE_SHIFT) + bo_adev->vm_manager.vram_base_offset - +#ifdef HAVE_DEV_PAGEMAP_RANGE bo_adev->kfd.pgmap.range.start; +#else + bo_adev->kfd.dev->pgmap.res.start; +#endif addr[i] |= SVM_RANGE_VRAM_DOMAIN; pr_debug_ratelimited("vram address: 0x%llx\n", addr[i]); continue; From 04c8b7b894540281ff47141e9c36c83e3712bce4 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 10 Aug 2021 14:44:49 +0800 Subject: [PATCH 0471/1868] drm/amdkcl: wrap the code under macro HAVE_DRM_DP_AUX_DRM_DEV This is caused by 6cba3fe43341 "drm/dp: Add backpointer to drm_device in drm_dp_aux" v5.12-rc7-1495-g6cba3fe43341 Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index ef745d6abdfc7..35233ab24bbab 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -886,7 +886,9 @@ void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm, kasprintf(GFP_KERNEL, "AMDGPU DM aux hw bus %d", link_index); aconnector->dm_dp_aux.aux.transfer = dm_dp_aux_transfer; +#ifdef HAVE_DRM_DP_AUX_DRM_DEV aconnector->dm_dp_aux.aux.drm_dev = dm->ddev; +#endif aconnector->dm_dp_aux.ddc_service = aconnector->dc_link->ddc; drm_dp_aux_init(&aconnector->dm_dp_aux.aux); From 200d05fb1fbcd93d83bb681fdb3bbdf2617c152e Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 10 Aug 2021 15:35:04 +0800 Subject: [PATCH 0472/1868] =?UTF-8?q?drm/amdkcl:=20Test=20whether=20drm=5F?= =?UTF-8?q?connector=5Fatomic=5Fhdr=5Fmetadata=5Fequal=EF=BC=88=EF=BC=89?= =?UTF-8?q?=20is=20available?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is caused by 72921cdf8ac2 "drm/connector: Add helper to compare HDR metadata" v5.12-rc7-1582-g72921cdf8ac2 Signed-off-by: Leslie Shi --- .../gpu/drm/amd/amdkcl/kcl_drm_connector.c | 23 +++++++++++++++++++ ...drm-connector-atomic-hdr-metadata-equal.m4 | 16 +++++++++++++ ...drm-connector-state-hdr-output-metadata.m4 | 17 ++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 5 ++++ include/kcl/kcl_drm_connector.h | 5 ++++ 5 files changed, 66 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-connector-atomic-hdr-metadata-equal.m4 create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-connector-state-hdr-output-metadata.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c index ebcb2ae541c33..f8bb8819388e6 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c @@ -40,3 +40,26 @@ amdkcl_dummy_symbol(drm_dp_set_subconnector_property, void, return, struct drm_connector *connector, enum drm_connector_status status, const u8 *dpcd, const u8 prot_cap[4]) #endif + +#ifndef HAVE_DRM_CONNECTOR_ATOMIC_HDR_METADATA_EQUAL + +bool drm_connector_atomic_hdr_metadata_equal(struct drm_connector_state *old_state, + struct drm_connector_state *new_state) +{ +#ifdef HAVE_DRM_CONNECTOR_STATE_HDR_OUTPUT_METADATA + struct drm_property_blob *old_blob = old_state->hdr_output_metadata; + struct drm_property_blob *new_blob = new_state->hdr_output_metadata; + + if (!old_blob || !new_blob) + return old_blob == new_blob; + + if (old_blob->length != new_blob->length) + return false; + + return !memcmp(old_blob->data, new_blob->data, old_blob->length); +#else + return false; +#endif +} +EXPORT_SYMBOL(drm_connector_atomic_hdr_metadata_equal); +#endif diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-atomic-hdr-metadata-equal.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-atomic-hdr-metadata-equal.m4 new file mode 100644 index 0000000000000..7ae2c3fd78efd --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector-atomic-hdr-metadata-equal.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.12-rc7-1582-g72921cdf8ac2 +dnl # drm/connector: Add helper to compare HDR metadata +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_ATOMIC_HDR_METADATA_EQUAL], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_connector_atomic_hdr_metadata_equal(NULL, NULL); + ], [drm_connector_atomic_hdr_metadata_equal], [drm/drm_connector.c], [ + AC_DEFINE(HAVE_DRM_CONNECTOR_ATOMIC_HDR_METADATA_EQUAL, 1, + [drm_connector_atomic_hdr_metadata_equal() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-state-hdr-output-metadata.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-state-hdr-output-metadata.m4 new file mode 100644 index 0000000000000..d79d5c876e35b --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector-state-hdr-output-metadata.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v5.1-rc5-1688-gfbb5d0353c62 +dnl # drm: Add HDR source metadata property +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_STATE_HDR_OUTPUT_METADATA], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_connector_state *state = NULL; + state->hdr_output_metadata = NULL; + ],[ + AC_DEFINE(HAVE_DRM_CONNECTOR_STATE_HDR_OUTPUT_METADATA, 1, + [struct drm_connector_state has hdr_output_metadata member]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index acdb4cb610885..76eca8675a168 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -161,6 +161,11 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_AUX_DRM_DEV AC_AMDGPU_DRM_DP_LINK_TRAIN_CLOCK_RECOVERY_DELAY AC_AMDGPU_DRM_DP_LINK_TRAIN_CHANNEL_EQ_DELAY + AC_AMDGPU_DRM_CONNECTOR_ATOMIC_HDR_METADATA_EQUAL + AC_AMDGPU_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY + AC_AMDGPU_DMA_BUF_UNPIN + AC_AMDGPU_STRUCT_DMA_BUF_OPS_UNPIN + AC_AMDGPU_DRM_CONNECTOR_STATE_HDR_OUTPUT_METADATA AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_connector.h b/include/kcl/kcl_drm_connector.h index 9074a56cce9fd..cc7d8fbfe6386 100644 --- a/include/kcl/kcl_drm_connector.h +++ b/include/kcl/kcl_drm_connector.h @@ -96,4 +96,9 @@ enum drm_mode_subconnector { #endif /* HAVE_DRM_MODE_SUBCONNECTOR_ENUM */ #endif /* HAVE_DRM_MODE_CONFIG_DP_SUBCONNECTOR_PROPERTY */ +#ifndef HAVE_DRM_CONNECTOR_ATOMIC_HDR_METADATA_EQUAL +bool drm_connector_atomic_hdr_metadata_equal(struct drm_connector_state *old_state, + struct drm_connector_state *new_state); +#endif + #endif /* AMDKCL_DRM_CONNECTOR_H */ From 097cdae84c6faa6ffa96e6d839837896e99d4365 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 10 Aug 2021 16:05:02 +0800 Subject: [PATCH 0473/1868] =?UTF-8?q?drm/amdkcl:=20Test=20whether=20drm=5F?= =?UTF-8?q?connector=5Fattach=5Fhdr=5Foutput=5Fmetadata=5Fproperty?= =?UTF-8?q?=EF=BC=88=EF=BC=89=20is=20available?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is caused by e057b52c1d90 "drm/connector: Create a helper to attach the hdr_output_metadata property" v5.12-rc7-1581-ge057b52c1d90 Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c | 15 +++++++++++++++ ...nector-attach-hdr-output-metadata-property.m4 | 16 ++++++++++++++++ include/kcl/kcl_drm_connector.h | 4 ++++ 3 files changed, 35 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-connector-attach-hdr-output-metadata-property.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c index f8bb8819388e6..79c907264d709 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c @@ -63,3 +63,18 @@ bool drm_connector_atomic_hdr_metadata_equal(struct drm_connector_state *old_sta } EXPORT_SYMBOL(drm_connector_atomic_hdr_metadata_equal); #endif + +#if !defined(HAVE_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY) +int drm_connector_attach_hdr_output_metadata_property(struct drm_connector *connector) +{ +#ifdef HAVE_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY + struct drm_device *dev = connector->dev; + struct drm_property *prop = dev->mode_config.hdr_output_metadata_property; + + drm_object_attach_property(&connector->base, prop, 0); +#endif + + return 0; +} +EXPORT_SYMBOL(drm_connector_attach_hdr_output_metadata_property); +#endif diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-attach-hdr-output-metadata-property.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-attach-hdr-output-metadata-property.m4 new file mode 100644 index 0000000000000..fccf8755fc7fe --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector-attach-hdr-output-metadata-property.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.12-rc7-1581-ge057b52c1d90 +dnl # drm/connector: Create a helper to attach the hdr_output_metadata property +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_connector_attach_hdr_output_metadata_property(NULL); + ], [drm_connector_attach_hdr_output_metadata_property], [drm/drm_connector.c], [ + AC_DEFINE(HAVE_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY, 1, + [drm_connector_attach_hdr_output_metadata_property() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_drm_connector.h b/include/kcl/kcl_drm_connector.h index cc7d8fbfe6386..f50f00e2f17fb 100644 --- a/include/kcl/kcl_drm_connector.h +++ b/include/kcl/kcl_drm_connector.h @@ -101,4 +101,8 @@ bool drm_connector_atomic_hdr_metadata_equal(struct drm_connector_state *old_sta struct drm_connector_state *new_state); #endif +#if !defined(HAVE_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY) +int drm_connector_attach_hdr_output_metadata_property(struct drm_connector *connector); +#endif + #endif /* AMDKCL_DRM_CONNECTOR_H */ From 3ca4a5fe60ad4fd3d716691ad3184faba42aa09a Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 10 Aug 2021 16:57:47 +0800 Subject: [PATCH 0474/1868] drm/amdkcl: Test whether drm_plane_helper_funcs.atomic_check second param is struct drm_atomic_state* This is caused by 5ddb0bd4ddc3 "drm/atomic: Pass the full state to planes async atomic check and update" v5.11-rc2-698-g5ddb0bd4ddc3 Signed-off-by: Leslie Shi Signed-off-by: Ma Jun Change-Id: Ib363f19e14009df6191f30959f76fe17ce68a5ca --- .../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 35 ++++++++++++++++--- .../dkms/m4/struct_drm_plane_helper_funcs.m4 | 20 +++++++++++ 2 files changed, 50 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 3e900ecfd3405..957e1e59ba668 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -1246,10 +1246,18 @@ int amdgpu_dm_plane_fill_dc_scaling_info(struct amdgpu_device *adev, } static int amdgpu_dm_plane_atomic_check(struct drm_plane *plane, - struct drm_atomic_state *state) +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS + struct drm_atomic_state *state) +#else + struct drm_plane_state *state) +#endif { +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); +#else + struct drm_plane_state *new_plane_state = state; +#endif struct amdgpu_device *adev = drm_to_adev(plane->dev); struct dc *dc = adev->dm.dc; struct dm_plane_state *dm_plane_state; @@ -1264,8 +1272,12 @@ static int amdgpu_dm_plane_atomic_check(struct drm_plane *plane, if (!dm_plane_state->dc_state) return 0; - new_crtc_state = kcl_drm_atomic_get_new_crtc_state_before_commit( - state, new_plane_state->crtc); + new_crtc_state = +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS + drm_atomic_get_new_crtc_state(state, new_plane_state->crtc); +#else + drm_atomic_get_new_crtc_state(state->state, state->crtc); +#endif if (!new_crtc_state) return -EINVAL; @@ -1286,7 +1298,11 @@ static int amdgpu_dm_plane_atomic_check(struct drm_plane *plane, #ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_ASYNC_CHECK static int amdgpu_dm_plane_atomic_async_check(struct drm_plane *plane, - struct drm_atomic_state *state) +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS + struct drm_atomic_state *state) +#else + struct drm_plane_state *state) +#endif { struct drm_crtc_state *new_crtc_state; struct drm_plane_state *new_plane_state; @@ -1422,12 +1438,21 @@ void amdgpu_dm_plane_handle_cursor_update(struct drm_plane *plane, } static void amdgpu_dm_plane_atomic_async_update(struct drm_plane *plane, - struct drm_atomic_state *state) +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS + struct drm_atomic_state *state) +#else + struct drm_plane_state *new_state) +#endif { +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane); struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, plane); +#else + struct drm_plane_state *old_state = + drm_atomic_get_old_plane_state(new_state->state, plane); +#endif trace_amdgpu_dm_atomic_update_cursor(new_state); diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_plane_helper_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_plane_helper_funcs.m4 index 4dd6e4db74ff6..68b8e02668cae 100644 --- a/drivers/gpu/drm/amd/dkms/m4/struct_drm_plane_helper_funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_plane_helper_funcs.m4 @@ -16,3 +16,23 @@ AC_DEFUN([AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS], [ ]) ]) ]) + +dnl # commit v5.11-rc2-701-g7c11b99a8e58 +dnl # drm/atomic: Pass the full state to planes atomic_check +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_plane_helper_funcs *funcs = NULL; + funcs->atomic_check((struct drm_crtc *)NULL, (struct drm_atomic_state *)NULL); + ], [ + AC_DEFINE(HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS, 1, + [drm_plane_helper_funcs->atomic_check() second param wants drm_atomic_state arg]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS], [ + AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS +]) From 96045a9d0f1d061e32aa424558165e6324aa30ba Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 10 Aug 2021 17:15:56 +0800 Subject: [PATCH 0475/1868] drm/amdkcl: fix build error for renamed struct field Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c b/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c index ef1c82463f8e0..5acf8485888f7 100644 --- a/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c +++ b/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c @@ -32,7 +32,7 @@ void _kcl_drm_gem_ttm_vunmap(struct drm_gem_object *gem, struct dma_buf_map map; map.vaddr = vaddr; - map.is_iomem = bo->mem.bus.is_iomem; + map.is_iomem = bo->resource->bus.is_iomem; ttm_bo_vunmap(bo, &map); } From efd0c8046f2d5de92a7c50b469c37c3278e5a1e3 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Fri, 13 Aug 2021 16:26:58 +0800 Subject: [PATCH 0476/1868] drm/amdkcl: access resv field using amdkcl_ttm_resvp Signed-off-by: Leslie Shi --- drivers/gpu/drm/ttm/ttm_bo.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index b1696c3911983..ca42efa8a7ed8 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -498,7 +498,7 @@ bool ttm_bo_eviction_valuable(struct ttm_buffer_object *bo, struct ttm_resource *res = bo->resource; struct ttm_device *bdev = bo->bdev; - dma_resv_assert_held(bo->base.resv); + dma_resv_assert_held(amdkcl_ttm_resvp(bo)); if (bo->resource->mem_type == TTM_PL_SYSTEM) return true; @@ -551,7 +551,7 @@ static bool ttm_bo_evict_swapout_allowable(struct ttm_buffer_object *bo, !bo->bdev->funcs->eviction_valuable(bo, place))) { ret = false; if (*locked) { - dma_resv_unlock(bo->base.resv); + dma_resv_unlock(amdkcl_ttm_resvp(bo)); *locked = false; } } From bbac35d6b441d624e975eb565b3dcd93576eb262 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 18 Aug 2021 10:51:54 +0800 Subject: [PATCH 0477/1868] drm/amdkcl: DROPME rework config.h Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 69 ++++++++++++++++++++---- 1 file changed, 59 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index bce21674fb244..b8d0184b66fa5 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -11,7 +11,7 @@ #define HAVE_ACCESS_OK_WITH_TWO_ARGUMENTS 1 /* acpi_put_table() is available */ -#define HAVE_ACPI_PUT_TABLE 1 +/* #undef HAVE_ACPI_PUT_TABLE */ /* struct acpi_srat_generic_affinity is available */ #define HAVE_ACPI_SRAT_GENERIC_AFFINITY 1 @@ -29,7 +29,7 @@ #define HAVE_AMD_IOMMU_INVALIDATE_CTX_PASID_U32 1 /* amd_iommu_pc_supported() is available */ -#define HAVE_AMD_IOMMU_PC_SUPPORTED 1 +/* #undef HAVE_AMD_IOMMU_PC_SUPPORTED */ /* arch_io_{reserve/free}_memtype_wc() are available */ #define HAVE_ARCH_IO_RESERVE_FREE_MEMTYPE_WC 1 @@ -115,6 +115,12 @@ /* Define to 1 if you have the header file. */ /* #undef HAVE_DRM_AMDGPU_PCIID_H */ +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_AMD_ASIC_TYPE_H 1 + +/* drm_aperture_remove_* is availablea */ +#define HAVE_DRM_APERTURE 1 + /* drm_atomic_get_old_crtc_state() and drm_atomic_get_new_crtc_state() are available */ #define HAVE_DRM_ATOMIC_GET_CRTC_STATE 1 @@ -128,9 +134,6 @@ /* drm_atomic_helper_check_plane_state() is available */ #define HAVE_DRM_ATOMIC_HELPER_CHECK_PLANE_STATE 1 -/* HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL is available */ -#define HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL 1 - /* drm_atomic_helper_shutdown() is available */ #define HAVE_DRM_ATOMIC_HELPER_SHUTDOWN 1 @@ -163,6 +166,12 @@ /* drm_color_lut_size() is available */ #define HAVE_DRM_COLOR_LUT_SIZE 1 +/* drm_connector_atomic_hdr_metadata_equal() is available */ +/* #undef HAVE_DRM_CONNECTOR_ATOMIC_HDR_METADATA_EQUAL */ + +/* drm_connector_attach_hdr_output_metadata_property() is available */ +/* #undef HAVE_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY */ + /* drm_connector_for_each_possible_encoder() wants 2 arguments */ #define HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS 1 @@ -255,6 +264,9 @@ /* drm_dp_atomic_find_vcpi_slots() wants 5args */ #define HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS_5ARGS 1 +/* struct drm_dp_aux has member named 'drm_dev' */ +#define HAVE_DRM_DP_AUX_DRM_DEV 1 + /* drm_dp_calc_pbn_mode() wants 3args */ #define HAVE_DRM_DP_CALC_PBN_MODE_3ARGS 1 @@ -264,6 +276,12 @@ /* drm_dp_cec_register_connector() wants p,p interface */ #define HAVE_DRM_DP_CEC_REGISTER_CONNECTOR_PP 1 +/* drm_dp_link_train_channel_eq_delay() has 2 args */ +/* #undef HAVE_DRM_DP_LINK_TRAIN_CHANNEL_EQ_DELAY_2ARGS */ + +/* drm_dp_link_train_clock_recovery_delay() has 2 args */ +/* #undef HAVE_DRM_DP_LINK_TRAIN_CLOCK_RECOVERY_DELAY_2ARGS */ + /* drm_dp_mst_add_affected_dsc_crtcs() is available */ #define HAVE_DRM_DP_MST_ADD_AFFECTED_DSC_CRTCS 1 @@ -324,6 +342,9 @@ /* Define to 1 if you have the header file. */ /* #undef HAVE_DRM_DRMP_H */ +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_APERTURE_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_ATOMIC_UAPI_H 1 @@ -423,13 +444,13 @@ #define HAVE_DRM_FB_HELPER_LASTCLOSE 1 /* drm_fb_helper_remove_conflicting_pci_framebuffers() is available */ -#define HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS 1 +/* #undef HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS */ /* drm_fb_helper_remove_conflicting_pci_framebuffers() wants p,i,p args */ /* #undef HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PIP */ /* drm_fb_helper_remove_conflicting_pci_framebuffers() wants p,p args */ -#define HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP 1 +/* #undef HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP */ /* drm_fb_helper_set_suspend_unlocked() is available */ #define HAVE_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED 1 @@ -455,6 +476,9 @@ /* ttm_buffer_object->base is available */ #define HAVE_DRM_GEM_OBJECT_RESV 1 +/* drm_gem_prime_mmap() is available */ +/* #undef HAVE_DRM_GEM_PRIME_MMAP */ + /* drm_gem_ttm_vmap() is available */ #define HAVE_DRM_GEM_TTM_VMAP 1 @@ -465,7 +489,7 @@ #define HAVE_DRM_GET_FORMAT_INFO 1 /* drm_get_format_name() has i,p interface */ -#define HAVE_DRM_GET_FORMAT_NAME_I_P 1 +/* #undef HAVE_DRM_GET_FORMAT_NAME_I_P */ /* drm_hdcp_update_content_protection is available */ #define HAVE_DRM_HDCP_UPDATE_CONTENT_PROTECTION 1 @@ -491,6 +515,9 @@ /* drm_kms_helper_is_poll_worker() is available */ #define HAVE_DRM_KMS_HELPER_IS_POLL_WORKER 1 +/* drm_memcpy_from_wc() is availablea */ +#define HAVE_DRM_MEMCPY_FROM_WC 1 + /* whether drm_mm_insert_mode is available */ #define HAVE_DRM_MM_INSERT_MODE 1 @@ -630,6 +657,15 @@ /* in_compat_syscall is defined */ #define HAVE_IN_COMPAT_SYSCALL 1 +/* io_mapping_map_local_wc() is available */ +#define HAVE_IO_MAPPING_MAP_LOCAL_WC 1 + +/* io_mapping_unmap_local() is available */ +#define HAVE_IO_MAPPING_UNMAP_LOCAL 1 + +/* is_cow_mapping() is available */ +#define HAVE_IS_COW_MAPPING 1 + /* jiffies64_to_msecs() is available */ #define HAVE_JIFFIES64_TO_MSECS 1 @@ -639,6 +675,9 @@ /* kernel_write() take arg type of position as pointer */ #define HAVE_KERNEL_WRITE_PPOS 1 +/* kmap_local_page_prot() is available */ +#define HAVE_KMAP_LOCAL_PAGE_PROT 1 + /* kref_read() function is available */ #define HAVE_KREF_READ 1 @@ -789,6 +828,9 @@ /* pci_dev_id() is available */ #define HAVE_PCI_DEV_ID 1 +/* struct pci_driver has field dev_groups */ +#define HAVE_PCI_DRIVER_DEV_GROUPS 1 + /* pci_is_thunderbolt_attached() is available */ #define HAVE_PCI_IS_THUNDERBOLD_ATTACHED 1 @@ -820,7 +862,7 @@ #define HAVE_PXM_TO_NODE 1 /* remove_conflicting_framebuffers() returns int */ -/* #undef HAVE_REMOVE_CONFLICTING_FRAMEBUFFERS_RETURNS_INT */ +#define HAVE_REMOVE_CONFLICTING_FRAMEBUFFERS_RETURNS_INT 1 /* request_firmware_direct() is available */ #define HAVE_REQUEST_FIRMWARE_DIRECT 1 @@ -873,6 +915,9 @@ /* crtc->funcs->gamma_set() wants 6 args */ #define HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_6ARGS 1 +/* HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL is available */ +#define HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL 1 + /* struct drm_crtc_funcs->get_vblank_timestamp() is available */ #define HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP 1 @@ -912,6 +957,10 @@ /* drm_plane_helper_funcs->atomic_async_check() is available */ #define HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_ASYNC_CHECK 1 +/* drm_plane_helper_funcs->atomic_check() second param wants drm_atomic_state + arg */ +/* #undef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS */ + /* drm_plane_helper_funcs->prepare_fb() wants const p arg */ /* #undef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_PREPARE_FB_CONST */ @@ -924,7 +973,7 @@ /* zone->managed_pages is available */ /* #undef HAVE_STRUCT_ZONE_MANAGED_PAGES */ -/* sysfs_emit() and sysfs_emit_at are available */ +/* sysfs_emit() and sysfs_emit_at() are available */ #define HAVE_SYSFS_EMIT 1 /* timer_setup() is available */ From 5fbdf282ecb0e8608f37a39a6dad35bdce92f3b9 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Fri, 20 Aug 2021 17:45:09 +0800 Subject: [PATCH 0478/1868] drm/amdkcl: fake drm_gem_mmap for drm_gem_prime_mmap for legacy ps This is caused by following commits: 71df0368e9b6 drm/amdgpu: Implement mmap as GEM object function 47d35c1c40d5 drm: Set vm_ops to GEM object's values during mmap Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 48 ++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h | 6 + drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 5 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 84 ++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 4 + drivers/gpu/drm/amd/backport/Makefile | 2 +- drivers/gpu/drm/amd/backport/backport.h | 1 + .../backport/include/kcl/kcl_amdgpu_drm_gem.h | 49 ++++++ drivers/gpu/drm/amd/backport/kcl_drm_gem.c | 149 ++++++++++++++++++ drivers/gpu/drm/ttm/ttm_bo_vm.c | 77 +++++++++ include/drm/ttm/ttm_bo.h | 14 ++ include/drm/ttm/ttm_device.h | 18 +++ 12 files changed, 454 insertions(+), 3 deletions(-) create mode 100644 drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_gem.h create mode 100644 drivers/gpu/drm/amd/backport/kcl_drm_gem.c diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index 790ce0671b43d..664e7b211e0aa 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -42,6 +42,54 @@ #include #include +#ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK +/** + * amdgpu_gem_prime_mmap - &drm_driver.gem_prime_mmap implementation + * @obj: GEM BO + * @vma: Virtual memory area + * + * Sets up a userspace mapping of the BO's memory in the given + * virtual memory area. + * + * Returns: + * 0 on success or a negative error code on failure. + */ +int amdgpu_gem_prime_mmap(struct drm_gem_object *obj, + struct vm_area_struct *vma) +{ + struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); + struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); + unsigned asize = amdgpu_bo_size(bo); + int ret; + + if (!vma->vm_file) + return -ENODEV; + + if (adev == NULL) + return -ENODEV; + + /* Check for valid size. */ + if (asize < vma->vm_end - vma->vm_start) + return -EINVAL; + + if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm) || + (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) { + return -EPERM; + } + vma->vm_pgoff += amdgpu_bo_mmap_offset(bo) >> PAGE_SHIFT; + + /* prime mmap does not need to check access, so allow here */ + ret = drm_vma_node_allow(&obj->vma_node, vma->vm_file->private_data); + if (ret) + return ret; + + ret = ttm_bo_mmap(vma->vm_file, vma, &adev->mman.bdev); + drm_vma_node_revoke(&obj->vma_node, vma->vm_file->private_data); + + return ret; +} +#endif + #if defined(AMDKCL_AMDGPU_DMABUF_OPS) static int __dma_resv_make_exclusive(struct dma_resv *obj) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h index f7a7492b68f55..dbc9384febd43 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.h @@ -54,6 +54,12 @@ bool amdgpu_dmabuf_is_xgmi_accessible(struct amdgpu_device *adev, struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *); #endif +#ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK +int amdgpu_gem_prime_mmap(struct drm_gem_object *obj, + struct vm_area_struct *vma); +#endif + + extern const struct dma_buf_ops amdgpu_dmabuf_ops; #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 58b8561ddba5c..7afaded24e86a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2961,7 +2961,7 @@ static const struct file_operations amdgpu_driver_kms_fops = { .flush = amdgpu_flush, .release = drm_release, .unlocked_ioctl = amdgpu_drm_ioctl, - .mmap = drm_gem_mmap, + .mmap = amdkcl_drm_gem_mmap, .poll = drm_poll, .read = drm_read, #ifdef CONFIG_COMPAT @@ -3088,7 +3088,8 @@ static struct drm_driver amdgpu_kms_driver = { .gem_prime_vunmap = drm_gem_ttm_vunmap, #endif - .gem_prime_mmap = drm_gem_prime_mmap, + .gem_prime_mmap = amdkcl_drm_gem_prime_mmap, + .name = DRIVER_NAME, .desc = DRIVER_DESC, .date = DRIVER_DATE, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index db8f39c48ea11..8e8f0034ec6ce 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -171,6 +171,27 @@ static void amdgpu_evict_flags(struct ttm_buffer_object *bo, *placement = abo->placement; } +#ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK +/** + * amdgpu_verify_access - Verify access for a mmap call + * + * @bo: The buffer object to map + * @filp: The file pointer from the process performing the mmap + * + * This is called by ttm_bo_mmap() to verify whether a process + * has the right to mmap a BO to their process space. + */ +static int amdgpu_verify_access(struct ttm_buffer_object *bo, struct file *filp) +{ + struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo); + + if (amdgpu_ttm_tt_get_usermm(bo->ttm)) + return -EPERM; + return drm_vma_node_verify_access(&abo->tbo.base.vma_node, + filp->private_data); +} +#endif + /** * amdgpu_ttm_map_buffer - Map memory into the GART windows * @bo: buffer object to map @@ -1878,6 +1899,9 @@ static struct ttm_device_funcs amdgpu_bo_driver = { .eviction_valuable = amdgpu_ttm_bo_eviction_valuable, .evict_flags = &amdgpu_evict_flags, .move = &amdgpu_bo_move, +#ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK + .verify_access = &amdgpu_verify_access, +#endif .delete_mem_notify = &amdgpu_bo_delete_mem_notify, .release_notify = &amdgpu_bo_release_notify, .io_mem_reserve = &amdgpu_ttm_io_mem_reserve, @@ -2708,6 +2732,66 @@ static int amdgpu_ttm_prepare_job(struct amdgpu_device *adev, DMA_RESV_USAGE_BOOKKEEP); } +#ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK +#ifndef HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG +static vm_fault_t amdgpu_ttm_fault(struct vm_area_struct *vma, struct vm_fault *vmf) +{ + struct ttm_buffer_object *bo = vma->vm_private_data; +#else +static vm_fault_t amdgpu_ttm_fault(struct vm_fault *vmf) +{ + struct ttm_buffer_object *bo = vmf->vma->vm_private_data; +#endif + vm_fault_t ret; + +#ifndef HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG + ret = ttm_bo_vm_reserve(bo, vmf, vma); +#else + ret = ttm_bo_vm_reserve(bo, vmf); +#endif + if (ret) + return ret; + + ret = amdgpu_bo_fault_reserve_notify(bo); + if (ret) + goto unlock; + +#ifndef HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG + ret = ttm_bo_vm_fault_reserved(vmf, vma, vma->vm_page_prot, TTM_BO_VM_NUM_PREFAULT); +#else + ret = ttm_bo_vm_fault_reserved(vmf, vmf->vma->vm_page_prot, + TTM_BO_VM_NUM_PREFAULT); +#endif + if (ret == VM_FAULT_RETRY && !(vmf->flags & FAULT_FLAG_RETRY_NOWAIT)) + return ret; + +unlock: + dma_resv_unlock(amdkcl_ttm_resvp(bo)); + return ret; +} + +static struct vm_operations_struct amdgpu_ttm_vm_ops = { + .fault = amdgpu_ttm_fault, + .open = ttm_bo_vm_open, + .close = ttm_bo_vm_close, + .access = ttm_bo_vm_access +}; + +int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma) +{ + struct drm_file *file_priv = filp->private_data; + struct amdgpu_device *adev = drm_to_adev(file_priv->minor->dev); + int r; + + r = ttm_bo_mmap(filp, vma, &adev->mman.bdev); + if (unlikely(r != 0)) + return r; + + vma->vm_ops = &amdgpu_ttm_vm_ops; + return 0; +} +#endif /* HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK */ + int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset, uint64_t dst_offset, uint32_t byte_count, struct dma_resv *resv, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h index a49d8718d6432..acd83977731f8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h @@ -189,6 +189,10 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo, struct dma_fence **fence, bool delayed); +#ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK +int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma); +#endif + int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo); void amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo); uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type); diff --git a/drivers/gpu/drm/amd/backport/Makefile b/drivers/gpu/drm/amd/backport/Makefile index ba3805d29cbc3..fa78abd428129 100644 --- a/drivers/gpu/drm/amd/backport/Makefile +++ b/drivers/gpu/drm/amd/backport/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: MIT BACKPORT_OBJS := kcl_drm_drv.o kcl_drm_gem_ttm_helper.o \ - kcl_drm_gem_framebuffer_helper.o + kcl_drm_gem_framebuffer_helper.o kcl_drm_gem.o amdgpu-y += $(addprefix ../backport/,$(BACKPORT_OBJS)) diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 810a40bc1d1d6..e10a0d22ed94b 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -72,6 +72,7 @@ #include "kcl/kcl_amdgpu_drm_gem_framebuffer_helper.h" #include "kcl/kcl_amdgpu.h" #include "kcl/kcl_amdgpu_drm_drv.h" +#include "kcl/kcl_amdgpu_drm_gem.h" #include "kcl/kcl_drm_gem_ttm_helper.h" #include "kcl/kcl_drm_aperture.h" diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_gem.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_gem.h new file mode 100644 index 0000000000000..9ad60a7646fa0 --- /dev/null +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_gem.h @@ -0,0 +1,49 @@ +/* + * GEM Graphics Execution Manager Driver Interfaces + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * Copyright (c) 2009-2010, Code Aurora Forum. + * All rights reserved. + * Copyright © 2014 Intel Corporation + * Daniel Vetter + * + * Author: Rickard E. (Rik) Faith + * Author: Gareth Hughes + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef __AMDGPU_BACKPORT_KCL_AMDGPU_DRM_GEM_H__ +#define __AMDGPU_BACKPORT_KCL_AMDGPU_DRM_GEM_H__ + +int _kcl_drm_gem_mmap(struct file *filp, struct vm_area_struct *vma); + +static inline int amdkcl_drm_gem_mmap(struct file *filp, struct vm_area_struct *vma) { + return _kcl_drm_gem_mmap(filp, vma); +} + + +int _kcl_drm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma); + +static inline int amdkcl_drm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma) { + return _kcl_drm_gem_prime_mmap(obj, vma); +} + +#endif diff --git a/drivers/gpu/drm/amd/backport/kcl_drm_gem.c b/drivers/gpu/drm/amd/backport/kcl_drm_gem.c new file mode 100644 index 0000000000000..328395cbd0125 --- /dev/null +++ b/drivers/gpu/drm/amd/backport/kcl_drm_gem.c @@ -0,0 +1,149 @@ +/* + * Copyright © 2008 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Eric Anholt + * + */ + +#include +#include "amdgpu_ttm.h" +#include "amdgpu_dma_buf.h" + +#ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK +int _kcl_drm_gem_mmap(struct file *filp, struct vm_area_struct *vma) { + return amdgpu_mmap(filp, vma); +} + +int _kcl_drm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma) { + return amdgpu_gem_prime_mmap(obj, vma); +} + +#else +static int _kcl_drm_gem_mmap_obj(struct drm_gem_object *obj, unsigned long obj_size, + struct vm_area_struct *vma) +{ + int ret; + + /* Check for valid size. */ + if (obj_size < vma->vm_end - vma->vm_start) + return -EINVAL; + + /* Take a ref for this mapping of the object, so that the fault + * handler can dereference the mmap offset's pointer to the object. + * This reference is cleaned up by the corresponding vm_close + * (which should happen whether the vma was created by this call, or + * by a vm_open due to mremap or partial unmap or whatever). + */ + drm_gem_object_get(obj); + + vma->vm_private_data = obj; + vma->vm_ops = obj->funcs->vm_ops; + + if (obj->funcs->mmap) { + ret = obj->funcs->mmap(obj, vma); + if (ret) + goto err_drm_gem_object_put; + WARN_ON(!(vma->vm_flags & VM_DONTEXPAND)); + } else { + if (!vma->vm_ops) { + ret = -EINVAL; + goto err_drm_gem_object_put; + } + + vma->vm_flags |= VM_IO | VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP; + vma->vm_page_prot = pgprot_writecombine(vm_get_page_prot(vma->vm_flags)); + vma->vm_page_prot = pgprot_decrypted(vma->vm_page_prot); + } + + return 0; + +err_drm_gem_object_put: + drm_gem_object_put(obj); + return ret; +} + +int _kcl_drm_gem_mmap(struct file *filp, struct vm_area_struct *vma) { + struct drm_file *priv = filp->private_data; + struct drm_device *dev = priv->minor->dev; + struct drm_gem_object *obj = NULL; + struct drm_vma_offset_node *node; + int ret; + + if (drm_dev_is_unplugged(dev)) + return -ENODEV; + + drm_vma_offset_lock_lookup(dev->vma_offset_manager); + node = drm_vma_offset_exact_lookup_locked(dev->vma_offset_manager, + vma->vm_pgoff, + vma_pages(vma)); + if (likely(node)) { + obj = container_of(node, struct drm_gem_object, vma_node); + /* + * When the object is being freed, after it hits 0-refcnt it + * proceeds to tear down the object. In the process it will + * attempt to remove the VMA offset and so acquire this + * mgr->vm_lock. Therefore if we find an object with a 0-refcnt + * that matches our range, we know it is in the process of being + * destroyed and will be freed as soon as we release the lock - + * so we have to check for the 0-refcnted object and treat it as + * invalid. + */ + if (!kref_get_unless_zero(&obj->refcount)) + obj = NULL; + } + drm_vma_offset_unlock_lookup(dev->vma_offset_manager); + + if (!obj) + return -EINVAL; + + if (!drm_vma_node_is_allowed(node, priv)) { + drm_gem_object_put(obj); + return -EACCES; + } + + if (node->readonly) { + if (vma->vm_flags & VM_WRITE) { + drm_gem_object_put(obj); + return -EINVAL; + } + + vma->vm_flags &= ~VM_MAYWRITE; + } + + ret = _kcl_drm_gem_mmap_obj(obj, drm_vma_node_size(node) << PAGE_SHIFT, + vma); + + drm_gem_object_put(obj); + + return ret; + +} + +int _kcl_drm_gem_prime_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma) { + if (obj->funcs && obj->funcs->mmap) { + vma->vm_ops = obj->funcs->vm_ops; + } + return drm_gem_prime_mmap(obj, vma); +} + +#endif diff --git a/drivers/gpu/drm/ttm/ttm_bo_vm.c b/drivers/gpu/drm/ttm/ttm_bo_vm.c index 19ea3c3cbf461..236c71df66da0 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_vm.c +++ b/drivers/gpu/drm/ttm/ttm_bo_vm.c @@ -488,6 +488,83 @@ static const struct vm_operations_struct ttm_bo_vm_ops = { .access = ttm_bo_vm_access, }; +#ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK +static struct ttm_buffer_object *ttm_bo_vm_lookup(struct ttm_device *bdev, + unsigned long offset, + unsigned long pages) +{ + struct drm_vma_offset_node *node; + struct ttm_buffer_object *bo = NULL; + + drm_vma_offset_lock_lookup(bdev->vma_manager); + + node = drm_vma_offset_lookup_locked(bdev->vma_manager, offset, pages); + if (likely(node)) { + bo = container_of(node, struct ttm_buffer_object, + base.vma_node); + bo = ttm_bo_get_unless_zero(bo); + } + + drm_vma_offset_unlock_lookup(bdev->vma_manager); + + if (!bo) + pr_err("Could not find buffer object to map\n"); + + return bo; +} + +static void ttm_bo_mmap_vma_setup(struct ttm_buffer_object *bo, struct vm_area_struct *vma) +{ + vma->vm_ops = &ttm_bo_vm_ops; + + /* + * Note: We're transferring the bo reference to + * vma->vm_private_data here. + */ + + vma->vm_private_data = bo; + + /* + * We'd like to use VM_PFNMAP on shared mappings, where + * (vma->vm_flags & VM_SHARED) != 0, for performance reasons, + * but for some reason VM_PFNMAP + x86 PAT + write-combine is very + * bad for performance. Until that has been sorted out, use + * VM_MIXEDMAP on all mappings. See freedesktop.org bug #75719 + */ + vma->vm_flags |= VM_PFNMAP; + vma->vm_flags |= VM_IO | VM_DONTEXPAND | VM_DONTDUMP; +} + +int ttm_bo_mmap(struct file *filp, struct vm_area_struct *vma, + struct ttm_device *bdev) +{ + struct ttm_buffer_object *bo; + int ret; + + if (unlikely(vma->vm_pgoff < DRM_FILE_PAGE_OFFSET_START)) + return -EINVAL; + + bo = ttm_bo_vm_lookup(bdev, vma->vm_pgoff, vma_pages(vma)); + if (unlikely(!bo)) + return -EINVAL; + + if (unlikely(!bo->bdev->funcs->verify_access)) { + ret = -EPERM; + goto out_unref; + } + ret = bo->bdev->funcs->verify_access(bo, filp); + if (unlikely(ret != 0)) + goto out_unref; + + ttm_bo_mmap_vma_setup(bo, vma); + return 0; +out_unref: + ttm_bo_put(bo); + return ret; +} +EXPORT_SYMBOL(ttm_bo_mmap); +#endif /* HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK */ + /** * ttm_bo_mmap_obj - mmap memory backed by a ttm buffer object. * diff --git a/include/drm/ttm/ttm_bo.h b/include/drm/ttm/ttm_bo.h index 0d3ef4deb8b1a..977b6fd2404d2 100644 --- a/include/drm/ttm/ttm_bo.h +++ b/include/drm/ttm/ttm_bo.h @@ -399,6 +399,20 @@ void ttm_bo_kunmap(struct ttm_bo_kmap_obj *map); int ttm_bo_vmap(struct ttm_buffer_object *bo, struct iosys_map *map); void ttm_bo_vunmap(struct ttm_buffer_object *bo, struct iosys_map *map); int ttm_bo_mmap_obj(struct vm_area_struct *vma, struct ttm_buffer_object *bo); + +/** + * ttm_bo_mmap - mmap out of the ttm device address space. + * + * @filp: filp as input from the mmap method. + * @vma: vma as input from the mmap method. + * @bdev: Pointer to the ttm_device with the address space manager. + * + * This function is intended to be called by the device mmap method. + * if the device address space is to be backed by the bo manager. + */ +int ttm_bo_mmap(struct file *filp, struct vm_area_struct *vma, + struct ttm_device *bdev); + int ttm_bo_swapout(struct ttm_buffer_object *bo, struct ttm_operation_ctx *ctx, gfp_t gfp_flags); void ttm_bo_pin(struct ttm_buffer_object *bo); diff --git a/include/drm/ttm/ttm_device.h b/include/drm/ttm/ttm_device.h index c22f30535c848..3aab0c5a62bad 100644 --- a/include/drm/ttm/ttm_device.h +++ b/include/drm/ttm/ttm_device.h @@ -151,6 +151,24 @@ struct ttm_device_funcs { struct ttm_resource *new_mem, struct ttm_place *hop); +#ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK + /** + * struct ttm_bo_driver_member verify_access + * + * @bo: Pointer to a buffer object. + * @filp: Pointer to a struct file trying to access the object. + * + * Called from the map / write / read methods to verify that the + * caller is permitted to access the buffer object. + * This member may be set to NULL, which will refuse this kind of + * access for all buffer objects. + * This function should return 0 if access is granted, -EPERM otherwise. + */ + int (*verify_access)(struct ttm_buffer_object *bo, + struct file *filp); +#endif + + /** * Hook to notify driver about a resource delete. */ From c7f3e308542990298998d6c1bfd5f90f7fc85b5d Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 23 Aug 2021 10:22:00 +0800 Subject: [PATCH 0479/1868] drm/amdkcl: wrap the code under macro drmm_add_action_or_reset This is caused by 267d51d77fda "drm/amdgpu: Implement mmap as GEM object function" v5.13-rc1-231-g267d51d77fda Signed-off-by: Leslie Shi --- drivers/gpu/drm/ttm/ttm_bo_vm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/ttm/ttm_bo_vm.c b/drivers/gpu/drm/ttm/ttm_bo_vm.c index 236c71df66da0..71dc72ef19f3b 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_vm.c +++ b/drivers/gpu/drm/ttm/ttm_bo_vm.c @@ -330,8 +330,10 @@ vm_fault_t ttm_bo_vm_dummy_page(struct vm_fault *vmf, pgprot_t prot) return VM_FAULT_OOM; /* Set the page to be freed using drmm release action */ +#ifdef drmm_add_action_or_reset if (drmm_add_action_or_reset(ddev, ttm_bo_release_dummy_page, page)) return VM_FAULT_OOM; +#endif pfn = page_to_pfn(page); From 3067fd1ab643ba24574b57685c102cbf37a46939 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 23 Aug 2021 11:06:02 +0800 Subject: [PATCH 0480/1868] drm/amdkcl: Test whether dma_buf_unpin() is available This is caused by a448cb003edc "drm/amdgpu: implement amdgpu_gem_prime_move_notify v2" v5.6-rc2-339-ga448cb003edc Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 2 ++ drivers/gpu/drm/amd/dkms/m4/dma-buf-unpin.m4 | 34 ++++++++++++++++++++ 2 files changed, 36 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/dma-buf-unpin.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index b39cc2dc47888..6521d4c35c2d8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -1061,8 +1061,10 @@ void amdgpu_bo_unpin(struct amdgpu_bo *bo) if (bo->tbo.pin_count) return; +#ifdef HAVE_DMA_BUF_UNPIN if (bo->tbo.base.import_attach) dma_buf_unpin(bo->tbo.base.import_attach); +#endif if (bo->tbo.resource->mem_type == TTM_PL_VRAM) { atomic64_sub(amdgpu_bo_size(bo), &adev->vram_pin_size); diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-buf-unpin.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-buf-unpin.m4 new file mode 100644 index 0000000000000..4c07a856211f9 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dma-buf-unpin.m4 @@ -0,0 +1,34 @@ +dnl # +dnl # v5.6-rc2-335-gbb42df4662a4 +dnl # dma-buf: add dynamic DMA-buf handling v15 +dnl # +AC_DEFUN([AC_AMDGPU_DMA_BUF_UNPIN], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + dma_buf_unpin(NULL); + ],[ + AC_DEFINE(HAVE_DMA_BUF_UNPIN, 1, + [dma_buf_unpin() is available]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_STRUCT_DMA_BUF_OPS_UNPIN], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct dma_buf_ops *ptr = NULL; + ptr->unpin(NULL); + ],[ + AC_DEFINE(HAVE_STRUCT_DMA_BUF_OPS_UNPIN, 1, + [struct dma_buf_ops->unpin() is available]) + ]) + ]) +]) + + + + From 8a7ac1f89f9e0e9deaa2648382a956c36474c106 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 23 Aug 2021 12:46:55 +0800 Subject: [PATCH 0481/1868] drm/amdkcl: Test whether linux/pgtable.h is available This is caused by 3bf3710e3718 "drm/ttm: Add a generic TTM memcpy move for page-based iomem" v5.13-rc3-860-g3bf3710e3718 Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 6 ++++++ drivers/gpu/drm/ttm/ttm_module.c | 2 ++ 2 files changed, 8 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index 5c9cf41e67120..05687ebbd1ec7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -56,4 +56,10 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # drm/aperture: Add infrastructure for aperture ownership dnl # AC_KERNEL_CHECK_HEADERS([drm/drm_aperture.h]) + + dnl # + dnl # v5.7-13141-gca5999fde0a1 + dnl # mm: introduce include/linux/pgtable.h + dnl # + AC_KERNEL_CHECK_HEADERS([linux/pgtable.h]) ]) diff --git a/drivers/gpu/drm/ttm/ttm_module.c b/drivers/gpu/drm/ttm/ttm_module.c index b3fffe7b5062a..7e8366ece9d6d 100644 --- a/drivers/gpu/drm/ttm/ttm_module.c +++ b/drivers/gpu/drm/ttm/ttm_module.c @@ -31,7 +31,9 @@ */ #include #include +#ifdef HAVE_LINUX_PGTABLE_H #include +#endif #include #include #include From 2ef567321f2195b4ba38d3f984a6bd1fb47549ae Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 23 Aug 2021 14:20:05 +0800 Subject: [PATCH 0482/1868] drm/amdkcl: wrap the code under macro HAVE_DRM_DRIVER_RELEASE This is caused by 07775fc13878 "drm/amdgpu: Unmap all MMIO mappings" v5.13-rc1-246-g07775fc13878 Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 17c33193d645f..2d88ffef81c4c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -4462,7 +4462,11 @@ static void amdgpu_device_unmap_mmio(struct amdgpu_device *adev) { /* Clear all CPU mappings pointing to this device */ +#ifdef HAVE_DRM_DRIVER_RELEASE unmap_mapping_range(adev->ddev.anon_inode->i_mapping, 0, 0, 1); +#else + unmap_mapping_range(adev->ddev->anon_inode->i_mapping, 0, 0, 1); +#endif /* Unmap all mapped bars - Doorbell, registers and VRAM */ amdgpu_doorbell_fini(adev); From 7b78766a9902fdec78d17d5ecf425d4df6c9149b Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 23 Aug 2021 14:23:20 +0800 Subject: [PATCH 0483/1868] drm/amdkcl: wrap the code under macro HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index 5cf5133d793a7..b41baa440c5ee 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -328,6 +328,7 @@ static void amdgpu_gem_object_close(struct drm_gem_object *obj, drm_exec_fini(&exec); } +#ifndef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK static int amdgpu_gem_object_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma) { struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); @@ -348,6 +349,7 @@ static int amdgpu_gem_object_mmap(struct drm_gem_object *obj, struct vm_area_str return drm_gem_ttm_mmap(obj, vma); } +#endif #ifndef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK static const struct drm_gem_object_funcs amdgpu_gem_object_funcs = { From 190cb1c37d18f3c08973e94792ae905b97dfbdd9 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 24 Aug 2021 11:02:08 +0800 Subject: [PATCH 0484/1868] drm/amdkcl: adapt code for remove_conflicting_pci_framebuffers with argument numbers Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c | 6 +++ drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c | 40 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../m4/remove-conflicting-pci-framebuffers.m4 | 26 ++++++++++++ include/kcl/kcl_drm_fb.h | 14 +++++++ 5 files changed, 87 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/remove-conflicting-pci-framebuffers.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c index b3fa22920b7f2..99c29f3b4c803 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c @@ -126,7 +126,13 @@ int drm_aperture_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, const #ifdef HAVE_VGA_REMOVE_VGACON #if IS_REACHABLE(CONFIG_FB) + +#ifdef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_NO_RES_ID_ARG ret = remove_conflicting_pci_framebuffers(pdev, name); +#else + ret = remove_conflicting_pci_framebuffers(pdev, 0, name); +#endif + #endif if (ret == 0) ret = vga_remove_vgacon(pdev); diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c b/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c index 11a2fe7ab066e..18f2a20d821da 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c @@ -15,6 +15,44 @@ /* Copied from drivers/video/fbdev/core/fbmem.c and modified for KCL */ #if !defined(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS) + +#ifdef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_NO_RES_ID_ARG +int remove_conflicting_pci_framebuffers(struct pci_dev *pdev, const char *name) +{ + struct apertures_struct *ap; + bool primary = false; + int err, idx, bar; + + for (idx = 0, bar = 0; bar < PCI_STD_NUM_BARS; bar++) { + if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) + continue; + idx++; + } + + ap = alloc_apertures(idx); + if (!ap) + return -ENOMEM; + + for (idx = 0, bar = 0; bar < PCI_STD_NUM_BARS; bar++) { + if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) + continue; + ap->ranges[idx].base = pci_resource_start(pdev, bar); + ap->ranges[idx].size = pci_resource_len(pdev, bar); + pci_dbg(pdev, "%s: bar %d: 0x%lx -> 0x%lx\n", __func__, bar, + (unsigned long)pci_resource_start(pdev, bar), + (unsigned long)pci_resource_end(pdev, bar)); + idx++; + } + +#ifdef CONFIG_X86 + primary = pdev->resource[PCI_ROM_RESOURCE].flags & + IORESOURCE_ROM_SHADOW; +#endif + err = remove_conflicting_framebuffers(ap, name, primary); + kfree(ap); + return err; +} +#else /* HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_NO_RES_ID_ARG */ int remove_conflicting_pci_framebuffers(struct pci_dev *pdev, int res_id, const char *name) { struct apertures_struct *ap; @@ -39,5 +77,7 @@ int remove_conflicting_pci_framebuffers(struct pci_dev *pdev, int res_id, const kfree(ap); return err; } +#endif /* HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_NO_RES_ID_ARG */ + EXPORT_SYMBOL(remove_conflicting_pci_framebuffers); #endif diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 76eca8675a168..df00fec1429c1 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -166,6 +166,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DMA_BUF_UNPIN AC_AMDGPU_STRUCT_DMA_BUF_OPS_UNPIN AC_AMDGPU_DRM_CONNECTOR_STATE_HDR_OUTPUT_METADATA + AC_AMDGPU_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/remove-conflicting-pci-framebuffers.m4 b/drivers/gpu/drm/amd/dkms/m4/remove-conflicting-pci-framebuffers.m4 new file mode 100644 index 0000000000000..06241044fe4d4 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/remove-conflicting-pci-framebuffers.m4 @@ -0,0 +1,26 @@ +dnl # +dnl # v5.3-rc1-540-g0a8459693238 +dnl # fbdev: drop res_id parameter from remove_conflicting_pci_framebuffers +dnl # +AC_DEFUN([AC_AMDGPU_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + remove_conflicting_pci_framebuffers(NULL, NULL); + ],[ + AC_DEFINE(HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_NO_RES_ID_ARG, 1, + [remove_conflicting_pci_framebuffers() is available and doesn't have res_id arg]) + ],[ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + remove_conflicting_pci_framebuffers(NULL, 0, NULL); + ], [ + AC_DEFINE(HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_WITH_RES_ID_ARG, 1, + [remove_conflicting_pci_framebuffers() is available and has res_id arg]) + ]) + ]) + ]) +]) + diff --git a/include/kcl/kcl_drm_fb.h b/include/kcl/kcl_drm_fb.h index 2b90f5bcd8682..2e66b7b2aa2fa 100644 --- a/include/kcl/kcl_drm_fb.h +++ b/include/kcl/kcl_drm_fb.h @@ -77,14 +77,24 @@ __and(IS_MODULE(option), __is_defined(MODULE))) #endif /*IS_REACHABLE*/ +#ifdef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_NO_RES_ID_ARG +extern int remove_conflicting_pci_framebuffers(struct pci_dev *pdev, + const char *name); +#else extern int remove_conflicting_pci_framebuffers(struct pci_dev *pdev, int res_id, const char *name); +#endif + static inline int _kcl_drm_fb_helper_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, const char *name) { #if IS_REACHABLE(CONFIG_FB) +#ifdef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_NO_RES_ID_ARG + return remove_conflicting_pci_framebuffers(pdev, name); +#else return remove_conflicting_pci_framebuffers(pdev, 0, name); +#endif #else return 0; #endif @@ -94,7 +104,11 @@ static inline int _kcl_drm_fb_helper_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, const char *name) { +#ifdef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_WITH_RES_ID_ARG return drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, 0, name); +#else + return drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, name); +#endif } #endif /* HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS */ From bd1c906c4a6aeb78fdd91aed5a2f78d79dcf759f Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 24 Aug 2021 13:22:55 +0800 Subject: [PATCH 0485/1868] drm/amdkcl: fake drm_dev_{enter, exit, is_unplugged} for legacy os Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/Makefile | 3 +- drivers/gpu/drm/amd/amdkcl/kcl_drm_drv.c | 73 +++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/drm-dev-enter.m4 | 19 +++++ .../drm/amd/dkms/m4/drm-dev-is-unplugged.m4 | 21 ++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 + drivers/gpu/drm/ttm/backport/backport.h | 1 + include/kcl/kcl_drm_drv.h | 66 +++++++++++++++++ 8 files changed, 185 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_drv.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dev-enter.m4 create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dev-is-unplugged.m4 create mode 100644 include/kcl/kcl_drm_drv.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 662dbafdd44d2..a26c5110afa79 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -11,7 +11,8 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_drm_fb.o kcl_drm_print.o kcl_fbmem.o \ kcl_drm_crtc.o kcl_drm_connector.o kcl_drm_atomic_helper.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o kcl_ftrace.o \ - kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_fs_read_write.o kcl_drm_aperture.o + kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_fs_read_write.o kcl_drm_aperture.o \ + kcl_drm_drv.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_drv.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_drv.c new file mode 100644 index 0000000000000..8014069a7c654 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_drv.c @@ -0,0 +1,73 @@ +/* + * Created: Fri Jan 19 10:48:35 2001 by faith@acm.org + * + * Copyright 2001 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Author Rickard E. (Rik) Faith + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef HAVE_DRM_DEV_ENTER +#include +#include + +DEFINE_STATIC_SRCU(drm_unplug_srcu); + +/** + * drm_dev_enter - Enter device critical section + * @dev: DRM device + * @idx: Pointer to index that will be passed to the matching drm_dev_exit() + * + * This function marks and protects the beginning of a section that should not + * be entered after the device has been unplugged. The section end is marked + * with drm_dev_exit(). Calls to this function can be nested. + * + * Returns: + * True if it is OK to enter the section, false otherwise. + */ +bool drm_dev_enter(struct drm_device *dev, int *idx) +{ + *idx = srcu_read_lock(&drm_unplug_srcu); + + if (atomic_read(&dev->unplugged)) { + srcu_read_unlock(&drm_unplug_srcu, *idx); + return false; + } + + return true; +} +EXPORT_SYMBOL(drm_dev_enter); + +/** + * drm_dev_exit - Exit device critical section + * @idx: index returned from drm_dev_enter() + * + * This function marks the end of a section that should not be entered after + * the device has been unplugged. + */ +void drm_dev_exit(int idx) +{ + srcu_read_unlock(&drm_unplug_srcu, idx); +} +EXPORT_SYMBOL(drm_dev_exit); + +#endif /* HAVE_DRM_DEV_ENTER */ diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index e10a0d22ed94b..b2b923f962a40 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -51,6 +51,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dev-enter.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dev-enter.m4 new file mode 100644 index 0000000000000..4ac5579c0f5c2 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dev-enter.m4 @@ -0,0 +1,19 @@ +dnl # +dnl # commit bee330f3d67273a68dcb99f59480d59553c008b2 +dnl # drm: Use srcu to protect drm_device.unplugged +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DEV_ENTER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #ifdef HAVE_DRM_DRMP_H + #include + #else + #include + #endif + ], [ + drm_dev_enter(NULL, NULL); + ], [drm_dev_enter], [drivers/gpu/drm/drm_drv.c], [ + AC_DEFINE(HAVE_DRM_DEV_ENTER, 1, [drm_dev_enter() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dev-is-unplugged.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dev-is-unplugged.m4 new file mode 100644 index 0000000000000..4a05d157649e4 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dev-is-unplugged.m4 @@ -0,0 +1,21 @@ +dnl # +dnl # commit bee330f3d67273a68dcb99f59480d59553c008b2 +dnl # drm: Use srcu to protect drm_device.unplugged +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DEV_IS_UNPLUGGED], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DRMP_H + #include + #endif + #ifdef HAVE_DRM_DRM_DRV_H + #include + #endif + ], [ + drm_dev_is_unplugged(NULL); + ], [ + AC_DEFINE(HAVE_DRM_DEV_IS_UNPLUGGED, 1, + [drm_dev_is_unplugged() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index df00fec1429c1..77fe97289f048 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -167,6 +167,8 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_STRUCT_DMA_BUF_OPS_UNPIN AC_AMDGPU_DRM_CONNECTOR_STATE_HDR_OUTPUT_METADATA AC_AMDGPU_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS + AC_AMDGPU_DRM_DEV_ENTER + AC_AMDGPU_DRM_DEV_IS_UNPLUGGED AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index e6763a9dfb224..97ee04f8c9330 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include diff --git a/include/kcl/kcl_drm_drv.h b/include/kcl/kcl_drm_drv.h new file mode 100644 index 0000000000000..b4e923bfa1465 --- /dev/null +++ b/include/kcl/kcl_drm_drv.h @@ -0,0 +1,66 @@ +/* + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * Copyright (c) 2009-2010, Code Aurora Forum. + * Copyright 2016 Intel Corp. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef __KCL_KCL_DRM_DRV_H__ +#define __KCL_KCL_DRM_DRV_H__ + +#include +#include + +#ifndef HAVE_DRM_DEV_ENTER +/* Copied from include/drm/drm_drv.h*/ + +bool drm_dev_enter(struct drm_device *dev, int *idx); +void drm_dev_exit(int idx); + +#ifndef HAVE_DRM_DEV_IS_UNPLUGGED +/** + * drm_dev_is_unplugged - is a DRM device unplugged + * @dev: DRM device + * + * This function can be called to check whether a hotpluggable is unplugged. + * Unplugging itself is singalled through drm_dev_unplug(). If a device is + * unplugged, these two functions guarantee that any store before calling + * drm_dev_unplug() is visible to callers of this function after it completes + * + * WARNING: This function fundamentally races against drm_dev_unplug(). It is + * recommended that drivers instead use the underlying drm_dev_enter() and + * drm_dev_exit() function pairs. + */ +static inline bool drm_dev_is_unplugged(struct drm_device *dev) +{ + int idx; + + if (drm_dev_enter(dev, &idx)) { + drm_dev_exit(idx); + return false; + } + + return true; +} +#endif /* HAVE_DRM_DEV_IS_UNPLUGGED */ +#endif /* HAVE_DRM_DEV_ENTER */ + +#endif From 3a9dec97e127da8655955de37b6f7849f3e92455 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 24 Aug 2021 13:52:05 +0800 Subject: [PATCH 0486/1868] drm/amdkcl: replace dma_resv_get_list with dma_resv_shared_list Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/kcl_reservation.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_reservation.c b/drivers/gpu/drm/amd/amdkcl/kcl_reservation.c index 5bb5b8b68e64e..bad215a62e54d 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_reservation.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_reservation.c @@ -164,7 +164,7 @@ void _kcl_dma_resv_add_shared_fence(struct dma_resv *obj, struct dma_fence *fenc { struct dma_resv_list *old, *fobj = obj->staged; - old = dma_resv_get_list(obj); + old = dma_resv_shared_list(obj); obj->staged = NULL; if (!fobj) From 8ba2beb1a856bccfae6792d57a0f51571fbe3245 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 24 Aug 2021 17:29:29 +0800 Subject: [PATCH 0487/1868] drm/amdkcl: REWORKME: config.h Signed-off-by: Leslie Shi Change-Id: Id383189a33e53194d9b6f98879bf1e95a6987243 --- drivers/gpu/drm/amd/dkms/config/config.h | 41 +++++++++++++++++++----- 1 file changed, 33 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index b8d0184b66fa5..c517b7649bd82 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -76,6 +76,9 @@ /* dma_buf dynamic_mapping is available */ /* #undef HAVE_DMA_BUF_OPS_DYNAMIC_MAPPING */ +/* dma_buf_unpin() is available */ +#define HAVE_DMA_BUF_UNPIN 1 + /* whether dma_fence_get_stub exits */ #define HAVE_DMA_FENCE_GET_STUB 1 @@ -204,6 +207,9 @@ /* struct drm_connector_state has hdcp_content_type member */ #define HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE 1 +/* struct drm_connector_state has hdr_output_metadata member */ +#define HAVE_DRM_CONNECTOR_STATE_HDR_OUTPUT_METADATA 1 + /* drm_connector_unreference() is available */ /* #undef HAVE_DRM_CONNECTOR_UNREFERENCE */ @@ -243,6 +249,12 @@ /* drm_dev_dbg() is available */ #define HAVE_DRM_DEV_DBG 1 +/* drm_dev_enter() is available */ +#define HAVE_DRM_DEV_ENTER 1 + +/* drm_dev_is_unplugged() is availablea */ +#define HAVE_DRM_DEV_IS_UNPLUGGED 1 + /* drm_dev_put() is available */ #define HAVE_DRM_DEV_PUT 1 @@ -277,10 +289,10 @@ #define HAVE_DRM_DP_CEC_REGISTER_CONNECTOR_PP 1 /* drm_dp_link_train_channel_eq_delay() has 2 args */ -/* #undef HAVE_DRM_DP_LINK_TRAIN_CHANNEL_EQ_DELAY_2ARGS */ +#define HAVE_DRM_DP_LINK_TRAIN_CHANNEL_EQ_DELAY_2ARGS 1 /* drm_dp_link_train_clock_recovery_delay() has 2 args */ -/* #undef HAVE_DRM_DP_LINK_TRAIN_CLOCK_RECOVERY_DELAY_2ARGS */ +#define HAVE_DRM_DP_LINK_TRAIN_CLOCK_RECOVERY_DELAY_2ARGS 1 /* drm_dp_mst_add_affected_dsc_crtcs() is available */ #define HAVE_DRM_DP_MST_ADD_AFFECTED_DSC_CRTCS 1 @@ -476,9 +488,6 @@ /* ttm_buffer_object->base is available */ #define HAVE_DRM_GEM_OBJECT_RESV 1 -/* drm_gem_prime_mmap() is available */ -/* #undef HAVE_DRM_GEM_PRIME_MMAP */ - /* drm_gem_ttm_vmap() is available */ #define HAVE_DRM_GEM_TTM_VMAP 1 @@ -675,8 +684,8 @@ /* kernel_write() take arg type of position as pointer */ #define HAVE_KERNEL_WRITE_PPOS 1 -/* kmap_local_page_prot() is available */ -#define HAVE_KMAP_LOCAL_PAGE_PROT 1 +/* kmap_local_* is available */ +#define HAVE_KMAP_LOCAL 1 /* kref_read() function is available */ #define HAVE_KREF_READ 1 @@ -759,6 +768,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_PCI_P2PDMA_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_PGTABLE_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_LINUX_SCHED_MM_H 1 @@ -864,6 +876,13 @@ /* remove_conflicting_framebuffers() returns int */ #define HAVE_REMOVE_CONFLICTING_FRAMEBUFFERS_RETURNS_INT 1 +/* remove_conflicting_pci_framebuffers() is available and doesn't have res_id + arg */ +#define HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_NO_RES_ID_ARG 1 + +/* remove_conflicting_pci_framebuffers() is available and has res_id arg */ +/* #undef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_WITH_RES_ID_ARG */ + /* request_firmware_direct() is available */ #define HAVE_REQUEST_FIRMWARE_DIRECT 1 @@ -894,6 +913,9 @@ /* struct dma_buf_ops->pin() is available */ #define HAVE_STRUCT_DMA_BUF_OPS_PIN 1 +/* struct dma_buf_ops->unpin() is available */ +#define HAVE_STRUCT_DMA_BUF_OPS_UNPIN 1 + /* struct drm_connector_state->duplicated is available */ #define HAVE_STRUCT_DRM_ATOMIC_STATE_DUPLICATED 1 @@ -959,7 +981,7 @@ /* drm_plane_helper_funcs->atomic_check() second param wants drm_atomic_state arg */ -/* #undef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS */ +#define HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS 1 /* drm_plane_helper_funcs->prepare_fb() wants const p arg */ /* #undef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_PREPARE_FB_CONST */ @@ -991,6 +1013,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_UAPI_LINUX_SCHED_TYPES_H 1 +/* vga_remove_vgacon() is available */ +#define HAVE_VGA_REMOVE_VGACON 1 + /* vga_switcheroo_set_dynamic_switch() exist */ /* #undef HAVE_VGA_SWITCHEROO_SET_DYNAMIC_SWITCH */ From b5e5db323bea52f49d316509f9965838f42addc3 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 25 Aug 2021 10:25:27 +0800 Subject: [PATCH 0488/1868] drm/amdkcl: Test whether struct drm_device has pdev member This is caused by 5c0cd6459c5a "drm/amdkcl: init the ddev->pdev for legacy os" v5.13-2411-g5c0cd6459c5a Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 ++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../gpu/drm/amd/dkms/m4/drm-device-pdev.m4 | 19 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 25 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-device-pdev.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 7afaded24e86a..4967939195218 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2353,7 +2353,9 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, goto err_free; #endif +#ifdef HAVE_DRM_DEVICE_PDEV ddev->pdev = pdev; +#endif pci_set_drvdata(pdev, ddev); amdgpu_init_debug_options(adev); diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index c517b7649bd82..d5ac7494a44ac 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -246,6 +246,9 @@ /* drm_device->open_count is int */ /* #undef HAVE_DRM_DEVICE_OPEN_COUNT_INT */ +/* struct drm_device has pdev member */ +/* #undef HAVE_DRM_DEVICE_PDEV */ + /* drm_dev_dbg() is available */ #define HAVE_DRM_DEV_DBG 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-device-pdev.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-device-pdev.m4 new file mode 100644 index 0000000000000..25f5b1ca72eca --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-device-pdev.m4 @@ -0,0 +1,19 @@ +dnl # +dnl # commit b347e04452ff6382ace8fba9c81f5bcb63be17a6 +dnl # drm: Remove pdev field from struct drm_device +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DEVICE_PDEV], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DRMP_H + #include + #endif + #include + ], [ + struct drm_device *pdd = NULL; + pdd->pdev = NULL; + ], [ + AC_DEFINE(HAVE_DRM_DEVICE_PDEV, 1, [struct drm_device has pdev member]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 77fe97289f048..4cb5f8b5dd60d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -169,6 +169,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS AC_AMDGPU_DRM_DEV_ENTER AC_AMDGPU_DRM_DEV_IS_UNPLUGGED + AC_AMDGPU_DRM_DEVICE_PDEV AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 0dcd7f5042981c34c5f15d5a280eded3e8bf9d43 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 25 Aug 2021 10:43:19 +0800 Subject: [PATCH 0489/1868] drm/amdkcl: call dma_resv_init for legacy os This is caused by d02117f8efaa "drm/ttm: remove special handling for non GEM drivers" v5.12-rc3-374-gd02117f8efaa Signed-off-by: Leslie Shi --- drivers/gpu/drm/ttm/ttm_bo.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index ca42efa8a7ed8..d8defca9f3419 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -977,6 +977,11 @@ int ttm_bo_init_reserved(struct ttm_device *bdev, struct ttm_buffer_object *bo, amdkcl_ttm_resvp(bo) = resv; else amdkcl_ttm_resvp(bo) = &amdkcl_ttm_resv(bo); + +#ifndef HAVE_DRM_GEM_OBJECT_RESV + dma_resv_init(&amdkcl_ttm_resv(bo)); +#endif + atomic_inc(&ttm_glob.bo_count); /* From e040d1baca4be2dc1f5a4590eed459cf58549d9b Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 25 Aug 2021 14:05:33 +0800 Subject: [PATCH 0490/1868] drm/amdkcl: wrap the code under macro PCI_IRQ_MSI Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c index 19ce4da285e8d..8816017dc9e29 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c @@ -332,7 +332,11 @@ void amdgpu_irq_fini_hw(struct amdgpu_device *adev) free_irq(adev->irq.irq, adev_to_drm(adev)); adev->irq.installed = false; if (adev->irq.msi_enabled) +#ifdef PCI_IRQ_MSI pci_free_irq_vectors(adev->pdev); +#else + pci_disable_msi(adev->pdev); +#endif } amdgpu_ih_ring_fini(adev, &adev->irq.ih_soft); From fe81c233ccbe55d9e13cfd3090f2ed03765148d4 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 25 Aug 2021 14:08:04 +0800 Subject: [PATCH 0491/1868] drm/amdkcl: drop dma_resv rcu postfix This is caused by d3fae3b3daac "dma-buf: drop the _rcu postfix on function names v3" v5.13-rc3-854-gd3fae3b3daac Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index a0756e23ac83d..afa793b8681f7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -455,7 +455,7 @@ int amdgpu_crtc_page_flip(struct drm_crtc *crtc, goto unreserve; } - r = dma_resv_get_fences_rcu(amdkcl_ttm_resvp(&new_abo->tbo), &work->excl, + r = dma_resv_get_fences(amdkcl_ttm_resvp(&new_abo->tbo), &work->excl, &work->shared_count, &work->shared); if (unlikely(r != 0)) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index 664e7b211e0aa..7f672ab0ca9ee 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -844,7 +844,7 @@ int amdgpu_gem_prime_pin(struct drm_gem_object *obj) * Wait for all shared fences to complete before we switch to future * use of exclusive fence on this prime shared bo. */ - ret = dma_resv_wait_timeout_rcu(bo->tbo.resv, true, false, + ret = dma_resv_wait_timeout(bo->tbo.resv, true, false, MAX_SCHEDULE_TIMEOUT); if (unlikely(ret < 0)) { DRM_DEBUG_PRIME("Fence wait failed: %li\n", ret); From b6f0112d2ef446afbef7ec03a2616392e34d2ea4 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 25 Aug 2021 15:14:25 +0800 Subject: [PATCH 0492/1868] drm/amdkcl: add vma parameter for ttm_bo_vm_dummy_page() to adapt legacy os This is caused by 267d51d77fda "drm/ttm: Remap all page faults to per process dummy page." v5.13-rc1-231-g267d51d77fda Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 14 ++++++++++---- drivers/gpu/drm/ttm/ttm_bo_vm.c | 9 +++++++++ 2 files changed, 19 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index b41baa440c5ee..7f3f5f31c8672 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -48,9 +48,15 @@ void amdgpu_gem_object_free(struct drm_gem_object *gobj) #else static const struct drm_gem_object_funcs amdgpu_gem_object_funcs; +#ifndef HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG +static vm_fault_t amdgpu_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) +{ +#else static vm_fault_t amdgpu_gem_fault(struct vm_fault *vmf) { - struct ttm_buffer_object *bo = vmf->vma->vm_private_data; + struct vm_area_struct *vma = vmf->vma; +#endif + struct ttm_buffer_object *bo = vma->vm_private_data; struct drm_device *ddev = bo->base.dev; vm_fault_t ret; int idx; @@ -66,12 +72,12 @@ static vm_fault_t amdgpu_gem_fault(struct vm_fault *vmf) goto unlock; } - ret = ttm_bo_vm_fault_reserved(vmf, vmf->vma->vm_page_prot, - TTM_BO_VM_NUM_PREFAULT); + ret = ttm_bo_vm_fault_reserved(vmf, vma->vm_page_prot, + TTM_BO_VM_NUM_PREFAULT); drm_dev_exit(idx); } else { - ret = ttm_bo_vm_dummy_page(vmf, vmf->vma->vm_page_prot); + ret = ttm_bo_vm_dummy_page(vmf, vma->vm_page_prot); } if (ret == VM_FAULT_RETRY && !(vmf->flags & FAULT_FLAG_RETRY_NOWAIT)) return ret; diff --git a/drivers/gpu/drm/ttm/ttm_bo_vm.c b/drivers/gpu/drm/ttm/ttm_bo_vm.c index 71dc72ef19f3b..b5339205bdc9f 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_vm.c +++ b/drivers/gpu/drm/ttm/ttm_bo_vm.c @@ -314,9 +314,14 @@ static void ttm_bo_release_dummy_page(struct drm_device *dev, void *res) __free_page(dummy_page); } +#ifndef HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG +vm_fault_t ttm_bo_vm_dummy_page(struct vm_fault *vmf, struct vm_area_struct *vma, pgprot_t prot) +{ +#else vm_fault_t ttm_bo_vm_dummy_page(struct vm_fault *vmf, pgprot_t prot) { struct vm_area_struct *vma = vmf->vma; +#endif struct ttm_buffer_object *bo = vma->vm_private_data; struct drm_device *ddev = bo->base.dev; vm_fault_t ret = VM_FAULT_NOPAGE; @@ -378,7 +383,11 @@ vm_fault_t ttm_bo_vm_fault(struct vm_fault *vmf) #endif drm_dev_exit(idx); } else { +#ifndef HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG + ret = ttm_bo_vm_dummy_page(vmf, vma, prot); +#else ret = ttm_bo_vm_dummy_page(vmf, prot); +#endif } if (ret == VM_FAULT_RETRY && !(vmf->flags & FAULT_FLAG_RETRY_NOWAIT)) return ret; From 65c963991499ee2957e17f169ab82cd086aa8214 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 31 Aug 2021 11:52:31 +0800 Subject: [PATCH 0493/1868] drm/amdkcl: fake drm_gem_ttm_mmap function Signed-off-by: Leslie Shi --- .../include/kcl/kcl_drm_gem_ttm_helper.h | 10 +++++++++ .../drm/amd/backport/kcl_drm_gem_ttm_helper.c | 22 +++++++++++++++++++ 2 files changed, 32 insertions(+) diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_gem_ttm_helper.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_gem_ttm_helper.h index 10d002f55b191..e9d8d3fd9d9d8 100644 --- a/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_gem_ttm_helper.h +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_gem_ttm_helper.h @@ -34,4 +34,14 @@ void amdgpu_gem_object_close(struct drm_gem_object *obj, struct drm_file *file_priv); #endif +#ifndef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK +int _kcl_drm_gem_ttm_mmap(struct drm_gem_object *gem, + struct vm_area_struct *vma); +static inline +int drm_gem_ttm_mmap(struct drm_gem_object *gem, + struct vm_area_struct *vma) { + return _kcl_drm_gem_ttm_mmap(gem, vma); +} +#endif + #endif diff --git a/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c b/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c index 5acf8485888f7..b5fb22fa5a50a 100644 --- a/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c +++ b/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c @@ -38,3 +38,25 @@ void _kcl_drm_gem_ttm_vunmap(struct drm_gem_object *gem, } EXPORT_SYMBOL(_kcl_drm_gem_ttm_vunmap); #endif + +#ifndef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK +int _kcl_drm_gem_ttm_mmap(struct drm_gem_object *gem, + struct vm_area_struct *vma) { + + struct ttm_buffer_object *bo = drm_gem_ttm_of_gem(gem); + int ret; + + ret = ttm_bo_mmap_obj(vma, bo); + if (ret < 0) + return ret; + + /* + * ttm has its own object refcounting, so drop gem reference + * to avoid double accounting counting. + */ + drm_gem_object_put(gem); + + return 0; +} +EXPORT_SYMBOL(_kcl_drm_gem_ttm_mmap); +#endif From c2cf585614a39b368ba2f246cd15977731aa0ddf Mon Sep 17 00:00:00 2001 From: Eric Huang Date: Tue, 3 Aug 2021 14:44:31 -0400 Subject: [PATCH 0494/1868] drm/amdkfd: add parameter force in kfd_process_evict_queues It is to differenciate case scenario for proper behavior when calling evict queues, such as GPU reset doesn't need to roll back restoring partial evicted queues. Signed-off-by: Eric Huang Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 4 ++-- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 4 ++-- drivers/gpu/drm/amd/amdkfd/kfd_device.c | 8 ++++---- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 4 ++-- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 18 ++++++++++-------- 6 files changed, 21 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c index 20702e6a4c892..f048553e4cdf4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c @@ -252,7 +252,7 @@ void amdgpu_amdkfd_interrupt(struct amdgpu_device *adev, void amdgpu_amdkfd_suspend(struct amdgpu_device *adev, bool run_pm) { if (adev->kfd.dev) - kgd2kfd_suspend(adev->kfd.dev, run_pm); + kgd2kfd_suspend(adev->kfd.dev, run_pm, true); } int amdgpu_amdkfd_resume(struct amdgpu_device *adev, bool run_pm) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index 3c30ac61323e5..449d5c3da1da2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -456,7 +456,7 @@ struct kfd_dev *kgd2kfd_probe(struct amdgpu_device *adev, bool vf); bool kgd2kfd_device_init(struct kfd_dev *kfd, const struct kgd2kfd_shared_resources *gpu_resources); void kgd2kfd_device_exit(struct kfd_dev *kfd); -void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm); +void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm, bool force); int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm); int kgd2kfd_pre_reset(struct kfd_dev *kfd, struct amdgpu_reset_context *reset_context); @@ -493,7 +493,7 @@ static inline void kgd2kfd_device_exit(struct kfd_dev *kfd) { } -static inline void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm) +static inline void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm, bool force) { } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 01e4bbb539f57..1e4a9083a72fb 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -2633,7 +2633,7 @@ static int criu_restore(struct file *filep, * Set the process to evicted state to avoid running any new queues before all the memory * mappings are ready. */ - ret = kfd_process_evict_queues(p, KFD_QUEUE_EVICTION_CRIU_RESTORE); + ret = kfd_process_evict_queues(p, false, KFD_QUEUE_EVICTION_CRIU_RESTORE); if (ret) goto exit_unlock; @@ -2752,7 +2752,7 @@ static int criu_process_info(struct file *filep, goto err_unlock; } - ret = kfd_process_evict_queues(p, KFD_QUEUE_EVICTION_CRIU_CHECKPOINT); + ret = kfd_process_evict_queues(p, false, KFD_QUEUE_EVICTION_CRIU_CHECKPOINT); if (ret) goto err_unlock; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index cdd956b232a15..1bec162a30845 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -955,7 +955,7 @@ int kgd2kfd_pre_reset(struct kfd_dev *kfd, kfd_smi_event_update_gpu_reset(node, false, reset_context); } - kgd2kfd_suspend(kfd, false); + kgd2kfd_suspend(kfd, false, true); for (i = 0; i < kfd->num_nodes; i++) kfd_signal_reset_event(kfd->nodes[i]); @@ -1003,7 +1003,7 @@ bool kfd_is_locked(void) return (kfd_locked > 0); } -void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm) +void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm, bool force) { struct kfd_node *node; int i; @@ -1016,7 +1016,7 @@ void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm) mutex_lock(&kfd_processes_mutex); /* For first KFD device suspend all the KFD processes */ if (++kfd_locked == 1) - kfd_suspend_all_processes(); + kfd_suspend_all_processes(force); mutex_unlock(&kfd_processes_mutex); } @@ -1127,7 +1127,7 @@ int kgd2kfd_quiesce_mm(struct mm_struct *mm, uint32_t trigger) return -ESRCH; WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid); - r = kfd_process_evict_queues(p, trigger); + r = kfd_process_evict_queues(p, true, trigger); kfd_unref_process(p); return r; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 6e39058b90539..fcb6121ddf437 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -1104,9 +1104,9 @@ static inline struct kfd_process_device *kfd_process_device_from_gpuidx( } void kfd_unref_process(struct kfd_process *p); -int kfd_process_evict_queues(struct kfd_process *p, uint32_t trigger); +int kfd_process_evict_queues(struct kfd_process *p, bool force, uint32_t trigger); int kfd_process_restore_queues(struct kfd_process *p); -void kfd_suspend_all_processes(void); +void kfd_suspend_all_processes(bool force); int kfd_resume_all_processes(void); struct kfd_process_device *kfd_process_device_data_by_id(struct kfd_process *process, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 0bdeba89be480..74d7ec4f3e389 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -1947,9 +1947,9 @@ struct kfd_process *kfd_lookup_process_by_mm(const struct mm_struct *mm) * Eviction is reference-counted per process-device. This means multiple * evictions from different sources can be nested safely. */ -int kfd_process_evict_queues(struct kfd_process *p, uint32_t trigger) +int kfd_process_evict_queues(struct kfd_process *p, bool force, uint32_t trigger) { - int r = 0; + int r = 0, r_tmp = 0; int i; unsigned int n_evicted = 0; @@ -1960,15 +1960,17 @@ int kfd_process_evict_queues(struct kfd_process *p, uint32_t trigger) kfd_smi_event_queue_eviction(pdd->dev, p->lead_thread->pid, trigger); - r = pdd->dev->dqm->ops.evict_process_queues(pdd->dev->dqm, + r_tmp = pdd->dev->dqm->ops.evict_process_queues(pdd->dev->dqm, &pdd->qpd); /* evict return -EIO if HWS is hang or asic is resetting, in this case * we would like to set all the queues to be in evicted state to prevent * them been add back since they actually not be saved right now. */ - if (r && r != -EIO) { + if (r_tmp && r_tmp != -EIO) { dev_err(dev, "Failed to evict process queues\n"); - goto fail; + r = r_tmp; + if (!force) + goto fail; } n_evicted++; @@ -2172,7 +2174,7 @@ static void evict_process_worker(struct work_struct *work) p->last_evict_timestamp = get_jiffies_64(); pr_debug("Started evicting pasid 0x%x\n", p->pasid); - ret = kfd_process_evict_queues(p, KFD_QUEUE_EVICTION_TRIGGER_TTM); + ret = kfd_process_evict_queues(p, false, KFD_QUEUE_EVICTION_TRIGGER_TTM); if (!ret) { /* If another thread already signaled the eviction fence, * they are responsible stopping the queues and scheduling @@ -2253,7 +2255,7 @@ static void restore_process_worker(struct work_struct *work) } } -void kfd_suspend_all_processes(void) +void kfd_suspend_all_processes(bool force) { struct kfd_process *p; unsigned int temp; @@ -2261,7 +2263,7 @@ void kfd_suspend_all_processes(void) WARN(debug_evictions, "Evicting all processes"); hash_for_each_rcu(kfd_processes_table, temp, p, kfd_processes) { - if (kfd_process_evict_queues(p, KFD_QUEUE_EVICTION_TRIGGER_SUSPEND)) + if (kfd_process_evict_queues(p, force, KFD_QUEUE_EVICTION_TRIGGER_SUSPEND)) pr_err("Failed to suspend process 0x%x\n", p->pasid); signal_eviction_fence(p); } From 5754dfac43c2eabe1f1f030dd631914010a0d530 Mon Sep 17 00:00:00 2001 From: Mukul Joshi Date: Tue, 3 Aug 2021 16:10:43 -0400 Subject: [PATCH 0495/1868] drm/amdgpu: Fix bad page address calculation on Aldebaran Fix normalized address to physical address calculation during page retirement, by using the channel index table instead of channel instance. While at it, do general cleanup, use macros instead of function to fetch UMC instance and channel instance from MCA registers. Signed-off-by: Mukul Joshi Reviewed-by: John Clements --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index e1ea61eb4a9e1..27e4f6d902519 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -127,11 +127,6 @@ const char *get_ras_block_str(struct ras_common_if *ras_block) #define MAX_FLUSH_RETIRE_DWORK_TIMES 100 #ifdef HAVE_SMCA_UMC_V2 -#define GET_MCA_IPID_GPUID(m) (((m) >> 44) & 0xF) -#define GET_UMC_INST_NIBBLE(m) (((m) >> 20) & 0xF) -#define GET_CHAN_INDEX_NIBBLE(m) (((m) >> 12) & 0xF) -#define GPU_ID_OFFSET 8 - static bool notifier_registered = false; static void amdgpu_register_bad_pages_mca_notifier(void); #endif From 976ada7346df0f419ea6b4e942fe798c19603f63 Mon Sep 17 00:00:00 2001 From: Ramesh Errabolu Date: Wed, 4 Aug 2021 16:38:11 -0500 Subject: [PATCH 0496/1868] drm/amdkcl: Fix the macro for HAVE_STRUCT_DMA_BUF_OPS_ALLOW_PEER2PEER The code body that is used to determine if compile time macro HAVE_STRUCT_DMA_BUF_OPS_ALLOW_PEER2PEER should be enabled or not is incorrect. It references the wrong structure. The correct struct to reference is dma_buf_attach_ops not dma_buf_ops Signed-off-by: Ramesh Errabolu Reviewed-by: Flora Cui Change-Id: I735de6e7aa30ee86159b67846fa5b4de056375a8 --- drivers/gpu/drm/amd/dkms/config/config.h | 2 +- drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index d5ac7494a44ac..7594060ba31a2 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -911,7 +911,7 @@ #define HAVE_STRSCPY 1 /* struct dma_buf_ops->allow_peer2peer is available */ -/* #undef HAVE_STRUCT_DMA_BUF_OPS_ALLOW_PEER2PEER */ +#define HAVE_STRUCT_DMA_BUF_OPS_ALLOW_PEER2PEER 1 /* struct dma_buf_ops->pin() is available */ #define HAVE_STRUCT_DMA_BUF_OPS_PIN 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 index 3f408896f437b..e402bf57f2ec6 100644 --- a/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 @@ -7,12 +7,12 @@ AC_DEFUN([AC_AMDGPU_DMA_BUF], [ AC_KERNEL_TRY_COMPILE([ #include ],[ - struct dma_buf_ops *ptr = NULL; + struct dma_buf_attach_ops *ptr = NULL; ptr->allow_peer2peer = false; ],[ AC_DEFINE(HAVE_STRUCT_DMA_BUF_OPS_ALLOW_PEER2PEER, 1, - [struct dma_buf_ops->allow_peer2peer is available]) + [struct dma_buf_attach_ops->allow_peer2peer is available]) ],[ dnl # dnl # 4981cdb063e3 dma-buf: make move_notify mandatory if importer_ops are provided From a07f45d9beccadc9900ee1c20eb4927a48997998 Mon Sep 17 00:00:00 2001 From: Kent Russell Date: Thu, 12 Aug 2021 12:17:30 -0400 Subject: [PATCH 0497/1868] drm/amdkcl: Add XEC macro v2 v2: Change header from kcl_xec.h to kcl_mce.h Signed-off-by: Kent Russell Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_mce.h | 11 +++++++++++ 2 files changed, 12 insertions(+) create mode 100644 include/kcl/kcl_mce.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index b2b923f962a40..b9f8ad0f5d7f2 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -75,6 +75,7 @@ #include "kcl/kcl_amdgpu_drm_drv.h" #include "kcl/kcl_amdgpu_drm_gem.h" #include "kcl/kcl_drm_gem_ttm_helper.h" +#include "kcl/kcl_mce.h" #include "kcl/kcl_drm_aperture.h" #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_mce.h b/include/kcl/kcl_mce.h new file mode 100644 index 0000000000000..037fb0c1b3e37 --- /dev/null +++ b/include/kcl/kcl_mce.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_MCE_H +#define AMDKCL_MCE_H + +#include +/* Copied from asm/mce.h */ +#ifndef XEC +#define XEC(x, mask) (((x) >> 16) & mask) +#endif + +#endif From d29295dfa5094f5bf6d4b3bccf5ffeac070f1c07 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michel=20D=C3=A4nzer?= Date: Wed, 11 Aug 2021 18:52:11 +0200 Subject: [PATCH 0498/1868] drm/amdgpu: Use mod_delayed_work in JPEG/UVD/VCE/VCN ring_end_use hooks MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In contrast to schedule_delayed_work, this pushes back the work if it was already scheduled before. Specific behaviour change: Before: The scheduled work ran ~1 second after the first time ring_end_use was called, even if the ring was used again during that second. After: The scheduled work runs ~1 second after the last time ring_end_use is called. Inspired by the corresponding change in amdgpu_gfx_off_ctrl. While I haven't run into specific issues in this case, the new behaviour makes more sense to me. Signed-off-by: Michel Dänzer Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 2 +- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 2 +- 5 files changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index 449d5c3da1da2..84f396cedeef9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -34,6 +34,7 @@ #include #include #include +#include "amdgpu_gfx.h" #include "amdgpu_sync.h" #include "amdgpu_vm.h" #include "amdgpu_xcp.h" diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c index 6df99cb00d9a5..cae26cd9da733 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c @@ -140,7 +140,7 @@ void amdgpu_jpeg_ring_begin_use(struct amdgpu_ring *ring) void amdgpu_jpeg_ring_end_use(struct amdgpu_ring *ring) { atomic_dec(&ring->adev->jpeg.total_submission_cnt); - schedule_delayed_work(&ring->adev->jpeg.idle_work, JPEG_IDLE_TIMEOUT); + mod_delayed_work(system_wq, &ring->adev->jpeg.idle_work, JPEG_IDLE_TIMEOUT); } int amdgpu_jpeg_dec_ring_test_ring(struct amdgpu_ring *ring) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c index bd5e71c3fdb0f..b7a0be93bde7e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c @@ -1311,7 +1311,7 @@ void amdgpu_uvd_ring_begin_use(struct amdgpu_ring *ring) void amdgpu_uvd_ring_end_use(struct amdgpu_ring *ring) { if (!amdgpu_sriov_vf(ring->adev)) - schedule_delayed_work(&ring->adev->uvd.idle_work, UVD_IDLE_TIMEOUT); + mod_delayed_work(system_wq, &ring->adev->uvd.idle_work, UVD_IDLE_TIMEOUT); } /** diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c index 74fdbf71d95b7..9fe93826c23f9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c @@ -395,7 +395,7 @@ void amdgpu_vce_ring_begin_use(struct amdgpu_ring *ring) void amdgpu_vce_ring_end_use(struct amdgpu_ring *ring) { if (!amdgpu_sriov_vf(ring->adev)) - schedule_delayed_work(&ring->adev->vce.idle_work, VCE_IDLE_TIMEOUT); + mod_delayed_work(system_wq, &ring->adev->vce.idle_work, VCE_IDLE_TIMEOUT); } /** diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index a280b9fecb773..6d82504384e10 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c @@ -1873,7 +1873,7 @@ void vcn_v1_0_set_pg_for_begin_use(struct amdgpu_ring *ring, bool set_clocks) void vcn_v1_0_ring_end_use(struct amdgpu_ring *ring) { - schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT); + mod_delayed_work(system_wq, &ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT); mutex_unlock(&ring->adev->vcn.vcn1_jpeg1_workaround); } From 49ce38f44eb18d55dae6a224aab2720efc685664 Mon Sep 17 00:00:00 2001 From: Ramesh Errabolu Date: Thu, 12 Aug 2021 20:09:20 -0500 Subject: [PATCH 0499/1868] Use DMABUF for remote VRAM BOs only if CONFIG_PCI_P2PDMA is SET Without CONFIG_PCI_P2PDMA, pci_p2pdma_distance_many will always fail. This will cause DMABUF implementation to migrate VRAM BOs to GTT domain. Therefore, use DMABuf for remote VRAM mappings only if CONFIG_PCI_P2PDMA is enabled. Signed-off-by: Ramesh Errabolu Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index a4b50a5210b49..5bfd2fe253488 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -880,7 +880,7 @@ static int kfd_mem_attach_vram_bo(struct amdgpu_device *adev, { int ret = 0; -#ifdef CONFIG_DMABUF_MOVE_NOTIFY +#if defined(CONFIG_DMABUF_MOVE_NOTIFY) && defined(CONFIG_PCI_P2PDMA) attachment->type = KFD_MEM_ATT_DMABUF; ret = kfd_mem_attach_dmabuf(adev, mem, bo); pr_debug("Employ DMABUF mechanim to enable peer GPU access\n"); From c457e192e964faac0b96eb1cb57f1bd479c67c46 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 16 Aug 2021 17:04:36 +0800 Subject: [PATCH 0500/1868] drm/amdkcl: add DMA_FENCE_FLAG_USER_BITS macro This is caused by de7515d43659f852590645a688f8d493e4a18141 "drm/amd/amdgpu embed hw_fence into amdgpu_job" v5.13-2021-gde7515d43659 Signed-off-by: Asher Song Reviewed-by: Flora Cui --- include/kcl/kcl_fence.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/kcl/kcl_fence.h b/include/kcl/kcl_fence.h index 947efbf7e38aa..88a2d1a425ec2 100644 --- a/include/kcl/kcl_fence.h +++ b/include/kcl/kcl_fence.h @@ -27,6 +27,7 @@ #define DMA_FENCE_TRACE FENCE_TRACE #define DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT FENCE_FLAG_ENABLE_SIGNAL_BIT #define DMA_FENCE_FLAG_SIGNALED_BIT FENCE_FLAG_SIGNALED_BIT +#define DMA_FENCE_FLAG_USER_BITS FENCE_FLAG_USER_BITS #define dma_fence_wait fence_wait #define dma_fence_get fence_get #define dma_fence_put fence_put From 5dd5b492498925187a29dff1c9fc3a4a5a025062 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 26 Aug 2021 16:57:29 +0800 Subject: [PATCH 0501/1868] drm/amdkcl: wrap code under the macro HAVE_DRM_DISPLAY_INFO_MONITOR_RANGE this is caused by db060ba26e17250e66593d89907cad740f629e49 "drm/amd/display: Add emulated sink support for updating FS". v5.13-2101-gdb060ba26e17 Signed-off-by: Asher Song --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index b234d5a5724dd..3bc0c094727d2 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -12307,8 +12307,10 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, amdgpu_dm_connector->min_vfreq = 0; amdgpu_dm_connector->max_vfreq = 0; +#ifdef HAVE_DRM_DISPLAY_INFO_MONITOR_RANGE connector->display_info.monitor_range.min_vfreq = 0; connector->display_info.monitor_range.max_vfreq = 0; +#endif freesync_capable = false; goto update; From 1150f31d8f102ca32a42d6abc4002a60973a6a09 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 30 Aug 2021 14:29:55 +0800 Subject: [PATCH 0502/1868] drm/amdkcl: wrap code under the macro HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN It is caused by 00be4268d32c495798878c1b971a2e2fd18cf0d4 "drm/amd/display: Support for DMUB HPD interrupt handling" v5.13-2097-g00be4268d32c Signed-off-by: Asher Song Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 3bc0c094727d2..a5ad92c221756 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -763,7 +763,9 @@ static void dmub_hpd_callback(struct amdgpu_device *adev, struct amdgpu_dm_connector *aconnector; struct amdgpu_dm_connector *hpd_aconnector = NULL; struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif struct dc_link *link; u8 link_index = 0; struct drm_device *dev; @@ -784,9 +786,12 @@ static void dmub_hpd_callback(struct amdgpu_device *adev, link_index = notify->link_index; link = adev->dm.dc->links[link_index]; dev = adev->dm.ddev; - +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { +#else + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { +#endif if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) continue; @@ -805,7 +810,10 @@ static void dmub_hpd_callback(struct amdgpu_device *adev, break; } } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif + drm_modeset_unlock(&dev->mode_config.connection_mutex); if (hpd_aconnector) { if (notify->type == DMUB_NOTIFICATION_HPD) { From d9244adc398aaad709fe97aff454f49c8dc44861 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 1 Sep 2021 18:52:10 +0800 Subject: [PATCH 0503/1868] drm/amdkcl: add macro INTEL_FAM6_ROCKETLAKE It's caused by 857d1b24aa8d97a7e1cb50ed3b02773a159a8c4d "drm/amdgpu: Disable PCIE_DPM on Intel RKL Platform" v5.13-2160-g857d1b24aa8d Signed-off-by: Asher Song Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_intel_family.h | 12 ++++++++++++ 2 files changed, 13 insertions(+) create mode 100644 include/kcl/kcl_intel_family.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index b9f8ad0f5d7f2..db2ccf68b324d 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -77,5 +77,6 @@ #include "kcl/kcl_drm_gem_ttm_helper.h" #include "kcl/kcl_mce.h" #include "kcl/kcl_drm_aperture.h" +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_intel_family.h b/include/kcl/kcl_intel_family.h new file mode 100644 index 0000000000000..20781af676d6b --- /dev/null +++ b/include/kcl/kcl_intel_family.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_INTEL_FAMILY_H +#define AMDKCL_INTEL_FAMILY_H + +#include +/* Copied froma asm/intel-family.h*/ +#ifndef INTEL_FAM6_ROCKETLAKE +#define INTEL_FAM6_ROCKETLAKE 0xA7 +#endif + +#endif + From 6c60a222a62fdda608f66e7aa22bbbc5a368a54f Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Fri, 10 Sep 2021 10:50:25 +0800 Subject: [PATCH 0504/1868] drm/amdkcl: Avoid array out of bounds This is caused by bb892cd603b7 "drm/amdgpu: [hybrid] add direct gma(dgma) support" v5.13-2077-gbb892cd603b7 Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 8e8f0034ec6ce..876bdac748047 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -2129,6 +2129,7 @@ static int amdgpu_dgma_import_mgr_init(struct amdgpu_device *adev, uint64_t p_si spin_lock_init(&mgr->lock); atomic64_set(&mgr->available, p_size); + BUG_ON(AMDGPU_PL_DGMA_IMPORT >= TTM_NUM_MEM_TYPES); ttm_set_driver_manager(&adev->mman.bdev, AMDGPU_PL_DGMA_IMPORT, man); ttm_resource_manager_set_used(man, true); return 0; From 896001fb79e1eb1587ea15135fc455fe492a71a3 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 14 Sep 2021 10:20:43 +0800 Subject: [PATCH 0505/1868] drm/amdkcl: retain explicit creation and destruction of sysfs attributes for legacy os It's caused by 35bba8313b95a5cd074fc910a9c2670b4a1b105d "drm/amdgpu: Convert driver sysfs attributes to static attributes" v5.13-rc1-237-g35bba8313b95 Signed-off-by: Leslie Shi Reviewed-by: Flora Cui Change-Id: Id4d05534e1329859546cc642d0ee1536e47114b0 --- drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 16 +++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 23 ++++++++++++++++++- drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 18 +++++++++++++++ .../drm/amd/dkms/m4/pci-driver-dev-groups.m4 | 8 +++---- 5 files changed, 62 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c index 0c8975ac5af9e..5e2dab49f52e7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c @@ -1799,6 +1799,7 @@ static ssize_t amdgpu_atombios_get_vbios_version(struct device *dev, static DEVICE_ATTR(vbios_version, 0444, amdgpu_atombios_get_vbios_version, NULL); +#ifdef HAVE_PCI_DRIVER_DEV_GROUPS static struct attribute *amdgpu_vbios_version_attrs[] = { &dev_attr_vbios_version.attr, NULL @@ -1807,6 +1808,7 @@ static struct attribute *amdgpu_vbios_version_attrs[] = { const struct attribute_group amdgpu_vbios_version_attr_group = { .attrs = amdgpu_vbios_version_attrs }; +#endif int amdgpu_atombios_sysfs_init(struct amdgpu_device *adev) { @@ -1836,6 +1838,9 @@ void amdgpu_atombios_fini(struct amdgpu_device *adev) adev->mode_info.atom_context = NULL; kfree(adev->mode_info.atom_card_info); adev->mode_info.atom_card_info = NULL; +#ifndef HAVE_PCI_DRIVER_DEV_GROUPS + device_remove_file(adev->dev, &dev_attr_vbios_version); +#endif } /** @@ -1852,6 +1857,9 @@ int amdgpu_atombios_init(struct amdgpu_device *adev) { struct card_info *atom_card_info = kzalloc(sizeof(struct card_info), GFP_KERNEL); +#ifndef HAVE_PCI_DRIVER_DEV_GROUPS + int ret; +#endif if (!atom_card_info) return -ENOMEM; @@ -1883,6 +1891,14 @@ int amdgpu_atombios_init(struct amdgpu_device *adev) amdgpu_atombios_allocate_fb_scratch(adev); } +#ifndef HAVE_PCI_DRIVER_DEV_GROUPS + ret = device_create_file(adev->dev, &dev_attr_vbios_version); + if (ret) { + DRM_ERROR("Failed to create device file for VBIOS version\n"); + return ret; + } +#endif + return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 4967939195218..304344283edf1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3131,12 +3131,14 @@ static struct pci_error_handlers amdgpu_pci_err_handler = { .resume = amdgpu_pci_resume, }; +#ifdef HAVE_PCI_DRIVER_DEV_GROUPS static const struct attribute_group *amdgpu_sysfs_groups[] = { &amdgpu_vram_mgr_attr_group, &amdgpu_gtt_mgr_attr_group, &amdgpu_flash_attr_group, NULL, }; +#endif static struct pci_driver amdgpu_kms_pci_driver = { .name = DRIVER_NAME, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c index 0760e70402ec1..071241ccfb646 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c @@ -76,6 +76,7 @@ static DEVICE_ATTR(mem_info_gtt_total, S_IRUGO, static DEVICE_ATTR(mem_info_gtt_used, S_IRUGO, amdgpu_mem_info_gtt_used_show, NULL); +#ifdef HAVE_PCI_DRIVER_DEV_GROUPS static struct attribute *amdgpu_gtt_mgr_attributes[] = { &dev_attr_mem_info_gtt_total.attr, &dev_attr_mem_info_gtt_used.attr, @@ -85,6 +86,7 @@ static struct attribute *amdgpu_gtt_mgr_attributes[] = { const struct attribute_group amdgpu_gtt_mgr_attr_group = { .attrs = amdgpu_gtt_mgr_attributes }; +#endif /** * amdgpu_gtt_mgr_has_gart_addr - Check if mem has address space @@ -277,6 +279,9 @@ int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, uint64_t gtt_size) struct amdgpu_gtt_mgr *mgr = &adev->mman.gtt_mgr; struct ttm_resource_manager *man = &mgr->manager; uint64_t start, size; +#ifndef HAVE_PCI_DRIVER_DEV_GROUPS + int ret; +#endif man->use_tt = true; man->func = &amdgpu_gtt_mgr_func; @@ -288,6 +293,19 @@ int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, uint64_t gtt_size) drm_mm_init(&mgr->mm, start, size); spin_lock_init(&mgr->lock); +#ifndef HAVE_PCI_DRIVER_DEV_GROUPS + ret = device_create_file(adev->dev, &dev_attr_mem_info_gtt_total); + if (ret) { + DRM_ERROR("Failed to create device file mem_info_gtt_total\n"); + return ret; + } + ret = device_create_file(adev->dev, &dev_attr_mem_info_gtt_used); + if (ret) { + DRM_ERROR("Failed to create device file mem_info_gtt_used\n"); + return ret; + } +#endif + ttm_set_driver_manager(&adev->mman.bdev, TTM_PL_TT, &mgr->manager); ttm_resource_manager_set_used(man, true); return 0; @@ -316,7 +334,10 @@ void amdgpu_gtt_mgr_fini(struct amdgpu_device *adev) spin_lock(&mgr->lock); drm_mm_takedown(&mgr->mm); spin_unlock(&mgr->lock); - +#ifndef HAVE_PCI_DRIVER_DEV_GROUPS + device_remove_file(adev->dev, &dev_attr_mem_info_gtt_total); + device_remove_file(adev->dev, &dev_attr_mem_info_gtt_used); +#endif ttm_resource_manager_cleanup(man); ttm_set_driver_manager(&adev->mman.bdev, TTM_PL_TT, NULL); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c index 7d26a962f811c..52ffa82db94df 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c @@ -214,7 +214,11 @@ static DEVICE_ATTR(mem_info_vis_vram_used, S_IRUGO, static DEVICE_ATTR(mem_info_vram_vendor, S_IRUGO, amdgpu_mem_info_vram_vendor, NULL); +#ifdef HAVE_PCI_DRIVER_DEV_GROUPS static struct attribute *amdgpu_vram_mgr_attributes[] = { +#else +static const struct attribute *amdgpu_vram_mgr_attributes[] = { +#endif &dev_attr_mem_info_vram_total.attr, &dev_attr_mem_info_vis_vram_total.attr, &dev_attr_mem_info_vram_used.attr, @@ -223,6 +227,7 @@ static struct attribute *amdgpu_vram_mgr_attributes[] = { NULL }; +#ifdef HAVE_PCI_DRIVER_DEV_GROUPS static umode_t amdgpu_vram_attrs_is_visible(struct kobject *kobj, struct attribute *attr, int i) { @@ -241,6 +246,7 @@ const struct attribute_group amdgpu_vram_mgr_attr_group = { .attrs = amdgpu_vram_mgr_attributes, .is_visible = amdgpu_vram_attrs_is_visible }; +#endif /** * amdgpu_vram_mgr_vis_size - Calculate visible block size @@ -907,6 +913,9 @@ int amdgpu_vram_mgr_init(struct amdgpu_device *adev) struct amdgpu_vram_mgr *mgr = &adev->mman.vram_mgr; struct ttm_resource_manager *man = &mgr->manager; int err; +#ifndef HAVE_PCI_DRIVER_DEV_GROUPS + int ret; +#endif ttm_resource_manager_init(man, &adev->mman.bdev, adev->gmc.real_vram_size); @@ -915,6 +924,12 @@ int amdgpu_vram_mgr_init(struct amdgpu_device *adev) INIT_LIST_HEAD(&mgr->reservations_pending); INIT_LIST_HEAD(&mgr->reserved_pages); mgr->default_page_size = PAGE_SIZE; +#ifndef HAVE_PCI_DRIVER_DEV_GROUPS + /* Add the two VRAM-related sysfs files */ + ret = sysfs_create_files(&adev->dev->kobj, amdgpu_vram_mgr_attributes); + if (ret) + DRM_ERROR("Failed to register sysfs\n"); +#endif if (!adev->gmc.is_app_apu) { man->func = &amdgpu_vram_mgr_func; @@ -965,6 +980,9 @@ void amdgpu_vram_mgr_fini(struct amdgpu_device *adev) drm_buddy_fini(&mgr->mm); mutex_unlock(&mgr->lock); +#ifndef HAVE_PCI_DRIVER_DEV_GROUPS + sysfs_remove_files(&adev->dev->kobj, amdgpu_vram_mgr_attributes); +#endif ttm_resource_manager_cleanup(man); ttm_set_driver_manager(&adev->mman.bdev, TTM_PL_VRAM, NULL); } diff --git a/drivers/gpu/drm/amd/dkms/m4/pci-driver-dev-groups.m4 b/drivers/gpu/drm/amd/dkms/m4/pci-driver-dev-groups.m4 index 7a673c73d6b1c..dfb7bd92cade1 100644 --- a/drivers/gpu/drm/amd/dkms/m4/pci-driver-dev-groups.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/pci-driver-dev-groups.m4 @@ -4,12 +4,12 @@ dnl # PCI: Add support for dev_groups to struct pci_driver dnl # AC_DEFUN([AC_AMDGPU_PCI_DRIVER_DEV_GROUPS], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE_SYMBOL([ + AC_KERNEL_TRY_COMPILE([ #include ], [ - struct pci_driver pd; - pd.dev_groups = NULL; - ], [], [], [ + struct pci_driver *pd = NULL; + pd->dev_groups = NULL; + ], [ AC_DEFINE(HAVE_PCI_DRIVER_DEV_GROUPS, 1, [struct pci_driver has field dev_groups]) ]) ]) From 68db89d7bd2e379d0f95b5698696686fb4da09ef Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 15 Sep 2021 10:22:22 +0800 Subject: [PATCH 0506/1868] drm/amdkcl: update config.h Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/dkms/config/config.h | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 7594060ba31a2..0fa6ca4093282 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -11,7 +11,7 @@ #define HAVE_ACCESS_OK_WITH_TWO_ARGUMENTS 1 /* acpi_put_table() is available */ -/* #undef HAVE_ACPI_PUT_TABLE */ +#define HAVE_ACPI_PUT_TABLE 1 /* struct acpi_srat_generic_affinity is available */ #define HAVE_ACPI_SRAT_GENERIC_AFFINITY 1 @@ -29,7 +29,7 @@ #define HAVE_AMD_IOMMU_INVALIDATE_CTX_PASID_U32 1 /* amd_iommu_pc_supported() is available */ -/* #undef HAVE_AMD_IOMMU_PC_SUPPORTED */ +#define HAVE_AMD_IOMMU_PC_SUPPORTED 1 /* arch_io_{reserve/free}_memtype_wc() are available */ #define HAVE_ARCH_IO_RESERVE_FREE_MEMTYPE_WC 1 @@ -65,7 +65,7 @@ /* #undef HAVE_DEVM_MEMREMAP_PAGES_P_P_P_P */ /* dev_pagemap->owner is available */ -#define HAVE_DEV_PAGEMAP_OWNER 1 +/* #undef HAVE_DEV_PAGEMAP_OWNER */ /* there is 'range' field within dev_pagemap structure */ #define HAVE_DEV_PAGEMAP_RANGE 1 @@ -170,10 +170,10 @@ #define HAVE_DRM_COLOR_LUT_SIZE 1 /* drm_connector_atomic_hdr_metadata_equal() is available */ -/* #undef HAVE_DRM_CONNECTOR_ATOMIC_HDR_METADATA_EQUAL */ +#define HAVE_DRM_CONNECTOR_ATOMIC_HDR_METADATA_EQUAL 1 /* drm_connector_attach_hdr_output_metadata_property() is available */ -/* #undef HAVE_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY */ +#define HAVE_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY 1 /* drm_connector_for_each_possible_encoder() wants 2 arguments */ #define HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS 1 @@ -255,7 +255,7 @@ /* drm_dev_enter() is available */ #define HAVE_DRM_DEV_ENTER 1 -/* drm_dev_is_unplugged() is availablea */ +/* drm_dev_is_unplugged() is available */ #define HAVE_DRM_DEV_IS_UNPLUGGED 1 /* drm_dev_put() is available */ @@ -672,6 +672,9 @@ /* io_mapping_map_local_wc() is available */ #define HAVE_IO_MAPPING_MAP_LOCAL_WC 1 +/* io_mapping_map_wc() has size argument */ +#define HAVE_IO_MAPPING_MAP_WC_HAS_SIZE_ARG 1 + /* io_mapping_unmap_local() is available */ #define HAVE_IO_MAPPING_UNMAP_LOCAL 1 @@ -802,7 +805,7 @@ #define HAVE_MEM_ENCRYPT_ACTIVE 1 /* migrate_vma->pgmap_owner is available */ -#define HAVE_MIGRATE_VMA_PGMAP_OWNER 1 +/* #undef HAVE_MIGRATE_VMA_PGMAP_OWNER */ /* mmgrab() is available */ #define HAVE_MMGRAB 1 @@ -984,7 +987,7 @@ /* drm_plane_helper_funcs->atomic_check() second param wants drm_atomic_state arg */ -#define HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS 1 +/* #undef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS */ /* drm_plane_helper_funcs->prepare_fb() wants const p arg */ /* #undef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_PREPARE_FB_CONST */ @@ -1052,6 +1055,9 @@ /* wait_queue_entry_t exists */ #define HAVE_WAIT_QUEUE_ENTRY 1 +/* is_device_page is available */ +/* #undef HAVE_ZONE_DEVICE_PUBLIC */ + /* zone_managed_pages() is available */ #define HAVE_ZONE_MANAGED_PAGES 1 From 9a4a322386fefa0c3b8a9fced807eb1689d9f921 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 15 Sep 2021 10:20:41 +0800 Subject: [PATCH 0507/1868] drm/amdkcl: fix test for is_cow_mapping Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/dkms/m4/is_cow_mapping.m4 | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/is_cow_mapping.m4 b/drivers/gpu/drm/amd/dkms/m4/is_cow_mapping.m4 index c0bf84f081f2a..116779b2674f0 100644 --- a/drivers/gpu/drm/amd/dkms/m4/is_cow_mapping.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/is_cow_mapping.m4 @@ -1,10 +1,10 @@ dnl # -dnl # commit 97a7e4733b9b221d012ae68fcd3b3251febf6341 +dnl # commit v5.12-rc2-346-g97a7e4733b9b dnl # mm: introduce page_needs_cow_for_dma() for deciding whether cow dnl # AC_DEFUN([AC_AMDGPU_IS_COW_MAPPING], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE_SYMBOL([ + AC_KERNEL_TRY_COMPILE([ #include ], [ is_cow_mapping(VM_SHARED); From 097e3a898eeb5bf326a75ed520c97eb4c7f3a6c4 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 15 Sep 2021 15:59:24 +0800 Subject: [PATCH 0508/1868] drm/amdkcl: fix test for drm_plane_helper_funcs->atomic_check() Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/dkms/config/config.h | 2 +- drivers/gpu/drm/amd/dkms/m4/struct_drm_plane_helper_funcs.m4 | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 0fa6ca4093282..52bb9db3ef526 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -987,7 +987,7 @@ /* drm_plane_helper_funcs->atomic_check() second param wants drm_atomic_state arg */ -/* #undef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS */ +#define HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS 1 /* drm_plane_helper_funcs->prepare_fb() wants const p arg */ /* #undef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_PREPARE_FB_CONST */ diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_plane_helper_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_plane_helper_funcs.m4 index 68b8e02668cae..59fe64ed86c35 100644 --- a/drivers/gpu/drm/amd/dkms/m4/struct_drm_plane_helper_funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_plane_helper_funcs.m4 @@ -25,7 +25,7 @@ AC_DEFUN([AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_ #include ], [ struct drm_plane_helper_funcs *funcs = NULL; - funcs->atomic_check((struct drm_crtc *)NULL, (struct drm_atomic_state *)NULL); + funcs->atomic_check(NULL, (struct drm_atomic_state *)NULL); ], [ AC_DEFINE(HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS, 1, [drm_plane_helper_funcs->atomic_check() second param wants drm_atomic_state arg]) From 91b7f00f23ef6280369037610852f8e49e690f6a Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 15 Sep 2021 15:38:20 +0800 Subject: [PATCH 0509/1868] drm/amdkcl: fix test for amd_iommu_pc_xxx Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdkfd/kfd_topology.h | 6 ----- drivers/gpu/drm/amd/dkms/config/config.h | 6 +++++ .../drm/amd/dkms/m4/amd-iommu-pc-supported.m4 | 27 +++++++++++++++++-- 3 files changed, 31 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h index 924534289b0a2..d83a41dce7d60 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h @@ -190,10 +190,4 @@ struct kfd_topology_device *kfd_create_topology_device( struct list_head *device_list); void kfd_release_topology_device_list(struct list_head *device_list); -#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED -extern bool amd_iommu_pc_supported(void); -extern u8 amd_iommu_pc_get_max_banks(u16 devid); -extern u8 amd_iommu_pc_get_max_counters(u16 devid); -#endif - #endif /* __KFD_TOPOLOGY_H__ */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 52bb9db3ef526..b7b1007ab10e5 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -28,6 +28,12 @@ /* amd_iommu_invalidate_ctx take arg type of pasid as u32 */ #define HAVE_AMD_IOMMU_INVALIDATE_CTX_PASID_U32 1 +/* amd_iommu_pc_get_max_banks() declared */ +#define HAVE_AMD_IOMMU_PC_GET_MAX_BANKS_DECLARED 1 + +/* amd_iommu_pc_get_max_banks() arg is unsigned int */ +/* #undef HAVE_AMD_IOMMU_PC_GET_MAX_BANKS_UINT */ + /* amd_iommu_pc_supported() is available */ #define HAVE_AMD_IOMMU_PC_SUPPORTED 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/amd-iommu-pc-supported.m4 b/drivers/gpu/drm/amd/dkms/m4/amd-iommu-pc-supported.m4 index 27bed9e6beb3b..67cbbec8cac3e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/amd-iommu-pc-supported.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/amd-iommu-pc-supported.m4 @@ -1,5 +1,27 @@ dnl # -dnl # commit 30861ddc9cca479a7fc6a5efef4e5c69d6b274f4 +dnl # v5.12-rc3-5-gfc1b6620501f iommu/amd: Move a few prototypes to include/linux/amd-iommu.h +dnl # v5.12-rc3-4-gb29a1fc7595a iommu/amd: Remove a few unused exports +dnl # v4.11-rc4-171-gf5863a00e73c x86/events/amd/iommu.c: Modify functions to query max banks and counters +dnl # +AC_DEFUN([AC_AMDGPU_AMD_IOMMU_PC_GET_MAX_BANKS], [ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + amd_iommu_pc_get_max_banks(0); + ], [ + AC_DEFINE(HAVE_AMD_IOMMU_PC_GET_MAX_BANKS_DECLARED, 1, + [amd_iommu_pc_get_max_banks() declared]) + ], [ + AC_KERNEL_CHECK_SYMBOL_EXPORT([get_amd_iommu], + [drivers/iommu/amd/init.c], [ + AC_DEFINE(HAVE_AMD_IOMMU_PC_GET_MAX_BANKS_UINT, 1, + [amd_iommu_pc_get_max_banks() arg is unsigned int]) + ]) + ]) +]) + +dnl # +dnl # commit v3.10-rc3-89-g30861ddc9cca dnl # perf/x86/amd: Add IOMMU Performance Counter resource management dnl # AC_DEFUN([AC_AMDGPU_AMD_IOMMU_PC_SUPPORTED], [ @@ -10,9 +32,10 @@ AC_DEFUN([AC_AMDGPU_AMD_IOMMU_PC_SUPPORTED], [ #ifndef CONFIG_AMD_IOMMU #error CONFIG_AMD_IOMMU not enabled #endif - ], [amd_iommu_pc_supported], [drivers/iommu/amd_iommu_init.c], [ + ], [amd_iommu_pc_supported], [drivers/iommu/amd/init.c], [ AC_DEFINE(HAVE_AMD_IOMMU_PC_SUPPORTED, 1, [amd_iommu_pc_supported() is available]) + AC_AMDGPU_AMD_IOMMU_PC_GET_MAX_BANKS ]) ]) ]) From a8f0c1b6ace911dee5bc10719d297ea8cf75d3d6 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 10 Sep 2021 11:44:49 +0800 Subject: [PATCH 0510/1868] drm/amdkcl: fake a dummy mmput_async v2: fix the missing ; HAVE_MMPUT_ASYNC must be defined for monolithic build Signed-off-by: Flora Cui Reviewed-and-tested-by: Jonathan Kim --- drivers/gpu/drm/amd/amdkcl/kcl_mm.c | 13 +++++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/mmput_async.m4 | 12 ++++++++++++ include/kcl/backport/kcl_mm_backport.h | 4 ++++ include/kcl/kcl_mm.h | 4 ++++ 6 files changed, 37 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/mmput_async.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_mm.c b/drivers/gpu/drm/amd/amdkcl/kcl_mm.c index e60ac00cba573..9d7534002b7e1 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_mm.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_mm.c @@ -6,6 +6,19 @@ */ #include +#ifndef HAVE_MMPUT_ASYNC +void (*_kcl_mmput_async)(struct mm_struct *mm); +EXPORT_SYMBOL(_kcl_mmput_async); + +void __kcl_mmput_async(struct mm_struct *mm) +{ + pr_warn_once("This kernel version not support API: mmput_async !\n"); +} +#endif + void amdkcl_mm_init(void) { +#ifndef HAVE_MMPUT_ASYNC + _kcl_mmput_async = amdkcl_fp_setup("mmput_async", __kcl_mmput_async); +#endif } diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index b7b1007ab10e5..3bf2610fde6a4 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -816,6 +816,9 @@ /* mmgrab() is available */ #define HAVE_MMGRAB 1 +/* mmput_async() is available */ +#define HAVE_MMPUT_ASYNC 1 + /* mmu_notifier_call_srcu() is available */ /* #undef HAVE_MMU_NOTIFIER_CALL_SRCU */ diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 4cb5f8b5dd60d..b14d290a3674b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -149,6 +149,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_ACPI_SRAT_GENERIC_AFFINITY AC_AMDGPU_KERNEL_WRITE AC_AMDGPU_STRUCT_XARRAY + AC_AMDGPU_MMPUT_ASYNC AC_AMDGPU_DRM_MEMCPY_FROM_WC AC_AMDGPU_IS_COW_MAPPING AC_AMDGPU_VGA_REMOVE_VGACON diff --git a/drivers/gpu/drm/amd/dkms/m4/mmput_async.m4 b/drivers/gpu/drm/amd/dkms/m4/mmput_async.m4 new file mode 100644 index 0000000000000..2c8863597781f --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/mmput_async.m4 @@ -0,0 +1,12 @@ +dnl # +dnl # v4.14-rc3-117-ga1b2289cef92 android: binder: drop lru lock in isolate callback +dnl # v4.13-4372-g212925802454 mm: oom: let oom_reap_task and exit_mmap run concurrently +dnl # v4.6-6601-gec8d7c14ea14 mm, oom_reaper: do not mmput synchronously from the oom reaper context +dnl # +AC_DEFUN([AC_AMDGPU_MMPUT_ASYNC], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([mmput_async], [kernel/fork.c], [ + AC_DEFINE(HAVE_MMPUT_ASYNC, 1, [mmput_async() is available]) + ]) + ]) +]) diff --git a/include/kcl/backport/kcl_mm_backport.h b/include/kcl/backport/kcl_mm_backport.h index 3fc317a922a8d..48312d64e5869 100644 --- a/include/kcl/backport/kcl_mm_backport.h +++ b/include/kcl/backport/kcl_mm_backport.h @@ -5,6 +5,10 @@ #include #include +#ifndef HAVE_MMPUT_ASYNC +#define mmput_async _kcl_mmput_async +#endif + #ifdef get_user_pages_remote #undef get_user_pages_remote #endif diff --git a/include/kcl/kcl_mm.h b/include/kcl/kcl_mm.h index be023c0b95edd..57b2ee1fcb846 100644 --- a/include/kcl/kcl_mm.h +++ b/include/kcl/kcl_mm.h @@ -22,6 +22,10 @@ #define untagged_addr(addr) (addr) #endif +#ifndef HAVE_MMPUT_ASYNC +extern void (*_kcl_mmput_async)(struct mm_struct *mm); +#endif + #ifndef HAVE_FAULT_FLAG_ALLOW_RETRY_FIRST static inline bool fault_flag_allow_retry_first(unsigned int flags) { From 231e450cb0e0b18ceca066675fd02c6354c33d8a Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 22 Sep 2021 15:54:28 +0800 Subject: [PATCH 0511/1868] drm/amdkcl: wrap code under macro HAVE_DOWN_WRITE_KILLABLE It's caused by 3e563486be3ca0c716f6ac1b888eef59626d72fe "drm/amdgpu: Fix a race of IB test" v5.13-2444-g3e563486be3c Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c index c44a3e2b03625..d4a791c442adf 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c @@ -1689,9 +1689,13 @@ static int amdgpu_debugfs_test_ib_show(struct seq_file *m, void *unused) } /* Avoid accidently unparking the sched thread during GPU reset */ +#ifndef HAVE_DOWN_WRITE_KILLABLE + down_write(&adev->reset_domain->sem); +#else r = down_write_killable(&adev->reset_domain->sem); if (r) return r; +#endif /* hold on the scheduler */ for (i = 0; i < AMDGPU_MAX_RINGS; i++) { From dc308ca603bb5f40404dea1f3f8c5368cd234c9c Mon Sep 17 00:00:00 2001 From: Jingwen Chen Date: Tue, 7 Sep 2021 11:12:06 +0800 Subject: [PATCH 0512/1868] drm/amd/amdgpu: use ordered workqueue for tdr in SRIOV [Why] When two job timedout happens during a very close time, the job bailing will happen. As drm scheduler will delete the bad job from pending list when entering the tdr and add it back when calling drm_sched_stop during tdr handling, the bailing job will be deleted from pending list but it will directly return before calling drm_sched_stop as the first job has already sets the in_gpu_reset. So this bailing job will not be added back ever. And this can lead to this job never be finished. [How] 1. Use an ordered_workqueue as the timeout_wq for all tdr. As there will only be one tdr work at the same time, the bailing will never happen. 2. Use mdelay in sriov flr work to make sure the polling flr won't exceeds the default ring timeout. v2: Add detailed description. Use gpu_recovery=2 for SRIOV v3: split recovery mode and mdelay into seperate patch Based on: https://patchwork.freedesktop.org/patch/msgid/20210630062751.2832545-3-boris.brezillon@collabora.com Signed-off-by: Jingwen Chen Acked-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 ++++++ 2 files changed, 7 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 6f91ae1a44e65..98eaea4cd1ffe 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -996,6 +996,7 @@ struct amdgpu_device { bool ib_pool_ready; struct amdgpu_sa_manager ib_pools[AMDGPU_IB_POOL_MAX]; struct amdgpu_sched gpu_sched[AMDGPU_HW_IP_NUM][AMDGPU_RING_PRIO_MAX]; + struct workqueue_struct *timeout_wq; /* interrupts */ struct amdgpu_irq irq; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 2d88ffef81c4c..a47dd8dd18e36 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -4312,6 +4312,12 @@ int amdgpu_device_init(struct amdgpu_device *adev, /* init the mode config */ drm_mode_config_init(adev_to_drm(adev)); + if (amdgpu_sriov_vf(adev)) { + adev->timeout_wq = alloc_ordered_workqueue("amdgpu_ring_timeout_wq", 0); + if (!adev->timeout_wq) + dev_warn(adev->dev, "alloc_ordered_workqueue failed\n"); + } + r = amdgpu_device_ip_init(adev); if (r) { dev_err(adev->dev, "amdgpu_device_ip_init failed\n"); From 1546251bc05e36eab94cf552b612eb07fc92b237 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 11 Oct 2023 16:48:10 +0800 Subject: [PATCH 0513/1868] drm/amdkcl: Resolve target kernel 4.14 amdgpu_dm build issue invalid operands to binary - (have 'struct timeval' and 'ktime_t' {aka long long int}') frame_duration = vblank->time - previous_timestamp; incompatible type for argument 2 of 'atomic64_set' atomic64_set(irq_params->previous_timestamp, vblank->time) v2: create separated KCL macro for vblank field time of type ktime_t or timeval v3: fix typo in new m4 configuration v4: use initialized variable in m4 configuration file Signed-off-by: Nikola Prica Reviewed-by: Flora Cui Signed-off-by: Ma Jun Change-Id: I539392044b24600278315f09323974dc0ef36ba7 Signed-off-by: Asher Song --- .../gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h | 11 +++++++++++ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 12 ++++++++++-- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../dkms/m4/drm_vblank_use_ktime_t_time_field.m4 | 15 +++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 5 files changed, 40 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_vblank_use_ktime_t_time_field.m4 diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h index 383d7ec209af1..825228898e963 100644 --- a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h @@ -89,4 +89,15 @@ static inline int kcl_amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, un #endif /* HAVE_DRM_DRIVER_GET_VBLANK_TIMESTAMP_USE_KTIMER_T_ARG */ #endif /* HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP */ +#if defined(HAVE_DRM_VBLANK_USE_KTIME_T) +static inline ktime_t kcl_amdgpu_get_vblank_time_ns(struct drm_vblank_crtc *vblank) { + return vblank->time; +} +#else +static inline ktime_t kcl_amdgpu_get_vblank_time_ns(struct drm_vblank_crtc *vblank) { + return timeval_to_ns(&vblank->time); +} +#endif /* HAVE_DRM_VBLANK_USE_KTIME_T */ + + #endif /* AMDGPU_BACKPORT_KCL_AMDGPU_H */ diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index a5ad92c221756..152c71d076157 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -532,6 +532,13 @@ static void dm_pflip_high_irq(void *interrupt_params) amdgpu_crtc->crtc_id, amdgpu_crtc, vrr_active, (int)!e); } +#ifndef HAVE_KTIME_IS_UNION +static inline ktime_t get_drm_vblank_crtc_time(struct drm_vblank_crtc *vblank) +{ + return kcl_amdgpu_get_vblank_time_ns(vblank); +} +#endif + static void dm_vupdate_high_irq(void *interrupt_params) { struct common_irq_params *irq_params = interrupt_params; @@ -553,13 +560,14 @@ static void dm_vupdate_high_irq(void *interrupt_params) drm_dev = acrtc->base.dev; vblank = drm_crtc_vblank_crtc(&acrtc->base); previous_timestamp = atomic64_read(&irq_params->previous_timestamp); - frame_duration_ns = vblank->time - previous_timestamp; + frame_duration_ns = get_drm_vblank_crtc_time(vblank) - previous_timestamp; if (frame_duration_ns > 0) { trace_amdgpu_refresh_rate_track(acrtc->base.index, frame_duration_ns, ktime_divns(NSEC_PER_SEC, frame_duration_ns)); - atomic64_set(&irq_params->previous_timestamp, vblank->time); + atomic64_set(&irq_params->previous_timestamp, + get_drm_vblank_crtc_time(vblank)); } #endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 3bf2610fde6a4..5dffaca76c2a7 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -357,6 +357,9 @@ /* drm_calc_vbltimestamp_from_scanoutpos() use ktime_t arg */ /* #undef HAVE_DRM_DRIVER_GET_VBLANK_TIMESTAMP_USE_KTIMER_T_ARG */ +/* drm_vblank struct use ktime_t for time field */ +#define HAVE_DRM_VBLANK_USE_KTIME_T 1 + /* drm_driver->release() is available */ #define HAVE_DRM_DRIVER_RELEASE 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_vblank_use_ktime_t_time_field.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_vblank_use_ktime_t_time_field.m4 new file mode 100644 index 0000000000000..1107aa2219eca --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_vblank_use_ktime_t_time_field.m4 @@ -0,0 +1,15 @@ +dnl # +dnl # commit v4.14-rc3-721-g67680d3c0464 dnl # drm: vblank: use ktime_t instead of timeval +AC_DEFUN([AC_AMDGPU_DRM_VBLANK_USE_KTIME_T], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_vblank_crtc *vblank = NULL; + vblank->time = 0; + ], [ + AC_DEFINE(HAVE_DRM_VBLANK_USE_KTIME_T, 1, + [drm_vblank->time uses ktime_t type]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index b14d290a3674b..1fff8bd730c87 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -171,6 +171,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DEV_ENTER AC_AMDGPU_DRM_DEV_IS_UNPLUGGED AC_AMDGPU_DRM_DEVICE_PDEV + AC_AMDGPU_DRM_VBLANK_USE_KTIME_T AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From d7fd48899849376cac0c2199c3792d2e0f6d3917 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Sat, 9 Oct 2021 15:21:18 +0800 Subject: [PATCH 0514/1868] drm/amdkcl: adapt code of ktime_t api for legacy os Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h | 4 +++- .../drm/amd/dkms/m4/drm_vblank_use_ktime_t_time_field.m4 | 9 +++++++-- 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h index 825228898e963..fc2eecd49d62b 100644 --- a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h @@ -95,7 +95,9 @@ static inline ktime_t kcl_amdgpu_get_vblank_time_ns(struct drm_vblank_crtc *vbla } #else static inline ktime_t kcl_amdgpu_get_vblank_time_ns(struct drm_vblank_crtc *vblank) { - return timeval_to_ns(&vblank->time); + struct timeval tv; + drm_crtc_vblank_count_and_time(vblank, &tv); + return timeval_to_ktime(tv); } #endif /* HAVE_DRM_VBLANK_USE_KTIME_T */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_vblank_use_ktime_t_time_field.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_vblank_use_ktime_t_time_field.m4 index 1107aa2219eca..b846cb2f57a41 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_vblank_use_ktime_t_time_field.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_vblank_use_ktime_t_time_field.m4 @@ -1,12 +1,17 @@ dnl # -dnl # commit v4.14-rc3-721-g67680d3c0464 dnl # drm: vblank: use ktime_t instead of timeval +dnl # commit v4.14-rc3-721-g67680d3c0464 dnl # drm: vblank: use ktime_t instead of timeval AC_DEFUN([AC_AMDGPU_DRM_VBLANK_USE_KTIME_T], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DRMP_H + #include + #else #include + #endif + #include ], [ struct drm_vblank_crtc *vblank = NULL; - vblank->time = 0; + vblank->time = ns_to_ktime(0); ], [ AC_DEFINE(HAVE_DRM_VBLANK_USE_KTIME_T, 1, [drm_vblank->time uses ktime_t type]) From 9d6e4ade25be9941be2aa38f36b556a352752468 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 11 Oct 2021 14:50:16 +0800 Subject: [PATCH 0515/1868] drm/amdkcl: fix dependency for HSA_AMD_SVM Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/dkms/Makefile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index b1eecc92ebfb3..ef8bfe38400f5 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -159,9 +159,11 @@ subdir-ccflags-y += -DCONFIG_DRM_AMD_DC subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN1_0 ifeq ($(call _is_kcl_macro_defined,HAVE_AMDKCL_HMM_MIRROR_ENABLED),y) +ifdef CONFIG_DEVICE_PRIVATE export CONFIG_HSA_AMD_SVM=y subdir-ccflags-y += -DCONFIG_HSA_AMD_SVM endif +endif export CONFIG_DRM_AMD_DC_HDCP=y subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_HDCP From b4160210e7b914fb287d6e5c2d95b2027b10722c Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 11 Oct 2021 14:49:42 +0800 Subject: [PATCH 0516/1868] drm/amdkcl: fix mmu_notifier_range_blockable on rhel8.5 Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- include/kcl/kcl_mmu_notifier.h | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/include/kcl/kcl_mmu_notifier.h b/include/kcl/kcl_mmu_notifier.h index 1af9433bdbfe5..eb18197778b02 100644 --- a/include/kcl/kcl_mmu_notifier.h +++ b/include/kcl/kcl_mmu_notifier.h @@ -4,16 +4,25 @@ #include -#if !defined(HAVE_MMU_NOTIFIER_RANGE_BLOCKABLE) && \ - defined(HAVE_2ARGS_INVALIDATE_RANGE_START) +#if !defined(HAVE_MMU_NOTIFIER_RANGE_BLOCKABLE) /* Copied from v5.1-10225-g4a83bfe916f3 include/linux/mmu_notifier.h */ -#ifdef CONFIG_MMU_NOTIFIER +#if defined(CONFIG_MMU_NOTIFIER) && \ + defined(HAVE_2ARGS_INVALIDATE_RANGE_START) static inline bool mmu_notifier_range_blockable(const struct mmu_notifier_range *range) { +/* + * It's for rhel8.5 which has the latest struct mmu_notifier_range + * and no mmu_notifier_range_blockable + */ +#ifdef MMU_NOTIFIER_RANGE_BLOCKABLE + return (range->flags & MMU_NOTIFIER_RANGE_BLOCKABLE); +#else return range->blockable; +#endif } #else +struct mmu_notifier_range; static inline bool mmu_notifier_range_blockable(const struct mmu_notifier_range *range) { From d5e0f31f925b3e43e20f9e23cce470b87dda949e Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 11 Oct 2021 19:12:08 +0800 Subject: [PATCH 0517/1868] drm/amdkcl: fake drm_connector_set_panel_orientation_with_quirk() It's caused by 01265b703af5e7cd99545319bc88aba22ab7b95f "amd/display: enable panel orientation quirks" v5.13-2450-g01265b703af5 Signed-off-by: Asher Song Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c | 11 +++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ ...connector-set-panel-orientation-with-quirk.m4 | 13 +++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_connector.h | 16 ++++++++++++++++ 5 files changed, 44 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-connector-set-panel-orientation-with-quirk.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c index 79c907264d709..a4a4e8d2e9acf 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c @@ -78,3 +78,14 @@ int drm_connector_attach_hdr_output_metadata_property(struct drm_connector *conn } EXPORT_SYMBOL(drm_connector_attach_hdr_output_metadata_property); #endif + +#if !defined(HAVE_DRM_CONNECTOR_SET_PANEL_ORIENTATION_WITH_QUIRK) +int _kcl_drm_connector_set_panel_orientation_with_quirk( + struct drm_connector *connector, + enum drm_panel_orientation panel_orientation, + int width, int height) +{ + return drm_connector_init_panel_orientation_property(connector, width, height); +} +EXPORT_SYMBOL(_kcl_drm_connector_set_panel_orientation_with_quirk); +#endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 5dffaca76c2a7..3beb7d29369a3 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -210,6 +210,9 @@ /* connector reference counting is available */ #define HAVE_DRM_CONNECTOR_REFERENCE_COUNTING_SUPPORTED 1 +/* drm_connector_set_panel_orientation_with_quirk() is available */ +#define HAVE_DRM_CONNECTOR_SET_PANEL_ORIENTATION_WITH_QUIRK 1 + /* struct drm_connector_state has hdcp_content_type member */ #define HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-set-panel-orientation-with-quirk.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-set-panel-orientation-with-quirk.m4 new file mode 100644 index 0000000000000..463767cb7e3a6 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector-set-panel-orientation-with-quirk.m4 @@ -0,0 +1,13 @@ +dnl # +dnl # commit v5.5-rc2-1360-g69654c632d80 +dnl # drm/connector: Split out orientation quirk detection (v2) +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_SET_PANEL_ORIENTATION_WITH_QUIRK], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([drm_connector_set_panel_orientation_with_quirk], + [drivers/gpu/drm/drm_connector.c], [ + AC_DEFINE(HAVE_DRM_CONNECTOR_SET_PANEL_ORIENTATION_WITH_QUIRK, 1, + [drm_connector_set_panel_orientation_with_quirk() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 1fff8bd730c87..f2245c6421123 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -172,6 +172,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DEV_IS_UNPLUGGED AC_AMDGPU_DRM_DEVICE_PDEV AC_AMDGPU_DRM_VBLANK_USE_KTIME_T + AC_AMDGPU_DRM_CONNECTOR_SET_PANEL_ORIENTATION_WITH_QUIRK AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_connector.h b/include/kcl/kcl_drm_connector.h index f50f00e2f17fb..d77022ef022ac 100644 --- a/include/kcl/kcl_drm_connector.h +++ b/include/kcl/kcl_drm_connector.h @@ -105,4 +105,20 @@ bool drm_connector_atomic_hdr_metadata_equal(struct drm_connector_state *old_sta int drm_connector_attach_hdr_output_metadata_property(struct drm_connector *connector); #endif +#ifndef HAVE_DRM_CONNECTOR_SET_PANEL_ORIENTATION_WITH_QUIRK +int _kcl_drm_connector_set_panel_orientation_with_quirk( + struct drm_connector *connector, + enum drm_panel_orientation panel_orientation, + int width, int height); + +static inline +int drm_connector_set_panel_orientation_with_quirk( + struct drm_connector *connector, + enum drm_panel_orientation panel_orientation, + int width, int height) +{ + return _kcl_drm_connector_set_panel_orientation_with_quirk(connector, panel_orientation, width, height); +} +#endif + #endif /* AMDKCL_DRM_CONNECTOR_H */ From c298cd5633d6c182bc8e217e5cd965c0ebb631f9 Mon Sep 17 00:00:00 2001 From: Marko Zekovic Date: Mon, 11 Oct 2021 15:03:35 +0200 Subject: [PATCH 0518/1868] drm/amdkcl: fix issue with dirver unloading Fix issue with driver unloading on kernel 5.4. Backported from 5.11 version of driver. Signed-off-by: Marko Zekovic Reviewed-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 304344283edf1..eddcac8a2cbe5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2478,6 +2478,9 @@ amdgpu_pci_remove(struct pci_dev *pdev) kcl_pci_remove_measure_file(pdev); pci_disable_device(pdev); pci_wait_for_pending_transaction(pdev); +#ifdef AMDKCL_DEVM_DRM_DEV_ALLOC + amdkcl_drm_dev_release(dev); +#endif } #ifdef HAVE_DRM_DRIVER_RELEASE From 9b5c5f3b6fd11efcf6a34508a3d458d6dc104ebf Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 15 Oct 2021 16:13:34 +0800 Subject: [PATCH 0519/1868] drm/amdkcl: add arguments of function amdgpu_ttm_tt_affect_userptr() It's caused by 2d3ad5529663465fd1443f9cf8230ec2bba2cd77 "drm/amdkfd: unregistered svm range not overlap with TTM range" v5.13-2731-g2d3ad5529663 Signed-off-by: Asher Song Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c | 9 ++++++--- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 5 ++++- 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c index 128f079102013..43bb1ec468fe8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c @@ -270,10 +270,11 @@ static void amdgpu_mn_invalidate_node(struct amdgpu_mn_node *node, { struct amdgpu_bo *bo; long r; + unsigned long userptr; list_for_each_entry(bo, &node->bos, mn_list) { - if (!amdgpu_ttm_tt_affect_userptr(bo->tbo.ttm, start, end)) + if (!amdgpu_ttm_tt_affect_userptr(bo->tbo.ttm, start, end, &userptr)) continue; r = dma_resv_wait_timeout(amdkcl_ttm_resvp(&bo->tbo), @@ -342,6 +343,7 @@ static int amdgpu_mn_invalidate_range_start_hsa(struct mmu_notifier *mn, struct amdgpu_mn *amn = container_of(mn, struct amdgpu_mn, mn); struct interval_tree_node *it; unsigned long end; + unsigned long userptr; /* notification is exclusive, but interval is inclusive */ end = range->end - 1; @@ -362,7 +364,7 @@ static int amdgpu_mn_invalidate_range_start_hsa(struct mmu_notifier *mn, if (amdgpu_ttm_tt_affect_userptr(bo->tbo.ttm, range->start, - end)) + end, &userptr)) amdgpu_amdkfd_evict_userptr(mem, range->mm); } } @@ -452,6 +454,7 @@ static void amdgpu_mn_invalidate_range_start_hsa(struct mmu_notifier *mn, { struct amdgpu_mn *amn = container_of(mn, struct amdgpu_mn, mn); struct interval_tree_node *it; + unsigned long userptr; /* notification is exclusive, but interval is inclusive */ end -= 1; @@ -475,7 +478,7 @@ static void amdgpu_mn_invalidate_range_start_hsa(struct mmu_notifier *mn, struct kgd_mem *mem = bo->kfd_bo; if (amdgpu_ttm_tt_affect_userptr(bo->tbo.ttm, - start, end)) + start, end, &userptr)) amdgpu_amdkfd_evict_userptr(mem, mm); } } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 876bdac748047..7313b29c048a0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -1556,7 +1556,7 @@ bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm) * */ bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, - unsigned long end) + unsigned long end, unsigned long *userptr) { struct amdgpu_ttm_tt *gtt = (void *)ttm; struct amdgpu_ttm_gup_task_list *entry; @@ -1586,6 +1586,9 @@ bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start, atomic_inc(>t->mmu_invalidations); + if (userptr) + *userptr = gtt->userptr; + return true; } From dee497cb1640ded27a57f66949ef72bf593e51b3 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 20 Oct 2021 16:11:29 +0800 Subject: [PATCH 0520/1868] drm/amdkcl: fake a get_mm_exe_file get_mm_exe_file is not export in legacy kernel. It's caused by 0d4da915c7098eca2aa6f559f42e33b5e9c7c5e8 "amd/display: only require overlay plane to cover whole CRTC on ChromeOS" v5.13-2703-g0d4da915c709 Signed-off-by: Asher Song Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/kcl_mm.c | 10 ++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/get_mm_exe_file.m4 | 10 ++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/backport/kcl_mm_backport.h | 4 ++++ include/kcl/kcl_mm.h | 4 ++++ 6 files changed, 32 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/get_mm_exe_file.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_mm.c b/drivers/gpu/drm/amd/amdkcl/kcl_mm.c index 9d7534002b7e1..65ae09624622f 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_mm.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_mm.c @@ -16,9 +16,19 @@ void __kcl_mmput_async(struct mm_struct *mm) } #endif + +#ifndef HAVE_GET_MM_EXE_FILE +struct file *(*_kcl_get_mm_exe_file)(struct mm_struct *mm); +EXPORT_SYMBOL(_kcl_get_mm_exe_file); +#endif + void amdkcl_mm_init(void) { #ifndef HAVE_MMPUT_ASYNC _kcl_mmput_async = amdkcl_fp_setup("mmput_async", __kcl_mmput_async); #endif + +#ifndef HAVE_GET_MM_EXE_FILE + _kcl_get_mm_exe_file = amdkcl_fp_setup("get_mm_exe_file", NULL); +#endif } diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 3beb7d29369a3..4a844b33546e1 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -642,6 +642,9 @@ /* drm_driver->gem_free_object_unlocked() is available */ /* #undef HAVE_GEM_FREE_OBJECT_UNLOCKED_IN_DRM_DRIVER */ +/* get_mm_exe_file() is available */ +#define HAVE_GET_MM_EXE_FILE 1 + /* get_user_pages() wants 6 args */ /* #undef HAVE_GET_USER_PAGES_6ARGS */ diff --git a/drivers/gpu/drm/amd/dkms/m4/get_mm_exe_file.m4 b/drivers/gpu/drm/amd/dkms/m4/get_mm_exe_file.m4 new file mode 100644 index 0000000000000..9c024190e405d --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/get_mm_exe_file.m4 @@ -0,0 +1,10 @@ +dnl # +dnl # v2.6.39-6856-g3864601387cf mm: extract exe_file handling from procfs +dnl # +AC_DEFUN([AC_AMDGPU_GET_MM_EXE_FILE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([get_mm_exe_file], [kernel/fork.c], [ + AC_DEFINE(HAVE_GET_MM_EXE_FILE, 1, [get_mm_exe_file() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index f2245c6421123..79374bd218e07 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -173,6 +173,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DEVICE_PDEV AC_AMDGPU_DRM_VBLANK_USE_KTIME_T AC_AMDGPU_DRM_CONNECTOR_SET_PANEL_ORIENTATION_WITH_QUIRK + AC_AMDGPU_GET_MM_EXE_FILE AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/backport/kcl_mm_backport.h b/include/kcl/backport/kcl_mm_backport.h index 48312d64e5869..131403b50a6b4 100644 --- a/include/kcl/backport/kcl_mm_backport.h +++ b/include/kcl/backport/kcl_mm_backport.h @@ -9,6 +9,10 @@ #define mmput_async _kcl_mmput_async #endif +#ifndef HAVE_GET_MM_EXE_FILE +#define get_mm_exe_file _kcl_get_mm_exe_file +#endif + #ifdef get_user_pages_remote #undef get_user_pages_remote #endif diff --git a/include/kcl/kcl_mm.h b/include/kcl/kcl_mm.h index 57b2ee1fcb846..4f33936bf7dd9 100644 --- a/include/kcl/kcl_mm.h +++ b/include/kcl/kcl_mm.h @@ -26,6 +26,10 @@ extern void (*_kcl_mmput_async)(struct mm_struct *mm); #endif +#ifndef HAVE_GET_MM_EXE_FILE +extern struct file *(*_kcl_get_mm_exe_file)(struct mm_struct *mm); +#endif + #ifndef HAVE_FAULT_FLAG_ALLOW_RETRY_FIRST static inline bool fault_flag_allow_retry_first(unsigned int flags) { From 3698b33705ff284f595a0d89993a0b708adc4d14 Mon Sep 17 00:00:00 2001 From: Amber Lin Date: Fri, 22 Oct 2021 12:08:37 -0400 Subject: [PATCH 0521/1868] drm/amdkcl: Set PAGEMAP_OWNER for in-tree build PAGEMAP_OWNER should be defined in config.h for in-tree build on 5.13 kernel. This fixes "failed to register HMM device memory" error when loading amdgpu driver where a 5.13 monolithic kernel is used. Signed-off-by: Amber Lin Reviewed-by: Philip Yang Change-Id: I5a09a4ec30649c202096fa1f95248ad802e9fdd7 --- drivers/gpu/drm/amd/dkms/config/config.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 4a844b33546e1..36f268b2239c8 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -71,7 +71,7 @@ /* #undef HAVE_DEVM_MEMREMAP_PAGES_P_P_P_P */ /* dev_pagemap->owner is available */ -/* #undef HAVE_DEV_PAGEMAP_OWNER */ +#define HAVE_DEV_PAGEMAP_OWNER 1 /* there is 'range' field within dev_pagemap structure */ #define HAVE_DEV_PAGEMAP_RANGE 1 @@ -820,7 +820,7 @@ #define HAVE_MEM_ENCRYPT_ACTIVE 1 /* migrate_vma->pgmap_owner is available */ -/* #undef HAVE_MIGRATE_VMA_PGMAP_OWNER */ +#define HAVE_MIGRATE_VMA_PGMAP_OWNER 1 /* mmgrab() is available */ #define HAVE_MMGRAB 1 From 9458dfeba4e3cd0a43e01531221098dc74684fa3 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 28 Oct 2021 17:00:24 +0800 Subject: [PATCH 0522/1868] drm/amdkcl: add forward declaration of task_struct v5.12-rc3-304-gf7b21a0e4117 fixes a build error when linux/fb.h is used outside of the kernel tree. This patch adds forward declaration of task_struct to adapt legacy os. Reviewed-by: Flora Cui --- .../m4/drm-fb-helper-remove-conflicting-pci-framebuffers.m4 | 1 + .../gpu/drm/amd/dkms/m4/remove-conflicting-pci-framebuffers.m4 | 2 ++ 2 files changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-remove-conflicting-pci-framebuffers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-remove-conflicting-pci-framebuffers.m4 index ec30c7ffa874c..ee6e915098f5c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-remove-conflicting-pci-framebuffers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-remove-conflicting-pci-framebuffers.m4 @@ -43,6 +43,7 @@ AC_DEFUN([AC_AMDGPU_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS], [ dnl # video/fb: Propagate error code from failing to unregister conflicting fb dnl # AC_KERNEL_TRY_COMPILE_SYMBOL([ + struct task_struct; #include ], [ int ret = remove_conflicting_framebuffers(NULL, NULL, false); diff --git a/drivers/gpu/drm/amd/dkms/m4/remove-conflicting-pci-framebuffers.m4 b/drivers/gpu/drm/amd/dkms/m4/remove-conflicting-pci-framebuffers.m4 index 06241044fe4d4..bde011042303f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/remove-conflicting-pci-framebuffers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/remove-conflicting-pci-framebuffers.m4 @@ -5,6 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ + struct task_struct; #include ],[ remove_conflicting_pci_framebuffers(NULL, NULL); @@ -13,6 +14,7 @@ AC_DEFUN([AC_AMDGPU_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS], [ [remove_conflicting_pci_framebuffers() is available and doesn't have res_id arg]) ],[ AC_KERNEL_TRY_COMPILE([ + struct task_struct; #include ], [ remove_conflicting_pci_framebuffers(NULL, 0, NULL); From 1636e4d696671aab4751bcb7f37c65c6e8e7e947 Mon Sep 17 00:00:00 2001 From: Jingwen Chen Date: Fri, 29 Oct 2021 18:04:05 +0800 Subject: [PATCH 0523/1868] drm/amdkcl: fix minor index not removed after unload driver [Why] In kernel 5.4, current driver will not remove minor->index from drm_minors_idr during unload driver. Which will lead to minor index increase after reload amdgpu. [How] As there's no drm_managed.h to call drm_minor_alloc_release when release dev, add drm_dev_fini to amdgpu_driver_release_kms Signed-off-by: Jingwen Chen Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index 3d8aab004d934..a7599d6cbbd5c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -1520,6 +1520,10 @@ void amdgpu_driver_release_kms(struct drm_device *dev) amdgpu_device_fini_sw(adev); pci_set_drvdata(adev->pdev, NULL); +#ifndef HAVE_DRM_DRM_MANAGED_H + drm_dev_fini(dev); + kfree(adev); +#endif } /* From 88c21843613c75599d9739fe944175f11374f2ac Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 2 Nov 2021 10:07:22 +0800 Subject: [PATCH 0524/1868] drm/amdkcl: Fix DKMS makefile include path filter As of Ubuntu 20.04.4, the given paths from LINUXINCLUDE variable would be filtered incorrectly as each token is considered a word and done independently. This would lead to the case where two '-include' switches would appear in sequence causing later switches to be parsed incorrectly. When the kconfig file is filtered out, it should be filtered out together with the preceding '-include', so adding quotes fixes this. v1: add quotes to filter out the specific string v2: handle the extra space with "-I " Signed-off-by: George Cave Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/dkms/Makefile | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index ef8bfe38400f5..b9f423b84ddaf 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -124,9 +124,10 @@ endif export OS_NAME OS_VERSION +_KCL_LINUXINCLUDE=$(subst -I ,-I,$(strip $(LINUXINCLUDE))) LINUX_SRCTREE_INCLUDE := \ - $(filter-out -I%/uapi -include %/kconfig.h,$(LINUXINCLUDE)) -USER_INCLUDE := $(filter-out $(LINUX_SRCTREE_INCLUDE), $(LINUXINCLUDE)) + $(filter-out -I%/uapi "-include %/kconfig.h",$(_KCL_LINUXINCLUDE)) +USER_INCLUDE := $(filter-out $(LINUX_SRCTREE_INCLUDE), $(_KCL_LINUXINCLUDE)) LINUXINCLUDE := \ -I$(src)/include \ From 4ff44da3ffb8c526767f5b4fdb896b69b61ffb08 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 3 Nov 2021 11:54:40 +0800 Subject: [PATCH 0525/1868] drm/amdkcl: fake drm_simple_encoder_init It's caused by ba5317109d0ce7809831abfcea9b8157464b263f "drm/amdgpu: create amdgpu_vkms (v4)" v5.13-1946-gba5317109d0c Signed-off-by: Asher Song Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- .../amd/amdkcl/kcl_drm_simple_kms_helper.c | 24 +++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../drm/amd/dkms/m4/drm_simple_kms_helper.m4 | 12 ++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_simple_kms_helper.h | 22 +++++++++++++++++ 7 files changed, 64 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_simple_kms_helper.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_simple_kms_helper.m4 create mode 100644 include/kcl/kcl_drm_simple_kms_helper.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index a26c5110afa79..ef7887752b276 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -12,7 +12,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_drm_crtc.o kcl_drm_connector.o kcl_drm_atomic_helper.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o kcl_ftrace.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_fs_read_write.o kcl_drm_aperture.o \ - kcl_drm_drv.o + kcl_drm_drv.o kcl_drm_simple_kms_helper.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_simple_kms_helper.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_simple_kms_helper.c new file mode 100644 index 0000000000000..7a44428ce88e2 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_simple_kms_helper.c @@ -0,0 +1,24 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2016 Noralf Trønnes + */ + +#include + +/* Copied from drivers/gpu/drm/drm_simple_kms_helper.c and modified for KCL */ +#ifndef HAVE_DRM_SIMPLE_ENCODER_INIT +static const struct drm_encoder_funcs drm_simple_encoder_funcs_cleanup = { + .destroy = drm_encoder_cleanup, +}; + +int _kcl_drm_simple_encoder_init(struct drm_device *dev, + struct drm_encoder *encoder, + int encoder_type) +{ + return drm_encoder_init(dev, encoder, + &drm_simple_encoder_funcs_cleanup, + encoder_type, NULL); +} +EXPORT_SYMBOL(_kcl_drm_simple_encoder_init); + +#endif diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index db2ccf68b324d..e2a1e3e409bde 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -78,5 +78,6 @@ #include "kcl/kcl_mce.h" #include "kcl/kcl_drm_aperture.h" #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 36f268b2239c8..47a227eaee844 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -597,6 +597,9 @@ /* drm_printer->prefix is available */ #define HAVE_DRM_PRINTER_PREFIX 1 +/* drm_simple_encoder is available */ +#define HAVE_DRM_SIMPLE_ENCODER_INIT 1 + /* drm_syncobj_fence_get() is available */ /* #undef HAVE_DRM_SYNCOBJ_FENCE_GET */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_simple_kms_helper.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_simple_kms_helper.m4 new file mode 100644 index 0000000000000..0ffcd218e5a99 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_simple_kms_helper.m4 @@ -0,0 +1,12 @@ +dnl # +dnl # v5.6-rc2-359-g63170ac6f2e8 +dnl # drm/simple-kms: Add drm_simple_encoder_{init,create}() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_SIMPLE_ENCODER_INIT], [ + AC_KERNEL_CHECK_SYMBOL_EXPORT( + [drm_simple_encoder_init], + [drivers/gpu/drm/drm_simple_kms_helper.c],[ + AC_DEFINE(HAVE_DRM_SIMPLE_ENCODER_INIT, 1, + [drm_simple_encoder is available]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 79374bd218e07..338bf44b7cd3a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -174,6 +174,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_VBLANK_USE_KTIME_T AC_AMDGPU_DRM_CONNECTOR_SET_PANEL_ORIENTATION_WITH_QUIRK AC_AMDGPU_GET_MM_EXE_FILE + AC_AMDGPU_DRM_SIMPLE_ENCODER_INIT AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_simple_kms_helper.h b/include/kcl/kcl_drm_simple_kms_helper.h new file mode 100644 index 0000000000000..51a6699486da0 --- /dev/null +++ b/include/kcl/kcl_drm_simple_kms_helper.h @@ -0,0 +1,22 @@ +/*SPDX-License-Identifier: GPL-2.0*/ +/* + * Copyright (C) 2016 Noralf Trønnes + */ + +#include +#include +#include +#include + +#ifndef HAVE_DRM_SIMPLE_ENCODER_INIT +extern int _kcl_drm_simple_encoder_init(struct drm_device *dev, + struct drm_encoder *encoder, + int encoder_type); +static inline +int drm_simple_encoder_init(struct drm_device *dev, + struct drm_encoder *encoder, + int encoder_type) +{ + return _kcl_drm_simple_encoder_init(dev,encoder,encoder_type); +} +#endif From 118b14032d3c3e28fd0462c346a6dd6e918beed0 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 2 Nov 2021 12:27:34 +0800 Subject: [PATCH 0526/1868] drm/amdkcl: convert ktime_t to adapt legacy os It's caused by ba5317109d0ce7809831abfcea9b8157464b263f "drm/amdgpu: create amdgpu_vkms (v4)" v5.13-1946-gba5317109d0c Signed-off-by: Asher Song Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c index e5f508d34ed83..2947de8985ae1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c @@ -101,9 +101,8 @@ static bool amdgpu_vkms_get_vblank_timestamp(struct drm_crtc *crtc, *vblank_time = READ_ONCE(amdgpu_crtc->vblank_timer.node.expires); - if (WARN_ON(*vblank_time == vblank->time)) + if (WARN_ON(ktime_to_us(*vblank_time) == ktime_to_us(vblank->time))) return true; - /* * To prevent races we roll the hrtimer forward before we do any * interrupt processing - this is how real hw works (the interrupt is @@ -111,8 +110,8 @@ static bool amdgpu_vkms_get_vblank_timestamp(struct drm_crtc *crtc, * the vblank core expects. Therefore we need to always correct the * timestampe by one frame. */ - *vblank_time -= output->period_ns; + *vblank_time = ktime_sub(*vblank_time, output->period_ns); return true; } From d38bfa5e72f37f9ce240a7e326f3e194aaf7a25b Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 20 Aug 2021 18:58:21 +0800 Subject: [PATCH 0527/1868] drm/amdkcl: wrap the code under macro HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP It's caused by ba5317109d0ce7809831abfcea9b8157464b263f "drm/amdgpu: create amdgpu_vkms (v4)" v5.13-1946-gba5317109d0c Signed-off-by: Asher Song Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c index 2947de8985ae1..bc3b3390b9bef 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c @@ -122,9 +122,11 @@ static const struct drm_crtc_funcs amdgpu_vkms_crtc_funcs = { .reset = drm_atomic_helper_crtc_reset, .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP .enable_vblank = amdgpu_vkms_enable_vblank, .disable_vblank = amdgpu_vkms_disable_vblank, .get_vblank_timestamp = amdgpu_vkms_get_vblank_timestamp, +#endif }; static void amdgpu_vkms_crtc_atomic_enable(struct drm_crtc *crtc, From d686355962e0d67daf665bdf55f4a640503a5b2c Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 3 Nov 2021 12:48:17 +0800 Subject: [PATCH 0528/1868] drm/amdkcl: test atomic_enable function in drm_crtc_helper_funcs and its argument type It's caused by ba5317109d0ce7809831abfcea9b8157464b263f "drm/amdgpu: create amdgpu_vkms (v4)" v5.13-1946-gba5317109d0c Signed-off-by: Asher Song Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 26 ++++++++-- drivers/gpu/drm/amd/dkms/config/config.h | 10 +++- .../drm/amd/dkms/m4/drm-crtc-helper-funcs.m4 | 52 +++++++++++++++++-- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 +- 4 files changed, 81 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c index bc3b3390b9bef..ceecb83ce9a50 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c @@ -129,20 +129,34 @@ static const struct drm_crtc_funcs amdgpu_vkms_crtc_funcs = { #endif }; -static void amdgpu_vkms_crtc_atomic_enable(struct drm_crtc *crtc, - struct drm_atomic_state *state) +static void amdgpu_vkms_crtc_atomic_enable(struct drm_crtc *crtc +#if defined(HAVE_DRM_CRTC_HELPER_FUNCS_ATOMIC_ENABLE_ARG_DRM_ATOMIC_STATE) + , struct drm_atomic_state *state) +#elif defined(HAVE_DRM_CRTC_HELPER_FUNCS_HAVE_ATOMIC_ENABLE) + , struct drm_crtc_state *state) +#else + ) +#endif { drm_crtc_vblank_on(crtc); } static void amdgpu_vkms_crtc_atomic_disable(struct drm_crtc *crtc, - struct drm_atomic_state *state) +#if defined(HAVE_DRM_CRTC_HELPER_FUNCS_ATOMIC_ENABLE_ARG_DRM_ATOMIC_STATE) + struct drm_atomic_state *state) +#else + struct drm_crtc_state *state) +#endif { drm_crtc_vblank_off(crtc); } static void amdgpu_vkms_crtc_atomic_flush(struct drm_crtc *crtc, - struct drm_atomic_state *state) +#if defined(HAVE_DRM_CRTC_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE) + struct drm_atomic_state *state) +#else + struct drm_crtc_state *state) +#endif { unsigned long flags; if (crtc->state->event) { @@ -161,7 +175,11 @@ static void amdgpu_vkms_crtc_atomic_flush(struct drm_crtc *crtc, static const struct drm_crtc_helper_funcs amdgpu_vkms_crtc_helper_funcs = { .atomic_flush = amdgpu_vkms_crtc_atomic_flush, +#if defined(HAVE_DRM_CRTC_HELPER_FUNCS_HAVE_ATOMIC_ENABLE) .atomic_enable = amdgpu_vkms_crtc_atomic_enable, +#else + .enable = amdgpu_vkms_crtc_atomic_enable, +#endif .atomic_disable = amdgpu_vkms_crtc_atomic_disable, }; diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 47a227eaee844..d2e0712acf4f3 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -237,9 +237,17 @@ /* drm_crtc_from_index() is available */ #define HAVE_DRM_CRTC_FROM_INDEX 1 -/* drm_crtc_helper_funcs->atomic_check() wants struct drm_atomic_state arg */ +/* drm_crtc_helper_funcs->atomic_check()/atomic_flush()/atomic_begin() wants + struct drm_atomic_state arg */ #define HAVE_DRM_CRTC_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE 1 +/* drm_crtc_helper_funcs->atomic_enable()/atomic_disable() wants struct + drm_atomic_state arg */ +#define HAVE_DRM_CRTC_HELPER_FUNCS_ATOMIC_ENABLE_ARG_DRM_ATOMIC_STATE 1 + +/* have drm_crtc_helper_funcs->atomic_enable() */ +#define HAVE_DRM_CRTC_HELPER_FUNCS_HAVE_ATOMIC_ENABLE 1 + /* drm_crtc_init_with_planes() wants name */ #define HAVE_DRM_CRTC_INIT_WITH_PLANES_VALID_WITH_NAME 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-crtc-helper-funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-crtc-helper-funcs.m4 index 7f43ce7a2f5e2..ea944aff250c5 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-crtc-helper-funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-crtc-helper-funcs.m4 @@ -1,6 +1,9 @@ dnl # -dnl # commit v5.2-rc2-529-g6f3b62781bbd -dnl # drm: Convert connector_helper_funcs->atomic_check to accept drm_atomic_state +dnl # v5.10-rc2-260-g29b77ad7b9ca +dnl # drm/atomic: Pass the full state to CRTC atomic_check +dnl +dnl # v5.10-rc2-261-gf6ebe9f9c923 +dnl # drm/atomic: Pass the full state to CRTC atomic begin and flush dnl # AC_DEFUN([AC_AMDGPU_DRM_CRTC_HELPER_FUNCS_ATOMIC_CHECK], [ AC_KERNEL_DO_BACKGROUND([ @@ -12,7 +15,50 @@ AC_DEFUN([AC_AMDGPU_DRM_CRTC_HELPER_FUNCS_ATOMIC_CHECK], [ p->atomic_check(NULL, (struct drm_atomic_state*)NULL); ], [ AC_DEFINE(HAVE_DRM_CRTC_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE, 1, - [drm_crtc_helper_funcs->atomic_check() wants struct drm_atomic_state arg]) + [drm_crtc_helper_funcs->atomic_check()/atomic_flush()/atomic_begin() wants struct drm_atomic_state arg]) ]) ]) ]) + +dnl # +dnl # v5.9-rc5-1161-g351f950db4ab +dnl # drm/atomic: Pass the full state to CRTC atomic enable/disable +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CRTC_HELPER_FUNCS_ATOMIC_ENABLE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + struct drm_crtc_helper_funcs *p = NULL; + p->atomic_enable(NULL, (struct drm_atomic_state*)NULL); + ], [ + AC_DEFINE(HAVE_DRM_CRTC_HELPER_FUNCS_ATOMIC_ENABLE_ARG_DRM_ATOMIC_STATE, 1, + [drm_crtc_helper_funcs->atomic_enable()/atomic_disable() wants struct drm_atomic_state arg]) + AC_DEFINE(HAVE_DRM_CRTC_HELPER_FUNCS_HAVE_ATOMIC_ENABLE, 1, + [have drm_crtc_helper_funcs->atomic_enable()]) + + ],[ + dnl # + dnl # v4.12-rc7-1332-g0b20a0f8c3cb + dnl # drm: Add old state pointer to CRTC .enable() helper function + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + struct drm_crtc_helper_funcs *p = NULL; + p->atomic_enable(NULL, NULL); + ], [ + AC_DEFINE(HAVE_DRM_CRTC_HELPER_FUNCS_HAVE_ATOMIC_ENABLE, 1, + [have drm_crtc_helper_funcs->atomic_enable()]) + ]) + + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_DRM_CRTC_HELPER_FUNCS], [ + AC_AMDGPU_DRM_CRTC_HELPER_FUNCS_ATOMIC_CHECK + AC_AMDGPU_DRM_CRTC_HELPER_FUNCS_ATOMIC_ENABLE +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 338bf44b7cd3a..60a3e87267cf6 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -136,7 +136,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_SUBCONNECTOR AC_AMDGPU_DRM_PRIME_SG_TO_DMA_ADDR_ARRAY AC_AMDGPU_DRM_PRIME_PAGES_TO_SG - AC_AMDGPU_DRM_CRTC_HELPER_FUNCS_ATOMIC_CHECK + AC_AMDGPU_DRM_CRTC_HELPER_FUNCS AC_AMDGPU_DEBUGFS_CREATE_FILE_SIZE AC_AMDGPU_DRM_GEM_TTM_VMAP AC_AMDGPU_FS_RECLAIM_ACQUIRE From a25310b220dca95dcbfbf9813f452cf4cf9564ce Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 4 Nov 2021 11:28:49 +0800 Subject: [PATCH 0529/1868] drm/amdkcl: fake drm_mode_config_helper_suspend/resume() It's caused by 16dcf291698ca37e89c481ae622cd5dc50afa6f4 "drm/amdgpu: replace dce_virtual with amdgpu_vkms (v3)" v5.13-1948-g16dcf291698c Signed-off-by: Flora Cui Reviewed-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 3 + drivers/gpu/drm/amd/backport/Makefile | 3 +- drivers/gpu/drm/amd/backport/backport.h | 1 + .../kcl/kcl_amdgpu_drm_modeset_helper.h | 31 +++++++ .../drm/amd/backport/kcl_drm_modeset_helper.c | 89 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 + .../dkms/m4/drm_mode_config_helper_suspend.m4 | 13 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 8 files changed, 143 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_modeset_helper.h create mode 100644 drivers/gpu/drm/amd/backport/kcl_drm_modeset_helper.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_mode_config_helper_suspend.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index 10bb7988efdbd..50eb99f45c937 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -345,6 +345,9 @@ struct amdgpu_mode_info { int disp_priority; const struct amdgpu_display_funcs *funcs; const enum drm_plane_type *plane_type; +#ifndef HAVE_DRM_MODE_CONFIG_HELPER_SUSPEND + struct drm_atomic_state *suspend_state; +#endif /* Driver-private color mgmt props */ diff --git a/drivers/gpu/drm/amd/backport/Makefile b/drivers/gpu/drm/amd/backport/Makefile index fa78abd428129..cba90812f73b2 100644 --- a/drivers/gpu/drm/amd/backport/Makefile +++ b/drivers/gpu/drm/amd/backport/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: MIT BACKPORT_OBJS := kcl_drm_drv.o kcl_drm_gem_ttm_helper.o \ - kcl_drm_gem_framebuffer_helper.o kcl_drm_gem.o + kcl_drm_gem_framebuffer_helper.o kcl_drm_gem.o \ + kcl_drm_modeset_helper.o amdgpu-y += $(addprefix ../backport/,$(BACKPORT_OBJS)) diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index e2a1e3e409bde..4ede69680225a 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -75,6 +75,7 @@ #include "kcl/kcl_amdgpu_drm_drv.h" #include "kcl/kcl_amdgpu_drm_gem.h" #include "kcl/kcl_drm_gem_ttm_helper.h" +#include "kcl/kcl_amdgpu_drm_modeset_helper.h" #include "kcl/kcl_mce.h" #include "kcl/kcl_drm_aperture.h" #include diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_modeset_helper.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_modeset_helper.h new file mode 100644 index 0000000000000..611d801aa6c33 --- /dev/null +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_modeset_helper.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2016 Intel Corporation + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE. + */ + +#ifndef AMDGPU_BACKPORT_KCL_AMDGPU_DRM_MODESET_HELPER_H +#define AMDGPU_BACKPORT_KCL_AMDGPU_DRM_MODESET_HELPER_H + +#ifndef HAVE_DRM_MODE_CONFIG_HELPER_SUSPEND +int drm_mode_config_helper_suspend(struct drm_device *dev); +int drm_mode_config_helper_resume(struct drm_device *dev); +#endif + +#endif diff --git a/drivers/gpu/drm/amd/backport/kcl_drm_modeset_helper.c b/drivers/gpu/drm/amd/backport/kcl_drm_modeset_helper.c new file mode 100644 index 0000000000000..e6015f0a7efce --- /dev/null +++ b/drivers/gpu/drm/amd/backport/kcl_drm_modeset_helper.c @@ -0,0 +1,89 @@ +/* + * Copyright (c) 2016 Intel Corporation + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE. + */ + +#include +#include "amdgpu.h" + +/* Copied from drivers/gpu/drm/drm_modeset_helper.c and modified for KCL */ +#ifndef HAVE_DRM_MODE_CONFIG_HELPER_SUSPEND +int drm_mode_config_helper_suspend(struct drm_device *dev) +{ + struct drm_atomic_state *state; + struct amdgpu_device *adev; + struct amdgpu_fbdev *afbdev; + struct drm_fb_helper *fb_helper; + + if (!dev) + return 0; + + adev = drm_to_adev(dev); + afbdev = adev->mode_info.rfbdev; + if (!afbdev) + return 0; + + fb_helper = &afbdev->helper; + + drm_kms_helper_poll_disable(dev); + drm_fb_helper_set_suspend_unlocked(fb_helper, 1); + state = drm_atomic_helper_suspend(dev); + if (IS_ERR(state)) { + drm_fb_helper_set_suspend_unlocked(fb_helper, 0); + drm_kms_helper_poll_enable(dev); + return PTR_ERR(state); + } + + adev->mode_info.suspend_state = state; + + return 0; +} + +int drm_mode_config_helper_resume(struct drm_device *dev) +{ + int ret; + struct amdgpu_device *adev; + struct amdgpu_fbdev *afbdev; + struct drm_fb_helper *fb_helper; + + if (!dev) + return 0; + + adev = drm_to_adev(dev); + afbdev = adev->mode_info.rfbdev; + if (!afbdev) + return 0; + + fb_helper = &afbdev->helper; + + if (WARN_ON(!adev->mode_info.suspend_state)) + return -EINVAL; + + ret = drm_atomic_helper_resume(dev, adev->mode_info.suspend_state); + if (ret) + DRM_ERROR("Failed to resume (%d)\n", ret); + adev->mode_info.suspend_state = NULL; + + drm_fb_helper_set_suspend_unlocked(fb_helper, 0); + drm_kms_helper_poll_enable(dev); + + return ret; +} +#endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index d2e0712acf4f3..087e718c16ab9 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -565,6 +565,9 @@ /* drm_mode_config->helper_private is available */ #define HAVE_DRM_MODE_CONFIG_HELPER_PRIVATE 1 +/* drm_mode_config_helper_{suspend/resume}() is available */ +#define HAVE_DRM_MODE_CONFIG_HELPER_SUSPEND 1 + /* drm_mode_get_hv_timing is available */ #define HAVE_DRM_MODE_GET_HV_TIMING 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_mode_config_helper_suspend.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_mode_config_helper_suspend.m4 new file mode 100644 index 0000000000000..8d30e1afba578 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_mode_config_helper_suspend.m4 @@ -0,0 +1,13 @@ +dnl # +dnl # v4.14-rc7-1626-gca038cfb5cfa +dnl # drm/modeset-helper: Add simple modeset suspend/resume helpers +dnl # +AC_DEFUN([AC_AMDGPU_DRM_MODE_CONFIG_HELPER_SUSPEND], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([drm_mode_config_helper_suspend drm_mode_config_helper_resume], + [drivers/gpu/drm/drm_modeset_helper.c],[ + AC_DEFINE(HAVE_DRM_MODE_CONFIG_HELPER_SUSPEND, 1, + [drm_mode_config_helper_{suspend/resume}() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 60a3e87267cf6..527a8c168ff85 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -175,6 +175,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_SET_PANEL_ORIENTATION_WITH_QUIRK AC_AMDGPU_GET_MM_EXE_FILE AC_AMDGPU_DRM_SIMPLE_ENCODER_INIT + AC_AMDGPU_DRM_MODE_CONFIG_HELPER_SUSPEND AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From eee1ba42d878dd6d0e227b06d9f60c7732fae3c0 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 2 Nov 2021 21:41:40 +0800 Subject: [PATCH 0530/1868] drm/amdkcl: wrap code under macro AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS It's caused by ba5317109d0ce7809831abfcea9b8157464b263f "drm/amdgpu: create amdgpu_vkms (v4)" v5.13-1946-gba5317109d0c Signed-off-by: Asher Song Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c index ceecb83ce9a50..466596481fe69 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c @@ -280,16 +280,26 @@ static const struct drm_plane_funcs amdgpu_vkms_plane_funcs = { }; static void amdgpu_vkms_plane_atomic_update(struct drm_plane *plane, +#if defined(HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS) struct drm_atomic_state *old_state) +#else + struct drm_plane_state *old_state) +#endif { return; } static int amdgpu_vkms_plane_atomic_check(struct drm_plane *plane, +#if defined(HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS) struct drm_atomic_state *state) { struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, plane); +#else + struct drm_plane_state *new_plane_state) +{ + struct drm_atomic_state *state = new_plane_state->state; +#endif struct drm_crtc_state *crtc_state; int ret; @@ -298,6 +308,7 @@ static int amdgpu_vkms_plane_atomic_check(struct drm_plane *plane, crtc_state = drm_atomic_get_crtc_state(state, new_plane_state->crtc); + if (IS_ERR(crtc_state)) return PTR_ERR(crtc_state); From 10774143df1dd71f4a274bc2692285b2b0dfd953 Mon Sep 17 00:00:00 2001 From: Guchun Chen Date: Sat, 6 Nov 2021 20:01:37 +0800 Subject: [PATCH 0531/1868] drm/amdkcl: update sources file to include kfd_sysfs.h Fix: 1aefe844453b("drm/amdkfd: Add sysfs bitfields and enums to uAPI") Signed-off-by: Guchun Chen Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/sources | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/dkms/sources b/drivers/gpu/drm/amd/dkms/sources index a1b74441203de..da9e9612a23fb 100644 --- a/drivers/gpu/drm/amd/dkms/sources +++ b/drivers/gpu/drm/amd/dkms/sources @@ -28,3 +28,4 @@ include/drm/amd_rdma.h include/drm/ drivers/dma-buf/dma-resv.c amd/amdkcl/dma-buf/ include/linux/dma-resv.h include/linux/ include/kcl/reservation.h include/linux/ +include/uapi/linux/kfd_sysfs.h include/uapi/linux/ From 342c3f0e491823a08be00f95958c0c170288ac17 Mon Sep 17 00:00:00 2001 From: Guchun Chen Date: Mon, 8 Nov 2021 14:58:25 +0800 Subject: [PATCH 0532/1868] drm/amdkcl: guard amdgpu_driver_release_kms by HAVE_DRM_DRIVER_RELEASE Fix: 1776040c6227("drm/amd/amdkcl: fix minor index not removed after unload driver") Signed-off-by: Guchun Chen Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index a7599d6cbbd5c..d56eb39de6f43 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -1513,7 +1513,7 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev, pm_runtime_put_autosuspend(dev->dev); } - +#ifdef HAVE_DRM_DRIVER_RELEASE void amdgpu_driver_release_kms(struct drm_device *dev) { struct amdgpu_device *adev = drm_to_adev(dev); @@ -1525,6 +1525,7 @@ void amdgpu_driver_release_kms(struct drm_device *dev) kfree(adev); #endif } +#endif /* * VBlank related functions. From 51f80a5492d7429fef264e66bf105f29b7abd65d Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 8 Nov 2021 10:55:23 +0800 Subject: [PATCH 0533/1868] drm/amdkcl: drop drmP.h in kcl_drm_simple_encoder_init.h Fix a intree build error caused by 925fd65464c80f28ed1bea7357c7389acbb618ea "drm/amdkcl: fake drm_simple_encoder_init" Signed-off-by: Asher Song Reviewed-by: Flora Cui --- include/kcl/kcl_drm_simple_kms_helper.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/kcl/kcl_drm_simple_kms_helper.h b/include/kcl/kcl_drm_simple_kms_helper.h index 51a6699486da0..f6a5ac0c15d00 100644 --- a/include/kcl/kcl_drm_simple_kms_helper.h +++ b/include/kcl/kcl_drm_simple_kms_helper.h @@ -4,7 +4,7 @@ */ #include -#include +#include #include #include From 78be80aa0080e4a23800661ed54fd05e233c36da Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 1 Nov 2021 20:18:06 +0800 Subject: [PATCH 0534/1868] drm/amdkcl: assign dpms for amdgpu_vkms_crtc_helper_funcs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In drm_helper_disable_unused_functions(), when !crtc->enable is false, a NULL pointer crtc_funcs->dpms may occur. To avoid this, assign dpms for amdgpu_vkms_crtc_helper_funcs. Call Trace: __drm_helper_disable_unused_functions+0xac/0xe0 [drm_kms_helper] drm_helper_disable_unused_functions+0x38/0x60 [drm_kms_helper] amdgpu_fbdev_init+0xf6/0x100 [amdgpu] amdgpu_device_init+0x13d4/0x1f10 [amdgpu] Fixes: ba5317109d0ce ("drm/amdgpu: create amdgpu_vkms (v4)") Ackded-by：Guchun Chen Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 26 ++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c index 466596481fe69..e679dc267aabb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c @@ -173,7 +173,33 @@ static void amdgpu_vkms_crtc_atomic_flush(struct drm_crtc *crtc, } } +static void amdgpu_vkms_crtc_dpms(struct drm_crtc *crtc, int mode) +{ + struct drm_device *dev = crtc->dev; + struct amdgpu_device *adev = drm_to_adev(dev); + struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + unsigned type; + + switch (mode) { + case DRM_MODE_DPMS_ON: + amdgpu_crtc->enabled = true; + /* Make sure VBLANK interrupts are still enabled */ + type = amdgpu_display_crtc_idx_to_irq_type(adev, + amdgpu_crtc->crtc_id); + amdgpu_irq_update(adev, &adev->crtc_irq, type); + drm_crtc_vblank_on(crtc); + break; + case DRM_MODE_DPMS_STANDBY: + case DRM_MODE_DPMS_SUSPEND: + case DRM_MODE_DPMS_OFF: + drm_crtc_vblank_off(crtc); + amdgpu_crtc->enabled = false; + break; + } +} + static const struct drm_crtc_helper_funcs amdgpu_vkms_crtc_helper_funcs = { + .dpms = amdgpu_vkms_crtc_dpms, .atomic_flush = amdgpu_vkms_crtc_atomic_flush, #if defined(HAVE_DRM_CRTC_HELPER_FUNCS_HAVE_ATOMIC_ENABLE) .atomic_enable = amdgpu_vkms_crtc_atomic_enable, From fcba95b0583d8e43cfa7a9d158cdeff909f1ad6c Mon Sep 17 00:00:00 2001 From: Ramesh Errabolu Date: Tue, 26 Oct 2021 17:35:34 -0500 Subject: [PATCH 0535/1868] drm/amdkfd: Pin MMIO/DOORBELL BO's in GTT domain MMIO/DOORBELL BOs encode control data and should be pinned in GTT domain before enabling PCIe connected peer devices in accessing it Signed-off-by: Ramesh Errabolu Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 23 ++++++++++++++++++- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 17 ++++++++++++++ drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c | 3 ++- 3 files changed, 41 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index 84f396cedeef9..5f2c94d2b696f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -338,7 +338,28 @@ struct amdgpu_bo *amdgpu_amdkfd_gpuvm_get_bo_ref(struct kgd_mem *mem, uint32_t *flags); void amdgpu_amdkfd_gpuvm_put_bo_ref(struct amdgpu_bo *bo); -int amdgpu_amdkfd_gpuvm_pin_bo(struct amdgpu_bo *bo); +/** + * amdgpu_amdkfd_gpuvm_pin_bo() - Pins a BO using following criteria + * @bo: Handle of buffer object being pinned + * @domain: Domain into which BO should be pinned + * + * - USERPTR BOs are UNPINNABLE and will return error + * - All other BO types (GTT, VRAM, MMIO and DOORBELL) will have their + * PIN count incremented. It is valid to PIN a BO multiple times + * + * Return: ZERO if successful in pinning, Non-Zero in case of error. + * Will return -EINVAL if input BO parameter is a USERPTR type. + */ +int amdgpu_amdkfd_gpuvm_pin_bo(struct amdgpu_bo *bo, u32 domain); + +/** + * amdgpu_amdkfd_gpuvm_unpin_bo() - Unpins BO using following criteria + * @bo: Handle of buffer object being unpinned + * + * - Is a illegal request for USERPTR BOs and is ignored + * - All other BO types (GTT, VRAM, MMIO and DOORBELL) will have their + * PIN count decremented. Calls to UNPIN must balance calls to PIN + */ void amdgpu_amdkfd_gpuvm_unpin_bo(struct amdgpu_bo *bo); int amdgpu_amdkfd_gpuvm_get_sg_table(struct kgd_dev *kgd, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 5bfd2fe253488..4732efea13c5c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -1957,6 +1957,23 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( if (offset) *offset = amdgpu_bo_mmap_offset(bo); + if (flags & (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL | + KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) { + ret = amdgpu_amdkfd_bo_validate(bo, AMDGPU_GEM_DOMAIN_GTT, false); + if (ret) { + pr_err("Validating MMIO/DOORBELL BO during ALLOC FAILED\n"); + goto err_node_allow; + } + + ret = amdgpu_amdkfd_gpuvm_pin_bo(bo, AMDGPU_GEM_DOMAIN_GTT); + if (ret) { + pr_err("Pinning MMIO/DOORBELL BO during ALLOC FAILED\n"); + goto err_node_allow; + } + bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT; + bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT; + } + return 0; allocate_init_user_pages_failed: diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c b/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c index 27fe96b788de6..f8c89ba5ff86b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c @@ -261,7 +261,8 @@ static int amd_get_pages(unsigned long addr, size_t size, int write, int force, return -EINVAL; } - ret = amdgpu_amdkfd_gpuvm_pin_bo(mem_context->bo); + ret = amdgpu_amdkfd_gpuvm_pin_bo(mem_context->bo, + mem_context->bo->kfd_bo->domain); if (ret) { pr_err("Pinning of buffer failed.\n"); return ret; From 7ddacf575da7ac4dd9e6eb0331f7b10bfd4618a1 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 9 Nov 2021 17:49:38 +0800 Subject: [PATCH 0536/1868] drm/amdkcl: nuke dpms callback Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 22 +--------------------- 1 file changed, 1 insertion(+), 21 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c index e679dc267aabb..73ef25c5172fc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c @@ -175,27 +175,7 @@ static void amdgpu_vkms_crtc_atomic_flush(struct drm_crtc *crtc, static void amdgpu_vkms_crtc_dpms(struct drm_crtc *crtc, int mode) { - struct drm_device *dev = crtc->dev; - struct amdgpu_device *adev = drm_to_adev(dev); - struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); - unsigned type; - - switch (mode) { - case DRM_MODE_DPMS_ON: - amdgpu_crtc->enabled = true; - /* Make sure VBLANK interrupts are still enabled */ - type = amdgpu_display_crtc_idx_to_irq_type(adev, - amdgpu_crtc->crtc_id); - amdgpu_irq_update(adev, &adev->crtc_irq, type); - drm_crtc_vblank_on(crtc); - break; - case DRM_MODE_DPMS_STANDBY: - case DRM_MODE_DPMS_SUSPEND: - case DRM_MODE_DPMS_OFF: - drm_crtc_vblank_off(crtc); - amdgpu_crtc->enabled = false; - break; - } + return; } static const struct drm_crtc_helper_funcs amdgpu_vkms_crtc_helper_funcs = { From c5230d98c1a153fa610eafdeb57d66860e64fda9 Mon Sep 17 00:00:00 2001 From: Ramesh Errabolu Date: Wed, 10 Nov 2021 15:04:58 -0600 Subject: [PATCH 0537/1868] drm/amdgpu: Fix error handling path while allocating MMIO/DOORBELL BOs MMIO/DOORBELL BOs are pinned as part allocation procedure. The patch fixes a bug in error handling part of pinning MMIO/DOORBELL BO Signed-off-by: Ramesh Errabolu Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 1 - drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 8 +------- 2 files changed, 1 insertion(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index 5f2c94d2b696f..e6efb76f19046 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -348,7 +348,6 @@ void amdgpu_amdkfd_gpuvm_put_bo_ref(struct amdgpu_bo *bo); * PIN count incremented. It is valid to PIN a BO multiple times * * Return: ZERO if successful in pinning, Non-Zero in case of error. - * Will return -EINVAL if input BO parameter is a USERPTR type. */ int amdgpu_amdkfd_gpuvm_pin_bo(struct amdgpu_bo *bo, u32 domain); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 4732efea13c5c..cd9d969378081 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -1959,16 +1959,10 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( if (flags & (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL | KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) { - ret = amdgpu_amdkfd_bo_validate(bo, AMDGPU_GEM_DOMAIN_GTT, false); - if (ret) { - pr_err("Validating MMIO/DOORBELL BO during ALLOC FAILED\n"); - goto err_node_allow; - } - ret = amdgpu_amdkfd_gpuvm_pin_bo(bo, AMDGPU_GEM_DOMAIN_GTT); if (ret) { pr_err("Pinning MMIO/DOORBELL BO during ALLOC FAILED\n"); - goto err_node_allow; + goto err_pin_bo; } bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT; bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT; From e5f47313a19d35bcb1ece04f1cd83f3f3c590762 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 11 Nov 2021 14:09:46 +0800 Subject: [PATCH 0538/1868] drm/amdkcl: check whether drm_fbdev_generic_setup() is available It's caused by 844612e1149d0cd6fd2346018c91f5744b2615f5 "drm/amdgpu: use generic fb helpers instead of setting up AMD own's." v5.13-2445-g844612e1149d Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../drm/amd/dkms/m4/drm-fbdev-generic-setup.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 20 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-fbdev-generic-setup.m4 diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 087e718c16ab9..4ec060c7b20cf 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -462,6 +462,9 @@ /* drm_encoder_find() wants file_priv */ #define HAVE_DRM_ENCODER_FIND_VALID_WITH_FILE 1 +/* drm_fbdev_generic_setup() is available */ +#define HAVE_DRM_FBDEV_GENERIC_SETUP 1 + /* drm_fb_helper_single_add_all_connectors() && drm_fb_helper_remove_one_connector() are symbol */ /* #undef HAVE_DRM_FB_HELPER_ADD_REMOVE_CONNECTORS */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-fbdev-generic-setup.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-fbdev-generic-setup.m4 new file mode 100644 index 0000000000000..cfd16b033ccbf --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-fbdev-generic-setup.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v4.18-rc3-614-g9060d7f49376 +dnl # drm/fb-helper: Finish the generic fbdev emulation +dnl # +AC_DEFUN([AC_AMDGPU_DRM_FBDEV_GENERIC_SETUP], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_fbdev_generic_setup(NULL, 0); + ], [drm_fbdev_generic_setup], [drivers/gpu/drm/drm_fb_helper.c],[ + AC_DEFINE(HAVE_DRM_FBDEV_GENERIC_SETUP, 1, + [drm_fbdev_generic_setup() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 527a8c168ff85..86c1fa8ffebc8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -176,6 +176,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_GET_MM_EXE_FILE AC_AMDGPU_DRM_SIMPLE_ENCODER_INIT AC_AMDGPU_DRM_MODE_CONFIG_HELPER_SUSPEND + AC_AMDGPU_DRM_FBDEV_GENERIC_SETUP AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From d6f6c605ef51e56092967fdc92e574829900e42f Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 11 Nov 2021 15:07:23 +0800 Subject: [PATCH 0539/1868] drm/amdkcl: check whether struct drm_device has fb_helper member It's caused by 844612e1149d0cd6fd2346018c91f5744b2615f5 "drm/amdgpu: use generic fb helpers instead of setting up AMD own's." v5.13-2445-g844612e1149d Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/Makefile | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 16 ++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 3 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 29 +++++++++++++++++++ .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 5 +++- drivers/gpu/drm/amd/dkms/config/config.h | 3 ++ .../drm/amd/dkms/m4/drm-device-fb-helper.m4 | 21 ++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 8 files changed, 78 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-device-fb-helper.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index 37347b2d30374..e275c73f81c68 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -66,7 +66,7 @@ amdgpu-y += amdgpu_device.o amdgpu_doorbell_mgr.o amdgpu_kms.o \ amdgpu_atombios.o atombios_crtc.o amdgpu_connectors.o \ atom.o amdgpu_fence.o amdgpu_ttm.o amdgpu_object.o amdgpu_gart.o \ amdgpu_encoders.o amdgpu_display.o amdgpu_i2c.o \ - amdgpu_gem.o amdgpu_ring.o \ + amdgpu_fb.o amdgpu_gem.o amdgpu_ring.o \ amdgpu_cs.o amdgpu_bios.o amdgpu_benchmark.o \ atombios_dp.o amdgpu_afmt.o amdgpu_trace_points.o \ atombios_encoders.o amdgpu_sa.o atombios_i2c.o \ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index a47dd8dd18e36..bccfc2ba7ac05 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -4712,7 +4712,11 @@ int amdgpu_device_suspend(struct drm_device *dev, bool fbcon) DRM_WARN("smart shift update failed\n"); if (fbcon) +#ifdef HAVE_DRM_DEVICE_FB_HELPER drm_fb_helper_set_suspend_unlocked(adev_to_drm(adev)->fb_helper, true); +#else + amdgpu_fbdev_set_suspend(adev, 1); +#endif cancel_delayed_work_sync(&adev->delayed_init_work); @@ -4810,7 +4814,11 @@ int amdgpu_device_resume(struct drm_device *dev, bool fbcon) flush_delayed_work(&adev->delayed_init_work); if (fbcon) +#ifdef HAVE_DRM_DEVICE_FB_HELPER drm_fb_helper_set_suspend_unlocked(adev_to_drm(adev)->fb_helper, false); +#else + amdgpu_fbdev_set_suspend(adev, 0); +#endif amdgpu_ras_resume(adev); @@ -5500,7 +5508,11 @@ int amdgpu_do_asic_reset(struct list_head *device_list_handle, if (r) goto out; +#ifdef HAVE_DRM_DEVICE_FB_HELPER drm_fb_helper_set_suspend_unlocked(adev_to_drm(tmp_adev)->fb_helper, false); +#else + amdgpu_fbdev_set_suspend(tmp_adev, 0); +#endif /* * The GPU enters bad state once faulty pages @@ -5788,7 +5800,11 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, */ amdgpu_unregister_gpu_instance(tmp_adev); +#ifdef HAVE_DRM_DEVICE_FB_HELPER drm_fb_helper_set_suspend_unlocked(adev_to_drm(tmp_adev)->fb_helper, true); +#else + amdgpu_fbdev_set_suspend(tmp_adev, 1); +#endif /* disable ras on ALL IPs */ if (!need_emergency_restart && diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c index 2367c391e6f33..7fbd2b4f964b9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c @@ -24,6 +24,8 @@ * David Airlie */ +#ifndef HAVE_DRM_DEVICE_FB_HELPER + #include #include #include @@ -412,3 +414,4 @@ bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj) return true; return false; } +#endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index 50eb99f45c937..b0f3350c3e0a0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -231,6 +231,11 @@ struct amdgpu_i2c_chan { struct mutex mutex; }; + +#ifndef HAVE_DRM_DEVICE_FB_HELPER +struct amdgpu_fbdev; +#endif + struct amdgpu_afmt { bool enabled; int offset; @@ -310,6 +315,15 @@ struct amdgpu_framebuffer { uint64_t address; }; +#ifndef HAVE_DRM_DEVICE_FB_HELPER +struct amdgpu_fbdev { + struct drm_fb_helper helper; + struct amdgpu_framebuffer rfb; + struct list_head fbdev_list; + struct amdgpu_device *adev; +}; +#endif + struct amdgpu_mode_info { struct atom_context *atom_context; struct card_info *atom_card_info; @@ -332,6 +346,10 @@ struct amdgpu_mode_info { /* hardcoded DFP edid from BIOS */ const struct drm_edid *bios_hardcoded_edid; +#ifndef HAVE_DRM_DEVICE_FB_HELPER + /* pointer to fbdev info structure */ + struct amdgpu_fbdev *rfbdev; +#endif /* firmware flags */ u32 firmware_flags; /* pointer to backlight encoder */ @@ -703,6 +721,17 @@ bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc, int *hpos, ktime_t *stime, ktime_t *etime, const struct drm_display_mode *mode); +#ifndef HAVE_DRM_DEVICE_FB_HELPER +/* fbdev layer */ +int amdgpu_fbdev_init(struct amdgpu_device *adev); +void amdgpu_fbdev_fini(struct amdgpu_device *adev); +void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state); +int amdgpu_fbdev_total_size(struct amdgpu_device *adev); +bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj); + +int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int bpp, bool tiled); +#endif + /* amdgpu_display.c */ void amdgpu_display_print_display_setup(struct drm_device *dev); int amdgpu_display_modeset_create_props(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 35233ab24bbab..16e103d403fbc 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -822,7 +822,7 @@ static void dm_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr, mutex_unlock(&mgr->lock); } drm_connector_unregister(connector); -#ifdef HAVE_DRM_FB_HELPER_ADD_REMOVE_CONNECTORS +#if defined(HAVE_DRM_FB_HELPER_ADD_REMOVE_CONNECTORS) && !defined(HAVE_DRM_DEVICE_FB_HELPER) if (adev->mode_info.rfbdev) drm_fb_helper_remove_one_connector(&adev->mode_info.rfbdev->helper, connector); #endif @@ -849,10 +849,13 @@ static void dm_dp_mst_register_connector(struct drm_connector *connector) #ifndef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_modeset_lock_all(dev); #endif + +#ifndef HAVE_DRM_DEVICE_FB_HELPER if (adev->mode_info.rfbdev) drm_fb_helper_add_one_connector(&adev->mode_info.rfbdev->helper, connector); else DRM_ERROR("adev->mode_info.rfbdev is NULL\n"); +#endif #ifndef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_modeset_unlock_all(dev); diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 4ec060c7b20cf..32b8940f5385e 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -257,6 +257,9 @@ /* dev_device->driver_features is available */ #define HAVE_DRM_DEVICE_DRIVER_FEATURES 1 +/* struct drm_device has fb_helper member */ +#define HAVE_DRM_DEVICE_FB_HELPER 1 + /* drm_device->filelist_mutex is available */ #define HAVE_DRM_DEVICE_FILELIST_MUTEX 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-device-fb-helper.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-device-fb-helper.m4 new file mode 100644 index 0000000000000..b5e24caf0a842 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-device-fb-helper.m4 @@ -0,0 +1,21 @@ +dnl # +dnl # commit v4.14-rc3-575-g29ad20b22c8f +dnl # drm: Add drm_device->fb_helper pointer +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DEVICE_FB_HELPER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DRMP_H + #include + #endif + #ifdef HAVE_DRM_DRM_DEVICE_H + #include + #endif + ], [ + struct drm_device *pdd = NULL; + pdd->fb_helper = NULL; + ], [ + AC_DEFINE(HAVE_DRM_DEVICE_FB_HELPER, 1, [struct drm_device has fb_helper member]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 86c1fa8ffebc8..0c54e161eaeaa 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -177,6 +177,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_SIMPLE_ENCODER_INIT AC_AMDGPU_DRM_MODE_CONFIG_HELPER_SUSPEND AC_AMDGPU_DRM_FBDEV_GENERIC_SETUP + AC_AMDGPU_DRM_DEVICE_FB_HELPER AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 707730baea90594ed6691540982e714ded24b015 Mon Sep 17 00:00:00 2001 From: Jonathan Kim Date: Fri, 12 Nov 2021 12:40:38 -0500 Subject: [PATCH 0540/1868] drm/amdkfd: remove unused variable in alloc gpuvm Unused "int mem_type" got removed in drm-next during alloc gpuvm update but not in dkms staging for whatever reason. Remove it to silence the usused variable warning during compile. Signed-off-by: Jonathan Kim Reviewed-by: Kevin Wang --- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 74d7ec4f3e389..0ee35921f7a8a 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -728,7 +728,6 @@ static int kfd_process_alloc_gpuvm(struct kfd_process_device *pdd, { struct kfd_node *kdev = pdd->dev; int err; - unsigned int mem_type; err = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(kdev->adev, gpu_va, size, pdd->drm_priv, mem, NULL, From 64da9e134d7bff9fc2f48ba5e4c352056365fdac Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 15 Nov 2021 17:38:07 +0800 Subject: [PATCH 0541/1868] drm/amdgpu: fix amdgpu_vkms support otherwise adev->mode_info.crtcs[] & adev->mode_info.funcs are NULL and would trigger NULL pointer error Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 69 +++++++++++++++++++++++- 1 file changed, 68 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c index 73ef25c5172fc..f064eab569beb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c @@ -522,6 +522,73 @@ static int amdgpu_vkms_output_init(struct drm_device *dev, struct return ret; } +static u32 amdgpu_vkms_vblank_get_counter(struct amdgpu_device *adev, int crtc) +{ + return 0; +} + +static void amdgpu_vkms_page_flip(struct amdgpu_device *adev, + int crtc_id, u64 crtc_base, bool async) +{ + return; +} + +static int amdgpu_vkms_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc, + u32 *vbl, u32 *position) +{ + *vbl = 0; + *position = 0; + + return -EINVAL; +} + +static bool amdgpu_vkms_hpd_sense(struct amdgpu_device *adev, + enum amdgpu_hpd_id hpd) +{ + return true; +} + +static void amdgpu_vkms_hpd_set_polarity(struct amdgpu_device *adev, + enum amdgpu_hpd_id hpd) +{ + return; +} + +static u32 amdgpu_vkms_hpd_get_gpio_reg(struct amdgpu_device *adev) +{ + return 0; +} + +static void amdgpu_vkms_bandwidth_update(struct amdgpu_device *adev) +{ + return; +} + +static const struct amdgpu_display_funcs amdgpu_vkms_display_funcs = { + .bandwidth_update = &amdgpu_vkms_bandwidth_update, + .vblank_get_counter = &amdgpu_vkms_vblank_get_counter, + .backlight_set_level = NULL, + .backlight_get_level = NULL, + .hpd_sense = &amdgpu_vkms_hpd_sense, + .hpd_set_polarity = &amdgpu_vkms_hpd_set_polarity, + .hpd_get_gpio_reg = &amdgpu_vkms_hpd_get_gpio_reg, + .page_flip = &amdgpu_vkms_page_flip, + .page_flip_get_scanoutpos = &amdgpu_vkms_crtc_get_scanoutpos, + .add_encoder = NULL, + .add_connector = NULL, +}; + +static int amdgpu_vkms_early_init(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + adev->mode_info.funcs = &amdgpu_vkms_display_funcs; + + adev->mode_info.num_hpd = 1; + adev->mode_info.num_dig = 1; + return 0; +} + const struct drm_mode_config_funcs amdgpu_vkms_mode_funcs = { .fb_create = amdgpu_display_user_framebuffer_create, .atomic_check = drm_atomic_helper_check, @@ -691,7 +758,7 @@ static int amdgpu_vkms_set_powergating_state(void *handle, static const struct amd_ip_funcs amdgpu_vkms_ip_funcs = { .name = "amdgpu_vkms", - .early_init = NULL, + .early_init = amdgpu_vkms_early_init, .late_init = NULL, .sw_init = amdgpu_vkms_sw_init, .sw_fini = amdgpu_vkms_sw_fini, From 62a1eb543bfec159b82037982a517bc33fc47d60 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 11 Nov 2021 15:55:39 +0800 Subject: [PATCH 0542/1868] drm/amdkcl: check whether drm_dp_update_payload_part1() has start_slot argument It's caused by cf95d5c0c94100fd76bb590657ceb94db4097c42 "drm: Update MST First Link Slot Information Based on Encoding Format" v5.13-2803-gcf95d5c0c941 Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ ...drm-up-update-payload-part1-start-slot-arg.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 20 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-up-update-payload-part1-start-slot-arg.m4 diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 32b8940f5385e..6209ae0f757a7 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -359,6 +359,9 @@ /* drm_dp_start_crc() is available */ #define HAVE_DRM_DP_START_CRC 1 +/* drm_dp_update_payload_part1() function has start_slot argument */ +#define HAVE_DRM_DP_UPDATE_PAYLOAD_PART1_START_SLOT_ARG 1 + /* drm_driver->gem_prime_res_obj() is available */ /* #undef HAVE_DRM_DRIVER_GEM_PRIME_RES_OBJ */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-up-update-payload-part1-start-slot-arg.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-up-update-payload-part1-start-slot-arg.m4 new file mode 100644 index 0000000000000..1b341003bb985 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-up-update-payload-part1-start-slot-arg.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.13-2803-gcf95d5c0c941 +dnl # drm: Update MST First Link Slot Information Based on Encoding Format +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_UPDATE_PAYLOAD_PART1_START_SLOT_ARG], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_dp_update_payload_part1(NULL, 0); + ], [ + AC_DEFINE(HAVE_DRM_DP_UPDATE_PAYLOAD_PART1_START_SLOT_ARG, 1, + [drm_dp_update_payload_part1() function has start_slot argument]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 0c54e161eaeaa..dedafa2f6e508 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -178,6 +178,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_MODE_CONFIG_HELPER_SUSPEND AC_AMDGPU_DRM_FBDEV_GENERIC_SETUP AC_AMDGPU_DRM_DEVICE_FB_HELPER + AC_AMDGPU_DRM_DP_UPDATE_PAYLOAD_PART1_START_SLOT_ARG AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 66cdafb89d95b87e312e633518c6ec71c716c798 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 15 Nov 2021 13:03:51 +0800 Subject: [PATCH 0543/1868] drm/amdkcl: test whether struct drm_dp_mst_topology_state has member total_avail_slots It's caused by cf95d5c0c94100fd76bb590657ceb94db4097c42 "drm: Update MST First Link Slot Information Based on Encoding Format" v5.13-2803-gcf95d5c0c941 Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../amd/dkms/m4/drm-dp-mst-topology-state.m4 | 18 ++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 24 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 152c71d076157..df830e4343f38 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -11867,6 +11867,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, lock_and_validation_needed = true; } +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS /* set the slot info for each mst_state based on the link encoding format */ for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) { struct amdgpu_dm_connector *aconnector; @@ -11886,7 +11887,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, } drm_connector_list_iter_end(&iter); } - +#endif /** * Streams and planes are reset when there are changes that affect * bandwidth. Anything that affects bandwidth needs to go through diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 6209ae0f757a7..c448f4fcde788 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -353,6 +353,9 @@ /* drm_dp_mst_topology_mgr_resume() wants 2 args */ #define HAVE_DRM_DP_MST_TOPOLOGY_MGR_RESUME_2ARGS 1 +/* struct drm_dp_mst_topology_state has member total_avail_slots */ +#define HAVE_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS 1 + /* drm_dp_send_real_edid_checksum() is available */ #define HAVE_DRM_DP_SEND_REAL_EDID_CHECKSUM 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 new file mode 100644 index 0000000000000..bd46fb9e30abb --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit v4.11-rc7-1869-g3f3353b7e121 +dnl # drm/dp: Introduce MST topology state to track available link bandwidth +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_dp_mst_topology_state * mst_state = NULL; + mst_state->total_avail_slots = 0; + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS, 1, + [struct drm_dp_mst_topology_state has member total_avail_slots]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index dedafa2f6e508..ffaa94fdbbae8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -179,6 +179,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_FBDEV_GENERIC_SETUP AC_AMDGPU_DRM_DEVICE_FB_HELPER AC_AMDGPU_DRM_DP_UPDATE_PAYLOAD_PART1_START_SLOT_ARG + AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 3ac1424613809bb302204c0612f5392f0bc5b9b0 Mon Sep 17 00:00:00 2001 From: Guchun Chen Date: Tue, 16 Nov 2021 14:57:28 +0800 Subject: [PATCH 0544/1868] drm/amdkcl: temporarily drop vblank_timer in amdgpu_vkms This code needs to be re-visited from upstream, so drop vblank_timer first to prevent NULL access pointer when conducting guest driver unload test in SRIOV case. Signed-off-by: Guchun Chen Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c index f064eab569beb..8c9f57db9b5f2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c @@ -641,11 +641,6 @@ static int amdgpu_vkms_sw_init(void *handle) static int amdgpu_vkms_sw_fini(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; - int i = 0; - - for (i = 0; i < adev->mode_info.num_crtc; i++) - if (adev->mode_info.crtcs[i]) - hrtimer_cancel(&adev->mode_info.crtcs[i]->vblank_timer); drm_kms_helper_poll_fini(adev_to_drm(adev)); drm_mode_config_cleanup(adev_to_drm(adev)); From 71e421495dfd6c7397f8b910acd90e251cf2654e Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Fri, 12 Nov 2021 11:22:38 -0500 Subject: [PATCH 0545/1868] drm/amdkcl: use autoconf to tarck amdgpu version Change-Id: Idef567dd18760272fbc5e4b7fda76d35f47062d0 Signed-off-by: Slava Grigorev Reviewed-by: Jeremy Newton Reviewed-by: Rui Teng --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 1 - drivers/gpu/drm/amd/dkms/configure.ac | 2 +- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index eddcac8a2cbe5..a1fdbd53a94b3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -123,7 +123,6 @@ #define KMS_DRIVER_MINOR 59 #define KMS_DRIVER_PATCHLEVEL 0 -#define AMDGPU_VERSION "19.10.9.418" /* * amdgpu.debug module options. Are all disabled by default */ diff --git a/drivers/gpu/drm/amd/dkms/configure.ac b/drivers/gpu/drm/amd/dkms/configure.ac index b367e452d4cbb..71855ccd6e523 100644 --- a/drivers/gpu/drm/amd/dkms/configure.ac +++ b/drivers/gpu/drm/amd/dkms/configure.ac @@ -1,4 +1,4 @@ -AC_INIT(amdgpu-dkms, 19.40) +AC_INIT(amdgpu-dkms, 5.13.5) AC_LANG(C) AC_CONFIG_AUX_DIR([config]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index ffaa94fdbbae8..93f50740bbe2a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -188,6 +188,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_SUBST(KERNEL_MAKE) AH_BOTTOM([#include "config-amd-chips.h"]) + AH_BOTTOM([#define AMDGPU_VERSION PACKAGE_VERSION]) ]) dnl # From dbee431e51888188a72af06dda4650d953ceab33 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Thu, 18 Nov 2021 09:59:29 -0500 Subject: [PATCH 0546/1868] Version strings in DKMS config.h Correct version strings in config.h and add AMDGPU_VERSION macro to fix in-tree kernel build. Other diffs observed in the file after regeneration are pointing to problematic tests that may affect DKMS functionality. They have to be re-visited and fixed. The list of suspicious test results is: HAVE_ACPI_PUT_TABLE HAVE_DRM_CONNECTOR_ATOMIC_HDR_METADATA_EQUAL HAVE_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY HAVE_DRM_DP_LINK_TRAIN_CHANNEL_EQ_DELAY_2ARGS HAVE_DRM_DP_LINK_TRAIN_CLOCK_RECOVERY_DELAY_2ARGS Change-Id: I5afb975182c029d047f71356098514196b719aee Signed-off-by: Slava Grigorev --- drivers/gpu/drm/amd/dkms/config/config.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index c448f4fcde788..a7cc3bf23c054 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1127,7 +1127,7 @@ #define PACKAGE_NAME "amdgpu-dkms" /* Define to the full name and version of this package. */ -#define PACKAGE_STRING "amdgpu-dkms 19.40" +#define PACKAGE_STRING "amdgpu-dkms 5.13.6" /* Define to the one symbol short name of this package. */ #define PACKAGE_TARNAME "amdgpu-dkms" @@ -1136,6 +1136,8 @@ #define PACKAGE_URL "" /* Define to the version of this package. */ -#define PACKAGE_VERSION "19.40" +#define PACKAGE_VERSION "5.13.6" #include "config-amd-chips.h" + +#define AMDGPU_VERSION PACKAGE_VERSION From 3af5db06f14f8f191a8c3a16b4a33d1c2dd02983 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 18 Nov 2021 16:17:34 +0800 Subject: [PATCH 0547/1868] drm/amdkcl: guard CONFIG_X86 for x86 related stuff Signed-off-by: Flora Cui Tested-by: Emily.Deng Reviewed-by: Leslie Shi --- include/kcl/kcl_intel_family.h | 4 +++- include/kcl/kcl_mce.h | 4 ++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/include/kcl/kcl_intel_family.h b/include/kcl/kcl_intel_family.h index 20781af676d6b..a4d7693bf0b0b 100644 --- a/include/kcl/kcl_intel_family.h +++ b/include/kcl/kcl_intel_family.h @@ -2,11 +2,13 @@ #ifndef AMDKCL_INTEL_FAMILY_H #define AMDKCL_INTEL_FAMILY_H +#ifdef CONFIG_X86 + #include /* Copied froma asm/intel-family.h*/ #ifndef INTEL_FAM6_ROCKETLAKE #define INTEL_FAM6_ROCKETLAKE 0xA7 #endif +#endif /* CONFIG_X86 */ #endif - diff --git a/include/kcl/kcl_mce.h b/include/kcl/kcl_mce.h index 037fb0c1b3e37..5418ec9351e36 100644 --- a/include/kcl/kcl_mce.h +++ b/include/kcl/kcl_mce.h @@ -2,10 +2,14 @@ #ifndef AMDKCL_MCE_H #define AMDKCL_MCE_H +#ifdef CONFIG_X86 + #include + /* Copied from asm/mce.h */ #ifndef XEC #define XEC(x, mask) (((x) >> 16) & mask) #endif +#endif /* CONFIG_X86 */ #endif From 8a0ae35ecc35f807176a37f052a201d8cade22ab Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 18 Nov 2021 16:18:34 +0800 Subject: [PATCH 0548/1868] drm/amdkcl: misc fix for autoconf test Signed-off-by: Flora Cui Tested-by: Emily.Deng Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/m4/access-ok.m4 | 2 +- drivers/gpu/drm/amd/dkms/m4/mem_encrypt_active.m4 | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/access-ok.m4 b/drivers/gpu/drm/amd/dkms/m4/access-ok.m4 index 066bd767ddf78..70a1ec664ef7f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/access-ok.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/access-ok.m4 @@ -9,7 +9,7 @@ AC_DEFUN([AC_AMDGPU_ACCESS_OK_WITH_TWO_ARGUMENTS], [ AC_KERNEL_TRY_COMPILE([ #include ],[ - access_ok(1, 1); + access_ok(0, 0); ],[ AC_DEFINE(HAVE_ACCESS_OK_WITH_TWO_ARGUMENTS, 1, [whether access_ok(x, x) is available]) diff --git a/drivers/gpu/drm/amd/dkms/m4/mem_encrypt_active.m4 b/drivers/gpu/drm/amd/dkms/m4/mem_encrypt_active.m4 index ad484a873022a..5b80d8cf1223a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/mem_encrypt_active.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/mem_encrypt_active.m4 @@ -5,6 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_MEM_ENCRYPT_ACTIVE], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ + #include #include ], [ mem_encrypt_active(); From 361385bd5c1ebffd97c78c9b25fbd8b00890d32c Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 22 Jan 2024 16:05:41 +0800 Subject: [PATCH 0549/1868] drm/amdkcl: fix vkms hrtimer settings Signed-off-by: Flora Cui Reviewed-by: Guchun Chen Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 69 +++++++++++++++++++++--- include/kcl/backport/kcl_drm_backport.h | 8 +++ 2 files changed, 70 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c index 8c9f57db9b5f2..f71604a513ff4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c @@ -47,6 +47,7 @@ static enum hrtimer_restart amdgpu_vkms_vblank_simulate(struct hrtimer *timer) { struct amdgpu_crtc *amdgpu_crtc = container_of(timer, struct amdgpu_crtc, vblank_timer); struct drm_crtc *crtc = &amdgpu_crtc->base; + struct amdgpu_device *adev = drm_to_adev(crtc->dev); struct amdgpu_vkms_output *output = drm_crtc_to_amdgpu_vkms_output(crtc); u64 ret_overrun; bool ret; @@ -100,7 +101,6 @@ static bool amdgpu_vkms_get_vblank_timestamp(struct drm_crtc *crtc, } *vblank_time = READ_ONCE(amdgpu_crtc->vblank_timer.node.expires); - if (WARN_ON(ktime_to_us(*vblank_time) == ktime_to_us(vblank->time))) return true; /* @@ -173,13 +173,8 @@ static void amdgpu_vkms_crtc_atomic_flush(struct drm_crtc *crtc, } } -static void amdgpu_vkms_crtc_dpms(struct drm_crtc *crtc, int mode) -{ - return; -} static const struct drm_crtc_helper_funcs amdgpu_vkms_crtc_helper_funcs = { - .dpms = amdgpu_vkms_crtc_dpms, .atomic_flush = amdgpu_vkms_crtc_atomic_flush, #if defined(HAVE_DRM_CRTC_HELPER_FUNCS_HAVE_ATOMIC_ENABLE) .atomic_enable = amdgpu_vkms_crtc_atomic_enable, @@ -219,12 +214,33 @@ static int amdgpu_vkms_crtc_init(struct drm_device *dev, struct drm_crtc *crtc, return ret; } +#ifdef AMDKCL_DRM_CONNECTOR_FUNCS_DPMS_MANDATORY +static int +amdgpu_vkms_connector_dpms(struct drm_connector *connector, int mode) +{ + return 0; +} + + +static int +amdgpu_vkms_connector_set_property(struct drm_connector *connector, + struct drm_property *property, + uint64_t val) +{ + return 0; +} +#endif + static const struct drm_connector_funcs amdgpu_vkms_connector_funcs = { .fill_modes = drm_helper_probe_single_connector_modes, .destroy = drm_connector_cleanup, .reset = drm_atomic_helper_connector_reset, .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, +#ifdef AMDKCL_DRM_CONNECTOR_FUNCS_DPMS_MANDATORY + .set_property = amdgpu_vkms_connector_set_property, + .dpms = amdgpu_vkms_connector_dpms, +#endif }; static int amdgpu_vkms_conn_get_modes(struct drm_connector *connector) @@ -522,6 +538,7 @@ static int amdgpu_vkms_output_init(struct drm_device *dev, struct return ret; } +#ifndef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP static u32 amdgpu_vkms_vblank_get_counter(struct amdgpu_device *adev, int crtc) { return 0; @@ -578,16 +595,47 @@ static const struct amdgpu_display_funcs amdgpu_vkms_display_funcs = { .add_connector = NULL, }; +static int amdgpu_vkms_set_crtc_irq_state(struct amdgpu_device *adev, + struct amdgpu_irq_src *source, + unsigned type, + enum amdgpu_interrupt_state state) +{ + if (type > AMDGPU_CRTC_IRQ_VBLANK6) + return -EINVAL; + + if (type >= adev->mode_info.num_crtc || !adev->mode_info.crtcs[type]) { + DRM_DEBUG("invalid crtc %d\n", type); + return -EINVAL; + } + + adev->mode_info.crtcs[type]->vsync_timer_enabled = state; + + if (state == AMDGPU_IRQ_STATE_ENABLE) + amdgpu_vkms_enable_vblank(&adev->mode_info.crtcs[type]->base); + else + amdgpu_vkms_disable_vblank(&adev->mode_info.crtcs[type]->base); + + return 0; +} + +static const struct amdgpu_irq_src_funcs amdgpu_vkms_crtc_irq_funcs = { + .set = amdgpu_vkms_set_crtc_irq_state, + .process = NULL, +}; + static int amdgpu_vkms_early_init(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; - adev->mode_info.funcs = &amdgpu_vkms_display_funcs; + adev->crtc_irq.num_types = adev->mode_info.num_crtc; + adev->crtc_irq.funcs = &amdgpu_vkms_crtc_irq_funcs; + adev->mode_info.funcs = &amdgpu_vkms_display_funcs; adev->mode_info.num_hpd = 1; adev->mode_info.num_dig = 1; return 0; } +#endif const struct drm_mode_config_funcs amdgpu_vkms_mode_funcs = { .fb_create = amdgpu_display_user_framebuffer_create, @@ -641,6 +689,11 @@ static int amdgpu_vkms_sw_init(void *handle) static int amdgpu_vkms_sw_fini(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; + int i = 0; + + for (i = 0; i < adev->mode_info.num_crtc; i++) + if (adev->mode_info.crtcs[i]) + hrtimer_cancel(&adev->mode_info.crtcs[i]->vblank_timer); drm_kms_helper_poll_fini(adev_to_drm(adev)); drm_mode_config_cleanup(adev_to_drm(adev)); @@ -753,7 +806,9 @@ static int amdgpu_vkms_set_powergating_state(void *handle, static const struct amd_ip_funcs amdgpu_vkms_ip_funcs = { .name = "amdgpu_vkms", +#ifndef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP .early_init = amdgpu_vkms_early_init, +#endif .late_init = NULL, .sw_init = amdgpu_vkms_sw_init, .sw_fini = amdgpu_vkms_sw_fini, diff --git a/include/kcl/backport/kcl_drm_backport.h b/include/kcl/backport/kcl_drm_backport.h index 668fa168e20bd..c17c10af84c09 100644 --- a/include/kcl/backport/kcl_drm_backport.h +++ b/include/kcl/backport/kcl_drm_backport.h @@ -22,4 +22,12 @@ #define AMDKCL_DMA_BUF_SHARE_ADDR_SPACE #endif +/* + * commit v4.13-rc2-365-g144a7999d633 + * drm: Handle properties in the core for atomic drivers + */ +#if DRM_VERSION_CODE < DRM_VERSION(4, 14, 0) +#define AMDKCL_DRM_CONNECTOR_FUNCS_DPMS_MANDATORY +#endif + #endif/*AMDKCL_DRM_BACKPORT_H*/ From 4df91e4fbf5620e74640ac1d572645ab41467836 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 18 Nov 2021 16:25:45 +0800 Subject: [PATCH 0550/1868] drm/amdkcl: update related flags for atomic unsupported case Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 6 ++++-- drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 2 +- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index a1fdbd53a94b3..6a4fec849537e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2259,8 +2259,10 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, return -ENODEV; } - if (amdgpu_aspm == -1 && !pcie_aspm_enabled(pdev)) - amdgpu_aspm = 0; + if (flags == 0) { + DRM_INFO("Unsupported asic. Remove me when IP discovery init is in place.\n"); + return -ENODEV; + } if (amdgpu_virtual_display || amdgpu_device_asic_has_dc_support(flags & AMD_ASIC_MASK)) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c index 7fbd2b4f964b9..6f1dd87d31ee9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c @@ -369,7 +369,7 @@ int amdgpu_fbdev_init(struct amdgpu_device *adev) } /* disable all the possible outputs/crtcs before entering KMS mode */ - if (!amdgpu_device_has_dc_support(adev)) + if (!drm_drv_uses_atomic_modeset(adev_to_drm(adev))) drm_helper_disable_unused_functions(adev_to_drm(adev)); drm_fb_helper_initial_config(&rfbdev->helper, bpp_sel); From 91fcdac8cd106d6499b4baf7b9196c65fabd61b2 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Fri, 19 Nov 2021 10:34:32 +0800 Subject: [PATCH 0551/1868] drm/amdkcl: add strict restriction when calling drm_fbdev_generic_setup It's caused by 844612e1149d0cd6fd2346018c91f5744b2615f5 "drm/amdgpu: use generic fb helpers instead of setting up AMD own's." v5.13-2445-g844612e1149d Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 14 ++++++++++---- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 13 +++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 7 +++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 8 ++++---- include/kcl/backport/kcl_drm_fb.h | 6 ++++++ 6 files changed, 41 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index bccfc2ba7ac05..1e3d527290ffc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -4346,6 +4346,9 @@ int amdgpu_device_init(struct amdgpu_device *adev, /* Get a log2 for easy divisions. */ adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps)); +#ifndef AMDKCL_DRM_FBDEV_GENERIC + amdgpu_fbdev_init(adev); +#endif /* * Register gpu instance before amdgpu_device_enable_mgpu_fan_boost. * Otherwise the mgpu fan boost feature will be skipped due to the @@ -4534,6 +4537,9 @@ void amdgpu_device_fini_hw(struct amdgpu_device *adev) amdgpu_reg_state_sysfs_fini(adev); +#ifndef AMDKCL_DRM_FBDEV_GENERIC + amdgpu_fbdev_fini(adev); +#endif /* disable ras feature must before hw fini */ amdgpu_ras_pre_fini(adev); @@ -4712,7 +4718,7 @@ int amdgpu_device_suspend(struct drm_device *dev, bool fbcon) DRM_WARN("smart shift update failed\n"); if (fbcon) -#ifdef HAVE_DRM_DEVICE_FB_HELPER +#ifdef AMDKCL_DRM_FBDEV_GENERIC drm_fb_helper_set_suspend_unlocked(adev_to_drm(adev)->fb_helper, true); #else amdgpu_fbdev_set_suspend(adev, 1); @@ -4814,7 +4820,7 @@ int amdgpu_device_resume(struct drm_device *dev, bool fbcon) flush_delayed_work(&adev->delayed_init_work); if (fbcon) -#ifdef HAVE_DRM_DEVICE_FB_HELPER +#ifdef AMDKCL_DRM_FBDEV_GENERIC drm_fb_helper_set_suspend_unlocked(adev_to_drm(adev)->fb_helper, false); #else amdgpu_fbdev_set_suspend(adev, 0); @@ -5508,7 +5514,7 @@ int amdgpu_do_asic_reset(struct list_head *device_list_handle, if (r) goto out; -#ifdef HAVE_DRM_DEVICE_FB_HELPER +#ifdef AMDKCL_DRM_FBDEV_GENERIC drm_fb_helper_set_suspend_unlocked(adev_to_drm(tmp_adev)->fb_helper, false); #else amdgpu_fbdev_set_suspend(tmp_adev, 0); @@ -5800,7 +5806,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, */ amdgpu_unregister_gpu_instance(tmp_adev); -#ifdef HAVE_DRM_DEVICE_FB_HELPER +#ifdef AMDKCL_DRM_FBDEV_GENERIC drm_fb_helper_set_suspend_unlocked(adev_to_drm(tmp_adev)->fb_helper, true); #else amdgpu_fbdev_set_suspend(tmp_adev, 1); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index afa793b8681f7..a7e60d2e575a3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1952,6 +1952,7 @@ bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc, stime, etime, mode); } +#ifdef AMDKCL_DRM_FBDEV_GENERIC static bool amdgpu_display_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj) { @@ -1966,6 +1967,7 @@ amdgpu_display_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj) return true; } +#endif int amdgpu_display_suspend_helper(struct amdgpu_device *adev) { @@ -2015,6 +2017,16 @@ int amdgpu_display_suspend_helper(struct amdgpu_device *adev) continue; robj = gem_to_amdgpu_bo(drm_gem_fb_get_obj(fb, 0)); +#ifndef AMDKCL_DRM_FBDEV_GENERIC + /* don't unpin kernel fb objects */ + if (!amdgpu_fbdev_robj_is_fb(adev, robj)) { + r = amdgpu_bo_reserve(robj, true); + if (r == 0) { + amdgpu_bo_unpin(robj); + amdgpu_bo_unreserve(robj); + } + } +#else if (!amdgpu_display_robj_is_fb(adev, robj)) { r = amdgpu_bo_reserve(robj, true); if (r == 0) { @@ -2022,6 +2034,7 @@ int amdgpu_display_suspend_helper(struct amdgpu_device *adev) amdgpu_bo_unreserve(robj); } } +#endif } return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c index 6f1dd87d31ee9..60bf213b8c85d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c @@ -24,7 +24,7 @@ * David Airlie */ -#ifndef HAVE_DRM_DEVICE_FB_HELPER +#ifndef AMDKCL_DRM_FBDEV_GENERIC #include #include diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index 7f3f5f31c8672..fae8bd35d6229 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -1047,6 +1047,7 @@ int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, return r; } +#ifdef AMDKCL_DRM_FBDEV_GENERIC static int amdgpu_gem_align_pitch(struct amdgpu_device *adev, int width, int cpp, @@ -1072,6 +1073,7 @@ static int amdgpu_gem_align_pitch(struct amdgpu_device *adev, aligned &= ~pitch_mask; return aligned * cpp; } +#endif int amdgpu_mode_dumb_create(struct drm_file *file_priv, struct drm_device *dev, @@ -1095,8 +1097,13 @@ int amdgpu_mode_dumb_create(struct drm_file *file_priv, if (adev->mman.buffer_funcs_enabled) flags |= AMDGPU_GEM_CREATE_VRAM_CLEARED; +#ifdef AMDKCL_DRM_FBDEV_GENERIC args->pitch = amdgpu_gem_align_pitch(adev, args->width, DIV_ROUND_UP(args->bpp, 8), 0); +#else + args->pitch = amdgpu_align_pitch(adev, args->width, + DIV_ROUND_UP(args->bpp, 8), 0); +#endif args->size = (u64)args->pitch * args->height; args->size = ALIGN(args->size, PAGE_SIZE); domain = amdgpu_bo_get_preferred_domain(adev, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index b0f3350c3e0a0..4ed812bf32cd5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -232,7 +232,7 @@ struct amdgpu_i2c_chan { }; -#ifndef HAVE_DRM_DEVICE_FB_HELPER +#ifndef AMDKCL_DRM_FBDEV_GENERIC struct amdgpu_fbdev; #endif @@ -315,7 +315,7 @@ struct amdgpu_framebuffer { uint64_t address; }; -#ifndef HAVE_DRM_DEVICE_FB_HELPER +#ifndef AMDKCL_DRM_FBDEV_GENERIC struct amdgpu_fbdev { struct drm_fb_helper helper; struct amdgpu_framebuffer rfb; @@ -346,7 +346,7 @@ struct amdgpu_mode_info { /* hardcoded DFP edid from BIOS */ const struct drm_edid *bios_hardcoded_edid; -#ifndef HAVE_DRM_DEVICE_FB_HELPER +#ifndef AMDKCL_DRM_FBDEV_GENERIC /* pointer to fbdev info structure */ struct amdgpu_fbdev *rfbdev; #endif @@ -721,7 +721,7 @@ bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc, int *hpos, ktime_t *stime, ktime_t *etime, const struct drm_display_mode *mode); -#ifndef HAVE_DRM_DEVICE_FB_HELPER +#ifndef AMDKCL_DRM_FBDEV_GENERIC /* fbdev layer */ int amdgpu_fbdev_init(struct amdgpu_device *adev); void amdgpu_fbdev_fini(struct amdgpu_device *adev); diff --git a/include/kcl/backport/kcl_drm_fb.h b/include/kcl/backport/kcl_drm_fb.h index fd7f828ca96fd..2d165e481704b 100644 --- a/include/kcl/backport/kcl_drm_fb.h +++ b/include/kcl/backport/kcl_drm_fb.h @@ -42,4 +42,10 @@ void _kcl_drm_helper_mode_fill_fb_struct(struct drm_device *dev, #define drm_helper_mode_fill_fb_struct _kcl_drm_helper_mode_fill_fb_struct #endif +#if defined(HAVE_DRM_FBDEV_GENERIC_SETUP) && \ + defined(HAVE_DRM_DEVICE_FB_HELPER) && \ + DRM_VERSION_CODE >= DRM_VERSION(5, 13, 0) +#define AMDKCL_DRM_FBDEV_GENERIC +#endif + #endif From dbbd4ae0fff75003924d03c808fbaa99e391741a Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 15 Nov 2021 14:52:04 +0800 Subject: [PATCH 0552/1868] drm/amdkfd: replace kgd_dev with amdgpu_device Modified definitions: - amdgpu_amdkfd_copy_mem_to_mem - amdgpu_amdkfd_send_close_event_drain_irq - amdgpu_amdkfd_gfx_off_ctrl - amdgpu_amdkfd_gpuvm_get_sg_table - amdgpu_amdkfd_gpuvm_export_ipc_obj - amdgpu_amdkfd_debug_mem_fence - amdgpu_amdkfd_rlc_spm_cntl - amdgpu_amdkfd_rlc_spm_acquire - amdgpu_amdkfd_rlc_spm_release - amdgpu_amdkfd_rlc_spm_set_rdptr - kgd_aldebaran_enable_debug_trap - kgd_aldebaran_disable_debug_trap - kgd_aldebaran_set_wave_launch_trap_override - kgd_aldebaran_set_wave_launch_mode - kgd_aldebaran_set_precise_mem_ops - kgd_gfx_v10_enable_debug_trap - kgd_gfx_v10_disable_debug_trap - kgd_gfx_v10_set_wave_launch_trap_override - kgd_gfx_v10_set_wave_launch_mode - kgd_gfx_v10_set_address_watch - kgd_gfx_v10_clear_address_watch - kgd_gfx_v10_set_precise_mem_ops - kgd_gfx_v10_get_iq_wait_times - kgd_gfx_v10_build_grace_period_packet_info - kgd_gfx_v9_enable_debug_trap - kgd_gfx_v9_disable_debug_trap - kgd_gfx_v9_set_wave_launch_trap_override - kgd_gfx_v9_set_wave_launch_mode - kgd_gfx_v9_set_address_watch - kgd_gfx_v9_clear_address_watch - kgd_gfx_v9_set_precise_mem_ops - kgd_gfx_v9_get_iq_wait_times - kgd_gfx_v9_build_grace_period_packet_info Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 15 +++++----- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 9 ++---- .../drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c | 12 +++----- drivers/gpu/drm/amd/amdkfd/kfd_ipc.c | 6 ++-- drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_spm.c | 28 +++++++++---------- drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 2 +- 8 files changed, 34 insertions(+), 42 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index e6efb76f19046..ff8e5974b82e7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -361,7 +361,7 @@ int amdgpu_amdkfd_gpuvm_pin_bo(struct amdgpu_bo *bo, u32 domain); */ void amdgpu_amdkfd_gpuvm_unpin_bo(struct amdgpu_bo *bo); -int amdgpu_amdkfd_gpuvm_get_sg_table(struct kgd_dev *kgd, +int amdgpu_amdkfd_gpuvm_get_sg_table(struct amdgpu_device *adev, struct amdgpu_bo *bo, uint32_t flags, uint64_t offset, uint64_t size, struct device *dma_dev, enum dma_data_direction dir, @@ -370,7 +370,7 @@ void amdgpu_amdkfd_gpuvm_put_sg_table(struct amdgpu_bo *bo, struct device *dma_dev, enum dma_data_direction dir, struct sg_table *sg); -int amdgpu_amdkfd_gpuvm_import_dmabuf(struct kgd_dev *kgd, +int amdgpu_amdkfd_gpuvm_import_dmabuf(struct amdgpu_device *adev, struct dma_buf *dmabuf, struct kfd_ipc_obj *ipc_obj, uint64_t va, void *drm_priv, @@ -382,7 +382,7 @@ int amdgpu_amdkfd_gpuvm_import_dmabuf_fd(struct amdgpu_device *adev, int fd, uint64_t *mmap_offset); int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_mem *mem, struct dma_buf **dmabuf); -int amdgpu_amdkfd_gpuvm_export_ipc_obj(struct kgd_dev *kgd, void *vm, +int amdgpu_amdkfd_gpuvm_export_ipc_obj(struct amdgpu_device *adev, void *vm, struct kgd_mem *mem, struct kfd_ipc_obj **ipc_obj, uint32_t flags); @@ -446,12 +446,11 @@ void amdgpu_amdkfd_release_notify(struct amdgpu_bo *bo) } #endif -void amdgpu_amdkfd_rlc_spm_cntl(struct kgd_dev *kgd, bool cntl); -int amdgpu_amdkfd_rlc_spm(struct kgd_dev *kgd, void *args); -int amdgpu_amdkfd_rlc_spm_acquire(struct kgd_dev *kgd, +void amdgpu_amdkfd_rlc_spm_cntl(struct amdgpu_device *adev, bool cntl); +int amdgpu_amdkfd_rlc_spm_acquire(struct amdgpu_device *adev, struct amdgpu_vm *vm, u64 gpu_addr, u32 size); -void amdgpu_amdkfd_rlc_spm_release(struct kgd_dev *kgd, struct amdgpu_vm *vm); -void amdgpu_amdkfd_rlc_spm_set_rdptr(struct kgd_dev *kgd, u32 rptr); +void amdgpu_amdkfd_rlc_spm_release(struct amdgpu_device *adev, struct amdgpu_vm *vm); +void amdgpu_amdkfd_rlc_spm_set_rdptr(struct amdgpu_device *adev, u32 rptr); void amdgpu_amdkfd_rlc_spm_interrupt(struct amdgpu_device *adev); #if IS_ENABLED(CONFIG_HSA_AMD_SVM) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index cd9d969378081..1b2505fbe6442 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -2557,13 +2557,12 @@ static int get_sg_table_of_mmio_or_doorbel_bo(struct amdgpu_bo *bo, return 0; } -int amdgpu_amdkfd_gpuvm_get_sg_table(struct kgd_dev *kgd, +int amdgpu_amdkfd_gpuvm_get_sg_table(struct amdgpu_device *adev, struct amdgpu_bo *bo, uint32_t flags, uint64_t offset, uint64_t size, struct device *dma_dev, enum dma_data_direction dir, struct sg_table **ret_sg) { - struct amdgpu_device *adev = get_amdgpu_device(kgd); struct sg_table *sg = NULL; struct scatterlist *s; struct page **pages; @@ -2807,19 +2806,17 @@ int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_mem *mem, return ret; } -int amdgpu_amdkfd_gpuvm_export_ipc_obj(struct kgd_dev *kgd, void *vm, +int amdgpu_amdkfd_gpuvm_export_ipc_obj(struct amdgpu_device *adev, void *vm, struct kgd_mem *mem, struct kfd_ipc_obj **ipc_obj, uint32_t flags) { - struct amdgpu_device *adev = NULL; struct dma_buf *dmabuf; int r = 0; - if (!kgd || !vm || !mem) + if (!adev || !vm || !mem) return -EINVAL; - adev = get_amdgpu_device(kgd); mutex_lock(&mem->lock); if (mem->ipc_obj) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c index eeaca9d1e02b9..1dd189536c764 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c @@ -25,9 +25,8 @@ #include #include "amdgpu_ids.h" -void amdgpu_amdkfd_rlc_spm_cntl(struct kgd_dev *kgd, bool cntl) +void amdgpu_amdkfd_rlc_spm_cntl(struct amdgpu_device *adev, bool cntl) { - struct amdgpu_device *adev = (struct amdgpu_device *)kgd; struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; spin_lock(&adev->gfx.kiq.ring_lock); @@ -40,9 +39,8 @@ void amdgpu_amdkfd_rlc_spm_cntl(struct kgd_dev *kgd, bool cntl) spin_unlock(&adev->gfx.kiq.ring_lock); } -void amdgpu_amdkfd_rlc_spm_set_rdptr(struct kgd_dev *kgd, u32 rptr) +void amdgpu_amdkfd_rlc_spm_set_rdptr(struct amdgpu_device *adev, u32 rptr) { - struct amdgpu_device *adev = (struct amdgpu_device *)kgd; struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; spin_lock(&adev->gfx.kiq.ring_lock); @@ -52,9 +50,8 @@ void amdgpu_amdkfd_rlc_spm_set_rdptr(struct kgd_dev *kgd, u32 rptr) spin_unlock(&adev->gfx.kiq.ring_lock); } -int amdgpu_amdkfd_rlc_spm_acquire(struct kgd_dev *kgd, struct amdgpu_vm *vm, u64 gpu_addr, u32 size) +int amdgpu_amdkfd_rlc_spm_acquire(struct amdgpu_device *adev, struct amdgpu_vm *vm, u64 gpu_addr, u32 size) { - struct amdgpu_device *adev = (struct amdgpu_device *)kgd; struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; int r; @@ -77,9 +74,8 @@ int amdgpu_amdkfd_rlc_spm_acquire(struct kgd_dev *kgd, struct amdgpu_vm *vm, u64 return r; } -void amdgpu_amdkfd_rlc_spm_release(struct kgd_dev *kgd, struct amdgpu_vm *vm) +void amdgpu_amdkfd_rlc_spm_release(struct amdgpu_device *adev, struct amdgpu_vm *vm) { - struct amdgpu_device *adev = (struct amdgpu_device *)kgd; struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; /* stop spm stream and interrupt */ diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c index b5d89265d3c2d..b7208b22ad883 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c @@ -136,7 +136,7 @@ static int kfd_import_dmabuf_create_kfd_bo(struct kfd_dev *dev, goto err_unlock; } - r = amdgpu_amdkfd_gpuvm_import_dmabuf(dev->kgd, dmabuf, ipc_obj, + r = amdgpu_amdkfd_gpuvm_import_dmabuf(dev->adev, dmabuf, ipc_obj, va_addr, pdd->drm_priv, (struct kgd_mem **)&mem, &size, mmap_offset); @@ -157,7 +157,7 @@ static int kfd_import_dmabuf_create_kfd_bo(struct kfd_dev *dev, return 0; err_free: - amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->kgd, (struct kgd_mem *)mem, NULL); + amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->adev, (struct kgd_mem *)mem, pdd->drm_priv, NULL); err_unlock: mutex_unlock(&p->mutex); return r; @@ -252,7 +252,7 @@ int kfd_ipc_export_as_handle(struct kfd_dev *dev, struct kfd_process *p, } mem = (struct kgd_mem *)kfd_bo->mem; - r = amdgpu_amdkfd_gpuvm_export_ipc_obj(dev->kgd, pdd->drm_priv, mem, + r = amdgpu_amdkfd_gpuvm_export_ipc_obj(dev->adev, pdd->drm_priv, mem, &ipc_obj, flags); if (r) return r; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c b/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c index f8c89ba5ff86b..09cf783e460d3 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c @@ -320,7 +320,7 @@ static int amd_dma_map(struct sg_table *sg_head, void *client_context, /* Build sg_table for buffer being exported, including DMA mapping */ ret = amdgpu_amdkfd_gpuvm_get_sg_table( - mem_context->dev->kgd, mem_context->bo, mem_context->flags, + mem_context->dev->adev, mem_context->bo, mem_context->flags, mem_context->offset, mem_context->size, dma_device, DMA_BIDIRECTIONAL, &sg_table_tmp); if (ret) { diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 0ee35921f7a8a..2df5bfdbd0cc1 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -986,7 +986,7 @@ static void kfd_process_device_free_bos(struct kfd_process_device *pdd) if (!peer_pdd->drm_priv) continue; amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu( - peer_pdd->dev->kgd, buf_obj->mem, peer_pdd->drm_priv); + peer_pdd->dev->adev, buf_obj->mem, peer_pdd->drm_priv); } run_rdma_free_callback(buf_obj); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c index ceabdb3680a64..b1fc5ace4015d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c @@ -147,7 +147,7 @@ static int kfd_spm_read_ring_buffer(struct kfd_process_device *pdd) } exit: - amdgpu_amdkfd_rlc_spm_set_rdptr(pdd->dev->kgd, spm->ring_rptr); + amdgpu_amdkfd_rlc_spm_set_rdptr(pdd->dev->adev, spm->ring_rptr); return ret; } @@ -176,7 +176,7 @@ void kfd_spm_init_process_device(struct kfd_process_device *pdd) pdd->spm_cntr = NULL; } -static int kfd_acquire_spm(struct kfd_process_device *pdd, struct kgd_dev *kgd) +static int kfd_acquire_spm(struct kfd_process_device *pdd, struct amdgpu_device *adev) { int ret = 0; @@ -200,7 +200,7 @@ static int kfd_acquire_spm(struct kfd_process_device *pdd, struct kgd_dev *kgd) pdd->spm_cntr->ring_mask = pdd->spm_cntr->ring_size - 1; pdd->spm_cntr->has_user_buf = false; - ret = amdgpu_amdkfd_alloc_gtt_mem(kgd, + ret = amdgpu_amdkfd_alloc_gtt_mem(adev, pdd->spm_cntr->ring_size, &pdd->spm_cntr->spm_obj, &pdd->spm_cntr->gpu_addr, (void *)&pdd->spm_cntr->cpu_addr, false, false); @@ -208,7 +208,7 @@ static int kfd_acquire_spm(struct kfd_process_device *pdd, struct kgd_dev *kgd) if (ret) goto alloc_gtt_mem_failure; - ret = amdgpu_amdkfd_rlc_spm_acquire(kgd, pdd->drm_priv, + ret = amdgpu_amdkfd_rlc_spm_acquire(adev, pdd->drm_priv, pdd->spm_cntr->gpu_addr, pdd->spm_cntr->ring_size); /* @@ -230,7 +230,7 @@ static int kfd_acquire_spm(struct kfd_process_device *pdd, struct kgd_dev *kgd) goto out; acquire_spm_failure: - amdgpu_amdkfd_free_gtt_mem(kgd, pdd->spm_cntr->spm_obj); + amdgpu_amdkfd_free_gtt_mem(adev, pdd->spm_cntr->spm_obj); alloc_gtt_mem_failure: mutex_lock(&pdd->spm_mutex); @@ -242,7 +242,7 @@ static int kfd_acquire_spm(struct kfd_process_device *pdd, struct kgd_dev *kgd) return ret; } -static int kfd_release_spm(struct kfd_process_device *pdd, struct kgd_dev *kgd) +static int kfd_release_spm(struct kfd_process_device *pdd, struct amdgpu_device *adev) { unsigned long flags; @@ -259,8 +259,8 @@ static int kfd_release_spm(struct kfd_process_device *pdd, struct kgd_dev *kgd) flush_work(&pdd->spm_work); wake_up_all(&pdd->spm_cntr->spm_buf_wq); - amdgpu_amdkfd_rlc_spm_release(kgd, pdd->drm_priv); - amdgpu_amdkfd_free_gtt_mem(kgd, pdd->spm_cntr->spm_obj); + amdgpu_amdkfd_rlc_spm_release(adev, pdd->drm_priv); + amdgpu_amdkfd_free_gtt_mem(adev, pdd->spm_cntr->spm_obj); spin_lock_irqsave(&pdd->spm_irq_lock, flags); kfree(pdd->spm_cntr); @@ -330,7 +330,7 @@ static int spm_wait_for_fill_awake(struct kfd_spm_cntr *spm, return ret; } -static int kfd_set_dest_buffer(struct kfd_process_device *pdd, struct kgd_dev *kgd, void *data) +static int kfd_set_dest_buffer(struct kfd_process_device *pdd, struct amdgpu_device *adev, void *data) { struct kfd_ioctl_spm_args *user_spm_data; struct kfd_spm_cntr *spm; @@ -378,7 +378,7 @@ static int kfd_set_dest_buffer(struct kfd_process_device *pdd, struct kgd_dev *k /* Start SPM */ if (spm->is_spm_started == false) { - amdgpu_amdkfd_rlc_spm_cntl(kgd, 1); + amdgpu_amdkfd_rlc_spm_cntl(adev, 1); spin_lock_irqsave(&pdd->spm_irq_lock, flags); spm->is_spm_started = true; spin_unlock_irqrestore(&pdd->spm_irq_lock, flags); @@ -389,7 +389,7 @@ static int kfd_set_dest_buffer(struct kfd_process_device *pdd, struct kgd_dev *k schedule_work(&pdd->spm_work); } } else { - amdgpu_amdkfd_rlc_spm_cntl(kgd, 0); + amdgpu_amdkfd_rlc_spm_cntl(adev, 0); spin_lock_irqsave(&pdd->spm_irq_lock, flags); spm->is_spm_started = false; spin_unlock_irqrestore(&pdd->spm_irq_lock, flags); @@ -419,13 +419,13 @@ int kfd_rlc_spm(struct kfd_process *p, void *data) switch (args->op) { case KFD_IOCTL_SPM_OP_ACQUIRE: dev->spm_pasid = p->pasid; - return kfd_acquire_spm(pdd, dev->kgd); + return kfd_acquire_spm(pdd, dev->adev); case KFD_IOCTL_SPM_OP_RELEASE: - return kfd_release_spm(pdd, dev->kgd); + return kfd_release_spm(pdd, dev->adev); case KFD_IOCTL_SPM_OP_SET_DEST_BUF: - return kfd_set_dest_buffer(pdd, dev->kgd, data); + return kfd_set_dest_buffer(pdd, dev->adev, data); default: return -EINVAL; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index 420ec88344ffa..44776bd74c97f 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -332,7 +332,7 @@ static ssize_t mem_show(struct kobject *kobj, struct attribute *attr, if (mem->gpu) { if (kfd_devcgroup_check_permission(mem->gpu)) return -EPERM; - used_mem = amdgpu_amdkfd_get_vram_usage(mem->gpu->kgd); + used_mem = amdgpu_amdkfd_get_vram_usage(mem->gpu->adev); return sysfs_show_64bit_val(buffer, offs, used_mem); } /* TODO: Report APU/CPU-allocated memory; For now return 0 */ From ab356f451aa3bf181adf4a0512db9d4fc8148219 Mon Sep 17 00:00:00 2001 From: Hawking Zhang Date: Thu, 25 Nov 2021 22:25:12 +0800 Subject: [PATCH 0553/1868] drm/amdgpu: correct RLC_SPM_INT_CNTL register address should count on gc base address Signed-off-by: Hawking Zhang Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 661df6aceccff..e96beb4358783 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -7142,10 +7142,10 @@ static int gfx_v9_0_spm_set_interrupt_state(struct amdgpu_device *adev, { switch (state) { case AMDGPU_IRQ_STATE_DISABLE: - WREG32(mmRLC_SPM_INT_CNTL, 0); + WREG32_SOC15(GC, 0, mmRLC_SPM_INT_CNTL, 0); break; case AMDGPU_IRQ_STATE_ENABLE: - WREG32(mmRLC_SPM_INT_CNTL, 1); + WREG32_SOC15(GC, 0, mmRLC_SPM_INT_CNTL, 1); break; default: break; From f9a2dc58ba979a81b9b7eb55f3742896ad299625 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Wed, 17 Nov 2021 19:44:55 -0500 Subject: [PATCH 0554/1868] drm/amdkfd: Fix amdgpu_read_lock lockdep errors The amdgpu_read_lock must be taken inside the p->mutex to avoid circular lock dependencies between these two locks. Move locking from IPC and dmabuf import ioctls into kfd_import_dmabuf_create_kfd_bo to satisfy this constraint. Signed-off-by: Felix Kuehling Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdkfd/kfd_ipc.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c index b7208b22ad883..c1f5f7dc6c5d7 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c @@ -129,11 +129,14 @@ static int kfd_import_dmabuf_create_kfd_bo(struct kfd_dev *dev, return -EINVAL; mutex_lock(&p->mutex); + r = amdgpu_read_lock(dev->ddev, true); + if (r) + goto err_unlock; pdd = kfd_bind_process_to_device(dev, p); if (IS_ERR(pdd)) { r = PTR_ERR(pdd); - goto err_unlock; + goto err_read_unlock; } r = amdgpu_amdkfd_gpuvm_import_dmabuf(dev->adev, dmabuf, ipc_obj, @@ -141,7 +144,7 @@ static int kfd_import_dmabuf_create_kfd_bo(struct kfd_dev *dev, (struct kgd_mem **)&mem, &size, mmap_offset); if (r) - goto err_unlock; + goto err_read_unlock; idr_handle = kfd_process_device_create_obj_handle(pdd, mem, va_addr, size, 0, 0); @@ -150,6 +153,7 @@ static int kfd_import_dmabuf_create_kfd_bo(struct kfd_dev *dev, goto err_free; } + amdgpu_read_unlock(dev->ddev); mutex_unlock(&p->mutex); *handle = MAKE_HANDLE(gpu_id, idr_handle); @@ -158,6 +162,8 @@ static int kfd_import_dmabuf_create_kfd_bo(struct kfd_dev *dev, err_free: amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->adev, (struct kgd_mem *)mem, pdd->drm_priv, NULL); +err_read_unlock: + amdgpu_read_unlock(dev->ddev); err_unlock: mutex_unlock(&p->mutex); return r; From d2e8d42ee2091984c5c42bda7fcb37fbd6efce3f Mon Sep 17 00:00:00 2001 From: Emily Deng Date: Tue, 30 Nov 2021 11:58:39 +0800 Subject: [PATCH 0555/1868] amd/amdgpu: Fix build issue on arm platform On arm platform, couldn't support float build. And for container it doesn't need dcn. So directly remove dcn parts. Signed-off-by: Emily Deng Reviewed-by: Flora Cui Change-Id: Ic01a003271a9481c4e04fb1eb15fbc1162d6ccc6 --- drivers/gpu/drm/amd/dkms/Makefile | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index b9f423b84ddaf..340258b04f0aa 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -149,7 +149,9 @@ export CONFIG_DRM_AMDGPU_CIK=y export CONFIG_DRM_AMDGPU_SI=y export CONFIG_DRM_AMDGPU_USERPTR=y export CONFIG_DRM_AMD_DC=y +ifndef CONFIG_ARM64 export CONFIG_DRM_AMD_DC_DCN1_0=y +endif subdir-ccflags-y += -DCONFIG_HSA_AMD subdir-ccflags-y += -DCONFIG_DRM_TTM_DMA_PAGE_POOL @@ -157,7 +159,9 @@ subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_CIK subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_SI subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_USERPTR subdir-ccflags-y += -DCONFIG_DRM_AMD_DC +ifndef CONFIG_ARM64 subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN1_0 +endif ifeq ($(call _is_kcl_macro_defined,HAVE_AMDKCL_HMM_MIRROR_ENABLED),y) ifdef CONFIG_DEVICE_PRIVATE @@ -173,11 +177,13 @@ subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_HDCP # older versions of GCC hanging during building/installing. Check # if the compiler is using core2 optimizations and only build DCN2/3 # if core2 isn't in the compiler flags +ifndef CONFIG_ARM64 ifeq ($(filter %core2, $(KBUILD_CFLAGS)),) export CONFIG_DRM_AMD_DC_DCN2_x=y export CONFIG_DRM_AMD_DC_DCN3_x=y subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN2_x subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN3_x endif +endif obj-m += scheduler/ amd/amdgpu/ ttm/ amd/amdkcl/ From 95b22b4d16c0878692f76d3ad847fadc37346c5f Mon Sep 17 00:00:00 2001 From: Jiange Zhao Date: Thu, 29 Jul 2021 13:36:19 +0800 Subject: [PATCH 0556/1868] amd/amdkcl - Make dkms package compile and run on arm64 4.19 kernel Resolve the compile error about access ok Signed-off-by: Jiange Zhao Signed-off-by: Emily Deng Reviewed-by: Flora Cui Change-Id: I703025483dd8e5fb30f5004162c3de19fe04b12c --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 12 ++++++------ drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c | 2 +- include/kcl/backport/kcl_uaccess_backport.h | 10 +++++----- 3 files changed, 12 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 1e4a9083a72fb..eebc124f11390 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -205,7 +205,7 @@ static int set_queue_properties_from_user(struct queue_properties *q_properties, } if ((args->ring_base_address) && - (!access_ok((const void __user *) args->ring_base_address, + (!kcl_access_ok((const void __user *) args->ring_base_address, sizeof(uint64_t)))) { pr_err("Can't access ring base address\n"); return -EFAULT; @@ -216,27 +216,27 @@ static int set_queue_properties_from_user(struct queue_properties *q_properties, return -EINVAL; } - if (!access_ok((const void __user *) args->read_pointer_address, + if (!kcl_access_ok((const void __user *) args->read_pointer_address, sizeof(uint32_t))) { pr_err("Can't access read pointer\n"); return -EFAULT; } - if (!access_ok((const void __user *) args->write_pointer_address, + if (!kcl_access_ok((const void __user *) args->write_pointer_address, sizeof(uint32_t))) { pr_err("Can't access write pointer\n"); return -EFAULT; } if (args->eop_buffer_address && - !access_ok((const void __user *) args->eop_buffer_address, + !kcl_access_ok((const void __user *) args->eop_buffer_address, sizeof(uint32_t))) { pr_debug("Can't access eop buffer"); return -EFAULT; } if (args->ctx_save_restore_address && - !access_ok((const void __user *) args->ctx_save_restore_address, + !kcl_access_ok((const void __user *) args->ctx_save_restore_address, sizeof(uint32_t))) { pr_debug("Can't access ctx save restore buffer"); return -EFAULT; @@ -454,7 +454,7 @@ static int kfd_ioctl_update_queue(struct file *filp, struct kfd_process *p, } if ((args->ring_base_address) && - (!access_ok((const void __user *) args->ring_base_address, + (!kcl_access_ok((const void __user *) args->ring_base_address, sizeof(uint64_t)))) { pr_err("Can't access ring base address\n"); return -EFAULT; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c b/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c index ea6a8e43bd5b2..2976a6c873dd2 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c @@ -129,7 +129,7 @@ static ssize_t kfd_smi_ev_write(struct file *filep, const char __user *user, struct kfd_smi_client *client = filep->private_data; uint64_t events; - if (!access_ok(user, size) || size < sizeof(events)) + if (!kcl_access_ok(user, size) || size < sizeof(events)) return -EFAULT; if (copy_from_user(&events, user, sizeof(events))) return -EFAULT; diff --git a/include/kcl/backport/kcl_uaccess_backport.h b/include/kcl/backport/kcl_uaccess_backport.h index c7466949cad39..5e358c64a8fce 100644 --- a/include/kcl/backport/kcl_uaccess_backport.h +++ b/include/kcl/backport/kcl_uaccess_backport.h @@ -3,12 +3,12 @@ #define AMDKCL_UACCESS_BACKPORT_H #include -#if !defined(HAVE_ACCESS_OK_WITH_TWO_ARGUMENTS) -static inline int _kcl_access_ok(unsigned long addr, unsigned long size) +static inline int kcl_access_ok(unsigned long addr, unsigned long size) { +#if !defined(HAVE_ACCESS_OK_WITH_TWO_ARGUMENTS) return access_ok(VERIFY_WRITE, (addr), (size)); -} -#undef access_ok -#define access_ok _kcl_access_ok +#else + return access_ok((addr), (size)); #endif +} #endif From 5e1acd8c5d4093c2854ddb644b0cf3b494adc85e Mon Sep 17 00:00:00 2001 From: Ramesh Errabolu Date: Fri, 12 Nov 2021 15:39:32 -0600 Subject: [PATCH 0557/1868] drm/amdgpu: Fix config macro HAVE_STRUCT_DMA_BUF_OPS_ALLOW_PEER2PEER Logic determining status of HAVE_STRUCT_DMA_BUF_OPS_ALLOW_PEER2PEER is incorrect. Code body should reference struct dma_buf_attach_ops. Rename macro as HAVE_STRUCT_DMA_BUF_ATTACH_OPS_ALLOW_PEER2PEER Signed-off-by: Ramesh Errabolu Acked-by: Felix Kuehling Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 6 +++--- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 | 2 +- 3 files changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index 7f672ab0ca9ee..14607811ff913 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -246,7 +246,7 @@ static int amdgpu_dma_buf_attach(struct dma_buf *dmabuf, struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj); struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); -#ifdef HAVE_STRUCT_DMA_BUF_OPS_ALLOW_PEER2PEER +#ifdef HAVE_STRUCT_DMA_BUF_ATTACH_OPS_ALLOW_PEER2PEER if (pci_p2pdma_distance(adev->pdev, attach->dev, false) < 0) attach->peer2peer = false; #endif @@ -334,7 +334,7 @@ static struct sg_table *amdgpu_dma_buf_map(struct dma_buf_attachment *attach, struct ttm_operation_ctx ctx = { false, false }; unsigned int domains = AMDGPU_GEM_DOMAIN_GTT; -#ifdef HAVE_STRUCT_DMA_BUF_OPS_ALLOW_PEER2PEER +#ifdef HAVE_STRUCT_DMA_BUF_ATTACH_OPS_ALLOW_PEER2PEER if (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM && attach->peer2peer) { bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; @@ -775,7 +775,7 @@ amdgpu_dma_buf_move_notify(struct dma_buf_attachment *attach) } static const struct dma_buf_attach_ops amdgpu_dma_buf_attach_ops = { -#ifdef HAVE_STRUCT_DMA_BUF_OPS_ALLOW_PEER2PEER +#ifdef HAVE_STRUCT_DMA_BUF_ATTACH_OPS_ALLOW_PEER2PEER .allow_peer2peer = true, #endif .move_notify = amdgpu_dma_buf_move_notify diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index a7cc3bf23c054..a7bca453c6b00 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -960,6 +960,9 @@ /* struct dma_buf_ops->allow_peer2peer is available */ #define HAVE_STRUCT_DMA_BUF_OPS_ALLOW_PEER2PEER 1 +/* struct dma_buf_attach_ops->allow_peer2peer is available */ +#define HAVE_STRUCT_DMA_BUF_ATTACH_OPS_ALLOW_PEER2PEER 1 + /* struct dma_buf_ops->pin() is available */ #define HAVE_STRUCT_DMA_BUF_OPS_PIN 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 index e402bf57f2ec6..5f773c28a1b9e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 @@ -10,7 +10,7 @@ AC_DEFUN([AC_AMDGPU_DMA_BUF], [ struct dma_buf_attach_ops *ptr = NULL; ptr->allow_peer2peer = false; ],[ - AC_DEFINE(HAVE_STRUCT_DMA_BUF_OPS_ALLOW_PEER2PEER, + AC_DEFINE(HAVE_STRUCT_DMA_BUF_ATTACH_OPS_ALLOW_PEER2PEER, 1, [struct dma_buf_attach_ops->allow_peer2peer is available]) ],[ From b9300776b08c63f98c154f8fd3eed2455faa6dc2 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 3 Dec 2021 11:11:58 +0800 Subject: [PATCH 0558/1868] drm/amdkcl: fix dma-buf related check Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 6 ++---- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 +-- drivers/gpu/drm/amd/dkms/config/config.h | 5 ++++- drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 | 9 ++++++++- 4 files changed, 15 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index 14607811ff913..2eae529e2a6c7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -133,8 +133,7 @@ __dma_resv_make_exclusive(struct dma_resv *obj) return -ENOMEM; } -#if !defined(HAVE_DMA_BUF_OPS_DYNAMIC_MAPPING) && \ - !defined(HAVE_STRUCT_DMA_BUF_OPS_PIN) +#if defined(HAVE_DMA_BUF_OPS_LEGACY) /** * amdgpu_dma_buf_map_attach - &dma_buf_ops.attach implementation * @dma_buf: Shared DMA buffer @@ -462,8 +461,7 @@ static int amdgpu_dma_buf_begin_cpu_access(struct dma_buf *dma_buf, } const struct dma_buf_ops amdgpu_dmabuf_ops = { -#if !defined(HAVE_DMA_BUF_OPS_DYNAMIC_MAPPING) && \ - !defined(HAVE_STRUCT_DMA_BUF_OPS_PIN) +#if defined(HAVE_DMA_BUF_OPS_LEGACY) .attach = amdgpu_dma_buf_map_attach, .detach = amdgpu_dma_buf_map_detach, .map_dma_buf = drm_gem_map_dma_buf, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 6a4fec849537e..a993b0486740b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3083,8 +3083,7 @@ static struct drm_driver amdgpu_kms_driver = { #ifdef HAVE_DRM_DRIVER_GEM_PRIME_RES_OBJ .gem_prime_res_obj = amdgpu_gem_prime_res_obj, #endif -#if !defined(HAVE_DMA_BUF_OPS_DYNAMIC_MAPPING) && \ - !defined(HAVE_STRUCT_DMA_BUF_OPS_PIN) +#if defined(HAVE_DMA_BUF_OPS_LEGACY) .gem_prime_get_sg_table = amdgpu_gem_prime_get_sg_table, .gem_prime_import_sg_table = amdgpu_gem_prime_import_sg_table, #endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index a7bca453c6b00..7c15f6c11260b 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -79,9 +79,12 @@ /* dev_pm_set_driver_flags() is available */ #define HAVE_DEV_PM_SET_DRIVER_FLAGS 1 -/* dma_buf dynamic_mapping is available */ +/* dma_buf->dynamic_mapping is available */ /* #undef HAVE_DMA_BUF_OPS_DYNAMIC_MAPPING */ +/* dma_buf->dynamic_mapping is not available */ +/* #undef HAVE_DMA_BUF_OPS_LEGACY */ + /* dma_buf_unpin() is available */ #define HAVE_DMA_BUF_UNPIN 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 index 5f773c28a1b9e..d4f139e428849 100644 --- a/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 @@ -13,6 +13,10 @@ AC_DEFUN([AC_AMDGPU_DMA_BUF], [ AC_DEFINE(HAVE_STRUCT_DMA_BUF_ATTACH_OPS_ALLOW_PEER2PEER, 1, [struct dma_buf_attach_ops->allow_peer2peer is available]) + + AC_DEFINE(HAVE_STRUCT_DMA_BUF_OPS_PIN, + 1, + [struct dma_buf_ops->pin() is available]) ],[ dnl # dnl # 4981cdb063e3 dma-buf: make move_notify mandatory if importer_ops are provided @@ -44,8 +48,11 @@ AC_DEFUN([AC_AMDGPU_DMA_BUF], [ dma_buf_ops->dynamic_mapping = true; ],[ AC_DEFINE(HAVE_DMA_BUF_OPS_DYNAMIC_MAPPING, 1, - [dma_buf dynamic_mapping is available]) + [dma_buf->dynamic_mapping is available]) ],[ + AC_DEFINE(HAVE_DMA_BUF_OPS_LEGACY, 1, + [dma_buf->dynamic_mapping is not available]) + AC_AMDGPU_DRM_GEM_MAP_ATTACH ]) ]) From dab90a115b5772a3b2bc187458558846546f2631 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 3 Dec 2021 11:23:06 +0800 Subject: [PATCH 0559/1868] drm/amdkcl: drop test for dma_buf_unpin It's the same with test for dma_buf_pin Signed-off-by: Flora Cui Reviewed-by: Yuan Perry --- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 2 +- drivers/gpu/drm/amd/dkms/config/config.h | 6 ---- drivers/gpu/drm/amd/dkms/m4/dma-buf-unpin.m4 | 34 -------------------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 -- 4 files changed, 1 insertion(+), 43 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/dma-buf-unpin.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index 6521d4c35c2d8..bc3127118da6d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -1061,7 +1061,7 @@ void amdgpu_bo_unpin(struct amdgpu_bo *bo) if (bo->tbo.pin_count) return; -#ifdef HAVE_DMA_BUF_UNPIN +#ifdef HAVE_STRUCT_DMA_BUF_OPS_PIN if (bo->tbo.base.import_attach) dma_buf_unpin(bo->tbo.base.import_attach); #endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 7c15f6c11260b..712202125631d 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -85,9 +85,6 @@ /* dma_buf->dynamic_mapping is not available */ /* #undef HAVE_DMA_BUF_OPS_LEGACY */ -/* dma_buf_unpin() is available */ -#define HAVE_DMA_BUF_UNPIN 1 - /* whether dma_fence_get_stub exits */ #define HAVE_DMA_FENCE_GET_STUB 1 @@ -969,9 +966,6 @@ /* struct dma_buf_ops->pin() is available */ #define HAVE_STRUCT_DMA_BUF_OPS_PIN 1 -/* struct dma_buf_ops->unpin() is available */ -#define HAVE_STRUCT_DMA_BUF_OPS_UNPIN 1 - /* struct drm_connector_state->duplicated is available */ #define HAVE_STRUCT_DRM_ATOMIC_STATE_DUPLICATED 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-buf-unpin.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-buf-unpin.m4 deleted file mode 100644 index 4c07a856211f9..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/dma-buf-unpin.m4 +++ /dev/null @@ -1,34 +0,0 @@ -dnl # -dnl # v5.6-rc2-335-gbb42df4662a4 -dnl # dma-buf: add dynamic DMA-buf handling v15 -dnl # -AC_DEFUN([AC_AMDGPU_DMA_BUF_UNPIN], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ],[ - dma_buf_unpin(NULL); - ],[ - AC_DEFINE(HAVE_DMA_BUF_UNPIN, 1, - [dma_buf_unpin() is available]) - ]) - ]) -]) - -AC_DEFUN([AC_AMDGPU_STRUCT_DMA_BUF_OPS_UNPIN], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ],[ - struct dma_buf_ops *ptr = NULL; - ptr->unpin(NULL); - ],[ - AC_DEFINE(HAVE_STRUCT_DMA_BUF_OPS_UNPIN, 1, - [struct dma_buf_ops->unpin() is available]) - ]) - ]) -]) - - - - diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 93f50740bbe2a..102146c662c22 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -164,8 +164,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_LINK_TRAIN_CHANNEL_EQ_DELAY AC_AMDGPU_DRM_CONNECTOR_ATOMIC_HDR_METADATA_EQUAL AC_AMDGPU_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY - AC_AMDGPU_DMA_BUF_UNPIN - AC_AMDGPU_STRUCT_DMA_BUF_OPS_UNPIN AC_AMDGPU_DRM_CONNECTOR_STATE_HDR_OUTPUT_METADATA AC_AMDGPU_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS AC_AMDGPU_DRM_DEV_ENTER From f0686e5774eb6243edeceb8e315a8dec6974eb91 Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Mon, 6 Dec 2021 04:02:25 -0500 Subject: [PATCH 0560/1868] drm/amdkfd: fix build error by replacing asic_name with asic type The patch will fix the build error which was caused by below commit: f31e07ea10f1 amdkfd: replace asic_family with asic_type v5.13-2961-gf31e07ea10f1 Signed-off-by: Perry Yuan Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkfd/kfd_device.c | 8 ++++---- drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index 1bec162a30845..a972110e37626 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -572,12 +572,12 @@ static int kfd_gws_init(struct kfd_node *node) ret = amdgpu_amdkfd_alloc_gws(node->adev, node->adev->gds.gws_size, &node->gws); - if ((kfd->device_info->asic_family == CHIP_VEGA10 + if ((kfd->adev->asic_type == CHIP_VEGA10 && kfd->mec2_fw_version < 0x81b6) - || (kfd->device_info->asic_family >= CHIP_VEGA12 - && kfd->device_info->asic_family <= CHIP_RAVEN + || (kfd->adev->asic_type >= CHIP_VEGA12 + && kfd->adev->asic_type <= CHIP_RAVEN && kfd->mec2_fw_version < 0x1b6) - || (kfd->device_info->asic_family == CHIP_ARCTURUS + || (kfd->adev->asic_type == CHIP_ARCTURUS && kfd->mec2_fw_version < 0x30)) kfd->gws_debug_workaround = true; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index 44776bd74c97f..50ede505c86dd 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -1292,7 +1292,7 @@ static void kfd_set_iolink_no_atomics(struct kfd_topology_device *dev, /* checkout source dev has atomics support on root. */ if (dev->gpu && (!dev->gpu->pci_atomic_requested || - dev->gpu->device_info->asic_family == + dev->gpu->adev->asic_type == CHIP_HAWAII)) { link->flags |= CRAT_IOLINK_FLAGS_NO_ATOMICS_32_BIT | CRAT_IOLINK_FLAGS_NO_ATOMICS_64_BIT; From af1ae1cc7609199201f7f547e6ddea9152a124e2 Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Tue, 7 Dec 2021 21:28:21 -0500 Subject: [PATCH 0561/1868] drm/amdkfd: fix coding style problem The patch fix the code format for the below patch. b751ff5666 drm/amdkfd: fix build error by replacing asic_name with asic type Signed-off-by: Perry Yuan Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index 50ede505c86dd..1c416a610b00c 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -1292,8 +1292,7 @@ static void kfd_set_iolink_no_atomics(struct kfd_topology_device *dev, /* checkout source dev has atomics support on root. */ if (dev->gpu && (!dev->gpu->pci_atomic_requested || - dev->gpu->adev->asic_type == - CHIP_HAWAII)) { + dev->gpu->adev->asic_type == CHIP_HAWAII)) { link->flags |= CRAT_IOLINK_FLAGS_NO_ATOMICS_32_BIT | CRAT_IOLINK_FLAGS_NO_ATOMICS_64_BIT; return; From c7e3784b22171109704c3858943e587ed783a3ee Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Wed, 8 Dec 2021 04:56:12 -0500 Subject: [PATCH 0562/1868] drm/amdkcl: fix build error by adding drm_display_info.is_hdmi check The build failure caused by below commit, the patch will check if the is_hdmi is available on the current kernel. dfbe9bf067 drm/amdgpu: replace drm_detect_hdmi_monitor() with drm_display_info.is_hdmi v5.13-3121-gdfbe9bf067a2 Signed-off-by: Perry Yuan Reviewed-by: Flora Cui --- .../gpu/drm/amd/amdgpu/amdgpu_connectors.c | 24 +++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 4 ++++ drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c | 8 +++++++ .../gpu/drm/amd/amdgpu/atombios_encoders.c | 12 ++++++++++ .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 5 ++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../m4/drm-connector-display-info-hdmi.m4 | 18 ++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 8 files changed, 75 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-connector-display-info-hdmi.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c index 4131569c8ee15..6be3a8ee4119c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c @@ -116,7 +116,11 @@ int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector) case DRM_MODE_CONNECTOR_DVII: case DRM_MODE_CONNECTOR_HDMIB: if (amdgpu_connector->use_digital) { +#if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) if (connector->display_info.is_hdmi) { +#else + if (drm_detect_hdmi_monitor(amdgpu_connector->edid)) { +#endif if (connector->display_info.bpc) bpc = connector->display_info.bpc; } @@ -124,7 +128,11 @@ int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector) break; case DRM_MODE_CONNECTOR_DVID: case DRM_MODE_CONNECTOR_HDMIA: +#if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) if (connector->display_info.is_hdmi) { +#else + if (drm_detect_hdmi_monitor(amdgpu_connector->edid)) { +#endif if (connector->display_info.bpc) bpc = connector->display_info.bpc; } @@ -133,7 +141,11 @@ int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector) dig_connector = amdgpu_connector->con_priv; if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) || +#if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) connector->display_info.is_hdmi) { +#else + drm_detect_hdmi_monitor(amdgpu_connector->edid)) { +#endif if (connector->display_info.bpc) bpc = connector->display_info.bpc; } @@ -157,7 +169,11 @@ int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector) break; } +#if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) if (connector->display_info.is_hdmi) { +#else + if (drm_detect_hdmi_monitor(amdgpu_connector->edid)) { +#endif /* * Pre DCE-8 hw can't handle > 12 bpc, and more than 12 bpc doesn't make * much sense without support for > 12 bpc framebuffers. RGB 4:4:4 at @@ -1245,7 +1261,11 @@ static enum drm_mode_status amdgpu_connector_dvi_mode_valid(struct drm_connector (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D) || (amdgpu_connector->connector_object_id == CONNECTOR_OBJECT_ID_HDMI_TYPE_B)) { return MODE_OK; +#if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) } else if (connector->display_info.is_hdmi) { +#else + } else if (drm_detect_hdmi_monitor(amdgpu_connector->edid)) { +#endif /* HDMI 1.3+ supports max clock of 340 Mhz */ if (mode->clock > 340000) return MODE_CLOCK_HIGH; @@ -1548,7 +1568,11 @@ static enum drm_mode_status amdgpu_connector_dp_mode_valid(struct drm_connector (amdgpu_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { return amdgpu_atombios_dp_mode_valid_helper(connector, mode); } else { +#if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) if (connector->display_info.is_hdmi) { +#else + if (drm_detect_hdmi_monitor(amdgpu_connector->edid)) { +#endif /* HDMI 1.3+ supports max clock of 340 Mhz */ if (mode->clock > 340000) return MODE_CLOCK_HIGH; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index a7e60d2e575a3..514a784c83b9c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1748,7 +1748,11 @@ bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc, if ((!(mode->flags & DRM_MODE_FLAG_INTERLACE)) && ((amdgpu_encoder->underscan_type == UNDERSCAN_ON) || ((amdgpu_encoder->underscan_type == UNDERSCAN_AUTO) && +#if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) connector->display_info.is_hdmi && +#else + drm_detect_hdmi_monitor(to_amdgpu_connector(connector)->edid) && +#endif amdgpu_display_is_hdtv_mode(mode)))) { if (amdgpu_encoder->underscan_hborder != 0) amdgpu_crtc->h_border = amdgpu_encoder->underscan_hborder; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c index 54913ae5148b6..ccd095286b0b0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c @@ -252,7 +252,11 @@ bool amdgpu_dig_monitor_is_duallink(struct drm_encoder *encoder, case DRM_MODE_CONNECTOR_HDMIB: if (amdgpu_connector->use_digital) { /* HDMI 1.3 supports up to 340 Mhz over single link */ +#if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) if (connector->display_info.is_hdmi) { +#else + if (drm_detect_hdmi_monitor(amdgpu_connector->edid)) { +#endif if (pixel_clock > 340000) return true; else @@ -274,7 +278,11 @@ bool amdgpu_dig_monitor_is_duallink(struct drm_encoder *encoder, return false; else { /* HDMI 1.3 supports up to 340 Mhz over single link */ +#if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) if (connector->display_info.is_hdmi) { +#else + if (drm_detect_hdmi_monitor(amdgpu_connector->edid)) { +#endif if (pixel_clock > 340000) return true; else diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c index 8defca3705d51..a15d80a896369 100644 --- a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c +++ b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c @@ -466,7 +466,11 @@ int amdgpu_atombios_encoder_get_encoder_mode(struct drm_encoder *encoder) if (amdgpu_connector->use_digital && (amdgpu_connector->audio == AMDGPU_AUDIO_ENABLE)) return ATOM_ENCODER_MODE_HDMI; +#if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) else if (connector->display_info.is_hdmi && +#else + else if (drm_detect_hdmi_monitor(amdgpu_connector->edid) && +#endif (amdgpu_connector->audio == AMDGPU_AUDIO_AUTO)) return ATOM_ENCODER_MODE_HDMI; else if (amdgpu_connector->use_digital) @@ -485,7 +489,11 @@ int amdgpu_atombios_encoder_get_encoder_mode(struct drm_encoder *encoder) if (amdgpu_audio != 0) { if (amdgpu_connector->audio == AMDGPU_AUDIO_ENABLE) return ATOM_ENCODER_MODE_HDMI; +#if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) else if (connector->display_info.is_hdmi && +#else + else if (drm_detect_hdmi_monitor(amdgpu_connector->edid) && +#endif (amdgpu_connector->audio == AMDGPU_AUDIO_AUTO)) return ATOM_ENCODER_MODE_HDMI; else @@ -503,7 +511,11 @@ int amdgpu_atombios_encoder_get_encoder_mode(struct drm_encoder *encoder) } else if (amdgpu_audio != 0) { if (amdgpu_connector->audio == AMDGPU_AUDIO_ENABLE) return ATOM_ENCODER_MODE_HDMI; +#if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) else if (connector->display_info.is_hdmi && +#else + else if (drm_detect_hdmi_monitor(amdgpu_connector->edid) && +#endif (amdgpu_connector->audio == AMDGPU_AUDIO_AUTO)) return ATOM_ENCODER_MODE_HDMI; else diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index 68a3a87b11348..c750a03a7e5f4 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -121,7 +121,12 @@ enum dc_edid_status dm_helpers_parse_edid_caps( edid_caps->display_name, AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS); +#if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) edid_caps->edid_hdmi = connector->display_info.is_hdmi; +#else + edid_caps->edid_hdmi = drm_detect_hdmi_monitor( + (struct edid *) edid->raw_edid); +#endif apply_edid_quirks(edid_buf, edid_caps); diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 712202125631d..3543aa7d3a959 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -293,6 +293,9 @@ /* struct drm_display_info has monitor_range member */ #define HAVE_DRM_DISPLAY_INFO_MONITOR_RANGE 1 +/* display_info->is_hdmi is available */ +#define HAVE_DRM_DISPLAY_INFO_IS_HDMI 1 + /* drm_dp_atomic_find_vcpi_slots() is available */ #define HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-display-info-hdmi.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-display-info-hdmi.m4 new file mode 100644 index 0000000000000..7c3454c843d50 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector-display-info-hdmi.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # dfbe9bf0 introduce this change +dnl # drm/amdgpu: replace drm_detect_hdmi_monitor() with drm_display_info.is_hdmi +dnl # v5.13-3121-gdfbe9bf067a2 +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DISPLAY_INFO_IS_HDMI], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_display_info *display_info = NULL; + display_info->is_hdmi = 0; + ], [ + AC_DEFINE(HAVE_DRM_DISPLAY_INFO_IS_HDMI, 1, + [display_info->is_hdmi is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 102146c662c22..b1ff287817c87 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -178,6 +178,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DEVICE_FB_HELPER AC_AMDGPU_DRM_DP_UPDATE_PAYLOAD_PART1_START_SLOT_ARG AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS + AC_AMDGPU_DRM_DISPLAY_INFO_IS_HDMI AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 2aeb75caa1926cecc7596bfc9d9a6730d629de6a Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Wed, 8 Dec 2021 10:45:57 -0500 Subject: [PATCH 0563/1868] drm/amdkcl: fix build error of debugfs entry dp_set_mst_en_for_sst_ops wrap the dp_set_mst_en_for_sst_ops debug entry code, the build error was caused by below commit : ad9601f002 drm/amd/display: Add Debugfs Entry to Force in SST Sequence v5.13-3122-gad9601f00296 Signed-off-by: Perry Yuan Reviewed-by: Shi, Leslie --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index b925151f8fc0d..1979f3bbf3724 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -3997,9 +3997,10 @@ static int dp_force_sst_get(void *data, u64 *val) return 0; } + +#if defined(DEFINE_DEBUGFS_ATTRIBUTE) DEFINE_DEBUGFS_ATTRIBUTE(dp_set_mst_en_for_sst_ops, dp_force_sst_get, dp_force_sst_set, "%llu\n"); - /* * Force DP2 sequence without VESA certified cable. * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dp_ignore_cable_id @@ -4023,6 +4024,7 @@ static int dp_ignore_cable_id_get(void *data, u64 *val) } DEFINE_DEBUGFS_ATTRIBUTE(dp_ignore_cable_id_ops, dp_ignore_cable_id_get, dp_ignore_cable_id_set, "%llu\n"); +#endif /* * Sets the DC visual confirm debug option from the given string. @@ -4175,12 +4177,12 @@ void dtn_debugfs_init(struct amdgpu_device *adev) adev, &capabilities_fops); debugfs_create_file("amdgpu_dm_dtn_log", 0644, root, adev, &dtn_log_fops); + +#ifdef DEFINE_DEBUGFS_ATTRIBUTE debugfs_create_file("amdgpu_dm_dp_set_mst_en_for_sst", 0644, root, adev, &dp_set_mst_en_for_sst_ops); debugfs_create_file("amdgpu_dm_dp_ignore_cable_id", 0644, root, adev, &dp_ignore_cable_id_ops); - -#ifdef DEFINE_DEBUGFS_ATTRIBUTE debugfs_create_file_unsafe("amdgpu_dm_visual_confirm", 0644, root, adev, &visual_confirm_fops); From 902053407c06953176fee69dc4e51d067e8a67c3 Mon Sep 17 00:00:00 2001 From: Xiaogang Chen Date: Mon, 13 Dec 2021 16:28:57 -0600 Subject: [PATCH 0564/1868] drm/amdkfd: explicitly create/destroy queue attributes under /sys When application is about finish it destroys queues it has created by an ioctl. Driver deletes queue entry(/sys/class/kfd/kfd/proc/pid/queues/queueid/) which is directory including this queue all attributes. Low level kernel code deletes all attributes under this directory. The lock from kernel is on queue entry, not its attributes. At meantime another user space application can read the attributes. There is possibility that the application can hold/read the attributes while kernel is deleting the queue entry, cause the application have invalid memory access, then killed by kernel. Driver changes: explicitly create/destroy each attribute for each queue, let kernel put lock on each attribute too. Signed-off-by: Xiaogang Chen Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 3 +++ drivers/gpu/drm/amd/amdkfd/kfd_process.c | 10 ++++++++++ 2 files changed, 13 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index fcb6121ddf437..6c4ba925532fc 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -637,6 +637,9 @@ struct queue { /* procfs */ struct kobject kobj; + struct attribute attr_guid; + struct attribute attr_size; + struct attribute attr_type; void *gang_ctx_bo; uint64_t gang_ctx_gpu_addr; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 2df5bfdbd0cc1..2fb4efa2e5e24 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -87,6 +87,8 @@ static void evict_process_worker(struct work_struct *work); static void restore_process_worker(struct work_struct *work); static void kfd_process_device_destroy_cwsr_dgpu(struct kfd_process_device *pdd); +static void kfd_sysfs_create_file(struct kobject *kobj, struct attribute *attr, + char *name); struct kfd_procfs_tree { struct kobject *kobj; @@ -525,6 +527,10 @@ int kfd_procfs_add_queue(struct queue *q) return ret; } + kfd_sysfs_create_file(&q->kobj, &q->attr_guid, "guid"); + kfd_sysfs_create_file(&q->kobj, &q->attr_size, "size"); + kfd_sysfs_create_file(&q->kobj, &q->attr_type, "type"); + return 0; } @@ -669,6 +675,10 @@ void kfd_procfs_del_queue(struct queue *q) if (!q) return; + sysfs_remove_file(&q->kobj, &q->attr_guid); + sysfs_remove_file(&q->kobj, &q->attr_size); + sysfs_remove_file(&q->kobj, &q->attr_type); + kobject_del(&q->kobj); kobject_put(&q->kobj); } From 597281e9f83dbf6baa95b7341fae104f1bd46931 Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Mon, 13 Dec 2021 03:34:27 -0500 Subject: [PATCH 0565/1868] drm/amdkcl: define macro of HDMI FRL feature for legacy os * Add some micro definition missing when building on ubuntu 5.8 kernel version * wrap DSC code with DSC support micro 8808f3ffb14 drm/amd/display: Add DP-HDMI FRL PCON Support in DC v5.13-3064-g8808f3ffb14d Signed-off-by: Perry Yuan Reviewed-by: Leslie Shi --- include/kcl/kcl_drm_dp_helper.h | 54 +++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/include/kcl/kcl_drm_dp_helper.h b/include/kcl/kcl_drm_dp_helper.h index 7fb0da12e569b..d92383908edc8 100644 --- a/include/kcl/kcl_drm_dp_helper.h +++ b/include/kcl/kcl_drm_dp_helper.h @@ -207,4 +207,58 @@ enum drm_dp_phy { #endif +/* + * v5.10-rc2-482-gce32a6239de6 + * drm/dp_helper: Add Helpers for FRL Link Training support for DP-HDMI2.1 PCON + */ +#ifndef DP_PCON_HDMI_POST_FRL_STATUS + +/* PCON CONFIGURE-1 FRL FOR HDMI SINK */ +#define DP_PCON_HDMI_LINK_CONFIG_1 0x305A +# define DP_PCON_ENABLE_MAX_FRL_BW (7 << 0) +# define DP_PCON_ENABLE_MAX_BW_0GBPS 0 +# define DP_PCON_ENABLE_MAX_BW_9GBPS 1 +# define DP_PCON_ENABLE_MAX_BW_18GBPS 2 +# define DP_PCON_ENABLE_MAX_BW_24GBPS 3 +# define DP_PCON_ENABLE_MAX_BW_32GBPS 4 +# define DP_PCON_ENABLE_MAX_BW_40GBPS 5 +# define DP_PCON_ENABLE_MAX_BW_48GBPS 6 +# define DP_PCON_ENABLE_SOURCE_CTL_MODE (1 << 3) +# define DP_PCON_ENABLE_CONCURRENT_LINK (1 << 4) +# define DP_PCON_ENABLE_SEQUENTIAL_LINK (0 << 4) +# define DP_PCON_ENABLE_LINK_FRL_MODE (1 << 5) +# define DP_PCON_ENABLE_HPD_READY (1 << 6) +# define DP_PCON_ENABLE_HDMI_LINK (1 << 7) + +/* PCON CONFIGURE-2 FRL FOR HDMI SINK */ +#define DP_PCON_HDMI_LINK_CONFIG_2 0x305B +# define DP_PCON_MAX_LINK_BW_MASK (0x3F << 0) +# define DP_PCON_FRL_BW_MASK_9GBPS (1 << 0) +# define DP_PCON_FRL_BW_MASK_18GBPS (1 << 1) +# define DP_PCON_FRL_BW_MASK_24GBPS (1 << 2) +# define DP_PCON_FRL_BW_MASK_32GBPS (1 << 3) +# define DP_PCON_FRL_BW_MASK_40GBPS (1 << 4) +# define DP_PCON_FRL_BW_MASK_48GBPS (1 << 5) +# define DP_PCON_FRL_LINK_TRAIN_EXTENDED (1 << 6) +# define DP_PCON_FRL_LINK_TRAIN_NORMAL (0 << 6) + +/* PCON HDMI LINK STATUS */ +#define DP_PCON_HDMI_TX_LINK_STATUS 0x303B +# define DP_PCON_HDMI_TX_LINK_ACTIVE (1 << 0) +# define DP_PCON_FRL_READY (1 << 1) + +/* PCON HDMI POST FRL STATUS */ +#define DP_PCON_HDMI_POST_FRL_STATUS 0x3036 +# define DP_PCON_HDMI_LINK_MODE (1 << 0) +# define DP_PCON_HDMI_MODE_TMDS 0 +# define DP_PCON_HDMI_MODE_FRL 1 +# define DP_PCON_HDMI_FRL_TRAINED_BW (0x3F << 1) +# define DP_PCON_FRL_TRAINED_BW_9GBPS (1 << 1) +# define DP_PCON_FRL_TRAINED_BW_18GBPS (1 << 2) +# define DP_PCON_FRL_TRAINED_BW_24GBPS (1 << 3) +# define DP_PCON_FRL_TRAINED_BW_32GBPS (1 << 4) +# define DP_PCON_FRL_TRAINED_BW_40GBPS (1 << 5) +# define DP_PCON_FRL_TRAINED_BW_48GBPS (1 << 6) +#endif + #endif /* _KCL_DRM_DP_HELPER_H_ */ From 3c1c7792a216b777a720adb351a2b82435201cef Mon Sep 17 00:00:00 2001 From: Fangzhi Zuo Date: Fri, 10 Dec 2021 21:31:38 -0500 Subject: [PATCH 0566/1868] drm/amd/display: Fix Compile Error for DCE Guard the new debugfs entry to DCN only Follow-up fix for: drm/amd/display: Add Debugfs Entry to Force in SST Sequence Signed-off-by: Fangzhi Zuo Reviewed-by: Nicholas Choi Acked-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index 1979f3bbf3724..500ab1469515b 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -4001,6 +4001,7 @@ static int dp_force_sst_get(void *data, u64 *val) #if defined(DEFINE_DEBUGFS_ATTRIBUTE) DEFINE_DEBUGFS_ATTRIBUTE(dp_set_mst_en_for_sst_ops, dp_force_sst_get, dp_force_sst_set, "%llu\n"); + /* * Force DP2 sequence without VESA certified cable. * Example usage: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dp_ignore_cable_id From 99866407389a7a051e65e2b7fe711ef8e1ba4b4e Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Tue, 14 Dec 2021 00:22:48 -0500 Subject: [PATCH 0567/1868] drm/amdkcl: add definition of DP_DPCD_REV_XX to kcl_drm_dp_helper The patch add some missing micro definition of DP_DPCD_REV_XX to drm kcl header kcl_drm_dp_helper.h to resolve some dependency case. original commit: 0597017cd1 drm/dp: Add DP_DPCD_REV_XX to drm_dp_helper v4.16-rc7-1860-g0597017cd18d Signed-off-by: Perry Yuan Reviewed-by: Leslie Shi --- include/kcl/kcl_drm_dp_helper.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/include/kcl/kcl_drm_dp_helper.h b/include/kcl/kcl_drm_dp_helper.h index d92383908edc8..ec52d89063426 100644 --- a/include/kcl/kcl_drm_dp_helper.h +++ b/include/kcl/kcl_drm_dp_helper.h @@ -260,5 +260,20 @@ enum drm_dp_phy { # define DP_PCON_FRL_TRAINED_BW_40GBPS (1 << 5) # define DP_PCON_FRL_TRAINED_BW_48GBPS (1 << 6) #endif +/* + * v4.16-rc7-1860-g0597017cd18d + * drm/dp: Add DP_DPCD_REV_XX to drm_dp_helper + */ + +/* DPCD Field Address Mapping */ + +/* Receiver Capability */ +#ifndef DP_DPCD_REV_14 +# define DP_DPCD_REV_10 0x10 +# define DP_DPCD_REV_11 0x11 +# define DP_DPCD_REV_12 0x12 +# define DP_DPCD_REV_13 0x13 +# define DP_DPCD_REV_14 0x14 +#endif #endif /* _KCL_DRM_DP_HELPER_H_ */ From da7cc1412e1e42fd9c37dc872e16d7696a24ca91 Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Wed, 15 Dec 2021 03:25:57 -0500 Subject: [PATCH 0568/1868] drm/amdkcl: fake bitmap_alloc(), bitmap_zalloc() and bitmap_free() This patch will fix the below patch building dependency issue on some old kernels version. 1a48fbd4 drm/amdkfd: Use bitmap_zalloc() when applicable v5.13-3049-g1a48fbd4ce19 Signed-off-by: Perry Yuan Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_bitmap.c | 48 +++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 ++ .../drm/amd/dkms/m4/drm-bitmap-functions.m4 | 12 +++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_bitmap.h | 42 ++++++++++++++++ 7 files changed, 108 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_bitmap.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-bitmap-functions.m4 create mode 100644 include/kcl/kcl_bitmap.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index ef7887752b276..5352465a012f4 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -12,7 +12,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_drm_crtc.o kcl_drm_connector.o kcl_drm_atomic_helper.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o kcl_ftrace.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_fs_read_write.o kcl_drm_aperture.o \ - kcl_drm_drv.o kcl_drm_simple_kms_helper.o + kcl_drm_drv.o kcl_drm_simple_kms_helper.o kcl_bitmap.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_bitmap.c b/drivers/gpu/drm/amd/amdkcl/kcl_bitmap.c new file mode 100644 index 0000000000000..106a0960013d2 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_bitmap.c @@ -0,0 +1,48 @@ +/* + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef HAVE_BITMAP_FUNCS + +#include +#include +#include +#include + +unsigned long *bitmap_alloc(unsigned int nbits, gfp_t flags) +{ + return kmalloc_array(BITS_TO_LONGS(nbits), sizeof(unsigned long), + flags); +} +EXPORT_SYMBOL(bitmap_alloc); + +unsigned long *bitmap_zalloc(unsigned int nbits, gfp_t flags) +{ + return bitmap_alloc(nbits, flags | __GFP_ZERO); +} +EXPORT_SYMBOL(bitmap_zalloc); + +void bitmap_free(const unsigned long *bitmap) +{ + kfree(bitmap); +} +EXPORT_SYMBOL(bitmap_free); +#endif /* HAVE_BITMAP_FUNCS */ + diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 4ede69680225a..c26be24e7c01b 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -80,5 +80,6 @@ #include "kcl/kcl_drm_aperture.h" #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 3543aa7d3a959..6db9845cfabed 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1108,6 +1108,9 @@ /* zone_managed_pages() is available */ #define HAVE_ZONE_MANAGED_PAGES 1 +/* bitmap_free() is available */ +#define HAVE_BITMAP_FUNCS 1 + /* __drm_atomic_helper_connector_destroy_state() wants 1 arg */ #define HAVE___DRM_ATOMIC_HELPER_CONNECTOR_DESTROY_STATE_P 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-bitmap-functions.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-bitmap-functions.m4 new file mode 100644 index 0000000000000..542826aa5e405 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-bitmap-functions.m4 @@ -0,0 +1,12 @@ +dnl # +dnl # commit c42b65e363ce introduce this change +dnl # v4.17-3-gc42b65e363ce +dnl # bitmap: Add bitmap_alloc(), bitmap_zalloc() and bitmap_free() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_BITMAP_FUNCS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([bitmap_free], [linux/bitmap.h], [ + AC_DEFINE(HAVE_BITMAP_FUNCS, 1, [bitmap_free() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index b1ff287817c87..e21d707785304 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -179,6 +179,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_UPDATE_PAYLOAD_PART1_START_SLOT_ARG AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS AC_AMDGPU_DRM_DISPLAY_INFO_IS_HDMI + AC_AMDGPU_DRM_BITMAP_FUNCS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_bitmap.h b/include/kcl/kcl_bitmap.h new file mode 100644 index 0000000000000..5eb728c542ef3 --- /dev/null +++ b/include/kcl/kcl_bitmap.h @@ -0,0 +1,42 @@ +/* + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef KCL_BITMAP_H +#define KCL_BITMAP_H + +#ifndef HAVE_BITMAP_FUNCS +/* Copied from include/linux/bitmap.h*/ + +/* + * v4.17-3-gc42b65e363ce + * bitmap: Add bitmap_alloc(), bitmap_zalloc() and bitmap_free() + */ + +/* + * Allocation and deallocation of bitmap. + * Provided in lib/bitmap.c to avoid circular dependency. + */ +unsigned long *bitmap_alloc(unsigned int nbits, gfp_t flags); +unsigned long *bitmap_zalloc(unsigned int nbits, gfp_t flags); +void bitmap_free(const unsigned long *bitmap); +#endif /* HAVE_BITMAP_FUNCS */ + +#endif /* KCL_BITMAP_H */ From c4a6cf5199c867229cdb2bae2fa7c886ff5cd85b Mon Sep 17 00:00:00 2001 From: Jeremy Newton Date: Fri, 17 Dec 2021 10:42:35 -0500 Subject: [PATCH 0569/1868] drm/amdkcl: Remove REMAKE_INITRD from dkms This is deprecated and causes issues during installation of the amdgpu-dkms package on RHEL. For manual testing, please use dracut manually to regenerate initrd. Fixes SWDEV-315476 SWDEV-314875 Signed-off-by: Jeremy Newton Change-Id: If2ab6bf7d00aa2689ffe543134e1291b0b95f5da --- drivers/gpu/drm/amd/dkms/dkms.conf | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/dkms.conf b/drivers/gpu/drm/amd/dkms/dkms.conf index 7a6075f32cb5a..146f1b4db6148 100644 --- a/drivers/gpu/drm/amd/dkms/dkms.conf +++ b/drivers/gpu/drm/amd/dkms/dkms.conf @@ -1,7 +1,6 @@ PACKAGE_NAME="amdgpu" PACKAGE_VERSION="1.0" AUTOINSTALL="yes" -REMAKE_INITRD="yes" PRE_BUILD="amd/dkms/pre-build.sh $kernelver" # not work with RHEL DKMS From 68b6bab0010f45d85f4806e27d693252b24b4ef0 Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Mon, 20 Dec 2021 22:44:06 -0500 Subject: [PATCH 0570/1868] drm/amdkcl: wrap drm_edid_get_monitor_name with macro HAVE_DRM_EDID_GET_MONITOR_NAME This patch will check if the drm_edid_get_monitor_name exist in the some old kernel to avoid build dependency failure. b5f640ae7a0 drm/amdgpu: use drm_edid_get_monitor_name() instead of duplicating the code v5.13-3120-gb5f640ae7a0a Signed-off-by: Perry Yuan Reviewed-by: Leslie Shi --- .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 21 ++++++++++++++++++- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../amd/dkms/m4/drm-edid-get-monitor-name.m4 | 17 +++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 41 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-edid-get-monitor-name.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index c750a03a7e5f4..4b3e81600575f 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -100,6 +100,9 @@ enum dc_edid_status dm_helpers_parse_edid_caps( int sadb_count = -1; int i = 0; uint8_t *sadb = NULL; +#if !defined(HAVE_DRM_EDID_GET_MONITOR_NAME) + int j = 0; +#endif enum dc_edid_status result = EDID_OK; @@ -116,10 +119,26 @@ enum dc_edid_status dm_helpers_parse_edid_caps( edid_caps->serial_number = edid_buf->serial; edid_caps->manufacture_week = edid_buf->mfg_week; edid_caps->manufacture_year = edid_buf->mfg_year; - +#if defined(HAVE_DRM_EDID_GET_MONITOR_NAME) drm_edid_get_monitor_name(edid_buf, edid_caps->display_name, AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS); +#else + /* One of the four detailed_timings stores the monitor name. It's + * stored in an array of length 13. */ + for (i = 0; i < 4; i++) { + if (edid_buf->detailed_timings[i].data.other_data.type == 0xfc) { + while (j < 13 && edid_buf->detailed_timings[i].data.other_data.data.str.str[j]) { + if (edid_buf->detailed_timings[i].data.other_data.data.str.str[j] == '\n') + break; + + edid_caps->display_name[j] = + edid_buf->detailed_timings[i].data.other_data.data.str.str[j]; + j++; + } + } + } +#endif #if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) edid_caps->edid_hdmi = connector->display_info.is_hdmi; diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 6db9845cfabed..e03b550b5ae49 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1111,6 +1111,9 @@ /* bitmap_free() is available */ #define HAVE_BITMAP_FUNCS 1 +/* drm_edid_get_monitor_name is available*/ +#define HAVE_DRM_EDID_GET_MONITOR_NAME 1 + /* __drm_atomic_helper_connector_destroy_state() wants 1 arg */ #define HAVE___DRM_ATOMIC_HELPER_CONNECTOR_DESTROY_STATE_P 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-edid-get-monitor-name.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-edid-get-monitor-name.m4 new file mode 100644 index 0000000000000..c5de63f48eb91 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-edid-get-monitor-name.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v4.6-rc2-221-g59f7c0fa325e +dnl # drm/edid: Add drm_edid_get_monitor_name() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_EDID_GET_MONITOR_NAME], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_edid_get_monitor_name(NULL, NULL, NULL); + ], [drm_edid_get_monitor_name], [drivers/gpu/drm/drm_edid.c], [ + AC_DEFINE(HAVE_DRM_EDID_GET_MONITOR_NAME, 1, + [drm_edid_get_monitor_name() are available]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index e21d707785304..3fb987f3bfb86 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -180,6 +180,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS AC_AMDGPU_DRM_DISPLAY_INFO_IS_HDMI AC_AMDGPU_DRM_BITMAP_FUNCS + AC_AMDGPU_DRM_EDID_GET_MONITOR_NAME AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 7a379f35a20b61e3f687d23a7a9a20f4894edec4 Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Mon, 27 Dec 2021 21:50:08 -0500 Subject: [PATCH 0571/1868] drm/amddkms: remove the duplicated amdgpu_amdkfd_gpuvm_pin_bo call The patch fix the amdgpu bo released twice kernel warning [ 604.329614] Workqueue: kfd_process_wq kfd_process_wq_release [amdgpu] [ 604.329752] RIP: 0010:ttm_bo_release+0x2f6/0x320 [amdttm] [ 604.329757] Code: e8 2f 68 e8 d4 e9 9e fd ff ff 48 8b 7b 94 b9 4c 1d 00 00 31 d2 be 01 00 00 00 e8 65 23 36 00 48 8b 7b e4 eb 9d 4c 89 e7 eb 98 <0f> 0b e9 2e fd ff ff e8 6e 60 e8 d4 e9 ed fe ff ff be 03 00 00 00 [ 604.329758] RSP: 0018:ffffaebec0c8fc40 EFLAGS: 00010202 [ 604.329759] RAX: 0000000000000001 RBX: ffff971f8716adbc RCX: 0000000080400039 [ 604.329760] RDX: 0000000000000001 RSI: 0000000080400039 RDI: ffff971f8716adbc [ 604.329761] RBP: ffffaebec0c8fc68 R08: ffff971f8716adbc R09: ffffffffc053b900 [ 604.329762] R10: ffff971fee794540 R11: 0000000000000001 R12: ffff971f93c65368 [ 604.329762] R13: ffff971f8db13038 R14: ffff971f8716ac58 R15: dead000000000100 [ 604.329763] FS: 0000000000000000(0000) GS:ffff97268edc0000(0000) knlGS:0000000000000000 [ 604.329764] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 604.329765] CR2: 0000000620cdc258 CR3: 000000051c610005 CR4: 00000000003706e0 [ 604.329766] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 [ 604.329767] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 [ 604.329767] Call Trace: [ 604.329769] amdttm_bo_put+0x30/0x50 [amdttm] [ 604.329772] amdgpu_bo_unref+0x1e/0x30 [amdgpu] [ 604.329856] amdgpu_gem_object_free+0x8c/0x160 [amdgpu] [ 604.329939] drm_gem_object_free+0x1d/0x30 [drm] [ 604.329956] amdgpu_amdkfd_gpuvm_free_memory_of_gpu+0x35e/0x3b0 [amdgpu] [ 604.330071] ? preempt_schedule_common+0x18/0x30 [ 604.330074] kfd_process_device_free_bos+0xda/0x120 [amdgpu] [ 604.330183] kfd_process_wq_release+0x2a4/0x360 [amdgpu] [ 604.330289] process_one_work+0x220/0x3c0 [ 604.330291] worker_thread+0x4d/0x3f0 [ 604.330292] ? process_one_work+0x3c0/0x3c0 [ 604.330293] kthread+0x12b/0x150 [ 604.330295] ? set_kthread_struct+0x40/0x40 [ 604.330297] ret_from_fork+0x22/0x30 [ 604.330300] ---[ end trace acd84dcb8e491ccb ]--- It was caused by below commit deffdd3f09 drm/amdgpu: Pin MMIO/DOORBELL BO's in GTT domain v5.13-2965-gdeffdd3f0971 Signed-off-by: Perry Yuan Reviewed-by: Guchun Chen Change-Id: Ica29a250dae065f9999803d94f858f8dda6840aa --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 1b2505fbe6442..c4475899bfe8c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -1957,17 +1957,6 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( if (offset) *offset = amdgpu_bo_mmap_offset(bo); - if (flags & (KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL | - KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP)) { - ret = amdgpu_amdkfd_gpuvm_pin_bo(bo, AMDGPU_GEM_DOMAIN_GTT); - if (ret) { - pr_err("Pinning MMIO/DOORBELL BO during ALLOC FAILED\n"); - goto err_pin_bo; - } - bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT; - bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT; - } - return 0; allocate_init_user_pages_failed: From 37cf349522edc4e943f849401560688b03fc4375 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 28 Dec 2021 12:26:09 +0800 Subject: [PATCH 0572/1868] drm/amdkcl: refactor code for drm_aperture.h Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c | 5 +++-- drivers/gpu/drm/amd/dkms/m4/drm-aperture.m4 | 16 ---------------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - include/kcl/header/drm/drm_aperture.h | 9 +++++++++ include/kcl/kcl_drm_aperture.h | 4 ++-- 5 files changed, 14 insertions(+), 21 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-aperture.m4 create mode 100644 include/kcl/header/drm/drm_aperture.h diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c index 99c29f3b4c803..f91a4d60ffd11 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: MIT -#ifndef HAVE_DRM_APERTURE +#ifndef HAVE_DRM_APERTURE_H + #include #include #include @@ -142,4 +143,4 @@ int drm_aperture_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, const } EXPORT_SYMBOL(drm_aperture_remove_conflicting_pci_framebuffers); -#endif /* HAVE_DRM_APERTURE */ +#endif /* HAVE_DRM_APERTURE_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-aperture.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-aperture.m4 deleted file mode 100644 index 532e9149653c9..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm-aperture.m4 +++ /dev/null @@ -1,16 +0,0 @@ -dnl # -dnl # commit 2916059147ea38f76787d7b38dee883da2e9def2 -dnl # drm/aperture: Add infrastructure for aperture ownership -dnl # -AC_DEFUN([AC_AMDGPU_DRM_APERTURE], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - drm_aperture_remove_conflicting_pci_framebuffers(NULL, NULL); - ], [ - AC_DEFINE(HAVE_DRM_APERTURE, 1, - [drm_aperture_remove_* is availablea]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 3fb987f3bfb86..455b69201e0ee 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -153,7 +153,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_MEMCPY_FROM_WC AC_AMDGPU_IS_COW_MAPPING AC_AMDGPU_VGA_REMOVE_VGACON - AC_AMDGPU_DRM_APERTURE AC_AMDGPU_PCI_DRIVER_DEV_GROUPS AC_AMDGPU_DRM_DISPLAY_INFO AC_AMDGPU_IO_MAPPING_UNMAP_LOCAL diff --git a/include/kcl/header/drm/drm_aperture.h b/include/kcl/header/drm/drm_aperture.h new file mode 100644 index 0000000000000..9197d9538fc69 --- /dev/null +++ b/include/kcl/header/drm/drm_aperture.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DRM_APERTURE_H_H_ +#define _KCL_HEADER_DRM_APERTURE_H_H_ + +#if defined(HAVE_DRM_DRM_APERTURE_H) +#include_next +#endif + +#endif diff --git a/include/kcl/kcl_drm_aperture.h b/include/kcl/kcl_drm_aperture.h index 5c402e251a5d9..e1af88ce1ba85 100644 --- a/include/kcl/kcl_drm_aperture.h +++ b/include/kcl/kcl_drm_aperture.h @@ -2,7 +2,7 @@ #ifndef KCL_KCL_DRM_APERTURE_H #define KCL_KCL_DRM_APERTURE_H -#ifndef HAVE_DRM_APERTURE +#ifndef HAVE_DRM_DRM_APERTURE_H #include @@ -20,6 +20,6 @@ int drm_aperture_remove_conflicting_framebuffers(resource_size_t base, resource_ int drm_aperture_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, const char *name); -#endif /* HAVE_DRM_APERTURE */ +#endif /* HAVE_DRM_DRM_APERTURE_H */ #endif From 2fcfb849dcfa4407eedf06add392f4839cbc7974 Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Tue, 28 Dec 2021 22:54:31 -0500 Subject: [PATCH 0573/1868] drm/amdkcl: rename the bitmap function prefix for definition conflicts The patch will fix the bitmap_free and some other new bitmap_xx function on the some old version kernel, including ubuntu 18.04 4.15.0-72-generic kernel, the patch rename the bitmap function with kcl_ as prefix to resolve the name space conflict issue. the new patch is based on below commit and improve it. 99eae3189d5f drm/amdkcl: fake bitmap_alloc(), bitmap_zalloc() and bitmap_free() Signed-off-by: Perry Yuan Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/kcl_bitmap.c | 14 +++++++------- .../drm/amd/amdkfd/kfd_process_queue_manager.c | 9 +++++++++ .../drm/amd/dkms/m4/drm-bitmap-functions.m4 | 18 +++++++++++++----- include/kcl/kcl_bitmap.h | 6 +++--- 4 files changed, 32 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_bitmap.c b/drivers/gpu/drm/amd/amdkcl/kcl_bitmap.c index 106a0960013d2..946b29d66408b 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_bitmap.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_bitmap.c @@ -26,23 +26,23 @@ #include #include -unsigned long *bitmap_alloc(unsigned int nbits, gfp_t flags) +unsigned long *kcl_bitmap_alloc(unsigned int nbits, gfp_t flags) { return kmalloc_array(BITS_TO_LONGS(nbits), sizeof(unsigned long), flags); } -EXPORT_SYMBOL(bitmap_alloc); +EXPORT_SYMBOL(kcl_bitmap_alloc); -unsigned long *bitmap_zalloc(unsigned int nbits, gfp_t flags) +unsigned long *kcl_bitmap_zalloc(unsigned int nbits, gfp_t flags) { - return bitmap_alloc(nbits, flags | __GFP_ZERO); + return kcl_bitmap_alloc(nbits, flags | __GFP_ZERO); } -EXPORT_SYMBOL(bitmap_zalloc); +EXPORT_SYMBOL(kcl_bitmap_zalloc); -void bitmap_free(const unsigned long *bitmap) +void kcl_bitmap_free(const unsigned long *bitmap) { kfree(bitmap); } -EXPORT_SYMBOL(bitmap_free); +EXPORT_SYMBOL(kcl_bitmap_free); #endif /* HAVE_BITMAP_FUNCS */ diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c index e15da906b6d22..22a15c7193233 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c @@ -171,8 +171,13 @@ void kfd_process_dequeue_from_all_devices(struct kfd_process *p) int pqm_init(struct process_queue_manager *pqm, struct kfd_process *p) { INIT_LIST_HEAD(&pqm->queues); +#if defined(HAVE_BITMAP_FUNCS) pqm->queue_slot_bitmap = bitmap_zalloc(KFD_MAX_NUM_OF_QUEUES_PER_PROCESS, GFP_KERNEL); +#else + pqm->queue_slot_bitmap = kcl_bitmap_zalloc(KFD_MAX_NUM_OF_QUEUES_PER_PROCESS, + GFP_KERNEL); +#endif if (!pqm->queue_slot_bitmap) return -ENOMEM; pqm->process = p; @@ -228,7 +233,11 @@ void pqm_uninit(struct process_queue_manager *pqm) kfree(pqn); } +#if defined(HAVE_BITMAP_FUNCS) bitmap_free(pqm->queue_slot_bitmap); +#else + kcl_bitmap_free(pqm->queue_slot_bitmap); +#endif pqm->queue_slot_bitmap = NULL; } diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-bitmap-functions.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-bitmap-functions.m4 index 542826aa5e405..b91abf96c4598 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-bitmap-functions.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-bitmap-functions.m4 @@ -4,9 +4,17 @@ dnl # v4.17-3-gc42b65e363ce dnl # bitmap: Add bitmap_alloc(), bitmap_zalloc() and bitmap_free() dnl # AC_DEFUN([AC_AMDGPU_DRM_BITMAP_FUNCS], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([bitmap_free], [linux/bitmap.h], [ - AC_DEFINE(HAVE_BITMAP_FUNCS, 1, [bitmap_free() is available]) - ]) - ]) + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + bitmap_free(NULL); + bitmap_alloc(NULL); + bitmap_zalloc(NULL); + ],[ + AC_DEFINE(HAVE_BITMAP_FUNCS, + 1, + [bitmap_free(),bitmap_alloc(),bitmap_zalloc is available]) + ]) + ]) ]) diff --git a/include/kcl/kcl_bitmap.h b/include/kcl/kcl_bitmap.h index 5eb728c542ef3..f65fa8fbcc56d 100644 --- a/include/kcl/kcl_bitmap.h +++ b/include/kcl/kcl_bitmap.h @@ -34,9 +34,9 @@ * Allocation and deallocation of bitmap. * Provided in lib/bitmap.c to avoid circular dependency. */ -unsigned long *bitmap_alloc(unsigned int nbits, gfp_t flags); -unsigned long *bitmap_zalloc(unsigned int nbits, gfp_t flags); -void bitmap_free(const unsigned long *bitmap); +unsigned long *kcl_bitmap_alloc(unsigned int nbits, gfp_t flags); +unsigned long *kcl_bitmap_zalloc(unsigned int nbits, gfp_t flags); +void kcl_bitmap_free(const unsigned long *bitmap); #endif /* HAVE_BITMAP_FUNCS */ #endif /* KCL_BITMAP_H */ From 08d380b56aef52578a3ee8f738dcfd00e876fd41 Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Sun, 26 Dec 2021 21:21:31 -0500 Subject: [PATCH 0574/1868] drm/amdkcl: add wait callback to the amdgpu_job_fence_ops the patch fix the kernel hang issue which was caused by below commit. 8daddbf88a414b33be drm/amdgpu: introduce new amdgpu_fence object to indicate the job embedded fence v5.13-3204-g8daddbf88a41 Signed-off-by: Perry Yuan Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index 0285bc1c26673..5f4b3f933bc68 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c @@ -900,6 +900,7 @@ static const struct dma_fence_ops amdgpu_job_fence_ops = { .get_driver_name = amdgpu_fence_get_driver_name, .get_timeline_name = amdgpu_job_fence_get_timeline_name, .enable_signaling = amdgpu_job_fence_enable_signaling, + AMDKCL_DMA_FENCE_OPS_WAIT_OPTIONAL .release = amdgpu_job_fence_release, }; From 8e8354fbea8c30e086d233a6ddd6e681e80aa36e Mon Sep 17 00:00:00 2001 From: Kent Russell Date: Wed, 5 Jan 2022 13:33:44 -0500 Subject: [PATCH 0575/1868] drm/amdgpu: Re-enable GFX RAS by default This was disabled due to issues on A+A but these have been addressed. Re-enable GFX RAS by default and remove the requirement on ras_mask=0xe Signed-off-by: Kent Russell Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 27e4f6d902519..016ceec114cce 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -3456,14 +3456,9 @@ static void amdgpu_ras_check_supported(struct amdgpu_device *adev) } else { /* driver only manages a few IP blocks RAS feature * when GPU is connected cpu through XGMI */ - adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__SDMA | - 1 << AMDGPU_RAS_BLOCK__MMHUB); - /* This is temporary workaround to leverage ras_mask - * to allow nable GFX RAS manually. Should be removed later - */ - if (amdgpu_ras_enable && - (amdgpu_ras_mask == 0xe)) - adev->ras_hw_enabled |= 1 << AMDGPU_RAS_BLOCK__GFX; + adev->ras_hw_enabled |= (1 << AMDGPU_RAS_BLOCK__GFX | + 1 << AMDGPU_RAS_BLOCK__SDMA | + 1 << AMDGPU_RAS_BLOCK__MMHUB); } /* apply asic specific settings (vega20 only for now) */ From 8a7b63c497fd31e257f7f4d96e84429e46f891c3 Mon Sep 17 00:00:00 2001 From: Jonathan Kim Date: Mon, 20 Dec 2021 16:06:19 -0500 Subject: [PATCH 0576/1868] drm/amdkfd: switch debugger asic type checks to ip version checks The rest of the driver now uses IP version checks so have the debugger code do the same. Signed-off-by: Jonathan Kim Reviewed-by: Graham Sider --- drivers/gpu/drm/amd/amdkfd/kfd_device.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index a972110e37626..e40f40d1a2259 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -572,12 +572,14 @@ static int kfd_gws_init(struct kfd_node *node) ret = amdgpu_amdkfd_alloc_gws(node->adev, node->adev->gds.gws_size, &node->gws); - if ((kfd->adev->asic_type == CHIP_VEGA10 - && kfd->mec2_fw_version < 0x81b6) - || (kfd->adev->asic_type >= CHIP_VEGA12 - && kfd->adev->asic_type <= CHIP_RAVEN - && kfd->mec2_fw_version < 0x1b6) - || (kfd->adev->asic_type == CHIP_ARCTURUS + if ((KFD_GC_VERSION(kfd) == IP_VERSION(9, 0, 1) + && kfd->mec2_fw_version < 0x81b6) || + (KFD_GC_VERSION(kfd) >= IP_VERSION(9, 1, 0) + && KFD_GC_VERSION(kfd) <= IP_VERSION(9, 2, 2) + && kfd->mec2_fw_version < 0x1b6) || + (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 0) + && kfd->mec2_fw_version < 0x1b6) || + (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 1) && kfd->mec2_fw_version < 0x30)) kfd->gws_debug_workaround = true; From 153153e4066327261fd9716ed04029802cd1dbc4 Mon Sep 17 00:00:00 2001 From: Alex Sierra Date: Wed, 5 Jan 2022 20:54:22 -0600 Subject: [PATCH 0577/1868] drm/amdkcl: test for full HMM support in kernel Make sure HMM is fully supported in the current kernel version. Some Kernels that were HMM back ported, have missing implementation. Ex. RHEL 8.5 with Kernel 4.18. Signed-off-by: Alex Sierra Suggested-by: Flora Cui Acked-by: Felix Kuehling Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/m4/hmm.m4 | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/hmm.m4 b/drivers/gpu/drm/amd/dkms/m4/hmm.m4 index c175fd6289702..72147cbe68a28 100644 --- a/drivers/gpu/drm/amd/dkms/m4/hmm.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/hmm.m4 @@ -32,6 +32,7 @@ AC_DEFUN([AC_AMDGPU_HMM_RANGE_FAULT], [ ]) dnl # +dnl # v5.1-10231-gbf198b2b34bf: mm/mmu_notifier: pass down vma and reasons why mmu notifier is happening dnl # 93f4e735b6d9 - mm/hmm: remove hmm_range_dma_map and hmm_range_dma_unmap 2019-11-23 19:56:45 -0400 dnl # d28c2c9a4877 - mm/hmm: make full use of walk_page_range() 2019-11-23 19:56:45 -0400 dnl # d3eeb1d77c5d - xen/gntdev: use mmu_interval_notifier_insert 2019-11-23 19:56:45 -0400 @@ -53,10 +54,14 @@ AC_DEFUN([AC_AMDGPU_HMM], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ #include + #include ], [ #ifdef CONFIG_HMM_MIRROR struct hmm_range *range = NULL; + struct mmu_notifier_range *mmu_range = NULL; + range->notifier = NULL; + mmu_range->vma = NULL; #else #error CONFIG_HMM_MIRROR not enabled #endif From aa837164b533f53aef94bfe13f24cc9cfedabc23 Mon Sep 17 00:00:00 2001 From: majun Date: Wed, 12 Jan 2022 14:16:44 +0800 Subject: [PATCH 0578/1868] amd/amdkcl: Fix the compile error caused by struct kobj_type The patch (drm/amdgpu: use default_groups in kobj_type) introduced a new member "default_groups" in struct kobj_type. To fix the compile errors cuased by this patch, a new kcl macro is added. Reviewed-by: Guchun Chen Signed-off-by: majun Change-Id: If536c7cddfafd17be652a7f15cb68f2e7b4a80d4 --- drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 6 ++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../gpu/drm/amd/dkms/m4/struct_kobj_type.m4 | 19 +++++++++++++++++++ 4 files changed, 29 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/struct_kobj_type.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c index 7de449fae1e3a..c142e79ef81b6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c @@ -325,7 +325,9 @@ static struct attribute *amdgpu_xgmi_hive_attrs[] = { &amdgpu_xgmi_hive_id, NULL }; +#ifdef HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE ATTRIBUTE_GROUPS(amdgpu_xgmi_hive); +#endif static ssize_t amdgpu_xgmi_show_attrs(struct kobject *kobj, struct attribute *attr, char *buf) @@ -358,7 +360,11 @@ static const struct sysfs_ops amdgpu_xgmi_hive_ops = { static const struct kobj_type amdgpu_xgmi_hive_type = { .release = amdgpu_xgmi_hive_release, .sysfs_ops = &amdgpu_xgmi_hive_ops, +#ifdef HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE .default_groups = amdgpu_xgmi_hive_groups, +#else + .default_attrs = amdgpu_xgmi_hive_attrs, +#endif }; static ssize_t amdgpu_xgmi_show_device_id(struct device *dev, diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index e03b550b5ae49..ab745ced8746c 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1129,6 +1129,9 @@ /* __print_array is available */ #define HAVE___PRINT_ARRAY 1 +/* kobj_type->default_groups is available */ +#define HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE 1 + /* Define to the address where bug reports for this package should be sent. */ #define PACKAGE_BUGREPORT "" diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 455b69201e0ee..b7d4b5d0f3e1a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -180,6 +180,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DISPLAY_INFO_IS_HDMI AC_AMDGPU_DRM_BITMAP_FUNCS AC_AMDGPU_DRM_EDID_GET_MONITOR_NAME + AC_AMDGPU_STRUCT_KOBJ_TYPE AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_kobj_type.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_kobj_type.m4 new file mode 100644 index 0000000000000..a698f80362f2c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/struct_kobj_type.m4 @@ -0,0 +1,19 @@ +dnl # +dnl # commit aa30f47cf666111f6bbfd15f290a27e8a7b9d854 +dnl # kobject: Add support for default attribute groups to kobj_type +dnl # + +AC_DEFUN([AC_AMDGPU_STRUCT_KOBJ_TYPE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct kobj_type *k_type = NULL; + k_type->default_groups = NULL; + ],[ + AC_DEFINE(HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE, 1, + [kobj_type->default_groups is available]) + ],[ + ]) + ]) +]) From 41d17aa440dc87ab78cc03336f26c87bafcabda3 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 11 Jan 2022 13:35:09 +0800 Subject: [PATCH 0579/1868] drm/amdkcl: cleanup kcl_bitmap_xxx rename to bitmap_xxx to avoid changes in amdgpu part Reviewed-by: Ma Jun Signed-off-by: Flora Cui Change-Id: I3401f1758f146521f7115a14880f779811e3bb4f --- .../amd/amdkfd/kfd_process_queue_manager.c | 4 +-- drivers/gpu/drm/amd/backport/backport.h | 2 +- include/kcl/backport/kcl_bitmap.h | 34 +++++++++++++++++++ 3 files changed, 37 insertions(+), 3 deletions(-) create mode 100644 include/kcl/backport/kcl_bitmap.h diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c index 22a15c7193233..d1ac315c25125 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c @@ -175,7 +175,7 @@ int pqm_init(struct process_queue_manager *pqm, struct kfd_process *p) pqm->queue_slot_bitmap = bitmap_zalloc(KFD_MAX_NUM_OF_QUEUES_PER_PROCESS, GFP_KERNEL); #else - pqm->queue_slot_bitmap = kcl_bitmap_zalloc(KFD_MAX_NUM_OF_QUEUES_PER_PROCESS, + pqm->queue_slot_bitmap = bitmap_zalloc(KFD_MAX_NUM_OF_QUEUES_PER_PROCESS, GFP_KERNEL); #endif if (!pqm->queue_slot_bitmap) @@ -236,7 +236,7 @@ void pqm_uninit(struct process_queue_manager *pqm) #if defined(HAVE_BITMAP_FUNCS) bitmap_free(pqm->queue_slot_bitmap); #else - kcl_bitmap_free(pqm->queue_slot_bitmap); + bitmap_free(pqm->queue_slot_bitmap); #endif pqm->queue_slot_bitmap = NULL; } diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index c26be24e7c01b..0bb5673cc401e 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -80,6 +80,6 @@ #include "kcl/kcl_drm_aperture.h" #include #include -#include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/backport/kcl_bitmap.h b/include/kcl/backport/kcl_bitmap.h new file mode 100644 index 0000000000000..5871f13aff831 --- /dev/null +++ b/include/kcl/backport/kcl_bitmap.h @@ -0,0 +1,34 @@ +/* + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef __KCL_BACKPORT_KCL_BITMAP_H_ +#define __KCL_BACKPORT_KCL_BITMAP_H_ + +#include +#include + +#ifndef HAVE_BITMAP_FUNCS +#define bitmap_alloc kcl_bitmap_alloc +#define bitmap_zalloc kcl_bitmap_zalloc +#define bitmap_free kcl_bitmap_free +#endif /* HAVE_BITMAP_FUNCS */ + +#endif /* KCL_BITMAP_H */ From 64811074511e43e2dc4a56581291f8f6fb8a3da1 Mon Sep 17 00:00:00 2001 From: David Yat Sin Date: Tue, 18 Jan 2022 02:06:39 -0500 Subject: [PATCH 0580/1868] drm/amdkcl: Fix for CAP_CHECKPOINT_RESTORE not defined Fix for CAP_CHECKPOINT_RESTORE not defined on kernels before 5.9 Reviewed-by: Flora Cui Reviewed-by: Felix Kuehling Signed-off-by: David Yat Sin --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_capability.h | 31 +++++++++++++++++++++++++ 2 files changed, 32 insertions(+) create mode 100644 include/kcl/kcl_capability.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 0bb5673cc401e..7f1ec2c474a53 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -81,5 +81,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_capability.h b/include/kcl/kcl_capability.h new file mode 100644 index 0000000000000..2cc984db5ac19 --- /dev/null +++ b/include/kcl/kcl_capability.h @@ -0,0 +1,31 @@ +/* + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#ifndef _KCL_KCL_CAPABILITY_H +#define _KCL_KCL_CAPABILITY_H + +#include + +#ifndef CAP_CHECKPOINT_RESTORE +#define CAP_CHECKPOINT_RESTORE CAP_SYS_ADMIN +#endif + +#endif From cf52b2105ee460f3b114ff59972d39672527ebf9 Mon Sep 17 00:00:00 2001 From: David Yat Sin Date: Tue, 18 Jan 2022 02:06:40 -0500 Subject: [PATCH 0581/1868] drm/amdkcl: fix for close_fd not defined Use ksys_close instead of close_fd on older kernels Reviewed-by: Flora Cui Reviewed-by: Felix Kuehling (rajneesh: removed new line EOF warning) Signed-off-by: Rajneesh Bhardwaj Signed-off-by: David Yat Sin --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/kfd-close-fd.m4 | 15 +++++++++++++++ include/kcl/kcl_fdtable.h | 10 ++++++++++ 5 files changed, 30 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/kfd-close-fd.m4 create mode 100644 include/kcl/kcl_fdtable.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 7f1ec2c474a53..c712af60c7345 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -82,5 +82,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index ab745ced8746c..54d03fda804e6 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1132,6 +1132,9 @@ /* kobj_type->default_groups is available */ #define HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE 1 +/* close_fd() is available */ +#define HAVE_KERNEL_CLOSE_FD 1 + /* Define to the address where bug reports for this package should be sent. */ #define PACKAGE_BUGREPORT "" diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index b7d4b5d0f3e1a..d251f744fe758 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -181,6 +181,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_BITMAP_FUNCS AC_AMDGPU_DRM_EDID_GET_MONITOR_NAME AC_AMDGPU_STRUCT_KOBJ_TYPE + AC_AMDGPU_CLOSE_FD AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/kfd-close-fd.m4 b/drivers/gpu/drm/amd/dkms/m4/kfd-close-fd.m4 new file mode 100644 index 0000000000000..59eb3c9632fdc --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/kfd-close-fd.m4 @@ -0,0 +1,15 @@ +dnl # +dnl # commit 8760c909f54a82aaa6e76da19afe798a0c77c3c3 +dnl # file: Rename __close_fd to close_fd and remove the files parameter +dnl # +AC_DEFUN([AC_AMDGPU_CLOSE_FD], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + close_fd(0); + ], [ + AC_DEFINE(HAVE_KERNEL_CLOSE_FD, 1, [close_fd() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_fdtable.h b/include/kcl/kcl_fdtable.h new file mode 100644 index 0000000000000..0a4b97605e146 --- /dev/null +++ b/include/kcl/kcl_fdtable.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _KCL_FDTABLE_H +#define _KCL_FDTABLE_H + +#ifndef HAVE_KERNEL_CLOSE_FD +#include +#define close_fd ksys_close +#endif + +#endif From 4ce99120bb972a062b9bb38873f20623a71d1bfa Mon Sep 17 00:00:00 2001 From: majun Date: Wed, 19 Jan 2022 19:28:44 +0800 Subject: [PATCH 0582/1868] amd/amdkcl: Fix the compile bug of ksys_close missing Fix the bug caused by ksys_close missing in some kernels. Reviewed-by: Flora Cui Signed-off-by: majun Change-Id: Ibc94fdac9392b642f1f748c1dacff076f524a8ce --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kfd-close-fd.m4 | 12 ++++++++++++ include/kcl/kcl_fdtable.h | 4 ++++ 3 files changed, 19 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 54d03fda804e6..6527a353d3005 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1135,6 +1135,9 @@ /* close_fd() is available */ #define HAVE_KERNEL_CLOSE_FD 1 +/* ksys_close() is available */ +#define HAVE_KSYS_CLOSE_FD 1 + /* Define to the address where bug reports for this package should be sent. */ #define PACKAGE_BUGREPORT "" diff --git a/drivers/gpu/drm/amd/dkms/m4/kfd-close-fd.m4 b/drivers/gpu/drm/amd/dkms/m4/kfd-close-fd.m4 index 59eb3c9632fdc..82b1e366bd09a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kfd-close-fd.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kfd-close-fd.m4 @@ -10,6 +10,18 @@ AC_DEFUN([AC_AMDGPU_CLOSE_FD], [ close_fd(0); ], [ AC_DEFINE(HAVE_KERNEL_CLOSE_FD, 1, [close_fd() is available]) + ], [ + dnl # + dnl # commit 16a78543a1d3537645de737934b9387c42bfb53b + dnl # drm/amdkcl: fix for close_fd not defined + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + ksys_close(0); + ], [ + AC_DEFINE(HAVE_KSYS_CLOSE_FD, 1, [ksys_fd() is available]) + ]) ]) ]) ]) diff --git a/include/kcl/kcl_fdtable.h b/include/kcl/kcl_fdtable.h index 0a4b97605e146..f6829418719c5 100644 --- a/include/kcl/kcl_fdtable.h +++ b/include/kcl/kcl_fdtable.h @@ -4,7 +4,11 @@ #ifndef HAVE_KERNEL_CLOSE_FD #include +#ifdef HAVE_KSYS_CLOSE_FD #define close_fd ksys_close +#else +#define close_fd sys_close +#endif #endif #endif From d8395c72a9fa9d6f35a98755f88f8385cb87f7d7 Mon Sep 17 00:00:00 2001 From: David Yat Sin Date: Wed, 19 Jan 2022 10:34:09 -0500 Subject: [PATCH 0583/1868] drm/amdkfd: Fix ipc_import_handle to use user_gpu_id Change kfd_ioctl_ipc_import_handle to use user_gpu_id. When a process is checkpointed and restored using CRIU on a different server, pdd->dev->id could be different on the restored server. So we use pdd->user_gpu_id as it remains the same throughout the life of kfd_process. Reviewed-by: Rajneesh Bhardwaj Signed-off-by: David Yat Sin --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index eebc124f11390..8d857c4e0c7f8 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1667,14 +1667,16 @@ static int kfd_ioctl_ipc_import_handle(struct file *filep, void *data) { struct kfd_ioctl_ipc_import_handle_args *args = data; - struct kfd_dev *dev = NULL; + struct kfd_process_device *pdd; int r; - dev = kfd_device_by_id(args->gpu_id); - if (!dev) + mutex_lock(&p->mutex); + pdd = kfd_process_device_data_by_id(p, args->gpu_id); + mutex_unlock(&p->mutex); + if (!pdd) return -EINVAL; - r = kfd_ipc_import_handle(dev, p, args->gpu_id, args->share_handle, + r = kfd_ipc_import_handle(pdd->dev, p, args->gpu_id, args->share_handle, args->va_addr, &args->handle, &args->mmap_offset, &args->flags); if (r) From bae2ac803d83e9e10e53c70ef472244c43265167 Mon Sep 17 00:00:00 2001 From: majun Date: Thu, 13 Jan 2022 14:33:45 +0800 Subject: [PATCH 0584/1868] amd/amdkcl: Fix the compile error caused by missing fucntions in fbdev Because the patch (drm/amdgpu: disable runpm if we are the primary adapter) introduced a new function is_firmware_frambuffer which implemented in drivers/video/fbdev. To avoid the dkms compile error, a new KCL function is added here. v5: - Print the function name in warning message. v4: - Remove the change point in kms v3:(based on Alex's suggestion) - Return false defaultly in is_firmware_framebuffer() - Check the amdgpu_runtime_pm for runpm setup v2: - Fix the typo - Remove the for-each-registered-fb.m4 - Remove the function prefix kcl - Checking the symbol instead of compiling. Signed-off-by: majun Change-Id: I8144b216df9318c95f8083ec3b1e86e00dbdb414 --- drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c | 9 +++++++++ .../gpu/drm/amd/dkms/m4/is-firmware-framebuffer.m4 | 13 +++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_fb.h | 5 +++++ 4 files changed, 28 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/is-firmware-framebuffer.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c b/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c index 18f2a20d821da..a4f4f80696c19 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c @@ -81,3 +81,12 @@ int remove_conflicting_pci_framebuffers(struct pci_dev *pdev, int res_id, const EXPORT_SYMBOL(remove_conflicting_pci_framebuffers); #endif + +#ifndef HAVE_IS_FIRMWARE_FRAMEBUFFER +bool is_firmware_framebuffer(struct apertures_struct *a) +{ + pr_warn_once("%s:enable the runtime pm\n", __func__); + return false; +} +EXPORT_SYMBOL(is_firmware_framebuffer); +#endif diff --git a/drivers/gpu/drm/amd/dkms/m4/is-firmware-framebuffer.m4 b/drivers/gpu/drm/amd/dkms/m4/is-firmware-framebuffer.m4 new file mode 100644 index 0000000000000..44d0db303a161 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/is-firmware-framebuffer.m4 @@ -0,0 +1,13 @@ +dnl # +dnl # commit a99952170b19db855b7b45fba8e263ddc5205a0c +dnl # drm/amdgpu: disable runpm if we are the primary adapter +dnl # + +AC_DEFUN([AC_AMDGPU_IS_FIRMWARE_FRAMEBUFFER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([is_firmware_framebuffer], [include/linux/fb.h], [ + AC_DEFINE(HAVE_IS_FIRMWARE_FRAMEBUFFER, 1, [is_firmware_framebuffer() is available]) + ],[ + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index d251f744fe758..2f983caacbc24 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -182,6 +182,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_EDID_GET_MONITOR_NAME AC_AMDGPU_STRUCT_KOBJ_TYPE AC_AMDGPU_CLOSE_FD + AC_AMDGPU_IS_FIRMWARE_FRAMEBUFFER AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_fb.h b/include/kcl/kcl_drm_fb.h index 2e66b7b2aa2fa..56361a8b43ebd 100644 --- a/include/kcl/kcl_drm_fb.h +++ b/include/kcl/kcl_drm_fb.h @@ -128,4 +128,9 @@ void drm_fb_helper_set_suspend_unlocked(struct drm_fb_helper *fb_helper, _kcl_drm_fb_helper_set_suspend_unlocked(fb_helper, suspend); } #endif + +#ifndef HAVE_IS_FIRMWARE_FRAMEBUFFER +extern bool is_firmware_framebuffer(struct apertures_struct *a); +#endif + #endif From bc6b1868f421d8e4551dd680ba1f533d80108022 Mon Sep 17 00:00:00 2001 From: Guchun Chen Date: Thu, 20 Jan 2022 14:59:05 +0800 Subject: [PATCH 0585/1868] drm/amdkcl: defer to enable generic FB setup by drm version >=5.15 This is workaround, and will be dropped when rooting cause it. Below are the collected failures from drm_fb_helper_damage_work on different kernels. In 5.13.0-27-generic kernel: amdgpu 0000:03:00.0: Damage blitter failed: ret=-22 In 5.13.0-22-generic: BUG: unable to handle page fault for address: 0000000100000008 Signed-off-by: Guchun Chen Reviewed-by: Leslie Shi --- include/kcl/backport/kcl_drm_fb.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/kcl/backport/kcl_drm_fb.h b/include/kcl/backport/kcl_drm_fb.h index 2d165e481704b..87df9c35328f4 100644 --- a/include/kcl/backport/kcl_drm_fb.h +++ b/include/kcl/backport/kcl_drm_fb.h @@ -44,7 +44,7 @@ void _kcl_drm_helper_mode_fill_fb_struct(struct drm_device *dev, #if defined(HAVE_DRM_FBDEV_GENERIC_SETUP) && \ defined(HAVE_DRM_DEVICE_FB_HELPER) && \ - DRM_VERSION_CODE >= DRM_VERSION(5, 13, 0) + DRM_VERSION_CODE >= DRM_VERSION(5, 15, 0) #define AMDKCL_DRM_FBDEV_GENERIC #endif From 97ef6b2c59716486edc51802776ad51fbe42734f Mon Sep 17 00:00:00 2001 From: Nikola Prica Date: Tue, 18 Jan 2022 20:31:16 +0100 Subject: [PATCH 0586/1868] amd/amdkcl: fix ddrv->release check for legacy kernels Fix following error that is detected on Centos 3.10 kernel drm_drv.h:500:12: error: 'struct vm_area_struct' declared inside parameter list Signed-off-by: Nikola Prica Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/m4/drm-driver-release.m4 | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-driver-release.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-driver-release.m4 index 05801784c5188..8d844a5d7124c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-driver-release.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-driver-release.m4 @@ -5,6 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DRIVER_RELEASE], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ + struct vm_area_struct; #ifdef HAVE_DRM_DRM_DRV_H #include #else From cc396a1a1216c64534faf3e313069470c2df5213 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 11 Oct 2023 16:49:29 +0800 Subject: [PATCH 0587/1868] drm/amdkcl: Resolve build issue with kcl_amdgpu_get_vblank_time_ns Fix incompatible pointer type passed as argument 1 of 'drm_crtc_vblank_count_and_time'. Access time field of drm_vblank_crtc structure depending on the field type, defined by HAVE_DRM_VBLANK_USE_KTIME_T or HAVE_DRM_VBLANK_CRTC_HAS_ARRAY_TIME_FIELD. v2: merge tests for drm_vblank_crtc->time, drop checking if drm_vblank_struct exists and fix test for checking if time is array based on test on centos7.3 v3: switch HAVE_DRM_VBLANK_USE_KTIME_T to be tested first and unset HAVE_DRM_VBLANK_CRTC_HAS_ARRAY_TIME_FIELD Signed-off-by: Danijel Slivka Reviewed-by: Flora Cui Signed-off-by: Asher Song --- .../drm/amd/backport/include/kcl/kcl_amdgpu.h | 12 ++--------- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../m4/drm_vblank_use_ktime_t_time_field.m4 | 20 ------------------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - 4 files changed, 5 insertions(+), 31 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_vblank_use_ktime_t_time_field.m4 diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h index fc2eecd49d62b..9b26a06085c84 100644 --- a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h @@ -89,17 +89,9 @@ static inline int kcl_amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, un #endif /* HAVE_DRM_DRIVER_GET_VBLANK_TIMESTAMP_USE_KTIMER_T_ARG */ #endif /* HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP */ -#if defined(HAVE_DRM_VBLANK_USE_KTIME_T) -static inline ktime_t kcl_amdgpu_get_vblank_time_ns(struct drm_vblank_crtc *vblank) { +static inline ktime_t kcl_amdgpu_get_vblank_time_ns(struct drm_vblank_crtc *vblank) +{ return vblank->time; } -#else -static inline ktime_t kcl_amdgpu_get_vblank_time_ns(struct drm_vblank_crtc *vblank) { - struct timeval tv; - drm_crtc_vblank_count_and_time(vblank, &tv); - return timeval_to_ktime(tv); -} -#endif /* HAVE_DRM_VBLANK_USE_KTIME_T */ - #endif /* AMDGPU_BACKPORT_KCL_AMDGPU_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 6527a353d3005..a81d3ace44f4a 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -383,6 +383,9 @@ /* drm_vblank struct use ktime_t for time field */ #define HAVE_DRM_VBLANK_USE_KTIME_T 1 +/* drm_vblank->time is array */ +/* #undef HAVE_DRM_VBLANK_CRTC_HAS_ARRAY_TIME_FIELD */ + /* drm_driver->release() is available */ #define HAVE_DRM_DRIVER_RELEASE 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_vblank_use_ktime_t_time_field.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_vblank_use_ktime_t_time_field.m4 deleted file mode 100644 index b846cb2f57a41..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm_vblank_use_ktime_t_time_field.m4 +++ /dev/null @@ -1,20 +0,0 @@ -dnl # -dnl # commit v4.14-rc3-721-g67680d3c0464 dnl # drm: vblank: use ktime_t instead of timeval -AC_DEFUN([AC_AMDGPU_DRM_VBLANK_USE_KTIME_T], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DRMP_H - #include - #else - #include - #endif - #include - ], [ - struct drm_vblank_crtc *vblank = NULL; - vblank->time = ns_to_ktime(0); - ], [ - AC_DEFINE(HAVE_DRM_VBLANK_USE_KTIME_T, 1, - [drm_vblank->time uses ktime_t type]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 2f983caacbc24..dcc6dc2ff2817 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -168,7 +168,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DEV_ENTER AC_AMDGPU_DRM_DEV_IS_UNPLUGGED AC_AMDGPU_DRM_DEVICE_PDEV - AC_AMDGPU_DRM_VBLANK_USE_KTIME_T AC_AMDGPU_DRM_CONNECTOR_SET_PANEL_ORIENTATION_WITH_QUIRK AC_AMDGPU_GET_MM_EXE_FILE AC_AMDGPU_DRM_SIMPLE_ENCODER_INIT From 01b51cae025802d9739e532a1cfaca65e4dc9cf0 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 27 Jan 2022 19:38:00 +0800 Subject: [PATCH 0588/1868] drm/amdkcl: fix macro name error Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c index f91a4d60ffd11..c81b1cadf0099 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: MIT -#ifndef HAVE_DRM_APERTURE_H +#ifndef HAVE_DRM_DRM_APERTURE_H #include #include From 5dc0454aaa49bed9ebaa3b678de0c2bdd0962b01 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 27 Jan 2022 19:42:09 +0800 Subject: [PATCH 0589/1868] drm/amdkcl: no need to export remove_conflicting_pci_framebuffers it's not used by amdgpu Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c b/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c index a4f4f80696c19..742edcc32b042 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c @@ -79,7 +79,6 @@ int remove_conflicting_pci_framebuffers(struct pci_dev *pdev, int res_id, const } #endif /* HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_NO_RES_ID_ARG */ -EXPORT_SYMBOL(remove_conflicting_pci_framebuffers); #endif #ifndef HAVE_IS_FIRMWARE_FRAMEBUFFER From 5034e6e9e55342439981a2d158a730c37829443f Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 21 Jan 2022 16:00:32 +0800 Subject: [PATCH 0590/1868] drm/amdkcl: fix test for bitmap_xxx api Signed-off-by: Flora Cui Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/m4/drm-bitmap-functions.m4 | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-bitmap-functions.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-bitmap-functions.m4 index b91abf96c4598..c5a71aac5af1e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-bitmap-functions.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-bitmap-functions.m4 @@ -9,8 +9,8 @@ AC_DEFUN([AC_AMDGPU_DRM_BITMAP_FUNCS], [ #include ],[ bitmap_free(NULL); - bitmap_alloc(NULL); - bitmap_zalloc(NULL); + bitmap_alloc(0, 0); + bitmap_zalloc(0, 0); ],[ AC_DEFINE(HAVE_BITMAP_FUNCS, 1, From d00af90ef50aa1bf91c211ac1f1560b2bc2c0f67 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 21 Jan 2022 14:01:56 +0800 Subject: [PATCH 0591/1868] drm/amdkcl: include drm_ttm_helper.ko into dkms package Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/files | 2 +- drivers/gpu/drm/amd/dkms/Makefile | 8 ++++++++ drivers/gpu/drm/amd/dkms/dkms.conf | 4 ++++ drivers/gpu/drm/amd/dkms/sources | 2 ++ 4 files changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkcl/files b/drivers/gpu/drm/amd/amdkcl/files index a5a39207c730e..6cc9587ebc525 100644 --- a/drivers/gpu/drm/amd/amdkcl/files +++ b/drivers/gpu/drm/amd/amdkcl/files @@ -1 +1 @@ -FILES="ttm/*.c scheduler/*.c amd/amdkcl/dma-buf/dma-resv.c" +FILES="ttm/*.c scheduler/*.c amd/amdkcl/dma-buf/dma-resv.c drm_gem_ttm_helper.c" diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 340258b04f0aa..e7b791c8195f0 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -186,4 +186,12 @@ subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN3_x endif endif +export CONFIG_DRM_TTM_HELPER=m +subdir-ccflags-y += -DCONFIG_DRM_TTM_HELPER +CFLAGS_drm_gem_ttm_helper.o += -include $(src)/ttm/backport/backport.h \ + -include $(src)/include/kcl/backport/kcl_drm_gem.h \ + -DHAVE_CONFIG_H +amddrm_ttm_helper-y := drm_gem_ttm_helper.o +obj-$(CONFIG_DRM_TTM_HELPER) += amddrm_ttm_helper.o + obj-m += scheduler/ amd/amdgpu/ ttm/ amd/amdkcl/ diff --git a/drivers/gpu/drm/amd/dkms/dkms.conf b/drivers/gpu/drm/amd/dkms/dkms.conf index 146f1b4db6148..bd79232132f60 100644 --- a/drivers/gpu/drm/amd/dkms/dkms.conf +++ b/drivers/gpu/drm/amd/dkms/dkms.conf @@ -22,6 +22,10 @@ BUILT_MODULE_NAME[3]="amd-sched" BUILT_MODULE_LOCATION[3]="scheduler" DEST_MODULE_LOCATION[3]="/kernel/drivers/gpu/drm/scheduler" +BUILT_MODULE_NAME[4]="amddrm_ttm_helper" +BUILT_MODULE_LOCATION[4]="." +DEST_MODULE_LOCATION[4]="/kernel/drivers/gpu/drm" + # Find out how many CPU cores can be use if we pass appropriate -j option to make. # DKMS could use all cores on multicore systems to build the kernel module. num_cpu_cores() diff --git a/drivers/gpu/drm/amd/dkms/sources b/drivers/gpu/drm/amd/dkms/sources index da9e9612a23fb..60563cf6abf8e 100644 --- a/drivers/gpu/drm/amd/dkms/sources +++ b/drivers/gpu/drm/amd/dkms/sources @@ -29,3 +29,5 @@ drivers/dma-buf/dma-resv.c amd/amdkcl/dma-buf/ include/linux/dma-resv.h include/linux/ include/kcl/reservation.h include/linux/ include/uapi/linux/kfd_sysfs.h include/uapi/linux/ +drivers/gpu/drm/drm_gem_ttm_helper.c . +include/drm/drm_gem_ttm_helper.h include/drm/ From 0b0291e18a6afa70fdeac1dcfdaad2052c4f85b1 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 25 Jan 2022 10:24:15 +0800 Subject: [PATCH 0592/1868] drm/amdkcl: add kcl copy of drm_printf_indent Signed-off-by: Flora Cui --- include/kcl/kcl_drm_print.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index 6dea17070b5de..3c4e6b62a6e15 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -159,4 +159,10 @@ static inline bool drm_debug_enabled(unsigned int category) } #endif /* HAVE_DRM_DEBUG_ENABLED */ +/* Copied from v4.14-rc3-610-gbf6234a294c5 include/drm/drm_print.h */ +#ifndef drm_printf_indent +#define drm_printf_indent(printer, indent, fmt, ...) \ + drm_printf((printer), "%.*s" fmt, (indent), "\t\t\t\t\tX", ##__VA_ARGS__) +#endif + #endif From 14059436aa4a8280d586818d0f82ee1b95f17271 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 25 Jan 2022 11:44:18 +0800 Subject: [PATCH 0593/1868] drm/amdkcl: add kcl copy drm_print_bits Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c | 25 +++++++++ drivers/gpu/drm/amd/backport/backport.h | 2 +- drivers/gpu/drm/amd/dkms/config/config.h | 6 +++ drivers/gpu/drm/amd/dkms/m4/drm_print_bits.m4 | 26 ++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/scheduler/backport/backport.h | 2 +- drivers/gpu/drm/ttm/backport/backport.h | 2 +- include/kcl/backport/kcl_drm_print.h | 51 +++++++++++++++++++ include/kcl/kcl_drm_print.h | 5 ++ 9 files changed, 117 insertions(+), 3 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_print_bits.m4 create mode 100644 include/kcl/backport/kcl_drm_print.h diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c index b5d9e1a9113a3..907a902c5f204 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c @@ -23,6 +23,7 @@ * Rob Clark */ #include +#include #include #if !defined(HAVE_DRM_DRM_PRINT_H) @@ -102,3 +103,27 @@ void kcl_drm_err(const char *format, ...) EXPORT_SYMBOL(kcl_drm_err); #endif + +#ifndef HAVE_DRM_PRINT_BITS +/* Copied from v5.3-rc1-684-g141f6357f45c drivers/gpu/drm/drm_print.c */ +void drm_print_bits(struct drm_printer *p, unsigned long value, + const char * const bits[], unsigned int nbits) +{ + bool first = true; + unsigned int i; + + if (WARN_ON_ONCE(nbits > BITS_PER_TYPE(value))) + nbits = BITS_PER_TYPE(value); + + for_each_set_bit(i, &value, nbits) { + if (WARN_ON_ONCE(!bits[i])) + continue; + drm_printf(p, "%s%s", first ? "" : ",", + bits[i]); + first = false; + } + if (first) + drm_printf(p, "(none)"); +} +EXPORT_SYMBOL(drm_print_bits); +#endif diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index c712af60c7345..9cad31b0f38d7 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -45,7 +45,7 @@ #endif #include #include -#include +#include #include #include #include diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index a81d3ace44f4a..562d9d6485769 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -626,6 +626,12 @@ /* drm_printer->prefix is available */ #define HAVE_DRM_PRINTER_PREFIX 1 +/* drm_print_bits() is available */ +#define HAVE_DRM_PRINT_BITS 1 + +/* drm_print_bits() has 4 args */ +#define HAVE_DRM_PRINT_BITS_4ARGS 1 + /* drm_simple_encoder is available */ #define HAVE_DRM_SIMPLE_ENCODER_INIT 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_print_bits.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_print_bits.m4 new file mode 100644 index 0000000000000..62209f24b90e0 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_print_bits.m4 @@ -0,0 +1,26 @@ +dnl # +dnl # v5.3-rc1-684-g141f6357f45c +dnl # drm: tweak drm_print_bits() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_PRINT_BITS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_print_bits(NULL, 0, NULL, 0); + ], [ + AC_DEFINE(HAVE_DRM_PRINT_BITS_4ARGS, 1, + [drm_print_bits() has 4 args]) + AC_DEFINE(HAVE_DRM_PRINT_BITS, 1, + [drm_print_bits() is available]) + ], [ + dnl # v5.3-rc1-622-g2dc5d44ccc5e + dnl # drm: add drm_print_bits + AC_KERNEL_CHECK_SYMBOL_EXPORT([drm_print_bits], + [drivers/gpu/drm/drm_print.c], [ + AC_DEFINE(HAVE_DRM_PRINT_BITS, 1, + [drm_print_bits() is available]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index dcc6dc2ff2817..ee177078ff935 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -83,6 +83,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DRIVER_GEM_PRIME_RES_OBJ AC_AMDGPU_DRM_DRV_GEM_PRIME_EXPORT AC_AMDGPU_DRM_PRINTER + AC_AMDGPU_DRM_PRINT_BITS AC_AMDGPU_DRM_MM_INSERT_MODE AC_AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES AC_AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL diff --git a/drivers/gpu/drm/scheduler/backport/backport.h b/drivers/gpu/drm/scheduler/backport/backport.h index 690cfe2fbe358..25460de490b35 100644 --- a/drivers/gpu/drm/scheduler/backport/backport.h +++ b/drivers/gpu/drm/scheduler/backport/backport.h @@ -6,7 +6,7 @@ #include #include #include -#include +#include #include #endif diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index 97ee04f8c9330..21badd8cad2e9 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -13,7 +13,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/include/kcl/backport/kcl_drm_print.h b/include/kcl/backport/kcl_drm_print.h new file mode 100644 index 0000000000000..379308c2563d4 --- /dev/null +++ b/include/kcl/backport/kcl_drm_print.h @@ -0,0 +1,51 @@ +/* + * Copyright (C) 2016 Red Hat + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + * Authors: + * Rob Clark + */ + + +// Copied from include/drm/drm_print.h +#ifndef _KCL_BACKPORT_KCL__DRM_PRINT_H__H_ +#define _KCL_BACKPORT_KCL__DRM_PRINT_H__H_ + +#include +#include + +#if !defined(HAVE_DRM_PRINT_BITS_4ARGS) && \ + defined(HAVE_DRM_PRINT_BITS) +static inline +void _kcl_drm_print_bits(struct drm_printer *p, unsigned long value, + const char * const bits[], unsigned int nbits) +{ + unsigned int from, to; + + from = ffs(value); + to = fls(value); + WARN_ON_ONCE(to > nbits); + + drm_print_bits(p, value, bits, from, nbits); +} +#define drm_print_bits _kcl_drm_print_bits +#endif + +#endif diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index 3c4e6b62a6e15..d92e4744fea4b 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -165,4 +165,9 @@ static inline bool drm_debug_enabled(unsigned int category) drm_printf((printer), "%.*s" fmt, (indent), "\t\t\t\t\tX", ##__VA_ARGS__) #endif +#ifndef HAVE_DRM_PRINT_BITS +void drm_print_bits(struct drm_printer *p, unsigned long value, + const char * const bits[], unsigned int nbits); +#endif + #endif From ba04d19d7117ffdf59cacafac4ce6c78fbbfe548 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 26 Jan 2022 17:04:10 +0800 Subject: [PATCH 0594/1868] drm/amdkcl: rework kcl stuff for drm_ttm_helper.ko Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 4 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 5 +++ .../include/kcl/kcl_drm_gem_ttm_helper.h | 33 +++---------------- .../drm/amd/backport/kcl_drm_gem_ttm_helper.c | 30 ++--------------- drivers/gpu/drm/amd/dkms/config/config.h | 9 ++--- .../amd/dkms/m4/drm-driver-gem-open-object.m4 | 33 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 7 ---- .../drm/amd/dkms/m4/drm_gem_object_funcs.m4 | 28 ---------------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 +- include/kcl/header/drm/drm_gem_ttm_helper.h | 9 ----- 10 files changed, 51 insertions(+), 109 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-open-object.m4 delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_gem_object_funcs.m4 delete mode 100644 include/kcl/header/drm/drm_gem_ttm_helper.h diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index a993b0486740b..a17b251cade3f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3089,8 +3089,8 @@ static struct drm_driver amdgpu_kms_driver = { #endif #ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK - .gem_prime_vmap = drm_gem_ttm_vmap, - .gem_prime_vunmap = drm_gem_ttm_vunmap, + .gem_prime_vmap = amdgpu_gem_prime_vmap, + .gem_prime_vunmap = amdgpu_gem_prime_vunmap, #endif .gem_prime_mmap = amdkcl_drm_gem_prime_mmap, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index fae8bd35d6229..bb946c9568d7a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -363,8 +363,13 @@ static const struct drm_gem_object_funcs amdgpu_gem_object_funcs = { .open = amdgpu_gem_object_open, .close = amdgpu_gem_object_close, .export = amdgpu_gem_prime_export, +#ifdef HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_2ARGS .vmap = drm_gem_ttm_vmap, .vunmap = drm_gem_ttm_vunmap, +#else + .vmap = amdgpu_gem_prime_vmap, + .vunmap = amdgpu_gem_prime_vunmap, +#endif .mmap = amdgpu_gem_object_mmap, .vm_ops = &amdgpu_gem_vm_ops, }; diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_gem_ttm_helper.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_gem_ttm_helper.h index e9d8d3fd9d9d8..ae25af4cbc8c5 100644 --- a/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_gem_ttm_helper.h +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_gem_ttm_helper.h @@ -1,29 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -/* Copied from include/drm/drm_gem_ttm_helper.h */ - #ifndef _KCL_KCL_DRM_GEM_TTM_HELPER_H_H #define _KCL_KCL_DRM_GEM_TTM_HELPER_H_H #include +#include -#ifndef HAVE_DRM_GEM_TTM_VMAP -void _kcl_drm_gem_ttm_vunmap(struct drm_gem_object *gem, +#ifndef HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_2ARGS +void amdgpu_gem_prime_vunmap(struct drm_gem_object *gem, void *vaddr); - -void *_kcl_drm_gem_ttm_vmap(struct drm_gem_object *obj); - -static inline -void drm_gem_ttm_vunmap(struct drm_gem_object *gem, - void *vaddr) -{ - _kcl_drm_gem_ttm_vunmap(gem, vaddr); -} - -static inline -void *drm_gem_ttm_vmap(struct drm_gem_object *obj) -{ - return _kcl_drm_gem_ttm_vmap(obj); -} +void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj); #endif #ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK @@ -34,14 +19,4 @@ void amdgpu_gem_object_close(struct drm_gem_object *obj, struct drm_file *file_priv); #endif -#ifndef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK -int _kcl_drm_gem_ttm_mmap(struct drm_gem_object *gem, - struct vm_area_struct *vma); -static inline -int drm_gem_ttm_mmap(struct drm_gem_object *gem, - struct vm_area_struct *vma) { - return _kcl_drm_gem_ttm_mmap(gem, vma); -} -#endif - #endif diff --git a/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c b/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c index b5fb22fa5a50a..2cef03209d156 100644 --- a/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c +++ b/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c @@ -14,8 +14,8 @@ container_of(gem_obj, struct ttm_buffer_object, base) #endif -#ifndef HAVE_DRM_GEM_TTM_VMAP -void *_kcl_drm_gem_ttm_vmap(struct drm_gem_object *obj) +#ifndef HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_2ARGS +void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj) { struct ttm_buffer_object *bo = drm_gem_ttm_of_gem(obj); struct dma_buf_map map; @@ -23,9 +23,8 @@ void *_kcl_drm_gem_ttm_vmap(struct drm_gem_object *obj) ttm_bo_vmap(bo, &map); return map.vaddr; } -EXPORT_SYMBOL(_kcl_drm_gem_ttm_vmap); -void _kcl_drm_gem_ttm_vunmap(struct drm_gem_object *gem, +void amdgpu_gem_prime_vunmap(struct drm_gem_object *gem, void *vaddr) { struct ttm_buffer_object *bo = drm_gem_ttm_of_gem(gem); @@ -36,27 +35,4 @@ void _kcl_drm_gem_ttm_vunmap(struct drm_gem_object *gem, ttm_bo_vunmap(bo, &map); } -EXPORT_SYMBOL(_kcl_drm_gem_ttm_vunmap); -#endif - -#ifndef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK -int _kcl_drm_gem_ttm_mmap(struct drm_gem_object *gem, - struct vm_area_struct *vma) { - - struct ttm_buffer_object *bo = drm_gem_ttm_of_gem(gem); - int ret; - - ret = ttm_bo_mmap_obj(vma, bo); - if (ret < 0) - return ret; - - /* - * ttm has its own object refcounting, so drop gem reference - * to avoid double accounting counting. - */ - drm_gem_object_put(gem); - - return 0; -} -EXPORT_SYMBOL(_kcl_drm_gem_ttm_mmap); #endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 562d9d6485769..ea50bc19e2532 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -429,9 +429,6 @@ */ #define HAVE_DRM_DRM_GEM_FRAMEBUFFER_HELPER_H 1 -/* Define to 1 if you have the header file. */ -#define HAVE_DRM_DRM_GEM_TTM_HELPER_H 1 - /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_HDCP_H 1 @@ -517,6 +514,9 @@ /* drm_gem_map_attach() wants 2 arguments */ /* #undef HAVE_DRM_GEM_MAP_ATTACH_2ARGS */ +/* drm_gem_object_funcs->vmap() has 2 args */ +#define HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_2ARGS 1 + /* drm_gem_object_lookup() wants 2 args */ #define HAVE_DRM_GEM_OBJECT_LOOKUP_2ARGS 1 @@ -529,9 +529,6 @@ /* ttm_buffer_object->base is available */ #define HAVE_DRM_GEM_OBJECT_RESV 1 -/* drm_gem_ttm_vmap() is available */ -#define HAVE_DRM_GEM_TTM_VMAP 1 - /* drm_gen_fb_init_with_funcs() is available */ #define HAVE_DRM_GEN_FB_INIT_WITH_FUNCS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-open-object.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-open-object.m4 new file mode 100644 index 0000000000000..cb583a5e9dafd --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-open-object.m4 @@ -0,0 +1,33 @@ +AC_DEFUN([AC_AMDGPU_DRM_DRIVER_GEM_OPEN_OBJECT], [ + AC_KERNEL_DO_BACKGROUND([ + dnl # + dnl # commit v5.10-rc2-329-g49a3f51dfeee + dnl # drm/gem: Use struct dma_buf_map in GEM vmap ops and convert GEM backends + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_gem_object_funcs *funcs = NULL; + funcs->vmap(NULL, NULL); + ], [ + AC_DEFINE(HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_2ARGS, 1, [drm_gem_object_funcs->vmap() has 2 args]) + ],[ + dnl # commit v5.9-rc5-1077-gd693def4fd1c + dnl # drm: Remove obsolete GEM and PRIME callbacks from struct drm_driver + AC_KERNEL_TRY_COMPILE([ + struct vm_area_struct; + #ifdef HAVE_DRM_DRMP_H + #include + #else + #include + #endif + ],[ + struct drm_driver *drv = NULL; + drv->gem_open_object = NULL; + ],[ + AC_DEFINE(HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK, 1, + [drm_gem_open_object is defined in struct drm_drv]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index 05687ebbd1ec7..b3b69a3e8dea7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -39,13 +39,6 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # AC_KERNEL_CHECK_HEADERS([drm/drm_managed.h]) - dnl # - dnl # v5.3-rc1-623-gff540b76f14a - dnl # drm/ttm: add drm gem ttm helpers, - dnl # starting with drm_gem_ttm_print_info() - dnl # - AC_KERNEL_CHECK_HEADERS([drm/drm_gem_ttm_helper.h]) - dnl # dnl # Required by AC_KERNEL_SUPPORTED_AMD_CHIPS macro dnl # diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_gem_object_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_gem_object_funcs.m4 deleted file mode 100644 index 353a678db52d7..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm_gem_object_funcs.m4 +++ /dev/null @@ -1,28 +0,0 @@ -dnl # -dnl # commit v4.9-rc8-1739-g6d1b81d8e25d -dnl # drm: add crtc helper drm_crtc_from_index() -dnl # commit v5.9-rc5-1077-gd693def4fd1c -dnl # drm: Remove obsolete GEM and PRIME callbacks from struct drm_driver -dnl # -AC_DEFUN([AC_AMDGPU_DRM_GEM_TTM_VMAP], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([drm_gem_ttm_vmap], [drivers/gpu/drm/drm_gem_ttm_helper.c], [ - AC_DEFINE(HAVE_DRM_GEM_TTM_VMAP, 1, [drm_gem_ttm_vmap() is available]) - ],[ - AC_KERNEL_TRY_COMPILE([ - struct vm_area_struct; - #ifdef HAVE_DRM_DRMP_H - #include - #else - #include - #endif - ],[ - struct drm_driver *drv = NULL; - drv->gem_open_object = NULL; - ],[ - AC_DEFINE(HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK, 1, - [drm_gem_open_object is defined in struct drm_drv]) - ]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index ee177078ff935..b418f5b1033a8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -139,7 +139,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_PRIME_PAGES_TO_SG AC_AMDGPU_DRM_CRTC_HELPER_FUNCS AC_AMDGPU_DEBUGFS_CREATE_FILE_SIZE - AC_AMDGPU_DRM_GEM_TTM_VMAP + AC_AMDGPU_DRM_DRIVER_GEM_OPEN_OBJECT AC_AMDGPU_FS_RECLAIM_ACQUIRE AC_AMDGPU_MEMALLOC_NORECLAIM_SAVE AC_AMDGPU_PM_SUSPEND_VIA_FIRMWARE diff --git a/include/kcl/header/drm/drm_gem_ttm_helper.h b/include/kcl/header/drm/drm_gem_ttm_helper.h deleted file mode 100644 index 5612902e4958d..0000000000000 --- a/include/kcl/header/drm/drm_gem_ttm_helper.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -#ifndef _KCL_HEADER_DRM_GEM_TTM_HELPER_H_H_ -#define _KCL_HEADER_DRM_GEM_TTM_HELPER_H_H_ - -#ifdef HAVE_DRM_DRM_GEM_TTM_HELPER_H -#include_next -#endif - -#endif From 9e96c4856b531273b2394d3c7b72ca3c704da58e Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 21 Jan 2022 15:29:52 +0800 Subject: [PATCH 0595/1868] drm/amdkcl: drop trict restriction for drm_fbdev_generic_setup Signed-off-by: Flora Cui --- include/kcl/backport/kcl_drm_fb.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/include/kcl/backport/kcl_drm_fb.h b/include/kcl/backport/kcl_drm_fb.h index 87df9c35328f4..662d312577d93 100644 --- a/include/kcl/backport/kcl_drm_fb.h +++ b/include/kcl/backport/kcl_drm_fb.h @@ -43,8 +43,7 @@ void _kcl_drm_helper_mode_fill_fb_struct(struct drm_device *dev, #endif #if defined(HAVE_DRM_FBDEV_GENERIC_SETUP) && \ - defined(HAVE_DRM_DEVICE_FB_HELPER) && \ - DRM_VERSION_CODE >= DRM_VERSION(5, 15, 0) + defined(HAVE_DRM_DEVICE_FB_HELPER) #define AMDKCL_DRM_FBDEV_GENERIC #endif From fc924619d2d4982447e71409804077be5112d7c6 Mon Sep 17 00:00:00 2001 From: Rajneesh Bhardwaj Date: Mon, 31 Jan 2022 22:10:31 -0500 Subject: [PATCH 0596/1868] drm/amdkfd: CRIU Update attributes during resume KFD_IOCTL_SVM_ATTR_CLR_FLAGS is not available for querying via get_attr interface but we must clear the flags during restore as there might be some default flags set when the prange is created. Also fix for invalid PREFETCH atribute values saved during checkpoint by replacing them with another dummy KFD_IOCTL_SVM_ATTR_SET_FLAGS attribute. Change-Id: Ibbe573ac5d7cffee80e08668d829b46f6b6aa688 Reviewed-by: Felix Kuehling Signed-off-by: Rajneesh Bhardwaj --- drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c index 229da4a0283d0..d41e0a247aeab 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c @@ -3927,6 +3927,24 @@ int kfd_criu_resume_svm(struct kfd_process *p) set_attr[num_attrs].type = KFD_IOCTL_SVM_ATTR_CLR_FLAGS; set_attr[num_attrs].value = ~set_flags; + /* CLR_FLAGS is not available via get_attr during checkpoint but + * it needs to be inserted before restoring the ranges so + * allocate extra space for it before calling set_attr + */ + set_attr_size = sizeof(struct kfd_ioctl_svm_attribute) * + (num_attrs + 1); + set_attr = krealloc(set_attr, set_attr_size, + GFP_KERNEL); + if (!set_attr) { + ret = -ENOMEM; + goto exit; + } + + memcpy(set_attr, criu_svm_md->data.attrs, num_attrs * + sizeof(struct kfd_ioctl_svm_attribute)); + set_attr[num_attrs].type = KFD_IOCTL_SVM_ATTR_CLR_FLAGS; + set_attr[num_attrs].value = ~set_flags; + ret = svm_range_set_attr(p, mm, criu_svm_md->data.start_addr, criu_svm_md->data.size, num_attrs + 1, set_attr); From c35a997a9b5ef4aa9eb975809f97d0caa5cae07f Mon Sep 17 00:00:00 2001 From: majun Date: Fri, 28 Jan 2022 11:53:21 +0800 Subject: [PATCH 0597/1868] drm/amdkcl: Check if pm_suspend_target_state is defined Fixed the compile error caused by pm_suspend_target_state which is not defined in some legacy kernel versions. v3: - Fix the wrong return value v2: - Modify the patch subject - Fix the return value for APU Signed-off-by: majun Change-Id: Idc26e7045132b61130d9cc9e555729c85ae238b6 --- drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 8 ++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../drm/amd/dkms/m4/pm_suspend_target_state.m4 | 17 +++++++++++++++++ 3 files changed, 28 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/pm_suspend_target_state.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c index f85ace0384d21..36de0c9788bbf 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c @@ -1478,8 +1478,12 @@ void amdgpu_acpi_release(void) */ bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { +#ifdef HAVE_PM_SUSPEND_TARGET_STATE return !(adev->flags & AMD_IS_APU) || (pm_suspend_target_state == PM_SUSPEND_MEM); +#else + return true; +#endif } /** @@ -1491,9 +1495,13 @@ bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) */ bool amdgpu_acpi_is_s0ix_active(struct amdgpu_device *adev) { +#ifdef HAVE_PM_SUSPEND_TARGET_STATE if (!(adev->flags & AMD_IS_APU) || (pm_suspend_target_state != PM_SUSPEND_TO_IDLE)) return false; +#else + return false; +#endif if (adev->asic_type < CHIP_RAVEN) return false; diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index ea50bc19e2532..7849687698bd9 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1144,6 +1144,9 @@ /* ksys_close() is available */ #define HAVE_KSYS_CLOSE_FD 1 +/* pm_suspend_target_state is available */ +#define HAVE_PM_SUSPEND_TARGET_STATE 1 + /* Define to the address where bug reports for this package should be sent. */ #define PACKAGE_BUGREPORT "" diff --git a/drivers/gpu/drm/amd/dkms/m4/pm_suspend_target_state.m4 b/drivers/gpu/drm/amd/dkms/m4/pm_suspend_target_state.m4 new file mode 100644 index 0000000000000..7f4394902241d --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pm_suspend_target_state.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit edf3ad32f18b0ea7d27ea9420f3bb9b2c850b48b +dnl # drm/amd: Warn users about potential s0ix problems +dnl # +AC_DEFUN([AC_AMDGPU_PM_SUSPEND_TARGET_STATE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + pm_suspend_target_state = PM_SUSPEND_TO_IDLE; + ],[ + AC_DEFINE(HAVE_PM_SUSPEND_TARGET_STATE, + 1, + [pm_suspend_target_state is available]) + ]) + ]) +]) From bd734a59cf63c78c58ed1a9597869e56dfc3c033 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 6 Jan 2022 10:45:13 +0800 Subject: [PATCH 0598/1868] drm/amdkcl: update config.h Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 7849687698bd9..a589a6f1f9f80 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -49,6 +49,9 @@ /* backlight_device_set_brightness() is available */ #define HAVE_BACKLIGHT_DEVICE_SET_BRIGHTNESS 1 +/* bitmap_free() is available */ +#define HAVE_BITMAP_FUNCS 1 + /* whether CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL is defined */ #define HAVE_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL 1 @@ -287,15 +290,15 @@ /* display_info->hdmi.scdc.scrambling are available */ #define HAVE_DRM_DISPLAY_INFO_HDMI_SCDC_SCRAMBLING 1 +/* display_info->is_hdmi is available */ +#define HAVE_DRM_DISPLAY_INFO_IS_HDMI 1 + /* display_info->max_tmds_clock is available */ #define HAVE_DRM_DISPLAY_INFO_MAX_TMDS_CLOCK 1 /* struct drm_display_info has monitor_range member */ #define HAVE_DRM_DISPLAY_INFO_MONITOR_RANGE 1 -/* display_info->is_hdmi is available */ -#define HAVE_DRM_DISPLAY_INFO_IS_HDMI 1 - /* drm_dp_atomic_find_vcpi_slots() is available */ #define HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS 1 @@ -436,7 +439,7 @@ #define HAVE_DRM_DRM_IOCTL_H 1 /* Define to 1 if you have the header file. */ -#define HAVE_DRM_DRM_IRQ_H 1 +/* #undef HAVE_DRM_DRM_IRQ_H */ /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_MANAGED_H 1 @@ -659,6 +662,9 @@ /* drm_universal_plane_init() wants 9 args */ #define HAVE_DRM_UNIVERSAL_PLANE_INIT_9ARGS 1 +/* drm_vblank->time uses ktime_t type */ +#define HAVE_DRM_VBLANK_USE_KTIME_T 1 + /* drm_vma_node_verify_access() 2nd argument is drm_file */ #define HAVE_DRM_VMA_NODE_VERIFY_ACCESS_HAS_DRM_FILE 1 @@ -1154,7 +1160,7 @@ #define PACKAGE_NAME "amdgpu-dkms" /* Define to the full name and version of this package. */ -#define PACKAGE_STRING "amdgpu-dkms 5.13.6" +#define PACKAGE_STRING "amdgpu-dkms 5.13.5" /* Define to the one symbol short name of this package. */ #define PACKAGE_TARNAME "amdgpu-dkms" @@ -1163,7 +1169,7 @@ #define PACKAGE_URL "" /* Define to the version of this package. */ -#define PACKAGE_VERSION "5.13.6" +#define PACKAGE_VERSION "5.13.5" #include "config-amd-chips.h" From 9fc190ad07864726d1b4f64e77473735d204c08c Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 6 Jan 2022 12:39:56 +0800 Subject: [PATCH 0599/1868] drm/amdkcl: wrap the code under macro CONFIG_DRM_LEGACY The following patch hides the DRM midlayer behind CONFIG_DRM_LEGACY c1736b9008cb "drm: IRQ midlayer is now legacy" Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 5 ++++- drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h | 3 +++ 3 files changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index a17b251cade3f..6121776ad03ba 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3051,7 +3051,9 @@ static struct drm_driver amdgpu_kms_driver = { .get_vblank_timestamp = kcl_amdgpu_get_vblank_timestamp_kms, .get_scanout_position = kcl_amdgpu_get_crtc_scanout_position, #endif +#ifdef CONFIG_DRM_LEGACY .irq_handler = amdgpu_irq_handler, +#endif .ioctls = amdgpu_ioctls_kms, #ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK .gem_free_object_unlocked = amdgpu_gem_object_free, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c index 8816017dc9e29..437a81342e2b8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c @@ -161,7 +161,10 @@ void amdgpu_irq_disable_all(struct amdgpu_device *adev) * Returns: * result of handling the IRQ, as defined by &irqreturn_t */ -static irqreturn_t amdgpu_irq_handler(int irq, void *arg) +#ifndef CONFIG_DRM_LEGACY +static +#endif +irqreturn_t amdgpu_irq_handler(int irq, void *arg) { struct drm_device *dev = (struct drm_device *) arg; struct amdgpu_device *adev = drm_to_adev(dev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h index 04c0b4fa17a4e..aef5c216b1911 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.h @@ -121,6 +121,9 @@ enum interrupt_node_id_per_aid { extern const int node_id_to_phys_map[NODEID_MAX]; void amdgpu_irq_disable_all(struct amdgpu_device *adev); +#ifdef CONFIG_DRM_LEGACY +irqreturn_t amdgpu_irq_handler(int irq, void *arg); +#endif int amdgpu_irq_init(struct amdgpu_device *adev); void amdgpu_irq_fini_sw(struct amdgpu_device *adev); From b92e2305debcff2009622ed1e91d3c71ca132ffd Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Fri, 14 Jan 2022 16:03:54 +0800 Subject: [PATCH 0600/1868] drm/amdkcl: test whether struct drm_vma_offset_node has member readonly This is cause by f425821b946847282708121600fffc20344183a0 "drm/vma: Add a driver_private member to vma_node." v5.13-rc3-1382-gf425821b9468 Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/backport/kcl_drm_gem.c | 2 ++ .../m4/drm-vma-offset-node-readonly-field.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 19 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-vma-offset-node-readonly-field.m4 diff --git a/drivers/gpu/drm/amd/backport/kcl_drm_gem.c b/drivers/gpu/drm/amd/backport/kcl_drm_gem.c index 328395cbd0125..359099cb8af9e 100644 --- a/drivers/gpu/drm/amd/backport/kcl_drm_gem.c +++ b/drivers/gpu/drm/amd/backport/kcl_drm_gem.c @@ -121,6 +121,7 @@ int _kcl_drm_gem_mmap(struct file *filp, struct vm_area_struct *vma) { return -EACCES; } +#ifdef HAVE_DRM_VMA_OFFSET_NODE_READONLY_FIELD if (node->readonly) { if (vma->vm_flags & VM_WRITE) { drm_gem_object_put(obj); @@ -129,6 +130,7 @@ int _kcl_drm_gem_mmap(struct file *filp, struct vm_area_struct *vma) { vma->vm_flags &= ~VM_MAYWRITE; } +#endif ret = _kcl_drm_gem_mmap_obj(obj, drm_vma_node_size(node) << PAGE_SHIFT, vma); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-vma-offset-node-readonly-field.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-vma-offset-node-readonly-field.m4 new file mode 100644 index 0000000000000..06ca73cc0fe91 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-vma-offset-node-readonly-field.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.13-rc3-1382-gf425821b9468 +dnl # drm/vma: Add a driver_private member to vma_node. +dnl # +AC_DEFUN([AC_AMDGPU_DRM_VMA_OFFSET_NODE_READONLY_FIELD], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_vma_offset_node *node = NULL; + node->readonly = false; + ], [ + AC_DEFINE(HAVE_DRM_VMA_OFFSET_NODE_READONLY_FIELD, 1, [struct drm_vma_offset_node has readonly field]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index b418f5b1033a8..8c5abf43d4746 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -183,6 +183,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_STRUCT_KOBJ_TYPE AC_AMDGPU_CLOSE_FD AC_AMDGPU_IS_FIRMWARE_FRAMEBUFFER + AC_AMDGPU_DRM_VMA_OFFSET_NODE_READONLY_FIELD AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 0432ea2dbb29774bf26ac8f40e198b2c134c4c03 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 17 Jan 2022 10:34:10 +0800 Subject: [PATCH 0601/1868] drm/amdkcl: Test whether ww_mutex_trylock() has context argument Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 3 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../gpu/drm/amd/dkms/m4/ww_mutex_trylock.m4 | 16 ++++++++++ include/kcl/backport/kcl_ww_mutex.h | 29 +++++++++++++++++++ include/kcl/kcl_dma-resv.h | 1 + 5 files changed, 50 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/ww_mutex_trylock.m4 create mode 100644 include/kcl/backport/kcl_ww_mutex.h diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index a589a6f1f9f80..1e737875cb974 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1114,6 +1114,9 @@ /* wait_queue_entry_t exists */ #define HAVE_WAIT_QUEUE_ENTRY 1 +/* ww_mutex_trylock() has context arg */ +#define HAVE_WW_MUTEX_TRYLOCK_CONTEXT_ARG 1 + /* is_device_page is available */ /* #undef HAVE_ZONE_DEVICE_PUBLIC */ diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 8c5abf43d4746..c32ccb2e7dc67 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -184,6 +184,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_CLOSE_FD AC_AMDGPU_IS_FIRMWARE_FRAMEBUFFER AC_AMDGPU_DRM_VMA_OFFSET_NODE_READONLY_FIELD + AC_AMDGPU_WW_MUTEX_TRYLOCK_CONTEXT_ARG AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/ww_mutex_trylock.m4 b/drivers/gpu/drm/amd/dkms/m4/ww_mutex_trylock.m4 new file mode 100644 index 0000000000000..e3018a1b798e0 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/ww_mutex_trylock.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v5.15-rc1-1-g12235da8c80a +dnl # kernel/locking: Add context to ww_mutex_trylock() +dnl # +AC_DEFUN([AC_AMDGPU_WW_MUTEX_TRYLOCK_CONTEXT_ARG], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + int r = ww_mutex_trylock(NULL, NULL); + ], [ + AC_DEFINE(HAVE_WW_MUTEX_TRYLOCK_CONTEXT_ARG, 1, + [ww_mutex_trylock() has context arg]) + ]) + ]) +]) diff --git a/include/kcl/backport/kcl_ww_mutex.h b/include/kcl/backport/kcl_ww_mutex.h new file mode 100644 index 0000000000000..101a5b8aacafa --- /dev/null +++ b/include/kcl/backport/kcl_ww_mutex.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Wound/Wait Mutexes: blocking mutual exclusion locks with deadlock avoidance + * + * Original mutex implementation started by Ingo Molnar: + * + * Copyright (C) 2004, 2005, 2006 Red Hat, Inc., Ingo Molnar + * + * Wait/Die implementation: + * Copyright (C) 2013 Canonical Ltd. + * Choice of algorithm: + * Copyright (C) 2018 WMWare Inc. + * + * This file contains the main data structure and API definitions. + */ +#ifndef __KCL_BACKPORT_KCL_WW_MUTEX_H__ +#define __KCL_BACKPORT_KCL_WW_MUTEX_H__ + +#include + +#ifndef HAVE_WW_MUTEX_TRYLOCK_CONTEXT_ARG +static inline int _kcl_ww_mutex_trylock(struct ww_mutex *lock) +{ + return ww_mutex_trylock(lock); +} +#define ww_mutex_trylock(MUTEX, CTX) _kcl_ww_mutex_trylock(MUTEX) +#endif + +#endif diff --git a/include/kcl/kcl_dma-resv.h b/include/kcl/kcl_dma-resv.h index 680f1fe9c1757..0d0ccbbb5d043 100644 --- a/include/kcl/kcl_dma-resv.h +++ b/include/kcl/kcl_dma-resv.h @@ -48,6 +48,7 @@ #include #include +#include #include struct dma_resv_list; From ce0d667aeb549813c0fcd188baf6b65229f38386 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 17 Jan 2022 12:03:59 +0800 Subject: [PATCH 0602/1868] drm/amdkcl: Test whether drm_aperture_remove_conflicting_pci_framebuffers() has drm_driver argument Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c | 9 +++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 4 ++++ ...ture-remove-conflicting-pci-framebuffers.m4 | 18 ++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 32 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-aperture-remove-conflicting-pci-framebuffers.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c index c81b1cadf0099..c597046dee062 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c @@ -107,7 +107,12 @@ EXPORT_SYMBOL(drm_aperture_remove_conflicting_framebuffers); * Returns: * 0 on success, or a negative errno code otherwise */ +#ifdef HAVE_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ARG +int drm_aperture_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, + const struct drm_driver *req_driver) +#else int drm_aperture_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, const char *name) +#endif { resource_size_t base, size; int bar, ret = 0; @@ -128,11 +133,15 @@ int drm_aperture_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, const #ifdef HAVE_VGA_REMOVE_VGACON #if IS_REACHABLE(CONFIG_FB) +#ifdef HAVE_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ARG + ret = remove_conflicting_pci_framebuffers(pdev, req_driver->name); +#else #ifdef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_NO_RES_ID_ARG ret = remove_conflicting_pci_framebuffers(pdev, name); #else ret = remove_conflicting_pci_framebuffers(pdev, 0, name); #endif +#endif /* HAVE_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ARG */ #endif if (ret == 0) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 1e737875cb974..f13f6a45e35d8 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -133,6 +133,10 @@ /* drm_aperture_remove_* is availablea */ #define HAVE_DRM_APERTURE 1 +/* drm_aperture_remove_conflicting_pci_framebuffers() second arg is + drm_driver* */ +#define HAVE_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ARG 1 + /* drm_atomic_get_old_crtc_state() and drm_atomic_get_new_crtc_state() are available */ #define HAVE_DRM_ATOMIC_GET_CRTC_STATE 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-aperture-remove-conflicting-pci-framebuffers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-aperture-remove-conflicting-pci-framebuffers.m4 new file mode 100644 index 0000000000000..50cfd872b53b3 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-aperture-remove-conflicting-pci-framebuffers.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit v5.13-rc3-1543-g97c9bfe3f660 +dnl # drm/aperture: Pass DRM driver structure instead of driver name +dnl # +AC_DEFUN([AC_AMDGPU_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ARG], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + struct drm_driver; + ], [ + const struct drm_driver *drv = NULL; + drm_aperture_remove_conflicting_pci_framebuffers(NULL, drv); + ], [ + AC_DEFINE(HAVE_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ARG, 1, + [drm_aperture_remove_conflicting_pci_framebuffers() second arg is drm_driver*]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index c32ccb2e7dc67..ed2bd131d148a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -185,6 +185,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_IS_FIRMWARE_FRAMEBUFFER AC_AMDGPU_DRM_VMA_OFFSET_NODE_READONLY_FIELD AC_AMDGPU_WW_MUTEX_TRYLOCK_CONTEXT_ARG + AC_AMDGPU_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ARG AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 2e22efb7bf1577703df6df3638e56478b1be611e Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 17 Jan 2022 12:41:56 +0800 Subject: [PATCH 0603/1868] drm/amdkcl: Test whether synchronize_shrinkers() is available Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_vmscan.c | 31 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../drm/amd/dkms/m4/synchronize-shrinkers.m4 | 13 ++++++++ drivers/gpu/drm/ttm/backport/backport.h | 1 + include/kcl/kcl_shrinker.h | 10 ++++++ 7 files changed, 60 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_vmscan.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/synchronize-shrinkers.m4 create mode 100644 include/kcl/kcl_shrinker.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 5352465a012f4..dab6bdb4b03ea 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -12,7 +12,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_drm_crtc.o kcl_drm_connector.o kcl_drm_atomic_helper.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o kcl_ftrace.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_fs_read_write.o kcl_drm_aperture.o \ - kcl_drm_drv.o kcl_drm_simple_kms_helper.o kcl_bitmap.o + kcl_drm_drv.o kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_vmscan.c b/drivers/gpu/drm/amd/amdkcl/kcl_vmscan.c new file mode 100644 index 0000000000000..fb57e87ff981b --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_vmscan.c @@ -0,0 +1,31 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds + * + * Swap reorganised 29.12.95, Stephen Tweedie. + * kswapd added: 7.1.96 sct + * Removed kswapd_ctl limits, and swap out as many pages as needed + * to bring the system back to freepages.high: 2.4.97, Rik van Riel. + * Zone aware kswapd started 02/00, Kanoj Sarcar (kanoj@sgi.com). + * Multiqueue VM started 5.8.00, Rik van Riel. + */ +#include + +#ifndef HAVE_SYNCHRONIZE_SHRINKERS +static DECLARE_RWSEM(shrinker_rwsem); + +/** + * synchronize_shrinkers - Wait for all running shrinkers to complete. + * + * This is equivalent to calling unregister_shrink() and register_shrinker(), + * but atomically and with less overhead. This is useful to guarantee that all + * shrinker invocations have seen an update, before freeing memory, similar to + * rcu. + */ +void synchronize_shrinkers(void) +{ + down_write(&shrinker_rwsem); + up_write(&shrinker_rwsem); +} +EXPORT_SYMBOL(synchronize_shrinkers); +#endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index f13f6a45e35d8..a7bd3f8fbc6db 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1064,6 +1064,9 @@ /* zone->managed_pages is available */ /* #undef HAVE_STRUCT_ZONE_MANAGED_PAGES */ +/* synchronize_shrinkers() is available */ +#define HAVE_SYNCHRONIZE_SHRINKERS 1 + /* sysfs_emit() and sysfs_emit_at() are available */ #define HAVE_SYSFS_EMIT 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index ed2bd131d148a..c389fd02af4c3 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -186,6 +186,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_VMA_OFFSET_NODE_READONLY_FIELD AC_AMDGPU_WW_MUTEX_TRYLOCK_CONTEXT_ARG AC_AMDGPU_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ARG + AC_AMDGPU_SYNCHRONIZE_SHRINKERS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/synchronize-shrinkers.m4 b/drivers/gpu/drm/amd/dkms/m4/synchronize-shrinkers.m4 new file mode 100644 index 0000000000000..3abf21e7f2b67 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/synchronize-shrinkers.m4 @@ -0,0 +1,13 @@ +dnl # +dnl # v5.14-rc3-760-g880121be1179 +dnl # mm/vmscan: add sync_shrinkers function v3 +dnl # +AC_DEFUN([AC_AMDGPU_SYNCHRONIZE_SHRINKERS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([synchronize_shrinkers], + [mm/vmscan.c], [ + AC_DEFINE(HAVE_SYNCHRONIZE_SHRINKERS, 1, + [synchronize_shrinkers() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index 21badd8cad2e9..cc5ba307b7e10 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -19,5 +19,6 @@ #include #include #include +#include #endif diff --git a/include/kcl/kcl_shrinker.h b/include/kcl/kcl_shrinker.h new file mode 100644 index 0000000000000..d8704a749d2dd --- /dev/null +++ b/include/kcl/kcl_shrinker.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef AMDKCL_SHRINKER_H +#define AMDKCL_SHRINKER_H + +#ifndef HAVE_SYNCHRONIZE_SHRINKERS +extern void synchronize_shrinkers(void); +#endif + +#endif From 988981809c1e696f24d2ab37e573ea6b655aa428 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 17 Jan 2022 13:00:54 +0800 Subject: [PATCH 0604/1868] drm/amdkcl: Test whether krealloc_array() is available Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 3 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/krealloc-array.m4 | 18 +++++++++ include/kcl/backport/kcl_fence_backport.h | 1 + include/kcl/kcl_slab.h | 37 +++++++++++++++++++ 5 files changed, 60 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/krealloc-array.m4 create mode 100644 include/kcl/kcl_slab.h diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index a7bd3f8fbc6db..085a46d6325b2 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -753,6 +753,9 @@ /* kmap_local_* is available */ #define HAVE_KMAP_LOCAL 1 +/* krealloc_array() is available */ +#define HAVE_KREALLOC_ARRAY 1 + /* kref_read() function is available */ #define HAVE_KREF_READ 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index c389fd02af4c3..f05ef19a69b17 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -187,6 +187,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_WW_MUTEX_TRYLOCK_CONTEXT_ARG AC_AMDGPU_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ARG AC_AMDGPU_SYNCHRONIZE_SHRINKERS + AC_AMDGPU_KREALLOC_ARRAY AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/krealloc-array.m4 b/drivers/gpu/drm/amd/dkms/m4/krealloc-array.m4 new file mode 100644 index 0000000000000..f9f0fa0a1862f --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/krealloc-array.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # v5.10-13-gf0dbd2bd1c22 +dnl # mm: slab: provide krealloc_array() +dnl # +AC_DEFUN([AC_AMDGPU_KREALLOC_ARRAY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + void *p = krealloc_array(NULL, 0, 0, GFP_KERNEL); + (void)p; + ], [ + AC_DEFINE(HAVE_KREALLOC_ARRAY, 1, + [krealloc_array() is available]) + ]) + ]) +]) diff --git a/include/kcl/backport/kcl_fence_backport.h b/include/kcl/backport/kcl_fence_backport.h index 7e3e1ab42138b..a29c3293c6c88 100644 --- a/include/kcl/backport/kcl_fence_backport.h +++ b/include/kcl/backport/kcl_fence_backport.h @@ -2,6 +2,7 @@ #ifndef AMDKCL_FENCE_BACKPORT_H #define AMDKCL_FENCE_BACKPORT_H #include +#include /* * commit v4.18-rc2-533-g418cc6ca0607 diff --git a/include/kcl/kcl_slab.h b/include/kcl/kcl_slab.h new file mode 100644 index 0000000000000..e095f8a46088e --- /dev/null +++ b/include/kcl/kcl_slab.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Written by Mark Hemment, 1996 (markhe@nextd.demon.co.uk). + * + * (C) SGI 2006, Christoph Lameter + * Cleaned up and restructured to ease the addition of alternative + * implementations of SLAB allocators. + * (C) Linux Foundation 2008-2013 + * Unified interface for all slab allocators + */ +#ifndef AMDKCL_SLAB_H +#define AMDKCL_SLAB_H + +#include +#include + +#ifndef HAVE_KREALLOC_ARRAY +/** + * krealloc_array - reallocate memory for an array. + * @p: pointer to the memory chunk to reallocate + * @new_n: new number of elements to alloc + * @new_size: new size of a single member of the array + * @flags: the type of memory to allocate (see kmalloc) + */ +static __must_check inline void * +krealloc_array(void *p, size_t new_n, size_t new_size, gfp_t flags) +{ + size_t bytes; + + if (unlikely(check_mul_overflow(new_n, new_size, &bytes))) + return NULL; + + return krealloc(p, bytes, flags); +} +#endif + +#endif From c645a742ea22eec25b4ce3ad5f8f878710266228 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 17 Jan 2022 13:27:47 +0800 Subject: [PATCH 0605/1868] drm/amdkcl: Test whether vga_client_register() don't pass cookie argument Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 17 ++++++++++++++++- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../gpu/drm/amd/dkms/m4/vga-client-register.m4 | 18 ++++++++++++++++++ 4 files changed, 38 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/vga-client-register.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 1e3d527290ffc..1092a54474113 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -1766,11 +1766,18 @@ bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev) * Enable/disable vga decode (all asics). * Returns VGA resource flags. */ +#ifdef HAVE_VGA_CLIENT_REGISTER_NOT_PASS_COOKIE static unsigned int amdgpu_device_vga_set_decode(struct pci_dev *pdev, bool state) +#else +static unsigned int amdgpu_device_vga_set_decode(void *cookie, bool state) +#endif { +#ifdef HAVE_VGA_CLIENT_REGISTER_NOT_PASS_COOKIE struct amdgpu_device *adev = drm_to_adev(pci_get_drvdata(pdev)); - +#else + struct amdgpu_device *adev = cookie; +#endif amdgpu_asic_set_vga_state(adev, state); if (state) return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | @@ -4424,7 +4431,11 @@ int amdgpu_device_init(struct amdgpu_device *adev, * ignore it */ if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA) +#ifdef HAVE_VGA_CLIENT_REGISTER_NOT_PASS_COOKIE vga_client_register(adev->pdev, amdgpu_device_vga_set_decode); +#else + vga_client_register(adev->pdev, adev, NULL, amdgpu_device_vga_set_decode); +#endif px = amdgpu_device_supports_px(ddev); @@ -4595,7 +4606,11 @@ void amdgpu_device_fini_sw(struct amdgpu_device *adev) vga_switcheroo_fini_domain_pm_ops(adev->dev); if ((adev->pdev->class >> 8) == PCI_CLASS_DISPLAY_VGA) +#ifdef HAVE_VGA_CLIENT_REGISTER_NOT_PASS_COOKIE vga_client_unregister(adev->pdev); +#else + vga_client_register(adev->pdev, NULL, NULL, NULL); +#endif if (drm_dev_enter(adev_to_drm(adev), &idx)) { diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 085a46d6325b2..2343d06843b57 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1088,6 +1088,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_UAPI_LINUX_SCHED_TYPES_H 1 +/* vga_client_register() don't pass a cookie */ +#define HAVE_VGA_CLIENT_REGISTER_NOT_PASS_COOKIE 1 + /* vga_remove_vgacon() is available */ #define HAVE_VGA_REMOVE_VGACON 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index f05ef19a69b17..0d97eb58f5106 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -188,6 +188,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ARG AC_AMDGPU_SYNCHRONIZE_SHRINKERS AC_AMDGPU_KREALLOC_ARRAY + AC_AMDGPU_VGA_CLIENT_REGISTER_NOT_PASS_COOKIE AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/vga-client-register.m4 b/drivers/gpu/drm/amd/dkms/m4/vga-client-register.m4 new file mode 100644 index 0000000000000..603da40bd05db --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/vga-client-register.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # v5.13-rc3-1630-gbf44e8cecc03 +dnl # vgaarb: don't pass a cookie to vga_client_register +dnl # +AC_DEFUN([AC_AMDGPU_VGA_CLIENT_REGISTER_NOT_PASS_COOKIE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + struct pci_dev; + ], [ + unsigned int (*callback)(struct pci_dev *, bool) = NULL; + vga_client_register(NULL, callback); + ], [ + AC_DEFINE(HAVE_VGA_CLIENT_REGISTER_NOT_PASS_COOKIE, 1, + [vga_client_register() don't pass a cookie]) + ]) + ]) +]) From e3ed75aee6782c09cfab83e4a44b703c718a178c Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 11 Oct 2023 16:51:31 +0800 Subject: [PATCH 0606/1868] drm/amdkcl: Test whether vma_lookup() is available Signed-off-by: Leslie Shi Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/vma-lookup.m4 | 16 ++++++++++++++++ include/kcl/kcl_mm.h | 20 ++++++++++++++++++++ 4 files changed, 40 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/vma-lookup.m4 diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 2343d06843b57..ec9c4c948950c 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1097,6 +1097,9 @@ /* vga_switcheroo_set_dynamic_switch() exist */ /* #undef HAVE_VGA_SWITCHEROO_SET_DYNAMIC_SWITCH */ +/* vma_lookup() is available */ +#define HAVE_VMA_LOOKUP 1 + /* vmf_insert_*() are available */ #define HAVE_VMF_INSERT 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 0d97eb58f5106..225b312ce2968 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -189,6 +189,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_SYNCHRONIZE_SHRINKERS AC_AMDGPU_KREALLOC_ARRAY AC_AMDGPU_VGA_CLIENT_REGISTER_NOT_PASS_COOKIE + AC_AMDGPU_VMA_LOOKUP AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/vma-lookup.m4 b/drivers/gpu/drm/amd/dkms/m4/vma-lookup.m4 new file mode 100644 index 0000000000000..1eb0129ff303c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/vma-lookup.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v5.13-105-gce6d42f2e4a2 +dnl # mm: add vma_lookup(), update find_vma_intersection() comments +dnl # +AC_DEFUN([AC_AMDGPU_VMA_LOOKUP], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + vma_lookup(NULL, 0); + ], [ + AC_DEFINE(HAVE_VMA_LOOKUP, 1, + [vma_lookup() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_mm.h b/include/kcl/kcl_mm.h index 4f33936bf7dd9..6a9f864111c47 100644 --- a/include/kcl/kcl_mm.h +++ b/include/kcl/kcl_mm.h @@ -70,4 +70,24 @@ static inline bool is_cow_mapping(vm_flags_t flags) } #endif /* HAVE_IS_COW_MAPPING */ +#ifndef HAVE_VMA_LOOKUP +/** + * vma_lookup() - Find a VMA at a specific address + * @mm: The process address space. + * @addr: The user address. + * + * Return: The vm_area_struct at the given address, %NULL otherwise. + */ +static inline +struct vm_area_struct *vma_lookup(struct mm_struct *mm, unsigned long addr) +{ + struct vm_area_struct *vma = find_vma(mm, addr); + + if (vma && addr < vma->vm_start) + vma = NULL; + + return vma; +} +#endif /* HAVE_VMA_LOOKUP */ + #endif /* AMDKCL_MM_H */ From bf0e4218aad6658f4f4c373fb2e15b3173ea03a2 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 17 Jan 2022 14:24:31 +0800 Subject: [PATCH 0607/1868] drm/amdkcl: Test whether generic_handle_domain_irq() is available Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 4 ++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../drm/amd/dkms/m4/generic_handle_domain_irq.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 3 +++ 4 files changed, 26 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/generic_handle_domain_irq.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c index 437a81342e2b8..0c9da161205f9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c @@ -476,7 +476,11 @@ void amdgpu_irq_dispatch(struct amdgpu_device *adev, } else if (((client_id == AMDGPU_IRQ_CLIENTID_LEGACY) || (client_id == SOC15_IH_CLIENTID_ISP)) && adev->irq.virq[src_id]) { +#ifdef HAVE_GENERIC_HANDLE_DOMAIN_IRQ generic_handle_domain_irq(adev->irq.domain, src_id); +#else + generic_handle_irq(irq_find_mapping(adev->irq.domain, src_id)); +#endif } else if (!adev->irq.client[client_id].sources) { DRM_DEBUG("Unregistered interrupt client_id: %d src_id: %d\n", diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index ec9c4c948950c..566f38b03388b 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -687,6 +687,9 @@ /* drm_driver->gem_free_object_unlocked() is available */ /* #undef HAVE_GEM_FREE_OBJECT_UNLOCKED_IN_DRM_DRIVER */ +/* generic_handle_domain_irq() is available */ +#define HAVE_GENERIC_HANDLE_DOMAIN_IRQ 1 + /* get_mm_exe_file() is available */ #define HAVE_GET_MM_EXE_FILE 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/generic_handle_domain_irq.m4 b/drivers/gpu/drm/amd/dkms/m4/generic_handle_domain_irq.m4 new file mode 100644 index 0000000000000..d02f0f7f60014 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/generic_handle_domain_irq.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v5.13-rc4-24-g8240ef50d486 +dnl # genirq: Add generic_handle_domain_irq() helper +dnl # +AC_DEFUN([AC_AMDGPU_GENERIC_HANDLE_DOMAIN_IRQ], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + generic_handle_domain_irq(NULL, 0); + ], [ + AC_DEFINE(HAVE_GENERIC_HANDLE_DOMAIN_IRQ, 1, + [generic_handle_domain_irq() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 225b312ce2968..b7a47bb35055c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -190,6 +190,9 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_KREALLOC_ARRAY AC_AMDGPU_VGA_CLIENT_REGISTER_NOT_PASS_COOKIE AC_AMDGPU_VMA_LOOKUP + AC_AMDGPU_DMA_FENCE_CHAIN_ALLOC + AC_AMDGPU_DMA_FENCE_CHAIN_STRUCT + AC_AMDGPU_GENERIC_HANDLE_DOMAIN_IRQ AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 01668f8e8429a79f7594532d322a93699d88bc9c Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 17 Jan 2022 15:17:19 +0800 Subject: [PATCH 0608/1868] drm/amdkcl: Test whether linux/stdarg.h is available Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/display/dc/dc_helper.c | 2 -- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 | 6 ++++++ include/kcl/header/linux/stdarg.h | 11 +++++++++++ 4 files changed, 20 insertions(+), 2 deletions(-) create mode 100644 include/kcl/header/linux/stdarg.h diff --git a/drivers/gpu/drm/amd/display/dc/dc_helper.c b/drivers/gpu/drm/amd/display/dc/dc_helper.c index b402be59b2c83..8d0eb9798254a 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_helper.c +++ b/drivers/gpu/drm/amd/display/dc/dc_helper.c @@ -28,8 +28,6 @@ */ #include -#include - #include "dm_services.h" #include "dc.h" diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 566f38b03388b..82b09d7fdc090 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -852,6 +852,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_SCHED_TASK_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_STDARG_H 1 + /* list_bulk_move_tail() is available */ #define HAVE_LIST_BULK_MOVE_TAIL 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 index 38b46427e3689..9e7deb65f6a95 100644 --- a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 @@ -72,4 +72,10 @@ AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ dnl # dma-buf: Add struct dma-buf-map for storing struct dma_buf.vaddr_ptr dnl # AC_KERNEL_CHECK_HEADERS([linux/dma-buf-map.h]) + + dnl # + dnl # v5.14-rc5-11-gc0891ac15f04 + dnl # isystem: ship and use stdarg.h + dnl # + AC_KERNEL_CHECK_HEADERS([linux/stdarg.h]) ]) diff --git a/include/kcl/header/linux/stdarg.h b/include/kcl/header/linux/stdarg.h new file mode 100644 index 0000000000000..c7564aec2d86d --- /dev/null +++ b/include/kcl/header/linux/stdarg.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_LINUX_STDARG_H_H +#define _KCL_HEADER_LINUX_STDARG_H_H + +#if defined(HAVE_LINUX_STDARG_H) +#include_next +#else +#include +#endif + +#endif From 768d5021912e6ceb1f9d753bfee2dd2161595705 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 18 Jan 2022 12:41:13 +0800 Subject: [PATCH 0609/1868] drm/amdkcl: access resv field using amdkcl_ttm_resv Signed-off-by: Leslie Shi --- drivers/gpu/drm/ttm/ttm_bo_util.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c index 09af9bc43ebad..e5cd214a84bad 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_util.c +++ b/drivers/gpu/drm/ttm/ttm_bo_util.c @@ -222,7 +222,7 @@ static void ttm_transfered_destroy(struct ttm_buffer_object *bo) struct ttm_transfer_obj *fbo; fbo = container_of(bo, struct ttm_transfer_obj, base); - dma_resv_fini(&fbo->base.base._resv); + dma_resv_fini(&amdkcl_ttm_resv(&fbo->base)); ttm_bo_put(fbo->bo); kfree(fbo); } From 2d1ffdb343ab5c7aeb18d8d9e06ab70fac1d3f97 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 18 Jan 2022 13:18:16 +0800 Subject: [PATCH 0610/1868] drm/amdkcl: add rcu_replace_pointer macro for legacy os Signed-off-by: Leslie Shi --- include/kcl/kcl_rcupdate.h | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/include/kcl/kcl_rcupdate.h b/include/kcl/kcl_rcupdate.h index da63bf6d4f9e0..d2b09177e7c56 100644 --- a/include/kcl/kcl_rcupdate.h +++ b/include/kcl/kcl_rcupdate.h @@ -26,4 +26,26 @@ #define rcu_pointer_handoff(p) (p) #endif +#ifndef rcu_replace_pointer +#if defined(rcu_dereference_protected) && defined(rcu_assign_pointer) +/** + * rcu_replace_pointer() - replace an RCU pointer, returning its old value + * @rcu_ptr: RCU pointer, whose old value is returned + * @ptr: regular pointer + * @c: the lockdep conditions under which the dereference will take place + * + * Perform a replacement, where @rcu_ptr is an RCU-annotated + * pointer and @c is the lockdep argument that is passed to the + * rcu_dereference_protected() call used to read that pointer. The old + * value of @rcu_ptr is returned, and @rcu_ptr is set to @ptr. + */ +#define rcu_replace_pointer(rcu_ptr, ptr, c) \ +({ \ + typeof(ptr) __tmp = rcu_dereference_protected((rcu_ptr), (c)); \ + rcu_assign_pointer((rcu_ptr), (ptr)); \ + __tmp; \ +}) +#endif +#endif + #endif /* AMDKCL_RCUPDATE_H */ From cf49dcc3cc45a7bf4ec547817669bd743c5a7a83 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 17 Jan 2022 14:05:53 +0800 Subject: [PATCH 0611/1868] drm/amdkcl: Test whether dma_fence_chain is available Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- .../gpu/drm/amd/amdkcl/kcl_dma_fence_chain.c | 262 ++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 2 + drivers/gpu/drm/amd/dkms/config/config.h | 6 + .../gpu/drm/amd/dkms/m4/dma-fence-chain.m4 | 34 +++ include/kcl/kcl_dma_fence_chain.h | 123 ++++++++ include/kcl/kcl_fence.h | 2 + 7 files changed, 430 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_chain.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/dma-fence-chain.m4 create mode 100644 include/kcl/kcl_dma_fence_chain.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index dab6bdb4b03ea..d18e0cbe51c9a 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -12,7 +12,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_drm_crtc.o kcl_drm_connector.o kcl_drm_atomic_helper.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o kcl_ftrace.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_fs_read_write.o kcl_drm_aperture.o \ - kcl_drm_drv.o kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o + kcl_drm_drv.o kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_chain.c b/drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_chain.c new file mode 100644 index 0000000000000..d396b7439a8d1 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_chain.c @@ -0,0 +1,262 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * fence-chain: chain fences together in a timeline + * + * Copyright (C) 2018 Advanced Micro Devices, Inc. + * Authors: + * Christian König + */ + +#if !defined(HAVE_STRUCT_DMA_FENCE_CHAIN) + +#include +#include + +static bool dma_fence_chain_enable_signaling(struct dma_fence *fence); + +/** + * dma_fence_chain_get_prev - use RCU to get a reference to the previous fence + * @chain: chain node to get the previous node from + * + * Use dma_fence_get_rcu_safe to get a reference to the previous fence of the + * chain node. + */ +static struct dma_fence *dma_fence_chain_get_prev(struct dma_fence_chain *chain) +{ + struct dma_fence *prev; + + rcu_read_lock(); + prev = dma_fence_get_rcu_safe(&chain->prev); + rcu_read_unlock(); + return prev; +} + +/** + * dma_fence_chain_walk - chain walking function + * @fence: current chain node + * + * Walk the chain to the next node. Returns the next fence or NULL if we are at + * the end of the chain. Garbage collects chain nodes which are already + * signaled. + */ +struct dma_fence *dma_fence_chain_walk(struct dma_fence *fence) +{ + struct dma_fence_chain *chain, *prev_chain; + struct dma_fence *prev, *replacement, *tmp; + + chain = to_dma_fence_chain(fence); + if (!chain) { + dma_fence_put(fence); + return NULL; + } + + while ((prev = dma_fence_chain_get_prev(chain))) { + + prev_chain = to_dma_fence_chain(prev); + if (prev_chain) { + if (!dma_fence_is_signaled(prev_chain->fence)) + break; + + replacement = dma_fence_chain_get_prev(prev_chain); + } else { + if (!dma_fence_is_signaled(prev)) + break; + + replacement = NULL; + } + + tmp = cmpxchg((struct dma_fence __force **)&chain->prev, + prev, replacement); + if (tmp == prev) + dma_fence_put(tmp); + else + dma_fence_put(replacement); + dma_fence_put(prev); + } + + dma_fence_put(fence); + return prev; +} +EXPORT_SYMBOL(dma_fence_chain_walk); + +/** + * dma_fence_chain_find_seqno - find fence chain node by seqno + * @pfence: pointer to the chain node where to start + * @seqno: the sequence number to search for + * + * Advance the fence pointer to the chain node which will signal this sequence + * number. If no sequence number is provided then this is a no-op. + * + * Returns EINVAL if the fence is not a chain node or the sequence number has + * not yet advanced far enough. + */ +int dma_fence_chain_find_seqno(struct dma_fence **pfence, uint64_t seqno) +{ + struct dma_fence_chain *chain; + + if (!seqno) + return 0; + + chain = to_dma_fence_chain(*pfence); + if (!chain || chain->base.seqno < seqno) + return -EINVAL; + + dma_fence_chain_for_each(*pfence, &chain->base) { + if ((*pfence)->context != chain->base.context || + to_dma_fence_chain(*pfence)->prev_seqno < seqno) + break; + } + dma_fence_put(&chain->base); + + return 0; +} +EXPORT_SYMBOL(dma_fence_chain_find_seqno); + +static const char *dma_fence_chain_get_driver_name(struct dma_fence *fence) +{ + return "dma_fence_chain"; +} + +static const char *dma_fence_chain_get_timeline_name(struct dma_fence *fence) +{ + return "unbound"; +} + +static void dma_fence_chain_irq_work(struct irq_work *work) +{ + struct dma_fence_chain *chain; + + chain = container_of(work, typeof(*chain), work); + + /* Try to rearm the callback */ + if (!dma_fence_chain_enable_signaling(&chain->base)) + /* Ok, we are done. No more unsignaled fences left */ + dma_fence_signal(&chain->base); + dma_fence_put(&chain->base); +} + +static void dma_fence_chain_cb(struct dma_fence *f, struct dma_fence_cb *cb) +{ + struct dma_fence_chain *chain; + + chain = container_of(cb, typeof(*chain), cb); + init_irq_work(&chain->work, dma_fence_chain_irq_work); + irq_work_queue(&chain->work); + dma_fence_put(f); +} + +static bool dma_fence_chain_enable_signaling(struct dma_fence *fence) +{ + struct dma_fence_chain *head = to_dma_fence_chain(fence); + + dma_fence_get(&head->base); + dma_fence_chain_for_each(fence, &head->base) { + struct dma_fence_chain *chain = to_dma_fence_chain(fence); + struct dma_fence *f = chain ? chain->fence : fence; + + dma_fence_get(f); + if (!dma_fence_add_callback(f, &head->cb, dma_fence_chain_cb)) { + dma_fence_put(fence); + return true; + } + dma_fence_put(f); + } + dma_fence_put(&head->base); + return false; +} + +static bool dma_fence_chain_signaled(struct dma_fence *fence) +{ + dma_fence_chain_for_each(fence, fence) { + struct dma_fence_chain *chain = to_dma_fence_chain(fence); + struct dma_fence *f = chain ? chain->fence : fence; + + if (!dma_fence_is_signaled(f)) { + dma_fence_put(fence); + return false; + } + } + + return true; +} + +static void dma_fence_chain_release(struct dma_fence *fence) +{ + struct dma_fence_chain *chain = to_dma_fence_chain(fence); + struct dma_fence *prev; + + /* Manually unlink the chain as much as possible to avoid recursion + * and potential stack overflow. + */ + while ((prev = rcu_dereference_protected(chain->prev, true))) { + struct dma_fence_chain *prev_chain; + + if (kref_read(&prev->refcount) > 1) + break; + + prev_chain = to_dma_fence_chain(prev); + if (!prev_chain) + break; + + /* No need for atomic operations since we hold the last + * reference to prev_chain. + */ + chain->prev = prev_chain->prev; + RCU_INIT_POINTER(prev_chain->prev, NULL); + dma_fence_put(prev); + } + dma_fence_put(prev); + + dma_fence_put(chain->fence); + dma_fence_free(fence); +} + +const struct dma_fence_ops dma_fence_chain_ops = { + .use_64bit_seqno = true, + .get_driver_name = dma_fence_chain_get_driver_name, + .get_timeline_name = dma_fence_chain_get_timeline_name, + .enable_signaling = dma_fence_chain_enable_signaling, + .signaled = dma_fence_chain_signaled, + .release = dma_fence_chain_release, +}; +EXPORT_SYMBOL(dma_fence_chain_ops); + +/** + * dma_fence_chain_init - initialize a fence chain + * @chain: the chain node to initialize + * @prev: the previous fence + * @fence: the current fence + * @seqno: the sequence number to use for the fence chain + * + * Initialize a new chain node and either start a new chain or add the node to + * the existing chain of the previous fence. + */ +void dma_fence_chain_init(struct dma_fence_chain *chain, + struct dma_fence *prev, + struct dma_fence *fence, + uint64_t seqno) +{ + struct dma_fence_chain *prev_chain = to_dma_fence_chain(prev); + uint64_t context; + + spin_lock_init(&chain->lock); + rcu_assign_pointer(chain->prev, prev); + chain->fence = fence; + chain->prev_seqno = 0; + + /* Try to reuse the context of the previous chain node. */ + if (prev_chain && __dma_fence_is_later(seqno, prev->seqno, prev->ops)) { + context = prev->context; + chain->prev_seqno = prev->seqno; + } else { + context = dma_fence_context_alloc(1); + /* Make sure that we always have a valid sequence number. */ + if (prev_chain) + seqno = max(prev->seqno, seqno); + } + + dma_fence_init(&chain->base, &dma_fence_chain_ops, + &chain->lock, context, seqno); +} +EXPORT_SYMBOL(dma_fence_chain_init); +#endif /* HAVE_STRUCT_DMA_FENCE_CHAIN */ diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 9cad31b0f38d7..a2ab4cd5687fb 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -83,5 +83,7 @@ #include #include #include +#include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 82b09d7fdc090..b2c35e119e36e 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -88,6 +88,9 @@ /* dma_buf->dynamic_mapping is not available */ /* #undef HAVE_DMA_BUF_OPS_LEGACY */ +/* dma_fence_chain_alloc() is available */ +#define HAVE_DMA_FENCE_CHAIN_ALLOC 1 + /* whether dma_fence_get_stub exits */ #define HAVE_DMA_FENCE_GET_STUB 1 @@ -994,6 +997,9 @@ /* struct dma_buf_ops->pin() is available */ #define HAVE_STRUCT_DMA_BUF_OPS_PIN 1 +/* struct dma_fence_chain is available */ +#define HAVE_STRUCT_DMA_FENCE_CHAIN 1 + /* struct drm_connector_state->duplicated is available */ #define HAVE_STRUCT_DRM_ATOMIC_STATE_DUPLICATED 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-fence-chain.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-fence-chain.m4 new file mode 100644 index 0000000000000..34231d5d2028d --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dma-fence-chain.m4 @@ -0,0 +1,34 @@ +dnl # +dnl # v5.13-rc3-1424-g440d0f12b52a +dnl # dma-buf: add dma_fence_chain_alloc/free v3 +dnl # +AC_DEFUN([AC_AMDGPU_DMA_FENCE_CHAIN_ALLOC], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + dma_fence_chain_alloc(); + ], [ + AC_DEFINE(HAVE_DMA_FENCE_CHAIN_ALLOC, 1, + [dma_fence_chain_alloc() is available]) + ]) + ]) +]) + +dnl # +dnl # v5.0-1331-g7bf60c52e093 +dnl # dma-buf: add new dma_fence_chain container v7 +dnl # +AC_DEFUN([AC_AMDGPU_DMA_FENCE_CHAIN_STRUCT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct dma_fence_chain *chain = NULL; + ], [ + AC_DEFINE(HAVE_STRUCT_DMA_FENCE_CHAIN, 1, + [struct dma_fence_chain is available]) + ]) + ]) +]) + diff --git a/include/kcl/kcl_dma_fence_chain.h b/include/kcl/kcl_dma_fence_chain.h new file mode 100644 index 0000000000000..4cde69227a3f1 --- /dev/null +++ b/include/kcl/kcl_dma_fence_chain.h @@ -0,0 +1,123 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * fence-chain: chain fences together in a timeline + * + * Copyright (C) 2018 Advanced Micro Devices, Inc. + * Authors: + * Christian König + */ +#ifndef AMDKCL_DMA_FENCE_CHAIN_H +#define AMDKCL_DMA_FENCE_CHAIN_H + + +#if !defined(HAVE_STRUCT_DMA_FENCE_CHAIN) +#ifdef HAVE_LINUX_DMA_FENCE_H +#include +#else +#include +#endif +#include +#include + +/** + * struct dma_fence_chain - fence to represent an node of a fence chain + * @base: fence base class + * @prev: previous fence of the chain + * @prev_seqno: original previous seqno before garbage collection + * @fence: encapsulated fence + * @lock: spinlock for fence handling + */ +struct dma_fence_chain { + struct dma_fence base; + struct dma_fence __rcu *prev; + u64 prev_seqno; + struct dma_fence *fence; + union { + /** + * @cb: callback for signaling + * + * This is used to add the callback for signaling the + * complection of the fence chain. Never used at the same time + * as the irq work. + */ + struct dma_fence_cb cb; + + /** + * @work: irq work item for signaling + * + * Irq work structure to allow us to add the callback without + * running into lock inversion. Never used at the same time as + * the callback. + */ + struct irq_work work; + }; + spinlock_t lock; +}; + +extern const struct dma_fence_ops dma_fence_chain_ops; + +/** + * to_dma_fence_chain - cast a fence to a dma_fence_chain + * @fence: fence to cast to a dma_fence_array + * + * Returns NULL if the fence is not a dma_fence_chain, + * or the dma_fence_chain otherwise. + */ +static inline struct dma_fence_chain * +to_dma_fence_chain(struct dma_fence *fence) +{ + if (!fence || fence->ops != &dma_fence_chain_ops) + return NULL; + + return container_of(fence, struct dma_fence_chain, base); +} + +/** + * dma_fence_chain_for_each - iterate over all fences in chain + * @iter: current fence + * @head: starting point + * + * Iterate over all fences in the chain. We keep a reference to the current + * fence while inside the loop which must be dropped when breaking out. + */ +#define dma_fence_chain_for_each(iter, head) \ + for (iter = dma_fence_get(head); iter; \ + iter = dma_fence_chain_walk(iter)) + +struct dma_fence *dma_fence_chain_walk(struct dma_fence *fence); +int dma_fence_chain_find_seqno(struct dma_fence **pfence, uint64_t seqno); +void dma_fence_chain_init(struct dma_fence_chain *chain, + struct dma_fence *prev, + struct dma_fence *fence, + uint64_t seqno); + +#endif /* HAVE_STRUCT_DMA_FENCE_CHAIN */ + +#if !defined(HAVE_STRUCT_DMA_FENCE_CHAIN) || !defined(HAVE_DMA_FENCE_CHAIN_ALLOC) +/** + * dma_fence_chain_alloc + * + * Returns a new struct dma_fence_chain object or NULL on failure. + */ +static inline struct dma_fence_chain *dma_fence_chain_alloc(void) +{ + return kmalloc(sizeof(struct dma_fence_chain), GFP_KERNEL); +}; + +/** + * dma_fence_chain_free + * @chain: chain node to free + * + * Frees up an allocated but not used struct dma_fence_chain object. This + * doesn't need an RCU grace period since the fence was never initialized nor + * published. After dma_fence_chain_init() has been called the fence must be + * released by calling dma_fence_put(), and not through this function. + */ +static inline void dma_fence_chain_free(struct dma_fence_chain *chain) +{ + kfree(chain); +}; + +#endif + +#endif diff --git a/include/kcl/kcl_fence.h b/include/kcl/kcl_fence.h index 88a2d1a425ec2..ec9f6c83ab8da 100644 --- a/include/kcl/kcl_fence.h +++ b/include/kcl/kcl_fence.h @@ -40,6 +40,8 @@ #define dma_fence_remove_callback fence_remove_callback #define dma_fence_enable_sw_signaling fence_enable_sw_signaling #define dma_fence_default_wait fence_default_wait +#define dma_fence_free fence_free +#define dma_fence_get_rcu_safe fence_get_rcu #define dma_fence_set_error fence_set_error #endif From 7cb9f0b77a3f9387b7b7f3231c378ef2a6e53ddd Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 18 Jan 2022 13:35:38 +0800 Subject: [PATCH 0612/1868] drm/amdkcl: Test whether struct dma_fence_ops has use_64bit_seqno field Signed-off-by: Leslie Shi --- .../gpu/drm/amd/amdkcl/kcl_dma_fence_chain.c | 6 ++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/dma-fence-ops.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 27 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/dma-fence-ops.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_chain.c b/drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_chain.c index d396b7439a8d1..8ee9e8bf76779 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_chain.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_chain.c @@ -212,7 +212,9 @@ static void dma_fence_chain_release(struct dma_fence *fence) } const struct dma_fence_ops dma_fence_chain_ops = { +#ifdef HAVE_DMA_FENCE_OPS_USE_64BIT_SEQNO .use_64bit_seqno = true, +#endif .get_driver_name = dma_fence_chain_get_driver_name, .get_timeline_name = dma_fence_chain_get_timeline_name, .enable_signaling = dma_fence_chain_enable_signaling, @@ -245,7 +247,11 @@ void dma_fence_chain_init(struct dma_fence_chain *chain, chain->prev_seqno = 0; /* Try to reuse the context of the previous chain node. */ +#ifdef HAVE_DMA_FENCE_OPS_USE_64BIT_SEQNO if (prev_chain && __dma_fence_is_later(seqno, prev->seqno, prev->ops)) { +#else + if (prev_chain && __dma_fence_is_later(seqno, prev->seqno)) { +#endif context = prev->context; chain->prev_seqno = prev->seqno; } else { diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index b2c35e119e36e..5b2d06af70f69 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -94,6 +94,9 @@ /* whether dma_fence_get_stub exits */ #define HAVE_DMA_FENCE_GET_STUB 1 +/* struct dma_fence_ops has use_64bit_seqno field */ +#define HAVE_DMA_FENCE_OPS_USE_64BIT_SEQNO 1 + /* dma_fence_set_error() is available */ #define HAVE_DMA_FENCE_SET_ERROR 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-fence-ops.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-fence-ops.m4 new file mode 100644 index 0000000000000..c10c92dfb503e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dma-fence-ops.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # v5.1-rc2-1115-g5e498abf1485 +dnl # dma-buf: explicitely note that dma-fence-chains use 64bit seqno +dnl # +AC_DEFUN([AC_AMDGPU_DMA_FENCE_OPS_USE_64BIT_SEQNO], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct dma_fence_ops *ops = NULL; + ops->use_64bit_seqno = false; + ], [ + AC_DEFINE(HAVE_DMA_FENCE_OPS_USE_64BIT_SEQNO, 1, + [struct dma_fence_ops has use_64bit_seqno field]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index b7a47bb35055c..b371016123432 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -192,6 +192,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_VMA_LOOKUP AC_AMDGPU_DMA_FENCE_CHAIN_ALLOC AC_AMDGPU_DMA_FENCE_CHAIN_STRUCT + AC_AMDGPU_DMA_FENCE_OPS_USE_64BIT_SEQNO AC_AMDGPU_GENERIC_HANDLE_DOMAIN_IRQ AC_KERNEL_WAIT From 503f69c143a8465563633791d0aeb1cd527bca79 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 18 Jan 2022 14:04:37 +0800 Subject: [PATCH 0613/1868] drm/amdkcl: Test whether linux/dma-fence-chain.h is available Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c | 2 -- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 | 6 ++++++ include/kcl/header/linux/dma-fence-chain.h | 9 +++++++++ 4 files changed, 18 insertions(+), 2 deletions(-) create mode 100644 include/kcl/header/linux/dma-fence-chain.h diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c index bdf1ef825d896..13b401905d68f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c @@ -29,8 +29,6 @@ * Christian König */ -#include - #include "amdgpu.h" #include "amdgpu_trace.h" #include "amdgpu_amdkfd.h" diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 5b2d06af70f69..224ce75be2c1c 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -819,6 +819,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_DMA_BUF_MAP_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_DMA_FENCE_CHAIN_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_LINUX_DMA_FENCE_H 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 index 9e7deb65f6a95..456e16dba8935 100644 --- a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 @@ -78,4 +78,10 @@ AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ dnl # isystem: ship and use stdarg.h dnl # AC_KERNEL_CHECK_HEADERS([linux/stdarg.h]) + + dnl # + dnl # v5.0-1331-g7bf60c52e093 + dnl # dma-buf: add new dma_fence_chain container v7 + dnl # + AC_KERNEL_CHECK_HEADERS([linux/dma-fence-chain.h]) ]) diff --git a/include/kcl/header/linux/dma-fence-chain.h b/include/kcl/header/linux/dma-fence-chain.h new file mode 100644 index 0000000000000..ff429da204f75 --- /dev/null +++ b/include/kcl/header/linux/dma-fence-chain.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER__LINUX_DMA_FENCE_CHAIN_H_H_ +#define _KCL_HEADER__LINUX_DMA_FENCE_CHAIN_H_H_ + +#if defined(HAVE_LINUX_DMA_FENCE_CHAIN_H) +#include_next +#endif + +#endif From 1f0032c7af40fdae28fdee8e889d689f0af89af2 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 18 Jan 2022 14:44:13 +0800 Subject: [PATCH 0614/1868] drm/amdkcl: wrap the code under macro HAVE_DRM_GEM_OBJECT_RESV Signed-off-by: Leslie Shi --- drivers/gpu/drm/scheduler/sched_main.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/scheduler/sched_main.c b/drivers/gpu/drm/scheduler/sched_main.c index 7e90c9f95611a..5166559933043 100644 --- a/drivers/gpu/drm/scheduler/sched_main.c +++ b/drivers/gpu/drm/scheduler/sched_main.c @@ -959,6 +959,7 @@ int drm_sched_job_add_resv_dependencies(struct drm_sched_job *job, } EXPORT_SYMBOL(drm_sched_job_add_resv_dependencies); +#ifdef HAVE_DRM_GEM_OBJECT_RESV /** * drm_sched_job_add_implicit_dependencies - adds implicit dependencies as job * dependencies @@ -982,6 +983,7 @@ int drm_sched_job_add_implicit_dependencies(struct drm_sched_job *job, dma_resv_usage_rw(write)); } EXPORT_SYMBOL(drm_sched_job_add_implicit_dependencies); +#endif /** * drm_sched_job_cleanup - clean up scheduler job resources From fe17ec20195192650e3917d3c47d428369cef083 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 18 Jan 2022 16:36:08 +0800 Subject: [PATCH 0615/1868] drm/amdkcl: wrap the code under HAVE_STRUCT_XARRAY for legacy os Signed-off-by: Leslie Shi --- drivers/gpu/drm/scheduler/sched_entity.c | 7 +++++++ drivers/gpu/drm/scheduler/sched_main.c | 10 ++++++++-- include/drm/gpu_scheduler.h | 4 +++- include/kcl/header/linux/xarray.h | 9 +++++++++ 4 files changed, 27 insertions(+), 3 deletions(-) create mode 100644 include/kcl/header/linux/xarray.h diff --git a/drivers/gpu/drm/scheduler/sched_entity.c b/drivers/gpu/drm/scheduler/sched_entity.c index 58c8161289fea..934687f6f7d37 100644 --- a/drivers/gpu/drm/scheduler/sched_entity.c +++ b/drivers/gpu/drm/scheduler/sched_entity.c @@ -473,6 +473,9 @@ drm_sched_job_dependency(struct drm_sched_job *job, struct drm_sched_job *drm_sched_entity_pop_job(struct drm_sched_entity *entity) { +#ifndef HAVE_STRUCT_XARRAY + struct drm_gpu_scheduler *sched = entity->rq->sched; +#endif struct drm_sched_job *sched_job; sched_job = to_drm_sched_job(spsc_queue_peek(&entity->job_queue)); @@ -480,7 +483,11 @@ struct drm_sched_job *drm_sched_entity_pop_job(struct drm_sched_entity *entity) return NULL; while ((entity->dependency = +#ifdef HAVE_STRUCT_XARRAY drm_sched_job_dependency(sched_job, entity))) { +#else + sched->ops->dependency(sched_job, entity))) { +#endif trace_drm_sched_job_wait_dep(sched_job, entity->dependency); if (drm_sched_entity_add_dependency_cb(entity)) diff --git a/drivers/gpu/drm/scheduler/sched_main.c b/drivers/gpu/drm/scheduler/sched_main.c index 5166559933043..5adab4b3386c1 100644 --- a/drivers/gpu/drm/scheduler/sched_main.c +++ b/drivers/gpu/drm/scheduler/sched_main.c @@ -813,8 +813,9 @@ int drm_sched_job_init(struct drm_sched_job *job, return -ENOMEM; INIT_LIST_HEAD(&job->list); - +#ifdef HAVE_STRUCT_XARRAY xa_init_flags(&job->dependencies, XA_FLAGS_ALLOC); +#endif return 0; } @@ -850,6 +851,7 @@ void drm_sched_job_arm(struct drm_sched_job *job) } EXPORT_SYMBOL(drm_sched_job_arm); +#ifdef HAVE_STRUCT_XARRAY /** * drm_sched_job_add_dependency - adds the fence as a job dependency * @job: scheduler job to add the dependencies to @@ -984,6 +986,7 @@ int drm_sched_job_add_implicit_dependencies(struct drm_sched_job *job, } EXPORT_SYMBOL(drm_sched_job_add_implicit_dependencies); #endif +#endif /* HAVE_STRUCR_XARRAY */ /** * drm_sched_job_cleanup - clean up scheduler job resources @@ -1000,8 +1003,10 @@ EXPORT_SYMBOL(drm_sched_job_add_implicit_dependencies); */ void drm_sched_job_cleanup(struct drm_sched_job *job) { +#ifdef HAVE_STRUCT_XARRAY struct dma_fence *fence; unsigned long index; +#endif if (kref_read(&job->s_fence->finished.refcount)) { /* drm_sched_job_arm() has been called */ @@ -1013,11 +1018,12 @@ void drm_sched_job_cleanup(struct drm_sched_job *job) job->s_fence = NULL; +#ifdef HAVE_STRUCT_XARRAY xa_for_each(&job->dependencies, index, fence) { dma_fence_put(fence); } xa_destroy(&job->dependencies); - +#endif } EXPORT_SYMBOL(drm_sched_job_cleanup); diff --git a/include/drm/gpu_scheduler.h b/include/drm/gpu_scheduler.h index 5acc64954a883..150c5906c590f 100644 --- a/include/drm/gpu_scheduler.h +++ b/include/drm/gpu_scheduler.h @@ -363,10 +363,12 @@ struct drm_sched_job { * drm_sched_job_add_dependency() and * drm_sched_job_add_implicit_dependencies(). */ +#ifdef HAVE_STRUCT_XARRAY struct xarray dependencies; /** @last_dependency: tracks @dependencies as they signal */ unsigned long last_dependency; +#endif /** * @submit_ts: @@ -554,6 +556,7 @@ int drm_sched_job_init(struct drm_sched_job *job, struct drm_sched_entity *entity, u32 credits, void *owner); void drm_sched_job_arm(struct drm_sched_job *job); + int drm_sched_job_add_dependency(struct drm_sched_job *job, struct dma_fence *fence); int drm_sched_job_add_syncobj_dependency(struct drm_sched_job *job, @@ -567,7 +570,6 @@ int drm_sched_job_add_implicit_dependencies(struct drm_sched_job *job, struct drm_gem_object *obj, bool write); - void drm_sched_entity_modify_sched(struct drm_sched_entity *entity, struct drm_gpu_scheduler **sched_list, unsigned int num_sched_list); diff --git a/include/kcl/header/linux/xarray.h b/include/kcl/header/linux/xarray.h new file mode 100644 index 0000000000000..3df793f177365 --- /dev/null +++ b/include/kcl/header/linux/xarray.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +#ifndef _KCL_HEADER_LINUX_XARRAY_H_H +#define _KCL_HEADER_LINUX_XARRAY_H_H + +#ifdef HAVE_STRUCT_XARRAY +#include_next +#endif + +#endif From e985de5ed487ff1aede961826753d7a47593a655 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 19 Jan 2022 11:58:32 +0800 Subject: [PATCH 0616/1868] drm/amdkcl: add macro DP_PSR2_SU_X_GRANULARITY for legacy os Signed-off-by: Leslie Shi --- include/kcl/kcl_drm_dp_helper.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/include/kcl/kcl_drm_dp_helper.h b/include/kcl/kcl_drm_dp_helper.h index ec52d89063426..10b162b5c4693 100644 --- a/include/kcl/kcl_drm_dp_helper.h +++ b/include/kcl/kcl_drm_dp_helper.h @@ -276,4 +276,16 @@ enum drm_dp_phy { # define DP_DPCD_REV_14 0x14 #endif +/* + * v4.20-rc3-897-g71b15621f097 + * drm: Add the PSR SU granularity registers offsets + */ +#ifndef DP_PSR2_SU_X_GRANULARITY +#define DP_PSR2_SU_X_GRANULARITY 0x072 /* eDP 1.4b */ +#endif +#ifndef DP_PSR2_SU_Y_GRANULARITY +#define DP_PSR2_SU_Y_GRANULARITY 0x074 /* eDP 1.4b */ +#endif + + #endif /* _KCL_DRM_DP_HELPER_H_ */ From b1937aa0ac064c8d3246a54cf48681a11b43a346 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 19 Jan 2022 15:35:09 +0800 Subject: [PATCH 0617/1868] drm/amdkcl: include kcl_kref.h for drm scheduler code Signed-off-by: Leslie Shi --- drivers/gpu/drm/scheduler/backport/backport.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/scheduler/backport/backport.h b/drivers/gpu/drm/scheduler/backport/backport.h index 25460de490b35..3327879e06a15 100644 --- a/drivers/gpu/drm/scheduler/backport/backport.h +++ b/drivers/gpu/drm/scheduler/backport/backport.h @@ -8,5 +8,6 @@ #include #include #include +#include #endif From 261fde7f29150e62b2f8effdfb94197b0e9c0058 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 19 Jan 2022 15:59:05 +0800 Subject: [PATCH 0618/1868] drm/amdkcl: test whether __dma_fence_is_later() is available Signed-off-by: Leslie Shi --- .../gpu/drm/amd/amdkcl/kcl_dma_fence_chain.c | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 8 ++--- .../gpu/drm/amd/dkms/m4/dma-fence-is-later.m4 | 30 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_fence.h | 35 +++++++++++++++++++ 5 files changed, 71 insertions(+), 4 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/dma-fence-is-later.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_chain.c b/drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_chain.c index 8ee9e8bf76779..d19d8b3733657 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_chain.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_chain.c @@ -10,6 +10,7 @@ #if !defined(HAVE_STRUCT_DMA_FENCE_CHAIN) #include +#include #include static bool dma_fence_chain_enable_signaling(struct dma_fence *fence); diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 224ce75be2c1c..fe769beac3a15 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1157,11 +1157,11 @@ /* zone_managed_pages() is available */ #define HAVE_ZONE_MANAGED_PAGES 1 -/* bitmap_free() is available */ -#define HAVE_BITMAP_FUNCS 1 +/* __dma_fence_is_later() is available and has 2 args */ +/* #undef HAVE__DMA_FENCE_IS_LATER_2ARGS */ -/* drm_edid_get_monitor_name is available*/ -#define HAVE_DRM_EDID_GET_MONITOR_NAME 1 +/* __dma_fence_is_later() is available and has ops arg */ +#define HAVE__DMA_FENCE_IS_LATER_WITH_OPS_ARG 1 /* __drm_atomic_helper_connector_destroy_state() wants 1 arg */ #define HAVE___DRM_ATOMIC_HELPER_CONNECTOR_DESTROY_STATE_P 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-fence-is-later.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-fence-is-later.m4 new file mode 100644 index 0000000000000..bbc3eb8117f9c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dma-fence-is-later.m4 @@ -0,0 +1,30 @@ +dnl # +dnl # v5.1-rc2-1115-g5e498abf1485 +dnl # dma-buf: explicitely note that dma-fence-chains use 64bit seqno +dnl # +AC_DEFUN([AC_AMDGPU__DMA_FENCE_IS_LATER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + const struct dma_fence_ops *ops = NULL; + __dma_fence_is_later(0, 0, ops); + ], [ + AC_DEFINE(HAVE__DMA_FENCE_IS_LATER_WITH_OPS_ARG, 1, + [__dma_fence_is_later() is available and has ops arg]) + ], [ + dnl # + dnl # v4.20-rc4-931-gb312d8ca3a7c + dnl # dma-buf: make fence sequence numbers 64 bit v2 + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + __dma_fence_is_later(0, 0); + ], [ + AC_DEFINE(HAVE__DMA_FENCE_IS_LATER_2ARGS, 1, + [__dma_fence_is_later() is available and has 2 args]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index b371016123432..4a74f9fc5950f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -194,6 +194,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DMA_FENCE_CHAIN_STRUCT AC_AMDGPU_DMA_FENCE_OPS_USE_64BIT_SEQNO AC_AMDGPU_GENERIC_HANDLE_DOMAIN_IRQ + AC_AMDGPU__DMA_FENCE_IS_LATER AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_fence.h b/include/kcl/kcl_fence.h index ec9f6c83ab8da..addd6733ff680 100644 --- a/include/kcl/kcl_fence.h +++ b/include/kcl/kcl_fence.h @@ -46,6 +46,41 @@ #define dma_fence_set_error fence_set_error #endif +#if !defined(HAVE__DMA_FENCE_IS_LATER_2ARGS) + +#if !defined(HAVE_DMA_FENCE_OPS_USE_64BIT_SEQNO) +static inline bool __dma_fence_is_later(u64 f1, u64 f2) +{ + + /* This is for backward compatibility with drivers which can only handle + * 32bit sequence numbers. Use a 64bit compare when any of the higher + * bits are none zero, otherwise use a 32bit compare with wrap around + * handling. + */ + if (upper_32_bits(f1) || upper_32_bits(f2)) + return f1 > f2; + + return (int)(lower_32_bits(f1) - lower_32_bits(f2)) > 0; +} + +#elif !defined(HAVE__DMA_FENCE_IS_LATER_WITH_OPS_ARG) && \ + defined(HAVE_DMA_FENCE_OPS_USE_64BIT_SEQNO) +static inline bool __dma_fence_is_later(u64 f1, u64 f2, + const struct dma_fence_ops *ops) +{ + /* This is for backward compatibility with drivers which can only handle + * 32bit sequence numbers. Use a 64bit compare when the driver says to + * do so. + */ + if (ops->use_64bit_seqno) + return f1 > f2; + + return (int)(lower_32_bits(f1) - lower_32_bits(f2)) > 0; +} + +#endif +#endif /* HAVE__DMA_FENCE_IS_LATER_2ARGS */ + /* commit v4.5-rc3-715-gb47bcb93bbf2 * fall back to HAVE_LINUX_DMA_FENCE_H check directly * as it's hard to detect the implementation in kernel From 93a974ec892ef4aefe2ea9689413481e45b50099 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 19 Jan 2022 16:31:28 +0800 Subject: [PATCH 0619/1868] drm/amdkcl: test whether pci_irq_vector() is available Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/pci-irq-vector.m4 | 16 ++++++++++++++++ include/kcl/kcl_pci.h | 9 +++++++++ 5 files changed, 30 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/pci-irq-vector.m4 diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index a2ab4cd5687fb..0fc8065196bae 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -85,5 +85,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index fe769beac3a15..e99886fd8dc15 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -930,6 +930,9 @@ /* struct pci_driver has field dev_groups */ #define HAVE_PCI_DRIVER_DEV_GROUPS 1 +/* pci_irq_vector() is available */ +#define HAVE_PCI_IRQ_VECTOR 1 + /* pci_is_thunderbolt_attached() is available */ #define HAVE_PCI_IS_THUNDERBOLD_ATTACHED 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 4a74f9fc5950f..dfa7db19e3895 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -195,6 +195,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DMA_FENCE_OPS_USE_64BIT_SEQNO AC_AMDGPU_GENERIC_HANDLE_DOMAIN_IRQ AC_AMDGPU__DMA_FENCE_IS_LATER + AC_AMDGPU_PCI_IRQ_VECTOR AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/pci-irq-vector.m4 b/drivers/gpu/drm/amd/dkms/m4/pci-irq-vector.m4 new file mode 100644 index 0000000000000..5567ed9920070 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pci-irq-vector.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v4.7-rc6-10-gaff171641d18 +dnl # PCI: Provide sensible IRQ vector alloc/free routines +dnl # +AC_DEFUN([AC_AMDGPU_PCI_IRQ_VECTOR], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + pci_irq_vector(NULL, 0); + ], [ + AC_DEFINE(HAVE_PCI_IRQ_VECTOR, 1, + [pci_irq_vector() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_pci.h b/include/kcl/kcl_pci.h index f10e5e5c84106..cf46e2db8d19b 100644 --- a/include/kcl/kcl_pci.h +++ b/include/kcl/kcl_pci.h @@ -241,4 +241,13 @@ u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar) #endif /* PCI_REBAR_CTRL_BAR_SHIFT */ +#if !defined(HAVE_PCI_IRQ_VECTOR) +static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr) +{ + if (WARN_ON_ONCE(nr > 0)) + return -EINVAL; + return dev->irq; +} +#endif /* HAVE_PCI_IRQ_VECTOR */ + #endif /* AMDKCL_PCI_H */ From 1be26b43b57b46fb324d6d092bb86d8b88511962 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 20 Jan 2022 10:43:24 +0800 Subject: [PATCH 0620/1868] drm/amdkcl: add macro DP_PSR2_SU_GRANULARITY_REQUIRED Signed-off-by: Leslie Shi --- include/kcl/kcl_drm_dp_helper.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/include/kcl/kcl_drm_dp_helper.h b/include/kcl/kcl_drm_dp_helper.h index 10b162b5c4693..f32ad22d172db 100644 --- a/include/kcl/kcl_drm_dp_helper.h +++ b/include/kcl/kcl_drm_dp_helper.h @@ -287,5 +287,15 @@ enum drm_dp_phy { #define DP_PSR2_SU_Y_GRANULARITY 0x074 /* eDP 1.4b */ #endif +/* + * v4.10-rc3-483-gd0ce90629120 + * drm : adds Y-coordinate and Colorimetry Format + */ +#ifndef DP_PSR2_SU_Y_COORDINATE_REQUIRED +# define DP_PSR2_SU_Y_COORDINATE_REQUIRED (1 << 4) /* eDP 1.4a */ +# define DP_PSR2_SU_GRANULARITY_REQUIRED (1 << 5) /* eDP 1.4b */ +#endif + + #endif /* _KCL_DRM_DP_HELPER_H_ */ From 200e17050bc56d8e4ac6b870ef7063eb4d961c61 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 20 Jan 2022 15:53:46 +0800 Subject: [PATCH 0621/1868] drm/amdkcl: test whether linux/xarray.h is available Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 | 7 +++++++ include/kcl/header/linux/xarray.h | 2 +- 3 files changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index e99886fd8dc15..8404a1f3d9a83 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -864,6 +864,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_STDARG_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_XARRAY_H 1 + /* list_bulk_move_tail() is available */ #define HAVE_LIST_BULK_MOVE_TAIL 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 index 456e16dba8935..8f7a4ca59147b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 @@ -84,4 +84,11 @@ AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ dnl # dma-buf: add new dma_fence_chain container v7 dnl # AC_KERNEL_CHECK_HEADERS([linux/dma-fence-chain.h]) + + + dnl # + dnl # v4.16-11455-gf6bb2a2c0b81 + dnl # xarray: add the xa_lock to the radix_tree_root + dnl # + AC_KERNEL_CHECK_HEADERS([linux/xarray.h]) ]) diff --git a/include/kcl/header/linux/xarray.h b/include/kcl/header/linux/xarray.h index 3df793f177365..80d73c2ed9065 100644 --- a/include/kcl/header/linux/xarray.h +++ b/include/kcl/header/linux/xarray.h @@ -2,7 +2,7 @@ #ifndef _KCL_HEADER_LINUX_XARRAY_H_H #define _KCL_HEADER_LINUX_XARRAY_H_H -#ifdef HAVE_STRUCT_XARRAY +#ifdef HAVE_LINUX_XARRAY_H #include_next #endif From 960fb864e2981d2b7d35aed229ac63fef8b2bcac Mon Sep 17 00:00:00 2001 From: Perry Yuan Date: Mon, 20 Dec 2021 22:44:06 -0500 Subject: [PATCH 0622/1868] drm/amdkcl: wrap drm_edid_get_monitor_name with macro HAVE_DRM_EDID_GET_MONITOR_NAME This patch will check if the drm_edid_get_monitor_name exist in the some old kernel to avoid build dependency failure. b5f640ae7a0 drm/amdgpu: use drm_edid_get_monitor_name() instead of duplicating the code v5.13-3120-gb5f640ae7a0a Signed-off-by: Perry Yuan Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 8404a1f3d9a83..ea447693c38fd 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1169,6 +1169,9 @@ /* __dma_fence_is_later() is available and has ops arg */ #define HAVE__DMA_FENCE_IS_LATER_WITH_OPS_ARG 1 +/* drm_edid_get_monitor_name is available*/ +#define HAVE_DRM_EDID_GET_MONITOR_NAME 1 + /* __drm_atomic_helper_connector_destroy_state() wants 1 arg */ #define HAVE___DRM_ATOMIC_HELPER_CONNECTOR_DESTROY_STATE_P 1 From ca36b345bb84cb197b34aacc8086f48bf126fdcf Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 10 Feb 2022 11:01:46 +0800 Subject: [PATCH 0623/1868] drm/amdkcl: Test whether linux/container_of.h is available Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 | 7 ++++++- include/kcl/header/linux/container_of.h | 10 ++++++++++ 3 files changed, 19 insertions(+), 1 deletion(-) create mode 100644 include/kcl/header/linux/container_of.h diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index ea447693c38fd..7c7a43b69cb6d 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -813,6 +813,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_COMPILER_ATTRIBUTES_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_CONTAINER_OF_H 1 + /* Define to 1 if you have the header file. */ /* #undef HAVE_LINUX_DMA_ATTRS_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 index 8f7a4ca59147b..0ea53ea27426d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 @@ -85,10 +85,15 @@ AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ dnl # AC_KERNEL_CHECK_HEADERS([linux/dma-fence-chain.h]) - dnl # dnl # v4.16-11455-gf6bb2a2c0b81 dnl # xarray: add the xa_lock to the radix_tree_root dnl # AC_KERNEL_CHECK_HEADERS([linux/xarray.h]) + + dnl # + dnl # v5.15-272-gd2a8ebbf8192 + dnl # kernel.h: split out container_of() and typeof_member() macros + dnl # + AC_KERNEL_CHECK_HEADERS([linux/container_of.h]) ]) diff --git a/include/kcl/header/linux/container_of.h b/include/kcl/header/linux/container_of.h new file mode 100644 index 0000000000000..cf1f8a85f216f --- /dev/null +++ b/include/kcl/header/linux/container_of.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_LINUX_CONTAINER_OF_H_H +#define _KCL_HEADER_LINUX_CONTAINER_OF_H_H + +#if defined(HAVE_LINUX_CONTAINER_OF_H) +#include_next +#endif + +#endif + From 9b04c95fccd1d5c45fd4146115efd9b6f7a9eb77 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 10 Feb 2022 11:13:51 +0800 Subject: [PATCH 0624/1868] drm/amdkcl: Test whether linux/cc_platform.h is available It's caused by v6.7-rc3-802-g71ce046327cf drm/ttm: Make sure the mapped tt pages are decrypted when needed Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 + drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 | 6 ++ drivers/gpu/drm/ttm/backport/backport.h | 1 + include/kcl/header/linux/cc_platform.h | 10 +++ include/kcl/kcl_cc_platform.h | 66 ++++++++++++++++++++ 6 files changed, 87 insertions(+) create mode 100644 include/kcl/header/linux/cc_platform.h create mode 100644 include/kcl/kcl_cc_platform.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 0fc8065196bae..7e6a3520aa453 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -86,5 +86,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 7c7a43b69cb6d..f4d2c57119971 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -810,6 +810,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_BITS_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_CC_PLATFORM_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_LINUX_COMPILER_ATTRIBUTES_H 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 index 0ea53ea27426d..7b2aa10060569 100644 --- a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 @@ -96,4 +96,10 @@ AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ dnl # kernel.h: split out container_of() and typeof_member() macros dnl # AC_KERNEL_CHECK_HEADERS([linux/container_of.h]) + + dnl # + dnl # v5.15-rc4-2-g46b49b12f3fc + dnl # arch/cc: Introduce a function to check for confidential computing features + dnl # + AC_KERNEL_CHECK_HEADERS([linux/cc_platform.h]) ]) diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index cc5ba307b7e10..1e6024331b9f1 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -20,5 +20,6 @@ #include #include #include +#include #endif diff --git a/include/kcl/header/linux/cc_platform.h b/include/kcl/header/linux/cc_platform.h new file mode 100644 index 0000000000000..cea7cc0c28876 --- /dev/null +++ b/include/kcl/header/linux/cc_platform.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_LINUX_CC_PLATFORM_H_H +#define _KCL_HEADER_LINUX_CC_PLATFORM_H_H + +#if defined(HAVE_LINUX_CC_PLATFORM_H) +#include_next +#endif + +#endif + diff --git a/include/kcl/kcl_cc_platform.h b/include/kcl/kcl_cc_platform.h new file mode 100644 index 0000000000000..8a2d455442e4f --- /dev/null +++ b/include/kcl/kcl_cc_platform.h @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Confidential Computing Platform Capability checks + * + * Copyright (C) 2021 Advanced Micro Devices, Inc. + * + * Author: Tom Lendacky + */ +#ifndef AMDKCL_CC_PLATFORM_H +#define AMDKCL_CC_PLATFORM_H + +#ifndef HAVE_LINUX_CC_PLATFORM_H +/** + * enum cc_attr - Confidential computing attributes + * + * These attributes represent confidential computing features that are + * currently active. + */ +enum cc_attr { + /** + * @CC_ATTR_MEM_ENCRYPT: Memory encryption is active + * + * The platform/OS is running with active memory encryption. This + * includes running either as a bare-metal system or a hypervisor + * and actively using memory encryption or as a guest/virtual machine + * and actively using memory encryption. + * + * Examples include SME, SEV and SEV-ES. + */ + CC_ATTR_MEM_ENCRYPT, + + /** + * @CC_ATTR_HOST_MEM_ENCRYPT: Host memory encryption is active + * + * The platform/OS is running as a bare-metal system or a hypervisor + * and actively using memory encryption. + * + * Examples include SME. + */ + CC_ATTR_HOST_MEM_ENCRYPT, + + /** + * @CC_ATTR_GUEST_MEM_ENCRYPT: Guest memory encryption is active + * + * The platform/OS is running as a guest/virtual machine and actively + * using memory encryption. + * + * Examples include SEV and SEV-ES. + */ + CC_ATTR_GUEST_MEM_ENCRYPT, + + /** + * @CC_ATTR_GUEST_STATE_ENCRYPT: Guest state encryption is active + * + * The platform/OS is running as a guest/virtual machine and actively + * using memory encryption and register state encryption. + * + * Examples include SEV-ES. + */ + CC_ATTR_GUEST_STATE_ENCRYPT, +}; + +static inline bool cc_platform_has(enum cc_attr attr) { return false; } + +#endif /* HAVE_LINUX_CC_PLATFORM_H */ +#endif From f08210ec8ecaff39c1df65b30be9cb9d4259686f Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 10 Feb 2022 13:22:14 +0800 Subject: [PATCH 0625/1868] drm/amdkcl: Test whether drm_firmware_drivers_only() is available Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/Makefile | 3 ++- .../gpu/drm/amd/amdkcl/kcl_drm_nomodeset.c | 25 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../amd/dkms/m4/drm_firmware_drivers_only.m4 | 16 ++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_drv.h | 4 +++ 6 files changed, 51 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_nomodeset.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_firmware_drivers_only.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index d18e0cbe51c9a..d268f4a39a272 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -12,7 +12,8 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_drm_crtc.o kcl_drm_connector.o kcl_drm_atomic_helper.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o kcl_ftrace.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_fs_read_write.o kcl_drm_aperture.o \ - kcl_drm_drv.o kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o + kcl_drm_drv.o kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o \ + kcl_drm_nomodeset.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_nomodeset.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_nomodeset.c new file mode 100644 index 0000000000000..c60ce331ebb3a --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_nomodeset.c @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0 + +#ifndef HAVE_DRM_FIRMWARE_DRIVERS_ONLY + +static bool drm_nomodeset; + +bool drm_firmware_drivers_only(void) +{ + return drm_nomodeset; +} +EXPORT_SYMBOL(drm_firmware_drivers_only); + +static int __init disable_modeset(char *str) +{ + drm_nomodeset = true; + + pr_warn("Booted with the nomodeset parameter. Only the system framebuffer will be available\n"); + + return 1; +} + +/* Disable kernel modesetting */ +__setup("nomodeset", disable_modeset); + +#endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index f4d2c57119971..a48a321e53f5e 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -518,6 +518,9 @@ /* drm_fb_helper_set_suspend_unlocked() is available */ #define HAVE_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED 1 +/* drm_firmware_drivers_only() is available */ +#define HAVE_DRM_FIRMWARE_DRIVERS_ONLY 1 + /* drm_format_info.block_w and rm_format_info.block_h is available */ #define HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_firmware_drivers_only.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_firmware_drivers_only.m4 new file mode 100644 index 0000000000000..b390e877bece7 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_firmware_drivers_only.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v5.16-rc1-268-g6a2d2ddf2c34 +dnl # drm: Move nomodeset kernel parameter to the DRM subsystem +dnl # +AC_DEFUN([AC_AMDGPU_DRM_FIRMWARE_DRIVERS_ONLY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_firmware_drivers_only(); + ], [ + AC_DEFINE(HAVE_DRM_FIRMWARE_DRIVERS_ONLY, 1, + [drm_firmware_drivers_only() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index dfa7db19e3895..90a78e5f4531e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -196,6 +196,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_GENERIC_HANDLE_DOMAIN_IRQ AC_AMDGPU__DMA_FENCE_IS_LATER AC_AMDGPU_PCI_IRQ_VECTOR + AC_AMDGPU_DRM_FIRMWARE_DRIVERS_ONLY AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_drv.h b/include/kcl/kcl_drm_drv.h index b4e923bfa1465..0360a07613727 100644 --- a/include/kcl/kcl_drm_drv.h +++ b/include/kcl/kcl_drm_drv.h @@ -63,4 +63,8 @@ static inline bool drm_dev_is_unplugged(struct drm_device *dev) #endif /* HAVE_DRM_DEV_IS_UNPLUGGED */ #endif /* HAVE_DRM_DEV_ENTER */ +#ifndef HAVE_DRM_FIRMWARE_DRIVERS_ONLY +extern bool drm_firmware_drivers_only(void); +#endif /* HAVE_DRM_FIRMWARE_DRIVERS_ONLY */ + #endif From 2101ac8aea08b0002a33ba8550dfa4037c2d669e Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 10 Feb 2022 14:00:35 +0800 Subject: [PATCH 0626/1868] drm/amdkcl: Test whether dma_resv_describe() is available Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/kcl_fence.c | 18 ++++++++++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../gpu/drm/amd/dkms/m4/dma-fence-describe.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_fence.h | 4 ++++ 5 files changed, 43 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/dma-fence-describe.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fence.c b/drivers/gpu/drm/amd/amdkcl/kcl_fence.c index 1376705d31822..1969d6e0f289c 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_fence.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fence.c @@ -244,3 +244,21 @@ void amdkcl_fence_init(void) _kcl_fence_default_wait_cb = amdkcl_fp_setup("fence_default_wait_cb", NULL); #endif } + +#if !defined(HAVE_DMA_FENCE_DESCRIBE) +/** + * dma_fence_describe - Dump fence describtion into seq_file + * @fence: the 6fence to describe + * @seq: the seq_file to put the textual description into + * + * Dump a textual description of the fence and it's state into the seq_file. + */ +void dma_fence_describe(struct dma_fence *fence, struct seq_file *seq) +{ + seq_printf(seq, "%s %s seq %llu %ssignalled\n", + fence->ops->get_driver_name(fence), + fence->ops->get_timeline_name(fence), fence->seqno, + dma_fence_is_signaled(fence) ? "" : "un"); +} +EXPORT_SYMBOL(dma_fence_describe); +#endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index a48a321e53f5e..7b584a3c027d1 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -91,6 +91,9 @@ /* dma_fence_chain_alloc() is available */ #define HAVE_DMA_FENCE_CHAIN_ALLOC 1 +/* dma_fence_describe() is available */ +#define HAVE_DMA_FENCE_DESCRIBE 1 + /* whether dma_fence_get_stub exits */ #define HAVE_DMA_FENCE_GET_STUB 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-fence-describe.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-fence-describe.m4 new file mode 100644 index 0000000000000..e82d65e149645 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dma-fence-describe.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # v5.15-rc2-1312-ga25efb3863d0 +dnl # dma-buf: add dma_fence_describe and dma_resv_describe v2 +dnl # +AC_DEFUN([AC_AMDGPU_DMA_FENCE_DESCRIBE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + dma_fence_describe(NULL, NULL); + ], [ + AC_DEFINE(HAVE_DMA_FENCE_DESCRIBE, 1, + [dma_fence_describe() is available]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 90a78e5f4531e..31a2b9a9fb03c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -197,6 +197,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU__DMA_FENCE_IS_LATER AC_AMDGPU_PCI_IRQ_VECTOR AC_AMDGPU_DRM_FIRMWARE_DRIVERS_ONLY + AC_AMDGPU_DMA_FENCE_DESCRIBE AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_fence.h b/include/kcl/kcl_fence.h index addd6733ff680..e8adf7bef1c57 100644 --- a/include/kcl/kcl_fence.h +++ b/include/kcl/kcl_fence.h @@ -186,4 +186,8 @@ bool _kcl_fence_enable_signaling(struct dma_fence *f); #define AMDKCL_DMA_FENCE_OPS_WAIT_OPTIONAL #endif +#if !defined(HAVE_DMA_FENCE_DESCRIBE) +void dma_fence_describe(struct dma_fence *fence, struct seq_file *seq); +#endif + #endif /* AMDKCL_FENCE_H */ From dc6b45b0204e09da1bcd9a46b8e3f41b4a993987 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 13 Jan 2022 12:39:35 +0800 Subject: [PATCH 0627/1868] drm/amdgpu: remove code access prime_shared_count field of struct amdgpu_bo commit "drm/amdgpu: rework dma_resv handling v3" removes the `prime_shared_count` field of struct amdgpu_bo Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 99 +++++++-------------- 1 file changed, 34 insertions(+), 65 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index 2eae529e2a6c7..9dc3c26f7f582 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -94,43 +94,43 @@ int amdgpu_gem_prime_mmap(struct drm_gem_object *obj, static int __dma_resv_make_exclusive(struct dma_resv *obj) { - struct dma_fence **fences; - unsigned int count; - int r; - - if (!dma_resv_shared_list(obj)) /* no shared fences to convert */ - return 0; - - r = dma_resv_get_fences(obj, NULL, &count, &fences); - if (r) - return r; - - if (count == 0) { - /* Now that was unexpected. */ - } else if (count == 1) { - dma_resv_add_excl_fence(obj, fences[0]); - dma_fence_put(fences[0]); - kfree(fences); - } else { - struct dma_fence_array *array; - - array = dma_fence_array_create(count, fences, - dma_fence_context_alloc(1), 0, - false); - if (!array) - goto err_fences_put; - - dma_resv_add_excl_fence(obj, &array->base); - dma_fence_put(&array->base); - } + struct dma_fence **fences; + unsigned int count; + int r; + + if (!dma_resv_shared_list(obj)) /* no shared fences to convert */ + return 0; + + r = dma_resv_get_fences(obj, NULL, &count, &fences); + if (r) + return r; + + if (count == 0) { + /* Now that was unexpected. */ + } else if (count == 1) { + dma_resv_add_excl_fence(obj, fences[0]); + dma_fence_put(fences[0]); + kfree(fences); + } else { + struct dma_fence_array *array; + + array = dma_fence_array_create(count, fences, + dma_fence_context_alloc(1), 0, + false); + if (!array) + goto err_fences_put; + + dma_resv_add_excl_fence(obj, &array->base); + dma_fence_put(&array->base); + } - return 0; + return 0; err_fences_put: - while (count--) - dma_fence_put(fences[count]); - kfree(fences); - return -ENOMEM; + while (count--) + dma_fence_put(fences[count]); + kfree(fences); + return -ENOMEM; } #if defined(HAVE_DMA_BUF_OPS_LEGACY) @@ -189,8 +189,6 @@ static int amdgpu_dma_buf_map_attach(struct dma_buf *dma_buf, if (r) goto error_unreserve; - if (attach->dev->driver != adev->dev->driver) - bo->prime_shared_count++; error_unreserve: amdgpu_bo_unreserve(bo); @@ -222,8 +220,6 @@ static void amdgpu_dma_buf_map_detach(struct dma_buf *dma_buf, goto error; amdgpu_bo_unpin(bo); - if (attach->dev->driver != adev->dev->driver && bo->prime_shared_count) - bo->prime_shared_count--; amdgpu_bo_unreserve(bo); error: @@ -250,24 +246,6 @@ static int amdgpu_dma_buf_attach(struct dma_buf *dmabuf, attach->peer2peer = false; #endif - r = amdgpu_bo_reserve(bo, false); - if (unlikely(r != 0)) - goto out; - - /* - * We only create shared fences for internal use, but importers - * of the dmabuf rely on exclusive fences for implicitly - * tracking write hazards. As any of the current fences may - * correspond to a write, we need to convert all existing - * fences on the reservation object into a single exclusive - * fence. - */ - r = __dma_resv_make_exclusive(amdkcl_ttm_resvp(&bo->tbo)); - if (r) - goto out; - - bo->prime_shared_count++; - amdgpu_bo_unreserve(bo); return 0; } @@ -604,11 +582,6 @@ amdgpu_gem_prime_import_sg_table(struct drm_device *dev, bo->tbo.ttm->sg = sg; bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT; bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT; -#if defined(AMDKCL_AMDGPU_DMABUF_OPS) - if (attach->dmabuf->ops != &amdgpu_dmabuf_ops) -#endif - bo->prime_shared_count = 1; - dma_resv_unlock(resv); return &bo->tbo.base; @@ -852,8 +825,6 @@ int amdgpu_gem_prime_pin(struct drm_gem_object *obj) /* pin buffer into GTT */ ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT); - if (likely(ret == 0)) - bo->prime_shared_count++; amdgpu_bo_unreserve(bo); return ret; @@ -869,8 +840,6 @@ void amdgpu_gem_prime_unpin(struct drm_gem_object *obj) return; amdgpu_bo_unpin(bo); - if (bo->prime_shared_count) - bo->prime_shared_count--; amdgpu_bo_unreserve(bo); } #endif From 1ca40acacd2c0783d03ebe0e6b931814b9816b0f Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Fri, 11 Feb 2022 11:01:14 +0800 Subject: [PATCH 0628/1868] drm/amdkfd: add removed amdgpu_amdkfd_get_vram_usage() function This is removed by v5.16-rc5-1294-gffb378fb3069 "drm/amdkfd: remove unused function" Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 6 ++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 1 + 2 files changed, 7 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c index f048553e4cdf4..6745d35a98789 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c @@ -561,6 +561,12 @@ int amdgpu_amdkfd_get_dmabuf_info(struct amdgpu_device *adev, int dma_buf_fd, return r; } +uint64_t amdgpu_amdkfd_get_vram_usage(struct amdgpu_device *adev) +{ + + return amdgpu_vram_mgr_usage(&adev->mman.vram_mgr); +} + uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct amdgpu_device *dst, struct amdgpu_device *src) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index ff8e5974b82e7..629a870e330ae 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -259,6 +259,7 @@ int amdgpu_amdkfd_get_dmabuf_info(struct amdgpu_device *adev, int dma_buf_fd, uint64_t *bo_size, void *metadata_buffer, size_t buffer_size, uint32_t *metadata_size, uint32_t *flags, int8_t *xcp_id); +uint64_t amdgpu_amdkfd_get_vram_usage(struct amdgpu_device *adev); uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct amdgpu_device *dst, struct amdgpu_device *src); int amdgpu_amdkfd_get_xgmi_bandwidth_mbytes(struct amdgpu_device *dst, From 603b7ce34b731b23836f2321ffe299d548bbb93f Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 15 Feb 2022 13:11:56 +0800 Subject: [PATCH 0629/1868] drm/amdkcl: Test whether drm_sysfs_connector_hotplug_event() is available Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_drm_sysfs.c | 44 +++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 ++ .../m4/drm-sysfs-connector-hotplug-event.m4 | 16 +++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_sysfs.h | 10 +++++ 7 files changed, 76 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_sysfs.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-sysfs-connector-hotplug-event.m4 create mode 100644 include/kcl/kcl_drm_sysfs.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index d268f4a39a272..30e4532c21b24 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -13,7 +13,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o kcl_ftrace.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_fs_read_write.o kcl_drm_aperture.o \ kcl_drm_drv.o kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o \ - kcl_drm_nomodeset.o + kcl_drm_nomodeset.o kcl_drm_sysfs.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_sysfs.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_sysfs.c new file mode 100644 index 0000000000000..5be759d09043b --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_sysfs.c @@ -0,0 +1,44 @@ +// SPDX-License-Identifier: GPL-2.0-only + +/* + * drm_sysfs.c - Modifications to drm_sysfs_class.c to support + * extra sysfs attribute from DRM. Normal drm_sysfs_class + * does not allow adding attributes. + * + * Copyright (c) 2004 Jon Smirl + * Copyright (c) 2003-2004 Greg Kroah-Hartman + * Copyright (c) 2003-2004 IBM Corp. + */ +#include +#include +#include +#include +#include + +#ifndef HAVE_DRM_SYSFS_CONNECTOR_HOTPLUG_EVENT +/** + * drm_sysfs_connector_hotplug_event - generate a DRM uevent for any connector + * change + * @connector: connector which has changed + * + * Send a uevent for the DRM connector specified by @connector. This will send + * a uevent with the properties HOTPLUG=1 and CONNECTOR. + */ +void drm_sysfs_connector_hotplug_event(struct drm_connector *connector) +{ + struct drm_device *dev = connector->dev; + char hotplug_str[] = "HOTPLUG=1", conn_id[21]; + char *envp[] = { hotplug_str, conn_id, NULL }; + + snprintf(conn_id, sizeof(conn_id), + "CONNECTOR=%u", connector->base.id); + + drm_dbg_kms(connector->dev, + "[CONNECTOR:%d:%s] generating connector hotplug event\n", + connector->base.id, connector->name); + + kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, envp); +} +EXPORT_SYMBOL(drm_sysfs_connector_hotplug_event); + +#endif diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 7e6a3520aa453..b8a8cb558937b 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -87,5 +87,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 7b584a3c027d1..b12a79b7f0b08 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -666,6 +666,9 @@ /* whether drm_syncobj_find_fence() wants 5 args */ #define HAVE_DRM_SYNCOBJ_FIND_FENCE_5ARGS 1 +/* drm_sysfs_connector_hotplug_event() function is available */ +#define HAVE_DRM_SYSFS_CONNECTOR_HOTPLUG_EVENT 1 + /* Define to 1 if you have the header file. */ #define HAVE_DRM_TASK_BARRIER_H 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-sysfs-connector-hotplug-event.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-sysfs-connector-hotplug-event.m4 new file mode 100644 index 0000000000000..3db7dabaf0b15 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-sysfs-connector-hotplug-event.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.15-rc2-1273-g0d6a8c5e9683 +dnl # drm/sysfs: introduce drm_sysfs_connector_hotplug_event +dnl # +AC_DEFUN([AC_AMDGPU_DRM_SYSFS_CONNECTOR_HOTPLUG_EVENT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_sysfs_connector_hotplug_event(NULL); + ], [ + AC_DEFINE(HAVE_DRM_SYSFS_CONNECTOR_HOTPLUG_EVENT, 1, + [drm_sysfs_connector_hotplug_event() function is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 31a2b9a9fb03c..500c4f3233285 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -198,6 +198,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_PCI_IRQ_VECTOR AC_AMDGPU_DRM_FIRMWARE_DRIVERS_ONLY AC_AMDGPU_DMA_FENCE_DESCRIBE + AC_AMDGPU_DRM_SYSFS_CONNECTOR_HOTPLUG_EVENT AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_sysfs.h b/include/kcl/kcl_drm_sysfs.h new file mode 100644 index 0000000000000..aaa27638d4659 --- /dev/null +++ b/include/kcl/kcl_drm_sysfs.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_DRM_SYSFS_H +#define AMDKCL_DRM_SYSFS_H + +struct drm_connector; +#ifndef HAVE_DRM_SYSFS_CONNECTOR_HOTPLUG_EVENT +void drm_sysfs_connector_hotplug_event(struct drm_connector *connector); +#endif + +#endif From fd18e5cd89678c756ab238b5942fc718c4b80be1 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 15 Feb 2022 13:50:54 +0800 Subject: [PATCH 0630/1868] drm/amdkcl: Test whether drm_kms_helper_connector_hotplug_event() is available This is cause by fc320a6f64044f12128519ca98404b641340d136 "amdgpu: use drm_kms_helper_connector_hotplug_event" v5.15-rc2-1276-gfc320a6f6404 Signed-off-by: Leslie Shi --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 16 ++++++++++++++++ .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 8 ++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../amd/dkms/m4/drm-kms-helper-hotplug-event.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 5 files changed, 44 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-kms-helper-hotplug-event.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index df830e4343f38..24350f7958889 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3690,7 +3690,11 @@ static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector) drm_modeset_unlock_all(dev); if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) +#ifdef HAVE_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT drm_kms_helper_connector_hotplug_event(connector); +#else + drm_kms_helper_hotplug_event(dev); +#endif } else { mutex_lock(&adev->dm.dc_lock); dc_exit_ips_for_hw_access(dc); @@ -3704,7 +3708,11 @@ static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector) drm_modeset_unlock_all(dev); if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) +#ifdef HAVE_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT drm_kms_helper_connector_hotplug_event(connector); +#else + drm_kms_helper_hotplug_event(dev); +#endif } } mutex_unlock(&aconnector->hpd_lock); @@ -3838,7 +3846,11 @@ static void handle_hpd_rx_irq(void *param) dm_restore_drm_connector_state(dev, connector); drm_modeset_unlock_all(dev); +#ifdef HAVE_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT drm_kms_helper_connector_hotplug_event(connector); +#else + drm_kms_helper_hotplug_event(dev); +#endif } else { bool ret = false; @@ -3857,7 +3869,11 @@ static void handle_hpd_rx_irq(void *param) dm_restore_drm_connector_state(dev, connector); drm_modeset_unlock_all(dev); +#ifdef HAVE_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT drm_kms_helper_connector_hotplug_event(connector); +#else + drm_kms_helper_hotplug_event(dev); +#endif } } } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index 500ab1469515b..49d7e84a8c339 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -1477,7 +1477,11 @@ static ssize_t trigger_hotplug(struct file *f, const char __user *buf, dm_restore_drm_connector_state(dev, connector); drm_modeset_unlock_all(dev); +#ifdef HAVE_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT drm_kms_helper_connector_hotplug_event(connector); +#else + drm_kms_helper_hotplug_event(dev); +#endif } else if (param[0] == 0) { if (!aconnector->dc_link) goto unlock; @@ -1503,7 +1507,11 @@ static ssize_t trigger_hotplug(struct file *f, const char __user *buf, dm_restore_drm_connector_state(dev, connector); drm_modeset_unlock_all(dev); +#ifdef HAVE_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT drm_kms_helper_connector_hotplug_event(connector); +#else + drm_kms_helper_hotplug_event(dev); +#endif } unlock: diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index b12a79b7f0b08..d3bc537e20173 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -578,6 +578,9 @@ /* drm_is_current_master() is available */ #define HAVE_DRM_IS_CURRENT_MASTER 1 +/* drm_kms_helper_connector_hotplug_event() function is available */ +#define HAVE_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT 1 + /* drm_kms_helper_is_poll_worker() is available */ #define HAVE_DRM_KMS_HELPER_IS_POLL_WORKER 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-kms-helper-hotplug-event.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-kms-helper-hotplug-event.m4 new file mode 100644 index 0000000000000..2bb2ec7fade6e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-kms-helper-hotplug-event.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.15-rc2-1274-g710074bb8ab0 +dnl # drm/probe-helper: add drm_kms_helper_connector_hotplug_event +dnl # +AC_DEFUN([AC_AMDGPU_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_kms_helper_connector_hotplug_event(NULL); + ], [ + AC_DEFINE(HAVE_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT, 1, + [drm_kms_helper_connector_hotplug_event() function is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 500c4f3233285..ce1ceae7f8f97 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -199,6 +199,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_FIRMWARE_DRIVERS_ONLY AC_AMDGPU_DMA_FENCE_DESCRIBE AC_AMDGPU_DRM_SYSFS_CONNECTOR_HOTPLUG_EVENT + AC_AMDGPU_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From a1d4e5ded7edcbfce1de78681cfb65a0fff729f3 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 17 Feb 2022 10:50:25 +0800 Subject: [PATCH 0631/1868] drm/amdkcl: fake macro MODULE_IMPORT_NS for legacy os Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_module.h | 18 ++++++++++++++++++ 2 files changed, 19 insertions(+) create mode 100644 include/kcl/kcl_module.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index b8a8cb558937b..b7a34ffd5527f 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -88,5 +88,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_module.h b/include/kcl/kcl_module.h new file mode 100644 index 0000000000000..2265f3bed4091 --- /dev/null +++ b/include/kcl/kcl_module.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Dynamic loading of modules into the kernel. + * + * Rewritten by Richard Henderson Dec 1996 + * Rewritten again by Rusty Russell, 2002 + */ +#ifndef _KCL_KCL_LINUX_MODULE_H_H +#define _KCL_KCL_LINUX_MODULE_H_H + +#include + +/* Copied from v5.3-11739-g3e4d890a26d5 include/linux/module.h */ +#ifndef MODULE_IMPORT_NS +#define MODULE_IMPORT_NS(ns) MODULE_INFO(import_ns, #ns) +#endif + +#endif From 9245e27908f840cd8298cc9445f460161e2f2529 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 17 Feb 2022 11:08:18 +0800 Subject: [PATCH 0632/1868] drm/amdkcl: wrap the code under HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE for legacy os This is caused by 5fea167ec0a13 "drm/amdkfd: use default_groups in kobj_type" v5.16-rc5-1299-g5fea167ec0a1 Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 12 ++++++++++++ drivers/gpu/drm/amd/amdkfd/kfd_process.c | 6 ++++++ 2 files changed, 18 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index ac108fca64fe6..de5adc9c3cf9d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -829,7 +829,9 @@ static struct ip_hw_instance_attr ip_hw_attr[] = { }; static struct attribute *ip_hw_instance_attrs[ARRAY_SIZE(ip_hw_attr) + 1]; +#ifdef HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE ATTRIBUTE_GROUPS(ip_hw_instance); +#endif #define to_ip_hw_instance(x) container_of(x, struct ip_hw_instance, kobj) #define to_ip_hw_instance_attr(x) container_of(x, struct ip_hw_instance_attr, attr) @@ -861,7 +863,11 @@ static void ip_hw_instance_release(struct kobject *kobj) static const struct kobj_type ip_hw_instance_ktype = { .release = ip_hw_instance_release, .sysfs_ops = &ip_hw_instance_sysfs_ops, +#ifdef HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE .default_groups = ip_hw_instance_groups, +#else + .default_attrs = ip_hw_instance_attrs, +#endif }; /* -------------------------------------------------- */ @@ -910,7 +916,9 @@ static struct attribute *ip_die_entry_attrs[] = { &num_ips_attr.attr, NULL, }; +#ifdef HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE ATTRIBUTE_GROUPS(ip_die_entry); /* ip_die_entry_groups */ +#endif #define to_ip_die_entry(x) container_of(to_kset(x), struct ip_die_entry, ip_kset) @@ -943,7 +951,11 @@ static const struct sysfs_ops ip_die_entry_sysfs_ops = { static const struct kobj_type ip_die_entry_ktype = { .release = ip_die_entry_release, .sysfs_ops = &ip_die_entry_sysfs_ops, +#ifdef HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE .default_groups = ip_die_entry_groups, +#else + .default_attrs = ip_die_entry_attrs, +#endif }; static const struct kobj_type die_kobj_ktype = { diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 2fb4efa2e5e24..fe1073273fa63 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -477,7 +477,9 @@ static struct attribute *procfs_queue_attrs[] = { &attr_queue_gpuid, NULL }; +#ifdef HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE ATTRIBUTE_GROUPS(procfs_queue); +#endif static const struct sysfs_ops procfs_queue_ops = { .show = kfd_procfs_queue_show, @@ -485,7 +487,11 @@ static const struct sysfs_ops procfs_queue_ops = { static const struct kobj_type procfs_queue_type = { .sysfs_ops = &procfs_queue_ops, +#ifdef HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE .default_groups = procfs_queue_groups, +#else + .default_attrs = procfs_queue_attrs, +#endif }; static const struct sysfs_ops procfs_stats_ops = { From 4df1379ea472fba86496d915c42f5d9c4d4588ba Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 21 Feb 2022 15:08:07 +0800 Subject: [PATCH 0633/1868] drm/amdkcl: access resv field using amdkcl_ttm_resvp Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 7313b29c048a0..45714eafe12b9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -1720,7 +1720,7 @@ static bool amdgpu_ttm_bo_eviction_valuable(struct ttm_buffer_object *bo, * If true, then return false as any KFD process needs all its BOs to * be resident to run successfully */ - dma_resv_for_each_fence(&resv_cursor, bo->base.resv, + dma_resv_for_each_fence(&resv_cursor, amdkcl_ttm_resvp(bo), DMA_RESV_USAGE_BOOKKEEP, f) { if (amdkfd_fence_check_mm(f, current->mm) && !(place->flags & TTM_PL_FLAG_CONTIGUOUS)) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 227418abede5f..32cd37c24189f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -351,7 +351,7 @@ void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base, if (!amdgpu_vm_is_bo_always_valid(vm, bo)) return; - dma_resv_assert_held(vm->root.bo->tbo.base.resv); + dma_resv_assert_held(amdkcl_ttm_resvp(&vm->root.bo->tbo)); ttm_bo_set_bulk_move(&bo->tbo, &vm->lru_bulk_move); if (bo->tbo.type == ttm_bo_type_kernel && bo->parent) @@ -1648,7 +1648,7 @@ struct amdgpu_bo_va *amdgpu_vm_bo_add(struct amdgpu_device *adev, if (!bo) return bo_va; - dma_resv_assert_held(bo->tbo.base.resv); + dma_resv_assert_held(amdkcl_ttm_resvp(&bo->tbo)); if (amdgpu_dmabuf_is_xgmi_accessible(adev, bo)) { bo_va->is_xgmi = true; /* Power up XGMI if it can be potentially used */ @@ -2074,10 +2074,10 @@ void amdgpu_vm_bo_del(struct amdgpu_device *adev, struct amdgpu_vm *vm = bo_va->base.vm; struct amdgpu_vm_bo_base **base; - dma_resv_assert_held(vm->root.bo->tbo.base.resv); + dma_resv_assert_held(amdkcl_ttm_resvp(&vm->root.bo->tbo)); if (bo) { - dma_resv_assert_held(bo->tbo.base.resv); + dma_resv_assert_held(amdkcl_ttm_resvp(&bo->tbo)); if (amdgpu_vm_is_bo_always_valid(vm, bo)) ttm_bo_set_bulk_move(&bo->tbo, NULL); From 3ea0f909a6b05dfa01b1ab0dd4ac4192b2fe5c57 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 21 Feb 2022 10:44:56 +0800 Subject: [PATCH 0634/1868] drm/amdkcl: replace with for_each_crtc_in_state for legacy os Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 24350f7958889..7480e41ff02b9 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -11781,7 +11781,11 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, goto fail; } +#if !defined(for_each_new_crtc_in_state) + for_each_crtc_in_state(state, crtc, new_crtc_state, i) { +#else for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { +#endif dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); if (dm_new_crtc_state->mpo_requested) drm_dbg_atomic(dev, "MPO enablement requested on crtc:[%p]\n", crtc); From 6eb3532cf9c8c46340b27b14c25ed430755d6e20 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 21 Feb 2022 12:51:08 +0800 Subject: [PATCH 0635/1868] drm/amdgpu: remove code accessing excl field This is caused by fa78e367a249 "drm/amdgpu: stop getting excl fence separately" v5.15-rc2-1366-gfa78e367a249 Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 514a784c83b9c..53604ac128c5b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -133,8 +133,6 @@ static void amdgpu_flip_work_func(struct work_struct *__work) int vpos, hpos, stat, min_udelay = 0; struct drm_vblank_crtc *vblank = &crtc->dev->vblank[work->crtc_id]; - if (amdgpu_display_flip_handle_fence(work, &work->excl)) - return; for (i = 0; i < work->shared_count; ++i) if (amdgpu_display_flip_handle_fence(work, &work->shared[i])) @@ -455,7 +453,7 @@ int amdgpu_crtc_page_flip(struct drm_crtc *crtc, goto unreserve; } - r = dma_resv_get_fences(amdkcl_ttm_resvp(&new_abo->tbo), &work->excl, + r = dma_resv_get_fences(amdkcl_ttm_resvp(&new_abo->tbo), NULL, &work->shared_count, &work->shared); if (unlikely(r != 0)) { @@ -511,7 +509,6 @@ int amdgpu_crtc_page_flip(struct drm_crtc *crtc, cleanup: amdgpu_bo_unref(&work->old_abo); - fence_put(work->excl); for (i = 0; i < work->shared_count; ++i) fence_put(work->shared[i]); kfree(work->shared); From 86b3ff5dc65a26adfdc9a503e2bf8c8d49629cc6 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 22 Feb 2022 17:16:40 +0800 Subject: [PATCH 0636/1868] drm/amdkcl: Test whether pcie_aspm_enabled() is available Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/pcie-aspm-enabled.m4 | 16 ++++++++++++++++ 4 files changed, 24 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/pcie-aspm-enabled.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 1092a54474113..83ef84052ddbf 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -1753,7 +1753,11 @@ bool amdgpu_device_should_use_aspm(struct amdgpu_device *adev) return false; if (!(adev->pm.pp_feature & PP_PCIE_DPM_MASK)) return false; +#ifdef HAVE_PCIE_ASPM_ENABLED return pcie_aspm_enabled(adev->pdev); +#else + return false; +#endif } /* if we get transitioned to only one device, take VGA back */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index d3bc537e20173..f3023dbd85820 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -933,6 +933,9 @@ /* num_u32_u32 is available */ #define HAVE_MUL_U32_U32 1 +/* pcie_aspm_enabled() is available */ +#define HAVE_PCIE_ASPM_ENABLED 1 + /* pcie_bandwidth_available() is available */ #define HAVE_PCIE_BANDWIDTH_AVAILABLE 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index ce1ceae7f8f97..febb6fafb2128 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -200,6 +200,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DMA_FENCE_DESCRIBE AC_AMDGPU_DRM_SYSFS_CONNECTOR_HOTPLUG_EVENT AC_AMDGPU_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT + AC_AMDGPU_PCIE_ASPM_ENABLED AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/pcie-aspm-enabled.m4 b/drivers/gpu/drm/amd/dkms/m4/pcie-aspm-enabled.m4 new file mode 100644 index 0000000000000..32927a35d28f5 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pcie-aspm-enabled.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v5.3-rc4-1-gaccd2dd72c8f +dnl # PCI/ASPM: Add pcie_aspm_enabled() +dnl # +AC_DEFUN([AC_AMDGPU_PCIE_ASPM_ENABLED], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + pcie_aspm_enabled(NULL); + ], [ + AC_DEFINE(HAVE_PCIE_ASPM_ENABLED, 1, + [pcie_aspm_enabled() is available]) + ]) + ]) +]) From 0f0028e9deefd0498c01242bcd3e3d2a1d3413ff Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Mon, 21 Feb 2022 16:24:22 +0800 Subject: [PATCH 0637/1868] drm/amdkcl: Implement drm_WARN_ONCE for older versions of kernel Implement drm_WARN_ONCE function for older versions of kernel Otherwise,there are compile errors. Signed-off-by: Ma Jun Reviewed-by: Flora Cui Change-Id: I4c85aa289dad6577bf04e7d1a5069af833b7a641 --- include/kcl/kcl_drm_print.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index d92e4744fea4b..a7ef405b97cdc 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -93,6 +93,13 @@ void drm_mm_print(const struct drm_mm *mm, struct drm_printer *p) _DRM_PRINTK(_once, WARNING, fmt, ##__VA_ARGS__) #endif +#ifndef drm_WARN_ONCE +#define drm_WARN_ONCE(drm, condition, format, arg...) \ + WARN_ONCE(condition, "%s %s: " format, \ + dev_driver_string((drm)->dev), \ + dev_name((drm)->dev), ## arg) +#endif + #ifndef DRM_NOTE #define DRM_NOTE(fmt, ...) \ _DRM_PRINTK(, NOTICE, fmt, ##__VA_ARGS__) From a19098f890fcb13d64e652c5538440ea2c2c0921 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 23 Feb 2022 10:15:32 +0800 Subject: [PATCH 0638/1868] drm/amdkcl: Test whether linux/processor.h is available Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 | 6 ++++++ include/kcl/header/linux/processor.h | 10 ++++++++++ 3 files changed, 19 insertions(+) create mode 100644 include/kcl/header/linux/processor.h diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index f3023dbd85820..4d5862b92bb59 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -870,6 +870,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_PGTABLE_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_PROCESSOR_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_LINUX_SCHED_MM_H 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 index 7b2aa10060569..203f810772d52 100644 --- a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 @@ -102,4 +102,10 @@ AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ dnl # arch/cc: Introduce a function to check for confidential computing features dnl # AC_KERNEL_CHECK_HEADERS([linux/cc_platform.h]) + + dnl # + dnl # v4.12-rc3-120-gfd851a3cdc19 + dnl # spin loop primitives for busy waiting + dnl # + AC_KERNEL_CHECK_HEADERS([linux/processor.h]) ]) diff --git a/include/kcl/header/linux/processor.h b/include/kcl/header/linux/processor.h new file mode 100644 index 0000000000000..873ab8368cb12 --- /dev/null +++ b/include/kcl/header/linux/processor.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_LINUX_PROCESSOR_H_H +#define _KCL_HEADER_LINUX_PROCESSOR_H_H + +#if defined(HAVE_LINUX_PROCESSOR_H) +#include_next +#endif + +#endif + From 1765951ab0d3fd400aea68c369de1d3f9d26b3b6 Mon Sep 17 00:00:00 2001 From: Shiwu Zhang Date: Tue, 2 Mar 2021 14:19:40 +0800 Subject: [PATCH 0639/1868] Revert "drm/amd/display: Clean up GFX9 tiling_flags path." This reverts commit 9a33e8819b346864f58d31cf6b60096fd681801b. Change-Id: I19c672532bf23ddc3090b90f7c3c6749ffa2e5b7 Signed-off-by: Shiwu Zhang --- .../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 74 +++++++++++++++++-- 1 file changed, 67 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 957e1e59ba668..851a175923b32 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -304,6 +304,55 @@ static int amdgpu_dm_plane_validate_dcc(struct amdgpu_device *adev, return 0; } +static void +fill_dcc_params_from_flags(const struct amdgpu_framebuffer *afb, + struct dc_plane_dcc_param *dcc, + struct dc_plane_address *address, + const uint64_t flags, bool force_disable_dcc) +{ + uint64_t dcc_address; + uint64_t plane_address = afb->address + afb->base.offsets[0]; + uint32_t offset = AMDGPU_TILING_GET(flags, DCC_OFFSET_256B); + uint32_t i64b = AMDGPU_TILING_GET(flags, DCC_INDEPENDENT_64B) != 0; + + if (!offset || force_disable_dcc) + return; + + dcc->enable = 1; + dcc->meta_pitch = AMDGPU_TILING_GET(flags, DCC_PITCH_MAX) + 1; + dcc->independent_64b_blks = i64b; + + dcc_address = plane_address + (uint64_t)offset * 256; + address->grph.meta_addr.low_part = lower_32_bits(dcc_address); + address->grph.meta_addr.high_part = upper_32_bits(dcc_address); +} + +static int +fill_gfx9_plane_attributes_from_flags(struct amdgpu_device *adev, + const struct amdgpu_framebuffer *afb, + const enum surface_pixel_format format, + const enum dc_rotation_angle rotation, + const struct plane_size *plane_size, + union dc_tiling_info *tiling_info, + struct dc_plane_dcc_param *dcc, + struct dc_plane_address *address, + uint64_t tiling_flags, + bool force_disable_dcc) +{ + int ret; + + fill_gfx9_tiling_info_from_device(adev, tiling_info); + + tiling_info->gfx9.swizzle = + AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE); + + fill_dcc_params_from_flags(afb, dcc, address, tiling_flags, force_disable_dcc); + ret = validate_dcc(adev, format, rotation, tiling_info, dcc, address, plane_size); + if (ret) + return ret; + + return 0; +} #ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED static int amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers(struct amdgpu_device *adev, @@ -925,13 +974,24 @@ int amdgpu_dm_plane_fill_plane_buffer_attributes(struct amdgpu_device *adev, return ret; } else if (adev->family >= AMDGPU_FAMILY_AI) { #ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED - ret = amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers(adev, afb, format, - rotation, plane_size, - tiling_info, dcc, - address, - force_disable_dcc); - if (ret) - return ret; + if (afb->base.flags & DRM_MODE_FB_MODIFIERS) { + ret = amdgpu_dm_plane_fill_gfx9_plane_attributes_from_modifiers(adev, afb, format, + rotation, plane_size, + tiling_info, dcc, + address, + force_disable_dcc); + if (ret) + return ret; + } else { +#endif + ret = fill_gfx9_plane_attributes_from_flags(adev, afb, format, rotation, + plane_size, tiling_info, dcc, + address, tiling_flags, + force_disable_dcc); + if (ret) + return ret; +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED + } #endif } else { amdgpu_dm_plane_fill_gfx8_tiling_info_from_flags(tiling_info, tiling_flags); From fb551db64220d346303ad12fbbcae75c0e5f1ebe Mon Sep 17 00:00:00 2001 From: Ramesh Errabolu Date: Wed, 9 Feb 2022 17:07:22 -0600 Subject: [PATCH 0640/1868] drm/amdkfd: Protect BO during acquisition of its IPC handle Ensure the process of acquiring IPC handle of a BO is safe i.e. BO is not exposed from being destroyed. This is done by serializing user accesses to BO's of a process Signed-off-by: Ramesh Errabolu Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_ipc.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c index c1f5f7dc6c5d7..1e3d9af012651 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c @@ -241,30 +241,33 @@ int kfd_ipc_export_as_handle(struct kfd_dev *dev, struct kfd_process *p, if (!dev || !ipc_handle) return -EINVAL; + /* Protect kgd_mem object from being deleted by another thread */ mutex_lock(&p->mutex); pdd = kfd_bind_process_to_device(dev, p); if (IS_ERR(pdd)) { - mutex_unlock(&p->mutex); pr_err("Failed to get pdd\n"); - return PTR_ERR(pdd); + r = PTR_ERR(pdd); + goto unlock; } kfd_bo = kfd_process_device_find_bo(pdd, GET_IDR_HANDLE(handle)); - mutex_unlock(&p->mutex); if (!kfd_bo) { pr_err("Failed to get bo"); - return -EINVAL; + r = -EINVAL; + goto unlock; } mem = (struct kgd_mem *)kfd_bo->mem; r = amdgpu_amdkfd_gpuvm_export_ipc_obj(dev->adev, pdd->drm_priv, mem, &ipc_obj, flags); if (r) - return r; + goto unlock; memcpy(ipc_handle, ipc_obj->share_handle, sizeof(ipc_obj->share_handle)); +unlock: + mutex_unlock(&p->mutex); return r; } From a514bcff348db786135876adcb51e25e31bf2aa4 Mon Sep 17 00:00:00 2001 From: Rui Teng Date: Mon, 28 Feb 2022 16:08:43 +0800 Subject: [PATCH 0641/1868] drm/amdkcl: Bump AMDGPU version to 5.16.0 Signed-off-by: Rui Teng Change-Id: I708952a593cbd3205227c065e98f4fee4add4a01 --- drivers/gpu/drm/amd/dkms/configure.ac | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/configure.ac b/drivers/gpu/drm/amd/dkms/configure.ac index 71855ccd6e523..3feca735c2140 100644 --- a/drivers/gpu/drm/amd/dkms/configure.ac +++ b/drivers/gpu/drm/amd/dkms/configure.ac @@ -1,4 +1,4 @@ -AC_INIT(amdgpu-dkms, 5.13.5) +AC_INIT(amdgpu-dkms, 5.16.0) AC_LANG(C) AC_CONFIG_AUX_DIR([config]) From 0716998bb291c5d6b109bba1f4435e95000e968b Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 7 Feb 2022 16:34:52 +0800 Subject: [PATCH 0642/1868] drm/amdkcl: rework drm_aperture_remove_conflicting_pci_framebuffers() Signed-off-by: Flora Cui Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c | 153 ++---------------- drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c | 70 +++----- drivers/gpu/drm/amd/amdkcl/kcl_fbmem.h | 38 +++++ drivers/gpu/drm/amd/dkms/config/config.h | 22 +-- ...per-remove-conflicting-pci-framebuffers.m4 | 57 ------- ...ure_remove_conflicting_pci_framebuffers.m4 | 38 +++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 3 +- .../m4/remove-conflicting-pci-framebuffers.m4 | 28 ---- include/kcl/backport/kcl_drm_fb.h | 4 - include/kcl/kcl_drm_aperture.h | 8 - include/kcl/kcl_drm_fb.h | 57 ------- 11 files changed, 118 insertions(+), 360 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_fbmem.h delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-remove-conflicting-pci-framebuffers.m4 create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_aperture_remove_conflicting_pci_framebuffers.m4 delete mode 100644 drivers/gpu/drm/amd/dkms/m4/remove-conflicting-pci-framebuffers.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c index c597046dee062..91f2508079ff1 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_aperture.c @@ -3,153 +3,28 @@ #ifndef HAVE_DRM_DRM_APERTURE_H #include -#include #include -#include -#include -#include - -struct drm_aperture { - struct drm_device *dev; - resource_size_t base; - resource_size_t size; - struct list_head lh; - void (*detach)(struct drm_device *dev); -}; - -static LIST_HEAD(drm_apertures); -static DEFINE_MUTEX(drm_apertures_lock); - -static bool overlap(resource_size_t base1, resource_size_t end1, - resource_size_t base2, resource_size_t end2) -{ - return (base1 < end2) && (end1 > base2); -} - - -static void drm_aperture_detach_drivers(resource_size_t base, resource_size_t size) -{ - resource_size_t end = base + size; - struct list_head *pos, *n; - - mutex_lock(&drm_apertures_lock); - list_for_each_safe(pos, n, &drm_apertures) { - struct drm_aperture *ap = - container_of(pos, struct drm_aperture, lh); - struct drm_device *dev = ap->dev; - - if (WARN_ON_ONCE(!dev)) - continue; - - if (!overlap(base, end, ap->base, ap->base + ap->size)) - continue; - - ap->dev = NULL; /* detach from device */ - list_del(&ap->lh); - - ap->detach(dev); - } - - mutex_unlock(&drm_apertures_lock); -} - - -/** - * drm_aperture_remove_conflicting_framebuffers - remove existing framebuffers in the given range - * @base: the aperture's base address in physical memory - * @size: aperture size in bytes - * @primary: also kick vga16fb if present - * @name: requesting driver name - * - * This function removes graphics device drivers which use memory range described by - * @base and @size. - * - * Returns: - * 0 on success, or a negative errno code otherwise - */ -int drm_aperture_remove_conflicting_framebuffers(resource_size_t base, resource_size_t size, - bool primary, const char *name) -{ -#if IS_REACHABLE(CONFIG_FB) - struct apertures_struct *a; - int ret; - - a = alloc_apertures(1); - if (!a) - return -ENOMEM; - - a->ranges[0].base = base; - a->ranges[0].size = size; - - ret = remove_conflicting_framebuffers(a, name, primary); - kfree(a); - - if (ret) - return ret; -#endif - - drm_aperture_detach_drivers(base, size); - - return 0; -} -EXPORT_SYMBOL(drm_aperture_remove_conflicting_framebuffers); +#include +#include +#include "kcl_fbmem.h" -/** - * drm_aperture_remove_conflicting_pci_framebuffers - remove existing framebuffers for PCI devices - * @pdev: PCI device - * @name: requesting driver name - * - * This function removes graphics device drivers using memory range configured - * for any of @pdev's memory bars. The function assumes that PCI device with - * shadowed ROM drives a primary display and so kicks out vga16fb. - * - * Returns: - * 0 on success, or a negative errno code otherwise - */ -#ifdef HAVE_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ARG -int drm_aperture_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, - const struct drm_driver *req_driver) -#else int drm_aperture_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, const char *name) -#endif { - resource_size_t base, size; - int bar, ret = 0; + int ret = 0; - for (bar = 0; bar < PCI_STD_NUM_BARS; ++bar) { - if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) - continue; - base = pci_resource_start(pdev, bar); - size = pci_resource_len(pdev, bar); - drm_aperture_detach_drivers(base, size); - } - - /* - * WARNING: Apparently we must kick fbdev drivers before vgacon, - * otherwise the vga fbdev driver falls over. - */ - -#ifdef HAVE_VGA_REMOVE_VGACON + /* + * WARNING: Apparently we must kick fbdev drivers before vgacon, + * otherwise the vga fbdev driver falls over. + */ #if IS_REACHABLE(CONFIG_FB) - -#ifdef HAVE_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ARG - ret = remove_conflicting_pci_framebuffers(pdev, req_driver->name); -#else -#ifdef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_NO_RES_ID_ARG - ret = remove_conflicting_pci_framebuffers(pdev, name); -#else - ret = remove_conflicting_pci_framebuffers(pdev, 0, name); + ret = _kcl_remove_conflicting_pci_framebuffers(pdev, name); #endif -#endif /* HAVE_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ARG */ - -#endif - if (ret == 0) - ret = vga_remove_vgacon(pdev); +#ifdef HAVE_VGA_REMOVE_VGACON + if (ret == 0) + ret = vga_remove_vgacon(pdev); #endif - - return ret; + return ret; } EXPORT_SYMBOL(drm_aperture_remove_conflicting_pci_framebuffers); - -#endif /* HAVE_DRM_APERTURE_H */ +#endif /* HAVE_DRM_DRM_APERTURE_H */ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c b/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c index 742edcc32b042..eae1bf4134541 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c @@ -14,71 +14,43 @@ #include /* Copied from drivers/video/fbdev/core/fbmem.c and modified for KCL */ -#if !defined(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS) - -#ifdef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_NO_RES_ID_ARG +#if !defined(HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS) int remove_conflicting_pci_framebuffers(struct pci_dev *pdev, const char *name) -{ - struct apertures_struct *ap; - bool primary = false; - int err, idx, bar; - - for (idx = 0, bar = 0; bar < PCI_STD_NUM_BARS; bar++) { - if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) - continue; - idx++; - } - - ap = alloc_apertures(idx); - if (!ap) - return -ENOMEM; - - for (idx = 0, bar = 0; bar < PCI_STD_NUM_BARS; bar++) { - if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) - continue; - ap->ranges[idx].base = pci_resource_start(pdev, bar); - ap->ranges[idx].size = pci_resource_len(pdev, bar); - pci_dbg(pdev, "%s: bar %d: 0x%lx -> 0x%lx\n", __func__, bar, - (unsigned long)pci_resource_start(pdev, bar), - (unsigned long)pci_resource_end(pdev, bar)); - idx++; - } - -#ifdef CONFIG_X86 - primary = pdev->resource[PCI_ROM_RESOURCE].flags & - IORESOURCE_ROM_SHADOW; -#endif - err = remove_conflicting_framebuffers(ap, name, primary); - kfree(ap); - return err; -} -#else /* HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_NO_RES_ID_ARG */ -int remove_conflicting_pci_framebuffers(struct pci_dev *pdev, int res_id, const char *name) { struct apertures_struct *ap; bool primary = false; - int err = 0; + int err, idx, bar; + + for (idx = 0, bar = 0; bar < PCI_ROM_RESOURCE; bar++) { + if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) + continue; + idx++; + } - ap = alloc_apertures(1); + ap = alloc_apertures(idx); if (!ap) return -ENOMEM; - ap->ranges[0].base = pci_resource_start(pdev, res_id); - ap->ranges[0].size = pci_resource_len(pdev, res_id); + for (idx = 0, bar = 0; bar < PCI_ROM_RESOURCE; bar++) { + if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) + continue; + ap->ranges[idx].base = pci_resource_start(pdev, bar); + ap->ranges[idx].size = pci_resource_len(pdev, bar); + dev_dbg(&pdev->dev, "%s: bar %d: 0x%lx -> 0x%lx\n", __func__, bar, + (unsigned long)pci_resource_start(pdev, bar), + (unsigned long)pci_resource_end(pdev, bar)); + idx++; + } + #ifdef CONFIG_X86 primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW; #endif -#ifdef HAVE_REMOVE_CONFLICTING_FRAMEBUFFERS_RETURNS_INT err = remove_conflicting_framebuffers(ap, name, primary); -#else - remove_conflicting_framebuffers(ap, name, primary); -#endif kfree(ap); return err; } -#endif /* HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_NO_RES_ID_ARG */ - +EXPORT_SYMBOL(remove_conflicting_pci_framebuffers); #endif #ifndef HAVE_IS_FIRMWARE_FRAMEBUFFER diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.h b/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.h new file mode 100644 index 0000000000000..de4bdea92fa7f --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _AMDKCL_KCL_FBMEM_H_ +#define _AMDKCL_KCL_FBMEM_H_ + +#include +#include + +/* Copied from include/linux/fb.h */ +#if !defined(HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS) +extern int remove_conflicting_pci_framebuffers(struct pci_dev *pdev, + const char *name); +#endif +static inline +int _kcl_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, + const char *name) +{ +#ifdef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PIP + /** + * v5.1-rc3-20-gb0e999c95581 fbdev: list all pci memory bars as conflicting apertures + * handle bar 0 directly. + * as remove_conflicting_pci_framebuffers() for bar 2/5 fails on rhel7.9 + int bar, err; + + for (bar = 0; bar < PCI_ROM_RESOURCE; bar++) { + if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) + continue; + err = remove_conflicting_pci_framebuffers(pdev, bar, name); + if (err) + return err; + } + */ + pr_warn_once("remove conflicting pci framebuffers on bar 0\n"); + return remove_conflicting_pci_framebuffers(pdev, 0, name); +#else + return remove_conflicting_pci_framebuffers(pdev, name); +#endif +} +#endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 4d5862b92bb59..c9d73d317b8d2 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -509,15 +509,6 @@ /* whether drm_fb_helper_lastclose() is available */ #define HAVE_DRM_FB_HELPER_LASTCLOSE 1 -/* drm_fb_helper_remove_conflicting_pci_framebuffers() is available */ -/* #undef HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS */ - -/* drm_fb_helper_remove_conflicting_pci_framebuffers() wants p,i,p args */ -/* #undef HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PIP */ - -/* drm_fb_helper_remove_conflicting_pci_framebuffers() wants p,p args */ -/* #undef HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP */ - /* drm_fb_helper_set_suspend_unlocked() is available */ #define HAVE_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED 1 @@ -990,15 +981,14 @@ /* pxm_to_node() is available */ #define HAVE_PXM_TO_NODE 1 -/* remove_conflicting_framebuffers() returns int */ -#define HAVE_REMOVE_CONFLICTING_FRAMEBUFFERS_RETURNS_INT 1 +/* remove_conflicting_pci_framebuffers() is available */ +/* #undef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS */ -/* remove_conflicting_pci_framebuffers() is available and doesn't have res_id - arg */ -#define HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_NO_RES_ID_ARG 1 +/* remove_conflicting_pci_framebuffers() wants p,i,p args */ +/* #undef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PIP */ -/* remove_conflicting_pci_framebuffers() is available and has res_id arg */ -/* #undef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_WITH_RES_ID_ARG */ +/* remove_conflicting_pci_framebuffers() wants p,p args */ +/* #undef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP */ /* request_firmware_direct() is available */ #define HAVE_REQUEST_FIRMWARE_DIRECT 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-remove-conflicting-pci-framebuffers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-remove-conflicting-pci-framebuffers.m4 deleted file mode 100644 index ee6e915098f5c..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-remove-conflicting-pci-framebuffers.m4 +++ /dev/null @@ -1,57 +0,0 @@ -dnl # -dnl # commit v5.3-rc1-541-g35616a4aa919 -dnl # fbdev: drop res_id parameter from remove_conflicting_pci_framebuffers -dnl # -AC_DEFUN([AC_AMDGPU_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DRMP_H - struct vm_area_struct; - #include - #endif - #include - ], [ - drm_fb_helper_remove_conflicting_pci_framebuffers(NULL, NULL); - ], [ - AC_DEFINE(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP, 1, - [drm_fb_helper_remove_conflicting_pci_framebuffers() wants p,p args]) - AC_DEFINE(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS, 1, - [drm_fb_helper_remove_conflicting_pci_framebuffers() is available]) - ], [ - dnl # - dnl # commit v4.19-rc1-110-g4d18975c78f2 - dnl # Author: Michał Mirosław - dnl # Date: Sat Sep 1 16:08:45 2018 +0200 - dnl # fbdev: add remove_conflicting_pci_framebuffers() - dnl # - AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DRMP_H - struct vm_area_struct; - #include - #endif - #include - ], [ - drm_fb_helper_remove_conflicting_pci_framebuffers(NULL, 0, NULL); - ], [ - AC_DEFINE(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PIP, 1, - [drm_fb_helper_remove_conflicting_pci_framebuffers() wants p,i,p args]) - AC_DEFINE(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS, 1, - [drm_fb_helper_remove_conflicting_pci_framebuffers() is available]) - ], [ - dnl # - dnl # commit 46eeb2c144956e88197439b5ee5cf221a91b0a81 - dnl # video/fb: Propagate error code from failing to unregister conflicting fb - dnl # - AC_KERNEL_TRY_COMPILE_SYMBOL([ - struct task_struct; - #include - ], [ - int ret = remove_conflicting_framebuffers(NULL, NULL, false); - ], [remove_conflicting_framebuffers], [drivers/video/fbdev/core/fbmem.c], [ - AC_DEFINE(HAVE_REMOVE_CONFLICTING_FRAMEBUFFERS_RETURNS_INT, 1, - [remove_conflicting_framebuffers() returns int]) - ]) - ]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_aperture_remove_conflicting_pci_framebuffers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_aperture_remove_conflicting_pci_framebuffers.m4 new file mode 100644 index 0000000000000..50e28229344bf --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_aperture_remove_conflicting_pci_framebuffers.m4 @@ -0,0 +1,38 @@ +dnl # +dnl # v5.12-rc3-332-g603dc7ed917f drm/aperture: Inline fbdev conflict helpers into aperture helpers +dnl # v5.12-rc3-330-g2916059147ea drm/aperture: Add infrastructure for aperture ownership +dnl # +AC_DEFUN([AC_AMDGPU_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS], [ + AC_KERNEL_DO_BACKGROUND([ + AS_IF([test x$HAVE_DRM_DRM_APERTURE_H = x ], [ + dnl # + dnl # v5.3-rc1-540-g0a8459693238 fbdev: drop res_id parameter from remove_conflicting_pci_framebuffers + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + remove_conflicting_pci_framebuffers(NULL, NULL); + ], [ + AC_DEFINE(HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP, 1, + [remove_conflicting_pci_framebuffers() wants p,p args]) + AC_DEFINE(HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS, 1, + [remove_conflicting_pci_framebuffers() is available]) + ], [ + dnl # + dnl # v4.19-rc1-110-g4d18975c78f2 fbdev: add remove_conflicting_pci_framebuffers() + dnl # + AC_KERNEL_TRY_COMPILE([ + struct task_struct; + #include + ], [ + remove_conflicting_pci_framebuffers(NULL, 0, NULL); + ], [ + AC_DEFINE(HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PIP, 1, + [remove_conflicting_pci_framebuffers() wants p,i,p args]) + AC_DEFINE(HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS, 1, + [remove_conflicting_pci_framebuffers() is available]) + ]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index febb6fafb2128..4f2e7dbc2f27f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -72,7 +72,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CACHE AC_AMDGPU_DRM_DEBUG_ENABLED AC_AMDGPU_DRM_GEM_OBJECT_PUT_UNLOCKED - AC_AMDGPU_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS + AC_AMDGPU_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS AC_AMDGPU_DRM_CONNECTOR_INIT_WITH_DDC AC_AMDGPU_DRM_DP_CALC_PBN_MODE AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS @@ -165,7 +165,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_ATOMIC_HDR_METADATA_EQUAL AC_AMDGPU_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY AC_AMDGPU_DRM_CONNECTOR_STATE_HDR_OUTPUT_METADATA - AC_AMDGPU_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS AC_AMDGPU_DRM_DEV_ENTER AC_AMDGPU_DRM_DEV_IS_UNPLUGGED AC_AMDGPU_DRM_DEVICE_PDEV diff --git a/drivers/gpu/drm/amd/dkms/m4/remove-conflicting-pci-framebuffers.m4 b/drivers/gpu/drm/amd/dkms/m4/remove-conflicting-pci-framebuffers.m4 deleted file mode 100644 index bde011042303f..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/remove-conflicting-pci-framebuffers.m4 +++ /dev/null @@ -1,28 +0,0 @@ -dnl # -dnl # v5.3-rc1-540-g0a8459693238 -dnl # fbdev: drop res_id parameter from remove_conflicting_pci_framebuffers -dnl # -AC_DEFUN([AC_AMDGPU_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - struct task_struct; - #include - ],[ - remove_conflicting_pci_framebuffers(NULL, NULL); - ],[ - AC_DEFINE(HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_NO_RES_ID_ARG, 1, - [remove_conflicting_pci_framebuffers() is available and doesn't have res_id arg]) - ],[ - AC_KERNEL_TRY_COMPILE([ - struct task_struct; - #include - ], [ - remove_conflicting_pci_framebuffers(NULL, 0, NULL); - ], [ - AC_DEFINE(HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_WITH_RES_ID_ARG, 1, - [remove_conflicting_pci_framebuffers() is available and has res_id arg]) - ]) - ]) - ]) -]) - diff --git a/include/kcl/backport/kcl_drm_fb.h b/include/kcl/backport/kcl_drm_fb.h index 662d312577d93..f1d242ac9d61f 100644 --- a/include/kcl/backport/kcl_drm_fb.h +++ b/include/kcl/backport/kcl_drm_fb.h @@ -25,10 +25,6 @@ #include #include -#if !defined(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP) -#define drm_fb_helper_remove_conflicting_pci_framebuffers _kcl_drm_fb_helper_remove_conflicting_pci_framebuffers -#endif - #ifndef HAVE_DRM_HELPER_MODE_FILL_FB_STRUCT_DEV static inline void _kcl_drm_helper_mode_fill_fb_struct(struct drm_device *dev, diff --git a/include/kcl/kcl_drm_aperture.h b/include/kcl/kcl_drm_aperture.h index e1af88ce1ba85..d4ca18d5c1792 100644 --- a/include/kcl/kcl_drm_aperture.h +++ b/include/kcl/kcl_drm_aperture.h @@ -6,18 +6,10 @@ #include -/* Copied from uapi/linux/pci_regs.h */ -#ifndef PCI_STD_NUM_BARS -#define PCI_STD_NUM_BARS 6 -#endif - /* Copied from drm/drm_aperture.h */ struct drm_device; struct pci_dev; -int drm_aperture_remove_conflicting_framebuffers(resource_size_t base, resource_size_t size, - bool primary, const char *name); - int drm_aperture_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, const char *name); #endif /* HAVE_DRM_DRM_APERTURE_H */ diff --git a/include/kcl/kcl_drm_fb.h b/include/kcl/kcl_drm_fb.h index 56361a8b43ebd..392638c78018c 100644 --- a/include/kcl/kcl_drm_fb.h +++ b/include/kcl/kcl_drm_fb.h @@ -55,63 +55,6 @@ .fb_pan_display = drm_fb_helper_pan_display #endif -#if !defined(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS) -#if !defined(IS_REACHABLE) -/* Copied from include/linux/kconfig.h */ -#define __ARG_PLACEHOLDER_1 0, -#define __take_second_arg(__ignored, val, ...) val - -/* - * The use of "&&" / "||" is limited in certain expressions. - * The followings enable to calculate "and" / "or" with macro expansion only. - */ -#define __and(x, y) ___and(x, y) -#define ___and(x, y) ____and(__ARG_PLACEHOLDER_##x, y) -#define ____and(arg1_or_junk, y) __take_second_arg(arg1_or_junk y, 0) - -#define __or(x, y) ___or(x, y) -#define ___or(x, y) ____or(__ARG_PLACEHOLDER_##x, y) -#define ____or(arg1_or_junk, y) __take_second_arg(arg1_or_junk 1, y) - -#define IS_REACHABLE(option) __or(IS_BUILTIN(option), \ - __and(IS_MODULE(option), __is_defined(MODULE))) -#endif /*IS_REACHABLE*/ - -#ifdef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_NO_RES_ID_ARG -extern int remove_conflicting_pci_framebuffers(struct pci_dev *pdev, - const char *name); -#else -extern int remove_conflicting_pci_framebuffers(struct pci_dev *pdev, int res_id, - const char *name); -#endif - -static inline int -_kcl_drm_fb_helper_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, - const char *name) -{ -#if IS_REACHABLE(CONFIG_FB) -#ifdef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_NO_RES_ID_ARG - return remove_conflicting_pci_framebuffers(pdev, name); -#else - return remove_conflicting_pci_framebuffers(pdev, 0, name); -#endif -#else - return 0; -#endif -} -#elif !defined(HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP) -static inline int -_kcl_drm_fb_helper_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, - const char *name) -{ -#ifdef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_WITH_RES_ID_ARG - return drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, 0, name); -#else - return drm_fb_helper_remove_conflicting_pci_framebuffers(pdev, name); -#endif -} -#endif /* HAVE_DRM_FB_HELPER_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS */ - #ifndef HAVE_DRM_FB_HELPER_FILL_INFO void drm_fb_helper_fill_info(struct fb_info *info, struct drm_fb_helper *fb_helper, From 0c334de48c982eafd6feec8100d921ee8a779549 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 22 Feb 2022 19:24:56 +0800 Subject: [PATCH 0643/1868] drm/amdkcl: fix kcl implementation for remove_conflicting_pci_framebuffers Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c | 3 ++- drivers/gpu/drm/amd/amdkcl/kcl_fbmem.h | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c b/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c index eae1bf4134541..ce1cdaad500a0 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c @@ -14,7 +14,8 @@ #include /* Copied from drivers/video/fbdev/core/fbmem.c and modified for KCL */ -#if !defined(HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS) +#if !defined(HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS) && \ + !defined(HAVE_DRM_DRM_APERTURE_H) int remove_conflicting_pci_framebuffers(struct pci_dev *pdev, const char *name) { struct apertures_struct *ap; diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.h b/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.h index de4bdea92fa7f..b734ca7c3d36a 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.h +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.h @@ -6,7 +6,8 @@ #include /* Copied from include/linux/fb.h */ -#if !defined(HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS) +#if !defined(HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS) && \ + !defined(HAVE_DRM_DRM_APERTURE_H) extern int remove_conflicting_pci_framebuffers(struct pci_dev *pdev, const char *name); #endif From 3bdc39bf03154a54609af860ca5f32999ed71992 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 24 Feb 2022 18:44:26 +0800 Subject: [PATCH 0644/1868] drm/amdkcl: Add the PSR related macro definition Add DP_PSR2_SU_Y_GRANULARITY definition for older versions of kernel Signed-off-by: Ma Jun Reviewed-by: Flora Cui Change-Id: I3badfeb16886544c2548597e2f1eb085e58e7c5d --- include/kcl/kcl_drm_dp_helper.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/include/kcl/kcl_drm_dp_helper.h b/include/kcl/kcl_drm_dp_helper.h index f32ad22d172db..60b18feee18f4 100644 --- a/include/kcl/kcl_drm_dp_helper.h +++ b/include/kcl/kcl_drm_dp_helper.h @@ -296,6 +296,4 @@ enum drm_dp_phy { # define DP_PSR2_SU_GRANULARITY_REQUIRED (1 << 5) /* eDP 1.4b */ #endif - - #endif /* _KCL_DRM_DP_HELPER_H_ */ From dce1fbcb145926513fc3ab58917b7a36d6618e46 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 2 Mar 2022 14:59:11 +0800 Subject: [PATCH 0645/1868] drm/amdkcl: drm/amd/display: Use adjusted DCN301 watermarks the patch was not applied completely in the rebase. Original patch is 808643ea56a2 - drm/amd/display: Use adjusted DCN301 watermarks Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- .../gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c index 045c008335866..c3653c6e878a4 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c @@ -1396,7 +1396,7 @@ static struct resource_funcs dcn301_res_pool_funcs = { .link_enc_create = dcn301_link_encoder_create, .panel_cntl_create = dcn301_panel_cntl_create, .validate_bandwidth = dcn30_validate_bandwidth, - .calculate_wm_and_dlg = dcn30_calculate_wm_and_dlg, + .calculate_wm_and_dlg = dcn301_calculate_wm_and_dlg, .update_soc_for_wm_a = dcn30_update_soc_for_wm_a, .populate_dml_pipes = dcn30_populate_dml_pipes_from_context, .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, From 891c106c81364e7ec9553c00e459b3fde099296c Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 2 Mar 2022 15:55:07 +0800 Subject: [PATCH 0646/1868] drm/amdkcl: undef REG_SET/REG_GET in display part fix warning for REG_SET/REG_GET redefined in display/dmub part Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h index 123d1704670ee..b314e60714ee2 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h @@ -28,6 +28,14 @@ #include "../inc/dmub_cmd.h" +#ifdef REG_SET +#undef REG_SET +#endif + +#ifdef REG_GET +#undef REG_GET +#endif + struct dmub_srv; /* Register offset and field lookup. */ From 7f9e5d1e3bf9abf2ff0c3f98e9fd006f477020fd Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 2 Mar 2022 13:55:12 +0800 Subject: [PATCH 0647/1868] drm/amdkcl: move __dma_resv_make_exclusive near to its caller MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit fix warning: ‘__dma_resv_make_exclusive’ defined but not used [-Wunused-function] Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index 9dc3c26f7f582..ffd28e47b034a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -91,6 +91,7 @@ int amdgpu_gem_prime_mmap(struct drm_gem_object *obj, #endif #if defined(AMDKCL_AMDGPU_DMABUF_OPS) +#if defined(HAVE_DMA_BUF_OPS_LEGACY) static int __dma_resv_make_exclusive(struct dma_resv *obj) { @@ -133,7 +134,6 @@ __dma_resv_make_exclusive(struct dma_resv *obj) return -ENOMEM; } -#if defined(HAVE_DMA_BUF_OPS_LEGACY) /** * amdgpu_dma_buf_map_attach - &dma_buf_ops.attach implementation * @dma_buf: Shared DMA buffer From f07f445c1cab3125ec9bb2da317e516e80a79d6c Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 2 Mar 2022 14:19:08 +0800 Subject: [PATCH 0648/1868] drm/amdkcl: fix warning in amdgpu_ras.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:133:13: warning: ‘amdgpu_register_bad_pages_mca_notifier’ declared ‘static’ but never defined [-Wunused-function] 133 | static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:138:38: warning: ‘mce_adev_list’ defined but not used [-Wunused-variable] 138 | static struct mce_notifier_adev_list mce_adev_list; | ^~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c:44:13: warning: ‘notifier_registered’ defined but not used [-Wunused-variable] 44 | static bool notifier_registered; | ^~~~~~~~~~~~~~~~~~~ Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 016ceec114cce..8fee69697535d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -44,8 +44,10 @@ #ifdef CONFIG_X86_MCE_AMD #include +#ifdef HAVE_SMCA_UMC_V2 static bool notifier_registered; #endif +#endif static const char *RAS_FS_NAME = "ras"; const char *ras_error_string[] = { @@ -126,11 +128,6 @@ const char *get_ras_block_str(struct ras_common_if *ras_block) #define MAX_FLUSH_RETIRE_DWORK_TIMES 100 -#ifdef HAVE_SMCA_UMC_V2 -static bool notifier_registered = false; -static void amdgpu_register_bad_pages_mca_notifier(void); -#endif - enum amdgpu_ras_retire_page_reservation { AMDGPU_RAS_RETIRE_PAGE_RESERVED, AMDGPU_RAS_RETIRE_PAGE_PENDING, @@ -144,6 +141,7 @@ static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con, static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev, uint64_t addr); #ifdef CONFIG_X86_MCE_AMD +#ifdef HAVE_SMCA_UMC_V2 static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev); struct mce_notifier_adev_list { struct amdgpu_device *devs[MAX_GPU_INSTANCE]; @@ -151,6 +149,7 @@ struct mce_notifier_adev_list { }; static struct mce_notifier_adev_list mce_adev_list; #endif +#endif void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready) { From fcb5b1a5e4b7c09a25ca6a19b2789b2068e9fd27 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 2 Mar 2022 14:24:50 +0800 Subject: [PATCH 0649/1868] drm/amdkcl: drop unused var in amdgpu_vkms_vblank_simulate MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c: In function ‘amdgpu_vkms_vblank_simulate’: drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c:48:24: warning: unused variable ‘adev’ [-Wunused-variable] 48 | struct amdgpu_device *adev = drm_to_adev(crtc->dev); | ^~~~ Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c index f71604a513ff4..3b124a2215875 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c @@ -47,7 +47,6 @@ static enum hrtimer_restart amdgpu_vkms_vblank_simulate(struct hrtimer *timer) { struct amdgpu_crtc *amdgpu_crtc = container_of(timer, struct amdgpu_crtc, vblank_timer); struct drm_crtc *crtc = &amdgpu_crtc->base; - struct amdgpu_device *adev = drm_to_adev(crtc->dev); struct amdgpu_vkms_output *output = drm_crtc_to_amdgpu_vkms_output(crtc); u64 ret_overrun; bool ret; From 75bf537ebd0b7e5a98eee25a2dcb91a7c9b54a6e Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 2 Mar 2022 15:53:44 +0800 Subject: [PATCH 0650/1868] drm/amdkcl: fix warning in amdgpu_display_get_fb_info MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit drivers/gpu/drm/amd/amdgpu/amdgpu_display.c:1153:44: warning: passing argument 1 of ‘drm_gem_fb_get_obj’ discards ‘const’ qualifier from pointer target type [-Wdiscarded-qualifiers] 1153 | rbo = gem_to_amdgpu_bo(drm_gem_fb_get_obj(&amdgpu_fb->base, 0)); Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 53604ac128c5b..2039435651022 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1403,7 +1403,7 @@ static int amdgpu_display_get_fb_info(const struct amdgpu_framebuffer *amdgpu_fb return 0; } - rbo = gem_to_amdgpu_bo(drm_gem_fb_get_obj(&amdgpu_fb->base, 0)); + rbo = gem_to_amdgpu_bo(drm_gem_fb_get_obj(&((struct amdgpu_framebuffer *)amdgpu_fb)->base, 0)); r = amdgpu_bo_reserve(rbo, false); if (unlikely(r)) { From 726597bc819c22cc9a91350b3becbaf896b13840 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Tue, 1 Mar 2022 16:24:54 -0500 Subject: [PATCH 0651/1868] drm/amdkfd: Fixup rebase errors in CRIU code Signed-off-by: Felix Kuehling Acked-by: Guchun Chen Reviewed-and-tested-by: Rajneesh Bhardwaj --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 14 +++++++------- drivers/gpu/drm/amd/amdkfd/kfd_ipc.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 3 ++- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 9 +++++++-- drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 18 ------------------ 5 files changed, 17 insertions(+), 29 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 8d857c4e0c7f8..6a378e5412cfb 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1177,7 +1177,7 @@ static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep, KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL | KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP); idr_handle = kfd_process_device_create_obj_handle(pdd, mem, - args->va_addr, args->size, cpuva, mem_type); + args->va_addr, args->size, cpuva, mem_type, -1); if (idr_handle < 0) { err = -EFAULT; goto err_free; @@ -1917,11 +1917,11 @@ static uint32_t get_process_num_bos(struct kfd_process *p) /* Run over all PDDs of the process */ for (i = 0; i < p->n_pdds; i++) { struct kfd_process_device *pdd = p->pdds[i]; - void *mem; + struct kfd_bo *buf_obj; int id; - idr_for_each_entry(&pdd->alloc_idr, mem, id) { - struct kgd_mem *kgd_mem = (struct kgd_mem *)mem; + idr_for_each_entry(&pdd->alloc_idr, buf_obj, id) { + struct kgd_mem *kgd_mem = (struct kgd_mem *)buf_obj->mem; if (!kgd_mem->va || kgd_mem->va > pdd->gpuvm_base) num_of_bos++; @@ -1965,7 +1965,7 @@ static int criu_checkpoint_bos(struct kfd_process *p, struct kfd_criu_bo_bucket *bo_buckets; struct kfd_criu_bo_priv_data *bo_privs; int ret = 0, pdd_index, bo_index = 0, id; - void *mem; + struct kfd_bo *buf_obj; bo_buckets = kvzalloc(num_bos * sizeof(*bo_buckets), GFP_KERNEL); if (!bo_buckets) @@ -1982,12 +1982,12 @@ static int criu_checkpoint_bos(struct kfd_process *p, struct amdgpu_bo *dumper_bo; struct kgd_mem *kgd_mem; - idr_for_each_entry(&pdd->alloc_idr, mem, id) { + idr_for_each_entry(&pdd->alloc_idr, buf_obj, id) { struct kfd_criu_bo_bucket *bo_bucket; struct kfd_criu_bo_priv_data *bo_priv; int i, dev_idx = 0; - kgd_mem = (struct kgd_mem *)mem; + kgd_mem = (struct kgd_mem *)buf_obj->mem; dumper_bo = kgd_mem->bo; /* Skip checkpointing BOs that are used for Trap handler diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c index 1e3d9af012651..e0a41feb7966f 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c @@ -147,7 +147,7 @@ static int kfd_import_dmabuf_create_kfd_bo(struct kfd_dev *dev, goto err_read_unlock; idr_handle = kfd_process_device_create_obj_handle(pdd, mem, - va_addr, size, 0, 0); + va_addr, size, 0, 0, -1); if (idr_handle < 0) { r = -EFAULT; goto err_free; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 6c4ba925532fc..fe2869a2389b1 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -1135,7 +1135,8 @@ int kfd_reserved_mem_mmap(struct kfd_node *dev, struct kfd_process *process, int kfd_process_device_create_obj_handle(struct kfd_process_device *pdd, void *mem, uint64_t start, uint64_t length, uint64_t cpuva, - unsigned int mem_type); + unsigned int mem_type, + int preferred_id); void *kfd_process_device_translate_handle(struct kfd_process_device *p, int handle); struct kfd_bo *kfd_process_device_find_bo(struct kfd_process_device *pdd, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index fe1073273fa63..6e3d18f5526c1 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -1819,7 +1819,8 @@ struct kfd_process_device *kfd_bind_process_to_device(struct kfd_node *dev, int kfd_process_device_create_obj_handle(struct kfd_process_device *pdd, void *mem, uint64_t start, uint64_t length, uint64_t cpuva, - unsigned int mem_type) + unsigned int mem_type, + int preferred_id) { int handle; struct kfd_bo *buf_obj; @@ -1841,7 +1842,11 @@ int kfd_process_device_create_obj_handle(struct kfd_process_device *pdd, buf_obj->cpuva = cpuva; buf_obj->mem_type = mem_type; - handle = idr_alloc(&pdd->alloc_idr, buf_obj, 0, 0, GFP_KERNEL); + if (preferred_id < 0) + handle = idr_alloc(&pdd->alloc_idr, buf_obj, 0, 0, GFP_KERNEL); + else + handle = idr_alloc(&pdd->alloc_idr, buf_obj, preferred_id, + preferred_id + 1, GFP_KERNEL); if (handle < 0) kfree(buf_obj); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c index d41e0a247aeab..229da4a0283d0 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c @@ -3927,24 +3927,6 @@ int kfd_criu_resume_svm(struct kfd_process *p) set_attr[num_attrs].type = KFD_IOCTL_SVM_ATTR_CLR_FLAGS; set_attr[num_attrs].value = ~set_flags; - /* CLR_FLAGS is not available via get_attr during checkpoint but - * it needs to be inserted before restoring the ranges so - * allocate extra space for it before calling set_attr - */ - set_attr_size = sizeof(struct kfd_ioctl_svm_attribute) * - (num_attrs + 1); - set_attr = krealloc(set_attr, set_attr_size, - GFP_KERNEL); - if (!set_attr) { - ret = -ENOMEM; - goto exit; - } - - memcpy(set_attr, criu_svm_md->data.attrs, num_attrs * - sizeof(struct kfd_ioctl_svm_attribute)); - set_attr[num_attrs].type = KFD_IOCTL_SVM_ATTR_CLR_FLAGS; - set_attr[num_attrs].value = ~set_flags; - ret = svm_range_set_attr(p, mm, criu_svm_md->data.start_addr, criu_svm_md->data.size, num_attrs + 1, set_attr); From 458e33643b6d4d9db591a7bad3d3f83da05ef3e1 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Tue, 1 Mar 2022 16:47:00 -0500 Subject: [PATCH 0652/1868] drm/amdkcl: Add support for kernels with MIGRATE_PFN_LOCKED MIGRATE_PFN_LOCKED was removed in commit ab09243aa95a ("mm/migrate.c: remove MIGRATE_PFN_LOCKED"). This patch restores compatibility with older kernels that still require this bit. Signed-off-by: Felix Kuehling Reviewed-by: Philip Yang Acked-by: Guchun Chen --- drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 2 ++ drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/backport/kcl_migrate.h | 14 ++++++++++++++ 3 files changed, 17 insertions(+) create mode 100644 include/kcl/backport/kcl_migrate.h diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c index 5e3547dfc01f4..f409e1aba1c57 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@ -311,6 +311,7 @@ svm_migrate_copy_to_vram(struct kfd_node *node, struct svm_range *prange, migrate->dst[i] = svm_migrate_addr_to_pfn(adev, dst[i]); svm_migrate_get_vram_page(prange, migrate->dst[i]); migrate->dst[i] = migrate_pfn(migrate->dst[i]); + migrate->dst[i] |= MIGRATE_PFN_LOCKED; spage = migrate_pfn_to_page(migrate->src[i]); if (spage && !is_zone_device_page(spage)) { @@ -654,6 +655,7 @@ svm_migrate_copy_to_ram(struct amdgpu_device *adev, struct svm_range *prange, dst[i] >> PAGE_SHIFT, page_to_pfn(dpage)); migrate->dst[i] = migrate_pfn(page_to_pfn(dpage)); + migrate->dst[i] |= MIGRATE_PFN_LOCKED; j++; } diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index b7a34ffd5527f..1375da8d63065 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -39,6 +39,7 @@ #include #include #include +#include #include #ifdef HAVE_DRM_DRIVER_GEM_PRIME_RES_OBJ #include diff --git a/include/kcl/backport/kcl_migrate.h b/include/kcl/backport/kcl_migrate.h new file mode 100644 index 0000000000000..55a817d8cf2aa --- /dev/null +++ b/include/kcl/backport/kcl_migrate.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _KCL_BACKPORT_KCL_MIGRATE_H +#define _KCL_BACKPORT_KCL_MIGRATE_H + +#include + +/* Compatibility with kernels before ab09243aa95a ("mm/migrate.c: remove + * MIGRATE_PFN_LOCKED") + */ +#ifndef MIGRATE_PFN_LOCKED +#define MIGRATE_PFN_LOCKED 0 +#endif + +#endif From aa680bae84c7839c7b2758894dea07221b5de4e8 Mon Sep 17 00:00:00 2001 From: Xiaogang Chen Date: Mon, 13 Dec 2021 16:28:57 -0600 Subject: [PATCH 0653/1868] drm/amdkfd: explicitly create/destroy queue attributes under /sys This patch was not applied completely in the rebase. Original patch description follows. When application is about finish it destroys queues it has created by an ioctl. Driver deletes queue entry(/sys/class/kfd/kfd/proc/pid/queues/queueid/) which is directory including this queue all attributes. Low level kernel code deletes all attributes under this directory. The lock from kernel is on queue entry, not its attributes. At meantime another user space application can read the attributes. There is possibility that the application can hold/read the attributes while kernel is deleting the queue entry, cause the application have invalid memory access, then killed by kernel. Driver changes: explicitly create/destroy each attribute for each queue, let kernel put lock on each attribute too. Signed-off-by: Xiaogang Chen Reviewed-by: Felix Kuehling Acked-by: Guchun Chen Reviewed-by: Xiaogang.Chen --- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 30 ------------------------ 1 file changed, 30 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 6e3d18f5526c1..0d8bb82155bb8 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -456,42 +456,12 @@ static ssize_t kfd_sysfs_counters_show(struct kobject *kobj, return 0; } -static struct attribute attr_queue_size = { - .name = "size", - .mode = KFD_SYSFS_FILE_MODE -}; - -static struct attribute attr_queue_type = { - .name = "type", - .mode = KFD_SYSFS_FILE_MODE -}; - -static struct attribute attr_queue_gpuid = { - .name = "gpuid", - .mode = KFD_SYSFS_FILE_MODE -}; - -static struct attribute *procfs_queue_attrs[] = { - &attr_queue_size, - &attr_queue_type, - &attr_queue_gpuid, - NULL -}; -#ifdef HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE -ATTRIBUTE_GROUPS(procfs_queue); -#endif - static const struct sysfs_ops procfs_queue_ops = { .show = kfd_procfs_queue_show, }; static const struct kobj_type procfs_queue_type = { .sysfs_ops = &procfs_queue_ops, -#ifdef HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE - .default_groups = procfs_queue_groups, -#else - .default_attrs = procfs_queue_attrs, -#endif }; static const struct sysfs_ops procfs_stats_ops = { From 08d2c6e4abcedf0a641050e4f7cd647360ca1d16 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Fri, 4 Mar 2022 19:11:53 -0500 Subject: [PATCH 0654/1868] drm/amdkfd: Hold mmap_read_lock for find_vma find_vma throws a warning if them mmap_read_lock is not held. Hold the lock as long as the vma returned by the call is needed. Once the lock is dropped, the VMA can become invalid. Signed-off-by: Felix Kuehling Reviewed-and-tested-by: Rajneesh Bhardwaj --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 6a378e5412cfb..6b25243b19d7e 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1119,12 +1119,14 @@ static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep, * space will be oblivious of this and will use this doorbell * BO as a regular userptr BO */ + mmap_read_lock(current->mm); vma = find_vma(current->mm, args->mmap_offset); if (vma && args->mmap_offset >= vma->vm_start && (vma->vm_flags & VM_IO)) { unsigned long pfn; err = follow_pfn(vma, args->mmap_offset, &pfn); + mmap_read_unlock(current->mm); if (err) { pr_debug("Failed to get PFN: %ld\n", err); goto err_unlock; @@ -1133,6 +1135,7 @@ static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep, flags &= ~KFD_IOC_ALLOC_MEM_FLAGS_USERPTR; offset = (pfn << PAGE_SHIFT); } else { + mmap_read_unlock(current->mm); if (offset & (PAGE_SIZE - 1)) { pr_debug("Unaligned userptr address:%llx\n", offset); From 671659e25f2f8fbe7bd8620294e6abb2797b0db2 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 7 Mar 2022 11:52:33 +0800 Subject: [PATCH 0655/1868] drm/amdkcl: fix warning for redefined MIN drivers/gpu/drm/amd/amdgpu/../display/modules/hdcp/hdcp_ddc.c:28: warning: "MIN" redefined 28 | #define MIN(a, b) ((a) < (b) ? (a) : (b)) Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c index 7ecf76aea9505..6e064e6ae949f 100644 --- a/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c +++ b/drivers/gpu/drm/amd/display/modules/hdcp/hdcp_ddc.c @@ -25,7 +25,9 @@ #include "hdcp.h" +#ifndef MIN #define MIN(a, b) ((a) < (b) ? (a) : (b)) +#endif #define HDCP_I2C_ADDR 0x3a /* 0x74 >> 1*/ #define KSV_READ_SIZE 0xf /* 0x6803b - 0x6802c */ #define HDCP_MAX_AUX_TRANSACTION_SIZE 16 From b7a1727661805f20ae3da36ae5ef3505b1645c69 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 7 Mar 2022 12:03:23 +0800 Subject: [PATCH 0656/1868] drm/amdkcl: fix warning for unused variable in amdgpu_connector.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c: In function ‘amdgpu_connector_update_scratch_regs’: drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c:252:6: warning: unused variable ‘i’ [-Wunused-variable] 252 | int i; | ^ drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c: In function ‘amdgpu_connector_find_encoder’: drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c:275:6: warning: unused variable ‘i’ [-Wunused-variable] 275 | int i; | ^ drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c: In function ‘amdgpu_connector_best_single_encoder’: drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c:393:6: warning: unused variable ‘i’ [-Wunused-variable] 393 | int i; | ^ drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c: In function ‘amdgpu_connector_dvi_detect’: drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c:1148:7: warning: unused variable ‘i’ [-Wunused-variable] 1148 | int i; | ^ drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c: In function ‘amdgpu_connector_dvi_encoder’: drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c:1204:6: warning: unused variable ‘i’ [-Wunused-variable] 1204 | int i; | ^ drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c: In function ‘amdgpu_connector_encoder_get_dp_bridge_encoder_id’: drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c:1372:6: warning: unused variable ‘i’ [-Wunused-variable] 1372 | int i; | ^ drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c: In function ‘amdgpu_connector_encoder_is_hbr2’: drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c:1397:6: warning: unused variable ‘i’ [-Wunused-variable] 1397 | int i; | ^ Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c index 6be3a8ee4119c..8232d4ef60783 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c @@ -242,7 +242,9 @@ amdgpu_connector_update_scratch_regs(struct drm_connector *connector, struct drm_encoder *encoder; const struct drm_connector_helper_funcs *connector_funcs = connector->helper_private; bool connected; +#ifndef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS int i; +#endif best_encoder = connector_funcs->best_encoder(connector); @@ -265,7 +267,9 @@ amdgpu_connector_find_encoder(struct drm_connector *connector, int encoder_type) { struct drm_encoder *encoder; +#ifndef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS int i; +#endif #ifdef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS drm_connector_for_each_possible_encoder(connector, encoder) { @@ -356,7 +360,9 @@ static struct drm_encoder * amdgpu_connector_best_single_encoder(struct drm_connector *connector) { struct drm_encoder *encoder; +#ifndef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS int i; +#endif /* pick the first one */ #ifdef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS @@ -1149,7 +1155,9 @@ amdgpu_connector_dvi_detect(struct drm_connector *connector, bool force) /* find analog encoder */ if (amdgpu_connector->dac_load_detect) { struct drm_encoder *encoder; +#ifndef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS int i; +#endif #ifdef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS drm_connector_for_each_possible_encoder(connector, encoder) { @@ -1206,7 +1214,9 @@ amdgpu_connector_dvi_encoder(struct drm_connector *connector) { struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); struct drm_encoder *encoder; +#ifndef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS int i; +#endif #ifdef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS drm_connector_for_each_possible_encoder(connector, encoder) { @@ -1373,7 +1383,9 @@ u16 amdgpu_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *conn { struct drm_encoder *encoder; struct amdgpu_encoder *amdgpu_encoder; +#ifndef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS int i; +#endif #ifdef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS drm_connector_for_each_possible_encoder(connector, encoder) { @@ -1398,7 +1410,9 @@ static bool amdgpu_connector_encoder_is_hbr2(struct drm_connector *connector) { struct drm_encoder *encoder; struct amdgpu_encoder *amdgpu_encoder; +#ifndef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS int i; +#endif bool found = false; #ifdef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS From 77473d9bb3c28ae0bc2e9e0c451e45b7e1d7167b Mon Sep 17 00:00:00 2001 From: David Yat Sin Date: Thu, 3 Mar 2022 14:48:19 -0500 Subject: [PATCH 0657/1868] drm/amdkfd: CRIU Add support for IPC handles Add support for checkpointing/restoring BOs with IPC handles. Reviewed-by: Felix Kuehling Signed-off-by: David Yat Sin --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 4 +- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 5 +- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 110 +++++++++++++++++- drivers/gpu/drm/amd/amdkfd/kfd_ipc.c | 103 +++++++++++----- drivers/gpu/drm/amd/amdkfd/kfd_ipc.h | 4 +- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 5 + 6 files changed, 191 insertions(+), 40 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index 629a870e330ae..85c7e4ed46d2f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -386,7 +386,9 @@ int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_mem *mem, int amdgpu_amdkfd_gpuvm_export_ipc_obj(struct amdgpu_device *adev, void *vm, struct kgd_mem *mem, struct kfd_ipc_obj **ipc_obj, - uint32_t flags); + uint32_t flags, + uint32_t *restore_handle); + void amdgpu_amdkfd_debug_mem_fence(struct amdgpu_device *adev); int amdgpu_amdkfd_get_tile_config(struct amdgpu_device *adev, struct tile_config *config); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index c4475899bfe8c..7bb7812e717cc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -2798,7 +2798,8 @@ int amdgpu_amdkfd_gpuvm_export_dmabuf(struct kgd_mem *mem, int amdgpu_amdkfd_gpuvm_export_ipc_obj(struct amdgpu_device *adev, void *vm, struct kgd_mem *mem, struct kfd_ipc_obj **ipc_obj, - uint32_t flags) + uint32_t flags, + uint32_t *restore_handle) { struct dma_buf *dmabuf; int r = 0; @@ -2819,7 +2820,7 @@ int amdgpu_amdkfd_gpuvm_export_ipc_obj(struct amdgpu_device *adev, void *vm, goto unlock_out; } - r = kfd_ipc_store_insert(dmabuf, &mem->ipc_obj, flags); + r = kfd_ipc_store_insert(dmabuf, &mem->ipc_obj, flags, restore_handle); if (r) dma_buf_put(dmabuf); else diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 6b25243b19d7e..b426c49d42189 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1681,7 +1681,7 @@ static int kfd_ioctl_ipc_import_handle(struct file *filep, r = kfd_ipc_import_handle(pdd->dev, p, args->gpu_id, args->share_handle, args->va_addr, &args->handle, - &args->mmap_offset, &args->flags); + &args->mmap_offset, &args->flags, false); if (r) pr_err("Failed to import IPC handle\n"); @@ -2044,8 +2044,18 @@ static int criu_checkpoint_bos(struct kfd_process *p, bo_priv->mapped_gpuids[dev_idx++] = p->pdds[i]->user_gpu_id; } - pr_debug("bo_size = 0x%llx, bo_addr = 0x%llx bo_offset = 0x%llx\n" + if (kgd_mem->ipc_obj) { + bo_priv->ipc_flags = kgd_mem->ipc_obj->flags; + bo_priv->is_imported = kgd_mem->is_imported; + + memcpy(bo_priv->ipc_share_handle, + kgd_mem->ipc_obj->share_handle, + sizeof(kgd_mem->ipc_obj->share_handle)); + } + + pr_debug("[%d]bo_size = 0x%llx, bo_addr = 0x%llx bo_offset = 0x%llx" "gpu_id = 0x%x alloc_flags = 0x%x idr_handle = 0x%x", + bo_index, bo_bucket->size, bo_bucket->addr, bo_bucket->offset, @@ -2359,6 +2369,93 @@ static int criu_restore_devices(struct kfd_process *p, return ret; } +static int criu_restore_memory_of_gpu_ipc(struct kfd_process_device *pdd, + struct kfd_criu_bo_bucket *bo_bucket, + struct kfd_criu_bo_priv_data *bo_priv, + struct kgd_mem **kgd_mem) +{ + uint64_t alloc_handle = MAKE_HANDLE(pdd->user_gpu_id, bo_priv->idr_handle); + struct kfd_dev *dev = pdd->dev; + struct kfd_bo *kfd_bo; + int ret, idr_handle; + uint64_t offset; + + ret = kfd_ipc_import_handle(dev, pdd->process, pdd->user_gpu_id, bo_priv->ipc_share_handle, + bo_bucket->addr, &alloc_handle, &offset, NULL, true); + if (ret) { + unsigned int mem_type; + + if (ret != -EINVAL) { + pr_err("Failed to import IPC handle ret:%d\n", ret); + return ret; + } + + /* kfd_ipc_import_handle returns -EINVAL if the ipc share_handle does not exist. + * In that case create a new BO and create a new ipc share_handle by calling + * amdgpu_amdkfd_gpuvm_export_ipc_obj. + */ + ret = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(dev->adev, bo_bucket->addr, + bo_bucket->size, pdd->drm_priv, + NULL, kgd_mem, &offset, + bo_bucket->alloc_flags, true); + if (ret) { + pr_err("Could not create the BO\n"); + return ret; + } + + pr_debug("New IPC BO created: size:0x%llx addr:0x%llx offset:0x%llx\n", + bo_bucket->size, bo_bucket->addr, offset); + + mem_type = bo_bucket->alloc_flags & + (KFD_IOC_ALLOC_MEM_FLAGS_VRAM | KFD_IOC_ALLOC_MEM_FLAGS_GTT); + + idr_handle = kfd_process_device_create_obj_handle(pdd, *kgd_mem, bo_bucket->addr, + bo_bucket->size, 0, mem_type, + bo_priv->idr_handle); + if (idr_handle < 0) { + pr_err("Could not allocate idr\n"); + + amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->adev, *kgd_mem, pdd->drm_priv, + NULL); + return -ENOMEM; + } + + ret = amdgpu_amdkfd_gpuvm_export_ipc_obj(dev->adev, pdd->drm_priv, *kgd_mem, + &(*kgd_mem)->ipc_obj, bo_priv->ipc_flags, + bo_priv->ipc_share_handle); + if (ret == -EINVAL) { + /* This is a race condition. The other process that owns this same IPC + * handle created the handle before this process. Delete BO and re-use + * import IPC handle created by the other process. + */ + ret = amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->adev, *kgd_mem, + pdd->drm_priv, NULL); + if (ret) + return ret; + + kfd_process_device_remove_obj_handle(pdd, idr_handle); + + ret = kfd_ipc_import_handle(dev, pdd->process, pdd->user_gpu_id, + bo_priv->ipc_share_handle, + bo_bucket->addr, &alloc_handle, + &offset, NULL, true); + if (ret) + return ret; + } + } + + kfd_bo = kfd_process_device_find_bo(pdd, bo_priv->idr_handle); + *kgd_mem = kfd_bo->mem; + (*kgd_mem)->is_imported = bo_priv->is_imported; + + bo_bucket->restored_offset = offset; + if ((bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) && !bo_priv->is_imported) + /* Update the VRAM usage count */ + WRITE_ONCE(pdd->vram_usage, pdd->vram_usage + bo_bucket->size); + + return 0; +} + static int criu_restore_memory_of_gpu(struct kfd_process_device *pdd, struct kfd_criu_bo_bucket *bo_bucket, struct kfd_criu_bo_priv_data *bo_priv, @@ -2432,11 +2529,14 @@ static int criu_restore_bo(struct kfd_process *p, struct kfd_criu_bo_bucket *bo_bucket, struct kfd_criu_bo_priv_data *bo_priv) { + const uint32_t zero_handle[4] = { 0, 0, 0, 0 }; struct kfd_process_device *pdd; struct kgd_mem *kgd_mem; int ret; int j; + BUILD_BUG_ON(sizeof_field(struct kfd_ipc_obj, share_handle) != sizeof(zero_handle)); + pr_debug("Restoring BO size:0x%llx addr:0x%llx gpu_id:0x%x flags:0x%x idr_handle:0x%x\n", bo_bucket->size, bo_bucket->addr, bo_bucket->gpu_id, bo_bucket->alloc_flags, bo_priv->idr_handle); @@ -2447,7 +2547,11 @@ static int criu_restore_bo(struct kfd_process *p, return -ENODEV; } - ret = criu_restore_memory_of_gpu(pdd, bo_bucket, bo_priv, &kgd_mem); + if (memcmp(bo_priv->ipc_share_handle, zero_handle, sizeof(zero_handle))) + ret = criu_restore_memory_of_gpu_ipc(pdd, bo_bucket, bo_priv, &kgd_mem); + else + ret = criu_restore_memory_of_gpu(pdd, bo_bucket, bo_priv, &kgd_mem); + if (ret) return ret; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c index e0a41feb7966f..6021077f7199b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c @@ -42,7 +42,7 @@ static struct kfd_ipc_handles { #define HANDLE_TO_KEY(sh) ((*(uint64_t *)sh) & KFD_IPC_HASH_TABLE_SIZE_MASK) int kfd_ipc_store_insert(struct dma_buf *dmabuf, struct kfd_ipc_obj **ipc_obj, - uint32_t flags) + uint32_t flags, uint32_t *restore_handle) { struct kfd_ipc_obj *obj; @@ -50,6 +50,30 @@ int kfd_ipc_store_insert(struct dma_buf *dmabuf, struct kfd_ipc_obj **ipc_obj, if (!obj) return -ENOMEM; + if (restore_handle) + memcpy(obj->share_handle, restore_handle, sizeof(obj->share_handle)); + else + get_random_bytes(obj->share_handle, sizeof(obj->share_handle)); + + mutex_lock(&kfd_ipc_handles.lock); + if (restore_handle) { + struct kfd_ipc_obj *entry; + + /* When doing CRIU restore, we may have a race condition where two processes try + * to insert handles with the same key. Make sure this key does not already exist + */ + hlist_for_each_entry(entry, + &kfd_ipc_handles.handles[HANDLE_TO_KEY(obj->share_handle)], node) { + if (!memcmp(entry->share_handle, + obj->share_handle, + sizeof(entry->share_handle))) { + mutex_unlock(&kfd_ipc_handles.lock); + kfree(obj); + return -EINVAL; + } + } + } + /* The initial ref belongs to the allocator process. * The IPC object store itself does not hold a ref since * there is no specific moment in time where that ref should @@ -59,12 +83,9 @@ int kfd_ipc_store_insert(struct dma_buf *dmabuf, struct kfd_ipc_obj **ipc_obj, */ kref_init(&obj->ref); obj->dmabuf = dmabuf; - get_random_bytes(obj->share_handle, sizeof(obj->share_handle)); obj->flags = flags; - mutex_lock(&kfd_ipc_handles.lock); - hlist_add_head(&obj->node, - &kfd_ipc_handles.handles[HANDLE_TO_KEY(obj->share_handle)]); + hlist_add_head(&obj->node, &kfd_ipc_handles.handles[HANDLE_TO_KEY(obj->share_handle)]); mutex_unlock(&kfd_ipc_handles.lock); if (ipc_obj) @@ -114,10 +135,10 @@ static int kfd_import_dmabuf_create_kfd_bo(struct kfd_dev *dev, uint32_t gpu_id, struct dma_buf *dmabuf, struct kfd_ipc_obj *ipc_obj, uint64_t va_addr, uint64_t *handle, - uint64_t *mmap_offset) + uint64_t *mmap_offset, bool restore) { int r; - void *mem; + struct kgd_mem *mem; uint64_t size; int idr_handle; struct kfd_process_device *pdd = NULL; @@ -128,44 +149,34 @@ static int kfd_import_dmabuf_create_kfd_bo(struct kfd_dev *dev, if (!dev) return -EINVAL; - mutex_lock(&p->mutex); - r = amdgpu_read_lock(dev->ddev, true); - if (r) - goto err_unlock; + if (restore) + idr_handle = GET_IDR_HANDLE(*handle); + else + idr_handle = -1; pdd = kfd_bind_process_to_device(dev, p); - if (IS_ERR(pdd)) { - r = PTR_ERR(pdd); - goto err_read_unlock; - } + if (IS_ERR(pdd)) + return PTR_ERR(pdd); r = amdgpu_amdkfd_gpuvm_import_dmabuf(dev->adev, dmabuf, ipc_obj, - va_addr, pdd->drm_priv, - (struct kgd_mem **)&mem, &size, - mmap_offset); + va_addr, pdd->drm_priv, + &mem, &size, mmap_offset); if (r) - goto err_read_unlock; + return r; idr_handle = kfd_process_device_create_obj_handle(pdd, mem, - va_addr, size, 0, 0, -1); + va_addr, size, 0, 0, idr_handle); if (idr_handle < 0) { r = -EFAULT; goto err_free; } - amdgpu_read_unlock(dev->ddev); - mutex_unlock(&p->mutex); - *handle = MAKE_HANDLE(gpu_id, idr_handle); return 0; err_free: amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->adev, (struct kgd_mem *)mem, pdd->drm_priv, NULL); -err_read_unlock: - amdgpu_read_unlock(dev->ddev); -err_unlock: - mutex_unlock(&p->mutex); return r; } @@ -181,8 +192,19 @@ int kfd_ipc_import_dmabuf(struct kfd_dev *dev, if (!dmabuf) return -EINVAL; + mutex_lock(&p->mutex); + r = amdgpu_read_lock(dev->ddev, true); + if (r) + goto err_unlock; + r = kfd_import_dmabuf_create_kfd_bo(dev, p, gpu_id, dmabuf, NULL, - va_addr, handle, mmap_offset); + va_addr, handle, mmap_offset, false); + + amdgpu_read_unlock(dev->ddev); + +err_unlock: + mutex_unlock(&p->mutex); + dma_buf_put(dmabuf); return r; } @@ -190,7 +212,7 @@ int kfd_ipc_import_dmabuf(struct kfd_dev *dev, int kfd_ipc_import_handle(struct kfd_dev *dev, struct kfd_process *p, uint32_t gpu_id, uint32_t *share_handle, uint64_t va_addr, uint64_t *handle, - uint64_t *mmap_offset, uint32_t *pflags) + uint64_t *mmap_offset, uint32_t *pflags, bool restore) { int r; struct kfd_ipc_obj *entry, *found = NULL; @@ -214,15 +236,32 @@ int kfd_ipc_import_handle(struct kfd_dev *dev, struct kfd_process *p, pr_debug("Found ipc_dma_buf: %p\n", found->dmabuf); + if (!restore) { + mutex_lock(&p->mutex); + r = amdgpu_read_lock(dev->ddev, true); + if (r) + goto err_unlock; + } + r = kfd_import_dmabuf_create_kfd_bo(dev, p, gpu_id, found->dmabuf, found, - va_addr, handle, mmap_offset); + va_addr, handle, mmap_offset, + restore); + if (!restore) { + amdgpu_read_unlock(dev->ddev); + mutex_unlock(&p->mutex); + } if (r) goto error_unref; - *pflags = found->flags; + if (pflags) + *pflags = found->flags; + return r; +err_unlock: + mutex_unlock(&p->mutex); + error_unref: kfd_ipc_obj_put(&found); return r; @@ -260,7 +299,7 @@ int kfd_ipc_export_as_handle(struct kfd_dev *dev, struct kfd_process *p, mem = (struct kgd_mem *)kfd_bo->mem; r = amdgpu_amdkfd_gpuvm_export_ipc_obj(dev->adev, pdd->drm_priv, mem, - &ipc_obj, flags); + &ipc_obj, flags, NULL); if (r) goto unlock; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h index 7915b8cad13db..be0bf2b388194 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h @@ -42,7 +42,7 @@ struct kfd_ipc_obj { int kfd_ipc_import_handle(struct kfd_dev *dev, struct kfd_process *p, uint32_t gpu_id, uint32_t *share_handle, uint64_t va_addr, uint64_t *handle, - uint64_t *mmap_offset, uint32_t *pflags); + uint64_t *mmap_offset, uint32_t *pflags, bool restore); int kfd_ipc_import_dmabuf(struct kfd_dev *kfd, struct kfd_process *p, uint32_t gpu_id, int dmabuf_fd, uint64_t va_addr, uint64_t *handle, @@ -52,7 +52,7 @@ int kfd_ipc_export_as_handle(struct kfd_dev *dev, struct kfd_process *p, uint32_t flags); int kfd_ipc_store_insert(struct dma_buf *dmabuf, struct kfd_ipc_obj **ipc_obj, - uint32_t flags); + uint32_t flags, uint32_t *restore_handle); void kfd_ipc_obj_put(struct kfd_ipc_obj **obj); #endif /* KFD_IPC_H_ */ diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index fe2869a2389b1..09841fb78bae5 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -1292,6 +1292,11 @@ struct kfd_criu_bo_priv_data { uint64_t user_addr; uint32_t idr_handle; uint32_t mapped_gpuids[MAX_GPU_INSTANCE]; + + /* IPC related variables */ + uint32_t is_imported; + uint32_t ipc_flags; + uint32_t ipc_share_handle[4]; }; /* From 793e6a0f81107bdcc17dd9385abe6bec711c9248 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 9 Mar 2022 15:54:38 +0800 Subject: [PATCH 0658/1868] drm/amdkcl: Add the sizeof_field() macro definition Add the sizeof_field() macro definiton for older versions of kernel Signed-off-by: Ma Jun Reviewed-by: Flora Cui Change-Id: I94d722db8c9fbfed92f07a3bd926e4fdaa7a8de3 --- drivers/gpu/drm/amd/backport/backport.h | 2 +- include/kcl/kcl_stddef.h | 16 ++++++++++++++++ 2 files changed, 17 insertions(+), 1 deletion(-) create mode 100644 include/kcl/kcl_stddef.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 1375da8d63065..7a3191d02da5d 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -90,5 +90,5 @@ #include #include #include - +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_stddef.h b/include/kcl/kcl_stddef.h new file mode 100644 index 0000000000000..dc455e1423ab1 --- /dev/null +++ b/include/kcl/kcl_stddef.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _KCL_KCL_STDDEF_H_ +#define _KCL_KCL_STDDEF_H_ + +#include +#ifndef sizeof_field +/** + * sizeof_field() - Report the size of a struct field in bytes + * + * @TYPE: The structure containing the field of interest + * @MEMBER: The field to return the size of + */ +#define sizeof_field(TYPE, MEMBER) sizeof((((TYPE *)0)->MEMBER)) +#endif + +#endif From 34dfe4420e22d2f4e28c43038b7517b27caa5950 Mon Sep 17 00:00:00 2001 From: David Yat Sin Date: Thu, 10 Mar 2022 12:34:39 -0500 Subject: [PATCH 0659/1868] drm/amdkfd: Fix incorrect identation and compile warning Fix incorrect indentation and compile warning Signed-off-by: David Yat Sin Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index b426c49d42189..3441585f668d6 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1225,7 +1225,6 @@ static int kfd_ioctl_free_memory_of_gpu(struct file *filep, struct kfd_ioctl_free_memory_of_gpu_args *args = data; struct kfd_process_device *pdd; struct kfd_bo *buf_obj; - struct kfd_dev *dev; int ret; uint64_t size = 0; From 1823e671e7237a06624d2ab81549bd0cb686a157 Mon Sep 17 00:00:00 2001 From: Eric Huang Date: Mon, 14 Mar 2022 14:41:36 -0400 Subject: [PATCH 0660/1868] drm/amdkfd: fix a bug on creating gpuid sysfs entry Correct guid to gpuid to make kfd_procfs_queue_show() return a valid value. Signed-off-by: Eric Huang Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 09841fb78bae5..c16abbe5f6314 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -637,7 +637,7 @@ struct queue { /* procfs */ struct kobject kobj; - struct attribute attr_guid; + struct attribute attr_gpuid; struct attribute attr_size; struct attribute attr_type; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 0d8bb82155bb8..75d468e2d97c4 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -503,7 +503,7 @@ int kfd_procfs_add_queue(struct queue *q) return ret; } - kfd_sysfs_create_file(&q->kobj, &q->attr_guid, "guid"); + kfd_sysfs_create_file(&q->kobj, &q->attr_gpuid, "gpuid"); kfd_sysfs_create_file(&q->kobj, &q->attr_size, "size"); kfd_sysfs_create_file(&q->kobj, &q->attr_type, "type"); @@ -651,7 +651,7 @@ void kfd_procfs_del_queue(struct queue *q) if (!q) return; - sysfs_remove_file(&q->kobj, &q->attr_guid); + sysfs_remove_file(&q->kobj, &q->attr_gpuid); sysfs_remove_file(&q->kobj, &q->attr_size); sysfs_remove_file(&q->kobj, &q->attr_type); From 5245a34fb4b77dce37a0d67825521022590a8dd4 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 14 Mar 2022 11:44:14 +0800 Subject: [PATCH 0661/1868] drm/amdkcl: fix test for drm_gem_object_put Signed-off-by: Flora Cui Reviewed-by: Rui Teng --- drivers/gpu/drm/amd/dkms/config/config.h | 8 ++--- .../gpu/drm/amd/dkms/m4/drm-gem-object-ref.m4 | 29 ++++++++----------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 +- include/kcl/backport/kcl_drm_gem.h | 4 +-- include/kcl/kcl_drm_gem.h | 8 ++--- 5 files changed, 23 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index c9d73d317b8d2..47a86bc31cee8 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -530,11 +530,11 @@ /* drm_gem_object_lookup() wants 2 args */ #define HAVE_DRM_GEM_OBJECT_LOOKUP_2ARGS 1 -/* drm_gem_object_put_locked() is available */ -#define HAVE_DRM_GEM_OBJECT_PUT_LOCKED 1 +/* drm_gem_object_put() is available */ +#define HAVE_DRM_GEM_OBJECT_PUT 1 -/* drm_gem_object_put_unlocked() is available */ -/* #undef HAVE_DRM_GEM_OBJECT_PUT_UNLOCKED */ +/* drm_gem_object_put() is exported */ +/* #undef HAVE_DRM_GEM_OBJECT_PUT_SYMBOL */ /* ttm_buffer_object->base is available */ #define HAVE_DRM_GEM_OBJECT_RESV 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-gem-object-ref.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-gem-object-ref.m4 index f73dc8440b756..c4d2a03ec81c0 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-gem-object-ref.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-gem-object-ref.m4 @@ -3,25 +3,20 @@ dnl # v5.7-rc1-518-gab15d56e27be drm: remove transient drm_gem_object_put_unlock dnl # v5.7-rc1-491-geecd7fd8bf58 drm/gem: add _locked suffix to drm_gem_object_put dnl # v5.7-rc1-490-gb5d250744ccc drm/gem: fold drm_gem_object_put_unlocked and __drm_gem_object_put() dnl # -AC_DEFUN([AC_AMDGPU_DRM_GEM_OBJECT_PUT_UNLOCKED], [ +AC_DEFUN([AC_AMDGPU_DRM_GEM_OBJECT_PUT], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT( - [drm_gem_object_put_locked], [drivers/gpu/drm/drm_gem.c], - [ - AC_DEFINE(HAVE_DRM_GEM_OBJECT_PUT_LOCKED, 1, - [drm_gem_object_put_locked() is available]) + AC_KERNEL_TRY_COMPILE([ + #include ], [ - dnl # - dnl # commit v4.10-rc8-1302-ge6b62714e87c - dnl # drm: Introduce drm_gem_object_{get,put}() - dnl # - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include - ], [ - drm_gem_object_put_unlocked(NULL); - ], [drm_gem_object_put_unlocked], [drivers/gpu/drm/drm_gem.c], [ - AC_DEFINE(HAVE_DRM_GEM_OBJECT_PUT_UNLOCKED, 1, - [drm_gem_object_put_unlocked() is available]) + drm_gem_object_put(NULL); + ], [ + AC_DEFINE(HAVE_DRM_GEM_OBJECT_PUT, 1, + [drm_gem_object_put() is available]) + + AC_KERNEL_CHECK_SYMBOL_EXPORT([drm_gem_object_put], + [drivers/gpu/drm/drm_gem.c], [ + AC_DEFINE(HAVE_DRM_GEM_OBJECT_PUT_SYMBOL, 1, + [drm_gem_object_put() is exported]) ]) ]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 4f2e7dbc2f27f..66ed05dce05d4 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -71,7 +71,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DOWN_READ_KILLABLE AC_AMDGPU_DRM_CACHE AC_AMDGPU_DRM_DEBUG_ENABLED - AC_AMDGPU_DRM_GEM_OBJECT_PUT_UNLOCKED + AC_AMDGPU_DRM_GEM_OBJECT_PUT AC_AMDGPU_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS AC_AMDGPU_DRM_CONNECTOR_INIT_WITH_DDC AC_AMDGPU_DRM_DP_CALC_PBN_MODE diff --git a/include/kcl/backport/kcl_drm_gem.h b/include/kcl/backport/kcl_drm_gem.h index 373e3719b4c57..6f04e71ca35fd 100644 --- a/include/kcl/backport/kcl_drm_gem.h +++ b/include/kcl/backport/kcl_drm_gem.h @@ -36,8 +36,8 @@ #include -#if !defined(HAVE_DRM_GEM_OBJECT_PUT_LOCKED) -#if defined(HAVE_DRM_GEM_OBJECT_PUT_UNLOCKED) +#if defined(HAVE_DRM_GEM_OBJECT_PUT) +#if defined(HAVE_DRM_GEM_OBJECT_PUT_SYMBOL) #define drm_gem_object_put _kcl_drm_gem_object_put #endif #endif diff --git a/include/kcl/kcl_drm_gem.h b/include/kcl/kcl_drm_gem.h index a0f90deb18b06..cded9b424aa89 100644 --- a/include/kcl/kcl_drm_gem.h +++ b/include/kcl/kcl_drm_gem.h @@ -35,13 +35,14 @@ #define __KCL_KCL_DRM_GEM_H__ #include -#if !defined(HAVE_DRM_GEM_OBJECT_PUT_LOCKED) -#if defined(HAVE_DRM_GEM_OBJECT_PUT_UNLOCKED) +#if defined(HAVE_DRM_GEM_OBJECT_PUT) +#if defined(HAVE_DRM_GEM_OBJECT_PUT_SYMBOL) static inline void _kcl_drm_gem_object_put(struct drm_gem_object *obj) { return drm_gem_object_put_unlocked(obj); } +#endif #else static inline void drm_gem_object_put(struct drm_gem_object *obj) @@ -54,7 +55,6 @@ drm_gem_object_get(struct drm_gem_object *obj) { kref_get(&obj->refcount); } -#endif -#endif /* HAVE_DRM_GEM_OBJECT_PUT_LOCKED */ +#endif /* HAVE_DRM_GEM_OBJECT_PUT */ #endif From 9a907860fd141098924192f66ff84ecd72db135b Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 15 Mar 2022 16:17:42 +0800 Subject: [PATCH 0662/1868] drm/amdkcl: fix CC CFLAGS check Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 4 +-- .../drm/amd/dkms/m4/kernel_single_target.m4 | 25 ++++++++----------- 2 files changed, 13 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 66ed05dce05d4..2ce641d0927c2 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -459,7 +459,7 @@ AC_DEFUN([AC_KERNEL_COMPILE_IFELSE], [ m4_ifvaln([$1], [AC_KERNEL_CONFTEST_C([$1])]) m4_ifvaln([$5], [AC_KERNEL_CONFTEST_H([$5])], [AC_KERNEL_CONFTEST_H([])]) AS_IF( - [AC_TRY_COMMAND($CC $CFLAGS -o conftest.o conftest.c) >/dev/null && AC_TRY_COMMAND([$2])], + [AC_TRY_COMMAND(eval $CC $CFLAGS) > /dev/null && AC_TRY_COMMAND([$2])], [$3], [_AC_MSG_LOG_CONFTEST m4_ifvaln([$4],[$4])] ) @@ -474,7 +474,7 @@ dnl # AC_DEFUN([AC_KERNEL_TRY_COMPILE], [AC_KERNEL_COMPILE_IFELSE( [AC_LANG_SOURCE([AC_KERNEL_LANG_PROGRAM([[$1]], [[$2]])])], - [test -s conftest.o], + [test -s conftest.o || test -s .tmp_conftest.o], [$3], [$4]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 index b4af835c8928f..7fd86cef1e099 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 @@ -3,28 +3,25 @@ dnl # extract cc, cflags, cppflags dnl # AC_DEFUN([AC_KERNEL_SINGLE_TARGET_CFLAGS], [ AS_IF([test -s .conftest.o.cmd], [ - _base_cflags="-DKBUILD_BASENAME='\"conftest\"' -DKBUILD_MODNAME='\"conftest\"'" - _base_dir=$(basename $PWD) _conftest_cmd=$(head -1 .conftest.o.cmd) CC=$(echo $_conftest_cmd | awk -F ' ' '{print $[3]}') + CFLAGS=$(echo $_conftest_cmd | \ - sed -e 's| -|\n&|g' | \ - sed -e "s|\./|${LINUX_OBJ}/|" \ - -e "s|-I\([[[a-z]]]*\)|-I${LINUX_OBJ}/\1|" \ - -e "s|-include \([[[a-z]]]*\)|-include ${LINUX_OBJ}/\1|" \ - -e '/conftest/d' \ - -e '/KBUILD_/d' \ - -e "/$_base_dir/d" | \ - xargs) + cut -d ' ' -f 4- | \ + sed -e "s|\./|${LINUX_OBJ}/|g" \ + -e "s|-I\([[[a-z]]]*\)|-I${LINUX_OBJ}/\1|g" \ + -e "s|-include \([[[a-z]]]*\)|-include ${LINUX_OBJ}/\1|g" \ + -e "s|$PWD|\${PWD}|g") + CPPFLAGS=$(echo $CFLAGS | \ + cut -d ';' -f 1 | \ sed 's| -|\n&|g' | \ - sed -n '/-I/p; /-include/p; /-isystem/p; /-D/p' | \ + sed -n -e '/conftest/d' \ + -e '/KBUILD/d' \ + -e '/-I/p; /-include/p; /-isystem/p; /-D/p' | \ xargs) - CFLAGS="$CFLAGS $_base_cflags" - CPPFLAGS="$CPPFLAGS $_base_cflags" - AC_SUBST(CC) AC_SUBST(CFLAGS) AC_SUBST(CPPFLAGS) From 261693f8f9ba31561ad13985a14810f2506d7d43 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 15 Mar 2022 16:50:44 +0800 Subject: [PATCH 0663/1868] drm/amdkcl: drop test for mem_encrypt_active not needed anymore Signed-off-by: Flora Cui Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 3 --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - .../gpu/drm/amd/dkms/m4/mem_encrypt_active.m4 | 17 ------------ include/kcl/kcl_dma_mapping.h | 1 - include/kcl/kcl_mem_encrypt.h | 26 ------------------- 5 files changed, 48 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/mem_encrypt_active.m4 delete mode 100644 include/kcl/kcl_mem_encrypt.h diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 47a86bc31cee8..b51ad53a9fbf5 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -894,9 +894,6 @@ /* memalloc_noreclaim_save() is available */ #define HAVE_MEMALLOC_NORECLAIM_SAVE 1 -/* mem_encrypt_active() is available */ -#define HAVE_MEM_ENCRYPT_ACTIVE 1 - /* migrate_vma->pgmap_owner is available */ #define HAVE_MIGRATE_VMA_PGMAP_OWNER 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 2ce641d0927c2..be4bca3435d39 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -126,7 +126,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_INIT AC_AMDGPU_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION - AC_AMDGPU_MEM_ENCRYPT_ACTIVE AC_AMDGPU_JIFFIES64_TO_MSECS AC_AMDGPU___PRINT_ARRAY AC_AMDGPU_ACPI_PUT_TABLE diff --git a/drivers/gpu/drm/amd/dkms/m4/mem_encrypt_active.m4 b/drivers/gpu/drm/amd/dkms/m4/mem_encrypt_active.m4 deleted file mode 100644 index 5b80d8cf1223a..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/mem_encrypt_active.m4 +++ /dev/null @@ -1,17 +0,0 @@ -dnl # -dnl # commit v4.14-rc8-89-gd8aa7eea78a1 -dnl # x86/mm: Add Secure Encrypted Virtualization (SEV) support -dnl # -AC_DEFUN([AC_AMDGPU_MEM_ENCRYPT_ACTIVE], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - #include - ], [ - mem_encrypt_active(); - ], [ - AC_DEFINE(HAVE_MEM_ENCRYPT_ACTIVE, 1, - [mem_encrypt_active() is available]) - ]) - ]) -]) diff --git a/include/kcl/kcl_dma_mapping.h b/include/kcl/kcl_dma_mapping.h index ba248dc82f298..81d15205ec77e 100644 --- a/include/kcl/kcl_dma_mapping.h +++ b/include/kcl/kcl_dma_mapping.h @@ -3,7 +3,6 @@ #define AMDKCL_DMA_MAPPING_H #include -#include /* * commit v4.8-11962-ga9a62c938441 diff --git a/include/kcl/kcl_mem_encrypt.h b/include/kcl/kcl_mem_encrypt.h deleted file mode 100644 index 60d24e198587e..0000000000000 --- a/include/kcl/kcl_mem_encrypt.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * AMD Memory Encryption Support - * - * Copyright (C) 2016 Advanced Micro Devices, Inc. - * - * Author: Tom Lendacky - */ -#ifndef KCL_KCL_MEM_ENCRYPT_H -#define KCL_KCL_MEM_ENCRYPT_H - -#ifdef HAVE_LINUX_MEM_ENCRYPT_H -#include -#ifndef HAVE_MEM_ENCRYPT_ACTIVE -static inline bool mem_encrypt_active(void) -{ - return sme_me_mask; -} -#endif -#else -static inline bool mem_encrypt_active(void) -{ - return false; -} -#endif -#endif From 79e00c281accf7c6d787f3b0ccfe07536e5f6994 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 15 Mar 2022 17:40:57 +0800 Subject: [PATCH 0664/1868] drm/amdkcl: drop test for drm_sysfs_connector_hotplug_event not needed anymore Signed-off-by: Flora Cui Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_drm_sysfs.c | 44 ------------------- drivers/gpu/drm/amd/backport/backport.h | 1 - drivers/gpu/drm/amd/dkms/config/config.h | 3 -- .../m4/drm-sysfs-connector-hotplug-event.m4 | 16 ------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - include/kcl/kcl_drm_sysfs.h | 10 ----- 7 files changed, 1 insertion(+), 76 deletions(-) delete mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_sysfs.c delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-sysfs-connector-hotplug-event.m4 delete mode 100644 include/kcl/kcl_drm_sysfs.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 30e4532c21b24..d268f4a39a272 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -13,7 +13,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o kcl_ftrace.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_fs_read_write.o kcl_drm_aperture.o \ kcl_drm_drv.o kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o \ - kcl_drm_nomodeset.o kcl_drm_sysfs.o + kcl_drm_nomodeset.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_sysfs.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_sysfs.c deleted file mode 100644 index 5be759d09043b..0000000000000 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_sysfs.c +++ /dev/null @@ -1,44 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only - -/* - * drm_sysfs.c - Modifications to drm_sysfs_class.c to support - * extra sysfs attribute from DRM. Normal drm_sysfs_class - * does not allow adding attributes. - * - * Copyright (c) 2004 Jon Smirl - * Copyright (c) 2003-2004 Greg Kroah-Hartman - * Copyright (c) 2003-2004 IBM Corp. - */ -#include -#include -#include -#include -#include - -#ifndef HAVE_DRM_SYSFS_CONNECTOR_HOTPLUG_EVENT -/** - * drm_sysfs_connector_hotplug_event - generate a DRM uevent for any connector - * change - * @connector: connector which has changed - * - * Send a uevent for the DRM connector specified by @connector. This will send - * a uevent with the properties HOTPLUG=1 and CONNECTOR. - */ -void drm_sysfs_connector_hotplug_event(struct drm_connector *connector) -{ - struct drm_device *dev = connector->dev; - char hotplug_str[] = "HOTPLUG=1", conn_id[21]; - char *envp[] = { hotplug_str, conn_id, NULL }; - - snprintf(conn_id, sizeof(conn_id), - "CONNECTOR=%u", connector->base.id); - - drm_dbg_kms(connector->dev, - "[CONNECTOR:%d:%s] generating connector hotplug event\n", - connector->base.id, connector->name); - - kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, envp); -} -EXPORT_SYMBOL(drm_sysfs_connector_hotplug_event); - -#endif diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 7a3191d02da5d..1887b9a0952fd 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -88,7 +88,6 @@ #include #include #include -#include #include #include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index b51ad53a9fbf5..ac3bca351e4c3 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -660,9 +660,6 @@ /* whether drm_syncobj_find_fence() wants 5 args */ #define HAVE_DRM_SYNCOBJ_FIND_FENCE_5ARGS 1 -/* drm_sysfs_connector_hotplug_event() function is available */ -#define HAVE_DRM_SYSFS_CONNECTOR_HOTPLUG_EVENT 1 - /* Define to 1 if you have the header file. */ #define HAVE_DRM_TASK_BARRIER_H 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-sysfs-connector-hotplug-event.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-sysfs-connector-hotplug-event.m4 deleted file mode 100644 index 3db7dabaf0b15..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm-sysfs-connector-hotplug-event.m4 +++ /dev/null @@ -1,16 +0,0 @@ -dnl # -dnl # commit v5.15-rc2-1273-g0d6a8c5e9683 -dnl # drm/sysfs: introduce drm_sysfs_connector_hotplug_event -dnl # -AC_DEFUN([AC_AMDGPU_DRM_SYSFS_CONNECTOR_HOTPLUG_EVENT], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - drm_sysfs_connector_hotplug_event(NULL); - ], [ - AC_DEFINE(HAVE_DRM_SYSFS_CONNECTOR_HOTPLUG_EVENT, 1, - [drm_sysfs_connector_hotplug_event() function is available]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index be4bca3435d39..df1e2b739e052 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -196,7 +196,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_PCI_IRQ_VECTOR AC_AMDGPU_DRM_FIRMWARE_DRIVERS_ONLY AC_AMDGPU_DMA_FENCE_DESCRIBE - AC_AMDGPU_DRM_SYSFS_CONNECTOR_HOTPLUG_EVENT AC_AMDGPU_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT AC_AMDGPU_PCIE_ASPM_ENABLED diff --git a/include/kcl/kcl_drm_sysfs.h b/include/kcl/kcl_drm_sysfs.h deleted file mode 100644 index aaa27638d4659..0000000000000 --- a/include/kcl/kcl_drm_sysfs.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef AMDKCL_DRM_SYSFS_H -#define AMDKCL_DRM_SYSFS_H - -struct drm_connector; -#ifndef HAVE_DRM_SYSFS_CONNECTOR_HOTPLUG_EVENT -void drm_sysfs_connector_hotplug_event(struct drm_connector *connector); -#endif - -#endif From 709d1f6a19b37b1aa900475d74f5b060bdd12ffd Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Wed, 16 Mar 2022 10:25:00 +0800 Subject: [PATCH 0665/1868] drm/amdkcl: drop kcl part of get_mm_exe_file not needed any more Signed-off-by: Flora Cui Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/kcl_mm.c | 10 ---------- drivers/gpu/drm/amd/dkms/config/config.h | 3 --- drivers/gpu/drm/amd/dkms/m4/get_mm_exe_file.m4 | 10 ---------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - include/kcl/backport/kcl_mm_backport.h | 4 ---- include/kcl/kcl_mm.h | 4 ---- 6 files changed, 32 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/get_mm_exe_file.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_mm.c b/drivers/gpu/drm/amd/amdkcl/kcl_mm.c index 65ae09624622f..9d7534002b7e1 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_mm.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_mm.c @@ -16,19 +16,9 @@ void __kcl_mmput_async(struct mm_struct *mm) } #endif - -#ifndef HAVE_GET_MM_EXE_FILE -struct file *(*_kcl_get_mm_exe_file)(struct mm_struct *mm); -EXPORT_SYMBOL(_kcl_get_mm_exe_file); -#endif - void amdkcl_mm_init(void) { #ifndef HAVE_MMPUT_ASYNC _kcl_mmput_async = amdkcl_fp_setup("mmput_async", __kcl_mmput_async); #endif - -#ifndef HAVE_GET_MM_EXE_FILE - _kcl_get_mm_exe_file = amdkcl_fp_setup("get_mm_exe_file", NULL); -#endif } diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index ac3bca351e4c3..77555469a3de5 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -696,9 +696,6 @@ /* generic_handle_domain_irq() is available */ #define HAVE_GENERIC_HANDLE_DOMAIN_IRQ 1 -/* get_mm_exe_file() is available */ -#define HAVE_GET_MM_EXE_FILE 1 - /* get_user_pages() wants 6 args */ /* #undef HAVE_GET_USER_PAGES_6ARGS */ diff --git a/drivers/gpu/drm/amd/dkms/m4/get_mm_exe_file.m4 b/drivers/gpu/drm/amd/dkms/m4/get_mm_exe_file.m4 deleted file mode 100644 index 9c024190e405d..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/get_mm_exe_file.m4 +++ /dev/null @@ -1,10 +0,0 @@ -dnl # -dnl # v2.6.39-6856-g3864601387cf mm: extract exe_file handling from procfs -dnl # -AC_DEFUN([AC_AMDGPU_GET_MM_EXE_FILE], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([get_mm_exe_file], [kernel/fork.c], [ - AC_DEFINE(HAVE_GET_MM_EXE_FILE, 1, [get_mm_exe_file() is available]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index df1e2b739e052..08aa50b88dc69 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -168,7 +168,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DEV_IS_UNPLUGGED AC_AMDGPU_DRM_DEVICE_PDEV AC_AMDGPU_DRM_CONNECTOR_SET_PANEL_ORIENTATION_WITH_QUIRK - AC_AMDGPU_GET_MM_EXE_FILE AC_AMDGPU_DRM_SIMPLE_ENCODER_INIT AC_AMDGPU_DRM_MODE_CONFIG_HELPER_SUSPEND AC_AMDGPU_DRM_FBDEV_GENERIC_SETUP diff --git a/include/kcl/backport/kcl_mm_backport.h b/include/kcl/backport/kcl_mm_backport.h index 131403b50a6b4..48312d64e5869 100644 --- a/include/kcl/backport/kcl_mm_backport.h +++ b/include/kcl/backport/kcl_mm_backport.h @@ -9,10 +9,6 @@ #define mmput_async _kcl_mmput_async #endif -#ifndef HAVE_GET_MM_EXE_FILE -#define get_mm_exe_file _kcl_get_mm_exe_file -#endif - #ifdef get_user_pages_remote #undef get_user_pages_remote #endif diff --git a/include/kcl/kcl_mm.h b/include/kcl/kcl_mm.h index 6a9f864111c47..a3fb87d51aa61 100644 --- a/include/kcl/kcl_mm.h +++ b/include/kcl/kcl_mm.h @@ -26,10 +26,6 @@ extern void (*_kcl_mmput_async)(struct mm_struct *mm); #endif -#ifndef HAVE_GET_MM_EXE_FILE -extern struct file *(*_kcl_get_mm_exe_file)(struct mm_struct *mm); -#endif - #ifndef HAVE_FAULT_FLAG_ALLOW_RETRY_FIRST static inline bool fault_flag_allow_retry_first(unsigned int flags) { From dbb622033805bcbfbb5427d3079fc659c19bbc2a Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 15 Mar 2022 16:28:03 +0800 Subject: [PATCH 0666/1868] drm/amdkcl: add missing AC_AMDGPU_PM_SUSPEND_TARGET_STATE Signed-off-by: Flora Cui Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 08aa50b88dc69..5b3cc9eb92891 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -197,6 +197,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DMA_FENCE_DESCRIBE AC_AMDGPU_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT AC_AMDGPU_PCIE_ASPM_ENABLED + AC_AMDGPU_PM_SUSPEND_TARGET_STATE AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 5daedc48388a0927124d0b71d7f283d4addac23f Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 17 Mar 2022 13:15:35 +0800 Subject: [PATCH 0667/1868] drm/amdkcl: Test whether smca_get_bank_type() is exported v2: add CONFIG_X86_MCE_AMD guard v3: remove CONFIG_X86 guard v4: improve test for struct smca_bank and kcl implementation of smca_get_bank_type() Signed-off-by: Leslie Shi Reviewed-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_mce_amd.c | 42 +++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 6 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../gpu/drm/amd/dkms/m4/smca_get_bank_type.m4 | 27 ++++++++++++ include/kcl/kcl_mce.h | 13 +++++- 7 files changed, 89 insertions(+), 3 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_mce_amd.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/smca_get_bank_type.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index d268f4a39a272..4f4e70f2280c1 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -13,7 +13,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o kcl_ftrace.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_fs_read_write.o kcl_drm_aperture.o \ kcl_drm_drv.o kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o \ - kcl_drm_nomodeset.o + kcl_drm_nomodeset.o kcl_mce_amd.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_mce_amd.c b/drivers/gpu/drm/amd/amdkcl/kcl_mce_amd.c new file mode 100644 index 0000000000000..30e62d94fbead --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_mce_amd.c @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * (c) 2005-2016 Advanced Micro Devices, Inc. + * + * Written by Jacob Shin - AMD, Inc. + * Maintained by: Borislav Petkov + * + * All MC4_MISCi registers are shared between cores on a node. + */ + + +#ifdef CONFIG_X86_MCE_AMD +#include + +#ifndef HAVE_SMCA_GET_BANK_TYPE + +/* Copied from v5.15-rc2-452-gf38ce910d8df:arch/x86/kernel/cpu/mce/amd.c and modified for KCL */ +#ifdef HAVE_SMCA_BANK_STRUCT +enum smca_bank_types smca_get_bank_type(unsigned int bank) +{ + struct smca_bank *b; + + if (bank >= MAX_NR_BANKS) + return N_SMCA_BANK_TYPES; + + b = &smca_banks[bank]; + if (!b->hwid) + return N_SMCA_BANK_TYPES; + + return b->hwid->bank_type; +} +#else +int smca_get_bank_type(unsigned int bank) +{ + pr_warn_once("smca_get_bank_type is not supported\n"); + return 0; +} +#endif /* HAVE_SMCA_BANK_STRUCT */ +EXPORT_SYMBOL_GPL(smca_get_bank_type); +#endif /* HAVE_SMCA_GET_BANK_TYPE */ + +#endif /* CONFIG_X86_MCE_AMD */ diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 1887b9a0952fd..5498d12b697f2 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -90,4 +90,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 77555469a3de5..34277bb23679b 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -999,6 +999,9 @@ /* whether si_mem_available() is available */ #define HAVE_SI_MEM_AVAILABLE 1 +/* smca_get_bank_type() is available */ +#define HAVE_SMCA_GET_BANK_TYPE 1 + /* is_smca_umc_v2() is available */ /* #undef HAVE_SMCA_UMC_V2 */ @@ -1090,6 +1093,9 @@ /* drm_plane_helper_funcs->prepare_fb() wants p,p arg */ #define HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_PREPARE_FB_PP 1 +/* struct smca_bank is available */ +/* #undef HAVE_STRUCT_SMCA_BANK */ + /* struct xarray is available */ #define HAVE_STRUCT_XARRAY 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 5b3cc9eb92891..db75a8ee860de 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -198,6 +198,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT AC_AMDGPU_PCIE_ASPM_ENABLED AC_AMDGPU_PM_SUSPEND_TARGET_STATE + AC_AMDGPU_SMCA_GET_BANK_TYPE AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/smca_get_bank_type.m4 b/drivers/gpu/drm/amd/dkms/m4/smca_get_bank_type.m4 new file mode 100644 index 0000000000000..2ed1eef7d5149 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/smca_get_bank_type.m4 @@ -0,0 +1,27 @@ +dnl # +dnl # +dnl # v5.15-rc2-452-gf38ce910d8df x86/MCE/AMD: Export smca_get_bank_type symbol +dnl # +AC_DEFUN([AC_AMDGPU_SMCA_GET_BANK_TYPE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([smca_get_bank_type], + [arch/x86/kernel/cpu/mce/amd.c], [ + AC_DEFINE(HAVE_SMCA_GET_BANK_TYPE, 1, + [smca_get_bank_type() is available]) + ], [ + dnl # + dnl # + dnl # v4.9-rc4-4-g79349f529ab1 x86/RAS: Simplify SMCA bank descriptor struct + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct smca_bank *b = NULL; + b->id = 0; + ], [ + AC_DEFINE(HAVE_STRUCT_SMCA_BANK, 1, + [struct smca_bank is available]) + ]) + ]) + ]) +]) diff --git a/include/kcl/kcl_mce.h b/include/kcl/kcl_mce.h index 5418ec9351e36..fee8c17c7d8fc 100644 --- a/include/kcl/kcl_mce.h +++ b/include/kcl/kcl_mce.h @@ -2,7 +2,7 @@ #ifndef AMDKCL_MCE_H #define AMDKCL_MCE_H -#ifdef CONFIG_X86 +#ifdef CONFIG_X86_MCE_AMD #include @@ -11,5 +11,14 @@ #define XEC(x, mask) (((x) >> 16) & mask) #endif -#endif /* CONFIG_X86 */ + +#if !defined(HAVE_SMCA_GET_BANK_TYPE) && defined(HAVE_SMCA_BANK_STRUCT) +enum smca_bank_types smca_get_bank_type(unsigned int bank); +#endif + +#ifndef HAVE_MCE_PRIO_UC +#define MCE_PRIO_UC MCE_PRIO_SRAO +#endif + +#endif /* CONFIG_X86_MCE_AMD */ #endif From f7c9c903abd6b31313d72662284198201f172b9c Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 17 Mar 2022 14:56:32 +0800 Subject: [PATCH 0668/1868] drm/amdkcl: Test whether enum MCE_PRIO_UC is available v2: define MCE_PRIO_UC macro if HAVE_MCE_PRIO_UC is not defined Signed-off-by: Leslie Shi Reviewed-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/mce_notifier_prios.m4 | 15 +++++++++++++++ 3 files changed, 19 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/mce_notifier_prios.m4 diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 34277bb23679b..c68804bb5cd39 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -882,6 +882,9 @@ /* list_rotate_to_front() is available */ #define HAVE_LIST_ROTATE_TO_FRONT 1 +/* enum MCE_PRIO_UC is available */ +#define HAVE_MCE_PRIO_UC 1 + /* memalloc_nofs_{save,restore}() are available */ #define HAVE_MEMALLOC_NOFS_SAVE 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index db75a8ee860de..f58c5ca740bdc 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -199,6 +199,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_PCIE_ASPM_ENABLED AC_AMDGPU_PM_SUSPEND_TARGET_STATE AC_AMDGPU_SMCA_GET_BANK_TYPE + AC_AMDGPU_MCE_PRIO_UC AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/mce_notifier_prios.m4 b/drivers/gpu/drm/amd/dkms/m4/mce_notifier_prios.m4 new file mode 100644 index 0000000000000..ac2a78006ea2e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/mce_notifier_prios.m4 @@ -0,0 +1,15 @@ +dnl # +dnl # +dnl # v5.5-rc2-5-g8438b84ab42d x86/mce: Take action on UCNA/Deferred errors again +dnl # +AC_DEFUN([AC_AMDGPU_MCE_PRIO_UC], [ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + enum mce_notifier_prios pri; + pri = MCE_PRIO_UC; + ], [ + AC_DEFINE(HAVE_MCE_PRIO_UC, 1, + [enum MCE_PRIO_UC is available]) + ]) +]) From 55371f3aa3ee8922f86c7143c7cd35c2d1ab5913 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 15 Mar 2022 16:28:28 +0800 Subject: [PATCH 0669/1868] drm/amdkcl: fix test for generic_handle_domain_irq Signed-off-by: Flora Cui Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/m4/generic_handle_domain_irq.m4 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/generic_handle_domain_irq.m4 b/drivers/gpu/drm/amd/dkms/m4/generic_handle_domain_irq.m4 index d02f0f7f60014..01d095dd14cb8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/generic_handle_domain_irq.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/generic_handle_domain_irq.m4 @@ -5,7 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_GENERIC_HANDLE_DOMAIN_IRQ], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #include + #include ], [ generic_handle_domain_irq(NULL, 0); ], [ From 5e053b48078ab5e6b54d73258fb34464871b251d Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 15 Mar 2022 17:58:08 +0800 Subject: [PATCH 0670/1868] drm/amdkcl: fix test for drm_edid_get_monitor_name Signed-off-by: Flora Cui Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/m4/drm-edid-get-monitor-name.m4 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-edid-get-monitor-name.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-edid-get-monitor-name.m4 index c5de63f48eb91..4a6a10c962f4c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-edid-get-monitor-name.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-edid-get-monitor-name.m4 @@ -7,7 +7,7 @@ AC_DEFUN([AC_AMDGPU_DRM_EDID_GET_MONITOR_NAME], [ AC_KERNEL_TRY_COMPILE_SYMBOL([ #include ], [ - drm_edid_get_monitor_name(NULL, NULL, NULL); + drm_edid_get_monitor_name(NULL, NULL, 0); ], [drm_edid_get_monitor_name], [drivers/gpu/drm/drm_edid.c], [ AC_DEFINE(HAVE_DRM_EDID_GET_MONITOR_NAME, 1, [drm_edid_get_monitor_name() are available]) From 29b4e51312c027706a355385887fc49b0bc6d64d Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Mon, 28 Mar 2022 09:52:24 +0800 Subject: [PATCH 0671/1868] drm/amdkcl: Add drm_dbg_* related definition Add the drm_dbg_state, drm_dbg_vbl and related macro definition for older versions of kernel. Reviewed-by: Flora Cui Signed-off-by: Ma Jun Change-Id: Ia5766e1b9d51b2ceedd1f42b1866a6c836c729d6 --- include/kcl/kcl_drm_print.h | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index a7ef405b97cdc..f4a7ee6d44a16 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -125,6 +125,14 @@ void kcl_drm_err(const char *format, ...); #define HAVE_DRM_ERR_MACRO #endif /* drm_err */ +#if !defined(DRM_UT_STATE) +#define DRM_UT_STATE 0x40 +#endif + +#if !defined(DRM_UT_VBL) +#define DRM_UT_VBL 0x20 +#endif + #if !defined(DRM_DEV_DEBUG) #define DRM_DEV_DEBUG(dev, fmt, ...) \ DRM_DEBUG(fmt, ##__VA_ARGS__) @@ -136,7 +144,6 @@ void kcl_drm_err(const char *format, ...); #endif #ifndef DRM_DEBUG_VBL -#define DRM_UT_VBL 0x20 #define DRM_DEBUG_VBL(fmt, args...) \ do { \ if (unlikely(drm_debug & DRM_UT_VBL)) \ @@ -153,6 +160,16 @@ void drm_dev_dbg(const struct device *dev, int category, const char *format, ... drm_dev_dbg((drm)->dev, DRM_UT_ATOMIC, fmt, ##__VA_ARGS__) #endif +#if !defined(drm_dbg_state) +#define drm_dbg_state(drm, fmt, ...) \ + drm_dev_dbg((drm) ? (drm)->dev : NULL, DRM_UT_STATE, fmt, ##__VA_ARGS__) +#endif + +#if !defined(drm_dbg_vbl) +#define drm_dbg_vbl(drm, fmt, ...) \ + drm_dev_dbg((drm) ? (drm)->dev : NULL, DRM_UT_VBL, fmt, ##__VA_ARGS__) +#endif + #if !defined(drm_dbg_kms) #define drm_dbg_kms(drm, fmt, ...) \ drm_dev_dbg((drm)->dev, 0x04, fmt, ##__VA_ARGS__) From 5558b68f69daaff323beeffda3fbeefe4168ace2 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 31 Mar 2022 18:11:19 +0800 Subject: [PATCH 0672/1868] drm/amdkcl: rework kcl implementation drm_firmware_drivers_only() Signed-off-by: Flora Cui Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- .../gpu/drm/amd/amdkcl/kcl_drm_nomodeset.c | 25 ------------------- .../amd/dkms/m4/drm_firmware_drivers_only.m4 | 12 ++++----- include/kcl/backport/kcl_drm_drv.h | 6 +++++ 4 files changed, 13 insertions(+), 32 deletions(-) delete mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_nomodeset.c diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 4f4e70f2280c1..97214f65dfbe2 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -13,7 +13,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o kcl_ftrace.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_fs_read_write.o kcl_drm_aperture.o \ kcl_drm_drv.o kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o \ - kcl_drm_nomodeset.o kcl_mce_amd.o + kcl_mce_amd.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_nomodeset.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_nomodeset.c deleted file mode 100644 index c60ce331ebb3a..0000000000000 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_nomodeset.c +++ /dev/null @@ -1,25 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 - -#ifndef HAVE_DRM_FIRMWARE_DRIVERS_ONLY - -static bool drm_nomodeset; - -bool drm_firmware_drivers_only(void) -{ - return drm_nomodeset; -} -EXPORT_SYMBOL(drm_firmware_drivers_only); - -static int __init disable_modeset(char *str) -{ - drm_nomodeset = true; - - pr_warn("Booted with the nomodeset parameter. Only the system framebuffer will be available\n"); - - return 1; -} - -/* Disable kernel modesetting */ -__setup("nomodeset", disable_modeset); - -#endif diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_firmware_drivers_only.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_firmware_drivers_only.m4 index b390e877bece7..3d95cd4406fe2 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_firmware_drivers_only.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_firmware_drivers_only.m4 @@ -3,14 +3,14 @@ dnl # v5.16-rc1-268-g6a2d2ddf2c34 dnl # drm: Move nomodeset kernel parameter to the DRM subsystem dnl # AC_DEFUN([AC_AMDGPU_DRM_FIRMWARE_DRIVERS_ONLY], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ #include ], [ drm_firmware_drivers_only(); ], [ - AC_DEFINE(HAVE_DRM_FIRMWARE_DRIVERS_ONLY, 1, - [drm_firmware_drivers_only() is available]) - ]) - ]) + AC_DEFINE(HAVE_DRM_FIRMWARE_DRIVERS_ONLY, 1, + [drm_firmware_drivers_only() is available]) + ]) + ]) ]) diff --git a/include/kcl/backport/kcl_drm_drv.h b/include/kcl/backport/kcl_drm_drv.h index dcc5c195b2d08..2fd32a57bb5d5 100644 --- a/include/kcl/backport/kcl_drm_drv.h +++ b/include/kcl/backport/kcl_drm_drv.h @@ -27,6 +27,7 @@ #ifndef __KCL_BACKPORT_KCL_DRM_DRV_H__ #define __KCL_BACKPORT_KCL_DRM_DRV_H__ +#include /* * v5.1-rc5-1150-gbd53280ef042 drm/drv: Fix incorrect resolution of merge conflict * v5.1-rc2-5-g3f04e0a6cfeb drm: Fix drm_release() and device unplug @@ -49,4 +50,9 @@ void _kcl_drm_dev_unplug(struct drm_device *dev) #define drm_dev_unplug _kcl_drm_dev_unplug #endif + +#ifndef HAVE_DRM_FIRMWARE_DRIVERS_ONLY +#define drm_firmware_drivers_only vgacon_text_force +#endif /* HAVE_DRM_FIRMWARE_DRIVERS_ONLY */ + #endif From 0b1eda6fda105bdee599cde887ce2fab04ebbd47 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 6 Apr 2022 13:18:51 +0800 Subject: [PATCH 0673/1868] drm/amdkcl: fix kcl of smca_get_bank_type() Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- include/kcl/kcl_mce.h | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/include/kcl/kcl_mce.h b/include/kcl/kcl_mce.h index fee8c17c7d8fc..80625b60944b7 100644 --- a/include/kcl/kcl_mce.h +++ b/include/kcl/kcl_mce.h @@ -11,9 +11,12 @@ #define XEC(x, mask) (((x) >> 16) & mask) #endif - -#if !defined(HAVE_SMCA_GET_BANK_TYPE) && defined(HAVE_SMCA_BANK_STRUCT) +#if !defined(HAVE_SMCA_GET_BANK_TYPE) +#ifdef HAVE_SMCA_BANK_STRUCT enum smca_bank_types smca_get_bank_type(unsigned int bank); +#else +int smca_get_bank_type(unsigned int bank); +#endif #endif #ifndef HAVE_MCE_PRIO_UC From 8f15fe755e6bb5cc39d7d8f4fd0961475ddd5358 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Fri, 8 Apr 2022 10:33:53 +0800 Subject: [PATCH 0674/1868] drm/amdkcl: Check if x86_hypervisor_type is defined Check and define x86_hypervisor_type for older versions of kernel Signed-off-by: Ma Jun Reviewed-by: Flora Cui Change-Id: I1428dcf4c10a7ceaa6b42815370589fdeba8595a --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../drm/amd/dkms/m4/x86_hypervisor_type.m4 | 19 +++++++++++++++++ include/kcl/kcl_hypervisor.h | 21 +++++++++++++++++++ 5 files changed, 45 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/x86_hypervisor_type.m4 create mode 100644 include/kcl/kcl_hypervisor.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 5498d12b697f2..3428419009f27 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -91,4 +91,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index c68804bb5cd39..55a59e5b5011c 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1213,6 +1213,9 @@ /* pm_suspend_target_state is available */ #define HAVE_PM_SUSPEND_TARGET_STATE 1 +/* enum x86_hypervisor_type is available */ +#define HAVE_X86_HYPERVISOR_TYPE 1 + /* Define to the address where bug reports for this package should be sent. */ #define PACKAGE_BUGREPORT "" diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index f58c5ca740bdc..e762b09497202 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -200,6 +200,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_PM_SUSPEND_TARGET_STATE AC_AMDGPU_SMCA_GET_BANK_TYPE AC_AMDGPU_MCE_PRIO_UC + AC_AMDGPU_X86_HYPERVISOR_TYPE AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/x86_hypervisor_type.m4 b/drivers/gpu/drm/amd/dkms/m4/x86_hypervisor_type.m4 new file mode 100644 index 0000000000000..677a6050d5745 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/x86_hypervisor_type.m4 @@ -0,0 +1,19 @@ +dnl # +dnl # commit: 03b2a320b19f1424e9ac9c21696be9c60b6d0d93 +dnl # x86/virt: Add enum for hypervisors to replace x86_hyper +dnl # +AC_DEFUN([AC_AMDGPU_X86_HYPERVISOR_TYPE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + enum x86_hypervisor_type test; + test = X86_HYPER_NATIVE; + ], [ + AC_DEFINE(HAVE_X86_HYPERVISOR_TYPE, 1, + [enum x86_hypervisor_type is available]) + ], [ + ]) + ]) +]) \ No newline at end of file diff --git a/include/kcl/kcl_hypervisor.h b/include/kcl/kcl_hypervisor.h new file mode 100644 index 0000000000000..270d6ddb53d44 --- /dev/null +++ b/include/kcl/kcl_hypervisor.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_HYPERVISOR_H +#define AMDKCL_HYPERVISOR_H + +#include + +#ifdef CONFIG_X86 +#if !defined(HAVE_X86_HYPERVISOR_TYPE) +enum x86_hypervisor_type { + X86_HYPER_NATIVE = 0, + X86_HYPER_VMWARE, + X86_HYPER_MS_HYPERV, + X86_HYPER_XEN_PV, + X86_HYPER_XEN_HVM, + X86_HYPER_KVM, + X86_HYPER_JAILHOUSE, + X86_HYPER_ACRN, +}; +#endif +#endif +#endif From 2273345277d38eb0652497adc8cca91c03122b7d Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Fri, 8 Apr 2022 14:08:51 +0800 Subject: [PATCH 0675/1868] drm/amdkcl: Implement the hypervisor_is_type function Implement the hypervisor_is_type() function for older versions of kernel. Signed-off-by: Ma Jun Reviewed-by: Flora Cui Change-Id: Ib1dc33d7d6e02037e756c602bc21200e6941827c --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../gpu/drm/amd/dkms/m4/hypervisor_is_type.m4 | 18 ++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_hypervisor.h | 10 +++++++++- 4 files changed, 31 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/hypervisor_is_type.m4 diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 55a59e5b5011c..8f3e304cf8e52 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1216,6 +1216,9 @@ /* enum x86_hypervisor_type is available */ #define HAVE_X86_HYPERVISOR_TYPE 1 +/* hypervisor_is_type() is available */ +#define HAVE_HYPERVISOR_IS_TYPE 1 + /* Define to the address where bug reports for this package should be sent. */ #define PACKAGE_BUGREPORT "" diff --git a/drivers/gpu/drm/amd/dkms/m4/hypervisor_is_type.m4 b/drivers/gpu/drm/amd/dkms/m4/hypervisor_is_type.m4 new file mode 100644 index 0000000000000..2d2702416ffd7 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/hypervisor_is_type.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit: 79cc74155218316b9a5d28577c7077b2adba8e58 +dnl # x86/paravirt: Provide a way to check for hypervisors +dnl # +AC_DEFUN([AC_AMDGPU_HYPERVISOR_IS_TYPE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + hypervisor_is_type(X86_HYPER_NATIVE); + ], [ + AC_DEFINE(HAVE_HYPERVISOR_IS_TYPE, 1, + [hypervisor_is_type() is available]) + ], [ + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index e762b09497202..1a53f175347c4 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -201,6 +201,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_SMCA_GET_BANK_TYPE AC_AMDGPU_MCE_PRIO_UC AC_AMDGPU_X86_HYPERVISOR_TYPE + AC_AMDGPU_HYPERVISOR_IS_TYPE AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_hypervisor.h b/include/kcl/kcl_hypervisor.h index 270d6ddb53d44..60521c70b9ba5 100644 --- a/include/kcl/kcl_hypervisor.h +++ b/include/kcl/kcl_hypervisor.h @@ -17,5 +17,13 @@ enum x86_hypervisor_type { X86_HYPER_ACRN, }; #endif + +#ifndef HAVE_HYPERVISOR_IS_TYPE +static inline bool hypervisor_is_type(enum x86_hypervisor_type type) +{ + return false; +} #endif -#endif + +#endif /* CONFIG_X86 */ +#endif /* AMDKCL_HYPERVISOR_H */ From d231d8f6056b8b3815ed6a4bf2a2a84476f0d1a2 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Tue, 12 Apr 2022 10:34:35 +0800 Subject: [PATCH 0676/1868] drm/amdkcl: Add support for ullong type module parameter Add support for ullong type module parameter in older versions of kernel. Signed-off-by: Ma Jun Reviewed-by: Flora Cui Change-Id: Ief04a76fb56a00632df15041df612d0e3256e5c4 --- drivers/gpu/drm/amd/amdkcl/kcl_kernel_params.c | 4 ++++ include/kcl/kcl_moduleparam.h | 8 ++++++++ 2 files changed, 12 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_kernel_params.c b/drivers/gpu/drm/amd/amdkcl/kcl_kernel_params.c index d350a6bd07769..10fe1c5d9d9c4 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_kernel_params.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_kernel_params.c @@ -27,3 +27,7 @@ #ifdef _kcl_param_check_hexint STANDARD_PARAM_DEF(hexint, unsigned int, "%#08x", kstrtouint); #endif + +#ifdef _kcl_param_check_ullong +STANDARD_PARAM_DEF(ullong, unsigned long long, "%llu", kstrtoull); +#endif \ No newline at end of file diff --git a/include/kcl/kcl_moduleparam.h b/include/kcl/kcl_moduleparam.h index 427abe45ea8af..e579efe182bbd 100644 --- a/include/kcl/kcl_moduleparam.h +++ b/include/kcl/kcl_moduleparam.h @@ -14,4 +14,12 @@ extern int param_get_hexint(char *buffer, const struct kernel_param *kp); #define param_check_hexint(name, p) param_check_uint(name, p) #endif /* param_check_hexint */ +#ifndef param_check_ullong +#define _kcl_param_check_ullong +extern const struct kernel_param_ops param_ops_ullong; +extern int param_set_ullong(const char *val, const struct kernel_param *kp); +extern int param_get_ullong(char *buffer, const struct kernel_param *kp); +#define param_check_ullong(name, p) __param_check(name, p, unsigned long long) +#endif /* param_check_ullong */ + #endif From 6e23d9ddb24885341ad34cfeeaefa909475e89d2 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Tue, 12 Apr 2022 20:01:00 +0800 Subject: [PATCH 0677/1868] drm/amdkcl: Add PSR2 related macro Add PSR2 related macro definition for older versions of kernle. Signed-off-by: Ma Jun Change-Id: Id2d7ed0934faaaa2e91678426ea396cb99cbc54e --- include/kcl/kcl_drm_dp_helper.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/include/kcl/kcl_drm_dp_helper.h b/include/kcl/kcl_drm_dp_helper.h index 60b18feee18f4..74163ac1e0e2a 100644 --- a/include/kcl/kcl_drm_dp_helper.h +++ b/include/kcl/kcl_drm_dp_helper.h @@ -287,6 +287,20 @@ enum drm_dp_phy { #define DP_PSR2_SU_Y_GRANULARITY 0x074 /* eDP 1.4b */ #endif +/* + * drm: Add PSR version 3 macro + */ +#ifndef DP_PSR2_WITH_Y_COORD_IS_SUPPORTED +# define DP_PSR2_WITH_Y_COORD_IS_SUPPORTED 3 /* eDP 1.4a */ +#endif + +/* + * drm: add PSR2 support and capability definition as per eDP 1.5 + */ +#ifndef DP_PSR2_WITH_Y_COORD_ET_SUPPORTED +# define DP_PSR2_WITH_Y_COORD_ET_SUPPORTED 4 /* eDP 1.5, adopted eDP 1.4b SCR */ +#endif + /* * v4.10-rc3-483-gd0ce90629120 * drm : adds Y-coordinate and Colorimetry Format From 1c621c368b2503b846a4da080aef3c7ea5815561 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 19 Apr 2022 17:40:47 +0800 Subject: [PATCH 0678/1868] drm/amdkcl: add task_struct forward declaration Signed-off-by: Leslie Shi --- .../dkms/m4/drm_aperture_remove_conflicting_pci_framebuffers.m4 | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_aperture_remove_conflicting_pci_framebuffers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_aperture_remove_conflicting_pci_framebuffers.m4 index 50e28229344bf..87f2f1c951581 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_aperture_remove_conflicting_pci_framebuffers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_aperture_remove_conflicting_pci_framebuffers.m4 @@ -9,6 +9,7 @@ AC_DEFUN([AC_AMDGPU_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS], [ dnl # v5.3-rc1-540-g0a8459693238 fbdev: drop res_id parameter from remove_conflicting_pci_framebuffers dnl # AC_KERNEL_TRY_COMPILE([ + struct task_struct; #include ], [ remove_conflicting_pci_framebuffers(NULL, NULL); From f51aee4265573b96b1324a8b40d99857df797294 Mon Sep 17 00:00:00 2001 From: "Tianci.Yin" Date: Mon, 15 Nov 2021 10:44:32 +0800 Subject: [PATCH 0679/1868] drm/amdkcl: fix screen tile blur issue on kernel older than 4.9 [why] The member "modifier" of struct drm_framebuffer is introduced by patch "drm: Extract drm_framebuffer.[hc]" at v4.9-rc1. But the Redhat7.9 distributes with kernel v3.10, on this version, parameter "flags" of fill_dcc_params_from_flags() was used to pass dcc info, this "flags" substituted by "modifier" later. So dcc->dcc_ind_blk should also need assigned according to "flags" like what's done in "drm/amd/display: Use dcc_ind_blk value to set register directly". [how] Assign dcc->dcc_ind_blk accordingly. The current kernel does not use "flags" but "modifier", so this patch does not need to go drm-next. The "flags" and "modifier" can coexist, the new code lines does not need the condition that the "modifier" does not exist. Change-Id: I7e42d77fb84a1607d5412842e1c63ad581fae041 Reviewed-by: Guchun Chen Signed-off-by: Tianci.Yin (cherry picked from commit 6b66219a356b579df249e2d8bd2b49b6ce595f59) Signed-off-by: Ma Jun --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 851a175923b32..c6f2c892ba34d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -322,6 +322,11 @@ fill_dcc_params_from_flags(const struct amdgpu_framebuffer *afb, dcc->meta_pitch = AMDGPU_TILING_GET(flags, DCC_PITCH_MAX) + 1; dcc->independent_64b_blks = i64b; + if (dcc->independent_64b_blks) + dcc->dcc_ind_blk = hubp_ind_block_64b; + else + dcc->dcc_ind_blk = hubp_ind_block_unconstrained; + dcc_address = plane_address + (uint64_t)offset * 256; address->grph.meta_addr.low_part = lower_32_bits(dcc_address); address->grph.meta_addr.high_part = upper_32_bits(dcc_address); From 01aa52f6be55425e005f58419e21b5c50631ea38 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Sat, 7 May 2022 15:53:28 +0800 Subject: [PATCH 0680/1868] drm/amdkcl:Add the INTEL_FAM6_ALDERLAKE definition Add the INTEL_FAM6_ALDERLAKE definition for older verisons of kernel. Signed-off-by: Ma Jun Reviewed-by: Flora Cui Change-Id: I3e88fe0aa0f6b7be48bcd23be5b5dc63edf7274e --- include/kcl/kcl_intel_family.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/kcl/kcl_intel_family.h b/include/kcl/kcl_intel_family.h index a4d7693bf0b0b..90793a772861b 100644 --- a/include/kcl/kcl_intel_family.h +++ b/include/kcl/kcl_intel_family.h @@ -10,5 +10,9 @@ #define INTEL_FAM6_ROCKETLAKE 0xA7 #endif +#ifndef INTEL_FAM6_ALDERLAKE +#define INTEL_FAM6_ALDERLAKE 0x97 /* Golden Cove / Gracemont */ +#endif + #endif /* CONFIG_X86 */ #endif From e84ee0780cf38346cff83098b184a4fc6d1df729 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Sat, 7 May 2022 16:17:00 +0800 Subject: [PATCH 0681/1868] drm/amdkcl:Add DRM_DEV_INFO macro definition Add DRM_DEV_INFO macro definition for older versions of kernel. Signed-off-by: Ma Jun Reviewed-by: Flora Cui Change-Id: I0337286e68f45420232e652f3c42cf0cb340260e --- include/kcl/kcl_drm_print.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index f4a7ee6d44a16..bba9e048cf699 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -143,6 +143,12 @@ void kcl_drm_err(const char *format, ...); DRM_ERROR(fmt, ##__VA_ARGS__) #endif +#ifndef DRM_DEV_INFO +/* NOTE: this is deprecated in favor of drm_info() or dev_info(). */ +#define DRM_DEV_INFO(dev, fmt, ...) \ + DRM_INFO(fmt, ##__VA_ARGS__) +#endif + #ifndef DRM_DEBUG_VBL #define DRM_DEBUG_VBL(fmt, args...) \ do { \ From 3ce13a4bba00b789edf3671ed80485026a54f76e Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 16 May 2022 12:04:45 +0800 Subject: [PATCH 0682/1868] drm/amdkcl: fix access_ok prototype MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit fix warning drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_smi_events.c: In function ‘kfd_smi_ev_write’: drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_smi_events.c:128:21: warning: passing argument 1 of ‘kcl_access_ok’ makes integer from pointer without a cast [-Wint-conversion] Signed-off-by: Flora Cui Reviewed-by: Guchun Chen Reviewed-by: Leslie Shi --- include/kcl/backport/kcl_uaccess_backport.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/kcl/backport/kcl_uaccess_backport.h b/include/kcl/backport/kcl_uaccess_backport.h index 5e358c64a8fce..e781a42201f49 100644 --- a/include/kcl/backport/kcl_uaccess_backport.h +++ b/include/kcl/backport/kcl_uaccess_backport.h @@ -3,7 +3,7 @@ #define AMDKCL_UACCESS_BACKPORT_H #include -static inline int kcl_access_ok(unsigned long addr, unsigned long size) +static inline int kcl_access_ok(const void __user *addr, unsigned long size) { #if !defined(HAVE_ACCESS_OK_WITH_TWO_ARGUMENTS) return access_ok(VERIFY_WRITE, (addr), (size)); From 51d83fe060c8ad99b17c49082523051a8614e07f Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 11 May 2022 10:39:14 +0800 Subject: [PATCH 0683/1868] drm/amdkcl: Add the DP_PHY_REPEATER_128B132B_RATES definition Add the macro definiton of DP_PHY_REPEATER_128B132B_RATES for older versions of kernel. Signed-off-by: Ma Jun Reviewed-by: Leslie Shi Change-Id: If48731e99796af81c36599f26d6497ab11f7aa18 --- include/kcl/kcl_drm_dp_helper.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/kcl/kcl_drm_dp_helper.h b/include/kcl/kcl_drm_dp_helper.h index 74163ac1e0e2a..e379e156b74d9 100644 --- a/include/kcl/kcl_drm_dp_helper.h +++ b/include/kcl/kcl_drm_dp_helper.h @@ -158,6 +158,11 @@ #define DP_DSC_THROUGHPUT_MODE_0_UNSUPPORTED DP_DSC_THROUGHPUT_MODE_0_UPSUPPORTED #endif +#ifndef DP_PHY_REPEATER_128B132B_RATES +/* See DP_128B132B_SUPPORTED_LINK_RATES for values */ +#define DP_PHY_REPEATER_128B132B_RATES 0xf0007 /* 2.0 */ +#endif + /* v5.9-rc4-979-g9782f52ab5d6 * drm/dp: Add LTTPR helpers */ From 9706e9090ac93655a5602de1eb44dafcd3fa8096 Mon Sep 17 00:00:00 2001 From: Ramesh Errabolu Date: Wed, 13 Apr 2022 13:14:29 -0500 Subject: [PATCH 0684/1868] drm/amdgpu: Access MMIO/DOORBELL BO's of peer devices when IOMMU is ON Current design does not allow a GPU to access MMIO/DOORBELL memory of a peer device when IOMMU is turned ON. Changes made by this patch relax this constraint i.e. it allows GPU's to access MMIO/DOORBELL memory of peer devices without regard to IOMMU being ON or OFF. Signed-off-by: Ramesh Errabolu Reviewed-by: Felix Kuehling --- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 42 +++++++++++-------- 1 file changed, 24 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 7bb7812e717cc..3664bcb90a179 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -999,10 +999,24 @@ static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem, &bo[i], attachment[i]); if (ret) goto unwind; + + /* Handle DOORBELL BOs of peer devices and MMIO BOs of local and peer devices */ + } else if ((mem->bo->tbo.type == ttm_bo_type_sg) && + ((mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) || + (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP))) { + attachment[i]->type = KFD_MEM_ATT_SG; + ret = create_dmamap_sg_bo(adev, mem, &bo[i]); + if (ret) + goto unwind; } else { +#ifdef AMDKCL_AMDGPU_DMABUF_OPS WARN_ONCE(true, "Handling invalid ATTACH request"); ret = -EINVAL; goto unwind; +#endif + attachment[i]->type = KFD_MEM_ATT_SHARED; + bo[i] = mem->bo; + drm_gem_object_get(&bo[i]->tbo.base); } /* Add BO to VM internal data structures */ @@ -2486,35 +2500,27 @@ void amdgpu_amdkfd_gpuvm_put_bo_ref(struct amdgpu_bo *bo) /** * @get_sg_table_of_mmio_or_doorbel_bo - Builds and returns an instance - * of scatter gather table (sg_table) for BO's that represent MMIO or - * DOORBELL memory. An example of this is the MMIO BO that is used to - * surface HDP registers. + * of scatter gather table (sg_table) for a MMIO/DOORBELL BO. An example + * of this is the MMIO BO that's used to surface HDP registers. * - * @note: Per current design and implementation MMIO or DOORBELL BO's - * use only one scatterlist node in their sg_table. This is because - * the size of backing memory is relatively small (e.g. 4096 bytes - * for MMIO BO surfacing HDP registers). Implementation of this method - * relies on this design choice. + * @note: This method will only work as long as the address encapsulated + * by MMIO/DOORBELL BO is not a DMA mapped address * * The method does the following: * Acquire address to use in building scatterlist nodes * Acquire size of memory to use in building scatterlist nodes - * Invoke DMA Map service to obtain DMA'able address + * Invoke DMA Map service to obtain DMA mapped address * Access sg_table construction service with above parameters * Return the handle of scatter gather table * - * @adev: GPU device whose MMIO address needs to be exported - * @bo: Buffer object representing MMIO/DOORBELL memory e.g. HDP registers - * @dma_dev: Handle of peer PCIe device that wishes to access BO's memory + * @adev: GPU device whose MMIO/DOORBELL BO is being exported + * @bo: Handle of MMIO/DOORBELL BO e.g. HDP registers + * @dma_dev: Handle of peer PCIe device that wishes to access * @dir: Direction of data movement from peer PCIe devices perspective * * @sgt: Output parameter that is built and returned * * Return: zero if successful, non-zero otherwise - * - * @FIXME: This will only work as long as bo->tbo.sg->sgl->dma_address - * is not a DMA address but a physical BAR address. This will be reworked - * later when we add DMA mapping support for doorbell and MMIO BOs */ static int get_sg_table_of_mmio_or_doorbel_bo(struct amdgpu_bo *bo, struct device *dma_dev, enum dma_data_direction dir, @@ -2542,8 +2548,8 @@ static int get_sg_table_of_mmio_or_doorbel_bo(struct amdgpu_bo *bo, /* Update output parameter with a new sg_table */ pr_debug("MMIO/Doorbell BO size: %d\n", size); pr_debug("MMIO/Doorbell's DMA Address: %llx\n", dma_addr); - *sgt = create_doorbell_sg(dma_addr, size); - return 0; + *sgt = create_sg_table(dma_addr, size); + return (*sgt) ? 0 : -ENOMEM; } int amdgpu_amdkfd_gpuvm_get_sg_table(struct amdgpu_device *adev, From fb1e670b4cb42d35a23caa30f67ad6741fe811a7 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 2 Jun 2022 09:16:22 +0800 Subject: [PATCH 0685/1868] drm/amdkcl: Add macro definition for some new plane formats Add macro definition for some new plane formats Signed-off-by: Ma Jun Reviewed-by: Flora Cui Reviewed-by: Guchun Chen Change-Id: I290eefb6c39114a4790fde869429539957578e32 --- include/kcl/kcl_drm_fourcc.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/kcl/kcl_drm_fourcc.h b/include/kcl/kcl_drm_fourcc.h index 25cf40f897b23..959f64bb803a6 100644 --- a/include/kcl/kcl_drm_fourcc.h +++ b/include/kcl/kcl_drm_fourcc.h @@ -96,6 +96,14 @@ * 55:36 - Reserved for future use, must be zero */ +#ifndef AMD_FMT_MOD_TILE_VER_GFX11 +#define AMD_FMT_MOD_TILE_VER_GFX11 4 +#endif + +#ifndef AMD_FMT_MOD_TILE_GFX11_256K_R_X +#define AMD_FMT_MOD_TILE_GFX11_256K_R_X 31 +#endif + #if !defined(AMD_FMT_MOD) #define AMD_FMT_MOD fourcc_mod_code(AMD, 0) From d276bc68980be6ea418fa05a61b025f477bc2eab Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 9 Jun 2022 14:57:42 +0800 Subject: [PATCH 0686/1868] drm/amdkcl: Check if ltr_path is defined Check if ltr_path is defined in struct pci_dev Signed-off-by: Ma Jun Reviewed-by: Guchun Chen Change-Id: I55201dca99824b144f6272198f68dedc46f114ce --- drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c | 2 ++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/ltr_path.m4 | 18 ++++++++++++++++++ 4 files changed, 24 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/ltr_path.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c b/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c index a54052dea8bf5..8374df22a03d7 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v4_3.c @@ -375,9 +375,11 @@ static void nbio_v4_3_program_ltr(struct amdgpu_device *adev) WREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_BIF_STRAP2, data); def = data = RREG32_SOC15(NBIO, 0, regBIF_CFG_DEV0_EPF0_DEVICE_CNTL2); +#ifdef HAVE_PCI_DEV_LTR_PATH if (adev->pdev->ltr_path) data |= BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK; else +#endif data &= ~BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK; if (def != data) WREG32_SOC15(NBIO, 0, regBIF_CFG_DEV0_EPF0_DEVICE_CNTL2, data); diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 8f3e304cf8e52..b33a9460cce97 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -882,6 +882,9 @@ /* list_rotate_to_front() is available */ #define HAVE_LIST_ROTATE_TO_FRONT 1 +/* strurct pci_dev->ltr_path is available */ +#define HAVE_PCI_DEV_LTR_PATH 1 + /* enum MCE_PRIO_UC is available */ #define HAVE_MCE_PRIO_UC 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 1a53f175347c4..9f9901573e1bc 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -202,6 +202,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_MCE_PRIO_UC AC_AMDGPU_X86_HYPERVISOR_TYPE AC_AMDGPU_HYPERVISOR_IS_TYPE + AC_AMDGPU_PCI_DEV_LTR_PATH AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/ltr_path.m4 b/drivers/gpu/drm/amd/dkms/m4/ltr_path.m4 new file mode 100644 index 0000000000000..a629dac5f4aad --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/ltr_path.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit c46fd358070f22ba68d6e74c22016a33b914c20a +dnl # PCI/ASPM: Enable Latency Tolerance Reporting when supported +dnl # +dnl # +AC_DEFUN([AC_AMDGPU_PCI_DEV_LTR_PATH], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct pci_dev *dev; + dev->ltr_path = 0; + ], [ + AC_DEFINE(HAVE_PCI_DEV_LTR_PATH, 1, + [strurct pci_dev->ltr_path is available]) + ]) + ]) +]) From 9d43e6c8d7652ff9a1e65ec7b5f88f1ea8c5c83f Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Fri, 10 Jun 2022 20:43:25 +0800 Subject: [PATCH 0687/1868] drm/amdkcl: Check if display_info->edid_hdmi_rgb444_dc_modes is defined Check if display_info->edid_hdmi_rgb444_dc_modes is defined introduced in v4.9-rc1-522171951761153172c75b94ae1f4bc9ab631745 Signed-off-by: Yifan Zhang Signed-off-by: Ma Jun Change-Id: Ic2659a288fae2af696cf2c3d20c3e97491341c5f --- .../gpu/drm/amd/amdgpu/amdgpu_connectors.c | 4 ++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../gpu/drm/amd/dkms/m4/drm-display-info.m4 | 20 +++++++++++++++++++ 3 files changed, 27 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c index 8232d4ef60783..86058682b0d55 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c @@ -199,7 +199,11 @@ int amdgpu_connector_get_monitor_bpc(struct drm_connector *connector) /* Check if bpc is within clock limit. Try to degrade gracefully otherwise */ if ((bpc == 12) && (mode_clock * 3/2 > max_tmds_clock)) { +#ifndef HAVE_DRM_DISPLAY_INFO_EDID_HDMI_RGB444_DC_MODES + if ((connector->display_info.edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_30) && +#else if ((connector->display_info.edid_hdmi_rgb444_dc_modes & DRM_EDID_HDMI_DC_30) && +#endif (mode_clock * 5/4 <= max_tmds_clock)) bpc = 10; else diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index b33a9460cce97..52fed73a65292 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -300,6 +300,9 @@ /* drm_dev_unplug() is available */ #define HAVE_DRM_DEV_UNPLUG 1 +/* display_info->edid_hdmi_rgb444_dc_modes is available */ +#define HAVE_DRM_DISPLAY_INFO_EDID_HDMI_RGB444_DC_MODES 1 + /* display_info->hdmi.scdc.scrambling are available */ #define HAVE_DRM_DISPLAY_INFO_HDMI_SCDC_SCRAMBLING 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-display-info.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-display-info.m4 index 61eef3b454776..6e726111f8c16 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-display-info.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-display-info.m4 @@ -1,3 +1,22 @@ +dnl # +dnl # commit v4.9-rc1-522171951761153172c75b94ae1f4bc9ab631745 +dnl # drm: Extract drm_connector.[hc] +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DISPLAY_INFO_EDID_HDMI_RGB444_DC_MODES], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_display_info *display_info = NULL; + display_info->edid_hdmi_rgb444_dc_modes = 0; + ], [ + AC_DEFINE(HAVE_DRM_DISPLAY_INFO_EDID_HDMI_RGB444_DC_MODES, 1, + [display_info->edid_hdmi_rgb444_dc_modes is available]) + ]) + ]) +]) + + dnl # dnl # commit v5.6-rc2-1062-ga1d11d1efe4d dnl # drm/edid: Add function to parse EDID descriptors for monitor range @@ -18,5 +37,6 @@ AC_DEFUN([AC_AMDGPU_DRM_DISPLAY_INFO_MONITOR_RANGE], [ ]) AC_DEFUN([AC_AMDGPU_DRM_DISPLAY_INFO], [ + AC_AMDGPU_DRM_DISPLAY_INFO_EDID_HDMI_RGB444_DC_MODES AC_AMDGPU_DRM_DISPLAY_INFO_MONITOR_RANGE ]) From 6280e74239168b98eb6e3fffb5b5e526f06ff392 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Sun, 12 Jun 2022 16:58:46 +0800 Subject: [PATCH 0688/1868] drm/amdkcl: Check if cancel_work is defined Check and add cancel_work() function Signed-off-by: Ma Jun Reviewed-by: Flora Cui Change-Id: I002962a0476e253cbad2f4f414965c95b96b2d78 --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_workqueue.c | 41 +++++++++++++++++++ drivers/gpu/drm/amd/amdkcl/main.c | 2 + drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 ++ drivers/gpu/drm/amd/dkms/m4/cancel_work.m4 | 17 ++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/backport/kcl_workqueue_backport.h | 13 ++++++ 8 files changed, 79 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_workqueue.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/cancel_work.m4 create mode 100644 include/kcl/backport/kcl_workqueue_backport.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 97214f65dfbe2..d0ccd6f534348 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -13,7 +13,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o kcl_ftrace.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_fs_read_write.o kcl_drm_aperture.o \ kcl_drm_drv.o kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o \ - kcl_mce_amd.o + kcl_mce_amd.o kcl_workqueue.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_workqueue.c b/drivers/gpu/drm/amd/amdkcl/kcl_workqueue.c new file mode 100644 index 0000000000000..461066e047ac3 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_workqueue.c @@ -0,0 +1,41 @@ +/* + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include + +#ifndef HAVE_CANCEL_WORK +bool (*_kcl_cancel_work)(struct work_struct *work); +EXPORT_SYMBOL(_kcl_cancel_work); + +bool _kcl_cancel_work_stub(struct work_struct *work) +{ + pr_warn_once("cancel_work function is not supported\n"); + return false; +} +#endif + +void amdkcl_workqueue_init(void) +{ +#ifndef HAVE_CANCEL_WORK + _kcl_cancel_work = amdkcl_fp_setup("cancel_work", _kcl_cancel_work_stub); +#endif /* HAVE_CANCEL_WORK */ +} + diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c index feb2d6548f323..bd158234c6db0 100644 --- a/drivers/gpu/drm/amd/amdkcl/main.c +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -14,6 +14,7 @@ extern void amdkcl_pci_init(void); extern void amdkcl_suspend_init(void); extern void amdkcl_sched_init(void); extern void amdkcl_numa_init(void); +extern void amdkcl_workqueue_init(void); int __init amdkcl_init(void) { @@ -29,6 +30,7 @@ int __init amdkcl_init(void) amdkcl_suspend_init(); amdkcl_sched_init(); amdkcl_numa_init(); + amdkcl_workqueue_init(); return 0; } diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 3428419009f27..3de3c768a6147 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -92,4 +92,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 52fed73a65292..545032a26c018 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -52,6 +52,9 @@ /* bitmap_free() is available */ #define HAVE_BITMAP_FUNCS 1 +/* cancel_work() is available */ +#define HAVE_CANCEL_WORK 1 + /* whether CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL is defined */ #define HAVE_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/cancel_work.m4 b/drivers/gpu/drm/amd/dkms/m4/cancel_work.m4 new file mode 100644 index 0000000000000..b0cabe1643a14 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/cancel_work.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit id:c46fd358070f22ba68d6e74c22016a33b914c20a +dnl # PCI/ASPM: Enable Latency Tolerance Reporting when supported +dnl # +dnl # +AC_DEFUN([AC_AMDGPU_CANCEL_WORK], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + cancel_work(NULL); + ], [ + AC_DEFINE(HAVE_CANCEL_WORK, 1, + [cancel_work() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 9f9901573e1bc..321687e780f63 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -203,6 +203,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_X86_HYPERVISOR_TYPE AC_AMDGPU_HYPERVISOR_IS_TYPE AC_AMDGPU_PCI_DEV_LTR_PATH + AC_AMDGPU_CANCEL_WORK AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/backport/kcl_workqueue_backport.h b/include/kcl/backport/kcl_workqueue_backport.h new file mode 100644 index 0000000000000..3e6adabc0f08c --- /dev/null +++ b/include/kcl/backport/kcl_workqueue_backport.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#ifndef KCL_LINUX_WORKQUEUE_BACKPORT_H +#define KCL_LINUX_WORKQUEUE_BACKPORT_H + +#include + +#ifndef HAVE_CANCEL_WORK +extern bool (*_kcl_cancel_work)(struct work_struct *work); +#define cancel_work _kcl_cancel_work +#endif + +#endif /* KCL_LINUX_WORKQUEUE_BACKPORT_H */ From 462329387f3ec4aa83b6820fd674f545ac3860c0 Mon Sep 17 00:00:00 2001 From: Ramesh Errabolu Date: Wed, 8 Jun 2022 10:13:16 -0500 Subject: [PATCH 0689/1868] drm/amdgpu: Reduce P2P code divergence in DRM vs DKMS branches Cleans up the DKMS-version of P2P to reduce differences from the upstream implementation (DRM-version) without breaking the P2P functionality supported on the DKMS branch. Signed-off-by: Ramesh Errabolu Reviewed-by: Felix Kuehling Change-Id: I6de18c791a6def548024d03526de695b6032adff --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 16 +++------------- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 + 3 files changed, 5 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 98eaea4cd1ffe..49896e73c5aa3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -231,6 +231,7 @@ extern int amdgpu_noretry; extern int amdgpu_force_asic_type; extern int amdgpu_smartshift_bias; extern int amdgpu_use_xgmi_p2p; +extern bool pcie_p2p; extern int amdgpu_mtype_local; extern bool enforce_isolation; #ifdef CONFIG_HSA_AMD diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 3664bcb90a179..6294b3d62233d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -867,7 +867,7 @@ kfd_mem_attach_dmabuf(struct amdgpu_device *adev, struct kgd_mem *mem, * * Implementation determines if access to VRAM BO would employ DMABUF * or Shared BO mechanism. Employ DMABUF mechanism if kernel has config - * option DMABUF_MOVE_NOTIFY enabled. Employ Shared BO mechanism if above + * option HSA_AMD_P2P enabled. Employ Shared BO mechanism if above * config option is not set. It is important to note that a Shared BO * cannot be used to enable peer acces if system has IOMMU enabled * @@ -880,7 +880,7 @@ static int kfd_mem_attach_vram_bo(struct amdgpu_device *adev, { int ret = 0; -#if defined(CONFIG_DMABUF_MOVE_NOTIFY) && defined(CONFIG_PCI_P2PDMA) +#ifdef CONFIG_HSA_AMD_P2P attachment->type = KFD_MEM_ATT_DMABUF; ret = kfd_mem_attach_dmabuf(adev, mem, bo); pr_debug("Employ DMABUF mechanim to enable peer GPU access\n"); @@ -993,21 +993,11 @@ static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem, pr_debug("Employ DMABUF mechanism to enable peer GPU access\n"); #endif /* Enable peer acces to VRAM BO's */ - } else if (mem->domain == AMDGPU_GEM_DOMAIN_VRAM && - mem->bo->tbo.type == ttm_bo_type_device) { + } else if (mem->domain == AMDGPU_GEM_DOMAIN_VRAM) { ret = kfd_mem_attach_vram_bo(adev, mem, &bo[i], attachment[i]); if (ret) goto unwind; - - /* Handle DOORBELL BOs of peer devices and MMIO BOs of local and peer devices */ - } else if ((mem->bo->tbo.type == ttm_bo_type_sg) && - ((mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) || - (mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP))) { - attachment[i]->type = KFD_MEM_ATT_SG; - ret = create_dmamap_sg_bo(adev, mem, &bo[i]); - if (ret) - goto unwind; } else { #ifdef AMDKCL_AMDGPU_DMABUF_OPS WARN_ONCE(true, "Handling invalid ATTACH request"); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 83ef84052ddbf..637b16282a876 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -34,6 +34,7 @@ #include #include #include +#include #include #include From 6d4534858cc009d22531aa6faddad5e63a0f2f21 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Fri, 17 Jun 2022 16:02:27 +0800 Subject: [PATCH 0690/1868] drm/amdkcl: Fix 64 bit wraparound resulting in illegal drm mode [Why] For m = drm_display_mode{.clock = 533250, .htotal = 4000, .vtotal = 2222}, common_rates[i] = 60000, the result of target_vtotal is 2221. This cause wraparound of variable target_vtotal_diff. [How] Skip the loop if target_vtotal less than m->vtotal Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 7480e41ff02b9..ac0663b92a877 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8157,6 +8157,10 @@ static uint add_fs_modes(struct amdgpu_dm_connector *aconnector) num = (unsigned long long)m->clock * 1000 * 1000; den = common_rates[i] * (unsigned long long)m->htotal; target_vtotal = div_u64(num, den); + + if (target_vtotal < m->vtotal) + continue; + target_vtotal_diff = target_vtotal - m->vtotal; /* Check for illegal modes */ From fc972ca8a89c6b5ca64742cfff0bc0e154e92216 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Fri, 24 Jun 2022 09:02:20 +0800 Subject: [PATCH 0691/1868] drm/amdkcl: Change the temp build dir name Changing the build-XXXXXXXX to build.XXXXXXXX to fix the CFLAGS parse error in case of using build-Ixxx as temp dir name. Signed-off-by: Ma Jun Reviewed-by: Flora Cui Change-Id: I92ef6e3aaafae103b48d12786f3eac15b6bab708 --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 321687e780f63..65b1171ee3727 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -425,7 +425,7 @@ dnl # AC_KERNEL_TMP_BUILD_DIR dnl # $1: contents to be executed in a temporary directory dnl # AC_DEFUN([AC_KERNEL_TMP_BUILD_DIR], [ - build_dir=$(mktemp -d -t build-XXXXXXXX -p $build_dir_root) + build_dir=$(mktemp -d -t build_XXXXXXXX -p $build_dir_root) cd $build_dir $1 AS_IF([test -s confdefs.h], [ From 5cd2b21e60ff784320dc052b3c63013fd969f593 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 21 Jun 2022 13:43:48 +0800 Subject: [PATCH 0692/1868] drm/amdkcl: add kcl/kcl_iosys-map.h Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 5 +- drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 | 6 + drivers/gpu/drm/ttm/backport/backport.h | 1 + drivers/gpu/drm/ttm/ttm_bo_util.c | 2 +- include/kcl/header/linux/iosys-map.h | 9 + include/kcl/kcl_dma-buf-map.h | 2 + include/kcl/kcl_iosys-map.h | 179 +++++++++++++++++++ 8 files changed, 203 insertions(+), 2 deletions(-) create mode 100644 include/kcl/header/linux/iosys-map.h create mode 100644 include/kcl/kcl_iosys-map.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 3de3c768a6147..1846a72101907 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 545032a26c018..7f7bc35b2d0d0 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -826,7 +826,7 @@ /* #undef HAVE_LINUX_DMA_ATTRS_H */ /* Define to 1 if you have the header file. */ -#define HAVE_LINUX_DMA_BUF_MAP_H 1 +/* #undef HAVE_LINUX_DMA_BUF_MAP_H */ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_DMA_FENCE_CHAIN_H 1 @@ -840,6 +840,9 @@ /* Define to 1 if you have the header file. */ /* #undef HAVE_LINUX_FENCE_ARRAY_H */ +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_IOSYS_MAP_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_LINUX_IO_64_NONATOMIC_LO_HI_H 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 index 203f810772d52..b6024239ef2f5 100644 --- a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 @@ -73,6 +73,12 @@ AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ dnl # AC_KERNEL_CHECK_HEADERS([linux/dma-buf-map.h]) + dnl # + dnl # 7938f4218168 + dnl # dma-buf: dma-buf-map: Rename to iosys-map + dnl # + AC_KERNEL_CHECK_HEADERS([linux/iosys-map.h]) + dnl # dnl # v5.14-rc5-11-gc0891ac15f04 dnl # isystem: ship and use stdarg.h diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index 1e6024331b9f1..23eea49ccf6ae 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c index e5cd214a84bad..523d1ead90b48 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_util.c +++ b/drivers/gpu/drm/ttm/ttm_bo_util.c @@ -119,7 +119,7 @@ void ttm_move_memcpy(bool clear, if (!src_map.is_iomem && !dst_map.is_iomem) { memcpy(dst_map.vaddr, src_map.vaddr, PAGE_SIZE); } else if (!src_map.is_iomem) { - dma_buf_map_memcpy_to(&dst_map, src_map.vaddr, + iosys_map_memcpy_to(&dst_map, 0, src_map.vaddr, PAGE_SIZE); } else if (!dst_map.is_iomem) { memcpy_fromio(dst_map.vaddr, src_map.vaddr_iomem, diff --git a/include/kcl/header/linux/iosys-map.h b/include/kcl/header/linux/iosys-map.h new file mode 100644 index 0000000000000..a96b1547378c6 --- /dev/null +++ b/include/kcl/header/linux/iosys-map.h @@ -0,0 +1,9 @@ +#ifndef _KCL_HEADER___IOSYS_MAP_H___H_ +#define _KCL_HEADER___IOSYS_MAP_H___H_ + +#ifdef HAVE_LINUX_IOSYS_MAP_H +#include_next +#endif + +#endif + diff --git a/include/kcl/kcl_dma-buf-map.h b/include/kcl/kcl_dma-buf-map.h index 4ce925f647ec5..c3112da74c090 100644 --- a/include/kcl/kcl_dma-buf-map.h +++ b/include/kcl/kcl_dma-buf-map.h @@ -7,7 +7,9 @@ #ifndef _KCL_KCL__DMA_BUF_MAP_H__H__ #define _KCL_KCL__DMA_BUF_MAP_H__H__ +#ifndef HAVE_LINUX_IOSYS_MAP_H #include +#endif #ifndef HAVE_LINUX_DMA_BUF_MAP_H #include diff --git a/include/kcl/kcl_iosys-map.h b/include/kcl/kcl_iosys-map.h new file mode 100644 index 0000000000000..d35ce3a8f5c58 --- /dev/null +++ b/include/kcl/kcl_iosys-map.h @@ -0,0 +1,179 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Pointer abstraction for IO/system memory + * Copied from include/kcl/iosys-map.h + */ + +#ifndef _KCL_KCL__IOSYS_MAP_H__H__ +#define _KCL_KCL__IOSYS_MAP_H__H__ + +#include + +#ifndef HAVE_LINUX_IOSYS_MAP_H +#include +#include + +/** + * struct iosys_map - Pointer to IO/system memory + * @vaddr_iomem: The buffer's address if in I/O memory + * @vaddr: The buffer's address if in system memory + * @is_iomem: True if the buffer is located in I/O memory, or false + * otherwise. + */ +struct iosys_map { + union { + void __iomem *vaddr_iomem; + void *vaddr; + }; + bool is_iomem; +}; + +/** + * IOSYS_MAP_INIT_VADDR - Initializes struct iosys_map to an address in system memory + * @vaddr_: A system-memory address + */ +#define IOSYS_MAP_INIT_VADDR(vaddr_) \ + { \ + .vaddr = (vaddr_), \ + .is_iomem = false, \ + } + + +/** + * iosys_map_set_vaddr - Sets a iosys mapping structure to an address in system memory + * @map: The iosys_map structure + * @vaddr: A system-memory address + * + * Sets the address and clears the I/O-memory flag. + */ +static inline void iosys_map_set_vaddr(struct iosys_map *map, void *vaddr) +{ + map->vaddr = vaddr; + map->is_iomem = false; +} + +/** + * iosys_map_set_vaddr_iomem - Sets a iosys mapping structure to an address in I/O memory + * @map: The iosys_map structure + * @vaddr_iomem: An I/O-memory address + * + * Sets the address and the I/O-memory flag. + */ +static inline void iosys_map_set_vaddr_iomem(struct iosys_map *map, + void __iomem *vaddr_iomem) +{ + map->vaddr_iomem = vaddr_iomem; + map->is_iomem = true; +} + +/** + * iosys_map_is_equal - Compares two iosys mapping structures for equality + * @lhs: The iosys_map structure + * @rhs: A iosys_map structure to compare with + * + * Two iosys mapping structures are equal if they both refer to the same type of memory + * and to the same address within that memory. + * + * Returns: + * True is both structures are equal, or false otherwise. + */ +static inline bool iosys_map_is_equal(const struct iosys_map *lhs, + const struct iosys_map *rhs) +{ + if (lhs->is_iomem != rhs->is_iomem) + return false; + else if (lhs->is_iomem) + return lhs->vaddr_iomem == rhs->vaddr_iomem; + else + return lhs->vaddr == rhs->vaddr; +} + +/** + * iosys_map_is_null - Tests for a iosys mapping to be NULL + * @map: The iosys_map structure + * + * Depending on the state of struct iosys_map.is_iomem, tests if the + * mapping is NULL. + * + * Returns: + * True if the mapping is NULL, or false otherwise. + */ +static inline bool iosys_map_is_null(const struct iosys_map *map) +{ + if (map->is_iomem) + return !map->vaddr_iomem; + return !map->vaddr; +} + +/** + * iosys_map_is_set - Tests if the iosys mapping has been set + * @map: The iosys_map structure + * + * Depending on the state of struct iosys_map.is_iomem, tests if the + * mapping has been set. + * + * Returns: + * True if the mapping is been set, or false otherwise. + */ +static inline bool iosys_map_is_set(const struct iosys_map *map) +{ + return !iosys_map_is_null(map); +} + +/** + * iosys_map_clear - Clears a iosys mapping structure + * @map: The iosys_map structure + * + * Clears all fields to zero, including struct iosys_map.is_iomem, so + * mapping structures that were set to point to I/O memory are reset for + * system memory. Pointers are cleared to NULL. This is the default. + */ +static inline void iosys_map_clear(struct iosys_map *map) +{ + if (map->is_iomem) { + map->vaddr_iomem = NULL; + map->is_iomem = false; + } else { + map->vaddr = NULL; + } +} + +/** + * iosys_map_memcpy_to - Memcpy into offset of iosys_map + * @dst: The iosys_map structure + * @dst_offset: The offset from which to copy + * @src: The source buffer + * @len: The number of byte in src + * + * Copies data into a iosys_map with an offset. The source buffer is in + * system memory. Depending on the buffer's location, the helper picks the + * correct method of accessing the memory. + */ +static inline void iosys_map_memcpy_to(struct iosys_map *dst, size_t dst_offset, + const void *src, size_t len) +{ + if (dst->is_iomem) + memcpy_toio(dst->vaddr_iomem + dst_offset, src, len); + else + memcpy(dst->vaddr + dst_offset, src, len); +} + +/** + * iosys_map_incr - Increments the address stored in a iosys mapping + * @map: The iosys_map structure + * @incr: The number of bytes to increment + * + * Increments the address stored in a iosys mapping. Depending on the + * buffer's location, the correct value will be updated. + */ +static inline void iosys_map_incr(struct iosys_map *map, size_t incr) +{ + if (map->is_iomem) + map->vaddr_iomem += incr; + else + map->vaddr += incr; +} + +#endif /* HAVE_LINUX_IOSYS_MAP_H */ + +#endif From fd3964d3c396d0b1913657a84b70b9e1a1134209 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 21 Jun 2022 14:01:45 +0800 Subject: [PATCH 0693/1868] drm/amdkcl: test for drm/dp/drm_dp_helper.h Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/drm-dp-aux-drm-dev.m4 | 4 ++++ .../drm/amd/dkms/m4/drm-dp-cec-correlation-functions.m4 | 8 ++++++++ .../amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 | 4 ++++ .../dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 | 4 ++++ .../drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 | 4 ++++ drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 6 ++++++ include/kcl/backport/kcl_drm_dp_helper_backport.h | 1 - include/kcl/header/drm/dp/drm_dp_helper.h | 9 +++++++++ include/kcl/kcl_drm_dp_cec.h | 4 ++++ include/kcl/kcl_drm_dp_helper.h | 4 ++++ 11 files changed, 50 insertions(+), 1 deletion(-) create mode 100644 include/kcl/header/drm/dp/drm_dp_helper.h diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 7f7bc35b2d0d0..766f8c57ce815 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -336,6 +336,9 @@ /* drm_dp_cec_register_connector() wants p,p interface */ #define HAVE_DRM_DP_CEC_REGISTER_CONNECTOR_PP 1 +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DP_DRM_DP_HELPER_H 1 + /* drm_dp_link_train_channel_eq_delay() has 2 args */ #define HAVE_DRM_DP_LINK_TRAIN_CHANNEL_EQ_DELAY_2ARGS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-aux-drm-dev.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-aux-drm-dev.m4 index d851ad71eab97..49994828e0873 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-aux-drm-dev.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-aux-drm-dev.m4 @@ -5,7 +5,11 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_AUX_DRM_DEV], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ + #ifdef HAVE_DRM_DP_DRM_DP_HELPER_H + #include + #else #include + #endif ], [ struct drm_dp_aux dda; dda.drm_dev = NULL; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-cec-correlation-functions.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-cec-correlation-functions.m4 index 52f51298caf4d..141e3a6ff65d0 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-cec-correlation-functions.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-cec-correlation-functions.m4 @@ -5,7 +5,11 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_CEC_CORRELATION_FUNCTIONS], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DP_DRM_DP_HELPER_H + #include + #else #include + #endif ], [ drm_dp_cec_register_connector(NULL, NULL); ], [ @@ -15,7 +19,11 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_CEC_CORRELATION_FUNCTIONS], [ [drm_dp_cec* correlation functions are available]) ], [ AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DP_DRM_DP_HELPER_H + #include + #else #include + #endif ], [ drm_dp_cec_irq(NULL); drm_dp_cec_register_connector(NULL, NULL, NULL); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 index 664b63498814e..e6713844783e2 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 @@ -5,7 +5,11 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_LINK_TRAIN_CHANNEL_EQ_DELAY], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ + #ifdef HAVE_DRM_DP_DRM_DP_HELPER_H + #include + #else #include + #endif ], [ struct drm_dp_aux *aux = NULL; const u8 dpcd[DP_RECEIVER_CAP_SIZE]; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 index 4d8e0f733eb7e..af98096981e77 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 @@ -5,7 +5,11 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_LINK_TRAIN_CLOCK_RECOVERY_DELAY], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ + #ifdef HAVE_DRM_DP_DRM_DP_HELPER_H + #include + #else #include + #endif ], [ struct drm_dp_aux *aux = NULL; const u8 dpcd[DP_RECEIVER_CAP_SIZE]; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 index c15c7d3d88eb9..f49bd33a93a19 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 @@ -5,7 +5,11 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_SEND_REAL_EDID_CHECKSUM], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ + #ifdef HAVE_DRM_DP_DRM_DP_HELPER_H + #include + #else #include + #endif ], [ drm_dp_send_real_edid_checksum(NULL, 0); ], [drm_dp_send_real_edid_checksum], [drivers/gpu/drm/drm_dp_helper.c], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index b3b69a3e8dea7..da4ac4556d9b7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -50,6 +50,12 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # AC_KERNEL_CHECK_HEADERS([drm/drm_aperture.h]) + dnl # + dnl # v5.16-rc5-872-g5b529e8d9c38 + dnl # drm/dp: Move public DisplayPort headers into dp/ + dnl # + AC_KERNEL_CHECK_HEADERS([drm/dp/drm_dp_helper.h]) + dnl # dnl # v5.7-13141-gca5999fde0a1 dnl # mm: introduce include/linux/pgtable.h diff --git a/include/kcl/backport/kcl_drm_dp_helper_backport.h b/include/kcl/backport/kcl_drm_dp_helper_backport.h index 8a932361c9e0e..4c541b78127d7 100644 --- a/include/kcl/backport/kcl_drm_dp_helper_backport.h +++ b/include/kcl/backport/kcl_drm_dp_helper_backport.h @@ -3,7 +3,6 @@ #define _KCL_DRM_DP_HELPER_BACKPORT_H_ #include -#include /* * commit v4.19-rc1-100-g5ce70c799ac2 diff --git a/include/kcl/header/drm/dp/drm_dp_helper.h b/include/kcl/header/drm/dp/drm_dp_helper.h new file mode 100644 index 0000000000000..9aac78ed61294 --- /dev/null +++ b/include/kcl/header/drm/dp/drm_dp_helper.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DP_DRM_DP_HELPER_H_H_ +#define _KCL_HEADER_DP_DRM_DP_HELPER_H_H_ + +#ifdef HAVE_DRM_DP_DRM_DP_HELPER_H +#include_next +#endif + +#endif diff --git a/include/kcl/kcl_drm_dp_cec.h b/include/kcl/kcl_drm_dp_cec.h index 984b5d320f4fa..b810aae53f69a 100644 --- a/include/kcl/kcl_drm_dp_cec.h +++ b/include/kcl/kcl_drm_dp_cec.h @@ -8,7 +8,11 @@ #ifndef __KCL_KCL_DRM_DP_CEC_H__ #define __KCL_KCL_DRM_DP_CEC_H__ +#ifdef HAVE_DRM_DP_DRM_DP_HELPER_H +#include +#else #include +#endif /* * commit v4.19-rc1-100-g5ce70c799ac2 diff --git a/include/kcl/kcl_drm_dp_helper.h b/include/kcl/kcl_drm_dp_helper.h index e379e156b74d9..6168671062032 100644 --- a/include/kcl/kcl_drm_dp_helper.h +++ b/include/kcl/kcl_drm_dp_helper.h @@ -30,7 +30,11 @@ #include #include +#ifdef HAVE_DRM_DP_DRM_DP_HELPER_H +#include +#else #include +#endif #include /* From d55f9ccff9467a8832f9e73439ae4ed20e457b9f Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 21 Jun 2022 14:06:15 +0800 Subject: [PATCH 0694/1868] drm/amdkcl: test for drm/dp/drm_dp_mst_helper.h Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../drm/amd/dkms/m4/drm-dp-atomic-find-vcpi-slots.m4 | 8 ++++++++ drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 | 6 +++++- .../amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 | 4 ++++ .../gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 | 4 ++++ .../drm/amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 | 4 ++++ .../gpu/drm/amd/dkms/m4/drm-dp-mst-detect-port.m4 | 4 ++++ .../drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 | 4 ++++ .../gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 | 12 ++++++++++++ .../amd/dkms/m4/drm-dp-mst-topology-mgr-resume.m4 | 4 ++++ .../gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 | 4 ++++ drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 | 12 ++++++++++++ drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 6 ++++++ .../m4/drm-up-update-payload-part1-start-slot-arg.m4 | 4 ++++ .../drm/amd/dkms/m4/drm_dp_mst_topology_mgr_init.m4 | 4 ++++ .../kcl/backport/kcl_drm_dp_mst_helper_backport.h | 4 ++++ include/kcl/header/drm/dp/drm_dp_mst_helper.h | 9 +++++++++ 17 files changed, 95 insertions(+), 1 deletion(-) create mode 100644 include/kcl/header/drm/dp/drm_dp_mst_helper.h diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 766f8c57ce815..d515cbafacc5c 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -339,6 +339,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_DRM_DP_DRM_DP_HELPER_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DP_DRM_DP_MST_HELPER_H 1 + /* drm_dp_link_train_channel_eq_delay() has 2 args */ #define HAVE_DRM_DP_LINK_TRAIN_CHANNEL_EQ_DELAY_2ARGS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-find-vcpi-slots.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-find-vcpi-slots.m4 index 448c9066f274a..65b49ae69f164 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-find-vcpi-slots.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-find-vcpi-slots.m4 @@ -5,7 +5,11 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ + #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #include + #else #include + #endif ], [ int retval; retval = drm_dp_atomic_find_vcpi_slots(NULL, NULL, NULL, 0); @@ -18,7 +22,11 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS], [ dnl # drm/dp_mst: Manually overwrite PBN divider for calculating timeslots dnl # AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #include + #else #include + #endif ], [ int retval; retval = drm_dp_atomic_find_vcpi_slots(NULL, NULL, NULL, 0, 0); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 index d168a591bcd23..8dc9ef9c8dd48 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 @@ -5,7 +5,11 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_CALC_PBN_MODE], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #include + #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #include + #else + #include + #endif ], [ drm_dp_calc_pbn_mode(0, 0, 0); ], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 index 1d4564270d065..1f637c137dad1 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 @@ -5,7 +5,11 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_ADD_AFFECTED_DSC_CRTCS], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ + #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #include + #else #include + #endif ], [ int ret; ret = drm_dp_mst_add_affected_dsc_crtcs(NULL, NULL); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 index dc4167e33a865..df6b3450485e0 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 @@ -5,7 +5,11 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_ATOMIC_CHECK], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ + #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #include + #else #include + #endif ], [ int ret; ret = drm_dp_mst_atomic_check(NULL); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 index 17422c2217f46..65d24257c4d25 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 @@ -5,7 +5,11 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_ATOMIC_ENABLE_DSC], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ + #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #include + #else #include + #endif ], [ drm_dp_mst_atomic_enable_dsc(NULL, NULL, 0, 0, false); ], [drm_dp_mst_atomic_enable_dsc], [drivers/gpu/drm/drm_dp_mst_topology.c], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-detect-port.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-detect-port.m4 index 4198140ed6a0e..913f4586acf6c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-detect-port.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-detect-port.m4 @@ -5,7 +5,11 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_DETECT_PORT], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #include + #else #include + #endif ], [ int ret; ret = drm_dp_mst_detect_port(NULL, NULL, NULL, NULL); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 index 06d77b61ab828..4c48b47b4c9bf 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 @@ -5,7 +5,11 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_DSC_AUX_FOR_PORT], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ + #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #include + #else #include + #endif ], [ drm_dp_mst_dsc_aux_for_port(NULL); ], [drm_dp_mst_dsc_aux_for_port], [drivers/gpu/drm/drm_dp_mst_topology.c], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 index f08316600fcbd..5540428fc8b49 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 @@ -4,7 +4,11 @@ dnl # drm/dp-mst-helper: Remove hotplug callback dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_HOTPLUG], [ AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #include + #else #include + #endif ], [ struct drm_dp_mst_topology_cbs *dp_mst_cbs = NULL; dp_mst_cbs->hotplug(NULL); @@ -24,7 +28,11 @@ dnl # drm/dp/mst: split connector registration into two parts (v2) dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_REGISTER_CONNECTOR], [ AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #include + #else #include + #endif ], [ struct drm_dp_mst_topology_cbs *dp_mst_cbs = NULL; dp_mst_cbs->register_connector(NULL); @@ -40,7 +48,11 @@ dnl # drm/dp_mst: Remove drm_dp_mst_topology_cbs.destroy_connector dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_DESTROY_CONNECTOR], [ AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #include + #else #include + #endif ], [ struct drm_dp_mst_topology_cbs *dp_mst_cbs = NULL; dp_mst_cbs->destroy_connector(NULL, NULL); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-mgr-resume.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-mgr-resume.m4 index 3c491e182062e..039132d5081d7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-mgr-resume.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-mgr-resume.m4 @@ -5,7 +5,11 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_RESUME], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #include + #else #include + #endif ], [ int ret; ret = drm_dp_mst_topology_mgr_resume(NULL, 0); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 index bd46fb9e30abb..720e605f38d4f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 @@ -5,7 +5,11 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #include + #else #include + #endif ], [ struct drm_dp_mst_topology_state * mst_state = NULL; mst_state->total_avail_slots = 0; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 index 5c6393f547854..5065a8ab6d0d6 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 @@ -8,7 +8,11 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #include + #else #include + #endif ], [ drm_dp_mst_allocate_vcpi(NULL, NULL, 1, 1); ], [ @@ -25,7 +29,11 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY], [ dnl # AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #include + #else #include + #endif ], [ drm_dp_mst_get_port_malloc(NULL); drm_dp_mst_put_port_malloc(NULL); @@ -40,7 +48,11 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY], [ dnl # AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #include + #else #include + #endif ], [ drm_dp_mst_connector_early_unregister(NULL, NULL); drm_dp_mst_connector_late_register(NULL, NULL); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index da4ac4556d9b7..db107edff41aa 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -56,6 +56,12 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # AC_KERNEL_CHECK_HEADERS([drm/dp/drm_dp_helper.h]) + dnl # + dnl # v5.16-rc5-872-g5b529e8d9c38 + dnl # drm/dp: Move public DisplayPort headers into dp/ + dnl # + AC_KERNEL_CHECK_HEADERS([drm/dp/drm_dp_mst_helper.h]) + dnl # dnl # v5.7-13141-gca5999fde0a1 dnl # mm: introduce include/linux/pgtable.h diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-up-update-payload-part1-start-slot-arg.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-up-update-payload-part1-start-slot-arg.m4 index 1b341003bb985..0c25016be1da4 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-up-update-payload-part1-start-slot-arg.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-up-update-payload-part1-start-slot-arg.m4 @@ -5,7 +5,11 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_UPDATE_PAYLOAD_PART1_START_SLOT_ARG], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #include + #else #include + #endif ], [ drm_dp_update_payload_part1(NULL, 0); ], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr_init.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr_init.m4 index 98d2982594b7c..ca29f48cb467a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr_init.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr_init.m4 @@ -5,7 +5,11 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_INIT], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #include + #else #include + #endif ], [ drm_dp_mst_topology_mgr_init(NULL, (struct drm_device *)NULL, NULL, 0, 0, 0, 0, 0); ], [ diff --git a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h index 183e49a5ba766..2412859be272a 100644 --- a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h +++ b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h @@ -22,7 +22,11 @@ #ifndef _KCL_DRM_DP_MST_HELPER_BACKPORT_H_ #define _KCL_DRM_DP_MST_HELPER_BACKPORT_H_ +#ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H +#include +#else #include +#endif /* Copied from drivers/gpu/drm/drm_dp_mst_topology.c and modified for KCL */ #if !defined(HAVE_DRM_DP_CALC_PBN_MODE_3ARGS) diff --git a/include/kcl/header/drm/dp/drm_dp_mst_helper.h b/include/kcl/header/drm/dp/drm_dp_mst_helper.h new file mode 100644 index 0000000000000..116be51b87c2c --- /dev/null +++ b/include/kcl/header/drm/dp/drm_dp_mst_helper.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DP_DRM_DP_MST_HELPER_H_H_ +#define _KCL_HEADER_DP_DRM_DP_MST_HELPER_H_H_ + +#ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H +#include_next +#endif + +#endif From 42de6afc0ec25c6a4222d6515c8cae4244b0870f Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 21 Jun 2022 16:28:32 +0800 Subject: [PATCH 0695/1868] drm/amdkcl: Test whether dma_fence_is_container() is available Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 3 ++ .../drm/amd/dkms/m4/dma-fence-is-container.m4 | 15 ++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_dma-resv.h | 1 + include/kcl/kcl_dma_fence.h | 46 +++++++++++++++++++ include/kcl/kcl_dma_fence_chain.h | 3 ++ include/kcl/kcl_fence_array.h | 11 +++++ 7 files changed, 80 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/dma-fence-is-container.m4 create mode 100644 include/kcl/kcl_dma_fence.h diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index d515cbafacc5c..2909f87ad0340 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -100,6 +100,9 @@ /* whether dma_fence_get_stub exits */ #define HAVE_DMA_FENCE_GET_STUB 1 +/* dma_fence_is_container() is available */ +#define HAVE_DMA_FENCE_IS_CONTAINER 1 + /* struct dma_fence_ops has use_64bit_seqno field */ #define HAVE_DMA_FENCE_OPS_USE_64BIT_SEQNO 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-fence-is-container.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-fence-is-container.m4 new file mode 100644 index 0000000000000..7c07948aa5205 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dma-fence-is-container.m4 @@ -0,0 +1,15 @@ +dnl # +dnl # commit v5.17-rc2-229-g976b6d97c623 +dnl # dma-buf: consolidate dma_fence subclass checking +dnl # +AC_DEFUN([AC_AMDGPU_DMA_FENCE_IS_CONTAINER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + dma_fence_is_container(NULL); + ], [ + AC_DEFINE(HAVE_DMA_FENCE_IS_CONTAINER, 1, [dma_fence_is_container() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 65b1171ee3727..9b2322cdebdaf 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -204,6 +204,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_HYPERVISOR_IS_TYPE AC_AMDGPU_PCI_DEV_LTR_PATH AC_AMDGPU_CANCEL_WORK + AC_AMDGPU_DMA_FENCE_IS_CONTAINER AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_dma-resv.h b/include/kcl/kcl_dma-resv.h index 0d0ccbbb5d043..0c4850cd6bf95 100644 --- a/include/kcl/kcl_dma-resv.h +++ b/include/kcl/kcl_dma-resv.h @@ -50,6 +50,7 @@ #include #include #include +#include struct dma_resv_list; diff --git a/include/kcl/kcl_dma_fence.h b/include/kcl/kcl_dma_fence.h new file mode 100644 index 0000000000000..cbf594a40d4de --- /dev/null +++ b/include/kcl/kcl_dma_fence.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Fence mechanism for dma-buf to allow for asynchronous dma access + * + * Copyright (C) 2012 Canonical Ltd + * Copyright (C) 2012 Texas Instruments + * + * Authors: + * Rob Clark + * Maarten Lankhorst + */ + +#ifndef AMDKCL_DMA_FENCE_H +#define AMDKCL_DMA_FENCE_H + +#ifndef HAVE_DMA_FENCE_IS_CONTAINER +#include +#include + +/** + * dma_fence_is_chain - check if a fence is from the chain subclass + * @fence: the fence to test + * + * Return true if it is a dma_fence_chain and false otherwise. + */ +static inline bool dma_fence_is_chain(struct dma_fence *fence) +{ + return fence->ops == &dma_fence_chain_ops; +} + +/** + * dma_fence_is_container - check if a fence is a container for other fences + * @fence: the fence to test + * + * Return true if this fence is a container for other fences, false otherwise. + * This is important since we can't build up large fence structure or otherwise + * we run into recursion during operation on those fences. + */ +static inline bool dma_fence_is_container(struct dma_fence *fence) +{ + return dma_fence_is_array(fence) || dma_fence_is_chain(fence); +} + +#endif /* HAVE_DMA_FENCE_IS_CONTAINER */ + +#endif diff --git a/include/kcl/kcl_dma_fence_chain.h b/include/kcl/kcl_dma_fence_chain.h index 4cde69227a3f1..eafcd818c1da3 100644 --- a/include/kcl/kcl_dma_fence_chain.h +++ b/include/kcl/kcl_dma_fence_chain.h @@ -9,6 +9,9 @@ #ifndef AMDKCL_DMA_FENCE_CHAIN_H #define AMDKCL_DMA_FENCE_CHAIN_H +#ifdef HAVE_LINUX_DMA_FENCE_CHAIN_H +#include +#endif #if !defined(HAVE_STRUCT_DMA_FENCE_CHAIN) #ifdef HAVE_LINUX_DMA_FENCE_H diff --git a/include/kcl/kcl_fence_array.h b/include/kcl/kcl_fence_array.h index 1e8f37c5864d3..060edd1567fda 100644 --- a/include/kcl/kcl_fence_array.h +++ b/include/kcl/kcl_fence_array.h @@ -76,6 +76,17 @@ static inline struct fence_array *to_fence_array(struct fence *fence) struct fence_array *fence_array_create(int num_fences, struct fence **fences, u64 context, unsigned seqno, bool signal_on_any); +/** + * dma_fence_is_array - check if a fence is from the array subclass + * @fence: the fence to test + * + * Return true if it is a dma_fence_array and false otherwise. + */ +static inline bool dma_fence_is_array(struct dma_fence *fence) +{ + return false; +} + #endif #endif From e1ebd76ec1ca74bf4f9cf86b8540b52a1cd6d949 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 21 Jun 2022 16:57:30 +0800 Subject: [PATCH 0696/1868] drm/amdkcl: Test whether str_yes_no() is available Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/backport/backport.h | 2 ++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/str_yes_no.m4 | 16 ++++++++++++ include/kcl/kcl_string_helpers.h | 30 +++++++++++++++++++++++ 5 files changed, 52 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/str_yes_no.m4 create mode 100644 include/kcl/kcl_string_helpers.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 1846a72101907..42072db6869d3 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -94,4 +94,6 @@ #include #include #include +#include + #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 2909f87ad0340..d48ab5b611781 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1126,6 +1126,9 @@ /* zone->managed_pages is available */ /* #undef HAVE_STRUCT_ZONE_MANAGED_PAGES */ +/* str_yes_no() is defined */ +#define HAVE_STR_YES_NO 1 + /* synchronize_shrinkers() is available */ #define HAVE_SYNCHRONIZE_SHRINKERS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 9b2322cdebdaf..fba2c3c34cca6 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -205,6 +205,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_PCI_DEV_LTR_PATH AC_AMDGPU_CANCEL_WORK AC_AMDGPU_DMA_FENCE_IS_CONTAINER + AC_AMDGPU_STR_YES_NO AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/str_yes_no.m4 b/drivers/gpu/drm/amd/dkms/m4/str_yes_no.m4 new file mode 100644 index 0000000000000..9ca6f08ae00e7 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/str_yes_no.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit ea4692c75e1c63926e4fb0728f5775ef0d733888 +dnl # lib/string_helpers: Consolidate string helpers implementation +dnl # +AC_DEFUN([AC_AMDGPU_STR_YES_NO], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + const char *str = str_yes_no(true); + ], [ + AC_DEFINE(HAVE_STR_YES_NO, 1, + [str_yes_no() is defined]) + ]) + ]) +]) diff --git a/include/kcl/kcl_string_helpers.h b/include/kcl/kcl_string_helpers.h new file mode 100644 index 0000000000000..ceac153f44bfd --- /dev/null +++ b/include/kcl/kcl_string_helpers.h @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_STRING_HELPERS_H +#define AMDKCL_STRING_HELPERS_H + + +/* Copied from v5.17-rc2-224-gea4692c75e1c linux/string_helpers.h */ + +#ifndef HAVE_STR_YES_NO +static inline const char *str_yes_no(bool v) +{ + return v ? "yes" : "no"; +} + +static inline const char *str_on_off(bool v) +{ + return v ? "on" : "off"; +} + +static inline const char *str_enable_disable(bool v) +{ + return v ? "enable" : "disable"; +} + +static inline const char *str_enabled_disabled(bool v) +{ + return v ? "enabled" : "disabled"; +} + +#endif /* HAVE_STR_YES_NO */ +#endif From a5ae788d636a4baf39a95e59056098565142984a Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 21 Mar 2024 11:27:12 +0800 Subject: [PATCH 0697/1868] drm/amdkcl: Test whether struct drm_mode_config has member fb_modifiers_not_supported Signed-off-by: Leslie Shi Signed-off-by: Ma Jun Change-Id: I37f2cbc1e506f97d09a4850d0b92dabcf4121a88 Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 12 ++++++++++++ drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 2 ++ drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 2 ++ drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 2 ++ drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 2 ++ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 - .../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 2 ++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/drm_mode_config.m4 | 18 ++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 10 files changed, 44 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_mode_config.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 2039435651022..f83bde74d6911 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1291,7 +1291,11 @@ static int amdgpu_display_verify_sizes(struct amdgpu_framebuffer *rfb) int ret; unsigned int i, block_width, block_height, block_size_log2; +#ifdef HAVE_DRM_MODE_CONFIG_FB_MODIFIERS_NOT_SUPPORTED if (rfb->base.dev->mode_config.fb_modifiers_not_supported) +#else + if (!rfb->base.dev->mode_config.allow_fb_modifiers) +#endif return 0; for (i = 0; i < format_info->num_planes; ++i) { @@ -1519,7 +1523,11 @@ static int amdgpu_display_framebuffer_init(struct drm_device *dev, return ret; #ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED +#ifdef HAVE_DRM_MODE_CONFIG_FB_MODIFIERS_NOT_SUPPORTED if (dev->mode_config.fb_modifiers_not_supported && !adev->enable_virtual_display) { +#else + if (!dev->mode_config.allow_fb_modifiers && !adev->enable_virtual_display) { +#endif drm_WARN_ONCE(dev, adev->family >= AMDGPU_FAMILY_AI, "GFX9+ requires FB check based on format modifier\n"); ret = check_tiling_flags_gfx6(rfb); @@ -1527,7 +1535,11 @@ static int amdgpu_display_framebuffer_init(struct drm_device *dev, return ret; } +#ifdef HAVE_DRM_MODE_CONFIG_FB_MODIFIERS_NOT_SUPPORTED if (!dev->mode_config.fb_modifiers_not_supported && +#else + if (dev->mode_config.allow_fb_modifiers && +#endif !(rfb->base.flags & DRM_MODE_FB_MODIFIERS)) { if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(12, 0, 0)) ret = convert_tiling_flags_to_modifier_gfx12(rfb); diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index 88956fa3f2b8b..5d3e9b2470a3a 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -2887,7 +2887,9 @@ static int dce_v10_0_sw_init(void *handle) adev_to_drm(adev)->mode_config.preferred_depth = 24; adev_to_drm(adev)->mode_config.prefer_shadow = 1; +#ifdef HAVE_DRM_MODE_CONFIG_FB_MODIFIERS_NOT_SUPPORTED adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true; +#endif r = amdgpu_display_modeset_create_props(adev); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index c27a40f596c6e..27e62bca0a245 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -3013,7 +3013,9 @@ static int dce_v11_0_sw_init(void *handle) adev_to_drm(adev)->mode_config.preferred_depth = 24; adev_to_drm(adev)->mode_config.prefer_shadow = 1; +#ifdef HAVE_DRM_MODE_CONFIG_FB_MODIFIERS_NOT_SUPPORTED adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true; +#endif r = amdgpu_display_modeset_create_props(adev); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c index 2c9be10e4f4c1..c64935de10841 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c @@ -2793,7 +2793,9 @@ static int dce_v6_0_sw_init(void *handle) adev_to_drm(adev)->mode_config.max_height = 16384; adev_to_drm(adev)->mode_config.preferred_depth = 24; adev_to_drm(adev)->mode_config.prefer_shadow = 1; +#ifdef HAVE_DRM_MODE_CONFIG_FB_MODIFIERS_NOT_SUPPORTED adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true; +#endif r = amdgpu_display_modeset_create_props(adev); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index 8ac78fc5e5dcb..70f859818b76a 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -2805,7 +2805,9 @@ static int dce_v8_0_sw_init(void *handle) else adev_to_drm(adev)->mode_config.prefer_shadow = 1; +#ifdef HAVE_DRM_MODE_CONFIG_FB_MODIFIERS_NOT_SUPPORTED adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true; +#endif r = amdgpu_display_modeset_create_props(adev); if (r) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index ac0663b92a877..a7a3cea54f71c 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -7748,7 +7748,6 @@ int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth) return 0; } #endif - static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, struct drm_crtc_state *crtc_state, struct drm_connector_state *conn_state) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index c6f2c892ba34d..fc125b94bceab 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -1909,8 +1909,10 @@ int amdgpu_dm_plane_init(struct amdgpu_display_manager *dm, return res; #endif +#ifdef HAVE_DRM_MODE_CONFIG_FB_MODIFIERS_NOT_SUPPORTED if (modifiers == NULL) adev_to_drm(dm->adev)->mode_config.fb_modifiers_not_supported = true; +#endif res = drm_universal_plane_init(adev_to_drm(dm->adev), plane, possible_crtcs, &dm_plane_funcs, formats, num_formats, diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index d48ab5b611781..b16a47d3e74e1 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -602,6 +602,9 @@ /* drm_mode_config->dp_subconnector_property is available */ #define HAVE_DRM_MODE_CONFIG_DP_SUBCONNECTOR_PROPERTY 1 +/* drm_mode_config->fb_modifiers_not_supported is available */ +#define HAVE_DRM_MODE_CONFIG_FB_MODIFIERS_NOT_SUPPORTED 1 + /* drm_mode_config_funcs->atomic_state_alloc() is available */ #define HAVE_DRM_MODE_CONFIG_FUNCS_ATOMIC_STATE_ALLOC 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_mode_config.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_mode_config.m4 new file mode 100644 index 0000000000000..add5633e0f26f --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_mode_config.m4 @@ -0,0 +1,18 @@ +AC_DEFUN([AC_AMDGPU_DRM_MODE_CONFIG_FB_MODIFIERS_NOT_SUPPORTED], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_mode_config *mode_config = NULL; + mode_config->fb_modifiers_not_supported = true; + ], [ + AC_DEFINE(HAVE_DRM_MODE_CONFIG_FB_MODIFIERS_NOT_SUPPORTED, 1, + [drm_mode_config->fb_modifiers_not_supported is available]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_DRM_MODE_CONFIG], [ + AC_AMDGPU_DRM_MODE_CONFIG_FB_MODIFIERS_NOT_SUPPORTED +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index fba2c3c34cca6..539b8ae08ff48 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -124,6 +124,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_ADD_AFFECTED_DSC_CRTCS AC_AMDGPU_DRM_CONNECTOR_HAVE_HDR_SINK_METADATA AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_INIT + AC_AMDGPU_DRM_MODE_CONFIG AC_AMDGPU_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION AC_AMDGPU_JIFFIES64_TO_MSECS From c831745172768df3549758bf2f2b98903b5b370b Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 22 Jun 2022 13:12:12 +0800 Subject: [PATCH 0698/1868] drm/amdkcl: Test whether dma_fence_chain_contained is available Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/dma-fence-chain.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_dma_fence_chain.h | 17 +++++++++++++++++ 4 files changed, 38 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index b16a47d3e74e1..6c4aedb8cfc8b 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1047,6 +1047,9 @@ /* struct dma_fence_chain is available */ #define HAVE_STRUCT_DMA_FENCE_CHAIN 1 +/* dma_fence_chain_contained() is available */ +#define HAVE_DMA_FENCE_CHAIN_CONTAINED 1 + /* struct drm_connector_state->duplicated is available */ #define HAVE_STRUCT_DRM_ATOMIC_STATE_DUPLICATED 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-fence-chain.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-fence-chain.m4 index 34231d5d2028d..7867a6283d95f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/dma-fence-chain.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/dma-fence-chain.m4 @@ -32,3 +32,20 @@ AC_DEFUN([AC_AMDGPU_DMA_FENCE_CHAIN_STRUCT], [ ]) ]) +dnl # +dnl # v5.17-rc2-233-g18f5fad275ef +dnl # dma-buf: add dma_fence_chain_contained helper +dnl # +AC_DEFUN([AC_AMDGPU_DMA_FENCE_CHAIN_CONTAINED], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + dma_fence_chain_contained(NULL); + ], [ + AC_DEFINE(HAVE_DMA_FENCE_CHAIN_CONTAINED, 1, + [dma_fence_chain_contained() is available]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 539b8ae08ff48..e7c40b7506fb4 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -207,6 +207,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_CANCEL_WORK AC_AMDGPU_DMA_FENCE_IS_CONTAINER AC_AMDGPU_STR_YES_NO + AC_AMDGPU_DMA_FENCE_CHAIN_CONTAINED AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_dma_fence_chain.h b/include/kcl/kcl_dma_fence_chain.h index eafcd818c1da3..b7b66a3b93c90 100644 --- a/include/kcl/kcl_dma_fence_chain.h +++ b/include/kcl/kcl_dma_fence_chain.h @@ -123,4 +123,21 @@ static inline void dma_fence_chain_free(struct dma_fence_chain *chain) #endif +#ifndef HAVE_DMA_FENCE_CHAIN_CONTAINED +/** + * dma_fence_chain_contained - return the contained fence + * @fence: the fence to test + * + * If the fence is a dma_fence_chain the function returns the fence contained + * inside the chain object, otherwise it returns the fence itself. + */ +static inline struct dma_fence * +dma_fence_chain_contained(struct dma_fence *fence) +{ + struct dma_fence_chain *chain = to_dma_fence_chain(fence); + + return chain ? chain->fence : fence; +} +#endif /* HAVE_DMA_FENCE_CHAIN_CONTAINED */ + #endif From e84a9d951bffffe597ed58b28d76cf75408602fd Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 23 Jun 2022 14:59:24 +0800 Subject: [PATCH 0699/1868] drm/amdkcl: add DRM_COLOR_FORMAT_YCRCB enums This is caused by c03d0b52ff71 "drm/connector: Fix typo in output format" v5.16-rc5-909-gc03d0b52ff71 Signed-off-by: Leslie Shi --- include/kcl/kcl_drm_connector.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/include/kcl/kcl_drm_connector.h b/include/kcl/kcl_drm_connector.h index d77022ef022ac..96e58541b57a4 100644 --- a/include/kcl/kcl_drm_connector.h +++ b/include/kcl/kcl_drm_connector.h @@ -121,4 +121,16 @@ int drm_connector_set_panel_orientation_with_quirk( } #endif +#ifndef DRM_COLOR_FORMAT_YCBCR444 +#define DRM_COLOR_FORMAT_YCBCR444 (1<<1) +#endif + +#ifndef DRM_COLOR_FORMAT_YCBCR422 +#define DRM_COLOR_FORMAT_YCBCR422 (1<<2) +#endif + +#ifndef DRM_COLOR_FORMAT_YCBCR420 +#define DRM_COLOR_FORMAT_YCBCR420 (1<<3) +#endif + #endif /* AMDKCL_DRM_CONNECTOR_H */ From efa861432c3fc88b62bfabdeaec8c1fa795426be Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 21 Mar 2024 12:24:06 +0800 Subject: [PATCH 0700/1868] drm/amdkcl: wrap code under macro CONFIG_DRM_AMD_DC_DSC_SUPPORT Signed-off-by: Leslie Shi Signed-off-by: Ma Jun Change-Id: I319776ac36ade90de99d03e520d6426efd7c31c4 Signed-off-by: Asher Song --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 +++- .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 11 +++++- .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 4 ++ .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 6 ++- drivers/gpu/drm/amd/display/dc/core/dc.c | 13 +++++++ .../gpu/drm/amd/display/dc/core/dc_resource.c | 6 +++ .../gpu/drm/amd/display/dc/core/dc_stream.c | 4 ++ drivers/gpu/drm/amd/display/dc/dc.h | 8 ++++ drivers/gpu/drm/amd/display/dc/dc_stream.h | 2 + drivers/gpu/drm/amd/display/dc/dc_types.h | 2 + drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 5 ++- .../display/dc/dcn201/dcn201_link_encoder.c | 2 + .../amd/display/dc/dcn21/dcn21_link_encoder.c | 2 + .../display/dc/dio/dcn20/dcn20_link_encoder.c | 8 +++- .../display/dc/dio/dcn20/dcn20_link_encoder.h | 2 + .../dc/dio/dcn20/dcn20_stream_encoder.c | 7 +++- .../dc/dio/dcn30/dcn30_dio_link_encoder.c | 2 + .../dc/dio/dcn30/dcn30_dio_stream_encoder.c | 4 ++ .../dc/dio/dcn31/dcn31_dio_link_encoder.c | 4 ++ .../dc/dio/dcn314/dcn314_dio_stream_encoder.c | 4 ++ .../dc/dio/dcn32/dcn32_dio_link_encoder.c | 2 + .../dc/dio/dcn32/dcn32_dio_stream_encoder.c | 3 ++ .../dc/dio/dcn321/dcn321_dio_link_encoder.c | 2 + drivers/gpu/drm/amd/display/dc/dm_helpers.h | 1 + .../amd/display/dc/dml/display_mode_enums.h | 2 + .../drm/amd/display/dc/dml/dsc/rc_calc_fpu.c | 3 +- .../drm/amd/display/dc/dml/dsc/rc_calc_fpu.h | 2 + drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 2 + .../drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c | 2 + .../drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h | 3 +- drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c | 2 + .../gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c | 3 +- .../hpo/dcn31/dcn31_hpo_dp_stream_encoder.c | 2 + .../amd/display/dc/hwss/dcn10/dcn10_hwseq.c | 4 ++ .../amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 8 ++++ .../amd/display/dc/hwss/dcn20/dcn20_hwseq.h | 2 + .../amd/display/dc/hwss/dcn20/dcn20_init.c | 4 ++ .../amd/display/dc/hwss/dcn21/dcn21_init.c | 2 + .../amd/display/dc/hwss/dcn30/dcn30_init.c | 2 + .../amd/display/dc/hwss/dcn31/dcn31_hwseq.c | 2 + .../amd/display/dc/hwss/dcn314/dcn314_hwseq.c | 4 ++ .../amd/display/dc/hwss/dcn314/dcn314_init.c | 2 + .../amd/display/dc/hwss/dcn32/dcn32_hwseq.c | 3 +- .../gpu/drm/amd/display/dc/inc/core_types.h | 5 ++- .../drm/amd/display/dc/inc/hw/link_encoder.h | 4 ++ .../amd/display/dc/inc/hw/timing_generator.h | 2 + .../dc/link/protocols/link_dp_training_dpia.c | 4 ++ .../amd/display/dc/optc/dcn20/dcn20_optc.c | 9 +++++ .../amd/display/dc/optc/dcn20/dcn20_optc.h | 2 + .../amd/display/dc/optc/dcn201/dcn201_optc.c | 2 + .../amd/display/dc/optc/dcn30/dcn30_optc.c | 4 ++ .../amd/display/dc/optc/dcn30/dcn30_optc.h | 2 + .../amd/display/dc/optc/dcn314/dcn314_optc.c | 2 + .../amd/display/dc/optc/dcn32/dcn32_optc.c | 2 + .../dc/resource/dcn20/dcn20_resource.c | 38 ++++++++++++++++--- .../dc/resource/dcn20/dcn20_resource.h | 2 + .../dc/resource/dcn201/dcn201_resource.c | 2 + .../dc/resource/dcn21/dcn21_resource.c | 15 +++++++- .../dc/resource/dcn30/dcn30_resource.c | 22 +++++++++++ .../dc/resource/dcn301/dcn301_resource.c | 2 + .../dc/resource/dcn314/dcn314_resource.c | 10 +++++ .../dc/resource/dcn315/dcn315_resource.c | 14 +++++++ .../dc/resource/dcn316/dcn316_resource.c | 15 ++++++++ .../dc/resource/dcn32/dcn32_resource.c | 10 +++++ .../resource/dcn32/dcn32_resource_helpers.c | 2 + .../dc/virtual/virtual_stream_encoder.c | 8 ++++ 66 files changed, 324 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index a7a3cea54f71c..57aa01741f79b 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -6881,7 +6881,6 @@ create_stream_for_sink(struct drm_connector *connector, if (aconnector->dsc_settings.dsc_force_enable != DSC_CLK_FORCE_DISABLE && dsc_caps.is_dsc_supported) apply_dsc_policy_for_stream(aconnector, sink, stream, &dsc_caps); #endif - update_stream_scaling_settings(&mode, dm_state, stream); fill_audio_info( @@ -7477,8 +7476,10 @@ create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector, return stream; dc_result = dc_validate_stream(adev->dm.dc, stream); +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (dc_result == DC_OK && stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) dc_result = dm_dp_mst_is_port_support_mode(aconnector, stream); +#endif if (dc_result == DC_OK) dc_result = dm_validate_stream_and_context(adev->dm.dc, stream); @@ -11561,10 +11562,11 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, bool lock_and_validation_needed = false; bool is_top_most_overlay = true; struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT struct drm_dp_mst_topology_mgr *mgr; struct drm_dp_mst_topology_state *mst_state; struct dsc_mst_fairness_vars vars[MAX_PIPES] = {0}; - +#endif trace_amdgpu_dm_atomic_check_begin(state); ret = drm_atomic_helper_check_modeset(dev, state); @@ -11890,6 +11892,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, lock_and_validation_needed = true; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS /* set the slot info for each mst_state based on the link encoding format */ for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) { @@ -11910,6 +11913,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, } drm_connector_list_iter_end(&iter); } +#endif #endif /** * Streams and planes are reset when there are changes that affect diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index 49d7e84a8c339..6a95d38c2ffff 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -1335,6 +1335,7 @@ static ssize_t dp_sdp_message_debugfs_write(struct file *f, const char __user *b * cat /sys/kernel/debug/dri/0/DP-X/dp_dsc_fec_support * */ +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static int dp_dsc_fec_support_show(struct seq_file *m, void *data) { struct drm_connector *connector = m->private; @@ -1390,6 +1391,7 @@ static int dp_dsc_fec_support_show(struct seq_file *m, void *data) return ret; } +#endif /* function: Trigger virtual HPD redetection on connector * @@ -1535,6 +1537,7 @@ static ssize_t trigger_hotplug(struct file *f, const char __user *buf, * 1 - means that DSC is currently enabled * 0 - means that DSC is disabled */ +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static ssize_t dp_dsc_clock_en_read(struct file *f, char __user *buf, size_t size, loff_t *pos) { @@ -2537,7 +2540,7 @@ static ssize_t dp_dsc_slice_bpg_offset_read(struct file *f, char __user *buf, kfree(rd_buf); return result; } - +#endif /* * function description: Read max_requested_bpc property from the connector @@ -2867,7 +2870,9 @@ static int is_dpia_link_show(struct seq_file *m, void *data) return 0; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT DEFINE_SHOW_ATTRIBUTE(dp_dsc_fec_support); +#endif DEFINE_SHOW_ATTRIBUTE(dmub_fw_state); DEFINE_SHOW_ATTRIBUTE(dmub_tracebuffer); #ifdef DEFINE_DEBUGFS_ATTRIBUTE @@ -2882,6 +2887,7 @@ DEFINE_SHOW_ATTRIBUTE(dp_is_mst_connector); DEFINE_SHOW_ATTRIBUTE(dp_mst_progress_status); DEFINE_SHOW_ATTRIBUTE(is_dpia_link); +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static const struct file_operations dp_dsc_clock_en_debugfs_fops = { .owner = THIS_MODULE, .read = dp_dsc_clock_en_read, @@ -2933,6 +2939,7 @@ static const struct file_operations dp_dsc_slice_bpg_offset_debugfs_fops = { .read = dp_dsc_slice_bpg_offset_read, .llseek = default_llseek }; +#endif static const struct file_operations trigger_hotplug_debugfs_fops = { .owner = THIS_MODULE, @@ -3006,6 +3013,8 @@ static const struct { {"dsc_chunk_size", &dp_dsc_chunk_size_debugfs_fops}, {"dsc_slice_bpg", &dp_dsc_slice_bpg_offset_debugfs_fops}, {"dp_dsc_fec_support", &dp_dsc_fec_support_fops}, +#endif + {"max_bpc", &dp_max_bpc_debugfs_fops}, {"dsc_disable_passthrough", &dp_dsc_disable_passthrough_debugfs_fops}, {"is_mst_connector", &dp_is_mst_connector_fops}, diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index 4b3e81600575f..d696722c1d98a 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -641,6 +641,7 @@ bool dm_helpers_submit_i2c( return result; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static bool execute_synaptics_rc_command(struct drm_dp_aux *aux, bool is_write_cmd, unsigned char cmd, @@ -811,7 +812,9 @@ static uint8_t write_dsc_enable_synaptics_non_virtual_dpcd_mst( return ret; } +#endif +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT bool dm_helpers_dp_write_dsc_enable( struct dc_context *ctx, const struct dc_stream_state *stream, @@ -894,6 +897,7 @@ bool dm_helpers_dp_write_dsc_enable( return ret; } +#endif bool dm_helpers_is_dp_sink_present(struct dc_link *link) { diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 16e103d403fbc..3ff4c755b05d4 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -233,6 +233,8 @@ static const struct drm_connector_funcs dm_dp_mst_connector_funcs = { #endif /* HAVE_DRM_DP_MST_CONNECTOR_EARLY_UNREGISTER */ }; +#if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT) +#if defined(HAVE_DRM_DP_MST_DSC_AUX_FOR_PORT) bool needs_dsc_aux_workaround(struct dc_link *link) { if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 && @@ -267,9 +269,7 @@ static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnecto u8 dsc_branch_dec_caps_raw[3] = { 0 }; // DSC branch decoder caps 0xA0 ~ 0xA2 u8 *dsc_branch_dec_caps = NULL; -#if defined(HAVE_DRM_DP_MST_DSC_AUX_FOR_PORT) aconnector->dsc_aux = drm_dp_mst_dsc_aux_for_port(port); -#endif /* * drm_dp_mst_dsc_aux_for_port() will return NULL for certain configs * because it only check the dsc/fec caps of the "port variable" and not the dock @@ -324,6 +324,8 @@ static bool retrieve_downstream_port_device(struct amdgpu_dm_connector *aconnect return true; } +#endif +#endif static int dm_dp_mst_get_modes(struct drm_connector *connector) { diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index c8dabb081b3d9..b362393c140f5 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -64,7 +64,9 @@ #include "dc_dmub_srv.h" +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include "dsc.h" +#endif #include "vm_helper.h" @@ -669,7 +671,9 @@ bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream, param.windowb_y_end = crc_window->windowb_y_end; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT param.dsc_mode = pipe->stream->timing.flags.DSC ? 1:0; +#endif param.odm_mode = pipe->next_odm_pipe ? 1:0; /* Default to the union of both windows */ @@ -2679,8 +2683,10 @@ static enum surface_update_type check_update_surfaces_for_stream( if (stream_update->wb_update) su_flags->bits.wb_update = 1; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (stream_update->dsc_config) su_flags->bits.dsc_changed = 1; +#endif if (stream_update->mst_bw_update) su_flags->bits.mst_bw = 1; @@ -2903,7 +2909,9 @@ static void copy_stream_update_to_stream(struct dc *dc, struct dc_stream_state *stream, struct dc_stream_update *update) { +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT struct dc_context *dc_ctx = dc->ctx; +#endif if (update == NULL || stream == NULL) return; @@ -2998,6 +3006,8 @@ static void copy_stream_update_to_stream(struct dc *dc, stream->writeback_info[i] = update->wb_update->writeback_info[i]; } + +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (update->dsc_config) { struct dc_dsc_config old_dsc_cfg = stream->timing.dsc_cfg; uint32_t old_dsc_enabled = stream->timing.flags.DSC; @@ -3022,6 +3032,7 @@ static void copy_stream_update_to_stream(struct dc *dc, update->dsc_config = NULL; } } +#endif } static void backup_planes_and_stream_state( @@ -3315,8 +3326,10 @@ static void commit_planes_do_stream_update(struct dc *dc, if (update_type == UPDATE_TYPE_FAST) continue; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (stream_update->dsc_config) dc->link_srv->update_dsc_config(pipe_ctx); +#endif if (stream_update->mst_bw_update) { if (stream_update->mst_bw_update->is_increase) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index b38340c690c60..41226e7a91be0 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -3755,7 +3755,11 @@ bool dc_resource_is_dsc_encoding_supported(const struct dc *dc) if (dc->res_pool == NULL) return false; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT return dc->res_pool->res_cap->num_dsc > 0; +#else + return 0; +#endif } static bool planes_changed_for_existing_stream(struct dc_state *context, @@ -4637,8 +4641,10 @@ bool pipe_need_reprogram( false == pipe_ctx_old->stream->dpms_off) return true; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (pipe_ctx_old->stream_res.dsc != pipe_ctx->stream_res.dsc) return true; +#endif if (pipe_ctx_old->stream_res.hpo_dp_stream_enc != pipe_ctx->stream_res.hpo_dp_stream_enc) return true; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index be2638c763d78..077947d031a31 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -107,6 +107,7 @@ bool dc_stream_construct(struct dc_stream_state *stream, /* EDID CAP translation for HDMI 2.0 */ stream->timing.flags.LTE_340MCSC_SCRAMBLE = dc_sink_data->edid_caps.lte_340mcsc_scramble; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT memset(&stream->timing.dsc_cfg, 0, sizeof(stream->timing.dsc_cfg)); stream->timing.dsc_cfg.num_slices_h = 0; stream->timing.dsc_cfg.num_slices_v = 0; @@ -115,6 +116,7 @@ bool dc_stream_construct(struct dc_stream_state *stream, stream->timing.dsc_cfg.linebuf_depth = 9; stream->timing.dsc_cfg.version_minor = 2; stream->timing.dsc_cfg.ycbcr422_simple = 0; +#endif update_stream_signal(stream, dc_sink_data); @@ -777,6 +779,7 @@ bool dc_stream_set_dynamic_metadata(struct dc *dc, return true; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT enum dc_status dc_stream_add_dsc_to_resource(struct dc *dc, struct dc_state *state, struct dc_stream_state *stream) @@ -787,6 +790,7 @@ enum dc_status dc_stream_add_dsc_to_resource(struct dc *dc, return DC_NO_DSC_RESOURCE; } } +#endif struct pipe_ctx *dc_stream_get_pipe_ctx(struct dc_stream_state *stream) { diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 6b036417a73ae..5f19d0df305ec 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -882,11 +882,13 @@ struct dc_debug_options { bool disable_dfs_bypass; bool disable_dpp_power_gate; bool disable_hubp_power_gate; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT bool disable_dsc_power_gate; bool disable_optc_power_gate; bool disable_hpo_power_gate; int dsc_min_slice_height_override; int dsc_bpp_increment_div; +#endif bool disable_pplib_wm_range; enum wm_report_mode pplib_wm_report_mode; unsigned int min_disp_clk_khz; @@ -2348,6 +2350,7 @@ struct dc_container_id { }; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT struct dc_sink_dsc_caps { // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), // 'false' if they are sink's DSC caps @@ -2357,6 +2360,7 @@ struct dc_sink_dsc_caps { bool is_dsc_passthrough_supported; struct dsc_dec_dpcd_caps dsc_dec_caps; }; +#endif struct dc_sink_fec_caps { bool is_rx_fec_supported; @@ -2382,8 +2386,10 @@ struct dc_sink { bool converter_disable_audio; struct scdc_caps scdc_caps; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT struct dc_sink_dsc_caps dsc_caps; struct dc_sink_fec_caps fec_caps; +#endif bool is_vsc_sdp_colorimetry_supported; @@ -2530,8 +2536,10 @@ struct dc_power_profile { struct dc_power_profile dc_get_power_profile_for_dc_state(const struct dc_state *context); +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* DSC Interfaces */ #include "dc_dsc.h" +#endif /* Disable acc mode Interfaces */ void dc_disable_accelerated_mode(struct dc *dc); diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h index de9bd72ca514d..68855b68a9764 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_stream.h +++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h @@ -437,9 +437,11 @@ bool dc_stream_remove_writeback(struct dc *dc, struct dc_stream_state *stream, uint32_t dwb_pipe_inst); +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT enum dc_status dc_stream_add_dsc_to_resource(struct dc *dc, struct dc_state *state, struct dc_stream_state *stream); +#endif bool dc_stream_warmup_writeback(struct dc *dc, int num_dwb, diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h index 97279b080f3e0..516a0f05cebc3 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_types.h @@ -535,7 +535,9 @@ enum dc_infoframe_type { DC_HDMI_INFOFRAME_TYPE_AVI = 0x82, DC_HDMI_INFOFRAME_TYPE_SPD = 0x83, DC_HDMI_INFOFRAME_TYPE_AUDIO = 0x84, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT DC_DP_INFOFRAME_TYPE_PPS = 0x10, +#endif }; struct dc_info_packet { diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c index cae18f8c1c9a0..abfd493314514 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c @@ -379,8 +379,9 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub, copy_settings_data->fec_enable_delay_in100us = link->dc->debug.fec_enable_delay_in100us; copy_settings_data->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1; copy_settings_data->panel_inst = panel_inst; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT copy_settings_data->dsc_enable_status = (pipe_ctx->stream->timing.flags.DSC == 1); - +#endif /** * WA for PSRSU+DSC on specific TCON, if DSC is enabled, force PSRSU as ffu mode(full frame update) * Note that PSRSU+DSC is still under development. @@ -394,6 +395,7 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub, link->psr_settings.force_ffu_mode = 0; copy_settings_data->force_ffu_mode = link->psr_settings.force_ffu_mode; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (((link->dpcd_caps.fec_cap.bits.FEC_CAPABLE && !link->dc->debug.disable_fec) && (link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT && @@ -406,6 +408,7 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub, sizeof(DP_SINK_DEVICE_STR_ID_2)))) copy_settings_data->debug.bitfields.force_wakeup_by_tps3 = 1; else +#endif copy_settings_data->debug.bitfields.force_wakeup_by_tps3 = 0; if (link->psr_settings.psr_version == DC_PSR_VERSION_1 && diff --git a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_link_encoder.c index 8d31fa131cd60..789d6800ff08c 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_link_encoder.c @@ -77,7 +77,9 @@ static bool dcn201_link_encoder_is_in_alt_mode(struct link_encoder *enc) } static const struct link_encoder_funcs dcn201_link_enc_funcs = { +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .read_state = link_enc2_read_state, +#endif .validate_output_with_stream = dcn10_link_encoder_validate_output_with_stream, .hw_init = enc2_hw_init, diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c index eb9abb9f96986..24fedaf5df408 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c @@ -298,7 +298,9 @@ static void dcn21_link_encoder_disable_output(struct link_encoder *enc, static const struct link_encoder_funcs dcn21_link_enc_funcs = { +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .read_state = link_enc2_read_state, +#endif .validate_output_with_stream = dcn10_link_encoder_validate_output_with_stream, .hw_init = enc2_hw_init, diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c index 51a57dae18114..d1518602a1702 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c @@ -173,8 +173,10 @@ static struct mpll_cfg dcn2_mpll_cfg[] = { void enc2_fec_set_enable(struct link_encoder *enc, bool enable) { struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT DC_LOG_DSC("%s FEC at link encoder inst %d", enable ? "Enabling" : "Disabling", enc->id.enum_id); +#endif REG_UPDATE(DP_DPHY_CNTL, DPHY_FEC_EN, enable); } @@ -194,7 +196,8 @@ bool enc2_fec_is_active(struct link_encoder *enc) return (active != 0); } - + +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* this function reads dsc related register fields to be logged later in dcn10_log_hw_state * into a dcn_dsc_state struct. */ @@ -207,6 +210,7 @@ void link_enc2_read_state(struct link_encoder *enc, struct link_enc_state *s) REG_GET(DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, &s->dphy_fec_active_status); REG_GET(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, &s->dp_link_training_complete); } +#endif static bool update_cfg_data( struct dcn10_link_encoder *enc10, @@ -356,7 +360,9 @@ void enc2_hw_init(struct link_encoder *enc) } static const struct link_encoder_funcs dcn20_link_enc_funcs = { +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .read_state = link_enc2_read_state, +#endif .validate_output_with_stream = dcn10_link_encoder_validate_output_with_stream, .hw_init = enc2_hw_init, diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h index 762c579fcb44d..39a5f6882cf95 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h @@ -342,7 +342,9 @@ void enc2_fec_set_ready(struct link_encoder *enc, bool ready); bool enc2_fec_is_active(struct link_encoder *enc); void enc2_hw_init(struct link_encoder *enc); +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void link_enc2_read_state(struct link_encoder *enc, struct link_enc_state *s); +#endif void dcn20_link_encoder_enable_dp_output( struct link_encoder *enc, diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c index 0b47aeb60e795..2fa2816e28aa0 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c @@ -207,7 +207,7 @@ static void enc2_stream_encoder_stop_hdmi_info_packets( HDMI_GENERIC7_LINE, 0); } - +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* Update GSP7 SDP 128 byte long */ static void enc2_update_gsp7_128_info_packet( struct dcn10_stream_encoder *enc1, @@ -365,6 +365,7 @@ static void enc2_read_state(struct stream_encoder *enc, struct enc_state *s) REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable); } } +#endif /* Set Dynamic Metadata-configuration. * enable_dme: TRUE: enables Dynamic Metadata Enfine, FALSE: disables DME @@ -460,8 +461,10 @@ static bool is_two_pixels_per_containter(const struct dc_crtc_timing *timing) { bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422 && !timing->dsc_cfg.ycbcr422_simple); +#endif return two_pix; } @@ -632,9 +635,11 @@ static const struct stream_encoder_funcs dcn20_str_enc_funcs = { .dp_get_pixel_format = enc1_stream_encoder_dp_get_pixel_format, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .enc_read_state = enc2_read_state, .dp_set_dsc_config = enc2_dp_set_dsc_config, .dp_set_dsc_pps_info_packet = enc2_dp_set_dsc_pps_info_packet, +#endif .set_dynamic_metadata = enc2_set_dynamic_metadata, .hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute, .get_fifo_cal_average_level = enc2_get_fifo_cal_average_level, diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c index b8e31b5ea1140..504b70931b701 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c @@ -56,7 +56,9 @@ bool dcn30_link_encoder_validate_output_with_stream( } static const struct link_encoder_funcs dcn30_link_enc_funcs = { +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .read_state = link_enc2_read_state, +#endif .validate_output_with_stream = dcn30_link_encoder_validate_output_with_stream, .hw_init = enc3_hw_init, diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c index 425b830b88d2c..8b0a72dd20846 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c @@ -295,6 +295,7 @@ void enc3_stream_encoder_stop_hdmi_info_packets( HDMI_GENERIC14_LINE, 0); } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* Set DSC-related configuration. * dsc_mode: 0 disables DSC, other values enable DSC in specified format * sc_bytes_per_pixel: Bytes per pixel in u3.28 format @@ -401,6 +402,7 @@ static void enc3_read_state(struct stream_encoder *enc, struct enc_state *s) REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable); } } +#endif void enc3_stream_encoder_update_dp_info_packets_sdp_line_num( struct stream_encoder *enc, @@ -865,9 +867,11 @@ static const struct stream_encoder_funcs dcn30_str_enc_funcs = { .dp_get_pixel_format = enc1_stream_encoder_dp_get_pixel_format, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .enc_read_state = enc3_read_state, .dp_set_dsc_config = enc3_dp_set_dsc_config, .dp_set_dsc_pps_info_packet = enc3_dp_set_dsc_pps_info_packet, +#endif .set_dynamic_metadata = enc2_set_dynamic_metadata, .hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute, diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c index 994b5ab885bb7..551f3918845dd 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c @@ -484,7 +484,9 @@ void dcn31_link_encoder_enable_dp_output( if (link) { dpia_control.dpia_id = link->ddc_hw_inst; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT dpia_control.fec_rdy = link->dc->link_srv->dp_should_enable_fec(link); +#endif } else { DC_LOG_ERROR("%s: Failed to execute DPIA enable DMUB command.\n", __func__); BREAK_TO_DEBUGGER(); @@ -531,7 +533,9 @@ void dcn31_link_encoder_enable_dp_mst_output( if (link) { dpia_control.dpia_id = link->ddc_hw_inst; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT dpia_control.fec_rdy = link->dc->link_srv->dp_should_enable_fec(link); +#endif } else { DC_LOG_ERROR("%s: Failed to execute DPIA enable DMUB command.\n", __func__); BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c index 5b343f745cf33..30a12b51e7896 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c @@ -375,6 +375,7 @@ void enc314_stream_encoder_dp_unblank( link->dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_ENABLE_DP_VID_STREAM); } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* Set DSC-related configuration. * dsc_mode: 0 disables DSC, other values enable DSC in specified format * sc_bytes_per_pixel: DP_DSC_BYTES_PER_PIXEL removed in DCN32 @@ -409,6 +410,7 @@ void enc314_read_state(struct stream_encoder *enc, struct enc_state *s) REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable); } } +#endif void enc314_set_dig_input_mode(struct stream_encoder *enc, unsigned int pix_per_container) { @@ -460,9 +462,11 @@ static const struct stream_encoder_funcs dcn314_str_enc_funcs = { .dp_get_pixel_format = enc1_stream_encoder_dp_get_pixel_format, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .enc_read_state = enc314_read_state, .dp_set_dsc_config = enc314_dp_set_dsc_config, .dp_set_dsc_pps_info_packet = enc3_dp_set_dsc_pps_info_packet, +#endif .set_dynamic_metadata = enc2_set_dynamic_metadata, .hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute, diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c index 06907e8a4eda1..cfcd48a67c760 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c @@ -195,7 +195,9 @@ void dcn32_link_encoder_get_max_link_cap(struct link_encoder *enc, static const struct link_encoder_funcs dcn32_link_enc_funcs = { +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .read_state = link_enc2_read_state, +#endif .validate_output_with_stream = dcn30_link_encoder_validate_output_with_stream, .hw_init = enc32_hw_init, diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c index 1a9bb614c41e0..173225fcdb6b5 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c @@ -346,6 +346,7 @@ void enc32_stream_encoder_dp_unblank( link->dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_ENABLE_DP_VID_STREAM); } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* Set DSC-related configuration. * dsc_mode: 0 disables DSC, other values enable DSC in specified format * sc_bytes_per_pixel: DP_DSC_BYTES_PER_PIXEL removed in DCN32 @@ -380,6 +381,7 @@ static void enc32_read_state(struct stream_encoder *enc, struct enc_state *s) REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable); } } +#endif static void enc32_set_dig_input_mode(struct stream_encoder *enc, unsigned int pix_per_container) { @@ -458,6 +460,7 @@ static const struct stream_encoder_funcs dcn32_str_enc_funcs = { .dp_get_pixel_format = enc1_stream_encoder_dp_get_pixel_format, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .enc_read_state = enc32_read_state, .dp_set_dsc_config = enc32_dp_set_dsc_config, .dp_set_dsc_pps_info_packet = enc3_dp_set_dsc_pps_info_packet, diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c index 2ed382a8e79c6..b555264990f6b 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c @@ -60,7 +60,9 @@ dm_write_reg(CTX, AUX_REG(reg_name), val) static const struct link_encoder_funcs dcn321_link_enc_funcs = { +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .read_state = link_enc2_read_state, +#endif .validate_output_with_stream = dcn30_link_encoder_validate_output_with_stream, .hw_init = enc32_hw_init, diff --git a/drivers/gpu/drm/amd/display/dc/dm_helpers.h b/drivers/gpu/drm/amd/display/dc/dm_helpers.h index 2e4a46f1b499d..69d846ccbb2a5 100644 --- a/drivers/gpu/drm/amd/display/dc/dm_helpers.h +++ b/drivers/gpu/drm/amd/display/dc/dm_helpers.h @@ -158,6 +158,7 @@ bool dm_helpers_dp_write_dsc_enable( const struct dc_stream_state *stream, bool enable ); + bool dm_helpers_is_dp_sink_present( struct dc_link *link); diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h index d5831a34f5a19..8975cd1529fa3 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h @@ -174,7 +174,9 @@ enum dm_validation_status { DML_FAIL_DIO_SUPPORT, DML_FAIL_NOT_ENOUGH_DSC, DML_FAIL_DSC_CLK_REQUIRED, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT DML_FAIL_DSC_VALIDATION_FAILURE, +#endif DML_FAIL_URGENT_LATENCY, DML_FAIL_REORDERING_BUFFER, DML_FAIL_DISPCLK_DPPCLK, diff --git a/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.c index ef75eb7d5adc3..e14e11ccf7d08 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.c @@ -23,6 +23,7 @@ * */ +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include "rc_calc_fpu.h" #include "qp_tables.h" @@ -257,4 +258,4 @@ void _do_calc_rc_params(struct rc_params *rc, rc->rc_buf_thresh[12] = 8000; rc->rc_buf_thresh[13] = 8064; } - +#endif diff --git a/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.h b/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.h index d7cd8cc247583..0b70eb9bcc6b9 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.h +++ b/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.h @@ -23,6 +23,7 @@ * */ +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #ifndef __RC_CALC_FPU_H__ #define __RC_CALC_FPU_H__ @@ -88,3 +89,4 @@ void _do_calc_rc_params(struct rc_params *rc, int minor_version); #endif +#endif diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c index a1727e5bf0247..6a1f4e778888e 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c @@ -22,6 +22,7 @@ * Author: AMD */ +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include #include #include "dc_hw_types.h" @@ -1268,3 +1269,4 @@ void dc_dsc_get_default_config_option(const struct dc *dc, struct dc_dsc_config_ options->max_target_bpp_limit_override_x16 = 0; options->slice_height_granularity = 1; } +#endif diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c index 75128fd343067..fd316e660df05 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c @@ -23,6 +23,7 @@ * */ +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include #include "reg_helper.h" @@ -772,3 +773,4 @@ static void dsc_write_to_registers(struct display_stream_compressor *dsc, const RANGE_BPG_OFFSET14, reg_vals->pps.rc_range_params[14].range_bpg_offset); } +#endif diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h index 1fb90b52b814b..18f62bd6f0c87 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h +++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h @@ -21,6 +21,7 @@ * Authors: AMD * */ +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #ifndef __DCN20_DSC_H__ #define __DCN20_DSC_H__ @@ -609,4 +610,4 @@ void dsc2_disconnect(struct display_stream_compressor *dsc); void dsc2_wait_disconnect_pending_clear(struct display_stream_compressor *dsc); #endif - +#endif diff --git a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c index 64cee8c80110c..d61b6430a6409 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c @@ -1,3 +1,4 @@ +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* * Copyright 2017 Advanced Micro Devices, Inc. @@ -62,3 +63,4 @@ void calc_rc_params(struct rc_params *rc, const struct drm_dsc_config *pps) DC_FP_END(); #endif } +#endif diff --git a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c index 59864130cf83b..b01295c412b1d 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c @@ -1,3 +1,4 @@ +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* * Copyright 2012-17 Advanced Micro Devices, Inc. * @@ -119,4 +120,4 @@ int dscc_compute_dsc_parameters(const struct drm_dsc_config *pps, dsc_params->rc_buffer_model_size = dsc_cfg.rc_bits; return ret; } - +#endif diff --git a/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c index 678db949cfe3c..b788f9d9d9306 100644 --- a/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c @@ -563,7 +563,9 @@ static void dcn31_hpo_dp_stream_enc_set_dsc_pps_info_packet( /* Load PPS into infoframe (SDP) registers */ pps_sdp.valid = true; pps_sdp.hb0 = 0; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT pps_sdp.hb1 = DC_DP_INFOFRAME_TYPE_PPS; +#endif pps_sdp.hb2 = 127; pps_sdp.hb3 = 0; diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c index 01dffed4d30ba..da01b34f65322 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c @@ -49,7 +49,9 @@ #include "clk_mgr.h" #include "link_hwss.h" #include "dpcd_defs.h" +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include "dsc.h" +#endif #include "dce/dmub_psr.h" #include "dc_dmub_srv.h" #include "dce/dmub_hw_lock_mgr.h" @@ -462,6 +464,7 @@ void dcn10_log_hw_state(struct dc *dc, } DTN_INFO("\n"); +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT // dcn_dsc_state struct field bytes_per_pixel was renamed to bits_per_pixel // TODO: Update golden log header to reflect this name change DTN_INFO("DSC: CLOCK_EN SLICE_WIDTH Bytes_pp\n"); @@ -518,6 +521,7 @@ void dcn10_log_hw_state(struct dc *dc, } } DTN_INFO("\n"); +#endif DTN_INFO("\nCALCULATED Clocks: dcfclk_khz:%d dcfclk_deep_sleep_khz:%d dispclk_khz:%d\n" "dppclk_khz:%d max_supported_dppclk_khz:%d fclk_khz:%d socclk_khz:%d\n\n", diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c index a80c085829320..761f5462f0716 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c @@ -32,7 +32,9 @@ #include "dcn20/dcn20_resource.h" #include "dcn20_hwseq.h" #include "dce/dce_hwseq.h" +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include "dcn20/dcn20_dsc.h" +#endif #include "dcn20/dcn20_optc.h" #include "abm.h" #include "clk_mgr.h" @@ -462,6 +464,7 @@ void dcn20_init_blank( hws->funcs.wait_for_blank_complete(opp); } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void dcn20_dsc_pg_control( struct dce_hwseq *hws, unsigned int dsc_inst, @@ -538,6 +541,7 @@ void dcn20_dsc_pg_control( if (org_ip_request_cntl == 0) REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); } +#endif void dcn20_dpp_pg_control( struct dce_hwseq *hws, @@ -2571,6 +2575,7 @@ bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx) void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx) { +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT struct dce_hwseq *hws = dc->hwseq; if (pipe_ctx->stream_res.dsc) { @@ -2582,10 +2587,12 @@ void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx) odm_pipe = odm_pipe->next_odm_pipe; } } +#endif } void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx) { +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT struct dce_hwseq *hws = dc->hwseq; if (pipe_ctx->stream_res.dsc) { @@ -2597,6 +2604,7 @@ void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx) odm_pipe = odm_pipe->next_odm_pipe; } } +#endif } void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h index 5c874f7b0683e..99f3e16f6fd67 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h @@ -130,10 +130,12 @@ void dcn20_init_vm_ctx( void dcn20_set_flip_control_gsl( struct pipe_ctx *pipe_ctx, bool flip_immediate); +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void dcn20_dsc_pg_control( struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on); +#endif void dcn20_fpga_init_hw(struct dc *dc); bool dcn20_wait_for_blank_complete( struct output_pixel_processor *opp); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c index 32707b344f0b6..e959818f70a9f 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c @@ -128,7 +128,11 @@ static const struct hwseq_private_funcs dcn20_private_funcs = { .dpp_pg_control = dcn20_dpp_pg_control, .hubp_pg_control = dcn20_hubp_pg_control, .update_odm = dcn20_update_odm, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .dsc_pg_control = dcn20_dsc_pg_control, +#else + .dsc_pg_control = NULL, +#endif .set_hdr_multiplier = dcn10_set_hdr_multiplier, .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high, .wait_for_blank_complete = dcn20_wait_for_blank_complete, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.c index e044e9e0a3a17..18095ea37a638 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.c @@ -131,7 +131,9 @@ static const struct hwseq_private_funcs dcn21_private_funcs = { .dpp_pg_control = dcn20_dpp_pg_control, .hubp_pg_control = dcn20_hubp_pg_control, .update_odm = dcn20_update_odm, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .dsc_pg_control = dcn20_dsc_pg_control, +#endif .set_hdr_multiplier = dcn10_set_hdr_multiplier, .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high, .s0i3_golden_init_wa = dcn21_s0i3_golden_init_wa, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c index 2a8dc40d28477..bf5438c9be761 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c @@ -137,7 +137,9 @@ static const struct hwseq_private_funcs dcn30_private_funcs = { .hubp_pg_control = dcn20_hubp_pg_control, .program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree, .update_odm = dcn20_update_odm, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .dsc_pg_control = dcn20_dsc_pg_control, +#endif .set_hdr_multiplier = dcn10_set_hdr_multiplier, .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high, .wait_for_blank_complete = dcn20_wait_for_blank_complete, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c index a4dcf7d95c5b6..f21171522013c 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c @@ -363,8 +363,10 @@ void dcn31_enable_power_gating_plane( REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); force_on = true; /* disable power gating */ +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (enable && !hws->ctx->dc->debug.disable_dsc_power_gate) force_on = false; +#endif /* DCS0/1/2/3/4/5 */ REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c index 4e93eeedfc1bb..fd9fd7d22eb39 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c @@ -195,6 +195,7 @@ void dcn314_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx } } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void dcn314_dsc_pg_control( struct dce_hwseq *hws, unsigned int dsc_inst, @@ -265,6 +266,7 @@ void dcn314_dsc_pg_control( } } +#endif void dcn314_enable_power_gating_plane(struct dce_hwseq *hws, bool enable) { @@ -285,8 +287,10 @@ void dcn314_enable_power_gating_plane(struct dce_hwseq *hws, bool enable) REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); force_on = true; /* disable power gating */ +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (enable && !hws->ctx->dc->debug.disable_dsc_power_gate) force_on = false; +#endif /* DCS0/1/2/3/4 */ REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c index fe5495a8e7a2b..28e6c89bbeac4 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c @@ -142,7 +142,9 @@ static const struct hwseq_private_funcs dcn314_private_funcs = { .hubp_pg_control = dcn31_hubp_pg_control, .program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree, .update_odm = dcn314_update_odm, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .dsc_pg_control = dcn314_dsc_pg_control, +#endif .set_hdr_multiplier = dcn10_set_hdr_multiplier, .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high, .wait_for_blank_complete = dcn20_wait_for_blank_complete, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c index a36e11606f90e..4199f8b0682e1 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c @@ -66,6 +66,7 @@ #define FN(reg_name, field_name) \ hws->shifts->field_name, hws->masks->field_name +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void dcn32_dsc_pg_control( struct dce_hwseq *hws, unsigned int dsc_inst, @@ -128,7 +129,7 @@ void dcn32_dsc_pg_control( if (org_ip_request_cntl == 0) REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); } - +#endif void dcn32_enable_power_gating_plane( struct dce_hwseq *hws, diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index bfb8b8502d202..b67cf5c01fe31 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -201,10 +201,11 @@ struct resource_funcs { const struct resource_pool *pool, struct dc_3dlut **lut, struct dc_transfer_func **shaper); - +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT enum dc_status (*add_dsc_to_stream_resource)( struct dc *dc, struct dc_state *state, struct dc_stream_state *stream); +#endif void (*add_phantom_pipes)( struct dc *dc, @@ -250,7 +251,9 @@ struct resource_pool { unsigned int gsl_2:1; } gsl_groups; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT struct display_stream_compressor *dscs[MAX_PIPES]; +#endif unsigned int pipe_count; unsigned int underlay_pipe_index; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h index af9183f5d69be..6210dc83601aa 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h @@ -89,6 +89,7 @@ struct link_encoder { bool usbc_combo_phy; }; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT struct link_enc_state { uint32_t dphy_fec_en; @@ -97,6 +98,7 @@ struct link_enc_state { uint32_t dp_link_training_complete; }; +#endif enum encoder_type_select { ENCODER_TYPE_DIG = 0, @@ -105,8 +107,10 @@ enum encoder_type_select { }; struct link_encoder_funcs { +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void (*read_state)( struct link_encoder *enc, struct link_enc_state *s); +#endif bool (*validate_output_with_stream)( struct link_encoder *enc, const struct dc_stream_state *stream); void (*hw_init)(struct link_encoder *enc); diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h index 3d4c8bd42b492..069aa15771b49 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h @@ -136,7 +136,9 @@ struct crc_params { enum crc_selection selection; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT uint8_t dsc_mode; +#endif uint8_t odm_mode; bool continuous_mode; diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c index cd1975c03f38d..bacf79bd77fe8 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c @@ -104,7 +104,9 @@ static enum link_training_result dpia_configure_link( struct link_training_settings *lt_settings) { enum dc_status status; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT bool fec_enable; +#endif DC_LOG_HW_LINK_TRAINING("%s\n DPIA(%d) configuring\n - LTTPR mode(%d)\n", __func__, @@ -132,6 +134,7 @@ static enum link_training_result dpia_configure_link( if (status != DC_OK && link->is_hpd_pending) return LINK_TRAINING_ABORT; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (link->preferred_training_settings.fec_enable != NULL) fec_enable = *link->preferred_training_settings.fec_enable; else @@ -139,6 +142,7 @@ static enum link_training_result dpia_configure_link( status = dp_set_fec_ready(link, link_res, fec_enable); if (status != DC_OK && link->is_hpd_pending) return LINK_TRAINING_ABORT; +#endif return LINK_TRAINING_SUCCESS; } diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c index b4694985a40a4..3ced93c471b4e 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c @@ -124,6 +124,7 @@ void optc2_set_gsl_source_select( } } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* Set DSC-related configuration. * dsc_mode: 0 disables DSC, other values enable DSC in specified format * sc_bytes_per_pixel: Bytes per pixel in u3.28 format @@ -145,6 +146,7 @@ void optc2_set_dsc_config(struct timing_generator *optc, REG_UPDATE(OPTC_WIDTH_CONTROL, OPTC_DSC_SLICE_WIDTH, dsc_slice_width); } +#endif /* Get DSC-related configuration. * dsc_mode: 0 disables DSC, other values enable DSC in specified format @@ -487,9 +489,14 @@ bool optc2_configure_crc(struct timing_generator *optc, { struct optc *optc1 = DCN10TG_FROM_TG(optc); +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT REG_SET_2(OTG_CRC_CNTL2, 0, OTG_CRC_DSC_MODE, params->dsc_mode, OTG_CRC_DATA_STREAM_COMBINE_MODE, params->odm_mode); +#else + REG_SET(OTG_CRC_CNTL2, 0, + OTG_CRC_DATA_STREAM_COMBINE_MODE, params->odm_mode); +#endif return optc1_configure_crc(optc, params); } @@ -548,7 +555,9 @@ static struct timing_generator_funcs dcn20_tg_funcs = { .setup_global_swap_lock = NULL, .get_crc = optc1_get_crc, .configure_crc = optc2_configure_crc, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .set_dsc_config = optc2_set_dsc_config, +#endif .get_dsc_status = optc2_get_dsc_status, .set_dwb_source = optc2_set_dwb_source, .set_odm_bypass = optc2_set_odm_bypass, diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h index 364034b190281..3b6fce749372d 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h @@ -93,10 +93,12 @@ void optc2_set_gsl_source_select(struct timing_generator *optc, int group_idx, uint32_t gsl_ready_signal); +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void optc2_set_dsc_config(struct timing_generator *optc, enum optc_dsc_mode dsc_mode, uint32_t dsc_bytes_per_pixel, uint32_t dsc_slice_width); +#endif void optc2_get_dsc_status(struct timing_generator *optc, uint32_t *dsc_mode); diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c index 49c2efdfa403a..1637b5064a267 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c @@ -172,7 +172,9 @@ static struct timing_generator_funcs dcn201_tg_funcs = { .clear_optc_underflow = optc1_clear_optc_underflow, .get_crc = optc1_get_crc, .configure_crc = optc2_configure_crc, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .set_dsc_config = optc2_set_dsc_config, +#endif .set_dwb_source = NULL, .get_optc_source = optc201_get_optc_source, .set_vtg_params = optc1_set_vtg_params, diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c index abcd03d786684..55be7da0cf34d 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c @@ -176,6 +176,7 @@ void optc3_set_vtotal_change_limit(struct timing_generator *optc, } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* Set DSC-related configuration. * dsc_mode: 0 disables DSC, other values enable DSC in specified format * sc_bytes_per_pixel: Bytes per pixel in u3.28 format @@ -191,6 +192,7 @@ void optc3_set_dsc_config(struct timing_generator *optc, optc2_set_dsc_config(optc, dsc_mode, dsc_bytes_per_pixel, dsc_slice_width); REG_UPDATE(OTG_V_SYNC_A_CNTL, OTG_V_SYNC_MODE, 0); } +#endif void optc3_set_odm_bypass(struct timing_generator *optc, const struct dc_crtc_timing *dc_crtc_timing) @@ -358,7 +360,9 @@ static struct timing_generator_funcs dcn30_tg_funcs = { .setup_global_swap_lock = NULL, .get_crc = optc1_get_crc, .configure_crc = optc2_configure_crc, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .set_dsc_config = optc3_set_dsc_config, +#endif .get_dsc_status = optc2_get_dsc_status, .set_dwb_source = NULL, .set_odm_bypass = optc3_set_odm_bypass, diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h index bda974d432ea6..05e1660963709 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h @@ -342,10 +342,12 @@ void optc3_program_blank_color(struct timing_generator *optc, void optc3_set_vtotal_change_limit(struct timing_generator *optc, uint32_t limit); +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void optc3_set_dsc_config(struct timing_generator *optc, enum optc_dsc_mode dsc_mode, uint32_t dsc_bytes_per_pixel, uint32_t dsc_slice_width); +#endif void optc3_set_timing_db_mode(struct timing_generator *optc, bool enable); diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c index 633d62addd4d2..05c8ecdb0ef18 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c @@ -237,7 +237,9 @@ static struct timing_generator_funcs dcn314_tg_funcs = { .setup_global_swap_lock = NULL, .get_crc = optc1_get_crc, .configure_crc = optc1_configure_crc, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .set_dsc_config = optc3_set_dsc_config, +#endif .get_dsc_status = optc2_get_dsc_status, .set_dwb_source = NULL, .get_optc_source = optc2_get_optc_source, diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c index 00094f0e84706..58e7084a3380f 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c @@ -354,7 +354,9 @@ static struct timing_generator_funcs dcn32_tg_funcs = { .setup_global_swap_lock = NULL, .get_crc = optc1_get_crc, .configure_crc = optc1_configure_crc, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .set_dsc_config = optc3_set_dsc_config, +#endif .get_dsc_status = optc2_get_dsc_status, .set_dwb_source = NULL, .set_odm_bypass = optc32_set_odm_bypass, diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c index eea2b3b307cd5..f81307a2d4780 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c @@ -618,6 +618,7 @@ static int map_transmitter_id_to_phy_instance( } } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #define dsc_regsDCN20(id)\ [id] = {\ DSC_REG_LIST_DCN20(id)\ @@ -639,6 +640,7 @@ static const struct dcn20_dsc_shift dsc_shift = { static const struct dcn20_dsc_mask dsc_mask = { DSC_REG_LIST_SH_MASK_DCN20(_MASK) }; +#endif static const struct dccg_registers dccg_regs = { DCCG_REG_LIST_DCN2() @@ -662,7 +664,9 @@ static const struct resource_caps res_cap_nv10 = { .num_dwb = 1, .num_ddc = 6, .num_vmid = 16, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .num_dsc = 6, +#endif }; static const struct dc_plane_cap plane_cap = { @@ -700,7 +704,9 @@ static const struct resource_caps res_cap_nv14 = { .num_dwb = 1, .num_ddc = 5, .num_vmid = 16, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .num_dsc = 5, +#endif }; static const struct dc_debug_options debug_defaults_drv = { @@ -1057,7 +1063,7 @@ void dcn20_clock_source_destroy(struct clock_source **clk_src) *clk_src = NULL; } - +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT struct display_stream_compressor *dcn20_dsc_create( struct dc_context *ctx, uint32_t inst) { @@ -1078,7 +1084,7 @@ void dcn20_dsc_destroy(struct display_stream_compressor **dsc) kfree(container_of(*dsc, struct dcn20_dsc, base)); *dsc = NULL; } - +#endif static void dcn20_resource_destruct(struct dcn20_resource_pool *pool) { @@ -1091,10 +1097,12 @@ static void dcn20_resource_destruct(struct dcn20_resource_pool *pool) } } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } +#endif if (pool->base.mpc != NULL) { kfree(TO_DCN20_MPC(pool->base.mpc)); @@ -1321,7 +1329,7 @@ enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state return status; } - +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void dcn20_acquire_dsc(const struct dc *dc, struct resource_context *res_ctx, struct display_stream_compressor **dsc, @@ -1371,8 +1379,6 @@ void dcn20_release_dsc(struct resource_context *res_ctx, } } - - enum dc_status dcn20_add_dsc_to_stream_resource(struct dc *dc, struct dc_state *dc_ctx, struct dc_stream_state *dc_stream) @@ -1428,7 +1434,7 @@ static enum dc_status remove_dsc_from_stream_resource(struct dc *dc, else return DC_OK; } - +#endif enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream) { @@ -1439,9 +1445,11 @@ enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, if (result == DC_OK) result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream); +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* Get a DSC if required and available */ if (result == DC_OK && dc_stream->timing.flags.DSC) result = dcn20_add_dsc_to_stream_resource(dc, new_ctx, dc_stream); +#endif if (result == DC_OK) result = dcn20_build_mapped_resource(dc, new_ctx, dc_stream); @@ -1454,7 +1462,9 @@ enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ { enum dc_status result = DC_OK; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT result = remove_dsc_from_stream_resource(dc, new_ctx, dc_stream); +#endif return result; } @@ -1493,7 +1503,9 @@ bool dcn20_split_stream_for_odm( next_odm_pipe->plane_res.xfm = pool->transforms[next_odm_pipe->pipe_idx]; next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx]; next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT next_odm_pipe->stream_res.dsc = NULL; +#endif if (prev_odm_pipe->next_odm_pipe && prev_odm_pipe->next_odm_pipe != next_odm_pipe) { next_odm_pipe->next_odm_pipe = prev_odm_pipe->next_odm_pipe; next_odm_pipe->next_odm_pipe->prev_odm_pipe = next_odm_pipe; @@ -1549,12 +1561,14 @@ bool dcn20_split_stream_for_odm( next_odm_pipe->stream_res.opp = pool->opps[next_odm_pipe->pipe_idx]; else next_odm_pipe->stream_res.opp = next_odm_pipe->top_pipe->stream_res.opp; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (next_odm_pipe->stream->timing.flags.DSC == 1 && !next_odm_pipe->top_pipe) { dcn20_acquire_dsc(dc, res_ctx, &next_odm_pipe->stream_res.dsc, next_odm_pipe->pipe_idx); ASSERT(next_odm_pipe->stream_res.dsc); if (next_odm_pipe->stream_res.dsc == NULL) return false; } +#endif return true; } @@ -1578,7 +1592,9 @@ void dcn20_split_stream_for_mpc( secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx]; secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx]; secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT secondary_pipe->stream_res.dsc = NULL; +#endif if (primary_pipe->bottom_pipe && primary_pipe->bottom_pipe != secondary_pipe) { ASSERT(!secondary_pipe->bottom_pipe); secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe; @@ -1669,6 +1685,7 @@ void dcn20_set_mcif_arb_params( } } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx) { int i; @@ -1703,6 +1720,7 @@ bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx) } return true; } +#endif struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc, struct resource_context *res_ctx, @@ -1806,8 +1824,10 @@ void dcn20_merge_pipes_for_validate( odm_pipe->bottom_pipe = NULL; odm_pipe->prev_odm_pipe = NULL; odm_pipe->next_odm_pipe = NULL; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (odm_pipe->stream_res.dsc) dcn20_release_dsc(&context->res_ctx, dc->res_pool, &odm_pipe->stream_res.dsc); +#endif /* Clear plane_res and stream_res */ memset(&odm_pipe->plane_res, 0, sizeof(odm_pipe->plane_res)); memset(&odm_pipe->stream_res, 0, sizeof(odm_pipe->stream_res)); @@ -2133,12 +2153,14 @@ bool dcn20_fast_validate_bw( ASSERT(0); } } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* Actual dsc count per stream dsc validation*/ if (!dcn20_validate_dsc(dc, context)) { context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] = DML_FAIL_DSC_VALIDATION_FAILURE; goto validate_fail; } +#endif *vlevel_out = vlevel; @@ -2252,7 +2274,9 @@ static const struct resource_funcs dcn20_res_pool_funcs = { .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, .add_stream_to_ctx = dcn20_add_stream_to_ctx, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, +#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context, .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, @@ -2719,6 +2743,7 @@ static bool dcn20_resource_construct( goto create_fail; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { pool->base.dscs[i] = dcn20_dsc_create(ctx, i); if (pool->base.dscs[i] == NULL) { @@ -2727,6 +2752,7 @@ static bool dcn20_resource_construct( goto create_fail; } } +#endif if (!dcn20_dwbc_create(ctx, &pool->base)) { BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h index 4cee3fa11a7ff..b1ba01c6d0f05 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h @@ -132,7 +132,9 @@ int dcn20_validate_apply_pipe_split_flags( void dcn20_release_dsc(struct resource_context *res_ctx, const struct resource_pool *pool, struct display_stream_compressor **dsc); +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx); +#endif void dcn20_split_stream_for_mpc( struct resource_context *res_ctx, const struct resource_pool *pool, diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c index fc54483b91047..610ac22626430 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c @@ -1073,7 +1073,9 @@ static struct resource_funcs dcn201_res_pool_funcs = { .validate_bandwidth = dcn20_validate_bandwidth, .populate_dml_pipes = dcn20_populate_dml_pipes_from_context, .add_stream_to_ctx = dcn20_add_stream_to_ctx, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = NULL, +#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .acquire_free_pipe_as_secondary_dpp_pipe = dcn201_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c index 347e6aaea582f..b6289060027eb 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c @@ -362,6 +362,7 @@ static const struct dcn20_vmid_mask vmid_masks = { DCN20_VMID_MASK_SH_LIST(_MASK) }; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #define dsc_regsDCN20(id)\ [id] = {\ DSC_REG_LIST_DCN20(id)\ @@ -383,6 +384,7 @@ static const struct dcn20_dsc_shift dsc_shift = { static const struct dcn20_dsc_mask dsc_mask = { DSC_REG_LIST_SH_MASK_DCN20(_MASK) }; +#endif #define ipp_regs(id)\ [id] = {\ @@ -578,7 +580,9 @@ static const struct resource_caps res_cap_rn = { .num_dwb = 1, .num_ddc = 5, .num_vmid = 16, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .num_dsc = 3, +#endif }; static const struct dc_plane_cap plane_cap = { @@ -662,10 +666,12 @@ static void dcn21_resource_destruct(struct dcn21_resource_pool *pool) } } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } +#endif if (pool->base.mpc != NULL) { kfree(TO_DCN20_MPC(pool->base.mpc)); @@ -900,12 +906,14 @@ bool dcn21_fast_validate_bw(struct dc *dc, ASSERT(0); } } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* Actual dsc count per stream dsc validation*/ if (!dcn20_validate_dsc(dc, context)) { context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] = DML_FAIL_DSC_VALIDATION_FAILURE; goto validate_fail; } +#endif *vlevel_out = vlevel; @@ -1086,7 +1094,7 @@ static void read_dce_straps( } - +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static struct display_stream_compressor *dcn21_dsc_create(struct dc_context *ctx, uint32_t inst) { @@ -1101,6 +1109,7 @@ static struct display_stream_compressor *dcn21_dsc_create(struct dc_context *ctx dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); return &dsc->base; } +#endif static struct pp_smu_funcs *dcn21_pp_smu_create(struct dc_context *ctx) { @@ -1369,7 +1378,9 @@ static const struct resource_funcs dcn21_res_pool_funcs = { .validate_bandwidth = dcn21_validate_bandwidth, .populate_dml_pipes = dcn21_populate_dml_pipes_from_context, .add_stream_to_ctx = dcn20_add_stream_to_ctx, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, +#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, @@ -1653,6 +1664,7 @@ static bool dcn21_resource_construct( goto create_fail; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { pool->base.dscs[i] = dcn21_dsc_create(ctx, i); if (pool->base.dscs[i] == NULL) { @@ -1661,6 +1673,7 @@ static bool dcn21_resource_construct( goto create_fail; } } +#endif if (!dcn20_dwbc_create(ctx, &pool->base)) { BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c index 5040a4c6ed186..9f1678716f5f6 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c @@ -46,7 +46,9 @@ #include "dcn30/dcn30_hwseq.h" #include "dce110/dce110_hwseq.h" #include "dcn30/dcn30_opp.h" +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include "dcn20/dcn20_dsc.h" +#endif #include "dcn30/dcn30_vpg.h" #include "dcn30/dcn30_afmt.h" #include "dcn30/dcn30_dio_stream_encoder.h" @@ -511,6 +513,7 @@ static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { DSC_REG_LIST_DCN20(id)\ } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static const struct dcn20_dsc_registers dsc_regs[] = { dsc_regsDCN20(0), dsc_regsDCN20(1), @@ -527,6 +530,7 @@ static const struct dcn20_dsc_shift dsc_shift = { static const struct dcn20_dsc_mask dsc_mask = { DSC_REG_LIST_SH_MASK_DCN20(_MASK) }; +#endif static const struct dcn30_mpc_registers mpc_regs = { MPC_REG_LIST_DCN3_0(0), @@ -677,7 +681,9 @@ static const struct resource_caps res_cap_dcn3 = { .num_ddc = 6, .num_vmid = 16, .num_mpc_3dlut = 3, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .num_dsc = 6, +#endif }; static const struct dc_plane_cap plane_cap = { @@ -1082,10 +1088,12 @@ static void dcn30_resource_destruct(struct dcn30_resource_pool *pool) } } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } +#endif if (pool->base.mpc != NULL) { kfree(TO_DCN20_MPC(pool->base.mpc)); @@ -1263,6 +1271,7 @@ static bool dcn30_mmhubbub_create(struct dc_context *ctx, struct resource_pool * return true; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static struct display_stream_compressor *dcn30_dsc_create( struct dc_context *ctx, uint32_t inst) { @@ -1277,6 +1286,7 @@ static struct display_stream_compressor *dcn30_dsc_create( dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); return &dsc->base; } +#endif enum dc_status dcn30_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream) { @@ -1537,7 +1547,9 @@ static bool dcn30_split_stream_for_mpc_or_odm( sec_pipe->plane_res.xfm = pool->transforms[pipe_idx]; sec_pipe->plane_res.dpp = pool->dpps[pipe_idx]; sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT sec_pipe->stream_res.dsc = NULL; +#endif if (odm) { if (pri_pipe->next_odm_pipe) { ASSERT(pri_pipe->next_odm_pipe != sec_pipe); @@ -1559,12 +1571,14 @@ static bool dcn30_split_stream_for_mpc_or_odm( sec_pipe->stream_res.opp = pool->opps[pipe_idx]; else sec_pipe->stream_res.opp = sec_pipe->top_pipe->stream_res.opp; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (sec_pipe->stream->timing.flags.DSC == 1) { dcn20_acquire_dsc(dc, res_ctx, &sec_pipe->stream_res.dsc, pipe_idx); ASSERT(sec_pipe->stream_res.dsc); if (sec_pipe->stream_res.dsc == NULL) return false; } +#endif } else { if (pri_pipe->bottom_pipe) { ASSERT(pri_pipe->bottom_pipe != sec_pipe); @@ -1739,8 +1753,10 @@ noinline bool dcn30_internal_validate_bw( pipe->stream = NULL; pipe->top_pipe = NULL; pipe->prev_odm_pipe = NULL; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (pipe->stream_res.dsc) dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc); +#endif memset(&pipe->plane_res, 0, sizeof(pipe->plane_res)); memset(&pipe->stream_res, 0, sizeof(pipe->stream_res)); repopulate_pipes = true; @@ -1859,11 +1875,13 @@ noinline bool dcn30_internal_validate_bw( } } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* Actual dsc count per stream dsc validation*/ if (!dcn20_validate_dsc(dc, context)) { vba->ValidationStatus[vba->soc.num_states] = DML_FAIL_DSC_VALIDATION_FAILURE; goto validate_fail; } +#endif if (repopulate_pipes) pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate); @@ -2241,7 +2259,9 @@ static const struct resource_funcs dcn30_res_pool_funcs = { .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, .add_stream_to_ctx = dcn30_add_stream_to_ctx, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, +#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, .set_mcif_arb_params = dcn30_set_mcif_arb_params, @@ -2532,6 +2552,7 @@ static bool dcn30_resource_construct( goto create_fail; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { pool->base.dscs[i] = dcn30_dsc_create(ctx, i); if (pool->base.dscs[i] == NULL) { @@ -2540,6 +2561,7 @@ static bool dcn30_resource_construct( goto create_fail; } } +#endif /* DWB and MMHUBBUB */ if (!dcn30_dwbc_create(ctx, &pool->base)) { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c index c3653c6e878a4..75bd9b8dc8dfd 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c @@ -1402,7 +1402,9 @@ static struct resource_funcs dcn301_res_pool_funcs = { .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, .add_stream_to_ctx = dcn30_add_stream_to_ctx, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, +#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, .set_mcif_arb_params = dcn30_set_mcif_arb_params, diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c index 169924d0a8393..2b10c2c1d3683 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c @@ -574,6 +574,7 @@ static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { DSC_REG_LIST_DCN20(id)\ } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static const struct dcn20_dsc_registers dsc_regs[] = { dsc_regsDCN314(0), dsc_regsDCN314(1), @@ -588,6 +589,7 @@ static const struct dcn20_dsc_shift dsc_shift = { static const struct dcn20_dsc_mask dsc_mask = { DSC_REG_LIST_SH_MASK_DCN20(_MASK) }; +#endif static const struct dcn30_mpc_registers mpc_regs = { MPC_REG_LIST_DCN3_0(0), @@ -1440,10 +1442,12 @@ static void dcn314_resource_destruct(struct dcn314_resource_pool *pool) } } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } +#endif if (pool->base.mpc != NULL) { kfree(TO_DCN20_MPC(pool->base.mpc)); @@ -1617,6 +1621,7 @@ static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool * return true; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static struct display_stream_compressor *dcn314_dsc_create( struct dc_context *ctx, uint32_t inst) { @@ -1631,6 +1636,7 @@ static struct display_stream_compressor *dcn314_dsc_create( dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); return &dsc->base; } +#endif static void dcn314_destroy_resource_pool(struct resource_pool **pool) { @@ -1767,7 +1773,9 @@ static struct resource_funcs dcn314_res_pool_funcs = { .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, .add_stream_to_ctx = dcn30_add_stream_to_ctx, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, +#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, .set_mcif_arb_params = dcn30_set_mcif_arb_params, @@ -2055,6 +2063,7 @@ static bool dcn314_resource_construct( goto create_fail; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { pool->base.dscs[i] = dcn314_dsc_create(ctx, i); if (pool->base.dscs[i] == NULL) { @@ -2063,6 +2072,7 @@ static bool dcn314_resource_construct( goto create_fail; } } +#endif /* DWB and MMHUBBUB */ if (!dcn31_dwbc_create(ctx, &pool->base)) { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c index 3f4b9dba41124..65d9bc4c262ea 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c @@ -49,7 +49,9 @@ #include "dcn30/dcn30_hwseq.h" #include "dce110/dce110_hwseq.h" #include "dcn30/dcn30_opp.h" +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include "dcn20/dcn20_dsc.h" +#endif #include "dcn30/dcn30_vpg.h" #include "dcn30/dcn30_afmt.h" #include "dcn30/dcn30_dio_stream_encoder.h" @@ -566,6 +568,7 @@ static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) }; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #define dsc_regsDCN20(id)\ [id] = {\ DSC_REG_LIST_DCN20(id)\ @@ -584,6 +587,7 @@ static const struct dcn20_dsc_shift dsc_shift = { static const struct dcn20_dsc_mask dsc_mask = { DSC_REG_LIST_SH_MASK_DCN20(_MASK) }; +#endif static const struct dcn30_mpc_registers mpc_regs = { MPC_REG_LIST_DCN3_0(0), @@ -823,7 +827,9 @@ static const struct resource_caps res_cap_dcn31 = { .num_ddc = 5, .num_vmid = 16, .num_mpc_3dlut = 2, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .num_dsc = 3, +#endif }; static const struct dc_plane_cap plane_cap = { @@ -1383,10 +1389,12 @@ static void dcn315_resource_destruct(struct dcn315_resource_pool *pool) } } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } +#endif if (pool->base.mpc != NULL) { kfree(TO_DCN20_MPC(pool->base.mpc)); @@ -1561,6 +1569,7 @@ static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool * return true; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static struct display_stream_compressor *dcn31_dsc_create( struct dc_context *ctx, uint32_t inst) { @@ -1575,6 +1584,7 @@ static struct display_stream_compressor *dcn31_dsc_create( dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); return &dsc->base; } +#endif static void dcn315_destroy_resource_pool(struct resource_pool **pool) { @@ -1830,7 +1840,9 @@ static struct resource_funcs dcn315_res_pool_funcs = { .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, .add_stream_to_ctx = dcn30_add_stream_to_ctx, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, +#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .populate_dml_writeback_from_context = dcn31_populate_dml_writeback_from_context, .set_mcif_arb_params = dcn31_set_mcif_arb_params, @@ -2081,6 +2093,7 @@ static bool dcn315_resource_construct( goto create_fail; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { pool->base.dscs[i] = dcn31_dsc_create(ctx, i); if (pool->base.dscs[i] == NULL) { @@ -2089,6 +2102,7 @@ static bool dcn315_resource_construct( goto create_fail; } } +#endif /* DWB and MMHUBBUB */ if (!dcn31_dwbc_create(ctx, &pool->base)) { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c index 5fd52c5fcee45..405661e66d4b9 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c @@ -49,7 +49,9 @@ #include "dcn30/dcn30_hwseq.h" #include "dce110/dce110_hwseq.h" #include "dcn30/dcn30_opp.h" +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include "dcn20/dcn20_dsc.h" +#endif #include "dcn30/dcn30_vpg.h" #include "dcn30/dcn30_afmt.h" #include "dcn30/dcn30_dio_stream_encoder.h" @@ -557,6 +559,8 @@ static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) }; + +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #define dsc_regsDCN20(id)\ [id] = {\ DSC_REG_LIST_DCN20(id)\ @@ -575,6 +579,7 @@ static const struct dcn20_dsc_shift dsc_shift = { static const struct dcn20_dsc_mask dsc_mask = { DSC_REG_LIST_SH_MASK_DCN20(_MASK) }; +#endif static const struct dcn30_mpc_registers mpc_regs = { MPC_REG_LIST_DCN3_0(0), @@ -818,7 +823,9 @@ static const struct resource_caps res_cap_dcn31 = { .num_ddc = 5, .num_vmid = 16, .num_mpc_3dlut = 2, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .num_dsc = 3, +#endif }; static const struct dc_plane_cap plane_cap = { @@ -1379,10 +1386,12 @@ static void dcn316_resource_destruct(struct dcn316_resource_pool *pool) } } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } +#endif if (pool->base.mpc != NULL) { kfree(TO_DCN20_MPC(pool->base.mpc)); @@ -1554,6 +1563,7 @@ static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool * return true; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static struct display_stream_compressor *dcn31_dsc_create( struct dc_context *ctx, uint32_t inst) { @@ -1568,6 +1578,7 @@ static struct display_stream_compressor *dcn31_dsc_create( dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); return &dsc->base; } +#endif static void dcn316_destroy_resource_pool(struct resource_pool **pool) { @@ -1710,7 +1721,9 @@ static struct resource_funcs dcn316_res_pool_funcs = { .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, .add_stream_to_ctx = dcn30_add_stream_to_ctx, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, +#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .populate_dml_writeback_from_context = dcn31_populate_dml_writeback_from_context, .set_mcif_arb_params = dcn31_set_mcif_arb_params, @@ -1953,6 +1966,7 @@ static bool dcn316_resource_construct( goto create_fail; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { pool->base.dscs[i] = dcn31_dsc_create(ctx, i); if (pool->base.dscs[i] == NULL) { @@ -1961,6 +1975,7 @@ static bool dcn316_resource_construct( goto create_fail; } } +#endif /* DWB and MMHUBBUB */ if (!dcn31_dwbc_create(ctx, &pool->base)) { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c index a124ad9bd108c..8695579c4a702 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c @@ -437,6 +437,7 @@ static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { #define dsc_regsDCN20_init(id)\ DSC_REG_LIST_DCN20_RI(id) +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static struct dcn20_dsc_registers dsc_regs[4]; static const struct dcn20_dsc_shift dsc_shift = { @@ -446,6 +447,7 @@ static const struct dcn20_dsc_shift dsc_shift = { static const struct dcn20_dsc_mask dsc_mask = { DSC_REG_LIST_SH_MASK_DCN20(_MASK) }; +#endif static struct dcn30_mpc_registers mpc_regs; @@ -1387,10 +1389,12 @@ static void dcn32_resource_destruct(struct dcn32_resource_pool *pool) } } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } +#endif if (pool->base.mpc != NULL) { kfree(TO_DCN20_MPC(pool->base.mpc)); @@ -1558,6 +1562,7 @@ static bool dcn32_mmhubbub_create(struct dc_context *ctx, struct resource_pool * return true; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static struct display_stream_compressor *dcn32_dsc_create( struct dc_context *ctx, uint32_t inst) { @@ -1582,6 +1587,7 @@ static struct display_stream_compressor *dcn32_dsc_create( return &dsc->base; } +#endif static void dcn32_destroy_resource_pool(struct resource_pool **pool) { @@ -2050,7 +2056,9 @@ static struct resource_funcs dcn32_res_pool_funcs = { .acquire_free_pipe_as_secondary_opp_head = dcn32_acquire_free_pipe_as_secondary_opp_head, .release_pipe = dcn20_release_pipe, .add_stream_to_ctx = dcn30_add_stream_to_ctx, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, +#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, .set_mcif_arb_params = dcn30_set_mcif_arb_params, @@ -2393,6 +2401,7 @@ static bool dcn32_resource_construct( goto create_fail; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* DSCs */ for (i = 0; i < pool->base.res_cap->num_dsc; i++) { pool->base.dscs[i] = dcn32_dsc_create(ctx, i); @@ -2402,6 +2411,7 @@ static bool dcn32_resource_construct( goto create_fail; } } +#endif /* DWB */ if (!dcn32_dwbc_create(ctx, &pool->base)) { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c index f5a4e97c40ced..eb78191838c7c 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c @@ -128,8 +128,10 @@ void dcn32_merge_pipes_for_subvp(struct dc *dc, pipe->stream = NULL; pipe->top_pipe = NULL; pipe->prev_odm_pipe = NULL; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (pipe->stream_res.dsc) dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc); +#endif memset(&pipe->plane_res, 0, sizeof(pipe->plane_res)); memset(&pipe->stream_res, 0, sizeof(pipe->stream_res)); } else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) { diff --git a/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c index ad088d70e1893..0e2688067f329 100644 --- a/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c @@ -83,10 +83,12 @@ static void virtual_stream_encoder_reset_hdmi_stream_attribute( struct stream_encoder *enc) {} +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static void virtual_enc_dp_set_odm_combine( struct stream_encoder *enc, bool odm_combine) {} +#endif static void virtual_dig_connect_to_otg( struct stream_encoder *enc, @@ -99,16 +101,20 @@ static void virtual_setup_stereo_sync( bool enable) {} +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static void virtual_stream_encoder_set_dsc_pps_info_packet( struct stream_encoder *enc, bool enable, uint8_t *dsc_packed_pps, bool immediate_update) {} +#endif static const struct stream_encoder_funcs virtual_str_enc_funcs = { +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .dp_set_odm_combine = virtual_enc_dp_set_odm_combine, +#endif .dp_set_stream_attribute = virtual_stream_encoder_dp_set_stream_attribute, .hdmi_set_stream_attribute = @@ -135,7 +141,9 @@ static const struct stream_encoder_funcs virtual_str_enc_funcs = { .hdmi_reset_stream_attribute = virtual_stream_encoder_reset_hdmi_stream_attribute, .dig_connect_to_otg = virtual_dig_connect_to_otg, .setup_stereo_sync = virtual_setup_stereo_sync, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .dp_set_dsc_pps_info_packet = virtual_stream_encoder_set_dsc_pps_info_packet, +#endif }; bool virtual_stream_encoder_construct( From 9b9c9ee1533447ed1d8555c33c52efe7cdd2b3cc Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 28 Jun 2022 11:16:02 +0800 Subject: [PATCH 0701/1868] drm/amdkfd: remove redundant sg_table* argument This is caused by dropping of patch v5.16-1998-g1d11a577d7f0 "drm/amdkfd: Add CMA API" Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 3441585f668d6..b97cad8ef6265 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -2395,7 +2395,7 @@ static int criu_restore_memory_of_gpu_ipc(struct kfd_process_device *pdd, */ ret = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(dev->adev, bo_bucket->addr, bo_bucket->size, pdd->drm_priv, - NULL, kgd_mem, &offset, + kgd_mem, &offset, bo_bucket->alloc_flags, true); if (ret) { pr_err("Could not create the BO\n"); From 6ac609f382bf4b3c155b796b2704ce37b2fd2f33 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Mon, 7 Mar 2022 16:42:59 +0800 Subject: [PATCH 0702/1868] Revert "drm/amdkfd: add reset lock protection for kfd entry functions" This reverts commit f09bc5e4580c1aa0c2d7eb43b762f58dbd239423. Signed-off-by: Ma Jun Change-Id: I7e7c136bb9831224bb0fc749f2f109b6f9e8d976 --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 4 ++-- drivers/gpu/drm/amd/amdkfd/kfd_ipc.c | 14 -------------- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 1 - 3 files changed, 2 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index b97cad8ef6265..40b5bfdfb46a9 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1250,7 +1250,7 @@ static int kfd_ioctl_free_memory_of_gpu(struct file *filep, GET_IDR_HANDLE(args->handle)); if (!buf_obj) { ret = -EINVAL; - goto err_unlock; + goto err_pdd; } ret = amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, @@ -1354,6 +1354,7 @@ static int kfd_ioctl_map_memory_to_gpu(struct file *filep, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), ((struct kgd_mem *)mem)->domain); + goto map_memory_to_gpu_failed; } args->n_success = i+1; @@ -1482,7 +1483,6 @@ static int kfd_ioctl_unmap_memory_from_gpu(struct file *filep, mutex_unlock(&p->mutex); kfree(devices_arr); - return 0; bind_process_to_device_failed: diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c index 6021077f7199b..9cb5155809752 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c @@ -193,18 +193,11 @@ int kfd_ipc_import_dmabuf(struct kfd_dev *dev, return -EINVAL; mutex_lock(&p->mutex); - r = amdgpu_read_lock(dev->ddev, true); - if (r) - goto err_unlock; r = kfd_import_dmabuf_create_kfd_bo(dev, p, gpu_id, dmabuf, NULL, va_addr, handle, mmap_offset, false); - amdgpu_read_unlock(dev->ddev); - -err_unlock: mutex_unlock(&p->mutex); - dma_buf_put(dmabuf); return r; } @@ -238,9 +231,6 @@ int kfd_ipc_import_handle(struct kfd_dev *dev, struct kfd_process *p, if (!restore) { mutex_lock(&p->mutex); - r = amdgpu_read_lock(dev->ddev, true); - if (r) - goto err_unlock; } r = kfd_import_dmabuf_create_kfd_bo(dev, p, gpu_id, @@ -248,7 +238,6 @@ int kfd_ipc_import_handle(struct kfd_dev *dev, struct kfd_process *p, va_addr, handle, mmap_offset, restore); if (!restore) { - amdgpu_read_unlock(dev->ddev); mutex_unlock(&p->mutex); } if (r) @@ -259,9 +248,6 @@ int kfd_ipc_import_handle(struct kfd_dev *dev, struct kfd_process *p, return r; -err_unlock: - mutex_unlock(&p->mutex); - error_unref: kfd_ipc_obj_put(&found); return r; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 75d468e2d97c4..7e51dbc01b2e4 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -975,7 +975,6 @@ static void kfd_process_device_free_bos(struct kfd_process_device *pdd) peer_pdd->dev->adev, buf_obj->mem, peer_pdd->drm_priv); } - run_rdma_free_callback(buf_obj); amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, buf_obj->mem, pdd->drm_priv, NULL); kfd_process_device_remove_obj_handle(pdd, id); From 37350abd06aa28794c89aeb1b125ca6b18e01a4d Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 28 Jun 2022 17:38:36 +0800 Subject: [PATCH 0703/1868] drm/amdkcl: fake drm_gem_ttm_vmap which the type of second arg is dma_buf_map pointer Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 5 ++- .../include/kcl/kcl_drm_gem_ttm_helper.h | 20 +++++++++- .../drm/amd/backport/kcl_drm_gem_ttm_helper.c | 38 ++++++++++++++++++- drivers/gpu/drm/amd/dkms/config/config.h | 3 ++ .../amd/dkms/m4/drm-driver-gem-open-object.m4 | 21 ++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 6 files changed, 84 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index bb946c9568d7a..3f4556b8fccbc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -363,9 +363,12 @@ static const struct drm_gem_object_funcs amdgpu_gem_object_funcs = { .open = amdgpu_gem_object_open, .close = amdgpu_gem_object_close, .export = amdgpu_gem_prime_export, -#ifdef HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_2ARGS +#ifdef HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_HAS_IOSYS_MAP_ARG .vmap = drm_gem_ttm_vmap, .vunmap = drm_gem_ttm_vunmap, +#elif defined(HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_2ARGS) + .vmap = amdgpu_drm_gem_ttm_vmap, + .vunmap = amdgpu_drm_gem_ttm_vunmap, #else .vmap = amdgpu_gem_prime_vmap, .vunmap = amdgpu_gem_prime_vunmap, diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_gem_ttm_helper.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_gem_ttm_helper.h index ae25af4cbc8c5..aa89982b0c2c7 100644 --- a/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_gem_ttm_helper.h +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_gem_ttm_helper.h @@ -5,10 +5,28 @@ #include #include -#ifndef HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_2ARGS +#if !defined(HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_2ARGS) void amdgpu_gem_prime_vunmap(struct drm_gem_object *gem, void *vaddr); void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj); +#elif !defined(HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_HAS_IOSYS_MAP_ARG) +int _kcl_drm_gem_ttm_vmap(struct drm_gem_object *gem, + struct dma_buf_map *map); +void _kcl_drm_gem_ttm_vunmap(struct drm_gem_object *gem, + struct dma_buf_map *map); +static inline +void amdgpu_drm_gem_ttm_vunmap(struct drm_gem_object *gem, + struct dma_buf_map *map) +{ + _kcl_drm_gem_ttm_vunmap(gem, map); +} + +static inline +int amdgpu_drm_gem_ttm_vmap(struct drm_gem_object *obj, + struct dma_buf_map *map) +{ + return _kcl_drm_gem_ttm_vmap(obj, map); +} #endif #ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK diff --git a/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c b/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c index 2cef03209d156..04b308171928f 100644 --- a/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c +++ b/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #ifndef drm_gem_ttm_of_gem @@ -18,7 +19,7 @@ void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj) { struct ttm_buffer_object *bo = drm_gem_ttm_of_gem(obj); - struct dma_buf_map map; + struct iosys_map map; ttm_bo_vmap(bo, &map); return map.vaddr; @@ -28,11 +29,44 @@ void amdgpu_gem_prime_vunmap(struct drm_gem_object *gem, void *vaddr) { struct ttm_buffer_object *bo = drm_gem_ttm_of_gem(gem); - struct dma_buf_map map; + struct iosys_map map; map.vaddr = vaddr; map.is_iomem = bo->resource->bus.is_iomem; ttm_bo_vunmap(bo, &map); } +#elif !defined(HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_HAS_IOSYS_MAP_ARG) + +int _kcl_drm_gem_ttm_vmap(struct drm_gem_object *gem, + struct dma_buf_map *map) +{ + struct ttm_buffer_object *bo = drm_gem_ttm_of_gem(gem); + struct iosys_map iosys_map; + int r; + + iosys_map.vaddr = map->vaddr; + iosys_map.is_iomem = map->is_iomem; + + r = ttm_bo_vmap(bo, &iosys_map); + + map->vaddr = iosys_map.vaddr; + map->is_iomem = iosys_map.is_iomem; + return r; +} + +void _kcl_drm_gem_ttm_vunmap(struct drm_gem_object *gem, + struct dma_buf_map *map) +{ + struct ttm_buffer_object *bo = drm_gem_ttm_of_gem(gem); + struct iosys_map iosys_map; + + iosys_map.vaddr = map->vaddr; + iosys_map.is_iomem = map->is_iomem; + + ttm_bo_vunmap(bo, &iosys_map); + + map->vaddr = iosys_map.vaddr; + map->is_iomem = iosys_map.is_iomem; +} #endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 6c4aedb8cfc8b..23612516b3ad7 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -542,6 +542,9 @@ /* drm_gem_object_funcs->vmap() has 2 args */ #define HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_2ARGS 1 +/* drm_gem_object_funcs.vmap hsa iosys_map arg */ +#define HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_HAS_IOSYS_MAP_ARG 1 + /* drm_gem_object_lookup() wants 2 args */ #define HAVE_DRM_GEM_OBJECT_LOOKUP_2ARGS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-open-object.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-open-object.m4 index cb583a5e9dafd..6631ba066edcf 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-open-object.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-open-object.m4 @@ -31,3 +31,24 @@ AC_DEFUN([AC_AMDGPU_DRM_DRIVER_GEM_OPEN_OBJECT], [ ]) ]) ]) + + +dnl # +dnl # commit v5.17-rc2-157-g7938f4218168 +dnl # dma-buf-map: Rename to iosys-map +dnl # +AC_DEFUN([AC_AMDGPU_DRM_GEM_OBJECT_FUNCS_VMAP_HAS_IOSYS_MAP_ARG], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_gem_object_funcs *funcs = NULL; + struct iosys_map *map = NULL; + funcs->vmap(NULL, map); + ], [ + AC_DEFINE(HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_HAS_IOSYS_MAP_ARG, 1, + [drm_gem_object_funcs.vmap hsa iosys_map arg]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index e7c40b7506fb4..5a1e58c24c255 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -208,6 +208,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DMA_FENCE_IS_CONTAINER AC_AMDGPU_STR_YES_NO AC_AMDGPU_DMA_FENCE_CHAIN_CONTAINED + AC_AMDGPU_DRM_GEM_OBJECT_FUNCS_VMAP_HAS_IOSYS_MAP_ARG AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 47889e829440b1b0c470303e03f1b0a5b8edea44 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 29 Jun 2022 14:11:03 +0800 Subject: [PATCH 0704/1868] drm/amdkcl: Test whether drm_memcpy_from_wc argument type is struct iosys_map Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 5 ++++- .../gpu/drm/amd/dkms/m4/drm-memcpy-from-wc.m4 | 17 ++++++++++++++--- drivers/gpu/drm/ttm/ttm_bo_util.c | 2 +- 3 files changed, 19 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 23612516b3ad7..812ed631934a4 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -594,7 +594,10 @@ #define HAVE_DRM_KMS_HELPER_IS_POLL_WORKER 1 /* drm_memcpy_from_wc() is availablea */ -#define HAVE_DRM_MEMCPY_FROM_WC 1 +/* #undef HAVE_DRM_MEMCPY_FROM_WC */ + +/* drm_memcpy_from_wc() is availablea and has struct iosys_map* arg */ +#define HAVE_DRM_MEMCPY_FROM_WC_IOSYS_MAP_ARG 1 /* whether drm_mm_insert_mode is available */ #define HAVE_DRM_MM_INSERT_MODE 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-memcpy-from-wc.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-memcpy-from-wc.m4 index 491ada31c112a..8ab4aaf2521dc 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-memcpy-from-wc.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-memcpy-from-wc.m4 @@ -6,11 +6,22 @@ AC_DEFUN([AC_AMDGPU_DRM_MEMCPY_FROM_WC], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ #include + #include ], [ - drm_memcpy_from_wc(NULL, NULL, 0); + struct iosys_map *dst = NULL, *src = NULL; + drm_memcpy_from_wc(dst, src, 0); ], [ - AC_DEFINE(HAVE_DRM_MEMCPY_FROM_WC, 1, - [drm_memcpy_from_wc() is availablea]) + AC_DEFINE(HAVE_DRM_MEMCPY_FROM_WC_IOSYS_MAP_ARG, 1, + [drm_memcpy_from_wc() is availablea and has struct iosys_map* arg]) + ], [ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_memcpy_from_wc(NULL, NULL, 0); + ], [ + AC_DEFINE(HAVE_DRM_MEMCPY_FROM_WC, 1, + [drm_memcpy_from_wc() is availablea]) + ]) ]) ]) ]) diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c index 523d1ead90b48..a4e5e1f06e8f3 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_util.c +++ b/drivers/gpu/drm/ttm/ttm_bo_util.c @@ -113,7 +113,7 @@ void ttm_move_memcpy(bool clear, dst_ops->map_local(dst_iter, &dst_map, i); src_ops->map_local(src_iter, &src_map, i); -#ifdef HAVE_DRM_MEMCPY_FROM_WC +#ifdef HAVE_DRM_MEMCPY_FROM_WC_IOSYS_MAP_ARG drm_memcpy_from_wc(&dst_map, &src_map, PAGE_SIZE); #else if (!src_map.is_iomem && !dst_map.is_iomem) { From 771fafd5203b4184f2ad78cd172f3e5b0e03b511 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 4 Jul 2022 13:54:52 +0800 Subject: [PATCH 0705/1868] drm/amdkfd: using TTM provided vram usage function Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c index 6745d35a98789..71e472d810f64 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c @@ -564,7 +564,7 @@ int amdgpu_amdkfd_get_dmabuf_info(struct amdgpu_device *adev, int dma_buf_fd, uint64_t amdgpu_amdkfd_get_vram_usage(struct amdgpu_device *adev) { - return amdgpu_vram_mgr_usage(&adev->mman.vram_mgr); + return ttm_resource_manager_usage(&adev->mman.vram_mgr.manager); } uint8_t amdgpu_amdkfd_get_xgmi_hops_count(struct amdgpu_device *dst, From 76125ca66da1d2399c7662b3f5b36782b372ce04 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 4 Jul 2022 17:33:14 +0800 Subject: [PATCH 0706/1868] drm/amdkcl: wrap the code under HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN for legacy os Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 6121776ad03ba..6ce10f03e9cbb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2713,7 +2713,9 @@ static int amdgpu_runtime_idle_check_display(struct device *dev) if (adev->mode_info.num_crtc) { struct drm_connector *list_connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif int ret = 0; if (amdgpu_runtime_pm != -2) { @@ -2723,14 +2725,20 @@ static int amdgpu_runtime_idle_check_display(struct device *dev) * the GPU was in suspend. Remove this once that is fixed. */ mutex_lock(&drm_dev->mode_config.mutex); +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(drm_dev, &iter); drm_for_each_connector_iter(list_connector, &iter) { +#else + list_for_each_entry(list_connector, &(drm_dev)->mode_config.connector_list, head) { +#endif if (list_connector->status == connector_status_connected) { ret = -EBUSY; break; } } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif mutex_unlock(&drm_dev->mode_config.mutex); if (ret) @@ -2752,15 +2760,21 @@ static int amdgpu_runtime_idle_check_display(struct device *dev) mutex_lock(&drm_dev->mode_config.mutex); drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(drm_dev, &iter); drm_for_each_connector_iter(list_connector, &iter) { +#else + list_for_each_entry(list_connector, &(drm_dev)->mode_config.connector_list, head) { +#endif if (list_connector->dpms == DRM_MODE_DPMS_ON) { ret = -EBUSY; break; } } +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); mutex_unlock(&drm_dev->mode_config.mutex); From 0f9a47fb708ed369d65b1e6932e16ec123d1de20 Mon Sep 17 00:00:00 2001 From: Alex Sierra Date: Fri, 20 Aug 2021 12:53:14 -0500 Subject: [PATCH 0707/1868] drm/amdkfd: ref count init for device pages Ref counter from device pages is init to zero during memmap init zone. The first time a new device page is allocated to migrate data into it, its ref counter needs to be initialized to one. Signed-off-by: Alex Sierra Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c index f409e1aba1c57..185e6ae36d682 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@ -221,7 +221,13 @@ svm_migrate_get_vram_page(struct svm_range *prange, unsigned long pfn) page = pfn_to_page(pfn); svm_range_bo_ref(prange->svm_bo); page->zone_device_data = prange->svm_bo; - zone_device_page_init(page); +#ifdef HAVE_ZONE_DEVICE_PUBLIC + VM_BUG_ON_PAGE(page_ref_count(page), page); + init_page_count(page); +#else + get_page(page); +#endif + lock_page(page); } static void From 59271326727e84a47b9b8ad4e1a5cf4ffe5898ac Mon Sep 17 00:00:00 2001 From: George Cave Date: Tue, 5 Jul 2022 17:56:04 -0400 Subject: [PATCH 0708/1868] drm/amdkcl: Add directory to included header path As of RedHat 9.1, building the DKMS module fails due to it being unable to find a stdarg.h header. This file is available in a directory that is not included via the compiler, but can be by adding the subdirectory it resides in at the include point. Signed-off-by: George Cave Reviewed-by: Flora Cui flora.cui@amd.com --- drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c index 907a902c5f204..9e0c95502367c 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c @@ -24,7 +24,7 @@ */ #include #include -#include +#include #if !defined(HAVE_DRM_DRM_PRINT_H) void drm_printf(struct drm_printer *p, const char *f, ...) From 293e4be90897d2917e300175468c2c8a5ed63b6d Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Thu, 23 Apr 2020 02:10:31 -0400 Subject: [PATCH 0709/1868] drm/amdkfd: Add CMA API This is similar to Cross Memory Attach, except that it uses SDMA to copy data between processes, and can access GPU memory that's not CPU accessible. Signed-off-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 7 +- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 86 +- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 841 +++++++++++++++++- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 32 + drivers/gpu/drm/amd/amdkfd/kfd_process.c | 2 +- include/uapi/linux/kfd_ioctl.h | 35 + 6 files changed, 998 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index 85c7e4ed46d2f..6dcec35258c50 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -174,6 +174,11 @@ int amdgpu_amdkfd_submit_ib(struct amdgpu_device *adev, void amdgpu_amdkfd_set_compute_idle(struct amdgpu_device *adev, bool idle); bool amdgpu_amdkfd_have_atomics_support(struct amdgpu_device *adev); +int amdgpu_amdkfd_copy_mem_to_mem(struct kgd_dev *kgd, struct kgd_mem *src_mem, + uint64_t src_offset, struct kgd_mem *dst_mem, + uint64_t dest_offset, uint64_t size, struct dma_fence **f, + uint64_t *actual_size); + bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid); int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev, @@ -312,7 +317,7 @@ size_t amdgpu_amdkfd_get_available_memory(struct amdgpu_device *adev, uint8_t xcp_id); int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( struct amdgpu_device *adev, uint64_t va, uint64_t size, - void *drm_priv, struct kgd_mem **mem, + void *drm_priv, struct sg_table *sg, struct kgd_mem **mem, uint64_t *offset, uint32_t flags, bool criu_resume); int amdgpu_amdkfd_gpuvm_free_memory_of_gpu( struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 6294b3d62233d..c1da17e3c83bf 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -1800,13 +1800,12 @@ size_t amdgpu_amdkfd_get_available_memory(struct amdgpu_device *adev, int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( struct amdgpu_device *adev, uint64_t va, uint64_t size, - void *drm_priv, struct kgd_mem **mem, + void *drm_priv, struct sg_table *sg, struct kgd_mem **mem, uint64_t *offset, uint32_t flags, bool criu_resume) { struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv); struct amdgpu_fpriv *fpriv = container_of(avm, struct amdgpu_fpriv, vm); enum ttm_bo_type bo_type = ttm_bo_type_device; - struct sg_table *sg = NULL; uint64_t user_addr = 0; struct amdgpu_bo *bo; struct drm_gem_object *gobj = NULL; @@ -1869,6 +1868,10 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( if (flags & KFD_IOC_ALLOC_MEM_FLAGS_UNCACHED) alloc_flags |= AMDGPU_GEM_CREATE_UNCACHED; + if (sg) { + alloc_domain = AMDGPU_GEM_DOMAIN_CPU; + bo_type = ttm_bo_type_sg; + } *mem = kzalloc(sizeof(struct kgd_mem), GFP_KERNEL); if (!*mem) { ret = -ENOMEM; @@ -3568,6 +3571,85 @@ int amdgpu_amdkfd_remove_gws_from_process(void *info, void *mem) return 0; } +int amdgpu_amdkfd_copy_mem_to_mem(struct kgd_dev *kgd, struct kgd_mem *src_mem, + uint64_t src_offset, struct kgd_mem *dst_mem, + uint64_t dst_offset, uint64_t size, + struct dma_fence **f, uint64_t *actual_size) +{ + struct amdgpu_device *adev = NULL; + struct amdgpu_copy_mem src, dst; + struct ww_acquire_ctx ticket; + struct list_head list, duplicates; + struct ttm_validate_buffer resv_list[2]; + struct dma_fence *fence = NULL; + int i, r; + + if (!kgd || !src_mem || !dst_mem || !actual_size) + return -EINVAL; + + *actual_size = 0; + + adev = get_amdgpu_device(kgd); + INIT_LIST_HEAD(&list); + INIT_LIST_HEAD(&duplicates); + + src.bo = &src_mem->bo->tbo; + dst.bo = &dst_mem->bo->tbo; + src.mem = &src.bo->mem; + dst.mem = &dst.bo->mem; + src.offset = src_offset; + dst.offset = dst_offset; + + resv_list[0].bo = src.bo; + resv_list[1].bo = dst.bo; + + for (i = 0; i < 2; i++) { + resv_list[i].num_shared = 1; + list_add_tail(&resv_list[i].head, &list); + } + + r = ttm_eu_reserve_buffers(&ticket, &list, false, &duplicates); + if (r) { + pr_err("Copy buffer failed. Unable to reserve bo (%d)\n", r); + return r; + } + + /* The process to which the Source and Dest BOs belong to could be + * evicted and the BOs invalidated. So validate BOs before use + */ + r = amdgpu_amdkfd_bo_validate(src_mem->bo, src_mem->domain, false); + if (r) { + pr_err("CMA fail: SRC BO validate failed %d\n", r); + goto validate_fail; + } + + + r = amdgpu_amdkfd_bo_validate(dst_mem->bo, dst_mem->domain, false); + if (r) { + pr_err("CMA fail: DST BO validate failed %d\n", r); + goto validate_fail; + } + + + r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst, size, false, NULL, + &fence); + if (r) + pr_err("Copy buffer failed %d\n", r); + else + *actual_size = size; + if (fence) { + amdgpu_bo_fence(src_mem->bo, fence, true); + amdgpu_bo_fence(dst_mem->bo, fence, true); + } + if (f) + *f = dma_fence_get(fence); + dma_fence_put(fence); + +validate_fail: + ttm_eu_backoff_reservation(&ticket, &list); + return r; +} + /* Returns GPU-specific tiling mode information */ int amdgpu_amdkfd_get_tile_config(struct amdgpu_device *adev, struct tile_config *config) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 40b5bfdfb46a9..69f55f3993f4a 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1168,7 +1168,7 @@ static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep, err = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( dev->adev, args->va_addr, args->size, - pdd->drm_priv, (struct kgd_mem **) &mem, &offset, + pdd->drm_priv, NULL, (struct kgd_mem **) &mem, &offset, flags, false); if (err) @@ -1687,6 +1687,843 @@ static int kfd_ioctl_ipc_import_handle(struct file *filep, return r; } +/* Maximum number of entries for process pages array which lives on stack */ +#define MAX_PP_STACK_COUNT 16 +/* Maximum number of pages kmalloc'd to hold struct page's during copy */ +#define MAX_KMALLOC_PAGES (PAGE_SIZE * 2) +#define MAX_PP_KMALLOC_COUNT (MAX_KMALLOC_PAGES/sizeof(struct page *)) + +static void kfd_put_sg_table(struct sg_table *sg) +{ + unsigned int i; + struct scatterlist *s; + + for_each_sg(sg->sgl, s, sg->nents, i) + put_page(sg_page(s)); +} + + +/* Create a sg table for the given userptr BO by pinning its system pages + * @bo: userptr BO + * @offset: Offset into BO + * @mm/@task: mm_struct & task_struct of the process that holds the BO + * @size: in/out: desired size / actual size which could be smaller + * @sg_size: out: Size of sg table. This is ALIGN_UP(@size) + * @ret_sg: out sg table + */ +static int kfd_create_sg_table_from_userptr_bo(struct kfd_bo *bo, + int64_t offset, int cma_write, + struct mm_struct *mm, + struct task_struct *task, + uint64_t *size, + uint64_t *sg_size, + struct sg_table **ret_sg) +{ + int ret, locked = 1; + struct sg_table *sg = NULL; + unsigned int i, offset_in_page, flags = 0; + unsigned long nents, n; + unsigned long pa = (bo->cpuva + offset) & PAGE_MASK; + unsigned int cur_page = 0; + struct scatterlist *s; + uint64_t sz = *size; + struct page **process_pages; + + *sg_size = 0; + sg = kmalloc(sizeof(*sg), GFP_KERNEL); + if (!sg) + return -ENOMEM; + + offset_in_page = offset & (PAGE_SIZE - 1); + nents = (sz + offset_in_page + PAGE_SIZE - 1) / PAGE_SIZE; + + ret = sg_alloc_table(sg, nents, GFP_KERNEL); + if (unlikely(ret)) { + ret = -ENOMEM; + goto sg_alloc_fail; + } + process_pages = kmalloc_array(nents, sizeof(struct pages *), + GFP_KERNEL); + if (!process_pages) { + ret = -ENOMEM; + goto page_alloc_fail; + } + + if (cma_write) + flags = FOLL_WRITE; + locked = 1; + mmap_read_lock(mm); + n = get_user_pages_remote(mm, pa, nents, flags, process_pages, + NULL, &locked); + if (locked) + mmap_read_unlock(mm); + if (n <= 0) { + pr_err("CMA: Invalid virtual address 0x%lx\n", pa); + ret = -EFAULT; + goto get_user_fail; + } + if (n != nents) { + /* Pages pinned < requested. Set the size accordingly */ + *size = (n * PAGE_SIZE) - offset_in_page; + pr_debug("Requested %lx but pinned %lx\n", nents, n); + } + + sz = 0; + for_each_sg(sg->sgl, s, n, i) { + sg_set_page(s, process_pages[cur_page], PAGE_SIZE, + offset_in_page); + sg_dma_address(s) = page_to_phys(process_pages[cur_page]); + offset_in_page = 0; + cur_page++; + sz += PAGE_SIZE; + } + *ret_sg = sg; + *sg_size = sz; + + kfree(process_pages); + return 0; + +get_user_fail: + kfree(process_pages); +page_alloc_fail: + sg_free_table(sg); +sg_alloc_fail: + kfree(sg); + return ret; +} + +static void kfd_free_cma_bos(struct cma_iter *ci) +{ + struct cma_system_bo *cma_bo, *tmp; + + list_for_each_entry_safe(cma_bo, tmp, &ci->cma_list, list) { + struct kfd_dev *dev = cma_bo->dev; + + /* sg table is deleted by free_memory_of_gpu */ + if (cma_bo->sg) + kfd_put_sg_table(cma_bo->sg); + amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->kgd, cma_bo->mem, NULL); + list_del(&cma_bo->list); + kfree(cma_bo); + } +} + +/* 1 second timeout */ +#define CMA_WAIT_TIMEOUT msecs_to_jiffies(1000) + +static int kfd_cma_fence_wait(struct dma_fence *f) +{ + int ret; + + ret = dma_fence_wait_timeout(f, false, CMA_WAIT_TIMEOUT); + if (likely(ret > 0)) + return 0; + if (!ret) + ret = -ETIME; + return ret; +} + +/* Put previous (old) fence @pf but it waits for @pf to signal if the context + * of the current fence @cf is different. + */ +static int kfd_fence_put_wait_if_diff_context(struct dma_fence *cf, + struct dma_fence *pf) +{ + int ret = 0; + + if (pf && cf && cf->context != pf->context) + ret = kfd_cma_fence_wait(pf); + dma_fence_put(pf); + return ret; +} + +#define MAX_SYSTEM_BO_SIZE (512*PAGE_SIZE) + +/* Create an equivalent system BO for the given @bo. If @bo is a userptr then + * create a new system BO by pinning underlying system pages of the given + * userptr BO. If @bo is in Local Memory then create an empty system BO and + * then copy @bo into this new BO. + * @bo: Userptr BO or Local Memory BO + * @offset: Offset into bo + * @size: in/out: The size of the new BO could be less than requested if all + * the pages couldn't be pinned or size > MAX_SYSTEM_BO_SIZE. This would + * be reflected in @size + * @mm/@task: mm/task to which @bo belongs to + * @cma_bo: out: new system BO + */ +static int kfd_create_cma_system_bo(struct kfd_dev *kdev, struct kfd_bo *bo, + uint64_t *size, uint64_t offset, + int cma_write, struct kfd_process *p, + struct mm_struct *mm, + struct task_struct *task, + struct cma_system_bo **cma_bo) +{ + int ret; + struct kfd_process_device *pdd = NULL; + struct cma_system_bo *cbo; + uint64_t bo_size = 0; + struct dma_fence *f; + + uint32_t flags = KFD_IOC_ALLOC_MEM_FLAGS_GTT | KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE | + KFD_IOC_ALLOC_MEM_FLAGS_NO_SUBSTITUTE; + + *cma_bo = NULL; + cbo = kzalloc(sizeof(**cma_bo), GFP_KERNEL); + if (!cbo) + return -ENOMEM; + + INIT_LIST_HEAD(&cbo->list); + if (bo->mem_type == KFD_IOC_ALLOC_MEM_FLAGS_VRAM) + bo_size = min_t(uint64_t, *size, MAX_SYSTEM_BO_SIZE); + else if (bo->cpuva) { + ret = kfd_create_sg_table_from_userptr_bo(bo, offset, + cma_write, mm, task, + size, &bo_size, + &cbo->sg); + if (ret) { + pr_err("CMA: BO create with sg failed %d\n", ret); + goto sg_fail; + } + } else { + WARN_ON(1); + ret = -EINVAL; + goto sg_fail; + } + mutex_lock(&p->mutex); + pdd = kfd_get_process_device_data(kdev, p); + if (!pdd) { + mutex_unlock(&p->mutex); + pr_err("Process device data doesn't exist\n"); + ret = -EINVAL; + goto pdd_fail; + } + + ret = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(kdev->kgd, 0ULL, bo_size, + pdd->drm_priv, cbo->sg, + &cbo->mem, NULL, flags); + mutex_unlock(&p->mutex); + if (ret) { + pr_err("Failed to create shadow system BO %d\n", ret); + goto pdd_fail; + } + + if (bo->mem_type == KFD_IOC_ALLOC_MEM_FLAGS_VRAM) { + ret = amdgpu_amdkfd_copy_mem_to_mem(kdev->kgd, bo->mem, + offset, cbo->mem, 0, + bo_size, &f, size); + if (ret) { + pr_err("CMA: Intermediate copy failed %d\n", ret); + goto copy_fail; + } + + /* Wait for the copy to finish as subsequent copy will be done + * by different device + */ + ret = kfd_cma_fence_wait(f); + dma_fence_put(f); + if (ret) { + pr_err("CMA: Intermediate copy timed out %d\n", ret); + goto copy_fail; + } + } + + cbo->dev = kdev; + *cma_bo = cbo; + + return ret; + +copy_fail: + amdgpu_amdkfd_gpuvm_free_memory_of_gpu(kdev->kgd, bo->mem, NULL); +pdd_fail: + if (cbo->sg) { + kfd_put_sg_table(cbo->sg); + sg_free_table(cbo->sg); + kfree(cbo->sg); + } +sg_fail: + kfree(cbo); + return ret; +} + +/* Update cma_iter.cur_bo with KFD BO that is assocaited with + * cma_iter.array.va_addr + */ +static int kfd_cma_iter_update_bo(struct cma_iter *ci) +{ + struct kfd_memory_range *arr = ci->array; + uint64_t va_end = arr->va_addr + arr->size - 1; + + mutex_lock(&ci->p->mutex); + ci->cur_bo = kfd_process_find_bo_from_interval(ci->p, arr->va_addr, + va_end); + mutex_unlock(&ci->p->mutex); + + if (!ci->cur_bo || va_end > ci->cur_bo->it.last) { + pr_err("CMA failed. Range out of bounds\n"); + return -EFAULT; + } + return 0; +} + +/* Advance iter by @size bytes. */ +static int kfd_cma_iter_advance(struct cma_iter *ci, unsigned long size) +{ + int ret = 0; + + ci->offset += size; + if (WARN_ON(size > ci->total || ci->offset > ci->array->size)) + return -EFAULT; + ci->total -= size; + /* If current range is copied, move to next range if available. */ + if (ci->offset == ci->array->size) { + + /* End of all ranges */ + if (!(--ci->nr_segs)) + return 0; + + ci->array++; + ci->offset = 0; + ret = kfd_cma_iter_update_bo(ci); + if (ret) + return ret; + } + ci->bo_offset = (ci->array->va_addr + ci->offset) - + ci->cur_bo->it.start; + return ret; +} + +static int kfd_cma_iter_init(struct kfd_memory_range *arr, unsigned long segs, + struct kfd_process *p, struct mm_struct *mm, + struct task_struct *task, struct cma_iter *ci) +{ + int ret; + int nr; + + if (!arr || !segs) + return -EINVAL; + + memset(ci, 0, sizeof(*ci)); + INIT_LIST_HEAD(&ci->cma_list); + ci->array = arr; + ci->nr_segs = segs; + ci->p = p; + ci->offset = 0; + ci->mm = mm; + ci->task = task; + for (nr = 0; nr < segs; nr++) + ci->total += arr[nr].size; + + /* Valid but size is 0. So copied will also be 0 */ + if (!ci->total) + return 0; + + ret = kfd_cma_iter_update_bo(ci); + if (!ret) + ci->bo_offset = arr->va_addr - ci->cur_bo->it.start; + return ret; +} + +static bool kfd_cma_iter_end(struct cma_iter *ci) +{ + if (!(ci->nr_segs) || !(ci->total)) + return true; + return false; +} + +/* Copies @size bytes from si->cur_bo to di->cur_bo BO. The function assumes + * both source and dest. BOs are userptr BOs. Both BOs can either belong to + * current process or one of the BOs can belong to a differnt + * process. @Returns 0 on success, -ve on failure + * + * @si: Source iter + * @di: Dest. iter + * @cma_write: Indicates if it is write to remote or read from remote + * @size: amount of bytes to be copied + * @copied: Return number of bytes actually copied. + */ +static int kfd_copy_userptr_bos(struct cma_iter *si, struct cma_iter *di, + bool cma_write, uint64_t size, + uint64_t *copied) +{ + int i, ret = 0, locked; + unsigned int nents, nl; + unsigned int offset_in_page; + struct page *pp_stack[MAX_PP_STACK_COUNT]; + struct page **process_pages = pp_stack; + unsigned long rva, lva = 0, flags = 0; + uint64_t copy_size, to_copy = size; + struct cma_iter *li, *ri; + + if (cma_write) { + ri = di; + li = si; + flags |= FOLL_WRITE; + } else { + li = di; + ri = si; + } + /* rva: remote virtual address. Page aligned to start page. + * rva + offset_in_page: Points to remote start address + * lva: local virtual address. Points to the start address. + * nents: computes number of remote pages to request + */ + offset_in_page = ri->bo_offset & (PAGE_SIZE - 1); + rva = (ri->cur_bo->cpuva + ri->bo_offset) & PAGE_MASK; + lva = li->cur_bo->cpuva + li->bo_offset; + + nents = (size + offset_in_page + PAGE_SIZE - 1) / PAGE_SIZE; + + copy_size = min_t(uint64_t, size, PAGE_SIZE - offset_in_page); + *copied = 0; + + if (nents > MAX_PP_STACK_COUNT) { + /* For reliability kmalloc only 2 pages worth */ + process_pages = kmalloc(min_t(size_t, MAX_KMALLOC_PAGES, + sizeof(struct pages *)*nents), + GFP_KERNEL); + + if (!process_pages) + return -ENOMEM; + } + + while (nents && to_copy) { + nl = min_t(unsigned int, MAX_PP_KMALLOC_COUNT, nents); + locked = 1; + mmap_read_lock(ri->mm); + nl = get_user_pages_remote(ri->mm, rva, nl, + flags, process_pages, NULL, + &locked); + if (locked) + mmap_read_unlock(ri->mm); + if (nl <= 0) { + pr_err("CMA: Invalid virtual address 0x%lx\n", rva); + ret = -EFAULT; + break; + } + + for (i = 0; i < nl; i++) { + unsigned int n; + void *kaddr = kmap(process_pages[i]); + + if (cma_write) { + n = copy_from_user(kaddr+offset_in_page, + (void *)lva, copy_size); + set_page_dirty(process_pages[i]); + } else { + n = copy_to_user((void *)lva, + kaddr+offset_in_page, + copy_size); + } + kunmap(kaddr); + if (n) { + ret = -EFAULT; + break; + } + to_copy -= copy_size; + if (!to_copy) + break; + lva += copy_size; + rva += (copy_size + offset_in_page); + WARN_ONCE(rva & (PAGE_SIZE - 1), + "CMA: Error in remote VA computation"); + offset_in_page = 0; + copy_size = min_t(uint64_t, to_copy, PAGE_SIZE); + } + + for (i = 0; i < nl; i++) + put_page(process_pages[i]); + + if (ret) + break; + nents -= nl; + } + + if (process_pages != pp_stack) + kfree(process_pages); + + *copied = (size - to_copy); + return ret; + +} + +static int kfd_create_kgd_mem(struct kfd_dev *kdev, uint64_t size, + struct kfd_process *p, struct kgd_mem **mem) +{ + int ret; + struct kfd_process_device *pdd = NULL; + uint32_t flags = KFD_IOC_ALLOC_MEM_FLAGS_GTT | KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE | + KFD_IOC_ALLOC_MEM_FLAGS_NO_SUBSTITUTE; + + if (!mem || !size || !p || !kdev) + return -EINVAL; + + *mem = NULL; + + mutex_lock(&p->mutex); + pdd = kfd_get_process_device_data(kdev, p); + if (!pdd) { + mutex_unlock(&p->mutex); + pr_err("Process device data doesn't exist\n"); + return -EINVAL; + } + + ret = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(kdev->kgd, 0ULL, size, + pdd->drm_priv, NULL, + mem, NULL, flags); + mutex_unlock(&p->mutex); + if (ret) { + pr_err("Failed to create shadow system BO %d\n", ret); + return -EINVAL; + } + + return 0; +} + +static int kfd_destroy_kgd_mem(struct kgd_mem *mem) +{ + if (!mem) + return -EINVAL; + + /* param adev is not used*/ + return amdgpu_amdkfd_gpuvm_free_memory_of_gpu(NULL, mem, NULL); +} + +/* Copies @size bytes from si->cur_bo to di->cur_bo starting at their + * respective offset. + * @si: Source iter + * @di: Dest. iter + * @cma_write: Indicates if it is write to remote or read from remote + * @size: amount of bytes to be copied + * @f: Return the last fence if any + * @copied: Return number of bytes actually copied. + */ +static int kfd_copy_bos(struct cma_iter *si, struct cma_iter *di, + int cma_write, uint64_t size, + struct dma_fence **f, uint64_t *copied, + struct kgd_mem **tmp_mem) +{ + int err = 0; + struct kfd_bo *dst_bo = di->cur_bo, *src_bo = si->cur_bo; + uint64_t src_offset = si->bo_offset, dst_offset = di->bo_offset; + struct kgd_mem *src_mem = src_bo->mem, *dst_mem = dst_bo->mem; + struct kfd_dev *dev = dst_bo->dev; + int d2d = 0; + + *copied = 0; + if (f) + *f = NULL; + if (src_bo->cpuva && dst_bo->cpuva) + return kfd_copy_userptr_bos(si, di, cma_write, size, copied); + + /* If either source or dest. is userptr, create a shadow system BO + * by using the underlying userptr BO pages. Then use this shadow + * BO for copy. src_offset & dst_offset are adjusted because the new BO + * is only created for the window (offset, size) requested. + * The shadow BO is created on the other device. This means if the + * other BO is a device memory, the copy will be using that device. + * The BOs are stored in cma_list for deferred cleanup. This minimizes + * fence waiting just to the last fence. + */ + if (src_bo->cpuva) { + dev = dst_bo->dev; + err = kfd_create_cma_system_bo(dev, src_bo, &size, + si->bo_offset, cma_write, + si->p, si->mm, si->task, + &si->cma_bo); + src_mem = si->cma_bo->mem; + src_offset = si->bo_offset & (PAGE_SIZE - 1); + list_add_tail(&si->cma_bo->list, &si->cma_list); + } else if (dst_bo->cpuva) { + dev = src_bo->dev; + err = kfd_create_cma_system_bo(dev, dst_bo, &size, + di->bo_offset, cma_write, + di->p, di->mm, di->task, + &di->cma_bo); + dst_mem = di->cma_bo->mem; + dst_offset = di->bo_offset & (PAGE_SIZE - 1); + list_add_tail(&di->cma_bo->list, &di->cma_list); + } else if (src_bo->dev->kgd != dst_bo->dev->kgd) { + /* This indicates that atleast on of the BO is in local mem. + * If both are in local mem of different devices then create an + * intermediate System BO and do a double copy + * [VRAM]--gpu1-->[System BO]--gpu2-->[VRAM]. + * If only one BO is in VRAM then use that GPU to do the copy + */ + if (src_bo->mem_type == KFD_IOC_ALLOC_MEM_FLAGS_VRAM && + dst_bo->mem_type == KFD_IOC_ALLOC_MEM_FLAGS_VRAM) { + dev = dst_bo->dev; + size = min_t(uint64_t, size, MAX_SYSTEM_BO_SIZE); + d2d = 1; + + if (*tmp_mem == NULL) { + if (kfd_create_kgd_mem(src_bo->dev, + MAX_SYSTEM_BO_SIZE, + si->p, + tmp_mem)) + return -EINVAL; + } + + if (amdgpu_amdkfd_copy_mem_to_mem(src_bo->dev->kgd, + src_bo->mem, si->bo_offset, + *tmp_mem, 0, + size, f, &size)) + /* tmp_mem will be freed in caller.*/ + return -EINVAL; + + kfd_cma_fence_wait(*f); + dma_fence_put(*f); + + src_mem = *tmp_mem; + src_offset = 0; + } else if (src_bo->mem_type == KFD_IOC_ALLOC_MEM_FLAGS_VRAM) + dev = src_bo->dev; + /* else already set to dst_bo->dev */ + } + + if (err) { + pr_err("Failed to create system BO %d", err); + return -EINVAL; + } + + err = amdgpu_amdkfd_copy_mem_to_mem(dev->kgd, src_mem, src_offset, + dst_mem, dst_offset, size, f, + copied); + /* The tmp_bo allocates additional memory. So it is better to wait and + * delete. Also since multiple GPUs are involved the copies are + * currently not pipelined. + */ + if (*tmp_mem && d2d) { + if (!err) { + kfd_cma_fence_wait(*f); + dma_fence_put(*f); + *f = NULL; + } + } + return err; +} + +/* Copy single range from source iterator @si to destination iterator @di. + * @si will move to next range and @di will move by bytes copied. + * @return : 0 for success or -ve for failure + * @f: The last fence if any + * @copied: out: number of bytes copied + */ +static int kfd_copy_single_range(struct cma_iter *si, struct cma_iter *di, + bool cma_write, struct dma_fence **f, + uint64_t *copied, struct kgd_mem **tmp_mem) +{ + int err = 0; + uint64_t copy_size, n; + uint64_t size = si->array->size; + struct kfd_bo *src_bo = si->cur_bo; + struct dma_fence *lfence = NULL; + + if (!src_bo || !di || !copied) + return -EINVAL; + *copied = 0; + if (f) + *f = NULL; + + while (size && !kfd_cma_iter_end(di)) { + struct dma_fence *fence = NULL; + + copy_size = min(size, (di->array->size - di->offset)); + + err = kfd_copy_bos(si, di, cma_write, copy_size, + &fence, &n, tmp_mem); + if (err) { + pr_err("CMA %d failed\n", err); + break; + } + + if (fence) { + err = kfd_fence_put_wait_if_diff_context(fence, + lfence); + lfence = fence; + if (err) + break; + } + + size -= n; + *copied += n; + err = kfd_cma_iter_advance(si, n); + if (err) + break; + err = kfd_cma_iter_advance(di, n); + if (err) + break; + } + + if (f) + *f = dma_fence_get(lfence); + dma_fence_put(lfence); + + return err; +} + +static int kfd_ioctl_cross_memory_copy(struct file *filep, + struct kfd_process *local_p, void *data) +{ + struct kfd_ioctl_cross_memory_copy_args *args = data; + struct kfd_memory_range *src_array, *dst_array; + struct kfd_process *remote_p; + struct task_struct *remote_task; + struct mm_struct *remote_mm; + struct pid *remote_pid; + struct dma_fence *lfence = NULL; + uint64_t copied = 0, total_copied = 0; + struct cma_iter di, si; + const char *cma_op; + int err = 0; + struct kgd_mem *tmp_mem = NULL; + + /* Check parameters */ + if (args->src_mem_range_array == 0 || args->dst_mem_range_array == 0 || + args->src_mem_array_size == 0 || args->dst_mem_array_size == 0) + return -EINVAL; + args->bytes_copied = 0; + + /* Allocate space for source and destination arrays */ + src_array = kmalloc_array((args->src_mem_array_size + + args->dst_mem_array_size), + sizeof(struct kfd_memory_range), + GFP_KERNEL); + if (!src_array) + return -ENOMEM; + dst_array = &src_array[args->src_mem_array_size]; + + if (copy_from_user(src_array, (void __user *)args->src_mem_range_array, + args->src_mem_array_size * + sizeof(struct kfd_memory_range))) { + err = -EFAULT; + goto copy_from_user_fail; + } + if (copy_from_user(dst_array, (void __user *)args->dst_mem_range_array, + args->dst_mem_array_size * + sizeof(struct kfd_memory_range))) { + err = -EFAULT; + goto copy_from_user_fail; + } + + /* Get remote process */ + remote_pid = find_get_pid(args->pid); + if (!remote_pid) { + pr_err("Cross mem copy failed. Invalid PID %d\n", args->pid); + err = -ESRCH; + goto copy_from_user_fail; + } + + remote_task = get_pid_task(remote_pid, PIDTYPE_PID); + if (!remote_pid) { + pr_err("Cross mem copy failed. Invalid PID or task died %d\n", + args->pid); + err = -ESRCH; + goto get_pid_task_fail; + } + + /* Check access permission */ + remote_mm = mm_access(remote_task, PTRACE_MODE_ATTACH_REALCREDS); + if (!remote_mm || IS_ERR(remote_mm)) { + err = IS_ERR(remote_mm) ? PTR_ERR(remote_mm) : -ESRCH; + if (err == -EACCES) { + pr_err("Cross mem copy failed. Permission error\n"); + err = -EPERM; + } else + pr_err("Cross mem copy failed. Invalid task %d\n", + err); + goto mm_access_fail; + } + + remote_p = kfd_get_process(remote_task); + if (IS_ERR(remote_p)) { + pr_err("Cross mem copy failed. Invalid kfd process %d\n", + args->pid); + err = -EINVAL; + goto kfd_process_fail; + } + /* Initialise cma_iter si & @di with source & destination range. */ + if (KFD_IS_CROSS_MEMORY_WRITE(args->flags)) { + cma_op = "WRITE"; + pr_debug("CMA WRITE: local -> remote\n"); + err = kfd_cma_iter_init(dst_array, args->dst_mem_array_size, + remote_p, remote_mm, remote_task, &di); + if (err) + goto kfd_process_fail; + err = kfd_cma_iter_init(src_array, args->src_mem_array_size, + local_p, current->mm, current, &si); + if (err) + goto kfd_process_fail; + } else { + cma_op = "READ"; + pr_debug("CMA READ: remote -> local\n"); + + err = kfd_cma_iter_init(dst_array, args->dst_mem_array_size, + local_p, current->mm, current, &di); + if (err) + goto kfd_process_fail; + err = kfd_cma_iter_init(src_array, args->src_mem_array_size, + remote_p, remote_mm, remote_task, &si); + if (err) + goto kfd_process_fail; + } + + /* Copy one si range at a time into di. After each call to + * kfd_copy_single_range() si will move to next range. di will be + * incremented by bytes copied + */ + while (!kfd_cma_iter_end(&si) && !kfd_cma_iter_end(&di)) { + struct dma_fence *fence = NULL; + + err = kfd_copy_single_range(&si, &di, + KFD_IS_CROSS_MEMORY_WRITE(args->flags), + &fence, &copied, &tmp_mem); + total_copied += copied; + + if (err) + break; + + /* Release old fence if a later fence is created. If no + * new fence is created, then keep the preivous fence + */ + if (fence) { + err = kfd_fence_put_wait_if_diff_context(fence, + lfence); + lfence = fence; + if (err) + break; + } + } + + /* Wait for the last fence irrespective of error condition */ + if (lfence) { + err = kfd_cma_fence_wait(lfence); + dma_fence_put(lfence); + if (err) + pr_err("CMA %s failed. BO timed out\n", cma_op); + } + + if (tmp_mem) + kfd_destroy_kgd_mem(tmp_mem); + + kfd_free_cma_bos(&si); + kfd_free_cma_bos(&di); + +kfd_process_fail: + mmput(remote_mm); +mm_access_fail: + put_task_struct(remote_task); +get_pid_task_fail: + put_pid(remote_pid); +copy_from_user_fail: + kfree(src_array); + + /* An error could happen after partial copy. In that case this will + * reflect partial amount of bytes copied + */ + args->bytes_copied = total_copied; + return err; +} + static int kfd_ioctl_export_dmabuf(struct file *filep, struct kfd_process *p, void *data) { @@ -3411,6 +4248,8 @@ static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = { AMDKFD_IOCTL_DEF(AMDKFD_IOC_RLC_SPM, kfd_ioctl_rlc_spm, 0), + AMDKFD_IOCTL_DEF(AMDKFD_IOC_CROSS_MEMORY_COPY, + kfd_ioctl_cross_memory_copy, 0), }; static long kfd_ioctl(struct file *filep, unsigned int cmd, unsigned long arg) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index c16abbe5f6314..ff4b1d92b086f 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -402,6 +402,38 @@ struct kfd_bo { unsigned int mem_type; }; +struct cma_system_bo { + struct kgd_mem *mem; + struct sg_table *sg; + struct kfd_dev *dev; + struct list_head list; +}; + +/* Similar to iov_iter */ +struct cma_iter { + /* points to current entry of range array */ + struct kfd_memory_range *array; + /* total number of entries in the initial array */ + unsigned long nr_segs; + /* total amount of data pointed by kfd array*/ + unsigned long total; + /* offset into the entry pointed by cma_iter.array */ + unsigned long offset; + struct kfd_process *p; + struct mm_struct *mm; + struct task_struct *task; + /* current kfd_bo associated with cma_iter.array.va_addr */ + struct kfd_bo *cur_bo; + /* offset w.r.t cur_bo */ + unsigned long bo_offset; + /* If cur_bo is a userptr BO, then a shadow system BO is created + * using its underlying pages. cma_bo holds this BO. cma_list is a + * list cma_bos created in one session + */ + struct cma_system_bo *cma_bo; + struct list_head cma_list; +}; + enum kfd_mempool { KFD_MEMPOOL_SYSTEM_CACHEABLE = 1, KFD_MEMPOOL_SYSTEM_WRITECOMBINE = 2, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 7e51dbc01b2e4..ad7321550c189 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -716,7 +716,7 @@ static int kfd_process_alloc_gpuvm(struct kfd_process_device *pdd, int err; err = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(kdev->adev, gpu_va, size, - pdd->drm_priv, mem, NULL, + pdd->drm_priv, NULL, &mem, NULL, flags, false); if (err) goto err_alloc_mem; diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h index 4522660ee4003..3829644bd060b 100644 --- a/include/uapi/linux/kfd_ioctl.h +++ b/include/uapi/linux/kfd_ioctl.h @@ -754,6 +754,37 @@ struct kfd_ioctl_ipc_import_handle_args { __u32 flags; /* from KFD */ }; +struct kfd_memory_range { + __u64 va_addr; + __u64 size; +}; + +/* flags definitions + * BIT0: 0: read operation, 1: write operation. + * This also identifies if the src or dst array belongs to remote process + */ +#define KFD_CROSS_MEMORY_RW_BIT (1 << 0) +#define KFD_SET_CROSS_MEMORY_READ(flags) (flags &= ~KFD_CROSS_MEMORY_RW_BIT) +#define KFD_SET_CROSS_MEMORY_WRITE(flags) (flags |= KFD_CROSS_MEMORY_RW_BIT) +#define KFD_IS_CROSS_MEMORY_WRITE(flags) (flags & KFD_CROSS_MEMORY_RW_BIT) + +struct kfd_ioctl_cross_memory_copy_args { + /* to KFD: Process ID of the remote process */ + __u32 pid; + /* to KFD: See above definition */ + __u32 flags; + /* to KFD: Source GPU VM range */ + __u64 src_mem_range_array; + /* to KFD: Size of above array */ + __u64 src_mem_array_size; + /* to KFD: Destination GPU VM range */ + __u64 dst_mem_range_array; + /* to KFD: Size of above array */ + __u64 dst_mem_array_size; + /* from KFD: Total amount of bytes copied */ + __u64 bytes_copied; +}; + /* Guarantee host access to memory */ #define KFD_IOCTL_SVM_FLAG_HOST_ACCESS 0x00000001 /* Fine grained coherency between all devices with access */ @@ -1699,7 +1730,11 @@ struct kfd_ioctl_dbg_trap_args { #define AMDKFD_IOC_RLC_SPM \ AMDKFD_IOWR(0x84, struct kfd_ioctl_spm_args) +#define AMDKFD_IOC_CROSS_MEMORY_COPY \ + AMDKFD_IOWR(0x83, struct kfd_ioctl_cross_memory_copy_args) + #define AMDKFD_COMMAND_START_2 0x80 #define AMDKFD_COMMAND_END_2 0x85 + #endif From 2e682ad28704fa13bcb02e4d296f9745cb792575 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 7 Jul 2022 14:08:06 +0800 Subject: [PATCH 0710/1868] drm/amdkcl: fix build error Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 2 +- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 10 ++-- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 50 +++++++++++++------ drivers/gpu/drm/amd/amdkfd/kfd_process.c | 2 +- 4 files changed, 41 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index 6dcec35258c50..a490258eed405 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -174,7 +174,7 @@ int amdgpu_amdkfd_submit_ib(struct amdgpu_device *adev, void amdgpu_amdkfd_set_compute_idle(struct amdgpu_device *adev, bool idle); bool amdgpu_amdkfd_have_atomics_support(struct amdgpu_device *adev); -int amdgpu_amdkfd_copy_mem_to_mem(struct kgd_dev *kgd, struct kgd_mem *src_mem, +int amdgpu_amdkfd_copy_mem_to_mem(struct amdgpu_device *adev, struct kgd_mem *src_mem, uint64_t src_offset, struct kgd_mem *dst_mem, uint64_t dest_offset, uint64_t size, struct dma_fence **f, uint64_t *actual_size); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index c1da17e3c83bf..da90e44b2bf05 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -3571,12 +3571,11 @@ int amdgpu_amdkfd_remove_gws_from_process(void *info, void *mem) return 0; } -int amdgpu_amdkfd_copy_mem_to_mem(struct kgd_dev *kgd, struct kgd_mem *src_mem, +int amdgpu_amdkfd_copy_mem_to_mem(struct amdgpu_device *adev, struct kgd_mem *src_mem, uint64_t src_offset, struct kgd_mem *dst_mem, uint64_t dst_offset, uint64_t size, struct dma_fence **f, uint64_t *actual_size) { - struct amdgpu_device *adev = NULL; struct amdgpu_copy_mem src, dst; struct ww_acquire_ctx ticket; struct list_head list, duplicates; @@ -3584,19 +3583,18 @@ int amdgpu_amdkfd_copy_mem_to_mem(struct kgd_dev *kgd, struct kgd_mem *src_mem, struct dma_fence *fence = NULL; int i, r; - if (!kgd || !src_mem || !dst_mem || !actual_size) + if (!adev|| !src_mem || !dst_mem || !actual_size) return -EINVAL; *actual_size = 0; - adev = get_amdgpu_device(kgd); INIT_LIST_HEAD(&list); INIT_LIST_HEAD(&duplicates); src.bo = &src_mem->bo->tbo; dst.bo = &dst_mem->bo->tbo; - src.mem = &src.bo->mem; - dst.mem = &dst.bo->mem; + src.mem = src.bo->resource; + dst.mem = dst.bo->resource; src.offset = src_offset; dst.offset = dst_offset; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 69f55f3993f4a..38d39a30994ef 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1753,7 +1753,7 @@ static int kfd_create_sg_table_from_userptr_bo(struct kfd_bo *bo, flags = FOLL_WRITE; locked = 1; mmap_read_lock(mm); - n = get_user_pages_remote(mm, pa, nents, flags, process_pages, + n = kcl_get_user_pages_remote(task, mm, pa, nents, flags, process_pages, NULL, &locked); if (locked) mmap_read_unlock(mm); @@ -1798,11 +1798,13 @@ static void kfd_free_cma_bos(struct cma_iter *ci) list_for_each_entry_safe(cma_bo, tmp, &ci->cma_list, list) { struct kfd_dev *dev = cma_bo->dev; + struct kfd_process_device *pdd; /* sg table is deleted by free_memory_of_gpu */ if (cma_bo->sg) kfd_put_sg_table(cma_bo->sg); - amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->kgd, cma_bo->mem, NULL); + pdd = kfd_get_process_device_data(dev, ci->p); + amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->adev, cma_bo->mem, pdd->drm_priv, NULL); list_del(&cma_bo->list); kfree(cma_bo); } @@ -1898,9 +1900,10 @@ static int kfd_create_cma_system_bo(struct kfd_dev *kdev, struct kfd_bo *bo, goto pdd_fail; } - ret = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(kdev->kgd, 0ULL, bo_size, + ret = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(kdev->adev, 0ULL, bo_size, pdd->drm_priv, cbo->sg, - &cbo->mem, NULL, flags); + &cbo->mem, NULL, flags, + false); mutex_unlock(&p->mutex); if (ret) { pr_err("Failed to create shadow system BO %d\n", ret); @@ -1908,7 +1911,7 @@ static int kfd_create_cma_system_bo(struct kfd_dev *kdev, struct kfd_bo *bo, } if (bo->mem_type == KFD_IOC_ALLOC_MEM_FLAGS_VRAM) { - ret = amdgpu_amdkfd_copy_mem_to_mem(kdev->kgd, bo->mem, + ret = amdgpu_amdkfd_copy_mem_to_mem(kdev->adev, bo->mem, offset, cbo->mem, 0, bo_size, &f, size); if (ret) { @@ -1933,7 +1936,7 @@ static int kfd_create_cma_system_bo(struct kfd_dev *kdev, struct kfd_bo *bo, return ret; copy_fail: - amdgpu_amdkfd_gpuvm_free_memory_of_gpu(kdev->kgd, bo->mem, NULL); + amdgpu_amdkfd_gpuvm_free_memory_of_gpu(kdev->adev, bo->mem, pdd->drm_priv, NULL); pdd_fail: if (cbo->sg) { kfd_put_sg_table(cbo->sg); @@ -2090,7 +2093,7 @@ static int kfd_copy_userptr_bos(struct cma_iter *si, struct cma_iter *di, nl = min_t(unsigned int, MAX_PP_KMALLOC_COUNT, nents); locked = 1; mmap_read_lock(ri->mm); - nl = get_user_pages_remote(ri->mm, rva, nl, + nl = kcl_get_user_pages_remote(ri->task, ri->mm, rva, nl, flags, process_pages, NULL, &locked); if (locked) @@ -2167,9 +2170,9 @@ static int kfd_create_kgd_mem(struct kfd_dev *kdev, uint64_t size, return -EINVAL; } - ret = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(kdev->kgd, 0ULL, size, + ret = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(kdev->adev, 0ULL, size, pdd->drm_priv, NULL, - mem, NULL, flags); + mem, NULL, flags, false); mutex_unlock(&p->mutex); if (ret) { pr_err("Failed to create shadow system BO %d\n", ret); @@ -2181,11 +2184,28 @@ static int kfd_create_kgd_mem(struct kfd_dev *kdev, uint64_t size, static int kfd_destroy_kgd_mem(struct kgd_mem *mem) { + struct amdgpu_device *adev; + struct task_struct *task; + struct kfd_process *p; + struct kfd_process_device *pdd; + uint32_t gpu_id, gpu_idx; + int r; + if (!mem) return -EINVAL; + adev = amdgpu_ttm_adev(mem->bo->tbo.bdev); + task = get_pid_task(mem->process_info->pid, PIDTYPE_PID); + p = kfd_get_process(task); + r = kfd_process_gpuid_from_adev(p, adev, &gpu_id, &gpu_idx); + if (r < 0) { + pr_warn("no gpu id found, mem maybe leaking\n"); + return -EINVAL; + } + pdd = kfd_process_device_from_gpuidx(p, gpu_idx); + /* param adev is not used*/ - return amdgpu_amdkfd_gpuvm_free_memory_of_gpu(NULL, mem, NULL); + return amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, mem, pdd->drm_priv, NULL); } /* Copies @size bytes from si->cur_bo to di->cur_bo starting at their @@ -2242,7 +2262,7 @@ static int kfd_copy_bos(struct cma_iter *si, struct cma_iter *di, dst_mem = di->cma_bo->mem; dst_offset = di->bo_offset & (PAGE_SIZE - 1); list_add_tail(&di->cma_bo->list, &di->cma_list); - } else if (src_bo->dev->kgd != dst_bo->dev->kgd) { + } else if (src_bo->dev->adev != dst_bo->dev->adev) { /* This indicates that atleast on of the BO is in local mem. * If both are in local mem of different devices then create an * intermediate System BO and do a double copy @@ -2263,7 +2283,7 @@ static int kfd_copy_bos(struct cma_iter *si, struct cma_iter *di, return -EINVAL; } - if (amdgpu_amdkfd_copy_mem_to_mem(src_bo->dev->kgd, + if (amdgpu_amdkfd_copy_mem_to_mem(src_bo->dev->adev, src_bo->mem, si->bo_offset, *tmp_mem, 0, size, f, &size)) @@ -2285,7 +2305,7 @@ static int kfd_copy_bos(struct cma_iter *si, struct cma_iter *di, return -EINVAL; } - err = amdgpu_amdkfd_copy_mem_to_mem(dev->kgd, src_mem, src_offset, + err = amdgpu_amdkfd_copy_mem_to_mem(dev->adev, src_mem, src_offset, dst_mem, dst_offset, size, f, copied); /* The tmp_bo allocates additional memory. So it is better to wait and @@ -3232,7 +3252,7 @@ static int criu_restore_memory_of_gpu_ipc(struct kfd_process_device *pdd, */ ret = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(dev->adev, bo_bucket->addr, bo_bucket->size, pdd->drm_priv, - kgd_mem, &offset, + NULL, kgd_mem, &offset, bo_bucket->alloc_flags, true); if (ret) { pr_err("Could not create the BO\n"); @@ -3326,7 +3346,7 @@ static int criu_restore_memory_of_gpu(struct kfd_process_device *pdd, } /* Create the BO */ ret = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(pdd->dev->adev, bo_bucket->addr, - bo_bucket->size, pdd->drm_priv, kgd_mem, + bo_bucket->size, pdd->drm_priv, NULL, kgd_mem, &offset, bo_bucket->alloc_flags, criu_resume); if (ret) { pr_err("Could not create the BO\n"); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index ad7321550c189..146f3216a0a5b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -716,7 +716,7 @@ static int kfd_process_alloc_gpuvm(struct kfd_process_device *pdd, int err; err = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(kdev->adev, gpu_va, size, - pdd->drm_priv, NULL, &mem, NULL, + pdd->drm_priv, NULL, mem, NULL, flags, false); if (err) goto err_alloc_mem; From 1305ff8e11c4901e57051cb543834737eb5cdb1e Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 12 Jul 2022 16:30:02 +0800 Subject: [PATCH 0711/1868] drm/amdkcl: test for drm/display/drm_dp_helper.h Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 5 ++++- drivers/gpu/drm/amd/dkms/m4/drm-dp-aux-drm-dev.m4 | 6 ++++-- .../dkms/m4/drm-dp-cec-correlation-functions.m4 | 8 ++++++-- .../dkms/m4/drm-dp-link-train-channel-eq-delay.m4 | 6 ++++-- .../m4/drm-dp-link-train-clock-recovery-delay.m4 | 4 +++- .../amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 | 6 ++++-- drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 6 ++++++ include/kcl/header/drm/display/drm_dp_helper.h | 14 ++++++++++++++ include/kcl/kcl_drm_dp_cec.h | 4 +++- include/kcl/kcl_drm_dp_helper.h | 4 +++- 10 files changed, 51 insertions(+), 12 deletions(-) create mode 100644 include/kcl/header/drm/display/drm_dp_helper.h diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 812ed631934a4..1317935af57ad 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -306,6 +306,9 @@ /* drm_dev_unplug() is available */ #define HAVE_DRM_DEV_UNPLUG 1 +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DISPLAY_DRM_DP_HELPER_H 1 + /* display_info->edid_hdmi_rgb444_dc_modes is available */ #define HAVE_DRM_DISPLAY_INFO_EDID_HDMI_RGB444_DC_MODES 1 @@ -340,7 +343,7 @@ #define HAVE_DRM_DP_CEC_REGISTER_CONNECTOR_PP 1 /* Define to 1 if you have the header file. */ -#define HAVE_DRM_DP_DRM_DP_HELPER_H 1 +/* #undef HAVE_DRM_DP_DRM_DP_HELPER_H */ /* Define to 1 if you have the header file. */ #define HAVE_DRM_DP_DRM_DP_MST_HELPER_H 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-aux-drm-dev.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-aux-drm-dev.m4 index 49994828e0873..a20efecd2b022 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-aux-drm-dev.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-aux-drm-dev.m4 @@ -5,11 +5,13 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_AUX_DRM_DEV], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ - #ifdef HAVE_DRM_DP_DRM_DP_HELPER_H + #if defined(HAVE_DRM_DISPLAY_DRM_DP_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_HELPER_H) #include #else #include - #endif + #endif ], [ struct drm_dp_aux dda; dda.drm_dev = NULL; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-cec-correlation-functions.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-cec-correlation-functions.m4 index 141e3a6ff65d0..30cf21b106f4b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-cec-correlation-functions.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-cec-correlation-functions.m4 @@ -5,7 +5,9 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_CEC_CORRELATION_FUNCTIONS], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DP_DRM_DP_HELPER_H + #if defined(HAVE_DRM_DISPLAY_DRM_DP_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_HELPER_H) #include #else #include @@ -19,7 +21,9 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_CEC_CORRELATION_FUNCTIONS], [ [drm_dp_cec* correlation functions are available]) ], [ AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DP_DRM_DP_HELPER_H + #if defined(HAVE_DRM_DISPLAY_DRM_DP_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_HELPER_H) #include #else #include diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 index e6713844783e2..5dc461c4db3df 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 @@ -5,11 +5,13 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_LINK_TRAIN_CHANNEL_EQ_DELAY], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ - #ifdef HAVE_DRM_DP_DRM_DP_HELPER_H + #if defined(HAVE_DRM_DISPLAY_DRM_DP_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_HELPER_H) #include #else #include - #endif + #endif ], [ struct drm_dp_aux *aux = NULL; const u8 dpcd[DP_RECEIVER_CAP_SIZE]; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 index af98096981e77..4d0c1a7e21313 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 @@ -5,7 +5,9 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_LINK_TRAIN_CLOCK_RECOVERY_DELAY], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ - #ifdef HAVE_DRM_DP_DRM_DP_HELPER_H + #if defined(HAVE_DRM_DISPLAY_DRM_DP_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_HELPER_H) #include #else #include diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 index f49bd33a93a19..27b63066be2dc 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 @@ -5,11 +5,13 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_SEND_REAL_EDID_CHECKSUM], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ - #ifdef HAVE_DRM_DP_DRM_DP_HELPER_H + #if defined(HAVE_DRM_DISPLAY_DRM_DP_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_HELPER_H) #include #else #include - #endif + #endif ], [ drm_dp_send_real_edid_checksum(NULL, 0); ], [drm_dp_send_real_edid_checksum], [drivers/gpu/drm/drm_dp_helper.c], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index db107edff41aa..b4a3e320a016d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -62,6 +62,12 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # AC_KERNEL_CHECK_HEADERS([drm/dp/drm_dp_mst_helper.h]) + dnl # + dnl # v5.18-rc2-594-gda68386d9edb + dnl # drm: Rename dp/ to display/ + dnl # + AC_KERNEL_CHECK_HEADERS([drm/display/drm_dp_helper.h]) + dnl # dnl # v5.7-13141-gca5999fde0a1 dnl # mm: introduce include/linux/pgtable.h diff --git a/include/kcl/header/drm/display/drm_dp_helper.h b/include/kcl/header/drm/display/drm_dp_helper.h new file mode 100644 index 0000000000000..83269a83e90ba --- /dev/null +++ b/include/kcl/header/drm/display/drm_dp_helper.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DISPLAY_DRM_DP_HELPER_H_H_ +#define _KCL_HEADER_DISPLAY_DRM_DP_HELPER_H_H_ + +#if defined(HAVE_DRM_DISPLAY_DRM_DP_HELPER_H) +#include_next +#elif defined(HAVE_DRM_DP_DRM_DP_HELPER_H) +#include_next +#else +#include_next +#endif + +#endif + diff --git a/include/kcl/kcl_drm_dp_cec.h b/include/kcl/kcl_drm_dp_cec.h index b810aae53f69a..e76e90cc0fe59 100644 --- a/include/kcl/kcl_drm_dp_cec.h +++ b/include/kcl/kcl_drm_dp_cec.h @@ -8,7 +8,9 @@ #ifndef __KCL_KCL_DRM_DP_CEC_H__ #define __KCL_KCL_DRM_DP_CEC_H__ -#ifdef HAVE_DRM_DP_DRM_DP_HELPER_H +#if defined(HAVE_DRM_DISPLAY_DRM_DP_HELPER_H) +#include +#elif defined(HAVE_DRM_DP_DRM_DP_HELPER_H) #include #else #include diff --git a/include/kcl/kcl_drm_dp_helper.h b/include/kcl/kcl_drm_dp_helper.h index 6168671062032..2d6d15d2bedb8 100644 --- a/include/kcl/kcl_drm_dp_helper.h +++ b/include/kcl/kcl_drm_dp_helper.h @@ -30,7 +30,9 @@ #include #include -#ifdef HAVE_DRM_DP_DRM_DP_HELPER_H +#if defined(HAVE_DRM_DISPLAY_DRM_DP_HELPER_H) +#include +#elif defined(HAVE_DRM_DP_DRM_DP_HELPER_H) #include #else #include From 9a1f3c1eb399c69cba2efb1d7d36041d61561cc2 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 12 Jul 2022 16:34:47 +0800 Subject: [PATCH 0712/1868] drm/amdkcl: test for drm/display/drm_dp_mst_helper.h Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 5 ++++- .../amd/dkms/m4/drm-dp-atomic-find-vcpi-slots.m4 | 8 ++++++-- .../gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 | 12 +++++++----- .../dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 | 4 +++- .../gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 | 4 +++- .../amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 | 4 +++- .../gpu/drm/amd/dkms/m4/drm-dp-mst-detect-port.m4 | 4 +++- .../drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 | 4 +++- .../gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 | 12 +++++++++--- .../amd/dkms/m4/drm-dp-mst-topology-mgr-resume.m4 | 4 +++- .../drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 | 4 +++- drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 | 12 +++++++++--- drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 6 ++++++ .../drm-up-update-payload-part1-start-slot-arg.m4 | 4 +++- .../amd/dkms/m4/drm_dp_mst_topology_mgr_init.m4 | 4 +++- .../kcl/backport/kcl_drm_dp_mst_helper_backport.h | 4 +++- include/kcl/header/drm/display/drm_dp_mst_helper.h | 14 ++++++++++++++ 17 files changed, 85 insertions(+), 24 deletions(-) create mode 100644 include/kcl/header/drm/display/drm_dp_mst_helper.h diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 1317935af57ad..df734680faa29 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -309,6 +309,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_DRM_DISPLAY_DRM_DP_HELPER_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H 1 + /* display_info->edid_hdmi_rgb444_dc_modes is available */ #define HAVE_DRM_DISPLAY_INFO_EDID_HDMI_RGB444_DC_MODES 1 @@ -346,7 +349,7 @@ /* #undef HAVE_DRM_DP_DRM_DP_HELPER_H */ /* Define to 1 if you have the header file. */ -#define HAVE_DRM_DP_DRM_DP_MST_HELPER_H 1 +/* #undef HAVE_DRM_DP_DRM_DP_MST_HELPER_H */ /* drm_dp_link_train_channel_eq_delay() has 2 args */ #define HAVE_DRM_DP_LINK_TRAIN_CHANNEL_EQ_DELAY_2ARGS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-find-vcpi-slots.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-find-vcpi-slots.m4 index 65b49ae69f164..10cfe8e436f12 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-find-vcpi-slots.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-find-vcpi-slots.m4 @@ -5,7 +5,9 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ - #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) #include #else #include @@ -22,7 +24,9 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS], [ dnl # drm/dp_mst: Manually overwrite PBN divider for calculating timeslots dnl # AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) #include #else #include diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 index 8dc9ef9c8dd48..eabc0261dd0be 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 @@ -5,11 +5,13 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_CALC_PBN_MODE], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H - #include - #else - #include - #endif + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) + #include + #else + #include + #endif ], [ drm_dp_calc_pbn_mode(0, 0, 0); ], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 index 1f637c137dad1..42d7b5595403a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 @@ -5,7 +5,9 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_ADD_AFFECTED_DSC_CRTCS], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ - #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) #include #else #include diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 index df6b3450485e0..318f729096712 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 @@ -5,7 +5,9 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_ATOMIC_CHECK], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ - #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) #include #else #include diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 index 65d24257c4d25..806158f1562a8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 @@ -5,7 +5,9 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_ATOMIC_ENABLE_DSC], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ - #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) #include #else #include diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-detect-port.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-detect-port.m4 index 913f4586acf6c..7c01c0479075e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-detect-port.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-detect-port.m4 @@ -5,7 +5,9 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_DETECT_PORT], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) #include #else #include diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 index 4c48b47b4c9bf..522d9e0e4b565 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 @@ -5,7 +5,9 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_DSC_AUX_FOR_PORT], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ - #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) #include #else #include diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 index 5540428fc8b49..683d563cfc7bb 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 @@ -4,7 +4,9 @@ dnl # drm/dp-mst-helper: Remove hotplug callback dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_HOTPLUG], [ AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) #include #else #include @@ -28,7 +30,9 @@ dnl # drm/dp/mst: split connector registration into two parts (v2) dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_REGISTER_CONNECTOR], [ AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) #include #else #include @@ -48,7 +52,9 @@ dnl # drm/dp_mst: Remove drm_dp_mst_topology_cbs.destroy_connector dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_DESTROY_CONNECTOR], [ AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) #include #else #include diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-mgr-resume.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-mgr-resume.m4 index 039132d5081d7..961c150fe148e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-mgr-resume.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-mgr-resume.m4 @@ -5,7 +5,9 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_RESUME], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) #include #else #include diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 index 720e605f38d4f..646dc3b137f68 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 @@ -5,7 +5,9 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) #include #else #include diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 index 5065a8ab6d0d6..611bd25368735 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 @@ -8,7 +8,9 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) #include #else #include @@ -29,7 +31,9 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY], [ dnl # AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) #include #else #include @@ -48,7 +52,9 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY], [ dnl # AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) #include #else #include diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index b4a3e320a016d..ccdc2e200d0a0 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -68,6 +68,12 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # AC_KERNEL_CHECK_HEADERS([drm/display/drm_dp_helper.h]) + dnl # + dnl # v5.18-rc2-594-gda68386d9edb + dnl # drm: Rename dp/ to display/ + dnl # + AC_KERNEL_CHECK_HEADERS([drm/display/drm_dp_mst_helper.h]) + dnl # dnl # v5.7-13141-gca5999fde0a1 dnl # mm: introduce include/linux/pgtable.h diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-up-update-payload-part1-start-slot-arg.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-up-update-payload-part1-start-slot-arg.m4 index 0c25016be1da4..7839b7b00baee 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-up-update-payload-part1-start-slot-arg.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-up-update-payload-part1-start-slot-arg.m4 @@ -5,7 +5,9 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_UPDATE_PAYLOAD_PART1_START_SLOT_ARG], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) #include #else #include diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr_init.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr_init.m4 index ca29f48cb467a..66d1beb0b8a34 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr_init.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr_init.m4 @@ -5,7 +5,9 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_INIT], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) #include #else #include diff --git a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h index 2412859be272a..5623abd34416b 100644 --- a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h +++ b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h @@ -22,7 +22,9 @@ #ifndef _KCL_DRM_DP_MST_HELPER_BACKPORT_H_ #define _KCL_DRM_DP_MST_HELPER_BACKPORT_H_ -#ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H +#if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) +#include +#elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) #include #else #include diff --git a/include/kcl/header/drm/display/drm_dp_mst_helper.h b/include/kcl/header/drm/display/drm_dp_mst_helper.h new file mode 100644 index 0000000000000..35221a4f00645 --- /dev/null +++ b/include/kcl/header/drm/display/drm_dp_mst_helper.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DISPLAY_DRM_DP_MST_HELPER_H_H_ +#define _KCL_HEADER_DISPLAY_DRM_DP_MST_HELPER_H_H_ + +#if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) +#include_next +#elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) +#include_next +#else +#include_next +#endif + +#endif + From 1d769604bc0430eebca203fbab249f4d21b35a00 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 13 Jul 2022 15:06:51 +0800 Subject: [PATCH 0713/1868] drm/amdkcl: test for drm_* headers moved into drm/display directory Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 15 +++++++++++++++ .../dkms/m4/drm-hdcp-update-content-protection.m4 | 4 ++++ drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 6 ++++++ include/kcl/header/drm/display/drm_dsc.h | 12 ++++++++++++ include/kcl/header/drm/display/drm_dsc_helper.h | 10 ++++++++++ include/kcl/header/drm/display/drm_hdcp.h | 11 +++++++++++ include/kcl/header/drm/display/drm_hdcp_helper.h | 10 ++++++++++ include/kcl/header/drm/display/drm_hdmi_helper.h | 10 ++++++++++ include/kcl/kcl_drm_hdcp.h | 2 +- 9 files changed, 79 insertions(+), 1 deletion(-) create mode 100644 include/kcl/header/drm/display/drm_dsc.h create mode 100644 include/kcl/header/drm/display/drm_dsc_helper.h create mode 100644 include/kcl/header/drm/display/drm_hdcp.h create mode 100644 include/kcl/header/drm/display/drm_hdcp_helper.h create mode 100644 include/kcl/header/drm/display/drm_hdmi_helper.h diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index df734680faa29..3432ffad2b246 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -312,6 +312,21 @@ /* Define to 1 if you have the header file. */ #define HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DISPLAY_DRM_DSC_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DISPLAY_DRM_DSC_HELPER_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DISPLAY_DRM_HDCP_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DISPLAY_DRM_HDCP_HELPER_H 1 + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DISPLAY_DRM_HDMI_HELPER_H 1 + /* display_info->edid_hdmi_rgb444_dc_modes is available */ #define HAVE_DRM_DISPLAY_INFO_EDID_HDMI_RGB444_DC_MODES 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-hdcp-update-content-protection.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-hdcp-update-content-protection.m4 index 5b8c871002830..f91f55f90ced8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-hdcp-update-content-protection.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-hdcp-update-content-protection.m4 @@ -5,7 +5,11 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_DRM_DISPLAY_DRM_HDCP_H + #include + #else #include + #endif ], [ drm_hdcp_update_content_protection(NULL, 0); ], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index ccdc2e200d0a0..17fb837a138c4 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -74,6 +74,12 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # AC_KERNEL_CHECK_HEADERS([drm/display/drm_dp_mst_helper.h]) + AC_KERNEL_CHECK_HEADERS([drm/display/drm_dsc.h]) + AC_KERNEL_CHECK_HEADERS([drm/display/drm_dsc_helper.h]) + AC_KERNEL_CHECK_HEADERS([drm/display/drm_hdmi_helper.h]) + AC_KERNEL_CHECK_HEADERS([drm/display/drm_hdcp_helper.h]) + AC_KERNEL_CHECK_HEADERS([drm/display/drm_hdcp.h]) + dnl # dnl # v5.7-13141-gca5999fde0a1 dnl # mm: introduce include/linux/pgtable.h diff --git a/include/kcl/header/drm/display/drm_dsc.h b/include/kcl/header/drm/display/drm_dsc.h new file mode 100644 index 0000000000000..7b4f143d14323 --- /dev/null +++ b/include/kcl/header/drm/display/drm_dsc.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DISPLAY_DRM_DSC_H_H_ +#define _KCL_HEADER_DISPLAY_DRM_DSC_H_H_ + +#if defined(HAVE_DRM_DISPLAY_DRM_DSC_H) +#include_next +#else +#include +#endif + +#endif + diff --git a/include/kcl/header/drm/display/drm_dsc_helper.h b/include/kcl/header/drm/display/drm_dsc_helper.h new file mode 100644 index 0000000000000..162730616ccb2 --- /dev/null +++ b/include/kcl/header/drm/display/drm_dsc_helper.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DISPLAY_DRM_DSC_HELPER_H_H_ +#define _KCL_HEADER_DISPLAY_DRM_DSC_HELPER_H_H_ + +#if defined(HAVE_DRM_DISPLAY_DRM_DSC_HELPER_H) +#include_next +#endif + +#endif + diff --git a/include/kcl/header/drm/display/drm_hdcp.h b/include/kcl/header/drm/display/drm_hdcp.h new file mode 100644 index 0000000000000..a3c3aad2a794d --- /dev/null +++ b/include/kcl/header/drm/display/drm_hdcp.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DRM_DISPLAY_HDCP_H_INCLUDED_H_ +#define _KCL_HEADER_DRM_DISPLAY_HDCP_H_INCLUDED_H_ + +#ifdef HAVE_DRM_DISPLAY_DRM_HDCP_H +#include_next +#else +#include +#endif + +#endif diff --git a/include/kcl/header/drm/display/drm_hdcp_helper.h b/include/kcl/header/drm/display/drm_hdcp_helper.h new file mode 100644 index 0000000000000..047decb7fc695 --- /dev/null +++ b/include/kcl/header/drm/display/drm_hdcp_helper.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DISPLAY_DRM_HDCP_HELPER_H_H_ +#define _KCL_HEADER_DISPLAY_DRM_HDCP_HELPER_H_H_ + +#if defined(HAVE_DRM_DISPLAY_DRM_HDCP_HELPER_H) +#include_next +#endif + +#endif + diff --git a/include/kcl/header/drm/display/drm_hdmi_helper.h b/include/kcl/header/drm/display/drm_hdmi_helper.h new file mode 100644 index 0000000000000..da7492d32e946 --- /dev/null +++ b/include/kcl/header/drm/display/drm_hdmi_helper.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DISPLAY_DRM_HDMI_HELPER_H_H_ +#define _KCL_HEADER_DISPLAY_DRM_HDMI_HELPER_H_H_ + +#if defined(HAVE_DRM_DISPLAY_DRM_HDMI_HELPER_H) +#include_next +#endif + +#endif + diff --git a/include/kcl/kcl_drm_hdcp.h b/include/kcl/kcl_drm_hdcp.h index b3f6318e1f652..76c7823fe6f88 100644 --- a/include/kcl/kcl_drm_hdcp.h +++ b/include/kcl/kcl_drm_hdcp.h @@ -9,7 +9,7 @@ #define AMDKCL_DRM_HDCP_H #ifdef CONFIG_DRM_AMD_DC_HDCP -#include +#include #include /* changed in v4.16-rc7-1717-gb8e47d87be65 From 65d89fdd72f0188d44192c88021d9cab55d3b39a Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 19 Jul 2022 18:12:49 +0800 Subject: [PATCH 0714/1868] drm/amdkcl: fix build error by adding missing arguments Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 146f3216a0a5b..faac3035068c9 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -1638,7 +1638,7 @@ struct kfd_process_device *kfd_create_process_device_data(struct kfd_node *dev, &pdd->proc_ctx_bo, &pdd->proc_ctx_gpu_addr, &pdd->proc_ctx_cpu_ptr, - false); + false, true); if (retval) { dev_err(dev->adev->dev, "failed to allocate process context bo\n"); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c index d1ac315c25125..d5a26737d52a0 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c @@ -269,7 +269,7 @@ static int init_user_queue(struct process_queue_manager *pqm, &(*q)->gang_ctx_bo, &(*q)->gang_ctx_gpu_addr, &(*q)->gang_ctx_cpu_ptr, - false); + false, true); if (retval) { pr_err("failed to allocate gang context bo\n"); goto cleanup; From 47e69f807ec653620a5057e7af06b8f0d17ebb1d Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 21 Jul 2022 14:05:13 +0800 Subject: [PATCH 0715/1868] drm/amdkcl: fix build error of amdkcl_ttm_resvp Signed-off-by: Leslie Shi Signed-off-by: Ma Jun Change-Id: Ifbb5c079dfa13b34b5ae0d893ec243165da74ce8 --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 3 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c | 8 ++++---- drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 2 +- drivers/gpu/drm/ttm/ttm_bo.c | 10 +++++----- drivers/gpu/drm/ttm/ttm_bo_util.c | 2 +- drivers/gpu/drm/ttm/ttm_bo_vm.c | 4 ++-- drivers/gpu/drm/ttm/ttm_resource.c | 4 ++-- 12 files changed, 21 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index da90e44b2bf05..a094de698d275 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -3350,7 +3350,7 @@ int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence __rcu * goto validate_map_fail; } } - dma_resv_for_each_fence(&cursor, bo->tbo.base.resv, + dma_resv_for_each_fence(&cursor, amdkcl_ttm_resvp(&bo->tbo), DMA_RESV_USAGE_KERNEL, fence) { ret = amdgpu_sync_fence(&sync_obj, fence); if (ret) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index 3f4556b8fccbc..513646ec83f67 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -83,7 +83,7 @@ static vm_fault_t amdgpu_gem_fault(struct vm_fault *vmf) return ret; unlock: - dma_resv_unlock(bo->base.resv); + dma_resv_unlock(amdkcl_ttm_resvp(bo)); return ret; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c index c598c3edff7ee..0caf5abfb8ccc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c @@ -1337,8 +1337,7 @@ int amdgpu_mes_ctx_unmap_meta_data(struct amdgpu_device *adev, if (!amdgpu_vm_ready(vm)) goto out_unlock; - r = dma_resv_get_singleton(bo->tbo.base.resv, DMA_RESV_USAGE_BOOKKEEP, - &fence); + r = dma_resv_get_singleton(amdkcl_ttm_resvp(&bo->tbo), DMA_RESV_USAGE_BOOKKEEP, &fence); if (r) goto out_unlock; if (fence) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index bc3127118da6d..4a3aea629d6dd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -660,7 +660,7 @@ int amdgpu_bo_create(struct amdgpu_device *adev, if (unlikely(r)) goto fail_unreserve; - dma_resv_add_fence(bo->tbo.base.resv, fence, + dma_resv_add_fence(amdkcl_ttm_resvp(&bo->tbo), fence, DMA_RESV_USAGE_KERNEL); dma_fence_put(fence); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c index 3b124a2215875..ddeccca905504 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c @@ -378,7 +378,7 @@ static int amdgpu_vkms_prepare_fb(struct drm_plane *plane, return r; } - r = dma_resv_reserve_fences(rbo->tbo.base.resv, 1); + r = dma_resv_reserve_fences(amdkcl_ttm_resvp(&rbo->tbo), 1); if (r) { dev_err(adev->dev, "allocating fence slot failed (%d)\n", r); goto error_unlock; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c index 3895bd7d176a9..01092929f61d6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c @@ -77,7 +77,7 @@ static int amdgpu_vm_cpu_update(struct amdgpu_vm_update_params *p, uint64_t value; long r; - r = dma_resv_wait_timeout(vmbo->bo.tbo.base.resv, DMA_RESV_USAGE_KERNEL, + r = dma_resv_wait_timeout(amdkcl_ttm_resvp(&vmbo->bo.tbo), DMA_RESV_USAGE_KERNEL, true, MAX_SCHEDULE_TIMEOUT); if (r < 0) return r; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c index e39d6e7643bfb..5cf2d5d87c879 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c @@ -482,7 +482,7 @@ int amdgpu_vm_pt_create(struct amdgpu_device *adev, struct amdgpu_vm *vm, bp.xcp_id_plus1 = xcp_id + 1; if (vm->root.bo) - bp.resv = vm->root.bo->tbo.base.resv; + bp.resv = amdkcl_ttm_resvp(&vm->root.bo->tbo); r = amdgpu_bo_create_vm(adev, &bp, vmbo); if (r) @@ -495,7 +495,7 @@ int amdgpu_vm_pt_create(struct amdgpu_device *adev, struct amdgpu_vm *vm, } if (!bp.resv) - WARN_ON(dma_resv_lock(bo->tbo.base.resv, + WARN_ON(dma_resv_lock(amdkcl_ttm_resvp(&bo->tbo), NULL)); resv = bp.resv; memset(&bp, 0, sizeof(bp)); @@ -503,14 +503,14 @@ int amdgpu_vm_pt_create(struct amdgpu_device *adev, struct amdgpu_vm *vm, bp.domain = AMDGPU_GEM_DOMAIN_GTT; bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC; bp.type = ttm_bo_type_kernel; - bp.resv = bo->tbo.base.resv; + bp.resv = amdkcl_ttm_resvp(&bo->tbo); bp.bo_ptr_size = sizeof(struct amdgpu_bo); bp.xcp_id_plus1 = xcp_id + 1; r = amdgpu_bo_create(adev, &bp, &(*vmbo)->shadow); if (!resv) - dma_resv_unlock(bo->tbo.base.resv); + dma_resv_unlock(amdkcl_ttm_resvp(&bo->tbo)); if (r) { amdgpu_bo_unref(&bo); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c index 229da4a0283d0..47e128c728ff8 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c @@ -607,7 +607,7 @@ svm_range_vram_node_new(struct kfd_node *node, struct svm_range *prange, } } - r = dma_resv_reserve_fences(bo->tbo.base.resv, 1); + r = dma_resv_reserve_fences(amdkcl_ttm_resvp(&bo->tbo), 1); if (r) { pr_debug("failed %d to reserve bo\n", r); amdgpu_bo_unreserve(bo); diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index d8defca9f3419..54098ab269e35 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -148,7 +148,7 @@ static int ttm_bo_handle_move_mem(struct ttm_buffer_object *bo, } } - ret = dma_resv_reserve_fences(bo->base.resv, 1); + ret = dma_resv_reserve_fences(amdkcl_ttm_resvp(bo), 1); if (ret) goto out_err; @@ -623,7 +623,7 @@ int ttm_mem_evict_first(struct ttm_device *bdev, break; } if (locked) - dma_resv_unlock(res->bo->base.resv); + dma_resv_unlock(amdkcl_ttm_resvp(res->bo)); } if (!bo) { @@ -664,7 +664,7 @@ int ttm_mem_evict_first(struct ttm_device *bdev, */ void ttm_bo_pin(struct ttm_buffer_object *bo) { - dma_resv_assert_held(bo->base.resv); + dma_resv_assert_held(amdkcl_ttm_resvp(bo)); WARN_ON_ONCE(!kref_read(&bo->kref)); spin_lock(&bo->bdev->lru_lock); if (bo->resource) @@ -682,7 +682,7 @@ EXPORT_SYMBOL(ttm_bo_pin); */ void ttm_bo_unpin(struct ttm_buffer_object *bo) { - dma_resv_assert_held(bo->base.resv); + dma_resv_assert_held(amdkcl_ttm_resvp(bo)); WARN_ON_ONCE(!kref_read(&bo->kref)); if (WARN_ON_ONCE(!bo->pin_count)) return; @@ -721,7 +721,7 @@ static int ttm_bo_add_move_fence(struct ttm_buffer_object *bo, dma_resv_add_fence(amdkcl_ttm_resvp(bo), fence, DMA_RESV_USAGE_KERNEL); - ret = dma_resv_reserve_fences(bo->base.resv, 1); + ret = dma_resv_reserve_fences(amdkcl_ttm_resvp(bo), 1); dma_fence_put(fence); return ret; } diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c index a4e5e1f06e8f3..f31d9c65609ef 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_util.c +++ b/drivers/gpu/drm/ttm/ttm_bo_util.c @@ -281,7 +281,7 @@ static int ttm_buffer_object_transfer(struct ttm_buffer_object *bo, fbo->base.bulk_move = NULL; } - ret = dma_resv_reserve_fences(&fbo->base.base._resv, 1); + ret = dma_resv_reserve_fences(&amdkcl_ttm_resv(&fbo->base), 1); if (ret) { kfree(fbo); return ret; diff --git a/drivers/gpu/drm/ttm/ttm_bo_vm.c b/drivers/gpu/drm/ttm/ttm_bo_vm.c index b5339205bdc9f..98d61fd7d6ddd 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_vm.c +++ b/drivers/gpu/drm/ttm/ttm_bo_vm.c @@ -50,7 +50,7 @@ static vm_fault_t ttm_bo_vm_fault_idle(struct ttm_buffer_object *bo, /* * Quick non-stalling check for idle. */ - if (dma_resv_test_signaled(bo->base.resv, DMA_RESV_USAGE_KERNEL)) + if (dma_resv_test_signaled(amdkcl_ttm_resvp(bo), DMA_RESV_USAGE_KERNEL)) return 0; /* @@ -75,7 +75,7 @@ static vm_fault_t ttm_bo_vm_fault_idle(struct ttm_buffer_object *bo, /* * Ordinary wait. */ - err = dma_resv_wait_timeout(bo->base.resv, DMA_RESV_USAGE_KERNEL, true, + err = dma_resv_wait_timeout(amdkcl_ttm_resvp(bo), DMA_RESV_USAGE_KERNEL, true, MAX_SCHEDULE_TIMEOUT); if (unlikely(err < 0)) { return (err != -ERESTARTSYS) ? VM_FAULT_SIGBUS : diff --git a/drivers/gpu/drm/ttm/ttm_resource.c b/drivers/gpu/drm/ttm/ttm_resource.c index 4a66b851b67da..1776a006a9cb7 100644 --- a/drivers/gpu/drm/ttm/ttm_resource.c +++ b/drivers/gpu/drm/ttm/ttm_resource.c @@ -66,8 +66,8 @@ void ttm_lru_bulk_move_tail(struct ttm_lru_bulk_move *bulk) continue; lockdep_assert_held(&pos->first->bo->bdev->lru_lock); - dma_resv_assert_held(pos->first->bo->base.resv); - dma_resv_assert_held(pos->last->bo->base.resv); + dma_resv_assert_held(amdkcl_ttm_resvp(pos->first->bo)); + dma_resv_assert_held(amdkcl_ttm_resvp(pos->last->bo)); man = ttm_manager_type(pos->first->bo->bdev, i); list_bulk_move_tail(&man->lru[j], &pos->first->lru, From b777b0780132a40c59e4dac9a1506140eb8b3ad6 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 21 Jul 2022 14:13:33 +0800 Subject: [PATCH 0716/1868] drm/amdkcl: wrap the code under HAVE_KTIME_IS_UNION for legacy os Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c index c7df7fa3459f1..fd5c979d54479 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.c @@ -102,8 +102,13 @@ void amdgpu_show_fdinfo(struct drm_printer *p, struct drm_file *file) drm_printf(p, "drm-shared-cpu:\t%llu KiB\n", stats.cpu_shared/1024UL); for (hw_ip = 0; hw_ip < AMDGPU_HW_IP_NUM; ++hw_ip) { +#ifdef HAVE_KTIME_IS_UNION + if (!usage[hw_ip].tv64) + continue; +#else if (!usage[hw_ip]) continue; +#endif drm_printf(p, "drm-engine-%s:\t%lld ns\n", amdgpu_ip_name[hw_ip], ktime_to_ns(usage[hw_ip])); From 3e1da8e57d3a2a6c9a658175e500286c1c47b8c7 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 21 Jul 2022 14:31:08 +0800 Subject: [PATCH 0717/1868] drm/amdkcl: fix compile error if DEFINE_DEBUGFS_ATTRIBUTE not defined Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index 6a95d38c2ffff..8203a6367982a 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -4074,7 +4074,6 @@ DEFINE_SHOW_ATTRIBUTE(mst_topo); #ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(visual_confirm_fops, visual_confirm_get, visual_confirm_set, "%llu\n"); -#endif /* @@ -4109,6 +4108,7 @@ static int skip_detection_link_training_get(void *data, u64 *val) DEFINE_DEBUGFS_ATTRIBUTE(skip_detection_link_training_fops, skip_detection_link_training_get, skip_detection_link_training_set, "%llu\n"); +#endif /* * Dumps the DCC_EN bit for each pipe. From 51a45c7844b21b1eb1245e5ccefc95f6371b64cf Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 21 Jul 2022 14:46:50 +0800 Subject: [PATCH 0718/1868] drm/amdkcl: include linux/debugfs.h Signed-off-by: Leslie Shi --- drivers/gpu/drm/ttm/ttm_resource.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/ttm/ttm_resource.c b/drivers/gpu/drm/ttm/ttm_resource.c index 1776a006a9cb7..3caa24dcf1c51 100644 --- a/drivers/gpu/drm/ttm/ttm_resource.c +++ b/drivers/gpu/drm/ttm/ttm_resource.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include From a643b1338be11b26bd6ca90851deed0772a2ef2d Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 21 Jul 2022 15:11:01 +0800 Subject: [PATCH 0719/1868] drm/amdkcl: adjust vblank_lock position of struct amdgpu_display_manager Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index d360ef5618df3..96240ddf02fea 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -451,6 +451,13 @@ struct amdgpu_display_manager { */ bool audio_registered; + /** + * @vblank_lock: + * + * Guards access to deferred vblank work state. + */ + spinlock_t vblank_lock; + /** * @irq_handler_list_low_tab: * From aa8cbc790ce7f63c9dc85ca5a7ed21b88ddb1b28 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 13 Jul 2022 16:09:52 +0800 Subject: [PATCH 0720/1868] drm/amdkcl: fake dma_resv api using legacy structure Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c | 841 ++++++++++++++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 7 +- drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 | 20 + drivers/gpu/drm/amd/dkms/pre-build.sh | 8 +- include/kcl/kcl_dma-resv.h | 151 ++++ 5 files changed, 1024 insertions(+), 3 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c b/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c new file mode 100644 index 0000000000000..e3525a0973f71 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c @@ -0,0 +1,841 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright (C) 2012-2014 Canonical Ltd (Maarten Lankhorst) + * + * Based on bo.c which bears the following copyright notice, + * but is dual licensed: + * + * Copyright (c) 2006-2009 VMware, Inc., Palo Alto, CA., USA + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + **************************************************************************/ +/* + * Authors: Thomas Hellstrom + */ +#include +#include +#include +#include +#include +#include +#include + +/* Copied from drivers/dma-buf/dma-resv.c */ +#ifndef HAVE_DMA_RESV_FENCES + +/** + * DOC: Reservation Object Overview + * + * The reservation object provides a mechanism to manage a container of + * dma_fence object associated with a resource. A reservation object + * can have any number of fences attaches to it. Each fence carries an usage + * parameter determining how the operation represented by the fence is using the + * resource. The RCU mechanism is used to protect read access to fences from + * locked write-side updates. + * + * See struct dma_resv for more details. + */ + +extern struct ww_class reservation_ww_class; + +/** + * dma_resv_list_alloc - allocate fence list + * @shared_max: number of fences we need space for + * + * Allocate a new dma_resv_list and make sure to correctly initialize + * shared_max. + */ +static struct dma_resv_list *dma_resv_list_alloc(unsigned int shared_max) +{ + struct dma_resv_list *list; + + list = kmalloc(struct_size(list, shared, shared_max), GFP_KERNEL); + if (!list) + return NULL; + + list->shared_max = (ksize(list) - offsetof(typeof(*list), shared)) / + sizeof(*list->shared); + + return list; +} + +/** + * dma_resv_list_free - free fence list + * @list: list to free + * + * Free a dma_resv_list and make sure to drop all references. + */ +static void dma_resv_list_free(struct dma_resv_list *list) +{ + unsigned int i; + + if (!list) + return; + + for (i = 0; i < list->shared_count; ++i) + dma_fence_put(rcu_dereference_protected(list->shared[i], true)); + + kfree_rcu(list, rcu); +} + +/** + * dma_resv_init - initialize a reservation object + * @obj: the reservation object + */ +void dma_resv_init(struct dma_resv *obj) +{ + ww_mutex_init(&obj->lock, &reservation_ww_class); + seqcount_ww_mutex_init(&obj->seq, &obj->lock); + + RCU_INIT_POINTER(obj->fence, NULL); + RCU_INIT_POINTER(obj->fence_excl, NULL); +} +EXPORT_SYMBOL(dma_resv_init); + +/** + * dma_resv_fini - destroys a reservation object + * @obj: the reservation object + */ +void dma_resv_fini(struct dma_resv *obj) +{ + struct dma_resv_list *fobj; + struct dma_fence *excl; + + /* + * This object should be dead and all references must have + * been released to it, so no need to be protected with rcu. + */ + excl = rcu_dereference_protected(obj->fence_excl, 1); + if (excl) + dma_fence_put(excl); + + fobj = rcu_dereference_protected(obj->fence, 1); + dma_resv_list_free(fobj); + ww_mutex_destroy(&obj->lock); +} +EXPORT_SYMBOL(dma_resv_fini); + +/** + * dma_resv_reserve_fences - Reserve space to add shared fences to + * a dma_resv. + * @obj: reservation object + * @num_fences: number of fences we want to add + * + * Should be called before dma_resv_add_shared_fence(). Must + * be called with @obj locked through dma_resv_lock(). + * + * Note that the preallocated slots need to be re-reserved if @obj is unlocked + * at any time before calling dma_resv_add_shared_fence(). This is validated + * when CONFIG_DEBUG_MUTEXES is enabled. + * + * RETURNS + * Zero for success, or -errno + */ +int dma_resv_reserve_fences(struct dma_resv *obj, unsigned int num_fences) +{ + struct dma_resv_list *old, *new; + unsigned int i, j, k, max; + + dma_resv_assert_held(obj); + + old = dma_resv_shared_list(obj); + if (old && old->shared_max) { + if ((old->shared_count + num_fences) <= old->shared_max) + return 0; + max = max(old->shared_count + num_fences, old->shared_max * 2); + } else { + max = max(4ul, roundup_pow_of_two(num_fences)); + } + + new = dma_resv_list_alloc(max); + if (!new) + return -ENOMEM; + + /* + * no need to bump fence refcounts, rcu_read access + * requires the use of kref_get_unless_zero, and the + * references from the old struct are carried over to + * the new. + */ + for (i = 0, j = 0, k = max; i < (old ? old->shared_count : 0); ++i) { + struct dma_fence *fence; + + fence = rcu_dereference_protected(old->shared[i], + dma_resv_held(obj)); + if (dma_fence_is_signaled(fence)) + RCU_INIT_POINTER(new->shared[--k], fence); + else + RCU_INIT_POINTER(new->shared[j++], fence); + } + new->shared_count = j; + + /* + * We are not changing the effective set of fences here so can + * merely update the pointer to the new array; both existing + * readers and new readers will see exactly the same set of + * active (unsignaled) shared fences. Individual fences and the + * old array are protected by RCU and so will not vanish under + * the gaze of the rcu_read_lock() readers. + */ + rcu_assign_pointer(obj->fence, new); + + if (!old) + return 0; + + /* Drop the references to the signaled fences */ + for (i = k; i < max; ++i) { + struct dma_fence *fence; + + fence = rcu_dereference_protected(new->shared[i], + dma_resv_held(obj)); + dma_fence_put(fence); + } + kfree_rcu(old, rcu); + + return 0; +} +EXPORT_SYMBOL(dma_resv_reserve_fences); + +#ifdef CONFIG_DEBUG_MUTEXES +/** + * dma_resv_reset_max_fences - reset shared fences for debugging + * @obj: the dma_resv object to reset + * + * Reset the number of pre-reserved shared slots to test that drivers do + * correct slot allocation using dma_resv_reserve_fences(). See also + * &dma_resv_list.shared_max. + */ +void dma_resv_reset_max_fences(struct dma_resv *obj) +{ + struct dma_resv_list *fences = dma_resv_shared_list(obj); + + dma_resv_assert_held(obj); + + /* Test shared fence slot reservation */ + if (fences) + fences->shared_max = fences->shared_count; +} +EXPORT_SYMBOL(dma_resv_reset_max_fences); +#endif + +/** + * dma_resv_add_shared_fence - Add a fence to a shared slot + * @obj: the reservation object + * @fence: the shared fence to add + * + * Add a fence to a shared slot, @obj must be locked with dma_resv_lock(), and + * dma_resv_reserve_fences() has been called. + * + * See also &dma_resv.fence for a discussion of the semantics. + */ +static void dma_resv_add_shared_fence(struct dma_resv *obj, + struct dma_fence *fence) +{ + struct dma_resv_list *fobj; + struct dma_fence *old; + unsigned int i, count; + + dma_fence_get(fence); + + dma_resv_assert_held(obj); + + /* Drivers should not add containers here, instead add each fence + * individually. + */ + WARN_ON(dma_fence_is_container(fence)); + + fobj = dma_resv_shared_list(obj); + count = fobj->shared_count; + + write_seqcount_begin(&obj->seq); + + for (i = 0; i < count; ++i) { + + old = rcu_dereference_protected(fobj->shared[i], + dma_resv_held(obj)); + if (old->context == fence->context || + dma_fence_is_signaled(old)) + goto replace; + } + + BUG_ON(fobj->shared_count >= fobj->shared_max); + old = NULL; + count++; + +replace: + RCU_INIT_POINTER(fobj->shared[i], fence); + /* pointer update must be visible before we extend the shared_count */ + smp_store_mb(fobj->shared_count, count); + + write_seqcount_end(&obj->seq); + dma_fence_put(old); +} + +/** + * dma_resv_replace_fences - replace fences in the dma_resv obj + * @obj: the reservation object + * @context: the context of the fences to replace + * @replacement: the new fence to use instead + * @usage: how the new fence is used, see enum dma_resv_usage + * + * Replace fences with a specified context with a new fence. Only valid if the + * operation represented by the original fence has no longer access to the + * resources represented by the dma_resv object when the new fence completes. + * + * And example for using this is replacing a preemption fence with a page table + * update fence which makes the resource inaccessible. + */ +void dma_resv_replace_fences(struct dma_resv *obj, uint64_t context, + struct dma_fence *replacement, + enum dma_resv_usage usage) +{ + struct dma_resv_list *list; + struct dma_fence *old; + unsigned int i; + + /* Only readers supported for now */ + WARN_ON(usage != DMA_RESV_USAGE_READ); + + dma_resv_assert_held(obj); + + write_seqcount_begin(&obj->seq); + + old = dma_resv_excl_fence(obj); + if (old->context == context) { + RCU_INIT_POINTER(obj->fence_excl, dma_fence_get(replacement)); + dma_fence_put(old); + } + + list = dma_resv_shared_list(obj); + for (i = 0; list && i < list->shared_count; ++i) { + old = rcu_dereference_protected(list->shared[i], + dma_resv_held(obj)); + if (old->context != context) + continue; + + rcu_assign_pointer(list->shared[i], dma_fence_get(replacement)); + dma_fence_put(old); + } + + write_seqcount_end(&obj->seq); +} +EXPORT_SYMBOL(dma_resv_replace_fences); + +/** + * dma_resv_add_excl_fence - Add an exclusive fence. + * @obj: the reservation object + * @fence: the exclusive fence to add + * + * Add a fence to the exclusive slot. @obj must be locked with dma_resv_lock(). + * See also &dma_resv.fence_excl for a discussion of the semantics. + */ +static void dma_resv_add_excl_fence(struct dma_resv *obj, + struct dma_fence *fence) +{ + struct dma_fence *old_fence = dma_resv_excl_fence(obj); + + dma_resv_assert_held(obj); + + dma_fence_get(fence); + + write_seqcount_begin(&obj->seq); + /* write_seqcount_begin provides the necessary memory barrier */ + RCU_INIT_POINTER(obj->fence_excl, fence); + write_seqcount_end(&obj->seq); + + dma_fence_put(old_fence); +} + +/** + * dma_resv_add_fence - Add a fence to the dma_resv obj + * @obj: the reservation object + * @fence: the fence to add + * @usage: how the fence is used, see enum dma_resv_usage + * + * Add a fence to a slot, @obj must be locked with dma_resv_lock(), and + * dma_resv_reserve_fences() has been called. + * + * See also &dma_resv.fence for a discussion of the semantics. + */ +void dma_resv_add_fence(struct dma_resv *obj, struct dma_fence *fence, + enum dma_resv_usage usage) +{ + if (usage == DMA_RESV_USAGE_WRITE) + dma_resv_add_excl_fence(obj, fence); + else + dma_resv_add_shared_fence(obj, fence); +} +EXPORT_SYMBOL(dma_resv_add_fence); + +/* Restart the iterator by initializing all the necessary fields, but not the + * relation to the dma_resv object. */ +static void dma_resv_iter_restart_unlocked(struct dma_resv_iter *cursor) +{ + cursor->seq = read_seqcount_begin(&cursor->obj->seq); + cursor->index = -1; + cursor->shared_count = 0; + if (cursor->usage >= DMA_RESV_USAGE_READ) { + cursor->fences = dma_resv_shared_list(cursor->obj); + if (cursor->fences) + cursor->shared_count = cursor->fences->shared_count; + } else { + cursor->fences = NULL; + } + cursor->is_restarted = true; +} + +/* Walk to the next not signaled fence and grab a reference to it */ +static void dma_resv_iter_walk_unlocked(struct dma_resv_iter *cursor) +{ + struct dma_resv *obj = cursor->obj; + + do { + /* Drop the reference from the previous round */ + dma_fence_put(cursor->fence); + + if (cursor->index == -1) { + cursor->fence = dma_resv_excl_fence(obj); + cursor->index++; + if (!cursor->fence) + continue; + + } else if (!cursor->fences || + cursor->index >= cursor->shared_count) { + cursor->fence = NULL; + break; + + } else { + struct dma_resv_list *fences = cursor->fences; + unsigned int idx = cursor->index++; + + cursor->fence = rcu_dereference(fences->shared[idx]); + } + cursor->fence = dma_fence_get_rcu(cursor->fence); + if (!cursor->fence || !dma_fence_is_signaled(cursor->fence)) + break; + } while (true); +} + +/** + * dma_resv_iter_first_unlocked - first fence in an unlocked dma_resv obj. + * @cursor: the cursor with the current position + * + * Subsequent fences are iterated with dma_resv_iter_next_unlocked(). + * + * Beware that the iterator can be restarted. Code which accumulates statistics + * or similar needs to check for this with dma_resv_iter_is_restarted(). For + * this reason prefer the locked dma_resv_iter_first() whenver possible. + * + * Returns the first fence from an unlocked dma_resv obj. + */ +struct dma_fence *dma_resv_iter_first_unlocked(struct dma_resv_iter *cursor) +{ + rcu_read_lock(); + do { + dma_resv_iter_restart_unlocked(cursor); + dma_resv_iter_walk_unlocked(cursor); + } while (read_seqcount_retry(&cursor->obj->seq, cursor->seq)); + rcu_read_unlock(); + + return cursor->fence; +} +EXPORT_SYMBOL(dma_resv_iter_first_unlocked); + +/** + * dma_resv_iter_next_unlocked - next fence in an unlocked dma_resv obj. + * @cursor: the cursor with the current position + * + * Beware that the iterator can be restarted. Code which accumulates statistics + * or similar needs to check for this with dma_resv_iter_is_restarted(). For + * this reason prefer the locked dma_resv_iter_next() whenver possible. + * + * Returns the next fence from an unlocked dma_resv obj. + */ +struct dma_fence *dma_resv_iter_next_unlocked(struct dma_resv_iter *cursor) +{ + bool restart; + + rcu_read_lock(); + cursor->is_restarted = false; + restart = read_seqcount_retry(&cursor->obj->seq, cursor->seq); + do { + if (restart) + dma_resv_iter_restart_unlocked(cursor); + dma_resv_iter_walk_unlocked(cursor); + restart = true; + } while (read_seqcount_retry(&cursor->obj->seq, cursor->seq)); + rcu_read_unlock(); + + return cursor->fence; +} +EXPORT_SYMBOL(dma_resv_iter_next_unlocked); + +/** + * dma_resv_iter_first - first fence from a locked dma_resv object + * @cursor: cursor to record the current position + * + * Subsequent fences are iterated with dma_resv_iter_next_unlocked(). + * + * Return the first fence in the dma_resv object while holding the + * &dma_resv.lock. + */ +struct dma_fence *dma_resv_iter_first(struct dma_resv_iter *cursor) +{ + struct dma_fence *fence; + + dma_resv_assert_held(cursor->obj); + + cursor->index = 0; + if (cursor->usage >= DMA_RESV_USAGE_READ) + cursor->fences = dma_resv_shared_list(cursor->obj); + else + cursor->fences = NULL; + + fence = dma_resv_excl_fence(cursor->obj); + if (!fence) + fence = dma_resv_iter_next(cursor); + + cursor->is_restarted = true; + return fence; +} +EXPORT_SYMBOL_GPL(dma_resv_iter_first); + +/** + * dma_resv_iter_next - next fence from a locked dma_resv object + * @cursor: cursor to record the current position + * + * Return the next fences from the dma_resv object while holding the + * &dma_resv.lock. + */ +struct dma_fence *dma_resv_iter_next(struct dma_resv_iter *cursor) +{ + unsigned int idx; + + dma_resv_assert_held(cursor->obj); + + cursor->is_restarted = false; + if (!cursor->fences || cursor->index >= cursor->fences->shared_count) + return NULL; + + idx = cursor->index++; + return rcu_dereference_protected(cursor->fences->shared[idx], + dma_resv_held(cursor->obj)); +} +EXPORT_SYMBOL_GPL(dma_resv_iter_next); + +/** + * dma_resv_copy_fences - Copy all fences from src to dst. + * @dst: the destination reservation object + * @src: the source reservation object + * + * Copy all fences from src to dst. dst-lock must be held. + */ +int dma_resv_copy_fences(struct dma_resv *dst, struct dma_resv *src) +{ + struct dma_resv_iter cursor; + struct dma_resv_list *list; + struct dma_fence *f, *excl; + + dma_resv_assert_held(dst); + + list = NULL; + excl = NULL; + + dma_resv_iter_begin(&cursor, src, DMA_RESV_USAGE_READ); + dma_resv_for_each_fence_unlocked(&cursor, f) { + + if (dma_resv_iter_is_restarted(&cursor)) { + dma_resv_list_free(list); + dma_fence_put(excl); + + if (cursor.shared_count) { + list = dma_resv_list_alloc(cursor.shared_count); + if (!list) { + dma_resv_iter_end(&cursor); + return -ENOMEM; + } + + list->shared_count = 0; + + } else { + list = NULL; + } + excl = NULL; + } + + dma_fence_get(f); + if (dma_resv_iter_usage(&cursor) == DMA_RESV_USAGE_WRITE) + excl = f; + else + RCU_INIT_POINTER(list->shared[list->shared_count++], f); + } + dma_resv_iter_end(&cursor); + + write_seqcount_begin(&dst->seq); + excl = rcu_replace_pointer(dst->fence_excl, excl, dma_resv_held(dst)); + list = rcu_replace_pointer(dst->fence, list, dma_resv_held(dst)); + write_seqcount_end(&dst->seq); + + dma_resv_list_free(list); + dma_fence_put(excl); + + return 0; +} +EXPORT_SYMBOL(dma_resv_copy_fences); + +/** + * dma_resv_get_fences - Get an object's shared and exclusive + * fences without update side lock held + * @obj: the reservation object + * @usage: controls which fences to include, see enum dma_resv_usage. + * @num_fences: the number of fences returned + * @fences: the array of fence ptrs returned (array is krealloc'd to the + * required size, and must be freed by caller) + * + * Retrieve all fences from the reservation object. + * Returns either zero or -ENOMEM. + */ +int dma_resv_get_fences(struct dma_resv *obj, enum dma_resv_usage usage, + unsigned int *num_fences, struct dma_fence ***fences) +{ + struct dma_resv_iter cursor; + struct dma_fence *fence; + + *num_fences = 0; + *fences = NULL; + + dma_resv_iter_begin(&cursor, obj, usage); + dma_resv_for_each_fence_unlocked(&cursor, fence) { + + if (dma_resv_iter_is_restarted(&cursor)) { + unsigned int count; + + while (*num_fences) + dma_fence_put((*fences)[--(*num_fences)]); + + count = cursor.shared_count + 1; + + /* Eventually re-allocate the array */ + *fences = krealloc_array(*fences, count, + sizeof(void *), + GFP_KERNEL); + if (count && !*fences) { + dma_resv_iter_end(&cursor); + return -ENOMEM; + } + } + + (*fences)[(*num_fences)++] = dma_fence_get(fence); + } + dma_resv_iter_end(&cursor); + + return 0; +} +EXPORT_SYMBOL_GPL(dma_resv_get_fences); + +/** + * dma_resv_get_singleton - Get a single fence for all the fences + * @obj: the reservation object + * @usage: controls which fences to include, see enum dma_resv_usage. + * @fence: the resulting fence + * + * Get a single fence representing all the fences inside the resv object. + * Returns either 0 for success or -ENOMEM. + * + * Warning: This can't be used like this when adding the fence back to the resv + * object since that can lead to stack corruption when finalizing the + * dma_fence_array. + * + * Returns 0 on success and negative error values on failure. + */ +int dma_resv_get_singleton(struct dma_resv *obj, enum dma_resv_usage usage, + struct dma_fence **fence) +{ + struct dma_fence_array *array; + struct dma_fence **fences; + unsigned count; + int r; + + r = dma_resv_get_fences(obj, usage, &count, &fences); + if (r) + return r; + + if (count == 0) { + *fence = NULL; + return 0; + } + + if (count == 1) { + *fence = fences[0]; + kfree(fences); + return 0; + } + + array = dma_fence_array_create(count, fences, + dma_fence_context_alloc(1), + 1, false); + if (!array) { + while (count--) + dma_fence_put(fences[count]); + kfree(fences); + return -ENOMEM; + } + + *fence = &array->base; + return 0; +} +EXPORT_SYMBOL_GPL(dma_resv_get_singleton); + +/** + * dma_resv_wait_timeout - Wait on reservation's objects + * shared and/or exclusive fences. + * @obj: the reservation object + * @usage: controls which fences to include, see enum dma_resv_usage. + * @intr: if true, do interruptible wait + * @timeout: timeout value in jiffies or zero to return immediately + * + * Callers are not required to hold specific locks, but maybe hold + * dma_resv_lock() already + * RETURNS + * Returns -ERESTARTSYS if interrupted, 0 if the wait timed out, or + * greater than zer on success. + */ +long dma_resv_wait_timeout(struct dma_resv *obj, enum dma_resv_usage usage, + bool intr, unsigned long timeout) +{ + long ret = timeout ? timeout : 1; + struct dma_resv_iter cursor; + struct dma_fence *fence; + + dma_resv_iter_begin(&cursor, obj, usage); + dma_resv_for_each_fence_unlocked(&cursor, fence) { + + ret = dma_fence_wait_timeout(fence, intr, ret); + if (ret <= 0) { + dma_resv_iter_end(&cursor); + return ret; + } + } + dma_resv_iter_end(&cursor); + + return ret; +} +EXPORT_SYMBOL_GPL(dma_resv_wait_timeout); + +/** + * dma_resv_test_signaled - Test if a reservation object's fences have been + * signaled. + * @obj: the reservation object + * @usage: controls which fences to include, see enum dma_resv_usage. + * + * Callers are not required to hold specific locks, but maybe hold + * dma_resv_lock() already. + * + * RETURNS + * + * True if all fences signaled, else false. + */ +bool dma_resv_test_signaled(struct dma_resv *obj, enum dma_resv_usage usage) +{ + struct dma_resv_iter cursor; + struct dma_fence *fence; + + dma_resv_iter_begin(&cursor, obj, usage); + dma_resv_for_each_fence_unlocked(&cursor, fence) { + dma_resv_iter_end(&cursor); + return false; + } + dma_resv_iter_end(&cursor); + return true; +} +EXPORT_SYMBOL_GPL(dma_resv_test_signaled); + +/** + * dma_resv_describe - Dump description of the resv object into seq_file + * @obj: the reservation object + * @seq: the seq_file to dump the description into + * + * Dump a textual description of the fences inside an dma_resv object into the + * seq_file. + */ +void dma_resv_describe(struct dma_resv *obj, struct seq_file *seq) +{ + static const char *usage[] = { "write", "read" }; + struct dma_resv_iter cursor; + struct dma_fence *fence; + + dma_resv_for_each_fence(&cursor, obj, DMA_RESV_USAGE_READ, fence) { + seq_printf(seq, "\t%s fence:", + usage[dma_resv_iter_usage(&cursor)]); + dma_fence_describe(fence, seq); + } +} +EXPORT_SYMBOL_GPL(dma_resv_describe); + +#if IS_ENABLED(CONFIG_LOCKDEP) +static int __init dma_resv_lockdep(void) +{ + struct mm_struct *mm = mm_alloc(); + struct ww_acquire_ctx ctx; + struct dma_resv obj; + struct address_space mapping; + int ret; + + if (!mm) + return -ENOMEM; + + dma_resv_init(&obj); + address_space_init_once(&mapping); + + mmap_read_lock(mm); + ww_acquire_init(&ctx, &reservation_ww_class); + ret = dma_resv_lock(&obj, &ctx); + if (ret == -EDEADLK) + dma_resv_lock_slow(&obj, &ctx); + fs_reclaim_acquire(GFP_KERNEL); + /* for unmap_mapping_range on trylocked buffer objects in shrinkers */ + i_mmap_lock_write(&mapping); + i_mmap_unlock_write(&mapping); +#ifdef CONFIG_MMU_NOTIFIER + lock_map_acquire(&__mmu_notifier_invalidate_range_start_map); + __dma_fence_might_wait(); + lock_map_release(&__mmu_notifier_invalidate_range_start_map); +#else + __dma_fence_might_wait(); +#endif + fs_reclaim_release(GFP_KERNEL); + ww_mutex_unlock(&obj.lock); + ww_acquire_fini(&ctx); + mmap_read_unlock(mm); + + mmput(mm); + + return 0; +} +subsys_initcall(dma_resv_lockdep); +#endif + + + + +#endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 3432ffad2b246..11c8c58681418 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -115,11 +115,14 @@ /* dma_map_sgtable() is enabled */ #define HAVE_DMA_MAP_SGTABLE 1 +/* dma_resv->fences is available */ +#define HAVE_DMA_RESV_FENCES 1 + /* dma_resv->seq is available */ -#define HAVE_DMA_RESV_SEQ 1 +/* #undef HAVE_DMA_RESV_SEQ */ /* dma_resv->seq is seqcount_ww_mutex_t */ -#define HAVE_DMA_RESV_SEQCOUNT_WW_MUTEX_T 1 +/* #undef HAVE_DMA_RESV_SEQCOUNT_WW_MUTEX_T */ /* down_read_killable() is available */ #define HAVE_DOWN_READ_KILLABLE 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 index 1ede56611c58d..9d11fb99c397a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 @@ -41,6 +41,25 @@ AC_DEFUN([AC_AMDGPU_DMA_RESV_SEQ], [ ]) ]) +dnl # +dnl # v5.18-rc1-237-g047a1b877ed4 +dnl # dma-buf & drm/amdgpu: remove dma_resv workaround +dnl # +AC_DEFUN([AC_AMDGPU_DMA_RESV_FENCES], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct dma_resv *resv = NULL; + resv->fences = NULL; + ], [ + AC_DEFINE(HAVE_DMA_RESV_FENCES, 1, + [dma_resv->fences is available]) + ]) + ]) +]) + + dnl # dnl # v4.19-rc6-1514-g27836b641c1b dnl # dma-buf: remove shared fence staging in reservation object @@ -63,5 +82,6 @@ AC_DEFUN([AC_AMDGPU_RESERVATION_OBJECT_STAGED], [ AC_DEFUN([AC_AMDGPU_DMA_RESV], [ AC_AMDGPU_DMA_RESV_SEQ + AC_AMDGPU_DMA_RESV_FENCES AC_AMDGPU_RESERVATION_OBJECT_STAGED ]) diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index 7d481851f944d..81a0d5da5c8bd 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -41,7 +41,9 @@ done sed -i -e '/DEFINE_WD_CLASS(reservation_ww_class)/,/EXPORT_SYMBOL(reservation_ww_class)/d' \ -e '/dma_resv_lockdep/,/subsys_initcall/d' $KCL/dma-buf/dma-resv.c sed -i -e '/extern struct ww_class reservation_ww_class/i #include ' \ - -e '/struct dma_resv {/, /}/d' $INC/linux/dma-resv.h + -e '/struct dma_resv {/, /}/d' $INC/linux/dma-resv.h \ + -e '/struct dma_resv_iter {/, /}/d' $INC/linux/dma-resv.h \ + -e '/enum dma_resv_usage {/, /}/d' $INC/linux/dma-resv.h # add amd prefix to exported symbols for file in $FILES; do @@ -71,3 +73,7 @@ if ! grep -q 'define HAVE_AMDKCL_FLAGS_TAKE_PATH' $SRC/config/config.h; then sed -i 's|$(AMDDALPATH)/.*/\(.*\.o\)|\1|' $file done fi + +if ! grep -q 'define HAVE_DMA_RESV_FENCES' $SRC/config/config.h; then + sed -i 's|dma-buf/dma-resv.o|kcl_dma-resv.o|' amd/amdkcl/Makefile +fi diff --git a/include/kcl/kcl_dma-resv.h b/include/kcl/kcl_dma-resv.h index 0c4850cd6bf95..39a4e3b5e67f1 100644 --- a/include/kcl/kcl_dma-resv.h +++ b/include/kcl/kcl_dma-resv.h @@ -54,6 +54,125 @@ struct dma_resv_list; +enum dma_resv_usage { + /** + * @DMA_RESV_USAGE_KERNEL: For in kernel memory management only. + * + * This should only be used for things like copying or clearing memory + * with a DMA hardware engine for the purpose of kernel memory + * management. + * + * Drivers *always* must wait for those fences before accessing the + * resource protected by the dma_resv object. The only exception for + * that is when the resource is known to be locked down in place by + * pinning it previously. + */ + DMA_RESV_USAGE_KERNEL, + + /** + * @DMA_RESV_USAGE_WRITE: Implicit write synchronization. + * + * This should only be used for userspace command submissions which add + * an implicit write dependency. + */ + DMA_RESV_USAGE_WRITE, + + /** + * @DMA_RESV_USAGE_READ: Implicit read synchronization. + * + * This should only be used for userspace command submissions which add + * an implicit read dependency. + */ + DMA_RESV_USAGE_READ, + + /** + * @DMA_RESV_USAGE_BOOKKEEP: No implicit sync. + * + * This should be used by submissions which don't want to participate in + * implicit synchronization. + * + * The most common case are preemption fences as well as page table + * updates and their TLB flushes. + */ + DMA_RESV_USAGE_BOOKKEEP +}; + +#if defined(HAVE_DMA_RESV_FENCES) +struct dma_resv { + struct ww_mutex lock; + struct dma_resv_list __rcu *fences; +}; + +struct dma_resv_iter { + /** @obj: The dma_resv object we iterate over */ + struct dma_resv *obj; + + /** @usage: Return fences with this usage or lower. */ + enum dma_resv_usage usage; + + /** @fence: the currently handled fence */ + struct dma_fence *fence; + + /** @fence_usage: the usage of the current fence */ + enum dma_resv_usage fence_usage; + + /** @index: index into the shared fences */ + unsigned int index; + + /** @fences: the shared fences; private, *MUST* not dereference */ + struct dma_resv_list *fences; + + /** @num_fences: number of fences */ + unsigned int num_fences; + + /** @is_restarted: true if this is the first returned fence */ + bool is_restarted; +}; + +#else + +/** + * struct dma_resv_list - a list of shared fences + * @rcu: for internal use + * @shared_count: table of shared fences + * @shared_max: for growing shared fence table + * @shared: shared fence table + */ +struct dma_resv_list { + struct rcu_head rcu; + u32 shared_count, shared_max; + struct dma_fence __rcu *shared[]; +}; + +struct dma_resv_iter { + /** @obj: The dma_resv object we iterate over */ + struct dma_resv *obj; + + /** @usage: Return fences with this usage or lower. */ + enum dma_resv_usage usage; + + /** @fence: the currently handled fence */ + struct dma_fence *fence; + + /** @fence_usage: the usage of the current fence */ + enum dma_resv_usage fence_usage; + + /** @seq: sequence number to check for modifications */ + unsigned int seq; + + /** @index: index into the shared fences */ + unsigned int index; + + /** @fences: the shared fences; private, *MUST* not dereference */ + struct dma_resv_list *fences; + + /** @shared_count: number of shared fences */ + unsigned int shared_count; + + /** @is_restarted: true if this is the first returned fence */ + bool is_restarted; +}; + #if defined(HAVE_DMA_RESV_SEQCOUNT_WW_MUTEX_T) struct dma_resv { struct ww_mutex lock; @@ -81,6 +200,38 @@ struct dma_resv { }; #endif +/** + * dma_resv_excl_fence - return the object's exclusive fence + * @obj: the reservation object + * + * Returns the exclusive fence (if any). Caller must either hold the objects + * through dma_resv_lock() or the RCU read side lock through rcu_read_lock(), + * or one of the variants of each + * + * RETURNS + * The exclusive fence or NULL + */ +static inline struct dma_fence * +dma_resv_excl_fence(struct dma_resv *obj) +{ + return rcu_dereference_check(obj->fence_excl, lockdep_is_held(&(obj)->lock.base)); +} + +/** + * dma_resv_shared_list - get the reservation object's shared fence list + * @obj: the reservation object + * + * Returns the shared fence list. Caller must either hold the objects + * through dma_resv_lock() or the RCU read side lock through rcu_read_lock(), + * or one of the variants of each + */ +static inline struct dma_resv_list *dma_resv_shared_list(struct dma_resv *obj) +{ + return rcu_dereference_check(obj->fence, lockdep_is_held(&(obj)->lock.base)); +} + +#endif /* !defined(HAVE_DMA_RESV_FENCES) */ + #if !defined(smp_store_mb) #define smp_store_mb set_mb #endif From 770d8d9ebbd3d46af29ebb6cd4e1112b40e0b27c Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 21 Jul 2022 10:30:52 +0800 Subject: [PATCH 0721/1868] drm/amdkcl: replace dma_resv_add_excl_fence with dma_resv_add_fence Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index ffd28e47b034a..eb303d6fb1637 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -102,14 +102,14 @@ __dma_resv_make_exclusive(struct dma_resv *obj) if (!dma_resv_shared_list(obj)) /* no shared fences to convert */ return 0; - r = dma_resv_get_fences(obj, NULL, &count, &fences); + r = dma_resv_get_fences(obj, DMA_RESV_USAGE_READ, &count, &fences); if (r) return r; if (count == 0) { /* Now that was unexpected. */ } else if (count == 1) { - dma_resv_add_excl_fence(obj, fences[0]); + dma_resv_add_fence(obj, fences[0], DMA_RESV_USAGE_WRITE); dma_fence_put(fences[0]); kfree(fences); } else { @@ -121,7 +121,7 @@ __dma_resv_make_exclusive(struct dma_resv *obj) if (!array) goto err_fences_put; - dma_resv_add_excl_fence(obj, &array->base); + dma_resv_add_fence(obj, &array->base, DMA_RESV_USAGE_WRITE); dma_fence_put(&array->base); } From 1be881aecee8b354e9af271522d31f604b9541d9 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 21 Jul 2022 12:58:52 +0800 Subject: [PATCH 0722/1868] drm/amdkcl: use DMA_RESV_USAGE_KERNEL as DMA_REV_USAGE_WRITE for legacy os Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c b/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c index e3525a0973f71..5cd7528f0c2a7 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c @@ -380,7 +380,7 @@ static void dma_resv_add_excl_fence(struct dma_resv *obj, void dma_resv_add_fence(struct dma_resv *obj, struct dma_fence *fence, enum dma_resv_usage usage) { - if (usage == DMA_RESV_USAGE_WRITE) + if (usage == DMA_RESV_USAGE_WRITE || usage == DMA_RESV_USAGE_KERNEL) dma_resv_add_excl_fence(obj, fence); else dma_resv_add_shared_fence(obj, fence); From 8e25f7a4f8f44235f51f09a066bd265639610b7b Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 21 Jul 2022 13:00:56 +0800 Subject: [PATCH 0723/1868] drm/amdkcl: fix NULL pointer check Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c b/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c index 5cd7528f0c2a7..db40a6e5f035a 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c @@ -321,7 +321,7 @@ void dma_resv_replace_fences(struct dma_resv *obj, uint64_t context, write_seqcount_begin(&obj->seq); old = dma_resv_excl_fence(obj); - if (old->context == context) { + if (old && old->context == context) { RCU_INIT_POINTER(obj->fence_excl, dma_fence_get(replacement)); dma_fence_put(old); } From 4d19932b3a66fc8383c3c3ebe62ed005a7d34ffc Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 21 Jul 2022 15:50:43 +0800 Subject: [PATCH 0724/1868] drm/amdkcl: replace arg with DMA_RESV_USAGE_WRITE Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index f83bde74d6911..10289e627b8c1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -453,7 +453,7 @@ int amdgpu_crtc_page_flip(struct drm_crtc *crtc, goto unreserve; } - r = dma_resv_get_fences(amdkcl_ttm_resvp(&new_abo->tbo), NULL, + r = dma_resv_get_fences(amdkcl_ttm_resvp(&new_abo->tbo), DMA_RESV_USAGE_WRITE, &work->shared_count, &work->shared); if (unlikely(r != 0)) { From 4d0c5305e3422f77a64f8469d71075c05af1f875 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 21 Jul 2022 22:33:58 +0800 Subject: [PATCH 0725/1868] drm/amdkcl: remove useless header Signed-off-by: Leslie Shi Signed-off-by: Ma Jun Change-Id: Ic20beeebc180c41f7b6f0a7510c3f03aa4370985 --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 57aa01741f79b..48606fc29978e 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -97,9 +97,6 @@ #include #include #include -#ifdef CONFIG_DRM_AMD_DC_HDCP -#include -#endif #include From a0f9d670aba7541a3864d9b47de26dd77249e457 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 25 Jul 2022 10:21:47 +0800 Subject: [PATCH 0726/1868] drm/amdkcl: drop DRM_AMD_DC_DCN{1_0/2_x/3_x} Signed-off-by: Leslie Shi Change-Id: I6e3f9d20a8573901fabcc13538abc988936d803e Signed-off-by: Ma Jun --- drivers/gpu/drm/amd/dkms/Makefile | 12 ++---------- 1 file changed, 2 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index e7b791c8195f0..1fc960e3cae03 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -149,9 +149,6 @@ export CONFIG_DRM_AMDGPU_CIK=y export CONFIG_DRM_AMDGPU_SI=y export CONFIG_DRM_AMDGPU_USERPTR=y export CONFIG_DRM_AMD_DC=y -ifndef CONFIG_ARM64 -export CONFIG_DRM_AMD_DC_DCN1_0=y -endif subdir-ccflags-y += -DCONFIG_HSA_AMD subdir-ccflags-y += -DCONFIG_DRM_TTM_DMA_PAGE_POOL @@ -159,9 +156,6 @@ subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_CIK subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_SI subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_USERPTR subdir-ccflags-y += -DCONFIG_DRM_AMD_DC -ifndef CONFIG_ARM64 -subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN1_0 -endif ifeq ($(call _is_kcl_macro_defined,HAVE_AMDKCL_HMM_MIRROR_ENABLED),y) ifdef CONFIG_DEVICE_PRIVATE @@ -179,10 +173,8 @@ subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_HDCP # if core2 isn't in the compiler flags ifndef CONFIG_ARM64 ifeq ($(filter %core2, $(KBUILD_CFLAGS)),) -export CONFIG_DRM_AMD_DC_DCN2_x=y -export CONFIG_DRM_AMD_DC_DCN3_x=y -subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN2_x -subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN3_x +export CONFIG_DRM_AMD_DC_DCN=y +subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN endif endif From 6804ca9c9b8c43bdefd4a93d6e1b635b5a6ee11f Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 27 Jul 2022 18:56:58 +0800 Subject: [PATCH 0727/1868] drm/amdkcl: Test if drm_private_obj is defined Test if drm_private_obj is defined in struct drm_dp_mst_topology_mrg Signed-off-by: Ma Jun Reviewed-by: Leslie Shi Change-Id: I9daeac36f316b5183cd732aa13a7283be43ea097 --- .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 6 +++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../amd/dkms/m4/drm_dp_mst_topology_mgr.m4 | 26 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 36 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index 8203a6367982a..e2809f3e87b6e 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -2778,6 +2778,7 @@ static int target_backlight_show(struct seq_file *m, void *unused) * cat /sys/kernel/debug/dri/0/DP-X/is_mst_connector * */ +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_MGR_BASE static int dp_is_mst_connector_show(struct seq_file *m, void *unused) { struct drm_connector *connector = m->private; @@ -2814,6 +2815,7 @@ static int dp_is_mst_connector_show(struct seq_file *m, void *unused) return 0; } +#endif /* * function description: Read out the mst progress status @@ -2883,7 +2885,9 @@ DEFINE_SHOW_ATTRIBUTE(internal_display); DEFINE_SHOW_ATTRIBUTE(odm_combine_segments); DEFINE_SHOW_ATTRIBUTE(replay_capability); DEFINE_SHOW_ATTRIBUTE(psr_capability); +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_MGR_BASE DEFINE_SHOW_ATTRIBUTE(dp_is_mst_connector); +#endif DEFINE_SHOW_ATTRIBUTE(dp_mst_progress_status); DEFINE_SHOW_ATTRIBUTE(is_dpia_link); @@ -3017,7 +3021,9 @@ static const struct { {"max_bpc", &dp_max_bpc_debugfs_fops}, {"dsc_disable_passthrough", &dp_dsc_disable_passthrough_debugfs_fops}, +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_MGR_BASE {"is_mst_connector", &dp_is_mst_connector_fops}, +#endif {"mst_progress_status", &dp_mst_progress_status_fops}, {"is_dpia_link", &is_dpia_link_fops}, {"mst_link_settings", &dp_mst_link_settings_debugfs_fops} diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 11c8c58681418..c3e1e5c202995 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -405,6 +405,9 @@ /* struct drm_dp_mst_topology_cbs->register_connector is available */ /* #undef HAVE_DRM_DP_MST_TOPOLOGY_CBS_REGISTER_CONNECTOR */ +/* struct drm_dp_mst_topology_mgr.base is available */ +#define HAVE_DRM_DP_MST_TOPOLOGY_MGR_BASE 1 + /* drm_dp_mst_topology_mgr_init() wants drm_device arg */ #define HAVE_DRM_DP_MST_TOPOLOGY_MGR_INIT_DRM_DEV 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr.m4 new file mode 100644 index 0000000000000..06cdbe40de8cf --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr.m4 @@ -0,0 +1,26 @@ +dnl # +dnl # commit v4.14-rc1-a4370c7774 +dnl # drm/atomic: Make private objs proper objects +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_BASE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) + #include + #else + #include + #endif + #include + ], [ + struct drm_dp_mst_topology_mgr *mst_mgr = 0; + int i = 0; + if ((&mst_mgr->base) && (&mst_mgr->base.lock)) + i++; + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_TOPOLOGY_MGR_BASE, 1, + [struct drm_dp_mst_topology_mgr.base is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 5a1e58c24c255..9cf11bba77d1a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -209,6 +209,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_STR_YES_NO AC_AMDGPU_DMA_FENCE_CHAIN_CONTAINED AC_AMDGPU_DRM_GEM_OBJECT_FUNCS_VMAP_HAS_IOSYS_MAP_ARG + AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_BASE AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 4df9e7fdf0a695caa67218ef6e9224a8daf21db7 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Fri, 29 Jul 2022 13:54:21 +0800 Subject: [PATCH 0728/1868] drm/amdkcl: refactor kcl implementation for drm/display header change Signed-off-by: Flora Cui Reviewed-by: Leslie Shi --- include/kcl/backport/kcl_drm_dp_mst_helper_backport.h | 6 ------ include/kcl/header/drm/display/drm_dp_helper.h | 4 ++-- include/kcl/header/drm/display/drm_dp_mst_helper.h | 4 ++-- include/kcl/header/drm/dp/drm_dp_helper.h | 9 --------- include/kcl/header/drm/dp/drm_dp_mst_helper.h | 9 --------- include/kcl/kcl_drm_dp_cec.h | 6 ------ include/kcl/kcl_drm_dp_helper.h | 6 ------ 7 files changed, 4 insertions(+), 40 deletions(-) delete mode 100644 include/kcl/header/drm/dp/drm_dp_helper.h delete mode 100644 include/kcl/header/drm/dp/drm_dp_mst_helper.h diff --git a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h index 5623abd34416b..9be8ef18696a1 100644 --- a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h +++ b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h @@ -22,13 +22,7 @@ #ifndef _KCL_DRM_DP_MST_HELPER_BACKPORT_H_ #define _KCL_DRM_DP_MST_HELPER_BACKPORT_H_ -#if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) #include -#elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) -#include -#else -#include -#endif /* Copied from drivers/gpu/drm/drm_dp_mst_topology.c and modified for KCL */ #if !defined(HAVE_DRM_DP_CALC_PBN_MODE_3ARGS) diff --git a/include/kcl/header/drm/display/drm_dp_helper.h b/include/kcl/header/drm/display/drm_dp_helper.h index 83269a83e90ba..3435bd45d5669 100644 --- a/include/kcl/header/drm/display/drm_dp_helper.h +++ b/include/kcl/header/drm/display/drm_dp_helper.h @@ -5,9 +5,9 @@ #if defined(HAVE_DRM_DISPLAY_DRM_DP_HELPER_H) #include_next #elif defined(HAVE_DRM_DP_DRM_DP_HELPER_H) -#include_next +#include #else -#include_next +#include #endif #endif diff --git a/include/kcl/header/drm/display/drm_dp_mst_helper.h b/include/kcl/header/drm/display/drm_dp_mst_helper.h index 35221a4f00645..c667873640a00 100644 --- a/include/kcl/header/drm/display/drm_dp_mst_helper.h +++ b/include/kcl/header/drm/display/drm_dp_mst_helper.h @@ -5,9 +5,9 @@ #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) #include_next #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) -#include_next +#include #else -#include_next +#include #endif #endif diff --git a/include/kcl/header/drm/dp/drm_dp_helper.h b/include/kcl/header/drm/dp/drm_dp_helper.h deleted file mode 100644 index 9aac78ed61294..0000000000000 --- a/include/kcl/header/drm/dp/drm_dp_helper.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -#ifndef _KCL_HEADER_DP_DRM_DP_HELPER_H_H_ -#define _KCL_HEADER_DP_DRM_DP_HELPER_H_H_ - -#ifdef HAVE_DRM_DP_DRM_DP_HELPER_H -#include_next -#endif - -#endif diff --git a/include/kcl/header/drm/dp/drm_dp_mst_helper.h b/include/kcl/header/drm/dp/drm_dp_mst_helper.h deleted file mode 100644 index 116be51b87c2c..0000000000000 --- a/include/kcl/header/drm/dp/drm_dp_mst_helper.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -#ifndef _KCL_HEADER_DP_DRM_DP_MST_HELPER_H_H_ -#define _KCL_HEADER_DP_DRM_DP_MST_HELPER_H_H_ - -#ifdef HAVE_DRM_DP_DRM_DP_MST_HELPER_H -#include_next -#endif - -#endif diff --git a/include/kcl/kcl_drm_dp_cec.h b/include/kcl/kcl_drm_dp_cec.h index e76e90cc0fe59..58549a2e15bf1 100644 --- a/include/kcl/kcl_drm_dp_cec.h +++ b/include/kcl/kcl_drm_dp_cec.h @@ -8,13 +8,7 @@ #ifndef __KCL_KCL_DRM_DP_CEC_H__ #define __KCL_KCL_DRM_DP_CEC_H__ -#if defined(HAVE_DRM_DISPLAY_DRM_DP_HELPER_H) #include -#elif defined(HAVE_DRM_DP_DRM_DP_HELPER_H) -#include -#else -#include -#endif /* * commit v4.19-rc1-100-g5ce70c799ac2 diff --git a/include/kcl/kcl_drm_dp_helper.h b/include/kcl/kcl_drm_dp_helper.h index 2d6d15d2bedb8..43ddfa2ed899d 100644 --- a/include/kcl/kcl_drm_dp_helper.h +++ b/include/kcl/kcl_drm_dp_helper.h @@ -30,13 +30,7 @@ #include #include -#if defined(HAVE_DRM_DISPLAY_DRM_DP_HELPER_H) #include -#elif defined(HAVE_DRM_DP_DRM_DP_HELPER_H) -#include -#else -#include -#endif #include /* From 93bc04c0ece41c8122d63037293f483c4dc751cb Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 3 Aug 2022 10:29:12 +0800 Subject: [PATCH 0729/1868] drm/amdkcl: enable CONFIG_HSA_AMD_P2P Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Makefile | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 1fc960e3cae03..a00c632cc588f 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -167,6 +167,11 @@ endif export CONFIG_DRM_AMD_DC_HDCP=y subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_HDCP +ifeq ($(call _is_kcl_macro_defined,HAVE_LINUX_PCI_P2PDMA_H),y) +export CONFIG_HSA_AMD_P2P=y +subdir-ccflags-y += -DCONFIG_HSA_AMD_P2P +endif + # Trying to enable DCN2/3 with core2 optimizations will result in # older versions of GCC hanging during building/installing. Check # if the compiler is using core2 optimizations and only build DCN2/3 From 76a1f60383d16fb6f60ed95890b2a1621ca9a889 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Wed, 13 Jul 2022 09:54:49 -0400 Subject: [PATCH 0730/1868] drm/amdkcl: test for available memory Do not kick off new background compiling processes if amount of available system memory less than 20%. It prevents from killing the driver installation on the systems with small amount of memory. SWDEV-336154 Change-Id: Idaf71093526ce2a4a734c5c168a239c927d543b3 Signed-off-by: Slava Grigorev Reviewed-by: Flora Cui Reviewed-by: Slava Abramov --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 9cf11bba77d1a..68f3bac4d4a21 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -596,6 +596,22 @@ AC_DEFUN([AC_KERNEL_CHECK_HEADERS], [ AC_CHECK_HEADERS([$1],[AS_TR_CPP([HAVE_$1])=1],,[-]) ]) +dnl # +dnl # AC_KERNEL_FREE_MEM +dnl # return true if available memory >20% +dnl # +AC_DEFUN([AC_KERNEL_FREE_MEM], [ + free_mem=$(free -t | awk '/^Total:/ { + printf("%d\n", $[4] / $[2] * 100) + }') + + AS_IF([[[ $free_mem -gt 20 ]]], [ + $1 + ], [ + $2 + ]) +]) + dnl # dnl # AC_KERNEL_DO_BACKGROUND dnl # $1: contents to be executed @@ -604,6 +620,17 @@ AC_DEFUN([AC_KERNEL_DO_BACKGROUND], [ do_background() { AC_KERNEL_TMP_BUILD_DIR([$1]) } + + while : + do + AC_KERNEL_FREE_MEM([rc=0], [rc=1]) + if test $rc -ne 0; then : + sleep 1 + else : + break + fi + done + do_background & procs="$! $procs" ]) From 4a10fdda7580403985c74fb23704ee301d352143 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 10 Aug 2022 11:40:18 +0800 Subject: [PATCH 0731/1868] Revert "drm/amdkcl: fix build error" This reverts commit b57ae4cfbeb096d6f01809599c6194b79c4620a5. --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 2 +- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 10 ++-- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 50 ++++++------------- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 2 +- 4 files changed, 23 insertions(+), 41 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index a490258eed405..6dcec35258c50 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -174,7 +174,7 @@ int amdgpu_amdkfd_submit_ib(struct amdgpu_device *adev, void amdgpu_amdkfd_set_compute_idle(struct amdgpu_device *adev, bool idle); bool amdgpu_amdkfd_have_atomics_support(struct amdgpu_device *adev); -int amdgpu_amdkfd_copy_mem_to_mem(struct amdgpu_device *adev, struct kgd_mem *src_mem, +int amdgpu_amdkfd_copy_mem_to_mem(struct kgd_dev *kgd, struct kgd_mem *src_mem, uint64_t src_offset, struct kgd_mem *dst_mem, uint64_t dest_offset, uint64_t size, struct dma_fence **f, uint64_t *actual_size); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index a094de698d275..c82c749e83d57 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -3571,11 +3571,12 @@ int amdgpu_amdkfd_remove_gws_from_process(void *info, void *mem) return 0; } -int amdgpu_amdkfd_copy_mem_to_mem(struct amdgpu_device *adev, struct kgd_mem *src_mem, +int amdgpu_amdkfd_copy_mem_to_mem(struct kgd_dev *kgd, struct kgd_mem *src_mem, uint64_t src_offset, struct kgd_mem *dst_mem, uint64_t dst_offset, uint64_t size, struct dma_fence **f, uint64_t *actual_size) { + struct amdgpu_device *adev = NULL; struct amdgpu_copy_mem src, dst; struct ww_acquire_ctx ticket; struct list_head list, duplicates; @@ -3583,18 +3584,19 @@ int amdgpu_amdkfd_copy_mem_to_mem(struct amdgpu_device *adev, struct kgd_mem *sr struct dma_fence *fence = NULL; int i, r; - if (!adev|| !src_mem || !dst_mem || !actual_size) + if (!kgd || !src_mem || !dst_mem || !actual_size) return -EINVAL; *actual_size = 0; + adev = get_amdgpu_device(kgd); INIT_LIST_HEAD(&list); INIT_LIST_HEAD(&duplicates); src.bo = &src_mem->bo->tbo; dst.bo = &dst_mem->bo->tbo; - src.mem = src.bo->resource; - dst.mem = dst.bo->resource; + src.mem = &src.bo->mem; + dst.mem = &dst.bo->mem; src.offset = src_offset; dst.offset = dst_offset; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 38d39a30994ef..69f55f3993f4a 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1753,7 +1753,7 @@ static int kfd_create_sg_table_from_userptr_bo(struct kfd_bo *bo, flags = FOLL_WRITE; locked = 1; mmap_read_lock(mm); - n = kcl_get_user_pages_remote(task, mm, pa, nents, flags, process_pages, + n = get_user_pages_remote(mm, pa, nents, flags, process_pages, NULL, &locked); if (locked) mmap_read_unlock(mm); @@ -1798,13 +1798,11 @@ static void kfd_free_cma_bos(struct cma_iter *ci) list_for_each_entry_safe(cma_bo, tmp, &ci->cma_list, list) { struct kfd_dev *dev = cma_bo->dev; - struct kfd_process_device *pdd; /* sg table is deleted by free_memory_of_gpu */ if (cma_bo->sg) kfd_put_sg_table(cma_bo->sg); - pdd = kfd_get_process_device_data(dev, ci->p); - amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->adev, cma_bo->mem, pdd->drm_priv, NULL); + amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->kgd, cma_bo->mem, NULL); list_del(&cma_bo->list); kfree(cma_bo); } @@ -1900,10 +1898,9 @@ static int kfd_create_cma_system_bo(struct kfd_dev *kdev, struct kfd_bo *bo, goto pdd_fail; } - ret = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(kdev->adev, 0ULL, bo_size, + ret = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(kdev->kgd, 0ULL, bo_size, pdd->drm_priv, cbo->sg, - &cbo->mem, NULL, flags, - false); + &cbo->mem, NULL, flags); mutex_unlock(&p->mutex); if (ret) { pr_err("Failed to create shadow system BO %d\n", ret); @@ -1911,7 +1908,7 @@ static int kfd_create_cma_system_bo(struct kfd_dev *kdev, struct kfd_bo *bo, } if (bo->mem_type == KFD_IOC_ALLOC_MEM_FLAGS_VRAM) { - ret = amdgpu_amdkfd_copy_mem_to_mem(kdev->adev, bo->mem, + ret = amdgpu_amdkfd_copy_mem_to_mem(kdev->kgd, bo->mem, offset, cbo->mem, 0, bo_size, &f, size); if (ret) { @@ -1936,7 +1933,7 @@ static int kfd_create_cma_system_bo(struct kfd_dev *kdev, struct kfd_bo *bo, return ret; copy_fail: - amdgpu_amdkfd_gpuvm_free_memory_of_gpu(kdev->adev, bo->mem, pdd->drm_priv, NULL); + amdgpu_amdkfd_gpuvm_free_memory_of_gpu(kdev->kgd, bo->mem, NULL); pdd_fail: if (cbo->sg) { kfd_put_sg_table(cbo->sg); @@ -2093,7 +2090,7 @@ static int kfd_copy_userptr_bos(struct cma_iter *si, struct cma_iter *di, nl = min_t(unsigned int, MAX_PP_KMALLOC_COUNT, nents); locked = 1; mmap_read_lock(ri->mm); - nl = kcl_get_user_pages_remote(ri->task, ri->mm, rva, nl, + nl = get_user_pages_remote(ri->mm, rva, nl, flags, process_pages, NULL, &locked); if (locked) @@ -2170,9 +2167,9 @@ static int kfd_create_kgd_mem(struct kfd_dev *kdev, uint64_t size, return -EINVAL; } - ret = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(kdev->adev, 0ULL, size, + ret = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(kdev->kgd, 0ULL, size, pdd->drm_priv, NULL, - mem, NULL, flags, false); + mem, NULL, flags); mutex_unlock(&p->mutex); if (ret) { pr_err("Failed to create shadow system BO %d\n", ret); @@ -2184,28 +2181,11 @@ static int kfd_create_kgd_mem(struct kfd_dev *kdev, uint64_t size, static int kfd_destroy_kgd_mem(struct kgd_mem *mem) { - struct amdgpu_device *adev; - struct task_struct *task; - struct kfd_process *p; - struct kfd_process_device *pdd; - uint32_t gpu_id, gpu_idx; - int r; - if (!mem) return -EINVAL; - adev = amdgpu_ttm_adev(mem->bo->tbo.bdev); - task = get_pid_task(mem->process_info->pid, PIDTYPE_PID); - p = kfd_get_process(task); - r = kfd_process_gpuid_from_adev(p, adev, &gpu_id, &gpu_idx); - if (r < 0) { - pr_warn("no gpu id found, mem maybe leaking\n"); - return -EINVAL; - } - pdd = kfd_process_device_from_gpuidx(p, gpu_idx); - /* param adev is not used*/ - return amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, mem, pdd->drm_priv, NULL); + return amdgpu_amdkfd_gpuvm_free_memory_of_gpu(NULL, mem, NULL); } /* Copies @size bytes from si->cur_bo to di->cur_bo starting at their @@ -2262,7 +2242,7 @@ static int kfd_copy_bos(struct cma_iter *si, struct cma_iter *di, dst_mem = di->cma_bo->mem; dst_offset = di->bo_offset & (PAGE_SIZE - 1); list_add_tail(&di->cma_bo->list, &di->cma_list); - } else if (src_bo->dev->adev != dst_bo->dev->adev) { + } else if (src_bo->dev->kgd != dst_bo->dev->kgd) { /* This indicates that atleast on of the BO is in local mem. * If both are in local mem of different devices then create an * intermediate System BO and do a double copy @@ -2283,7 +2263,7 @@ static int kfd_copy_bos(struct cma_iter *si, struct cma_iter *di, return -EINVAL; } - if (amdgpu_amdkfd_copy_mem_to_mem(src_bo->dev->adev, + if (amdgpu_amdkfd_copy_mem_to_mem(src_bo->dev->kgd, src_bo->mem, si->bo_offset, *tmp_mem, 0, size, f, &size)) @@ -2305,7 +2285,7 @@ static int kfd_copy_bos(struct cma_iter *si, struct cma_iter *di, return -EINVAL; } - err = amdgpu_amdkfd_copy_mem_to_mem(dev->adev, src_mem, src_offset, + err = amdgpu_amdkfd_copy_mem_to_mem(dev->kgd, src_mem, src_offset, dst_mem, dst_offset, size, f, copied); /* The tmp_bo allocates additional memory. So it is better to wait and @@ -3252,7 +3232,7 @@ static int criu_restore_memory_of_gpu_ipc(struct kfd_process_device *pdd, */ ret = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(dev->adev, bo_bucket->addr, bo_bucket->size, pdd->drm_priv, - NULL, kgd_mem, &offset, + kgd_mem, &offset, bo_bucket->alloc_flags, true); if (ret) { pr_err("Could not create the BO\n"); @@ -3346,7 +3326,7 @@ static int criu_restore_memory_of_gpu(struct kfd_process_device *pdd, } /* Create the BO */ ret = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(pdd->dev->adev, bo_bucket->addr, - bo_bucket->size, pdd->drm_priv, NULL, kgd_mem, + bo_bucket->size, pdd->drm_priv, kgd_mem, &offset, bo_bucket->alloc_flags, criu_resume); if (ret) { pr_err("Could not create the BO\n"); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index faac3035068c9..9baf37567d9a0 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -716,7 +716,7 @@ static int kfd_process_alloc_gpuvm(struct kfd_process_device *pdd, int err; err = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(kdev->adev, gpu_va, size, - pdd->drm_priv, NULL, mem, NULL, + pdd->drm_priv, NULL, &mem, NULL, flags, false); if (err) goto err_alloc_mem; From 4796e19eb43d20950c2e0466d27a967d1baf70d8 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 10 Aug 2022 11:47:47 +0800 Subject: [PATCH 0732/1868] Revert "drm/amdkfd: Add CMA API" This reverts commit 4397c7e24bdd5a65ab131266c1acbe6078235e74. CMA is not supported anymore. So revert this patch Signed-off-by: Ma Jun Change-Id: I341df8470a1666cdd37e1c167dad139aafb4dc08 --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 7 +- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 86 +- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 842 +----------------- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 32 - drivers/gpu/drm/amd/amdkfd/kfd_process.c | 2 +- include/uapi/linux/kfd_ioctl.h | 35 - 6 files changed, 5 insertions(+), 999 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index 6dcec35258c50..85c7e4ed46d2f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -174,11 +174,6 @@ int amdgpu_amdkfd_submit_ib(struct amdgpu_device *adev, void amdgpu_amdkfd_set_compute_idle(struct amdgpu_device *adev, bool idle); bool amdgpu_amdkfd_have_atomics_support(struct amdgpu_device *adev); -int amdgpu_amdkfd_copy_mem_to_mem(struct kgd_dev *kgd, struct kgd_mem *src_mem, - uint64_t src_offset, struct kgd_mem *dst_mem, - uint64_t dest_offset, uint64_t size, struct dma_fence **f, - uint64_t *actual_size); - bool amdgpu_amdkfd_is_kfd_vmid(struct amdgpu_device *adev, u32 vmid); int amdgpu_amdkfd_pre_reset(struct amdgpu_device *adev, @@ -317,7 +312,7 @@ size_t amdgpu_amdkfd_get_available_memory(struct amdgpu_device *adev, uint8_t xcp_id); int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( struct amdgpu_device *adev, uint64_t va, uint64_t size, - void *drm_priv, struct sg_table *sg, struct kgd_mem **mem, + void *drm_priv, struct kgd_mem **mem, uint64_t *offset, uint32_t flags, bool criu_resume); int amdgpu_amdkfd_gpuvm_free_memory_of_gpu( struct amdgpu_device *adev, struct kgd_mem *mem, void *drm_priv, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index c82c749e83d57..bea20c28404b7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -1800,12 +1800,13 @@ size_t amdgpu_amdkfd_get_available_memory(struct amdgpu_device *adev, int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( struct amdgpu_device *adev, uint64_t va, uint64_t size, - void *drm_priv, struct sg_table *sg, struct kgd_mem **mem, + void *drm_priv, struct kgd_mem **mem, uint64_t *offset, uint32_t flags, bool criu_resume) { struct amdgpu_vm *avm = drm_priv_to_vm(drm_priv); struct amdgpu_fpriv *fpriv = container_of(avm, struct amdgpu_fpriv, vm); enum ttm_bo_type bo_type = ttm_bo_type_device; + struct sg_table *sg = NULL; uint64_t user_addr = 0; struct amdgpu_bo *bo; struct drm_gem_object *gobj = NULL; @@ -1868,10 +1869,6 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( if (flags & KFD_IOC_ALLOC_MEM_FLAGS_UNCACHED) alloc_flags |= AMDGPU_GEM_CREATE_UNCACHED; - if (sg) { - alloc_domain = AMDGPU_GEM_DOMAIN_CPU; - bo_type = ttm_bo_type_sg; - } *mem = kzalloc(sizeof(struct kgd_mem), GFP_KERNEL); if (!*mem) { ret = -ENOMEM; @@ -3571,85 +3568,6 @@ int amdgpu_amdkfd_remove_gws_from_process(void *info, void *mem) return 0; } -int amdgpu_amdkfd_copy_mem_to_mem(struct kgd_dev *kgd, struct kgd_mem *src_mem, - uint64_t src_offset, struct kgd_mem *dst_mem, - uint64_t dst_offset, uint64_t size, - struct dma_fence **f, uint64_t *actual_size) -{ - struct amdgpu_device *adev = NULL; - struct amdgpu_copy_mem src, dst; - struct ww_acquire_ctx ticket; - struct list_head list, duplicates; - struct ttm_validate_buffer resv_list[2]; - struct dma_fence *fence = NULL; - int i, r; - - if (!kgd || !src_mem || !dst_mem || !actual_size) - return -EINVAL; - - *actual_size = 0; - - adev = get_amdgpu_device(kgd); - INIT_LIST_HEAD(&list); - INIT_LIST_HEAD(&duplicates); - - src.bo = &src_mem->bo->tbo; - dst.bo = &dst_mem->bo->tbo; - src.mem = &src.bo->mem; - dst.mem = &dst.bo->mem; - src.offset = src_offset; - dst.offset = dst_offset; - - resv_list[0].bo = src.bo; - resv_list[1].bo = dst.bo; - - for (i = 0; i < 2; i++) { - resv_list[i].num_shared = 1; - list_add_tail(&resv_list[i].head, &list); - } - - r = ttm_eu_reserve_buffers(&ticket, &list, false, &duplicates); - if (r) { - pr_err("Copy buffer failed. Unable to reserve bo (%d)\n", r); - return r; - } - - /* The process to which the Source and Dest BOs belong to could be - * evicted and the BOs invalidated. So validate BOs before use - */ - r = amdgpu_amdkfd_bo_validate(src_mem->bo, src_mem->domain, false); - if (r) { - pr_err("CMA fail: SRC BO validate failed %d\n", r); - goto validate_fail; - } - - - r = amdgpu_amdkfd_bo_validate(dst_mem->bo, dst_mem->domain, false); - if (r) { - pr_err("CMA fail: DST BO validate failed %d\n", r); - goto validate_fail; - } - - - r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst, size, false, NULL, - &fence); - if (r) - pr_err("Copy buffer failed %d\n", r); - else - *actual_size = size; - if (fence) { - amdgpu_bo_fence(src_mem->bo, fence, true); - amdgpu_bo_fence(dst_mem->bo, fence, true); - } - if (f) - *f = dma_fence_get(fence); - dma_fence_put(fence); - -validate_fail: - ttm_eu_backoff_reservation(&ticket, &list); - return r; -} - /* Returns GPU-specific tiling mode information */ int amdgpu_amdkfd_get_tile_config(struct amdgpu_device *adev, struct tile_config *config) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 69f55f3993f4a..92a531c41ee28 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1168,7 +1168,7 @@ static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep, err = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu( dev->adev, args->va_addr, args->size, - pdd->drm_priv, NULL, (struct kgd_mem **) &mem, &offset, + pdd->drm_priv, (struct kgd_mem **) &mem, &offset, flags, false); if (err) @@ -1687,843 +1687,6 @@ static int kfd_ioctl_ipc_import_handle(struct file *filep, return r; } -/* Maximum number of entries for process pages array which lives on stack */ -#define MAX_PP_STACK_COUNT 16 -/* Maximum number of pages kmalloc'd to hold struct page's during copy */ -#define MAX_KMALLOC_PAGES (PAGE_SIZE * 2) -#define MAX_PP_KMALLOC_COUNT (MAX_KMALLOC_PAGES/sizeof(struct page *)) - -static void kfd_put_sg_table(struct sg_table *sg) -{ - unsigned int i; - struct scatterlist *s; - - for_each_sg(sg->sgl, s, sg->nents, i) - put_page(sg_page(s)); -} - - -/* Create a sg table for the given userptr BO by pinning its system pages - * @bo: userptr BO - * @offset: Offset into BO - * @mm/@task: mm_struct & task_struct of the process that holds the BO - * @size: in/out: desired size / actual size which could be smaller - * @sg_size: out: Size of sg table. This is ALIGN_UP(@size) - * @ret_sg: out sg table - */ -static int kfd_create_sg_table_from_userptr_bo(struct kfd_bo *bo, - int64_t offset, int cma_write, - struct mm_struct *mm, - struct task_struct *task, - uint64_t *size, - uint64_t *sg_size, - struct sg_table **ret_sg) -{ - int ret, locked = 1; - struct sg_table *sg = NULL; - unsigned int i, offset_in_page, flags = 0; - unsigned long nents, n; - unsigned long pa = (bo->cpuva + offset) & PAGE_MASK; - unsigned int cur_page = 0; - struct scatterlist *s; - uint64_t sz = *size; - struct page **process_pages; - - *sg_size = 0; - sg = kmalloc(sizeof(*sg), GFP_KERNEL); - if (!sg) - return -ENOMEM; - - offset_in_page = offset & (PAGE_SIZE - 1); - nents = (sz + offset_in_page + PAGE_SIZE - 1) / PAGE_SIZE; - - ret = sg_alloc_table(sg, nents, GFP_KERNEL); - if (unlikely(ret)) { - ret = -ENOMEM; - goto sg_alloc_fail; - } - process_pages = kmalloc_array(nents, sizeof(struct pages *), - GFP_KERNEL); - if (!process_pages) { - ret = -ENOMEM; - goto page_alloc_fail; - } - - if (cma_write) - flags = FOLL_WRITE; - locked = 1; - mmap_read_lock(mm); - n = get_user_pages_remote(mm, pa, nents, flags, process_pages, - NULL, &locked); - if (locked) - mmap_read_unlock(mm); - if (n <= 0) { - pr_err("CMA: Invalid virtual address 0x%lx\n", pa); - ret = -EFAULT; - goto get_user_fail; - } - if (n != nents) { - /* Pages pinned < requested. Set the size accordingly */ - *size = (n * PAGE_SIZE) - offset_in_page; - pr_debug("Requested %lx but pinned %lx\n", nents, n); - } - - sz = 0; - for_each_sg(sg->sgl, s, n, i) { - sg_set_page(s, process_pages[cur_page], PAGE_SIZE, - offset_in_page); - sg_dma_address(s) = page_to_phys(process_pages[cur_page]); - offset_in_page = 0; - cur_page++; - sz += PAGE_SIZE; - } - *ret_sg = sg; - *sg_size = sz; - - kfree(process_pages); - return 0; - -get_user_fail: - kfree(process_pages); -page_alloc_fail: - sg_free_table(sg); -sg_alloc_fail: - kfree(sg); - return ret; -} - -static void kfd_free_cma_bos(struct cma_iter *ci) -{ - struct cma_system_bo *cma_bo, *tmp; - - list_for_each_entry_safe(cma_bo, tmp, &ci->cma_list, list) { - struct kfd_dev *dev = cma_bo->dev; - - /* sg table is deleted by free_memory_of_gpu */ - if (cma_bo->sg) - kfd_put_sg_table(cma_bo->sg); - amdgpu_amdkfd_gpuvm_free_memory_of_gpu(dev->kgd, cma_bo->mem, NULL); - list_del(&cma_bo->list); - kfree(cma_bo); - } -} - -/* 1 second timeout */ -#define CMA_WAIT_TIMEOUT msecs_to_jiffies(1000) - -static int kfd_cma_fence_wait(struct dma_fence *f) -{ - int ret; - - ret = dma_fence_wait_timeout(f, false, CMA_WAIT_TIMEOUT); - if (likely(ret > 0)) - return 0; - if (!ret) - ret = -ETIME; - return ret; -} - -/* Put previous (old) fence @pf but it waits for @pf to signal if the context - * of the current fence @cf is different. - */ -static int kfd_fence_put_wait_if_diff_context(struct dma_fence *cf, - struct dma_fence *pf) -{ - int ret = 0; - - if (pf && cf && cf->context != pf->context) - ret = kfd_cma_fence_wait(pf); - dma_fence_put(pf); - return ret; -} - -#define MAX_SYSTEM_BO_SIZE (512*PAGE_SIZE) - -/* Create an equivalent system BO for the given @bo. If @bo is a userptr then - * create a new system BO by pinning underlying system pages of the given - * userptr BO. If @bo is in Local Memory then create an empty system BO and - * then copy @bo into this new BO. - * @bo: Userptr BO or Local Memory BO - * @offset: Offset into bo - * @size: in/out: The size of the new BO could be less than requested if all - * the pages couldn't be pinned or size > MAX_SYSTEM_BO_SIZE. This would - * be reflected in @size - * @mm/@task: mm/task to which @bo belongs to - * @cma_bo: out: new system BO - */ -static int kfd_create_cma_system_bo(struct kfd_dev *kdev, struct kfd_bo *bo, - uint64_t *size, uint64_t offset, - int cma_write, struct kfd_process *p, - struct mm_struct *mm, - struct task_struct *task, - struct cma_system_bo **cma_bo) -{ - int ret; - struct kfd_process_device *pdd = NULL; - struct cma_system_bo *cbo; - uint64_t bo_size = 0; - struct dma_fence *f; - - uint32_t flags = KFD_IOC_ALLOC_MEM_FLAGS_GTT | KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE | - KFD_IOC_ALLOC_MEM_FLAGS_NO_SUBSTITUTE; - - *cma_bo = NULL; - cbo = kzalloc(sizeof(**cma_bo), GFP_KERNEL); - if (!cbo) - return -ENOMEM; - - INIT_LIST_HEAD(&cbo->list); - if (bo->mem_type == KFD_IOC_ALLOC_MEM_FLAGS_VRAM) - bo_size = min_t(uint64_t, *size, MAX_SYSTEM_BO_SIZE); - else if (bo->cpuva) { - ret = kfd_create_sg_table_from_userptr_bo(bo, offset, - cma_write, mm, task, - size, &bo_size, - &cbo->sg); - if (ret) { - pr_err("CMA: BO create with sg failed %d\n", ret); - goto sg_fail; - } - } else { - WARN_ON(1); - ret = -EINVAL; - goto sg_fail; - } - mutex_lock(&p->mutex); - pdd = kfd_get_process_device_data(kdev, p); - if (!pdd) { - mutex_unlock(&p->mutex); - pr_err("Process device data doesn't exist\n"); - ret = -EINVAL; - goto pdd_fail; - } - - ret = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(kdev->kgd, 0ULL, bo_size, - pdd->drm_priv, cbo->sg, - &cbo->mem, NULL, flags); - mutex_unlock(&p->mutex); - if (ret) { - pr_err("Failed to create shadow system BO %d\n", ret); - goto pdd_fail; - } - - if (bo->mem_type == KFD_IOC_ALLOC_MEM_FLAGS_VRAM) { - ret = amdgpu_amdkfd_copy_mem_to_mem(kdev->kgd, bo->mem, - offset, cbo->mem, 0, - bo_size, &f, size); - if (ret) { - pr_err("CMA: Intermediate copy failed %d\n", ret); - goto copy_fail; - } - - /* Wait for the copy to finish as subsequent copy will be done - * by different device - */ - ret = kfd_cma_fence_wait(f); - dma_fence_put(f); - if (ret) { - pr_err("CMA: Intermediate copy timed out %d\n", ret); - goto copy_fail; - } - } - - cbo->dev = kdev; - *cma_bo = cbo; - - return ret; - -copy_fail: - amdgpu_amdkfd_gpuvm_free_memory_of_gpu(kdev->kgd, bo->mem, NULL); -pdd_fail: - if (cbo->sg) { - kfd_put_sg_table(cbo->sg); - sg_free_table(cbo->sg); - kfree(cbo->sg); - } -sg_fail: - kfree(cbo); - return ret; -} - -/* Update cma_iter.cur_bo with KFD BO that is assocaited with - * cma_iter.array.va_addr - */ -static int kfd_cma_iter_update_bo(struct cma_iter *ci) -{ - struct kfd_memory_range *arr = ci->array; - uint64_t va_end = arr->va_addr + arr->size - 1; - - mutex_lock(&ci->p->mutex); - ci->cur_bo = kfd_process_find_bo_from_interval(ci->p, arr->va_addr, - va_end); - mutex_unlock(&ci->p->mutex); - - if (!ci->cur_bo || va_end > ci->cur_bo->it.last) { - pr_err("CMA failed. Range out of bounds\n"); - return -EFAULT; - } - return 0; -} - -/* Advance iter by @size bytes. */ -static int kfd_cma_iter_advance(struct cma_iter *ci, unsigned long size) -{ - int ret = 0; - - ci->offset += size; - if (WARN_ON(size > ci->total || ci->offset > ci->array->size)) - return -EFAULT; - ci->total -= size; - /* If current range is copied, move to next range if available. */ - if (ci->offset == ci->array->size) { - - /* End of all ranges */ - if (!(--ci->nr_segs)) - return 0; - - ci->array++; - ci->offset = 0; - ret = kfd_cma_iter_update_bo(ci); - if (ret) - return ret; - } - ci->bo_offset = (ci->array->va_addr + ci->offset) - - ci->cur_bo->it.start; - return ret; -} - -static int kfd_cma_iter_init(struct kfd_memory_range *arr, unsigned long segs, - struct kfd_process *p, struct mm_struct *mm, - struct task_struct *task, struct cma_iter *ci) -{ - int ret; - int nr; - - if (!arr || !segs) - return -EINVAL; - - memset(ci, 0, sizeof(*ci)); - INIT_LIST_HEAD(&ci->cma_list); - ci->array = arr; - ci->nr_segs = segs; - ci->p = p; - ci->offset = 0; - ci->mm = mm; - ci->task = task; - for (nr = 0; nr < segs; nr++) - ci->total += arr[nr].size; - - /* Valid but size is 0. So copied will also be 0 */ - if (!ci->total) - return 0; - - ret = kfd_cma_iter_update_bo(ci); - if (!ret) - ci->bo_offset = arr->va_addr - ci->cur_bo->it.start; - return ret; -} - -static bool kfd_cma_iter_end(struct cma_iter *ci) -{ - if (!(ci->nr_segs) || !(ci->total)) - return true; - return false; -} - -/* Copies @size bytes from si->cur_bo to di->cur_bo BO. The function assumes - * both source and dest. BOs are userptr BOs. Both BOs can either belong to - * current process or one of the BOs can belong to a differnt - * process. @Returns 0 on success, -ve on failure - * - * @si: Source iter - * @di: Dest. iter - * @cma_write: Indicates if it is write to remote or read from remote - * @size: amount of bytes to be copied - * @copied: Return number of bytes actually copied. - */ -static int kfd_copy_userptr_bos(struct cma_iter *si, struct cma_iter *di, - bool cma_write, uint64_t size, - uint64_t *copied) -{ - int i, ret = 0, locked; - unsigned int nents, nl; - unsigned int offset_in_page; - struct page *pp_stack[MAX_PP_STACK_COUNT]; - struct page **process_pages = pp_stack; - unsigned long rva, lva = 0, flags = 0; - uint64_t copy_size, to_copy = size; - struct cma_iter *li, *ri; - - if (cma_write) { - ri = di; - li = si; - flags |= FOLL_WRITE; - } else { - li = di; - ri = si; - } - /* rva: remote virtual address. Page aligned to start page. - * rva + offset_in_page: Points to remote start address - * lva: local virtual address. Points to the start address. - * nents: computes number of remote pages to request - */ - offset_in_page = ri->bo_offset & (PAGE_SIZE - 1); - rva = (ri->cur_bo->cpuva + ri->bo_offset) & PAGE_MASK; - lva = li->cur_bo->cpuva + li->bo_offset; - - nents = (size + offset_in_page + PAGE_SIZE - 1) / PAGE_SIZE; - - copy_size = min_t(uint64_t, size, PAGE_SIZE - offset_in_page); - *copied = 0; - - if (nents > MAX_PP_STACK_COUNT) { - /* For reliability kmalloc only 2 pages worth */ - process_pages = kmalloc(min_t(size_t, MAX_KMALLOC_PAGES, - sizeof(struct pages *)*nents), - GFP_KERNEL); - - if (!process_pages) - return -ENOMEM; - } - - while (nents && to_copy) { - nl = min_t(unsigned int, MAX_PP_KMALLOC_COUNT, nents); - locked = 1; - mmap_read_lock(ri->mm); - nl = get_user_pages_remote(ri->mm, rva, nl, - flags, process_pages, NULL, - &locked); - if (locked) - mmap_read_unlock(ri->mm); - if (nl <= 0) { - pr_err("CMA: Invalid virtual address 0x%lx\n", rva); - ret = -EFAULT; - break; - } - - for (i = 0; i < nl; i++) { - unsigned int n; - void *kaddr = kmap(process_pages[i]); - - if (cma_write) { - n = copy_from_user(kaddr+offset_in_page, - (void *)lva, copy_size); - set_page_dirty(process_pages[i]); - } else { - n = copy_to_user((void *)lva, - kaddr+offset_in_page, - copy_size); - } - kunmap(kaddr); - if (n) { - ret = -EFAULT; - break; - } - to_copy -= copy_size; - if (!to_copy) - break; - lva += copy_size; - rva += (copy_size + offset_in_page); - WARN_ONCE(rva & (PAGE_SIZE - 1), - "CMA: Error in remote VA computation"); - offset_in_page = 0; - copy_size = min_t(uint64_t, to_copy, PAGE_SIZE); - } - - for (i = 0; i < nl; i++) - put_page(process_pages[i]); - - if (ret) - break; - nents -= nl; - } - - if (process_pages != pp_stack) - kfree(process_pages); - - *copied = (size - to_copy); - return ret; - -} - -static int kfd_create_kgd_mem(struct kfd_dev *kdev, uint64_t size, - struct kfd_process *p, struct kgd_mem **mem) -{ - int ret; - struct kfd_process_device *pdd = NULL; - uint32_t flags = KFD_IOC_ALLOC_MEM_FLAGS_GTT | KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE | - KFD_IOC_ALLOC_MEM_FLAGS_NO_SUBSTITUTE; - - if (!mem || !size || !p || !kdev) - return -EINVAL; - - *mem = NULL; - - mutex_lock(&p->mutex); - pdd = kfd_get_process_device_data(kdev, p); - if (!pdd) { - mutex_unlock(&p->mutex); - pr_err("Process device data doesn't exist\n"); - return -EINVAL; - } - - ret = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(kdev->kgd, 0ULL, size, - pdd->drm_priv, NULL, - mem, NULL, flags); - mutex_unlock(&p->mutex); - if (ret) { - pr_err("Failed to create shadow system BO %d\n", ret); - return -EINVAL; - } - - return 0; -} - -static int kfd_destroy_kgd_mem(struct kgd_mem *mem) -{ - if (!mem) - return -EINVAL; - - /* param adev is not used*/ - return amdgpu_amdkfd_gpuvm_free_memory_of_gpu(NULL, mem, NULL); -} - -/* Copies @size bytes from si->cur_bo to di->cur_bo starting at their - * respective offset. - * @si: Source iter - * @di: Dest. iter - * @cma_write: Indicates if it is write to remote or read from remote - * @size: amount of bytes to be copied - * @f: Return the last fence if any - * @copied: Return number of bytes actually copied. - */ -static int kfd_copy_bos(struct cma_iter *si, struct cma_iter *di, - int cma_write, uint64_t size, - struct dma_fence **f, uint64_t *copied, - struct kgd_mem **tmp_mem) -{ - int err = 0; - struct kfd_bo *dst_bo = di->cur_bo, *src_bo = si->cur_bo; - uint64_t src_offset = si->bo_offset, dst_offset = di->bo_offset; - struct kgd_mem *src_mem = src_bo->mem, *dst_mem = dst_bo->mem; - struct kfd_dev *dev = dst_bo->dev; - int d2d = 0; - - *copied = 0; - if (f) - *f = NULL; - if (src_bo->cpuva && dst_bo->cpuva) - return kfd_copy_userptr_bos(si, di, cma_write, size, copied); - - /* If either source or dest. is userptr, create a shadow system BO - * by using the underlying userptr BO pages. Then use this shadow - * BO for copy. src_offset & dst_offset are adjusted because the new BO - * is only created for the window (offset, size) requested. - * The shadow BO is created on the other device. This means if the - * other BO is a device memory, the copy will be using that device. - * The BOs are stored in cma_list for deferred cleanup. This minimizes - * fence waiting just to the last fence. - */ - if (src_bo->cpuva) { - dev = dst_bo->dev; - err = kfd_create_cma_system_bo(dev, src_bo, &size, - si->bo_offset, cma_write, - si->p, si->mm, si->task, - &si->cma_bo); - src_mem = si->cma_bo->mem; - src_offset = si->bo_offset & (PAGE_SIZE - 1); - list_add_tail(&si->cma_bo->list, &si->cma_list); - } else if (dst_bo->cpuva) { - dev = src_bo->dev; - err = kfd_create_cma_system_bo(dev, dst_bo, &size, - di->bo_offset, cma_write, - di->p, di->mm, di->task, - &di->cma_bo); - dst_mem = di->cma_bo->mem; - dst_offset = di->bo_offset & (PAGE_SIZE - 1); - list_add_tail(&di->cma_bo->list, &di->cma_list); - } else if (src_bo->dev->kgd != dst_bo->dev->kgd) { - /* This indicates that atleast on of the BO is in local mem. - * If both are in local mem of different devices then create an - * intermediate System BO and do a double copy - * [VRAM]--gpu1-->[System BO]--gpu2-->[VRAM]. - * If only one BO is in VRAM then use that GPU to do the copy - */ - if (src_bo->mem_type == KFD_IOC_ALLOC_MEM_FLAGS_VRAM && - dst_bo->mem_type == KFD_IOC_ALLOC_MEM_FLAGS_VRAM) { - dev = dst_bo->dev; - size = min_t(uint64_t, size, MAX_SYSTEM_BO_SIZE); - d2d = 1; - - if (*tmp_mem == NULL) { - if (kfd_create_kgd_mem(src_bo->dev, - MAX_SYSTEM_BO_SIZE, - si->p, - tmp_mem)) - return -EINVAL; - } - - if (amdgpu_amdkfd_copy_mem_to_mem(src_bo->dev->kgd, - src_bo->mem, si->bo_offset, - *tmp_mem, 0, - size, f, &size)) - /* tmp_mem will be freed in caller.*/ - return -EINVAL; - - kfd_cma_fence_wait(*f); - dma_fence_put(*f); - - src_mem = *tmp_mem; - src_offset = 0; - } else if (src_bo->mem_type == KFD_IOC_ALLOC_MEM_FLAGS_VRAM) - dev = src_bo->dev; - /* else already set to dst_bo->dev */ - } - - if (err) { - pr_err("Failed to create system BO %d", err); - return -EINVAL; - } - - err = amdgpu_amdkfd_copy_mem_to_mem(dev->kgd, src_mem, src_offset, - dst_mem, dst_offset, size, f, - copied); - /* The tmp_bo allocates additional memory. So it is better to wait and - * delete. Also since multiple GPUs are involved the copies are - * currently not pipelined. - */ - if (*tmp_mem && d2d) { - if (!err) { - kfd_cma_fence_wait(*f); - dma_fence_put(*f); - *f = NULL; - } - } - return err; -} - -/* Copy single range from source iterator @si to destination iterator @di. - * @si will move to next range and @di will move by bytes copied. - * @return : 0 for success or -ve for failure - * @f: The last fence if any - * @copied: out: number of bytes copied - */ -static int kfd_copy_single_range(struct cma_iter *si, struct cma_iter *di, - bool cma_write, struct dma_fence **f, - uint64_t *copied, struct kgd_mem **tmp_mem) -{ - int err = 0; - uint64_t copy_size, n; - uint64_t size = si->array->size; - struct kfd_bo *src_bo = si->cur_bo; - struct dma_fence *lfence = NULL; - - if (!src_bo || !di || !copied) - return -EINVAL; - *copied = 0; - if (f) - *f = NULL; - - while (size && !kfd_cma_iter_end(di)) { - struct dma_fence *fence = NULL; - - copy_size = min(size, (di->array->size - di->offset)); - - err = kfd_copy_bos(si, di, cma_write, copy_size, - &fence, &n, tmp_mem); - if (err) { - pr_err("CMA %d failed\n", err); - break; - } - - if (fence) { - err = kfd_fence_put_wait_if_diff_context(fence, - lfence); - lfence = fence; - if (err) - break; - } - - size -= n; - *copied += n; - err = kfd_cma_iter_advance(si, n); - if (err) - break; - err = kfd_cma_iter_advance(di, n); - if (err) - break; - } - - if (f) - *f = dma_fence_get(lfence); - dma_fence_put(lfence); - - return err; -} - -static int kfd_ioctl_cross_memory_copy(struct file *filep, - struct kfd_process *local_p, void *data) -{ - struct kfd_ioctl_cross_memory_copy_args *args = data; - struct kfd_memory_range *src_array, *dst_array; - struct kfd_process *remote_p; - struct task_struct *remote_task; - struct mm_struct *remote_mm; - struct pid *remote_pid; - struct dma_fence *lfence = NULL; - uint64_t copied = 0, total_copied = 0; - struct cma_iter di, si; - const char *cma_op; - int err = 0; - struct kgd_mem *tmp_mem = NULL; - - /* Check parameters */ - if (args->src_mem_range_array == 0 || args->dst_mem_range_array == 0 || - args->src_mem_array_size == 0 || args->dst_mem_array_size == 0) - return -EINVAL; - args->bytes_copied = 0; - - /* Allocate space for source and destination arrays */ - src_array = kmalloc_array((args->src_mem_array_size + - args->dst_mem_array_size), - sizeof(struct kfd_memory_range), - GFP_KERNEL); - if (!src_array) - return -ENOMEM; - dst_array = &src_array[args->src_mem_array_size]; - - if (copy_from_user(src_array, (void __user *)args->src_mem_range_array, - args->src_mem_array_size * - sizeof(struct kfd_memory_range))) { - err = -EFAULT; - goto copy_from_user_fail; - } - if (copy_from_user(dst_array, (void __user *)args->dst_mem_range_array, - args->dst_mem_array_size * - sizeof(struct kfd_memory_range))) { - err = -EFAULT; - goto copy_from_user_fail; - } - - /* Get remote process */ - remote_pid = find_get_pid(args->pid); - if (!remote_pid) { - pr_err("Cross mem copy failed. Invalid PID %d\n", args->pid); - err = -ESRCH; - goto copy_from_user_fail; - } - - remote_task = get_pid_task(remote_pid, PIDTYPE_PID); - if (!remote_pid) { - pr_err("Cross mem copy failed. Invalid PID or task died %d\n", - args->pid); - err = -ESRCH; - goto get_pid_task_fail; - } - - /* Check access permission */ - remote_mm = mm_access(remote_task, PTRACE_MODE_ATTACH_REALCREDS); - if (!remote_mm || IS_ERR(remote_mm)) { - err = IS_ERR(remote_mm) ? PTR_ERR(remote_mm) : -ESRCH; - if (err == -EACCES) { - pr_err("Cross mem copy failed. Permission error\n"); - err = -EPERM; - } else - pr_err("Cross mem copy failed. Invalid task %d\n", - err); - goto mm_access_fail; - } - - remote_p = kfd_get_process(remote_task); - if (IS_ERR(remote_p)) { - pr_err("Cross mem copy failed. Invalid kfd process %d\n", - args->pid); - err = -EINVAL; - goto kfd_process_fail; - } - /* Initialise cma_iter si & @di with source & destination range. */ - if (KFD_IS_CROSS_MEMORY_WRITE(args->flags)) { - cma_op = "WRITE"; - pr_debug("CMA WRITE: local -> remote\n"); - err = kfd_cma_iter_init(dst_array, args->dst_mem_array_size, - remote_p, remote_mm, remote_task, &di); - if (err) - goto kfd_process_fail; - err = kfd_cma_iter_init(src_array, args->src_mem_array_size, - local_p, current->mm, current, &si); - if (err) - goto kfd_process_fail; - } else { - cma_op = "READ"; - pr_debug("CMA READ: remote -> local\n"); - - err = kfd_cma_iter_init(dst_array, args->dst_mem_array_size, - local_p, current->mm, current, &di); - if (err) - goto kfd_process_fail; - err = kfd_cma_iter_init(src_array, args->src_mem_array_size, - remote_p, remote_mm, remote_task, &si); - if (err) - goto kfd_process_fail; - } - - /* Copy one si range at a time into di. After each call to - * kfd_copy_single_range() si will move to next range. di will be - * incremented by bytes copied - */ - while (!kfd_cma_iter_end(&si) && !kfd_cma_iter_end(&di)) { - struct dma_fence *fence = NULL; - - err = kfd_copy_single_range(&si, &di, - KFD_IS_CROSS_MEMORY_WRITE(args->flags), - &fence, &copied, &tmp_mem); - total_copied += copied; - - if (err) - break; - - /* Release old fence if a later fence is created. If no - * new fence is created, then keep the preivous fence - */ - if (fence) { - err = kfd_fence_put_wait_if_diff_context(fence, - lfence); - lfence = fence; - if (err) - break; - } - } - - /* Wait for the last fence irrespective of error condition */ - if (lfence) { - err = kfd_cma_fence_wait(lfence); - dma_fence_put(lfence); - if (err) - pr_err("CMA %s failed. BO timed out\n", cma_op); - } - - if (tmp_mem) - kfd_destroy_kgd_mem(tmp_mem); - - kfd_free_cma_bos(&si); - kfd_free_cma_bos(&di); - -kfd_process_fail: - mmput(remote_mm); -mm_access_fail: - put_task_struct(remote_task); -get_pid_task_fail: - put_pid(remote_pid); -copy_from_user_fail: - kfree(src_array); - - /* An error could happen after partial copy. In that case this will - * reflect partial amount of bytes copied - */ - args->bytes_copied = total_copied; - return err; -} - static int kfd_ioctl_export_dmabuf(struct file *filep, struct kfd_process *p, void *data) { @@ -4247,9 +3410,6 @@ static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = { AMDKFD_IOCTL_DEF(AMDKFD_IOC_RLC_SPM, kfd_ioctl_rlc_spm, 0), - - AMDKFD_IOCTL_DEF(AMDKFD_IOC_CROSS_MEMORY_COPY, - kfd_ioctl_cross_memory_copy, 0), }; static long kfd_ioctl(struct file *filep, unsigned int cmd, unsigned long arg) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index ff4b1d92b086f..c16abbe5f6314 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -402,38 +402,6 @@ struct kfd_bo { unsigned int mem_type; }; -struct cma_system_bo { - struct kgd_mem *mem; - struct sg_table *sg; - struct kfd_dev *dev; - struct list_head list; -}; - -/* Similar to iov_iter */ -struct cma_iter { - /* points to current entry of range array */ - struct kfd_memory_range *array; - /* total number of entries in the initial array */ - unsigned long nr_segs; - /* total amount of data pointed by kfd array*/ - unsigned long total; - /* offset into the entry pointed by cma_iter.array */ - unsigned long offset; - struct kfd_process *p; - struct mm_struct *mm; - struct task_struct *task; - /* current kfd_bo associated with cma_iter.array.va_addr */ - struct kfd_bo *cur_bo; - /* offset w.r.t cur_bo */ - unsigned long bo_offset; - /* If cur_bo is a userptr BO, then a shadow system BO is created - * using its underlying pages. cma_bo holds this BO. cma_list is a - * list cma_bos created in one session - */ - struct cma_system_bo *cma_bo; - struct list_head cma_list; -}; - enum kfd_mempool { KFD_MEMPOOL_SYSTEM_CACHEABLE = 1, KFD_MEMPOOL_SYSTEM_WRITECOMBINE = 2, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 9baf37567d9a0..f6fb824acc54d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -716,7 +716,7 @@ static int kfd_process_alloc_gpuvm(struct kfd_process_device *pdd, int err; err = amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(kdev->adev, gpu_va, size, - pdd->drm_priv, NULL, &mem, NULL, + pdd->drm_priv, mem, NULL, flags, false); if (err) goto err_alloc_mem; diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h index 3829644bd060b..4522660ee4003 100644 --- a/include/uapi/linux/kfd_ioctl.h +++ b/include/uapi/linux/kfd_ioctl.h @@ -754,37 +754,6 @@ struct kfd_ioctl_ipc_import_handle_args { __u32 flags; /* from KFD */ }; -struct kfd_memory_range { - __u64 va_addr; - __u64 size; -}; - -/* flags definitions - * BIT0: 0: read operation, 1: write operation. - * This also identifies if the src or dst array belongs to remote process - */ -#define KFD_CROSS_MEMORY_RW_BIT (1 << 0) -#define KFD_SET_CROSS_MEMORY_READ(flags) (flags &= ~KFD_CROSS_MEMORY_RW_BIT) -#define KFD_SET_CROSS_MEMORY_WRITE(flags) (flags |= KFD_CROSS_MEMORY_RW_BIT) -#define KFD_IS_CROSS_MEMORY_WRITE(flags) (flags & KFD_CROSS_MEMORY_RW_BIT) - -struct kfd_ioctl_cross_memory_copy_args { - /* to KFD: Process ID of the remote process */ - __u32 pid; - /* to KFD: See above definition */ - __u32 flags; - /* to KFD: Source GPU VM range */ - __u64 src_mem_range_array; - /* to KFD: Size of above array */ - __u64 src_mem_array_size; - /* to KFD: Destination GPU VM range */ - __u64 dst_mem_range_array; - /* to KFD: Size of above array */ - __u64 dst_mem_array_size; - /* from KFD: Total amount of bytes copied */ - __u64 bytes_copied; -}; - /* Guarantee host access to memory */ #define KFD_IOCTL_SVM_FLAG_HOST_ACCESS 0x00000001 /* Fine grained coherency between all devices with access */ @@ -1730,11 +1699,7 @@ struct kfd_ioctl_dbg_trap_args { #define AMDKFD_IOC_RLC_SPM \ AMDKFD_IOWR(0x84, struct kfd_ioctl_spm_args) -#define AMDKFD_IOC_CROSS_MEMORY_COPY \ - AMDKFD_IOWR(0x83, struct kfd_ioctl_cross_memory_copy_args) - #define AMDKFD_COMMAND_START_2 0x80 #define AMDKFD_COMMAND_END_2 0x85 - #endif From 26251a826b15d6cbd164f0f01dee5bbe99fcce81 Mon Sep 17 00:00:00 2001 From: Guchun Chen Date: Fri, 5 Aug 2022 17:10:44 +0800 Subject: [PATCH 0733/1868] drm/amdgpu: relax the check in amdgpu_device_is_peer_accessible To support p2p feature on old kernels without defining CONFIG_PCI_P2PDMA, amdgpu_device_is_peer_accessible needs to return true in such scenario. So relax the requirement from upstream. Suggested-by: Ramesh Errabolu Suggested-by: Felix Kuehling Signed-off-by: Leslie Shi Signed-off-by: Guchun Chen Reviewed-by: Ramesh Errabolu --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 637b16282a876..02d9bc6b07ba6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -6184,22 +6184,21 @@ static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev) bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, struct amdgpu_device *peer_adev) { -#ifdef CONFIG_HSA_AMD_P2P + bool p2p_access = true; uint64_t address_mask = peer_adev->dev->dma_mask ? ~*peer_adev->dev->dma_mask : ~((1ULL << 32) - 1); resource_size_t aper_limit = adev->gmc.aper_base + adev->gmc.aper_size - 1; - bool p2p_access = +#ifdef CONFIG_PCI_P2PDMA + p2p_access = !adev->gmc.xgmi.connected_to_cpu && !(pci_p2pdma_distance(adev->pdev, peer_adev->dev, false) < 0); +#endif return pcie_p2p && p2p_access && (adev->gmc.visible_vram_size && adev->gmc.real_vram_size == adev->gmc.visible_vram_size && !(adev->gmc.aper_base & address_mask || aper_limit & address_mask)); -#else - return false; -#endif } int amdgpu_device_baco_enter(struct drm_device *dev) From 4a00b0de801485cbe9781dc516e05d0dd8984bb3 Mon Sep 17 00:00:00 2001 From: Guchun Chen Date: Mon, 8 Aug 2022 10:06:03 +0800 Subject: [PATCH 0734/1868] drm/amdgpu: drop compiler guard for pcie_p2p CONFIG_HSA_AMD_P2P is not needed as a build option for pcie_p2p, as p2p feature needs to be always supported on dkms branch, otherwise, intree build fails once CONFIG_HSA_AMD_P2P is not defined. Also drop redundant extern of pcie_p2p in amdgpu.h. Fixes: af428201b20e("drm/amdgpu: relax the check in amdgpu_device_is_peer_accessible") Signed-off-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 -- 2 files changed, 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 49896e73c5aa3..7bde44e0d5fc0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -245,9 +245,6 @@ static const bool __maybe_unused debug_evictions; /* = false */ static const bool __maybe_unused no_system_mem_limit; static const int __maybe_unused halt_if_hws_hang; #endif -#ifdef CONFIG_HSA_AMD_P2P -extern bool pcie_p2p; -#endif extern int amdgpu_tmz; extern int amdgpu_reset_method; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 6ce10f03e9cbb..f6718a3a7ce45 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -863,11 +863,9 @@ module_param_named(mtype_local, amdgpu_mtype_local, int, 0444); * DOC: pcie_p2p (bool) * Enable PCIe P2P (requires large-BAR). Default value: true (on) */ -#ifdef CONFIG_HSA_AMD_P2P bool pcie_p2p = true; module_param(pcie_p2p, bool, 0444); MODULE_PARM_DESC(pcie_p2p, "Enable PCIe P2P (requires large-BAR). (N = off, Y = on(default))"); -#endif /** * DOC: dcfeaturemask (uint) From 015d762615b23f9ff117b7a4c2a47e439c575f59 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 8 Aug 2022 10:49:08 +0800 Subject: [PATCH 0735/1868] drm/amdgpu: enable CONFIG_HSA_AMD_P2P when PCI_P2PDMA and DMABUF_MOVENOTIFY are set Suggested-by: Felix Kuehling Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/dkms/Makefile | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index a00c632cc588f..ff7758499d54d 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -167,9 +167,11 @@ endif export CONFIG_DRM_AMD_DC_HDCP=y subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_HDCP -ifeq ($(call _is_kcl_macro_defined,HAVE_LINUX_PCI_P2PDMA_H),y) -export CONFIG_HSA_AMD_P2P=y -subdir-ccflags-y += -DCONFIG_HSA_AMD_P2P +ifeq (y,$(CONFIG_PCI_P2PDMA)) + ifeq (y,$(CONFIG_DMABUF_MOVENOTIFY)) + export CONFIG_HSA_AMD_P2P=y + subdir-ccflags-y += -DCONFIG_HSA_AMD_P2P + endif endif # Trying to enable DCN2/3 with core2 optimizations will result in From efa5839b20d0701f70f42b5b6c83d61148e4c275 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Mon, 8 Aug 2022 17:38:51 -0400 Subject: [PATCH 0736/1868] drm/amdkfd: Fix VRAM attachment Use kfd_mem_attach_vram_bo instead of kfd_mem_attach_dmabuf. Signed-off-by: Felix Kuehling Reviewed-by: Ramesh Errabolu --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index bea20c28404b7..f7a76b95b9278 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -983,9 +983,8 @@ static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem, if (ret) goto unwind; #ifdef AMDKCL_AMDGPU_DMABUF_OPS - /* Enable acces to GTT and VRAM BOs of peer devices */ - } else if (mem->domain == AMDGPU_GEM_DOMAIN_GTT || - mem->domain == AMDGPU_GEM_DOMAIN_VRAM) { + /* Enable acces to GTT BOs of peer devices */ + } else if (mem->domain == AMDGPU_GEM_DOMAIN_GTT) { attachment[i]->type = KFD_MEM_ATT_DMABUF; ret = kfd_mem_attach_dmabuf(adev, mem, &bo[i]); if (ret) From fd93f2bd76627fa3fbeb9b4548bd2750e821aa1d Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Mon, 8 Aug 2022 19:51:45 -0400 Subject: [PATCH 0737/1868] drm/amdkfd: Fix DEVICE_PRIVATE page leak on 5.18 commit 27674ef6c73f ("mm: remove the extra ZONE_DEVICE struct page refcount") removed an extra reference count for ZONE_DEVICE pages. This requires a corresponding driver change (which was part of that patch). For DKMS builds, conditionally get a page reference only on old kernels without this patch. CONFIG_DEV_PAGEMAP_OPS is a suitable indicator, because this option was removed by the patch, and was previously selected by CONFIG_DEVICE_PRIVATE. Signed-off-by: Felix Kuehling Reviewed-by: Alex Sierra --- drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c index 185e6ae36d682..c449bb9ea5ba1 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@ -225,7 +225,9 @@ svm_migrate_get_vram_page(struct svm_range *prange, unsigned long pfn) VM_BUG_ON_PAGE(page_ref_count(page), page); init_page_count(page); #else +#if IS_ENABLED(CONFIG_DEV_PAGEMAP_OPS) get_page(page); +#endif #endif lock_page(page); } From 9d8906aff7659094105d7ea1886a7c5e3903bc6b Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Tue, 9 Aug 2022 17:10:52 -0400 Subject: [PATCH 0738/1868] drm/amdkfd: Remove useless #ifdefs Both branches are exactly the same, so the #ifdefs are no longer needed. Fixes: 90fbc2dc692e ("drm/amdkcl: cleanup kcl_bitmap_xxx") CC: Flora Cui Signed-off-by: Felix Kuehling Reviewed-by: Flora Cui Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 9 --------- 1 file changed, 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c index d5a26737d52a0..a9dba9a0b6029 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c @@ -171,13 +171,8 @@ void kfd_process_dequeue_from_all_devices(struct kfd_process *p) int pqm_init(struct process_queue_manager *pqm, struct kfd_process *p) { INIT_LIST_HEAD(&pqm->queues); -#if defined(HAVE_BITMAP_FUNCS) pqm->queue_slot_bitmap = bitmap_zalloc(KFD_MAX_NUM_OF_QUEUES_PER_PROCESS, GFP_KERNEL); -#else - pqm->queue_slot_bitmap = bitmap_zalloc(KFD_MAX_NUM_OF_QUEUES_PER_PROCESS, - GFP_KERNEL); -#endif if (!pqm->queue_slot_bitmap) return -ENOMEM; pqm->process = p; @@ -233,11 +228,7 @@ void pqm_uninit(struct process_queue_manager *pqm) kfree(pqn); } -#if defined(HAVE_BITMAP_FUNCS) bitmap_free(pqm->queue_slot_bitmap); -#else - bitmap_free(pqm->queue_slot_bitmap); -#endif pqm->queue_slot_bitmap = NULL; } From f526da2b6a65dfc1837cc46a6be0eb847149c3cc Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Mon, 8 Aug 2022 20:16:39 -0400 Subject: [PATCH 0739/1868] drm/amd/dkms: Bump package version to 5.18.0 DKMS packages built from staging should have verion 5.18, not 5.16. Signed-off-by: Felix Kuehling Reviewed-by: Hawking Zhang Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/configure.ac | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/configure.ac b/drivers/gpu/drm/amd/dkms/configure.ac index 3feca735c2140..eada36c6a9f53 100644 --- a/drivers/gpu/drm/amd/dkms/configure.ac +++ b/drivers/gpu/drm/amd/dkms/configure.ac @@ -1,4 +1,4 @@ -AC_INIT(amdgpu-dkms, 5.16.0) +AC_INIT(amdgpu-dkms, 5.18.0) AC_LANG(C) AC_CONFIG_AUX_DIR([config]) From bcbd763c34276cfe133a7e8934feb8ff999ba8e8 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 17 Aug 2022 17:02:02 +0800 Subject: [PATCH 0740/1868] drm/amdkcl: Bump dkms package version to 5.19.0 Bump dkms package version to 5.19.0 Signed-off-by: Ma Jun Change-Id: Ia94eea0c5d92a3e9673e069223f86f4811c7a6ee --- drivers/gpu/drm/amd/dkms/configure.ac | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/configure.ac b/drivers/gpu/drm/amd/dkms/configure.ac index eada36c6a9f53..fb89f280535c4 100644 --- a/drivers/gpu/drm/amd/dkms/configure.ac +++ b/drivers/gpu/drm/amd/dkms/configure.ac @@ -1,4 +1,4 @@ -AC_INIT(amdgpu-dkms, 5.18.0) +AC_INIT(amdgpu-dkms, 5.19.0) AC_LANG(C) AC_CONFIG_AUX_DIR([config]) From f10b813b9395f8ec1e0206d58e1bc6685b9a841b Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 6 Jul 2022 09:56:55 +0800 Subject: [PATCH 0741/1868] drm/amdkcl: Fix the CFLAGS_xx process script Only remove the AMDDALPATH with prefix CFLAGS_ Signed-off-by: Ma Jun Reviewed-by: Flora Cui Change-Id: I9be3fe482ccb1da0226572e2726c025d5487205c --- drivers/gpu/drm/amd/dkms/pre-build.sh | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index 81a0d5da5c8bd..07df3f07ea532 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -67,10 +67,11 @@ done export KERNELVER (cd $SRC && ./configure) -# rename CFLAGS_target.o to CFLAGS_target.o +# rename CFLAGS_target.o / CFLAGS_REMOVE_ to CFLAGS_target.o +# for kernel version < 5.3 if ! grep -q 'define HAVE_AMDKCL_FLAGS_TAKE_PATH' $SRC/config/config.h; then for file in $(grep -rl 'CFLAGS_' amd/display/); do - sed -i 's|$(AMDDALPATH)/.*/\(.*\.o\)|\1|' $file + sed -i 's|\(CFLAGS_[A-Z_]*\)$(AMDDALPATH)/.*/\(.*\.o\)|\1\2|' $file done fi From 273df17af08b74ef538814bb1f9fc144811e1b2e Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Fri, 8 Jul 2022 14:09:09 +0800 Subject: [PATCH 0742/1868] drm/amdkcl: Fix the bug when get gcc version Fix the bug when get gcc version Signed-off-by: Ma Jun Reviewed-by: Flora Cui Reviewed-by: Guchun Chen Change-Id: If49e6bb007c382cdd1e35e0597a4d9e77287f099 --- drivers/gpu/drm/amd/dkms/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index ff7758499d54d..64171883b4bb2 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -19,7 +19,7 @@ endif ifdef CONFIG_CC_IS_GCC GCCMAJ=$(shell echo __GNUC__ | $(CC) -E -x c - | tail -n 1) GCCMIN=$(shell echo __GNUC_MINOR__ | $(CC) -E -x c - | tail -n 1) -GCCPAT=$(shell echo __GNUC_MINOR__ | $(CC) -E -x c - | tail -n 1) +GCCPAT=$(shell echo __GNUC_PATCHLEVEL__ | $(CC) -E -x c - | tail -n 1) # CONFIG_GCC_VERSION returns x.xx.xx as the version format GCCSTR=$(shell printf "%d%02d%02d" $(GCCMAJ) $(GCCMIN) $(GCCPAT)) ifeq ($(shell [ $(CONFIG_GCC_VERSION) -ne $(GCCSTR) ] && echo y), y) From ca32b72c2c9e28c534010357472cfa5e92140a20 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Fri, 8 Jul 2022 10:46:54 +0800 Subject: [PATCH 0743/1868] drm/amdkcl: Export gcc related config Check and export CONFIG_CC_IS_GCC and CONFIG_GCC_VERSION for the kernels which has no these config. Signed-off-by: Ma Jun Reviewed-by: Flora Cui Change-Id: Id2f5da8b515a11bde8e40b8cc4a694b0b249ab47 --- drivers/gpu/drm/amd/dkms/Makefile | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 64171883b4bb2..6178008b48339 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -16,16 +16,22 @@ ifeq ($(call _is_kcl_macro_defined,HAVE_DMA_RESV_SEQ),n) $(error dma_resv->seq is missing., exit...) endif -ifdef CONFIG_CC_IS_GCC +ifeq ($(CC), gcc) GCCMAJ=$(shell echo __GNUC__ | $(CC) -E -x c - | tail -n 1) GCCMIN=$(shell echo __GNUC_MINOR__ | $(CC) -E -x c - | tail -n 1) GCCPAT=$(shell echo __GNUC_PATCHLEVEL__ | $(CC) -E -x c - | tail -n 1) # CONFIG_GCC_VERSION returns x.xx.xx as the version format GCCSTR=$(shell printf "%d%02d%02d" $(GCCMAJ) $(GCCMIN) $(GCCPAT)) +ifdef CONFIG_CC_IS_GCC ifeq ($(shell [ $(CONFIG_GCC_VERSION) -ne $(GCCSTR) ] && echo y), y) $(warning "Local GCC version $(GCCSTR) does not match kernel compiler GCC version $(CONFIG_GCC_VERSION)") $(warning "This may cause unexpected and hard-to-isolate compiler-related issues") endif +else +export CONFIG_CC_IS_GCC=y +export CONFIG_GCC_VERSION=$(GCCSTR) +$(warning "CONFIG_CC_IS_GCC is not defined. Let's export it with version $(CONFIG_GCC_VERSION)") +endif endif DRM_VER=$(shell sed -n 's/^RHEL_DRM_VERSION = \(.*\)/\1/p' $(srctree)/Makefile) From 15b7c3e8db80df98ccbad7a6124171d85e81939e Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Tue, 16 Aug 2022 16:50:39 +0800 Subject: [PATCH 0744/1868] drm/amdkcl: fix ttm debugfs dir name Signed-off-by: Flora Cui Reviewed-by: Leslie Shi --- drivers/gpu/drm/ttm/ttm_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/ttm/ttm_device.c b/drivers/gpu/drm/ttm/ttm_device.c index 434cf0258000e..9a0b0b051cb32 100644 --- a/drivers/gpu/drm/ttm/ttm_device.c +++ b/drivers/gpu/drm/ttm/ttm_device.c @@ -77,7 +77,7 @@ static int ttm_global_init(void) si_meminfo(&si); - ttm_debugfs_root = debugfs_create_dir("ttm", NULL); + ttm_debugfs_root = debugfs_create_dir(TTM_NAME, NULL); if (IS_ERR(ttm_debugfs_root)) { ttm_debugfs_root = NULL; } From 2734e525ab4bb88146d32ccc0125e90a8cc9d352 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 15 Aug 2022 22:07:12 +0800 Subject: [PATCH 0745/1868] drm/amdkcl: fake macro for_each_cpu_wrap and function cpumask_next_wrap It's caused by 78231f639e2eec3f14de8bb8309f459413ca86b4 drm/amdkfd: Try to schedule bottom half on same core Signed-off-by: Asher Song Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_cpumask.c | 38 +++++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_cpumask.h | 43 ++++++++++++++++++++++++ 4 files changed, 83 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_cpumask.c create mode 100644 include/kcl/kcl_cpumask.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index d0ccd6f534348..e9d5160622e08 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -13,7 +13,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o kcl_ftrace.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_fs_read_write.o kcl_drm_aperture.o \ kcl_drm_drv.o kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o \ - kcl_mce_amd.o kcl_workqueue.o + kcl_mce_amd.o kcl_workqueue.o kcl_cpumask.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_cpumask.c b/drivers/gpu/drm/amd/amdkcl/kcl_cpumask.c new file mode 100644 index 0000000000000..fe36b386ff52b --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_cpumask.c @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0-only + +#include +#ifndef for_each_cpu_wrap +/* copied from lib/cpumask.c +/** + * cpumask_next_wrap - helper to implement for_each_cpu_wrap + * @n: the cpu prior to the place to search + * @mask: the cpumask pointer + * @start: the start point of the iteration + * @wrap: assume @n crossing @start terminates the iteration + * + * Returns >= nr_cpu_ids on completion + * + * Note: the @wrap argument is required for the start condition when + * we cannot assume @start is set in @mask. + */ +int _kcl_cpumask_next_wrap(int n, const struct cpumask *mask, int start, bool wrap) +{ + int next; + +again: + next = cpumask_next(n, mask); + + if (wrap && n < start && next >= start) { + return nr_cpumask_bits; + + } else if (next >= nr_cpumask_bits) { + wrap = true; + n = -1; + goto again; + } + + return next; +} +EXPORT_SYMBOL(_kcl_cpumask_next_wrap); +#endif + diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 42072db6869d3..251fee9e35fca 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -95,5 +95,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_cpumask.h b/include/kcl/kcl_cpumask.h new file mode 100644 index 0000000000000..aee779d6ec5f2 --- /dev/null +++ b/include/kcl/kcl_cpumask.h @@ -0,0 +1,43 @@ +/*SPDX-License-Identifier: GPL-2.0*/ + +#include +#include +#include +#include +#include + +#ifndef for_each_cpu_wrap + +extern int _kcl_cpumask_next_wrap(int n, const struct cpumask *mask, + int start, bool wrap); + +static inline +int cpumask_next_wrap(int n, const struct cpumask *mask, + int start, bool wrap) +{ +return _kcl_cpumask_next_wrap(n, mask, start, wrap); +} + +/* Copied from include/linux/cpumask.h */ +#if NR_CPUS == 1 +#define for_each_cpu_wrap(cpu, mask, start) \ + for ((cpu) = 0; (cpu) < 1; (cpu)++, (void)mask, (void)(start)) +#else +/** + * for_each_cpu_wrap - iterate over every cpu in a mask, starting at a specified location + * @cpu: the (optionally unsigned) integer iterator + * @mask: the cpumask pointer + * @start: the start location + * + * The implementation does not assume any bit in @mask is set (including @start). + * + * After the loop, cpu is >= nr_cpu_ids. + */ +#define for_each_cpu_wrap(cpu, mask, start) \ + for ((cpu) = cpumask_next_wrap((start)-1, (mask), (start), false); \ + (cpu) < nr_cpumask_bits; \ + (cpu) = cpumask_next_wrap((cpu), (mask), (start), true)) + +#endif +#endif + From b88a83736bf16c26907d498b411c049fb763f1e7 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 18 Aug 2022 16:42:51 +0800 Subject: [PATCH 0746/1868] drm/amdkcl: Optimize the make command of dkms The parameter -j${num_cpu_cores} will be added by dkms, so remove this param here. Signed-off-by: Ma Jun Reviewed-by: Guchun Chen Reviewed-by: Flora Cui Change-Id: I4346afa99a0a06126bb21873e5c9d0c9c5059131 --- drivers/gpu/drm/amd/dkms/dkms.conf | 13 +------------ 1 file changed, 1 insertion(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/dkms.conf b/drivers/gpu/drm/amd/dkms/dkms.conf index bd79232132f60..a4fde02caa219 100644 --- a/drivers/gpu/drm/amd/dkms/dkms.conf +++ b/drivers/gpu/drm/amd/dkms/dkms.conf @@ -26,18 +26,7 @@ BUILT_MODULE_NAME[4]="amddrm_ttm_helper" BUILT_MODULE_LOCATION[4]="." DEST_MODULE_LOCATION[4]="/kernel/drivers/gpu/drm" -# Find out how many CPU cores can be use if we pass appropriate -j option to make. -# DKMS could use all cores on multicore systems to build the kernel module. -num_cpu_cores() -{ - if [ -x /usr/bin/nproc ]; then - nproc - else - echo "1" - fi -} - -MAKE[0]="make -j$(num_cpu_cores) TTM_NAME=${BUILT_MODULE_NAME[1]} \ +MAKE[0]="make TTM_NAME=${BUILT_MODULE_NAME[1]} \ SCHED_NAME=${BUILT_MODULE_NAME[3]} \ -C $kernel_source_dir \ M=$dkms_tree/$module/$module_version/build" From 8425db56896c7ef67d220e39259984f7e941d07c Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Tue, 23 Aug 2022 17:01:32 +0800 Subject: [PATCH 0747/1868] drm/amdkcl: Fix the compile error of drm_for_each_fb Fix the redefintion error of drm_for_each_fb. Because the drm_framebuffer.h is not include in drm_crtc.h anymore. Signed-off-by: Ma Jun Change-Id: Ie68880609d4ceba4aaddbf074b2682d0fc0ee577 --- include/kcl/kcl_drm_crtc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/kcl/kcl_drm_crtc.h b/include/kcl/kcl_drm_crtc.h index 2f01179d0c2b1..3911fa0faaa04 100644 --- a/include/kcl/kcl_drm_crtc.h +++ b/include/kcl/kcl_drm_crtc.h @@ -48,9 +48,9 @@ #ifndef KCL_KCL_DRM_CRTC_H #define KCL_KCL_DRM_CRTC_H -#include #include #include +#include /* Copied from include/drm/drm_mode.h */ #ifndef DRM_MODE_ROTATE_0 From 8873c8cb928a5050cfae2139c46e4b5292082ccc Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 14 Jul 2022 16:40:51 +0800 Subject: [PATCH 0748/1868] drm/amdkcl: fix redefined pr_fmt warning Signed-off-by: Leslie Shi --- drivers/gpu/drm/ttm/ttm_device.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/ttm/ttm_device.c b/drivers/gpu/drm/ttm/ttm_device.c index 9a0b0b051cb32..384eac25ccae7 100644 --- a/drivers/gpu/drm/ttm/ttm_device.c +++ b/drivers/gpu/drm/ttm/ttm_device.c @@ -25,8 +25,6 @@ * Authors: Christian König */ -#define pr_fmt(fmt) "[TTM DEVICE] " fmt - #include #include @@ -37,6 +35,11 @@ #include "ttm_module.h" +#ifdef pr_fmt +#undef pr_fmt +#endif +#define pr_fmt(fmt) "[TTM DEVICE] " fmt + /* * ttm_global_mutex - protecting the global state */ From dff4f959d1a51a61e5eabfacccf9cd1f1a03813b Mon Sep 17 00:00:00 2001 From: Rajneesh Bhardwaj Date: Fri, 19 Aug 2022 21:40:12 -0400 Subject: [PATCH 0749/1868] drm/amdkfd: Fix the criu restore regression The logic to create the IDR handles was broken, this fixes the issue seen during criu restore. Signed-off-by: Rajneesh Bhardwaj --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 92a531c41ee28..845accb8c651a 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -2463,6 +2463,7 @@ static int criu_restore_memory_of_gpu(struct kfd_process_device *pdd, int idr_handle; int ret; const bool criu_resume = true; + unsigned int mem_type = 0; u64 offset; if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL) { @@ -2499,13 +2500,22 @@ static int criu_restore_memory_of_gpu(struct kfd_process_device *pdd, bo_bucket->size, bo_bucket->addr, offset); /* Restore previous IDR handle */ - pr_debug("Restoring old IDR handle for the BO"); - idr_handle = idr_alloc(&pdd->alloc_idr, *kgd_mem, bo_priv->idr_handle, - bo_priv->idr_handle + 1, GFP_KERNEL); + mem_type = bo_bucket->alloc_flags & (KFD_IOC_ALLOC_MEM_FLAGS_VRAM | + KFD_IOC_ALLOC_MEM_FLAGS_GTT | + KFD_IOC_ALLOC_MEM_FLAGS_USERPTR | + KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL | + KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP); + + idr_handle = kfd_process_device_create_obj_handle(pdd, *kgd_mem, + bo_bucket->addr, + bo_bucket->size, + 0, mem_type, + bo_priv->idr_handle); if (idr_handle < 0) { pr_err("Could not allocate idr\n"); - amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, *kgd_mem, pdd->drm_priv, + amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, *kgd_mem, + pdd->drm_priv, NULL); return -ENOMEM; } From 29aadd854f8657564f96c7615cc75cfe9fb296ba Mon Sep 17 00:00:00 2001 From: Rajneesh Bhardwaj Date: Mon, 22 Aug 2022 12:17:43 -0400 Subject: [PATCH 0750/1868] drm/amdkfd: Fix some coding indentation Recently introduced patch to fix a criu regression due to a rebase, had some off indentation and extra newline. Fix that to stay close to the upstream version. Reviewed-by: Felix Kuehling Signed-off-by: Rajneesh Bhardwaj --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 845accb8c651a..1d6c0457fbffc 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -2504,7 +2504,7 @@ static int criu_restore_memory_of_gpu(struct kfd_process_device *pdd, KFD_IOC_ALLOC_MEM_FLAGS_GTT | KFD_IOC_ALLOC_MEM_FLAGS_USERPTR | KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL | - KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP); + KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP); idr_handle = kfd_process_device_create_obj_handle(pdd, *kgd_mem, bo_bucket->addr, @@ -2514,8 +2514,7 @@ static int criu_restore_memory_of_gpu(struct kfd_process_device *pdd, if (idr_handle < 0) { pr_err("Could not allocate idr\n"); - amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, *kgd_mem, - pdd->drm_priv, + amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, *kgd_mem, pdd->drm_priv, NULL); return -ENOMEM; } From 14726bb2b3c71fda0ee094c80bc330f7bed12b74 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Fri, 29 Jul 2022 16:20:27 +0800 Subject: [PATCH 0751/1868] drm/amdkcl: enable DRM_AMD_DC_DSC_SUPPORT by default v2: remove redundant check Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/dkms/Makefile | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 6178008b48339..3b41a6d897f59 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -191,6 +191,9 @@ subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN endif endif +export CONFIG_DRM_AMD_DC_DSC_SUPPORT=y +subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DSC_SUPPORT + export CONFIG_DRM_TTM_HELPER=m subdir-ccflags-y += -DCONFIG_DRM_TTM_HELPER CFLAGS_drm_gem_ttm_helper.o += -include $(src)/ttm/backport/backport.h \ From 60acb013d1fff736481307a87c985ca0707ff4e9 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 27 Jul 2022 10:54:21 +0800 Subject: [PATCH 0752/1868] drm/amdkcl: fake macro in drm/display/dsc_dp.h for legacy os v2: also include drm_dp_helper.h when drm_dp.h not exist v3: drop kcl_drm_dp.h and add some missing macros in kcl_drm_dp_helper.h for legacy os Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 1 + include/kcl/header/drm/display/drm_dp.h | 16 ++++++++++++++++ include/kcl/kcl_drm_dp_helper.h | 11 +++++++++++ 4 files changed, 31 insertions(+) create mode 100644 include/kcl/header/drm/display/drm_dp.h diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index c3e1e5c202995..af7b76eb527ec 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -309,6 +309,9 @@ /* drm_dev_unplug() is available */ #define HAVE_DRM_DEV_UNPLUG 1 +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DISPLAY_DRM_DP_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_DRM_DISPLAY_DRM_DP_HELPER_H 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index 17fb837a138c4..b9977c77c0f81 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -79,6 +79,7 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ AC_KERNEL_CHECK_HEADERS([drm/display/drm_hdmi_helper.h]) AC_KERNEL_CHECK_HEADERS([drm/display/drm_hdcp_helper.h]) AC_KERNEL_CHECK_HEADERS([drm/display/drm_hdcp.h]) + AC_KERNEL_CHECK_HEADERS([drm/display/drm_dp.h]) dnl # dnl # v5.7-13141-gca5999fde0a1 diff --git a/include/kcl/header/drm/display/drm_dp.h b/include/kcl/header/drm/display/drm_dp.h new file mode 100644 index 0000000000000..fc1cc1a4bac8e --- /dev/null +++ b/include/kcl/header/drm/display/drm_dp.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DISPLAY_DRM_DP_H_H_ +#define _KCL_HEADER_DISPLAY_DRM_DP_H_H_ + +#if defined(HAVE_DRM_DISPLAY_DRM_DP_H) +#include_next +#elif defined(HAVE_DRM_DISPLAY_DRM_DP_HELPER_H) +#include +#elif defined(HAVE_DRM_DP_DRM_DP_HELPER_H) +#include +#else +#include +#endif + +#endif + diff --git a/include/kcl/kcl_drm_dp_helper.h b/include/kcl/kcl_drm_dp_helper.h index 43ddfa2ed899d..cecb273e97d8a 100644 --- a/include/kcl/kcl_drm_dp_helper.h +++ b/include/kcl/kcl_drm_dp_helper.h @@ -158,6 +158,17 @@ #define DP_DSC_THROUGHPUT_MODE_0_UNSUPPORTED DP_DSC_THROUGHPUT_MODE_0_UPSUPPORTED #endif +#ifndef DP_DSC_THROUGHPUT_MODE_0_UNSUPPORTED +# define DP_DSC_THROUGHPUT_MODE_0_UNSUPPORTED 0 +# define DP_DSC_THROUGHPUT_MODE_0_170 (15 << 0) /* 1.4a */ +#endif + +#ifndef DP_UHBR10 +# define DP_UHBR10 (1 << 0) +# define DP_UHBR20 (1 << 1) +# define DP_UHBR13_5 (1 << 2) +#endif + #ifndef DP_PHY_REPEATER_128B132B_RATES /* See DP_128B132B_SUPPORTED_LINK_RATES for values */ #define DP_PHY_REPEATER_128B132B_RATES 0xf0007 /* 2.0 */ From cc46328a033869e501df2b433ed39fdaac4fea9d Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 27 Jul 2022 12:31:33 +0800 Subject: [PATCH 0753/1868] drm/amdkcl: define macro DRM_MODESET_ACQUIRE_INTERRUPTIBLE for legacy os v2: include Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_drm_modeset_lock.h | 12 ++++++++++++ 2 files changed, 13 insertions(+) create mode 100644 include/kcl/kcl_drm_modeset_lock.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 251fee9e35fca..8a8becd2a3d6f 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -96,5 +96,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_drm_modeset_lock.h b/include/kcl/kcl_drm_modeset_lock.h new file mode 100644 index 0000000000000..009e4af7a4c00 --- /dev/null +++ b/include/kcl/kcl_drm_modeset_lock.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _KCL_KCL_DRM_MODESET_LOCK_H_H_ +#define _KCL_KCL_DRM_MODESET_LOCK_H_H_ + +#include /* stackdepot.h is not self-contained */ +#include + +#ifndef DRM_MODESET_ACQUIRE_INTERRUPTIBLE +#define DRM_MODESET_ACQUIRE_INTERRUPTIBLE BIT(0) +#endif + +#endif From 5ea1e822570888a03220735957688f9962285101 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 27 Jul 2022 14:42:09 +0800 Subject: [PATCH 0754/1868] drm/amdkcl: Test whether struct drm_dsc_config has member simple_422 Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- .../drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c | 4 ++++ drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c | 5 +++++ .../gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c | 2 ++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/drm_dsc_config.m4 | 21 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 6 files changed, 36 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_dsc_config.m4 diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c index fd316e660df05..457da2d56ba4c 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c @@ -297,7 +297,9 @@ void dsc_log_pps(struct display_stream_compressor *dsc, struct drm_dsc_config *p DC_LOG_DSC("\tline_buf_depth %d", pps->line_buf_depth); DC_LOG_DSC("\tblock_pred_enable %d", pps->block_pred_enable); DC_LOG_DSC("\tconvert_rgb %d", pps->convert_rgb); +#ifdef HAVE_DRM_DSC_CONFIG_SIMPLE_422 DC_LOG_DSC("\tsimple_422 %d", pps->simple_422); +#endif DC_LOG_DSC("\tvbr_enable %d", pps->vbr_enable); DC_LOG_DSC("\tbits_per_pixel %d (%d.%04d)", bits_per_pixel, bits_per_pixel / 16, ((bits_per_pixel % 16) * 10000) / 16); DC_LOG_DSC("\tpic_height %d", pps->pic_height); @@ -434,7 +436,9 @@ bool dsc_prepare_config(const struct dsc_config *dsc_cfg, struct dsc_reg_values dsc_reg_vals->pps.convert_rgb = dsc_reg_vals->pixel_format == DSC_PIXFMT_RGB ? 1 : 0; dsc_reg_vals->pps.native_422 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422); dsc_reg_vals->pps.native_420 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420); +#ifdef HAVE_DRM_DSC_CONFIG_SIMPLE_422 dsc_reg_vals->pps.simple_422 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422); +#endif calc_rc_params(&rc, &dsc_reg_vals->pps); diff --git a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c index d61b6430a6409..1699a57ab7cb1 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c @@ -48,9 +48,14 @@ void calc_rc_params(struct rc_params *rc, const struct drm_dsc_config *pps) int slice_width = pps->slice_width; int slice_height = pps->slice_height; +#ifdef HAVE_DRM_DSC_CONFIG_SIMPLE_422 mode = pps->convert_rgb ? CM_RGB : (pps->simple_422 ? CM_444 : (pps->native_422 ? CM_422 : pps->native_420 ? CM_420 : CM_444)); +#else + mode = pps->convert_rgb ? CM_RGB : (pps->native_422 ? CM_422 : + pps->native_420 ? CM_420 : CM_444); +#endif bpc = (pps->bits_per_component == 8) ? BPC_8 : (pps->bits_per_component == 10) ? BPC_10 : BPC_12; diff --git a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c index b01295c412b1d..13fc27926468f 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c @@ -34,7 +34,9 @@ static void copy_pps_fields(struct drm_dsc_config *to, const struct drm_dsc_conf to->convert_rgb = from->convert_rgb; to->slice_width = from->slice_width; to->slice_height = from->slice_height; +#ifdef HAVE_DRM_DSC_CONFIG_SIMPLE_422 to->simple_422 = from->simple_422; +#endif to->native_422 = from->native_422; to->native_420 = from->native_420; to->pic_width = from->pic_width; diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index af7b76eb527ec..ee927932f1f36 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1249,6 +1249,9 @@ /* __dma_fence_is_later() is available and has ops arg */ #define HAVE__DMA_FENCE_IS_LATER_WITH_OPS_ARG 1 +/* struct drm_dsc_config has member simple_422 */ +#define HAVE_DRM_DSC_CONFIG_SIMPLE_422 1 + /* drm_edid_get_monitor_name is available*/ #define HAVE_DRM_EDID_GET_MONITOR_NAME 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dsc_config.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dsc_config.m4 new file mode 100644 index 0000000000000..c5c3c2c4418bb --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dsc_config.m4 @@ -0,0 +1,21 @@ +dnl # +dnl # commit v4.20-rc3-804-g19fd5adbb595 +dnl # drm/dsc: Define VESA Display Stream Compression Capabilities +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DSC_CONFIG_SIMPLE_422], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #if defined(HAVE_DRM_DISPLAY_DRM_DSC_H) + #include + #else + #include + #endif + ], [ + struct drm_dsc_config *conf = NULL; + conf->simple_422 = true; + ], [ + AC_DEFINE(HAVE_DRM_DSC_CONFIG_SIMPLE_422, 1, + [struct drm_dsc_config has member simple_422]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 68f3bac4d4a21..fd1cce7987b96 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -210,6 +210,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DMA_FENCE_CHAIN_CONTAINED AC_AMDGPU_DRM_GEM_OBJECT_FUNCS_VMAP_HAS_IOSYS_MAP_ARG AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_BASE + AC_AMDGPU_DRM_DSC_CONFIG_SIMPLE_422 AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 6ff0e5f438f9d962001a664e6293aeed5271c0d7 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 27 Jul 2022 17:06:15 +0800 Subject: [PATCH 0755/1868] drm/amdkcl: Test whether drm_dsc_pps_payload_pack() is available Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- .../gpu/drm/amd/amdkcl/kcl_drm_dsc_helper.c | 203 ++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 + .../amd/dkms/m4/drm_dsc_pps_payload_pack.m4 | 20 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_dsc_helper.h | 18 ++ 7 files changed, 247 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_dsc_helper.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_dsc_pps_payload_pack.m4 create mode 100644 include/kcl/kcl_drm_dsc_helper.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index e9d5160622e08..8e3650b52cfc0 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -13,7 +13,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o kcl_ftrace.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_fs_read_write.o kcl_drm_aperture.o \ kcl_drm_drv.o kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o \ - kcl_mce_amd.o kcl_workqueue.o kcl_cpumask.o + kcl_mce_amd.o kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_dsc_helper.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_dsc_helper.c new file mode 100644 index 0000000000000..d54ef86bceaf4 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_dsc_helper.c @@ -0,0 +1,203 @@ +/** + * drm_dsc_pps_payload_pack() - Populates the DSC PPS + * + * @pps_payload: + * Bitwise struct for DSC Picture Parameter Set. This is defined + * by &struct drm_dsc_picture_parameter_set + * @dsc_cfg: + * DSC Configuration data filled by driver as defined by + * &struct drm_dsc_config + * + * DSC source device sends a picture parameter set (PPS) containing the + * information required by the sink to decode the compressed frame. Driver + * populates the DSC PPS struct using the DSC configuration parameters in + * the order expected by the DSC Display Sink device. For the DSC, the sink + * device expects the PPS payload in big endian format for fields + * that span more than 1 byte. + */ + +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT +#include +#include + +#ifndef HAVE_DRM_DSC_PPS_PAYLOAD_PACK +void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_payload, + const struct drm_dsc_config *dsc_cfg) +{ + int i; + + /* Protect against someone accidentally changing struct size */ + BUILD_BUG_ON(sizeof(*pps_payload) != + DP_SDP_PPS_HEADER_PAYLOAD_BYTES_MINUS_1 + 1); + + memset(pps_payload, 0, sizeof(*pps_payload)); + + /* PPS 0 */ + pps_payload->dsc_version = + dsc_cfg->dsc_version_minor | + dsc_cfg->dsc_version_major << DSC_PPS_VERSION_MAJOR_SHIFT; + + /* PPS 1, 2 is 0 */ + + /* PPS 3 */ + pps_payload->pps_3 = + dsc_cfg->line_buf_depth | + dsc_cfg->bits_per_component << DSC_PPS_BPC_SHIFT; + + /* PPS 4 */ + pps_payload->pps_4 = + ((dsc_cfg->bits_per_pixel & DSC_PPS_BPP_HIGH_MASK) >> + DSC_PPS_MSB_SHIFT) | + dsc_cfg->vbr_enable << DSC_PPS_VBR_EN_SHIFT | +#ifdef HAVE_DRM_DSC_CONFIG_SIMPLE_422 + dsc_cfg->simple_422 << DSC_PPS_SIMPLE422_SHIFT | +#endif + dsc_cfg->convert_rgb << DSC_PPS_CONVERT_RGB_SHIFT | + dsc_cfg->block_pred_enable << DSC_PPS_BLOCK_PRED_EN_SHIFT; + + /* PPS 5 */ + pps_payload->bits_per_pixel_low = + (dsc_cfg->bits_per_pixel & DSC_PPS_LSB_MASK); + + /* + * The DSC panel expects the PPS packet to have big endian format + * for data spanning 2 bytes. Use a macro cpu_to_be16() to convert + * to big endian format. If format is little endian, it will swap + * bytes to convert to Big endian else keep it unchanged. + */ + + /* PPS 6, 7 */ + pps_payload->pic_height = cpu_to_be16(dsc_cfg->pic_height); + + /* PPS 8, 9 */ + pps_payload->pic_width = cpu_to_be16(dsc_cfg->pic_width); + + /* PPS 10, 11 */ + pps_payload->slice_height = cpu_to_be16(dsc_cfg->slice_height); + + /* PPS 12, 13 */ + pps_payload->slice_width = cpu_to_be16(dsc_cfg->slice_width); + + /* PPS 14, 15 */ + pps_payload->chunk_size = cpu_to_be16(dsc_cfg->slice_chunk_size); + + /* PPS 16 */ + pps_payload->initial_xmit_delay_high = + ((dsc_cfg->initial_xmit_delay & + DSC_PPS_INIT_XMIT_DELAY_HIGH_MASK) >> + DSC_PPS_MSB_SHIFT); + + /* PPS 17 */ + pps_payload->initial_xmit_delay_low = + (dsc_cfg->initial_xmit_delay & DSC_PPS_LSB_MASK); + + /* PPS 18, 19 */ + pps_payload->initial_dec_delay = + cpu_to_be16(dsc_cfg->initial_dec_delay); + + /* PPS 20 is 0 */ + + /* PPS 21 */ + pps_payload->initial_scale_value = + dsc_cfg->initial_scale_value; + + /* PPS 22, 23 */ + pps_payload->scale_increment_interval = + cpu_to_be16(dsc_cfg->scale_increment_interval); + + /* PPS 24 */ + pps_payload->scale_decrement_interval_high = + ((dsc_cfg->scale_decrement_interval & + DSC_PPS_SCALE_DEC_INT_HIGH_MASK) >> + DSC_PPS_MSB_SHIFT); + + /* PPS 25 */ + pps_payload->scale_decrement_interval_low = + (dsc_cfg->scale_decrement_interval & DSC_PPS_LSB_MASK); + + /* PPS 26[7:0], PPS 27[7:5] RESERVED */ + + /* PPS 27 */ + pps_payload->first_line_bpg_offset = + dsc_cfg->first_line_bpg_offset; + + /* PPS 28, 29 */ + pps_payload->nfl_bpg_offset = + cpu_to_be16(dsc_cfg->nfl_bpg_offset); + + /* PPS 30, 31 */ + pps_payload->slice_bpg_offset = + cpu_to_be16(dsc_cfg->slice_bpg_offset); + + /* PPS 32, 33 */ + pps_payload->initial_offset = + cpu_to_be16(dsc_cfg->initial_offset); + + /* PPS 34, 35 */ + pps_payload->final_offset = cpu_to_be16(dsc_cfg->final_offset); + + /* PPS 36 */ + pps_payload->flatness_min_qp = dsc_cfg->flatness_min_qp; + + /* PPS 37 */ + pps_payload->flatness_max_qp = dsc_cfg->flatness_max_qp; + + /* PPS 38, 39 */ + pps_payload->rc_model_size = cpu_to_be16(dsc_cfg->rc_model_size); + + /* PPS 40 */ + pps_payload->rc_edge_factor = DSC_RC_EDGE_FACTOR_CONST; + + /* PPS 41 */ + pps_payload->rc_quant_incr_limit0 = + dsc_cfg->rc_quant_incr_limit0; + + /* PPS 42 */ + pps_payload->rc_quant_incr_limit1 = + dsc_cfg->rc_quant_incr_limit1; + + /* PPS 43 */ + pps_payload->rc_tgt_offset = DSC_RC_TGT_OFFSET_LO_CONST | + DSC_RC_TGT_OFFSET_HI_CONST << DSC_PPS_RC_TGT_OFFSET_HI_SHIFT; + + /* PPS 44 - 57 */ + for (i = 0; i < DSC_NUM_BUF_RANGES - 1; i++) + pps_payload->rc_buf_thresh[i] = + dsc_cfg->rc_buf_thresh[i]; + + /* PPS 58 - 87 */ + /* + * For DSC sink programming the RC Range parameter fields + * are as follows: Min_qp[15:11], max_qp[10:6], offset[5:0] + */ + for (i = 0; i < DSC_NUM_BUF_RANGES; i++) { + pps_payload->rc_range_parameters[i] = + cpu_to_be16((dsc_cfg->rc_range_params[i].range_min_qp << + DSC_PPS_RC_RANGE_MINQP_SHIFT) | + (dsc_cfg->rc_range_params[i].range_max_qp << + DSC_PPS_RC_RANGE_MAXQP_SHIFT) | + (dsc_cfg->rc_range_params[i].range_bpg_offset)); + } + + /* PPS 88 */ + pps_payload->native_422_420 = dsc_cfg->native_422 | + dsc_cfg->native_420 << DSC_PPS_NATIVE_420_SHIFT; + + /* PPS 89 */ + pps_payload->second_line_bpg_offset = + dsc_cfg->second_line_bpg_offset; + + /* PPS 90, 91 */ + pps_payload->nsl_bpg_offset = + cpu_to_be16(dsc_cfg->nsl_bpg_offset); + + /* PPS 92, 93 */ + pps_payload->second_line_offset_adj = + cpu_to_be16(dsc_cfg->second_line_offset_adj); + + /* PPS 94 - 127 are O */ +} +EXPORT_SYMBOL(drm_dsc_pps_payload_pack); +#endif /* HAVE_DRM_DSC_PPS_PAYLOAD_PACK */ + +#endif /* CONFIG_DRM_AMD_DC_DSC_SUPPORT */ diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 8a8becd2a3d6f..e9b12c3982507 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -97,5 +97,6 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index ee927932f1f36..11b55ef32140a 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1252,6 +1252,9 @@ /* struct drm_dsc_config has member simple_422 */ #define HAVE_DRM_DSC_CONFIG_SIMPLE_422 1 +/* drm_dsc_pps_payload_pack() is available */ +#define HAVE_DRM_DSC_PPS_PAYLOAD_PACK 1 + /* drm_edid_get_monitor_name is available*/ #define HAVE_DRM_EDID_GET_MONITOR_NAME 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dsc_pps_payload_pack.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dsc_pps_payload_pack.m4 new file mode 100644 index 0000000000000..624e489e45e3a --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dsc_pps_payload_pack.m4 @@ -0,0 +1,20 @@ +dnl # +dnl # commit v5.18-rc2-597-g2a64b147350f +dnl # drm/display: Move DSC header and helpers into display-helper module +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DSC_PPS_PAYLOAD_PACK], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #if defined(HAVE_DRM_DISPLAY_DRM_DSC_HELPER_H) + #include + #else + #include + #endif + ], [ + drm_dsc_pps_payload_pack(NULL, NULL); + ], [ + AC_DEFINE(HAVE_DRM_DSC_PPS_PAYLOAD_PACK, 1, + [drm_dsc_pps_payload_pack() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index fd1cce7987b96..9683e30055f47 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -211,6 +211,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_GEM_OBJECT_FUNCS_VMAP_HAS_IOSYS_MAP_ARG AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_BASE AC_AMDGPU_DRM_DSC_CONFIG_SIMPLE_422 + AC_AMDGPU_DRM_DSC_PPS_PAYLOAD_PACK AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_dsc_helper.h b/include/kcl/kcl_drm_dsc_helper.h new file mode 100644 index 0000000000000..d7b02f62b5ed1 --- /dev/null +++ b/include/kcl/kcl_drm_dsc_helper.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: MIT */ + +#ifndef _KCL_KCL_DRM_DSC_HELPER_H +#define _KCL_KCL_DRM_DSC_HELPER_H + +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + +#include +#include + +#ifndef HAVE_DRM_DSC_PPS_PAYLOAD_PACK +void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp, + const struct drm_dsc_config *dsc_cfg); +#endif + +#endif /* CONFIG_DRM_AMD_DC_DSC_SUPPORT */ +#endif /* _KCL_KCL_DRM_DSC_HELPER_H */ + From 786bdcf0b2a8c03e9c0ba7188b5fa72966496535 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 28 Jul 2022 11:09:19 +0800 Subject: [PATCH 0756/1868] drm/amdkcl: Test whether drm_dsc_compute_rc_parameters() is available Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- .../gpu/drm/amd/amdkcl/kcl_drm_dsc_helper.c | 134 +++++++++++++++++- drivers/gpu/drm/amd/dkms/config/config.h | 6 + .../dkms/m4/drm_dsc_compute_rc_parameters.m4 | 20 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_dsc_helper.h | 4 + 5 files changed, 164 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_dsc_compute_rc_parameters.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_dsc_helper.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_dsc_helper.c index d54ef86bceaf4..f5546b4049608 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_dsc_helper.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_dsc_helper.c @@ -15,9 +15,11 @@ * device expects the PPS payload in big endian format for fields * that span more than 1 byte. */ - #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + +#include #include +#include #include #ifndef HAVE_DRM_DSC_PPS_PAYLOAD_PACK @@ -200,4 +202,134 @@ void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_payload, EXPORT_SYMBOL(drm_dsc_pps_payload_pack); #endif /* HAVE_DRM_DSC_PPS_PAYLOAD_PACK */ +#ifndef HAVE_DRM_DSC_COMPUTE_RC_PARAMETERS +int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg) +{ + unsigned long groups_per_line = 0; + unsigned long groups_total = 0; + unsigned long num_extra_mux_bits = 0; + unsigned long slice_bits = 0; + unsigned long hrd_delay = 0; + unsigned long final_scale = 0; + unsigned long rbs_min = 0; + + if (vdsc_cfg->native_420 || vdsc_cfg->native_422) { + /* Number of groups used to code each line of a slice */ + groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width / 2, + DSC_RC_PIXELS_PER_GROUP); + + /* chunksize in Bytes */ + vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width / 2 * + vdsc_cfg->bits_per_pixel, + (8 * 16)); + } else { + /* Number of groups used to code each line of a slice */ + groups_per_line = DIV_ROUND_UP(vdsc_cfg->slice_width, + DSC_RC_PIXELS_PER_GROUP); + + /* chunksize in Bytes */ + vdsc_cfg->slice_chunk_size = DIV_ROUND_UP(vdsc_cfg->slice_width * + vdsc_cfg->bits_per_pixel, + (8 * 16)); + } + + if (vdsc_cfg->convert_rgb) + num_extra_mux_bits = 3 * (vdsc_cfg->mux_word_size + + (4 * vdsc_cfg->bits_per_component + 4) + - 2); + else if (vdsc_cfg->native_422) + num_extra_mux_bits = 4 * vdsc_cfg->mux_word_size + + (4 * vdsc_cfg->bits_per_component + 4) + + 3 * (4 * vdsc_cfg->bits_per_component) - 2; + else + num_extra_mux_bits = 3 * vdsc_cfg->mux_word_size + + (4 * vdsc_cfg->bits_per_component + 4) + + 2 * (4 * vdsc_cfg->bits_per_component) - 2; + /* Number of bits in one Slice */ + slice_bits = 8 * vdsc_cfg->slice_chunk_size * vdsc_cfg->slice_height; + + while ((num_extra_mux_bits > 0) && + ((slice_bits - num_extra_mux_bits) % vdsc_cfg->mux_word_size)) + num_extra_mux_bits--; + + if (groups_per_line < vdsc_cfg->initial_scale_value - 8) + vdsc_cfg->initial_scale_value = groups_per_line + 8; + + /* scale_decrement_interval calculation according to DSC spec 1.11 */ + if (vdsc_cfg->initial_scale_value > 8) + vdsc_cfg->scale_decrement_interval = groups_per_line / + (vdsc_cfg->initial_scale_value - 8); + else + vdsc_cfg->scale_decrement_interval = DSC_SCALE_DECREMENT_INTERVAL_MAX; + + vdsc_cfg->final_offset = vdsc_cfg->rc_model_size - + (vdsc_cfg->initial_xmit_delay * + vdsc_cfg->bits_per_pixel + 8) / 16 + num_extra_mux_bits; + + if (vdsc_cfg->final_offset >= vdsc_cfg->rc_model_size) { + DRM_DEBUG_KMS("FinalOfs < RcModelSze for this InitialXmitDelay\n"); + return -ERANGE; + } + + final_scale = (vdsc_cfg->rc_model_size * 8) / + (vdsc_cfg->rc_model_size - vdsc_cfg->final_offset); + if (vdsc_cfg->slice_height > 1) + /* + * NflBpgOffset is 16 bit value with 11 fractional bits + * hence we multiply by 2^11 for preserving the + * fractional part + */ + vdsc_cfg->nfl_bpg_offset = DIV_ROUND_UP((vdsc_cfg->first_line_bpg_offset << 11), + (vdsc_cfg->slice_height - 1)); + else + vdsc_cfg->nfl_bpg_offset = 0; + + /* Number of groups used to code the entire slice */ + groups_total = groups_per_line * vdsc_cfg->slice_height; + + /* slice_bpg_offset is 16 bit value with 11 fractional bits */ + vdsc_cfg->slice_bpg_offset = DIV_ROUND_UP(((vdsc_cfg->rc_model_size - + vdsc_cfg->initial_offset + + num_extra_mux_bits) << 11), + groups_total); + + if (final_scale > 9) { + /* + * ScaleIncrementInterval = + * finaloffset/((NflBpgOffset + SliceBpgOffset)*8(finalscale - 1.125)) + * as (NflBpgOffset + SliceBpgOffset) has 11 bit fractional value, + * we need divide by 2^11 from pstDscCfg values + */ + vdsc_cfg->scale_increment_interval = + (vdsc_cfg->final_offset * (1 << 11)) / + ((vdsc_cfg->nfl_bpg_offset + + vdsc_cfg->slice_bpg_offset) * + (final_scale - 9)); + } else { + /* + * If finalScaleValue is less than or equal to 9, a value of 0 should + * be used to disable the scale increment at the end of the slice + */ + vdsc_cfg->scale_increment_interval = 0; + } + + /* + * DSC spec mentions that bits_per_pixel specifies the target + * bits/pixel (bpp) rate that is used by the encoder, + * in steps of 1/16 of a bit per pixel + */ + rbs_min = vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset + + DIV_ROUND_UP(vdsc_cfg->initial_xmit_delay * + vdsc_cfg->bits_per_pixel, 16) + + groups_per_line * vdsc_cfg->first_line_bpg_offset; + + hrd_delay = DIV_ROUND_UP((rbs_min * 16), vdsc_cfg->bits_per_pixel); + vdsc_cfg->rc_bits = (hrd_delay * vdsc_cfg->bits_per_pixel) / 16; + vdsc_cfg->initial_dec_delay = hrd_delay - vdsc_cfg->initial_xmit_delay; + + return 0; +} +EXPORT_SYMBOL(drm_dsc_compute_rc_parameters); +#endif /* HAVE_DRM_DSC_COMPUTE_RC_PARAMETERS */ + #endif /* CONFIG_DRM_AMD_DC_DSC_SUPPORT */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 11b55ef32140a..4d4822ada9873 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -529,6 +529,12 @@ /* drm_gem_prime_export() with p,i arg is available */ #define HAVE_DRM_DRV_GEM_PRIME_EXPORT_PI 1 +/* drm_drv_uses_atomic_modeset() is available */ +#define HAVE_DRM_DRV_USES_ATOMIC_MODESET 1 + +/* drm_dsc_compute_rc_parameters() is available */ +#define HAVE_DRM_DSC_COMPUTE_RC_PARAMETERS 1 + /* drm_edid_to_eld() are available */ /* #undef HAVE_DRM_EDID_TO_ELD */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dsc_compute_rc_parameters.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dsc_compute_rc_parameters.m4 new file mode 100644 index 0000000000000..57d179067d66b --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dsc_compute_rc_parameters.m4 @@ -0,0 +1,20 @@ +dnl # +dnl # commit v5.18-rc2-597-g2a64b147350f +dnl # drm/display: Move DSC header and helpers into display-helper module +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DSC_COMPUTE_RC_PARAMETERS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #if defined(HAVE_DRM_DISPLAY_DRM_DSC_HELPER_H) + #include + #else + #include + #endif + ], [ + drm_dsc_compute_rc_parameters(NULL); + ], [ + AC_DEFINE(HAVE_DRM_DSC_COMPUTE_RC_PARAMETERS, 1, + [drm_dsc_compute_rc_parameters() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 9683e30055f47..1998834f45c6a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -212,6 +212,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_BASE AC_AMDGPU_DRM_DSC_CONFIG_SIMPLE_422 AC_AMDGPU_DRM_DSC_PPS_PAYLOAD_PACK + AC_AMDGPU_DRM_DSC_COMPUTE_RC_PARAMETERS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_dsc_helper.h b/include/kcl/kcl_drm_dsc_helper.h index d7b02f62b5ed1..207bc76eb1195 100644 --- a/include/kcl/kcl_drm_dsc_helper.h +++ b/include/kcl/kcl_drm_dsc_helper.h @@ -13,6 +13,10 @@ void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp, const struct drm_dsc_config *dsc_cfg); #endif +#ifndef HAVE_DRM_DSC_COMPUTE_RC_PARAMETERS +int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg); +#endif + #endif /* CONFIG_DRM_AMD_DC_DSC_SUPPORT */ #endif /* _KCL_KCL_DRM_DSC_HELPER_H */ From 4d7a5d10c26c1d3ae0324b695d03f4abad5e5467 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 28 Jul 2022 13:00:10 +0800 Subject: [PATCH 0757/1868] drm/amdkcl: adjust macro to fix build error Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 48606fc29978e..0d5d493fc4b0f 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -11940,6 +11940,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, goto fail; } +#ifdef HAVE_DRM_DP_MST_ATOMIC_CHECK #if defined(CONFIG_DRM_AMD_DC_FP) if (dc_resource_is_dsc_encoding_supported(dc)) { ret = compute_mst_dsc_configs_for_state(state, dm_state->context, vars); @@ -11950,6 +11951,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, } } #endif +#endif #if defined(HAVE_DRM_DP_MST_ATOMIC_ENABLE_DSC) ret = dm_update_mst_vcpi_slots_for_dsc(state, dm_state->context, vars); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 3ff4c755b05d4..b7b4593530f2a 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -234,7 +234,6 @@ static const struct drm_connector_funcs dm_dp_mst_connector_funcs = { }; #if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT) -#if defined(HAVE_DRM_DP_MST_DSC_AUX_FOR_PORT) bool needs_dsc_aux_workaround(struct dc_link *link) { if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 && @@ -261,6 +260,7 @@ static bool is_synaptics_cascaded_panamera(struct dc_link *link, struct drm_dp_m return false; } +#if defined(HAVE_DRM_DP_MST_DSC_AUX_FOR_PORT) static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnector) { struct dc_sink *dc_sink = aconnector->dc_sink; From ccba57d7ea673307f485a4461a094c47774d549f Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 28 Jul 2022 13:00:43 +0800 Subject: [PATCH 0758/1868] drm/amdkcl: remove useless macro wrapper Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen Change-Id: Id09116daf768f3e17026e6db0826dbfb7bc179ee --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 0d5d493fc4b0f..33bd804d5d742 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -7724,7 +7724,6 @@ static void dm_encoder_helper_disable(struct drm_encoder *encoder) } -#if defined(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE) int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth) { switch (display_color_depth) { @@ -7745,7 +7744,7 @@ int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth) } return 0; } -#endif + static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, struct drm_crtc_state *crtc_state, struct drm_connector_state *conn_state) From d3a2e3847baf14901e38c6d98d350ab67cf938d4 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 28 Jul 2022 13:54:31 +0800 Subject: [PATCH 0759/1868] drm/amdkcl: fix unused variable warning Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 33bd804d5d742..6cf54d34b6a0d 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -11559,7 +11559,9 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, bool is_top_most_overlay = true; struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS struct drm_dp_mst_topology_mgr *mgr; +#endif struct drm_dp_mst_topology_state *mst_state; struct dsc_mst_fairness_vars vars[MAX_PIPES] = {0}; #endif From cc5a95dd2b46b0dff8c72d764b5ba266cda3ff73 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 24 Aug 2022 11:35:44 +0800 Subject: [PATCH 0760/1868] drm/amdkcl: Check if drm_buddy.h is exist Signed-off-by: Ma Jun Change-Id: I0981cffaa5da7fcd75273e8adc09051bb966037e --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 6 ++++++ 2 files changed, 9 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 4d4822ada9873..c90e5e61b257e 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -511,6 +511,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_PROBE_HELPER_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_BUDDY_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_UTIL_H 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index b9977c77c0f81..055736d17b86a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -86,4 +86,10 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # mm: introduce include/linux/pgtable.h dnl # AC_KERNEL_CHECK_HEADERS([linux/pgtable.h]) + + dnl # + dnl # v5.19-rc1- c9cad937c0 + dnl # drm/amdgpu: add drm buddy support to amdgpu + dnl # + AC_KERNEL_CHECK_HEADERS([drm/drm_buddy.h]) ]) From 69c3039e2024420e354034c1739575bd41e1529b Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 24 Aug 2022 16:01:56 +0800 Subject: [PATCH 0761/1868] drm/amdkcl: Add the drm buddy support for legacy os Signed-off-by: Ma Jun Change-Id: Ide9f05c3cdb024ba06fb70c12f72eb105af23118 --- drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h | 1 - drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_drm_buddy.c | 783 +++++++++++++++++++ drivers/gpu/drm/amd/amdkcl/main.c | 11 + drivers/gpu/drm/amd/backport/backport.h | 2 +- include/kcl/header/drm/drm_buddy.h | 11 + include/kcl/kcl_drm_buddy.h | 161 ++++ 7 files changed, 968 insertions(+), 3 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_buddy.c create mode 100644 include/kcl/header/drm/drm_buddy.h create mode 100644 include/kcl/kcl_drm_buddy.h diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h index b256cbc2bc270..7c27b38ebb193 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.h @@ -25,7 +25,6 @@ #define __AMDGPU_VRAM_MGR_H__ #include - struct amdgpu_vram_mgr { struct ttm_resource_manager manager; struct drm_buddy mm; diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 8e3650b52cfc0..0104acd2fd133 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -13,7 +13,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o kcl_ftrace.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_fs_read_write.o kcl_drm_aperture.o \ kcl_drm_drv.o kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o \ - kcl_mce_amd.o kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o + kcl_mce_amd.o kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o kcl_drm_buddy.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_buddy.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_buddy.c new file mode 100644 index 0000000000000..b8e89facbadd0 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_buddy.c @@ -0,0 +1,783 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright © 2021 Intel Corporation + */ + +#include +#ifndef HAVE_DRM_DRM_BUDDY_H + +#include + +static struct kmem_cache *slab_blocks; + +static struct drm_buddy_block *drm_block_alloc(struct drm_buddy *mm, + struct drm_buddy_block *parent, + unsigned int order, + u64 offset) +{ + struct drm_buddy_block *block; + + BUG_ON(order > DRM_BUDDY_MAX_ORDER); + + block = kmem_cache_zalloc(slab_blocks, GFP_KERNEL); + if (!block) + return NULL; + + block->header = offset; + block->header |= order; + block->parent = parent; + + BUG_ON(block->header & DRM_BUDDY_HEADER_UNUSED); + return block; +} + +static void drm_block_free(struct drm_buddy *mm, + struct drm_buddy_block *block) +{ + kmem_cache_free(slab_blocks, block); +} + +static void mark_allocated(struct drm_buddy_block *block) +{ + block->header &= ~DRM_BUDDY_HEADER_STATE; + block->header |= DRM_BUDDY_ALLOCATED; + + list_del(&block->link); +} + +static void mark_free(struct drm_buddy *mm, + struct drm_buddy_block *block) +{ + block->header &= ~DRM_BUDDY_HEADER_STATE; + block->header |= DRM_BUDDY_FREE; + + list_add(&block->link, + &mm->free_list[drm_buddy_block_order(block)]); +} + +static void mark_split(struct drm_buddy_block *block) +{ + block->header &= ~DRM_BUDDY_HEADER_STATE; + block->header |= DRM_BUDDY_SPLIT; + + list_del(&block->link); +} + +/** + * drm_buddy_init - init memory manager + * + * @mm: DRM buddy manager to initialize + * @size: size in bytes to manage + * @chunk_size: minimum page size in bytes for our allocations + * + * Initializes the memory manager and its resources. + * + * Returns: + * 0 on success, error code on failure. + */ +int drm_buddy_init(struct drm_buddy *mm, u64 size, u64 chunk_size) +{ + unsigned int i; + u64 offset; + + if (size < chunk_size) + return -EINVAL; + + if (chunk_size < PAGE_SIZE) + return -EINVAL; + + if (!is_power_of_2(chunk_size)) + return -EINVAL; + + size = round_down(size, chunk_size); + + mm->size = size; + mm->avail = size; + mm->chunk_size = chunk_size; + mm->max_order = ilog2(size) - ilog2(chunk_size); + + BUG_ON(mm->max_order > DRM_BUDDY_MAX_ORDER); + + mm->free_list = kmalloc_array(mm->max_order + 1, + sizeof(struct list_head), + GFP_KERNEL); + if (!mm->free_list) + return -ENOMEM; + + for (i = 0; i <= mm->max_order; ++i) + INIT_LIST_HEAD(&mm->free_list[i]); + + mm->n_roots = hweight64(size); + + mm->roots = kmalloc_array(mm->n_roots, + sizeof(struct drm_buddy_block *), + GFP_KERNEL); + if (!mm->roots) + goto out_free_list; + + offset = 0; + i = 0; + + /* + * Split into power-of-two blocks, in case we are given a size that is + * not itself a power-of-two. + */ + do { + struct drm_buddy_block *root; + unsigned int order; + u64 root_size; + + root_size = rounddown_pow_of_two(size); + order = ilog2(root_size) - ilog2(chunk_size); + + root = drm_block_alloc(mm, NULL, order, offset); + if (!root) + goto out_free_roots; + + mark_free(mm, root); + + BUG_ON(i > mm->max_order); + BUG_ON(drm_buddy_block_size(mm, root) < chunk_size); + + mm->roots[i] = root; + + offset += root_size; + size -= root_size; + i++; + } while (size); + + return 0; + +out_free_roots: + while (i--) + drm_block_free(mm, mm->roots[i]); + kfree(mm->roots); +out_free_list: + kfree(mm->free_list); + return -ENOMEM; +} +EXPORT_SYMBOL(drm_buddy_init); + +/** + * drm_buddy_fini - tear down the memory manager + * + * @mm: DRM buddy manager to free + * + * Cleanup memory manager resources and the freelist + */ +void drm_buddy_fini(struct drm_buddy *mm) +{ + int i; + + for (i = 0; i < mm->n_roots; ++i) { + WARN_ON(!drm_buddy_block_is_free(mm->roots[i])); + drm_block_free(mm, mm->roots[i]); + } + + WARN_ON(mm->avail != mm->size); + + kfree(mm->roots); + kfree(mm->free_list); +} +EXPORT_SYMBOL(drm_buddy_fini); + +static int split_block(struct drm_buddy *mm, + struct drm_buddy_block *block) +{ + unsigned int block_order = drm_buddy_block_order(block) - 1; + u64 offset = drm_buddy_block_offset(block); + + BUG_ON(!drm_buddy_block_is_free(block)); + BUG_ON(!drm_buddy_block_order(block)); + + block->left = drm_block_alloc(mm, block, block_order, offset); + if (!block->left) + return -ENOMEM; + + block->right = drm_block_alloc(mm, block, block_order, + offset + (mm->chunk_size << block_order)); + if (!block->right) { + drm_block_free(mm, block->left); + return -ENOMEM; + } + + mark_free(mm, block->left); + mark_free(mm, block->right); + + mark_split(block); + + return 0; +} + +static struct drm_buddy_block * +__get_buddy(struct drm_buddy_block *block) +{ + struct drm_buddy_block *parent; + + parent = block->parent; + if (!parent) + return NULL; + + if (parent->left == block) + return parent->right; + + return parent->left; +} + +/** + * drm_get_buddy - get buddy address + * + * @block: DRM buddy block + * + * Returns the corresponding buddy block for @block, or NULL + * if this is a root block and can't be merged further. + * Requires some kind of locking to protect against + * any concurrent allocate and free operations. + */ +struct drm_buddy_block * +drm_get_buddy(struct drm_buddy_block *block) +{ + return __get_buddy(block); +} +EXPORT_SYMBOL(drm_get_buddy); + +static void __drm_buddy_free(struct drm_buddy *mm, + struct drm_buddy_block *block) +{ + struct drm_buddy_block *parent; + + while ((parent = block->parent)) { + struct drm_buddy_block *buddy; + + buddy = __get_buddy(block); + + if (!drm_buddy_block_is_free(buddy)) + break; + + list_del(&buddy->link); + + drm_block_free(mm, block); + drm_block_free(mm, buddy); + + block = parent; + } + + mark_free(mm, block); +} + +/** + * drm_buddy_free_block - free a block + * + * @mm: DRM buddy manager + * @block: block to be freed + */ +void drm_buddy_free_block(struct drm_buddy *mm, + struct drm_buddy_block *block) +{ + BUG_ON(!drm_buddy_block_is_allocated(block)); + mm->avail += drm_buddy_block_size(mm, block); + __drm_buddy_free(mm, block); +} +EXPORT_SYMBOL(drm_buddy_free_block); + +/** + * drm_buddy_free_list - free blocks + * + * @mm: DRM buddy manager + * @objects: input list head to free blocks + */ +void drm_buddy_free_list(struct drm_buddy *mm, struct list_head *objects) +{ + struct drm_buddy_block *block, *on; + + list_for_each_entry_safe(block, on, objects, link) { + drm_buddy_free_block(mm, block); + cond_resched(); + } + INIT_LIST_HEAD(objects); +} +EXPORT_SYMBOL(drm_buddy_free_list); + +static inline bool overlaps(u64 s1, u64 e1, u64 s2, u64 e2) +{ + return s1 <= e2 && e1 >= s2; +} + +static inline bool contains(u64 s1, u64 e1, u64 s2, u64 e2) +{ + return s1 <= s2 && e1 >= e2; +} + +static struct drm_buddy_block * +alloc_range_bias(struct drm_buddy *mm, + u64 start, u64 end, + unsigned int order) +{ + struct drm_buddy_block *block; + struct drm_buddy_block *buddy; + LIST_HEAD(dfs); + int err; + int i; + + end = end - 1; + + for (i = 0; i < mm->n_roots; ++i) + list_add_tail(&mm->roots[i]->tmp_link, &dfs); + + do { + u64 block_start; + u64 block_end; + + block = list_first_entry_or_null(&dfs, + struct drm_buddy_block, + tmp_link); + if (!block) + break; + + list_del(&block->tmp_link); + + if (drm_buddy_block_order(block) < order) + continue; + + block_start = drm_buddy_block_offset(block); + block_end = block_start + drm_buddy_block_size(mm, block) - 1; + + if (!overlaps(start, end, block_start, block_end)) + continue; + + if (drm_buddy_block_is_allocated(block)) + continue; + + if (contains(start, end, block_start, block_end) && + order == drm_buddy_block_order(block)) { + /* + * Find the free block within the range. + */ + if (drm_buddy_block_is_free(block)) + return block; + + continue; + } + + if (!drm_buddy_block_is_split(block)) { + err = split_block(mm, block); + if (unlikely(err)) + goto err_undo; + } + + list_add(&block->right->tmp_link, &dfs); + list_add(&block->left->tmp_link, &dfs); + } while (1); + + return ERR_PTR(-ENOSPC); + +err_undo: + /* + * We really don't want to leave around a bunch of split blocks, since + * bigger is better, so make sure we merge everything back before we + * free the allocated blocks. + */ + buddy = __get_buddy(block); + if (buddy && + (drm_buddy_block_is_free(block) && + drm_buddy_block_is_free(buddy))) + __drm_buddy_free(mm, block); + return ERR_PTR(err); +} + +static struct drm_buddy_block * +get_maxblock(struct list_head *head) +{ + struct drm_buddy_block *max_block = NULL, *node; + + max_block = list_first_entry_or_null(head, + struct drm_buddy_block, + link); + if (!max_block) + return NULL; + + list_for_each_entry(node, head, link) { + if (drm_buddy_block_offset(node) > + drm_buddy_block_offset(max_block)) + max_block = node; + } + + return max_block; +} + +static struct drm_buddy_block * +alloc_from_freelist(struct drm_buddy *mm, + unsigned int order, + unsigned long flags) +{ + struct drm_buddy_block *block = NULL; + unsigned int i; + int err; + + for (i = order; i <= mm->max_order; ++i) { + if (flags & DRM_BUDDY_TOPDOWN_ALLOCATION) { + block = get_maxblock(&mm->free_list[i]); + if (block) + break; + } else { + block = list_first_entry_or_null(&mm->free_list[i], + struct drm_buddy_block, + link); + if (block) + break; + } + } + + if (!block) + return ERR_PTR(-ENOSPC); + + BUG_ON(!drm_buddy_block_is_free(block)); + + while (i != order) { + err = split_block(mm, block); + if (unlikely(err)) + goto err_undo; + + block = block->right; + i--; + } + return block; + +err_undo: + if (i != order) + __drm_buddy_free(mm, block); + return ERR_PTR(err); +} + +static int __alloc_range(struct drm_buddy *mm, + struct list_head *dfs, + u64 start, u64 size, + struct list_head *blocks) +{ + struct drm_buddy_block *block; + struct drm_buddy_block *buddy; + LIST_HEAD(allocated); + u64 end; + int err; + + end = start + size - 1; + + do { + u64 block_start; + u64 block_end; + + block = list_first_entry_or_null(dfs, + struct drm_buddy_block, + tmp_link); + if (!block) + break; + + list_del(&block->tmp_link); + + block_start = drm_buddy_block_offset(block); + block_end = block_start + drm_buddy_block_size(mm, block) - 1; + + if (!overlaps(start, end, block_start, block_end)) + continue; + + if (drm_buddy_block_is_allocated(block)) { + err = -ENOSPC; + goto err_free; + } + + if (contains(start, end, block_start, block_end)) { + if (!drm_buddy_block_is_free(block)) { + err = -ENOSPC; + goto err_free; + } + + mark_allocated(block); + mm->avail -= drm_buddy_block_size(mm, block); + list_add_tail(&block->link, &allocated); + continue; + } + + if (!drm_buddy_block_is_split(block)) { + err = split_block(mm, block); + if (unlikely(err)) + goto err_undo; + } + + list_add(&block->right->tmp_link, dfs); + list_add(&block->left->tmp_link, dfs); + } while (1); + + list_splice_tail(&allocated, blocks); + return 0; + +err_undo: + /* + * We really don't want to leave around a bunch of split blocks, since + * bigger is better, so make sure we merge everything back before we + * free the allocated blocks. + */ + buddy = __get_buddy(block); + if (buddy && + (drm_buddy_block_is_free(block) && + drm_buddy_block_is_free(buddy))) + __drm_buddy_free(mm, block); + +err_free: + drm_buddy_free_list(mm, &allocated); + return err; +} + +static int __drm_buddy_alloc_range(struct drm_buddy *mm, + u64 start, + u64 size, + struct list_head *blocks) +{ + LIST_HEAD(dfs); + int i; + + for (i = 0; i < mm->n_roots; ++i) + list_add_tail(&mm->roots[i]->tmp_link, &dfs); + + return __alloc_range(mm, &dfs, start, size, blocks); +} + +/** + * drm_buddy_block_trim - free unused pages + * + * @mm: DRM buddy manager + * @new_size: original size requested + * @blocks: Input and output list of allocated blocks. + * MUST contain single block as input to be trimmed. + * On success will contain the newly allocated blocks + * making up the @new_size. Blocks always appear in + * ascending order + * + * For contiguous allocation, we round up the size to the nearest + * power of two value, drivers consume *actual* size, so remaining + * portions are unused and can be optionally freed with this function + * + * Returns: + * 0 on success, error code on failure. + */ +int drm_buddy_block_trim(struct drm_buddy *mm, + u64 new_size, + struct list_head *blocks) +{ + struct drm_buddy_block *parent; + struct drm_buddy_block *block; + LIST_HEAD(dfs); + u64 new_start; + int err; + + if (!list_is_singular(blocks)) + return -EINVAL; + + block = list_first_entry(blocks, + struct drm_buddy_block, + link); + + if (WARN_ON(!drm_buddy_block_is_allocated(block))) + return -EINVAL; + + if (new_size > drm_buddy_block_size(mm, block)) + return -EINVAL; + + if (!new_size || !IS_ALIGNED(new_size, mm->chunk_size)) + return -EINVAL; + + if (new_size == drm_buddy_block_size(mm, block)) + return 0; + + list_del(&block->link); + mark_free(mm, block); + mm->avail += drm_buddy_block_size(mm, block); + + /* Prevent recursively freeing this node */ + parent = block->parent; + block->parent = NULL; + + new_start = drm_buddy_block_offset(block); + list_add(&block->tmp_link, &dfs); + err = __alloc_range(mm, &dfs, new_start, new_size, blocks); + if (err) { + mark_allocated(block); + mm->avail -= drm_buddy_block_size(mm, block); + list_add(&block->link, blocks); + } + + block->parent = parent; + return err; +} +EXPORT_SYMBOL(drm_buddy_block_trim); + +/** + * drm_buddy_alloc_blocks - allocate power-of-two blocks + * + * @mm: DRM buddy manager to allocate from + * @start: start of the allowed range for this block + * @end: end of the allowed range for this block + * @size: size of the allocation + * @min_page_size: alignment of the allocation + * @blocks: output list head to add allocated blocks + * @flags: DRM_BUDDY_*_ALLOCATION flags + * + * alloc_range_bias() called on range limitations, which traverses + * the tree and returns the desired block. + * + * alloc_from_freelist() called when *no* range restrictions + * are enforced, which picks the block from the freelist. + * + * Returns: + * 0 on success, error code on failure. + */ +int drm_buddy_alloc_blocks(struct drm_buddy *mm, + u64 start, u64 end, u64 size, + u64 min_page_size, + struct list_head *blocks, + unsigned long flags) +{ + struct drm_buddy_block *block = NULL; + unsigned int min_order, order; + unsigned long pages; + LIST_HEAD(allocated); + int err; + + if (size < mm->chunk_size) + return -EINVAL; + + if (min_page_size < mm->chunk_size) + return -EINVAL; + + if (!is_power_of_2(min_page_size)) + return -EINVAL; + + if (!IS_ALIGNED(start | end | size, mm->chunk_size)) + return -EINVAL; + + if (end > mm->size) + return -EINVAL; + + if (range_overflows(start, size, mm->size)) + return -EINVAL; + + /* Actual range allocation */ + if (start + size == end) + return __drm_buddy_alloc_range(mm, start, size, blocks); + + if (!IS_ALIGNED(size, min_page_size)) + return -EINVAL; + + pages = size >> ilog2(mm->chunk_size); + order = fls(pages) - 1; + min_order = ilog2(min_page_size) - ilog2(mm->chunk_size); + + do { + order = min(order, (unsigned int)fls(pages) - 1); + BUG_ON(order > mm->max_order); + BUG_ON(order < min_order); + + do { + if (flags & DRM_BUDDY_RANGE_ALLOCATION) + /* Allocate traversing within the range */ + block = alloc_range_bias(mm, start, end, order); + else + /* Allocate from freelist */ + block = alloc_from_freelist(mm, order, flags); + + if (!IS_ERR(block)) + break; + + if (order-- == min_order) { + err = -ENOSPC; + goto err_free; + } + } while (1); + + mark_allocated(block); + mm->avail -= drm_buddy_block_size(mm, block); + //kmemleak_update_trace(block); + list_add_tail(&block->link, &allocated); + + pages -= BIT(order); + + if (!pages) + break; + } while (1); + + list_splice_tail(&allocated, blocks); + return 0; + +err_free: + drm_buddy_free_list(mm, &allocated); + return err; +} +EXPORT_SYMBOL(drm_buddy_alloc_blocks); + +/** + * drm_buddy_block_print - print block information + * + * @mm: DRM buddy manager + * @block: DRM buddy block + * @p: DRM printer to use + */ +void drm_buddy_block_print(struct drm_buddy *mm, + struct drm_buddy_block *block, + struct drm_printer *p) +{ + u64 start = drm_buddy_block_offset(block); + u64 size = drm_buddy_block_size(mm, block); + + drm_printf(p, "%#018llx-%#018llx: %llu\n", start, start + size, size); +} +EXPORT_SYMBOL(drm_buddy_block_print); + +/** + * drm_buddy_print - print allocator state + * + * @mm: DRM buddy manager + * @p: DRM printer to use + */ +void drm_buddy_print(struct drm_buddy *mm, struct drm_printer *p) +{ + int order; + + drm_printf(p, "chunk_size: %lluKiB, total: %lluMiB, free: %lluMiB\n", + mm->chunk_size >> 10, mm->size >> 20, mm->avail >> 20); + + for (order = mm->max_order; order >= 0; order--) { + struct drm_buddy_block *block; + u64 count = 0, free; + + list_for_each_entry(block, &mm->free_list[order], link) { + BUG_ON(!drm_buddy_block_is_free(block)); + count++; + } + + drm_printf(p, "order-%d ", order); + + free = count * (mm->chunk_size << order); + if (free < SZ_1M) + drm_printf(p, "free: %lluKiB", free >> 10); + else + drm_printf(p, "free: %lluMiB", free >> 20); + + drm_printf(p, ", pages: %llu\n", count); + } +} +EXPORT_SYMBOL(drm_buddy_print); + +void amdkcl_drm_buddy_module_exit(void) +{ + kmem_cache_destroy(slab_blocks); +} + +int amdkcl_drm_buddy_module_init(void) +{ + slab_blocks = KMEM_CACHE(drm_buddy_block, 0); + if (!slab_blocks) + return -ENOMEM; + + return 0; +} + +#endif /* HAVE_DRM_DRM_BUDDY_H */ \ No newline at end of file diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c index bd158234c6db0..a98196918c9f9 100644 --- a/drivers/gpu/drm/amd/amdkcl/main.c +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -16,6 +16,11 @@ extern void amdkcl_sched_init(void); extern void amdkcl_numa_init(void); extern void amdkcl_workqueue_init(void); +#ifndef HAVE_DRM_DRM_BUDDY_H +extern int amdkcl_drm_buddy_module_init(void); +extern void amdkcl_drm_buddy_module_exit(void); +#endif + int __init amdkcl_init(void) { amdkcl_symbol_init(); @@ -31,6 +36,9 @@ int __init amdkcl_init(void) amdkcl_sched_init(); amdkcl_numa_init(); amdkcl_workqueue_init(); +#ifndef HAVE_DRM_DRM_BUDDY_H + amdkcl_drm_buddy_module_init(); +#endif return 0; } @@ -38,6 +46,9 @@ module_init(amdkcl_init); void __exit amdkcl_exit(void) { +#ifndef HAVE_DRM_DRM_BUDDY_H + amdkcl_drm_buddy_module_exit(); +#endif } module_exit(amdkcl_exit); diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index e9b12c3982507..fe458b9b1f4cc 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -98,5 +98,5 @@ #include #include #include - +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/header/drm/drm_buddy.h b/include/kcl/header/drm/drm_buddy.h new file mode 100644 index 0000000000000..37aa64b07a8e6 --- /dev/null +++ b/include/kcl/header/drm/drm_buddy.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DRM_BUDDY_H_H_ +#define _KCL_HEADER_DRM_BUDDY_H_H_ + +#ifdef HAVE_DRM_DRM_BUDDY_H +#include_next +#else +#include +#endif + +#endif diff --git a/include/kcl/kcl_drm_buddy.h b/include/kcl/kcl_drm_buddy.h new file mode 100644 index 0000000000000..5f13318751887 --- /dev/null +++ b/include/kcl/kcl_drm_buddy.h @@ -0,0 +1,161 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2021 Intel Corporation + */ +#ifndef __KCL_KCL_DRM_BUDDY_H__ +#define __KCL_KCL_DRM_BUDDY_H__ + +#ifdef HAVE_DRM_DRM_BUDDY_H +#include +#else +#include +#include +#include +#include +#include + +#define range_overflows(start, size, max) ({ \ + typeof(start) start__ = (start); \ + typeof(size) size__ = (size); \ + typeof(max) max__ = (max); \ + (void)(&start__ == &size__); \ + (void)(&start__ == &max__); \ + start__ >= max__ || size__ > max__ - start__; \ +}) + +#define DRM_BUDDY_RANGE_ALLOCATION (1 << 0) +#define DRM_BUDDY_TOPDOWN_ALLOCATION (1 << 1) + +struct drm_buddy_block { +#define DRM_BUDDY_HEADER_OFFSET GENMASK_ULL(63, 12) +#define DRM_BUDDY_HEADER_STATE GENMASK_ULL(11, 10) +#define DRM_BUDDY_ALLOCATED (1 << 10) +#define DRM_BUDDY_FREE (2 << 10) +#define DRM_BUDDY_SPLIT (3 << 10) +/* Free to be used, if needed in the future */ +#define DRM_BUDDY_HEADER_UNUSED GENMASK_ULL(9, 6) +#define DRM_BUDDY_HEADER_ORDER GENMASK_ULL(5, 0) + u64 header; + + struct drm_buddy_block *left; + struct drm_buddy_block *right; + struct drm_buddy_block *parent; + + void *private; /* owned by creator */ + + /* + * While the block is allocated by the user through drm_buddy_alloc*, + * the user has ownership of the link, for example to maintain within + * a list, if so desired. As soon as the block is freed with + * drm_buddy_free* ownership is given back to the mm. + */ + struct list_head link; + struct list_head tmp_link; +}; + +/* Order-zero must be at least PAGE_SIZE */ +#define DRM_BUDDY_MAX_ORDER (63 - PAGE_SHIFT) + +/* + * Binary Buddy System. + * + * Locking should be handled by the user, a simple mutex around + * drm_buddy_alloc* and drm_buddy_free* should suffice. + */ +struct drm_buddy { + /* Maintain a free list for each order. */ + struct list_head *free_list; + + /* + * Maintain explicit binary tree(s) to track the allocation of the + * address space. This gives us a simple way of finding a buddy block + * and performing the potentially recursive merge step when freeing a + * block. Nodes are either allocated or free, in which case they will + * also exist on the respective free list. + */ + struct drm_buddy_block **roots; + + /* + * Anything from here is public, and remains static for the lifetime of + * the mm. Everything above is considered do-not-touch. + */ + unsigned int n_roots; + unsigned int max_order; + + /* Must be at least PAGE_SIZE */ + u64 chunk_size; + u64 size; + u64 avail; +}; + +static inline u64 +drm_buddy_block_offset(struct drm_buddy_block *block) +{ + return block->header & DRM_BUDDY_HEADER_OFFSET; +} + +static inline unsigned int +drm_buddy_block_order(struct drm_buddy_block *block) +{ + return block->header & DRM_BUDDY_HEADER_ORDER; +} + +static inline unsigned int +drm_buddy_block_state(struct drm_buddy_block *block) +{ + return block->header & DRM_BUDDY_HEADER_STATE; +} + +static inline bool +drm_buddy_block_is_allocated(struct drm_buddy_block *block) +{ + return drm_buddy_block_state(block) == DRM_BUDDY_ALLOCATED; +} + +static inline bool +drm_buddy_block_is_free(struct drm_buddy_block *block) +{ + return drm_buddy_block_state(block) == DRM_BUDDY_FREE; +} + +static inline bool +drm_buddy_block_is_split(struct drm_buddy_block *block) +{ + return drm_buddy_block_state(block) == DRM_BUDDY_SPLIT; +} + +static inline u64 +drm_buddy_block_size(struct drm_buddy *mm, + struct drm_buddy_block *block) +{ + return mm->chunk_size << drm_buddy_block_order(block); +} + +int drm_buddy_init(struct drm_buddy *mm, u64 size, u64 chunk_size); + +void drm_buddy_fini(struct drm_buddy *mm); + +struct drm_buddy_block * +drm_get_buddy(struct drm_buddy_block *block); + +int drm_buddy_alloc_blocks(struct drm_buddy *mm, + u64 start, u64 end, u64 size, + u64 min_page_size, + struct list_head *blocks, + unsigned long flags); + +int drm_buddy_block_trim(struct drm_buddy *mm, + u64 new_size, + struct list_head *blocks); + +void drm_buddy_free_block(struct drm_buddy *mm, struct drm_buddy_block *block); + +void drm_buddy_free_list(struct drm_buddy *mm, struct list_head *objects); + +void drm_buddy_print(struct drm_buddy *mm, struct drm_printer *p); +void drm_buddy_block_print(struct drm_buddy *mm, + struct drm_buddy_block *block, + struct drm_printer *p); + +#endif /* HAVE_DRM_DRM_BUDDY_H */ +#endif /* __KCL_KCL_DRM_BUDDY_H__ */ From cf6aafe73daeefe704381a9da4f2667f168509dc Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 25 Aug 2022 09:43:28 +0800 Subject: [PATCH 0762/1868] drm/amdkcl: Remove the redundant reference of header file Signed-off-by: Ma Jun Change-Id: I257d7940e5770ce5399d72039ab47328cc3b105b --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 6cf54d34b6a0d..3182305c4b31f 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -96,7 +96,6 @@ #include #include #include -#include #include From ffe8d43017d2c24b96642699e8495ac9afa25f21 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 25 Aug 2022 10:04:40 +0800 Subject: [PATCH 0763/1868] drm/amdkcl: Test if drm_gem_plane_helper_prepare_fb() is defined Signed-off-by: Ma Jun Change-Id: Ie8eee916043ff4e7a52a256f548d6b89782259bc --- .../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 4 ++++ drivers/gpu/drm/amd/dkms/config/config.h | 4 ++++ .../dkms/m4/drm_gem_plane_helper_prepare_fb.m4 | 18 ++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 27 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_gem_plane_helper_prepare_fb.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index fc125b94bceab..8b3287f7a436a 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -26,7 +26,9 @@ #include #include +#ifdef HAVE_DRM_GEM_PLANE_HELPER_PREPARE_FB #include +#endif #include #include @@ -1056,9 +1058,11 @@ static int amdgpu_dm_plane_helper_prepare_fb(struct drm_plane *plane, goto error_unpin; } +#ifdef HAVE_DRM_GEM_PLANE_HELPER_PREPARE_FB r = drm_gem_plane_helper_prepare_fb(plane, new_state); if (unlikely(r != 0)) goto error_unpin; +#endif amdgpu_bo_unreserve(rbo); diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index c90e5e61b257e..1ac18b80aa28f 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -575,6 +575,10 @@ /* whether struct drm_framebuffer have format */ #define HAVE_DRM_FRAMEBUFFER_FORMAT 1 + + /* drm_gem_plane_helper_prepare_fb() is available */ + #define HAVE_DRM_GEM_PLANE_HELPER_PREPARE_FB 1 + /* drm_gem_map_attach() wants 2 arguments */ /* #undef HAVE_DRM_GEM_MAP_ATTACH_2ARGS */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_gem_plane_helper_prepare_fb.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_gem_plane_helper_prepare_fb.m4 new file mode 100644 index 0000000000000..e0311f6ebd145 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_gem_plane_helper_prepare_fb.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit 96d4f267e40f9509e8a66e2b39e8b95655617693 +dnl # Author: Linus Torvalds +dnl # Date: Thu Jan 3 18:57:57 2019 -0800 +dnl # Remove 'type' argument from access_ok() function +dnl # +AC_DEFUN([AC_AMDGPU_DRM_GEM_PLANE_HELPER_PREPARE_FB], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + drm_gem_plane_helper_prepare_fb(NULL, NULL); + ],[ + AC_DEFINE(HAVE_DRM_GEM_PLANE_HELPER_PREPARE_FB, 1, + [drm_gem_plane_helper_prepare_fb() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 1998834f45c6a..4a72111c3972e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -213,6 +213,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DSC_CONFIG_SIMPLE_422 AC_AMDGPU_DRM_DSC_PPS_PAYLOAD_PACK AC_AMDGPU_DRM_DSC_COMPUTE_RC_PARAMETERS + AC_AMDGPU_DRM_GEM_PLANE_HELPER_PREPARE_FB AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 76b3a10a3b1358ca2c880f284381045a1e344cb3 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Tue, 19 Jul 2022 21:00:28 -0400 Subject: [PATCH 0764/1868] drm/amdkfd: Add placeholder for deprecated CMA ioctl Implement a dummy ioctl to avoid undefined behaviour. Signed-off-by: Felix Kuehling Change-Id: I0cd535d891c64022d72aa4dc1b724944f558a219 --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 10 ++++++++++ include/uapi/linux/kfd_ioctl.h | 21 +++++++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 1d6c0457fbffc..9d136d6b88849 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1739,6 +1739,13 @@ static int kfd_ioctl_export_dmabuf(struct file *filep, return ret; } +/* Place holder for deprecated CMA API */ +static int kfd_ioctl_cross_memory_copy_deprecated(struct file *filep, + struct kfd_process *local_p, void *data) { + dev_dbg(kfd_device, "AMDKFD_IOC_CROSS_MEMORY_COPY is deprecated.\n"); + return -EINVAL; +} + /* Handle requests for watching SMI events */ static int kfd_ioctl_smi_events(struct file *filep, struct kfd_process *p, void *data) @@ -3419,6 +3426,9 @@ static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = { AMDKFD_IOCTL_DEF(AMDKFD_IOC_RLC_SPM, kfd_ioctl_rlc_spm, 0), + + AMDKFD_IOCTL_DEF(AMDKFD_IOC_CROSS_MEMORY_COPY_DEPRECATED, + kfd_ioctl_cross_memory_copy_deprecated, 0), }; static long kfd_ioctl(struct file *filep, unsigned int cmd, unsigned long arg) diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h index 4522660ee4003..35a8850d12fa8 100644 --- a/include/uapi/linux/kfd_ioctl.h +++ b/include/uapi/linux/kfd_ioctl.h @@ -754,6 +754,23 @@ struct kfd_ioctl_ipc_import_handle_args { __u32 flags; /* from KFD */ }; +struct kfd_ioctl_cross_memory_copy_deprecated_args { + /* to KFD: Process ID of the remote process */ + __u32 pid; + /* to KFD: See above definition */ + __u32 flags; + /* to KFD: Source GPU VM range */ + __u64 src_mem_range_array; + /* to KFD: Size of above array */ + __u64 src_mem_array_size; + /* to KFD: Destination GPU VM range */ + __u64 dst_mem_range_array; + /* to KFD: Size of above array */ + __u64 dst_mem_array_size; + /* from KFD: Total amount of bytes copied */ + __u64 bytes_copied; +}; + /* Guarantee host access to memory */ #define KFD_IOCTL_SVM_FLAG_HOST_ACCESS 0x00000001 /* Fine grained coherency between all devices with access */ @@ -1696,6 +1713,10 @@ struct kfd_ioctl_dbg_trap_args { #define AMDKFD_IOC_IPC_EXPORT_HANDLE \ AMDKFD_IOWR(0x81, struct kfd_ioctl_ipc_export_handle_args) + +#define AMDKFD_IOC_CROSS_MEMORY_COPY_DEPRECATED \ + AMDKFD_IOWR(0x83, struct kfd_ioctl_cross_memory_copy_deprecated_args) + #define AMDKFD_IOC_RLC_SPM \ AMDKFD_IOWR(0x84, struct kfd_ioctl_spm_args) From 4e2cf4407e087eafa44bb48c4f937fa4b17f93c4 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 25 Aug 2022 13:30:33 +0800 Subject: [PATCH 0765/1868] drm/amdkcl: Wrap the code with macro HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED Mainly fix the build error on legacy os by wrapping the code with macro HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED Signed-off-by: Ma Jun Change-Id: I3f0a1c1e86f82153930eefde88ad3e7d904308e2 --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 3 ++- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 4 ++++ 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 10289e627b8c1..855360c1abc7d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -806,6 +806,7 @@ uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev, return domain; } +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED static const struct drm_format_info dcc_formats[] = { { .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2, .cpp = { 4, 0, }, .block_w = {1, 1, 1}, .block_h = {1, 1, 1}, .hsub = 1, .vsub = 1, }, @@ -898,7 +899,7 @@ amdgpu_lookup_format_info(u32 format, uint64_t modifier) /* returning NULL will cause the default format structs to be used. */ return NULL; } - +#endif /* * Tries to extract the renderable DCC offset from the opaque metadata attached diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 8b3287f7a436a..aa6dbeb3c3f5e 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -94,10 +94,12 @@ enum dm_micro_swizzle { MICRO_SWIZZLE_R = 3 }; +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED const struct drm_format_info *amdgpu_dm_plane_get_format_info(const struct drm_mode_fb_cmd2 *cmd) { return amdgpu_lookup_format_info(cmd->pixel_format, cmd->modifier[0]); } +#endif void amdgpu_dm_plane_fill_blending_from_plane_state(const struct drm_plane_state *plane_state, bool *per_pixel_alpha, bool *pre_multiplied_alpha, @@ -1609,6 +1611,7 @@ static struct drm_plane_state *amdgpu_dm_plane_drm_plane_duplicate_state(struct return &dm_plane_state->base; } +#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED static bool amdgpu_dm_plane_format_mod_supported(struct drm_plane *plane, uint32_t format, uint64_t modifier) @@ -1670,6 +1673,7 @@ static bool amdgpu_dm_plane_format_mod_supported(struct drm_plane *plane, return true; } +#endif static void amdgpu_dm_plane_drm_plane_destroy_state(struct drm_plane *plane, struct drm_plane_state *state) From 718a3c413a7813b4a134a2c00e9471f1c47372b2 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 25 Aug 2022 14:29:07 +0800 Subject: [PATCH 0766/1868] drm/amdkcl: Wrap the code with kcl macro Wrap the code with macro HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE to avoid build error on legacy os. Signed-off-by: Ma Jun Change-Id: I761a11a9a270c08295807bb7f3a0bc340e82e416 --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 3182305c4b31f..a3c3a0992cfca 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -7748,6 +7748,7 @@ static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, struct drm_crtc_state *crtc_state, struct drm_connector_state *conn_state) { +#if defined(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE) struct drm_atomic_state *state = crtc_state->state; struct drm_connector *connector = conn_state->connector; struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); @@ -7795,6 +7796,7 @@ static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots); return dm_new_connector_state->vcpi_slots; } +#endif return 0; } From b5005fbba9af6a4478d906eed252b6b8cdd385ca Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 25 Aug 2022 13:46:45 +0800 Subject: [PATCH 0767/1868] drm/amdkcl: Fix the error caused by drm_gem_object->resv Use the amdkcl_ttm_resvp(bo) instead of drm_gem_object->resv Signed-off-by: Ma Jun Change-Id: Iada5d30f196ef81d4ea5148db6d1df84c96d9f90 --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index aa6dbeb3c3f5e..c8b9bc965ec9e 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -1036,7 +1036,7 @@ static int amdgpu_dm_plane_helper_prepare_fb(struct drm_plane *plane, return r; } - r = dma_resv_reserve_fences(rbo->tbo.base.resv, 1); + r = dma_resv_reserve_fences(amdkcl_ttm_resvp(&rbo->tbo), 1); if (r) { dev_err(adev->dev, "reserving fence slot failed (%d)\n", r); goto error_unlock; From f01618020193fc803dc0173aeb7c9b190a258913 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 25 Aug 2022 13:44:44 +0800 Subject: [PATCH 0768/1868] drm/amdkcl: Implement the bitmap_to_arr32() Implement the bitmap_to_arr32() for legacy os Signed-off-by: Ma Jun Change-Id: I9802dd45c5ce57a7bd4c83ea12e0c7ad689a83a6 --- drivers/gpu/drm/amd/amdkcl/kcl_bitmap.c | 29 ++++++++++++++++++- drivers/gpu/drm/amd/dkms/config/config.h | 4 ++- .../gpu/drm/amd/dkms/m4/bitmap_to_arr32.m4 | 16 ++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/backport/kcl_bitmap.h | 4 +++ include/kcl/kcl_bitmap.h | 12 ++++++++ 6 files changed, 64 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/bitmap_to_arr32.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_bitmap.c b/drivers/gpu/drm/amd/amdkcl/kcl_bitmap.c index 946b29d66408b..2b0c29936bc96 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_bitmap.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_bitmap.c @@ -19,9 +19,10 @@ * DEALINGS IN THE SOFTWARE. */ +#include + #ifndef HAVE_BITMAP_FUNCS -#include #include #include #include @@ -46,3 +47,29 @@ void kcl_bitmap_free(const unsigned long *bitmap) EXPORT_SYMBOL(kcl_bitmap_free); #endif /* HAVE_BITMAP_FUNCS */ +#ifndef HAVE_BITMAP_TO_ARR32 +#if BITS_PER_LONG == 64 +/** + * kcl_bitmap_to_arr32 - copy the contents of bitmap to a u32 array of bits + * @buf: array of u32 (in host byte order), the dest bitmap + * @bitmap: array of unsigned longs, the source bitmap + * @nbits: number of bits in @bitmap + */ +void kcl_bitmap_to_arr32(u32 *buf, const unsigned long *bitmap, unsigned int nbits) +{ + unsigned int i, halfwords; + + halfwords = DIV_ROUND_UP(nbits, 32); + for (i = 0; i < halfwords; i++) { + buf[i] = (u32) (bitmap[i/2] & UINT_MAX); + if (++i < halfwords) + buf[i] = (u32) (bitmap[i/2] >> 32); + } + + /* Clear tail bits in last element of array beyond nbits. */ + if (nbits % BITS_PER_LONG) + buf[halfwords - 1] &= (u32) (UINT_MAX >> ((-nbits) & 31)); +} +EXPORT_SYMBOL(kcl_bitmap_to_arr32); +#endif +#endif \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 1ac18b80aa28f..a900814a484b0 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -52,6 +52,9 @@ /* bitmap_free() is available */ #define HAVE_BITMAP_FUNCS 1 +/* bitmap_to_arr32() is available */ +#define HAVE_BITMAP_TO_ARR32 1 + /* cancel_work() is available */ #define HAVE_CANCEL_WORK 1 @@ -575,7 +578,6 @@ /* whether struct drm_framebuffer have format */ #define HAVE_DRM_FRAMEBUFFER_FORMAT 1 - /* drm_gem_plane_helper_prepare_fb() is available */ #define HAVE_DRM_GEM_PLANE_HELPER_PREPARE_FB 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/bitmap_to_arr32.m4 b/drivers/gpu/drm/amd/dkms/m4/bitmap_to_arr32.m4 new file mode 100644 index 0000000000000..3c981e3fa9518 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/bitmap_to_arr32.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v5.19-rc1-22-525d6515604e +dnl # drm/amd/pm: use bitmap_{from,to}_arr32 where appropriate +dnl # +AC_DEFUN([AC_AMDGPU_BITMAP_TO_ARR32], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + bitmap_to_arr32(NULL, NULL, 0); + ],[ + AC_DEFINE(HAVE_BITMAP_TO_ARR32, 1, + [bitmap_to_arr32() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 4a72111c3972e..d4a8341f98af0 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -214,6 +214,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DSC_PPS_PAYLOAD_PACK AC_AMDGPU_DRM_DSC_COMPUTE_RC_PARAMETERS AC_AMDGPU_DRM_GEM_PLANE_HELPER_PREPARE_FB + AC_AMDGPU_BITMAP_TO_ARR32 AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/backport/kcl_bitmap.h b/include/kcl/backport/kcl_bitmap.h index 5871f13aff831..1382530929001 100644 --- a/include/kcl/backport/kcl_bitmap.h +++ b/include/kcl/backport/kcl_bitmap.h @@ -31,4 +31,8 @@ #define bitmap_free kcl_bitmap_free #endif /* HAVE_BITMAP_FUNCS */ +#ifndef HAVE_BITMAP_TO_ARR32 +#define bitmap_to_arr32 kcl_bitmap_to_arr32 +#endif /* HAVE_BITMAP_TO_ARR32 */ + #endif /* KCL_BITMAP_H */ diff --git a/include/kcl/kcl_bitmap.h b/include/kcl/kcl_bitmap.h index f65fa8fbcc56d..f2c0863b7b7d8 100644 --- a/include/kcl/kcl_bitmap.h +++ b/include/kcl/kcl_bitmap.h @@ -39,4 +39,16 @@ unsigned long *kcl_bitmap_zalloc(unsigned int nbits, gfp_t flags); void kcl_bitmap_free(const unsigned long *bitmap); #endif /* HAVE_BITMAP_FUNCS */ +/* copy form bitmap.h */ +#ifndef HAVE_BITMAP_TO_ARR32 +#if BITS_PER_LONG == 64 +void kcl_bitmap_to_arr32(u32 *buf, const unsigned long *bitmap, + unsigned int nbits); +#else +#define kcl_bitmap_to_arr32(buf, bitmap, nbits) \ + bitmap_copy_clear_tail((unsigned long *) (buf), \ + (const unsigned long *) (bitmap), (nbits)) +#endif +#endif /* HAVE_BITMAP_TO_ARR32 */ + #endif /* KCL_BITMAP_H */ From 03310998ba74a1c87fc65c59c5a37e5d51a31124 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 24 Aug 2022 13:37:09 +0800 Subject: [PATCH 0769/1868] drm/amdkcl: Fix missing execl fence copy in dma_resv_copy_fences() add back dma_resv_iter_is_exclusive() to test current fence is excl fence Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c | 2 +- include/kcl/kcl_dma-resv.h | 11 +++++++++++ 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c b/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c index db40a6e5f035a..e6c4b9ef220d1 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c @@ -584,7 +584,7 @@ int dma_resv_copy_fences(struct dma_resv *dst, struct dma_resv *src) } dma_fence_get(f); - if (dma_resv_iter_usage(&cursor) == DMA_RESV_USAGE_WRITE) + if (dma_resv_iter_is_exclusive(&cursor)) excl = f; else RCU_INIT_POINTER(list->shared[list->shared_count++], f); diff --git a/include/kcl/kcl_dma-resv.h b/include/kcl/kcl_dma-resv.h index 39a4e3b5e67f1..4fe1fe0afac9d 100644 --- a/include/kcl/kcl_dma-resv.h +++ b/include/kcl/kcl_dma-resv.h @@ -230,6 +230,17 @@ static inline struct dma_resv_list *dma_resv_shared_list(struct dma_resv *obj) return rcu_dereference_check(obj->fence, lockdep_is_held(&(obj)->lock.base)); } +/** + * dma_resv_iter_is_exclusive - test if the current fence is the exclusive one + * @cursor: the cursor of the current position + * + * Returns true if the currently returned fence is the exclusive one. + */ +static inline bool dma_resv_iter_is_exclusive(struct dma_resv_iter *cursor) +{ + return cursor->index == 0; +} + #endif /* !defined(HAVE_DMA_RESV_FENCES) */ #if !defined(smp_store_mb) From 7a4cb95bcd977da63d8be285619f9ae30221951b Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Fri, 26 Aug 2022 15:05:52 +0800 Subject: [PATCH 0770/1868] drm/amdkcl: Check if dma_resv->seq is available Check if dma_resv->seq is available for kernel version >= 5.18.0 Signed-off-by: Ma Jun Change-Id: I17151eddb9bf97500d8abd28320505f4026b2291 --- drivers/gpu/drm/amd/dkms/Makefile | 2 +- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 | 17 +++++++++++++++++ 3 files changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 3b41a6d897f59..4755cde423517 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -12,7 +12,7 @@ endif _is_kcl_macro_defined=$(shell grep $1 $(src)/amd/dkms/config/config.h | grep -q "define" && echo "y" || echo "n") -ifeq ($(call _is_kcl_macro_defined,HAVE_DMA_RESV_SEQ),n) +ifeq ($(call _is_kcl_macro_defined,HAVE_DMA_RESV_SEQ_BUG),y) $(error dma_resv->seq is missing., exit...) endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index a900814a484b0..18c1a1cb412a5 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -127,6 +127,9 @@ /* dma_resv->seq is seqcount_ww_mutex_t */ /* #undef HAVE_DMA_RESV_SEQCOUNT_WW_MUTEX_T */ +/* bug for missing dma_resv->seq */ +/* #undef HAVE_DMA_RESV_SEQ_BUG */ + /* down_read_killable() is available */ #define HAVE_DOWN_READ_KILLABLE 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 index 9d11fb99c397a..93c6dbc25ae22 100644 --- a/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 @@ -36,6 +36,23 @@ AC_DEFUN([AC_AMDGPU_DMA_RESV_SEQ], [ ], [ AC_DEFINE(HAVE_DMA_RESV_SEQ, 1, [dma_resv->seq is available]) + ],[ + dnl # + dnl # dma_resv->seq is dropped since kernle 5.18.0 + dnl # So trigger the bug only for the kernel_version < 5.18.0 + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + #if LINUX_VERSION_CODE < KERNEL_VERSION(5, 18, 0) + int this_is_bug = 0; + #else + this_is_not_bug(); + #endif + ], [ + AC_DEFINE(HAVE_DMA_RESV_SEQ_BUG, 1, + [bug for missing dma_resv->seq]) + ]) ]) ]) ]) From 8293443fed7c5b0715623ed41d7416b877ad17b1 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 16 Aug 2022 17:05:25 +0800 Subject: [PATCH 0771/1868] drm/amdkcl: add buffer cache as available memory [Why] For system cache large amount of file buffer, free memory occupancy calculated from patch "f32b51764601 drm/amdkcl: test for available memory" will smaller than 20% and will hang the dkms install process. [How] consider buffer cache also as available memory Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index d4a8341f98af0..fc89ae3f0cc07 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -606,8 +606,8 @@ dnl # AC_KERNEL_FREE_MEM dnl # return true if available memory >20% dnl # AC_DEFUN([AC_KERNEL_FREE_MEM], [ - free_mem=$(free -t | awk '/^Total:/ { - printf("%d\n", $[4] / $[2] * 100) + free_mem=$(free -t | awk '/^Mem:/ { BUF_MEM=$[6]} /^Total:/ { TOTAL_MEM=$[2];FREE_MEM=$[4] } END { + printf("%d\n", (BUF_MEM + FREE_MEM) / TOTAL_MEM * 100) }') AS_IF([[[ $free_mem -gt 20 ]]], [ From 6d4ee84422709e299304e73c84088d7df7646626 Mon Sep 17 00:00:00 2001 From: Guchun Chen Date: Wed, 24 Aug 2022 22:09:58 +0800 Subject: [PATCH 0772/1868] drm/amdgpu: create p2p links unconditionally in dkms P2P needs to be enabled on old kernels without setting CONFIG_HSA_AMD_P2P, so p2p links needs to be created unconditionally. This also releases build option from upstream. Suggested-by: Ramesh Errabolu Signed-off-by: Guchun Chen Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index 1c416a610b00c..99deebdcac0d4 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -1582,7 +1582,6 @@ static int kfd_create_indirect_link_prop(struct kfd_topology_device *kdev, int g return ret; } -#if defined(CONFIG_HSA_AMD_P2P) static int kfd_add_peer_prop(struct kfd_topology_device *kdev, struct kfd_topology_device *peer, int from, int to) { @@ -1650,16 +1649,12 @@ static int kfd_add_peer_prop(struct kfd_topology_device *kdev, return ret; } -#endif static int kfd_dev_create_p2p_links(void) { struct kfd_topology_device *dev; struct kfd_topology_device *new_dev; -#if defined(CONFIG_HSA_AMD_P2P) - uint32_t i; -#endif - uint32_t k; + uint32_t i, k; int ret = 0; k = 0; @@ -1680,7 +1675,6 @@ static int kfd_dev_create_p2p_links(void) goto out; /* create p2p links */ -#if defined(CONFIG_HSA_AMD_P2P) i = 0; list_for_each_entry(dev, &topology_device_list, list) { if (dev == new_dev) @@ -1701,7 +1695,6 @@ static int kfd_dev_create_p2p_links(void) next: i++; } -#endif out: return ret; From 4b7f1d37552f7b3f73b0171e7d4ff609d5700477 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 26 Aug 2022 17:10:21 +0800 Subject: [PATCH 0773/1868] drm/amdkcl: Test whether smca_get_bank_type() has two arguments It's caused by 91f75eb481cfaee5c4ed8fb5214bf2fbfa04bd7b "x86/MCE/AMD, EDAC/mce_amd: Support non-uniform MCA bank type enumeration" Signed-off-by: Asher Song Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_mce_amd.c | 29 +++++++++-- drivers/gpu/drm/amd/dkms/config/config.h | 7 ++- .../gpu/drm/amd/dkms/m4/smca_get_bank_type.m4 | 52 +++++++++++++------ include/kcl/kcl_mce.h | 8 ++- 5 files changed, 70 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 8fee69697535d..f5b67adb65ae7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -4173,7 +4173,7 @@ static int amdgpu_bad_page_notifier(struct notifier_block *nb, * and error occurred in DramECC (Extended error code = 0) then only * process the error, else bail out. */ - if (!m || !((smca_get_bank_type(m->extcpu, m->bank) == SMCA_UMC_V2) && + if (!m || !((kcl_smca_get_bank_type(m->extcpu, m->bank) == SMCA_UMC_V2) && (XEC(m->status, 0x3f) == 0x0))) return NOTIFY_DONE; diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_mce_amd.c b/drivers/gpu/drm/amd/amdkcl/kcl_mce_amd.c index 30e62d94fbead..bd90d447713f5 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_mce_amd.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_mce_amd.c @@ -12,10 +12,19 @@ #ifdef CONFIG_X86_MCE_AMD #include -#ifndef HAVE_SMCA_GET_BANK_TYPE +#if defined(HAVE_SMCA_GET_BANK_TYPE_WITH_TWO_ARGUMENTS) +enum smca_bank_types kcl_smca_get_bank_type(unsigned int cpu, unsigned int bank) +{ + return smca_get_bank_type(cpu, bank); +} +#elif defined(HAVE_SMCA_GET_BANK_TYPE_WITH_ONE_ARGUMENT) +enum smca_bank_types kcl_smca_get_bank_type(unsigned int cpu, unsigned int bank) +{ + return smca_get_bank_type(bank); +} /* Copied from v5.15-rc2-452-gf38ce910d8df:arch/x86/kernel/cpu/mce/amd.c and modified for KCL */ -#ifdef HAVE_SMCA_BANK_STRUCT +#elif defined(HAVE_STRUCT_SMCA_BANK) enum smca_bank_types smca_get_bank_type(unsigned int bank) { struct smca_bank *b; @@ -29,14 +38,24 @@ enum smca_bank_types smca_get_bank_type(unsigned int bank) return b->hwid->bank_type; } +enum smca_bank_types kcl_smca_get_bank_type(unsigned int cpu, unsigned int bank) +{ + return smca_get_bank_type(bank); +} + #else int smca_get_bank_type(unsigned int bank) { pr_warn_once("smca_get_bank_type is not supported\n"); return 0; } -#endif /* HAVE_SMCA_BANK_STRUCT */ -EXPORT_SYMBOL_GPL(smca_get_bank_type); -#endif /* HAVE_SMCA_GET_BANK_TYPE */ + +int kcl_smca_get_bank_type(unsigned int cpu, unsigned int bank) +{ + return smca_get_bank_type(bank); +} + +#endif +EXPORT_SYMBOL_GPL(kcl_smca_get_bank_type); #endif /* CONFIG_X86_MCE_AMD */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 18c1a1cb412a5..b0162ceea2d3e 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1080,8 +1080,11 @@ /* whether si_mem_available() is available */ #define HAVE_SI_MEM_AVAILABLE 1 -/* smca_get_bank_type() is available */ -#define HAVE_SMCA_GET_BANK_TYPE 1 +/* smca_get_bank_type(x) is available */ +/* #undef HAVE_SMCA_GET_BANK_TYPE_WITH_ONE_ARGUMENT */ + +/* whether smca_get_bank_type(x, x) is available */ +#define HAVE_SMCA_GET_BANK_TYPE_WITH_TWO_ARGUMENTS 1 /* is_smca_umc_v2() is available */ /* #undef HAVE_SMCA_UMC_V2 */ diff --git a/drivers/gpu/drm/amd/dkms/m4/smca_get_bank_type.m4 b/drivers/gpu/drm/amd/dkms/m4/smca_get_bank_type.m4 index 2ed1eef7d5149..4dbfe78524f84 100644 --- a/drivers/gpu/drm/amd/dkms/m4/smca_get_bank_type.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/smca_get_bank_type.m4 @@ -1,27 +1,49 @@ dnl # -dnl # -dnl # v5.15-rc2-452-gf38ce910d8df x86/MCE/AMD: Export smca_get_bank_type symbol +dnl # v5.16-rc1-22-g91f75eb481cf x86/MCE/AMD, EDAC/mce_amd: Support non-uniform MCA bank type enumeration dnl # AC_DEFUN([AC_AMDGPU_SMCA_GET_BANK_TYPE], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([smca_get_bank_type], - [arch/x86/kernel/cpu/mce/amd.c], [ - AC_DEFINE(HAVE_SMCA_GET_BANK_TYPE, 1, - [smca_get_bank_type() is available]) - ], [ - dnl # + AC_KERNEL_TRY_COMPILE([ + #include + #include + ],[ + unsigned int a = 0, b = 0; + enum smca_bank_types bank_type; + bank_type = smca_get_bank_type(a, b); + ],[ + AC_DEFINE(HAVE_SMCA_GET_BANK_TYPE_WITH_TWO_ARGUMENTS, 1, + [whether smca_get_bank_type(x, x) is available]) + ],[ dnl # - dnl # v4.9-rc4-4-g79349f529ab1 x86/RAS: Simplify SMCA bank descriptor struct + dnl # v5.15-rc2-452-gf38ce910d8df x86/MCE/AMD: Export smca_get_bank_type symbol dnl # AC_KERNEL_TRY_COMPILE([ + #include #include - ], [ - struct smca_bank *b = NULL; - b->id = 0; - ], [ - AC_DEFINE(HAVE_STRUCT_SMCA_BANK, 1, - [struct smca_bank is available]) + ],[ + unsigned int a = 0; + enum smca_bank_types bank_type; + bank_type = smca_get_bank_type(a); + ],[ + AC_DEFINE(HAVE_SMCA_GET_BANK_TYPE_WITH_ONE_ARGUMENT, 1, + [smca_get_bank_type(x) is available]) + ],[ + dnl # + dnl # v4.9-rc4-4-g79349f529ab1 x86/RAS: Simplify SMCA bank descriptor struct + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + #include + ],[ + struct smca_bank *b = NULL; + b->id = 0; + ], [ + AC_DEFINE(HAVE_STRUCT_SMCA_BANK, 1, + [struct smca_bank is available]) + ]) + ]) ]) + ]) ]) diff --git a/include/kcl/kcl_mce.h b/include/kcl/kcl_mce.h index 80625b60944b7..fd6098c99a240 100644 --- a/include/kcl/kcl_mce.h +++ b/include/kcl/kcl_mce.h @@ -11,12 +11,10 @@ #define XEC(x, mask) (((x) >> 16) & mask) #endif -#if !defined(HAVE_SMCA_GET_BANK_TYPE) -#ifdef HAVE_SMCA_BANK_STRUCT -enum smca_bank_types smca_get_bank_type(unsigned int bank); +#if defined(HAVE_SMCA_GET_BANK_TYPE_WITH_TWO_ARGUMENTS) || defined(HAVE_SMCA_GET_BANK_TYPE_WITH_ONE_ARGUMENT) || defined(HAVE_STRUCT_SMCA_BANK) +enum smca_bank_types kcl_smca_get_bank_type(unsigned int cpu, unsigned int bank); #else -int smca_get_bank_type(unsigned int bank); -#endif +int kcl_smca_get_bank_type(unsigned int cpu, unsigned int bank); #endif #ifndef HAVE_MCE_PRIO_UC From f21ff7458cd1eb514d22f5d56058704fa06dd652 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Thu, 8 Sep 2022 12:37:59 -0400 Subject: [PATCH 0774/1868] drm/amdkcl: limit number of tests to number of CPU Limit the number of tests to be executed in parallel to the number of processors available in the system. Checking for available memory may cause a hang in the infinite loop on the system with small amount of the system memory. Change-Id: Ia7cc2e56d068c642975026c2e1b577128970c563 Signed-off-by: Slava Grigorev Reviewed-by: Jeremy Newton Reviewed-by: Slava Abramov --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 32 ++++++++------------------- 1 file changed, 9 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index fc89ae3f0cc07..cc3f0f968a8e3 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -601,22 +601,6 @@ AC_DEFUN([AC_KERNEL_CHECK_HEADERS], [ AC_CHECK_HEADERS([$1],[AS_TR_CPP([HAVE_$1])=1],,[-]) ]) -dnl # -dnl # AC_KERNEL_FREE_MEM -dnl # return true if available memory >20% -dnl # -AC_DEFUN([AC_KERNEL_FREE_MEM], [ - free_mem=$(free -t | awk '/^Mem:/ { BUF_MEM=$[6]} /^Total:/ { TOTAL_MEM=$[2];FREE_MEM=$[4] } END { - printf("%d\n", (BUF_MEM + FREE_MEM) / TOTAL_MEM * 100) - }') - - AS_IF([[[ $free_mem -gt 20 ]]], [ - $1 - ], [ - $2 - ]) -]) - dnl # dnl # AC_KERNEL_DO_BACKGROUND dnl # $1: contents to be executed @@ -626,14 +610,16 @@ AC_DEFUN([AC_KERNEL_DO_BACKGROUND], [ AC_KERNEL_TMP_BUILD_DIR([$1]) } - while : + AC_CHECK_PROG(NPROC, nproc, yes) + AS_IF([test x"$NPROC" != x"yes"], [ + ncpu=1 + ], [ + ncpu=$(nproc) + ]) + + while [[ $(jobs | wc -l) -gt $ncpu ]] do - AC_KERNEL_FREE_MEM([rc=0], [rc=1]) - if test $rc -ne 0; then : - sleep 1 - else : - break - fi + sleep 0.1 done do_background & From 0fb867da4427be8cbc9b5275c2205488b0a5adec Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 9 Sep 2022 15:12:04 +0800 Subject: [PATCH 0775/1868] drm/amdkcl: wrap code under macro HAVE_PCI_DEV_LTR_PATH It's caused by 9000fc3a77dbb05224a0053a85a0d515b4069286 "drm/amdgpu: Don't enable LTR if not supported" There is no member ltr_path in struc pci_dev in old kernels. So wrap the code under macro HAVE_PCI_DEV_LTR Signed-off-by: Asher Song Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c | 3 ++- drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c | 3 ++- drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 2 ++ 3 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c index fa479dfa1ec15..80cd6a08a0388 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c @@ -461,9 +461,10 @@ static void nbio_v2_3_program_aspm(struct amdgpu_device *adev) /* Don't bother about LTR if LTR is not enabled * in the path */ +#ifdef HAVE_PCI_DEV_LTR_PATH if (adev->pdev->ltr_path) nbio_v2_3_program_ltr(adev); - +#endif def = data = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP3); data |= 0x5DE0 << RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT; data |= 0x0010 << RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT; diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c index 34180c6070dd2..08f428586624a 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_1.c @@ -362,9 +362,10 @@ static void nbio_v6_1_program_aspm(struct amdgpu_device *adev) /* Don't bother about LTR if LTR is not enabled * in the path */ +#ifdef HAVE_PCI_DEV_LTR_PATH if (adev->pdev->ltr_path) nbio_v6_1_program_ltr(adev); - +#endif def = data = RREG32_PCIE(smnRCC_BIF_STRAP3); data |= 0x5DE0 << RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT; data |= 0x0010 << RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT; diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c index 8d80df94bd8b5..9446bf6f82c1e 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c @@ -761,8 +761,10 @@ static void nbio_v7_4_program_aspm(struct amdgpu_device *adev) /* Don't bother about LTR if LTR is not enabled * in the path */ +#ifdef HAVE_PCI_DEV_LTR_PATH if (adev->pdev->ltr_path) nbio_v7_4_program_ltr(adev); +#endif def = data = RREG32_PCIE(smnRCC_BIF_STRAP3); data |= 0x5DE0 << RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT; From 34f155454ae49fccfb4d23b64d0b83561bd4f852 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 14 Sep 2022 12:24:25 +0800 Subject: [PATCH 0776/1868] drm/amdkcl: wrap code under macro HAVE_CHUNK_ID_SYNOBJ_IN_OUT and HAVE_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL It's caused by 253c2b45dfa82a18530076bb743f67355948550c "drm/amdgpu: cleanup CS init/fini and pass1" Signed-off-by: Asher Song Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index d5c2b19caebd2..38b20493766ec 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -1504,11 +1504,15 @@ static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser) amdgpu_sync_free(&parser->sync); drm_exec_fini(&parser->exec); +#if defined(HAVE_CHUNK_ID_SYNOBJ_IN_OUT) for (i = 0; i < parser->num_post_deps; i++) { drm_syncobj_put(parser->post_deps[i].syncobj); +#if defined(HAVE_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL) kfree(parser->post_deps[i].chain); +#endif } kfree(parser->post_deps); +#endif dma_fence_put(parser->fence); From 1bb3f5db2602e5159d8e13ab70e860929f9bc66c Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 14 Sep 2022 15:35:09 +0800 Subject: [PATCH 0777/1868] drm/amdkcl: wrap code under macro HAVE_CHUNK_ID_SYNOBJ_IN_OUT, HAVE_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL, HAVE_AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES It's caused by d8ede49db6249fb8d274dde7475e7b33d2ab126c "drm/amdgpu: reorder CS code" Signed-off-by: Asher Song Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 38b20493766ec..fc163d903563c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -438,7 +438,6 @@ static int amdgpu_cs_p2_dependencies(struct amdgpu_cs_parser *p, } return 0; } - static int amdgpu_syncobj_lookup_and_add(struct amdgpu_cs_parser *p, uint32_t handle, u64 point, u64 flags) @@ -522,7 +521,9 @@ static int amdgpu_cs_p2_syncobj_out(struct amdgpu_cs_parser *p, drm_syncobj_find(p->filp, deps[i].handle); if (!p->post_deps[i].syncobj) return -EINVAL; +#if defined(HAVE_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL) p->post_deps[i].chain = NULL; +#endif p->post_deps[i].point = 0; p->num_post_deps++; } @@ -552,14 +553,14 @@ static int amdgpu_cs_p2_syncobj_timeline_signal(struct amdgpu_cs_parser *p, for (i = 0; i < num_deps; ++i) { struct amdgpu_cs_post_dep *dep = &p->post_deps[i]; - +#if defined(HAVE_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL) dep->chain = NULL; if (syncobj_deps[i].point) { dep->chain = dma_fence_chain_alloc(); if (!dep->chain) return -ENOMEM; } - +#endif dep->syncobj = drm_syncobj_find(p->filp, syncobj_deps[i].handle); if (!dep->syncobj) { @@ -572,7 +573,6 @@ static int amdgpu_cs_p2_syncobj_timeline_signal(struct amdgpu_cs_parser *p, return 0; } -#endif static int amdgpu_cs_p2_shadow(struct amdgpu_cs_parser *p, struct amdgpu_cs_chunk *chunk) @@ -611,7 +611,9 @@ static int amdgpu_cs_pass2(struct amdgpu_cs_parser *p) return r; break; case AMDGPU_CHUNK_ID_DEPENDENCIES: +#if defined(HAVE_AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES) case AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES: +#endif r = amdgpu_cs_p2_dependencies(p, chunk); if (r) return r; @@ -626,6 +628,7 @@ static int amdgpu_cs_pass2(struct amdgpu_cs_parser *p) if (r) return r; break; +#if defined(HAVE_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL) case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT: r = amdgpu_cs_p2_syncobj_timeline_wait(p, chunk); if (r) @@ -636,6 +639,7 @@ static int amdgpu_cs_pass2(struct amdgpu_cs_parser *p) if (r) return r; break; +#endif case AMDGPU_CHUNK_ID_CP_GFX_SHADOW: r = amdgpu_cs_p2_shadow(p, chunk); if (r) @@ -1504,7 +1508,6 @@ static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser) amdgpu_sync_free(&parser->sync); drm_exec_fini(&parser->exec); -#if defined(HAVE_CHUNK_ID_SYNOBJ_IN_OUT) for (i = 0; i < parser->num_post_deps; i++) { drm_syncobj_put(parser->post_deps[i].syncobj); #if defined(HAVE_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL) @@ -1512,7 +1515,6 @@ static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser) #endif } kfree(parser->post_deps); -#endif dma_fence_put(parser->fence); From 471152128ec0f7260ad209163dae20e1969ce89c Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 14 Sep 2022 17:27:20 +0800 Subject: [PATCH 0778/1868] drm/amdkcl: test whether drm_gem_object->resv is available It's caused by 708a6179d00f1d6cc060afcf7b5b6dc4e75d3ed6 "drm/amdgpu: use DMA_RESV_USAGE_BOOKKEEP v2" dd37405b55736ee33410ad653b8c2c9a2b2700c9 "drm/amdgpu: reorder CS code" Signed-off-by: Asher Song Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 8 ++++---- drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index f7a76b95b9278..b1f07e4d20d99 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -1514,7 +1514,7 @@ static int init_kfd_vm(struct amdgpu_vm *vm, void **process_info, ret = dma_resv_reserve_fences(amdkcl_ttm_resvp(&vm->root.bo->tbo), 1); if (ret) goto reserve_shared_fail; - dma_resv_add_fence(vm->root.bo->tbo.base.resv, + dma_resv_add_fence(amdkcl_ttm_resvp(&vm->root.bo->tbo), &vm->process_info->eviction_fence->base, DMA_RESV_USAGE_BOOKKEEP); amdgpu_bo_unreserve(vm->root.bo); @@ -3453,7 +3453,7 @@ int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence __rcu * if (mem->bo->tbo.pin_count) continue; - dma_resv_add_fence(mem->bo->tbo.base.resv, + dma_resv_add_fence(amdkcl_ttm_resvp(&mem->bo->tbo), &process_info->eviction_fence->base, DMA_RESV_USAGE_BOOKKEEP); } @@ -3462,7 +3462,7 @@ int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence __rcu * vm_list_node) { struct amdgpu_bo *bo = peer_vm->root.bo; - dma_resv_add_fence(bo->tbo.base.resv, + dma_resv_add_fence(amdkcl_ttm_resvp(&bo->tbo), &process_info->eviction_fence->base, DMA_RESV_USAGE_BOOKKEEP); } @@ -3517,7 +3517,7 @@ int amdgpu_amdkfd_add_gws_to_process(void *info, void *gws, struct kgd_mem **mem ret = dma_resv_reserve_fences(amdkcl_ttm_resvp(&gws_bo->tbo), 1); if (ret) goto reserve_shared_fail; - dma_resv_add_fence(gws_bo->tbo.base.resv, + dma_resv_add_fence(amdkcl_ttm_resvp(&gws_bo->tbo), &process_info->eviction_fence->base, DMA_RESV_USAGE_BOOKKEEP); amdgpu_bo_unreserve(gws_bo); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c index 9b748d7058b5c..abb88f858cf29 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c @@ -144,7 +144,7 @@ static int amdgpu_vm_sdma_commit(struct amdgpu_vm_update_params *p, swap(p->vm->last_unlocked, tmp); dma_fence_put(tmp); } else { - dma_resv_add_fence(p->vm->root.bo->tbo.base.resv, f, + dma_resv_add_fence(amdkcl_ttm_resvp(&p->vm->root.bo->tbo), f, DMA_RESV_USAGE_BOOKKEEP); } From fdb213088c23746948094a0c4f92f1fcbdeac4e7 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 20 Sep 2022 15:17:48 +0800 Subject: [PATCH 0779/1868] drm/amdkcl: regard DMA_RESV_USAGE_BOOKKEEP usage as read fence for legacy os For legacy os, the new usage DMA_RESV_USAGE_BOOKKEEP is regarded same as DMA_RESV_USAGE_READ Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c b/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c index e6c4b9ef220d1..1477c6349dad7 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c @@ -314,7 +314,7 @@ void dma_resv_replace_fences(struct dma_resv *obj, uint64_t context, unsigned int i; /* Only readers supported for now */ - WARN_ON(usage != DMA_RESV_USAGE_READ); + WARN_ON(usage != DMA_RESV_USAGE_READ && usage != DMA_RESV_USAGE_BOOKKEEP); dma_resv_assert_held(obj); From 4d237fb4907289bce36341f3504e3419cdb41b10 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 31 Aug 2022 17:25:12 +0800 Subject: [PATCH 0780/1868] drm/amdkcl: Update the config.h Update the version related macro in config.h Signed-off-by: Ma Jun Reviewed-by: Flora Cui Change-Id: I580539022bb383bcc54bf12a853cf690ec190318 --- drivers/gpu/drm/amd/dkms/config/config.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index b0162ceea2d3e..92dfec9ea8711 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1319,7 +1319,7 @@ #define PACKAGE_NAME "amdgpu-dkms" /* Define to the full name and version of this package. */ -#define PACKAGE_STRING "amdgpu-dkms 5.13.5" +#define PACKAGE_STRING "amdgpu-dkms 5.19.0" /* Define to the one symbol short name of this package. */ #define PACKAGE_TARNAME "amdgpu-dkms" @@ -1328,7 +1328,7 @@ #define PACKAGE_URL "" /* Define to the version of this package. */ -#define PACKAGE_VERSION "5.13.5" +#define PACKAGE_VERSION "5.19.0" #include "config-amd-chips.h" From 8a66e3b1449af6b6e5d0afc9cce0ec52de85d805 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 15 Sep 2022 14:20:19 +0800 Subject: [PATCH 0781/1868] drm/amdkcl: test whether drm_gem_object->resv is available It's caused by e406606fb782b811b6bfb6f51b5fc9e0c8f5d1bf "drm/amdgpu: SDMA update use unlocked iterator" Signed-off-by: Asher Song Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c index abb88f858cf29..40f464a46e12f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c @@ -245,7 +245,7 @@ static int amdgpu_vm_sdma_update(struct amdgpu_vm_update_params *p, int r; /* Wait for PD/PT moves to be completed */ - dma_resv_iter_begin(&cursor, bo->tbo.base.resv, DMA_RESV_USAGE_KERNEL); + dma_resv_iter_begin(&cursor, amdkcl_ttm_resvp(&bo->tbo), DMA_RESV_USAGE_KERNEL); dma_resv_for_each_fence_unlocked(&cursor, fence) { dma_fence_get(fence); r = drm_sched_job_add_dependency(&p->job->base, fence); From 4f2ceeb0c21499bec82b03f9bc940a81c1a598c6 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 7 Sep 2022 14:16:27 +0800 Subject: [PATCH 0782/1868] drm/amdkcl: Optimize cancel_work() test Search the __cancel_work() instead of cancel_work() to optimize the cancel_work() test. Suggested-by: Flora Cui Signed-off-by: Ma Jun Reviewed-by: Guchun Chen Reviewed-by: Flora Cui Change-Id: I595e947b5c98bc601b7e173fbd2ceed4ccd9f7f8 --- drivers/gpu/drm/amd/amdkcl/kcl_workqueue.c | 13 +++++++++---- include/kcl/backport/kcl_workqueue_backport.h | 4 ++-- 2 files changed, 11 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_workqueue.c b/drivers/gpu/drm/amd/amdkcl/kcl_workqueue.c index 461066e047ac3..7c9b248df0e27 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_workqueue.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_workqueue.c @@ -22,20 +22,25 @@ #include #ifndef HAVE_CANCEL_WORK -bool (*_kcl_cancel_work)(struct work_struct *work); -EXPORT_SYMBOL(_kcl_cancel_work); +static bool (*_kcl_cancel_work)(struct work_struct *work, bool is_dwork); -bool _kcl_cancel_work_stub(struct work_struct *work) +bool _kcl_cancel_work_stub(struct work_struct *work, bool is_dwork) { pr_warn_once("cancel_work function is not supported\n"); return false; } + +bool kcl_cancel_work(struct work_struct *work) +{ + return _kcl_cancel_work(work, false); +} +EXPORT_SYMBOL(kcl_cancel_work); #endif void amdkcl_workqueue_init(void) { #ifndef HAVE_CANCEL_WORK - _kcl_cancel_work = amdkcl_fp_setup("cancel_work", _kcl_cancel_work_stub); + _kcl_cancel_work = amdkcl_fp_setup("__cancel_work", _kcl_cancel_work_stub); #endif /* HAVE_CANCEL_WORK */ } diff --git a/include/kcl/backport/kcl_workqueue_backport.h b/include/kcl/backport/kcl_workqueue_backport.h index 3e6adabc0f08c..ac9ffbddd468c 100644 --- a/include/kcl/backport/kcl_workqueue_backport.h +++ b/include/kcl/backport/kcl_workqueue_backport.h @@ -6,8 +6,8 @@ #include #ifndef HAVE_CANCEL_WORK -extern bool (*_kcl_cancel_work)(struct work_struct *work); -#define cancel_work _kcl_cancel_work +extern bool kcl_cancel_work(struct work_struct *work); +#define cancel_work kcl_cancel_work #endif #endif /* KCL_LINUX_WORKQUEUE_BACKPORT_H */ From b74f5046bdc933c8a33552d09b1a1f44fa0d03f5 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 7 Sep 2022 20:57:09 +0800 Subject: [PATCH 0783/1868] drm/amdkcl: Modify the kcl drm buddy functions name Signed-off-by: Ma Jun Change-Id: Ia336a4c20279382d5f931edae10114c57fa756e3 --- drivers/gpu/drm/amd/amdkcl/kcl_drm_buddy.c | 36 +++++++++++----------- include/kcl/kcl_drm_buddy.h | 27 ++++++++++------ 2 files changed, 36 insertions(+), 27 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_buddy.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_buddy.c index b8e89facbadd0..0d18f0d43b68d 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_buddy.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_buddy.c @@ -75,7 +75,7 @@ static void mark_split(struct drm_buddy_block *block) * Returns: * 0 on success, error code on failure. */ -int drm_buddy_init(struct drm_buddy *mm, u64 size, u64 chunk_size) +int kcl_drm_buddy_init(struct drm_buddy *mm, u64 size, u64 chunk_size) { unsigned int i; u64 offset; @@ -156,7 +156,7 @@ int drm_buddy_init(struct drm_buddy *mm, u64 size, u64 chunk_size) kfree(mm->free_list); return -ENOMEM; } -EXPORT_SYMBOL(drm_buddy_init); +EXPORT_SYMBOL(kcl_drm_buddy_init); /** * drm_buddy_fini - tear down the memory manager @@ -165,7 +165,7 @@ EXPORT_SYMBOL(drm_buddy_init); * * Cleanup memory manager resources and the freelist */ -void drm_buddy_fini(struct drm_buddy *mm) +void kcl_drm_buddy_fini(struct drm_buddy *mm) { int i; @@ -179,7 +179,7 @@ void drm_buddy_fini(struct drm_buddy *mm) kfree(mm->roots); kfree(mm->free_list); } -EXPORT_SYMBOL(drm_buddy_fini); +EXPORT_SYMBOL(kcl_drm_buddy_fini); static int split_block(struct drm_buddy *mm, struct drm_buddy_block *block) @@ -235,11 +235,11 @@ __get_buddy(struct drm_buddy_block *block) * any concurrent allocate and free operations. */ struct drm_buddy_block * -drm_get_buddy(struct drm_buddy_block *block) +kcl_drm_get_buddy(struct drm_buddy_block *block) { return __get_buddy(block); } -EXPORT_SYMBOL(drm_get_buddy); +EXPORT_SYMBOL(kcl_drm_get_buddy); static void __drm_buddy_free(struct drm_buddy *mm, struct drm_buddy_block *block) @@ -271,14 +271,14 @@ static void __drm_buddy_free(struct drm_buddy *mm, * @mm: DRM buddy manager * @block: block to be freed */ -void drm_buddy_free_block(struct drm_buddy *mm, +void kcl_drm_buddy_free_block(struct drm_buddy *mm, struct drm_buddy_block *block) { BUG_ON(!drm_buddy_block_is_allocated(block)); mm->avail += drm_buddy_block_size(mm, block); __drm_buddy_free(mm, block); } -EXPORT_SYMBOL(drm_buddy_free_block); +EXPORT_SYMBOL(kcl_drm_buddy_free_block); /** * drm_buddy_free_list - free blocks @@ -286,7 +286,7 @@ EXPORT_SYMBOL(drm_buddy_free_block); * @mm: DRM buddy manager * @objects: input list head to free blocks */ -void drm_buddy_free_list(struct drm_buddy *mm, struct list_head *objects) +void kcl_drm_buddy_free_list(struct drm_buddy *mm, struct list_head *objects) { struct drm_buddy_block *block, *on; @@ -296,7 +296,7 @@ void drm_buddy_free_list(struct drm_buddy *mm, struct list_head *objects) } INIT_LIST_HEAD(objects); } -EXPORT_SYMBOL(drm_buddy_free_list); +EXPORT_SYMBOL(kcl_drm_buddy_free_list); static inline bool overlaps(u64 s1, u64 e1, u64 s2, u64 e2) { @@ -559,7 +559,7 @@ static int __drm_buddy_alloc_range(struct drm_buddy *mm, * Returns: * 0 on success, error code on failure. */ -int drm_buddy_block_trim(struct drm_buddy *mm, +int kcl_drm_buddy_block_trim(struct drm_buddy *mm, u64 new_size, struct list_head *blocks) { @@ -608,7 +608,7 @@ int drm_buddy_block_trim(struct drm_buddy *mm, block->parent = parent; return err; } -EXPORT_SYMBOL(drm_buddy_block_trim); +EXPORT_SYMBOL(kcl_drm_buddy_block_trim); /** * drm_buddy_alloc_blocks - allocate power-of-two blocks @@ -630,7 +630,7 @@ EXPORT_SYMBOL(drm_buddy_block_trim); * Returns: * 0 on success, error code on failure. */ -int drm_buddy_alloc_blocks(struct drm_buddy *mm, +int kcl_drm_buddy_alloc_blocks(struct drm_buddy *mm, u64 start, u64 end, u64 size, u64 min_page_size, struct list_head *blocks, @@ -711,7 +711,7 @@ int drm_buddy_alloc_blocks(struct drm_buddy *mm, drm_buddy_free_list(mm, &allocated); return err; } -EXPORT_SYMBOL(drm_buddy_alloc_blocks); +EXPORT_SYMBOL(kcl_drm_buddy_alloc_blocks); /** * drm_buddy_block_print - print block information @@ -720,7 +720,7 @@ EXPORT_SYMBOL(drm_buddy_alloc_blocks); * @block: DRM buddy block * @p: DRM printer to use */ -void drm_buddy_block_print(struct drm_buddy *mm, +void kcl_drm_buddy_block_print(struct drm_buddy *mm, struct drm_buddy_block *block, struct drm_printer *p) { @@ -729,7 +729,7 @@ void drm_buddy_block_print(struct drm_buddy *mm, drm_printf(p, "%#018llx-%#018llx: %llu\n", start, start + size, size); } -EXPORT_SYMBOL(drm_buddy_block_print); +EXPORT_SYMBOL(kcl_drm_buddy_block_print); /** * drm_buddy_print - print allocator state @@ -737,7 +737,7 @@ EXPORT_SYMBOL(drm_buddy_block_print); * @mm: DRM buddy manager * @p: DRM printer to use */ -void drm_buddy_print(struct drm_buddy *mm, struct drm_printer *p) +void kcl_drm_buddy_print(struct drm_buddy *mm, struct drm_printer *p) { int order; @@ -764,7 +764,7 @@ void drm_buddy_print(struct drm_buddy *mm, struct drm_printer *p) drm_printf(p, ", pages: %llu\n", count); } } -EXPORT_SYMBOL(drm_buddy_print); +EXPORT_SYMBOL(kcl_drm_buddy_print); void amdkcl_drm_buddy_module_exit(void) { diff --git a/include/kcl/kcl_drm_buddy.h b/include/kcl/kcl_drm_buddy.h index 5f13318751887..b87f9743342ea 100644 --- a/include/kcl/kcl_drm_buddy.h +++ b/include/kcl/kcl_drm_buddy.h @@ -131,31 +131,40 @@ drm_buddy_block_size(struct drm_buddy *mm, return mm->chunk_size << drm_buddy_block_order(block); } -int drm_buddy_init(struct drm_buddy *mm, u64 size, u64 chunk_size); +int kcl_drm_buddy_init(struct drm_buddy *mm, u64 size, u64 chunk_size); -void drm_buddy_fini(struct drm_buddy *mm); +void kcl_drm_buddy_fini(struct drm_buddy *mm); struct drm_buddy_block * -drm_get_buddy(struct drm_buddy_block *block); +kcl_drm_get_buddy(struct drm_buddy_block *block); -int drm_buddy_alloc_blocks(struct drm_buddy *mm, +int kcl_drm_buddy_alloc_blocks(struct drm_buddy *mm, u64 start, u64 end, u64 size, u64 min_page_size, struct list_head *blocks, unsigned long flags); -int drm_buddy_block_trim(struct drm_buddy *mm, +int kcl_drm_buddy_block_trim(struct drm_buddy *mm, u64 new_size, struct list_head *blocks); -void drm_buddy_free_block(struct drm_buddy *mm, struct drm_buddy_block *block); +void kcl_drm_buddy_free_block(struct drm_buddy *mm, struct drm_buddy_block *block); -void drm_buddy_free_list(struct drm_buddy *mm, struct list_head *objects); +void kcl_drm_buddy_free_list(struct drm_buddy *mm, struct list_head *objects); -void drm_buddy_print(struct drm_buddy *mm, struct drm_printer *p); -void drm_buddy_block_print(struct drm_buddy *mm, +void kcl_drm_buddy_print(struct drm_buddy *mm, struct drm_printer *p); +void kcl_drm_buddy_block_print(struct drm_buddy *mm, struct drm_buddy_block *block, struct drm_printer *p); +#define drm_buddy_print kcl_drm_buddy_print +#define drm_buddy_block_print kcl_drm_buddy_block_print +#define drm_buddy_alloc_blocks kcl_drm_buddy_alloc_blocks +#define drm_buddy_block_trim kcl_drm_buddy_block_trim +#define drm_buddy_free_list kcl_drm_buddy_free_list +#define drm_buddy_free_block kcl_drm_buddy_free_block +#define drm_get_buddy kcl_drm_get_buddy +#define drm_buddy_fini kcl_drm_buddy_fini +#define drm_buddy_init kcl_drm_buddy_init #endif /* HAVE_DRM_DRM_BUDDY_H */ #endif /* __KCL_KCL_DRM_BUDDY_H__ */ From 92e91b9bba837cdd24ba905493d314a447c47c31 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Fri, 16 Sep 2022 11:05:12 +0800 Subject: [PATCH 0784/1868] drm/amdkcl: fix the compile error caused by drm_printf() Fix the compile error caused by drm_printf() Signed-off-by: Ma Jun Reviewed-by: Flora Cui Change-Id: If3417d24b8a808de1d4b3ac83d0cd7c92d18e1b1 --- include/kcl/kcl_drm_buddy.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/kcl/kcl_drm_buddy.h b/include/kcl/kcl_drm_buddy.h index b87f9743342ea..4db95edb25369 100644 --- a/include/kcl/kcl_drm_buddy.h +++ b/include/kcl/kcl_drm_buddy.h @@ -13,6 +13,7 @@ #include #include #include +#include #define range_overflows(start, size, max) ({ \ typeof(start) start__ = (start); \ From 7a0bef64db41c63742d5cdabafb27e1bf082115d Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Fri, 16 Sep 2022 22:11:46 +0800 Subject: [PATCH 0785/1868] drm/amdkcl: Check if drm_crtc_funcs->late_register() is defined Check if drm_crtc_funcs->late_register() is defined Signed-off-by: Ma Jun Reviewed-by: Flora Cui Change-Id: Ie53ef60820cefd381976ac3b9922fda8660100f3 --- .../amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 4 ++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 | 19 +++++++++++++++++++ 3 files changed, 26 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c index ff25b4b928ee6..22d05c450b4d4 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c @@ -466,6 +466,7 @@ static void amdgpu_dm_crtc_reset_state(struct drm_crtc *crtc) } #ifdef CONFIG_DEBUG_FS +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_LATE_REGISTER static int amdgpu_dm_crtc_late_register(struct drm_crtc *crtc) { crtc_debugfs_init(crtc); @@ -473,6 +474,7 @@ static int amdgpu_dm_crtc_late_register(struct drm_crtc *crtc) return 0; } #endif +#endif #ifdef AMD_PRIVATE_COLOR /** @@ -563,8 +565,10 @@ static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = { .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, #endif #if defined(CONFIG_DEBUG_FS) +#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_LATE_REGISTER .late_register = amdgpu_dm_crtc_late_register, #endif +#endif #ifdef AMD_PRIVATE_COLOR .atomic_set_property = amdgpu_dm_atomic_crtc_set_property, .atomic_get_property = amdgpu_dm_atomic_crtc_get_property, diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 92dfec9ea8711..d0479ad29347d 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1146,6 +1146,9 @@ /* drm_crtc_funcs->set_config() wants ctx parameter */ #define HAVE_STRUCT_DRM_CRTC_FUNCS_SET_CONFIG_CTX 1 +/* drm_crtc_funcs->late_register() is available */ +#define HAVE_STRUCT_DRM_CRTC_FUNCS_LATE_REGISTER 1 + /* crtc->funcs->set_crc_source() is available */ #define HAVE_STRUCT_DRM_CRTC_FUNCS_SET_CRC_SOURCE 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 index e92c34e468d65..41d85b15ac85f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 @@ -171,6 +171,24 @@ AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL], [ ]) ]) +dnl # +dnl # commit v4.8-rc1~62-79190ea26 +dnl # drm: Add callbacks for late registering +dnl # +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_LATE_REGISTER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_crtc_funcs *crtc_funcs = NULL; + crtc_funcs->late_register(NULL); + ], [ + AC_DEFINE(HAVE_STRUCT_DRM_CRTC_FUNCS_LATE_REGISTER, 1, [ + drm_crtc_funcs->late_register() is available]) + ]) + ]) +]) + AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS], [ AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_ENABLE_VBLANK @@ -179,4 +197,5 @@ AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS], [ AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL + AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_LATE_REGISTER ]) From 34bf88e6d75cc774816fba07673a614de78be982 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Fri, 16 Sep 2022 22:44:57 +0800 Subject: [PATCH 0786/1868] drm/amdkcl: Check if drm_crtc->debugfs_entry is defined Check if drm_crtc->debugfs_entry is defined Signed-off-by: Ma Jun Reviewed-by: Flora Cui Change-Id: I407e6fdc0bf040dfb619f7718b0d077179fbe510 --- .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 2 ++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../gpu/drm/amd/dkms/m4/struct_drm_crtc.m4 | 21 +++++++++++++++++++ 4 files changed, 27 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index e2809f3e87b6e..2880eea91a5ab 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -3723,10 +3723,12 @@ void crtc_debugfs_init(struct drm_crtc *crtc) &crc_win_update_fops); dput(dir); #endif +#ifdef HAVE_STRUCT_DRM_CRTC_DEBUGFS_ENTRY debugfs_create_file("amdgpu_current_bpc", 0644, crtc->debugfs_entry, crtc, &amdgpu_current_bpc_fops); debugfs_create_file("amdgpu_current_colorspace", 0644, crtc->debugfs_entry, crtc, &amdgpu_current_colorspace_fops); +#endif } /* diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index d0479ad29347d..ff03bc13a416b 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1161,6 +1161,9 @@ /* struct drm_crtc_state has flag for flip */ #define HAVE_STRUCT_DRM_CRTC_STATE_FLIP_FLAG 1 +/* drm_crtc->debugfs_entry is available */ +#define HAVE_STRUCT_DRM_CRTC_DEBUGFS_ENTRY 1 + /* struct drm_crtc_state->pageflip_flags is available */ /* #undef HAVE_STRUCT_DRM_CRTC_STATE_PAGEFLIP_FLAGS */ diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index cc3f0f968a8e3..0db4444af38bc 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -215,6 +215,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DSC_COMPUTE_RC_PARAMETERS AC_AMDGPU_DRM_GEM_PLANE_HELPER_PREPARE_FB AC_AMDGPU_BITMAP_TO_ARR32 + AC_AMDGPU_STRUCT_DRM_CRTC AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc.m4 new file mode 100644 index 0000000000000..5c02ff4595856 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc.m4 @@ -0,0 +1,21 @@ +dnl # +dnl # commit v4.10-rc1~154-9edbf1fa6 +dnl # drm: Add API for capturing frame CRCs +dnl # +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_DEBUGFS_ENTRY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_crtc *test = NULL; + test->debugfs_entry = NULL; + ], [ + AC_DEFINE(HAVE_STRUCT_DRM_CRTC_DEBUGFS_ENTRY, 1, [ + drm_crtc->debugfs_entry is available]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC], [ + AC_AMDGPU_STRUCT_DRM_CRTC_DEBUGFS_ENTRY +]) From 4150557e99ca8256f38b8cd057c62257d8d8f25f Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Tue, 30 Aug 2022 16:30:56 +0800 Subject: [PATCH 0787/1868] drm/amdkcl: Wrap the code with kcl macro Wrap dm_plane_atomic_async_update() with kcl macro to fix the build error Signed-off-by: Ma Jun Change-Id: Idb856ed860b49e85f402c4e36221524db434725a --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index c8b9bc965ec9e..1770173e13df1 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -1508,6 +1508,7 @@ void amdgpu_dm_plane_handle_cursor_update(struct drm_plane *plane, } } +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_ASYNC_CHECK static void amdgpu_dm_plane_atomic_async_update(struct drm_plane *plane, #ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS struct drm_atomic_state *state) @@ -1540,7 +1541,7 @@ static void amdgpu_dm_plane_atomic_async_update(struct drm_plane *plane, amdgpu_dm_plane_handle_cursor_update(plane, old_state); } - +#endif static const struct drm_plane_helper_funcs dm_plane_helper_funcs = { .prepare_fb = amdgpu_dm_plane_helper_prepare_fb, .cleanup_fb = amdgpu_dm_plane_helper_cleanup_fb, From c0cbb00f110eb8ca7dab4d277a4d6394a53e4d9f Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 22 Sep 2022 14:58:47 +0800 Subject: [PATCH 0788/1868] drm/amdkcl: Remove redundant whitespace Signed-off-by: Ma Jun Reviewed-by: Flora Cui Change-Id: I107ee795d50908d08587d25a215012fd6403049f --- drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c index 60bf213b8c85d..65bf30a84fdd3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c @@ -279,7 +279,7 @@ static int amdgpufb_create(struct drm_fb_helper *helper, #else DRM_INFO("fb depth is %d\n", fb->format->depth); #endif - DRM_INFO(" pitch is %d\n", fb->pitches[0]); + DRM_INFO("pitch is %d\n", fb->pitches[0]); vga_switcheroo_client_fb_set(adev->pdev, info); return 0; From 526033914305b50cb5c00818c0eb2dee3a650622 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 22 Sep 2022 15:48:21 +0800 Subject: [PATCH 0789/1868] drm/amdgpu: [hybrid] revise semaphore object support Due to struct amdgpu_cs_parser change, revise semaphore object support. It's caused by "e89b45235fe6edd94595a3c437beaef0dbf762ca" drm/amdgpu: add gang submit frontend v6 Signed-off-by: Asher Song Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index fc163d903563c..1cde3b1d2e209 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -648,7 +648,12 @@ static int amdgpu_cs_pass2(struct amdgpu_cs_parser *p) } } - return amdgpu_sem_add_cs(p->ctx, p->entity, &p->job->sync); + for (i = 0; i < p->gang_size; ++i) { + r = amdgpu_sem_add_cs(p->ctx, p->entities[i], &p->jobs[i]->sync); + if (r) + return r; + } + return 0; } /* Convert microseconds to bytes. */ From 704ab5e985d66112dc6e79bc1e228c80df961108 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 26 Sep 2022 15:44:12 +0800 Subject: [PATCH 0790/1868] drm/amdkcl: wrap code under macro CONFIG_DRM_AMD_DC_DSC_SUPPORT It's caused by ac2e8b34b24ac3966df28d289fc2c03825bc8f1f drm/amd/display: Fix various dynamic ODM transitions on DCN32 Signed-off-by: Asher Song Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c | 2 ++ drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h | 2 ++ drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c | 2 ++ 3 files changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c index 4199f8b0682e1..b488885b277ba 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c @@ -1485,6 +1485,7 @@ bool dcn32_dsc_pg_status( return pwr_status == 0; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void dcn32_update_dsc_pg(struct dc *dc, struct dc_state *context, bool safe_to_disable) @@ -1507,6 +1508,7 @@ void dcn32_update_dsc_pg(struct dc *dc, } } } +#endif void dcn32_disable_phantom_streams(struct dc *dc, struct dc_state *context) { diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h index cac4a08b92a4d..5b4af3e0acf2f 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h @@ -107,9 +107,11 @@ bool dcn32_dsc_pg_status( struct dce_hwseq *hws, unsigned int dsc_inst); +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void dcn32_update_dsc_pg(struct dc *dc, struct dc_state *context, bool safe_to_disable); +#endif void dcn32_enable_phantom_streams(struct dc *dc, struct dc_state *context); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c index 3422b564ae984..6b0b9b9207cb6 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c @@ -115,7 +115,9 @@ static const struct hw_sequencer_funcs dcn32_funcs = { .update_visual_confirm_color = dcn10_update_visual_confirm_color, .subvp_pipe_control_lock_fast = dcn32_subvp_pipe_control_lock_fast, .update_phantom_vp_position = dcn32_update_phantom_vp_position, +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .update_dsc_pg = dcn32_update_dsc_pg, +#endif .apply_update_flags_for_phantom = dcn32_apply_update_flags_for_phantom, .blank_phantom = dcn32_blank_phantom, .is_pipe_topology_transition_seamless = dcn32_is_pipe_topology_transition_seamless, From 8e225f7fbe9eb344138481f31a273777990b8854 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 27 Sep 2022 13:43:38 +0800 Subject: [PATCH 0791/1868] drm/amdkcl: Test whether linux/dma-map-ops.h exist Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 | 6 ++++++ include/kcl/header/linux/dma-map-ops.h | 11 +++++++++++ 3 files changed, 20 insertions(+) create mode 100644 include/kcl/header/linux/dma-map-ops.h diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index ff03bc13a416b..28f62454fb160 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -900,6 +900,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_DMA_FENCE_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_DMA_MAP_OPS_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_LINUX_DMA_RESV_H 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 index b6024239ef2f5..0b21b17421ef2 100644 --- a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 @@ -114,4 +114,10 @@ AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ dnl # spin loop primitives for busy waiting dnl # AC_KERNEL_CHECK_HEADERS([linux/processor.h]) + + dnl # + dnl # v5.9-rc6-311-g0a0f0d8be76d + dnl # dma-mapping: split + dnl # + AC_KERNEL_CHECK_HEADERS([linux/dma-map-ops.h]) ]) diff --git a/include/kcl/header/linux/dma-map-ops.h b/include/kcl/header/linux/dma-map-ops.h new file mode 100644 index 0000000000000..0bda5e05b7eb1 --- /dev/null +++ b/include/kcl/header/linux/dma-map-ops.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER__LINUX_DMA_MAP_OPS_H_H_ +#define _KCL_HEADER__LINUX_DMA_MAP_OPS_H_H_ + +#if defined(HAVE_LINUX_DMA_MAP_OPS_H) +#include_next +#else +#include +#endif + +#endif From 9af42a49deb49d09a382240424f34d29a5749582 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 22 Sep 2022 14:24:55 +0800 Subject: [PATCH 0792/1868] drm/amdkcl: avoid DMA mapping of DOORBELL/MMIO bos for legacy os map_resource ops not provided On AMD platform for legacy os(e.g., ubuntu with kernel version <= 5.4), PCI device cannot access a peer device's BAR resource when a hardware IOMMU is enabled as the map_resource DMA op is not provided. This is fixed by commit "be62dbf554c5 iommu/amd: Convert AMD iommu driver to the dma-iommu api". This patch avoid DMA mapping of DOORBELL/MMIO bos for legacy os that dma map_resource ops is not provided. v2: remove kcl kernel version check v3: include linux/dma-map-ops.h Signed-off-by: Leslie Shi Reviewed-by: Felix Kuehling Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 15 +++++++++++---- include/kcl/kcl_dma_mapping.h | 6 ++++++ 2 files changed, 17 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index b1f07e4d20d99..ed584e64674dd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -978,10 +978,17 @@ static int kfd_mem_attach(struct amdgpu_device *adev, struct kgd_mem *mem, WARN_ONCE(!(mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL || mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP), "Handing invalid SG BO in ATTACH request"); - attachment[i]->type = KFD_MEM_ATT_SG; - ret = create_dmamap_sg_bo(adev, mem, &bo[i]); - if (ret) - goto unwind; + + if (kcl_has_dma_map_resource_ops(adev->dev)) { + attachment[i]->type = KFD_MEM_ATT_SG; + ret = create_dmamap_sg_bo(adev, mem, &bo[i]); + if (ret) + goto unwind; + } else { + attachment[i]->type = KFD_MEM_ATT_SHARED; + bo[i] = mem->bo; + drm_gem_object_get(&bo[i]->tbo.base); + } #ifdef AMDKCL_AMDGPU_DMABUF_OPS /* Enable acces to GTT BOs of peer devices */ } else if (mem->domain == AMDGPU_GEM_DOMAIN_GTT) { diff --git a/include/kcl/kcl_dma_mapping.h b/include/kcl/kcl_dma_mapping.h index 81d15205ec77e..c433caeca3d98 100644 --- a/include/kcl/kcl_dma_mapping.h +++ b/include/kcl/kcl_dma_mapping.h @@ -3,6 +3,7 @@ #define AMDKCL_DMA_MAPPING_H #include +#include /* * commit v4.8-11962-ga9a62c938441 @@ -127,6 +128,11 @@ static inline void dma_unmap_sgtable(struct device *dev, struct sg_table *sgt, } #endif +static inline bool kcl_has_dma_map_resource_ops(struct device *dev) +{ + const struct dma_map_ops *ops = get_dma_ops(dev); + return ops == NULL || ops->map_resource != NULL; +} /* * v5.8-rc3-2-g68d237056e00 ("scatterlist: protect parameters of the sg_table related macros") * v5.7-rc5-33-g709d6d73c756 ("scatterlist: add generic wrappers for iterating over sgtable objects") From 6cf239ffedbb506f33468162bc326ef8494a022c Mon Sep 17 00:00:00 2001 From: Ramesh Errabolu Date: Fri, 30 Sep 2022 17:32:20 -0500 Subject: [PATCH 0793/1868] drm/amdgpu: Query P2PDMA distance only if CONFIG_HSA_AMD_P2P is defined CONFIG_HSA_AMD_P2P indicates the requirements that are needed for P2P DMA Mappings. It is important to note that enabling CONFIG_HSA_AMD_P2P is a necessary but insufficient condition. It is possible to encounter runtime errors - e.g. CPU's do not support Inter-CPU transport of PCIe transaction packets i.e. P2PDMA distance API may return error Signed-off-by: Ramesh Errabolu Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 02d9bc6b07ba6..057b605053531 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -6180,6 +6180,12 @@ static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev) * Return true if @peer_adev can access (DMA) @adev through the PCIe * BAR, i.e. @adev is "large BAR" and the BAR matches the DMA mask of * @peer_adev. + * + * @note: CONFIG_HSA_AMD_P2P indicates support for P2P DMA mappings. Query + * P2PDMA distance only if the kernel has all the prerequisites for P2P DMA + * support. Otherwise fall back to the less reliable legacy P2P support to + * avoid regressions. + * */ bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, struct amdgpu_device *peer_adev) @@ -6189,7 +6195,7 @@ bool amdgpu_device_is_peer_accessible(struct amdgpu_device *adev, ~*peer_adev->dev->dma_mask : ~((1ULL << 32) - 1); resource_size_t aper_limit = adev->gmc.aper_base + adev->gmc.aper_size - 1; -#ifdef CONFIG_PCI_P2PDMA +#ifdef CONFIG_HSA_AMD_P2P p2p_access = !adev->gmc.xgmi.connected_to_cpu && !(pci_p2pdma_distance(adev->pdev, peer_adev->dev, false) < 0); From ea8ceaae97f4de7bc768cc9164669dff93ff8101 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 11 Oct 2022 10:24:53 +0800 Subject: [PATCH 0794/1868] drm/amdkcl: wrap code under macro CONFIG_DRM_AMD_DC_DSC_SUPPORT and HAVE_DRM_DP_MST_ATOMIC_CHECK It's caused by a7bfbdb0578e89ae380eeffdb2949bd0162e1cb1 "drm/amd/display: Validate DSC After Enable All New CRTCs" 64fbeb725d23878bea621dfddbd3c64a4b0868fe "drm/amd/display: Add a helper to map ODM/MPC/Multi-Plane resources" Signed-off-by: Asher Song Reviewed-by: Flora Cui Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index a3c3a0992cfca..629e586d7585d 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -11770,12 +11770,14 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, } } +#if defined(HAVE_DRM_DP_MST_ATOMIC_CHECK) #if defined(CONFIG_DRM_AMD_DC_FP) if (dc_resource_is_dsc_encoding_supported(dc)) { ret = pre_validate_dsc(state, &dm_state, vars); if (ret != 0) goto fail; } +#endif #endif /* Run this here since we want to validate the streams we created */ From 764fc021743a797ff361b2bc294248c162205eeb Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 12 Oct 2022 16:29:57 +0800 Subject: [PATCH 0795/1868] drm/amdgpu: [hybrid] fix dgma Signed-off-by: Flora Cui Tested-by: Andy Dong Reviewed-by: Leslie Shi Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 6 + drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 176 +----------------------- 2 files changed, 10 insertions(+), 172 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index d56eb39de6f43..8e8ef5a0e541e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -1089,6 +1089,12 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) memset(&cap, 0, sizeof(cap)); if (amdgpu_no_evict) cap.flag |= AMDGPU_CAPABILITY_PIN_MEM_FLAG; + + if (amdgpu_direct_gma_size) { + cap.flag |= AMDGPU_CAPABILITY_DIRECT_GMA_FLAG; + cap.direct_gma_size = amdgpu_direct_gma_size; + } + return copy_to_user(out, &cap, min((size_t)size, sizeof(cap))) ? -EFAULT : 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 45714eafe12b9..fb26f37c4c36c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -68,11 +68,6 @@ MODULE_IMPORT_NS(DMA_BUF); #define AMDGPU_TTM_VRAM_MAX_DW_READ ((size_t)128) -struct amdgpu_dgma_node { - struct ttm_buffer_object *tbo; - struct ttm_range_mgr_node base; -}; - static int amdgpu_ttm_backend_bind(struct ttm_device *bdev, struct ttm_tt *ttm, struct ttm_resource *bo_mem); @@ -665,11 +660,9 @@ static int amdgpu_ttm_io_mem_reserve(struct ttm_device *bdev, break; case AMDGPU_PL_DGMA_IMPORT: { - struct amdgpu_dgma_node *node; struct amdgpu_bo *abo; - node = container_of(mem, struct amdgpu_dgma_node, base.base); - abo = ttm_to_amdgpu_bo(node->tbo); + abo = ttm_to_amdgpu_bo(mem->bo); mem->bus.addr = abo->dgma_addr; mem->bus.offset = abo->dgma_import_base; mem->bus.is_iomem = true; @@ -2106,168 +2099,6 @@ static int amdgpu_ttm_reserve_tmr(struct amdgpu_device *adev) return 0; } -static inline struct amdgpu_dgma_import_mgr *to_dgma_import_mgr(struct ttm_resource_manager *man) -{ - return container_of(man, struct amdgpu_dgma_import_mgr, manager); -} - -static const struct ttm_resource_manager_func amdgpu_dgma_import_mgr_func; -/** - * amdgpu_dgma_import_mgr_init - init DGMA_import manager and DRM MM - * - * @adev: amdgpu_device pointer - * @dgma_size: maximum size of DGMA - * - * Allocate and initialize the DGMA manager. - */ -static int amdgpu_dgma_import_mgr_init(struct amdgpu_device *adev, uint64_t p_size) -{ - struct amdgpu_dgma_import_mgr *mgr = &adev->mman.dgma_import_mgr; - struct ttm_resource_manager *man = &mgr->manager; - - man->func = &amdgpu_dgma_import_mgr_func; - - ttm_resource_manager_init(man, &adev->mman.bdev, p_size); - drm_mm_init(&mgr->mm, 0, p_size); - spin_lock_init(&mgr->lock); - atomic64_set(&mgr->available, p_size); - - BUG_ON(AMDGPU_PL_DGMA_IMPORT >= TTM_NUM_MEM_TYPES); - ttm_set_driver_manager(&adev->mman.bdev, AMDGPU_PL_DGMA_IMPORT, man); - ttm_resource_manager_set_used(man, true); - return 0; -} - -/** - * amdgpu_dgma_import_mgr_fini - free and destroy DGMA import manager - * - * @adev: amdgpu_device pointer - * - * Destroy and free the DGMA import manager, returns -EBUSY if ranges are still - * allocated inside it. - */ -static void amdgpu_dgma_import_mgr_fini(struct amdgpu_device *adev) -{ - struct amdgpu_dgma_import_mgr *mgr = &adev->mman.dgma_import_mgr; - struct ttm_resource_manager *man = &mgr->manager; - int ret; - - ttm_resource_manager_set_used(man, false); - - ret = ttm_resource_manager_evict_all(&adev->mman.bdev, man); - if (ret) - return; - - spin_lock(&mgr->lock); - drm_mm_takedown(&mgr->mm); - spin_unlock(&mgr->lock); - ttm_resource_manager_cleanup(man); - ttm_set_driver_manager(&adev->mman.bdev, TTM_PL_TT, NULL); -} - -/** - * amdgpu_dgma_import_mgr_new - allocate a new node - * - * @man: TTM memory type manager - * @tbo: TTM BO we need this range for - * @place: placement flags and restrictions - * @mem: the resulting mem object - */ -static int amdgpu_dgma_import_mgr_new(struct ttm_resource_manager *man, - struct ttm_buffer_object *tbo, - const struct ttm_place *place, - struct ttm_resource **res) -{ - struct amdgpu_dgma_import_mgr *mgr = to_dgma_import_mgr(man); - uint32_t num_pages = PFN_UP(tbo->base.size); - struct amdgpu_dgma_node *node; - unsigned long lpfn; - int r; - - spin_lock(&mgr->lock); - if (atomic64_read(&mgr->available) < num_pages) { - spin_unlock(&mgr->lock); - return -ENOSPC; - } - atomic64_sub(num_pages, &mgr->available); - spin_unlock(&mgr->lock); - - lpfn = place->lpfn; - if (!lpfn) - lpfn = man->size; - - node = kzalloc(struct_size(node, base.mm_nodes, 1), GFP_KERNEL); - if (!node) { - r = -ENOMEM; - goto err_out; - } - - node->tbo = tbo; - ttm_resource_init(tbo, place, &node->base.base); - - spin_lock(&mgr->lock); - r = drm_mm_insert_node_in_range(&mgr->mm, &node->base.mm_nodes[0], num_pages, - tbo->page_alignment, 0, place->fpfn, - lpfn, DRM_MM_INSERT_BEST); - spin_unlock(&mgr->lock); - - if (unlikely(r)) - goto err_free; - - *res = &node->base.base; - (*res)->start = node->base.mm_nodes[0].start; - - return 0; - -err_free: - kfree(node); - -err_out: - atomic64_add(num_pages, &mgr->available); - - return r; -} - -/** - * amdgpu_dgma_import_mgr_del - free ranges - * - * @man: TTM memory type manager - * @mem: TTM memory object - * - * Free the allocated node. - */ -static void amdgpu_dgma_import_mgr_del(struct ttm_resource_manager *man, - struct ttm_resource *mem) -{ - struct amdgpu_dgma_import_mgr *mgr = to_dgma_import_mgr(man); - struct amdgpu_dgma_node *node = container_of(mem, struct amdgpu_dgma_node, base.base); - - if (node) { - spin_lock(&mgr->lock); - drm_mm_remove_node(&node->base.mm_nodes[0]); - spin_unlock(&mgr->lock); - kfree(node); - } - - atomic64_add(mem->num_pages, &mgr->available); -} - -static void amdgpu_dgma_import_mgr_debug(struct ttm_resource_manager *man, - struct drm_printer *printer) -{ - struct amdgpu_dgma_import_mgr *rman = to_dgma_import_mgr(man); - - spin_lock(&rman->lock); - drm_mm_print(&rman->mm, printer); - spin_unlock(&rman->lock); -} - -static const struct ttm_resource_manager_func amdgpu_dgma_import_mgr_func = { - .alloc = amdgpu_dgma_import_mgr_new, - .free = amdgpu_dgma_import_mgr_del, - .debug = amdgpu_dgma_import_mgr_debug -}; - static int amdgpu_direct_gma_init(struct amdgpu_device *adev) { struct amdgpu_bo *abo; @@ -2313,7 +2144,8 @@ static int amdgpu_direct_gma_init(struct amdgpu_device *adev) if (unlikely(r)) goto error_put_node; - r = amdgpu_dgma_import_mgr_init(adev, size >> PAGE_SHIFT); + r = ttm_range_man_init(&adev->mman.bdev, AMDGPU_PL_DGMA_IMPORT, + false, size >> PAGE_SHIFT); if (unlikely(r)) goto error_release_mm; @@ -2342,8 +2174,8 @@ static void amdgpu_direct_gma_fini(struct amdgpu_device *adev) if (amdgpu_direct_gma_size == 0) return; + ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_DGMA_IMPORT); ttm_range_man_fini(&adev->mman.bdev, AMDGPU_PL_DGMA); - amdgpu_dgma_import_mgr_fini(adev); r = amdgpu_bo_reserve(adev->direct_gma.dgma_bo, false); if (r == 0) { From dfdcc124869c75be400d4a6c76b0ec88724327b9 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 18 Oct 2022 16:25:34 +0800 Subject: [PATCH 0796/1868] drm/amdkcl: fix uninitialized bo_dev variable When bo is NULL pointer, the bo_dev variable will be used uninitialized. This is caused by 292718775885 "drm/amdkcl: fix pytorch test memory page fault" v5.18-2828-g292718775885 Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen Reviewed-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 32cd37c24189f..e27d0e8c9dca0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -1193,7 +1193,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va, uint64_t vram_base; uint64_t flags; int r; - struct amdgpu_device *bo_adev; + struct amdgpu_device *bo_adev = adev; if (clear || !bo) { mem = NULL; From ff32d01c32fc9b442ea20c1936c2c172830aeb1f Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 31 Oct 2022 19:27:32 +0800 Subject: [PATCH 0797/1868] drm/amdkcl: test register_shrinker whether has two arguments Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../gpu/drm/amd/dkms/m4/register_shrinker.m4 | 19 +++++++++++++++++++ include/kcl/kcl_shrinker.h | 10 ++++++++++ 4 files changed, 33 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/register_shrinker.m4 diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 28f62454fb160..4130071863f9f 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1056,6 +1056,9 @@ /* pxm_to_node() is available */ #define HAVE_PXM_TO_NODE 1 +/* whether register_shrinker(x, x) is available */ +#define HAVE_REGISTER_SHRINKER_WITH_TWO_ARGUMENTS 1 + /* remove_conflicting_pci_framebuffers() is available */ /* #undef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS */ diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 0db4444af38bc..869b55b92417c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -216,6 +216,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_GEM_PLANE_HELPER_PREPARE_FB AC_AMDGPU_BITMAP_TO_ARR32 AC_AMDGPU_STRUCT_DRM_CRTC + AC_AMDGPU_REGISTER_SHRINKER AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/register_shrinker.m4 b/drivers/gpu/drm/amd/dkms/m4/register_shrinker.m4 new file mode 100644 index 0000000000000..903f100bf18bd --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/register_shrinker.m4 @@ -0,0 +1,19 @@ +dnl # +dnl # v5.16-rc1-22-g91f75eb481cf x86/MCE/AMD, EDAC/mce_amd: Support non-uniform MCA bank type enumeration +dnl # +AC_DEFUN([AC_AMDGPU_REGISTER_SHRINKER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + #include + ],[ + struct shrinker *a = NULL; + const char *b = NULL; + register_shrinker(a, b); + ],[ + AC_DEFINE(HAVE_REGISTER_SHRINKER_WITH_TWO_ARGUMENTS, 1, + [whether register_shrinker(x, x) is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_shrinker.h b/include/kcl/kcl_shrinker.h index d8704a749d2dd..c237de4b867cf 100644 --- a/include/kcl/kcl_shrinker.h +++ b/include/kcl/kcl_shrinker.h @@ -7,4 +7,14 @@ extern void synchronize_shrinkers(void); #endif +static inline int __printf(2, 3) kcl_register_shrinker(struct shrinker *shrinker, + const char *fmt, ...) +{ +#if defined(HAVE_REGISTER_SHRINKER_WITH_TWO_ARGUMENTS) + return register_shrinker(shrinker, fmt); +#else + return register_shrinker(shrinker); +#endif +} + #endif From 8346285ad45a2f007f46169678c347e0548f4e14 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 12 Aug 2022 16:10:19 +0800 Subject: [PATCH 0798/1868] drm/amdkcl: test whether struct drm_dp_mst_port has member passthrough_aux It's caused by 0087990a9f572c6dd9533c973fe1072458f54b7a "drm/amd/display: consider DSC pass-through during mode validation" 99d08a5d1ad7fb76b33aabae46cd88bc7e6e6df4 "drm/amd/display: implement DSC pass-through support" Signed-off-by: Asher Song Reviewed-by: Flora Cui --- .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 16 ++++++++++--- .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../gpu/drm/amd/dkms/m4/drm-dp-mst-port.m4 | 23 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 5 files changed, 41 insertions(+), 3 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-port.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index d696722c1d98a..b218cb94c321e 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -820,16 +820,20 @@ bool dm_helpers_dp_write_dsc_enable( const struct dc_stream_state *stream, bool enable) { + struct amdgpu_dm_connector *aconnector = + (struct amdgpu_dm_connector *)stream->dm_stream_context; + struct drm_device *dev = aconnector->base.dev; +#if defined(HAVE_DRM_DP_MST_PORT_PASSTHROUGH_AUX) static const uint8_t DSC_DISABLE; static const uint8_t DSC_DECODING = 0x01; static const uint8_t DSC_PASSTHROUGH = 0x02; - struct amdgpu_dm_connector *aconnector = - (struct amdgpu_dm_connector *)stream->dm_stream_context; - struct drm_device *dev = aconnector->base.dev; struct drm_dp_mst_port *port; uint8_t enable_dsc = enable ? DSC_DECODING : DSC_DISABLE; uint8_t enable_passthrough = enable ? DSC_PASSTHROUGH : DSC_DISABLE; +#else + uint8_t enable_dsc = enable ? 1 : 0; +#endif uint8_t ret = 0; if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { @@ -842,6 +846,7 @@ bool dm_helpers_dp_write_dsc_enable( return write_dsc_enable_synaptics_non_virtual_dpcd_mst( aconnector->dsc_aux, stream, enable_dsc); +#if defined(HAVE_DRM_DP_MST_PORT_PASSTHROUGH_AUX) port = aconnector->mst_output_port; if (enable) { @@ -879,6 +884,11 @@ bool dm_helpers_dp_write_dsc_enable( ret); } } +#else + ret = drm_dp_dpcd_write(aconnector->dsc_aux, DP_DSC_ENABLE, &enable_dsc, 1); + DC_LOG_DC("Send DSC %s to MST RX\n", enable_dsc ? "enable" : "disable"); +#endif + } if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT || stream->signal == SIGNAL_TYPE_EDP) { diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index b7b4593530f2a..7b8350b0a5bf9 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -1915,6 +1915,7 @@ enum dc_status dm_dp_mst_is_port_support_mode( DRM_DEBUG_DRIVER("DSC is required but can't find common dsc config."); return DC_FAIL_BANDWIDTH_VALIDATE; } + #endif return DC_OK; } diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 4130071863f9f..bb79f8bc7a5bb 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -405,6 +405,9 @@ /* drm_dp_mst_{get,put}_port_malloc() is available */ #define HAVE_DRM_DP_MST_GET_PUT_PORT_MALLOC 1 +/* struct drm_dp_mst_port has passthrough_aux member */ +/* #undef HAVE_DRM_DP_MST_PORT_PASSTHROUGH_AUX */ + /* struct drm_dp_mst_topology_cbs->destroy_connector is available */ /* #undef HAVE_DRM_DP_MST_TOPOLOGY_CBS_DESTROY_CONNECTOR */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-port.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-port.m4 new file mode 100644 index 0000000000000..a1f26ca53e149 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-port.m4 @@ -0,0 +1,23 @@ +dnl # +dnl # commit v5.18-2579-g3af4b1f1d6e7 +dnl # "drm/dp_mst: add passthrough_aux to struct drm_dp_mst_port" +dnl +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_POST_PASSTHROUGH_AUX], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) + #include + #else + #include + #endif + ], [ + struct drm_dp_mst_port *dp_mst_port = NULL; + dp_mst_port->passthrough_aux = NULL; + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_PORT_PASSTHROUGH_AUX, 1, + [struct drm_dp_mst_port has passthrough_aux member]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 869b55b92417c..8743ed789c2a1 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -217,6 +217,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_BITMAP_TO_ARR32 AC_AMDGPU_STRUCT_DRM_CRTC AC_AMDGPU_REGISTER_SHRINKER + AC_AMDGPU_DRM_DP_MST_POST_PASSTHROUGH_AUX AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 1651329dddb57ad2d3f6dd56f2adf137f616a0f2 Mon Sep 17 00:00:00 2001 From: Bob zhou Date: Fri, 28 Oct 2022 16:36:06 +0800 Subject: [PATCH 0799/1868] drm/amdkcl: test whether display_info->max_dsc_bpp is available It's caused by cb4f0334768bb60ff144dd8ec1cd212dc09dcf6d "Revert "drm/amd/display: Limit max DSC target bpp for specific monitors"" affba10c1048d56a146cbb6b4ae13d0bf644a7b5 "drm/amd/display: use max_dsc_bpp in amdgpu_dm" Signed-off-by: Bob zhou Reviewed-by: Leslie Shi --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 7 ++++ .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 39 +++++++++++++++++++ .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 4 ++ drivers/gpu/drm/amd/dkms/config/config.h | 3 ++ .../gpu/drm/amd/dkms/m4/drm-display-info.m4 | 19 +++++++++ 5 files changed, 72 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 629e586d7585d..5459fcde8e63d 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -6664,8 +6664,15 @@ static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector, struct dc *dc = sink->ctx->dc; u32 max_supported_bw_in_kbps, timing_bw_in_kbps; u32 dsc_max_supported_bw_in_kbps; +#ifdef HAVE_DRM_DISPLAY_INFO_MAX_DSC_BPP u32 max_dsc_target_bpp_limit_override = drm_connector->display_info.max_dsc_bpp; +#else + u32 max_dsc_target_bpp_limit_override = 0; + if (stream->link && stream->link->local_sink) + max_dsc_target_bpp_limit_override = + stream->link->local_sink->edid_caps.panel_patch.max_dsc_target_bpp_limit; +#endif struct dc_dsc_config_options dsc_options = {0}; dc_dsc_get_default_config_option(dc, &dsc_options); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index b218cb94c321e..59d8a0b29edd6 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -45,6 +45,41 @@ #include "dm_helpers.h" #include "ddc_service_types.h" +#ifndef HAVE_DRM_DISPLAY_INFO_MAX_DSC_BPP +struct monitor_patch_info { + unsigned int manufacturer_id; + unsigned int product_id; + void (*patch_func)(struct dc_edid_caps *edid_caps, unsigned int param); + unsigned int patch_param; +}; +static void set_max_dsc_bpp_limit(struct dc_edid_caps *edid_caps, unsigned int param); + +static const struct monitor_patch_info monitor_patch_table[] = { +{0x6D1E, 0x5BBF, set_max_dsc_bpp_limit, 15}, +{0x6D1E, 0x5B9A, set_max_dsc_bpp_limit, 15}, +}; + +static void set_max_dsc_bpp_limit(struct dc_edid_caps *edid_caps, unsigned int param) +{ + if (edid_caps) + edid_caps->panel_patch.max_dsc_target_bpp_limit = param; +} + +static int amdgpu_dm_patch_edid_caps(struct dc_edid_caps *edid_caps) +{ + int i, ret = 0; + + for (i = 0; i < ARRAY_SIZE(monitor_patch_table); i++) + if ((edid_caps->manufacturer_id == monitor_patch_table[i].manufacturer_id) + && (edid_caps->product_id == monitor_patch_table[i].product_id)) { + monitor_patch_table[i].patch_func(edid_caps, monitor_patch_table[i].patch_param); + ret++; + } + + return ret; +} +#endif + static u32 edid_extract_panel_id(struct edid *edid) { return (u32)edid->mfg_id[0] << 24 | @@ -178,6 +213,10 @@ enum dc_edid_status dm_helpers_parse_edid_caps( kfree(sads); kfree(sadb); +#ifndef HAVE_DRM_DISPLAY_INFO_MAX_DSC_BPP + amdgpu_dm_patch_edid_caps(edid_caps); +#endif + return result; } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 7b8350b0a5bf9..95508ee3821bf 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -1024,7 +1024,11 @@ static int bpp_x16_from_pbn(struct dsc_mst_fairness_params param, int pbn) struct dc_dsc_config_options dsc_options = {0}; dc_dsc_get_default_config_option(param.sink->ctx->dc, &dsc_options); +#ifdef HAVE_DRM_DISPLAY_INFO_MAX_DSC_BPP dsc_options.max_target_bpp_limit_override_x16 = drm_connector->display_info.max_dsc_bpp * 16; +#else + dsc_options.max_target_bpp_limit_override_x16 = param.sink->edid_caps.panel_patch.max_dsc_target_bpp_limit * 16; +#endif kbps = div_u64((u64)pbn * 994 * 8 * 54, 64); dc_dsc_compute_config( diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index bb79f8bc7a5bb..267e5b2e7e13a 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -354,6 +354,9 @@ /* struct drm_display_info has monitor_range member */ #define HAVE_DRM_DISPLAY_INFO_MONITOR_RANGE 1 +/* display_info->max_dsc_bpp is available */ +/* #undef HAVE_DRM_DISPLAY_INFO_MAX_DSC_BPP */ + /* drm_dp_atomic_find_vcpi_slots() is available */ #define HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-display-info.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-display-info.m4 index 6e726111f8c16..e498f3bc94867 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-display-info.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-display-info.m4 @@ -36,7 +36,26 @@ AC_DEFUN([AC_AMDGPU_DRM_DISPLAY_INFO_MONITOR_RANGE], [ ]) ]) +dnl # +dnl # commit v5.18-3347-g721ed0ae5acf +dnl # drm/edid: add a quirk for two LG monitors to get them to work on 10bpc +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DISPLAY_INFO_MAX_DSC_BPP], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_display_info *display_info = NULL; + display_info->max_dsc_bpp=0; + ],[ + AC_DEFINE(HAVE_DRM_DISPLAY_INFO_MAX_DSC_BPP, 1, + [display_info->max_dsc_bpp is available]) + ]) + ]) +]) + AC_DEFUN([AC_AMDGPU_DRM_DISPLAY_INFO], [ AC_AMDGPU_DRM_DISPLAY_INFO_EDID_HDMI_RGB444_DC_MODES AC_AMDGPU_DRM_DISPLAY_INFO_MONITOR_RANGE + AC_AMDGPU_DRM_DISPLAY_INFO_MAX_DSC_BPP ]) From cbc8d6c364c171e85d594b333679c0acc1223418 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 13 Jun 2024 13:46:45 +0800 Subject: [PATCH 0800/1868] drm/amdkcl: wrap code under macro HAVE_DRM_DISPLAY_INFO_MAX_DSC_BPP It's caused by 13ba1f22181d90f4d62f9103351581b94d2442b2 "drm/amd/display: Refactor function dm_dp_mst_is_port_support_mode()" Signed-off-by: Bob Zhou Reviewed-by: Asher Song Reviewed-by: Wayne Lin --- .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 95508ee3821bf..3e11893928a1e 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -1812,6 +1812,7 @@ enum dc_status dm_dp_mst_is_port_support_mode( { #if defined(CONFIG_DRM_AMD_DC_FP) int branch_max_throughput_mps = 0; +#if defined(HAVE_DRM_DP_MST_PORT_PASSTHROUGH_AUX) && defined(HAVE_DRM_DISPLAY_INFO_MAX_DSC_BPP) struct dc_link_settings cur_link_settings; uint32_t end_to_end_bw_in_kbps = 0; uint32_t root_link_bw_in_kbps = 0; @@ -1919,7 +1920,41 @@ enum dc_status dm_dp_mst_is_port_support_mode( DRM_DEBUG_DRIVER("DSC is required but can't find common dsc config."); return DC_FAIL_BANDWIDTH_VALIDATE; } +#else + int pbn; + /* Check if mode could be supported within max slot + * number of current mst link and full_pbn of mst links. + */ + int pbn_div, slot_num, max_slot_num; + enum dc_link_encoding_format link_encoding; + uint32_t stream_kbps = dc_bandwidth_in_kbps_from_timing( + &stream->timing, + dc_link_get_highest_encoding_format(stream->link)); + + pbn = kbps_to_peak_pbn(stream_kbps); + pbn_div = dm_mst_get_pbn_divider(stream->link); + slot_num = DIV_ROUND_UP(pbn, pbn_div); + + link_encoding = dc_link_get_highest_encoding_format(stream->link); + if (link_encoding == DC_LINK_ENCODING_DP_8b_10b) + max_slot_num = 63; + else if (link_encoding == DC_LINK_ENCODING_DP_128b_132b) + max_slot_num = 64; + else { + DRM_DEBUG_DRIVER("Invalid link encoding format\n"); + return DC_FAIL_BANDWIDTH_VALIDATE; + } + if (slot_num > max_slot_num || +#ifdef HAVE_DRM_DP_MST_PORT_FULL_PBN + pbn > aconnector->mst_output_port->full_pbn) { +#else + pbn > aconnector->mst_output_port->available_pbn) { +#endif + DRM_DEBUG_DRIVER("Mode can not be supported within mst links!"); + return DC_FAIL_BANDWIDTH_VALIDATE; + } +#endif #endif return DC_OK; } From 575984e98ee8d8579ec6bee4c4ce8e0a11dd58f0 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 27 Jul 2022 10:34:23 +0800 Subject: [PATCH 0801/1868] drm/amdkcl: Test whether struct drm_dp_mst_port has full_pbn member Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../amd/dkms/m4/drm-dp-mst-port-full-pbn.m4 | 23 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 27 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-port-full-pbn.m4 diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 267e5b2e7e13a..6b05c9524ab2e 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -411,6 +411,9 @@ /* struct drm_dp_mst_port has passthrough_aux member */ /* #undef HAVE_DRM_DP_MST_PORT_PASSTHROUGH_AUX */ +/* drm_dp_mst_port struct has full_pbn member */ +#define HAVE_DRM_DP_MST_PORT_FULL_PBN 1 + /* struct drm_dp_mst_topology_cbs->destroy_connector is available */ /* #undef HAVE_DRM_DP_MST_TOPOLOGY_CBS_DESTROY_CONNECTOR */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-port-full-pbn.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-port-full-pbn.m4 new file mode 100644 index 0000000000000..dc2ce8bd06835 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-port-full-pbn.m4 @@ -0,0 +1,23 @@ +dnl # +dnl # commit v5.6-rc5-4-gfcf463807596 +dnl # drm/dp_mst: Use full_pbn instead of available_pbn for bandwidth checks +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_PORT_FULL_PBN], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) + #include + #else + #include + #endif + ], [ + struct drm_dp_mst_port *mst_port = NULL; + mst_port->full_pbn = 0; + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_PORT_FULL_PBN, 1, + [drm_dp_mst_port struct has full_pbn member]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 8743ed789c2a1..e997936f7f6b4 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -218,6 +218,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_STRUCT_DRM_CRTC AC_AMDGPU_REGISTER_SHRINKER AC_AMDGPU_DRM_DP_MST_POST_PASSTHROUGH_AUX + AC_AMDGPU_DRM_DP_MST_PORT_FULL_PBN AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From dd7e083ea970500c3572ddba2ff6bbec9f80dad9 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 7 Nov 2022 17:50:22 +0800 Subject: [PATCH 0802/1868] drm/amdkcl: wrap code under macro HAVE_DRM_DP_MST_PORT_PASSTHROUGH_AUX Signed-off-by: Asher Song --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 3e11893928a1e..3fe1c62fcd8b6 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -1724,6 +1724,7 @@ int pre_validate_dsc(struct drm_atomic_state *state, return ret; } +#ifdef HAVE_DRM_DP_MST_PORT_PASSTHROUGH_AUX static unsigned int kbps_from_pbn(unsigned int pbn) { unsigned int kbps = pbn; @@ -1753,6 +1754,7 @@ static bool is_dsc_common_config_possible(struct dc_stream_state *stream, } #endif #endif /* HAVE_DRM_DP_MST_ATOMIC_CHECK */ +#endif #if defined(CONFIG_DRM_AMD_DC_FP) static bool dp_get_link_current_set_bw(struct drm_dp_aux *aux, uint32_t *cur_link_bw) From ec3a018e1e3c985837c13a6e22b5f642a52ec21e Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 20 Oct 2022 14:06:45 +0800 Subject: [PATCH 0803/1868] drm/amdkcl: fake kmap_local_* It's caused by f7e8a8be4361c6cba23fd5df693a830e8351402c "drm/amd/amdgpu: Replace kmap() with kmap_local_page()" Signed-off-by: Asher Song --- drivers/gpu/drm/amd/backport/backport.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index fe458b9b1f4cc..475cc32dcc47c 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -99,4 +99,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ From 3fdea9340e216137d4ed9aca2c80a0e0a0305504 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 26 Oct 2022 14:31:13 +0800 Subject: [PATCH 0804/1868] drm/amdkcl: wrap code under macro HAVE_DRM_MODE_CONFIG_FB_MODIFIERS_NOT_SUPPORTED It's caused by 7a462295e26244d5d21d101b9d8b33cd327e95f1 "drm/amdgpu: set fb_modifiers_not_supported in vkms" Signed-off-by: Asher Song Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c index ddeccca905504..f4cc269122cc6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c @@ -662,7 +662,9 @@ static int amdgpu_vkms_sw_init(void *handle) adev_to_drm(adev)->mode_config.preferred_depth = 24; adev_to_drm(adev)->mode_config.prefer_shadow = 1; +#ifdef HAVE_DRM_MODE_CONFIG_FB_MODIFIERS_NOT_SUPPORTED adev_to_drm(adev)->mode_config.fb_modifiers_not_supported = true; +#endif r = amdgpu_display_modeset_create_props(adev); if (r) From 77f0217a16c05e843db26e49440c5e6379486c6e Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 26 Oct 2022 15:31:13 +0800 Subject: [PATCH 0805/1868] drm/amdkcl: Modify CONFIG_DRM_AMD_DC_DSC_SUPPORT enable condition According to the Kconfig file, the CONFIG_DRM_AMD_DC_DSC_SUPPORT is selected by CONFIG_DRM_AMD_DC_DCN. So, we should enable them together. Or else, there maybe are compile errors on phantoms or the arm64 platform Signed-off-by: Ma Jun Reviewed-by: Flora Cui Change-Id: Ia2e3f15195cf01f7521a8c0c50553484c155e842 --- drivers/gpu/drm/amd/dkms/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 4755cde423517..f7fa3166cdb33 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -188,11 +188,11 @@ ifndef CONFIG_ARM64 ifeq ($(filter %core2, $(KBUILD_CFLAGS)),) export CONFIG_DRM_AMD_DC_DCN=y subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN -endif -endif export CONFIG_DRM_AMD_DC_DSC_SUPPORT=y subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DSC_SUPPORT +endif +endif export CONFIG_DRM_TTM_HELPER=m subdir-ccflags-y += -DCONFIG_DRM_TTM_HELPER From 048167dec69abe99d054df3bc4d6645e37e53fec Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 26 Oct 2022 12:27:04 +0800 Subject: [PATCH 0806/1868] drm/amdkcl: join multiple exclusive fences instead of overwriting old fence If old exclusive fence is not signaled, use dma_fence_chain to join old and new fence together. Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c b/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c index 1477c6349dad7..67f67bcd4e2b4 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c @@ -34,6 +34,7 @@ */ #include #include +#include #include #include #include @@ -353,9 +354,21 @@ static void dma_resv_add_excl_fence(struct dma_resv *obj, struct dma_fence *fence) { struct dma_fence *old_fence = dma_resv_excl_fence(obj); + struct dma_fence_chain *chain; dma_resv_assert_held(obj); + if (old_fence && !dma_fence_is_signaled(old_fence)) { + + chain = dma_fence_chain_alloc(); + if (unlikely(!chain)) + pr_err("dma_resv_add_excl_fence OOM\n"); + else { + dma_fence_chain_init(chain, dma_fence_get(old_fence), dma_fence_get(fence), 1); + fence = &chain->base; + } + } + dma_fence_get(fence); write_seqcount_begin(&obj->seq); From 83c02d7fef62c06ef1382afe15276e8f260004d7 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 27 Oct 2022 17:14:12 +0800 Subject: [PATCH 0807/1868] drm/amdkcl: Add drm buddy Add drm_buddy.c as a new module Signed-off-by: Ma Jun Reviewed-by: Flora Cui Change-Id: I945c93d973c6bb9e6a401acce79789c80b58a2da --- drivers/gpu/drm/amd/amdkcl/files | 2 +- drivers/gpu/drm/amd/dkms/Makefile | 6 ++++++ drivers/gpu/drm/amd/dkms/dkms.conf | 4 ++++ drivers/gpu/drm/amd/dkms/sources | 2 ++ 4 files changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkcl/files b/drivers/gpu/drm/amd/amdkcl/files index 6cc9587ebc525..20534a90dbb86 100644 --- a/drivers/gpu/drm/amd/amdkcl/files +++ b/drivers/gpu/drm/amd/amdkcl/files @@ -1 +1 @@ -FILES="ttm/*.c scheduler/*.c amd/amdkcl/dma-buf/dma-resv.c drm_gem_ttm_helper.c" +FILES="ttm/*.c scheduler/*.c amd/amdkcl/dma-buf/dma-resv.c drm_gem_ttm_helper.c drm_buddy.c" diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index f7fa3166cdb33..eec0d7868d7c2 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -202,4 +202,10 @@ CFLAGS_drm_gem_ttm_helper.o += -include $(src)/ttm/backport/backport.h \ amddrm_ttm_helper-y := drm_gem_ttm_helper.o obj-$(CONFIG_DRM_TTM_HELPER) += amddrm_ttm_helper.o +export CONFIG_DRM_BUDDY=m +subdir-ccflags-y += -DCONFIG_DRM_BUDDY +CFLAGS_drm_buddy.o += -DHAVE_CONFIG_H +amddrm_buddy-y := drm_buddy.o +obj-$(CONFIG_DRM_BUDDY) += amddrm_buddy.o + obj-m += scheduler/ amd/amdgpu/ ttm/ amd/amdkcl/ diff --git a/drivers/gpu/drm/amd/dkms/dkms.conf b/drivers/gpu/drm/amd/dkms/dkms.conf index a4fde02caa219..caa34f979ef96 100644 --- a/drivers/gpu/drm/amd/dkms/dkms.conf +++ b/drivers/gpu/drm/amd/dkms/dkms.conf @@ -26,6 +26,10 @@ BUILT_MODULE_NAME[4]="amddrm_ttm_helper" BUILT_MODULE_LOCATION[4]="." DEST_MODULE_LOCATION[4]="/kernel/drivers/gpu/drm" +BUILT_MODULE_NAME[5]="amddrm_buddy" +BUILT_MODULE_LOCATION[5]="." +DEST_MODULE_LOCATION[5]="/kernel/drivers/gpu/drm" + MAKE[0]="make TTM_NAME=${BUILT_MODULE_NAME[1]} \ SCHED_NAME=${BUILT_MODULE_NAME[3]} \ -C $kernel_source_dir \ diff --git a/drivers/gpu/drm/amd/dkms/sources b/drivers/gpu/drm/amd/dkms/sources index 60563cf6abf8e..373b38d0d2325 100644 --- a/drivers/gpu/drm/amd/dkms/sources +++ b/drivers/gpu/drm/amd/dkms/sources @@ -31,3 +31,5 @@ include/kcl/reservation.h include/linux/ include/uapi/linux/kfd_sysfs.h include/uapi/linux/ drivers/gpu/drm/drm_gem_ttm_helper.c . include/drm/drm_gem_ttm_helper.h include/drm/ +drivers/gpu/drm/drm_buddy.c . +include/drm/drm_buddy.h include/drm/ From 42b82337f349616bed77f98265e92356ee39cf8d Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Fri, 28 Oct 2022 15:10:18 +0800 Subject: [PATCH 0808/1868] drm/amdkcl:Remove kcl_drm_buddy related file Because the drm_buddy is added as a module, these files can be removed now Signed-off-by: Ma Jun Reviewed-by: Flora Cui Change-Id: Idead98ab257bcdc689de6257a9aea88a0ddbdb02 --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_drm_buddy.c | 783 --------------------- drivers/gpu/drm/amd/amdkcl/main.c | 12 +- drivers/gpu/drm/amd/backport/backport.h | 1 - include/kcl/header/drm/drm_buddy.h | 11 - include/kcl/kcl_drm_buddy.h | 171 ----- 6 files changed, 2 insertions(+), 978 deletions(-) delete mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_buddy.c delete mode 100644 include/kcl/header/drm/drm_buddy.h delete mode 100644 include/kcl/kcl_drm_buddy.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 0104acd2fd133..8e3650b52cfc0 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -13,7 +13,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o kcl_ftrace.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_fs_read_write.o kcl_drm_aperture.o \ kcl_drm_drv.o kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o \ - kcl_mce_amd.o kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o kcl_drm_buddy.o + kcl_mce_amd.o kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_buddy.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_buddy.c deleted file mode 100644 index 0d18f0d43b68d..0000000000000 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_buddy.c +++ /dev/null @@ -1,783 +0,0 @@ -// SPDX-License-Identifier: MIT -/* - * Copyright © 2021 Intel Corporation - */ - -#include -#ifndef HAVE_DRM_DRM_BUDDY_H - -#include - -static struct kmem_cache *slab_blocks; - -static struct drm_buddy_block *drm_block_alloc(struct drm_buddy *mm, - struct drm_buddy_block *parent, - unsigned int order, - u64 offset) -{ - struct drm_buddy_block *block; - - BUG_ON(order > DRM_BUDDY_MAX_ORDER); - - block = kmem_cache_zalloc(slab_blocks, GFP_KERNEL); - if (!block) - return NULL; - - block->header = offset; - block->header |= order; - block->parent = parent; - - BUG_ON(block->header & DRM_BUDDY_HEADER_UNUSED); - return block; -} - -static void drm_block_free(struct drm_buddy *mm, - struct drm_buddy_block *block) -{ - kmem_cache_free(slab_blocks, block); -} - -static void mark_allocated(struct drm_buddy_block *block) -{ - block->header &= ~DRM_BUDDY_HEADER_STATE; - block->header |= DRM_BUDDY_ALLOCATED; - - list_del(&block->link); -} - -static void mark_free(struct drm_buddy *mm, - struct drm_buddy_block *block) -{ - block->header &= ~DRM_BUDDY_HEADER_STATE; - block->header |= DRM_BUDDY_FREE; - - list_add(&block->link, - &mm->free_list[drm_buddy_block_order(block)]); -} - -static void mark_split(struct drm_buddy_block *block) -{ - block->header &= ~DRM_BUDDY_HEADER_STATE; - block->header |= DRM_BUDDY_SPLIT; - - list_del(&block->link); -} - -/** - * drm_buddy_init - init memory manager - * - * @mm: DRM buddy manager to initialize - * @size: size in bytes to manage - * @chunk_size: minimum page size in bytes for our allocations - * - * Initializes the memory manager and its resources. - * - * Returns: - * 0 on success, error code on failure. - */ -int kcl_drm_buddy_init(struct drm_buddy *mm, u64 size, u64 chunk_size) -{ - unsigned int i; - u64 offset; - - if (size < chunk_size) - return -EINVAL; - - if (chunk_size < PAGE_SIZE) - return -EINVAL; - - if (!is_power_of_2(chunk_size)) - return -EINVAL; - - size = round_down(size, chunk_size); - - mm->size = size; - mm->avail = size; - mm->chunk_size = chunk_size; - mm->max_order = ilog2(size) - ilog2(chunk_size); - - BUG_ON(mm->max_order > DRM_BUDDY_MAX_ORDER); - - mm->free_list = kmalloc_array(mm->max_order + 1, - sizeof(struct list_head), - GFP_KERNEL); - if (!mm->free_list) - return -ENOMEM; - - for (i = 0; i <= mm->max_order; ++i) - INIT_LIST_HEAD(&mm->free_list[i]); - - mm->n_roots = hweight64(size); - - mm->roots = kmalloc_array(mm->n_roots, - sizeof(struct drm_buddy_block *), - GFP_KERNEL); - if (!mm->roots) - goto out_free_list; - - offset = 0; - i = 0; - - /* - * Split into power-of-two blocks, in case we are given a size that is - * not itself a power-of-two. - */ - do { - struct drm_buddy_block *root; - unsigned int order; - u64 root_size; - - root_size = rounddown_pow_of_two(size); - order = ilog2(root_size) - ilog2(chunk_size); - - root = drm_block_alloc(mm, NULL, order, offset); - if (!root) - goto out_free_roots; - - mark_free(mm, root); - - BUG_ON(i > mm->max_order); - BUG_ON(drm_buddy_block_size(mm, root) < chunk_size); - - mm->roots[i] = root; - - offset += root_size; - size -= root_size; - i++; - } while (size); - - return 0; - -out_free_roots: - while (i--) - drm_block_free(mm, mm->roots[i]); - kfree(mm->roots); -out_free_list: - kfree(mm->free_list); - return -ENOMEM; -} -EXPORT_SYMBOL(kcl_drm_buddy_init); - -/** - * drm_buddy_fini - tear down the memory manager - * - * @mm: DRM buddy manager to free - * - * Cleanup memory manager resources and the freelist - */ -void kcl_drm_buddy_fini(struct drm_buddy *mm) -{ - int i; - - for (i = 0; i < mm->n_roots; ++i) { - WARN_ON(!drm_buddy_block_is_free(mm->roots[i])); - drm_block_free(mm, mm->roots[i]); - } - - WARN_ON(mm->avail != mm->size); - - kfree(mm->roots); - kfree(mm->free_list); -} -EXPORT_SYMBOL(kcl_drm_buddy_fini); - -static int split_block(struct drm_buddy *mm, - struct drm_buddy_block *block) -{ - unsigned int block_order = drm_buddy_block_order(block) - 1; - u64 offset = drm_buddy_block_offset(block); - - BUG_ON(!drm_buddy_block_is_free(block)); - BUG_ON(!drm_buddy_block_order(block)); - - block->left = drm_block_alloc(mm, block, block_order, offset); - if (!block->left) - return -ENOMEM; - - block->right = drm_block_alloc(mm, block, block_order, - offset + (mm->chunk_size << block_order)); - if (!block->right) { - drm_block_free(mm, block->left); - return -ENOMEM; - } - - mark_free(mm, block->left); - mark_free(mm, block->right); - - mark_split(block); - - return 0; -} - -static struct drm_buddy_block * -__get_buddy(struct drm_buddy_block *block) -{ - struct drm_buddy_block *parent; - - parent = block->parent; - if (!parent) - return NULL; - - if (parent->left == block) - return parent->right; - - return parent->left; -} - -/** - * drm_get_buddy - get buddy address - * - * @block: DRM buddy block - * - * Returns the corresponding buddy block for @block, or NULL - * if this is a root block and can't be merged further. - * Requires some kind of locking to protect against - * any concurrent allocate and free operations. - */ -struct drm_buddy_block * -kcl_drm_get_buddy(struct drm_buddy_block *block) -{ - return __get_buddy(block); -} -EXPORT_SYMBOL(kcl_drm_get_buddy); - -static void __drm_buddy_free(struct drm_buddy *mm, - struct drm_buddy_block *block) -{ - struct drm_buddy_block *parent; - - while ((parent = block->parent)) { - struct drm_buddy_block *buddy; - - buddy = __get_buddy(block); - - if (!drm_buddy_block_is_free(buddy)) - break; - - list_del(&buddy->link); - - drm_block_free(mm, block); - drm_block_free(mm, buddy); - - block = parent; - } - - mark_free(mm, block); -} - -/** - * drm_buddy_free_block - free a block - * - * @mm: DRM buddy manager - * @block: block to be freed - */ -void kcl_drm_buddy_free_block(struct drm_buddy *mm, - struct drm_buddy_block *block) -{ - BUG_ON(!drm_buddy_block_is_allocated(block)); - mm->avail += drm_buddy_block_size(mm, block); - __drm_buddy_free(mm, block); -} -EXPORT_SYMBOL(kcl_drm_buddy_free_block); - -/** - * drm_buddy_free_list - free blocks - * - * @mm: DRM buddy manager - * @objects: input list head to free blocks - */ -void kcl_drm_buddy_free_list(struct drm_buddy *mm, struct list_head *objects) -{ - struct drm_buddy_block *block, *on; - - list_for_each_entry_safe(block, on, objects, link) { - drm_buddy_free_block(mm, block); - cond_resched(); - } - INIT_LIST_HEAD(objects); -} -EXPORT_SYMBOL(kcl_drm_buddy_free_list); - -static inline bool overlaps(u64 s1, u64 e1, u64 s2, u64 e2) -{ - return s1 <= e2 && e1 >= s2; -} - -static inline bool contains(u64 s1, u64 e1, u64 s2, u64 e2) -{ - return s1 <= s2 && e1 >= e2; -} - -static struct drm_buddy_block * -alloc_range_bias(struct drm_buddy *mm, - u64 start, u64 end, - unsigned int order) -{ - struct drm_buddy_block *block; - struct drm_buddy_block *buddy; - LIST_HEAD(dfs); - int err; - int i; - - end = end - 1; - - for (i = 0; i < mm->n_roots; ++i) - list_add_tail(&mm->roots[i]->tmp_link, &dfs); - - do { - u64 block_start; - u64 block_end; - - block = list_first_entry_or_null(&dfs, - struct drm_buddy_block, - tmp_link); - if (!block) - break; - - list_del(&block->tmp_link); - - if (drm_buddy_block_order(block) < order) - continue; - - block_start = drm_buddy_block_offset(block); - block_end = block_start + drm_buddy_block_size(mm, block) - 1; - - if (!overlaps(start, end, block_start, block_end)) - continue; - - if (drm_buddy_block_is_allocated(block)) - continue; - - if (contains(start, end, block_start, block_end) && - order == drm_buddy_block_order(block)) { - /* - * Find the free block within the range. - */ - if (drm_buddy_block_is_free(block)) - return block; - - continue; - } - - if (!drm_buddy_block_is_split(block)) { - err = split_block(mm, block); - if (unlikely(err)) - goto err_undo; - } - - list_add(&block->right->tmp_link, &dfs); - list_add(&block->left->tmp_link, &dfs); - } while (1); - - return ERR_PTR(-ENOSPC); - -err_undo: - /* - * We really don't want to leave around a bunch of split blocks, since - * bigger is better, so make sure we merge everything back before we - * free the allocated blocks. - */ - buddy = __get_buddy(block); - if (buddy && - (drm_buddy_block_is_free(block) && - drm_buddy_block_is_free(buddy))) - __drm_buddy_free(mm, block); - return ERR_PTR(err); -} - -static struct drm_buddy_block * -get_maxblock(struct list_head *head) -{ - struct drm_buddy_block *max_block = NULL, *node; - - max_block = list_first_entry_or_null(head, - struct drm_buddy_block, - link); - if (!max_block) - return NULL; - - list_for_each_entry(node, head, link) { - if (drm_buddy_block_offset(node) > - drm_buddy_block_offset(max_block)) - max_block = node; - } - - return max_block; -} - -static struct drm_buddy_block * -alloc_from_freelist(struct drm_buddy *mm, - unsigned int order, - unsigned long flags) -{ - struct drm_buddy_block *block = NULL; - unsigned int i; - int err; - - for (i = order; i <= mm->max_order; ++i) { - if (flags & DRM_BUDDY_TOPDOWN_ALLOCATION) { - block = get_maxblock(&mm->free_list[i]); - if (block) - break; - } else { - block = list_first_entry_or_null(&mm->free_list[i], - struct drm_buddy_block, - link); - if (block) - break; - } - } - - if (!block) - return ERR_PTR(-ENOSPC); - - BUG_ON(!drm_buddy_block_is_free(block)); - - while (i != order) { - err = split_block(mm, block); - if (unlikely(err)) - goto err_undo; - - block = block->right; - i--; - } - return block; - -err_undo: - if (i != order) - __drm_buddy_free(mm, block); - return ERR_PTR(err); -} - -static int __alloc_range(struct drm_buddy *mm, - struct list_head *dfs, - u64 start, u64 size, - struct list_head *blocks) -{ - struct drm_buddy_block *block; - struct drm_buddy_block *buddy; - LIST_HEAD(allocated); - u64 end; - int err; - - end = start + size - 1; - - do { - u64 block_start; - u64 block_end; - - block = list_first_entry_or_null(dfs, - struct drm_buddy_block, - tmp_link); - if (!block) - break; - - list_del(&block->tmp_link); - - block_start = drm_buddy_block_offset(block); - block_end = block_start + drm_buddy_block_size(mm, block) - 1; - - if (!overlaps(start, end, block_start, block_end)) - continue; - - if (drm_buddy_block_is_allocated(block)) { - err = -ENOSPC; - goto err_free; - } - - if (contains(start, end, block_start, block_end)) { - if (!drm_buddy_block_is_free(block)) { - err = -ENOSPC; - goto err_free; - } - - mark_allocated(block); - mm->avail -= drm_buddy_block_size(mm, block); - list_add_tail(&block->link, &allocated); - continue; - } - - if (!drm_buddy_block_is_split(block)) { - err = split_block(mm, block); - if (unlikely(err)) - goto err_undo; - } - - list_add(&block->right->tmp_link, dfs); - list_add(&block->left->tmp_link, dfs); - } while (1); - - list_splice_tail(&allocated, blocks); - return 0; - -err_undo: - /* - * We really don't want to leave around a bunch of split blocks, since - * bigger is better, so make sure we merge everything back before we - * free the allocated blocks. - */ - buddy = __get_buddy(block); - if (buddy && - (drm_buddy_block_is_free(block) && - drm_buddy_block_is_free(buddy))) - __drm_buddy_free(mm, block); - -err_free: - drm_buddy_free_list(mm, &allocated); - return err; -} - -static int __drm_buddy_alloc_range(struct drm_buddy *mm, - u64 start, - u64 size, - struct list_head *blocks) -{ - LIST_HEAD(dfs); - int i; - - for (i = 0; i < mm->n_roots; ++i) - list_add_tail(&mm->roots[i]->tmp_link, &dfs); - - return __alloc_range(mm, &dfs, start, size, blocks); -} - -/** - * drm_buddy_block_trim - free unused pages - * - * @mm: DRM buddy manager - * @new_size: original size requested - * @blocks: Input and output list of allocated blocks. - * MUST contain single block as input to be trimmed. - * On success will contain the newly allocated blocks - * making up the @new_size. Blocks always appear in - * ascending order - * - * For contiguous allocation, we round up the size to the nearest - * power of two value, drivers consume *actual* size, so remaining - * portions are unused and can be optionally freed with this function - * - * Returns: - * 0 on success, error code on failure. - */ -int kcl_drm_buddy_block_trim(struct drm_buddy *mm, - u64 new_size, - struct list_head *blocks) -{ - struct drm_buddy_block *parent; - struct drm_buddy_block *block; - LIST_HEAD(dfs); - u64 new_start; - int err; - - if (!list_is_singular(blocks)) - return -EINVAL; - - block = list_first_entry(blocks, - struct drm_buddy_block, - link); - - if (WARN_ON(!drm_buddy_block_is_allocated(block))) - return -EINVAL; - - if (new_size > drm_buddy_block_size(mm, block)) - return -EINVAL; - - if (!new_size || !IS_ALIGNED(new_size, mm->chunk_size)) - return -EINVAL; - - if (new_size == drm_buddy_block_size(mm, block)) - return 0; - - list_del(&block->link); - mark_free(mm, block); - mm->avail += drm_buddy_block_size(mm, block); - - /* Prevent recursively freeing this node */ - parent = block->parent; - block->parent = NULL; - - new_start = drm_buddy_block_offset(block); - list_add(&block->tmp_link, &dfs); - err = __alloc_range(mm, &dfs, new_start, new_size, blocks); - if (err) { - mark_allocated(block); - mm->avail -= drm_buddy_block_size(mm, block); - list_add(&block->link, blocks); - } - - block->parent = parent; - return err; -} -EXPORT_SYMBOL(kcl_drm_buddy_block_trim); - -/** - * drm_buddy_alloc_blocks - allocate power-of-two blocks - * - * @mm: DRM buddy manager to allocate from - * @start: start of the allowed range for this block - * @end: end of the allowed range for this block - * @size: size of the allocation - * @min_page_size: alignment of the allocation - * @blocks: output list head to add allocated blocks - * @flags: DRM_BUDDY_*_ALLOCATION flags - * - * alloc_range_bias() called on range limitations, which traverses - * the tree and returns the desired block. - * - * alloc_from_freelist() called when *no* range restrictions - * are enforced, which picks the block from the freelist. - * - * Returns: - * 0 on success, error code on failure. - */ -int kcl_drm_buddy_alloc_blocks(struct drm_buddy *mm, - u64 start, u64 end, u64 size, - u64 min_page_size, - struct list_head *blocks, - unsigned long flags) -{ - struct drm_buddy_block *block = NULL; - unsigned int min_order, order; - unsigned long pages; - LIST_HEAD(allocated); - int err; - - if (size < mm->chunk_size) - return -EINVAL; - - if (min_page_size < mm->chunk_size) - return -EINVAL; - - if (!is_power_of_2(min_page_size)) - return -EINVAL; - - if (!IS_ALIGNED(start | end | size, mm->chunk_size)) - return -EINVAL; - - if (end > mm->size) - return -EINVAL; - - if (range_overflows(start, size, mm->size)) - return -EINVAL; - - /* Actual range allocation */ - if (start + size == end) - return __drm_buddy_alloc_range(mm, start, size, blocks); - - if (!IS_ALIGNED(size, min_page_size)) - return -EINVAL; - - pages = size >> ilog2(mm->chunk_size); - order = fls(pages) - 1; - min_order = ilog2(min_page_size) - ilog2(mm->chunk_size); - - do { - order = min(order, (unsigned int)fls(pages) - 1); - BUG_ON(order > mm->max_order); - BUG_ON(order < min_order); - - do { - if (flags & DRM_BUDDY_RANGE_ALLOCATION) - /* Allocate traversing within the range */ - block = alloc_range_bias(mm, start, end, order); - else - /* Allocate from freelist */ - block = alloc_from_freelist(mm, order, flags); - - if (!IS_ERR(block)) - break; - - if (order-- == min_order) { - err = -ENOSPC; - goto err_free; - } - } while (1); - - mark_allocated(block); - mm->avail -= drm_buddy_block_size(mm, block); - //kmemleak_update_trace(block); - list_add_tail(&block->link, &allocated); - - pages -= BIT(order); - - if (!pages) - break; - } while (1); - - list_splice_tail(&allocated, blocks); - return 0; - -err_free: - drm_buddy_free_list(mm, &allocated); - return err; -} -EXPORT_SYMBOL(kcl_drm_buddy_alloc_blocks); - -/** - * drm_buddy_block_print - print block information - * - * @mm: DRM buddy manager - * @block: DRM buddy block - * @p: DRM printer to use - */ -void kcl_drm_buddy_block_print(struct drm_buddy *mm, - struct drm_buddy_block *block, - struct drm_printer *p) -{ - u64 start = drm_buddy_block_offset(block); - u64 size = drm_buddy_block_size(mm, block); - - drm_printf(p, "%#018llx-%#018llx: %llu\n", start, start + size, size); -} -EXPORT_SYMBOL(kcl_drm_buddy_block_print); - -/** - * drm_buddy_print - print allocator state - * - * @mm: DRM buddy manager - * @p: DRM printer to use - */ -void kcl_drm_buddy_print(struct drm_buddy *mm, struct drm_printer *p) -{ - int order; - - drm_printf(p, "chunk_size: %lluKiB, total: %lluMiB, free: %lluMiB\n", - mm->chunk_size >> 10, mm->size >> 20, mm->avail >> 20); - - for (order = mm->max_order; order >= 0; order--) { - struct drm_buddy_block *block; - u64 count = 0, free; - - list_for_each_entry(block, &mm->free_list[order], link) { - BUG_ON(!drm_buddy_block_is_free(block)); - count++; - } - - drm_printf(p, "order-%d ", order); - - free = count * (mm->chunk_size << order); - if (free < SZ_1M) - drm_printf(p, "free: %lluKiB", free >> 10); - else - drm_printf(p, "free: %lluMiB", free >> 20); - - drm_printf(p, ", pages: %llu\n", count); - } -} -EXPORT_SYMBOL(kcl_drm_buddy_print); - -void amdkcl_drm_buddy_module_exit(void) -{ - kmem_cache_destroy(slab_blocks); -} - -int amdkcl_drm_buddy_module_init(void) -{ - slab_blocks = KMEM_CACHE(drm_buddy_block, 0); - if (!slab_blocks) - return -ENOMEM; - - return 0; -} - -#endif /* HAVE_DRM_DRM_BUDDY_H */ \ No newline at end of file diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c index a98196918c9f9..3e01ddf3f82a6 100644 --- a/drivers/gpu/drm/amd/amdkcl/main.c +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -16,11 +16,6 @@ extern void amdkcl_sched_init(void); extern void amdkcl_numa_init(void); extern void amdkcl_workqueue_init(void); -#ifndef HAVE_DRM_DRM_BUDDY_H -extern int amdkcl_drm_buddy_module_init(void); -extern void amdkcl_drm_buddy_module_exit(void); -#endif - int __init amdkcl_init(void) { amdkcl_symbol_init(); @@ -36,9 +31,6 @@ int __init amdkcl_init(void) amdkcl_sched_init(); amdkcl_numa_init(); amdkcl_workqueue_init(); -#ifndef HAVE_DRM_DRM_BUDDY_H - amdkcl_drm_buddy_module_init(); -#endif return 0; } @@ -46,9 +38,7 @@ module_init(amdkcl_init); void __exit amdkcl_exit(void) { -#ifndef HAVE_DRM_DRM_BUDDY_H - amdkcl_drm_buddy_module_exit(); -#endif + } module_exit(amdkcl_exit); diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 475cc32dcc47c..b57813353fe7b 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -98,6 +98,5 @@ #include #include #include -#include #include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/header/drm/drm_buddy.h b/include/kcl/header/drm/drm_buddy.h deleted file mode 100644 index 37aa64b07a8e6..0000000000000 --- a/include/kcl/header/drm/drm_buddy.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -#ifndef _KCL_HEADER_DRM_BUDDY_H_H_ -#define _KCL_HEADER_DRM_BUDDY_H_H_ - -#ifdef HAVE_DRM_DRM_BUDDY_H -#include_next -#else -#include -#endif - -#endif diff --git a/include/kcl/kcl_drm_buddy.h b/include/kcl/kcl_drm_buddy.h deleted file mode 100644 index 4db95edb25369..0000000000000 --- a/include/kcl/kcl_drm_buddy.h +++ /dev/null @@ -1,171 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -/* - * Copyright © 2021 Intel Corporation - */ -#ifndef __KCL_KCL_DRM_BUDDY_H__ -#define __KCL_KCL_DRM_BUDDY_H__ - -#ifdef HAVE_DRM_DRM_BUDDY_H -#include -#else -#include -#include -#include -#include -#include -#include - -#define range_overflows(start, size, max) ({ \ - typeof(start) start__ = (start); \ - typeof(size) size__ = (size); \ - typeof(max) max__ = (max); \ - (void)(&start__ == &size__); \ - (void)(&start__ == &max__); \ - start__ >= max__ || size__ > max__ - start__; \ -}) - -#define DRM_BUDDY_RANGE_ALLOCATION (1 << 0) -#define DRM_BUDDY_TOPDOWN_ALLOCATION (1 << 1) - -struct drm_buddy_block { -#define DRM_BUDDY_HEADER_OFFSET GENMASK_ULL(63, 12) -#define DRM_BUDDY_HEADER_STATE GENMASK_ULL(11, 10) -#define DRM_BUDDY_ALLOCATED (1 << 10) -#define DRM_BUDDY_FREE (2 << 10) -#define DRM_BUDDY_SPLIT (3 << 10) -/* Free to be used, if needed in the future */ -#define DRM_BUDDY_HEADER_UNUSED GENMASK_ULL(9, 6) -#define DRM_BUDDY_HEADER_ORDER GENMASK_ULL(5, 0) - u64 header; - - struct drm_buddy_block *left; - struct drm_buddy_block *right; - struct drm_buddy_block *parent; - - void *private; /* owned by creator */ - - /* - * While the block is allocated by the user through drm_buddy_alloc*, - * the user has ownership of the link, for example to maintain within - * a list, if so desired. As soon as the block is freed with - * drm_buddy_free* ownership is given back to the mm. - */ - struct list_head link; - struct list_head tmp_link; -}; - -/* Order-zero must be at least PAGE_SIZE */ -#define DRM_BUDDY_MAX_ORDER (63 - PAGE_SHIFT) - -/* - * Binary Buddy System. - * - * Locking should be handled by the user, a simple mutex around - * drm_buddy_alloc* and drm_buddy_free* should suffice. - */ -struct drm_buddy { - /* Maintain a free list for each order. */ - struct list_head *free_list; - - /* - * Maintain explicit binary tree(s) to track the allocation of the - * address space. This gives us a simple way of finding a buddy block - * and performing the potentially recursive merge step when freeing a - * block. Nodes are either allocated or free, in which case they will - * also exist on the respective free list. - */ - struct drm_buddy_block **roots; - - /* - * Anything from here is public, and remains static for the lifetime of - * the mm. Everything above is considered do-not-touch. - */ - unsigned int n_roots; - unsigned int max_order; - - /* Must be at least PAGE_SIZE */ - u64 chunk_size; - u64 size; - u64 avail; -}; - -static inline u64 -drm_buddy_block_offset(struct drm_buddy_block *block) -{ - return block->header & DRM_BUDDY_HEADER_OFFSET; -} - -static inline unsigned int -drm_buddy_block_order(struct drm_buddy_block *block) -{ - return block->header & DRM_BUDDY_HEADER_ORDER; -} - -static inline unsigned int -drm_buddy_block_state(struct drm_buddy_block *block) -{ - return block->header & DRM_BUDDY_HEADER_STATE; -} - -static inline bool -drm_buddy_block_is_allocated(struct drm_buddy_block *block) -{ - return drm_buddy_block_state(block) == DRM_BUDDY_ALLOCATED; -} - -static inline bool -drm_buddy_block_is_free(struct drm_buddy_block *block) -{ - return drm_buddy_block_state(block) == DRM_BUDDY_FREE; -} - -static inline bool -drm_buddy_block_is_split(struct drm_buddy_block *block) -{ - return drm_buddy_block_state(block) == DRM_BUDDY_SPLIT; -} - -static inline u64 -drm_buddy_block_size(struct drm_buddy *mm, - struct drm_buddy_block *block) -{ - return mm->chunk_size << drm_buddy_block_order(block); -} - -int kcl_drm_buddy_init(struct drm_buddy *mm, u64 size, u64 chunk_size); - -void kcl_drm_buddy_fini(struct drm_buddy *mm); - -struct drm_buddy_block * -kcl_drm_get_buddy(struct drm_buddy_block *block); - -int kcl_drm_buddy_alloc_blocks(struct drm_buddy *mm, - u64 start, u64 end, u64 size, - u64 min_page_size, - struct list_head *blocks, - unsigned long flags); - -int kcl_drm_buddy_block_trim(struct drm_buddy *mm, - u64 new_size, - struct list_head *blocks); - -void kcl_drm_buddy_free_block(struct drm_buddy *mm, struct drm_buddy_block *block); - -void kcl_drm_buddy_free_list(struct drm_buddy *mm, struct list_head *objects); - -void kcl_drm_buddy_print(struct drm_buddy *mm, struct drm_printer *p); -void kcl_drm_buddy_block_print(struct drm_buddy *mm, - struct drm_buddy_block *block, - struct drm_printer *p); - -#define drm_buddy_print kcl_drm_buddy_print -#define drm_buddy_block_print kcl_drm_buddy_block_print -#define drm_buddy_alloc_blocks kcl_drm_buddy_alloc_blocks -#define drm_buddy_block_trim kcl_drm_buddy_block_trim -#define drm_buddy_free_list kcl_drm_buddy_free_list -#define drm_buddy_free_block kcl_drm_buddy_free_block -#define drm_get_buddy kcl_drm_get_buddy -#define drm_buddy_fini kcl_drm_buddy_fini -#define drm_buddy_init kcl_drm_buddy_init -#endif /* HAVE_DRM_DRM_BUDDY_H */ -#endif /* __KCL_KCL_DRM_BUDDY_H__ */ From f247df1dcddcc46faec8e62ed72dc9c92664de10 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Tue, 1 Nov 2022 17:40:14 -0400 Subject: [PATCH 0809/1868] drm/amdgpu: Fix in-tree build amdgpu_vram_mgr depents on DRM_BUDDY. Add the dependency in Kconfig to fix the in-tree build. Signed-off-by: Felix Kuehling Acked-by: Alex Deucher Tested-by: Philip Yang --- drivers/gpu/drm/amd/amdgpu/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/Kconfig b/drivers/gpu/drm/amd/amdgpu/Kconfig index 35c20e373b01b..56cac2b812a7a 100644 --- a/drivers/gpu/drm/amd/amdgpu/Kconfig +++ b/drivers/gpu/drm/amd/amdgpu/Kconfig @@ -5,6 +5,7 @@ config DRM_AMDGPU depends on DRM && PCI && MMU depends on !UML select FW_LOADER + select DRM_BUDDY select DRM_DISPLAY_DP_HELPER select DRM_DISPLAY_HDMI_HELPER select DRM_DISPLAY_HDCP_HELPER From f63d37206531f395ed5e75f8673f74083cb67008 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 8 Nov 2022 12:59:15 +0800 Subject: [PATCH 0810/1868] drm/amdkcl: Fix reference counting error of dma_fence_chain that causing memory leak In the code path of creating a new dma_fence_chain object, the dma_fence_chain_init() function has initialized the reference count. The additional incorrect dma_fence_get(fence) call will increase the reference count from 1 to 2. This will lead to memory leak of dma_fence_chain objects. This fix patch "be5685d2b0f9 drm/amdkcl: join multiple exclusive fences instead of overwriting old fence" Signed-off-by: Leslie Shi Reviewed-by: Guchun Chen Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c b/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c index 67f67bcd4e2b4..8edf3fccac3e9 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c @@ -367,9 +367,10 @@ static void dma_resv_add_excl_fence(struct dma_resv *obj, dma_fence_chain_init(chain, dma_fence_get(old_fence), dma_fence_get(fence), 1); fence = &chain->base; } + } else { + dma_fence_get(fence); } - dma_fence_get(fence); write_seqcount_begin(&obj->seq); /* write_seqcount_begin provides the necessary memory barrier */ From 1b7495fba53e03849ba0f77c71cbbd740479ce8c Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Tue, 8 Nov 2022 14:41:20 +0800 Subject: [PATCH 0811/1868] drm/amdkcl: Wrap the code under macro CONFIG_DRM_AMD_DC_DCN Wrap the code under macro CONFIG_DRM_AMD_DC_DCN to fix the compile error. Signed-off-by: Ma Jun Reviewed-by: Leslie Shi Change-Id: I3488aa2fe6d706f69e8741e1cb908cdda0e02bf4 --- drivers/gpu/drm/amd/display/dc/core/dc.c | 2 ++ drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index b362393c140f5..dcbb43d91837e 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1283,10 +1283,12 @@ static void disable_dangling_plane(struct dc *dc, struct dc_state *context) * The OTG is set to disable on falling edge of VUPDATE so the plane disable * will still get it's double buffer update. */ +#ifdef CONFIG_DRM_AMD_DC_DCN if (is_phantom) { if (tg->funcs->disable_phantom_crtc) tg->funcs->disable_phantom_crtc(tg); } +#endif } } diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c index 58e7084a3380f..56434a0859bbb 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c @@ -319,7 +319,9 @@ static struct timing_generator_funcs dcn32_tg_funcs = { .enable_crtc = optc32_enable_crtc, .disable_crtc = optc32_disable_crtc, .phantom_crtc_post_enable = optc32_phantom_crtc_post_enable, +#ifdef CONFIG_DRM_AMD_DC_DCN .disable_phantom_crtc = optc32_disable_phantom_otg, +#endif /* used by enable_timing_synchronization. Not need for FPGA */ .is_counter_moving = optc1_is_counter_moving, .get_position = optc1_get_position, From d4738bc685c68a1b4765deb01428a23e872587b0 Mon Sep 17 00:00:00 2001 From: Jeremy Newton Date: Tue, 15 Nov 2022 17:50:11 -0500 Subject: [PATCH 0812/1868] Disable weak module updates This is not supported on some OS, such as RHEL and Fedora, so we should disable it since it's harmless to disable for all OS. Signed-off-by: Jeremy Newton Reviewed-by: Slava Grigorev --- drivers/gpu/drm/amd/dkms/dkms.conf | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/dkms.conf b/drivers/gpu/drm/amd/dkms/dkms.conf index caa34f979ef96..bf06588ea6b9c 100644 --- a/drivers/gpu/drm/amd/dkms/dkms.conf +++ b/drivers/gpu/drm/amd/dkms/dkms.conf @@ -2,6 +2,8 @@ PACKAGE_NAME="amdgpu" PACKAGE_VERSION="1.0" AUTOINSTALL="yes" PRE_BUILD="amd/dkms/pre-build.sh $kernelver" +# not all OS supports weak module updates +NO_WEAK_MODULES="yes" # not work with RHEL DKMS #MODULES_CONF[0]="blacklist radeon" From 10a84f2814ab65ff3c13525fba6df6a4916f1b79 Mon Sep 17 00:00:00 2001 From: Jonathan Kim Date: Mon, 29 Aug 2022 22:28:18 -0400 Subject: [PATCH 0813/1868] drm/amdkfd: disable cooperative launch in gfx11 debug mode Since SA1 must be disabled during GFX11 debug mode, cooperative launch may shader hang on an indefinite barrier wait due to assymetrically enabled SEs. Prevent the debugger from attaching to a GWS using process or having the attached process create GWS using queues. Signed-off-by: Jonathan Kim Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_device.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index e40f40d1a2259..3a0f6880d0030 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -580,7 +580,9 @@ static int kfd_gws_init(struct kfd_node *node) (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 0) && kfd->mec2_fw_version < 0x1b6) || (KFD_GC_VERSION(kfd) == IP_VERSION(9, 4, 1) - && kfd->mec2_fw_version < 0x30)) + && kfd->mec2_fw_version < 0x30) || + (KFD_GC_VERSION(kfd) >= IP_VERSION(11, 0, 0) && + KFD_GC_VERSION(kfd) < IP_VERSION(12, 0, 0))) kfd->gws_debug_workaround = true; return ret; From 3fa0b6fe5cb937fe3c2f55f6528ec35b95175b74 Mon Sep 17 00:00:00 2001 From: Bob zhou Date: Mon, 14 Nov 2022 15:34:16 +0800 Subject: [PATCH 0814/1868] drm/amdkcl: Test whether drm_mode_init() is available Signed-off-by: Bob zhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/kcl_drm_modes.c | 12 ++++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/drm-mode-init.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_modes.h | 4 ++++ 5 files changed, 36 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-mode-init.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_modes.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_modes.c index bf57f999e4fc2..e01b01bd4ae09 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_modes.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_modes.c @@ -39,3 +39,15 @@ amdkcl_dummy_symbol(drm_mode_is_420_only, bool, return false, amdkcl_dummy_symbol(drm_mode_is_420_also, bool, return false, const struct drm_display_info *display, const struct drm_display_mode *mode) #endif + +#ifndef HAVE_DRM_MODE_INIT +void drm_mode_init(struct drm_display_mode *dst, const struct drm_display_mode *src) +{ + struct list_head head = dst->head; + + memset(dst, 0, sizeof(*dst)); + *dst = *src; + dst->head = head; +} +EXPORT_SYMBOL(drm_mode_init); +#endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 6b05c9524ab2e..647f60e742492 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -683,6 +683,9 @@ /* drm_mode_is_420_xxx() is available */ #define HAVE_DRM_MODE_IS_420_XXX 1 +/* drm_mode_init() is available */ +#define HAVE_DRM_MODE_INTT 1 + /* enum drm_mode_subconnector is available */ /* #undef HAVE_DRM_MODE_SUBCONNECTOR_ENUM */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-mode-init.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-mode-init.m4 new file mode 100644 index 0000000000000..9a220e320f721 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-mode-init.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.17-rc2-403-g2d3eec897033 +dnl # drm: Add drm_mode_init() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_MODE_INIT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_mode_init(NULL, NULL); + ], [drm_mode_init], [drivers/gpu/drm/drm_modes.c], [ + AC_DEFINE(HAVE_DRM_MODE_INIT, 1, + [drm_mode_init() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index e997936f7f6b4..2d78a1d0f6188 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -106,6 +106,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DRIVER_RELEASE AC_AMDGPU_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER AC_AMDGPU_DRM_MODE_IS_420_XXX + AC_AMDGPU_DRM_MODE_INIT AC_AMDGPU_DRM_FRAMEBUFFER_FORMAT AC_AMDGPU_STRSCPY AC_AMDGPU_DRM_DP_MST_TOPOLOGY diff --git a/include/kcl/kcl_drm_modes.h b/include/kcl/kcl_drm_modes.h index c47d691ca6e7a..efd58502aad15 100644 --- a/include/kcl/kcl_drm_modes.h +++ b/include/kcl/kcl_drm_modes.h @@ -36,4 +36,8 @@ bool drm_mode_is_420_also(const struct drm_display_info *display, const struct drm_display_mode *mode); #endif +#ifndef HAVE_DRM_MODE_INIT +void drm_mode_init(struct drm_display_mode *dst, const struct drm_display_mode *src); +#endif + #endif From fe18815de41efaebbbda4afe4d6ef20202de8c45 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 23 Nov 2022 19:35:54 +0800 Subject: [PATCH 0815/1868] drm/amdkcl: Check if DECLARE_DYNDBG_CLASSMAP is defined Check if DECLARE_DYNDBG_CLASSMAP is defined. This macro definition is introduced in dyndbg: add DECLARE_DYNDBG_CLASSMAP macro Signed-off-by: Ma Jun Change-Id: I4877b8610c0134b96183697a047eeae3d4ffe4da --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_dynamic_debug.h | 64 +++++++++++++++++++++++++ 2 files changed, 65 insertions(+) create mode 100644 include/kcl/kcl_dynamic_debug.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index b57813353fe7b..685614933b096 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -99,4 +99,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_dynamic_debug.h b/include/kcl/kcl_dynamic_debug.h new file mode 100644 index 0000000000000..6c6f7296eba94 --- /dev/null +++ b/include/kcl/kcl_dynamic_debug.h @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef AMDKCL_DYNAMIC_DEBUG_H +#define AMDKCL_DYNAMIC_DEBUG_H + +#ifndef DECLARE_DYNDBG_CLASSMAP +enum class_map_type { + DD_CLASS_TYPE_DISJOINT_BITS, + /** + * DD_CLASS_TYPE_DISJOINT_BITS: classes are independent, one per bit. + * expecting hex input. Built for drm.debug, basis for other types. + */ + DD_CLASS_TYPE_LEVEL_NUM, + /** + * DD_CLASS_TYPE_LEVEL_NUM: input is numeric level, 0-N. + * N turns on just bits N-1 .. 0, so N=0 turns all bits off. + */ + DD_CLASS_TYPE_DISJOINT_NAMES, + /** + * DD_CLASS_TYPE_DISJOINT_NAMES: input is a CSV of [+-]CLASS_NAMES, + * classes are independent, like _DISJOINT_BITS. + */ + DD_CLASS_TYPE_LEVEL_NAMES, + /** + * DD_CLASS_TYPE_LEVEL_NAMES: input is a CSV of [+-]CLASS_NAMES, + * intended for names like: INFO,DEBUG,TRACE, with a module prefix + * avoid EMERG,ALERT,CRIT,ERR,WARNING: they're not debug + */ +}; + +struct ddebug_class_map { + struct list_head link; + struct module *mod; + const char *mod_name; /* needed for builtins */ + const char **class_names; + const int length; + const int base; /* index of 1st .class_id, allows split/shared space */ + enum class_map_type map_type; +}; + +/** + * DECLARE_DYNDBG_CLASSMAP - declare classnames known by a module + * @_var: a struct ddebug_class_map, passed to module_param_cb + * @_type: enum class_map_type, chooses bits/verbose, numeric/symbolic + * @_base: offset of 1st class-name. splits .class_id space + * @classes: class-names used to control class'd prdbgs + */ +#define DECLARE_DYNDBG_CLASSMAP(_var, _maptype, _base, ...) \ + static const char *_var##_classnames[] = { __VA_ARGS__ }; \ + static struct ddebug_class_map __aligned(8) __used \ + __section("__dyndbg_classes") _var = { \ + .mod = THIS_MODULE, \ + .mod_name = KBUILD_MODNAME, \ + .base = _base, \ + .map_type = _maptype, \ + .length = NUM_TYPE_ARGS(char*, __VA_ARGS__), \ + .class_names = _var##_classnames, \ + } +#define NUM_TYPE_ARGS(eltype, ...) \ + (sizeof((eltype[]){__VA_ARGS__}) / sizeof(eltype)) + +#endif + +#endif /* AMDKCL_DYNAMIC_DEBUG_H */ From 8b0701f52ceef88e76165a754946844dc36bcb9e Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 23 Nov 2022 20:12:05 +0800 Subject: [PATCH 0816/1868] drm/amdkcl: Check if acpi_video_backlight_use_native() is implemented check if acpi_video_backlight_use_native is implemented Signed-off-by: Ma Jun Change-Id: I3c1fd6875436808205d7f6e6dbcf7d59a4722d3a --- .../gpu/drm/amd/amdgpu/atombios_encoders.c | 2 ++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../gpu/drm/amd/dkms/m4/acpi-video-funcs.m4 | 22 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 28 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/acpi-video-funcs.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c index a15d80a896369..77090658fae3c 100644 --- a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c +++ b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c @@ -186,10 +186,12 @@ void amdgpu_atombios_encoder_init_backlight(struct amdgpu_encoder *amdgpu_encode if (!(adev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU)) goto register_acpi_backlight; +#ifdef HAVE_ACPI_VIDEO_BACKLIGHT_USE_NATIVE if (!acpi_video_backlight_use_native()) { drm_info(dev, "Skipping amdgpu atom DIG backlight registration\n"); goto register_acpi_backlight; } +#endif pdata = kmalloc(sizeof(struct amdgpu_backlight_privdata), GFP_KERNEL); if (!pdata) { diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 647f60e742492..b1b48ab97020e 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -15,6 +15,9 @@ /* struct acpi_srat_generic_affinity is available */ #define HAVE_ACPI_SRAT_GENERIC_AFFINITY 1 + +/* acpi_video_backlight_use_native() is available */ +#define HAVE_ACPI_VIDEO_BACKLIGHT_USE_NATIVE 1 /* whether AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES is defined */ #define HAVE_AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/acpi-video-funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/acpi-video-funcs.m4 new file mode 100644 index 0000000000000..69f2cc28f537c --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/acpi-video-funcs.m4 @@ -0,0 +1,22 @@ +dnl # +dnl # commit: v6.1-rc1-17-da11ef832972 +dnl # drm/amdgpu: Don't register backlight when another +dnl # backlight should be used (v3) + +AC_DEFUN([AC_AMDGPU_ACPI_VIDEO_BACKLIGHT_USE_NATIVE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + acpi_video_backlight_use_native(); + ], [ + AC_DEFINE(HAVE_ACPI_VIDEO_BACKLIGHT_USE_NATIVE, 1, + [acpi_video_backlight_use_native() is available]) + ]) + ]) +]) + + +AC_DEFUN([AC_AMDGPU_ACPI_VIDEO_FUNCS], [ + AC_AMDGPU_ACPI_VIDEO_BACKLIGHT_USE_NATIVE +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 2d78a1d0f6188..f9c7c1b81c856 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -220,6 +220,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_REGISTER_SHRINKER AC_AMDGPU_DRM_DP_MST_POST_PASSTHROUGH_AUX AC_AMDGPU_DRM_DP_MST_PORT_FULL_PBN + AC_AMDGPU_ACPI_VIDEO_FUNCS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From fec4c06c589bb80c2ca1a207b7512fa6e01dfed1 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 23 Nov 2022 20:28:02 +0800 Subject: [PATCH 0817/1868] drm/amdkcl: check if acpi_video_register_backlight() is implemented check if acpi_video_register_backlight() is implemented Signed-off-by: Ma Jun Change-Id: I3e3930f01cf382a84fe2c0366b865c75d34febe6 --- .../gpu/drm/amd/amdgpu/atombios_encoders.c | 2 ++ drivers/gpu/drm/amd/dkms/config/config.h | 4 ++++ .../gpu/drm/amd/dkms/m4/acpi-video-funcs.m4 | 19 +++++++++++++++++++ 3 files changed, 25 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c index 77090658fae3c..3ed9f74a2c49d 100644 --- a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c +++ b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c @@ -230,7 +230,9 @@ void amdgpu_atombios_encoder_init_backlight(struct amdgpu_encoder *amdgpu_encode register_acpi_backlight: /* Try registering an ACPI video backlight device instead. */ +#ifdef HAVE_ACPI_VIDEO_REGISTER_BACKLIGHT acpi_video_register_backlight(); +#endif } void diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index b1b48ab97020e..7a9f2e696dbd8 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -19,6 +19,10 @@ /* acpi_video_backlight_use_native() is available */ #define HAVE_ACPI_VIDEO_BACKLIGHT_USE_NATIVE 1 + +/* acpi_video_register_backlight() is available */ +#define HAVE_ACPI_VIDEO_REGISTER_BACKLIGHT 1 + /* whether AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES is defined */ #define HAVE_AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/acpi-video-funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/acpi-video-funcs.m4 index 69f2cc28f537c..d2a957a3c28a7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/acpi-video-funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/acpi-video-funcs.m4 @@ -16,7 +16,26 @@ AC_DEFUN([AC_AMDGPU_ACPI_VIDEO_BACKLIGHT_USE_NATIVE], [ ]) ]) +dnl # +dnl # commit: v6.1-rc1-161-c0f50c5de93b +dnl # drm/amdgpu: Register ACPI video backlight when +dnl # skipping amdgpu backlight registration + +AC_DEFUN([AC_AMDGPU_ACPI_VIDEO_REGISTER_BACKLIGHT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + acpi_video_register_backlight(); + ], [ + AC_DEFINE(HAVE_ACPI_VIDEO_REGISTER_BACKLIGHT, 1, + [acpi_video_register_backlight() is available]) + ]) + ]) +]) + AC_DEFUN([AC_AMDGPU_ACPI_VIDEO_FUNCS], [ AC_AMDGPU_ACPI_VIDEO_BACKLIGHT_USE_NATIVE + AC_AMDGPU_ACPI_VIDEO_REGISTER_BACKLIGHT ]) From 7aab81347d8284ea17185fc450516f4dcf4f050f Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 9 Jul 2024 10:49:51 +0800 Subject: [PATCH 0818/1868] drm/amdkcl: Check if DRM_PLANE_NO_SCALING is defined Check if DRM_PLANE_NO_SCALING is defined Signed-off-by: Ma Jun Change-Id: Iaa3041b8bf4765b992f57837bf8c7e69cf34a3f1 Signed-off-by: Asher Song --- include/kcl/kcl_drm_atomic_helper.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/kcl/kcl_drm_atomic_helper.h b/include/kcl/kcl_drm_atomic_helper.h index 208a5e9edf330..7bedeace08ad0 100644 --- a/include/kcl/kcl_drm_atomic_helper.h +++ b/include/kcl/kcl_drm_atomic_helper.h @@ -34,6 +34,11 @@ #include #include +/* drm/atomic-helper: Remove _HELPER_ infix from DRM_PLANE_HELPER_NO_SCALING */ +#ifndef DRM_PLANE_NO_SCALING +#define DRM_PLANE_NO_SCALING (1<<16) +#endif + /* * v4.19-rc1-206-ge267364a6e1b * drm/atomic: Initialise planes with opaque alpha values From 97d09533b5b110bc3e7f85f15eea6940d8bd1ea1 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 23 Nov 2022 20:47:11 +0800 Subject: [PATCH 0819/1868] drm/amdkcl: Remove redundant macro DRM_UT_STATE This macro is defined in enum class_map_type now. Signed-off-by: Ma Jun Change-Id: Iadbbab2a0abafb3a83b918537a56296e083a2f20 --- include/kcl/kcl_drm_print.h | 4 ---- 1 file changed, 4 deletions(-) diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index bba9e048cf699..80d51e8721236 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -125,10 +125,6 @@ void kcl_drm_err(const char *format, ...); #define HAVE_DRM_ERR_MACRO #endif /* drm_err */ -#if !defined(DRM_UT_STATE) -#define DRM_UT_STATE 0x40 -#endif - #if !defined(DRM_UT_VBL) #define DRM_UT_VBL 0x20 #endif From a9398a910b2e70cf7dca8ff13e7c72a6ddff277e Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 23 Nov 2022 20:49:42 +0800 Subject: [PATCH 0820/1868] drm/amdkcl: Wrap code under HAVE_ACPI_VIDEO_BACKLIGHT_USE_NATIVE Signed-off-by: Ma Jun Change-Id: Ia7819db796197c1c00ccfd848dfc8b84372e32b0 --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 5459fcde8e63d..e17cf439b861b 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4795,12 +4795,14 @@ amdgpu_dm_register_backlight_device(struct amdgpu_dm_connector *aconnector) if (aconnector->bl_idx == -1) return; +#ifdef HAVE_ACPI_VIDEO_BACKLIGHT_USE_NATIVE if (!acpi_video_backlight_use_native()) { drm_info(drm, "Skipping amdgpu DM backlight registration\n"); /* Try registering an ACPI video backlight device instead. */ acpi_video_register_backlight(); return; } +#endif amdgpu_acpi_get_backlight_caps(&caps); if (caps.caps_valid) { From b00c42422fb133d5a824e7c5085f4c0b4dee2cb3 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 24 Nov 2022 09:57:18 +0800 Subject: [PATCH 0821/1868] drm/amdkcl: Check if drm_plane_helper_destroy() is implemented Check if drm_plane_helper_destroy is implemented Signed-off-by: Ma Jun Change-Id: Iaed7658f55768048ea9534aaeed12dd4cba70e8a --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../drm/amd/dkms/m4/drm-plane-helper-funcs.m4 | 21 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_plane_helper.h | 15 +++++++++++++ 5 files changed, 41 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-plane-helper-funcs.m4 create mode 100644 include/kcl/kcl_drm_plane_helper.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 685614933b096..ca935a3ea4838 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -100,4 +100,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 7a9f2e696dbd8..2758d0ce3479d 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -705,6 +705,9 @@ /* drm_plane_helper_check_state is available */ /* #undef HAVE_DRM_PLANE_HELPER_CHECK_STATE */ +/* drm_plane_helper_destroy() is available */ +/* #undef HAVE_DRM_PLANE_HELPER_DESTROY */ + /* drm_plane_mask is available */ #define HAVE_DRM_PLANE_MASK 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-plane-helper-funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-plane-helper-funcs.m4 new file mode 100644 index 0000000000000..e4a2a7d627810 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-plane-helper-funcs.m4 @@ -0,0 +1,21 @@ +dnl # +dnl # commit: v6.1-rc1-27-30c637151cfa +dnl # drm/plane-helper: Export individual helpers +dnl # + +AC_DEFUN([AC_AMDGPU_DRM_PLANE_HELPER_DESTROY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_plane_helper_destroy(NULL); + ], [ + AC_DEFINE(HAVE_DRM_PLANE_HELPER_DESTROY, 1, + [drm_plane_helper_destroy() is available]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_DRM_PLANE_HELPER_FUNCS], [ + AC_AMDGPU_DRM_PLANE_HELPER_DESTROY +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index f9c7c1b81c856..c58b3c8f29e25 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -221,6 +221,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_POST_PASSTHROUGH_AUX AC_AMDGPU_DRM_DP_MST_PORT_FULL_PBN AC_AMDGPU_ACPI_VIDEO_FUNCS + AC_AMDGPU_DRM_PLANE_HELPER_FUNCS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_plane_helper.h b/include/kcl/kcl_drm_plane_helper.h new file mode 100644 index 0000000000000..d1bc40bcebb4d --- /dev/null +++ b/include/kcl/kcl_drm_plane_helper.h @@ -0,0 +1,15 @@ +#ifndef AMDKCL_DRM_PLANE_HELPER_H +#define AMDKCL_DRM_PLANE_HELPER_H + +#include + +#ifndef HAVE_DRM_PLANE_HELPER_DESTROY +static void kcl_drm_plane_helper_destroy(struct drm_plane *plane) +{ + drm_plane_cleanup(plane); + kfree(plane); +} + +#define drm_plane_helper_destroy kcl_drm_plane_helper_destroy +#endif +#endif \ No newline at end of file From 10739a0d5fd5237057732dba0a17ce39ad8e530a Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 24 Nov 2022 10:11:25 +0800 Subject: [PATCH 0822/1868] drm/amdkcl: Check if display_info->luminance_range is defined check if display_info->luminance_range is defined Signed-off-by: Ma Jun Change-Id: I39fab65c8347df82fd857b6aa8a45bd50002244b --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../gpu/drm/amd/dkms/m4/drm-display-info.m4 | 20 +++++++++++++++++++ 3 files changed, 27 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index e17cf439b861b..dd0a393ce0593 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3457,7 +3457,9 @@ static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector) struct amdgpu_dm_backlight_caps *caps; struct drm_connector *conn_base; struct amdgpu_device *adev; +#ifdef HAVE_DRM_DISPLAY_INFO_LUMINANCE_RANGE struct drm_luminance_range_info *luminance_range; +#endif if (aconnector->bl_idx == -1 || aconnector->dc_link->connector_signal != SIGNAL_TYPE_EDP) @@ -3483,6 +3485,7 @@ static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector) else if (amdgpu_backlight == 1) caps->aux_support = true; +#ifdef HAVE_DRM_DISPLAY_INFO_LUMINANCE_RANGE luminance_range = &conn_base->display_info.luminance_range; if (luminance_range->max_luminance) { @@ -3492,6 +3495,7 @@ static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector) caps->aux_min_input_signal = 0; caps->aux_max_input_signal = 512; } +#endif } #endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 2758d0ce3479d..4a6a44e1eb172 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -361,6 +361,9 @@ /* struct drm_display_info has monitor_range member */ #define HAVE_DRM_DISPLAY_INFO_MONITOR_RANGE 1 +/* display_info->luminance_range is available */ +/* #undef HAVE_DRM_DISPLAY_INFO_LUMINANCE_RANGE */ + /* display_info->max_dsc_bpp is available */ /* #undef HAVE_DRM_DISPLAY_INFO_MAX_DSC_BPP */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-display-info.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-display-info.m4 index e498f3bc94867..f72df7f1ac808 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-display-info.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-display-info.m4 @@ -54,8 +54,28 @@ AC_DEFUN([AC_AMDGPU_DRM_DISPLAY_INFO_MAX_DSC_BPP], [ ]) ]) +dnl # +dnl # commit v6.1-rc1~27-a61bb3422e8d +dnl # drm/amdgpu_dm: Rely on split out luminance calculation function +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DISPLAY_INFO_LUMINANCE_RANGE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_display_info *display_info = NULL; + display_info->luminance_range=NULL; + ],[ + AC_DEFINE(HAVE_DRM_DISPLAY_INFO_LUMINANCE_RANGE, 1, + [display_info->luminance_range is available]) + ]) + ]) +]) + + AC_DEFUN([AC_AMDGPU_DRM_DISPLAY_INFO], [ AC_AMDGPU_DRM_DISPLAY_INFO_EDID_HDMI_RGB444_DC_MODES AC_AMDGPU_DRM_DISPLAY_INFO_MONITOR_RANGE AC_AMDGPU_DRM_DISPLAY_INFO_MAX_DSC_BPP + AC_AMDGPU_DRM_DISPLAY_INFO_LUMINANCE_RANGE ]) From 5ffd317a8594fca8b3fca42f002136e30dc4241a Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 24 Nov 2022 11:09:31 +0800 Subject: [PATCH 0823/1868] drm/amdkcl: Rename the drm-dp-atomic-find-vcpi-slots.m4 Rename drm-dp-atomic-find-vcpi-slots.m4 to drm-dp-atomic-funcs.m4 for better compatability Signed-off-by: Ma Jun Change-Id: I1bda63ad4526270fd0850801a10d969a621946fd --- ...rm-dp-atomic-find-vcpi-slots.m4 => drm-dp-atomic-funcs.m4} | 4 ++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) rename drivers/gpu/drm/amd/dkms/m4/{drm-dp-atomic-find-vcpi-slots.m4 => drm-dp-atomic-funcs.m4} (94%) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-find-vcpi-slots.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 similarity index 94% rename from drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-find-vcpi-slots.m4 rename to drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 index 10cfe8e436f12..336e89b2a2874 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-find-vcpi-slots.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 @@ -43,3 +43,7 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS], [ ]) ]) ]) + +AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FUNCS], [ + AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index c58b3c8f29e25..29e7e449e1542 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -75,7 +75,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS AC_AMDGPU_DRM_CONNECTOR_INIT_WITH_DDC AC_AMDGPU_DRM_DP_CALC_PBN_MODE - AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS + AC_AMDGPU_DRM_DP_ATOMIC_FUNCS AC_AMDGPU_DRM_DP_SEND_REAL_EDID_CHECKSUM AC_AMDGPU_DRM_DP_CEC_CORRELATION_FUNCTIONS AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_RESUME From e73ab9c434c7e7fc37f564d40e84dfcbb7f35b17 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 24 Nov 2022 11:17:26 +0800 Subject: [PATCH 0824/1868] drm/amdkcl: Check and implement the drm_dp_atomic_find_time_slots() Check and implement the drm_dp_atomic_find_time_slots() func Signed-off-by: Ma Jun Change-Id: I5fc1dd70ab3bbf0f62586136ccd999ef52606956 --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 | 19 +++++++++++++++++++ 2 files changed, 22 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 4a6a44e1eb172..54a5811fa3821 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -367,6 +367,9 @@ /* display_info->max_dsc_bpp is available */ /* #undef HAVE_DRM_DISPLAY_INFO_MAX_DSC_BPP */ +/* drm_dp_atomic_find_time_slots() is available */ +/* #undef HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS */ + /* drm_dp_atomic_find_vcpi_slots() is available */ #define HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 index 336e89b2a2874..9f766ab7f8fc1 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 @@ -44,6 +44,25 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS], [ ]) ]) +dnl # +dnl # commit v6.1-rc1~27-df78f7f660cd +dnl # drm/display/dp_mst: Call them time slots, not VCPI slots +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FIND_TIME_SLOTS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + int ret; + ret = drm_dp_atomic_find_time_slots(NULL, NULL, NULL, 0, 0); + ],[ + AC_DEFINE(HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS, 1, + [drm_dp_atomic_find_time_slots() is available]) + ]) + ]) +]) + AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FUNCS], [ AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS + AC_AMDGPU_DRM_DP_ATOMIC_FIND_TIME_SLOTS ]) From cd37ad5c1ebe985afe043c62f0f554d1eb28783d Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 24 Nov 2022 12:41:17 +0800 Subject: [PATCH 0825/1868] drm/amdkcl: Implement the func drm_dp_atomic_find_time_slots() Signed-off-by: Ma Jun Change-Id: I4c07fabde6050973e25c0516166bc0e6ac256514 --- .../kcl/backport/kcl_drm_dp_mst_helper_backport.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h index 9be8ef18696a1..6a5e6961228bb 100644 --- a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h +++ b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h @@ -65,6 +65,18 @@ int _kcl_drm_dp_atomic_find_vcpi_slots(struct drm_atomic_state *state, #endif /* HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS_5ARGS */ #endif /* HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS */ +#if !defined(HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS) +static inline +int _kcl_drm_dp_atomic_find_time_slots(struct drm_atomic_state *state, + struct drm_dp_mst_topology_mgr *mgr, + struct drm_dp_mst_port *port, int pbn, + int pbn_div) +{ + return 0; +} +#define drm_dp_atomic_find_time_slots _kcl_drm_dp_atomic_find_time_slots +#endif + #ifndef HAVE_DRM_DP_MST_TOPOLOGY_MGR_RESUME_2ARGS static inline int _kcl_drm_dp_mst_topology_mgr_resume(struct drm_dp_mst_topology_mgr *mgr, From c25a7c7a17ff39d1769ade66fcc9c53617f2f9e1 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 24 Nov 2022 12:51:30 +0800 Subject: [PATCH 0826/1868] drm/amdkcl: Check if drm_dp_mst_atomic_setup_commit() is available Check if drm_dp_mst_atomic_setup_commit() is available Signed-off-by: Ma Jun Change-Id: I5653a9e25f19242d7b53c905efd1a92666b400a5 --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 | 20 +++++++++++++++++++ 3 files changed, 25 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index dd0a393ce0593..ba334a051c2dc 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3447,7 +3447,9 @@ static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = { #ifdef HAVE_DRM_MODE_CONFIG_HELPER_PRIVATE static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = { .atomic_commit_tail = amdgpu_dm_atomic_commit_tail, +#ifdef HAVE_DRM_DP_ATOMIC_SETUP_COMMIT .atomic_commit_setup = drm_dp_mst_atomic_setup_commit, +#endif }; #endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 54a5811fa3821..211498db8c115 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -370,6 +370,9 @@ /* drm_dp_atomic_find_time_slots() is available */ /* #undef HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS */ +/* drm_dp_mst_atomic_setup_commit() is available */ +/* #undef HAVE_DRM_DP_ATOMIC_SETUP_COMMIT */ + /* drm_dp_atomic_find_vcpi_slots() is available */ #define HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 index 9f766ab7f8fc1..0e5b9a432aa01 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 @@ -62,7 +62,27 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FIND_TIME_SLOTS], [ ]) ]) +dnl # +dnl # commit v6.1-rc1~27-a5c2c0d164e9 +dnl # drm/display/dp_mst: Add nonblocking helpers for DP MST +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_SETUP_COMMIT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + int ret; + ret = drm_dp_mst_atomic_setup_commit(NULL); + ],[ + AC_DEFINE(HAVE_DRM_DP_ATOMIC_SETUP_COMMIT, 1, + [drm_dp_mst_atomic_setup_commit() is available]) + ]) + ]) +]) + + AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FUNCS], [ AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS AC_AMDGPU_DRM_DP_ATOMIC_FIND_TIME_SLOTS + AC_AMDGPU_DRM_DP_ATOMIC_SETUP_COMMIT ]) From 70743f4fa64bb0611502e6e7ad9770c9d14c659d Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 24 Nov 2022 13:00:44 +0800 Subject: [PATCH 0827/1868] drm/amdkcl: Check if drm_dp_mst_atomic_wait_for_dependencies() is available Check if drm_dp_mst_atomic_wait_for_dependencies() is available Signed-off-by: Ma Jun Change-Id: Ibcfd90165754d5d8a0abbbaba850e5567e39bab4 --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 | 21 +++++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 211498db8c115..8804528e63739 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -373,6 +373,9 @@ /* drm_dp_mst_atomic_setup_commit() is available */ /* #undef HAVE_DRM_DP_ATOMIC_SETUP_COMMIT */ +/* drm_dp_mst_atomic_wait_for_dependencies() is available */ +/* #undef HAVE_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES */ + /* drm_dp_atomic_find_vcpi_slots() is available */ #define HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 index 0e5b9a432aa01..bb74fab63718a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 @@ -80,9 +80,30 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_SETUP_COMMIT], [ ]) ]) +drm_dp_mst_atomic_wait_for_dependencies + +dnl # +dnl # commit v6.1-rc1~27-a5c2c0d164e9 +dnl # drm/display/dp_mst: Add nonblocking helpers for DP MST +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + int ret; + ret = drm_dp_mst_atomic_wait_for_dependencies(NULL); + ],[ + AC_DEFINE(HAVE_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES, 1, + [drm_dp_mst_atomic_wait_for_dependencies() is available]) + ]) + ]) +]) + AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FUNCS], [ AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS AC_AMDGPU_DRM_DP_ATOMIC_FIND_TIME_SLOTS AC_AMDGPU_DRM_DP_ATOMIC_SETUP_COMMIT + AC_AMDGPU_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES ]) From 833831ce19a4406e91fe503355b09837e4900dec Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 24 Nov 2022 13:15:48 +0800 Subject: [PATCH 0828/1868] drm/amdkcl: Check if drm_dp_mst_root_conn_atomic_check() is available Check if drm_dp_mst_root_conn_atomic_check() is available Signed-off-by: Ma Jun Change-Id: I3b91f33e2fd780e3b2c952aa2c5c95bcaae78a52 --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 +++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 | 18 ++++++++++++++++++ 3 files changed, 26 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index ba334a051c2dc..dbadc9e736969 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -7642,15 +7642,19 @@ amdgpu_dm_connector_atomic_check(struct drm_connector *conn, drm_atomic_get_old_connector_state(state, conn); struct drm_crtc *crtc = new_con_state->crtc; struct drm_crtc_state *new_crtc_state; +#ifdef HAVE_DRM_DP_MST_ROOT_CONN_ATOMIC_CHECK struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(conn); +#endif int ret; trace_amdgpu_dm_connector_atomic_check(new_con_state); if (conn->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { +#ifdef HAVE_DRM_DP_MST_ROOT_CONN_ATOMIC_CHECK ret = drm_dp_mst_root_conn_atomic_check(new_con_state, &aconn->mst_mgr); if (ret < 0) return ret; +#endif } if (!crtc) @@ -7702,6 +7706,7 @@ amdgpu_dm_connector_atomic_check(struct drm_connector *conn, return 0; } #endif + static struct drm_encoder *amdgpu_dm_connector_to_encoder(struct drm_connector *connector) { #ifdef HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 8804528e63739..c5c347067a4b7 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -430,6 +430,9 @@ /* struct drm_dp_mst_port has passthrough_aux member */ /* #undef HAVE_DRM_DP_MST_PORT_PASSTHROUGH_AUX */ +/* drm_dp_mst_root_conn_atomic_check() is available */ +/* #undef HAVE_DRM_DP_MST_ROOT_CONN_ATOMIC_CHECK */ + /* drm_dp_mst_port struct has full_pbn member */ #define HAVE_DRM_DP_MST_PORT_FULL_PBN 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 index bb74fab63718a..c28aae7a0814a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 @@ -100,10 +100,28 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES], [ ]) ]) +dnl # +dnl # commit v6.1-rc1~27-a5c2c0d164e9 +dnl # drm/display/dp_mst: Add nonblocking helpers for DP MST +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_ROOT_CONN_ATOMIC_CHECK], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + int ret; + ret = drm_dp_mst_root_conn_atomic_check(NULL, NULL); + ],[ + AC_DEFINE(HAVE_DRM_DP_MST_ROOT_CONN_ATOMIC_CHECK, 1, + [drm_dp_mst_root_conn_atomic_check() is available]) + ]) + ]) +]) AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FUNCS], [ AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS AC_AMDGPU_DRM_DP_ATOMIC_FIND_TIME_SLOTS AC_AMDGPU_DRM_DP_ATOMIC_SETUP_COMMIT AC_AMDGPU_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES + AC_AMDGPU_DRM_DP_MST_ROOT_CONN_ATOMIC_CHECK ]) From b0f9bd27e08422de7302a937870797b72db61185 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 24 Nov 2022 13:25:40 +0800 Subject: [PATCH 0829/1868] drm/amdkcl: Check if drm_dp_atomic_release_time_slots() is available Check if drm_dp_atomic_release_time_slots() is available Signed-off-by: Ma Jun Change-Id: I1fa8e5977f98a88d638dd93c7fb2398fdf447147 --- .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 4 ++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 | 19 +++++++++++++++++++ 3 files changed, 26 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 3fe1c62fcd8b6..52832f71193a6 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -560,11 +560,15 @@ dm_dp_mst_detect(struct drm_connector *connector, static int dm_dp_mst_atomic_check(struct drm_connector *connector, struct drm_atomic_state *state) { +#ifdef HAVE_DRM_DP_ATOMIC_RELEASE_TIME_SLOTS struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); struct drm_dp_mst_topology_mgr *mst_mgr = &aconnector->mst_root->mst_mgr; struct drm_dp_mst_port *mst_port = aconnector->mst_output_port; return drm_dp_atomic_release_time_slots(state, mst_mgr, mst_port); +#else + return 0; +#endif } #endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index c5c347067a4b7..805e8794bac31 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -379,6 +379,9 @@ /* drm_dp_atomic_find_vcpi_slots() is available */ #define HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS 1 +/* drm_dp_atomic_release_time_slots() is available */ +/* #undef HAVE_DRM_DP_ATOMIC_RELEASE_TIME_SLOTS */ + /* drm_dp_atomic_find_vcpi_slots() wants 5args */ #define HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS_5ARGS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 index c28aae7a0814a..a67dc29ccbeb2 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 @@ -118,10 +118,29 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_MST_ROOT_CONN_ATOMIC_CHECK], [ ]) ]) +dnl # +dnl # commit v6.1-rc1~27-df78f7f660cd +dnl # drm/display/dp_mst: Call them time slots, not VCPI slots +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_RELEASE_TIME_SLOTS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + int ret; + ret = drm_dp_atomic_release_time_slots(NULL, NULL, NULL); + ],[ + AC_DEFINE(HAVE_DRM_DP_ATOMIC_RELEASE_TIME_SLOTS, 1, + [drm_dp_atomic_release_time_slots() is available]) + ]) + ]) +]) + AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FUNCS], [ AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS AC_AMDGPU_DRM_DP_ATOMIC_FIND_TIME_SLOTS AC_AMDGPU_DRM_DP_ATOMIC_SETUP_COMMIT AC_AMDGPU_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES AC_AMDGPU_DRM_DP_MST_ROOT_CONN_ATOMIC_CHECK + AC_AMDGPU_DRM_DP_ATOMIC_RELEASE_TIME_SLOTS ]) From 1517dc8356da1615f8169f2e3456ad24369ed2f1 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 24 Nov 2022 14:38:58 +0800 Subject: [PATCH 0830/1868] drm/amdkcl: Using amdkcl_ttm_resvp() to get bo->resv Using amdkcl_ttm_resvp() to get bo->resv Signed-off-by: Ma Jun Change-Id: I11553784cdba0f2a1c91d3bf41b274d14a843d3e --- drivers/gpu/drm/ttm/ttm_bo.c | 2 +- drivers/gpu/drm/ttm/ttm_bo_util.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c index 54098ab269e35..acb8487ad4457 100644 --- a/drivers/gpu/drm/ttm/ttm_bo.c +++ b/drivers/gpu/drm/ttm/ttm_bo.c @@ -1011,7 +1011,7 @@ int ttm_bo_init_reserved(struct ttm_device *bdev, struct ttm_buffer_object *bo, err_unlock: if (!resv) - dma_resv_unlock(bo->base.resv); + dma_resv_unlock(amdkcl_ttm_resvp(bo)); err_put: ttm_bo_put(bo); diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c index f31d9c65609ef..f2b0bf7747f5f 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_util.c +++ b/drivers/gpu/drm/ttm/ttm_bo_util.c @@ -490,7 +490,7 @@ int ttm_bo_vmap(struct ttm_buffer_object *bo, struct iosys_map *map) struct ttm_resource *mem = bo->resource; int ret; - dma_resv_assert_held(bo->base.resv); + dma_resv_assert_held(amdkcl_ttm_resvp(bo)); ret = ttm_mem_io_reserve(bo->bdev, mem); if (ret) @@ -558,7 +558,7 @@ void ttm_bo_vunmap(struct ttm_buffer_object *bo, struct iosys_map *map) { struct ttm_resource *mem = bo->resource; - dma_resv_assert_held(bo->base.resv); + dma_resv_assert_held(amdkcl_ttm_resvp(bo)); if (iosys_map_is_null(map)) return; From 947a55f743e9f5cd03be5ea59090f9a8ac832db3 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 24 Nov 2022 14:48:06 +0800 Subject: [PATCH 0831/1868] drm/amdkcl: Rename idr-remove.m4 Rename idr-remove.m4 as idr.m4 for better compatability Signed-off-by: Ma Jun Change-Id: Iacfdba39cf4fd2224e51d8b3f018cb5dfcdbd5bd --- drivers/gpu/drm/amd/dkms/m4/{idr-remove.m4 => idr.m4} | 4 ++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) rename drivers/gpu/drm/amd/dkms/m4/{idr-remove.m4 => idr.m4} (90%) diff --git a/drivers/gpu/drm/amd/dkms/m4/idr-remove.m4 b/drivers/gpu/drm/amd/dkms/m4/idr.m4 similarity index 90% rename from drivers/gpu/drm/amd/dkms/m4/idr-remove.m4 rename to drivers/gpu/drm/amd/dkms/m4/idr.m4 index 397c76a73ed8e..0801f227c6421 100644 --- a/drivers/gpu/drm/amd/dkms/m4/idr-remove.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/idr.m4 @@ -17,3 +17,7 @@ AC_DEFUN([AC_AMDGPU_IDR_REMOVE], [ ]) ]) ]) + +AC_DEFUN([AC_AMDGPU_IDR], [ + AC_AMDGPU_IDR_REMOVE +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 29e7e449e1542..5d7b36afbf7b1 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -8,7 +8,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_HEADERS AC_AMDGPU_KALLSYMS_LOOKUP_NAME AC_KERNEL_SUPPORTED_AMD_CHIPS - AC_AMDGPU_IDR_REMOVE + AC_AMDGPU_IDR AC_AMDGPU_KREF_READ AC_AMDGPU_TYPE__POLL_T AC_AMDGPU_DMA_MAP_SGTABLE From 38a5ca43db2df99e96a2db5ad34b352fe557e0f5 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 24 Nov 2022 14:54:45 +0800 Subject: [PATCH 0832/1868] drm/amdkcl: Check and implement idr_init_base() Check and implement idr_init_base() Signed-off-by: Ma Jun Change-Id: Idb8feda0a5dd39b22b1e65e2cafec0c108640f4e --- drivers/gpu/drm/amd/dkms/m4/idr.m4 | 39 ++++++++++++++++++++++++++++++ include/kcl/kcl_idr.h | 16 ++++++++++++ 2 files changed, 55 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/idr.m4 b/drivers/gpu/drm/amd/dkms/m4/idr.m4 index 0801f227c6421..7816e84901c5a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/idr.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/idr.m4 @@ -18,6 +18,45 @@ AC_DEFUN([AC_AMDGPU_IDR_REMOVE], [ ]) ]) +dnl # +dnl # commit v6.1-rc1~27-c4f306e31632 +dnl # drm/amdgpu: use idr_init_base() to initialize fpriv->bo_list_handles +dnl # +AC_DEFUN([AC_AMDGPU_IDR_INIT_BASE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + void *i; + i = idr_init_base(NULL, 0); + ], [ + AC_DEFINE(HAVE_IDR_INIT_BASE, 1, + [idr_init_base() is available]) + ]) + ]) +]) + +dnl # +dnl # commit v4.16-rc1~25-6ce711f27500 +dnl # idr: Make 1-based IDRs more efficient +dnl # +AC_DEFUN([AC_AMDGPU_STRUCT_IDE_IDR_BASE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct idr *idr = NULL; + idr->idr_base = 0; + ], [ + AC_DEFINE(HAVE_STRUCT_IDE_IDR_BASE, 1, + [ide->idr_base is available]) + ]) + ]) +]) + + AC_DEFUN([AC_AMDGPU_IDR], [ AC_AMDGPU_IDR_REMOVE + AC_AMDGPU_IDR_INIT_BASE + AC_AMDGPU_STRUCT_IDE_IDR_BASE ]) diff --git a/include/kcl/kcl_idr.h b/include/kcl/kcl_idr.h index 63473317c2ead..1cdea5ec45d67 100644 --- a/include/kcl/kcl_idr.h +++ b/include/kcl/kcl_idr.h @@ -35,4 +35,20 @@ static inline void *_kcl_idr_remove(struct idr *idr, int id) #define idr_remove _kcl_idr_remove #endif /* HAVE_IDR_REMOVE_RETURN_VOID_POINTER */ +#ifndef HAVE_IDR_INIT_BASE +#ifdef HAVE_STRUCT_IDE_IDR_BASE +static inline void kc_idr_init_base(struct idr *idr, int base) +{ + INIT_RADIX_TREE(&idr->idr_rt, IDR_RT_MARKER); + idr->idr_base = base; + idr->idr_next = 0; +} +#else +static inline void kc_idr_init_base(struct idr *idr, int base) +{ + idr_init(idr); +} +#endif +#define idr_init_base kc_idr_init_base +#endif #endif /* AMDKCL_IDR_H */ From 8192476fd4587e2c447b7bb9297b2d2bdc060b38 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 24 Nov 2022 15:18:34 +0800 Subject: [PATCH 0833/1868] drm/amdkcl: change label from error_abort to error_unlock It's caused by 4624459c84d71e0d5f94ea6a7b2c4eec4f1d122b drm/amdgpu: add gang submit frontend v6 Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 1cde3b1d2e209..2e12f2d29895c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -1449,7 +1449,7 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm)) { r = -ERESTARTSYS; - goto error_abort; + goto error_unlock; } } #endif From eea27c5f6a05bc240f9de6c74eff6bfaa9fa74e4 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 24 Nov 2022 16:43:31 +0800 Subject: [PATCH 0834/1868] drm/amdkcl: Declare amdgpu_display_gem_fb_init() Declare amdgpu_display_gem_fb_init because this function still being used Signed-off-by: Ma Jun Change-Id: I5184237ba51dcd6623ca64c49118db63ed7211a7 --- drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index 4ed812bf32cd5..70caa28fa86f2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -705,6 +705,11 @@ int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev, int *hpos, ktime_t *stime, ktime_t *etime, const struct drm_display_mode *mode); +int amdgpu_display_gem_fb_init(struct drm_device *dev, + struct amdgpu_framebuffer *rfb, + const struct drm_mode_fb_cmd2 *mode_cmd, + struct drm_gem_object *obj); + int amdgpufb_remove(struct drm_device *dev, struct drm_framebuffer *fb); void amdgpu_enc_destroy(struct drm_encoder *encoder); From aea6dc914b5ed0e63753055d9831762bade78c32 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Fri, 11 Nov 2022 09:52:25 +0800 Subject: [PATCH 0835/1868] drm/amdkcl: Remove redundant call of drm_mode_config_cleanup() Remove redundant call of drm_mode_config_cleanup() to fix the uninstall error below and sync up with drm-next branch. But this solution is used for the OSs which has devm api [ +0.014971] amdgpu 0000:03:00.0: [drm] *ERROR* Error removing FB:0 (-2) [ +0.000150] BUG: kernel NULL pointer dereference, address: 0000000000000000 [ +0.000010] #PF: supervisor read access in kernel mode [ +0.000006] #PF: error_code(0x0000) - not-present page Signed-off-by: Ma Jun Change-Id: I463330733da375863f9825d4e2ced644e42f26d8 --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index dbadc9e736969..8b20145bd5a59 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -5230,7 +5230,10 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm) { +#ifdef AMDKCL_DEVM_DRM_DEV_ALLOC drm_mode_config_cleanup(dm->ddev); +#endif + #ifdef HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT drm_atomic_private_obj_fini(&dm->atomic_obj); #endif From 011c60f6dd430bd707849536a2bc019cb42e51f2 Mon Sep 17 00:00:00 2001 From: bobzhou Date: Wed, 23 Nov 2022 16:11:22 +0800 Subject: [PATCH 0836/1868] drm/amdkcl: rename the function name for HMM handling It's caused 735e66c12ec98751474db9e700c80e65355c1290 "drm/amdgpu: rename the files for HMM handling" Signed-off-by: bobzhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h | 8 ++++---- 3 files changed, 8 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 2e12f2d29895c..6f6d17b7b5272 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -41,6 +41,7 @@ #include "amdgpu_gem.h" #include "amdgpu_ras.h" #include "amdgpu_display.h" +#include "amdgpu_hmm.h" static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, struct amdgpu_device *adev, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c index 43bb1ec468fe8..580c06da4c55f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c @@ -609,7 +609,7 @@ struct amdgpu_mn *amdgpu_mn_get(struct amdgpu_device *adev, } /** - * amdgpu_mn_register - register a BO for notifier updates + * amdgpu_hmm_register - register a BO for notifier updates * * @bo: amdgpu buffer object * @addr: userptr addr we should monitor @@ -617,7 +617,7 @@ struct amdgpu_mn *amdgpu_mn_get(struct amdgpu_device *adev, * Registers an MMU notifier for the given BO at the specified address. * Returns 0 on success, -ERRNO if anything goes wrong. */ -int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr) +int amdgpu_hmm_register(struct amdgpu_bo *bo, unsigned long addr) { unsigned long end = addr + amdgpu_bo_size(bo) - 1; struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); @@ -676,7 +676,7 @@ int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr) * * Remove any registration of MMU notifier updates from the buffer object. */ -void amdgpu_mn_unregister(struct amdgpu_bo *bo) +void amdgpu_hmm_unregister(struct amdgpu_bo *bo) { struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); struct amdgpu_mn *amn; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h index b70e93444fabb..38492d5c4d72b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.h @@ -42,8 +42,8 @@ void amdgpu_mn_lock(struct amdgpu_mn *mn); void amdgpu_mn_unlock(struct amdgpu_mn *mn); struct amdgpu_mn *amdgpu_mn_get(struct amdgpu_device *adev, enum amdgpu_mn_type type); -int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr); -void amdgpu_mn_unregister(struct amdgpu_bo *bo); +int amdgpu_hmm_register(struct amdgpu_bo *bo, unsigned long addr); +void amdgpu_hmm_unregister(struct amdgpu_bo *bo); #else /* !CONFIG_MMU_NOTIFIER */ static inline void amdgpu_mn_lock(struct amdgpu_mn *mn) {} static inline void amdgpu_mn_unlock(struct amdgpu_mn *mn) {} @@ -52,11 +52,11 @@ static inline struct amdgpu_mn *amdgpu_mn_get(struct amdgpu_device *adev, { return NULL; } -static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr) +static inline int amdgpu_hmm_register(struct amdgpu_bo *bo, unsigned long addr) { return -ENODEV; } -static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {} +static inline void amdgpu_hmm_unregister(struct amdgpu_bo *bo) {} #endif /* CONFIG_MMU_NOTIFIER */ #else /* HAVE_AMDKCL_HMM_MIRROR_ENABLED */ #include From 1dcb578e17bb1ca71e24cc2e064ad33c22af0dcf Mon Sep 17 00:00:00 2001 From: bobzhou Date: Wed, 23 Nov 2022 14:32:31 +0800 Subject: [PATCH 0837/1868] drm/amdkcl: modify fake function for amdgpu_ttm_tt_get_user_pages It's caused by 3da41b3e6f43161b0878d71c4b92211e6495a1c3 "drm/amdgpu: fix userptr HMM range handling v2" Signed-off-by: bobzhou Reviewed-by: Leslie Shi Change-Id: I5455256f52b011df8e0d100ca2d4ab01975fd9f8 --- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 4 +- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 148 +++++++++--------- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 3 +- 3 files changed, 78 insertions(+), 77 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index ed584e64674dd..9162561c1dcd9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -1170,7 +1170,7 @@ static int init_user_pages(struct kgd_mem *mem, uint64_t user_addr, goto unregister_out; } - ret = amdgpu_ttm_tt_get_user_pages(bo, mem->user_pages); + ret = amdgpu_ttm_tt_get_user_pages(bo, mem->user_pages, NULL); if (ret) { pr_err("%s: Failed to get user pages: %d\n", __func__, ret); goto free_out; @@ -2970,7 +2970,7 @@ static int update_invalid_user_pages(struct amdkfd_process_info *process_info, } /* Get updated user pages */ - ret = amdgpu_ttm_tt_get_user_pages(bo, mem->user_pages); + ret = amdgpu_ttm_tt_get_user_pages(bo, mem->user_pages, NULL); if (ret) { mem->user_pages[0] = NULL; pr_info("%s: Failed to get user pages: %d\n", diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 6f6d17b7b5272..4e3f55f8a0d41 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -945,80 +945,80 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, } } #else - while (1) { - struct list_head need_pages; - - r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true, - &duplicates); - if (unlikely(r != 0)) { - if (r != -ERESTARTSYS) - DRM_ERROR("ttm_eu_reserve_buffers failed.\n"); - goto error_free_pages; - } - - INIT_LIST_HEAD(&need_pages); - amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) { - struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo); - - if (amdgpu_ttm_tt_userptr_invalidated(bo->tbo.ttm, - &e->user_invalidated) && e->user_pages) { - - /* We acquired a page array, but somebody - * invalidated it. Free it and try again - */ - release_pages(e->user_pages, - bo->tbo.ttm->num_pages); - kvfree(e->user_pages); - e->user_pages = NULL; - } - - if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm) && - !e->user_pages) { - list_del(&e->tv.head); - list_add(&e->tv.head, &need_pages); - - amdgpu_bo_unreserve(bo); - } - } - - if (list_empty(&need_pages)) - break; - - /* Unreserve everything again. */ - ttm_eu_backoff_reservation(&p->ticket, &p->validated); - - /* We tried too many times, just abort */ - if (!--tries) { - r = -EDEADLK; - DRM_ERROR("deadlock in %s\n", __func__); - goto error_free_pages; - } - - /* Fill the page arrays for all userptrs. */ - list_for_each_entry(e, &need_pages, tv.head) { - struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo); - - e->user_pages = kvmalloc_array(bo->tbo.ttm->num_pages, - sizeof(struct page*), - GFP_KERNEL | __GFP_ZERO); - if (!e->user_pages) { - r = -ENOMEM; - DRM_ERROR("calloc failure in %s\n", __func__); - goto error_free_pages; - } - - r = amdgpu_ttm_tt_get_user_pages(bo, e->user_pages); - if (r) { - DRM_ERROR("amdgpu_ttm_tt_get_user_pages failed.\n"); - kvfree(e->user_pages); - e->user_pages = NULL; - goto error_free_pages; - } - } - - /* And try again. */ - list_splice(&need_pages, &p->validated); - } + while (1) { + struct list_head need_pages; + + r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true, + &duplicates); + if (unlikely(r != 0)) { + if (r != -ERESTARTSYS) + DRM_ERROR("ttm_eu_reserve_buffers failed.\n"); + goto error_free_pages; + } + + INIT_LIST_HEAD(&need_pages); + amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) { + struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo); + + if (amdgpu_ttm_tt_userptr_invalidated(bo->tbo.ttm, + &e->user_invalidated) && e->user_pages) { + + /* We acquired a page array, but somebody + * invalidated it. Free it and try again + */ + release_pages(e->user_pages, + bo->tbo.ttm->num_pages); + kvfree(e->user_pages); + e->user_pages = NULL; + } + + if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm) && + !e->user_pages) { + list_del(&e->tv.head); + list_add(&e->tv.head, &need_pages); + + amdgpu_bo_unreserve(bo); + } + } + + if (list_empty(&need_pages)) + break; + + /* Unreserve everything again. */ + ttm_eu_backoff_reservation(&p->ticket, &p->validated); + + /* We tried too many times, just abort */ + if (!--tries) { + r = -EDEADLK; + DRM_ERROR("deadlock in %s\n", __func__); + goto error_free_pages; + } + + /* Fill the page arrays for all userptrs. */ + list_for_each_entry(e, &need_pages, tv.head) { + struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo); + + e->user_pages = kvmalloc_array(bo->tbo.ttm->num_pages, + sizeof(struct page*), + GFP_KERNEL | __GFP_ZERO); + if (!e->user_pages) { + r = -ENOMEM; + DRM_ERROR("calloc failure in %s\n", __func__); + goto error_free_pages; + } + + r = amdgpu_ttm_tt_get_user_pages(bo, e->user_pages, NULL); + if (r) { + DRM_ERROR("amdgpu_ttm_tt_get_user_pages failed.\n"); + kvfree(e->user_pages); + e->user_pages = NULL; + goto error_free_pages; + } + } + + /* And try again. */ + list_splice(&need_pages, &p->validated); + } #endif amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index fb26f37c4c36c..069947f864f73 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -854,7 +854,8 @@ bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm, * This provides a wrapper around the get_user_pages() call to provide * device accessible pages that back user memory. */ -int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages) +int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages, + struct hmm_range **range) { struct ttm_tt *ttm = bo->tbo.ttm; struct amdgpu_ttm_tt *gtt = (void *)ttm; From c9c0ef33c5dab2ed65be0f2bbc6eef4aeb45bf6f Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Sat, 26 Nov 2022 09:50:43 +0800 Subject: [PATCH 0838/1868] drm/amdkcl: Bump dkms package version to 6.0.0 Signed-off-by: Ma Jun Change-Id: Icd6b1a03c61a583ce076fff0662e014b95a6f81d --- drivers/gpu/drm/amd/dkms/configure.ac | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/configure.ac b/drivers/gpu/drm/amd/dkms/configure.ac index fb89f280535c4..15e057582c3c1 100644 --- a/drivers/gpu/drm/amd/dkms/configure.ac +++ b/drivers/gpu/drm/amd/dkms/configure.ac @@ -1,4 +1,4 @@ -AC_INIT(amdgpu-dkms, 5.19.0) +AC_INIT(amdgpu-dkms, 6.0.0) AC_LANG(C) AC_CONFIG_AUX_DIR([config]) From 2643fd9b8731600477891424b8d8919a93a281ab Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 2 Dec 2022 19:35:35 +0800 Subject: [PATCH 0839/1868] Revert "dma-buf: fix dma_fence_default_wait() signaling check" This reverts commit 3cc3dd73c420dc70cd366f91a680035ef47edf4f. Signed-off-by: Asher Song --- drivers/dma-buf/dma-fence.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/dma-buf/dma-fence.c b/drivers/dma-buf/dma-fence.c index 0393a9bba3a8a..51bd700f47797 100644 --- a/drivers/dma-buf/dma-fence.c +++ b/drivers/dma-buf/dma-fence.c @@ -764,10 +764,10 @@ dma_fence_default_wait(struct dma_fence *fence, bool intr, signed long timeout) unsigned long flags; signed long ret = timeout ? timeout : 1; - spin_lock_irqsave(fence->lock, flags); - if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) - goto out; + return ret; + + spin_lock_irqsave(fence->lock, flags); if (intr && signal_pending(current)) { ret = -ERESTARTSYS; From 88dac847009f3031bc72571ae1cc116f317c3a33 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 2 Dec 2022 19:36:10 +0800 Subject: [PATCH 0840/1868] Revert "dma-buf: dma_fence_wait must enable signaling" This reverts commit b96fb1e724ae6839d5bffcf42dd3503db7cc7df5. Signed-off-by: Asher Song --- drivers/dma-buf/dma-fence.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/dma-buf/dma-fence.c b/drivers/dma-buf/dma-fence.c index 51bd700f47797..0e7235624ef67 100644 --- a/drivers/dma-buf/dma-fence.c +++ b/drivers/dma-buf/dma-fence.c @@ -509,8 +509,6 @@ dma_fence_wait_timeout(struct dma_fence *fence, bool intr, signed long timeout) __dma_fence_might_wait(); - dma_fence_enable_sw_signaling(fence); - trace_dma_fence_wait_start(fence); if (fence->ops->wait) ret = fence->ops->wait(fence, intr, timeout); @@ -774,6 +772,9 @@ dma_fence_default_wait(struct dma_fence *fence, bool intr, signed long timeout) goto out; } + if (!__dma_fence_enable_signaling(fence)) + goto out; + if (!timeout) { ret = 0; goto out; From 56e44a4445443dd9bd3717098878f1222f138bcc Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 2 Dec 2022 19:36:28 +0800 Subject: [PATCH 0841/1868] Revert "dma-buf: Enable signaling on fence for selftests" This reverts commit d62c43a953ce02d54521ec06217d0c2ed6d489af. Signed-off-by: Asher Song --- drivers/dma-buf/st-dma-fence-chain.c | 2 -- drivers/dma-buf/st-dma-fence-unwrap.c | 22 ---------------------- drivers/dma-buf/st-dma-fence.c | 16 ---------------- drivers/dma-buf/st-dma-resv.c | 10 ---------- 4 files changed, 50 deletions(-) diff --git a/drivers/dma-buf/st-dma-fence-chain.c b/drivers/dma-buf/st-dma-fence-chain.c index ed4b323886e43..b08c90ebef95d 100644 --- a/drivers/dma-buf/st-dma-fence-chain.c +++ b/drivers/dma-buf/st-dma-fence-chain.c @@ -145,8 +145,6 @@ static int fence_chains_init(struct fence_chains *fc, unsigned int count, } fc->tail = fc->chains[i]; - - dma_fence_enable_sw_signaling(fc->chains[i]); } fc->chain_length = i; diff --git a/drivers/dma-buf/st-dma-fence-unwrap.c b/drivers/dma-buf/st-dma-fence-unwrap.c index f0cee984b6c74..4105d5ea8ddeb 100644 --- a/drivers/dma-buf/st-dma-fence-unwrap.c +++ b/drivers/dma-buf/st-dma-fence-unwrap.c @@ -102,8 +102,6 @@ static int sanitycheck(void *arg) if (!f) return -ENOMEM; - dma_fence_enable_sw_signaling(f); - array = mock_array(1, f); if (!array) return -ENOMEM; @@ -126,16 +124,12 @@ static int unwrap_array(void *arg) if (!f1) return -ENOMEM; - dma_fence_enable_sw_signaling(f1); - f2 = mock_fence(); if (!f2) { dma_fence_put(f1); return -ENOMEM; } - dma_fence_enable_sw_signaling(f2); - array = mock_array(2, f1, f2); if (!array) return -ENOMEM; @@ -170,16 +164,12 @@ static int unwrap_chain(void *arg) if (!f1) return -ENOMEM; - dma_fence_enable_sw_signaling(f1); - f2 = mock_fence(); if (!f2) { dma_fence_put(f1); return -ENOMEM; } - dma_fence_enable_sw_signaling(f2); - chain = mock_chain(f1, f2); if (!chain) return -ENOMEM; @@ -214,16 +204,12 @@ static int unwrap_chain_array(void *arg) if (!f1) return -ENOMEM; - dma_fence_enable_sw_signaling(f1); - f2 = mock_fence(); if (!f2) { dma_fence_put(f1); return -ENOMEM; } - dma_fence_enable_sw_signaling(f2); - array = mock_array(2, f1, f2); if (!array) return -ENOMEM; @@ -262,16 +248,12 @@ static int unwrap_merge(void *arg) if (!f1) return -ENOMEM; - dma_fence_enable_sw_signaling(f1); - f2 = mock_fence(); if (!f2) { err = -ENOMEM; goto error_put_f1; } - dma_fence_enable_sw_signaling(f2); - f3 = dma_fence_unwrap_merge(f1, f2); if (!f3) { err = -ENOMEM; @@ -314,14 +296,10 @@ static int unwrap_merge_complex(void *arg) if (!f1) return -ENOMEM; - dma_fence_enable_sw_signaling(f1); - f2 = mock_fence(); if (!f2) goto error_put_f1; - dma_fence_enable_sw_signaling(f2); - f3 = dma_fence_unwrap_merge(f1, f2); if (!f3) goto error_put_f2; diff --git a/drivers/dma-buf/st-dma-fence.c b/drivers/dma-buf/st-dma-fence.c index 6a1bfcd0cc210..d5c106e0b3d0a 100644 --- a/drivers/dma-buf/st-dma-fence.c +++ b/drivers/dma-buf/st-dma-fence.c @@ -102,8 +102,6 @@ static int sanitycheck(void *arg) if (!f) return -ENOMEM; - dma_fence_enable_sw_signaling(f); - dma_fence_signal(f); dma_fence_put(f); @@ -119,8 +117,6 @@ static int test_signaling(void *arg) if (!f) return -ENOMEM; - dma_fence_enable_sw_signaling(f); - if (dma_fence_is_signaled(f)) { pr_err("Fence unexpectedly signaled on creation\n"); goto err_free; @@ -194,8 +190,6 @@ static int test_late_add_callback(void *arg) if (!f) return -ENOMEM; - dma_fence_enable_sw_signaling(f); - dma_fence_signal(f); if (!dma_fence_add_callback(f, &cb.cb, simple_callback)) { @@ -288,8 +282,6 @@ static int test_status(void *arg) if (!f) return -ENOMEM; - dma_fence_enable_sw_signaling(f); - if (dma_fence_get_status(f)) { pr_err("Fence unexpectedly has signaled status on creation\n"); goto err_free; @@ -316,8 +308,6 @@ static int test_error(void *arg) if (!f) return -ENOMEM; - dma_fence_enable_sw_signaling(f); - dma_fence_set_error(f, -EIO); if (dma_fence_get_status(f)) { @@ -347,8 +337,6 @@ static int test_wait(void *arg) if (!f) return -ENOMEM; - dma_fence_enable_sw_signaling(f); - if (dma_fence_wait_timeout(f, false, 0) != -ETIME) { pr_err("Wait reported complete before being signaled\n"); goto err_free; @@ -391,8 +379,6 @@ static int test_wait_timeout(void *arg) if (!wt.f) return -ENOMEM; - dma_fence_enable_sw_signaling(wt.f); - if (dma_fence_wait_timeout(wt.f, false, 1) != -ETIME) { pr_err("Wait reported complete before being signaled\n"); goto err_free; @@ -472,8 +458,6 @@ static int thread_signal_callback(void *arg) break; } - dma_fence_enable_sw_signaling(f1); - rcu_assign_pointer(t->fences[t->id], f1); smp_wmb(); diff --git a/drivers/dma-buf/st-dma-resv.c b/drivers/dma-buf/st-dma-resv.c index 15dbea1462ed4..813779e3c9be5 100644 --- a/drivers/dma-buf/st-dma-resv.c +++ b/drivers/dma-buf/st-dma-resv.c @@ -45,8 +45,6 @@ static int sanitycheck(void *arg) if (!f) return -ENOMEM; - dma_fence_enable_sw_signaling(f); - dma_fence_signal(f); dma_fence_put(f); @@ -71,8 +69,6 @@ static int test_signaling(void *arg) if (!f) return -ENOMEM; - dma_fence_enable_sw_signaling(f); - dma_resv_init(&resv); r = dma_resv_lock(&resv, NULL); if (r) { @@ -118,8 +114,6 @@ static int test_for_each(void *arg) if (!f) return -ENOMEM; - dma_fence_enable_sw_signaling(f); - dma_resv_init(&resv); r = dma_resv_lock(&resv, NULL); if (r) { @@ -179,8 +173,6 @@ static int test_for_each_unlocked(void *arg) if (!f) return -ENOMEM; - dma_fence_enable_sw_signaling(f); - dma_resv_init(&resv); r = dma_resv_lock(&resv, NULL); if (r) { @@ -252,8 +244,6 @@ static int test_get_fences(void *arg) if (!f) return -ENOMEM; - dma_fence_enable_sw_signaling(f); - dma_resv_init(&resv); r = dma_resv_lock(&resv, NULL); if (r) { From cadc7c0491c12f8163bf0a99b0d66472b206c925 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 2 Dec 2022 19:36:43 +0800 Subject: [PATCH 0842/1868] Revert "dma-buf: set signaling bit for the stub fence" This reverts commit c85d00d4fd8b98ea4d16817f397a4de5e177afd6. Signed-off-by: Asher Song --- drivers/dma-buf/dma-fence.c | 7 ------- 1 file changed, 7 deletions(-) diff --git a/drivers/dma-buf/dma-fence.c b/drivers/dma-buf/dma-fence.c index 0e7235624ef67..0022ba945ba76 100644 --- a/drivers/dma-buf/dma-fence.c +++ b/drivers/dma-buf/dma-fence.c @@ -136,10 +136,6 @@ struct dma_fence *dma_fence_get_stub(void) &dma_fence_stub_ops, &dma_fence_stub_lock, 0, 0); - - set_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, - &dma_fence_stub.flags); - dma_fence_signal_locked(&dma_fence_stub); } spin_unlock(&dma_fence_stub_lock); @@ -167,9 +163,6 @@ struct dma_fence *dma_fence_allocate_private_stub(ktime_t timestamp) &dma_fence_stub_lock, 0, 0); - set_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, - &fence->flags); - dma_fence_signal_timestamp(fence, timestamp); return fence; From 875f0bfcd1ae9a5472262849f6c13fd6f4acc7f7 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 2 Dec 2022 19:36:59 +0800 Subject: [PATCH 0843/1868] Revert "dma-buf: Remove the signaled bit status check" This reverts commit 6ad9aa476ce23be45de9dcb03edcdbfdf6117c25. The following patches casue system hang when run MesaGL benchmark. So remove them. dmabuf: fix dma_fence_default_wait() signaling check drm/sched: Use parent fence instead of finished dmabuf: dma_fence_wait must enable signaling dmabuf: Enable signaling on fence for selftests dmabuf: set signaling bit for the stub fence dmabuf: Remove the signaled bit status check Signed-off-by: Asher Song --- drivers/dma-buf/dma-fence.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/dma-buf/dma-fence.c b/drivers/dma-buf/dma-fence.c index 0022ba945ba76..c788c38dc671e 100644 --- a/drivers/dma-buf/dma-fence.c +++ b/drivers/dma-buf/dma-fence.c @@ -603,6 +603,9 @@ void dma_fence_enable_sw_signaling(struct dma_fence *fence) { unsigned long flags; + if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) + return; + spin_lock_irqsave(fence->lock, flags); __dma_fence_enable_signaling(fence); spin_unlock_irqrestore(fence->lock, flags); From 90006488602d2b5bb163625ba591a65ebc1490f5 Mon Sep 17 00:00:00 2001 From: bobzhou Date: Mon, 28 Nov 2022 13:01:24 +0800 Subject: [PATCH 0844/1868] drm/amdkcl: fix macro for amdgpu_dm_mst_connector_early_unregister It's caused by m4 macro didn't align HAVE_DRM_DP_MST_CONNECTOR_EARLY_UNREGISTER and HAVE_DRM_DP_MST_CONNECTOR_LATE_REGISTER Signed-off-by: Aurabindo Pillai Signed-off-by: bobzhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 4 ++-- drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 805e8794bac31..c39b6ce270174 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -144,10 +144,10 @@ #define HAVE_DOWN_WRITE_KILLABLE 1 /* drm_dp_mst_connector_early_unregister() is available */ -#define HAVE_DP_MST_CONNECTOR_EARLY_UNREGISTER 1 +#define HAVE_DRM_DP_MST_CONNECTOR_EARLY_UNREGISTER 1 /* drm_dp_mst_connector_late_register() is available */ -#define HAVE_DP_MST_CONNECTOR_LATE_REGISTER 1 +#define HAVE_DRM_DP_MST_CONNECTOR_LATE_REGISTER 1 /* drm_accurate_vblank_count() is available */ /* #undef HAVE_DRM_ACCURATE_VBLANK_COUNT */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 index 611bd25368735..ef01260a09ddb 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 @@ -63,9 +63,9 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY], [ drm_dp_mst_connector_early_unregister(NULL, NULL); drm_dp_mst_connector_late_register(NULL, NULL); ], [ - AC_DEFINE(HAVE_DP_MST_CONNECTOR_EARLY_UNREGISTER, 1, [ + AC_DEFINE(HAVE_DRM_DP_MST_CONNECTOR_EARLY_UNREGISTER, 1, [ drm_dp_mst_connector_early_unregister() is available]) - AC_DEFINE(HAVE_DP_MST_CONNECTOR_LATE_REGISTER, 1, [ + AC_DEFINE(HAVE_DRM_DP_MST_CONNECTOR_LATE_REGISTER, 1, [ drm_dp_mst_connector_late_register() is available]) ]) ]) From 9dd5b2856cc3944ec6c2d4360f75fd794b44bad8 Mon Sep 17 00:00:00 2001 From: bobzhou Date: Mon, 28 Nov 2022 14:14:40 +0800 Subject: [PATCH 0845/1868] drm/amdkcl: update documentation of amdgpu_hmm_unregister Signed-off-by: bobzhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c index 580c06da4c55f..ca7304e7f45b0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c @@ -670,7 +670,7 @@ int amdgpu_hmm_register(struct amdgpu_bo *bo, unsigned long addr) } /** - * amdgpu_mn_unregister - unregister a BO for notifier updates + * amdgpu_hmm_unregister - unregister a BO for notifier updates * * @bo: amdgpu buffer object * From 6e3c8647c117014685addf5768fc3d52cb0fec81 Mon Sep 17 00:00:00 2001 From: bobzhou Date: Wed, 30 Nov 2022 16:21:23 +0800 Subject: [PATCH 0846/1868] drm/amdkcl: fix marco for amdgpu_display_hotplug_work_func It's caused by 99d4c5b3ad086bf777a577f3aeb6bf443b8df65c "drm/amdgpu: move non-DC vblank handling out of irq code" Fuction "amdgpu_hotplug_work_func" is changed to "amdgpu_display_hotplug_work_func" But, kcl marco haven't been moved to amdgpu_display_hotplug_work_func Signed-off-by: bobzhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 855360c1abc7d..0f169f93a97a1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -70,13 +70,22 @@ void amdgpu_display_hotplug_work_func(struct work_struct *work) struct drm_device *dev = adev_to_drm(adev); struct drm_mode_config *mode_config = &dev->mode_config; struct drm_connector *connector; +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; +#endif mutex_lock(&mode_config->mutex); +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) +#else + list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) +#endif amdgpu_connector_hotplug(connector); + +#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); +#endif mutex_unlock(&mode_config->mutex); /* Just fire off a uevent and let userspace tell us what to do */ drm_helper_hpd_irq_event(dev); From f727066d57ff12a3b0c9bb787aa6346d49b69cf2 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 7 Dec 2022 15:10:47 +0800 Subject: [PATCH 0847/1868] drm/amdkcl: Fix the type of function kcl_drm_plane_helper_destroy Fix the type of the function kcl_drm_plane_helper_destroy Signed-off-by: Ma Jun Change-Id: Ic2bdbbcd518581b3b5cd2ddd30997b8e7c9ba196 --- include/kcl/kcl_drm_plane_helper.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/include/kcl/kcl_drm_plane_helper.h b/include/kcl/kcl_drm_plane_helper.h index d1bc40bcebb4d..6b3798e0da151 100644 --- a/include/kcl/kcl_drm_plane_helper.h +++ b/include/kcl/kcl_drm_plane_helper.h @@ -4,12 +4,11 @@ #include #ifndef HAVE_DRM_PLANE_HELPER_DESTROY -static void kcl_drm_plane_helper_destroy(struct drm_plane *plane) +static inline void kcl_drm_plane_helper_destroy(struct drm_plane *plane) { drm_plane_cleanup(plane); kfree(plane); } - #define drm_plane_helper_destroy kcl_drm_plane_helper_destroy #endif #endif \ No newline at end of file From 49a77b762543f196a71170b571e81425e2992fd7 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 7 Dec 2022 16:29:19 +0800 Subject: [PATCH 0848/1868] drm/amdkcl: Fix the warning of comment Signed-off-by: Ma Jun Reviewed-by: Flora Cui Change-Id: If5721c8156ae7b147c90bb6dd2d9aff283b22ac6 --- drivers/gpu/drm/amd/amdkcl/kcl_cpumask.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_cpumask.c b/drivers/gpu/drm/amd/amdkcl/kcl_cpumask.c index fe36b386ff52b..f740a9626cd10 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_cpumask.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_cpumask.c @@ -2,7 +2,7 @@ #include #ifndef for_each_cpu_wrap -/* copied from lib/cpumask.c +/* copied from lib/cpumask.c */ /** * cpumask_next_wrap - helper to implement for_each_cpu_wrap * @n: the cpu prior to the place to search From 44698a192a2febfc3b5406e7761931da33a6c906 Mon Sep 17 00:00:00 2001 From: bobzhou Date: Mon, 5 Dec 2022 15:22:49 +0800 Subject: [PATCH 0849/1868] drm/amdkcl: Add support for drm_plane_enable_fb_damage_clips before v5.13 It's caused by 1f35cc57ec8c39b023bc1cfc4a29483e09fbbc89 "drm/amd/display: add FB_DAMAGE_CLIPS support" drm_plane_enable_fb_damage_clips is moved into core in v5.13-rc3-1669-gba6cd766e0bf Signed-off-by: bobzhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/backport/backport.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index ca935a3ea4838..cf0c936c52ad8 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -101,4 +101,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ From dea7704f8bddd8b950f1f66a945a17b26459cb87 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 8 Dec 2022 13:27:23 +0800 Subject: [PATCH 0850/1868] drm/dkms: Using the AS_HELPER_STRING intead of AC_HELP_STRING AC_HELP_STRING is deprecated now. So using the AS_HELPER_STRING intead of AC_HELP_STRING Signed-off-by: Ma Jun Reviewed-by: Flora Cui Change-Id: I144d13752fccf00f01a1a0dc4542603cebb9323f --- drivers/gpu/drm/amd/dkms/m4/config.m4 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/config.m4 b/drivers/gpu/drm/amd/dkms/m4/config.m4 index e22a4a49a5233..d66b31b9b3536 100644 --- a/drivers/gpu/drm/amd/dkms/m4/config.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/config.m4 @@ -1,6 +1,6 @@ AC_DEFUN([AC_AMDGPU_CONFIG], [ AC_ARG_ENABLE([linux-builtin], - [AC_HELP_STRING([--enable-linux-builtin], + [AS_HELP_STRING([--enable-linux-builtin], [Configure for builtin kernel modules @<:@default=no@:>@])], [], [enable_linux_builtin=no]) From 07252d046c960541626d3b6c0feb227ee3c3be31 Mon Sep 17 00:00:00 2001 From: bobzhou Date: Fri, 9 Dec 2022 10:29:36 +0800 Subject: [PATCH 0851/1868] drm/amdkcl: Add missing comments in backport.h for drm_plane_enable_fb_damage_clips Signed-off-by: bobzhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/backport/backport.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index cf0c936c52ad8..bbdb386892d49 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -101,5 +101,11 @@ #include #include #include +/* + * v5.13-rc3-1669-gba6cd766e0bf + * ("drm/plane: Move drm_plane_enable_fb_damage_clips into core") + * move drm_plane_enable_fb_damage_clips() to drm_planer.h. + * include drm_damage_helper.h to fix the missing function declaration for legacy kernel. + */ #include #endif /* AMDGPU_BACKPORT_H */ From 90a917ab4fe6a1534a8e3ed60d387726e89dc089 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Mon, 12 Dec 2022 10:00:23 +0800 Subject: [PATCH 0852/1868] drm/amdkcl: Remove redundant config of DRM_BUDDY Remove redundant config of DRM_BUDDY. Signed-off-by: Ma Jun Reviewed-by: Flora Cui Change-Id: I320e4879bb3bdd2bb0a0267435560ed86df74e4c --- drivers/gpu/drm/amd/amdgpu/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/Kconfig b/drivers/gpu/drm/amd/amdgpu/Kconfig index 56cac2b812a7a..35c20e373b01b 100644 --- a/drivers/gpu/drm/amd/amdgpu/Kconfig +++ b/drivers/gpu/drm/amd/amdgpu/Kconfig @@ -5,7 +5,6 @@ config DRM_AMDGPU depends on DRM && PCI && MMU depends on !UML select FW_LOADER - select DRM_BUDDY select DRM_DISPLAY_DP_HELPER select DRM_DISPLAY_HDMI_HELPER select DRM_DISPLAY_HDCP_HELPER From 3f26b5bcf4f2fd1208e02a3781f44a7902f8703d Mon Sep 17 00:00:00 2001 From: bobzhou2 Date: Wed, 21 Dec 2022 15:58:36 +0800 Subject: [PATCH 0853/1868] drm/amdkcl: wrap code under macro HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE It's caused by d090329b677c2f158755e886199c20b1acf93eb5 "drm/amd/display: save restore hdcp state when display is unplugged from mst hub" Signed-off-by: bobzhou2 Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 8b20145bd5a59..fd499e453b0ca 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -9986,6 +9986,7 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) if (new_con_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) enable_encryption = true; +#ifdef HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE if (aconnector->dc_link && aconnector->dc_sink && aconnector->dc_link->type == dc_connection_mst_branch) { struct hdcp_workqueue *hdcp_work = adev->dm.hdcp_workqueue; @@ -9997,6 +9998,7 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) hdcp_w->content_protection[connector->index] = new_con_state->content_protection; } +#endif if (new_crtc_state && new_crtc_state->mode_changed && new_con_state->content_protection >= DRM_MODE_CONTENT_PROTECTION_DESIRED) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 52832f71193a6..1fb9e4f64f10d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -420,6 +420,7 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector) * plugged back with same display index, its hdcp properties * will be retrieved from hdcp_work within dm_dp_mst_get_modes */ +#ifdef HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE if (aconnector->dc_sink && connector->state) { struct drm_device *dev = connector->dev; struct amdgpu_device *adev = drm_to_adev(dev); @@ -435,6 +436,7 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector) hdcp_w->content_protection[connector->index]; } } +#endif if (aconnector->dc_sink) { amdgpu_dm_update_freesync_caps( From 61ebe717019f58296e6510cd64a4944103ca83cf Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 5 Jan 2023 09:53:55 +0800 Subject: [PATCH 0854/1868] drm/amdkcl: Fix the compile warning when check dma_resv->seq Fix the compile warning when check dma_resv->seq Change-Id: I2580b66ff02a1991ce6e6b1b046365bc9cbfcb01 Signed-off-by: Ma Jun --- drivers/gpu/drm/amd/dkms/Makefile | 2 +- drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index eec0d7868d7c2..9d2de6369b657 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -13,7 +13,7 @@ endif _is_kcl_macro_defined=$(shell grep $1 $(src)/amd/dkms/config/config.h | grep -q "define" && echo "y" || echo "n") ifeq ($(call _is_kcl_macro_defined,HAVE_DMA_RESV_SEQ_BUG),y) -$(error dma_resv->seq is missing., exit...) +$(error dma_resv->seq is missing. exit...) endif ifeq ($(CC), gcc) diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 index 93c6dbc25ae22..8cf888eb3a6b4 100644 --- a/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 @@ -45,7 +45,8 @@ AC_DEFUN([AC_AMDGPU_DMA_RESV_SEQ], [ #include ], [ #if LINUX_VERSION_CODE < KERNEL_VERSION(5, 18, 0) - int this_is_bug = 0; + int this_is_bug; + this_is_bug = 0; #else this_is_not_bug(); #endif From 8ddfcc0a86e19d8cba574d1c5804891508ace884 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 15 Dec 2022 16:58:43 +0800 Subject: [PATCH 0855/1868] drm/amdkcl: Return only kernel fences when iterating dma_resv with DMA_RESV_USAGE_KERNEL Avoid returning unnecessary write fences when extracting DMA_RESV_USAGE_KERNEL fences that could impact performance v2: dma_fence_put kernel_iter when iter restart v3: simplify code Signed-off-by: Leslie Shi Reviewed-by: Flora Cui Reviewed-by: Ma Jun --- drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c | 174 ++++++++++++++++------ include/kcl/kcl_dma-resv.h | 6 + 2 files changed, 132 insertions(+), 48 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c b/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c index 8edf3fccac3e9..dc92c2d10f23d 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c @@ -342,44 +342,6 @@ void dma_resv_replace_fences(struct dma_resv *obj, uint64_t context, } EXPORT_SYMBOL(dma_resv_replace_fences); -/** - * dma_resv_add_excl_fence - Add an exclusive fence. - * @obj: the reservation object - * @fence: the exclusive fence to add - * - * Add a fence to the exclusive slot. @obj must be locked with dma_resv_lock(). - * See also &dma_resv.fence_excl for a discussion of the semantics. - */ -static void dma_resv_add_excl_fence(struct dma_resv *obj, - struct dma_fence *fence) -{ - struct dma_fence *old_fence = dma_resv_excl_fence(obj); - struct dma_fence_chain *chain; - - dma_resv_assert_held(obj); - - if (old_fence && !dma_fence_is_signaled(old_fence)) { - - chain = dma_fence_chain_alloc(); - if (unlikely(!chain)) - pr_err("dma_resv_add_excl_fence OOM\n"); - else { - dma_fence_chain_init(chain, dma_fence_get(old_fence), dma_fence_get(fence), 1); - fence = &chain->base; - } - } else { - dma_fence_get(fence); - } - - - write_seqcount_begin(&obj->seq); - /* write_seqcount_begin provides the necessary memory barrier */ - RCU_INIT_POINTER(obj->fence_excl, fence); - write_seqcount_end(&obj->seq); - - dma_fence_put(old_fence); -} - /** * dma_resv_add_fence - Add a fence to the dma_resv obj * @obj: the reservation object @@ -394,10 +356,28 @@ static void dma_resv_add_excl_fence(struct dma_resv *obj, void dma_resv_add_fence(struct dma_resv *obj, struct dma_fence *fence, enum dma_resv_usage usage) { - if (usage == DMA_RESV_USAGE_WRITE || usage == DMA_RESV_USAGE_KERNEL) - dma_resv_add_excl_fence(obj, fence); - else + struct dma_fence_chain *chain; + + if (usage >= DMA_RESV_USAGE_READ) { dma_resv_add_shared_fence(obj, fence); + return; + } + + chain = dma_fence_chain_alloc(); + if (unlikely(!chain)) { + /* We are out of memory, block as last resort */ + dma_fence_wait(fence, false); + return; + } + dma_fence_chain_init(chain, dma_resv_excl_fence(obj), dma_fence_get(fence), 1); + + /* Store the usage in the user bit to retrieve it later on */ + chain->base.flags |= usage << DMA_FENCE_FLAG_USER_BITS; + + /* Install the exclusive fence manually */ + write_seqcount_begin(&obj->seq); + RCU_INIT_POINTER(obj->fence_excl, &chain->base); + write_seqcount_end(&obj->seq); } EXPORT_SYMBOL(dma_resv_add_fence); @@ -408,6 +388,8 @@ static void dma_resv_iter_restart_unlocked(struct dma_resv_iter *cursor) cursor->seq = read_seqcount_begin(&cursor->obj->seq); cursor->index = -1; cursor->shared_count = 0; + cursor->excl_fence = NULL; + cursor->kernel_iter = NULL; if (cursor->usage >= DMA_RESV_USAGE_READ) { cursor->fences = dma_resv_shared_list(cursor->obj); if (cursor->fences) @@ -422,17 +404,55 @@ static void dma_resv_iter_restart_unlocked(struct dma_resv_iter *cursor) static void dma_resv_iter_walk_unlocked(struct dma_resv_iter *cursor) { struct dma_resv *obj = cursor->obj; + struct dma_fence_chain *chain; + struct dma_fence *f; + enum dma_resv_usage usage; do { /* Drop the reference from the previous round */ dma_fence_put(cursor->fence); if (cursor->index == -1) { - cursor->fence = dma_resv_excl_fence(obj); - cursor->index++; - if (!cursor->fence) - continue; - + if (cursor->usage >= DMA_RESV_USAGE_WRITE) { + cursor->fence = dma_resv_excl_fence(obj); + cursor->index++; + if (!cursor->fence) + continue; + } else { + cursor->fence = NULL; + /* Only return KERNEL fences */ + if (!cursor->excl_fence) { + cursor->excl_fence = dma_resv_excl_fence(obj); + if (!cursor->excl_fence) + break; + + cursor->excl_fence = dma_fence_get(cursor->excl_fence); + cursor->kernel_iter = dma_fence_get(cursor->excl_fence); + } + + while ((f = cursor->kernel_iter) != NULL) { + chain = to_dma_fence_chain(f); + if (!chain) { + dma_fence_put(f); + break; + } + + usage = chain->base.flags >> DMA_FENCE_FLAG_USER_BITS; + if (usage == DMA_RESV_USAGE_KERNEL && !dma_fence_is_signaled(chain->fence)) + cursor->fence = chain->fence; + + cursor->kernel_iter = dma_fence_chain_walk(f); + + if (cursor->fence) + break; + } + + if (!cursor->fence) { + dma_fence_put(cursor->excl_fence); + cursor->excl_fence = NULL; + break; + } + } } else if (!cursor->fences || cursor->index >= cursor->shared_count) { cursor->fence = NULL; @@ -464,10 +484,18 @@ static void dma_resv_iter_walk_unlocked(struct dma_resv_iter *cursor) */ struct dma_fence *dma_resv_iter_first_unlocked(struct dma_resv_iter *cursor) { + bool restart = false; + rcu_read_lock(); do { + if (restart) { + /* drop reference when iter restart */ + dma_fence_put(cursor->excl_fence); + dma_fence_put(cursor->kernel_iter); + } dma_resv_iter_restart_unlocked(cursor); dma_resv_iter_walk_unlocked(cursor); + restart = true; } while (read_seqcount_retry(&cursor->obj->seq, cursor->seq)); rcu_read_unlock(); @@ -493,8 +521,13 @@ struct dma_fence *dma_resv_iter_next_unlocked(struct dma_resv_iter *cursor) cursor->is_restarted = false; restart = read_seqcount_retry(&cursor->obj->seq, cursor->seq); do { - if (restart) + if (restart) { + /* drop reference when iter restart */ + dma_fence_put(cursor->excl_fence); + dma_fence_put(cursor->kernel_iter); + dma_resv_iter_restart_unlocked(cursor); + } dma_resv_iter_walk_unlocked(cursor); restart = true; } while (read_seqcount_retry(&cursor->obj->seq, cursor->seq)); @@ -515,7 +548,9 @@ EXPORT_SYMBOL(dma_resv_iter_next_unlocked); */ struct dma_fence *dma_resv_iter_first(struct dma_resv_iter *cursor) { - struct dma_fence *fence; + struct dma_fence *fence, *f; + struct dma_fence_chain *chain; + enum dma_resv_usage usage; dma_resv_assert_held(cursor->obj); @@ -525,11 +560,34 @@ struct dma_fence *dma_resv_iter_first(struct dma_resv_iter *cursor) else cursor->fences = NULL; + cursor->kernel_iter = NULL; fence = dma_resv_excl_fence(cursor->obj); if (!fence) fence = dma_resv_iter_next(cursor); + else if (cursor->usage == DMA_RESV_USAGE_KERNEL) { + cursor->kernel_iter = dma_fence_get(fence); + fence = NULL; + + while ((f = cursor->kernel_iter) != NULL) { + chain = to_dma_fence_chain(f); + if (!chain) { + dma_fence_put(f); + break; + } + + cursor->kernel_iter = dma_fence_chain_walk(f); + + usage = chain->base.flags >> DMA_FENCE_FLAG_USER_BITS; + if (usage == DMA_RESV_USAGE_KERNEL) + fence = chain->fence; + + if (fence) + break; + } + } cursor->is_restarted = true; + return fence; } EXPORT_SYMBOL_GPL(dma_resv_iter_first); @@ -544,10 +602,30 @@ EXPORT_SYMBOL_GPL(dma_resv_iter_first); struct dma_fence *dma_resv_iter_next(struct dma_resv_iter *cursor) { unsigned int idx; + struct dma_fence *f; + struct dma_fence_chain *chain; + enum dma_resv_usage usage; dma_resv_assert_held(cursor->obj); cursor->is_restarted = false; + + if (cursor->usage == DMA_RESV_USAGE_KERNEL && cursor->kernel_iter != NULL) { + while ((f = cursor->kernel_iter) != NULL) { + chain = to_dma_fence_chain(f); + if (!chain) { + dma_fence_put(f); + break; + } + + cursor->kernel_iter = dma_fence_chain_walk(f); + + usage = chain->base.flags >> DMA_FENCE_FLAG_USER_BITS; + if (usage == DMA_RESV_USAGE_KERNEL && chain->fence) + return chain->fence; + } + } + if (!cursor->fences || cursor->index >= cursor->fences->shared_count) return NULL; diff --git a/include/kcl/kcl_dma-resv.h b/include/kcl/kcl_dma-resv.h index 4fe1fe0afac9d..a6b8ab359aa0d 100644 --- a/include/kcl/kcl_dma-resv.h +++ b/include/kcl/kcl_dma-resv.h @@ -171,6 +171,12 @@ struct dma_resv_iter { /** @is_restarted: true if this is the first returned fence */ bool is_restarted; + + /** @excl_fence: keep a reference to excl_fence when begin iterating kernel fences */ + struct dma_fence *excl_fence; + + /** @kernel_iter: next kernel fence pointer when iterating kernel fences */ + struct dma_fence *kernel_iter; }; #if defined(HAVE_DMA_RESV_SEQCOUNT_WW_MUTEX_T) From 93b76d77721266b4cada6aaa956422ae368651d1 Mon Sep 17 00:00:00 2001 From: Horatio Zhang Date: Tue, 17 Jan 2023 18:23:23 +0800 Subject: [PATCH 0856/1868] drm/amdkcl: add macro DP_128B132B_TRAINING_AUX_RD_INTERVAL and DP_128B132B_SUPPORTED_LINK_RATES It's cause by 'commit 568c97c25cdb ("drm/amd/display: move dp link training logic to link_dp_training")' v6.0-2248-g568c97c25cdb Signed-off-by: Horatio Zhang Reviewed-by: Asher Song --- include/kcl/kcl_drm_dp_helper.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/include/kcl/kcl_drm_dp_helper.h b/include/kcl/kcl_drm_dp_helper.h index cecb273e97d8a..4d3a14e7df501 100644 --- a/include/kcl/kcl_drm_dp_helper.h +++ b/include/kcl/kcl_drm_dp_helper.h @@ -326,4 +326,20 @@ enum drm_dp_phy { # define DP_PSR2_SU_GRANULARITY_REQUIRED (1 << 5) /* eDP 1.4b */ #endif +/* + * v5.15-rc1-244-gba3078dad140 + * drm/dp: add helpers to read link training delays + */ +#ifndef DP_128B132B_TRAINING_AUX_RD_INTERVAL +#define DP_128B132B_TRAINING_AUX_RD_INTERVAL 0x2216 /* 2.0 */ +#endif + +/* + * v5.9-rc5-1031-g7d56927efac7 + * drm/dp: add a number of DP 2.0 DPCD definitions + */ +#ifndef DP_128B132B_SUPPORTED_LINK_RATES +#define DP_128B132B_SUPPORTED_LINK_RATES 0x2215 /* 2.0 */ +#endif + #endif /* _KCL_DRM_DP_HELPER_H_ */ From f98e5ea5be56c9e90efdc88827287e6a3851820c Mon Sep 17 00:00:00 2001 From: bobzhou2 Date: Sun, 29 Jan 2023 10:45:54 +0800 Subject: [PATCH 0857/1868] drm/amdkcl: wrap code under macro HAVE_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT It's caused by 2f21ecf75a71b8aad4e28ce05758fb3f74eff4d1 "drm/amd/display: force connector state when bpc changes during compliance" Signed-off-by: bobzhou2 Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index fd499e453b0ca..9c47d2683783d 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1437,7 +1437,11 @@ static void force_connector_state( mutex_unlock(&connector->dev->mode_config.mutex); mutex_lock(&aconnector->hpd_lock); - drm_kms_helper_connector_hotplug_event(connector); +#ifdef HAVE_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT + drm_kms_helper_connector_hotplug_event(connector); +#else + drm_kms_helper_hotplug_event(connector->dev); +#endif mutex_unlock(&aconnector->hpd_lock); } From 090af78de9826d0ad3ac1f46d1226a20d7dce7c0 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 12 Jan 2023 17:19:59 +0800 Subject: [PATCH 0858/1868] drm/amdkcl: Use debugfs_remove_recursive to remove ttm directory Use debugfs_remove_recursive to remove the /sys/kernel/debug/ttm directory for better compatibility. Becuase debugfs_remove fails on older kernel. Change-Id: Ifcf180d18592a64b038c768c2257200416ef860b Signed-off-by: Ma Jun Reviewed-by: GuChun Chen --- drivers/gpu/drm/ttm/ttm_device.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/ttm/ttm_device.c b/drivers/gpu/drm/ttm/ttm_device.c index 384eac25ccae7..a6dafce0aafc5 100644 --- a/drivers/gpu/drm/ttm/ttm_device.c +++ b/drivers/gpu/drm/ttm/ttm_device.c @@ -59,7 +59,13 @@ static void ttm_global_release(void) goto out; ttm_pool_mgr_fini(); - debugfs_remove(ttm_debugfs_root); + + /* + * Replace the debugfs_remove() with debugfs_remove_recursive() for dkms code. + * debugfs_remove() can't remove the ttm/ directory in legacy kernel. + * So use the debugfs_remove_recursive() here. + */ + debugfs_remove_recursive(ttm_debugfs_root); __free_page(glob->dummy_read_page); memset(glob, 0, sizeof(*glob)); From 1714fbe02e4ec7991bbc285c86a7ab83d94bb53a Mon Sep 17 00:00:00 2001 From: bobzhou2 Date: Sun, 29 Jan 2023 13:23:45 +0800 Subject: [PATCH 0859/1868] drm/amdkcl: wrap code under CONFIG_DRM_AMD_DC_DSC_SUPPORT It's caused by a966a85e03653371931c13496e6a1c7638606666 "drm/amd/display: move eDP panel control logic to link_edp_panel_control" Signed-off-by: bobzhou2 Reviewed-by: Leslie Shi --- .../amd/display/dc/link/protocols/link_edp_panel_control.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c index bf820d2b4dc4a..f85da653bf007 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c @@ -351,10 +351,14 @@ bool edp_is_ilr_optimization_required(struct dc_link *link, req_bw = dc_bandwidth_in_kbps_from_timing(crtc_timing, dc_link_get_highest_encoding_format(link)); +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (!crtc_timing->flags.DSC) edp_decide_link_settings(link, &link_setting, req_bw); else decide_edp_link_settings_with_dsc(link, &link_setting, req_bw, LINK_RATE_UNKNOWN); +#else + decide_edp_link_settings(link, &link_setting, req_bw); +#endif if (link->dpcd_caps.edp_supported_link_rates[link_rate_set] != link_setting.link_rate || lane_count_set.bits.LANE_COUNT_SET != link_setting.lane_count) { From 984c063061fed980de211d916b723e94fefebb92 Mon Sep 17 00:00:00 2001 From: bobzhou2 Date: Sun, 29 Jan 2023 16:02:02 +0800 Subject: [PATCH 0860/1868] drm/amdkcl: add macro DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1 It's caused by d9659c5e79a59264f633fbfec65d76a26bb8a274 "drm/amd/display: Enable AdaptiveSync in DC interface" Signed-off-by: bobzhou2 Reviewed-by: Leslie Shi --- include/kcl/kcl_drm_dp_helper.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/kcl/kcl_drm_dp_helper.h b/include/kcl/kcl_drm_dp_helper.h index 4d3a14e7df501..9f921c3d9db24 100644 --- a/include/kcl/kcl_drm_dp_helper.h +++ b/include/kcl/kcl_drm_dp_helper.h @@ -342,4 +342,12 @@ enum drm_dp_phy { #define DP_128B132B_SUPPORTED_LINK_RATES 0x2215 /* 2.0 */ #endif +/* + * v6.0-2085-gbdf4b00bee5d + * drm/display: Add missing Adaptive Sync DPCD definitions + */ +#ifndef DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1 +#define DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1 0x2214 /* 2.0 E11 */ +#endif + #endif /* _KCL_DRM_DP_HELPER_H_ */ From 36e75c4f392430482085fe2f71a9b7055b9370ec Mon Sep 17 00:00:00 2001 From: bobzhou2 Date: Tue, 31 Jan 2023 14:07:03 +0800 Subject: [PATCH 0861/1868] drm/amdkcl: wrap code under macro HAVE_DRM_DISPLAY_INFO_MONITOR_RANGE It's caused by 92ffdc98c5f71750ab18b01fd4a67c055127e59f "drm/amd/display: Enable Freesync over PCon" Signed-off-by: bobzhou2 Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 9c47d2683783d..ee06d790b6040 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -12491,8 +12491,10 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) freesync_capable = true; +#ifdef HAVE_DRM_DISPLAY_INFO_MONITOR_RANGE connector->display_info.monitor_range.min_vfreq = vsdb_info.min_refresh_rate_hz; connector->display_info.monitor_range.max_vfreq = vsdb_info.max_refresh_rate_hz; +#endif } } From 0dfd6a852da203806e71bbcb81e25c95fa3bd62e Mon Sep 17 00:00:00 2001 From: bobzhou2 Date: Tue, 31 Jan 2023 15:30:55 +0800 Subject: [PATCH 0862/1868] drm/amdkcl: fix redefine issue due to backport.h It's caused by 92ffdc98c5f71750ab18b01fd4a67c055127e59f "drm/amd/display: Enable Freesync over PCon" Redefine fuction get_reg_field_value_ex and FD(reg_field). When backport.h includes dm_services.h, It shouldn't define get_reg_field_value_ex and FD(reg_field). Signed-off-by: bobzhou2 Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/display/dmub/src/dmub_reg.c | 7 +++++++ drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h | 7 +++++++ 2 files changed, 14 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_reg.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_reg.c index ca0c8a54b635e..88bf59ee5fea7 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_reg.c +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_reg.c @@ -63,11 +63,18 @@ static void set_reg_field_values(struct dmub_reg_value_masks *field_value_mask, } } +/* + * v6.0-2372-g92ffdc98c5f7 + * ("drm/amd/display: Enable Freesync over PCon") + * verify __DM_SERVICES_H__ to fix the redefine function declaration for backport.h. + */ +#ifndef __DM_SERVICES_H__ static inline uint32_t get_reg_field_value_ex(uint32_t reg_value, uint32_t mask, uint8_t shift) { return (mask & reg_value) >> shift; } +#endif void dmub_reg_update(struct dmub_srv *srv, uint32_t addr, int n, uint8_t shift1, uint32_t mask1, uint32_t field_value1, ...) diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h index b314e60714ee2..10a87a277be22 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_reg.h @@ -50,7 +50,14 @@ struct dmub_srv; #define REG(reg) (REGS)->offset.reg +/* + * v6.0-2372-g92ffdc98c5f7 + * ("drm/amd/display: Enable Freesync over PCon") + * verify __DM_SERVICES_H__ to fix the redefine function declaration for backport.h. + */ +#ifndef __DM_SERVICES_H__ #define FD(reg_field) (REGS)->shift.reg_field, (REGS)->mask.reg_field +#endif #define FN(reg_name, field) FD(reg_name##__##field) From 7bd1f5e36ee333e7d844f786e99607135b82d2b1 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 15 Dec 2022 23:52:10 +0800 Subject: [PATCH 0863/1868] drm/amdkcl: kcl-cleanup HAVE_DRM_DEV_DBG Since the function drm_dev_dbg() is available on oldest supported OS REL7.9, remove drm_dev_dbg check. Signed-off-by: Asher Song Reviewed-by: Flora Cui Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c | 25 ---------------------- drivers/gpu/drm/amd/dkms/config/config.h | 3 --- drivers/gpu/drm/amd/dkms/m4/drm_dev_dbg.m4 | 11 ---------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - include/kcl/kcl_drm_print.h | 4 ---- 5 files changed, 44 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_dev_dbg.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c index 9e0c95502367c..95e75be1d5ee8 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c @@ -59,31 +59,6 @@ void __drm_printfn_debug(struct drm_printer *p, struct va_format *vaf) EXPORT_SYMBOL(__drm_printfn_debug); #endif -#if !defined(HAVE_DRM_DEV_DBG) -void drm_dev_dbg(const struct device *dev, int category, - const char *format, ...) -{ - struct va_format vaf; - va_list args; - - if (!drm_debug_enabled(category)) - return; - - va_start(args, format); - vaf.fmt = format; - vaf.va = &args; - - if (dev) - dev_printk(KERN_DEBUG, dev, "[" DRM_NAME ":%ps] %pV", - __builtin_return_address(0), &vaf); - else - printk(KERN_DEBUG "[" DRM_NAME ":%ps] %pV", - __builtin_return_address(0), &vaf); - - va_end(args); -} -EXPORT_SYMBOL(drm_dev_dbg); -#endif #if !defined(HAVE_DRM_ERR_MACRO) void kcl_drm_err(const char *format, ...) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index c39b6ce270174..7df0009c9f4ff 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -307,9 +307,6 @@ /* struct drm_device has pdev member */ /* #undef HAVE_DRM_DEVICE_PDEV */ -/* drm_dev_dbg() is available */ -#define HAVE_DRM_DEV_DBG 1 - /* drm_dev_enter() is available */ #define HAVE_DRM_DEV_ENTER 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dev_dbg.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dev_dbg.m4 deleted file mode 100644 index dfcc85e60e4bf..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm_dev_dbg.m4 +++ /dev/null @@ -1,11 +0,0 @@ -dnl # -dnl # v4.16-rc1-493-gdb8708649258 -dnl # drm: Reduce object size of DRM_DEV_ uses -dnl # -AC_DEFUN([AC_AMDGPU_DRM_DEV_DBG], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([drm_dev_dbg], [drivers/gpu/drm/drm_print.c], [ - AC_DEFINE(HAVE_DRM_DEV_DBG, 1, [drm_dev_dbg() is available]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 5d7b36afbf7b1..bef0572b5d72b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -90,7 +90,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_STRUCT_DRM_DEVICE AC_AMDGPU_DRM_DRIVER_FEATURE AC_AMDGPU___DRM_ATOMIC_HELPER_CRTC_RESET - AC_AMDGPU_DRM_DEV_DBG AC_AMDGPU_PCI_PR3_PRESENT AC_AMDGPU_KTHREAD_USE_MM AC_AMDGPU_DRM_FB_HELPER_FILL_INFO diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index 80d51e8721236..a726abd73190d 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -153,10 +153,6 @@ void kcl_drm_err(const char *format, ...); } while (0) #endif -#if !defined(HAVE_DRM_DEV_DBG) -void drm_dev_dbg(const struct device *dev, int category, const char *format, ...); -#endif - #if !defined(drm_dbg_atomic) #define drm_dbg_atomic(drm, fmt, ...) \ drm_dev_dbg((drm)->dev, DRM_UT_ATOMIC, fmt, ##__VA_ARGS__) From d881a56bdb6297ae4d4282e9203db0bdfffc0b0f Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 12 Dec 2022 16:34:58 +0800 Subject: [PATCH 0864/1868] drm/amdkcl: test whether MEMORY_DEVICE_COHERENT and MIGRATE_VMA_SELECT_DEVICE_PRIVATE is defined It's caused by 8dd9f5d2d0e4c14387e41c5231c3cff5a474b561 drm/amdkfd: add SPM support for SVM Signed-off-by: Felix Kuehling Signed-off-by: Asher Song Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 2 ++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/memremap-enum.m4 | 22 ++++++++++++++++++++ 4 files changed, 28 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/memremap-enum.m4 diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c index c449bb9ea5ba1..aed57b9d47403 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@ -723,9 +723,11 @@ svm_migrate_vma_to_ram(struct kfd_node *node, struct svm_range *prange, migrate.end = end; #ifdef HAVE_MIGRATE_VMA_PGMAP_OWNER migrate.pgmap_owner = SVM_ADEV_PGMAP_OWNER(adev); +#ifdef HAVE_DEVICE_COHERENT if (adev->gmc.xgmi.connected_to_cpu) migrate.flags = MIGRATE_VMA_SELECT_DEVICE_COHERENT; else +#endif migrate.flags = MIGRATE_VMA_SELECT_DEVICE_PRIVATE; #elif defined(HAVE_DEV_PAGEMAP_OWNER) migrate.src_owner = SVM_ADEV_PGMAP_OWNER(adev); diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 7df0009c9f4ff..43bdddd655540 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -80,6 +80,9 @@ /* devcgroup_check_permission() is available */ #define HAVE_DEVCGROUP_CHECK_PERMISSION 1 +/* MEMORY_DEVICE_COHERENT is availablea */ +#define HAVE_DEVICE_COHERENT 1 + /* devm_memremap_pages() wants struct dev_pagemap */ #define HAVE_DEVM_MEMREMAP_PAGES_DEV_PAGEMAP 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index bef0572b5d72b..0cb00b1709b69 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -221,6 +221,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_PORT_FULL_PBN AC_AMDGPU_ACPI_VIDEO_FUNCS AC_AMDGPU_DRM_PLANE_HELPER_FUNCS + AC_AMDGPU_MEMORY_DEVICE_COHERENT AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/memremap-enum.m4 b/drivers/gpu/drm/amd/dkms/m4/memremap-enum.m4 new file mode 100644 index 0000000000000..786ce2c5590ac --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/memremap-enum.m4 @@ -0,0 +1,22 @@ +dnl # +dnl # commit f25cbb7a95a24ff9a2a3bebd308e303942ae6b2c +dnl # mm: add zone device coherent type memory support +dnl # +dnl # commit dd19e6d8ffaa1289d75d7833de97faf1b6b2c8e4 +dnl # mm: add device coherent vma selection for memory migration +dnl # +AC_DEFUN([AC_AMDGPU_MEMORY_DEVICE_COHERENT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + int v = MEMORY_DEVICE_COHERENT; + int w = MIGRATE_VMA_SELECT_DEVICE_COHERENT; + ], [ + AC_DEFINE(HAVE_DEVICE_COHERENT, 1, + [MEMORY_DEVICE_COHERENT is availablea]) + ]) + ]) +]) + From 1a9f09cda4ef6fe3674c0d8393993d73e9a60620 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 2 Feb 2023 11:09:33 +0800 Subject: [PATCH 0865/1868] drm/amdkcl: wrap code under macro HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS It's caused by 4d07b0bc403403438d9cf88450506240c5faf92f "drm/display/dp_mst: Move all payload info into the atomic state" This patch is used to implent legacy payload code Signed-off-by: Asher Song Reviewed-by: Leslie Shi --- .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 161 +++++++++++++++++- drivers/gpu/drm/amd/dkms/config/config.h | 3 + .../amd/dkms/m4/drm-dp-mst-topology-state.m4 | 25 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 187 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index 59d8a0b29edd6..329d12391c683 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -220,6 +220,7 @@ enum dc_edid_status dm_helpers_parse_edid_caps( return result; } +#if defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS) static void fill_dc_mst_payload_table_from_drm(struct dc_link *link, bool enable, @@ -270,6 +271,44 @@ fill_dc_mst_payload_table_from_drm(struct dc_link *link, /* Overwrite the old table */ *table = new_table; } +#else +static void +fill_dc_mst_payload_table_from_drm(struct amdgpu_dm_connector *aconnector, + struct dc_dp_mst_stream_allocation_table *proposed_table) +{ + int i; + struct drm_dp_mst_topology_mgr *mst_mgr = + &aconnector->mst_port->mst_mgr; + + mutex_lock(&mst_mgr->payload_lock); + + proposed_table->stream_count = 0; + + /* number of active streams */ + for (i = 0; i < mst_mgr->max_payloads; i++) { + if (mst_mgr->payloads[i].num_slots == 0) + break; /* end of vcp_id table */ + + ASSERT(mst_mgr->payloads[i].payload_state != + DP_PAYLOAD_DELETE_LOCAL); + + if (mst_mgr->payloads[i].payload_state == DP_PAYLOAD_LOCAL || + mst_mgr->payloads[i].payload_state == + DP_PAYLOAD_REMOTE) { + + struct dc_dp_mst_stream_allocation *sa = + &proposed_table->stream_allocations[ + proposed_table->stream_count]; + + sa->slot_count = mst_mgr->payloads[i].num_slots; + sa->vcp_id = mst_mgr->proposed_vcpis[i]->vcpi; + proposed_table->stream_count++; + } + } + + mutex_unlock(&mst_mgr->payload_lock); +} +#endif /*HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS*/ void dm_helpers_dp_update_branch_info( struct dc_context *ctx, @@ -318,9 +357,26 @@ bool dm_helpers_dp_mst_write_payload_allocation_table( bool enable) { struct amdgpu_dm_connector *aconnector; + struct drm_dp_mst_topology_mgr *mst_mgr; +#if defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS) struct drm_dp_mst_topology_state *mst_state; struct drm_dp_mst_atomic_payload *target_payload, *new_payload, old_payload; - struct drm_dp_mst_topology_mgr *mst_mgr; +#else +#if defined(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE) + struct dm_connector_state *dm_conn_state; +#endif + struct drm_dp_mst_port *mst_port; +#if !defined(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE) + int slots = 0; +#endif + bool ret; +#if !defined(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE) + int clock; + int bpp = 0; + int pbn = 0; +#endif + u8 link_coding_cap = DP_8b_10b_ENCODING; +#endif /*HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS*/ aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; /* Accessing the connector state is required for vcpi_slots allocation @@ -333,6 +389,7 @@ bool dm_helpers_dp_mst_write_payload_allocation_table( return false; mst_mgr = &aconnector->mst_root->mst_mgr; +#if defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS) mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state); new_payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port); @@ -356,7 +413,91 @@ bool dm_helpers_dp_mst_write_payload_allocation_table( * sequence. copy DRM MST allocation to dc */ fill_dc_mst_payload_table_from_drm(stream->link, enable, target_payload, proposed_table); +#else +#if defined(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE) + dm_conn_state = to_dm_connector_state(aconnector->base.state); +#endif + if (!mst_mgr->mst_state) + return false; + + mst_port = aconnector->port; + +#if defined(CONFIG_DRM_AMD_DC_DCN) + link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link); +#endif + if (enable) { + +#if !defined(HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE) + clock = stream->timing.pix_clk_100hz / 10; + + switch (stream->timing.display_color_depth) { + + case COLOR_DEPTH_666: + bpp = 6; + break; + case COLOR_DEPTH_888: + bpp = 8; + break; + case COLOR_DEPTH_101010: + bpp = 10; + break; + case COLOR_DEPTH_121212: + bpp = 12; + break; + case COLOR_DEPTH_141414: + bpp = 14; + break; + case COLOR_DEPTH_161616: + bpp = 16; + break; + default: + ASSERT(bpp != 0); + break; + } + + bpp = bpp * 3; + + /* TODO need to know link rate */ + pbn = drm_dp_calc_pbn_mode(clock, bpp, false); + + slots = drm_dp_find_vcpi_slots(mst_mgr, pbn); + ret = drm_dp_mst_allocate_vcpi(mst_mgr, mst_port, pbn, +#ifdef HAVE_DRM_DP_MST_ALLOCATE_VCPI_P_P_I_I + slots); +#else + &slots); +#endif /* HAVE_DRM_DP_MST_ALLOCATE_VCPI_P_P_I_I */ +#else + ret = drm_dp_mst_allocate_vcpi(mst_mgr, mst_port, + dm_conn_state->pbn, +#ifdef HAVE_DRM_DP_MST_ALLOCATE_VCPI_P_P_I_I + dm_conn_state->vcpi_slots); +#else + &dm_conn_state->vcpi_slots); +#endif /* HAVE_DRM_DP_MST_ALLOCATE_VCPI_P_P_I_I */ +#endif + if (!ret) + return false; + + } else { + drm_dp_mst_reset_vcpi_slots(mst_mgr, mst_port); + } + + /* It's OK for this to fail */ +#ifdef HAVE_DRM_DP_UPDATE_PAYLOAD_PART1_START_SLOT_ARG + drm_dp_update_payload_part1(mst_mgr, (link_coding_cap == DP_CAP_ANSI_128B132B) ? 0:1); +#else + drm_dp_update_payload_part1(mst_mgr); +#endif + + /* mst_mgr->->payloads are VC payload notify MST branch using DPCD or + * AUX message. The sequence is slot 1-63 allocated sequence for each + * stream. AMD ASIC stream slot allocation should follow the same + * sequence. copy DRM MST allocation to dc */ + + fill_dc_mst_payload_table_from_drm(aconnector, proposed_table); +#endif return true; } @@ -411,9 +552,13 @@ void dm_helpers_dp_mst_send_payload_allocation( const struct dc_stream_state *stream) { struct amdgpu_dm_connector *aconnector; +#if defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS) struct drm_dp_mst_topology_state *mst_state; - struct drm_dp_mst_topology_mgr *mst_mgr; struct drm_dp_mst_atomic_payload *new_payload; +#else + struct drm_dp_mst_port *mst_port; +#endif + struct drm_dp_mst_topology_mgr *mst_mgr; enum mst_progress_status set_flag = MST_ALLOCATE_NEW_PAYLOAD; enum mst_progress_status clr_flag = MST_CLEAR_ALLOCATED_PAYLOAD; int ret = 0; @@ -424,11 +569,21 @@ void dm_helpers_dp_mst_send_payload_allocation( return; mst_mgr = &aconnector->mst_root->mst_mgr; +#if defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS) mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state); new_payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port); - ret = drm_dp_add_payload_part2(mst_mgr, new_payload); +#else + mst_port = aconnector->port; + if (!mst_mgr->mst_state) + return; +#endif +#if defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS) + ret = drm_dp_add_payload_part2(mst_mgr, new_payload); +#else + ret = drm_dp_update_payload_part2(mst_mgr); +#endif if (ret) { amdgpu_dm_set_mst_status(&aconnector->mst_status, set_flag, false); diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 43bdddd655540..9804fc6da7ee1 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -457,6 +457,9 @@ /* drm_dp_mst_topology_mgr_resume() wants 2 args */ #define HAVE_DRM_DP_MST_TOPOLOGY_MGR_RESUME_2ARGS 1 +/* struct drm_dp_mst_topology_state has member payloads */ +#define HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS 1 + /* struct drm_dp_mst_topology_state has member total_avail_slots */ #define HAVE_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 index 646dc3b137f68..8e57e77b7a138 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 @@ -22,3 +22,28 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS], [ ]) ]) + +dnl # +dnl # commit 8366f01fb15a54281c193658d1a916f6f2d5eb1e +dnl # drm/display/dp_mst: Move all payload info into the atomic state +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) + #include + #else + #include + #endif + ], [ + struct drm_dp_mst_topology_state * mst_state = NULL; + struct list_head payloads; + payloads = mst_state->payloads; + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS, 1, + [struct drm_dp_mst_topology_state has member payloads]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 0cb00b1709b69..0544735ebea3a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -222,6 +222,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_ACPI_VIDEO_FUNCS AC_AMDGPU_DRM_PLANE_HELPER_FUNCS AC_AMDGPU_MEMORY_DEVICE_COHERENT + AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From dfb65ed78a21c95438f681993868ab7e90e1b48c Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 1 Feb 2023 11:15:13 +0800 Subject: [PATCH 0866/1868] drm/amdkcl:wrap code under macro HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV It's caused by 4d07b0bc403403438d9cf88450506240c5faf92f "drm/display/dp_mst: Move all payload info into the atomic state" Signed-off-by: Asher Song Reviewed-by: Leslie Shi --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 +++++ .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 22 +++++++++++++-- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../amd/dkms/m4/drm-dp-mst-topology-state.m4 | 27 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 5 files changed, 57 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index ee06d790b6040..f22c92c23956d 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -7783,7 +7783,9 @@ static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; struct drm_dp_mst_topology_mgr *mst_mgr; struct drm_dp_mst_port *mst_port; +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV struct drm_dp_mst_topology_state *mst_state; +#endif enum dc_color_depth color_depth; int clock, bpp = 0; bool is_y420 = false; @@ -7797,11 +7799,13 @@ static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, if (!crtc_state->connectors_changed && !crtc_state->mode_changed) return 0; +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV mst_state = drm_atomic_get_mst_topology_state(state, mst_mgr); if (IS_ERR(mst_state)) return PTR_ERR(mst_state); mst_state->pbn_div.full = dfixed_const(dm_mst_get_pbn_divider(aconnector->mst_root->dc_link)); +#endif if (!state->duplicated) { int max_bpc = conn_state->max_requested_bpc; @@ -11922,6 +11926,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, lock_and_validation_needed = true; } +#ifndef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS /* set the slot info for each mst_state based on the link encoding format */ @@ -11944,6 +11949,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, drm_connector_list_iter_end(&iter); } #endif +#endif #endif /** * Streams and planes are reset when there are changes that affect diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 1fb9e4f64f10d..c9310da5f7580 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -1062,11 +1062,18 @@ static int increase_dsc_bpp(struct drm_atomic_state *state, int min_initial_slack; int next_index; int remaining_to_increase = 0; +#ifndef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV + int pbn_per_timeslot; +#endif int link_timeslots_used; int fair_pbn_alloc; int ret = 0; uint16_t fec_overhead_multiplier_x1000 = get_fec_overhead_multiplier(dc_link); +#ifndef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV + pbn_per_timeslot = dm_mst_get_pbn_divider(dc_link); +#endif + for (i = 0; i < count; i++) { if (vars[i + k].dsc_enabled) { initial_slack[i] = @@ -1097,10 +1104,21 @@ static int increase_dsc_bpp(struct drm_atomic_state *state, link_timeslots_used = 0; for (i = 0; i < count; i++) - link_timeslots_used += DIV_ROUND_UP(vars[i + k].pbn, dfixed_trunc(mst_state->pbn_div)); + link_timeslots_used += DIV_ROUND_UP(vars[i + k].pbn, +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV + dfixed_trunc(mst_state->pbn_div) +#else + pbn_per_timeslot +#endif + ); fair_pbn_alloc = - (63 - link_timeslots_used) / remaining_to_increase * dfixed_trunc(mst_state->pbn_div); + (63 - link_timeslots_used) / remaining_to_increase * +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV + dfixed_trunc(mst_state->pbn_div); +#else + pbn_per_timeslot; +#endif if (initial_slack[next_index] > fair_pbn_alloc) { vars[next_index].pbn += fair_pbn_alloc; diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 9804fc6da7ee1..7ca5449092713 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -460,6 +460,9 @@ /* struct drm_dp_mst_topology_state has member payloads */ #define HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS 1 +/* struct drm_dp_mst_topology_state has member pbn_div */ +#define HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV 1 + /* struct drm_dp_mst_topology_state has member total_avail_slots */ #define HAVE_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 index 8e57e77b7a138..717d2d88653c3 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 @@ -47,3 +47,30 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS], [ ]) ]) ]) + + +dnl # +dnl # commit v5.19-rc6-1771-g4d07b0bc4034 +dnl # drm/display/dp_mst: Move all payload info into the atomic state +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) + #include + #else + #include + #endif + ], [ + struct drm_dp_mst_topology_state * mst_state = NULL; + int pbn_div; + pbn_div = mst_state->pbn_div; + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV, 1, + [struct drm_dp_mst_topology_state has member pbn_div]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 0544735ebea3a..5709594b7210d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -223,6 +223,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_PLANE_HELPER_FUNCS AC_AMDGPU_MEMORY_DEVICE_COHERENT AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS + AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 210269a9a45b802df8239235f59a3c1a06d2a8bd Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 2 Feb 2023 13:27:02 +0800 Subject: [PATCH 0867/1868] drm/amdkcl: wrap code under macro HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS It's caused by 4d07b0bc403403438d9cf88450506240c5faf92f "drm/display/dp_mst: Move all payload info into the atomic state" Signed-off-by: Asher Song Reviewed-by: Leslie Shi Reviewed-by: Flora Cui --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 ++- .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 54 +++++++++++++++---- drivers/gpu/drm/amd/dkms/config/config.h | 2 +- .../drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 | 8 ++- .../backport/kcl_drm_dp_mst_helper_backport.h | 2 +- 5 files changed, 59 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index f22c92c23956d..cc6a8eba6f74b 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -7822,7 +7822,11 @@ static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, dm_new_connector_state->vcpi_slots = drm_dp_atomic_find_time_slots(state, mst_mgr, mst_port, - dm_new_connector_state->pbn); + dm_new_connector_state->pbn +#ifndef HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS + , dm_mst_get_pbn_divider(aconnector->dc_link) +#endif + ); if (dm_new_connector_state->vcpi_slots < 0) { DRM_DEBUG_ATOMIC("failed finding vcpi slots: %d\n", (int)dm_new_connector_state->vcpi_slots); return dm_new_connector_state->vcpi_slots; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index c9310da5f7580..9cf3b6525ff15 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -1125,7 +1125,11 @@ static int increase_dsc_bpp(struct drm_atomic_state *state, ret = drm_dp_atomic_find_time_slots(state, params[next_index].port->mgr, params[next_index].port, - vars[next_index].pbn); + vars[next_index].pbn +#ifndef HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS + , pbn_per_timeslot +#endif + ); if (ret < 0) return ret; @@ -1137,7 +1141,11 @@ static int increase_dsc_bpp(struct drm_atomic_state *state, ret = drm_dp_atomic_find_time_slots(state, params[next_index].port->mgr, params[next_index].port, - vars[next_index].pbn); + vars[next_index].pbn +#ifndef HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS + , pbn_per_timeslot +#endif + ); if (ret < 0) return ret; } @@ -1146,7 +1154,11 @@ static int increase_dsc_bpp(struct drm_atomic_state *state, ret = drm_dp_atomic_find_time_slots(state, params[next_index].port->mgr, params[next_index].port, - vars[next_index].pbn); + vars[next_index].pbn +#ifndef HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS + , pbn_per_timeslot +#endif + ); if (ret < 0) return ret; @@ -1158,7 +1170,11 @@ static int increase_dsc_bpp(struct drm_atomic_state *state, ret = drm_dp_atomic_find_time_slots(state, params[next_index].port->mgr, params[next_index].port, - vars[next_index].pbn); + vars[next_index].pbn +#ifndef HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS + , pbn_per_timeslot +#endif + ); if (ret < 0) return ret; } @@ -1218,7 +1234,11 @@ static int try_disable_dsc(struct drm_atomic_state *state, ret = drm_dp_atomic_find_time_slots(state, params[next_index].port->mgr, params[next_index].port, - vars[next_index].pbn); + vars[next_index].pbn +#ifndef HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS + , dm_mst_get_pbn_divider(dc_link) +#endif + ); if (ret < 0) return ret; @@ -1231,7 +1251,11 @@ static int try_disable_dsc(struct drm_atomic_state *state, ret = drm_dp_atomic_find_time_slots(state, params[next_index].port->mgr, params[next_index].port, - vars[next_index].pbn); + vars[next_index].pbn +#ifndef HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS + , dm_mst_get_pbn_divider(dc_link) +#endif + ); if (ret < 0) return ret; } @@ -1325,7 +1349,11 @@ static int compute_mst_dsc_configs_for_link(struct drm_atomic_state *state, vars[i + k].dsc_enabled = false; vars[i + k].bpp_x16 = 0; ret = drm_dp_atomic_find_time_slots(state, params[i].port->mgr, params[i].port, - vars[i + k].pbn); + vars[i + k].pbn +#ifndef HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS + , dm_mst_get_pbn_divider(dc_link) +#endif + ); if (ret < 0) return ret; } @@ -1344,7 +1372,11 @@ static int compute_mst_dsc_configs_for_link(struct drm_atomic_state *state, vars[i + k].dsc_enabled = true; vars[i + k].bpp_x16 = params[i].bw_range.min_target_bpp_x16; ret = drm_dp_atomic_find_time_slots(state, params[i].port->mgr, - params[i].port, vars[i + k].pbn); + params[i].port, vars[i + k].pbn +#ifndef HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS + , dm_mst_get_pbn_divider(dc_link) +#endif + ); if (ret < 0) return ret; } else { @@ -1352,7 +1384,11 @@ static int compute_mst_dsc_configs_for_link(struct drm_atomic_state *state, vars[i + k].dsc_enabled = false; vars[i + k].bpp_x16 = 0; ret = drm_dp_atomic_find_time_slots(state, params[i].port->mgr, - params[i].port, vars[i + k].pbn); + params[i].port, vars[i + k].pbn +#ifndef HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS + , dm_mst_get_pbn_divider(dc_link) +#endif + ); if (ret < 0) return ret; } diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 7ca5449092713..dcbe08cc190ef 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -368,7 +368,7 @@ /* #undef HAVE_DRM_DISPLAY_INFO_MAX_DSC_BPP */ /* drm_dp_atomic_find_time_slots() is available */ -/* #undef HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS */ +#define HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS 1 /* drm_dp_mst_atomic_setup_commit() is available */ /* #undef HAVE_DRM_DP_ATOMIC_SETUP_COMMIT */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 index a67dc29ccbeb2..f19d5bf4ea976 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 @@ -51,10 +51,16 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FIND_TIME_SLOTS], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) + #include + #else #include + #endif ],[ int ret; - ret = drm_dp_atomic_find_time_slots(NULL, NULL, NULL, 0, 0); + ret = drm_dp_atomic_find_time_slots(NULL, NULL, NULL, 0); ],[ AC_DEFINE(HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS, 1, [drm_dp_atomic_find_time_slots() is available]) diff --git a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h index 6a5e6961228bb..edac58606beb9 100644 --- a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h +++ b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h @@ -72,7 +72,7 @@ int _kcl_drm_dp_atomic_find_time_slots(struct drm_atomic_state *state, struct drm_dp_mst_port *port, int pbn, int pbn_div) { - return 0; + return drm_dp_atomic_find_vcpi_slots(state, mgr, port, pbn, pbn_div); } #define drm_dp_atomic_find_time_slots _kcl_drm_dp_atomic_find_time_slots #endif From 945047b46a80a7f91b4999dab42ea48735471797 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 1 Feb 2023 11:36:14 +0800 Subject: [PATCH 0868/1868] drm/amdkcl: wrap code under marco HAVE_DRM_DP_MST_TOPOLOGY_MGR_INIT_MAX_LANE_COUNT It's caused by 4d07b0bc403403438d9cf88450506240c5faf92f "drm/display/dp_mst: Move all payload info into the atomic state" Signed-off-by: Asher Song Reviewed-by: Flora Cui --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 7 ++++++- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 9cf3b6525ff15..d4ec6d5368044 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -912,7 +912,12 @@ void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm, dc_link_dp_get_max_link_enc_cap(aconnector->dc_link, &max_link_enc_cap); aconnector->mst_mgr.cbs = &dm_mst_cbs; drm_dp_mst_topology_mgr_init(&aconnector->mst_mgr, adev_to_drm(dm->adev), - &aconnector->dm_dp_aux.aux, 16, 4, aconnector->connector_id); + &aconnector->dm_dp_aux.aux, 16, 4, +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_MGR_INIT_MAX_LANE_COUNT + max_link_enc_cap.lane_count, + drm_dp_bw_code_to_link_rate(max_link_enc_cap.link_rate), +#endif + aconnector->connector_id); drm_connector_attach_dp_subconnector_property(&aconnector->base); } diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index dcbe08cc190ef..e1c812cfd0b94 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -454,6 +454,9 @@ /* drm_dp_mst_topology_mgr_init() wants drm_device arg */ #define HAVE_DRM_DP_MST_TOPOLOGY_MGR_INIT_DRM_DEV 1 +/* drm_dp_mst_topology_mgr_init() has max_lane_count and max_link_rate */ +/* #undef HAVE_DRM_DP_MST_TOPOLOGY_MGR_INIT_MAX_LANE_COUNT */ + /* drm_dp_mst_topology_mgr_resume() wants 2 args */ #define HAVE_DRM_DP_MST_TOPOLOGY_MGR_RESUME_2ARGS 1 From 9b1c28bf85d5bc27a3fbe5ea308650cc544f303b Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 2 Feb 2023 14:17:39 +0800 Subject: [PATCH 0869/1868] drm/amdkcl: check drm_dp_mst_atomic_enable_dsc whether has four arguments It's caused by 4d07b0bc403403438d9cf88450506240c5faf92f "drm/display/dp_mst: Move all payload info into the atomic state" Signed-off-by: Asher Song Reviewed-by: Leslie Shi --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 12 ++++++++-- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 | 22 +++++++++++++++++++ 3 files changed, 35 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index cc6a8eba6f74b..c93474ccd8273 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -7902,14 +7902,22 @@ static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state, dm_conn_state->vcpi_slots = slot_num; ret = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, - dm_conn_state->pbn, false); + dm_conn_state->pbn, +#ifdef HAVE_DRM_DP_MST_ATOMIC_ENABLE_DSC_WITH_5_ARGS + 0, +#endif + false); if (ret < 0) return ret; continue; } - vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, pbn, true); + vcpi = drm_dp_mst_atomic_enable_dsc(state, aconnector->mst_output_port, pbn, +#ifdef HAVE_DRM_DP_MST_ATOMIC_ENABLE_DSC_WITH_5_ARGS + 0, +#endif + true); if (vcpi < 0) return vcpi; diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index e1c812cfd0b94..2e14b125d76e1 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -421,6 +421,9 @@ /* drm_dp_mst_atomic_enable_dsc() is available */ #define HAVE_DRM_DP_MST_ATOMIC_ENABLE_DSC 1 +/* drm_dp_mst_atomic_enable_dsc() wants 5args */ +/* #undef HAVE_DRM_DP_MST_ATOMIC_ENABLE_DSC_WITH_5_ARGS */ + /* drm_dp_mst_detect_port() wants p,p,p,p args */ #define HAVE_DRM_DP_MST_DETECT_PORT_PPPP 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 index 806158f1562a8..0019f393b38f3 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 @@ -17,6 +17,28 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_MST_ATOMIC_ENABLE_DSC], [ ], [drm_dp_mst_atomic_enable_dsc], [drivers/gpu/drm/drm_dp_mst_topology.c], [ AC_DEFINE(HAVE_DRM_DP_MST_ATOMIC_ENABLE_DSC, 1, [drm_dp_mst_atomic_enable_dsc() is available]) + AC_DEFINE(HAVE_DRM_DP_MST_ATOMIC_ENABLE_DSC_WITH_5_ARGS, 1, + [drm_dp_mst_atomic_enable_dsc() wants 5args]) + ],[ + dnl # + dnl # commit 4d07b0bc403403438d9cf88450506240c5faf92f + dnl # drm/display/dp_mst: Move all payload info into the atomic state + dnl # + AC_KERNEL_TRY_COMPILE([ + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) + #include + #else + #include + #endif + ], [ + int vcpi; + vcpi = drm_dp_mst_atomic_enable_dsc(NULL, NULL, 0, false); + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_ATOMIC_ENABLE_DSC, 1, + [drm_dp_atomic_find_vcpi_slots() is available]) + ]) ]) ]) ]) From 4d15fcf39f603dc5506e64006bc8bdf81e3b4164 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Fri, 6 Jan 2023 09:23:42 +0800 Subject: [PATCH 0870/1868] drm/amdkcl: Check the gcc and kernel version before the compilation starts Check the gcc and kernel version before the compilation starts. This is mainly used for some special application scenarios. For example, Some customers use kernel 5.4 and gcc 4.8.5 This will cause the compilations failure. So we check this case and provide a hint. Change-Id: I448d9c289ea66da701291df42bed504ed4dfb782 Signed-off-by: Ma Jun Suggested-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/dkms/Makefile | 52 ++++++++++++++++++++----------- 1 file changed, 34 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 9d2de6369b657..2e8db344899bd 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -1,27 +1,24 @@ -ifndef CONFIG_DRM -$(error CONFIG_DRM disabled, exit...) -endif - -ifeq (y,$(CONFIG_DRM_AMDGPU)) -$(error DRM_AMDGPU is built-in, exit...) -endif - -ifndef CONFIG_KALLSYMS -$(error CONFIG_KALLSYMS disabled, kallsyms_lookup_name() is absent, exit...) -endif - -_is_kcl_macro_defined=$(shell grep $1 $(src)/amd/dkms/config/config.h | grep -q "define" && echo "y" || echo "n") - -ifeq ($(call _is_kcl_macro_defined,HAVE_DMA_RESV_SEQ_BUG),y) -$(error dma_resv->seq is missing. exit...) -endif - ifeq ($(CC), gcc) GCCMAJ=$(shell echo __GNUC__ | $(CC) -E -x c - | tail -n 1) GCCMIN=$(shell echo __GNUC_MINOR__ | $(CC) -E -x c - | tail -n 1) GCCPAT=$(shell echo __GNUC_PATCHLEVEL__ | $(CC) -E -x c - | tail -n 1) # CONFIG_GCC_VERSION returns x.xx.xx as the version format GCCSTR=$(shell printf "%d%02d%02d" $(GCCMAJ) $(GCCMIN) $(GCCPAT)) + +KERNEL_MAJ=$(VERSION) +KERNEL_PATCHLEVEL=$(PATCHLEVEL) +KERNEL_SUBLEVEL=$(SUBLEVEL) +KERNEL_VER=$(shell printf "%d%02d%02d" $(KERNEL_MAJ) $(KERNEL_PATCHLEVEL), $(KERNEL_SUBLEVEL)) + +kernel-version = $(shell [ $(KERNEL_VER)0 $(1) $(2)000 ] && echo $(3) || echo $(4)) + +# gcc 4.8.5 is too old for kernel >= 5.4, which will cause the compile failure. +ifeq ($(call cc-ifversion, -le, 0408, y), y) +ifeq ($(call kernel-version, -ge, 0504, y), y) +$(error "The GCC is too old for this kernel, please update the GCC to higher than 9.3") +endif +endif + ifdef CONFIG_CC_IS_GCC ifeq ($(shell [ $(CONFIG_GCC_VERSION) -ne $(GCCSTR) ] && echo y), y) $(warning "Local GCC version $(GCCSTR) does not match kernel compiler GCC version $(CONFIG_GCC_VERSION)") @@ -32,6 +29,25 @@ export CONFIG_CC_IS_GCC=y export CONFIG_GCC_VERSION=$(GCCSTR) $(warning "CONFIG_CC_IS_GCC is not defined. Let's export it with version $(CONFIG_GCC_VERSION)") endif + +endif + +ifndef CONFIG_DRM +$(error CONFIG_DRM disabled, exit...) +endif + +ifeq (y,$(CONFIG_DRM_AMDGPU)) +$(error DRM_AMDGPU is built-in, exit...) +endif + +ifndef CONFIG_KALLSYMS +$(error CONFIG_KALLSYMS disabled, kallsyms_lookup_name() is absent, exit...) +endif + +_is_kcl_macro_defined=$(shell grep $1 $(src)/amd/dkms/config/config.h | grep -q "define" && echo "y" || echo "n") + +ifeq ($(call _is_kcl_macro_defined,HAVE_DMA_RESV_SEQ_BUG),y) +$(error dma_resv->seq is missing. exit...) endif DRM_VER=$(shell sed -n 's/^RHEL_DRM_VERSION = \(.*\)/\1/p' $(srctree)/Makefile) From d9edc531f536196330052147ffb7f743cf42d077 Mon Sep 17 00:00:00 2001 From: Horatio Zhang Date: Mon, 30 Jan 2023 16:52:42 +0800 Subject: [PATCH 0871/1868] drm/amdkcl: wrap code under CONFIG_DRM_AMD_DC_DSC_SUPPORT and CONFIG_DRM_AMD_DC_DCN It's cause by 'commit 05c1deaaaa92 ("drm/amd/display: move dp capability related logic to link_dp_capability")' 'commit 9a29f20c0621 ("drm/amd/display: move dp link training logic to link_dp_training")' Missing macro during code movement. link_dp_capability - missing CONFIG_DRM_AMD_DC_DCN macro link_dp_training - missing CONFIG_DRM_AMD_DC_DSC_SUPPORT macro when moving code from dc_link_dp.c link_dp_training_8b_10b - missing CONFIG_DRM_AMD_DC_DSC_SUPPORT macro when moving code from dc_link_dp.c link_dp_training_dpia - missing CONFIG_DRM_AMD_DC_DSC_SUPPORT macro when moving code from link_dp_dpia.c Signed-off-by: Horatio Zhang --- .../drm/amd/display/dc/link/protocols/link_dp_capability.c | 6 ++++++ .../drm/amd/display/dc/link/protocols/link_dp_training.c | 5 +++++ .../amd/display/dc/link/protocols/link_dp_training_8b_10b.c | 2 ++ 3 files changed, 13 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c index 59c9dde108850..41e7996fe8ac3 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c @@ -157,6 +157,7 @@ uint8_t dp_parse_lttpr_repeater_count(uint8_t lttpr_repeater_count) return 0; // invalid value } +#if defined(CONFIG_DRM_AMD_DC_DCN) uint32_t link_bw_kbps_from_raw_frl_link_rate_data(uint8_t bw) { switch (bw) { @@ -176,6 +177,7 @@ uint32_t link_bw_kbps_from_raw_frl_link_rate_data(uint8_t bw) return 0; } +#endif static enum dc_link_rate linkRateInKHzToLinkRateMultiplier(uint32_t link_rate_in_khz) { @@ -233,6 +235,7 @@ static union dp_cable_id intersect_cable_id( return out; } +#if defined(CONFIG_DRM_AMD_DC_DCN) /* * Return PCON's post FRL link training supported BW if its non-zero, otherwise return max_supported_frl_bw. */ @@ -260,6 +263,7 @@ static uint32_t intersect_frl_link_bw_support( return supported_bw_in_kbps; } +#endif static enum clock_source_id get_clock_source_id(struct dc_link *link) { @@ -1153,6 +1157,7 @@ static void get_active_converter_info( translate_dpcd_max_bpc( hdmi_color_caps.bits.MAX_BITS_PER_COLOR_COMPONENT); +#if defined(CONFIG_DRM_AMD_DC_DCN) if (link->dc->caps.dp_hdmi21_pcon_support) { union hdmi_encoded_link_bw hdmi_encoded_link_bw; @@ -1173,6 +1178,7 @@ static void get_active_converter_info( if (link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps > 0) link->dpcd_caps.dongle_caps.extendedCapValid = true; } +#endif if (link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz != 0) link->dpcd_caps.dongle_caps.extendedCapValid = true; diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c index 988999c444754..65cc1a1af9aaf 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c @@ -740,8 +740,11 @@ void override_training_settings( lt_settings->pattern_for_eq = *overrides->pattern_for_eq; if (overrides->enhanced_framing != NULL) lt_settings->enhanced_framing = *overrides->enhanced_framing; + +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (link->preferred_training_settings.fec_enable != NULL) lt_settings->should_set_fec_ready = *link->preferred_training_settings.fec_enable; +#endif /* Check DP tunnel LTTPR mode debug option. */ if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && link->dc->debug.dpia_debug.bits.force_non_lttpr) @@ -1504,7 +1507,9 @@ enum link_training_result dp_perform_link_training( /* configure link prior to entering training mode */ dpcd_configure_lttpr_mode(link, <_settings); +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT dp_set_fec_ready(link, link_res, lt_settings.should_set_fec_ready); +#endif dpcd_configure_channel_coding(link, <_settings); /* enter training mode: diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c index 2b4c15b0b4070..7841cabfd7948 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c @@ -115,7 +115,9 @@ void decide_8b_10b_training_settings( lt_settings->pattern_for_cr = decide_cr_training_pattern(link_setting); lt_settings->pattern_for_eq = decide_eq_training_pattern(link, link_setting); lt_settings->enhanced_framing = 1; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT lt_settings->should_set_fec_ready = true; +#endif lt_settings->disallow_per_lane_settings = true; lt_settings->always_match_dpcd_with_hw_lane_settings = true; lt_settings->lttpr_mode = dp_decide_8b_10b_lttpr_mode(link); From 41e4c337f890b25a4756fde374a081e68467c3d3 Mon Sep 17 00:00:00 2001 From: Horatio Zhang Date: Tue, 31 Jan 2023 12:53:17 +0800 Subject: [PATCH 0872/1868] drm/amdkcl: wrap code under macro CONFIG_DRM_AMD_DC_DSC_SUPPORT It's cause by 'commit 05c1deaaaa92 ("drm/amd/display: move dp capability related logic to link_dp_capability")' Missing macro during code movement. link_dp_capability - missing CONFIG_DRM_AMD_DC_DSC_SUPPORT macro when moving code from dc_link_dp.c link_edp_panel_control - fuction "decide_edp_link_settings" is changed to "dc_link_decide_edp_link_settings" Signed-off-by: Horatio Zhang --- .../amd/display/dc/link/protocols/link_dp_capability.c | 8 ++++++++ .../amd/display/dc/link/protocols/link_dp_capability.h | 2 ++ .../display/dc/link/protocols/link_edp_panel_control.c | 2 +- 3 files changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c index 41e7996fe8ac3..b715f256cbe10 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c @@ -425,6 +425,7 @@ static enum dc_link_rate get_lttpr_max_link_rate(struct dc_link *link) return lttpr_max_link_rate; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static enum dc_link_rate get_cable_max_link_rate(struct dc_link *link) { enum dc_link_rate cable_max_link_rate = LINK_RATE_UNKNOWN; @@ -444,6 +445,7 @@ static enum dc_link_rate get_cable_max_link_rate(struct dc_link *link) return cable_max_link_rate; } +#endif static inline bool reached_minimum_lane_count(enum dc_lane_count lane_count) { @@ -776,6 +778,7 @@ bool edp_decide_link_settings(struct dc_link *link, return false; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT bool decide_edp_link_settings_with_dsc(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw, @@ -916,6 +919,7 @@ bool decide_edp_link_settings_with_dsc(struct dc_link *link, } return false; } +#endif static bool decide_mst_link_settings(const struct dc_link *link, struct dc_link_settings *link_setting) { @@ -1833,6 +1837,7 @@ static bool retrieve_link_cap(struct dc_link *link) } } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT memset(&link->dpcd_caps.dsc_caps, '\0', sizeof(link->dpcd_caps.dsc_caps)); memset(&link->dpcd_caps.fec_cap, '\0', sizeof(link->dpcd_caps.fec_cap)); @@ -1894,6 +1899,7 @@ static bool retrieve_link_cap(struct dc_link *link) } else link->wa_flags.dpia_forced_tbt3_mode = false; } +#endif if (!dpcd_read_sink_ext_caps(link)) link->dpcd_sink_ext_caps.raw = 0; @@ -2089,7 +2095,9 @@ struct dc_link_settings dp_get_max_link_cap(struct dc_link *link) { struct dc_link_settings max_link_cap = {0}; enum dc_link_rate lttpr_max_link_rate; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT enum dc_link_rate cable_max_link_rate; +#endif struct link_encoder *link_enc = NULL; bool is_uhbr13_5_supported = true; diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.h b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.h index 8f0ce97f23621..1725724983afb 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.h +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.h @@ -77,10 +77,12 @@ bool link_decide_link_settings( bool edp_decide_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw); +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT bool decide_edp_link_settings_with_dsc(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw, enum dc_link_rate max_link_rate); +#endif enum dp_link_encoding mst_decide_link_encoding_format(const struct dc_link *link); diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c index f85da653bf007..55726b8b233e9 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c @@ -357,7 +357,7 @@ bool edp_is_ilr_optimization_required(struct dc_link *link, else decide_edp_link_settings_with_dsc(link, &link_setting, req_bw, LINK_RATE_UNKNOWN); #else - decide_edp_link_settings(link, &link_setting, req_bw); + dc_link_decide_edp_link_settings(link, &link_setting, req_bw); #endif if (link->dpcd_caps.edp_supported_link_rates[link_rate_set] != link_setting.link_rate || From 6cd5f58f1905e4fba6ebb062225d5f38f502ba5b Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 14 Feb 2023 17:02:38 +0800 Subject: [PATCH 0873/1868] drm/amdkcl: update kcl macro for amdgpu_dm_atomic_check() It's caused by 52be8da751ab9476a0adfcd71d112850dae8248c "drm/amdgpu/display/mst: Fix mst_state->pbn_div and slot count assignments" Signed-off-by: Bob Zhou Reviewed-by: Asher Song Signed-off-by: Asher Song --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index c93474ccd8273..7e3b892b8183d 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -11605,9 +11605,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, bool is_top_most_overlay = true; struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT -#ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS struct drm_dp_mst_topology_mgr *mgr; -#endif struct drm_dp_mst_topology_state *mst_state; struct dsc_mst_fairness_vars vars[MAX_PIPES] = {0}; #endif @@ -11938,7 +11936,6 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, lock_and_validation_needed = true; } -#ifndef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS /* set the slot info for each mst_state based on the link encoding format */ @@ -11948,6 +11945,10 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, struct drm_connector_list_iter iter; u8 link_coding_cap; +#ifndef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV + if (!mgr->mst_state ) + continue; +#endif drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { if (connector->index == mst_state->mgr->conn_base_id) { From dc7882b8249ecf98994825a4cf05704abcc31a46 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 7 Feb 2023 17:24:27 +0800 Subject: [PATCH 0874/1868] drm/amdkcl: modify the naming of mst_port and port for kcl code It's caused by d6daeede3abe864d0dca1c74edf1af5a3a018297 "drm/amdgpu/display/mst: adjust the naming of mst_port and port of aconnector" The term (i.e. port & mst_port) are renamed to mst_output_port & mst_root respectively. So some code under kcl macro need to be renamed. Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 6 +++--- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 6 +++--- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index 329d12391c683..0fe8ddab1b609 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -278,7 +278,7 @@ fill_dc_mst_payload_table_from_drm(struct amdgpu_dm_connector *aconnector, { int i; struct drm_dp_mst_topology_mgr *mst_mgr = - &aconnector->mst_port->mst_mgr; + &aconnector->mst_root->mst_mgr; mutex_lock(&mst_mgr->payload_lock); @@ -420,7 +420,7 @@ bool dm_helpers_dp_mst_write_payload_allocation_table( if (!mst_mgr->mst_state) return false; - mst_port = aconnector->port; + mst_port = aconnector->mst_output_port; #if defined(CONFIG_DRM_AMD_DC_DCN) link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link); @@ -574,7 +574,7 @@ void dm_helpers_dp_mst_send_payload_allocation( new_payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port); #else - mst_port = aconnector->port; + mst_port = aconnector->mst_output_port; if (!mst_mgr->mst_state) return; #endif diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index d4ec6d5368044..79101ee472964 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -121,13 +121,13 @@ static enum drm_connector_status dm_dp_mst_detect(struct drm_connector *connector, bool force) { struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); - struct amdgpu_dm_connector *master = aconnector->mst_port; + struct amdgpu_dm_connector *master = aconnector->mst_root; enum drm_connector_status status = drm_dp_mst_detect_port( connector, &master->mst_mgr, - aconnector->port); + aconnector->mst_output_port); return status; } @@ -816,7 +816,7 @@ static void dm_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr, struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); DRM_INFO("DM_MST: Disabling connector: %p [id: %d] [master: %p]\n", - aconnector, connector->base.id, aconnector->mst_port); + aconnector, connector->base.id, aconnector->mst_root); if (aconnector->dc_sink) { amdgpu_dm_update_freesync_caps(connector, NULL); From 408b6311e916463634a81ef46900f2e594ab80df Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 14 Feb 2023 13:03:24 +0800 Subject: [PATCH 0875/1868] drm/amdkcl: check drm/drm_fbdev_generic.h whether exist It's caused by 8ab59da26bc0ae0abfcaabc4218c74827d154256 "drm/fb-helper: Move generic fbdev emulation into separate source file" Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index 055736d17b86a..ccdccb0e48d30 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -92,4 +92,11 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # drm/amdgpu: add drm buddy support to amdgpu dnl # AC_KERNEL_CHECK_HEADERS([drm/drm_buddy.h]) + + dnl # + dnl # v6.1-rc2-542-g8ab59da26bc0 + dnl # drm/fb-helper: Move generic fbdev emulation into separate source file + dnl # + AC_KERNEL_CHECK_HEADERS([drm/drm_fbdev_generic.h]) + ]) From 003397db75cc976df22c2b58c7c9439cd1034d4c Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 14 Feb 2023 13:04:54 +0800 Subject: [PATCH 0876/1868] drm/amdkcl: for instance of ttm_resource struct, change member num_pages to size It's caused by 0f9cd1ea10d307cad221d6693b648a8956e812b0 "drm/ttm: fix bulk move handling v2" Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index 513646ec83f67..9faf83dfa5ba5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -599,11 +599,11 @@ int amdgpu_gem_dgma_ioctl(struct drm_device *dev, void *data, return r; abo = gem_to_amdgpu_bo(gobj); - dma_addr = kmalloc_array(abo->tbo.resource->num_pages, sizeof(dma_addr_t), GFP_KERNEL); + dma_addr = kmalloc_array(PFN_UP(abo->tbo.resource->size), sizeof(dma_addr_t), GFP_KERNEL); if (unlikely(dma_addr == NULL)) goto release_object; - for (i = 0; i < abo->tbo.resource->num_pages; i++) + for (i = 0; i < PFN_UP(abo->tbo.resource->size); i++) dma_addr[i] = args->addr + i * PAGE_SIZE; abo->dgma_import_base = args->addr; abo->dgma_addr = (void *)dma_addr; From 4bab6ebd6e2aaad61823a8863bd89928115d42a1 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 14 Feb 2023 16:45:45 +0800 Subject: [PATCH 0877/1868] drm/amdkcl: test struct migrate_vma whether has member fault_page It's caused by 16ce101db85d "mm/memory.c: fix race when faulting a device private page" Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 2 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../drm/amd/dkms/m4/migrate_vma_fault_page.m4 | 19 +++++++++++++++++++ 3 files changed, 22 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/migrate_vma_fault_page.m4 diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c index aed57b9d47403..5521b6b70290d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@ -741,7 +741,9 @@ svm_migrate_vma_to_ram(struct kfd_node *node, struct svm_range *prange, migrate.src = buf; migrate.dst = migrate.src + npages; +#ifdef HAVE_MIGRATE_VMA_FAULT_PAGE migrate.fault_page = fault_page; +#endif scratch = (dma_addr_t *)(migrate.dst + npages); kfd_smi_event_migration_start(node, p->lead_thread->pid, diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 5709594b7210d..a209401e9ac9c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -224,6 +224,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_MEMORY_DEVICE_COHERENT AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV + AC_AMDGPU_MIGRATE_VMA_FAULT_PAGE AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/migrate_vma_fault_page.m4 b/drivers/gpu/drm/amd/dkms/m4/migrate_vma_fault_page.m4 new file mode 100644 index 0000000000000..406fa50e310c5 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/migrate_vma_fault_page.m4 @@ -0,0 +1,19 @@ +dnl # +dnl # commit v6.0-rc3-595-g16ce101db85d +dnl # mm/memory.c: fix race when faulting a device private page +dnl # +AC_DEFUN([AC_AMDGPU_MIGRATE_VMA_FAULT_PAGE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct migrate_vma mig = {0}; + struct page *fault_page; + mig.fault_page = fault_page; + ], [ + AC_DEFINE(HAVE_MIGRATE_VMA_FAULT_PAGE, 1, + [struct migrate_vma has fault_page]) + ]) + ]) +]) + From b7e6b9b0db94542b99c6ff856129fd23fc641203 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 2 Feb 2023 16:36:38 +0800 Subject: [PATCH 0878/1868] drm/amdkcl: move drm_buddy and drm_ttm_helper compile config from Makefile to subfile Create new files Makefile.drm_buddy and Makefile.drm_ttm_helper, and move drm_buddy and drm_ttm_helper compile config into them. Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Makefile | 16 +++------------- drivers/gpu/drm/amd/dkms/Makefile.drm_buddy | 6 ++++++ drivers/gpu/drm/amd/dkms/Makefile.drm_ttm_helper | 8 ++++++++ 3 files changed, 17 insertions(+), 13 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/Makefile.drm_buddy create mode 100644 drivers/gpu/drm/amd/dkms/Makefile.drm_ttm_helper diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 2e8db344899bd..a0e67352e5b38 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -210,18 +210,8 @@ subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DSC_SUPPORT endif endif -export CONFIG_DRM_TTM_HELPER=m -subdir-ccflags-y += -DCONFIG_DRM_TTM_HELPER -CFLAGS_drm_gem_ttm_helper.o += -include $(src)/ttm/backport/backport.h \ - -include $(src)/include/kcl/backport/kcl_drm_gem.h \ - -DHAVE_CONFIG_H -amddrm_ttm_helper-y := drm_gem_ttm_helper.o -obj-$(CONFIG_DRM_TTM_HELPER) += amddrm_ttm_helper.o - -export CONFIG_DRM_BUDDY=m -subdir-ccflags-y += -DCONFIG_DRM_BUDDY -CFLAGS_drm_buddy.o += -DHAVE_CONFIG_H -amddrm_buddy-y := drm_buddy.o -obj-$(CONFIG_DRM_BUDDY) += amddrm_buddy.o +include $(src)/amd/dkms/Makefile.drm_ttm_helper + +include $(src)/amd/dkms/Makefile.drm_buddy obj-m += scheduler/ amd/amdgpu/ ttm/ amd/amdkcl/ diff --git a/drivers/gpu/drm/amd/dkms/Makefile.drm_buddy b/drivers/gpu/drm/amd/dkms/Makefile.drm_buddy new file mode 100644 index 0000000000000..208c05b48758d --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/Makefile.drm_buddy @@ -0,0 +1,6 @@ +export CONFIG_DRM_BUDDY=m + +subdir-ccflags-y += -DCONFIG_DRM_BUDDY +CFLAGS_drm_buddy.o += -DHAVE_CONFIG_H +amddrm_buddy-y := drm_buddy.o +obj-$(CONFIG_DRM_BUDDY) += amddrm_buddy.o diff --git a/drivers/gpu/drm/amd/dkms/Makefile.drm_ttm_helper b/drivers/gpu/drm/amd/dkms/Makefile.drm_ttm_helper new file mode 100644 index 0000000000000..b76db38d020a2 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/Makefile.drm_ttm_helper @@ -0,0 +1,8 @@ +export CONFIG_DRM_TTM_HELPER=m + +subdir-ccflags-y += -DCONFIG_DRM_TTM_HELPER +CFLAGS_drm_gem_ttm_helper.o += -include $(src)/ttm/backport/backport.h \ + -include $(src)/include/kcl/backport/kcl_drm_gem.h \ + -DHAVE_CONFIG_H +amddrm_ttm_helper-y := drm_gem_ttm_helper.o +obj-$(CONFIG_DRM_TTM_HELPER) += amddrm_ttm_helper.o From 2ba6d533bd573cfd5c7c38f51c11163917d757f8 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 1 Feb 2023 16:19:14 +0800 Subject: [PATCH 0879/1868] drm/amdkcl: Implement the drm_kms_helper_connector_hotplug_event() Implement the drm_kms_helper_connector_hotplug_event() for legacy os Signed-off-by: Bob Zhou Reviewed-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/backport/backport.h | 1 + .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 20 ------------------- .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 8 -------- include/kcl/backport/kcl_drm_probe_helper.h | 16 +++++++++++++++ 4 files changed, 17 insertions(+), 28 deletions(-) create mode 100644 include/kcl/backport/kcl_drm_probe_helper.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index bbdb386892d49..76bf0d096d295 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -108,4 +108,5 @@ * include drm_damage_helper.h to fix the missing function declaration for legacy kernel. */ #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 7e3b892b8183d..58f08965f04a7 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1437,11 +1437,7 @@ static void force_connector_state( mutex_unlock(&connector->dev->mode_config.mutex); mutex_lock(&aconnector->hpd_lock); -#ifdef HAVE_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT drm_kms_helper_connector_hotplug_event(connector); -#else - drm_kms_helper_hotplug_event(connector->dev); -#endif mutex_unlock(&aconnector->hpd_lock); } @@ -3696,11 +3692,7 @@ static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector) drm_modeset_unlock_all(dev); if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) -#ifdef HAVE_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT drm_kms_helper_connector_hotplug_event(connector); -#else - drm_kms_helper_hotplug_event(dev); -#endif } else { mutex_lock(&adev->dm.dc_lock); dc_exit_ips_for_hw_access(dc); @@ -3714,11 +3706,7 @@ static void handle_hpd_irq_helper(struct amdgpu_dm_connector *aconnector) drm_modeset_unlock_all(dev); if (aconnector->base.force == DRM_FORCE_UNSPECIFIED) -#ifdef HAVE_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT drm_kms_helper_connector_hotplug_event(connector); -#else - drm_kms_helper_hotplug_event(dev); -#endif } } mutex_unlock(&aconnector->hpd_lock); @@ -3852,11 +3840,7 @@ static void handle_hpd_rx_irq(void *param) dm_restore_drm_connector_state(dev, connector); drm_modeset_unlock_all(dev); -#ifdef HAVE_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT drm_kms_helper_connector_hotplug_event(connector); -#else - drm_kms_helper_hotplug_event(dev); -#endif } else { bool ret = false; @@ -3875,11 +3859,7 @@ static void handle_hpd_rx_irq(void *param) dm_restore_drm_connector_state(dev, connector); drm_modeset_unlock_all(dev); -#ifdef HAVE_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT drm_kms_helper_connector_hotplug_event(connector); -#else - drm_kms_helper_hotplug_event(dev); -#endif } } } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index 2880eea91a5ab..1eb31b59e7a8a 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -1479,11 +1479,7 @@ static ssize_t trigger_hotplug(struct file *f, const char __user *buf, dm_restore_drm_connector_state(dev, connector); drm_modeset_unlock_all(dev); -#ifdef HAVE_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT drm_kms_helper_connector_hotplug_event(connector); -#else - drm_kms_helper_hotplug_event(dev); -#endif } else if (param[0] == 0) { if (!aconnector->dc_link) goto unlock; @@ -1509,11 +1505,7 @@ static ssize_t trigger_hotplug(struct file *f, const char __user *buf, dm_restore_drm_connector_state(dev, connector); drm_modeset_unlock_all(dev); -#ifdef HAVE_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT drm_kms_helper_connector_hotplug_event(connector); -#else - drm_kms_helper_hotplug_event(dev); -#endif } unlock: diff --git a/include/kcl/backport/kcl_drm_probe_helper.h b/include/kcl/backport/kcl_drm_probe_helper.h new file mode 100644 index 0000000000000..3ac7310361bb4 --- /dev/null +++ b/include/kcl/backport/kcl_drm_probe_helper.h @@ -0,0 +1,16 @@ +#ifndef AMDKCL_BACKPORT_DRM_PROBE_HELPER_H +#define AMDKCL_BACKPORT_DRM_PROBE_HELPER_H + +#include + +#ifndef HAVE_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT +static inline void _kcl_drm_kms_helper_connector_hotplug_event(struct drm_connector *connector) +{ + drm_kms_helper_hotplug_event(connector->dev); +} + +#define drm_kms_helper_connector_hotplug_event _kcl_drm_kms_helper_connector_hotplug_event + + +#endif +#endif From f9363ce39fcbc80e4fba1347ef1a8dfc0746d4e3 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 8 Feb 2023 17:48:59 +0800 Subject: [PATCH 0880/1868] drm/admkcl: wrap code under macro CONFIG_DRM_AMD_DC_DSC_SUPPORT It's caused by def6ddd09e22c65b4367fbf56310a8ed329a713a "drm/amd/display: break down dc_link.c" [why] Move remaining dc_link.c functions into link_detection, link_dpms, link_validation, link_resource, and link_fpga and remove dc_link. [how] Restore macro CONFIG_DRM_AMD_DC_DSC_SUPPORT for these new file. Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/display/dc/link/link_dpms.c | 9 ++++++++- drivers/gpu/drm/amd/display/dc/link/link_validation.c | 7 ++++++- .../gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c | 2 ++ .../gpu/drm/amd/display/dc/link/protocols/link_dp_phy.h | 4 ++-- 4 files changed, 18 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c index d6550b904b164..6b68fbba5992c 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c @@ -759,6 +759,7 @@ static void dsc_optc_config_log(struct display_stream_compressor *dsc, DC_LOG_DSC("\tslice_width %d", config->slice_width); } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable) { struct dc *dc = pipe_ctx->stream->ctx->dc; @@ -771,6 +772,7 @@ static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable) result = dm_helpers_dp_write_dsc_enable(dc->ctx, stream, enable); return result; } +#endif /* The stream with these settings can be sent (unblanked) only after DSC was enabled on RX first, * i.e. after dp_enable_dsc_on_rx() had been called @@ -982,6 +984,7 @@ bool link_set_dsc_pps_packet(struct pipe_ctx *pipe_ctx, bool enable, bool immedi return true; } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT bool link_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable) { struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; @@ -1005,6 +1008,7 @@ bool link_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable) out: return result; } +#endif bool link_update_dsc_config(struct pipe_ctx *pipe_ctx) { @@ -2527,12 +2531,13 @@ void link_set_dpms_on( * will be automatically set at a later time when the video is enabled * (DP_VID_STREAM_EN = 1). */ +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (pipe_ctx->stream->timing.flags.DSC) { if (dc_is_dp_signal(pipe_ctx->stream->signal) || dc_is_virtual_signal(pipe_ctx->stream->signal)) link_set_dsc_enable(pipe_ctx, true); } - +#endif status = enable_link(state, pipe_ctx); if (status != DC_OK) { @@ -2577,6 +2582,7 @@ void link_set_dpms_on( dc->hwss.enable_stream(pipe_ctx); +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* Set DPS PPS SDP (AKA "info frames") */ if (pipe_ctx->stream->timing.flags.DSC) { if (dc_is_dp_signal(pipe_ctx->stream->signal) || @@ -2585,6 +2591,7 @@ void link_set_dpms_on( link_set_dsc_pps_packet(pipe_ctx, true, true); } } +#endif if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) allocate_usb4_bandwidth(pipe_ctx->stream); diff --git a/drivers/gpu/drm/amd/display/dc/link/link_validation.c b/drivers/gpu/drm/amd/display/dc/link/link_validation.c index 1aed55b0ab6a0..914763fe8259d 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_validation.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_validation.c @@ -136,10 +136,13 @@ static bool dp_active_dongle_validate_timing( return false; } } - +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (dpcd_caps->channel_coding_cap.bits.DP_128b_132b_SUPPORTED == 0 && dpcd_caps->dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_PASSTHROUGH_SUPPORT == 0 && dongle_caps->dfp_cap_ext.supported) { +#else + if (dongle_caps->dfp_cap_ext.supported) { +#endif if (dongle_caps->dfp_cap_ext.max_pixel_rate_in_mps < (timing->pix_clk_100hz / 10000)) return false; @@ -234,10 +237,12 @@ uint32_t dp_link_bandwidth_kbps( */ link_rate_per_lane_kbps = link_settings->link_rate * LINK_RATE_REF_FREQ_IN_KHZ * BITS_PER_DP_BYTE; total_data_bw_efficiency_x10000 = DATA_EFFICIENCY_8b_10b_x10000; +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (dp_should_enable_fec(link)) { total_data_bw_efficiency_x10000 /= 100; total_data_bw_efficiency_x10000 *= DATA_EFFICIENCY_8b_10b_FEC_EFFICIENCY_x100; } +#endif break; case DP_128b_132b_ENCODING: /* For 128b/132b encoding: diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c index bafa52a0165a0..6bcace78e4124 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c @@ -134,6 +134,7 @@ void dp_set_drive_settings( dpcd_set_lane_settings(link, lt_settings, DPRX); } +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT enum dc_status dp_set_fec_ready(struct dc_link *link, const struct link_resource *link_res, bool ready) { /* FEC has to be "set ready" before the link training. @@ -173,6 +174,7 @@ enum dc_status dp_set_fec_ready(struct dc_link *link, const struct link_resource return status; } +#endif void dp_set_fec_enable(struct dc_link *link, bool enable) { diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.h b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.h index 1eb0619d6710e..6b46193296237 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.h +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.h @@ -48,10 +48,10 @@ void dp_set_drive_settings( struct dc_link *link, const struct link_resource *link_res, struct link_training_settings *lt_settings); - +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT enum dc_status dp_set_fec_ready(struct dc_link *link, const struct link_resource *link_res, bool ready); - +#endif void dp_set_fec_enable(struct dc_link *link, bool enable); void dpcd_write_rx_power_ctrl(struct dc_link *link, bool on); From d557cc1ee5804f297aa6bc1087a685d686d21212 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 14 Feb 2023 13:25:23 +0800 Subject: [PATCH 0881/1868] drm/admkcl: wrap code under macro CONFIG_DRM_AMD_DC_DSC_SUPPORT It's caused by f57b3411356d482078ad46aadece1847e74e4c83 "drm/amd/display: do not set RX back to SST mode for non 0 mst stream count" A part of disable_link() is moved into disable_link_dp(), so these kcl macro is restored. Signed-off-by: Bob Zhou Reviewed-by: Ma Jun --- drivers/gpu/drm/amd/display/dc/link/link_dpms.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c index 6b68fbba5992c..e7a9b09c750d4 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c @@ -1893,7 +1893,9 @@ static void disable_link_dp(struct dc_link *link, const struct link_resource *link_res, enum signal_type signal) { +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT struct dc_link_settings link_settings = link->cur_link_settings; +#endif if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST && link->mst_stream_alloc_table.stream_count > 0) @@ -1910,12 +1912,13 @@ static void disable_link_dp(struct dc_link *link, if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) /* set the sink to SST mode after disabling the link */ enable_mst_on_sink(link, false); - +#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (link_dp_get_encoding_format(&link_settings) == DP_8b_10b_ENCODING) { dp_set_fec_enable(link, false); dp_set_fec_ready(link, link_res, false); } +#endif } static void disable_link(struct dc_link *link, From 3aa65d6012d101fc73027e533fe6e40697e13cd4 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Sat, 18 Feb 2023 14:59:16 +0800 Subject: [PATCH 0882/1868] drm/amdkcl: add kcl_rbtee.h It's caused by 08fb97de03aa2205c6791301bd83a095abc1949c "drm/sched: Add FIFO sched policy to run queue" Signed-off-by: Asher Song --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/rbtree.m4 | 19 +++++ include/drm/gpu_scheduler.h | 1 + include/kcl/kcl_rbtree.h | 99 +++++++++++++++++++++++++ 5 files changed, 121 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/rbtree.m4 create mode 100644 include/kcl/kcl_rbtree.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 76bf0d096d295..29f5ada3bd6b3 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -109,4 +109,5 @@ */ #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index a209401e9ac9c..7d2b87bc21f8d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -225,6 +225,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV AC_AMDGPU_MIGRATE_VMA_FAULT_PAGE + AC_AMDGPU_RB_ADD_CACHED AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/rbtree.m4 b/drivers/gpu/drm/amd/dkms/m4/rbtree.m4 new file mode 100644 index 0000000000000..0a29c2b864323 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/rbtree.m4 @@ -0,0 +1,19 @@ +dnl # +dnl # v5.11-20-g2d24dd5798d0 +dnl # rbtree: Add generic add and find helpers +dnl # +AC_DEFUN([AC_AMDGPU_RB_ADD_CACHED], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + rb_add_cached(NULL, NULL, NULL); + ],[ + AC_DEFINE(HAVE_RB_ADD_CACHED, 1, + [rb_add_cached is available]) + ]) + ]) +]) + + + diff --git a/include/drm/gpu_scheduler.h b/include/drm/gpu_scheduler.h index 150c5906c590f..cfaa5ff144e5a 100644 --- a/include/drm/gpu_scheduler.h +++ b/include/drm/gpu_scheduler.h @@ -29,6 +29,7 @@ #include #include #include +#include #define MAX_WAIT_SCHED_ENTITY_Q_EMPTY msecs_to_jiffies(1000) diff --git a/include/kcl/kcl_rbtree.h b/include/kcl/kcl_rbtree.h new file mode 100644 index 0000000000000..6d3bf91f7b4f9 --- /dev/null +++ b/include/kcl/kcl_rbtree.h @@ -0,0 +1,99 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +#ifndef AMDKCL_LINUX_RBTREE_H +#define AMDKCL_LINUX_RBTREE_H + +#include + +#ifndef HAVE_RB_ROOT_CACHED +/* + * Leftmost-cached rbtrees. + * + * We do not cache the rightmost node based on footprint + * size vs number of potential users that could benefit + * from O(1) rb_last(). Just not worth it, users that want + * this feature can always implement the logic explicitly. + * Furthermore, users that want to cache both pointers may + * find it a bit asymmetric, but that's ok. + */ +struct rb_root_cached { + struct rb_root rb_root; + struct rb_node *rb_leftmost; +}; + +#define RB_ROOT_CACHED (struct rb_root_cached) { {NULL, }, NULL } +#define rb_first_cached(root) (root)->rb_leftmost + +static inline struct rb_node * +rb_erase_cached(struct rb_node *node, struct rb_root_cached *root) +{ + struct rb_node *leftmost = NULL; + + if (root->rb_leftmost == node) + leftmost = root->rb_leftmost = rb_next(node); + + rb_erase(node, &root->rb_root); + + return leftmost; +} + +static inline void rb_insert_color_cached(struct rb_node *node, + struct rb_root_cached *root, + bool leftmost) +{ + if (leftmost) + root->rb_leftmost = node; + rb_insert_color(node, &root->rb_root); +} +#endif + +#ifndef HAVE_RB_ADD_CACHED +/* + * The below helper functions use 2 operators with 3 different + * calling conventions. The operators are related like: + * + * comp(a->key,b) < 0 := less(a,b) + * comp(a->key,b) > 0 := less(b,a) + * comp(a->key,b) == 0 := !less(a,b) && !less(b,a) + * + * If these operators define a partial order on the elements we make no + * guarantee on which of the elements matching the key is found. See + * rb_find(). + * + * The reason for this is to allow the find() interface without requiring an + * on-stack dummy object, which might not be feasible due to object size. + */ + +/** + * rb_add_cached() - insert @node into the leftmost cached tree @tree + * @node: node to insert + * @tree: leftmost cached tree to insert @node into + * @less: operator defining the (partial) node order + * + * Returns @node when it is the new leftmost, or NULL. + */ +static __always_inline struct rb_node * +rb_add_cached(struct rb_node *node, struct rb_root_cached *tree, + bool (*less)(struct rb_node *, const struct rb_node *)) +{ + struct rb_node **link = &tree->rb_root.rb_node; + struct rb_node *parent = NULL; + bool leftmost = true; + + while (*link) { + parent = *link; + if (less(node, parent)) { + link = &parent->rb_left; + } else { + link = &parent->rb_right; + leftmost = false; + } + } + + rb_link_node(node, parent, link); + rb_insert_color_cached(node, tree, leftmost); + + return leftmost ? node : NULL; +} +#endif + +#endif From 816c72fb954435a5ec7ebba32948caf9d548070d Mon Sep 17 00:00:00 2001 From: Asher Song Date: Sat, 18 Feb 2023 16:19:33 +0800 Subject: [PATCH 0883/1868] drm/amdkcl:wrap code under macro HAVE_AMDKCL_HMM_MIRROR_ENABLED It's caused by e43a06a5ef73e1329861ad3a70c490d3eb6e072b "drm/amdgpu: Add notifier lock for KFD userptrs" Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 15 ++++-- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 47 ++++++++++++------- 2 files changed, 42 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index 85c7e4ed46d2f..6b4bf3c61b3d7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -72,7 +72,11 @@ struct kgd_mem { struct amdgpu_bo *bo; struct kfd_ipc_obj *ipc_obj; struct dma_buf *dmabuf; +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED struct hmm_range *range; +#else + struct page **user_pages; +#endif struct list_head attachments; /* protected by amdkfd_process_info.lock */ struct list_head validate_list; @@ -84,9 +88,6 @@ struct kgd_mem { uint32_t invalid; struct amdkfd_process_info *process_info; -#ifndef HAVE_AMDKCL_HMM_MIRROR_ENABLED - struct page **user_pages; -#endif struct amdgpu_sync sync; @@ -198,8 +199,12 @@ int kfd_debugfs_kfd_mem_limits(struct seq_file *m, void *data); bool amdkfd_fence_check_mm(struct dma_fence *f, struct mm_struct *mm); struct amdgpu_amdkfd_fence *to_amdgpu_amdkfd_fence(struct dma_fence *f); int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo); +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED int amdgpu_amdkfd_evict_userptr(struct mmu_interval_notifier *mni, unsigned long cur_seq, struct kgd_mem *mem); +#else +int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, struct mm_struct *mm); +#endif int amdgpu_amdkfd_bo_validate_and_fence(struct amdgpu_bo *bo, uint32_t domain, struct dma_fence *fence); @@ -223,8 +228,12 @@ int amdgpu_amdkfd_remove_fence_on_pt_pd_bos(struct amdgpu_bo *bo) } static inline +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED int amdgpu_amdkfd_evict_userptr(struct mmu_interval_notifier *mni, unsigned long cur_seq, struct kgd_mem *mem) +#else +int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, struct mm_struct *mm) +#endif { return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 9162561c1dcd9..e433d2db53b13 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -2039,21 +2039,21 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu( /* Cleanup user pages and MMU notifiers */ if (amdgpu_ttm_tt_get_usermm(mem->bo->tbo.ttm)) { amdgpu_hmm_unregister(mem->bo); +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED mutex_lock(&process_info->notifier_lock); amdgpu_ttm_tt_discard_user_pages(mem->bo->tbo.ttm, mem->range); mutex_unlock(&process_info->notifier_lock); - } - -#ifndef HAVE_AMDKCL_HMM_MIRROR_ENABLED - /* Free user pages if necessary */ - if (mem->user_pages) { - pr_debug("%s: Freeing user_pages array\n", __func__); - if (mem->user_pages[0]) - release_pages(mem->user_pages, +#else + /* Free user pages if necessary */ + if (mem->user_pages) { + pr_debug("%s: Freeing user_pages array\n", __func__); + if (mem->user_pages[0]) + release_pages(mem->user_pages, mem->bo->tbo.ttm->num_pages); - kvfree(mem->user_pages); - } + kvfree(mem->user_pages); + } #endif + } ret = reserve_bo_and_cond_vms(mem, NULL, BO_VM_ALL, &ctx); if (unlikely(ret)) @@ -2843,9 +2843,16 @@ int amdgpu_amdkfd_gpuvm_export_ipc_obj(struct amdgpu_device *adev, void *vm, * restore, where we get updated page addresses. This function only * ensures that GPU access to the BO is stopped. */ +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED int amdgpu_amdkfd_evict_userptr(struct mmu_interval_notifier *mni, unsigned long cur_seq, struct kgd_mem *mem) { + struct mm_struct *mm = mni->mm; +#else +int amdgpu_amdkfd_evict_userptr(struct kgd_mem *mem, + struct mm_struct *mm) +{ +#endif struct amdkfd_process_info *process_info = mem->process_info; int r = 0; @@ -2856,12 +2863,14 @@ int amdgpu_amdkfd_evict_userptr(struct mmu_interval_notifier *mni, return 0; mutex_lock(&process_info->notifier_lock); +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED mmu_interval_set_seq(mni, cur_seq); +#endif mem->invalid++; if (++process_info->evicted_bos == 1) { /* First eviction, stop the queues */ - r = kgd2kfd_quiesce_mm(mni->mm, + r = kgd2kfd_quiesce_mm(mm, KFD_QUEUE_EVICTION_TRIGGER_USERPTR); if (r) pr_err("Failed to quiesce KFD\n"); @@ -2911,8 +2920,10 @@ static int update_invalid_user_pages(struct amdkfd_process_info *process_info, bo = mem->bo; +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED amdgpu_ttm_tt_discard_user_pages(bo->tbo.ttm, mem->range); mem->range = NULL; +#endif /* BO reservations and getting user pages (hmm_range_fault) * must happen outside the notifier lock @@ -3069,7 +3080,7 @@ static int validate_invalid_user_pages(struct amdkfd_process_info *process_info) #else /* Copy pages array and validate the BO if we got user pages */ - if (mem->user_pages[0]) { + if (mem->user_pages && mem->user_pages[0]) { amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm, mem->user_pages); amdgpu_bo_placement_from_domain(bo, mem->domain); @@ -3081,12 +3092,12 @@ static int validate_invalid_user_pages(struct amdkfd_process_info *process_info) } /* Validate succeeded, now the BO owns the pages, free - * our copy of the pointer array. Put this BO back on - * the userptr_valid_list. If we need to revalidate - * it, we need to start from scratch. + * our copy of the pointer array. */ - kvfree(mem->user_pages); - mem->user_pages = NULL; + if (mem->user_pages) { + kvfree(mem->user_pages); + mem->user_pages = NULL; + } #endif /* Update mapping. If the BO was not validated @@ -3135,6 +3146,7 @@ static int confirm_valid_user_pages_locked(struct amdkfd_process_info *process_i list_for_each_entry_safe(mem, tmp_mem, &process_info->userptr_inval_list, validate_list) { +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED bool valid; /* keep mem without hmm range at userptr_inval_list */ @@ -3151,6 +3163,7 @@ static int confirm_valid_user_pages_locked(struct amdkfd_process_info *process_i ret = -EAGAIN; continue; } +#endif if (mem->invalid) { WARN(1, "Valid BO is marked invalid"); From 116ed907bee80328e394c245cb30b4118d1d3e7b Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 21 Feb 2023 14:41:33 +0800 Subject: [PATCH 0884/1868] drm/amdkcl: wrap the code under macro HAVE_DRM_MODE_CONFIG_FB_BASE It's caused by 7c99616e3fe7f35fe25bf6f5797267da29b4751e "drm: Remove drm_mode_config::fb_base" Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 2 ++ drivers/gpu/drm/amd/dkms/m4/drm_mode_config.m4 | 18 ++++++++++++++++++ 2 files changed, 20 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c index 65bf30a84fdd3..7aee5aeeecc91 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c @@ -261,7 +261,9 @@ static int amdgpufb_create(struct drm_fb_helper *helper, drm_fb_helper_fill_info(info, &rfbdev->helper, sizes); /* setup aperture base/size for vesafb takeover */ +#ifdef HAVE_DRM_MODE_CONFIG_FB_BASE info->apertures->ranges[0].base = adev_to_drm(adev)->mode_config.fb_base; +#endif info->apertures->ranges[0].size = adev->gmc.aper_size; /* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_mode_config.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_mode_config.m4 index add5633e0f26f..4b809aec8cd50 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_mode_config.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_mode_config.m4 @@ -12,7 +12,25 @@ AC_DEFUN([AC_AMDGPU_DRM_MODE_CONFIG_FB_MODIFIERS_NOT_SUPPORTED], [ ]) ]) +dnl # +dnl # v6.1-rc1-103-g7c99616e3fe7 drm: Remove drm_mode_config::fb_base +dnl # +AC_DEFUN([AC_AMDGPU_DRM_MODE_CONFIG_FB_BASE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_mode_config *mode_config = NULL; + mode_config->fb_base = 0; + ], [ + AC_DEFINE(HAVE_DRM_MODE_CONFIG_FB_BASE, 1, + [drm_mode_config->fb_base is available]) + ]) + ]) +]) + AC_DEFUN([AC_AMDGPU_DRM_MODE_CONFIG], [ AC_AMDGPU_DRM_MODE_CONFIG_FB_MODIFIERS_NOT_SUPPORTED + AC_AMDGPU_DRM_MODE_CONFIG_FB_BASE ]) From b27dbf4b67237635e928c60e6194a4208763a8be Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 21 Feb 2023 23:31:30 +0800 Subject: [PATCH 0885/1868] drm/amdkcl: update config.h Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/config/config.h | 24 +++++++++++++++++++++--- 1 file changed, 21 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 2e14b125d76e1..07ebdbb9ea0d3 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -23,6 +23,9 @@ /* acpi_video_register_backlight() is available */ #define HAVE_ACPI_VIDEO_REGISTER_BACKLIGHT 1 +/* acpi_video_report_nolcd() is available */ +#define HAVE_ACPI_VIDEO_REPORT_NOLCD 1 + /* whether AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES is defined */ #define HAVE_AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 1 @@ -597,12 +600,15 @@ #define HAVE_DRM_ENCODER_FIND_VALID_WITH_FILE 1 /* drm_fbdev_generic_setup() is available */ -#define HAVE_DRM_FBDEV_GENERIC_SETUP 1 +/* #undef HAVE_DRM_FBDEV_GENERIC_SETUP */ /* drm_fb_helper_single_add_all_connectors() && drm_fb_helper_remove_one_connector() are symbol */ /* #undef HAVE_DRM_FB_HELPER_ADD_REMOVE_CONNECTORS */ +/* drm_fb_helper_alloc_info() is available */ +#define HAVE_DRM_FB_HELPER_ALLOC_INFO 1 + /* drm_fb_helper_fill_info() is available */ #define HAVE_DRM_FB_HELPER_FILL_INFO 1 @@ -618,6 +624,9 @@ /* drm_fb_helper_set_suspend_unlocked() is available */ #define HAVE_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED 1 +/* drm_fb_helper_unregister_info() is available */ +#define HAVE_DRM_FB_HELPER_UNREGISTER_INFO 1 + /* drm_firmware_drivers_only() is available */ #define HAVE_DRM_FIRMWARE_DRIVERS_ONLY 1 @@ -702,6 +711,9 @@ /* drm_mode_config->dp_subconnector_property is available */ #define HAVE_DRM_MODE_CONFIG_DP_SUBCONNECTOR_PROPERTY 1 +/* drm_mode_config->fb_base is available */ +/* #undef HAVE_DRM_MODE_CONFIG_FB_BASE */ + /* drm_mode_config->fb_modifiers_not_supported is available */ #define HAVE_DRM_MODE_CONFIG_FB_MODIFIERS_NOT_SUPPORTED 1 @@ -1108,6 +1120,12 @@ /* pxm_to_node() is available */ #define HAVE_PXM_TO_NODE 1 +/* rb_add_cached is available */ +#define HAVE_RB_ADD_CACHED 1 + +/* struct rb_root_cached is available */ +#define HAVE_RB_ROOT_CACHED 1 + /* whether register_shrinker(x, x) is available */ #define HAVE_REGISTER_SHRINKER_WITH_TWO_ARGUMENTS 1 @@ -1383,7 +1401,7 @@ #define PACKAGE_NAME "amdgpu-dkms" /* Define to the full name and version of this package. */ -#define PACKAGE_STRING "amdgpu-dkms 5.19.0" +#define PACKAGE_STRING "amdgpu-dkms 6.1.0" /* Define to the one symbol short name of this package. */ #define PACKAGE_TARNAME "amdgpu-dkms" @@ -1392,7 +1410,7 @@ #define PACKAGE_URL "" /* Define to the version of this package. */ -#define PACKAGE_VERSION "5.19.0" +#define PACKAGE_VERSION "6.1.0" #include "config-amd-chips.h" From 39cc8ec02b6f2cc65f22eef0b77cd415a3b042b7 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 22 Feb 2023 12:22:31 +0800 Subject: [PATCH 0886/1868] drm/amdkcl: wrap the code under macro HAVE_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ARG It's caused by b7cdb41e7d25ceb4f8c1de7343517b29b58e357b drm/amd: Delay removal of the firmware framebuffer Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 057b605053531..da6ff92099a4d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -4175,7 +4175,11 @@ int amdgpu_device_init(struct amdgpu_device *adev, return r; /* Get rid of things like offb */ +#ifdef HAVE_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ARG r = drm_aperture_remove_conflicting_pci_framebuffers(adev->pdev, &amdgpu_kms_driver); +#else + r = drm_aperture_remove_conflicting_pci_framebuffers(pdev, "amdgpudrmfb"); +#endif if (r) return r; From 8e469b61e93de09664ddd44c0144e9eba260a53c Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Mon, 6 Feb 2023 14:52:54 +0800 Subject: [PATCH 0887/1868] drm/amdkcl: kcl-cleanup HAVE___PRINT_ARRAY This reverts commit 0932cfd7e5a93dfe3b19df0e4cfd88b47c236491. and ecd11581e729557a93f588eb1ad76b23100cec04 Change-Id: If5edf6583655ad7f59e528bbd1e3e0e688f3b35a Signed-off-by: Ma Jun Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_ftrace.c | 56 ------------------- drivers/gpu/drm/amd/backport/backport.h | 1 - drivers/gpu/drm/amd/dkms/config/config.h | 3 - .../drm/amd/dkms/m4/ftrace_print_array_seq.m4 | 23 -------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - include/kcl/kcl_ftrace.h | 18 ------ 7 files changed, 1 insertion(+), 103 deletions(-) delete mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_ftrace.c delete mode 100644 drivers/gpu/drm/amd/dkms/m4/ftrace_print_array_seq.m4 delete mode 100644 include/kcl/kcl_ftrace.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 8e3650b52cfc0..db840d6c94c4a 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -10,7 +10,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_fence.o kcl_fence_array.o kcl_reservation.o kcl_drm_cache.o \ kcl_drm_fb.o kcl_drm_print.o kcl_fbmem.o \ kcl_drm_crtc.o kcl_drm_connector.o kcl_drm_atomic_helper.o \ - kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o kcl_ftrace.o \ + kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_fs_read_write.o kcl_drm_aperture.o \ kcl_drm_drv.o kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o \ kcl_mce_amd.o kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_ftrace.c b/drivers/gpu/drm/amd/amdkcl/kcl_ftrace.c deleted file mode 100644 index 115bdc26363a5..0000000000000 --- a/drivers/gpu/drm/amd/amdkcl/kcl_ftrace.c +++ /dev/null @@ -1,56 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * trace_output.c - * - * Copyright (C) 2008 Red Hat Inc, Steven Rostedt - * - */ -#include - -/* Copied from v3.19-rc1-6-g6ea22486ba46 kernel/trace/trace_output.c */ -#if !defined(HAVE___PRINT_ARRAY) -const char * -ftrace_print_array_seq(struct trace_seq *p, const void *buf, int count, - size_t el_size) -{ - const char *ret = trace_seq_buffer_ptr(p); - const char *prefix = ""; - void *ptr = (void *)buf; - size_t buf_len = count * el_size; - - trace_seq_putc(p, '{'); - - while (ptr < buf + buf_len) { - switch (el_size) { - case 1: - trace_seq_printf(p, "%s0x%x", prefix, - *(u8 *)ptr); - break; - case 2: - trace_seq_printf(p, "%s0x%x", prefix, - *(u16 *)ptr); - break; - case 4: - trace_seq_printf(p, "%s0x%x", prefix, - *(u32 *)ptr); - break; - case 8: - trace_seq_printf(p, "%s0x%llx", prefix, - *(u64 *)ptr); - break; - default: - trace_seq_printf(p, "BAD SIZE:%zu 0x%x", el_size, - *(u8 *)ptr); - el_size = 1; - } - prefix = ","; - ptr += el_size; - } - - trace_seq_putc(p, '}'); - trace_seq_putc(p, 0); - - return ret; -} -EXPORT_SYMBOL(ftrace_print_array_seq); -#endif diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 29f5ada3bd6b3..aa1fbf2145202 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -60,7 +60,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 07ebdbb9ea0d3..8dc15b3fc56aa 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1373,9 +1373,6 @@ /* __kthread_should_park() is available */ #define HAVE___KTHREAD_SHOULD_PARK 1 -/* __print_array is available */ -#define HAVE___PRINT_ARRAY 1 - /* kobj_type->default_groups is available */ #define HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/ftrace_print_array_seq.m4 b/drivers/gpu/drm/amd/dkms/m4/ftrace_print_array_seq.m4 deleted file mode 100644 index ecc2aa76f18b1..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/ftrace_print_array_seq.m4 +++ /dev/null @@ -1,23 +0,0 @@ -dnl # -dnl # commit 0fe7e2764d6f -dnl # add new trace event for page table update -dnl # ftrace_print_array_seq() is exported in v3.19-rc1-6-g6ea22486ba46 -dnl # -AC_DEFUN([AC_AMDGPU___PRINT_ARRAY], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([ftrace_print_array_seq], [kernel/trace/trace_output.c], [ - AC_DEFINE(HAVE___PRINT_ARRAY, 1, [__print_array is available]) - ], [ - dnl # - dnl # 645df987f7c - dnl # trace_print_array_seq() is exported in v4.1-rc3-8-g645df987f7c1 - dnl # - AC_KERNEL_CHECK_SYMBOL_EXPORT( - [trace_print_array_seq], - [kernel/trace/trace_output.c],[ - AC_DEFINE(HAVE___PRINT_ARRAY, 1, - [__print_array is available]) - ]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 7d2b87bc21f8d..04c0ded6883b6 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -128,7 +128,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION AC_AMDGPU_JIFFIES64_TO_MSECS - AC_AMDGPU___PRINT_ARRAY AC_AMDGPU_ACPI_PUT_TABLE AC_AMDGPU_DRM_ATOMIC_HELPER_CALC_TIMESTAMPING_CONSTANTS AC_AMDGPU_DRM_FORMAT_INFO diff --git a/include/kcl/kcl_ftrace.h b/include/kcl/kcl_ftrace.h deleted file mode 100644 index ae106eff452b0..0000000000000 --- a/include/kcl/kcl_ftrace.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef AMDKCL_FTRACE_H -#define AMDKCL_FTRACE_H - -#include -/* Copied from v3.19-rc1-6-g6ea22486ba46 include/trace/ftrace.h */ -#if !defined(HAVE___PRINT_ARRAY) -extern const char * ftrace_print_array_seq(struct trace_seq *p, const void *buf, int count, - size_t el_size); -#define __print_array(array, count, el_size) \ - ({ \ - BUILD_BUG_ON(el_size != 1 && el_size != 2 && \ - el_size != 4 && el_size != 8); \ - ftrace_print_array_seq(p, array, count, el_size); \ - }) -#endif - -#endif From 56d2be4339ee5c79d435db5e8382055dc515e2d3 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Mon, 6 Feb 2023 17:10:56 +0800 Subject: [PATCH 0888/1868] drm/amdkcl: kcl-cleanup HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET* cleanup the HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET and HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET_CTX Change-Id: I8e7c105e57c42e4f03c42daac53d1eec132cbfe5 Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4 - drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 211 ------------------ drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 11 - drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 4 - drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 4 - drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 4 - drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 4 - drivers/gpu/drm/amd/dkms/config/config.h | 6 - .../drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 | 35 --- 9 files changed, 283 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 7bde44e0d5fc0..d59f4abed2ce2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -469,11 +469,7 @@ void amdgpu_fence_slab_fini(void); */ struct amdgpu_flip_work { -#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET struct delayed_work flip_work; -#else - struct work_struct flip_work; -#endif struct work_struct unpin_work; struct amdgpu_device *adev; int crtc_id; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 0f169f93a97a1..22c0db8d9d2a3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -103,11 +103,7 @@ static void amdgpu_display_flip_callback(struct dma_fence *f, container_of(cb, struct amdgpu_flip_work, cb); dma_fence_put(f); -#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET schedule_work(&work->flip_work.work); -#else - schedule_work(&work->flip_work); -#endif } static bool amdgpu_display_flip_handle_fence(struct amdgpu_flip_work *work, @@ -128,87 +124,6 @@ static bool amdgpu_display_flip_handle_fence(struct amdgpu_flip_work *work, return false; } -#if !defined(HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET) -static void amdgpu_flip_work_func(struct work_struct *__work) -{ - struct amdgpu_flip_work *work = - container_of(__work, struct amdgpu_flip_work, flip_work); - struct amdgpu_device *adev = work->adev; - struct amdgpu_crtc *amdgpuCrtc = adev->mode_info.crtcs[work->crtc_id]; - - struct drm_crtc *crtc = &amdgpuCrtc->base; - unsigned long flags; - unsigned i, repcnt = 4; - int vpos, hpos, stat, min_udelay = 0; - struct drm_vblank_crtc *vblank = &crtc->dev->vblank[work->crtc_id]; - - - for (i = 0; i < work->shared_count; ++i) - if (amdgpu_display_flip_handle_fence(work, &work->shared[i])) - return; - - /* We borrow the event spin lock for protecting flip_status */ - spin_lock_irqsave(&crtc->dev->event_lock, flags); - - /* If this happens to execute within the "virtually extended" vblank - * interval before the start of the real vblank interval then it needs - * to delay programming the mmio flip until the real vblank is entered. - * This prevents completing a flip too early due to the way we fudge - * our vblank counter and vblank timestamps in order to work around the - * problem that the hw fires vblank interrupts before actual start of - * vblank (when line buffer refilling is done for a frame). It - * complements the fudging logic in amdgpu_display_get_crtc_scanoutpos() for - * timestamping and amdgpu_get_vblank_counter_kms() for vblank counts. - * - * In practice this won't execute very often unless on very fast - * machines because the time window for this to happen is very small. - */ - while (amdgpuCrtc->enabled && --repcnt) { - /* GET_DISTANCE_TO_VBLANKSTART returns distance to real vblank - * start in hpos, and to the "fudged earlier" vblank start in - * vpos. - */ - stat = amdgpu_display_get_crtc_scanoutpos(adev_to_drm(adev), work->crtc_id, - GET_DISTANCE_TO_VBLANKSTART, - &vpos, &hpos, NULL, NULL, - &crtc->hwmode); - - if ((stat & (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE)) != - (DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE) || - !(vpos >= 0 && hpos <= 0)) - break; - - /* Sleep at least until estimated real start of hw vblank */ - min_udelay = (-hpos + 1) * max(vblank->linedur_ns / 1000, 5); - if (min_udelay > vblank->framedur_ns / 2000) { - /* Don't wait ridiculously long - something is wrong */ - repcnt = 0; - break; - } - spin_unlock_irqrestore(&crtc->dev->event_lock, flags); - usleep_range(min_udelay, 2 * min_udelay); - spin_lock_irqsave(&crtc->dev->event_lock, flags); - } - - if (!repcnt) - DRM_DEBUG_DRIVER("Delay problem on crtc %d: min_udelay %d, " - "framedur %d, linedur %d, stat %d, vpos %d, " - "hpos %d\n", work->crtc_id, min_udelay, - vblank->framedur_ns / 1000, - vblank->linedur_ns / 1000, stat, vpos, hpos); - - /* Do the flip (mmio) */ - adev->mode_info.funcs->page_flip(adev, work->crtc_id, work->base, work->async); - - /* Set the flip status */ - amdgpuCrtc->pflip_status = AMDGPU_FLIP_SUBMITTED; - spin_unlock_irqrestore(&crtc->dev->event_lock, flags); - - - DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_SUBMITTED, work: %p,\n", - amdgpuCrtc->crtc_id, amdgpuCrtc, work); -} -#else static void amdgpu_display_flip_work_func(struct work_struct *__work) { struct delayed_work *delayed_work = @@ -258,7 +173,6 @@ static void amdgpu_display_flip_work_func(struct work_struct *__work) amdgpu_crtc->crtc_id, amdgpu_crtc, work); } -#endif /* * Handle unpin events outside the interrupt handler proper. @@ -282,16 +196,11 @@ static void amdgpu_display_unpin_work_func(struct work_struct *__work) kfree(work); } -#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc, struct drm_framebuffer *fb, struct drm_pending_vblank_event *event, -#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET_CTX uint32_t page_flip_flags, uint32_t target, struct drm_modeset_acquire_ctx *ctx) -#else - uint32_t page_flip_flags, uint32_t target) -#endif { struct drm_device *dev = crtc->dev; struct amdgpu_device *adev = drm_to_adev(dev); @@ -405,127 +314,7 @@ int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc, return r; } -#else -int amdgpu_crtc_page_flip(struct drm_crtc *crtc, - struct drm_framebuffer *fb, - struct drm_pending_vblank_event *event, - uint32_t page_flip_flags) -{ - struct drm_device *dev = crtc->dev; - struct amdgpu_device *adev = drm_to_adev(dev); - struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); - struct amdgpu_framebuffer *old_amdgpu_fb; - struct amdgpu_framebuffer *new_amdgpu_fb; - struct drm_gem_object *obj; - struct amdgpu_flip_work *work; - struct amdgpu_bo *new_abo; - unsigned long flags; - u64 tiling_flags; - u64 base; - int i, r; - - work = kzalloc(sizeof *work, GFP_KERNEL); - if (work == NULL) - return -ENOMEM; - - INIT_WORK(&work->flip_work, amdgpu_flip_work_func); - INIT_WORK(&work->unpin_work, amdgpu_display_unpin_work_func); - - work->event = event; - work->adev = adev; - work->crtc_id = amdgpu_crtc->crtc_id; - work->async = (page_flip_flags & DRM_MODE_PAGE_FLIP_ASYNC) != 0; - - /* schedule unpin of the old buffer */ - old_amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb); - obj = old_amdgpu_fb->obj; - - /* take a reference to the old object */ - work->old_abo = gem_to_amdgpu_bo(obj); - amdgpu_bo_ref(work->old_abo); - - new_amdgpu_fb = to_amdgpu_framebuffer(fb); - obj = new_amdgpu_fb->obj; - new_abo = gem_to_amdgpu_bo(obj); - /* pin the new buffer */ - r = amdgpu_bo_reserve(new_abo, false); - if (unlikely(r != 0)) { - DRM_ERROR("failed to reserve new abo buffer before flip\n"); - goto cleanup; - } - - r = amdgpu_bo_pin(new_abo, AMDGPU_GEM_DOMAIN_VRAM); - if (unlikely(r != 0)) { - r = -EINVAL; - DRM_ERROR("failed to pin new abo buffer before flip\n"); - goto unreserve; - } - - r = dma_resv_get_fences(amdkcl_ttm_resvp(&new_abo->tbo), DMA_RESV_USAGE_WRITE, - &work->shared_count, - &work->shared); - if (unlikely(r != 0)) { - DRM_ERROR("failed to get fences for buffer\n"); - goto unpin; - } - - amdgpu_bo_get_tiling_flags(new_abo, &tiling_flags); - amdgpu_bo_unreserve(new_abo); - - work->base = base; - - r = drm_crtc_vblank_get(crtc); - if (r) { - DRM_ERROR("failed to get vblank before flip\n"); - goto pflip_cleanup; - } - - /* we borrow the event spin lock for protecting flip_wrok */ - spin_lock_irqsave(&crtc->dev->event_lock, flags); - if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_NONE) { - DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); - spin_unlock_irqrestore(&crtc->dev->event_lock, flags); - r = -EBUSY; - goto vblank_cleanup; - } - - amdgpu_crtc->pflip_status = AMDGPU_FLIP_PENDING; - amdgpu_crtc->pflip_works = work; - - - DRM_DEBUG_DRIVER("crtc:%d[%p], pflip_stat:AMDGPU_FLIP_PENDING, work: %p,\n", - amdgpu_crtc->crtc_id, amdgpu_crtc, work); - /* update crtc fb */ - crtc->primary->fb = fb; - spin_unlock_irqrestore(&crtc->dev->event_lock, flags); - amdgpu_flip_work_func(&work->flip_work); - return 0; - -vblank_cleanup: - drm_crtc_vblank_put(crtc); - -pflip_cleanup: - if (unlikely(amdgpu_bo_reserve(new_abo, false) != 0)) { - DRM_ERROR("failed to reserve new abo in error path\n"); - goto cleanup; - } -unpin: - amdgpu_bo_unpin(new_abo); - -unreserve: - amdgpu_bo_unreserve(new_abo); - -cleanup: - amdgpu_bo_unref(&work->old_abo); - for (i = 0; i < work->shared_count; ++i) - fence_put(work->shared[i]); - kfree(work->shared); - kfree(work); - - return r; -} -#endif #ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_SET_CONFIG_CTX int amdgpu_display_crtc_set_config(struct drm_mode_set *set, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index 70caa28fa86f2..4776e7179b944 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -747,22 +747,11 @@ int amdgpu_display_crtc_set_config(struct drm_mode_set *set, int amdgpu_display_crtc_set_config(struct drm_mode_set *set); #endif -#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc, struct drm_framebuffer *fb, struct drm_pending_vblank_event *event, -#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET_CTX uint32_t page_flip_flags, uint32_t target, struct drm_modeset_acquire_ctx *ctx); -#else - uint32_t page_flip_flags, uint32_t target); -#endif -#else -int amdgpu_crtc_page_flip(struct drm_crtc *crtc, - struct drm_framebuffer *fb, - struct drm_pending_vblank_event *event, - uint32_t page_flip_flags); -#endif extern const struct drm_mode_config_funcs amdgpu_mode_funcs; diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index 5d3e9b2470a3a..17f856a381aee 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -2570,11 +2570,7 @@ static const struct drm_crtc_funcs dce_v10_0_crtc_funcs = { .gamma_set = dce_v10_0_crtc_gamma_set, .set_config = amdgpu_display_crtc_set_config, .destroy = dce_v10_0_crtc_destroy, -#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET .page_flip_target = amdgpu_display_crtc_page_flip_target, -#else - .page_flip = amdgpu_crtc_page_flip, -#endif #ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP .get_vblank_counter = amdgpu_get_vblank_counter_kms, .enable_vblank = amdgpu_enable_vblank_kms, diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index 27e62bca0a245..3651495cd51e8 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -2654,11 +2654,7 @@ static const struct drm_crtc_funcs dce_v11_0_crtc_funcs = { .gamma_set = dce_v11_0_crtc_gamma_set, .set_config = amdgpu_display_crtc_set_config, .destroy = dce_v11_0_crtc_destroy, -#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET .page_flip_target = amdgpu_display_crtc_page_flip_target, -#else - .page_flip = amdgpu_crtc_page_flip, -#endif #ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP .get_vblank_counter = amdgpu_get_vblank_counter_kms, .enable_vblank = amdgpu_enable_vblank_kms, diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c index c64935de10841..269feee4e1574 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c @@ -2497,11 +2497,7 @@ static const struct drm_crtc_funcs dce_v6_0_crtc_funcs = { .gamma_set = dce_v6_0_crtc_gamma_set, .set_config = amdgpu_display_crtc_set_config, .destroy = dce_v6_0_crtc_destroy, -#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET .page_flip_target = amdgpu_display_crtc_page_flip_target, -#else - .page_flip = amdgpu_crtc_page_flip, -#endif #ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP .get_vblank_counter = amdgpu_get_vblank_counter_kms, .enable_vblank = amdgpu_enable_vblank_kms, diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index 70f859818b76a..aa6172c564aaa 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -2488,11 +2488,7 @@ static const struct drm_crtc_funcs dce_v8_0_crtc_funcs = { .gamma_set = dce_v8_0_crtc_gamma_set, .set_config = amdgpu_display_crtc_set_config, .destroy = dce_v8_0_crtc_destroy, -#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET .page_flip_target = amdgpu_display_crtc_page_flip_target, -#else - .page_flip = amdgpu_crtc_page_flip, -#endif #ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP .get_vblank_counter = amdgpu_get_vblank_counter_kms, .enable_vblank = amdgpu_enable_vblank_kms, diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 8dc15b3fc56aa..82f2bab540ae6 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1213,12 +1213,6 @@ /* drm_crtc_funcs->{get,verify}_crc_sources() is available */ #define HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VERIFY_CRC_SOURCES 1 -/* drm_crtc_funcs->page_flip_target() is available */ -#define HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET 1 - -/* drm_crtc_funcs->page_flip_target() wants ctx parameter */ -#define HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET_CTX 1 - /* drm_crtc_funcs->set_config() wants ctx parameter */ #define HAVE_STRUCT_DRM_CRTC_FUNCS_SET_CONFIG_CTX 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 index 41d85b15ac85f..a50e4f519bafd 100644 --- a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 @@ -39,40 +39,6 @@ AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_SET_CONFIG], [ ]) ]) -dnl # -dnl # v4.11-rc3-945-g41292b1fa13a -dnl # drm: Add acquire ctx parameter to ->page_flip(_target) -dnl # -AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - struct drm_crtc_funcs *funcs = NULL; - funcs->page_flip_target(NULL, NULL, NULL, 0, 0, NULL); - ], [ - AC_DEFINE(HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET_CTX, 1, - [drm_crtc_funcs->page_flip_target() wants ctx parameter]) - AC_DEFINE(HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET, 1, - [drm_crtc_funcs->page_flip_target() is available]) - ], [ - dnl # - dnl # v4.8-rc1-112-gc229bfbbd04a - dnl # drm: Add page_flip_target CRTC hook v2 - dnl # - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - struct drm_crtc_funcs *funcs = NULL; - funcs->page_flip_target(NULL, NULL, NULL, 0, 0); - ], [ - AC_DEFINE(HAVE_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET, 1, - [drm_crtc_funcs->page_flip_target() is available]) - ]) - ]) - ]) -]) - dnl # dnl # commit v4.10-rc5-1070-g84e354839b15 dnl # drm: add vblank hooks to struct drm_crtc_funcs @@ -194,7 +160,6 @@ AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS], [ AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_ENABLE_VBLANK AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GET_VERIFY_CRC_SOURCES AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_SET_CONFIG - AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_PAGE_FLIP_TARGET AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_LATE_REGISTER From 126810d16e245b06e2243843d98b554374e40aea Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Tue, 7 Feb 2023 10:03:49 +0800 Subject: [PATCH 0889/1868] drm/amdkcl: kcl-cleanup HAVE_STRUCT_DRM_CRTC_FUNCS_LATE_REGISTER Revert "drm/amdkcl: Check if drm_crtc_funcs->late_register() is defined" This reverts commit d3b4a52d2f8394b6d8e309e99a0cda2c7a8de651. Change-Id: I9d026fa4c039e635b2d55b89a895abf996592d73 Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- .../amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 4 ---- drivers/gpu/drm/amd/dkms/config/config.h | 9 --------- .../drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 | 19 ------------------- 3 files changed, 32 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c index 22d05c450b4d4..ff25b4b928ee6 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c @@ -466,7 +466,6 @@ static void amdgpu_dm_crtc_reset_state(struct drm_crtc *crtc) } #ifdef CONFIG_DEBUG_FS -#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_LATE_REGISTER static int amdgpu_dm_crtc_late_register(struct drm_crtc *crtc) { crtc_debugfs_init(crtc); @@ -474,7 +473,6 @@ static int amdgpu_dm_crtc_late_register(struct drm_crtc *crtc) return 0; } #endif -#endif #ifdef AMD_PRIVATE_COLOR /** @@ -565,10 +563,8 @@ static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = { .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, #endif #if defined(CONFIG_DEBUG_FS) -#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_LATE_REGISTER .late_register = amdgpu_dm_crtc_late_register, #endif -#endif #ifdef AMD_PRIVATE_COLOR .atomic_set_property = amdgpu_dm_atomic_crtc_set_property, .atomic_get_property = amdgpu_dm_atomic_crtc_get_property, diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 82f2bab540ae6..0ad029e6f6e51 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1216,15 +1216,6 @@ /* drm_crtc_funcs->set_config() wants ctx parameter */ #define HAVE_STRUCT_DRM_CRTC_FUNCS_SET_CONFIG_CTX 1 -/* drm_crtc_funcs->late_register() is available */ -#define HAVE_STRUCT_DRM_CRTC_FUNCS_LATE_REGISTER 1 - -/* crtc->funcs->set_crc_source() is available */ -#define HAVE_STRUCT_DRM_CRTC_FUNCS_SET_CRC_SOURCE 1 - -/* crtc->funcs->set_crc_source() wants 2 args */ -#define HAVE_STRUCT_DRM_CRTC_FUNCS_SET_CRC_SOURCE_2ARGS 1 - /* struct drm_crtc_state->async_flip is available */ #define HAVE_STRUCT_DRM_CRTC_STATE_ASYNC_FLIP 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 index a50e4f519bafd..a51f0225b4ad1 100644 --- a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 @@ -137,24 +137,6 @@ AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL], [ ]) ]) -dnl # -dnl # commit v4.8-rc1~62-79190ea26 -dnl # drm: Add callbacks for late registering -dnl # -AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_LATE_REGISTER], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - struct drm_crtc_funcs *crtc_funcs = NULL; - crtc_funcs->late_register(NULL); - ], [ - AC_DEFINE(HAVE_STRUCT_DRM_CRTC_FUNCS_LATE_REGISTER, 1, [ - drm_crtc_funcs->late_register() is available]) - ]) - ]) -]) - AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS], [ AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_ENABLE_VBLANK @@ -162,5 +144,4 @@ AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS], [ AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_SET_CONFIG AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL - AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_LATE_REGISTER ]) From bf2e9e42acac13d689e76d115137c3dac69ced80 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Tue, 7 Feb 2023 10:26:52 +0800 Subject: [PATCH 0890/1868] drm/amdkcl: kcl-cleanup HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_5ARGS/6ARGS Revert "drm/amdkcl: test drm_crtc_funcs->gamma_set" This reverts commit 4953b2eebbb829ceb89fd09b9edf67feae804a9d. Change-Id: Ie40ae7f3b4608af54680497403c1c12befae1143 Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 21 -------- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 21 -------- drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 21 -------- drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 21 -------- drivers/gpu/drm/amd/dkms/config/config.h | 6 --- .../drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 | 48 ------------------- 6 files changed, 138 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index 17f856a381aee..a0c6443568c46 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -2526,12 +2526,6 @@ static void dce_v10_0_cursor_reset(struct drm_crtc *crtc) } } -/* - * TODO: drm_fb_helper_setcmap() prev commit v4.12-rc7-1385-g964c60063bff - * ("drm/fb-helper: separate the fb_setcmap helper into atomic and legacy paths") - * don't work as expected. - */ -#if defined(HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_6ARGS) static int dce_v10_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, u16 *blue, uint32_t size, struct drm_modeset_acquire_ctx *ctx) @@ -2540,21 +2534,6 @@ static int dce_v10_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, return 0; } -#elif defined(HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_5ARGS) -static int dce_v10_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, - u16 *blue, uint32_t size) -{ - dce_v10_0_crtc_load_lut(crtc); - - return 0; -} -#else -static void dce_v10_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, - u16 *blue, uint32_t start, uint32_t size) -{ - dce_v10_0_crtc_load_lut(crtc); -} -#endif static void dce_v10_0_crtc_destroy(struct drm_crtc *crtc) { diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index 3651495cd51e8..c22e723ac9078 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -2610,12 +2610,6 @@ static void dce_v11_0_cursor_reset(struct drm_crtc *crtc) } } -/* - * TODO: drm_fb_helper_setcmap() prev commit v4.12-rc7-1385-g964c60063bff - * ("drm/fb-helper: separate the fb_setcmap helper into atomic and legacy paths") - * don't work as expected. - */ -#if defined(HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_6ARGS) static int dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, u16 *blue, uint32_t size, struct drm_modeset_acquire_ctx *ctx) @@ -2624,21 +2618,6 @@ static int dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, return 0; } -#elif defined(HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_5ARGS) -static int dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, - u16 *blue, uint32_t size) -{ - dce_v11_0_crtc_load_lut(crtc); - - return 0; -} -#else -static void dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, - u16 *blue, uint32_t start, uint32_t size) -{ - dce_v11_0_crtc_load_lut(crtc); -} -#endif static void dce_v11_0_crtc_destroy(struct drm_crtc *crtc) { diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c index 269feee4e1574..94df91bd93558 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c @@ -2453,12 +2453,6 @@ static void dce_v6_0_cursor_reset(struct drm_crtc *crtc) } } -/* - * TODO: drm_fb_helper_setcmap() prev commit v4.12-rc7-1385-g964c60063bff - * ("drm/fb-helper: separate the fb_setcmap helper into atomic and legacy paths") - * don't work as expected. - */ -#if defined(HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_6ARGS) static int dce_v6_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, u16 *blue, uint32_t size, struct drm_modeset_acquire_ctx *ctx) @@ -2467,21 +2461,6 @@ static int dce_v6_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, return 0; } -#elif defined(HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_5ARGS) -static int dce_v6_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, - u16 *blue, uint32_t size) -{ - dce_v6_0_crtc_load_lut(crtc); - - return 0; -} -#else -static void dce_v6_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, - u16 *blue, uint32_t start, uint32_t size) -{ - dce_v6_0_crtc_load_lut(crtc); -} -#endif static void dce_v6_0_crtc_destroy(struct drm_crtc *crtc) { diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index aa6172c564aaa..85cefb518ce2d 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -2444,12 +2444,6 @@ static void dce_v8_0_cursor_reset(struct drm_crtc *crtc) } } -/* - * TODO: drm_fb_helper_setcmap() prev commit v4.12-rc7-1385-g964c60063bff - * ("drm/fb-helper: separate the fb_setcmap helper into atomic and legacy paths") - * don't work as expected. - */ -#if defined(HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_6ARGS) static int dce_v8_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, u16 *blue, uint32_t size, struct drm_modeset_acquire_ctx *ctx) @@ -2458,21 +2452,6 @@ static int dce_v8_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, return 0; } -#elif defined(HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_5ARGS) -static int dce_v8_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, - u16 *blue, uint32_t size) -{ - dce_v8_0_crtc_load_lut(crtc); - - return 0; -} -#else -static void dce_v8_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, - u16 *blue, uint32_t start, uint32_t size) -{ - dce_v8_0_crtc_load_lut(crtc); -} -#endif static void dce_v8_0_crtc_destroy(struct drm_crtc *crtc) { diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 0ad029e6f6e51..955a5f9c9a17d 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1198,12 +1198,6 @@ /* drm_crtc_funcs->enable_vblank() is available */ #define HAVE_STRUCT_DRM_CRTC_FUNCS_ENABLE_VBLANK 1 -/* crtc->funcs->gamma_set() wants 5 args */ -/* #undef HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_5ARGS */ - -/* crtc->funcs->gamma_set() wants 6 args */ -#define HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_6ARGS 1 - /* HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL is available */ #define HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 index a51f0225b4ad1..2e19306272912 100644 --- a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 @@ -78,53 +78,6 @@ AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GET_VERIFY_CRC_SOURCES], [ ]) ]) -dnl # -dnl # v4.11-rc5-1392-g6d124ff84533 drm: Add acquire ctx to ->gamma_set hook -dnl # int (*gamma_set)(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, -dnl # - uint32_t size); -dnl # + uint32_t size, -dnl # + struct drm_modeset_acquire_ctx *ctx); -dnl # v4.7-rc1-260-g7ea772838782 drm/core: Change declaration for gamma_set. -dnl # - void (*gamma_set)(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, -dnl # - uint32_t start, uint32_t size); -dnl # + int (*gamma_set)(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, -dnl # + uint32_t size); -dnl # v2.6.35-260-g7203425a943e drm: expand gamma_set -dnl # void (*gamma_set)(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, -dnl # - uint32_t size); -dnl # + uint32_t start, uint32_t size); -dnl # v2.6.28-8-gf453ba046074 DRM: add mode setting support -dnl # + void (*gamma_set)(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, -dnl # + uint32_t size); -dnl # -AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - struct drm_crtc *crtc = NULL; - int ret; - - ret = crtc->funcs->gamma_set(NULL, NULL, NULL, NULL, 0, NULL); - ], [ - AC_DEFINE(HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_6ARGS, 1, - [crtc->funcs->gamma_set() wants 6 args]) - ], [ - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - struct drm_crtc *crtc = NULL; - int ret; - - ret = crtc->funcs->gamma_set(NULL, NULL, NULL, NULL, 0); - ], [ - AC_DEFINE(HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_5ARGS, 1, - [crtc->funcs->gamma_set() wants 5 args]) - ]) - ]) - ]) -]) - dnl # dnl # v5.10-1961-g6ca2ab8086af drm: automatic legacy gamma support dnl # @@ -142,6 +95,5 @@ AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS], [ AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_ENABLE_VBLANK AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GET_VERIFY_CRC_SOURCES AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_SET_CONFIG - AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL ]) From 5f0f7ab154038f8a891ae12d3b0017f434e55cd5 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Tue, 7 Feb 2023 15:04:42 +0800 Subject: [PATCH 0891/1868] drm/amdkcl: kcl-cleanup HAVE_LINUX_DMA_FENCE_H cleanup the HAVE_LINUX_DMA_FENCE_H and refactor related code Change-Id: I72ea2ff319cb741ff236dad4b8c30e770291807c Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_fence.c | 4 - drivers/gpu/drm/amd/amdkcl/kcl_fence_array.c | 149 ------------------ drivers/gpu/drm/amd/dkms/config/config.h | 3 - .../gpu/drm/amd/dkms/m4/dma-fence-headers.m4 | 18 --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 | 6 +- include/kcl/header/linux/dma-fence-array.h | 6 +- include/kcl/header/linux/dma-fence.h | 11 -- include/kcl/kcl_dma_fence.h | 4 +- include/kcl/kcl_dma_fence_chain.h | 4 - include/kcl/kcl_fence.h | 44 ------ include/kcl/kcl_fence_array.h | 93 ----------- 13 files changed, 10 insertions(+), 335 deletions(-) delete mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_fence_array.c delete mode 100644 drivers/gpu/drm/amd/dkms/m4/dma-fence-headers.m4 delete mode 100644 include/kcl/header/linux/dma-fence.h delete mode 100644 include/kcl/kcl_fence_array.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index db840d6c94c4a..0accf6c787b2b 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -7,7 +7,7 @@ amdkcl-y += dma-buf/dma-resv.o amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_kthread.o kcl_io.o kcl_perf_event.o kcl_seq_file.o \ kcl_suspend.o kcl_pci.o kcl_mm.o kcl_memory.o kcl_sched.o \ - kcl_fence.o kcl_fence_array.o kcl_reservation.o kcl_drm_cache.o \ + kcl_fence.o kcl_reservation.o kcl_drm_cache.o \ kcl_drm_fb.o kcl_drm_print.o kcl_fbmem.o \ kcl_drm_crtc.o kcl_drm_connector.o kcl_drm_atomic_helper.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o \ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fence.c b/drivers/gpu/drm/amd/amdkcl/kcl_fence.c index 1969d6e0f289c..6b962278954e6 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_fence.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fence.c @@ -238,11 +238,7 @@ EXPORT_SYMBOL(_kcl_fence_enable_signaling); */ void amdkcl_fence_init(void) { -#if defined(HAVE_LINUX_DMA_FENCE_H) _kcl_fence_default_wait_cb = amdkcl_fp_setup("dma_fence_default_wait_cb", NULL); -#else - _kcl_fence_default_wait_cb = amdkcl_fp_setup("fence_default_wait_cb", NULL); -#endif } #if !defined(HAVE_DMA_FENCE_DESCRIBE) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fence_array.c b/drivers/gpu/drm/amd/amdkcl/kcl_fence_array.c deleted file mode 100644 index d42a986ecfe1d..0000000000000 --- a/drivers/gpu/drm/amd/amdkcl/kcl_fence_array.c +++ /dev/null @@ -1,149 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * fence-array: aggregate fences to be waited together - * - * Copyright (C) 2016 Collabora Ltd - * Copyright (C) 2016 Advanced Micro Devices, Inc. - * Authors: - * Gustavo Padovan - * Christian König - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#include -#include -#include -#include - -#if !defined(HAVE_LINUX_DMA_FENCE_H) && !defined(HAVE_LINUX_FENCE_ARRAY_H) -static void fence_array_cb_func(struct fence *f, struct fence_cb *cb); - -static const char *fence_array_get_driver_name(struct fence *fence) -{ - return "fence_array"; -} - -static const char *fence_array_get_timeline_name(struct fence *fence) -{ - return "unbound"; -} - -static void fence_array_cb_func(struct fence *f, struct fence_cb *cb) -{ - struct fence_array_cb *array_cb = - container_of(cb, struct fence_array_cb, cb); - struct fence_array *array = array_cb->array; - - if (atomic_dec_and_test(&array->num_pending)) - fence_signal(&array->base); - fence_put(&array->base); -} - -static bool fence_array_enable_signaling(struct fence *fence) -{ - struct fence_array *array = to_fence_array(fence); - struct fence_array_cb *cb = (void *)(&array[1]); - unsigned i; - - for (i = 0; i < array->num_fences; ++i) { - cb[i].array = array; - /* - * As we may report that the fence is signaled before all - * callbacks are complete, we need to take an additional - * reference count on the array so that we do not free it too - * early. The core fence handling will only hold the reference - * until we signal the array as complete (but that is now - * insufficient). - */ - fence_get(&array->base); - if (fence_add_callback(array->fences[i], &cb[i].cb, - fence_array_cb_func)) { - fence_put(&array->base); - if (atomic_dec_and_test(&array->num_pending)) - return false; - } - } - - return true; -} - -static bool fence_array_signaled(struct fence *fence) -{ - struct fence_array *array = to_fence_array(fence); - - return atomic_read(&array->num_pending) <= 0; -} - -static void fence_array_release(struct fence *fence) -{ - struct fence_array *array = to_fence_array(fence); - unsigned i; - - for (i = 0; i < array->num_fences; ++i) - fence_put(array->fences[i]); - - kfree(array->fences); - fence_free(fence); -} - -const struct fence_ops fence_array_ops = { - .get_driver_name = fence_array_get_driver_name, - .get_timeline_name = fence_array_get_timeline_name, - .enable_signaling = fence_array_enable_signaling, - .signaled = fence_array_signaled, - .wait = _kcl_fence_default_wait, - .release = fence_array_release, -}; - -/** - * fence_array_create - Create a custom fence array - * @num_fences: [in] number of fences to add in the array - * @fences: [in] array containing the fences - * @context: [in] fence context to use - * @seqno: [in] sequence number to use - * @signal_on_any [in] signal on any fence in the array - * - * Allocate a fence_array object and initialize the base fence with fence_init(). - * In case of error it returns NULL. - * - * The caller should allocte the fences array with num_fences size - * and fill it with the fences it wants to add to the object. Ownership of this - * array is take and fence_put() is used on each fence on release. - * - * If @signal_on_any is true the fence array signals if any fence in the array - * signals, otherwise it signals when all fences in the array signal. - */ -struct fence_array *fence_array_create(int num_fences, struct fence **fences, - u64 context, unsigned seqno, - bool signal_on_any) -{ - struct fence_array *array; - size_t size = sizeof(*array); - - /* Allocate the callback structures behind the array. */ - size += num_fences * sizeof(struct fence_array_cb); - array = kzalloc(size, GFP_KERNEL); - if (!array) - return NULL; - - spin_lock_init(&array->lock); - fence_init(&array->base, &fence_array_ops, &array->lock, - context, seqno); - - array->num_fences = num_fences; - atomic_set(&array->num_pending, signal_on_any ? 1 : num_fences); - array->fences = fences; - - return array; -} -EXPORT_SYMBOL(fence_array_create); - -#endif /* !defined(HAVE_LINUX_DMA_FENCE_H) && !defined(HAVE_LINUX_FENCE_ARRAY_H) */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 955a5f9c9a17d..77b05f13f101a 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -961,9 +961,6 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_DMA_FENCE_CHAIN_H 1 -/* Define to 1 if you have the header file. */ -#define HAVE_LINUX_DMA_FENCE_H 1 - /* Define to 1 if you have the header file. */ #define HAVE_LINUX_DMA_MAP_OPS_H 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-fence-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-fence-headers.m4 deleted file mode 100644 index 843491bfe3aef..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/dma-fence-headers.m4 +++ /dev/null @@ -1,18 +0,0 @@ -dnl # -dnl # commit f54d1867005c3323f5d8ad83eed823e84226c429 -dnl # dma-buf: Rename struct fence to dma_fence -dnl # -AC_DEFUN([AC_AMDGPU_DMA_FENCE_HEADERS], [ - AS_IF([test $HAVE_LINUX_DMA_FENCE_H], [ - AC_KERNEL_DO_BACKGROUND([ - ]) - ], [ - dnl # - dnl # commit b3dfbdf261e076a997f812323edfdba84ba80256 - dnl # dma-buf/fence: add fence_array fences v6 - dnl # - AC_KERNEL_CHECK_HEADERS([linux/fence-array.h]) - AC_KERNEL_DO_BACKGROUND([ - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 04c0ded6883b6..e9e3686bf8c51 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -51,7 +51,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_MMU_NOTIFIER_CALL_SRCU AC_AMDGPU_MM_RELEASE_PAGES AC_AMDGPU_SCHED_SET_FIFO_LOW - AC_AMDGPU_DMA_FENCE_HEADERS AC_AMDGPU_DMA_RESV AC_AMDGPU_TTM_SG_TT_INIT AC_AMDGPU_TTM_BUFFER_OBJECT diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 index 0b21b17421ef2..c90bc2c7d2fd7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 @@ -38,10 +38,10 @@ AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ AC_KERNEL_CHECK_HEADERS([linux/compiler_attributes.h]) dnl # - dnl # v4.9-rc2-299-gf54d1867005c - dnl # dma-buf: Rename struct fence to dma_fence + dnl # commit b3dfbdf261e076a997f812323edfdba84ba80256 + dnl # dma-buf/fence: add fence_array fences v6 dnl # - AC_KERNEL_CHECK_HEADERS([linux/dma-fence.h]) + AC_KERNEL_CHECK_HEADERS([linux/fence-array.h]) dnl # dnl # v5.3-rc1-449-g52791eeec1d9 diff --git a/include/kcl/header/linux/dma-fence-array.h b/include/kcl/header/linux/dma-fence-array.h index 49bb1fcd2a798..bc3d2e4bbaca2 100644 --- a/include/kcl/header/linux/dma-fence-array.h +++ b/include/kcl/header/linux/dma-fence-array.h @@ -2,10 +2,10 @@ #ifndef _KCL_HEADER__LINUX_DMA_FENCE_ARRAY_H_H_ #define _KCL_HEADER__LINUX_DMA_FENCE_ARRAY_H_H_ -#if defined(HAVE_LINUX_DMA_FENCE_H) +#if !defined(HAVE_LINUX_FENCE_ARRAY_H) #include_next -#elif defined(HAVE_LINUX_FENCE_ARRAY_H) -#include +#else +#include_next #endif #endif diff --git a/include/kcl/header/linux/dma-fence.h b/include/kcl/header/linux/dma-fence.h deleted file mode 100644 index d4bb6177302a3..0000000000000 --- a/include/kcl/header/linux/dma-fence.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -#ifndef _KCL_HEADER__LINUX_DMA_FENCE_H_H_ -#define _KCL_HEADER__LINUX_DMA_FENCE_H_H_ - -#if defined(HAVE_LINUX_DMA_FENCE_H) -#include_next -#else -#include -#endif - -#endif diff --git a/include/kcl/kcl_dma_fence.h b/include/kcl/kcl_dma_fence.h index cbf594a40d4de..20a014352f967 100644 --- a/include/kcl/kcl_dma_fence.h +++ b/include/kcl/kcl_dma_fence.h @@ -14,9 +14,11 @@ #define AMDKCL_DMA_FENCE_H #ifndef HAVE_DMA_FENCE_IS_CONTAINER -#include #include +#if !defined(HAVE_LINUX_FENCE_ARRAY_H) +#include +#endif /** * dma_fence_is_chain - check if a fence is from the chain subclass * @fence: the fence to test diff --git a/include/kcl/kcl_dma_fence_chain.h b/include/kcl/kcl_dma_fence_chain.h index b7b66a3b93c90..97900481479c5 100644 --- a/include/kcl/kcl_dma_fence_chain.h +++ b/include/kcl/kcl_dma_fence_chain.h @@ -14,11 +14,7 @@ #endif #if !defined(HAVE_STRUCT_DMA_FENCE_CHAIN) -#ifdef HAVE_LINUX_DMA_FENCE_H #include -#else -#include -#endif #include #include diff --git a/include/kcl/kcl_fence.h b/include/kcl/kcl_fence.h index e8adf7bef1c57..a4a94e8a03e54 100644 --- a/include/kcl/kcl_fence.h +++ b/include/kcl/kcl_fence.h @@ -15,36 +15,6 @@ #include #include #include -#include - -#if !defined(HAVE_LINUX_DMA_FENCE_H) -#define dma_fence_cb fence_cb -#define dma_fence_ops fence_ops -#define dma_fence_array fence_array -#define dma_fence fence -#define dma_fence_init fence_init -#define dma_fence_context_alloc fence_context_alloc -#define DMA_FENCE_TRACE FENCE_TRACE -#define DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT FENCE_FLAG_ENABLE_SIGNAL_BIT -#define DMA_FENCE_FLAG_SIGNALED_BIT FENCE_FLAG_SIGNALED_BIT -#define DMA_FENCE_FLAG_USER_BITS FENCE_FLAG_USER_BITS -#define dma_fence_wait fence_wait -#define dma_fence_get fence_get -#define dma_fence_put fence_put -#define dma_fence_is_signaled fence_is_signaled -#define dma_fence_signal fence_signal -#define dma_fence_signal_locked fence_signal_locked -#define dma_fence_get_rcu fence_get_rcu -#define dma_fence_array_create fence_array_create -#define dma_fence_add_callback fence_add_callback -#define dma_fence_remove_callback fence_remove_callback -#define dma_fence_enable_sw_signaling fence_enable_sw_signaling -#define dma_fence_default_wait fence_default_wait -#define dma_fence_free fence_free -#define dma_fence_get_rcu_safe fence_get_rcu - -#define dma_fence_set_error fence_set_error -#endif #if !defined(HAVE__DMA_FENCE_IS_LATER_2ARGS) @@ -81,20 +51,6 @@ static inline bool __dma_fence_is_later(u64 f1, u64 f2, #endif #endif /* HAVE__DMA_FENCE_IS_LATER_2ARGS */ -/* commit v4.5-rc3-715-gb47bcb93bbf2 - * fall back to HAVE_LINUX_DMA_FENCE_H check directly - * as it's hard to detect the implementation in kernel - */ -#if !defined(HAVE_LINUX_DMA_FENCE_H) -static inline bool dma_fence_is_later(struct dma_fence *f1, struct dma_fence *f2) -{ - if (WARN_ON(f1->context != f2->context)) - return false; - - return (int)(f1->seqno - f2->seqno) > 0; -} -#endif - /* * commit v4.18-rc2-533-g418cc6ca0607 * dma-fence: Allow wait_any_timeout for all fences) diff --git a/include/kcl/kcl_fence_array.h b/include/kcl/kcl_fence_array.h deleted file mode 100644 index 060edd1567fda..0000000000000 --- a/include/kcl/kcl_fence_array.h +++ /dev/null @@ -1,93 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * this file is the copy of include/linux/fence-array.h, don't modify it - * - * fence-array: aggregates fence to be waited together - * - * Copyright (C) 2016 Collabora Ltd - * Copyright (C) 2016 Advanced Micro Devices, Inc. - * Authors: - * Gustavo Padovan - * Christian König - * - * This program is free software; you can redistribute it and/or modify it - * under the terms of the GNU General Public License version 2 as published by - * the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - */ - -#ifndef AMDKCL_FENCE_ARRAY_H -#define AMDKCL_FENCE_ARRAY_H - -#include - -#if !defined(HAVE_LINUX_DMA_FENCE_H) -#if !defined(HAVE_LINUX_FENCE_ARRAY_H) -#include - -/** - * struct fence_array_cb - callback helper for fence array - * @cb: fence callback structure for signaling - * @array: reference to the parent fence array object - */ -struct fence_array_cb { - struct fence_cb cb; - struct fence_array *array; -}; - -/** - * struct fence_array - fence to represent an array of fences - * @base: fence base class - * @lock: spinlock for fence handling - * @num_fences: number of fences in the array - * @num_pending: fences in the array still pending - * @fences: array of the fences - */ -struct fence_array { - struct fence base; - - spinlock_t lock; - unsigned num_fences; - atomic_t num_pending; - struct fence **fences; -}; - -extern const struct fence_ops fence_array_ops; - -/** - * to_fence_array - cast a fence to a fence_array - * @fence: fence to cast to a fence_array - * - * Returns NULL if the fence is not a fence_array, - * or the fence_array otherwise. - */ -static inline struct fence_array *to_fence_array(struct fence *fence) -{ - if (fence->ops != &fence_array_ops) - return NULL; - - return container_of(fence, struct fence_array, base); -} - -struct fence_array *fence_array_create(int num_fences, struct fence **fences, - u64 context, unsigned seqno, - bool signal_on_any); -/** - * dma_fence_is_array - check if a fence is from the array subclass - * @fence: the fence to test - * - * Return true if it is a dma_fence_array and false otherwise. - */ -static inline bool dma_fence_is_array(struct dma_fence *fence) -{ - return false; -} - -#endif -#endif - -#endif /* __LINUX_FENCE_ARRAY_H */ From 818257824eaf3e7f8c64bee14a1066ec8f68450f Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Tue, 7 Feb 2023 11:14:50 +0800 Subject: [PATCH 0892/1868] drm/amdkcl: kcl-cleanup HAVE_STRUCT_DRM_CRTC_DEBUGFS_ENTRY Revert "drm/amdkcl: Check if drm_crtc->debugfs_entry is defined" This reverts commit 015821cc652732fc336dc752dbd2ea6f6acc3ac1. Change-Id: I18b1d0387b2448f3267c105ed87163314ae25568 Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 2 -- drivers/gpu/drm/amd/dkms/config/config.h | 3 --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - .../gpu/drm/amd/dkms/m4/struct_drm_crtc.m4 | 21 ------------------- 4 files changed, 27 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index 1eb31b59e7a8a..dddacb5555a5c 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -3715,12 +3715,10 @@ void crtc_debugfs_init(struct drm_crtc *crtc) &crc_win_update_fops); dput(dir); #endif -#ifdef HAVE_STRUCT_DRM_CRTC_DEBUGFS_ENTRY debugfs_create_file("amdgpu_current_bpc", 0644, crtc->debugfs_entry, crtc, &amdgpu_current_bpc_fops); debugfs_create_file("amdgpu_current_colorspace", 0644, crtc->debugfs_entry, crtc, &amdgpu_current_colorspace_fops); -#endif } /* diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 77b05f13f101a..a3478a34d9288 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1213,9 +1213,6 @@ /* struct drm_crtc_state has flag for flip */ #define HAVE_STRUCT_DRM_CRTC_STATE_FLIP_FLAG 1 -/* drm_crtc->debugfs_entry is available */ -#define HAVE_STRUCT_DRM_CRTC_DEBUGFS_ENTRY 1 - /* struct drm_crtc_state->pageflip_flags is available */ /* #undef HAVE_STRUCT_DRM_CRTC_STATE_PAGEFLIP_FLAGS */ diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index e9e3686bf8c51..d6385c2476953 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -213,7 +213,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DSC_COMPUTE_RC_PARAMETERS AC_AMDGPU_DRM_GEM_PLANE_HELPER_PREPARE_FB AC_AMDGPU_BITMAP_TO_ARR32 - AC_AMDGPU_STRUCT_DRM_CRTC AC_AMDGPU_REGISTER_SHRINKER AC_AMDGPU_DRM_DP_MST_POST_PASSTHROUGH_AUX AC_AMDGPU_DRM_DP_MST_PORT_FULL_PBN diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc.m4 deleted file mode 100644 index 5c02ff4595856..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc.m4 +++ /dev/null @@ -1,21 +0,0 @@ -dnl # -dnl # commit v4.10-rc1~154-9edbf1fa6 -dnl # drm: Add API for capturing frame CRCs -dnl # -AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_DEBUGFS_ENTRY], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - struct drm_crtc *test = NULL; - test->debugfs_entry = NULL; - ], [ - AC_DEFINE(HAVE_STRUCT_DRM_CRTC_DEBUGFS_ENTRY, 1, [ - drm_crtc->debugfs_entry is available]) - ]) - ]) -]) - -AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC], [ - AC_AMDGPU_STRUCT_DRM_CRTC_DEBUGFS_ENTRY -]) From 343de45cfdbaf9519fd3c84e10c6e390bdb67b7b Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 8 Feb 2023 14:43:23 +0800 Subject: [PATCH 0893/1868] drm/amdkcl: kcl-cleanup HAVE_KTIME_GET_MONO_FAST_NS Revert "drm/amdkcl: add kcl for ktime_get_mono_fast_ns" This reverts commit c92bddf26415a7f42e5d9187cdda3ee0be490317. Change-Id: Ib3634b509369d67268f99057a335cbe9a92d0c76 Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 3 --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - drivers/gpu/drm/amd/dkms/m4/ktime-get-fast-ns.m4 | 16 ---------------- include/kcl/kcl_timekeeping.h | 7 ------- 4 files changed, 27 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/ktime-get-fast-ns.m4 diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index a3478a34d9288..4fa2881b001b1 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -913,9 +913,6 @@ /* ktime_get_boottime_ns() is available */ #define HAVE_KTIME_GET_BOOTTIME_NS 1 -/* ktime_get_mono_fast_ns is available */ -#define HAVE_KTIME_GET_MONO_FAST_NS 1 - /* ktime_get_ns is available */ #define HAVE_KTIME_GET_NS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index d6385c2476953..a06ec1711880b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -38,7 +38,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_KTIME_GET_BOOTTIME_NS AC_AMDGPU_KTIME_GET_RAW_NS AC_AMDGPU_KTIME_GET_REAL_SECONDS - AC_AMDGPU_KTIME_GET_FAST_NS AC_AMDGPU_MEMALLOC_NOFS_SAVE AC_AMDGPU_ZONE_MANAGED_PAGES AC_AMDGPU_FAULT_FLAG_ALLOW_RETRY_FIRST diff --git a/drivers/gpu/drm/amd/dkms/m4/ktime-get-fast-ns.m4 b/drivers/gpu/drm/amd/dkms/m4/ktime-get-fast-ns.m4 deleted file mode 100644 index 9e7158950fcbb..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/ktime-get-fast-ns.m4 +++ /dev/null @@ -1,16 +0,0 @@ -dnl # -dnl # commit v3.16-rc5-111-g4396e058c52e -dnl # timekeeping: Provide fast and NMI safe access to CLOCK_MONOTONIC -dnl # -AC_DEFUN([AC_AMDGPU_KTIME_GET_FAST_NS], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - ktime_get_mono_fast_ns(); - ], [ - AC_DEFINE(HAVE_KTIME_GET_MONO_FAST_NS, 1, - [ktime_get_mono_fast_ns is available]) - ]) - ]) -]) diff --git a/include/kcl/kcl_timekeeping.h b/include/kcl/kcl_timekeeping.h index 60b8c7fec82e5..90e1b1c045a75 100644 --- a/include/kcl/kcl_timekeeping.h +++ b/include/kcl/kcl_timekeeping.h @@ -47,13 +47,6 @@ static inline time64_t ktime_get_real_seconds(void) } #endif -#if !defined(HAVE_KTIME_GET_MONO_FAST_NS) -static inline u64 ktime_get_mono_fast_ns(void) -{ - return ktime_to_ns(ktime_get()); -} -#endif - #ifndef HAVE_JIFFIES64_TO_MSECS extern u64 jiffies64_to_msecs(u64 j); #endif From 0a7b8e287c3a869be9b20f9c9a345ac62681aa54 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 8 Feb 2023 14:52:17 +0800 Subject: [PATCH 0894/1868] drm/amdkcl: kcl-cleanup HAVE_KTHREAD_PARK_XX Change-Id: I040d5a11471e6e0d915cbf51f9a0d2eb693f4aa8 Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/kcl_kthread.c | 50 ------------------- drivers/gpu/drm/amd/amdkcl/main.c | 2 - drivers/gpu/drm/amd/dkms/config/config.h | 3 -- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - .../gpu/drm/amd/dkms/m4/kthread-park-xx.m4 | 14 ------ include/kcl/backport/kcl_kthread_backport.h | 6 --- include/kcl/kcl_kthread.h | 7 --- 7 files changed, 83 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/kthread-park-xx.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_kthread.c b/drivers/gpu/drm/amd/amdkcl/kcl_kthread.c index bfc57cb644dc9..df0b9d1c52b25 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_kthread.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_kthread.c @@ -23,53 +23,3 @@ bool __kcl_kthread_should_park(struct task_struct *k) } EXPORT_SYMBOL(__kcl_kthread_should_park); #endif - -#if !defined(HAVE_KTHREAD_PARK_XX) -bool (*_kcl_kthread_should_park)(void); -EXPORT_SYMBOL(_kcl_kthread_should_park); - -void (*_kcl_kthread_parkme)(void); -EXPORT_SYMBOL(_kcl_kthread_parkme); - -void (*_kcl_kthread_unpark)(struct task_struct *k); -EXPORT_SYMBOL(_kcl_kthread_unpark); - -int (*_kcl_kthread_park)(struct task_struct *k); -EXPORT_SYMBOL(_kcl_kthread_park); - -static bool _kcl_kthread_should_park_stub(void) -{ - pr_warn_once("This kernel version not support API: kthread_should_park!\n"); - return false; -} - -static void _kcl_kthread_parkme_stub(void) -{ - pr_warn_once("This kernel version not support API: kthread_parkme!\n"); -} - -static void _kcl_kthread_unpark_stub(struct task_struct *k) -{ - pr_warn_once("This kernel version not support API: kthread_unpark!\n"); -} - -static int _kcl_kthread_park_stub(struct task_struct *k) -{ - pr_warn_once("This kernel version not support API: kthread_park!\n"); - return 0; -} -#endif - -void amdkcl_kthread_init(void) -{ -#if !defined(HAVE_KTHREAD_PARK_XX) - _kcl_kthread_should_park = amdkcl_fp_setup("kthread_should_park", - _kcl_kthread_should_park_stub); - _kcl_kthread_parkme = amdkcl_fp_setup("kthread_parkme", - _kcl_kthread_parkme_stub); - _kcl_kthread_unpark = amdkcl_fp_setup("kthread_unpark", - _kcl_kthread_unpark_stub); - _kcl_kthread_park = amdkcl_fp_setup("kthread_park", - _kcl_kthread_park_stub); -#endif -} diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c index 3e01ddf3f82a6..58c46b4f04ae5 100644 --- a/drivers/gpu/drm/amd/amdkcl/main.c +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -7,7 +7,6 @@ extern void amdkcl_dev_cgroup_init(void); extern void amdkcl_fence_init(void); extern void amdkcl_reservation_init(void); extern void amdkcl_io_init(void); -extern void amdkcl_kthread_init(void); extern void amdkcl_mm_init(void); extern void amdkcl_perf_event_init(void); extern void amdkcl_pci_init(void); @@ -23,7 +22,6 @@ int __init amdkcl_init(void) amdkcl_fence_init(); amdkcl_reservation_init(); amdkcl_io_init(); - amdkcl_kthread_init(); amdkcl_mm_init(); amdkcl_perf_event_init(); amdkcl_pci_init(); diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 4fa2881b001b1..44575442400d2 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -904,9 +904,6 @@ /* ksys_sync_helper() is available */ #define HAVE_KSYS_SYNC_HELPER 1 -/* kthread_{park/unpark/parkme/should_park}() is available */ -#define HAVE_KTHREAD_PARK_XX 1 - /* kthread_{use,unuse}_mm() is available */ #define HAVE_KTHREAD_USE_MM 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index a06ec1711880b..26c4ceb6c956b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -18,7 +18,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_BACKLIGHT_DEVICE_SET_BRIGHTNESS AC_AMDGPU_DEV_PM_SET_DRIVER_FLAGS AC_AMDGPU_COMPAT_PTR_IOCTL - AC_AMDGPU_KTHREAD_PARK_XX AC_AMDGPU___KTHREAD_SHOULD_PARK AC_AMDGPU_LIST_ROTATE_TO_FRONT AC_AMDGPU_LIST_IS_FIRST diff --git a/drivers/gpu/drm/amd/dkms/m4/kthread-park-xx.m4 b/drivers/gpu/drm/amd/dkms/m4/kthread-park-xx.m4 deleted file mode 100644 index 06a8af53dcfe9..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/kthread-park-xx.m4 +++ /dev/null @@ -1,14 +0,0 @@ -dnl # -dnl # introduced commit 2a1d446019f9a5983ec5a335b95e8593fdb6fa2e -dnl # kthread: Implement park/unpark facility -dnl # exported commit 18896451eaeee497ef5c397d76902c6376a8787d -dnl # kthread: export kthread functions -dnl # -AC_DEFUN([AC_AMDGPU_KTHREAD_PARK_XX], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([kthread_parkme kthread_park kthread_unpark kthread_should_park],[kernel/kthread.c],[ - AC_DEFINE(HAVE_KTHREAD_PARK_XX, 1, - [kthread_{park/unpark/parkme/should_park}() is available]) - ]) - ]) -]) diff --git a/include/kcl/backport/kcl_kthread_backport.h b/include/kcl/backport/kcl_kthread_backport.h index 898766aa6e427..60732dc17f10e 100644 --- a/include/kcl/backport/kcl_kthread_backport.h +++ b/include/kcl/backport/kcl_kthread_backport.h @@ -9,10 +9,4 @@ #define __kthread_should_park __kcl_kthread_should_park #endif -#if !defined(HAVE_KTHREAD_PARK_XX) -#define kthread_parkme _kcl_kthread_parkme -#define kthread_unpark _kcl_kthread_unpark -#define kthread_park _kcl_kthread_park -#define kthread_should_park _kcl_kthread_should_park -#endif #endif diff --git a/include/kcl/kcl_kthread.h b/include/kcl/kcl_kthread.h index f9cca65e1ea6c..a4e7fdf6bb12f 100644 --- a/include/kcl/kcl_kthread.h +++ b/include/kcl/kcl_kthread.h @@ -10,13 +10,6 @@ extern bool __kcl_kthread_should_park(struct task_struct *k); #endif -#if !defined(HAVE_KTHREAD_PARK_XX) -extern void (*_kcl_kthread_parkme)(void); -extern void (*_kcl_kthread_unpark)(struct task_struct *k); -extern int (*_kcl_kthread_park)(struct task_struct *k); -extern bool (*_kcl_kthread_should_park)(void); -#endif - /* Copied from v5.7-13665-g9bf5b9eb232b kernel/kthread.c */ #ifndef HAVE_KTHREAD_USE_MM static inline From a70db57d7eec0f743b953920c2473951ed7f178f Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 8 Feb 2023 15:55:49 +0800 Subject: [PATCH 0895/1868] drm/amdkcl: kcl-cleanup HAVE_DRM_MODE_CONFIG_HELPER_PRIVATE Change-Id: Id5feee587dc3623b9c9e800b34885fa2979cf857 Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ---- drivers/gpu/drm/amd/dkms/config/config.h | 3 --- 2 files changed, 7 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 58f08965f04a7..1b9ee02760760 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3444,14 +3444,12 @@ static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = { #endif }; -#ifdef HAVE_DRM_MODE_CONFIG_HELPER_PRIVATE static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = { .atomic_commit_tail = amdgpu_dm_atomic_commit_tail, #ifdef HAVE_DRM_DP_ATOMIC_SETUP_COMMIT .atomic_commit_setup = drm_dp_mst_atomic_setup_commit, #endif }; -#endif #ifdef HAVE_HDR_SINK_METADATA static void update_connector_ext_caps(struct amdgpu_dm_connector *aconnector) @@ -4484,9 +4482,7 @@ static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) adev->mode_info.mode_config_initialized = true; adev_to_drm(adev)->mode_config.funcs = (void *)&amdgpu_dm_mode_funcs; -#ifdef HAVE_DRM_MODE_CONFIG_HELPER_PRIVATE adev_to_drm(adev)->mode_config.helper_private = &amdgpu_dm_mode_config_helperfuncs; -#endif adev_to_drm(adev)->mode_config.max_width = 16384; adev_to_drm(adev)->mode_config.max_height = 16384; diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 44575442400d2..e901d41c41c83 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -720,9 +720,6 @@ /* drm_mode_config_funcs->atomic_state_alloc() is available */ #define HAVE_DRM_MODE_CONFIG_FUNCS_ATOMIC_STATE_ALLOC 1 -/* drm_mode_config->helper_private is available */ -#define HAVE_DRM_MODE_CONFIG_HELPER_PRIVATE 1 - /* drm_mode_config_helper_{suspend/resume}() is available */ #define HAVE_DRM_MODE_CONFIG_HELPER_SUSPEND 1 From 584015e7ee6ab098460f4f337245b85e2e816ef9 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 9 Feb 2023 17:19:30 +0800 Subject: [PATCH 0896/1868] drm/amdkcl: Fix the dma_resv.seq checking bug Fix the dma_resv->seq checking bug Change-Id: I0ea3efe3d36d1e3996623f5f7fc5de16702516c9 Signed-off-by: Ma Jun Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 | 98 ++++++++++--------------- 1 file changed, 38 insertions(+), 60 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 index 8cf888eb3a6b4..f65379d76636f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 @@ -1,78 +1,57 @@ dnl # -dnl # v5.8-rc6-36-gcd29f22019ec dma-buf: Use sequence counter with associated wound/wait mutex -dnl # v5.8-rc6-35-g318ce71f3e3a dma-buf: Remove custom seqcount lockdep class key +dnl # v5.18-rc1-237-g047a1b877ed4 +dnl # dma-buf & drm/amdgpu: remove dma_resv workaround dnl # -AC_DEFUN([AC_AMDGPU_DMA_RESV_SEQ], [ +AC_DEFUN([AC_AMDGPU_DMA_RESV_FENCES], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ #include ], [ - struct dma_resv *obj = NULL; - seqcount_ww_mutex_init(&obj->seq, &obj->lock); + struct dma_resv *resv = NULL; + resv->fences = NULL; ], [ - AC_DEFINE(HAVE_DMA_RESV_SEQCOUNT_WW_MUTEX_T, 1, - [dma_resv->seq is seqcount_ww_mutex_t]) - AC_DEFINE(HAVE_DMA_RESV_SEQ, 1, - [dma_resv->seq is available]) + dnl # this is the latest kernel + AC_DEFINE(HAVE_DMA_RESV_FENCES, 1,[dma_resv->fences is available]) ], [ dnl # - dnl # v5.3-rc1-476-gb016cd6ed4b7 dma-buf: Restore seqlock around dma_resv updates - dnl # v5.3-rc1-449-g52791eeec1d9 dma-buf: rename reservation_object to dma_resv - dnl # v5.3-rc1-448-g5d344f58da76 dma-buf: nuke reservation_object seq number + dnl # v5.8-rc6-36-gcd29f22019ec dma-buf: Use sequence counter with associated wound/wait mutex + dnl # v5.8-rc6-35-g318ce71f3e3a dma-buf: Remove custom seqcount lockdep class key dnl # AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_LINUX_DMA_RESV_H #include - #else - #include - #endif ], [ - #ifdef HAVE_LINUX_DMA_RESV_H - struct dma_resv *resv = NULL; - #else - struct reservation_object *resv = NULL; - #endif - write_seqcount_begin(&resv->seq); + struct dma_resv *obj = NULL; + seqcount_ww_mutex_init(&obj->seq, &obj->lock); + ], [ + AC_DEFINE(HAVE_DMA_RESV_SEQCOUNT_WW_MUTEX_T, 1, [dma_resv->seq is seqcount_ww_mutex_t]) ], [ - AC_DEFINE(HAVE_DMA_RESV_SEQ, 1, - [dma_resv->seq is available]) - ],[ - dnl # - dnl # dma_resv->seq is dropped since kernle 5.18.0 - dnl # So trigger the bug only for the kernel_version < 5.18.0 - dnl # - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - #if LINUX_VERSION_CODE < KERNEL_VERSION(5, 18, 0) - int this_is_bug; - this_is_bug = 0; - #else - this_is_not_bug(); - #endif - ], [ - AC_DEFINE(HAVE_DMA_RESV_SEQ_BUG, 1, - [bug for missing dma_resv->seq]) - ]) + dnl # + dnl # v5.3-rc1-476-gb016cd6ed4b7 dma-buf: Restore seqlock around dma_resv updates + dnl # v5.3-rc1-449-g52791eeec1d9 dma-buf: rename reservation_object to dma_resv + dnl # v5.3-rc1-448-g5d344f58da76 dma-buf: nuke reservation_object seq number + dnl # + AC_KERNEL_TRY_COMPILE([ + #ifdef HAVE_LINUX_DMA_RESV_H + #include + #else + #include + #endif + ], [ + #ifdef HAVE_LINUX_DMA_RESV_H + struct dma_resv *resv = NULL; + #else + struct reservation_object *resv = NULL; + #endif + write_seqcount_begin(&resv->seq); + ], [ + AC_DEFINE(HAVE_DMA_RESV_SEQ, 1,[dma_resv->seq is available]) + ],[ + dnl # + dnl # Trigger the bug for dma_resv->seq definition + dnl # + AC_DEFINE(HAVE_DMA_RESV_SEQ_BUG, 1, [Reporting dma_resv->seq bug]) ]) ]) - ]) -]) - -dnl # -dnl # v5.18-rc1-237-g047a1b877ed4 -dnl # dma-buf & drm/amdgpu: remove dma_resv workaround -dnl # -AC_DEFUN([AC_AMDGPU_DMA_RESV_FENCES], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - struct dma_resv *resv = NULL; - resv->fences = NULL; - ], [ - AC_DEFINE(HAVE_DMA_RESV_FENCES, 1, - [dma_resv->fences is available]) ]) ]) ]) @@ -99,7 +78,6 @@ AC_DEFUN([AC_AMDGPU_RESERVATION_OBJECT_STAGED], [ ]) AC_DEFUN([AC_AMDGPU_DMA_RESV], [ - AC_AMDGPU_DMA_RESV_SEQ AC_AMDGPU_DMA_RESV_FENCES AC_AMDGPU_RESERVATION_OBJECT_STAGED ]) From 353826258997bbadebea57f6a26829f2b8fc65b2 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 7 Feb 2023 13:06:17 +0800 Subject: [PATCH 0897/1868] drm/amdkcl: kcl-cleanup HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT 1. remove HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT 2. rename HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT_P_P_P_P to HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT_4ARGS 3. remove HAVE_DRM_MODE_CONFIG_FUNCS_ATOMIC_STATE_ALLOC Signed-off-by: Leslie Shi Reviewed-by: Ma Jun --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 107 ++---------------- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 7 -- drivers/gpu/drm/amd/dkms/config/config.h | 4 +- .../dkms/m4/drm_atomic_private_obj_init.m4 | 19 +--- .../drm/amd/dkms/m4/drm_mode_config_funcs.m4 | 18 --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - 6 files changed, 14 insertions(+), 142 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_mode_config_funcs.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 1b9ee02760760..c78a8139cd5fc 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3118,9 +3118,7 @@ static int dm_resume(void *handle) struct drm_plane *plane; struct drm_plane_state *new_plane_state; struct dm_plane_state *dm_new_plane_state; -#ifdef HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT struct dm_atomic_state *dm_state = to_dm_atomic_state(dm->atomic_obj.state); -#endif enum dc_connection_type new_connection_type = dc_connection_none; struct dc_state *dc_state; int i, r, j, ret; @@ -3193,12 +3191,10 @@ static int dm_resume(void *handle) return 0; } -#ifdef HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT /* Recreate dc_state - DC invalidates it when setting power state to S3. */ dc_state_release(dm_state->context); dm_state->context = dc_state_create(dm->dc, NULL); /* TODO: Remove dc_state->dccg, use dc->dccg directly. */ -#endif /* Before powering on DC we need to re-initialize DMUB. */ dm_dmub_hw_resume(adev); @@ -3379,49 +3375,6 @@ const struct amdgpu_ip_block_version dm_ip_block = { .funcs = &amdgpu_dm_funcs, }; -#ifndef HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT -#ifdef HAVE_DRM_MODE_CONFIG_FUNCS_ATOMIC_STATE_ALLOC -static struct drm_atomic_state * -dm_atomic_state_alloc(struct drm_device *dev) -{ - struct dm_atomic_state *state = kzalloc(sizeof(*state), GFP_KERNEL); - - if (!state) - return NULL; - - if (drm_atomic_state_init(dev, &state->base) < 0) - goto fail; - - return &state->base; -fail: - kfree(state); - return NULL; -} - -static void -dm_atomic_state_clear(struct drm_atomic_state *state) -{ - struct dm_atomic_state *dm_state = to_dm_atomic_state(state); - - if (dm_state->context) { - dc_release_state(dm_state->context); - dm_state->context = NULL; - } - - drm_atomic_state_default_clear(state); -} - -static void -dm_atomic_state_alloc_free(struct drm_atomic_state *state) -{ - struct dm_atomic_state *dm_state = to_dm_atomic_state(state); - - drm_atomic_state_default_release(state); - kfree(dm_state); -} -#endif -#endif - /** * DOC: atomic * @@ -3435,13 +3388,6 @@ static const struct drm_mode_config_funcs amdgpu_dm_mode_funcs = { #endif .atomic_check = amdgpu_dm_atomic_check, .atomic_commit = drm_atomic_helper_commit, -#ifndef HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT -#ifdef HAVE_DRM_MODE_CONFIG_FUNCS_ATOMIC_STATE_ALLOC - .atomic_state_alloc = dm_atomic_state_alloc, - .atomic_state_clear = dm_atomic_state_clear, - .atomic_state_free = dm_atomic_state_alloc_free -#endif -#endif }; static struct drm_mode_config_helper_funcs amdgpu_dm_mode_config_helperfuncs = { @@ -4388,7 +4334,6 @@ static int register_outbox_irq_handlers(struct amdgpu_device *adev) return 0; } -#ifdef HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT /* * Acquires the lock for the atomic state object and returns * the new atomic state. @@ -4472,7 +4417,6 @@ static struct drm_private_state_funcs dm_atomic_state_funcs = { .atomic_duplicate_state = dm_atomic_duplicate_state, .atomic_destroy_state = dm_atomic_destroy_state, }; -#endif static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) { @@ -4500,24 +4444,19 @@ static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) if (!state) return -ENOMEM; -#ifdef HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT state->context = dc_state_create_current_copy(adev->dm.dc); if (!state->context) { kfree(state); return -ENOMEM; } -#ifdef HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT_P_P_P_P - drm_atomic_private_obj_init(adev_to_drm(adev), + drm_atomic_private_obj_init( +#ifdef HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT_4ARGS + adev_to_drm(adev), +#endif &adev->dm.atomic_obj, &state->base, &dm_atomic_state_funcs); -#else - drm_atomic_private_obj_init(&adev->dm.atomic_obj, - &state->base, - &dm_atomic_state_funcs); -#endif -#endif r = amdgpu_display_modeset_create_props(adev); if (r) { @@ -5214,9 +5153,7 @@ static void amdgpu_dm_destroy_drm_device(struct amdgpu_display_manager *dm) drm_mode_config_cleanup(dm->ddev); #endif -#ifdef HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT drm_atomic_private_obj_fini(&dm->atomic_obj); -#endif } /****************************************************************************** @@ -10525,11 +10462,7 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm, bool enable, bool *lock_and_validation_needed) { -#ifdef HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT struct dm_atomic_state *dm_state = NULL; -#else - struct dm_atomic_state *dm_state = to_dm_atomic_state(state); -#endif struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; struct dc_stream_state *new_stream; int ret = 0; @@ -10679,11 +10612,11 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm, if (!drm_mode_equal(&new_crtc_state->mode, high_mode)) set_freesync_fixed_config(dm_new_crtc_state); } -#ifdef HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT + ret = dm_atomic_get_state(state, &dm_state); if (ret) goto fail; -#endif + DRM_DEBUG_DRIVER("Disabling DRM crtc: %d\n", crtc->base.id); @@ -10719,11 +10652,11 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm, dm_old_crtc_state->stream)) { WARN_ON(dm_new_crtc_state->stream); -#ifdef HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT + ret = dm_atomic_get_state(state, &dm_state); if (ret) goto fail; -#endif + dm_new_crtc_state->stream = new_stream; dc_stream_retain(new_stream); @@ -11021,7 +10954,6 @@ static int dm_check_native_cursor_state(struct drm_crtc *new_plane_crtc, struct drm_plane_state *new_plane_state, bool enable) { - struct amdgpu_crtc *new_acrtc; int ret; @@ -11084,11 +11016,7 @@ static int dm_update_plane_state(struct dc *dc, bool *lock_and_validation_needed, bool *is_top_most_overlay) { -#ifdef HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT struct dm_atomic_state *dm_state = NULL; -#else - struct dm_atomic_state *dm_state = to_dm_atomic_state(state); -#endif struct drm_crtc *new_plane_crtc, *old_plane_crtc; struct drm_crtc_state *old_crtc_state, *new_crtc_state; struct dm_crtc_state *dm_new_crtc_state, *dm_old_crtc_state; @@ -11136,13 +11064,12 @@ static int dm_update_plane_state(struct dc *dc, DRM_DEBUG_ATOMIC("Disabling DRM plane: %d on DRM crtc %d\n", plane->base.id, old_plane_crtc->base.id); -#ifdef HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT + ret = dm_atomic_get_state(state, &dm_state); if (ret) return ret; if (!dc_state_remove_plane( -#endif dc, dm_old_crtc_state->stream, dm_old_plane_state->dc_state, @@ -11201,13 +11128,12 @@ static int dm_update_plane_state(struct dc *dc, goto out; } -#ifdef HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT ret = dm_atomic_get_state(state, &dm_state); if (ret) { dc_plane_state_release(dc_new_plane_state); goto out; } -#endif + /* * Any atomic check errors that occur after this will * not need a release. The plane state will be attached @@ -11563,11 +11489,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, struct drm_atomic_state *state) { struct amdgpu_device *adev = drm_to_adev(dev); -#ifdef HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT struct dm_atomic_state *dm_state = NULL; -#else - struct dm_atomic_state *dm_state = to_dm_atomic_state(state); -#endif struct dc *dc = adev->dm.dc; struct drm_connector *connector; struct drm_connector_state *old_con_state, *new_con_state; @@ -11698,11 +11620,6 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, } } -#ifndef HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT - dm_state->context = dc_create_state(dc); - ASSERT(dm_state->context); - dc_resource_state_copy_construct_current(dc, dm_state->context); -#endif /* * DC consults the zpos (layer_index in DC terminology) to determine the * hw plane on which to enable the hw cursor (see @@ -11954,13 +11871,11 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, * TODO: Remove this stall and drop DM state private objects. */ if (lock_and_validation_needed) { -#ifdef HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT ret = dm_atomic_get_state(state, &dm_state); if (ret) { drm_dbg_atomic(dev, "dm_atomic_get_state() failed\n"); goto fail; } -#endif ret = do_aquire_global_lock(dev, state); if (ret) { @@ -12012,7 +11927,6 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, goto fail; } } else { -#ifdef HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT /* * The commit is a fast update. Fast updates shouldn't change * the DC context, affect global validation, and can have their @@ -12053,7 +11967,6 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, break; } } -#endif } /* Store the overall update type for use later in atomic check. */ diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index 96240ddf02fea..b3d6443b8cd59 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -409,7 +409,6 @@ struct amdgpu_display_manager { struct drm_device *ddev; u16 display_indexes_num; -#ifdef HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT /** * @atomic_obj: * @@ -419,8 +418,6 @@ struct amdgpu_display_manager { */ struct drm_private_obj atomic_obj; -#endif - /** * @dc_lock: * @@ -939,11 +936,7 @@ struct dm_crtc_state { #define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base) struct dm_atomic_state { -#ifdef HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT struct drm_private_state base; -#else - struct drm_atomic_state base; -#endif struct dc_state *context; }; diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index e901d41c41c83..bb73d1ac8205f 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -207,8 +207,8 @@ /* drm_atomic_private_obj_init() is available */ #define HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT 1 -/* drm_atomic_private_obj_init() has p,p,p,p interface */ -#define HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT_P_P_P_P 1 +/* drm_atomic_private_obj_init() wants 4 args */ +#define HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT_4ARGS 1 /* whether struct drm_atomic_state have async_update */ #define HAVE_DRM_ATOMIC_STATE_ASYNC_UPDATE 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_atomic_private_obj_init.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_atomic_private_obj_init.m4 index 10d794c4ace79..12b80d67386a9 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_atomic_private_obj_init.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_atomic_private_obj_init.m4 @@ -9,23 +9,8 @@ AC_DEFUN([AC_AMDGPU_DRM_ATOMIC_PRIVATE_OBJ_INIT], [ ], [ drm_atomic_private_obj_init(NULL, NULL, NULL, NULL); ], [ - AC_DEFINE(HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT_P_P_P_P, 1, - [drm_atomic_private_obj_init() has p,p,p,p interface]) - AC_DEFINE(HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT, 1, - [drm_atomic_private_obj_init() is available]) - ], [ - dnl # - dnl # commit v4.12-rc7-1381-ga4370c777406 - dnl # drm/atomic: Make private objs proper objects - dnl # - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - drm_atomic_private_obj_init(NULL, NULL, NULL); - ], [ - AC_DEFINE(HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT, 1, - [drm_atomic_private_obj_init() is available]) - ]) + AC_DEFINE(HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT_4ARGS, 1, + [drm_atomic_private_obj_init() wants 4 args]) ]) ]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_mode_config_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_mode_config_funcs.m4 deleted file mode 100644 index fad6cdc4bd81d..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm_mode_config_funcs.m4 +++ /dev/null @@ -1,18 +0,0 @@ -dnl # -dnl # v4.1-rc2-37-g036ef5733ba4 -dnl # drm/atomic: Allow drivers to subclass drm_atomic_state, v3 -dnl # -AC_DEFUN([AC_AMDGPU_DRM_MODE_CONFIG_FUNCS], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - #include - ], [ - struct drm_mode_config_funcs *funcs = NULL; - funcs->atomic_state_alloc(NULL); - ], [ - AC_DEFINE(HAVE_DRM_MODE_CONFIG_FUNCS_ATOMIC_STATE_ALLOC, 1, - [drm_mode_config_funcs->atomic_state_alloc() is available]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 26c4ceb6c956b..224dfd529b06d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -109,7 +109,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_HDMI_VENDOR_INFOFRAME_FROM_DISPLAY_MODE AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS AC_AMDGPU_DRM_ATOMIC_PRIVATE_OBJ_INIT - AC_AMDGPU_DRM_MODE_CONFIG_FUNCS AC_AMDGPU_DRM_CONNECTOR_LIST_ITER_BEGIN AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS AC_AMDGPU_DRM_DP_MST_ATOMIC_CHECK From e92a4c42699ec234119226fdfd7ef1563b97dd10 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 8 Feb 2023 10:49:20 +0800 Subject: [PATCH 0898/1868] drm/amdkcl: kcl-cleanup HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- .../gpu/drm/amd/amdgpu/amdgpu_connectors.c | 10 ---- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 32 ------------- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 14 ------ drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c | 30 ------------ drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 40 ---------------- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 40 ---------------- drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 48 ------------------- drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 40 ---------------- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 40 ---------------- .../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c | 8 ---- .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 8 ---- .../drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c | 16 ------- .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 8 ---- drivers/gpu/drm/amd/dkms/config/config.h | 3 -- .../dkms/m4/drm-connector-list-iter-begin.m4 | 16 ------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - 16 files changed, 354 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-connector-list-iter-begin.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c index 86058682b0d55..f5745929571f6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c @@ -1658,9 +1658,7 @@ amdgpu_connector_add(struct amdgpu_device *adev, { struct drm_device *dev = adev_to_drm(adev); struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif struct amdgpu_connector *amdgpu_connector; struct amdgpu_connector_atom_dig *amdgpu_dig_connector; struct drm_encoder *encoder; @@ -1675,18 +1673,12 @@ amdgpu_connector_add(struct amdgpu_device *adev, return; /* see if we already added it */ -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { -#endif amdgpu_connector = to_amdgpu_connector(connector); if (amdgpu_connector->connector_id == connector_id) { amdgpu_connector->devices |= supported_device; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif return; } if (amdgpu_connector->ddc_bus && i2c_bus->valid) { @@ -1701,9 +1693,7 @@ amdgpu_connector_add(struct amdgpu_device *adev, } } } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif /* check if it's a dp bridge */ list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 22c0db8d9d2a3..3de34c93d539f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -70,22 +70,14 @@ void amdgpu_display_hotplug_work_func(struct work_struct *work) struct drm_device *dev = adev_to_drm(adev); struct drm_mode_config *mode_config = &dev->mode_config; struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif mutex_lock(&mode_config->mutex); -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) -#endif amdgpu_connector_hotplug(connector); -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif mutex_unlock(&mode_config->mutex); /* Just fire off a uevent and let userspace tell us what to do */ drm_helper_hpd_irq_event(dev); @@ -428,19 +420,13 @@ void amdgpu_display_print_display_setup(struct drm_device *dev) struct amdgpu_connector *amdgpu_connector; struct drm_encoder *encoder; struct amdgpu_encoder *amdgpu_encoder; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif uint32_t devices; int i = 0; DRM_INFO("AMDGPU Display Connectors\n"); -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { -#endif amdgpu_connector = to_amdgpu_connector(connector); DRM_INFO("Connector %d:\n", i); DRM_INFO(" %s\n", connector->name); @@ -504,9 +490,7 @@ void amdgpu_display_print_display_setup(struct drm_device *dev) } i++; } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif } bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector, @@ -1787,27 +1771,19 @@ int amdgpu_display_suspend_helper(struct amdgpu_device *adev) struct drm_crtc *crtc; struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif int r; drm_kms_helper_poll_disable(dev); /* turn off display hw */ drm_modeset_lock_all(dev); -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) -#endif drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif drm_modeset_unlock_all(dev); /* unpin the front buffers and cursors */ list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { @@ -1855,9 +1831,7 @@ int amdgpu_display_resume_helper(struct amdgpu_device *adev) { struct drm_device *dev = adev_to_drm(adev); struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif struct drm_crtc *crtc; int r; @@ -1884,18 +1858,12 @@ int amdgpu_display_resume_helper(struct amdgpu_device *adev) /* turn on display hw */ drm_modeset_lock_all(dev); -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) -#endif drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif drm_modeset_unlock_all(dev); drm_kms_helper_poll_enable(dev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index f6718a3a7ce45..3610612846771 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2711,9 +2711,7 @@ static int amdgpu_runtime_idle_check_display(struct device *dev) if (adev->mode_info.num_crtc) { struct drm_connector *list_connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif int ret = 0; if (amdgpu_runtime_pm != -2) { @@ -2723,20 +2721,14 @@ static int amdgpu_runtime_idle_check_display(struct device *dev) * the GPU was in suspend. Remove this once that is fixed. */ mutex_lock(&drm_dev->mode_config.mutex); -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(drm_dev, &iter); drm_for_each_connector_iter(list_connector, &iter) { -#else - list_for_each_entry(list_connector, &(drm_dev)->mode_config.connector_list, head) { -#endif if (list_connector->status == connector_status_connected) { ret = -EBUSY; break; } } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif mutex_unlock(&drm_dev->mode_config.mutex); if (ret) @@ -2758,21 +2750,15 @@ static int amdgpu_runtime_idle_check_display(struct device *dev) mutex_lock(&drm_dev->mode_config.mutex); drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(drm_dev, &iter); drm_for_each_connector_iter(list_connector, &iter) { -#else - list_for_each_entry(list_connector, &(drm_dev)->mode_config.connector_list, head) { -#endif if (list_connector->dpms == DRM_MODE_DPMS_ON) { ret = -EBUSY; break; } } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); mutex_unlock(&drm_dev->mode_config.mutex); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c index ccd095286b0b0..dbd12456ff5fa 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.c @@ -36,20 +36,14 @@ amdgpu_link_encoder_connector(struct drm_device *dev) { struct amdgpu_device *adev = drm_to_adev(dev); struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif struct amdgpu_connector *amdgpu_connector; struct drm_encoder *encoder; struct amdgpu_encoder *amdgpu_encoder; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); /* walk the list and link encoders to connectors */ drm_for_each_connector_iter(connector, &iter) { -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { -#endif amdgpu_connector = to_amdgpu_connector(connector); list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { amdgpu_encoder = to_amdgpu_encoder(encoder); @@ -62,9 +56,7 @@ amdgpu_link_encoder_connector(struct drm_device *dev) } } } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif } void amdgpu_encoder_set_active_device(struct drm_encoder *encoder) @@ -72,14 +64,10 @@ void amdgpu_encoder_set_active_device(struct drm_encoder *encoder) struct drm_device *dev = encoder->dev; struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { -#endif if (connector->encoder == encoder) { struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); @@ -89,9 +77,7 @@ void amdgpu_encoder_set_active_device(struct drm_encoder *encoder) amdgpu_connector->devices, encoder->encoder_type); } } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif } struct drm_connector * @@ -100,26 +86,18 @@ amdgpu_get_connector_for_encoder(struct drm_encoder *encoder) struct drm_device *dev = encoder->dev; struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct drm_connector *connector, *found = NULL; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif struct amdgpu_connector *amdgpu_connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { -#endif amdgpu_connector = to_amdgpu_connector(connector); if (amdgpu_encoder->active_device & amdgpu_connector->devices) { found = connector; break; } } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif return found; } @@ -129,26 +107,18 @@ amdgpu_get_connector_for_encoder_init(struct drm_encoder *encoder) struct drm_device *dev = encoder->dev; struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct drm_connector *connector, *found = NULL; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif struct amdgpu_connector *amdgpu_connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { -#endif amdgpu_connector = to_amdgpu_connector(connector); if (amdgpu_encoder->devices & amdgpu_connector->devices) { found = connector; break; } } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif return found; } diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index a0c6443568c46..064de11565190 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -334,17 +334,11 @@ static void dce_v10_0_hpd_init(struct amdgpu_device *adev) { struct drm_device *dev = adev_to_drm(adev); struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif u32 tmp; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { -#endif struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) @@ -381,9 +375,7 @@ static void dce_v10_0_hpd_init(struct amdgpu_device *adev) amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif } /** @@ -398,17 +390,11 @@ static void dce_v10_0_hpd_fini(struct amdgpu_device *adev) { struct drm_device *dev = adev_to_drm(adev); struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif u32 tmp; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { -#endif struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) @@ -421,9 +407,7 @@ static void dce_v10_0_hpd_fini(struct amdgpu_device *adev) amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif } static u32 dce_v10_0_hpd_get_gpio_reg(struct amdgpu_device *adev) @@ -1251,9 +1235,7 @@ static void dce_v10_0_audio_write_latency_fields(struct drm_encoder *encoder, struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif struct amdgpu_connector *amdgpu_connector = NULL; u32 tmp; int interlace = 0; @@ -1261,20 +1243,14 @@ static void dce_v10_0_audio_write_latency_fields(struct drm_encoder *encoder, if (!dig || !dig->afmt || !dig->afmt->pin) return; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { -#endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); break; } } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif if (!amdgpu_connector) { DRM_ERROR("Couldn't find encoder's connector\n"); @@ -1305,9 +1281,7 @@ static void dce_v10_0_audio_write_speaker_allocation(struct drm_encoder *encoder struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif struct amdgpu_connector *amdgpu_connector = NULL; u32 tmp; u8 *sadb = NULL; @@ -1316,20 +1290,14 @@ static void dce_v10_0_audio_write_speaker_allocation(struct drm_encoder *encoder if (!dig || !dig->afmt || !dig->afmt->pin) return; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { -#endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); break; } } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif if (!amdgpu_connector) { DRM_ERROR("Couldn't find encoder's connector\n"); @@ -1369,9 +1337,7 @@ static void dce_v10_0_audio_write_sad_regs(struct drm_encoder *encoder) struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif struct amdgpu_connector *amdgpu_connector = NULL; struct cea_sad *sads; int i, sad_count; @@ -1394,20 +1360,14 @@ static void dce_v10_0_audio_write_sad_regs(struct drm_encoder *encoder) if (!dig || !dig->afmt || !dig->afmt->pin) return; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { -#endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); break; } } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif if (!amdgpu_connector) { DRM_ERROR("Couldn't find encoder's connector\n"); diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index c22e723ac9078..5f3afd026394b 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -358,17 +358,11 @@ static void dce_v11_0_hpd_init(struct amdgpu_device *adev) { struct drm_device *dev = adev_to_drm(adev); struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif u32 tmp; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { -#endif struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) @@ -404,9 +398,7 @@ static void dce_v11_0_hpd_init(struct amdgpu_device *adev) dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif } /** @@ -421,17 +413,11 @@ static void dce_v11_0_hpd_fini(struct amdgpu_device *adev) { struct drm_device *dev = adev_to_drm(adev); struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif u32 tmp; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { -#endif struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) @@ -443,9 +429,7 @@ static void dce_v11_0_hpd_fini(struct amdgpu_device *adev) amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif } static u32 dce_v11_0_hpd_get_gpio_reg(struct amdgpu_device *adev) @@ -1283,9 +1267,7 @@ static void dce_v11_0_audio_write_latency_fields(struct drm_encoder *encoder, struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif struct amdgpu_connector *amdgpu_connector = NULL; u32 tmp; int interlace = 0; @@ -1293,20 +1275,14 @@ static void dce_v11_0_audio_write_latency_fields(struct drm_encoder *encoder, if (!dig || !dig->afmt || !dig->afmt->pin) return; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { -#endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); break; } } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif if (!amdgpu_connector) { DRM_ERROR("Couldn't find encoder's connector\n"); @@ -1337,9 +1313,7 @@ static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif struct amdgpu_connector *amdgpu_connector = NULL; u32 tmp; u8 *sadb = NULL; @@ -1348,20 +1322,14 @@ static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder if (!dig || !dig->afmt || !dig->afmt->pin) return; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { -#endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); break; } } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif if (!amdgpu_connector) { DRM_ERROR("Couldn't find encoder's connector\n"); @@ -1401,9 +1369,7 @@ static void dce_v11_0_audio_write_sad_regs(struct drm_encoder *encoder) struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif struct amdgpu_connector *amdgpu_connector = NULL; struct cea_sad *sads; int i, sad_count; @@ -1426,20 +1392,14 @@ static void dce_v11_0_audio_write_sad_regs(struct drm_encoder *encoder) if (!dig || !dig->afmt || !dig->afmt->pin) return; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { -#endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); break; } } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif if (!amdgpu_connector) { DRM_ERROR("Couldn't find encoder's connector\n"); diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c index 94df91bd93558..db87c4ae6c863 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c @@ -305,17 +305,11 @@ static void dce_v6_0_hpd_init(struct amdgpu_device *adev) { struct drm_device *dev = adev_to_drm(adev); struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif u32 tmp; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { -#endif struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) @@ -342,9 +336,7 @@ static void dce_v6_0_hpd_init(struct amdgpu_device *adev) dce_v6_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif } /** @@ -359,17 +351,11 @@ static void dce_v6_0_hpd_fini(struct amdgpu_device *adev) { struct drm_device *dev = adev_to_drm(adev); struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif u32 tmp; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { -#endif struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) @@ -381,9 +367,7 @@ static void dce_v6_0_hpd_fini(struct amdgpu_device *adev) amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif } static u32 dce_v6_0_hpd_get_gpio_reg(struct amdgpu_device *adev) @@ -1174,27 +1158,19 @@ static void dce_v6_0_audio_write_latency_fields(struct drm_encoder *encoder, struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif struct amdgpu_connector *amdgpu_connector = NULL; int interlace = 0; u32 tmp; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { -#endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); break; } } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif if (!amdgpu_connector) { DRM_ERROR("Couldn't find encoder's connector\n"); @@ -1226,28 +1202,20 @@ static void dce_v6_0_audio_write_speaker_allocation(struct drm_encoder *encoder) struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif struct amdgpu_connector *amdgpu_connector = NULL; u8 *sadb = NULL; int sad_count; u32 tmp; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { -#endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); break; } } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif if (!amdgpu_connector) { DRM_ERROR("Couldn't find encoder's connector\n"); @@ -1295,9 +1263,7 @@ static void dce_v6_0_audio_write_sad_regs(struct drm_encoder *encoder) struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif struct amdgpu_connector *amdgpu_connector = NULL; struct cea_sad *sads; int i, sad_count; @@ -1317,20 +1283,14 @@ static void dce_v6_0_audio_write_sad_regs(struct drm_encoder *encoder) { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, }; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { -#endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); break; } } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif if (!amdgpu_connector) { DRM_ERROR("Couldn't find encoder's connector\n"); @@ -1719,9 +1679,7 @@ static void dce_v6_0_afmt_setmode(struct drm_encoder *encoder, struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif struct amdgpu_connector *amdgpu_connector = NULL; int em = amdgpu_atombios_encoder_get_encoder_mode(encoder); int bpc = 8; @@ -1729,20 +1687,14 @@ static void dce_v6_0_afmt_setmode(struct drm_encoder *encoder, if (!dig || !dig->afmt) return; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { -#endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); break; } } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif if (!amdgpu_connector) { DRM_ERROR("Couldn't find encoder's connector\n"); diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index 85cefb518ce2d..eb72dfd75ba03 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -296,17 +296,11 @@ static void dce_v8_0_hpd_init(struct amdgpu_device *adev) { struct drm_device *dev = adev_to_drm(adev); struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif u32 tmp; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { -#endif struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) @@ -333,9 +327,7 @@ static void dce_v8_0_hpd_init(struct amdgpu_device *adev) dce_v8_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd); amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif } /** @@ -350,17 +342,11 @@ static void dce_v8_0_hpd_fini(struct amdgpu_device *adev) { struct drm_device *dev = adev_to_drm(adev); struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif u32 tmp; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { -#endif struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector); if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd) @@ -372,9 +358,7 @@ static void dce_v8_0_hpd_fini(struct amdgpu_device *adev) amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd); } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif } static u32 dce_v8_0_hpd_get_gpio_reg(struct amdgpu_device *adev) @@ -1206,9 +1190,7 @@ static void dce_v8_0_audio_write_latency_fields(struct drm_encoder *encoder, struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif struct amdgpu_connector *amdgpu_connector = NULL; u32 tmp = 0, offset; @@ -1217,20 +1199,14 @@ static void dce_v8_0_audio_write_latency_fields(struct drm_encoder *encoder, offset = dig->afmt->pin->offset; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { -#endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); break; } } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif if (!amdgpu_connector) { DRM_ERROR("Couldn't find encoder's connector\n"); @@ -1275,9 +1251,7 @@ static void dce_v8_0_audio_write_speaker_allocation(struct drm_encoder *encoder) struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder); struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif struct amdgpu_connector *amdgpu_connector = NULL; u32 offset, tmp; u8 *sadb = NULL; @@ -1288,20 +1262,14 @@ static void dce_v8_0_audio_write_speaker_allocation(struct drm_encoder *encoder) offset = dig->afmt->pin->offset; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { -#endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); break; } } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif if (!amdgpu_connector) { DRM_ERROR("Couldn't find encoder's connector\n"); @@ -1337,9 +1305,7 @@ static void dce_v8_0_audio_write_sad_regs(struct drm_encoder *encoder) struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; u32 offset; struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif struct amdgpu_connector *amdgpu_connector = NULL; struct cea_sad *sads; int i, sad_count; @@ -1364,20 +1330,14 @@ static void dce_v8_0_audio_write_sad_regs(struct drm_encoder *encoder) offset = dig->afmt->pin->offset; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { -#endif if (connector->encoder == encoder) { amdgpu_connector = to_amdgpu_connector(connector); break; } } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif if (!amdgpu_connector) { DRM_ERROR("Couldn't find encoder's connector\n"); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index c78a8139cd5fc..cfb7886fd27f1 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -767,9 +767,7 @@ static void dmub_hpd_callback(struct amdgpu_device *adev, struct amdgpu_dm_connector *aconnector; struct amdgpu_dm_connector *hpd_aconnector = NULL; struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif struct dc_link *link; u8 link_index = 0; struct drm_device *dev; @@ -790,12 +788,8 @@ static void dmub_hpd_callback(struct amdgpu_device *adev, link_index = notify->link_index; link = adev->dm.dc->links[link_index]; dev = adev->dm.ddev; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { -#endif if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) continue; @@ -814,9 +808,7 @@ static void dmub_hpd_callback(struct amdgpu_device *adev, break; } } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif drm_modeset_unlock(&dev->mode_config.connection_mutex); if (hpd_aconnector) { @@ -1020,9 +1012,7 @@ static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port, struct drm_device *dev = dev_get_drvdata(kdev); struct amdgpu_device *adev = drm_to_adev(dev); struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter conn_iter; -#endif struct amdgpu_dm_connector *aconnector; int ret = 0; @@ -1030,12 +1020,8 @@ static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port, mutex_lock(&adev->dm.audio_lock); -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &conn_iter); drm_for_each_connector_iter(connector, &conn_iter) { -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { -#endif if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) continue; @@ -1049,9 +1035,7 @@ static int amdgpu_dm_audio_component_get_eld(struct device *kdev, int port, break; } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&conn_iter); -#endif mutex_unlock(&adev->dm.audio_lock); @@ -2530,17 +2514,11 @@ static int detect_mst_link_for_all_connectors(struct drm_device *dev) { struct amdgpu_dm_connector *aconnector; struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif int ret = 0; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { -#endif if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) continue; @@ -2562,9 +2540,7 @@ static int detect_mst_link_for_all_connectors(struct drm_device *dev) } } } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif return ret; } @@ -2669,17 +2645,11 @@ static void s3_handle_mst(struct drm_device *dev, bool suspend) { struct amdgpu_dm_connector *aconnector; struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif struct drm_dp_mst_topology_mgr *mgr; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { -#endif if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) continue; @@ -2709,9 +2679,7 @@ static void s3_handle_mst(struct drm_device *dev, bool suspend) resume_mst_branch_status(mgr); } } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif } @@ -3109,9 +3077,7 @@ static int dm_resume(void *handle) struct amdgpu_display_manager *dm = &adev->dm; struct amdgpu_dm_connector *aconnector; struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif struct drm_crtc *crtc; struct drm_crtc_state *new_crtc_state; struct dm_crtc_state *dm_new_crtc_state; @@ -3222,12 +3188,8 @@ static int dm_resume(void *handle) s3_handle_mst(ddev, false); /* Do detection*/ -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(ddev, &iter); drm_for_each_connector_iter(connector, &iter) { -#else - list_for_each_entry(connector, &(ddev)->mode_config.connector_list, head) { -#endif if (connector->connector_type == DRM_MODE_CONNECTOR_WRITEBACK) continue; @@ -3265,9 +3227,7 @@ static int dm_resume(void *handle) amdgpu_dm_update_connector_after_detect(aconnector); mutex_unlock(&aconnector->hpd_lock); } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif /* Force mode set in atomic commit */ for_each_new_crtc_in_state(dm->cached_state, crtc, new_crtc_state, i) { diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c index 07a09ccf813a6..741e2526ec127 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c @@ -323,16 +323,10 @@ int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name) dm_is_crc_source_dprx(cur_crc_src))) { struct amdgpu_dm_connector *aconn = NULL; struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter conn_iter; -#endif -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(crtc->dev, &conn_iter); drm_for_each_connector_iter(connector, &conn_iter) { -#else - list_for_each_entry(connector, &(crtc->dev)->mode_config.connector_list, head) { -#endif if (!connector->state || connector->state->crtc != crtc) continue; @@ -342,9 +336,7 @@ int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name) aconn = to_amdgpu_dm_connector(connector); break; } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&conn_iter); -#endif if (!aconn) { DRM_DEBUG_DRIVER("No amd connector matching CRTC-%d\n", crtc->index); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index dddacb5555a5c..395cd360741e0 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -3788,17 +3788,11 @@ static int mst_topo_show(struct seq_file *m, void *unused) struct amdgpu_device *adev = (struct amdgpu_device *)m->private; struct drm_device *dev = adev_to_drm(adev); struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter conn_iter; -#endif struct amdgpu_dm_connector *aconnector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &conn_iter); drm_for_each_connector_iter(connector, &conn_iter) { -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { -#endif if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) continue; @@ -3811,9 +3805,7 @@ static int mst_topo_show(struct seq_file *m, void *unused) seq_printf(m, "\nMST topology for connector %d\n", aconnector->connector_id); drm_dp_mst_dump_topology(m, &aconnector->mst_mgr); } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&conn_iter); -#endif return 0; } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c index 155d6d7db7562..3390f0d8420a0 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_irq.c @@ -893,16 +893,10 @@ void amdgpu_dm_hpd_init(struct amdgpu_device *adev) { struct drm_device *dev = adev_to_drm(adev); struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { -#endif struct amdgpu_dm_connector *amdgpu_dm_connector; const struct dc_link *dc_link; @@ -925,9 +919,7 @@ void amdgpu_dm_hpd_init(struct amdgpu_device *adev) true); } } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif } /** @@ -942,16 +934,10 @@ void amdgpu_dm_hpd_fini(struct amdgpu_device *adev) { struct drm_device *dev = adev_to_drm(adev); struct drm_connector *connector; -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN struct drm_connector_list_iter iter; -#endif -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_begin(dev, &iter); drm_for_each_connector_iter(connector, &iter) { -#else - list_for_each_entry(connector, &(dev)->mode_config.connector_list, head) { -#endif struct amdgpu_dm_connector *amdgpu_dm_connector; const struct dc_link *dc_link; @@ -973,7 +959,5 @@ void amdgpu_dm_hpd_fini(struct amdgpu_device *adev) false); } } -#ifdef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN drm_connector_list_iter_end(&iter); -#endif } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 79101ee472964..f6c2b82391196 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -854,10 +854,6 @@ static void dm_dp_mst_register_connector(struct drm_connector *connector) struct drm_device *dev = connector->dev; struct amdgpu_device *adev = drm_to_adev(dev); -#ifndef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN - drm_modeset_lock_all(dev); -#endif - #ifndef HAVE_DRM_DEVICE_FB_HELPER if (adev->mode_info.rfbdev) drm_fb_helper_add_one_connector(&adev->mode_info.rfbdev->helper, connector); @@ -865,10 +861,6 @@ static void dm_dp_mst_register_connector(struct drm_connector *connector) DRM_ERROR("adev->mode_info.rfbdev is NULL\n"); #endif -#ifndef HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN - drm_modeset_unlock_all(dev); -#endif - drm_connector_register(connector); } #endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index bb73d1ac8205f..d5c9accbf3076 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -242,9 +242,6 @@ /* drm_connector_init_with_ddc() is available */ #define HAVE_DRM_CONNECTOR_INIT_WITH_DDC 1 -/* drm_connector_list_iter_begin() is available */ -#define HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN 1 - /* connector property "max bpc" is available */ #define HAVE_DRM_CONNECTOR_PROPERTY_MAX_BPC 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-list-iter-begin.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-list-iter-begin.m4 deleted file mode 100644 index b9b18381ae244..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm-connector-list-iter-begin.m4 +++ /dev/null @@ -1,16 +0,0 @@ -dnl # -dnl # commit 613051dac40da1751ab269572766d3348d45a197 -dnl # drm: locking&new iterators for connector_list -dnl # -AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_LIST_ITER_BEGIN], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ],[ - drm_connector_list_iter_begin(NULL, NULL); - ],[ - AC_DEFINE(HAVE_DRM_CONNECTOR_LIST_ITER_BEGIN, 1, - [drm_connector_list_iter_begin() is available]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 224dfd529b06d..ad69855366bf5 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -109,7 +109,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_HDMI_VENDOR_INFOFRAME_FROM_DISPLAY_MODE AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS AC_AMDGPU_DRM_ATOMIC_PRIVATE_OBJ_INIT - AC_AMDGPU_DRM_CONNECTOR_LIST_ITER_BEGIN AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS AC_AMDGPU_DRM_DP_MST_ATOMIC_CHECK AC_AMDGPU_DRM_DP_MST_ATOMIC_ENABLE_DSC From 8b99dac1fb9a1204364a741d5fc25cd1cf1eb8f8 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Fri, 10 Feb 2023 14:36:54 +0800 Subject: [PATCH 0899/1868] drm/amdkcl: kcl-cleanup HAVE_DRM_MODE_SUBCONNECTOR_ENUM Change-Id: I9c1a099e3cb61582473c3f0bea74aa90e3bf2543 Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 3 --- drivers/gpu/drm/amd/dkms/m4/drm_dp_subconnector.m4 | 9 --------- include/kcl/kcl_drm_connector.h | 13 ------------- 3 files changed, 25 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index d5c9accbf3076..5e77f18411c0f 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -729,9 +729,6 @@ /* drm_mode_init() is available */ #define HAVE_DRM_MODE_INTT 1 -/* enum drm_mode_subconnector is available */ -/* #undef HAVE_DRM_MODE_SUBCONNECTOR_ENUM */ - /* drm_need_swiotlb() is availablea */ #define HAVE_DRM_NEED_SWIOTLB 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dp_subconnector.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dp_subconnector.m4 index a6c7c75f41f9e..527068f2403f8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_dp_subconnector.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dp_subconnector.m4 @@ -12,15 +12,6 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_SUBCONNECTOR], [ ], [ AC_DEFINE(HAVE_DRM_MODE_CONFIG_DP_SUBCONNECTOR_PROPERTY, 1, [drm_mode_config->dp_subconnector_property is available]) - ], [ - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - enum drm_mode_subconnector sub = 0; - ], [ - AC_DEFINE(HAVE_DRM_MODE_SUBCONNECTOR_ENUM, 1, - [enum drm_mode_subconnector is available]) - ]) ]) ]) ]) diff --git a/include/kcl/kcl_drm_connector.h b/include/kcl/kcl_drm_connector.h index 96e58541b57a4..ee8d72d7a4d72 100644 --- a/include/kcl/kcl_drm_connector.h +++ b/include/kcl/kcl_drm_connector.h @@ -76,24 +76,11 @@ void drm_connector_attach_dp_subconnector_property(struct drm_connector *connect void drm_dp_set_subconnector_property(struct drm_connector *connector, enum drm_connector_status status, const u8 *dpcd, const u8 prot_cap[4]); -#ifdef HAVE_DRM_MODE_SUBCONNECTOR_ENUM #define DRM_MODE_SUBCONNECTOR_VGA 1 #define DRM_MODE_SUBCONNECTOR_DisplayPort 10 #define DRM_MODE_SUBCONNECTOR_HDMIA 11 #define DRM_MODE_SUBCONNECTOR_Native 15 #define DRM_MODE_SUBCONNECTOR_Wireless 18 -#else -/* Copied from include/uapi/drm/drm_mode.h */ -/* This is for connectors with multiple signal types. */ -/* Try to match DRM_MODE_CONNECTOR_X as closely as possible. */ -enum drm_mode_subconnector { - DRM_MODE_SUBCONNECTOR_VGA = 1, /* DP */ - DRM_MODE_SUBCONNECTOR_DisplayPort = 10, /* DP */ - DRM_MODE_SUBCONNECTOR_HDMIA = 11, /* DP */ - DRM_MODE_SUBCONNECTOR_Native = 15, /* DP */ - DRM_MODE_SUBCONNECTOR_Wireless = 18, /* DP */ -}; -#endif /* HAVE_DRM_MODE_SUBCONNECTOR_ENUM */ #endif /* HAVE_DRM_MODE_CONFIG_DP_SUBCONNECTOR_PROPERTY */ #ifndef HAVE_DRM_CONNECTOR_ATOMIC_HDR_METADATA_EQUAL From b2757b12fed5f5b6e0b6fe456f86ce2939327017 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 9 Feb 2023 10:53:37 +0800 Subject: [PATCH 0900/1868] drm/amdkcl: kcl-cleanup HAVE_DRM_CRTC_HELPER_FUNCS_HAVE_ATOMIC_ENABLE Signed-off-by: Leslie Shi Reviewed-by: Ma Jun --- drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 12 +++--------- drivers/gpu/drm/amd/dkms/config/config.h | 3 --- .../drm/amd/dkms/m4/drm-crtc-helper-funcs.m4 | 19 ------------------- 3 files changed, 3 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c index f4cc269122cc6..0e5bfeb1dbf05 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c @@ -128,13 +128,11 @@ static const struct drm_crtc_funcs amdgpu_vkms_crtc_funcs = { #endif }; -static void amdgpu_vkms_crtc_atomic_enable(struct drm_crtc *crtc +static void amdgpu_vkms_crtc_atomic_enable(struct drm_crtc *crtc, #if defined(HAVE_DRM_CRTC_HELPER_FUNCS_ATOMIC_ENABLE_ARG_DRM_ATOMIC_STATE) - , struct drm_atomic_state *state) -#elif defined(HAVE_DRM_CRTC_HELPER_FUNCS_HAVE_ATOMIC_ENABLE) - , struct drm_crtc_state *state) + struct drm_atomic_state *state) #else - ) + struct drm_crtc_state *state) #endif { drm_crtc_vblank_on(crtc); @@ -175,11 +173,7 @@ static void amdgpu_vkms_crtc_atomic_flush(struct drm_crtc *crtc, static const struct drm_crtc_helper_funcs amdgpu_vkms_crtc_helper_funcs = { .atomic_flush = amdgpu_vkms_crtc_atomic_flush, -#if defined(HAVE_DRM_CRTC_HELPER_FUNCS_HAVE_ATOMIC_ENABLE) .atomic_enable = amdgpu_vkms_crtc_atomic_enable, -#else - .enable = amdgpu_vkms_crtc_atomic_enable, -#endif .atomic_disable = amdgpu_vkms_crtc_atomic_disable, }; diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 5e77f18411c0f..a84a0fbae66e2 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -286,9 +286,6 @@ drm_atomic_state arg */ #define HAVE_DRM_CRTC_HELPER_FUNCS_ATOMIC_ENABLE_ARG_DRM_ATOMIC_STATE 1 -/* have drm_crtc_helper_funcs->atomic_enable() */ -#define HAVE_DRM_CRTC_HELPER_FUNCS_HAVE_ATOMIC_ENABLE 1 - /* drm_crtc_init_with_planes() wants name */ #define HAVE_DRM_CRTC_INIT_WITH_PLANES_VALID_WITH_NAME 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-crtc-helper-funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-crtc-helper-funcs.m4 index ea944aff250c5..5bfb416a8ed5e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-crtc-helper-funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-crtc-helper-funcs.m4 @@ -35,25 +35,6 @@ AC_DEFUN([AC_AMDGPU_DRM_CRTC_HELPER_FUNCS_ATOMIC_ENABLE], [ ], [ AC_DEFINE(HAVE_DRM_CRTC_HELPER_FUNCS_ATOMIC_ENABLE_ARG_DRM_ATOMIC_STATE, 1, [drm_crtc_helper_funcs->atomic_enable()/atomic_disable() wants struct drm_atomic_state arg]) - AC_DEFINE(HAVE_DRM_CRTC_HELPER_FUNCS_HAVE_ATOMIC_ENABLE, 1, - [have drm_crtc_helper_funcs->atomic_enable()]) - - ],[ - dnl # - dnl # v4.12-rc7-1332-g0b20a0f8c3cb - dnl # drm: Add old state pointer to CRTC .enable() helper function - dnl # - AC_KERNEL_TRY_COMPILE([ - #include - #include - ], [ - struct drm_crtc_helper_funcs *p = NULL; - p->atomic_enable(NULL, NULL); - ], [ - AC_DEFINE(HAVE_DRM_CRTC_HELPER_FUNCS_HAVE_ATOMIC_ENABLE, 1, - [have drm_crtc_helper_funcs->atomic_enable()]) - ]) - ]) ]) ]) From 365ec24010cbdf60ed14cb47ad2f2dc1e9c08d01 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 9 Feb 2023 11:27:07 +0800 Subject: [PATCH 0901/1868] drm/amdkcl: kcl-cleanup HAVE_DRM_DEVICE_DRIVER_FEATURES Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 14 +------------- drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 4 ---- drivers/gpu/drm/amd/dkms/config/config.h | 3 --- .../gpu/drm/amd/dkms/m4/struct_drm_device.m4 | 19 ------------------- 4 files changed, 1 insertion(+), 39 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 3610612846771..639b911534cdd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2330,17 +2330,8 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, kcl_drm_vma_offset_manager_init(ddev->vma_offset_manager); -#ifdef HAVE_DRM_DEVICE_DRIVER_FEATURES if (!supports_atomic) ddev->driver_features &= ~DRIVER_ATOMIC; -#else - /* warn the user if they mix atomic and non-atomic capable GPUs */ - if ((amdgpu_kms_driver.driver_features & DRIVER_ATOMIC) && !supports_atomic) - DRM_ERROR("Mixing atomic and non-atomic capable GPUs!\n"); - /* support atomic early so the atomic debugfs stuff gets created */ - if (supports_atomic) - amdgpu_kms_driver.driver_features |= DRIVER_ATOMIC; -#endif kcl_pci_create_measure_file(pdev); kcl_pci_configure_extended_tags(pdev); @@ -3015,10 +3006,7 @@ const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { static struct drm_driver amdgpu_kms_driver = { .driver_features = - 0 -#ifdef HAVE_DRM_DEVICE_DRIVER_FEATURES - | DRIVER_ATOMIC -#endif /* HAVE_DRM_DEVICE_DRIVER_FEATURES */ + DRIVER_ATOMIC | DRIVER_HAVE_IRQ #ifdef HAVE_DRM_DRV_DRIVER_IRQ_SHARED | DRIVER_IRQ_SHARED diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c index cf43d436e5f5d..b6397d3229e1b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c @@ -64,11 +64,7 @@ void amdgpu_virt_init_setting(struct amdgpu_device *adev) adev->mode_info.num_crtc = 1; adev->enable_virtual_display = true; } -#ifdef HAVE_DRM_DEVICE_DRIVER_FEATURES ddev->driver_features &= ~DRIVER_ATOMIC; -#else - ddev->driver->driver_features &= ~DRIVER_ATOMIC; -#endif adev->cg_flags = 0; adev->pg_flags = 0; diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index a84a0fbae66e2..439abaf9a22d0 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -292,9 +292,6 @@ /* drm_debug_enabled() is available */ #define HAVE_DRM_DEBUG_ENABLED 1 -/* dev_device->driver_features is available */ -#define HAVE_DRM_DEVICE_DRIVER_FEATURES 1 - /* struct drm_device has fb_helper member */ #define HAVE_DRM_DEVICE_FB_HELPER 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_device.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_device.m4 index 7ea0061caa47e..929e3edc5f603 100644 --- a/drivers/gpu/drm/amd/dkms/m4/struct_drm_device.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_device.m4 @@ -1,21 +1,3 @@ -dnl # -dnl # commit v4.19-rc1-194-g18ace11f87e6 -dnl # drm: Introduce per-device driver_features -dnl # -AC_DEFUN([AC_AMDGPU_DRM_DEVICE_DRIVER_FEATURES], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ],[ - struct drm_device *ddev = NULL; - ddev->driver_features = 0; - ],[ - AC_DEFINE(HAVE_DRM_DEVICE_DRIVER_FEATURES, 1, - [dev_device->driver_features is available]) - ]) - ]) -]) - dnl # dnl # commit v5.5-rc2-1419-g7e13ad896484 dnl # drm: Avoid drm_global_mutex for simple inc/dec of dev->open_count @@ -35,6 +17,5 @@ AC_DEFUN([AC_AMDGPU_DRM_DEVICE_OPEN_COUNT], [ ]) AC_DEFUN([AC_AMDGPU_STRUCT_DRM_DEVICE], [ - AC_AMDGPU_DRM_DEVICE_DRIVER_FEATURES AC_AMDGPU_DRM_DEVICE_OPEN_COUNT ]) From 2b348a7a584405ab01498d45ae63ba0e21754c1b Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 9 Feb 2023 11:45:51 +0800 Subject: [PATCH 0902/1868] drm/amdkcl: kcl-cleanup HAVE_DRM_DEVICE_FB_HELPER Signed-off-by: Leslie Shi Reviewed-by: Ma Jun --- .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 11 ---------- drivers/gpu/drm/amd/dkms/config/config.h | 3 --- .../drm/amd/dkms/m4/drm-device-fb-helper.m4 | 21 ------------------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - include/kcl/backport/kcl_drm_fb.h | 3 +-- 5 files changed, 1 insertion(+), 38 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-device-fb-helper.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index f6c2b82391196..9efeecbe2ccb7 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -830,10 +830,6 @@ static void dm_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr, mutex_unlock(&mgr->lock); } drm_connector_unregister(connector); -#if defined(HAVE_DRM_FB_HELPER_ADD_REMOVE_CONNECTORS) && !defined(HAVE_DRM_DEVICE_FB_HELPER) - if (adev->mode_info.rfbdev) - drm_fb_helper_remove_one_connector(&adev->mode_info.rfbdev->helper, connector); -#endif drm_connector_put(connector); } #endif @@ -854,13 +850,6 @@ static void dm_dp_mst_register_connector(struct drm_connector *connector) struct drm_device *dev = connector->dev; struct amdgpu_device *adev = drm_to_adev(dev); -#ifndef HAVE_DRM_DEVICE_FB_HELPER - if (adev->mode_info.rfbdev) - drm_fb_helper_add_one_connector(&adev->mode_info.rfbdev->helper, connector); - else - DRM_ERROR("adev->mode_info.rfbdev is NULL\n"); -#endif - drm_connector_register(connector); } #endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 439abaf9a22d0..6001bdc707243 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -292,9 +292,6 @@ /* drm_debug_enabled() is available */ #define HAVE_DRM_DEBUG_ENABLED 1 -/* struct drm_device has fb_helper member */ -#define HAVE_DRM_DEVICE_FB_HELPER 1 - /* drm_device->filelist_mutex is available */ #define HAVE_DRM_DEVICE_FILELIST_MUTEX 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-device-fb-helper.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-device-fb-helper.m4 deleted file mode 100644 index b5e24caf0a842..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm-device-fb-helper.m4 +++ /dev/null @@ -1,21 +0,0 @@ -dnl # -dnl # commit v4.14-rc3-575-g29ad20b22c8f -dnl # drm: Add drm_device->fb_helper pointer -dnl # -AC_DEFUN([AC_AMDGPU_DRM_DEVICE_FB_HELPER], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DRMP_H - #include - #endif - #ifdef HAVE_DRM_DRM_DEVICE_H - #include - #endif - ], [ - struct drm_device *pdd = NULL; - pdd->fb_helper = NULL; - ], [ - AC_DEFINE(HAVE_DRM_DEVICE_FB_HELPER, 1, [struct drm_device has fb_helper member]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index ad69855366bf5..42385bfb69d53 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -166,7 +166,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_SIMPLE_ENCODER_INIT AC_AMDGPU_DRM_MODE_CONFIG_HELPER_SUSPEND AC_AMDGPU_DRM_FBDEV_GENERIC_SETUP - AC_AMDGPU_DRM_DEVICE_FB_HELPER AC_AMDGPU_DRM_DP_UPDATE_PAYLOAD_PART1_START_SLOT_ARG AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS AC_AMDGPU_DRM_DISPLAY_INFO_IS_HDMI diff --git a/include/kcl/backport/kcl_drm_fb.h b/include/kcl/backport/kcl_drm_fb.h index f1d242ac9d61f..1269be6e2d9c9 100644 --- a/include/kcl/backport/kcl_drm_fb.h +++ b/include/kcl/backport/kcl_drm_fb.h @@ -38,8 +38,7 @@ void _kcl_drm_helper_mode_fill_fb_struct(struct drm_device *dev, #define drm_helper_mode_fill_fb_struct _kcl_drm_helper_mode_fill_fb_struct #endif -#if defined(HAVE_DRM_FBDEV_GENERIC_SETUP) && \ - defined(HAVE_DRM_DEVICE_FB_HELPER) +#if defined(HAVE_DRM_FBDEV_GENERIC_SETUP) #define AMDKCL_DRM_FBDEV_GENERIC #endif From 90ebc7e21b3e85840f49d785682d18f6588b17f1 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 9 Feb 2023 12:14:45 +0800 Subject: [PATCH 0903/1868] drm/amdkcl: kcl-cleanup HAVE_DRM_DEV_ENTER also remove macro HAVE_DRM_DEV_IS_UNPLUGGED Signed-off-by: Leslie Shi Reviewed-by: Ma Jun --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_drm_drv.c | 73 ------------------- drivers/gpu/drm/amd/dkms/config/config.h | 6 -- drivers/gpu/drm/amd/dkms/m4/drm-dev-enter.m4 | 19 ----- .../drm/amd/dkms/m4/drm-dev-is-unplugged.m4 | 21 ------ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 - include/kcl/kcl_drm_drv.h | 70 ------------------ 7 files changed, 1 insertion(+), 192 deletions(-) delete mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_drv.c delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dev-enter.m4 delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dev-is-unplugged.m4 delete mode 100644 include/kcl/kcl_drm_drv.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 0accf6c787b2b..eb1682f507b91 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -12,7 +12,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_drm_crtc.o kcl_drm_connector.o kcl_drm_atomic_helper.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_fs_read_write.o kcl_drm_aperture.o \ - kcl_drm_drv.o kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o \ + kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o \ kcl_mce_amd.o kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_drv.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_drv.c deleted file mode 100644 index 8014069a7c654..0000000000000 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_drv.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Created: Fri Jan 19 10:48:35 2001 by faith@acm.org - * - * Copyright 2001 VA Linux Systems, Inc., Sunnyvale, California. - * All Rights Reserved. - * - * Author Rickard E. (Rik) Faith - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef HAVE_DRM_DEV_ENTER -#include -#include - -DEFINE_STATIC_SRCU(drm_unplug_srcu); - -/** - * drm_dev_enter - Enter device critical section - * @dev: DRM device - * @idx: Pointer to index that will be passed to the matching drm_dev_exit() - * - * This function marks and protects the beginning of a section that should not - * be entered after the device has been unplugged. The section end is marked - * with drm_dev_exit(). Calls to this function can be nested. - * - * Returns: - * True if it is OK to enter the section, false otherwise. - */ -bool drm_dev_enter(struct drm_device *dev, int *idx) -{ - *idx = srcu_read_lock(&drm_unplug_srcu); - - if (atomic_read(&dev->unplugged)) { - srcu_read_unlock(&drm_unplug_srcu, *idx); - return false; - } - - return true; -} -EXPORT_SYMBOL(drm_dev_enter); - -/** - * drm_dev_exit - Exit device critical section - * @idx: index returned from drm_dev_enter() - * - * This function marks the end of a section that should not be entered after - * the device has been unplugged. - */ -void drm_dev_exit(int idx) -{ - srcu_read_unlock(&drm_unplug_srcu, idx); -} -EXPORT_SYMBOL(drm_dev_exit); - -#endif /* HAVE_DRM_DEV_ENTER */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 6001bdc707243..4510879b53b3a 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -301,12 +301,6 @@ /* struct drm_device has pdev member */ /* #undef HAVE_DRM_DEVICE_PDEV */ -/* drm_dev_enter() is available */ -#define HAVE_DRM_DEV_ENTER 1 - -/* drm_dev_is_unplugged() is available */ -#define HAVE_DRM_DEV_IS_UNPLUGGED 1 - /* drm_dev_put() is available */ #define HAVE_DRM_DEV_PUT 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dev-enter.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dev-enter.m4 deleted file mode 100644 index 4ac5579c0f5c2..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dev-enter.m4 +++ /dev/null @@ -1,19 +0,0 @@ -dnl # -dnl # commit bee330f3d67273a68dcb99f59480d59553c008b2 -dnl # drm: Use srcu to protect drm_device.unplugged -dnl # -AC_DEFUN([AC_AMDGPU_DRM_DEV_ENTER], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #ifdef HAVE_DRM_DRMP_H - #include - #else - #include - #endif - ], [ - drm_dev_enter(NULL, NULL); - ], [drm_dev_enter], [drivers/gpu/drm/drm_drv.c], [ - AC_DEFINE(HAVE_DRM_DEV_ENTER, 1, [drm_dev_enter() is available]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dev-is-unplugged.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dev-is-unplugged.m4 deleted file mode 100644 index 4a05d157649e4..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dev-is-unplugged.m4 +++ /dev/null @@ -1,21 +0,0 @@ -dnl # -dnl # commit bee330f3d67273a68dcb99f59480d59553c008b2 -dnl # drm: Use srcu to protect drm_device.unplugged -dnl # -AC_DEFUN([AC_AMDGPU_DRM_DEV_IS_UNPLUGGED], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DRMP_H - #include - #endif - #ifdef HAVE_DRM_DRM_DRV_H - #include - #endif - ], [ - drm_dev_is_unplugged(NULL); - ], [ - AC_DEFINE(HAVE_DRM_DEV_IS_UNPLUGGED, 1, - [drm_dev_is_unplugged() is available]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 42385bfb69d53..bd34e3c628222 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -159,8 +159,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_ATOMIC_HDR_METADATA_EQUAL AC_AMDGPU_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY AC_AMDGPU_DRM_CONNECTOR_STATE_HDR_OUTPUT_METADATA - AC_AMDGPU_DRM_DEV_ENTER - AC_AMDGPU_DRM_DEV_IS_UNPLUGGED AC_AMDGPU_DRM_DEVICE_PDEV AC_AMDGPU_DRM_CONNECTOR_SET_PANEL_ORIENTATION_WITH_QUIRK AC_AMDGPU_DRM_SIMPLE_ENCODER_INIT diff --git a/include/kcl/kcl_drm_drv.h b/include/kcl/kcl_drm_drv.h deleted file mode 100644 index 0360a07613727..0000000000000 --- a/include/kcl/kcl_drm_drv.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. - * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. - * Copyright (c) 2009-2010, Code Aurora Forum. - * Copyright 2016 Intel Corp. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ -#ifndef __KCL_KCL_DRM_DRV_H__ -#define __KCL_KCL_DRM_DRV_H__ - -#include -#include - -#ifndef HAVE_DRM_DEV_ENTER -/* Copied from include/drm/drm_drv.h*/ - -bool drm_dev_enter(struct drm_device *dev, int *idx); -void drm_dev_exit(int idx); - -#ifndef HAVE_DRM_DEV_IS_UNPLUGGED -/** - * drm_dev_is_unplugged - is a DRM device unplugged - * @dev: DRM device - * - * This function can be called to check whether a hotpluggable is unplugged. - * Unplugging itself is singalled through drm_dev_unplug(). If a device is - * unplugged, these two functions guarantee that any store before calling - * drm_dev_unplug() is visible to callers of this function after it completes - * - * WARNING: This function fundamentally races against drm_dev_unplug(). It is - * recommended that drivers instead use the underlying drm_dev_enter() and - * drm_dev_exit() function pairs. - */ -static inline bool drm_dev_is_unplugged(struct drm_device *dev) -{ - int idx; - - if (drm_dev_enter(dev, &idx)) { - drm_dev_exit(idx); - return false; - } - - return true; -} -#endif /* HAVE_DRM_DEV_IS_UNPLUGGED */ -#endif /* HAVE_DRM_DEV_ENTER */ - -#ifndef HAVE_DRM_FIRMWARE_DRIVERS_ONLY -extern bool drm_firmware_drivers_only(void); -#endif /* HAVE_DRM_FIRMWARE_DRIVERS_ONLY */ - -#endif From beae83d50cee8f715407508a0c35690924a36924 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Mon, 13 Feb 2023 09:40:57 +0800 Subject: [PATCH 0904/1868] drm/amdkcl: kcl-cleanup HAVE_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED Change-Id: I47eeadd6c7a9fd91ccaff1d8d7077a6961b543ee Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c | 23 +------------------ drivers/gpu/drm/amd/dkms/config/config.h | 3 --- .../m4/drm-fb-helper-set-suspend-unlocked.m4 | 20 ---------------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - include/kcl/kcl_drm_fb.h | 11 --------- 5 files changed, 1 insertion(+), 57 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-set-suspend-unlocked.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c index 139e955f225eb..bdd63a1cc9b36 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c @@ -56,25 +56,4 @@ void drm_fb_helper_fill_info(struct fb_info *info, } EXPORT_SYMBOL(drm_fb_helper_fill_info); -#endif - -#ifndef HAVE_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED -/** - * Copied from drivers/gpu/drm/drm_fb_helper.c and modified for KCL. - * _kcl_drm_fb_helper_set_suspend_stub - wrapper around fb_set_suspend - * @fb_helper: driver-allocated fbdev helper - * @state: desired state, zero to resume, non-zero to suspend - * - * A wrapper around fb_set_suspend implemented by fbdev core - */ -void _kcl_drm_fb_helper_set_suspend_unlocked(struct drm_fb_helper *fb_helper, int state) -{ - if (!fb_helper || !fb_helper->fbdev) - return; - - console_lock(); - fb_set_suspend(fb_helper->fbdev, state); - console_unlock(); -} -EXPORT_SYMBOL(_kcl_drm_fb_helper_set_suspend_unlocked); -#endif +#endif \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 4510879b53b3a..e2162408c74f7 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -603,9 +603,6 @@ /* whether drm_fb_helper_lastclose() is available */ #define HAVE_DRM_FB_HELPER_LASTCLOSE 1 -/* drm_fb_helper_set_suspend_unlocked() is available */ -#define HAVE_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED 1 - /* drm_fb_helper_unregister_info() is available */ #define HAVE_DRM_FB_HELPER_UNREGISTER_INFO 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-set-suspend-unlocked.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-set-suspend-unlocked.m4 deleted file mode 100644 index c2502e2f914da..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-set-suspend-unlocked.m4 +++ /dev/null @@ -1,20 +0,0 @@ -dnl # -dnl # commit cfe63423d9be3e7020296c3dfb512768a83cd099 -dnl # drm/fb-helper: Add drm_fb_helper_set_suspend_unlocked() -dnl # -AC_DEFUN([AC_AMDGPU_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DRMP_H - struct vm_area_struct; - #include - #endif - #include - ], [ - drm_fb_helper_set_suspend_unlocked(NULL,0); - ], [ - AC_DEFINE(HAVE_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED, 1, - [drm_fb_helper_set_suspend_unlocked() is available]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index bd34e3c628222..7fb5aacfa16eb 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -90,7 +90,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_PCI_PR3_PRESENT AC_AMDGPU_KTHREAD_USE_MM AC_AMDGPU_DRM_FB_HELPER_FILL_INFO - AC_AMDGPU_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED AC_AMDGPU_DRM_HELPER_MODE_FILL_FB_STRUCT AC_AMDGPU_DRM_FB_HELPER_INIT AC_AMDGPU_DRM_GET_FORMAT_INFO diff --git a/include/kcl/kcl_drm_fb.h b/include/kcl/kcl_drm_fb.h index 392638c78018c..795395d696484 100644 --- a/include/kcl/kcl_drm_fb.h +++ b/include/kcl/kcl_drm_fb.h @@ -61,17 +61,6 @@ void drm_fb_helper_fill_info(struct fb_info *info, struct drm_fb_helper_surface_size *sizes); #endif -#ifndef HAVE_DRM_FB_HELPER_SET_SUSPEND_UNLOCKED -extern void _kcl_drm_fb_helper_set_suspend_unlocked(struct drm_fb_helper *fb_helper, int state); -static inline -void drm_fb_helper_set_suspend_unlocked(struct drm_fb_helper *fb_helper, - bool suspend) - -{ - _kcl_drm_fb_helper_set_suspend_unlocked(fb_helper, suspend); -} -#endif - #ifndef HAVE_IS_FIRMWARE_FRAMEBUFFER extern bool is_firmware_framebuffer(struct apertures_struct *a); #endif From 29a540f8e41d62af0e171c6194e4f3741c280b82 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Mon, 13 Feb 2023 09:44:24 +0800 Subject: [PATCH 0905/1868] drm/amdkcl: kcl-cleanup HAVE_DRM_EDID_GET_MONITOR_NAME Change-Id: I919069ffe537d38ff16ebe6123eb5b33c6aa5276 Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 21 +------------------ drivers/gpu/drm/amd/dkms/config/config.h | 9 -------- .../amd/dkms/m4/drm-edid-get-monitor-name.m4 | 17 --------------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - 4 files changed, 1 insertion(+), 47 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-edid-get-monitor-name.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index 0fe8ddab1b609..d495db2b7667a 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -135,9 +135,6 @@ enum dc_edid_status dm_helpers_parse_edid_caps( int sadb_count = -1; int i = 0; uint8_t *sadb = NULL; -#if !defined(HAVE_DRM_EDID_GET_MONITOR_NAME) - int j = 0; -#endif enum dc_edid_status result = EDID_OK; @@ -154,26 +151,10 @@ enum dc_edid_status dm_helpers_parse_edid_caps( edid_caps->serial_number = edid_buf->serial; edid_caps->manufacture_week = edid_buf->mfg_week; edid_caps->manufacture_year = edid_buf->mfg_year; -#if defined(HAVE_DRM_EDID_GET_MONITOR_NAME) + drm_edid_get_monitor_name(edid_buf, edid_caps->display_name, AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS); -#else - /* One of the four detailed_timings stores the monitor name. It's - * stored in an array of length 13. */ - for (i = 0; i < 4; i++) { - if (edid_buf->detailed_timings[i].data.other_data.type == 0xfc) { - while (j < 13 && edid_buf->detailed_timings[i].data.other_data.data.str.str[j]) { - if (edid_buf->detailed_timings[i].data.other_data.data.str.str[j] == '\n') - break; - - edid_caps->display_name[j] = - edid_buf->detailed_timings[i].data.other_data.data.str.str[j]; - j++; - } - } - } -#endif #if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) edid_caps->edid_hdmi = connector->display_info.is_hdmi; diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index e2162408c74f7..1ca2d9291383b 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1298,15 +1298,6 @@ /* drm_dsc_pps_payload_pack() is available */ #define HAVE_DRM_DSC_PPS_PAYLOAD_PACK 1 -/* drm_edid_get_monitor_name is available*/ -#define HAVE_DRM_EDID_GET_MONITOR_NAME 1 - -/* __drm_atomic_helper_connector_destroy_state() wants 1 arg */ -#define HAVE___DRM_ATOMIC_HELPER_CONNECTOR_DESTROY_STATE_P 1 - -/* __drm_atomic_helper_crtc_destroy_state() wants 1 arg */ -#define HAVE___DRM_ATOMIC_HELPER_CRTC_DESTROY_STATE_P 1 - /* __drm_atomic_helper_crtc_reset() is available */ #define HAVE___DRM_ATOMIC_HELPER_CRTC_RESET 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-edid-get-monitor-name.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-edid-get-monitor-name.m4 deleted file mode 100644 index 4a6a10c962f4c..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm-edid-get-monitor-name.m4 +++ /dev/null @@ -1,17 +0,0 @@ -dnl # -dnl # commit v4.6-rc2-221-g59f7c0fa325e -dnl # drm/edid: Add drm_edid_get_monitor_name() -dnl # -AC_DEFUN([AC_AMDGPU_DRM_EDID_GET_MONITOR_NAME], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include - ], [ - drm_edid_get_monitor_name(NULL, NULL, 0); - ], [drm_edid_get_monitor_name], [drivers/gpu/drm/drm_edid.c], [ - AC_DEFINE(HAVE_DRM_EDID_GET_MONITOR_NAME, 1, - [drm_edid_get_monitor_name() are available]) - ]) - ]) -]) - diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 7fb5aacfa16eb..1364b19f00004 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -167,7 +167,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS AC_AMDGPU_DRM_DISPLAY_INFO_IS_HDMI AC_AMDGPU_DRM_BITMAP_FUNCS - AC_AMDGPU_DRM_EDID_GET_MONITOR_NAME AC_AMDGPU_STRUCT_KOBJ_TYPE AC_AMDGPU_CLOSE_FD AC_AMDGPU_IS_FIRMWARE_FRAMEBUFFER From 57538432a1cb19436a624c96206fb006be8ee2ad Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Mon, 13 Feb 2023 10:33:59 +0800 Subject: [PATCH 0906/1868] drm/amdkcl: kcl-cleanup HAVE_DRM_DRM_PRINT_H Also removed related macro HAVE_DRM_PRINTER_PREFIX Change-Id: Iac8228a7ce9011fbb67423ea55d811e3e810717d Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c | 34 ---------------- drivers/gpu/drm/amd/dkms/config/config.h | 6 --- drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 6 --- drivers/gpu/drm/amd/dkms/m4/drm_print.m4 | 21 ---------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - include/kcl/header/drm/drm_print.h | 2 - include/kcl/kcl_drm_print.h | 46 ---------------------- 7 files changed, 116 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_print.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c index 95e75be1d5ee8..68e4abe6470c6 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_print.c @@ -26,40 +26,6 @@ #include #include -#if !defined(HAVE_DRM_DRM_PRINT_H) -void drm_printf(struct drm_printer *p, const char *f, ...) -{ - struct va_format vaf; - va_list args; - - va_start(args, f); - vaf.fmt = f; - vaf.va = &args; - p->printfn(p, &vaf); - va_end(args); -} -EXPORT_SYMBOL(drm_printf); - -void __drm_printfn_seq_file(struct drm_printer *p, struct va_format *vaf) -{ - seq_printf(p->arg, "%pV", vaf); -} -EXPORT_SYMBOL(__drm_printfn_seq_file); -#endif - -#if !defined(HAVE_DRM_PRINTER_PREFIX) -void __drm_printfn_debug(struct drm_printer *p, struct va_format *vaf) -{ -#ifndef HAVE_DRM_DRM_PRINT_H - printk(KERN_DEBUG "[" DRM_NAME ":]" "%s %pV", p->prefix, vaf); -#else - printk(KERN_DEBUG "[" DRM_NAME ":]" "%s %pV", "no prefix", vaf); -#endif -} -EXPORT_SYMBOL(__drm_printfn_debug); -#endif - - #if !defined(HAVE_DRM_ERR_MACRO) void kcl_drm_err(const char *format, ...) { diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 1ca2d9291383b..c5b97228605e2 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -542,9 +542,6 @@ /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_PLANE_H 1 -/* Define to 1 if you have the header file. */ -#define HAVE_DRM_DRM_PRINT_H 1 - /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_PROBE_HELPER_H 1 @@ -742,9 +739,6 @@ /* drm_prime_sg_to_dma_addr_array() is available */ #define HAVE_DRM_PRIME_SG_TO_DMA_ADDR_ARRAY 1 -/* drm_printer->prefix is available */ -#define HAVE_DRM_PRINTER_PREFIX 1 - /* drm_print_bits() is available */ #define HAVE_DRM_PRINT_BITS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index ccdccb0e48d30..5004222733f88 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -9,12 +9,6 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # AC_KERNEL_CHECK_HEADERS([drm/amdgpu_pciid.h]) - dnl # - dnl # commit v4.9-rc2-477-gd8187177b0b1 - dnl # drm: add helper for printing to log or seq_file - dnl # - AC_KERNEL_CHECK_HEADERS([drm/drm_print.h]) - dnl # dnl # commit v5.0-rc1-342-gfcd70cd36b9b dnl # drm: Split out drm_probe_helper.h diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_print.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_print.m4 deleted file mode 100644 index 3c4a306d53cd3..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm_print.m4 +++ /dev/null @@ -1,21 +0,0 @@ -dnl # -dnl # v4.9-rc2-477-gd8187177b0b1 drm: add helper for printing to log or seq_file -dnl # -AC_DEFUN([AC_AMDGPU_DRM_PRINTER], [ - AC_KERNEL_DO_BACKGROUND([ - AS_IF([test $HAVE_DRM_DRM_PRINT_H], [ - dnl # - dnl # v4.9-rc8-1738-gb5c3714fe878 drm/mm: Convert to drm_printer - dnl # v4.9-rc8-1737-g3d387d923c18 drm/printer: add debug printer - dnl # - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - struct drm_printer *p = NULL; - p->prefix = NULL; - ], [ - AC_DEFINE(HAVE_DRM_PRINTER_PREFIX, 1, [drm_printer->prefix is available]) - ]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 1364b19f00004..edfcf05907149 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -79,7 +79,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU___DRM_ATOMIC_HELPER_CRTC_RESET AC_AMDGPU_DRM_DRIVER_GEM_PRIME_RES_OBJ AC_AMDGPU_DRM_DRV_GEM_PRIME_EXPORT - AC_AMDGPU_DRM_PRINTER AC_AMDGPU_DRM_PRINT_BITS AC_AMDGPU_DRM_MM_INSERT_MODE AC_AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES diff --git a/include/kcl/header/drm/drm_print.h b/include/kcl/header/drm/drm_print.h index 0f1db6376a8a3..a6734c48c8eb5 100644 --- a/include/kcl/header/drm/drm_print.h +++ b/include/kcl/header/drm/drm_print.h @@ -2,9 +2,7 @@ #ifndef _KCL_HEADER_DRM_PRINT_H_H_ #define _KCL_HEADER_DRM_PRINT_H_H_ -#if defined(HAVE_DRM_DRM_PRINT_H) #include_next -#endif #include #endif diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index a726abd73190d..71a5b6f419e46 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -29,52 +29,6 @@ #include #include -#if !defined(HAVE_DRM_DRM_PRINT_H) -/* Copied from d8187177b0b1 include/drm/drm_print.h */ -struct drm_printer { - void (*printfn)(struct drm_printer *p, struct va_format *vaf); - void *arg; - const char *prefix; -}; - -void drm_printf(struct drm_printer *p, const char *f, ...); -void __drm_printfn_seq_file(struct drm_printer *p, struct va_format *vaf); -static inline struct drm_printer drm_seq_file_printer(struct seq_file *f) -{ - struct drm_printer p = { - .printfn = __drm_printfn_seq_file, - .arg = f, - }; - return p; -} -#endif - -/* Copied from 3d387d923c18 include/drm/drm_print.h */ -#if !defined(HAVE_DRM_PRINTER_PREFIX) -extern void __drm_printfn_debug(struct drm_printer *p, struct va_format *vaf); - -static inline struct drm_printer drm_debug_printer(const char *prefix) -{ - struct drm_printer p = { - .printfn = __drm_printfn_debug, -#ifndef HAVE_DRM_DRM_PRINT_H - .prefix = prefix -#endif - }; - return p; -} - -static inline -void drm_mm_print(const struct drm_mm *mm, struct drm_printer *p) -{ -#ifndef HAVE_DRM_DRM_PRINT_H - drm_mm_debug_table((struct drm_mm *)mm, p->prefix); -#else - drm_mm_debug_table((struct drm_mm *)mm, "no prefix"); -#endif -} -#endif - #ifndef _DRM_PRINTK #define _DRM_PRINTK(once, level, fmt, ...) \ do { \ From cbd4e9072ae72ebfd41f9e5ede8031a944a08858 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Fri, 10 Feb 2023 10:58:47 +0800 Subject: [PATCH 0907/1868] drm/amdkcl: kcl-cleanup HAVE_DRM_DP_CEC_CORRELATION_FUNCTIONS Signed-off-by: Leslie Shi Reviewed-by: Ma Jun --- drivers/gpu/drm/amd/dkms/config/config.h | 3 --- .../m4/drm-dp-cec-correlation-functions.m4 | 21 ------------------- include/kcl/kcl_drm_dp_cec.h | 14 ------------- 3 files changed, 38 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index c5b97228605e2..ac2f345a476ab 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -376,9 +376,6 @@ /* drm_dp_calc_pbn_mode() wants 3args */ #define HAVE_DRM_DP_CALC_PBN_MODE_3ARGS 1 -/* drm_dp_cec* correlation functions are available */ -#define HAVE_DRM_DP_CEC_CORRELATION_FUNCTIONS 1 - /* drm_dp_cec_register_connector() wants p,p interface */ #define HAVE_DRM_DP_CEC_REGISTER_CONNECTOR_PP 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-cec-correlation-functions.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-cec-correlation-functions.m4 index 30cf21b106f4b..3ba925a8e076f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-cec-correlation-functions.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-cec-correlation-functions.m4 @@ -17,27 +17,6 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_CEC_CORRELATION_FUNCTIONS], [ ], [ AC_DEFINE(HAVE_DRM_DP_CEC_REGISTER_CONNECTOR_PP, 1, [drm_dp_cec_register_connector() wants p,p interface]) - AC_DEFINE(HAVE_DRM_DP_CEC_CORRELATION_FUNCTIONS, 1, - [drm_dp_cec* correlation functions are available]) - ], [ - AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_HELPER_H) - #include - #else - #include - #endif - ], [ - drm_dp_cec_irq(NULL); - drm_dp_cec_register_connector(NULL, NULL, NULL); - drm_dp_cec_unregister_connector(NULL); - drm_dp_cec_set_edid(NULL, NULL); - drm_dp_cec_unset_edid(NULL); - ], [ - AC_DEFINE(HAVE_DRM_DP_CEC_CORRELATION_FUNCTIONS, 1, - [drm_dp_cec* correlation functions are available]) - ]) ]) ]) ]) diff --git a/include/kcl/kcl_drm_dp_cec.h b/include/kcl/kcl_drm_dp_cec.h index 58549a2e15bf1..a50c290cc7248 100644 --- a/include/kcl/kcl_drm_dp_cec.h +++ b/include/kcl/kcl_drm_dp_cec.h @@ -22,7 +22,6 @@ #if defined(AMDKCL_DRM_DP_CEC_XXX_CHECK_CB) static inline void _kcl_drm_dp_cec_irq(struct drm_dp_aux *aux) { -#if defined(HAVE_DRM_DP_CEC_CORRELATION_FUNCTIONS) #ifdef CONFIG_DRM_DP_CEC /* No transfer function was set, so not a DP connector */ if (!aux->transfer) @@ -30,13 +29,11 @@ static inline void _kcl_drm_dp_cec_irq(struct drm_dp_aux *aux) #endif drm_dp_cec_irq(aux); -#endif } static inline void _kcl_drm_dp_cec_set_edid(struct drm_dp_aux *aux, const struct edid *edid) { -#if defined(HAVE_DRM_DP_CEC_CORRELATION_FUNCTIONS) #ifdef CONFIG_DRM_DP_CEC /* No transfer function was set, so not a DP connector */ if (!aux->transfer) @@ -44,12 +41,10 @@ static inline void _kcl_drm_dp_cec_set_edid(struct drm_dp_aux *aux, #endif drm_dp_cec_set_edid(aux, edid); -#endif } static inline void _kcl_drm_dp_cec_unset_edid(struct drm_dp_aux *aux) { -#if defined(HAVE_DRM_DP_CEC_CORRELATION_FUNCTIONS) #ifdef CONFIG_DRM_DP_CEC /* No transfer function was set, so not a DP connector */ if (!aux->transfer) @@ -57,13 +52,6 @@ static inline void _kcl_drm_dp_cec_unset_edid(struct drm_dp_aux *aux) #endif drm_dp_cec_unset_edid(aux); -#endif -} -#endif - -#if !defined(HAVE_DRM_DP_CEC_CORRELATION_FUNCTIONS) -static inline void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux) -{ } #endif @@ -71,14 +59,12 @@ static inline void drm_dp_cec_unregister_connector(struct drm_dp_aux *aux) static inline void _kcl_drm_dp_cec_register_connector(struct drm_dp_aux *aux, struct drm_connector *connector) { -#if defined(HAVE_DRM_DP_CEC_CORRELATION_FUNCTIONS) #ifdef CONFIG_DRM_DP_CEC if (WARN_ON(!aux->transfer)) return; #endif drm_dp_cec_register_connector(aux, connector->name, connector->dev->dev); -#endif } #endif From dc2dea8d834c6d0b72db1621ae4a40784c28feda Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Fri, 10 Feb 2023 12:48:43 +0800 Subject: [PATCH 0908/1868] drm/amdkcl: kcl-cleanup HAVE_DRM_DP_MST_ALLOCATE_VCPI_P_P_I_I Signed-off-by: Leslie Shi Reviewed-by: Ma Jun --- .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 8 -------- drivers/gpu/drm/amd/dkms/config/config.h | 3 --- .../gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 | 16 ---------------- 3 files changed, 27 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index d495db2b7667a..7d3ccc036bbc6 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -444,19 +444,11 @@ bool dm_helpers_dp_mst_write_payload_allocation_table( slots = drm_dp_find_vcpi_slots(mst_mgr, pbn); ret = drm_dp_mst_allocate_vcpi(mst_mgr, mst_port, pbn, -#ifdef HAVE_DRM_DP_MST_ALLOCATE_VCPI_P_P_I_I slots); -#else - &slots); -#endif /* HAVE_DRM_DP_MST_ALLOCATE_VCPI_P_P_I_I */ #else ret = drm_dp_mst_allocate_vcpi(mst_mgr, mst_port, dm_conn_state->pbn, -#ifdef HAVE_DRM_DP_MST_ALLOCATE_VCPI_P_P_I_I dm_conn_state->vcpi_slots); -#else - &dm_conn_state->vcpi_slots); -#endif /* HAVE_DRM_DP_MST_ALLOCATE_VCPI_P_P_I_I */ #endif if (!ret) return false; diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index ac2f345a476ab..4545e45ab0cd2 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -394,9 +394,6 @@ /* drm_dp_mst_add_affected_dsc_crtcs() is available */ #define HAVE_DRM_DP_MST_ADD_AFFECTED_DSC_CRTCS 1 -/* drm_dp_mst_allocate_vcpi() has p,p,i,i interface */ -#define HAVE_DRM_DP_MST_ALLOCATE_VCPI_P_P_I_I 1 - /* drm_dp_mst_atomic_check() is available */ #define HAVE_DRM_DP_MST_ATOMIC_CHECK 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 index ef01260a09ddb..cf4afe7538011 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 @@ -6,22 +6,6 @@ dnl # Note: This autoconf only works with compiler flag -Werror dnl # The interface types are specified in Hungarian notation dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else - #include - #endif - ], [ - drm_dp_mst_allocate_vcpi(NULL, NULL, 1, 1); - ], [ - AC_DEFINE(HAVE_DRM_DP_MST_ALLOCATE_VCPI_P_P_I_I, 1, [ - drm_dp_mst_allocate_vcpi() has p,p,i,i interface]) - ]) - ]) dnl # dnl # commit d25689760b747287c6ca03cfe0729da63e0717f4 dnl # drm/amdgpu/display: Keep malloc ref to MST port From 938956007bdf464d04e647d7f5334a1ce6fd1bb1 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Fri, 10 Feb 2023 13:17:02 +0800 Subject: [PATCH 0909/1868] drm/amdkcl: kcl-cleanup HAVE_DRM_DRIVER_GET_VBLANK_TIMESTAMP_USE_KTIMER_T_ARG This also remove macro HAVE_DRM_DRIVER_GET_SCANOUT_POSITION_RETURN_BOOL and HAVE_DRM_DRIVER_GET_VBLANK_TIMESTAMP_RETURN_BOOL Signed-off-by: Leslie Shi Reviewed-by: Ma Jun --- .../drm/amd/backport/include/kcl/kcl_amdgpu.h | 45 -------------- drivers/gpu/drm/amd/dkms/config/config.h | 9 --- .../drm_calc_vbltimestamp_from_scanoutpos.m4 | 58 ------------------- .../drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 | 2 - 4 files changed, 114 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_calc_vbltimestamp_from_scanoutpos.m4 diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h index 9b26a06085c84..33bf87c0568bd 100644 --- a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu.h @@ -28,7 +28,6 @@ static inline void kcl_amdgpu_disable_vblank_kms(struct drm_device *dev, unsigne return amdgpu_disable_vblank_kms(drm_crtc); } -#if defined(HAVE_DRM_DRIVER_GET_SCANOUT_POSITION_RETURN_BOOL) static inline bool kcl_amdgpu_get_crtc_scanout_position(struct drm_device *dev, unsigned int pipe, bool in_vblank_irq, int *vpos, int *hpos, ktime_t *stime, ktime_t *etime, @@ -36,57 +35,13 @@ static inline bool kcl_amdgpu_get_crtc_scanout_position(struct drm_device *dev, { return !!amdgpu_display_get_crtc_scanoutpos(dev, pipe, in_vblank_irq, vpos, hpos, stime, etime, mode); } -#else -static inline int kcl_amdgpu_get_crtc_scanout_position(struct drm_device *dev, unsigned int pipe, - unsigned int flags, int *vpos, int *hpos, - ktime_t *stime, ktime_t *etime, - const struct drm_display_mode *mode) -{ - return amdgpu_display_get_crtc_scanoutpos(dev, pipe, flags, vpos, hpos, stime, etime, mode); -} -#endif -#if defined(HAVE_DRM_DRIVER_GET_VBLANK_TIMESTAMP_USE_KTIMER_T_ARG) static inline bool kcl_amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, int *max_error, ktime_t *vblank_time, bool in_vblank_irq) { return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, vblank_time, in_vblank_irq); } -#elif defined(HAVE_DRM_DRIVER_GET_VBLANK_TIMESTAMP_RETURN_BOOL) -static inline bool kcl_amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, - int *max_error, struct timeval *vblank_time, - bool in_vblank_irq) -{ - return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, vblank_time, in_vblank_irq); -} -#else -static inline int kcl_amdgpu_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe, - int *max_error, struct timeval *vblank_time, - unsigned flags) -{ - struct drm_crtc *crtc; - struct amdgpu_device *adev = drm_to_adev(dev); - - if (pipe >= dev->num_crtcs) { - DRM_ERROR("Invalid crtc %u\n", pipe); - return -EINVAL; - } - - /* Get associated drm_crtc: */ - crtc = &adev->mode_info.crtcs[pipe]->base; - if (!crtc) { - /* This can occur on driver load if some component fails to - * initialize completely and driver is unloaded */ - DRM_ERROR("Uninitialized crtc %d\n", pipe); - return -EINVAL; - } - - return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error, - vblank_time, flags, - &crtc->hwmode); -} -#endif /* HAVE_DRM_DRIVER_GET_VBLANK_TIMESTAMP_USE_KTIMER_T_ARG */ #endif /* HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP */ static inline ktime_t kcl_amdgpu_get_vblank_time_ns(struct drm_vblank_crtc *vblank) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 4545e45ab0cd2..d803f4fb4e575 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -463,15 +463,6 @@ /* drm_driver->gem_prime_res_obj() is available */ /* #undef HAVE_DRM_DRIVER_GEM_PRIME_RES_OBJ */ -/* drm_driver->get_scanout_position() return bool */ -/* #undef HAVE_DRM_DRIVER_GET_SCANOUT_POSITION_RETURN_BOOL */ - -/* drm_driver->get_vblank_timestamp() return bool */ -/* #undef HAVE_DRM_DRIVER_GET_VBLANK_TIMESTAMP_RETURN_BOOL */ - -/* drm_calc_vbltimestamp_from_scanoutpos() use ktime_t arg */ -/* #undef HAVE_DRM_DRIVER_GET_VBLANK_TIMESTAMP_USE_KTIMER_T_ARG */ - /* drm_vblank struct use ktime_t for time field */ #define HAVE_DRM_VBLANK_USE_KTIME_T 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_calc_vbltimestamp_from_scanoutpos.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_calc_vbltimestamp_from_scanoutpos.m4 deleted file mode 100644 index 35e273468a27f..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm_calc_vbltimestamp_from_scanoutpos.m4 +++ /dev/null @@ -1,58 +0,0 @@ -dnl # -dnl # commit v4.14-rc3-721-g67680d3c0464 -dnl # drm: vblank: use ktime_t instead of timeval -dnl # -AC_DEFUN([AC_AMDGPU_DRM_CALC_VBLTIMESTAMP_FROM_SCANOUTPOS], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DRMP_H - struct vm_area_struct; - #include - #else - #include - #include - #endif - ], [ - struct drm_driver *kms_driver = NULL; - bool (*get_vblank_timestamp) (struct drm_device *dev, unsigned int pipe, - int *max_error, - ktime_t *vblank_time, - bool in_vblank_irq); - drm_calc_vbltimestamp_from_scanoutpos(NULL, 0, NULL, (ktime_t *)NULL, 0); - kms_driver->get_vblank_timestamp = get_vblank_timestamp; - ], [ - AC_DEFINE(HAVE_DRM_DRIVER_GET_VBLANK_TIMESTAMP_USE_KTIMER_T_ARG, 1, - [drm_calc_vbltimestamp_from_scanoutpos() use ktime_t arg]) - AC_DEFINE(HAVE_DRM_DRIVER_GET_SCANOUT_POSITION_RETURN_BOOL, 1, - [drm_driver->get_scanout_position() return bool]) - ], [ - dnl # - dnl # v4.11-rc7-1902-g1bf6ad622b9b drm/vblank: drop the mode argument from drm_calc_vbltimestamp_from_scanoutpos - dnl # v4.11-rc7-1900-g3fcdcb270936 drm/vblank: Switch to bool in_vblank_irq in get_vblank_timestamp - dnl # v4.11-rc7-1899-gd673c02c4bdb drm/vblank: Switch drm_driver->get_vblank_timestamp to return a bool - dnl # - AC_KERNEL_TRY_COMPILE([ - struct vm_area_struct; - #include - ], [ - struct drm_driver *kms_driver = NULL; - bool (*get_scanout_position) (struct drm_device *dev, unsigned int pipe, - bool in_vblank_irq, int *vpos, int *hpos, - ktime_t *stime, ktime_t *etime, - const struct drm_display_mode *mode); - bool (*get_vblank_timestamp) (struct drm_device *dev, unsigned int pipe, - int *max_error, - struct timeval *vblank_time, - bool in_vblank_irq); - kms_driver->get_scanout_position = get_scanout_position; - kms_driver->get_vblank_timestamp = get_vblank_timestamp; - drm_calc_vbltimestamp_from_scanoutpos(NULL, 0, NULL, (struct timeval *)NULL, 0); - ], [ - AC_DEFINE(HAVE_DRM_DRIVER_GET_SCANOUT_POSITION_RETURN_BOOL, 1, - [drm_driver->get_scanout_position() return bool]) - AC_DEFINE(HAVE_DRM_DRIVER_GET_VBLANK_TIMESTAMP_RETURN_BOOL, 1, - [drm_driver->get_vblank_timestamp() return bool]) - ]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 index 2e19306272912..7d78d8122d1dc 100644 --- a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 @@ -15,8 +15,6 @@ AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP], [ AC_DEFINE(HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP, 1, [struct drm_crtc_funcs->get_vblank_timestamp() is available]) - ],[ - AC_AMDGPU_DRM_CALC_VBLTIMESTAMP_FROM_SCANOUTPOS ]) ]) ]) From 2f0e51f7612f27582d7b21c7e1b30a7e70541fe3 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Fri, 10 Feb 2023 13:35:49 +0800 Subject: [PATCH 0910/1868] drm/amdkcl: kcl-cleanup HAVE_DRM_DRIVER_RELEASE Signed-off-by: Leslie Shi Reviewed-by: Ma Jun --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 12 ---------- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ---- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 4 ---- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2 -- drivers/gpu/drm/amd/backport/kcl_drm_drv.c | 13 ----------- drivers/gpu/drm/amd/dkms/config/config.h | 6 ----- .../gpu/drm/amd/dkms/m4/drm-driver-release.m4 | 22 ------------------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - 8 files changed, 64 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-driver-release.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index d59f4abed2ce2..d62396deb6ff1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -849,11 +849,7 @@ struct amdgpu_fru_info; struct amdgpu_device { struct device *dev; struct pci_dev *pdev; -#ifdef HAVE_DRM_DRIVER_RELEASE struct drm_device ddev; -#else - struct drm_device *ddev; -#endif #ifdef CONFIG_DRM_AMD_ACP struct amdgpu_acp acp; @@ -1210,20 +1206,12 @@ static inline uint32_t amdgpu_ip_version_full(const struct amdgpu_device *adev, static inline struct amdgpu_device *drm_to_adev(struct drm_device *ddev) { -#ifdef HAVE_DRM_DRIVER_RELEASE return container_of(ddev, struct amdgpu_device, ddev); -#else - return ddev->dev_private; -#endif } static inline struct drm_device *adev_to_drm(struct amdgpu_device *adev) { -#ifdef HAVE_DRM_DRIVER_RELEASE return &adev->ddev; -#else - return adev->ddev; -#endif } static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_device *bdev) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index da6ff92099a4d..7ce394921e6e0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -4491,11 +4491,7 @@ static void amdgpu_device_unmap_mmio(struct amdgpu_device *adev) { /* Clear all CPU mappings pointing to this device */ -#ifdef HAVE_DRM_DRIVER_RELEASE unmap_mapping_range(adev->ddev.anon_inode->i_mapping, 0, 0, 1); -#else - unmap_mapping_range(adev->ddev->anon_inode->i_mapping, 0, 0, 1); -#endif /* Unmap all mapped bars - Doorbell, registers and VRAM */ amdgpu_doorbell_fini(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 639b911534cdd..ee5267f916c5e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2473,7 +2473,6 @@ amdgpu_pci_remove(struct pci_dev *pdev) #endif } -#ifdef HAVE_DRM_DRIVER_RELEASE #ifndef HAVE_DRM_DRM_MANAGED_H static void amdgpu_driver_release(struct drm_device *ddev) { @@ -2483,7 +2482,6 @@ static void amdgpu_driver_release(struct drm_device *ddev) kfree(adev); } #endif -#endif static void amdgpu_pci_shutdown(struct pci_dev *pdev) @@ -3050,9 +3048,7 @@ static struct drm_driver amdgpu_kms_driver = { .dumb_create = amdgpu_mode_dumb_create, .dumb_map_offset = amdgpu_mode_dumb_mmap, .fops = &amdgpu_driver_kms_fops, -#ifdef HAVE_DRM_DRIVER_RELEASE .release = &amdgpu_driver_release_kms, -#endif #ifdef CONFIG_PROC_FS .show_fdinfo = amdgpu_show_fdinfo, #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index 8e8ef5a0e541e..8d4e0015c156a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -1519,7 +1519,6 @@ void amdgpu_driver_postclose_kms(struct drm_device *dev, pm_runtime_put_autosuspend(dev->dev); } -#ifdef HAVE_DRM_DRIVER_RELEASE void amdgpu_driver_release_kms(struct drm_device *dev) { struct amdgpu_device *adev = drm_to_adev(dev); @@ -1531,7 +1530,6 @@ void amdgpu_driver_release_kms(struct drm_device *dev) kfree(adev); #endif } -#endif /* * VBlank related functions. diff --git a/drivers/gpu/drm/amd/backport/kcl_drm_drv.c b/drivers/gpu/drm/amd/backport/kcl_drm_drv.c index 9783e852192a5..0d243c59b5f6a 100644 --- a/drivers/gpu/drm/amd/backport/kcl_drm_drv.c +++ b/drivers/gpu/drm/amd/backport/kcl_drm_drv.c @@ -41,7 +41,6 @@ void *__devm_drm_dev_alloc(struct device *parent, struct drm_driver *driver, if (!container) return ERR_PTR(-ENOMEM); -#ifdef HAVE_DRM_DRIVER_RELEASE drm = container + offset; ret = drm_dev_init(drm, driver, parent); if (ret) { @@ -50,12 +49,6 @@ void *__devm_drm_dev_alloc(struct device *parent, struct drm_driver *driver, } #ifdef HAVE_DRM_DRM_MANAGED_H drmm_add_final_kfree(drm, container); -#endif -#else - drm = drm_dev_alloc(driver, parent); - if (IS_ERR(drm)) - return PTR_ERR(drm); - ((struct amdgpu_device*)container)->ddev = drm; #endif drm->dev_private = container; return container; @@ -63,12 +56,6 @@ void *__devm_drm_dev_alloc(struct device *parent, struct drm_driver *driver, void amdkcl_drm_dev_release(struct drm_device *ddev) { -#ifndef HAVE_DRM_DRIVER_RELEASE - if (ddev) { - kfree(drm_to_adev(ddev)); - ddev->dev_private = NULL; - } -#endif drm_dev_put(ddev); } diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index d803f4fb4e575..64344234c1e03 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -466,12 +466,6 @@ /* drm_vblank struct use ktime_t for time field */ #define HAVE_DRM_VBLANK_USE_KTIME_T 1 -/* drm_vblank->time is array */ -/* #undef HAVE_DRM_VBLANK_CRTC_HAS_ARRAY_TIME_FIELD */ - -/* drm_driver->release() is available */ -#define HAVE_DRM_DRIVER_RELEASE 1 - /* Define to 1 if you have the header file. */ /* #undef HAVE_DRM_DRMP_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-driver-release.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-driver-release.m4 deleted file mode 100644 index 8d844a5d7124c..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm-driver-release.m4 +++ /dev/null @@ -1,22 +0,0 @@ -dnl # -dnl # commit v4.10-rc5-1045-gf30c92576af4 -dnl # drm: Provide a driver hook for drm_dev_release() -dnl # -AC_DEFUN([AC_AMDGPU_DRM_DRIVER_RELEASE], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - struct vm_area_struct; - #ifdef HAVE_DRM_DRM_DRV_H - #include - #else - #include - #endif - ],[ - struct drm_driver *ddrv = NULL; - ddrv->release = NULL; - ],[ - AC_DEFINE(HAVE_DRM_DRIVER_RELEASE, 1, - [drm_driver->release() is available]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index edfcf05907149..f15825bac5aff 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -97,7 +97,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS AC_AMDGPU_DRM_EDID AC_AMDGPU_DRM_KMS_HELPER_IS_POLL_WORKER - AC_AMDGPU_DRM_DRIVER_RELEASE AC_AMDGPU_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER AC_AMDGPU_DRM_MODE_IS_420_XXX AC_AMDGPU_DRM_MODE_INIT From 2f5468719d2426a17f7578c57a9688897bd5c93d Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 13 Feb 2023 13:03:04 +0800 Subject: [PATCH 0911/1868] drm/amdkcl: kcl-cleanup HAVE_DRM_DRM_GEM_FRAMEBUFFER_HELPER_H Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 8 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 3 -- drivers/gpu/drm/amd/backport/Makefile | 3 +- drivers/gpu/drm/amd/backport/backport.h | 1 - .../kcl_amdgpu_drm_gem_framebuffer_helper.h | 30 -------------- .../backport/kcl_drm_gem_framebuffer_helper.c | 40 ------------------- drivers/gpu/drm/amd/dkms/config/config.h | 10 ----- 8 files changed, 6 insertions(+), 91 deletions(-) delete mode 100644 drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_gem_framebuffer_helper.h delete mode 100644 drivers/gpu/drm/amd/backport/kcl_drm_gem_framebuffer_helper.c diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 3de34c93d539f..4db6cf12e4684 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1215,7 +1215,7 @@ int amdgpu_display_gem_fb_init(struct drm_device *dev, struct drm_gem_object *obj) { int ret; - kcl_drm_gem_fb_set_obj(&rfb->base, 0, obj); + rfb->base.obj[0] = obj; drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd); ret = amdgpu_display_framebuffer_init(dev, rfb, mode_cmd, obj); @@ -1229,7 +1229,7 @@ int amdgpu_display_gem_fb_init(struct drm_device *dev, return 0; err: drm_dbg_kms(dev, "Failed to init gem fb: %d\n", ret); - kcl_drm_gem_fb_set_obj(&rfb->base, 0, NULL); + rfb->base.obj[0] = NULL; return ret; } @@ -1241,7 +1241,7 @@ static int amdgpu_display_gem_fb_verify_and_init(struct drm_device *dev, { int ret; - kcl_drm_gem_fb_set_obj(&rfb->base, 0, obj); + rfb->base.obj[0] = obj; drm_helper_mode_fill_fb_struct(dev, &rfb->base, mode_cmd); #ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED @@ -1273,7 +1273,7 @@ static int amdgpu_display_gem_fb_verify_and_init(struct drm_device *dev, return 0; err: drm_dbg_kms(dev, "Failed to verify and init gem fb: %d\n", ret); - kcl_drm_gem_fb_set_obj(&rfb->base, 0, NULL); + rfb->base.obj[0] = NULL; return ret; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c index 7aee5aeeecc91..1d531c41fa5e6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c @@ -314,7 +314,7 @@ static int amdgpu_fbdev_destroy(struct drm_device *dev, struct amdgpu_fbdev *rfb drm_gem_object_put(obj); #endif amdgpufb_destroy_pinned_object(obj); - kcl_drm_gem_fb_set_obj(&rfb->base, 0, NULL); + rfb->base.obj[0] = NULL; drm_framebuffer_unregister_private(&rfb->base); drm_framebuffer_cleanup(&rfb->base); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index 4776e7179b944..c5b3cce030dc0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -303,9 +303,6 @@ struct amdgpu_display_funcs { struct amdgpu_framebuffer { struct drm_framebuffer base; -#ifndef HAVE_DRM_DRM_GEM_FRAMEBUFFER_HELPER_H - struct drm_gem_object *obj; -#endif uint64_t tiling_flags; bool tmz_surface; diff --git a/drivers/gpu/drm/amd/backport/Makefile b/drivers/gpu/drm/amd/backport/Makefile index cba90812f73b2..335363b5b8ee5 100644 --- a/drivers/gpu/drm/amd/backport/Makefile +++ b/drivers/gpu/drm/amd/backport/Makefile @@ -1,7 +1,6 @@ # SPDX-License-Identifier: MIT BACKPORT_OBJS := kcl_drm_drv.o kcl_drm_gem_ttm_helper.o \ - kcl_drm_gem_framebuffer_helper.o kcl_drm_gem.o \ - kcl_drm_modeset_helper.o + kcl_drm_gem.o kcl_drm_modeset_helper.o amdgpu-y += $(addprefix ../backport/,$(BACKPORT_OBJS)) diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index aa1fbf2145202..3200b99717ce1 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -71,7 +71,6 @@ #include #include #include "kcl/kcl_amdgpu_drm_fb_helper.h" -#include "kcl/kcl_amdgpu_drm_gem_framebuffer_helper.h" #include "kcl/kcl_amdgpu.h" #include "kcl/kcl_amdgpu_drm_drv.h" #include "kcl/kcl_amdgpu_drm_gem.h" diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_gem_framebuffer_helper.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_gem_framebuffer_helper.h deleted file mode 100644 index bbd3326b824bf..0000000000000 --- a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_gem_framebuffer_helper.h +++ /dev/null @@ -1,30 +0,0 @@ -#ifndef __AMDGPU_BACKPORT_KCL_AMDGPU_DRM_GEM_FRAMEBUFFER_HELPER_H__ -#define __AMDGPU_BACKPORT_KCL_AMDGPU_DRM_GEM_FRAMEBUFFER_HELPER_H__ - -#include -#include "amdgpu.h" - -static inline -void kcl_drm_gem_fb_set_obj(struct drm_framebuffer *fb, int index, struct drm_gem_object *obj) -{ -#ifdef HAVE_DRM_DRM_GEM_FRAMEBUFFER_HELPER_H - if (fb) - fb->obj[index] = obj; -#else - struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb); - (void)index; /* for compile un-used warning */ - if (afb) - afb->obj = obj; -#endif -} - -#ifndef HAVE_DRM_DRM_GEM_FRAMEBUFFER_HELPER_H -/* Copied from include/drm/drm_gem_framebuffer_helper.h */ -struct drm_gem_object *drm_gem_fb_get_obj(struct drm_framebuffer *fb, - unsigned int plane); -void drm_gem_fb_destroy(struct drm_framebuffer *fb); -int drm_gem_fb_create_handle(struct drm_framebuffer *fb, struct drm_file *file, - unsigned int *handle); -#endif - -#endif diff --git a/drivers/gpu/drm/amd/backport/kcl_drm_gem_framebuffer_helper.c b/drivers/gpu/drm/amd/backport/kcl_drm_gem_framebuffer_helper.c deleted file mode 100644 index 1f68cf8bbe2b3..0000000000000 --- a/drivers/gpu/drm/amd/backport/kcl_drm_gem_framebuffer_helper.c +++ /dev/null @@ -1,40 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-or-later -/* - * drm gem framebuffer helper functions - * - * Copyright (C) 2017 Noralf Trønnes - */ - -#include - -/* Copied from drivers/gpu/drm/drm_gem_framebuffer_helper.c and modified for KCL */ -#ifndef HAVE_DRM_DRM_GEM_FRAMEBUFFER_HELPER_H -struct drm_gem_object *drm_gem_fb_get_obj(struct drm_framebuffer *fb, - unsigned int plane) -{ - struct amdgpu_framebuffer *afb = to_amdgpu_framebuffer(fb); - (void)plane; /* for compile un-used warning */ - if (afb) - return afb->obj; - else - return NULL; -} - -void drm_gem_fb_destroy(struct drm_framebuffer *fb) -{ - struct amdgpu_framebuffer *amdgpu_fb = to_amdgpu_framebuffer(fb); - - drm_gem_object_put(amdgpu_fb->obj); - - drm_framebuffer_cleanup(fb); - kfree(fb); -} - -int drm_gem_fb_create_handle(struct drm_framebuffer *fb, struct drm_file *file, - unsigned int *handle) -{ - struct amdgpu_framebuffer *amdgpu_fb = to_amdgpu_framebuffer(fb); - - return drm_gem_handle_create(file, amdgpu_fb->obj, handle); -} -#endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 64344234c1e03..74990389e087b 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -496,16 +496,6 @@ /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_DRV_H 1 -/* Define to 1 if you have the header file. */ -#define HAVE_DRM_DRM_ENCODER_H 1 - -/* Define to 1 if you have the header file. */ -#define HAVE_DRM_DRM_FILE_H 1 - -/* Define to 1 if you have the header file. - */ -#define HAVE_DRM_DRM_GEM_FRAMEBUFFER_HELPER_H 1 - /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_HDCP_H 1 From aac4ccd9578e5d9c6c7f7d44c5ff7e96feafb6ba Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 15 Feb 2023 10:01:02 +0800 Subject: [PATCH 0912/1868] drm/amdkcl: kcl-cleanup HAVE_UAPI_LINUX_SCHED_TYPES_H Change-Id: I48aec8289333a37f5cdce644fc3bdeef9e292872 Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 3 --- drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 | 6 ------ include/kcl/header/uapi/linux/sched/types.h | 9 --------- 3 files changed, 18 deletions(-) delete mode 100644 include/kcl/header/uapi/linux/sched/types.h diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 74990389e087b..556c733f04b32 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1195,9 +1195,6 @@ /* __poll_t is available */ #define HAVE_TYPE__POLL_T 1 -/* Define to 1 if you have the header file. */ -#define HAVE_UAPI_LINUX_SCHED_TYPES_H 1 - /* vga_client_register() don't pass a cookie */ #define HAVE_VGA_CLIENT_REGISTER_NOT_PASS_COOKIE 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 index c90bc2c7d2fd7..2c9f72c524583 100644 --- a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 @@ -25,12 +25,6 @@ AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ dnl # AC_KERNEL_CHECK_HEADERS([asm/fpu/api.h]) - dnl # - dnl # commit 607ca46e97a1b6594b29647d98a32d545c24bdff - dnl # UAPI: (Scripted) Disintegrate include/linux - dnl # - AC_KERNEL_CHECK_HEADERS([uapi/linux/sched/types.h]) - dnl # dnl # v4.19-rc6-7-ga3f8a30f3f00 dnl # Compiler Attributes: use feature checks instead of version checks diff --git a/include/kcl/header/uapi/linux/sched/types.h b/include/kcl/header/uapi/linux/sched/types.h deleted file mode 100644 index 871f2abf23d37..0000000000000 --- a/include/kcl/header/uapi/linux/sched/types.h +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -#ifndef _KCL_HEADER_UAPI_LINUX_SCHED_TYPES_H_H_ -#define _KCL_HEADER_UAPI_LINUX_SCHED_TYPES_H_H_ - -#ifdef HAVE_UAPI_LINUX_SCHED_TYPES_H -#include_next -#endif - -#endif From e07f02a4fe28e637481045d15b1bd7bc5d3d34df Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 15 Feb 2023 10:11:01 +0800 Subject: [PATCH 0913/1868] drm/amdkcl: kcl-cleanup HAVE_TTM_SG_TT_INIT Change-Id: Ib30a80618a524ae9f1b68ce8fdd7a73c87898204 Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 3 --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - drivers/gpu/drm/amd/dkms/m4/ttm_sg_tt_init.m4 | 11 ----------- drivers/gpu/drm/ttm/ttm_tt.c | 5 +---- include/kcl/kcl_drm_prime.h | 12 ------------ 5 files changed, 1 insertion(+), 31 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/ttm_sg_tt_init.m4 diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 556c733f04b32..0b324013e6f24 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1189,9 +1189,6 @@ /* interval_tree_insert have struct rb_root_cached */ #define HAVE_TREE_INSERT_HAVE_RB_ROOT_CACHED 1 -/* ttm_sg_tt_init() is available */ -#define HAVE_TTM_SG_TT_INIT 1 - /* __poll_t is available */ #define HAVE_TYPE__POLL_T 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index f15825bac5aff..a93ca76b772f9 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -50,7 +50,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_MM_RELEASE_PAGES AC_AMDGPU_SCHED_SET_FIFO_LOW AC_AMDGPU_DMA_RESV - AC_AMDGPU_TTM_SG_TT_INIT AC_AMDGPU_TTM_BUFFER_OBJECT AC_AMDGPU_DEVCGROUP_CHECK_PERMISSION AC_AMDGPU_HMM diff --git a/drivers/gpu/drm/amd/dkms/m4/ttm_sg_tt_init.m4 b/drivers/gpu/drm/amd/dkms/m4/ttm_sg_tt_init.m4 deleted file mode 100644 index 5cbf835eaf401..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/ttm_sg_tt_init.m4 +++ /dev/null @@ -1,11 +0,0 @@ -dnl # -dnl # v4.16-rc1-1232-g75a57669cbc8 drm/ttm: add ttm_sg_tt_init -dnl # v4.16-rc1-409-g186ca446aea1 drm/prime: make the pages array optional for drm_prime_sg_to_page_addr_arrays -dnl # -AC_DEFUN([AC_AMDGPU_TTM_SG_TT_INIT], [ - AC_KERNEL_DO_BACKGROUND([ - AS_IF([grep -q ttm_sg_tt_init $LINUX/include/drm/ttm/ttm_tt.h > /dev/null 2>&1], [ - AC_DEFINE(HAVE_TTM_SG_TT_INIT, 1, [ttm_sg_tt_init() is available]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c index 63646d0ebfaed..107b7b546c347 100644 --- a/drivers/gpu/drm/ttm/ttm_tt.c +++ b/drivers/gpu/drm/ttm/ttm_tt.c @@ -203,14 +203,11 @@ int ttm_sg_tt_init(struct ttm_tt *ttm, struct ttm_buffer_object *bo, ttm_tt_init_fields(ttm, bo, page_flags, caching, 0); -#ifndef HAVE_TTM_SG_TT_INIT - ret = ttm_dma_tt_alloc_page_directory(ttm); -#else if (page_flags & TTM_TT_FLAG_EXTERNAL) ret = ttm_sg_tt_alloc_page_directory(ttm); else ret = ttm_dma_tt_alloc_page_directory(ttm); -#endif + if (ret) { pr_err("Failed allocating page table\n"); return -ENOMEM; diff --git a/include/kcl/kcl_drm_prime.h b/include/kcl/kcl_drm_prime.h index 2c5e972520576..c55e8d05c0318 100644 --- a/include/kcl/kcl_drm_prime.h +++ b/include/kcl/kcl_drm_prime.h @@ -12,19 +12,7 @@ static inline int drm_prime_sg_to_dma_addr_array(struct sg_table *sgt, dma_addr_t *addrs, int max_entries) { -#ifdef HAVE_TTM_SG_TT_INIT return drm_prime_sg_to_page_addr_arrays(sgt, NULL, addrs, max_entries); -#else - /* - * the page array stands right next to dma address array, - * so get the page array pointer directly by max_entries offset - * refer to ttm_sg_tt_init() for initial array allocation and - * c67e62790f5c drm/prime: split array import functions v4 for - * the change to drm_prime_sg_to_page_addr_arrays() - */ - struct page **pages = (void*)((unsigned long)addrs - max_entries*sizeof(dma_addr_t)); - return drm_prime_sg_to_page_addr_arrays(sgt, pages, addrs, max_entries); -#endif } #endif /* HAVE_DRM_PRIME_SG_TO_DMA_ADDR_ARRAY */ #endif From fadf32a7a09e40d8a3cb9631d3f0e9ddbbaee236 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 15 Feb 2023 10:12:58 +0800 Subject: [PATCH 0914/1868] drm/amdkcl: kcl-cleanup HAVE_TIMER_SETUP Change-Id: Ib4c13dbfe337150f6bedb3c147692d7bbc04576b Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 14 -------------- drivers/gpu/drm/amd/dkms/config/config.h | 3 --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - drivers/gpu/drm/amd/dkms/m4/timer-setup.m4 | 16 ---------------- 4 files changed, 34 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/timer-setup.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index 5f4b3f933bc68..b64821da99e84 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c @@ -320,7 +320,6 @@ bool amdgpu_fence_process(struct amdgpu_ring *ring) * * Checks for fence activity. */ -#if defined(HAVE_TIMER_SETUP) static void amdgpu_fence_fallback(struct timer_list *t) { struct amdgpu_ring *ring = from_timer(ring, t, @@ -329,14 +328,6 @@ static void amdgpu_fence_fallback(struct timer_list *t) if (amdgpu_fence_process(ring)) DRM_WARN("Fence fallback timer expired on ring %s\n", ring->name); } -#else -static void amdgpu_fence_fallback(unsigned long arg) -{ - struct amdgpu_ring *ring = (void *)arg; - - amdgpu_fence_process(ring); -} -#endif /** * amdgpu_fence_wait_empty - wait for all fences to signal @@ -528,12 +519,7 @@ int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring) atomic_set(&ring->fence_drv.last_seq, 0); ring->fence_drv.initialized = false; -#if defined(HAVE_TIMER_SETUP) timer_setup(&ring->fence_drv.fallback_timer, amdgpu_fence_fallback, 0); -#else - setup_timer(&ring->fence_drv.fallback_timer, amdgpu_fence_fallback, - (unsigned long)ring); -#endif ring->fence_drv.num_fences_mask = ring->num_hw_submission * 2 - 1; spin_lock_init(&ring->fence_drv.lock); diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 0b324013e6f24..7f5425d85e926 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1183,9 +1183,6 @@ /* sysfs_emit() and sysfs_emit_at() are available */ #define HAVE_SYSFS_EMIT 1 -/* timer_setup() is available */ -#define HAVE_TIMER_SETUP 1 - /* interval_tree_insert have struct rb_root_cached */ #define HAVE_TREE_INSERT_HAVE_RB_ROOT_CACHED 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index a93ca76b772f9..d13b6b645bec7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -60,7 +60,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_GET_USER_PAGES AC_AMDGPU_DMA_BUF AC_AMDGPU_LIST_FOR_EACH_ENTRY - AC_AMDGPU_TIMER_SETUP AC_AMDGPU_AMD_IOMMU_PC_SUPPORTED AC_AMDGPU_AMD_IOMMU_INVALIDATE_CTX AC_AMDGPU_DEV_PAGEMAP diff --git a/drivers/gpu/drm/amd/dkms/m4/timer-setup.m4 b/drivers/gpu/drm/amd/dkms/m4/timer-setup.m4 deleted file mode 100644 index 63a4498b7476a..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/timer-setup.m4 +++ /dev/null @@ -1,16 +0,0 @@ -dnl # -dnl # timer_setup is available -dnl # -dnl # -AC_DEFUN([AC_AMDGPU_TIMER_SETUP], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ],[ - timer_setup(NULL, NULL, 0); - ],[ - AC_DEFINE(HAVE_TIMER_SETUP, 1, - [timer_setup() is available]) - ]) - ]) -]) From 38de5c6bc157d14d9c75a05391363414ea60ff97 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 15 Feb 2023 11:32:01 +0800 Subject: [PATCH 0915/1868] drm/amdkcl: kcl-cleanup HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_ASYNC_CHECK Change-Id: I081d9f81f01145d5b7cf627acae3a621c3ac1d6a Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- .../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 6 ------ drivers/gpu/drm/amd/dkms/config/config.h | 3 --- .../dkms/m4/struct_drm_plane_helper_funcs.m4 | 19 ------------------- 3 files changed, 28 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 1770173e13df1..113de4559a861 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -1367,7 +1367,6 @@ static int amdgpu_dm_plane_atomic_check(struct drm_plane *plane, return -EINVAL; } -#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_ASYNC_CHECK static int amdgpu_dm_plane_atomic_async_check(struct drm_plane *plane, #ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS struct drm_atomic_state *state) @@ -1392,7 +1391,6 @@ static int amdgpu_dm_plane_atomic_async_check(struct drm_plane *plane, return 0; } -#endif int amdgpu_dm_plane_get_cursor_position(struct drm_plane *plane, struct drm_crtc *crtc, struct dc_cursor_position *position) @@ -1508,7 +1506,6 @@ void amdgpu_dm_plane_handle_cursor_update(struct drm_plane *plane, } } -#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_ASYNC_CHECK static void amdgpu_dm_plane_atomic_async_update(struct drm_plane *plane, #ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS struct drm_atomic_state *state) @@ -1541,15 +1538,12 @@ static void amdgpu_dm_plane_atomic_async_update(struct drm_plane *plane, amdgpu_dm_plane_handle_cursor_update(plane, old_state); } -#endif static const struct drm_plane_helper_funcs dm_plane_helper_funcs = { .prepare_fb = amdgpu_dm_plane_helper_prepare_fb, .cleanup_fb = amdgpu_dm_plane_helper_cleanup_fb, .atomic_check = amdgpu_dm_plane_atomic_check, -#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_ASYNC_CHECK .atomic_async_check = amdgpu_dm_plane_atomic_async_check, .atomic_async_update = amdgpu_dm_plane_atomic_async_update -#endif }; static void amdgpu_dm_plane_drm_plane_reset(struct drm_plane *plane) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 7f5425d85e926..d74295d3e3b2c 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1152,9 +1152,6 @@ /* drm_pending_vblank_event->sequence is available */ #define HAVE_STRUCT_DRM_PENDING_VBLANK_EVENT_SEQUENCE 1 -/* drm_plane_helper_funcs->atomic_async_check() is available */ -#define HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_ASYNC_CHECK 1 - /* drm_plane_helper_funcs->atomic_check() second param wants drm_atomic_state arg */ #define HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_plane_helper_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_plane_helper_funcs.m4 index 59fe64ed86c35..495dd9ef97c12 100644 --- a/drivers/gpu/drm/amd/dkms/m4/struct_drm_plane_helper_funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_plane_helper_funcs.m4 @@ -1,22 +1,3 @@ -dnl # -dnl # v4.12-rc7-1335-gfef9df8b5945 -dnl # drm/atomic: initial support for asynchronous plane update -dnl # -AC_DEFUN([AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - struct drm_plane_helper_funcs *funcs = NULL; - funcs->atomic_async_check(NULL, NULL); - funcs->atomic_async_update(NULL, NULL); - ], [ - AC_DEFINE(HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_ASYNC_CHECK, 1, - [drm_plane_helper_funcs->atomic_async_check() is available]) - ]) - ]) -]) - dnl # commit v5.11-rc2-701-g7c11b99a8e58 dnl # drm/atomic: Pass the full state to planes atomic_check AC_DEFUN([AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS], [ From 31e1d53b10c43209f07fa655d0a9ce27db83a818 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 15 Feb 2023 14:20:50 +0800 Subject: [PATCH 0916/1868] drm/amdkcl: kcl-cleanup HAVE_STRUCT_DRM_CRTC_FUNCS_SET_CONFIG_CTX Change-Id: I6117793d101c0b2321622d54dcbc3e1473b26efd Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 9 --------- drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 4 ---- drivers/gpu/drm/amd/dkms/config/config.h | 3 --- .../drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 | 19 ------------------- 4 files changed, 35 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 4db6cf12e4684..30355ac19d4dd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -307,13 +307,8 @@ int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc, return r; } - -#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_SET_CONFIG_CTX int amdgpu_display_crtc_set_config(struct drm_mode_set *set, struct drm_modeset_acquire_ctx *ctx) -#else -int amdgpu_display_crtc_set_config(struct drm_mode_set *set) -#endif { struct drm_device *dev; struct amdgpu_device *adev; @@ -330,11 +325,7 @@ int amdgpu_display_crtc_set_config(struct drm_mode_set *set) if (ret < 0) goto out; -#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_SET_CONFIG_CTX ret = drm_crtc_helper_set_config(set, ctx); -#else - ret = drm_crtc_helper_set_config(set); -#endif list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) if (crtc->enabled) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index c5b3cce030dc0..b4b19cae03c71 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -737,12 +737,8 @@ int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int bpp, bool tile /* amdgpu_display.c */ void amdgpu_display_print_display_setup(struct drm_device *dev); int amdgpu_display_modeset_create_props(struct amdgpu_device *adev); -#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_SET_CONFIG_CTX int amdgpu_display_crtc_set_config(struct drm_mode_set *set, struct drm_modeset_acquire_ctx *ctx); -#else -int amdgpu_display_crtc_set_config(struct drm_mode_set *set); -#endif int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc, struct drm_framebuffer *fb, diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index d74295d3e3b2c..7309b368da61a 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1134,9 +1134,6 @@ /* drm_crtc_funcs->{get,verify}_crc_sources() is available */ #define HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VERIFY_CRC_SOURCES 1 -/* drm_crtc_funcs->set_config() wants ctx parameter */ -#define HAVE_STRUCT_DRM_CRTC_FUNCS_SET_CONFIG_CTX 1 - /* struct drm_crtc_state->async_flip is available */ #define HAVE_STRUCT_DRM_CRTC_STATE_ASYNC_FLIP 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 index 7d78d8122d1dc..facfeb5ef02a9 100644 --- a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 @@ -19,24 +19,6 @@ AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP], [ ]) ]) -dnl # -dnl # v4.11-rc3-950-ga4eff9aa6db8 -dnl # drm: Add acquire ctx parameter to ->set_config -dnl # -AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_SET_CONFIG], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - struct drm_crtc_funcs *funcs = NULL; - funcs->set_config(NULL, NULL); - ], [ - AC_DEFINE(HAVE_STRUCT_DRM_CRTC_FUNCS_SET_CONFIG_CTX, 1, - [drm_crtc_funcs->set_config() wants ctx parameter]) - ]) - ]) -]) - dnl # dnl # commit v4.10-rc5-1070-g84e354839b15 dnl # drm: add vblank hooks to struct drm_crtc_funcs @@ -92,6 +74,5 @@ AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS], [ AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_ENABLE_VBLANK AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GET_VERIFY_CRC_SOURCES - AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_SET_CONFIG AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL ]) From d0d9c62ef42e31af03ff64a22bc76946ee2b06cb Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 16 Feb 2023 13:40:47 +0800 Subject: [PATCH 0917/1868] drm/amdkcl: kcl-cleanup HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VERIFY_CRC_SOURCES Change-Id: Ie8e3067682507105f6e50038cc539614b5dcdab0 Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 -- .../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c | 4 ---- .../drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h | 2 -- .../amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 2 -- drivers/gpu/drm/amd/dkms/config/config.h | 3 --- .../drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 | 22 ------------------- 6 files changed, 35 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index cfb7886fd27f1..c0c33370cd46e 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -666,9 +666,7 @@ static void dm_crtc_high_irq(void *interrupt_params) * Following stuff must happen at start of vblank, for crc * computation and below-the-range btr support in vrr mode. */ -#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VERIFY_CRC_SOURCES amdgpu_dm_crtc_handle_crc_irq(&acrtc->base); -#endif /* BTR updates need to happen before VUPDATE on Vega and above. */ if (adev->family < AMDGPU_FAMILY_AI) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c index 741e2526ec127..f936a35fa9ebb 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c @@ -31,7 +31,6 @@ #include "dc.h" #include "amdgpu_securedisplay.h" -#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VERIFY_CRC_SOURCES static const char *const pipe_crc_sources[] = { "none", "crtc", @@ -40,7 +39,6 @@ static const char *const pipe_crc_sources[] = { "dprx dither", "auto", }; -#endif static enum amdgpu_dm_pipe_crc_source dm_parse_crc_source(const char *source) { @@ -77,7 +75,6 @@ static bool dm_need_crc_dither(enum amdgpu_dm_pipe_crc_source src) (src == AMDGPU_DM_PIPE_CRC_SOURCE_NONE); } -#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VERIFY_CRC_SOURCES const char *const *amdgpu_dm_crtc_get_crc_sources(struct drm_crtc *crtc, size_t *count) { @@ -211,7 +208,6 @@ amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc, const char *src_name, *values_cnt = 3; return 0; } -#endif int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc, struct dm_crtc_state *dm_crtc_state, diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h index ce48316355cac..1682659bc8036 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.h @@ -80,13 +80,11 @@ int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc, enum amdgpu_dm_pipe_crc_source source); int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name); -#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VERIFY_CRC_SOURCES int amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc, const char *src_name, size_t *values_cnt); const char *const *amdgpu_dm_crtc_get_crc_sources(struct drm_crtc *crtc, size_t *count); -#endif /* HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VERIFY_CRC_SOURCES */ void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc); #else #define amdgpu_dm_crtc_set_crc_source NULL diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c index ff25b4b928ee6..d05483222b72e 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c @@ -550,10 +550,8 @@ static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = { .atomic_duplicate_state = amdgpu_dm_crtc_duplicate_state, .atomic_destroy_state = amdgpu_dm_crtc_destroy_state, .set_crc_source = amdgpu_dm_crtc_set_crc_source, -#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VERIFY_CRC_SOURCES .verify_crc_source = amdgpu_dm_crtc_verify_crc_source, .get_crc_sources = amdgpu_dm_crtc_get_crc_sources, -#endif #ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_ENABLE_VBLANK .enable_vblank = amdgpu_dm_crtc_enable_vblank, .disable_vblank = amdgpu_dm_crtc_disable_vblank, diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 7309b368da61a..9fd8635409833 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1131,9 +1131,6 @@ /* struct drm_crtc_funcs->get_vblank_timestamp() is available */ #define HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP 1 -/* drm_crtc_funcs->{get,verify}_crc_sources() is available */ -#define HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VERIFY_CRC_SOURCES 1 - /* struct drm_crtc_state->async_flip is available */ #define HAVE_STRUCT_DRM_CRTC_STATE_ASYNC_FLIP 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 index facfeb5ef02a9..747ec89036bd4 100644 --- a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 @@ -37,27 +37,6 @@ AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_ENABLE_VBLANK], [ ]) ]) -dnl # -dnl # v5.2-rc5-2034-g8fb843d179a6 drm/amd/display: add functionality to get pipe CRC source. -dnl # v4.18-rc3-759-g3b3b8448ebd1 drm/amdgpu_dm/crc: Implement verify_crc_source callback -dnl # v4.18-rc3-757-g4396551e9cf3 drm: crc: Introduce get_crc_sources callback -dnl # v4.18-rc3-756-gd5cc15a0c66e drm: crc: Introduce verify_crc_source callback -dnl # -AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GET_VERIFY_CRC_SOURCES], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - struct drm_crtc_funcs *crtc_funcs = NULL; - crtc_funcs->get_crc_sources(NULL, NULL); - crtc_funcs->verify_crc_source(NULL, NULL, NULL); - ], [ - AC_DEFINE(HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VERIFY_CRC_SOURCES, 1, [ - drm_crtc_funcs->{get,verify}_crc_sources() is available]) - ]) - ]) -]) - dnl # dnl # v5.10-1961-g6ca2ab8086af drm: automatic legacy gamma support dnl # @@ -73,6 +52,5 @@ AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL], [ AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS], [ AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_ENABLE_VBLANK - AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GET_VERIFY_CRC_SOURCES AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL ]) From 02b7a369328faa1bdee2ce6f0bcb26d587fdaa18 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 16 Feb 2023 13:42:14 +0800 Subject: [PATCH 0918/1868] drm/amdkcl: kcl-cleanup HAVE_STRUCT_DRM_CRTC_FUNCS_ENABLE_VBLANK Change-Id: If26eecc53b7d105cd064e69ad7a54f93b1f4f267 Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- .../amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 2 -- drivers/gpu/drm/amd/dkms/config/config.h | 3 --- .../drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 | 19 ------------------- 3 files changed, 24 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c index d05483222b72e..2368505c3d9ae 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c @@ -552,10 +552,8 @@ static const struct drm_crtc_funcs amdgpu_dm_crtc_funcs = { .set_crc_source = amdgpu_dm_crtc_set_crc_source, .verify_crc_source = amdgpu_dm_crtc_verify_crc_source, .get_crc_sources = amdgpu_dm_crtc_get_crc_sources, -#ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_ENABLE_VBLANK .enable_vblank = amdgpu_dm_crtc_enable_vblank, .disable_vblank = amdgpu_dm_crtc_disable_vblank, -#endif #ifdef HAVE_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP .get_vblank_counter = amdgpu_get_vblank_counter_kms, .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp, diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 9fd8635409833..e3ad7c93f2516 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1122,9 +1122,6 @@ /* drm_connector->ycbcr_420_allowed is available */ #define HAVE_STRUCT_DRM_CONNECTOR_YCBCR_420_ALLOWED 1 -/* drm_crtc_funcs->enable_vblank() is available */ -#define HAVE_STRUCT_DRM_CRTC_FUNCS_ENABLE_VBLANK 1 - /* HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL is available */ #define HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 index 747ec89036bd4..8ad24bc40f5fb 100644 --- a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 @@ -19,24 +19,6 @@ AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP], [ ]) ]) -dnl # -dnl # commit v4.10-rc5-1070-g84e354839b15 -dnl # drm: add vblank hooks to struct drm_crtc_funcs -dnl # -AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_ENABLE_VBLANK], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - struct drm_crtc_funcs *crtc_funcs = NULL; - crtc_funcs->enable_vblank(NULL); - ], [ - AC_DEFINE(HAVE_STRUCT_DRM_CRTC_FUNCS_ENABLE_VBLANK, 1, [ - drm_crtc_funcs->enable_vblank() is available]) - ]) - ]) -]) - dnl # dnl # v5.10-1961-g6ca2ab8086af drm: automatic legacy gamma support dnl # @@ -51,6 +33,5 @@ AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL], [ AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS], [ AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GET_VBLANK_TIMESTAMP - AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_ENABLE_VBLANK AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL ]) From c3a931362d5df5379f1c907aa12297a0f2dc5cc0 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 16 Feb 2023 13:44:58 +0800 Subject: [PATCH 0919/1868] drm/amdkcl: kcl-cleanup HAVE_STRSCPY Change-Id: I8eb0e883ffb1241a4fcea40aa02d0b7dea9b4bdf Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 11 +---------- drivers/gpu/drm/amd/dkms/config/config.h | 3 --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - drivers/gpu/drm/amd/dkms/m4/strscpy.m4 | 17 ----------------- 4 files changed, 1 insertion(+), 31 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/strscpy.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index c0c33370cd46e..5a4093f2569ff 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -6156,15 +6156,9 @@ static void fill_audio_info(struct audio_info *audio_info, cea_revision = drm_connector->display_info.cea_rev; -#if !defined(HAVE_STRSCPY) - strncpy(audio_info->display_name, - edid_caps->display_name, - AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS - 1); -#else strscpy(audio_info->display_name, edid_caps->display_name, AUDIO_INFO_DISPLAY_NAME_SIZE_IN_CHARS); -#endif if (cea_revision >= 3) { audio_info->mode_count = edid_caps->audio_mode_count; @@ -7872,11 +7866,8 @@ amdgpu_dm_create_common_mode(struct drm_encoder *encoder, mode->hdisplay = hdisplay; mode->vdisplay = vdisplay; mode->type &= ~DRM_MODE_TYPE_PREFERRED; -#if !defined(HAVE_STRSCPY) - strncpy(mode->name, name, DRM_DISPLAY_MODE_LEN); -#else + strscpy(mode->name, name, DRM_DISPLAY_MODE_LEN); -#endif return mode; diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index e3ad7c93f2516..9e7fd880f9515 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1092,9 +1092,6 @@ /* is_smca_umc_v2() is available */ /* #undef HAVE_SMCA_UMC_V2 */ -/* strscpy() is available */ -#define HAVE_STRSCPY 1 - /* struct dma_buf_ops->allow_peer2peer is available */ #define HAVE_STRUCT_DMA_BUF_OPS_ALLOW_PEER2PEER 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index d13b6b645bec7..7c137d8772f94 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -99,7 +99,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_MODE_IS_420_XXX AC_AMDGPU_DRM_MODE_INIT AC_AMDGPU_DRM_FRAMEBUFFER_FORMAT - AC_AMDGPU_STRSCPY AC_AMDGPU_DRM_DP_MST_TOPOLOGY AC_AMDGPU_DRM_HDMI_VENDOR_INFOFRAME_FROM_DISPLAY_MODE AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS diff --git a/drivers/gpu/drm/amd/dkms/m4/strscpy.m4 b/drivers/gpu/drm/amd/dkms/m4/strscpy.m4 deleted file mode 100644 index 35ace5a7694c7..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/strscpy.m4 +++ /dev/null @@ -1,17 +0,0 @@ -dnl # -dnl # commit 30035e45753b708e7d47a98398500ca005e02b86 -dnl # Author: Chris Metcalf -dnl # Date: Wed Apr 29 12:52:04 2015 -0400 -dnl # string: provide strscpy() -dnl # -AC_DEFUN([AC_AMDGPU_STRSCPY], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include - ], [ - strscpy(NULL, NULL, 8); - ], [strscpy], [lib/string.c], [ - AC_DEFINE(HAVE_STRSCPY, 1, [strscpy() is available]) - ]) - ]) -]) From a43761eb5428b907472e621cf05acbd8858e1e6c Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 16 Feb 2023 15:14:08 +0800 Subject: [PATCH 0920/1868] drm/amdkcl: kcl-cleanup HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS Signed-off-by: Leslie Shi Reviewed-by: Ma Jun --- drivers/gpu/drm/amd/dkms/config/config.h | 3 -- .../drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 | 30 +++---------------- .../backport/kcl_drm_dp_mst_helper_backport.h | 2 -- 3 files changed, 4 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 9e7fd880f9515..c9d82c0d6ccd7 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -361,9 +361,6 @@ /* drm_dp_mst_atomic_wait_for_dependencies() is available */ /* #undef HAVE_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES */ -/* drm_dp_atomic_find_vcpi_slots() is available */ -#define HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS 1 - /* drm_dp_atomic_release_time_slots() is available */ /* #undef HAVE_DRM_DP_ATOMIC_RELEASE_TIME_SLOTS */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 index f19d5bf4ea976..c89bcdbf10edd 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 @@ -4,7 +4,7 @@ dnl # drm/dp: Add DP MST helpers to atomically find and release vcpi slots dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE_SYMBOL([ + AC_KERNEL_TRY_COMPILE([ #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) #include #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) @@ -14,32 +14,10 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS], [ #endif ], [ int retval; - retval = drm_dp_atomic_find_vcpi_slots(NULL, NULL, NULL, 0); - ], [drm_dp_atomic_find_vcpi_slots], [drivers/gpu/drm/drm_dp_mst_topology.c], [ - AC_DEFINE(HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS, 1, - [drm_dp_atomic_find_vcpi_slots() is available]) + retval = drm_dp_atomic_find_vcpi_slots(NULL, NULL, NULL, 0, 0); ], [ - dnl # - dnl # commit dad1c2499a8f6d7ee01db8148f05ebba73cc41bd - dnl # drm/dp_mst: Manually overwrite PBN divider for calculating timeslots - dnl # - AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else - #include - #endif - ], [ - int retval; - retval = drm_dp_atomic_find_vcpi_slots(NULL, NULL, NULL, 0, 0); - ], [ - AC_DEFINE(HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS_5ARGS, 1, - [drm_dp_atomic_find_vcpi_slots() wants 5args]) - AC_DEFINE(HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS, 1, - [drm_dp_atomic_find_vcpi_slots() is available]) - ]) + AC_DEFINE(HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS_5ARGS, 1, + [drm_dp_atomic_find_vcpi_slots() wants 5args]) ]) ]) ]) diff --git a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h index edac58606beb9..97af03bd3e628 100644 --- a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h +++ b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h @@ -38,7 +38,6 @@ int _kcl_drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc) #define drm_dp_calc_pbn_mode _kcl_drm_dp_calc_pbn_mode #endif -#if defined(HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS) #if !defined(HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS_5ARGS) static inline int _kcl_drm_dp_atomic_find_vcpi_slots(struct drm_atomic_state *state, @@ -63,7 +62,6 @@ int _kcl_drm_dp_atomic_find_vcpi_slots(struct drm_atomic_state *state, } #define drm_dp_atomic_find_vcpi_slots _kcl_drm_dp_atomic_find_vcpi_slots #endif /* HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS_5ARGS */ -#endif /* HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS */ #if !defined(HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS) static inline From 6bed33bf0b16cc2e1a0abc72cabdabd4930d09d8 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Mon, 20 Feb 2023 15:35:34 +0800 Subject: [PATCH 0921/1868] drm/amdkcl: Fix the "array-bound" warning info when compile conftest.c There is a bug in gcc12 which caused the warning info below: "array subscript 0 is outside array bounds of 'atomic_t[0]' [-Werror=array-bounds]" To fix this issue, we add "-Wno-error=array-bounds" to ingore this warning. The same problem in the kernel has been fixed by the following patch: f0be87c42cbd gcc-12: disable '-Warray-bounds' universally for now Change-Id: If810c289579311bb0aafd43d2045e965dd710052 Signed-off-by: Ma Jun Reviewed-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 7c137d8772f94..8649879673083 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -419,7 +419,7 @@ AC_DEFUN([AC_KERNEL_COMPILE_MODULE_IFELSE], [ test "x$enable_linux_builtin" = xyes && kbuild_src_flag='KBUILD_SRC=' # override KBUILD_SRC test "x$enable_linux_builtin" = xyes && kbuild_workaround_flag='sub_make_done=' # override sub_make_done AS_IF( - [AC_TRY_COMMAND(make [$2] -C $LINUX_OBJ EXTRA_CFLAGS="-Werror -Wno-error=uninitialized -Wno-error=unused-variable" M=$PWD $kbuild_src_flag $kbuild_workaround_flag $kbuild_modpost_flag) >/dev/null && AC_TRY_COMMAND([$3])], + [AC_TRY_COMMAND(make [$2] -C $LINUX_OBJ EXTRA_CFLAGS="-Werror -Wno-error=uninitialized -Wno-error=unused-variable -Wno-error=array-bounds" M=$PWD $kbuild_src_flag $kbuild_workaround_flag $kbuild_modpost_flag) >/dev/null && AC_TRY_COMMAND([$3])], [$4], [_AC_MSG_LOG_CONFTEST m4_ifvaln([$5],[$5])] ) From 6ca059dbe82804f5f9a280fdeaa738f07dfc5880 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 1 Mar 2023 17:30:47 +0800 Subject: [PATCH 0922/1868] drm/amdkcl: wrap code under macro HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit To remove following compiling warning, wrap code under macro HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS. /var/lib/dkms/amdgpu-pro/1.0/build/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_helpers.c: In function ‘dm_helpers_dp_mst_send_payload_allocation’: /var/lib/dkms/amdgpu-pro/1.0/build/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_helpers.c:460:13: warning: unused variable ‘ret’ [-Wunused-variable] 460 | int ret = 0; | ^~~ Signed-off-by: Asher Song --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index 7d3ccc036bbc6..301746aa20465 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -534,7 +534,9 @@ void dm_helpers_dp_mst_send_payload_allocation( struct drm_dp_mst_topology_mgr *mst_mgr; enum mst_progress_status set_flag = MST_ALLOCATE_NEW_PAYLOAD; enum mst_progress_status clr_flag = MST_CLEAR_ALLOCATED_PAYLOAD; +#if defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS) int ret = 0; +#endif aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; From ce63bf41bf05a6cbbfc5d655058e0bc08e7c8f23 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 7 Mar 2023 09:36:24 +0800 Subject: [PATCH 0923/1868] drm/amdkcl: wrap code under macro RB_ROOT_CACHED Signed-off-by: Asher Song --- include/kcl/kcl_rbtree.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/kcl/kcl_rbtree.h b/include/kcl/kcl_rbtree.h index 6d3bf91f7b4f9..6a0f687a0801e 100644 --- a/include/kcl/kcl_rbtree.h +++ b/include/kcl/kcl_rbtree.h @@ -4,7 +4,7 @@ #include -#ifndef HAVE_RB_ROOT_CACHED +#ifndef RB_ROOT_CACHED /* * Leftmost-cached rbtrees. * From f3ca66f0abab5df7818cea6f79c9b2b2be44af45 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Wed, 10 Aug 2022 18:53:07 -0400 Subject: [PATCH 0924/1868] drm/amdkfd: Try to schedule bottom half on same core On systems that support SMT (hyperthreading) schedule the bottom half of the KFD interrupt handler on the same core. This makes it possible to reserve a core for interrupt handling and have the bottom half run on that same core. On systems without SMT, pick another core in the same NUMA node, as before. Use for_each_cpu_wrap instead of open-coding it. Signed-off-by: Felix Kuehling Reviewed-by: Philip Yang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdkfd/kfd_device.c | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index 3a0f6880d0030..8bb91d9c63057 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -24,6 +24,7 @@ #include #include #include +#include #include "kfd_priv.h" #include "kfd_device_queue_manager.h" #include "kfd_pm4_headers_vi.h" @@ -1072,13 +1073,24 @@ static inline void kfd_queue_work(struct workqueue_struct *wq, struct work_struct *work) { int cpu, new_cpu; + const struct cpumask *mask = NULL; cpu = new_cpu = smp_processor_id(); - do { - new_cpu = cpumask_next(new_cpu, cpu_online_mask) % nr_cpu_ids; - if (cpu_to_node(new_cpu) == numa_node_id()) + +#if defined(CONFIG_SCHED_SMT) + /* CPU threads in the same core */ + mask = cpu_smt_mask(cpu); +#endif + if (!mask || cpumask_weight(mask) <= 1) + /* CPU threads in the same NUMA node */ + mask = cpu_cpu_mask(cpu); + /* Pick the next online CPU thread in the same core or NUMA node */ + for_each_cpu_wrap(cpu, mask, cpu+1) { + if (cpu != new_cpu && cpu_online(cpu)) { + new_cpu = cpu; break; - } while (cpu != new_cpu); + } + } queue_work_on(new_cpu, wq, work); } From 33730df63bab052d259fdee2684738230eb8f69e Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 16 Feb 2023 14:39:55 +0800 Subject: [PATCH 0925/1868] drm/amdkcl: kcl-cleanup HAVE_RESERVATION_OBJECT_STAGED Change-Id: I7e226cc12719abd32970d33c08eaa965db50190b Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/kcl_reservation.c | 153 +------------------ drivers/gpu/drm/amd/dkms/config/config.h | 3 - drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 | 22 --- include/kcl/kcl_dma-resv.h | 9 -- include/kcl/reservation.h | 17 --- 5 files changed, 1 insertion(+), 203 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_reservation.c b/drivers/gpu/drm/amd/amdkcl/kcl_reservation.c index bad215a62e54d..e1b018386c601 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_reservation.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_reservation.c @@ -37,155 +37,4 @@ void amdkcl_reservation_init(void) { amdkcl_fp_setup("reservation_ww_class", NULL); -} - -#if defined(HAVE_RESERVATION_OBJECT_STAGED) -/* - * Copied from v4.19-rc6-1514-g27836b641c1b^:drivers/dma-buf/reservation.c - * and modified for KCL - */ -static void -reservation_object_add_shared_inplace(struct reservation_object *obj, - struct reservation_object_list *fobj, - struct dma_fence *fence) -{ - struct dma_fence *signaled = NULL; - u32 i, signaled_idx; - - dma_fence_get(fence); - - preempt_disable(); - write_seqcount_begin(&obj->seq); - - for (i = 0; i < fobj->shared_count; ++i) { - struct dma_fence *old_fence; - - old_fence = rcu_dereference_protected(fobj->shared[i], - dma_resv_held(obj)); - - if (old_fence->context == fence->context) { - /* memory barrier is added by write_seqcount_begin */ - RCU_INIT_POINTER(fobj->shared[i], fence); - write_seqcount_end(&obj->seq); - preempt_enable(); - - dma_fence_put(old_fence); - return; - } - - if (!signaled && dma_fence_is_signaled(old_fence)) { - signaled = old_fence; - signaled_idx = i; - } - } - - /* - * memory barrier is added by write_seqcount_begin, - * fobj->shared_count is protected by this lock too - */ - if (signaled) { - RCU_INIT_POINTER(fobj->shared[signaled_idx], fence); - } else { - BUG_ON(fobj->shared_count >= fobj->shared_max); - RCU_INIT_POINTER(fobj->shared[fobj->shared_count], fence); - fobj->shared_count++; - } - - write_seqcount_end(&obj->seq); - preempt_enable(); - - dma_fence_put(signaled); -} - -static void -reservation_object_add_shared_replace(struct reservation_object *obj, - struct reservation_object_list *old, - struct reservation_object_list *fobj, - struct dma_fence *fence) -{ - unsigned i, j, k; - - dma_fence_get(fence); - - if (!old) { - RCU_INIT_POINTER(fobj->shared[0], fence); - fobj->shared_count = 1; - goto done; - } - - /* - * no need to bump fence refcounts, rcu_read access - * requires the use of kref_get_unless_zero, and the - * references from the old struct are carried over to - * the new. - */ - for (i = 0, j = 0, k = fobj->shared_max; i < old->shared_count; ++i) { - struct dma_fence *check; - - check = rcu_dereference_protected(old->shared[i], - dma_resv_held(obj)); - - if (check->context == fence->context || - dma_fence_is_signaled(check)) - RCU_INIT_POINTER(fobj->shared[--k], check); - else - RCU_INIT_POINTER(fobj->shared[j++], check); - } - fobj->shared_count = j; - RCU_INIT_POINTER(fobj->shared[fobj->shared_count], fence); - fobj->shared_count++; - -done: - preempt_disable(); - write_seqcount_begin(&obj->seq); - /* - * RCU_INIT_POINTER can be used here, - * seqcount provides the necessary barriers - */ - RCU_INIT_POINTER(obj->fence, fobj); - write_seqcount_end(&obj->seq); - preempt_enable(); - - if (!old) - return; - - /* Drop the references to the signaled fences */ - for (i = k; i < fobj->shared_max; ++i) { - struct dma_fence *f; - - f = rcu_dereference_protected(fobj->shared[i], - dma_resv_held(obj)); - dma_fence_put(f); - } - kfree_rcu(old, rcu); -} - -void _kcl_dma_resv_add_shared_fence(struct dma_resv *obj, struct dma_fence *fence) -{ - struct dma_resv_list *old, *fobj = obj->staged; - - old = dma_resv_shared_list(obj); - obj->staged = NULL; - - if (!fobj) - reservation_object_add_shared_inplace(obj, old, fence); - else - reservation_object_add_shared_replace(obj, old, fobj, fence); -} -EXPORT_SYMBOL(_kcl_dma_resv_add_shared_fence); - -int _kcl_dma_resv_copy_fences(struct dma_resv *dst, struct dma_resv *src) -{ - int ret; - - ret = dma_resv_copy_fences(dst, src); - if (ret) - return ret; - - kfree(dst->staged); - dst->staged = NULL; - - return ret; -} -EXPORT_SYMBOL(_kcl_dma_resv_copy_fences); -#endif +} \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index c9d82c0d6ccd7..9d2a0a9f6175b 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1065,9 +1065,6 @@ /* request_firmware_direct() is available */ #define HAVE_REQUEST_FIRMWARE_DIRECT 1 -/* reservation_object->staged is available */ -/* #undef HAVE_RESERVATION_OBJECT_STAGED */ - /* sched_set_fifo_low() is available */ #define HAVE_SCHED_SET_FIFO_LOW 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 index f65379d76636f..baeb0ee766979 100644 --- a/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 @@ -56,28 +56,6 @@ AC_DEFUN([AC_AMDGPU_DMA_RESV_FENCES], [ ]) ]) - -dnl # -dnl # v4.19-rc6-1514-g27836b641c1b -dnl # dma-buf: remove shared fence staging in reservation object -dnl # -AC_DEFUN([AC_AMDGPU_RESERVATION_OBJECT_STAGED], [ - AC_KERNEL_DO_BACKGROUND([ - AS_IF([test x$HAVE_LINUX_DMA_RESV_H = x ], [ - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - struct reservation_object *resv = NULL; - resv->staged = NULL; - ], [ - AC_DEFINE(HAVE_RESERVATION_OBJECT_STAGED, 1, - [reservation_object->staged is available]) - ]) - ]) - ]) -]) - AC_DEFUN([AC_AMDGPU_DMA_RESV], [ AC_AMDGPU_DMA_RESV_FENCES - AC_AMDGPU_RESERVATION_OBJECT_STAGED ]) diff --git a/include/kcl/kcl_dma-resv.h b/include/kcl/kcl_dma-resv.h index a6b8ab359aa0d..4c2b2576374ed 100644 --- a/include/kcl/kcl_dma-resv.h +++ b/include/kcl/kcl_dma-resv.h @@ -187,15 +187,6 @@ struct dma_resv { struct dma_fence __rcu *fence_excl; struct dma_resv_list __rcu *fence; }; -#elif defined(HAVE_RESERVATION_OBJECT_STAGED) -struct dma_resv { - struct ww_mutex lock; - seqcount_t seq; - - struct dma_fence __rcu *fence_excl; - struct dma_resv_list __rcu *fence; - struct dma_resv_list *staged; -}; #else struct dma_resv { struct ww_mutex lock; diff --git a/include/kcl/reservation.h b/include/kcl/reservation.h index fbd036fdd650d..8dcc5e3c18479 100644 --- a/include/kcl/reservation.h +++ b/include/kcl/reservation.h @@ -4,23 +4,6 @@ #ifndef HAVE_LINUX_DMA_RESV_H #include - -#if defined(HAVE_RESERVATION_OBJECT_STAGED) -static inline void -_kcl_reservation_object_fini(struct reservation_object *obj) -{ - dma_resv_fini(obj); - kfree(obj->staged); -} -#define amddma_resv_fini _kcl_reservation_object_fini - -void _kcl_dma_resv_add_shared_fence(struct dma_resv *obj, struct dma_fence *fence); -#define amddma_resv_add_shared_fence _kcl_dma_resv_add_shared_fence - -int _kcl_dma_resv_copy_fences(struct dma_resv *dst, struct dma_resv *src); -#define amddma_resv_copy_fences _kcl_dma_resv_copy_fences - -#endif /* HAVE_RESERVATION_OBJECT_STAGED */ #endif /* HAVE_LINUX_DMA_RESV_H */ #endif From 791bd9d86422824160e9625e47611e9f43f8f89e Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 16 Feb 2023 15:52:24 +0800 Subject: [PATCH 0926/1868] drm/amdkcl: kcl-cleanup HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS Also removed HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PIP Change-Id: Ic77c42f0aebab15c6efece839c0ad7796ab1acf8 Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c | 41 ------------------- drivers/gpu/drm/amd/amdkcl/kcl_fbmem.h | 12 ++---- drivers/gpu/drm/amd/dkms/config/config.h | 6 --- ...ure_remove_conflicting_pci_framebuffers.m4 | 17 -------- 4 files changed, 3 insertions(+), 73 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c b/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c index ce1cdaad500a0..920cf50033339 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c @@ -13,47 +13,6 @@ #include -/* Copied from drivers/video/fbdev/core/fbmem.c and modified for KCL */ -#if !defined(HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS) && \ - !defined(HAVE_DRM_DRM_APERTURE_H) -int remove_conflicting_pci_framebuffers(struct pci_dev *pdev, const char *name) -{ - struct apertures_struct *ap; - bool primary = false; - int err, idx, bar; - - for (idx = 0, bar = 0; bar < PCI_ROM_RESOURCE; bar++) { - if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) - continue; - idx++; - } - - ap = alloc_apertures(idx); - if (!ap) - return -ENOMEM; - - for (idx = 0, bar = 0; bar < PCI_ROM_RESOURCE; bar++) { - if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) - continue; - ap->ranges[idx].base = pci_resource_start(pdev, bar); - ap->ranges[idx].size = pci_resource_len(pdev, bar); - dev_dbg(&pdev->dev, "%s: bar %d: 0x%lx -> 0x%lx\n", __func__, bar, - (unsigned long)pci_resource_start(pdev, bar), - (unsigned long)pci_resource_end(pdev, bar)); - idx++; - } - -#ifdef CONFIG_X86 - primary = pdev->resource[PCI_ROM_RESOURCE].flags & - IORESOURCE_ROM_SHADOW; -#endif - err = remove_conflicting_framebuffers(ap, name, primary); - kfree(ap); - return err; -} -EXPORT_SYMBOL(remove_conflicting_pci_framebuffers); -#endif - #ifndef HAVE_IS_FIRMWARE_FRAMEBUFFER bool is_firmware_framebuffer(struct apertures_struct *a) { diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.h b/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.h index b734ca7c3d36a..5275dfcb6b6ca 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.h +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.h @@ -5,17 +5,13 @@ #include #include -/* Copied from include/linux/fb.h */ -#if !defined(HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS) && \ - !defined(HAVE_DRM_DRM_APERTURE_H) -extern int remove_conflicting_pci_framebuffers(struct pci_dev *pdev, - const char *name); -#endif static inline int _kcl_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, const char *name) { -#ifdef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PIP +#ifdef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP + return remove_conflicting_pci_framebuffers(pdev, name); +#else /** * v5.1-rc3-20-gb0e999c95581 fbdev: list all pci memory bars as conflicting apertures * handle bar 0 directly. @@ -32,8 +28,6 @@ int _kcl_remove_conflicting_pci_framebuffers(struct pci_dev *pdev, */ pr_warn_once("remove conflicting pci framebuffers on bar 0\n"); return remove_conflicting_pci_framebuffers(pdev, 0, name); -#else - return remove_conflicting_pci_framebuffers(pdev, name); #endif } #endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 9d2a0a9f6175b..1a23578d73e6c 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1053,12 +1053,6 @@ /* whether register_shrinker(x, x) is available */ #define HAVE_REGISTER_SHRINKER_WITH_TWO_ARGUMENTS 1 -/* remove_conflicting_pci_framebuffers() is available */ -/* #undef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS */ - -/* remove_conflicting_pci_framebuffers() wants p,i,p args */ -/* #undef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PIP */ - /* remove_conflicting_pci_framebuffers() wants p,p args */ /* #undef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_aperture_remove_conflicting_pci_framebuffers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_aperture_remove_conflicting_pci_framebuffers.m4 index 87f2f1c951581..f4c7be22ebded 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_aperture_remove_conflicting_pci_framebuffers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_aperture_remove_conflicting_pci_framebuffers.m4 @@ -16,23 +16,6 @@ AC_DEFUN([AC_AMDGPU_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS], [ ], [ AC_DEFINE(HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP, 1, [remove_conflicting_pci_framebuffers() wants p,p args]) - AC_DEFINE(HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS, 1, - [remove_conflicting_pci_framebuffers() is available]) - ], [ - dnl # - dnl # v4.19-rc1-110-g4d18975c78f2 fbdev: add remove_conflicting_pci_framebuffers() - dnl # - AC_KERNEL_TRY_COMPILE([ - struct task_struct; - #include - ], [ - remove_conflicting_pci_framebuffers(NULL, 0, NULL); - ], [ - AC_DEFINE(HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PIP, 1, - [remove_conflicting_pci_framebuffers() wants p,i,p args]) - AC_DEFINE(HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS, 1, - [remove_conflicting_pci_framebuffers() is available]) - ]) ]) ]) ]) From 1804b8bad4f6ca261c0455d9cef70bf03dd98e6d Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 16 Feb 2023 15:52:55 +0800 Subject: [PATCH 0927/1868] drm/amdkcl: kcl-cleanup HAVE_PERF_EVENT_UPDATE_USERPAGE Change-Id: I44c5c04cbfb658c2faa84945e832fc5da5ebb3d6 Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_perf_event.c | 23 ------------------- drivers/gpu/drm/amd/amdkcl/main.c | 2 -- drivers/gpu/drm/amd/backport/backport.h | 1 - drivers/gpu/drm/amd/dkms/config/config.h | 3 --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - .../amd/dkms/m4/perf-event-update-userpage.m4 | 14 ----------- .../kcl/backport/kcl_perf_event_backport.h | 10 -------- 8 files changed, 1 insertion(+), 55 deletions(-) delete mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_perf_event.c delete mode 100644 drivers/gpu/drm/amd/dkms/m4/perf-event-update-userpage.m4 delete mode 100644 include/kcl/backport/kcl_perf_event_backport.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index eb1682f507b91..0f953fafc56ab 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -5,7 +5,7 @@ amdkcl-y += kcl_kernel_params.o amdkcl-y += dma-buf/dma-resv.o amdkcl-y += kcl_backlight.o kcl_ioctl.o \ - kcl_kthread.o kcl_io.o kcl_perf_event.o kcl_seq_file.o \ + kcl_kthread.o kcl_io.o kcl_seq_file.o \ kcl_suspend.o kcl_pci.o kcl_mm.o kcl_memory.o kcl_sched.o \ kcl_fence.o kcl_reservation.o kcl_drm_cache.o \ kcl_drm_fb.o kcl_drm_print.o kcl_fbmem.o \ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_perf_event.c b/drivers/gpu/drm/amd/amdkcl/kcl_perf_event.c deleted file mode 100644 index 8c7914b6ff67d..0000000000000 --- a/drivers/gpu/drm/amd/amdkcl/kcl_perf_event.c +++ /dev/null @@ -1,23 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Performance events core code: - * - * Copyright (C) 2008 Thomas Gleixner - * Copyright (C) 2008-2011 Red Hat, Inc., Ingo Molnar - * Copyright (C) 2008-2011 Red Hat, Inc., Peter Zijlstra - * Copyright © 2009 Paul Mackerras, IBM Corp. - */ -#include - -#if !defined(HAVE_PERF_EVENT_UPDATE_USERPAGE) -void (*_kcl_perf_event_update_userpage)(struct perf_event *event); -EXPORT_SYMBOL(_kcl_perf_event_update_userpage); -#endif - -void amdkcl_perf_event_init(void) -{ -#if !defined(HAVE_PERF_EVENT_UPDATE_USERPAGE) - _kcl_perf_event_update_userpage = amdkcl_fp_setup("perf_event_update_userpage", NULL); -#endif -} - diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c index 58c46b4f04ae5..b4c76ba82d292 100644 --- a/drivers/gpu/drm/amd/amdkcl/main.c +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -8,7 +8,6 @@ extern void amdkcl_fence_init(void); extern void amdkcl_reservation_init(void); extern void amdkcl_io_init(void); extern void amdkcl_mm_init(void); -extern void amdkcl_perf_event_init(void); extern void amdkcl_pci_init(void); extern void amdkcl_suspend_init(void); extern void amdkcl_sched_init(void); @@ -23,7 +22,6 @@ int __init amdkcl_init(void) amdkcl_reservation_init(); amdkcl_io_init(); amdkcl_mm_init(); - amdkcl_perf_event_init(); amdkcl_pci_init(); amdkcl_suspend_init(); amdkcl_sched_init(); diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 3200b99717ce1..109b65af58cf6 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -26,7 +26,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 1a23578d73e6c..60d94d128f055 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1026,9 +1026,6 @@ /* pci_upstream_bridge() is available */ #define HAVE_PCI_UPSTREAM_BRIDGE 1 -/* perf_event_update_userpage() is exported */ -#define HAVE_PERF_EVENT_UPDATE_USERPAGE 1 - /* pfn_t is defined */ #define HAVE_PFN_T 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 8649879673083..4434ee6c2c2c4 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -24,7 +24,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_ARCH_IO_RESERVE_FREE_MEMTYPE_WC AC_AMDGPU_ACCESS_OK_WITH_TWO_ARGUMENTS AC_AMDGPU_IN_COMPAT_SYSCALL - AC_AMDGPU_PERF_EVENT_UPDATE_USERPAGE AC_AMDGPU_SEQ_HEX_DUMP AC_AMDGPU_KSYS_SYNC_HELPER AC_AMDGPU_PCIE_GET_SPEED_AND_WIDTH_CAP diff --git a/drivers/gpu/drm/amd/dkms/m4/perf-event-update-userpage.m4 b/drivers/gpu/drm/amd/dkms/m4/perf-event-update-userpage.m4 deleted file mode 100644 index bf52b37b31d84..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/perf-event-update-userpage.m4 +++ /dev/null @@ -1,14 +0,0 @@ -dnl # -dnl # commit v4.15-rc3-1-g82975c46da82 -dnl # perf: Export perf_event_update_userpage -dnl # Export perf_event_update_userpage() so that PMU driver using them, -dnl # can be built as modules -dnl # -AC_DEFUN([AC_AMDGPU_PERF_EVENT_UPDATE_USERPAGE], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([perf_event_update_userpage],[kernel/events/core.c],[ - AC_DEFINE(HAVE_PERF_EVENT_UPDATE_USERPAGE, 1, - [perf_event_update_userpage() is exported]) - ]) - ]) -]) diff --git a/include/kcl/backport/kcl_perf_event_backport.h b/include/kcl/backport/kcl_perf_event_backport.h deleted file mode 100644 index 41f336d7039a7..0000000000000 --- a/include/kcl/backport/kcl_perf_event_backport.h +++ /dev/null @@ -1,10 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef AMD_KCL_PERF_EVENT_BACKPORT_H -#define AMD_KCL_PERF_EVENT_BACKPORT_H -#include -#include - -#if !defined(HAVE_PERF_EVENT_UPDATE_USERPAGE) -#define perf_event_update_userpage _kcl_perf_event_update_userpage -#endif -#endif From bca80d0cf3ec7bdb7c055791198fe9260a1b8163 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 16 Feb 2023 16:02:53 +0800 Subject: [PATCH 0928/1868] drm/amdkcl: kcl-cleanup HAVE_PCI_IRQ_VECTOR Change-Id: I6295c98fa61a0c09945ffe1af3491549a1235979 Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 3 --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - drivers/gpu/drm/amd/dkms/m4/pci-irq-vector.m4 | 16 ---------------- include/kcl/kcl_pci.h | 9 --------- 4 files changed, 29 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/pci-irq-vector.m4 diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 60d94d128f055..585b10e38bf02 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1011,9 +1011,6 @@ /* struct pci_driver has field dev_groups */ #define HAVE_PCI_DRIVER_DEV_GROUPS 1 -/* pci_irq_vector() is available */ -#define HAVE_PCI_IRQ_VECTOR 1 - /* pci_is_thunderbolt_attached() is available */ #define HAVE_PCI_IS_THUNDERBOLD_ATTACHED 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 4434ee6c2c2c4..cdc8945dca3b8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -176,7 +176,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DMA_FENCE_OPS_USE_64BIT_SEQNO AC_AMDGPU_GENERIC_HANDLE_DOMAIN_IRQ AC_AMDGPU__DMA_FENCE_IS_LATER - AC_AMDGPU_PCI_IRQ_VECTOR AC_AMDGPU_DRM_FIRMWARE_DRIVERS_ONLY AC_AMDGPU_DMA_FENCE_DESCRIBE AC_AMDGPU_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT diff --git a/drivers/gpu/drm/amd/dkms/m4/pci-irq-vector.m4 b/drivers/gpu/drm/amd/dkms/m4/pci-irq-vector.m4 deleted file mode 100644 index 5567ed9920070..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/pci-irq-vector.m4 +++ /dev/null @@ -1,16 +0,0 @@ -dnl # -dnl # v4.7-rc6-10-gaff171641d18 -dnl # PCI: Provide sensible IRQ vector alloc/free routines -dnl # -AC_DEFUN([AC_AMDGPU_PCI_IRQ_VECTOR], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - pci_irq_vector(NULL, 0); - ], [ - AC_DEFINE(HAVE_PCI_IRQ_VECTOR, 1, - [pci_irq_vector() is available]) - ]) - ]) -]) diff --git a/include/kcl/kcl_pci.h b/include/kcl/kcl_pci.h index cf46e2db8d19b..f10e5e5c84106 100644 --- a/include/kcl/kcl_pci.h +++ b/include/kcl/kcl_pci.h @@ -241,13 +241,4 @@ u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar) #endif /* PCI_REBAR_CTRL_BAR_SHIFT */ -#if !defined(HAVE_PCI_IRQ_VECTOR) -static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr) -{ - if (WARN_ON_ONCE(nr > 0)) - return -EINVAL; - return dev->irq; -} -#endif /* HAVE_PCI_IRQ_VECTOR */ - #endif /* AMDKCL_PCI_H */ From 874428293430801ffbbff578af9d5fc866a052db Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Fri, 17 Feb 2023 14:10:18 +0800 Subject: [PATCH 0929/1868] drm/amdkcl: kcl-cleanup HAVE_PCIE_GET_SPEED_AND_WIDTH_CAP Change-Id: I6e00c1b00b4640cbc0cf29649845d736a00e572c Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/kcl_pci.c | 68 ------------------- drivers/gpu/drm/amd/dkms/config/config.h | 3 - drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - .../amd/dkms/m4/pcie-get-speed-width-cap.m4 | 12 ---- include/kcl/backport/kcl_pci_backport.h | 4 -- include/kcl/kcl_pci.h | 13 ---- 6 files changed, 101 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/pcie-get-speed-width-cap.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_pci.c b/drivers/gpu/drm/amd/amdkcl/kcl_pci.c index 42ca0b4a36945..e334a99db43b9 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_pci.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_pci.c @@ -104,70 +104,6 @@ u32 _kcl_pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting EXPORT_SYMBOL(_kcl_pcie_bandwidth_available); #endif /* HAVE_PCIE_BANDWIDTH_AVAILABLE */ -#if !defined(HAVE_PCIE_GET_SPEED_AND_WIDTH_CAP) -/* - * pcie_get_speed_cap - query for the PCI device's link speed capability - * @dev: PCI device to query - * - * Query the PCI device speed capability. Return the maximum link speed - * supported by the device. - */ -enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev) -{ - u32 lnkcap2, lnkcap; - - /* - * PCIe r4.0 sec 7.5.3.18 recommends using the Supported Link - * Speeds Vector in Link Capabilities 2 when supported, falling - * back to Max Link Speed in Link Capabilities otherwise. - */ - pcie_capability_read_dword(dev, PCI_EXP_LNKCAP2, &lnkcap2); - if (lnkcap2) { /* PCIe r3.0-compliant */ - if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_16_0GB) - return PCIE_SPEED_16_0GT; - else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_8_0GB) - return PCIE_SPEED_8_0GT; - else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_5_0GB) - return PCIE_SPEED_5_0GT; - else if (lnkcap2 & PCI_EXP_LNKCAP2_SLS_2_5GB) - return PCIE_SPEED_2_5GT; - return PCI_SPEED_UNKNOWN; - } - - pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); - if (lnkcap) { - if (lnkcap & PCI_EXP_LNKCAP_SLS_16_0GB) - return PCIE_SPEED_16_0GT; - else if (lnkcap & PCI_EXP_LNKCAP_SLS_8_0GB) - return PCIE_SPEED_8_0GT; - else if (lnkcap & PCI_EXP_LNKCAP_SLS_5_0GB) - return PCIE_SPEED_5_0GT; - else if (lnkcap & PCI_EXP_LNKCAP_SLS_2_5GB) - return PCIE_SPEED_2_5GT; - } - - return PCI_SPEED_UNKNOWN; -} - -/** - * pcie_get_width_cap - query for the PCI device's link width capability - * @dev: PCI device to query - * - * Query the PCI device width capability. Return the maximum link width - * supported by the device. - */ -enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev) -{ - u32 lnkcap; - - pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); - if (lnkcap) - return (lnkcap & PCI_EXP_LNKCAP_MLW) >> 4; - - return PCIE_LNK_WIDTH_UNKNOWN; -} -#endif - enum pci_bus_speed (*_kcl_pcie_get_speed_cap)(struct pci_dev *dev); EXPORT_SYMBOL(_kcl_pcie_get_speed_cap); @@ -176,10 +112,6 @@ EXPORT_SYMBOL(_kcl_pcie_get_width_cap); void amdkcl_pci_init(void) { -#if !defined(HAVE_PCIE_GET_SPEED_AND_WIDTH_CAP) - _kcl_pcie_get_speed_cap = amdkcl_fp_setup("pcie_get_speed_cap", pcie_get_speed_cap); - _kcl_pcie_get_width_cap = amdkcl_fp_setup("pcie_get_width_cap", pcie_get_width_cap); -#endif #if !defined(HAVE_PCIE_BANDWIDTH_AVAILABLE) _kcl_pcie_link_speed = (const unsigned char *) amdkcl_fp_setup("pcie_link_speed", _kcl_pcie_link_speed_stub); #endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 585b10e38bf02..df676de5411e9 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -999,9 +999,6 @@ /* pci_enable_atomic_ops_to_root() exist */ #define HAVE_PCIE_ENABLE_ATOMIC_OPS_TO_ROOT 1 -/* pcie_get_speed_cap() and pcie_get_width_cap() exist */ -#define HAVE_PCIE_GET_SPEED_AND_WIDTH_CAP 1 - /* PCI driver handles extended tags */ #define HAVE_PCI_CONFIGURE_EXTENDED_TAGS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index cdc8945dca3b8..67834e5366a22 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -26,7 +26,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_IN_COMPAT_SYSCALL AC_AMDGPU_SEQ_HEX_DUMP AC_AMDGPU_KSYS_SYNC_HELPER - AC_AMDGPU_PCIE_GET_SPEED_AND_WIDTH_CAP AC_AMDGPU_PCIE_ENABLE_ATOMIC_OPS_TO_ROOT AC_AMDGPU_PCI_UPSTREAM_BRIDGE AC_AMDGPU_PCIE_BANDWIDTH_AVAILABLE diff --git a/drivers/gpu/drm/amd/dkms/m4/pcie-get-speed-width-cap.m4 b/drivers/gpu/drm/amd/dkms/m4/pcie-get-speed-width-cap.m4 deleted file mode 100644 index 905b62bc15628..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/pcie-get-speed-width-cap.m4 +++ /dev/null @@ -1,12 +0,0 @@ -dnl # -dnl # commit 576c7218a1546e0153480b208b125509cec71470 -dnl # PCI: Export pcie_get_speed_cap and pcie_get_width_cap -dnl # -AC_DEFUN([AC_AMDGPU_PCIE_GET_SPEED_AND_WIDTH_CAP], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([pcie_get_speed_cap pcie_get_width_cap], [drivers/pci/pci.c], [ - AC_DEFINE(HAVE_PCIE_GET_SPEED_AND_WIDTH_CAP, 1, - [pcie_get_speed_cap() and pcie_get_width_cap() exist]) - ]) - ]) -]) diff --git a/include/kcl/backport/kcl_pci_backport.h b/include/kcl/backport/kcl_pci_backport.h index 2cf66ef4aa69f..f75f4fbd7e7fa 100644 --- a/include/kcl/backport/kcl_pci_backport.h +++ b/include/kcl/backport/kcl_pci_backport.h @@ -6,10 +6,6 @@ #include #include -#if !defined(HAVE_PCIE_GET_SPEED_AND_WIDTH_CAP) -#define pcie_get_speed_cap _kcl_pcie_get_speed_cap -#endif - #if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 9, 0) #define AMDKCL_PCIE_BRIDGE_PM_USABLE #endif diff --git a/include/kcl/kcl_pci.h b/include/kcl/kcl_pci.h index f10e5e5c84106..e9547c0d7ffd1 100644 --- a/include/kcl/kcl_pci.h +++ b/include/kcl/kcl_pci.h @@ -97,27 +97,14 @@ 0) #endif -#if !defined(HAVE_PCIE_GET_SPEED_AND_WIDTH_CAP) -extern enum pci_bus_speed (*_kcl_pcie_get_speed_cap)(struct pci_dev *dev); -extern enum pcie_link_width (*_kcl_pcie_get_width_cap)(struct pci_dev *dev); -#endif - static inline enum pci_bus_speed kcl_pcie_get_speed_cap(struct pci_dev *dev) { -#if defined(HAVE_PCIE_GET_SPEED_AND_WIDTH_CAP) return pcie_get_speed_cap(dev); -#else - return _kcl_pcie_get_speed_cap(dev); -#endif } static inline enum pcie_link_width kcl_pcie_get_width_cap(struct pci_dev *dev) { -#if defined(HAVE_PCIE_GET_SPEED_AND_WIDTH_CAP) return pcie_get_width_cap(dev); -#else - return _kcl_pcie_get_width_cap(dev); -#endif } #if !defined(HAVE_PCIE_ENABLE_ATOMIC_OPS_TO_ROOT) From ec807561206ebb6a8ee6ea65bcdf6e119dff71b8 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Fri, 17 Feb 2023 14:21:08 +0800 Subject: [PATCH 0930/1868] drm/amdkcl: kcl-cleanup HAVE_PCIE_ENABLE_ATOMIC_OPS_TO_ROOT Change-Id: Ia12c8c8690eb14142d092a19d39d6bdf87d0dc92 Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/kcl_pci.c | 87 ------------------- drivers/gpu/drm/amd/dkms/config/config.h | 3 - drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - .../dkms/m4/pcie-enable-atomic-ops-to-root.m4 | 18 ---- include/kcl/kcl_pci.h | 9 -- 5 files changed, 118 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/pcie-enable-atomic-ops-to-root.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_pci.c b/drivers/gpu/drm/amd/amdkcl/kcl_pci.c index e334a99db43b9..f5664e46c26e2 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_pci.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_pci.c @@ -117,93 +117,6 @@ void amdkcl_pci_init(void) #endif } -#if !defined(HAVE_PCIE_ENABLE_ATOMIC_OPS_TO_ROOT) -/** - * pci_enable_atomic_ops_to_root - enable AtomicOp requests to root port - * @dev: the PCI device - * @comp_caps: Caps required for atomic request completion - * - * Return 0 if all upstream bridges support AtomicOp routing, egress - * blocking is disabled on all upstream ports, and the root port - * supports the requested completion capabilities (32-bit, 64-bit - * and/or 128-bit AtomicOp completion), or negative otherwise. - * - */ -int _kcl_pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 comp_caps) -{ - struct pci_bus *bus = dev->bus; - - if (!pci_is_pcie(dev)) - return -EINVAL; - - switch (pci_pcie_type(dev)) { - /* - * PCIe 3.0, 6.15 specifies that endpoints and root ports are permitted - * to implement AtomicOp requester capabilities. - */ - case PCI_EXP_TYPE_ENDPOINT: - case PCI_EXP_TYPE_LEG_END: - case PCI_EXP_TYPE_RC_END: - break; - default: - return -EINVAL; - } - - while (bus->parent) { - struct pci_dev *bridge = bus->self; - u32 cap; - - pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap); - - switch (pci_pcie_type(bridge)) { - /* - * Upstream, downstream and root ports may implement AtomicOp - * routing capabilities. AtomicOp routing via a root port is - * not considered. - */ - case PCI_EXP_TYPE_UPSTREAM: - case PCI_EXP_TYPE_DOWNSTREAM: - if (!(cap & PCI_EXP_DEVCAP2_ATOMIC_ROUTE)) - return -EINVAL; - break; - - /* - * Root ports are permitted to implement AtomicOp completion - * capabilities. - */ - case PCI_EXP_TYPE_ROOT_PORT: - if ((cap & comp_caps) != comp_caps) - return -EINVAL; - break; - } - - /* - * Upstream ports may block AtomicOps on egress. - */ -#if defined(OS_NAME_RHEL_6) - if (pci_pcie_type(bridge) == PCI_EXP_TYPE_DOWNSTREAM) { -#else - if (!bridge->has_secondary_link) { -#endif - u32 ctl2; - - pcie_capability_read_dword(bridge, PCI_EXP_DEVCTL2, - &ctl2); - if (ctl2 & PCI_EXP_DEVCTL2_ATOMIC_BLOCK) - return -EINVAL; - } - - bus = bus->parent; - } - - pcie_capability_set_word(dev, PCI_EXP_DEVCTL2, - PCI_EXP_DEVCTL2_ATOMIC_REQ); - - return 0; -} -EXPORT_SYMBOL(_kcl_pci_enable_atomic_ops_to_root); -#endif - #if !defined(HAVE_PCI_CONFIGURE_EXTENDED_TAGS) void _kcl_pci_configure_extended_tags(struct pci_dev *dev) { diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index df676de5411e9..1e95eb187accb 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -996,9 +996,6 @@ /* pcie_bandwidth_available() is available */ #define HAVE_PCIE_BANDWIDTH_AVAILABLE 1 -/* pci_enable_atomic_ops_to_root() exist */ -#define HAVE_PCIE_ENABLE_ATOMIC_OPS_TO_ROOT 1 - /* PCI driver handles extended tags */ #define HAVE_PCI_CONFIGURE_EXTENDED_TAGS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 67834e5366a22..1c1f00fce659a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -26,7 +26,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_IN_COMPAT_SYSCALL AC_AMDGPU_SEQ_HEX_DUMP AC_AMDGPU_KSYS_SYNC_HELPER - AC_AMDGPU_PCIE_ENABLE_ATOMIC_OPS_TO_ROOT AC_AMDGPU_PCI_UPSTREAM_BRIDGE AC_AMDGPU_PCIE_BANDWIDTH_AVAILABLE AC_AMDGPU_PCI_CONFIGURE_EXTENDED_TAGS diff --git a/drivers/gpu/drm/amd/dkms/m4/pcie-enable-atomic-ops-to-root.m4 b/drivers/gpu/drm/amd/dkms/m4/pcie-enable-atomic-ops-to-root.m4 deleted file mode 100644 index fe1539a268b96..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/pcie-enable-atomic-ops-to-root.m4 +++ /dev/null @@ -1,18 +0,0 @@ -dnl # -dnl # commit 430a23689dea2e36ae5a0fc75a67301fd46b18bf -dnl # Author: Jay Cornwall -dnl # Date: Thu Jan 4 19:44:59 2018 -0500 -dnl # PCI: Add pci_enable_atomic_ops_to_root() -dnl # -AC_DEFUN([AC_AMDGPU_PCIE_ENABLE_ATOMIC_OPS_TO_ROOT], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include - ], [ - pci_enable_atomic_ops_to_root(NULL, 0); - ], [pci_enable_atomic_ops_to_root], [drivers/pci/pci.c], [ - AC_DEFINE(HAVE_PCIE_ENABLE_ATOMIC_OPS_TO_ROOT, 1, - [pci_enable_atomic_ops_to_root() exist]) - ]) - ]) -]) diff --git a/include/kcl/kcl_pci.h b/include/kcl/kcl_pci.h index e9547c0d7ffd1..f3dd051548960 100644 --- a/include/kcl/kcl_pci.h +++ b/include/kcl/kcl_pci.h @@ -107,15 +107,6 @@ static inline enum pcie_link_width kcl_pcie_get_width_cap(struct pci_dev *dev) return pcie_get_width_cap(dev); } -#if !defined(HAVE_PCIE_ENABLE_ATOMIC_OPS_TO_ROOT) -int _kcl_pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 comp_caps); -static inline -int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask) -{ - return _kcl_pci_enable_atomic_ops_to_root(dev, cap_mask); -} -#endif - /* Copied from v3.12-rc2-29-gc6bde215acfd include/linux/pci.h */ #if !defined(HAVE_PCI_UPSTREAM_BRIDGE) static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev) From dfe99c3f3582bd3b0151f5739b45ec3d275a04e7 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Fri, 17 Feb 2023 14:23:02 +0800 Subject: [PATCH 0931/1868] drm/amdkcl: kcl-cleanup HAVE_PCIE_BANDWIDTH_AVAILABLE Change-Id: I39e6f5f778632ceb7d21d951c840f32b8b5a0bbf Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdkcl/kcl_pci.c | 90 ------------------- drivers/gpu/drm/amd/amdkcl/main.c | 2 - drivers/gpu/drm/amd/dkms/config/config.h | 3 - drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - .../amd/dkms/m4/pcie-bandwidth-available.m4 | 16 ---- include/kcl/kcl_pci.h | 13 --- 6 files changed, 125 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/pcie-bandwidth-available.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_pci.c b/drivers/gpu/drm/amd/amdkcl/kcl_pci.c index f5664e46c26e2..c62f0a2f9d6e9 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_pci.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_pci.c @@ -21,102 +21,12 @@ #include #include -#if !defined(HAVE_PCIE_BANDWIDTH_AVAILABLE) -/* Copied from drivers/pci/probe.c and modified for KCL */ -const unsigned char *_kcl_pcie_link_speed; - -const unsigned char _kcl_pcie_link_speed_stub[] = { - PCI_SPEED_UNKNOWN, /* 0 */ - PCIE_SPEED_2_5GT, /* 1 */ - PCIE_SPEED_5_0GT, /* 2 */ - PCIE_SPEED_8_0GT, /* 3 */ - PCI_SPEED_UNKNOWN, /* 4 */ - PCI_SPEED_UNKNOWN, /* 5 */ - PCI_SPEED_UNKNOWN, /* 6 */ - PCI_SPEED_UNKNOWN, /* 7 */ - PCI_SPEED_UNKNOWN, /* 8 */ - PCI_SPEED_UNKNOWN, /* 9 */ - PCI_SPEED_UNKNOWN, /* A */ - PCI_SPEED_UNKNOWN, /* B */ - PCI_SPEED_UNKNOWN, /* C */ - PCI_SPEED_UNKNOWN, /* D */ - PCI_SPEED_UNKNOWN, /* E */ - PCI_SPEED_UNKNOWN /* F */ -}; - -/* Copied from drivers/pci/pci.c */ -/** - * pcie_bandwidth_available - determine minimum link settings of a PCIe - * device and its bandwidth limitation - * @dev: PCI device to query - * @limiting_dev: storage for device causing the bandwidth limitation - * @speed: storage for speed of limiting device - * @width: storage for width of limiting device - * - * Walk up the PCI device chain and find the point where the minimum - * bandwidth is available. Return the bandwidth available there and (if - * limiting_dev, speed, and width pointers are supplied) information about - * that point. The bandwidth returned is in Mb/s, i.e., megabits/second of - * raw bandwidth. - */ -u32 _kcl_pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, - enum pci_bus_speed *speed, - enum pcie_link_width *width) -{ - u16 lnksta; - enum pci_bus_speed next_speed; - enum pcie_link_width next_width; - u32 bw, next_bw; - - if (speed) - *speed = PCI_SPEED_UNKNOWN; - if (width) - *width = PCIE_LNK_WIDTH_UNKNOWN; - - bw = 0; - - while (dev) { - pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); - - next_speed = _kcl_pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS]; - next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >> - PCI_EXP_LNKSTA_NLW_SHIFT; - - next_bw = next_width * PCIE_SPEED2MBS_ENC(next_speed); - - /* Check if current device limits the total bandwidth */ - if (!bw || next_bw <= bw) { - bw = next_bw; - - if (limiting_dev) - *limiting_dev = dev; - if (speed) - *speed = next_speed; - if (width) - *width = next_width; - } - - dev = pci_upstream_bridge(dev); - } - - return bw; -} -EXPORT_SYMBOL(_kcl_pcie_bandwidth_available); -#endif /* HAVE_PCIE_BANDWIDTH_AVAILABLE */ - enum pci_bus_speed (*_kcl_pcie_get_speed_cap)(struct pci_dev *dev); EXPORT_SYMBOL(_kcl_pcie_get_speed_cap); enum pcie_link_width (*_kcl_pcie_get_width_cap)(struct pci_dev *dev); EXPORT_SYMBOL(_kcl_pcie_get_width_cap); -void amdkcl_pci_init(void) -{ -#if !defined(HAVE_PCIE_BANDWIDTH_AVAILABLE) - _kcl_pcie_link_speed = (const unsigned char *) amdkcl_fp_setup("pcie_link_speed", _kcl_pcie_link_speed_stub); -#endif -} - #if !defined(HAVE_PCI_CONFIGURE_EXTENDED_TAGS) void _kcl_pci_configure_extended_tags(struct pci_dev *dev) { diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c index b4c76ba82d292..d33b1db010e1a 100644 --- a/drivers/gpu/drm/amd/amdkcl/main.c +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -8,7 +8,6 @@ extern void amdkcl_fence_init(void); extern void amdkcl_reservation_init(void); extern void amdkcl_io_init(void); extern void amdkcl_mm_init(void); -extern void amdkcl_pci_init(void); extern void amdkcl_suspend_init(void); extern void amdkcl_sched_init(void); extern void amdkcl_numa_init(void); @@ -22,7 +21,6 @@ int __init amdkcl_init(void) amdkcl_reservation_init(); amdkcl_io_init(); amdkcl_mm_init(); - amdkcl_pci_init(); amdkcl_suspend_init(); amdkcl_sched_init(); amdkcl_numa_init(); diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 1e95eb187accb..78dc36156ecbb 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -993,9 +993,6 @@ /* pcie_aspm_enabled() is available */ #define HAVE_PCIE_ASPM_ENABLED 1 -/* pcie_bandwidth_available() is available */ -#define HAVE_PCIE_BANDWIDTH_AVAILABLE 1 - /* PCI driver handles extended tags */ #define HAVE_PCI_CONFIGURE_EXTENDED_TAGS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 1c1f00fce659a..4c457d6839661 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -27,7 +27,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_SEQ_HEX_DUMP AC_AMDGPU_KSYS_SYNC_HELPER AC_AMDGPU_PCI_UPSTREAM_BRIDGE - AC_AMDGPU_PCIE_BANDWIDTH_AVAILABLE AC_AMDGPU_PCI_CONFIGURE_EXTENDED_TAGS AC_AMDGPU_PCI_DEV_ID AC_AMDGPU_PCI_REBAR_BYTES_TO_SIZE diff --git a/drivers/gpu/drm/amd/dkms/m4/pcie-bandwidth-available.m4 b/drivers/gpu/drm/amd/dkms/m4/pcie-bandwidth-available.m4 deleted file mode 100644 index e733ecc72488c..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/pcie-bandwidth-available.m4 +++ /dev/null @@ -1,16 +0,0 @@ -dnl # -dnl # commit 6db79a88c67e4679d9c1e4a3f05c6385e21f6e9a -dnl # PCI: Add pcie_bandwidth_available() to compute bandwidth available to device -dnl # -AC_DEFUN([AC_AMDGPU_PCIE_BANDWIDTH_AVAILABLE], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include - ], [ - pcie_bandwidth_available(NULL, NULL, NULL, NULL); - ], [pcie_bandwidth_available], [drivers/pci/pci.c], [ - AC_DEFINE(HAVE_PCIE_BANDWIDTH_AVAILABLE, 1, - [pcie_bandwidth_available() is available]) - ]) - ]) -]) diff --git a/include/kcl/kcl_pci.h b/include/kcl/kcl_pci.h index f3dd051548960..62e8d734fdf5c 100644 --- a/include/kcl/kcl_pci.h +++ b/include/kcl/kcl_pci.h @@ -119,19 +119,6 @@ static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev) } #endif -#if !defined(HAVE_PCIE_BANDWIDTH_AVAILABLE) -u32 _kcl_pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, - enum pci_bus_speed *speed, - enum pcie_link_width *width); -static inline -u32 pcie_bandwidth_available(struct pci_dev *dev, struct pci_dev **limiting_dev, - enum pci_bus_speed *speed, - enum pcie_link_width *width) -{ - return _kcl_pcie_bandwidth_available(dev, limiting_dev, speed, width); -} -#endif - #if !defined(HAVE_PCI_CONFIGURE_EXTENDED_TAGS) void _kcl_pci_configure_extended_tags(struct pci_dev *dev); #endif From ad96475a704da2593f90fa6d75f39cd0b63262f0 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 16 Feb 2023 14:42:08 +0800 Subject: [PATCH 0932/1868] drm/amdkcl: kcl-cleanup HAVE_REQUEST_FIRMWARE_DIRECT Change-Id: I91f5937cd38c55d365f385d874a796f92befd366 Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/backport/backport.h | 1 - drivers/gpu/drm/amd/dkms/config/config.h | 3 --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - .../drm/amd/dkms/m4/request-firmware-direct.m4 | 16 ---------------- include/kcl/kcl_firmware.h | 12 ------------ 5 files changed, 33 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/request-firmware-direct.m4 delete mode 100644 include/kcl/kcl_firmware.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 109b65af58cf6..e913c8e92c80c 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -15,7 +15,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 78dc36156ecbb..8914b7075e0c1 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1041,9 +1041,6 @@ /* remove_conflicting_pci_framebuffers() wants p,p args */ /* #undef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP */ -/* request_firmware_direct() is available */ -#define HAVE_REQUEST_FIRMWARE_DIRECT 1 - /* sched_set_fifo_low() is available */ #define HAVE_SCHED_SET_FIFO_LOW 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 4c457d6839661..04ccd6c58277e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -14,7 +14,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DMA_MAP_SGTABLE AC_AMDGPU_I2C_NEW_CLIENT_DEVICE AC_AMDGPU_I2C_LOCK_OPERATIONS_STRUCT - AC_AMDGPU_REQUEST_FIRMWARE_DIRECT AC_AMDGPU_BACKLIGHT_DEVICE_SET_BRIGHTNESS AC_AMDGPU_DEV_PM_SET_DRIVER_FLAGS AC_AMDGPU_COMPAT_PTR_IOCTL diff --git a/drivers/gpu/drm/amd/dkms/m4/request-firmware-direct.m4 b/drivers/gpu/drm/amd/dkms/m4/request-firmware-direct.m4 deleted file mode 100644 index 218e403328bc8..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/request-firmware-direct.m4 +++ /dev/null @@ -1,16 +0,0 @@ -dnl # -dnl # v3.13-rc2-51-gbba3a87e982a -dnl # firmware: Introduce request_firmware_direct() -dnl # -AC_DEFUN([AC_AMDGPU_REQUEST_FIRMWARE_DIRECT], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - request_firmware_direct(NULL, NULL, NULL); - ], [ - AC_DEFINE(HAVE_REQUEST_FIRMWARE_DIRECT, 1, - [request_firmware_direct() is available]) - ]) - ]) -]) diff --git a/include/kcl/kcl_firmware.h b/include/kcl/kcl_firmware.h deleted file mode 100644 index b846e2d4eee5d..0000000000000 --- a/include/kcl/kcl_firmware.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef AMDKCL_FIRMWARE_H -#define AMDKCL_FIRMWARE_H - -#if !defined(HAVE_REQUEST_FIRMWARE_DIRECT) -#include - -#define request_firmware_direct request_firmware - -#endif -#endif /* AMDKCL_FIRMWARE_H */ - From 17f608893da6f161d3669016a046f9b0c1bc25c3 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 23 Feb 2023 11:02:14 +0800 Subject: [PATCH 0933/1868] drm/amdkcl:kcl-cleanup HAVE_DRM_GEM_MAP_ATTACH_2ARGS Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c | 8 +------- drivers/gpu/drm/amd/dkms/config/config.h | 3 --- drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 | 2 -- drivers/gpu/drm/amd/dkms/m4/drm-gem-map-attach.m4 | 14 -------------- 4 files changed, 1 insertion(+), 26 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-gem-map-attach.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c index eb303d6fb1637..640d344975db0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c @@ -147,9 +147,6 @@ __dma_resv_make_exclusive(struct dma_resv *obj) * 0 on success or a negative error code on failure. */ static int amdgpu_dma_buf_map_attach(struct dma_buf *dma_buf, -#ifndef HAVE_DRM_GEM_MAP_ATTACH_2ARGS - struct device *target_dev, -#endif struct dma_buf_attachment *attach) { struct drm_gem_object *obj = dma_buf->priv; @@ -157,11 +154,8 @@ static int amdgpu_dma_buf_map_attach(struct dma_buf *dma_buf, struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); long r; -#ifdef HAVE_DRM_GEM_MAP_ATTACH_2ARGS r = drm_gem_map_attach(dma_buf, attach); -#else - r = drm_gem_map_attach(dma_buf, target_dev, attach); -#endif + if (r) return r; diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 8914b7075e0c1..53515c3c8863f 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -581,9 +581,6 @@ /* drm_gem_plane_helper_prepare_fb() is available */ #define HAVE_DRM_GEM_PLANE_HELPER_PREPARE_FB 1 -/* drm_gem_map_attach() wants 2 arguments */ -/* #undef HAVE_DRM_GEM_MAP_ATTACH_2ARGS */ - /* drm_gem_object_funcs->vmap() has 2 args */ #define HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_2ARGS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 index d4f139e428849..86159c3f96200 100644 --- a/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/dma-buf.m4 @@ -52,8 +52,6 @@ AC_DEFUN([AC_AMDGPU_DMA_BUF], [ ],[ AC_DEFINE(HAVE_DMA_BUF_OPS_LEGACY, 1, [dma_buf->dynamic_mapping is not available]) - - AC_AMDGPU_DRM_GEM_MAP_ATTACH ]) ]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-gem-map-attach.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-gem-map-attach.m4 deleted file mode 100644 index 031d62f21740f..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm-gem-map-attach.m4 +++ /dev/null @@ -1,14 +0,0 @@ -dnl # -dnl # commit v4.17-rc3-491-ga19741e5e5a9 -dnl # dma_buf: remove device parameter from attach callback v2 -dnl # -AC_DEFUN([AC_AMDGPU_DRM_GEM_MAP_ATTACH], [ - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include - ], [ - drm_gem_map_attach(NULL, NULL); - ], [drm_gem_map_attach], [drivers/gpu/drm/drm_prime.c], [ - AC_DEFINE(HAVE_DRM_GEM_MAP_ATTACH_2ARGS, 1, - [drm_gem_map_attach() wants 2 arguments]) - ]) -]) From c7d59c3f5948e66ede1504658e6b8a09aba0c2a9 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Fri, 24 Feb 2023 13:11:05 +0800 Subject: [PATCH 0934/1868] drm/amdkcl:kcl-cleanup CONFIG_DRM_AMD_DC_DSC_SUPPORT Signed-off-by: Ma Jun Reviewed-by: Leslie Shi Reviewed-by: Folra Cui --- .../gpu/drm/amd/amdkcl/kcl_drm_dsc_helper.c | 5 +-- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 9 ----- .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 10 ------ .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 4 --- .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 6 ---- drivers/gpu/drm/amd/display/dc/core/dc.c | 12 ------- .../gpu/drm/amd/display/dc/core/dc_resource.c | 6 ---- .../gpu/drm/amd/display/dc/core/dc_stream.c | 4 --- drivers/gpu/drm/amd/display/dc/dc.h | 8 ----- drivers/gpu/drm/amd/display/dc/dc_stream.h | 2 -- drivers/gpu/drm/amd/display/dc/dc_types.h | 2 -- drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c | 4 --- .../display/dc/dcn201/dcn201_link_encoder.c | 2 -- .../amd/display/dc/dcn21/dcn21_link_encoder.c | 2 -- .../display/dc/dio/dcn20/dcn20_link_encoder.c | 6 ---- .../display/dc/dio/dcn20/dcn20_link_encoder.h | 2 -- .../dc/dio/dcn20/dcn20_stream_encoder.c | 6 ---- .../dc/dio/dcn30/dcn30_dio_link_encoder.c | 2 -- .../dc/dio/dcn30/dcn30_dio_stream_encoder.c | 4 --- .../dc/dio/dcn301/dcn301_dio_link_encoder.c | 2 -- .../dc/dio/dcn31/dcn31_dio_link_encoder.c | 6 ---- .../dc/dio/dcn314/dcn314_dio_stream_encoder.c | 6 ---- .../dc/dio/dcn32/dcn32_dio_link_encoder.c | 2 -- .../dc/dio/dcn32/dcn32_dio_stream_encoder.c | 3 -- .../dc/dio/dcn321/dcn321_dio_link_encoder.c | 2 -- .../amd/display/dc/dml/display_mode_enums.h | 2 -- .../drm/amd/display/dc/dml/dsc/rc_calc_fpu.c | 2 -- .../drm/amd/display/dc/dml/dsc/rc_calc_fpu.h | 2 -- drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 2 -- .../drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c | 2 -- .../drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h | 2 -- drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c | 2 -- .../gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c | 2 -- .../hpo/dcn31/dcn31_hpo_dp_stream_encoder.c | 2 -- .../amd/display/dc/hwss/dcn10/dcn10_hwseq.c | 4 --- .../amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 8 ----- .../amd/display/dc/hwss/dcn20/dcn20_hwseq.h | 2 -- .../amd/display/dc/hwss/dcn20/dcn20_init.c | 4 --- .../amd/display/dc/hwss/dcn21/dcn21_init.c | 2 -- .../amd/display/dc/hwss/dcn30/dcn30_init.c | 2 -- .../amd/display/dc/hwss/dcn301/dcn301_init.c | 2 -- .../amd/display/dc/hwss/dcn302/dcn302_hwseq.c | 2 -- .../amd/display/dc/hwss/dcn302/dcn302_hwseq.h | 2 -- .../amd/display/dc/hwss/dcn302/dcn302_init.c | 2 -- .../amd/display/dc/hwss/dcn31/dcn31_hwseq.c | 6 ---- .../amd/display/dc/hwss/dcn31/dcn31_init.c | 2 -- .../amd/display/dc/hwss/dcn314/dcn314_hwseq.c | 4 --- .../amd/display/dc/hwss/dcn314/dcn314_init.c | 2 -- .../amd/display/dc/hwss/dcn32/dcn32_hwseq.c | 4 --- .../amd/display/dc/hwss/dcn32/dcn32_hwseq.h | 2 -- .../amd/display/dc/hwss/dcn32/dcn32_init.c | 2 -- .../gpu/drm/amd/display/dc/inc/core_types.h | 4 --- .../drm/amd/display/dc/inc/hw/link_encoder.h | 4 --- .../amd/display/dc/inc/hw/timing_generator.h | 2 -- drivers/gpu/drm/amd/display/dc/inc/link.h | 5 ++- .../gpu/drm/amd/display/dc/link/link_dpms.c | 12 ------- .../drm/amd/display/dc/link/link_validation.c | 7 ---- .../dc/link/protocols/link_dp_capability.c | 9 +---- .../dc/link/protocols/link_dp_capability.h | 2 -- .../display/dc/link/protocols/link_dp_phy.c | 2 -- .../display/dc/link/protocols/link_dp_phy.h | 2 -- .../dc/link/protocols/link_dp_training.c | 4 --- .../link/protocols/link_dp_training_8b_10b.c | 2 -- .../dc/link/protocols/link_dp_training_dpia.c | 4 --- .../link/protocols/link_edp_panel_control.c | 4 --- .../amd/display/dc/optc/dcn20/dcn20_optc.c | 9 ----- .../amd/display/dc/optc/dcn20/dcn20_optc.h | 2 -- .../amd/display/dc/optc/dcn201/dcn201_optc.c | 2 -- .../amd/display/dc/optc/dcn30/dcn30_optc.c | 4 --- .../amd/display/dc/optc/dcn30/dcn30_optc.h | 2 -- .../amd/display/dc/optc/dcn31/dcn31_optc.c | 2 -- .../amd/display/dc/optc/dcn314/dcn314_optc.c | 2 -- .../amd/display/dc/optc/dcn32/dcn32_optc.c | 2 -- .../dc/resource/dcn20/dcn20_resource.c | 33 ------------------- .../dc/resource/dcn20/dcn20_resource.h | 2 -- .../dc/resource/dcn201/dcn201_resource.c | 2 -- .../dc/resource/dcn21/dcn21_resource.c | 14 -------- .../dc/resource/dcn30/dcn30_resource.c | 22 ------------- .../dc/resource/dcn301/dcn301_resource.c | 14 -------- .../dc/resource/dcn302/dcn302_resource.c | 12 ------- .../dc/resource/dcn303/dcn303_resource.c | 10 ------ .../dc/resource/dcn31/dcn31_resource.c | 12 ------- .../dc/resource/dcn314/dcn314_resource.c | 10 ------ .../dc/resource/dcn315/dcn315_resource.c | 14 -------- .../dc/resource/dcn316/dcn316_resource.c | 14 -------- .../dc/resource/dcn32/dcn32_resource.c | 10 ------ .../resource/dcn32/dcn32_resource_helpers.c | 2 -- .../dc/resource/dcn321/dcn321_resource.c | 2 -- .../dc/virtual/virtual_stream_encoder.c | 8 ----- drivers/gpu/drm/amd/dkms/Makefile | 3 -- include/kcl/kcl_drm_dsc_helper.h | 3 -- 91 files changed, 4 insertions(+), 458 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_dsc_helper.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_dsc_helper.c index f5546b4049608..8c799582dbbd7 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_dsc_helper.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_dsc_helper.c @@ -15,7 +15,6 @@ * device expects the PPS payload in big endian format for fields * that span more than 1 byte. */ -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include #include @@ -330,6 +329,4 @@ int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg) return 0; } EXPORT_SYMBOL(drm_dsc_compute_rc_parameters); -#endif /* HAVE_DRM_DSC_COMPUTE_RC_PARAMETERS */ - -#endif /* CONFIG_DRM_AMD_DC_DSC_SUPPORT */ +#endif /* HAVE_DRM_DSC_COMPUTE_RC_PARAMETERS */ \ No newline at end of file diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 5a4093f2569ff..c93c60861d51d 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -7359,10 +7359,8 @@ create_validate_stream_for_sink(struct amdgpu_dm_connector *aconnector, return stream; dc_result = dc_validate_stream(adev->dm.dc, stream); -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (dc_result == DC_OK && stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) dc_result = dm_dp_mst_is_port_support_mode(aconnector, stream); -#endif if (dc_result == DC_OK) dc_result = dm_validate_stream_and_context(adev->dm.dc, stream); @@ -7705,7 +7703,6 @@ const struct drm_encoder_helper_funcs amdgpu_dm_encoder_helper_funcs = { .atomic_check = dm_encoder_helper_atomic_check }; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #if defined(HAVE_DRM_DP_MST_ATOMIC_ENABLE_DSC) static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state, struct dc_state *dc_state, @@ -7792,7 +7789,6 @@ static int dm_update_mst_vcpi_slots_for_dsc(struct drm_atomic_state *state, return 0; } #endif -#endif static int to_drm_connector_type(enum signal_type st) { @@ -11451,11 +11447,9 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, bool lock_and_validation_needed = false; bool is_top_most_overlay = true; struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT struct drm_dp_mst_topology_mgr *mgr; struct drm_dp_mst_topology_state *mst_state; struct dsc_mst_fairness_vars vars[MAX_PIPES] = {0}; -#endif trace_amdgpu_dm_atomic_check_begin(state); ret = drm_atomic_helper_check_modeset(dev, state); @@ -11778,7 +11772,6 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, lock_and_validation_needed = true; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS /* set the slot info for each mst_state based on the link encoding format */ for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) { @@ -11803,8 +11796,6 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, } drm_connector_list_iter_end(&iter); } -#endif -#endif #endif /** * Streams and planes are reset when there are changes that affect diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index 395cd360741e0..7f6e7e6679060 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -1335,7 +1335,6 @@ static ssize_t dp_sdp_message_debugfs_write(struct file *f, const char __user *b * cat /sys/kernel/debug/dri/0/DP-X/dp_dsc_fec_support * */ -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static int dp_dsc_fec_support_show(struct seq_file *m, void *data) { struct drm_connector *connector = m->private; @@ -1391,7 +1390,6 @@ static int dp_dsc_fec_support_show(struct seq_file *m, void *data) return ret; } -#endif /* function: Trigger virtual HPD redetection on connector * @@ -1529,7 +1527,6 @@ static ssize_t trigger_hotplug(struct file *f, const char __user *buf, * 1 - means that DSC is currently enabled * 0 - means that DSC is disabled */ -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static ssize_t dp_dsc_clock_en_read(struct file *f, char __user *buf, size_t size, loff_t *pos) { @@ -2532,7 +2529,6 @@ static ssize_t dp_dsc_slice_bpg_offset_read(struct file *f, char __user *buf, kfree(rd_buf); return result; } -#endif /* * function description: Read max_requested_bpc property from the connector @@ -2864,9 +2860,7 @@ static int is_dpia_link_show(struct seq_file *m, void *data) return 0; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT DEFINE_SHOW_ATTRIBUTE(dp_dsc_fec_support); -#endif DEFINE_SHOW_ATTRIBUTE(dmub_fw_state); DEFINE_SHOW_ATTRIBUTE(dmub_tracebuffer); #ifdef DEFINE_DEBUGFS_ATTRIBUTE @@ -2883,7 +2877,6 @@ DEFINE_SHOW_ATTRIBUTE(dp_is_mst_connector); DEFINE_SHOW_ATTRIBUTE(dp_mst_progress_status); DEFINE_SHOW_ATTRIBUTE(is_dpia_link); -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static const struct file_operations dp_dsc_clock_en_debugfs_fops = { .owner = THIS_MODULE, .read = dp_dsc_clock_en_read, @@ -2935,7 +2928,6 @@ static const struct file_operations dp_dsc_slice_bpg_offset_debugfs_fops = { .read = dp_dsc_slice_bpg_offset_read, .llseek = default_llseek }; -#endif static const struct file_operations trigger_hotplug_debugfs_fops = { .owner = THIS_MODULE, @@ -3009,8 +3001,6 @@ static const struct { {"dsc_chunk_size", &dp_dsc_chunk_size_debugfs_fops}, {"dsc_slice_bpg", &dp_dsc_slice_bpg_offset_debugfs_fops}, {"dp_dsc_fec_support", &dp_dsc_fec_support_fops}, -#endif - {"max_bpc", &dp_max_bpc_debugfs_fops}, {"dsc_disable_passthrough", &dp_dsc_disable_passthrough_debugfs_fops}, #ifdef HAVE_DRM_DP_MST_TOPOLOGY_MGR_BASE diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index 301746aa20465..6235e8de87805 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -810,7 +810,6 @@ bool dm_helpers_submit_i2c( return result; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static bool execute_synaptics_rc_command(struct drm_dp_aux *aux, bool is_write_cmd, unsigned char cmd, @@ -981,9 +980,7 @@ static uint8_t write_dsc_enable_synaptics_non_virtual_dpcd_mst( return ret; } -#endif -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT bool dm_helpers_dp_write_dsc_enable( struct dc_context *ctx, const struct dc_stream_state *stream, @@ -1076,7 +1073,6 @@ bool dm_helpers_dp_write_dsc_enable( return ret; } -#endif bool dm_helpers_is_dp_sink_present(struct dc_link *link) { diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 9efeecbe2ccb7..c71e8534b36c0 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -233,7 +233,6 @@ static const struct drm_connector_funcs dm_dp_mst_connector_funcs = { #endif /* HAVE_DRM_DP_MST_CONNECTOR_EARLY_UNREGISTER */ }; -#if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT) bool needs_dsc_aux_workaround(struct dc_link *link) { if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 && @@ -325,7 +324,6 @@ static bool retrieve_downstream_port_device(struct amdgpu_dm_connector *aconnect return true; } #endif -#endif static int dm_dp_mst_get_modes(struct drm_connector *connector) { @@ -442,7 +440,6 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector) amdgpu_dm_update_freesync_caps( connector, aconnector->edid); -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #if defined(HAVE_DRM_DP_MST_DSC_AUX_FOR_PORT) #if defined(CONFIG_DRM_AMD_DC_FP) if (!validate_dsc_caps_on_connector(aconnector)) @@ -453,7 +450,6 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector) if (!retrieve_downstream_port_device(aconnector)) memset(&aconnector->mst_downstream_port_present, 0, sizeof(aconnector->mst_downstream_port_present)); -#endif #endif } } @@ -912,7 +908,6 @@ int dm_mst_get_pbn_divider(struct dc_link *link) dc_link_get_link_cap(link)) / (8 * 1000 * 54); } -#if defined(CONFIG_DRM_AMD_DC_DSC_SUPPORT) #if defined(HAVE_DRM_DP_MST_ATOMIC_CHECK) struct dsc_mst_fairness_params { struct dc_crtc_timing *timing; @@ -2006,4 +2001,3 @@ enum dc_status dm_dp_mst_is_port_support_mode( #endif return DC_OK; } -#endif diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index dcbb43d91837e..f50ae8e8cbf73 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -64,9 +64,7 @@ #include "dc_dmub_srv.h" -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include "dsc.h" -#endif #include "vm_helper.h" @@ -671,9 +669,7 @@ bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream, param.windowb_y_end = crc_window->windowb_y_end; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT param.dsc_mode = pipe->stream->timing.flags.DSC ? 1:0; -#endif param.odm_mode = pipe->next_odm_pipe ? 1:0; /* Default to the union of both windows */ @@ -2685,10 +2681,8 @@ static enum surface_update_type check_update_surfaces_for_stream( if (stream_update->wb_update) su_flags->bits.wb_update = 1; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (stream_update->dsc_config) su_flags->bits.dsc_changed = 1; -#endif if (stream_update->mst_bw_update) su_flags->bits.mst_bw = 1; @@ -2911,9 +2905,7 @@ static void copy_stream_update_to_stream(struct dc *dc, struct dc_stream_state *stream, struct dc_stream_update *update) { -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT struct dc_context *dc_ctx = dc->ctx; -#endif if (update == NULL || stream == NULL) return; @@ -3009,7 +3001,6 @@ static void copy_stream_update_to_stream(struct dc *dc, update->wb_update->writeback_info[i]; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (update->dsc_config) { struct dc_dsc_config old_dsc_cfg = stream->timing.dsc_cfg; uint32_t old_dsc_enabled = stream->timing.flags.DSC; @@ -3034,7 +3025,6 @@ static void copy_stream_update_to_stream(struct dc *dc, update->dsc_config = NULL; } } -#endif } static void backup_planes_and_stream_state( @@ -3328,10 +3318,8 @@ static void commit_planes_do_stream_update(struct dc *dc, if (update_type == UPDATE_TYPE_FAST) continue; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (stream_update->dsc_config) dc->link_srv->update_dsc_config(pipe_ctx); -#endif if (stream_update->mst_bw_update) { if (stream_update->mst_bw_update->is_increase) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index 41226e7a91be0..b38340c690c60 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -3755,11 +3755,7 @@ bool dc_resource_is_dsc_encoding_supported(const struct dc *dc) if (dc->res_pool == NULL) return false; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT return dc->res_pool->res_cap->num_dsc > 0; -#else - return 0; -#endif } static bool planes_changed_for_existing_stream(struct dc_state *context, @@ -4641,10 +4637,8 @@ bool pipe_need_reprogram( false == pipe_ctx_old->stream->dpms_off) return true; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (pipe_ctx_old->stream_res.dsc != pipe_ctx->stream_res.dsc) return true; -#endif if (pipe_ctx_old->stream_res.hpo_dp_stream_enc != pipe_ctx->stream_res.hpo_dp_stream_enc) return true; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index 077947d031a31..be2638c763d78 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -107,7 +107,6 @@ bool dc_stream_construct(struct dc_stream_state *stream, /* EDID CAP translation for HDMI 2.0 */ stream->timing.flags.LTE_340MCSC_SCRAMBLE = dc_sink_data->edid_caps.lte_340mcsc_scramble; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT memset(&stream->timing.dsc_cfg, 0, sizeof(stream->timing.dsc_cfg)); stream->timing.dsc_cfg.num_slices_h = 0; stream->timing.dsc_cfg.num_slices_v = 0; @@ -116,7 +115,6 @@ bool dc_stream_construct(struct dc_stream_state *stream, stream->timing.dsc_cfg.linebuf_depth = 9; stream->timing.dsc_cfg.version_minor = 2; stream->timing.dsc_cfg.ycbcr422_simple = 0; -#endif update_stream_signal(stream, dc_sink_data); @@ -779,7 +777,6 @@ bool dc_stream_set_dynamic_metadata(struct dc *dc, return true; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT enum dc_status dc_stream_add_dsc_to_resource(struct dc *dc, struct dc_state *state, struct dc_stream_state *stream) @@ -790,7 +787,6 @@ enum dc_status dc_stream_add_dsc_to_resource(struct dc *dc, return DC_NO_DSC_RESOURCE; } } -#endif struct pipe_ctx *dc_stream_get_pipe_ctx(struct dc_stream_state *stream) { diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 5f19d0df305ec..6b036417a73ae 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -882,13 +882,11 @@ struct dc_debug_options { bool disable_dfs_bypass; bool disable_dpp_power_gate; bool disable_hubp_power_gate; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT bool disable_dsc_power_gate; bool disable_optc_power_gate; bool disable_hpo_power_gate; int dsc_min_slice_height_override; int dsc_bpp_increment_div; -#endif bool disable_pplib_wm_range; enum wm_report_mode pplib_wm_report_mode; unsigned int min_disp_clk_khz; @@ -2350,7 +2348,6 @@ struct dc_container_id { }; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT struct dc_sink_dsc_caps { // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), // 'false' if they are sink's DSC caps @@ -2360,7 +2357,6 @@ struct dc_sink_dsc_caps { bool is_dsc_passthrough_supported; struct dsc_dec_dpcd_caps dsc_dec_caps; }; -#endif struct dc_sink_fec_caps { bool is_rx_fec_supported; @@ -2386,10 +2382,8 @@ struct dc_sink { bool converter_disable_audio; struct scdc_caps scdc_caps; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT struct dc_sink_dsc_caps dsc_caps; struct dc_sink_fec_caps fec_caps; -#endif bool is_vsc_sdp_colorimetry_supported; @@ -2536,10 +2530,8 @@ struct dc_power_profile { struct dc_power_profile dc_get_power_profile_for_dc_state(const struct dc_state *context); -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* DSC Interfaces */ #include "dc_dsc.h" -#endif /* Disable acc mode Interfaces */ void dc_disable_accelerated_mode(struct dc *dc); diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h index 68855b68a9764..de9bd72ca514d 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_stream.h +++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h @@ -437,11 +437,9 @@ bool dc_stream_remove_writeback(struct dc *dc, struct dc_stream_state *stream, uint32_t dwb_pipe_inst); -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT enum dc_status dc_stream_add_dsc_to_resource(struct dc *dc, struct dc_state *state, struct dc_stream_state *stream); -#endif bool dc_stream_warmup_writeback(struct dc *dc, int num_dwb, diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h index 516a0f05cebc3..97279b080f3e0 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_types.h @@ -535,9 +535,7 @@ enum dc_infoframe_type { DC_HDMI_INFOFRAME_TYPE_AVI = 0x82, DC_HDMI_INFOFRAME_TYPE_SPD = 0x83, DC_HDMI_INFOFRAME_TYPE_AUDIO = 0x84, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT DC_DP_INFOFRAME_TYPE_PPS = 0x10, -#endif }; struct dc_info_packet { diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c index abfd493314514..f7b4867f0b330 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c @@ -379,9 +379,7 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub, copy_settings_data->fec_enable_delay_in100us = link->dc->debug.fec_enable_delay_in100us; copy_settings_data->cmd_version = DMUB_CMD_PSR_CONTROL_VERSION_1; copy_settings_data->panel_inst = panel_inst; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT copy_settings_data->dsc_enable_status = (pipe_ctx->stream->timing.flags.DSC == 1); -#endif /** * WA for PSRSU+DSC on specific TCON, if DSC is enabled, force PSRSU as ffu mode(full frame update) * Note that PSRSU+DSC is still under development. @@ -395,7 +393,6 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub, link->psr_settings.force_ffu_mode = 0; copy_settings_data->force_ffu_mode = link->psr_settings.force_ffu_mode; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (((link->dpcd_caps.fec_cap.bits.FEC_CAPABLE && !link->dc->debug.disable_fec) && (link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT && @@ -408,7 +405,6 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub, sizeof(DP_SINK_DEVICE_STR_ID_2)))) copy_settings_data->debug.bitfields.force_wakeup_by_tps3 = 1; else -#endif copy_settings_data->debug.bitfields.force_wakeup_by_tps3 = 0; if (link->psr_settings.psr_version == DC_PSR_VERSION_1 && diff --git a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_link_encoder.c index 789d6800ff08c..8d31fa131cd60 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dcn201/dcn201_link_encoder.c @@ -77,9 +77,7 @@ static bool dcn201_link_encoder_is_in_alt_mode(struct link_encoder *enc) } static const struct link_encoder_funcs dcn201_link_enc_funcs = { -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .read_state = link_enc2_read_state, -#endif .validate_output_with_stream = dcn10_link_encoder_validate_output_with_stream, .hw_init = enc2_hw_init, diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c index 24fedaf5df408..eb9abb9f96986 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_link_encoder.c @@ -298,9 +298,7 @@ static void dcn21_link_encoder_disable_output(struct link_encoder *enc, static const struct link_encoder_funcs dcn21_link_enc_funcs = { -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .read_state = link_enc2_read_state, -#endif .validate_output_with_stream = dcn10_link_encoder_validate_output_with_stream, .hw_init = enc2_hw_init, diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c index d1518602a1702..182437fd0e147 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.c @@ -173,10 +173,8 @@ static struct mpll_cfg dcn2_mpll_cfg[] = { void enc2_fec_set_enable(struct link_encoder *enc, bool enable) { struct dcn10_link_encoder *enc10 = TO_DCN10_LINK_ENC(enc); -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT DC_LOG_DSC("%s FEC at link encoder inst %d", enable ? "Enabling" : "Disabling", enc->id.enum_id); -#endif REG_UPDATE(DP_DPHY_CNTL, DPHY_FEC_EN, enable); } @@ -197,7 +195,6 @@ bool enc2_fec_is_active(struct link_encoder *enc) return (active != 0); } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* this function reads dsc related register fields to be logged later in dcn10_log_hw_state * into a dcn_dsc_state struct. */ @@ -210,7 +207,6 @@ void link_enc2_read_state(struct link_encoder *enc, struct link_enc_state *s) REG_GET(DP_DPHY_CNTL, DPHY_FEC_ACTIVE_STATUS, &s->dphy_fec_active_status); REG_GET(DP_LINK_CNTL, DP_LINK_TRAINING_COMPLETE, &s->dp_link_training_complete); } -#endif static bool update_cfg_data( struct dcn10_link_encoder *enc10, @@ -360,9 +356,7 @@ void enc2_hw_init(struct link_encoder *enc) } static const struct link_encoder_funcs dcn20_link_enc_funcs = { -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .read_state = link_enc2_read_state, -#endif .validate_output_with_stream = dcn10_link_encoder_validate_output_with_stream, .hw_init = enc2_hw_init, diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h index 39a5f6882cf95..762c579fcb44d 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_link_encoder.h @@ -342,9 +342,7 @@ void enc2_fec_set_ready(struct link_encoder *enc, bool ready); bool enc2_fec_is_active(struct link_encoder *enc); void enc2_hw_init(struct link_encoder *enc); -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void link_enc2_read_state(struct link_encoder *enc, struct link_enc_state *s); -#endif void dcn20_link_encoder_enable_dp_output( struct link_encoder *enc, diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c index 2fa2816e28aa0..1953c56367d32 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn20/dcn20_stream_encoder.c @@ -207,7 +207,6 @@ static void enc2_stream_encoder_stop_hdmi_info_packets( HDMI_GENERIC7_LINE, 0); } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* Update GSP7 SDP 128 byte long */ static void enc2_update_gsp7_128_info_packet( struct dcn10_stream_encoder *enc1, @@ -365,7 +364,6 @@ static void enc2_read_state(struct stream_encoder *enc, struct enc_state *s) REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable); } } -#endif /* Set Dynamic Metadata-configuration. * enable_dme: TRUE: enables Dynamic Metadata Enfine, FALSE: disables DME @@ -461,10 +459,8 @@ static bool is_two_pixels_per_containter(const struct dc_crtc_timing *timing) { bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422 && !timing->dsc_cfg.ycbcr422_simple); -#endif return two_pix; } @@ -635,11 +631,9 @@ static const struct stream_encoder_funcs dcn20_str_enc_funcs = { .dp_get_pixel_format = enc1_stream_encoder_dp_get_pixel_format, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .enc_read_state = enc2_read_state, .dp_set_dsc_config = enc2_dp_set_dsc_config, .dp_set_dsc_pps_info_packet = enc2_dp_set_dsc_pps_info_packet, -#endif .set_dynamic_metadata = enc2_set_dynamic_metadata, .hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute, .get_fifo_cal_average_level = enc2_get_fifo_cal_average_level, diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c index 504b70931b701..b8e31b5ea1140 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_link_encoder.c @@ -56,9 +56,7 @@ bool dcn30_link_encoder_validate_output_with_stream( } static const struct link_encoder_funcs dcn30_link_enc_funcs = { -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .read_state = link_enc2_read_state, -#endif .validate_output_with_stream = dcn30_link_encoder_validate_output_with_stream, .hw_init = enc3_hw_init, diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c index 8b0a72dd20846..425b830b88d2c 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn30/dcn30_dio_stream_encoder.c @@ -295,7 +295,6 @@ void enc3_stream_encoder_stop_hdmi_info_packets( HDMI_GENERIC14_LINE, 0); } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* Set DSC-related configuration. * dsc_mode: 0 disables DSC, other values enable DSC in specified format * sc_bytes_per_pixel: Bytes per pixel in u3.28 format @@ -402,7 +401,6 @@ static void enc3_read_state(struct stream_encoder *enc, struct enc_state *s) REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable); } } -#endif void enc3_stream_encoder_update_dp_info_packets_sdp_line_num( struct stream_encoder *enc, @@ -867,11 +865,9 @@ static const struct stream_encoder_funcs dcn30_str_enc_funcs = { .dp_get_pixel_format = enc1_stream_encoder_dp_get_pixel_format, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .enc_read_state = enc3_read_state, .dp_set_dsc_config = enc3_dp_set_dsc_config, .dp_set_dsc_pps_info_packet = enc3_dp_set_dsc_pps_info_packet, -#endif .set_dynamic_metadata = enc2_set_dynamic_metadata, .hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute, diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.c index 100953da7bc48..1b39a6e8a1ac5 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn301/dcn301_dio_link_encoder.c @@ -48,9 +48,7 @@ (enc10->link_regs->index) static const struct link_encoder_funcs dcn301_link_enc_funcs = { -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .read_state = link_enc2_read_state, -#endif .validate_output_with_stream = dcn10_link_encoder_validate_output_with_stream, .hw_init = enc3_hw_init, .setup = dcn10_link_encoder_setup, diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c index 551f3918845dd..b2cea59ba5d49 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn31/dcn31_dio_link_encoder.c @@ -247,9 +247,7 @@ void enc31_hw_init(struct link_encoder *enc) } static const struct link_encoder_funcs dcn31_link_enc_funcs = { -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .read_state = link_enc2_read_state, -#endif .validate_output_with_stream = dcn30_link_encoder_validate_output_with_stream, .hw_init = enc31_hw_init, @@ -484,9 +482,7 @@ void dcn31_link_encoder_enable_dp_output( if (link) { dpia_control.dpia_id = link->ddc_hw_inst; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT dpia_control.fec_rdy = link->dc->link_srv->dp_should_enable_fec(link); -#endif } else { DC_LOG_ERROR("%s: Failed to execute DPIA enable DMUB command.\n", __func__); BREAK_TO_DEBUGGER(); @@ -533,9 +529,7 @@ void dcn31_link_encoder_enable_dp_mst_output( if (link) { dpia_control.dpia_id = link->ddc_hw_inst; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT dpia_control.fec_rdy = link->dc->link_srv->dp_should_enable_fec(link); -#endif } else { DC_LOG_ERROR("%s: Failed to execute DPIA enable DMUB command.\n", __func__); BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c index 30a12b51e7896..de4c574fe9750 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c @@ -375,7 +375,6 @@ void enc314_stream_encoder_dp_unblank( link->dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_ENABLE_DP_VID_STREAM); } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* Set DSC-related configuration. * dsc_mode: 0 disables DSC, other values enable DSC in specified format * sc_bytes_per_pixel: DP_DSC_BYTES_PER_PIXEL removed in DCN32 @@ -410,7 +409,6 @@ void enc314_read_state(struct stream_encoder *enc, struct enc_state *s) REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable); } } -#endif void enc314_set_dig_input_mode(struct stream_encoder *enc, unsigned int pix_per_container) { @@ -459,14 +457,10 @@ static const struct stream_encoder_funcs dcn314_str_enc_funcs = { .set_avmute = enc1_stream_encoder_set_avmute, .dig_connect_to_otg = enc1_dig_connect_to_otg, .dig_source_otg = enc1_dig_source_otg, - .dp_get_pixel_format = enc1_stream_encoder_dp_get_pixel_format, - -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .enc_read_state = enc314_read_state, .dp_set_dsc_config = enc314_dp_set_dsc_config, .dp_set_dsc_pps_info_packet = enc3_dp_set_dsc_pps_info_packet, -#endif .set_dynamic_metadata = enc2_set_dynamic_metadata, .hdmi_reset_stream_attribute = enc1_reset_hdmi_stream_attribute, diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c index cfcd48a67c760..06907e8a4eda1 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_link_encoder.c @@ -195,9 +195,7 @@ void dcn32_link_encoder_get_max_link_cap(struct link_encoder *enc, static const struct link_encoder_funcs dcn32_link_enc_funcs = { -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .read_state = link_enc2_read_state, -#endif .validate_output_with_stream = dcn30_link_encoder_validate_output_with_stream, .hw_init = enc32_hw_init, diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c index 173225fcdb6b5..1a9bb614c41e0 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn32/dcn32_dio_stream_encoder.c @@ -346,7 +346,6 @@ void enc32_stream_encoder_dp_unblank( link->dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_ENABLE_DP_VID_STREAM); } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* Set DSC-related configuration. * dsc_mode: 0 disables DSC, other values enable DSC in specified format * sc_bytes_per_pixel: DP_DSC_BYTES_PER_PIXEL removed in DCN32 @@ -381,7 +380,6 @@ static void enc32_read_state(struct stream_encoder *enc, struct enc_state *s) REG_GET(DP_SEC_CNTL, DP_SEC_STREAM_ENABLE, &s->sec_stream_enable); } } -#endif static void enc32_set_dig_input_mode(struct stream_encoder *enc, unsigned int pix_per_container) { @@ -460,7 +458,6 @@ static const struct stream_encoder_funcs dcn32_str_enc_funcs = { .dp_get_pixel_format = enc1_stream_encoder_dp_get_pixel_format, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .enc_read_state = enc32_read_state, .dp_set_dsc_config = enc32_dp_set_dsc_config, .dp_set_dsc_pps_info_packet = enc3_dp_set_dsc_pps_info_packet, diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c index b555264990f6b..2ed382a8e79c6 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn321/dcn321_dio_link_encoder.c @@ -60,9 +60,7 @@ dm_write_reg(CTX, AUX_REG(reg_name), val) static const struct link_encoder_funcs dcn321_link_enc_funcs = { -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .read_state = link_enc2_read_state, -#endif .validate_output_with_stream = dcn30_link_encoder_validate_output_with_stream, .hw_init = enc32_hw_init, diff --git a/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h b/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h index 8975cd1529fa3..d5831a34f5a19 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h +++ b/drivers/gpu/drm/amd/display/dc/dml/display_mode_enums.h @@ -174,9 +174,7 @@ enum dm_validation_status { DML_FAIL_DIO_SUPPORT, DML_FAIL_NOT_ENOUGH_DSC, DML_FAIL_DSC_CLK_REQUIRED, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT DML_FAIL_DSC_VALIDATION_FAILURE, -#endif DML_FAIL_URGENT_LATENCY, DML_FAIL_REORDERING_BUFFER, DML_FAIL_DISPCLK_DPPCLK, diff --git a/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.c index e14e11ccf7d08..bf01d8a9e538b 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.c @@ -23,7 +23,6 @@ * */ -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include "rc_calc_fpu.h" #include "qp_tables.h" @@ -258,4 +257,3 @@ void _do_calc_rc_params(struct rc_params *rc, rc->rc_buf_thresh[12] = 8000; rc->rc_buf_thresh[13] = 8064; } -#endif diff --git a/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.h b/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.h index 0b70eb9bcc6b9..d7cd8cc247583 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.h +++ b/drivers/gpu/drm/amd/display/dc/dml/dsc/rc_calc_fpu.h @@ -23,7 +23,6 @@ * */ -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #ifndef __RC_CALC_FPU_H__ #define __RC_CALC_FPU_H__ @@ -89,4 +88,3 @@ void _do_calc_rc_params(struct rc_params *rc, int minor_version); #endif -#endif diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c index 6a1f4e778888e..a1727e5bf0247 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c @@ -22,7 +22,6 @@ * Author: AMD */ -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include #include #include "dc_hw_types.h" @@ -1269,4 +1268,3 @@ void dc_dsc_get_default_config_option(const struct dc *dc, struct dc_dsc_config_ options->max_target_bpp_limit_override_x16 = 0; options->slice_height_granularity = 1; } -#endif diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c index 457da2d56ba4c..ada393b613834 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c @@ -23,7 +23,6 @@ * */ -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include #include "reg_helper.h" @@ -777,4 +776,3 @@ static void dsc_write_to_registers(struct display_stream_compressor *dsc, const RANGE_BPG_OFFSET14, reg_vals->pps.rc_range_params[14].range_bpg_offset); } -#endif diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h index 18f62bd6f0c87..cec8d03c96714 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h +++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h @@ -21,7 +21,6 @@ * Authors: AMD * */ -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #ifndef __DCN20_DSC_H__ #define __DCN20_DSC_H__ @@ -610,4 +609,3 @@ void dsc2_disconnect(struct display_stream_compressor *dsc); void dsc2_wait_disconnect_pending_clear(struct display_stream_compressor *dsc); #endif -#endif diff --git a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c index 1699a57ab7cb1..25ea69bd2e820 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c @@ -1,4 +1,3 @@ -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* * Copyright 2017 Advanced Micro Devices, Inc. @@ -68,4 +67,3 @@ void calc_rc_params(struct rc_params *rc, const struct drm_dsc_config *pps) DC_FP_END(); #endif } -#endif diff --git a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c index 13fc27926468f..6f5ad09ad1404 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c @@ -1,4 +1,3 @@ -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* * Copyright 2012-17 Advanced Micro Devices, Inc. * @@ -122,4 +121,3 @@ int dscc_compute_dsc_parameters(const struct drm_dsc_config *pps, dsc_params->rc_buffer_model_size = dsc_cfg.rc_bits; return ret; } -#endif diff --git a/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c index b788f9d9d9306..678db949cfe3c 100644 --- a/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/hpo/dcn31/dcn31_hpo_dp_stream_encoder.c @@ -563,9 +563,7 @@ static void dcn31_hpo_dp_stream_enc_set_dsc_pps_info_packet( /* Load PPS into infoframe (SDP) registers */ pps_sdp.valid = true; pps_sdp.hb0 = 0; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT pps_sdp.hb1 = DC_DP_INFOFRAME_TYPE_PPS; -#endif pps_sdp.hb2 = 127; pps_sdp.hb3 = 0; diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c index da01b34f65322..01dffed4d30ba 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c @@ -49,9 +49,7 @@ #include "clk_mgr.h" #include "link_hwss.h" #include "dpcd_defs.h" -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include "dsc.h" -#endif #include "dce/dmub_psr.h" #include "dc_dmub_srv.h" #include "dce/dmub_hw_lock_mgr.h" @@ -464,7 +462,6 @@ void dcn10_log_hw_state(struct dc *dc, } DTN_INFO("\n"); -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT // dcn_dsc_state struct field bytes_per_pixel was renamed to bits_per_pixel // TODO: Update golden log header to reflect this name change DTN_INFO("DSC: CLOCK_EN SLICE_WIDTH Bytes_pp\n"); @@ -521,7 +518,6 @@ void dcn10_log_hw_state(struct dc *dc, } } DTN_INFO("\n"); -#endif DTN_INFO("\nCALCULATED Clocks: dcfclk_khz:%d dcfclk_deep_sleep_khz:%d dispclk_khz:%d\n" "dppclk_khz:%d max_supported_dppclk_khz:%d fclk_khz:%d socclk_khz:%d\n\n", diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c index 761f5462f0716..a80c085829320 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c @@ -32,9 +32,7 @@ #include "dcn20/dcn20_resource.h" #include "dcn20_hwseq.h" #include "dce/dce_hwseq.h" -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include "dcn20/dcn20_dsc.h" -#endif #include "dcn20/dcn20_optc.h" #include "abm.h" #include "clk_mgr.h" @@ -464,7 +462,6 @@ void dcn20_init_blank( hws->funcs.wait_for_blank_complete(opp); } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void dcn20_dsc_pg_control( struct dce_hwseq *hws, unsigned int dsc_inst, @@ -541,7 +538,6 @@ void dcn20_dsc_pg_control( if (org_ip_request_cntl == 0) REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); } -#endif void dcn20_dpp_pg_control( struct dce_hwseq *hws, @@ -2575,7 +2571,6 @@ bool dcn20_dmdata_status_done(struct pipe_ctx *pipe_ctx) void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx) { -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT struct dce_hwseq *hws = dc->hwseq; if (pipe_ctx->stream_res.dsc) { @@ -2587,12 +2582,10 @@ void dcn20_disable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx) odm_pipe = odm_pipe->next_odm_pipe; } } -#endif } void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx) { -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT struct dce_hwseq *hws = dc->hwseq; if (pipe_ctx->stream_res.dsc) { @@ -2604,7 +2597,6 @@ void dcn20_enable_stream_gating(struct dc *dc, struct pipe_ctx *pipe_ctx) odm_pipe = odm_pipe->next_odm_pipe; } } -#endif } void dcn20_set_dmdata_attributes(struct pipe_ctx *pipe_ctx) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h index 99f3e16f6fd67..5c874f7b0683e 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.h @@ -130,12 +130,10 @@ void dcn20_init_vm_ctx( void dcn20_set_flip_control_gsl( struct pipe_ctx *pipe_ctx, bool flip_immediate); -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void dcn20_dsc_pg_control( struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on); -#endif void dcn20_fpga_init_hw(struct dc *dc); bool dcn20_wait_for_blank_complete( struct output_pixel_processor *opp); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c index e959818f70a9f..32707b344f0b6 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_init.c @@ -128,11 +128,7 @@ static const struct hwseq_private_funcs dcn20_private_funcs = { .dpp_pg_control = dcn20_dpp_pg_control, .hubp_pg_control = dcn20_hubp_pg_control, .update_odm = dcn20_update_odm, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .dsc_pg_control = dcn20_dsc_pg_control, -#else - .dsc_pg_control = NULL, -#endif .set_hdr_multiplier = dcn10_set_hdr_multiplier, .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high, .wait_for_blank_complete = dcn20_wait_for_blank_complete, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.c index 18095ea37a638..e044e9e0a3a17 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_init.c @@ -131,9 +131,7 @@ static const struct hwseq_private_funcs dcn21_private_funcs = { .dpp_pg_control = dcn20_dpp_pg_control, .hubp_pg_control = dcn20_hubp_pg_control, .update_odm = dcn20_update_odm, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .dsc_pg_control = dcn20_dsc_pg_control, -#endif .set_hdr_multiplier = dcn10_set_hdr_multiplier, .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high, .s0i3_golden_init_wa = dcn21_s0i3_golden_init_wa, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c index bf5438c9be761..2a8dc40d28477 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c @@ -137,9 +137,7 @@ static const struct hwseq_private_funcs dcn30_private_funcs = { .hubp_pg_control = dcn20_hubp_pg_control, .program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree, .update_odm = dcn20_update_odm, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .dsc_pg_control = dcn20_dsc_pg_control, -#endif .set_hdr_multiplier = dcn10_set_hdr_multiplier, .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high, .wait_for_blank_complete = dcn20_wait_for_blank_complete, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c index 723fff4b8ac0b..93e49d87a67ce 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c @@ -135,9 +135,7 @@ static const struct hwseq_private_funcs dcn301_private_funcs = { .hubp_pg_control = dcn20_hubp_pg_control, .program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree, .update_odm = dcn20_update_odm, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .dsc_pg_control = dcn20_dsc_pg_control, -#endif .set_hdr_multiplier = dcn10_set_hdr_multiplier, .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high, .wait_for_blank_complete = dcn20_wait_for_blank_complete, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c index 40fad52521647..0a6d58dd8f6da 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.c @@ -156,7 +156,6 @@ void dcn302_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool } } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void dcn302_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on) { uint32_t power_gate = power_on ? 0 : 1; @@ -222,4 +221,3 @@ void dcn302_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool po if (org_ip_request_cntl == 0) REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); } -#endif diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.h index 6317b4a0f363e..1e5126a0e695d 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_hwseq.h @@ -30,8 +30,6 @@ void dcn302_dpp_pg_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool power_on); void dcn302_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool power_on); -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void dcn302_dsc_pg_control(struct dce_hwseq *hws, unsigned int dsc_inst, bool power_on); -#endif #endif /* __DC_HWSS_DCN302_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_init.c index 1602be017597a..637f9514d37b2 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn302/dcn302_init.c @@ -37,7 +37,5 @@ void dcn302_hw_sequencer_construct(struct dc *dc) dc->hwseq->funcs.dpp_pg_control = dcn302_dpp_pg_control; dc->hwseq->funcs.hubp_pg_control = dcn302_hubp_pg_control; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT dc->hwseq->funcs.dsc_pg_control = dcn302_dsc_pg_control; -#endif } diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c index f21171522013c..3d4b31bd99469 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c @@ -276,7 +276,6 @@ void dcn31_init_hw(struct dc *dc) dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch_ver; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void dcn31_dsc_pg_control( struct dce_hwseq *hws, unsigned int dsc_inst, @@ -339,7 +338,6 @@ void dcn31_dsc_pg_control( } } -#endif void dcn31_enable_power_gating_plane( @@ -363,10 +361,8 @@ void dcn31_enable_power_gating_plane( REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); force_on = true; /* disable power gating */ -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (enable && !hws->ctx->dc->debug.disable_dsc_power_gate) force_on = false; -#endif /* DCS0/1/2/3/4/5 */ REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); @@ -521,11 +517,9 @@ static void dcn31_reset_back_end_for_pipe( dc->hwss.set_abm_immediate_disable(pipe_ctx); -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT pipe_ctx->stream_res.tg->funcs->set_dsc_config( pipe_ctx->stream_res.tg, OPTC_DSC_DISABLED, 0, 0); -#endif pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg); pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false); if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c index cb208e2405bca..b57dd45611f23 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c @@ -138,9 +138,7 @@ static const struct hwseq_private_funcs dcn31_private_funcs = { .hubp_pg_control = dcn31_hubp_pg_control, .program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree, .update_odm = dcn20_update_odm, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .dsc_pg_control = dcn31_dsc_pg_control, -#endif .set_hdr_multiplier = dcn10_set_hdr_multiplier, .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high, .wait_for_blank_complete = dcn20_wait_for_blank_complete, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c index fd9fd7d22eb39..4e93eeedfc1bb 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c @@ -195,7 +195,6 @@ void dcn314_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx } } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void dcn314_dsc_pg_control( struct dce_hwseq *hws, unsigned int dsc_inst, @@ -266,7 +265,6 @@ void dcn314_dsc_pg_control( } } -#endif void dcn314_enable_power_gating_plane(struct dce_hwseq *hws, bool enable) { @@ -287,10 +285,8 @@ void dcn314_enable_power_gating_plane(struct dce_hwseq *hws, bool enable) REG_UPDATE(DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); force_on = true; /* disable power gating */ -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (enable && !hws->ctx->dc->debug.disable_dsc_power_gate) force_on = false; -#endif /* DCS0/1/2/3/4 */ REG_UPDATE(DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, force_on); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c index 28e6c89bbeac4..fe5495a8e7a2b 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c @@ -142,9 +142,7 @@ static const struct hwseq_private_funcs dcn314_private_funcs = { .hubp_pg_control = dcn31_hubp_pg_control, .program_all_writeback_pipes_in_tree = dcn30_program_all_writeback_pipes_in_tree, .update_odm = dcn314_update_odm, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .dsc_pg_control = dcn314_dsc_pg_control, -#endif .set_hdr_multiplier = dcn10_set_hdr_multiplier, .verify_allow_pstate_change_high = dcn10_verify_allow_pstate_change_high, .wait_for_blank_complete = dcn20_wait_for_blank_complete, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c index b488885b277ba..4a23eca625f5d 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c @@ -66,7 +66,6 @@ #define FN(reg_name, field_name) \ hws->shifts->field_name, hws->masks->field_name -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void dcn32_dsc_pg_control( struct dce_hwseq *hws, unsigned int dsc_inst, @@ -129,7 +128,6 @@ void dcn32_dsc_pg_control( if (org_ip_request_cntl == 0) REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); } -#endif void dcn32_enable_power_gating_plane( struct dce_hwseq *hws, @@ -1485,7 +1483,6 @@ bool dcn32_dsc_pg_status( return pwr_status == 0; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void dcn32_update_dsc_pg(struct dc *dc, struct dc_state *context, bool safe_to_disable) @@ -1508,7 +1505,6 @@ void dcn32_update_dsc_pg(struct dc *dc, } } } -#endif void dcn32_disable_phantom_streams(struct dc *dc, struct dc_state *context) { diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h index 5b4af3e0acf2f..cac4a08b92a4d 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h @@ -107,11 +107,9 @@ bool dcn32_dsc_pg_status( struct dce_hwseq *hws, unsigned int dsc_inst); -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void dcn32_update_dsc_pg(struct dc *dc, struct dc_state *context, bool safe_to_disable); -#endif void dcn32_enable_phantom_streams(struct dc *dc, struct dc_state *context); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c index 6b0b9b9207cb6..3422b564ae984 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c @@ -115,9 +115,7 @@ static const struct hw_sequencer_funcs dcn32_funcs = { .update_visual_confirm_color = dcn10_update_visual_confirm_color, .subvp_pipe_control_lock_fast = dcn32_subvp_pipe_control_lock_fast, .update_phantom_vp_position = dcn32_update_phantom_vp_position, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .update_dsc_pg = dcn32_update_dsc_pg, -#endif .apply_update_flags_for_phantom = dcn32_apply_update_flags_for_phantom, .blank_phantom = dcn32_blank_phantom, .is_pipe_topology_transition_seamless = dcn32_is_pipe_topology_transition_seamless, diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index b67cf5c01fe31..805b25676734e 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -201,11 +201,9 @@ struct resource_funcs { const struct resource_pool *pool, struct dc_3dlut **lut, struct dc_transfer_func **shaper); -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT enum dc_status (*add_dsc_to_stream_resource)( struct dc *dc, struct dc_state *state, struct dc_stream_state *stream); -#endif void (*add_phantom_pipes)( struct dc *dc, @@ -251,9 +249,7 @@ struct resource_pool { unsigned int gsl_2:1; } gsl_groups; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT struct display_stream_compressor *dscs[MAX_PIPES]; -#endif unsigned int pipe_count; unsigned int underlay_pipe_index; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h index 6210dc83601aa..af9183f5d69be 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h @@ -89,7 +89,6 @@ struct link_encoder { bool usbc_combo_phy; }; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT struct link_enc_state { uint32_t dphy_fec_en; @@ -98,7 +97,6 @@ struct link_enc_state { uint32_t dp_link_training_complete; }; -#endif enum encoder_type_select { ENCODER_TYPE_DIG = 0, @@ -107,10 +105,8 @@ enum encoder_type_select { }; struct link_encoder_funcs { -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void (*read_state)( struct link_encoder *enc, struct link_enc_state *s); -#endif bool (*validate_output_with_stream)( struct link_encoder *enc, const struct dc_stream_state *stream); void (*hw_init)(struct link_encoder *enc); diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h index 069aa15771b49..3d4c8bd42b492 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h @@ -136,9 +136,7 @@ struct crc_params { enum crc_selection selection; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT uint8_t dsc_mode; -#endif uint8_t odm_mode; bool continuous_mode; diff --git a/drivers/gpu/drm/amd/display/dc/inc/link.h b/drivers/gpu/drm/amd/display/dc/inc/link.h index 72a8479e1f2d7..dadedc2ccdcba 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/link.h +++ b/drivers/gpu/drm/amd/display/dc/inc/link.h @@ -164,7 +164,6 @@ struct link_service { bool (*set_dsc_enable)(struct pipe_ctx *pipe_ctx, bool enable); bool (*update_dsc_config)(struct pipe_ctx *pipe_ctx); - /*************************** DDC **************************************/ struct ddc_service *(*create_ddc_service)( struct ddc_service_init_data *ddc_init_data); @@ -223,9 +222,9 @@ struct link_service { const struct link_resource *link_res, struct link_training_settings *lt_settings); void (*dpcd_write_rx_power_ctrl)(struct dc_link *link, bool on); + - - /*************************** DP IRQ Handler ***************************/ + /*************************** DP IRQ Handler ***************************/ bool (*dp_parse_link_loss_status)( struct dc_link *link, union hpd_irq_data *hpd_irq_dpcd_data); diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c index e7a9b09c750d4..6ea0d9894741d 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c @@ -759,7 +759,6 @@ static void dsc_optc_config_log(struct display_stream_compressor *dsc, DC_LOG_DSC("\tslice_width %d", config->slice_width); } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable) { struct dc *dc = pipe_ctx->stream->ctx->dc; @@ -772,7 +771,6 @@ static bool dp_set_dsc_on_rx(struct pipe_ctx *pipe_ctx, bool enable) result = dm_helpers_dp_write_dsc_enable(dc->ctx, stream, enable); return result; } -#endif /* The stream with these settings can be sent (unblanked) only after DSC was enabled on RX first, * i.e. after dp_enable_dsc_on_rx() had been called @@ -984,7 +982,6 @@ bool link_set_dsc_pps_packet(struct pipe_ctx *pipe_ctx, bool enable, bool immedi return true; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT bool link_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable) { struct display_stream_compressor *dsc = pipe_ctx->stream_res.dsc; @@ -1008,7 +1005,6 @@ bool link_set_dsc_enable(struct pipe_ctx *pipe_ctx, bool enable) out: return result; } -#endif bool link_update_dsc_config(struct pipe_ctx *pipe_ctx) { @@ -1893,9 +1889,7 @@ static void disable_link_dp(struct dc_link *link, const struct link_resource *link_res, enum signal_type signal) { -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT struct dc_link_settings link_settings = link->cur_link_settings; -#endif if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST && link->mst_stream_alloc_table.stream_count > 0) @@ -1912,13 +1906,11 @@ static void disable_link_dp(struct dc_link *link, if (signal == SIGNAL_TYPE_DISPLAY_PORT_MST) /* set the sink to SST mode after disabling the link */ enable_mst_on_sink(link, false); -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (link_dp_get_encoding_format(&link_settings) == DP_8b_10b_ENCODING) { dp_set_fec_enable(link, false); dp_set_fec_ready(link, link_res, false); } -#endif } static void disable_link(struct dc_link *link, @@ -2534,13 +2526,11 @@ void link_set_dpms_on( * will be automatically set at a later time when the video is enabled * (DP_VID_STREAM_EN = 1). */ -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (pipe_ctx->stream->timing.flags.DSC) { if (dc_is_dp_signal(pipe_ctx->stream->signal) || dc_is_virtual_signal(pipe_ctx->stream->signal)) link_set_dsc_enable(pipe_ctx, true); } -#endif status = enable_link(state, pipe_ctx); if (status != DC_OK) { @@ -2585,7 +2575,6 @@ void link_set_dpms_on( dc->hwss.enable_stream(pipe_ctx); -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* Set DPS PPS SDP (AKA "info frames") */ if (pipe_ctx->stream->timing.flags.DSC) { if (dc_is_dp_signal(pipe_ctx->stream->signal) || @@ -2594,7 +2583,6 @@ void link_set_dpms_on( link_set_dsc_pps_packet(pipe_ctx, true, true); } } -#endif if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) allocate_usb4_bandwidth(pipe_ctx->stream); diff --git a/drivers/gpu/drm/amd/display/dc/link/link_validation.c b/drivers/gpu/drm/amd/display/dc/link/link_validation.c index 914763fe8259d..0b3e4f596cc2a 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_validation.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_validation.c @@ -136,14 +136,9 @@ static bool dp_active_dongle_validate_timing( return false; } } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (dpcd_caps->channel_coding_cap.bits.DP_128b_132b_SUPPORTED == 0 && dpcd_caps->dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_PASSTHROUGH_SUPPORT == 0 && dongle_caps->dfp_cap_ext.supported) { -#else - if (dongle_caps->dfp_cap_ext.supported) { -#endif - if (dongle_caps->dfp_cap_ext.max_pixel_rate_in_mps < (timing->pix_clk_100hz / 10000)) return false; @@ -237,12 +232,10 @@ uint32_t dp_link_bandwidth_kbps( */ link_rate_per_lane_kbps = link_settings->link_rate * LINK_RATE_REF_FREQ_IN_KHZ * BITS_PER_DP_BYTE; total_data_bw_efficiency_x10000 = DATA_EFFICIENCY_8b_10b_x10000; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (dp_should_enable_fec(link)) { total_data_bw_efficiency_x10000 /= 100; total_data_bw_efficiency_x10000 *= DATA_EFFICIENCY_8b_10b_FEC_EFFICIENCY_x100; } -#endif break; case DP_128b_132b_ENCODING: /* For 128b/132b encoding: diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c index b715f256cbe10..70dc293aa11ad 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c @@ -425,7 +425,6 @@ static enum dc_link_rate get_lttpr_max_link_rate(struct dc_link *link) return lttpr_max_link_rate; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static enum dc_link_rate get_cable_max_link_rate(struct dc_link *link) { enum dc_link_rate cable_max_link_rate = LINK_RATE_UNKNOWN; @@ -445,7 +444,6 @@ static enum dc_link_rate get_cable_max_link_rate(struct dc_link *link) return cable_max_link_rate; } -#endif static inline bool reached_minimum_lane_count(enum dc_lane_count lane_count) { @@ -778,7 +776,7 @@ bool edp_decide_link_settings(struct dc_link *link, return false; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT + bool decide_edp_link_settings_with_dsc(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw, @@ -919,7 +917,6 @@ bool decide_edp_link_settings_with_dsc(struct dc_link *link, } return false; } -#endif static bool decide_mst_link_settings(const struct dc_link *link, struct dc_link_settings *link_setting) { @@ -1837,7 +1834,6 @@ static bool retrieve_link_cap(struct dc_link *link) } } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT memset(&link->dpcd_caps.dsc_caps, '\0', sizeof(link->dpcd_caps.dsc_caps)); memset(&link->dpcd_caps.fec_cap, '\0', sizeof(link->dpcd_caps.fec_cap)); @@ -1899,7 +1895,6 @@ static bool retrieve_link_cap(struct dc_link *link) } else link->wa_flags.dpia_forced_tbt3_mode = false; } -#endif if (!dpcd_read_sink_ext_caps(link)) link->dpcd_sink_ext_caps.raw = 0; @@ -2095,9 +2090,7 @@ struct dc_link_settings dp_get_max_link_cap(struct dc_link *link) { struct dc_link_settings max_link_cap = {0}; enum dc_link_rate lttpr_max_link_rate; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT enum dc_link_rate cable_max_link_rate; -#endif struct link_encoder *link_enc = NULL; bool is_uhbr13_5_supported = true; diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.h b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.h index 1725724983afb..8f0ce97f23621 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.h +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.h @@ -77,12 +77,10 @@ bool link_decide_link_settings( bool edp_decide_link_settings(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw); -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT bool decide_edp_link_settings_with_dsc(struct dc_link *link, struct dc_link_settings *link_setting, uint32_t req_bw, enum dc_link_rate max_link_rate); -#endif enum dp_link_encoding mst_decide_link_encoding_format(const struct dc_link *link); diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c index 6bcace78e4124..bafa52a0165a0 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.c @@ -134,7 +134,6 @@ void dp_set_drive_settings( dpcd_set_lane_settings(link, lt_settings, DPRX); } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT enum dc_status dp_set_fec_ready(struct dc_link *link, const struct link_resource *link_res, bool ready) { /* FEC has to be "set ready" before the link training. @@ -174,7 +173,6 @@ enum dc_status dp_set_fec_ready(struct dc_link *link, const struct link_resource return status; } -#endif void dp_set_fec_enable(struct dc_link *link, bool enable) { diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.h b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.h index 6b46193296237..c67665395712b 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.h +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_phy.h @@ -48,10 +48,8 @@ void dp_set_drive_settings( struct dc_link *link, const struct link_resource *link_res, struct link_training_settings *lt_settings); -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT enum dc_status dp_set_fec_ready(struct dc_link *link, const struct link_resource *link_res, bool ready); -#endif void dp_set_fec_enable(struct dc_link *link, bool enable); void dpcd_write_rx_power_ctrl(struct dc_link *link, bool on); diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c index 65cc1a1af9aaf..c9de5d5f2c3ca 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c @@ -741,10 +741,8 @@ void override_training_settings( if (overrides->enhanced_framing != NULL) lt_settings->enhanced_framing = *overrides->enhanced_framing; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (link->preferred_training_settings.fec_enable != NULL) lt_settings->should_set_fec_ready = *link->preferred_training_settings.fec_enable; -#endif /* Check DP tunnel LTTPR mode debug option. */ if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && link->dc->debug.dpia_debug.bits.force_non_lttpr) @@ -1507,9 +1505,7 @@ enum link_training_result dp_perform_link_training( /* configure link prior to entering training mode */ dpcd_configure_lttpr_mode(link, <_settings); -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT dp_set_fec_ready(link, link_res, lt_settings.should_set_fec_ready); -#endif dpcd_configure_channel_coding(link, <_settings); /* enter training mode: diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c index 7841cabfd7948..2b4c15b0b4070 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c @@ -115,9 +115,7 @@ void decide_8b_10b_training_settings( lt_settings->pattern_for_cr = decide_cr_training_pattern(link_setting); lt_settings->pattern_for_eq = decide_eq_training_pattern(link, link_setting); lt_settings->enhanced_framing = 1; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT lt_settings->should_set_fec_ready = true; -#endif lt_settings->disallow_per_lane_settings = true; lt_settings->always_match_dpcd_with_hw_lane_settings = true; lt_settings->lttpr_mode = dp_decide_8b_10b_lttpr_mode(link); diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c index bacf79bd77fe8..cd1975c03f38d 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c @@ -104,9 +104,7 @@ static enum link_training_result dpia_configure_link( struct link_training_settings *lt_settings) { enum dc_status status; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT bool fec_enable; -#endif DC_LOG_HW_LINK_TRAINING("%s\n DPIA(%d) configuring\n - LTTPR mode(%d)\n", __func__, @@ -134,7 +132,6 @@ static enum link_training_result dpia_configure_link( if (status != DC_OK && link->is_hpd_pending) return LINK_TRAINING_ABORT; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (link->preferred_training_settings.fec_enable != NULL) fec_enable = *link->preferred_training_settings.fec_enable; else @@ -142,7 +139,6 @@ static enum link_training_result dpia_configure_link( status = dp_set_fec_ready(link, link_res, fec_enable); if (status != DC_OK && link->is_hpd_pending) return LINK_TRAINING_ABORT; -#endif return LINK_TRAINING_SUCCESS; } diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c index 55726b8b233e9..bf820d2b4dc4a 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c @@ -351,14 +351,10 @@ bool edp_is_ilr_optimization_required(struct dc_link *link, req_bw = dc_bandwidth_in_kbps_from_timing(crtc_timing, dc_link_get_highest_encoding_format(link)); -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (!crtc_timing->flags.DSC) edp_decide_link_settings(link, &link_setting, req_bw); else decide_edp_link_settings_with_dsc(link, &link_setting, req_bw, LINK_RATE_UNKNOWN); -#else - dc_link_decide_edp_link_settings(link, &link_setting, req_bw); -#endif if (link->dpcd_caps.edp_supported_link_rates[link_rate_set] != link_setting.link_rate || lane_count_set.bits.LANE_COUNT_SET != link_setting.lane_count) { diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c index 3ced93c471b4e..b4694985a40a4 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c @@ -124,7 +124,6 @@ void optc2_set_gsl_source_select( } } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* Set DSC-related configuration. * dsc_mode: 0 disables DSC, other values enable DSC in specified format * sc_bytes_per_pixel: Bytes per pixel in u3.28 format @@ -146,7 +145,6 @@ void optc2_set_dsc_config(struct timing_generator *optc, REG_UPDATE(OPTC_WIDTH_CONTROL, OPTC_DSC_SLICE_WIDTH, dsc_slice_width); } -#endif /* Get DSC-related configuration. * dsc_mode: 0 disables DSC, other values enable DSC in specified format @@ -489,14 +487,9 @@ bool optc2_configure_crc(struct timing_generator *optc, { struct optc *optc1 = DCN10TG_FROM_TG(optc); -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT REG_SET_2(OTG_CRC_CNTL2, 0, OTG_CRC_DSC_MODE, params->dsc_mode, OTG_CRC_DATA_STREAM_COMBINE_MODE, params->odm_mode); -#else - REG_SET(OTG_CRC_CNTL2, 0, - OTG_CRC_DATA_STREAM_COMBINE_MODE, params->odm_mode); -#endif return optc1_configure_crc(optc, params); } @@ -555,9 +548,7 @@ static struct timing_generator_funcs dcn20_tg_funcs = { .setup_global_swap_lock = NULL, .get_crc = optc1_get_crc, .configure_crc = optc2_configure_crc, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .set_dsc_config = optc2_set_dsc_config, -#endif .get_dsc_status = optc2_get_dsc_status, .set_dwb_source = optc2_set_dwb_source, .set_odm_bypass = optc2_set_odm_bypass, diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h index 3b6fce749372d..364034b190281 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h @@ -93,12 +93,10 @@ void optc2_set_gsl_source_select(struct timing_generator *optc, int group_idx, uint32_t gsl_ready_signal); -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void optc2_set_dsc_config(struct timing_generator *optc, enum optc_dsc_mode dsc_mode, uint32_t dsc_bytes_per_pixel, uint32_t dsc_slice_width); -#endif void optc2_get_dsc_status(struct timing_generator *optc, uint32_t *dsc_mode); diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c index 1637b5064a267..49c2efdfa403a 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn201/dcn201_optc.c @@ -172,9 +172,7 @@ static struct timing_generator_funcs dcn201_tg_funcs = { .clear_optc_underflow = optc1_clear_optc_underflow, .get_crc = optc1_get_crc, .configure_crc = optc2_configure_crc, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .set_dsc_config = optc2_set_dsc_config, -#endif .set_dwb_source = NULL, .get_optc_source = optc201_get_optc_source, .set_vtg_params = optc1_set_vtg_params, diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c index 55be7da0cf34d..abcd03d786684 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c @@ -176,7 +176,6 @@ void optc3_set_vtotal_change_limit(struct timing_generator *optc, } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* Set DSC-related configuration. * dsc_mode: 0 disables DSC, other values enable DSC in specified format * sc_bytes_per_pixel: Bytes per pixel in u3.28 format @@ -192,7 +191,6 @@ void optc3_set_dsc_config(struct timing_generator *optc, optc2_set_dsc_config(optc, dsc_mode, dsc_bytes_per_pixel, dsc_slice_width); REG_UPDATE(OTG_V_SYNC_A_CNTL, OTG_V_SYNC_MODE, 0); } -#endif void optc3_set_odm_bypass(struct timing_generator *optc, const struct dc_crtc_timing *dc_crtc_timing) @@ -360,9 +358,7 @@ static struct timing_generator_funcs dcn30_tg_funcs = { .setup_global_swap_lock = NULL, .get_crc = optc1_get_crc, .configure_crc = optc2_configure_crc, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .set_dsc_config = optc3_set_dsc_config, -#endif .get_dsc_status = optc2_get_dsc_status, .set_dwb_source = NULL, .set_odm_bypass = optc3_set_odm_bypass, diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h index 05e1660963709..bda974d432ea6 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h @@ -342,12 +342,10 @@ void optc3_program_blank_color(struct timing_generator *optc, void optc3_set_vtotal_change_limit(struct timing_generator *optc, uint32_t limit); -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void optc3_set_dsc_config(struct timing_generator *optc, enum optc_dsc_mode dsc_mode, uint32_t dsc_bytes_per_pixel, uint32_t dsc_slice_width); -#endif void optc3_set_timing_db_mode(struct timing_generator *optc, bool enable); diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c index 5822ceff727ab..4b6446ed4ce47 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.c @@ -289,9 +289,7 @@ static struct timing_generator_funcs dcn31_tg_funcs = { .setup_global_swap_lock = NULL, .get_crc = optc1_get_crc, .configure_crc = optc2_configure_crc, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .set_dsc_config = optc3_set_dsc_config, -#endif .get_dsc_status = optc2_get_dsc_status, .set_dwb_source = NULL, .set_odm_bypass = optc3_set_odm_bypass, diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c index 05c8ecdb0ef18..633d62addd4d2 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.c @@ -237,9 +237,7 @@ static struct timing_generator_funcs dcn314_tg_funcs = { .setup_global_swap_lock = NULL, .get_crc = optc1_get_crc, .configure_crc = optc1_configure_crc, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .set_dsc_config = optc3_set_dsc_config, -#endif .get_dsc_status = optc2_get_dsc_status, .set_dwb_source = NULL, .get_optc_source = optc2_get_optc_source, diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c index 56434a0859bbb..8c5727d81c1c4 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c @@ -356,9 +356,7 @@ static struct timing_generator_funcs dcn32_tg_funcs = { .setup_global_swap_lock = NULL, .get_crc = optc1_get_crc, .configure_crc = optc1_configure_crc, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .set_dsc_config = optc3_set_dsc_config, -#endif .get_dsc_status = optc2_get_dsc_status, .set_dwb_source = NULL, .set_odm_bypass = optc32_set_odm_bypass, diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c index f81307a2d4780..7d14b6538ebb1 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c @@ -618,7 +618,6 @@ static int map_transmitter_id_to_phy_instance( } } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #define dsc_regsDCN20(id)\ [id] = {\ DSC_REG_LIST_DCN20(id)\ @@ -640,7 +639,6 @@ static const struct dcn20_dsc_shift dsc_shift = { static const struct dcn20_dsc_mask dsc_mask = { DSC_REG_LIST_SH_MASK_DCN20(_MASK) }; -#endif static const struct dccg_registers dccg_regs = { DCCG_REG_LIST_DCN2() @@ -664,9 +662,7 @@ static const struct resource_caps res_cap_nv10 = { .num_dwb = 1, .num_ddc = 6, .num_vmid = 16, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .num_dsc = 6, -#endif }; static const struct dc_plane_cap plane_cap = { @@ -704,9 +700,7 @@ static const struct resource_caps res_cap_nv14 = { .num_dwb = 1, .num_ddc = 5, .num_vmid = 16, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .num_dsc = 5, -#endif }; static const struct dc_debug_options debug_defaults_drv = { @@ -1063,7 +1057,6 @@ void dcn20_clock_source_destroy(struct clock_source **clk_src) *clk_src = NULL; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT struct display_stream_compressor *dcn20_dsc_create( struct dc_context *ctx, uint32_t inst) { @@ -1084,7 +1077,6 @@ void dcn20_dsc_destroy(struct display_stream_compressor **dsc) kfree(container_of(*dsc, struct dcn20_dsc, base)); *dsc = NULL; } -#endif static void dcn20_resource_destruct(struct dcn20_resource_pool *pool) { @@ -1097,12 +1089,10 @@ static void dcn20_resource_destruct(struct dcn20_resource_pool *pool) } } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } -#endif if (pool->base.mpc != NULL) { kfree(TO_DCN20_MPC(pool->base.mpc)); @@ -1329,7 +1319,6 @@ enum dc_status dcn20_build_mapped_resource(const struct dc *dc, struct dc_state return status; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT void dcn20_acquire_dsc(const struct dc *dc, struct resource_context *res_ctx, struct display_stream_compressor **dsc, @@ -1434,7 +1423,6 @@ static enum dc_status remove_dsc_from_stream_resource(struct dc *dc, else return DC_OK; } -#endif enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream) { @@ -1445,11 +1433,9 @@ enum dc_status dcn20_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, if (result == DC_OK) result = resource_map_phy_clock_resources(dc, new_ctx, dc_stream); -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* Get a DSC if required and available */ if (result == DC_OK && dc_stream->timing.flags.DSC) result = dcn20_add_dsc_to_stream_resource(dc, new_ctx, dc_stream); -#endif if (result == DC_OK) result = dcn20_build_mapped_resource(dc, new_ctx, dc_stream); @@ -1462,9 +1448,7 @@ enum dc_status dcn20_remove_stream_from_ctx(struct dc *dc, struct dc_state *new_ { enum dc_status result = DC_OK; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT result = remove_dsc_from_stream_resource(dc, new_ctx, dc_stream); -#endif return result; } @@ -1503,9 +1487,7 @@ bool dcn20_split_stream_for_odm( next_odm_pipe->plane_res.xfm = pool->transforms[next_odm_pipe->pipe_idx]; next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx]; next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT next_odm_pipe->stream_res.dsc = NULL; -#endif if (prev_odm_pipe->next_odm_pipe && prev_odm_pipe->next_odm_pipe != next_odm_pipe) { next_odm_pipe->next_odm_pipe = prev_odm_pipe->next_odm_pipe; next_odm_pipe->next_odm_pipe->prev_odm_pipe = next_odm_pipe; @@ -1561,15 +1543,12 @@ bool dcn20_split_stream_for_odm( next_odm_pipe->stream_res.opp = pool->opps[next_odm_pipe->pipe_idx]; else next_odm_pipe->stream_res.opp = next_odm_pipe->top_pipe->stream_res.opp; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (next_odm_pipe->stream->timing.flags.DSC == 1 && !next_odm_pipe->top_pipe) { dcn20_acquire_dsc(dc, res_ctx, &next_odm_pipe->stream_res.dsc, next_odm_pipe->pipe_idx); ASSERT(next_odm_pipe->stream_res.dsc); if (next_odm_pipe->stream_res.dsc == NULL) return false; } -#endif - return true; } @@ -1592,9 +1571,7 @@ void dcn20_split_stream_for_mpc( secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx]; secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx]; secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT secondary_pipe->stream_res.dsc = NULL; -#endif if (primary_pipe->bottom_pipe && primary_pipe->bottom_pipe != secondary_pipe) { ASSERT(!secondary_pipe->bottom_pipe); secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe; @@ -1685,7 +1662,6 @@ void dcn20_set_mcif_arb_params( } } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx) { int i; @@ -1720,7 +1696,6 @@ bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx) } return true; } -#endif struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc, struct resource_context *res_ctx, @@ -1824,10 +1799,8 @@ void dcn20_merge_pipes_for_validate( odm_pipe->bottom_pipe = NULL; odm_pipe->prev_odm_pipe = NULL; odm_pipe->next_odm_pipe = NULL; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (odm_pipe->stream_res.dsc) dcn20_release_dsc(&context->res_ctx, dc->res_pool, &odm_pipe->stream_res.dsc); -#endif /* Clear plane_res and stream_res */ memset(&odm_pipe->plane_res, 0, sizeof(odm_pipe->plane_res)); memset(&odm_pipe->stream_res, 0, sizeof(odm_pipe->stream_res)); @@ -2153,14 +2126,12 @@ bool dcn20_fast_validate_bw( ASSERT(0); } } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* Actual dsc count per stream dsc validation*/ if (!dcn20_validate_dsc(dc, context)) { context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] = DML_FAIL_DSC_VALIDATION_FAILURE; goto validate_fail; } -#endif *vlevel_out = vlevel; @@ -2274,9 +2245,7 @@ static const struct resource_funcs dcn20_res_pool_funcs = { .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, .add_stream_to_ctx = dcn20_add_stream_to_ctx, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, -#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .populate_dml_writeback_from_context = dcn20_populate_dml_writeback_from_context, .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, @@ -2743,7 +2712,6 @@ static bool dcn20_resource_construct( goto create_fail; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { pool->base.dscs[i] = dcn20_dsc_create(ctx, i); if (pool->base.dscs[i] == NULL) { @@ -2752,7 +2720,6 @@ static bool dcn20_resource_construct( goto create_fail; } } -#endif if (!dcn20_dwbc_create(ctx, &pool->base)) { BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h index b1ba01c6d0f05..4cee3fa11a7ff 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.h @@ -132,9 +132,7 @@ int dcn20_validate_apply_pipe_split_flags( void dcn20_release_dsc(struct resource_context *res_ctx, const struct resource_pool *pool, struct display_stream_compressor **dsc); -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT bool dcn20_validate_dsc(struct dc *dc, struct dc_state *new_ctx); -#endif void dcn20_split_stream_for_mpc( struct resource_context *res_ctx, const struct resource_pool *pool, diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c index 610ac22626430..fc54483b91047 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn201/dcn201_resource.c @@ -1073,9 +1073,7 @@ static struct resource_funcs dcn201_res_pool_funcs = { .validate_bandwidth = dcn20_validate_bandwidth, .populate_dml_pipes = dcn20_populate_dml_pipes_from_context, .add_stream_to_ctx = dcn20_add_stream_to_ctx, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = NULL, -#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .acquire_free_pipe_as_secondary_dpp_pipe = dcn201_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c index b6289060027eb..228fe25077a7d 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c @@ -362,7 +362,6 @@ static const struct dcn20_vmid_mask vmid_masks = { DCN20_VMID_MASK_SH_LIST(_MASK) }; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #define dsc_regsDCN20(id)\ [id] = {\ DSC_REG_LIST_DCN20(id)\ @@ -384,7 +383,6 @@ static const struct dcn20_dsc_shift dsc_shift = { static const struct dcn20_dsc_mask dsc_mask = { DSC_REG_LIST_SH_MASK_DCN20(_MASK) }; -#endif #define ipp_regs(id)\ [id] = {\ @@ -580,9 +578,7 @@ static const struct resource_caps res_cap_rn = { .num_dwb = 1, .num_ddc = 5, .num_vmid = 16, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .num_dsc = 3, -#endif }; static const struct dc_plane_cap plane_cap = { @@ -666,12 +662,10 @@ static void dcn21_resource_destruct(struct dcn21_resource_pool *pool) } } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } -#endif if (pool->base.mpc != NULL) { kfree(TO_DCN20_MPC(pool->base.mpc)); @@ -906,14 +900,12 @@ bool dcn21_fast_validate_bw(struct dc *dc, ASSERT(0); } } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* Actual dsc count per stream dsc validation*/ if (!dcn20_validate_dsc(dc, context)) { context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] = DML_FAIL_DSC_VALIDATION_FAILURE; goto validate_fail; } -#endif *vlevel_out = vlevel; @@ -1094,7 +1086,6 @@ static void read_dce_straps( } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static struct display_stream_compressor *dcn21_dsc_create(struct dc_context *ctx, uint32_t inst) { @@ -1109,7 +1100,6 @@ static struct display_stream_compressor *dcn21_dsc_create(struct dc_context *ctx dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); return &dsc->base; } -#endif static struct pp_smu_funcs *dcn21_pp_smu_create(struct dc_context *ctx) { @@ -1378,9 +1368,7 @@ static const struct resource_funcs dcn21_res_pool_funcs = { .validate_bandwidth = dcn21_validate_bandwidth, .populate_dml_pipes = dcn21_populate_dml_pipes_from_context, .add_stream_to_ctx = dcn20_add_stream_to_ctx, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, -#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, @@ -1664,7 +1652,6 @@ static bool dcn21_resource_construct( goto create_fail; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { pool->base.dscs[i] = dcn21_dsc_create(ctx, i); if (pool->base.dscs[i] == NULL) { @@ -1673,7 +1660,6 @@ static bool dcn21_resource_construct( goto create_fail; } } -#endif if (!dcn20_dwbc_create(ctx, &pool->base)) { BREAK_TO_DEBUGGER(); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c index 9f1678716f5f6..5040a4c6ed186 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c @@ -46,9 +46,7 @@ #include "dcn30/dcn30_hwseq.h" #include "dce110/dce110_hwseq.h" #include "dcn30/dcn30_opp.h" -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include "dcn20/dcn20_dsc.h" -#endif #include "dcn30/dcn30_vpg.h" #include "dcn30/dcn30_afmt.h" #include "dcn30/dcn30_dio_stream_encoder.h" @@ -513,7 +511,6 @@ static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { DSC_REG_LIST_DCN20(id)\ } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static const struct dcn20_dsc_registers dsc_regs[] = { dsc_regsDCN20(0), dsc_regsDCN20(1), @@ -530,7 +527,6 @@ static const struct dcn20_dsc_shift dsc_shift = { static const struct dcn20_dsc_mask dsc_mask = { DSC_REG_LIST_SH_MASK_DCN20(_MASK) }; -#endif static const struct dcn30_mpc_registers mpc_regs = { MPC_REG_LIST_DCN3_0(0), @@ -681,9 +677,7 @@ static const struct resource_caps res_cap_dcn3 = { .num_ddc = 6, .num_vmid = 16, .num_mpc_3dlut = 3, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .num_dsc = 6, -#endif }; static const struct dc_plane_cap plane_cap = { @@ -1088,12 +1082,10 @@ static void dcn30_resource_destruct(struct dcn30_resource_pool *pool) } } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } -#endif if (pool->base.mpc != NULL) { kfree(TO_DCN20_MPC(pool->base.mpc)); @@ -1271,7 +1263,6 @@ static bool dcn30_mmhubbub_create(struct dc_context *ctx, struct resource_pool * return true; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static struct display_stream_compressor *dcn30_dsc_create( struct dc_context *ctx, uint32_t inst) { @@ -1286,7 +1277,6 @@ static struct display_stream_compressor *dcn30_dsc_create( dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); return &dsc->base; } -#endif enum dc_status dcn30_add_stream_to_ctx(struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *dc_stream) { @@ -1547,9 +1537,7 @@ static bool dcn30_split_stream_for_mpc_or_odm( sec_pipe->plane_res.xfm = pool->transforms[pipe_idx]; sec_pipe->plane_res.dpp = pool->dpps[pipe_idx]; sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT sec_pipe->stream_res.dsc = NULL; -#endif if (odm) { if (pri_pipe->next_odm_pipe) { ASSERT(pri_pipe->next_odm_pipe != sec_pipe); @@ -1571,14 +1559,12 @@ static bool dcn30_split_stream_for_mpc_or_odm( sec_pipe->stream_res.opp = pool->opps[pipe_idx]; else sec_pipe->stream_res.opp = sec_pipe->top_pipe->stream_res.opp; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (sec_pipe->stream->timing.flags.DSC == 1) { dcn20_acquire_dsc(dc, res_ctx, &sec_pipe->stream_res.dsc, pipe_idx); ASSERT(sec_pipe->stream_res.dsc); if (sec_pipe->stream_res.dsc == NULL) return false; } -#endif } else { if (pri_pipe->bottom_pipe) { ASSERT(pri_pipe->bottom_pipe != sec_pipe); @@ -1753,10 +1739,8 @@ noinline bool dcn30_internal_validate_bw( pipe->stream = NULL; pipe->top_pipe = NULL; pipe->prev_odm_pipe = NULL; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (pipe->stream_res.dsc) dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc); -#endif memset(&pipe->plane_res, 0, sizeof(pipe->plane_res)); memset(&pipe->stream_res, 0, sizeof(pipe->stream_res)); repopulate_pipes = true; @@ -1875,13 +1859,11 @@ noinline bool dcn30_internal_validate_bw( } } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* Actual dsc count per stream dsc validation*/ if (!dcn20_validate_dsc(dc, context)) { vba->ValidationStatus[vba->soc.num_states] = DML_FAIL_DSC_VALIDATION_FAILURE; goto validate_fail; } -#endif if (repopulate_pipes) pipe_cnt = dc->res_pool->funcs->populate_dml_pipes(dc, context, pipes, fast_validate); @@ -2259,9 +2241,7 @@ static const struct resource_funcs dcn30_res_pool_funcs = { .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, .add_stream_to_ctx = dcn30_add_stream_to_ctx, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, -#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, .set_mcif_arb_params = dcn30_set_mcif_arb_params, @@ -2552,7 +2532,6 @@ static bool dcn30_resource_construct( goto create_fail; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { pool->base.dscs[i] = dcn30_dsc_create(ctx, i); if (pool->base.dscs[i] == NULL) { @@ -2561,7 +2540,6 @@ static bool dcn30_resource_construct( goto create_fail; } } -#endif /* DWB and MMHUBBUB */ if (!dcn30_dwbc_create(ctx, &pool->base)) { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c index 75bd9b8dc8dfd..806e563e165b5 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c @@ -47,9 +47,7 @@ #include "dcn30/dcn30_hwseq.h" #include "dce110/dce110_hwseq.h" #include "dcn30/dcn30_opp.h" -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include "dcn20/dcn20_dsc.h" -#endif #include "dcn30/dcn30_vpg.h" #include "dcn30/dcn30_afmt.h" #include "dce/dce_clock_source.h" @@ -491,7 +489,6 @@ static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) }; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #define dsc_regsDCN20(id)\ [id] = {\ DSC_REG_LIST_DCN20(id)\ @@ -510,7 +507,6 @@ static const struct dcn20_dsc_shift dsc_shift = { static const struct dcn20_dsc_mask dsc_mask = { DSC_REG_LIST_SH_MASK_DCN20(_MASK) }; -#endif static const struct dcn30_mpc_registers mpc_regs = { MPC_REG_LIST_DCN3_0(0), @@ -652,9 +648,7 @@ static struct resource_caps res_cap_dcn301 = { .num_ddc = 4, .num_vmid = 16, .num_mpc_3dlut = 2, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .num_dsc = 3, -#endif }; static const struct dc_plane_cap plane_cap = { @@ -1059,12 +1053,10 @@ static void dcn301_destruct(struct dcn301_resource_pool *pool) } } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } -#endif if (pool->base.mpc != NULL) { kfree(TO_DCN20_MPC(pool->base.mpc)); @@ -1231,7 +1223,6 @@ static bool dcn301_mmhubbub_create(struct dc_context *ctx, struct resource_pool return true; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static struct display_stream_compressor *dcn301_dsc_create( struct dc_context *ctx, uint32_t inst) { @@ -1246,7 +1237,6 @@ static struct display_stream_compressor *dcn301_dsc_create( dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); return &dsc->base; } -#endif static void dcn301_destroy_resource_pool(struct resource_pool **pool) { @@ -1402,9 +1392,7 @@ static struct resource_funcs dcn301_res_pool_funcs = { .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, .add_stream_to_ctx = dcn30_add_stream_to_ctx, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, -#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, .set_mcif_arb_params = dcn30_set_mcif_arb_params, @@ -1663,7 +1651,6 @@ static bool dcn301_resource_construct( goto create_fail; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { pool->base.dscs[i] = dcn301_dsc_create(ctx, i); if (pool->base.dscs[i] == NULL) { @@ -1672,7 +1659,6 @@ static bool dcn301_resource_construct( goto create_fail; } } -#endif /* DWB and MMHUBBUB */ if (!dcn301_dwbc_create(ctx, &pool->base)) { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c index 00995cd380fe7..5791b5cc28752 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c @@ -40,9 +40,7 @@ #include "dcn30/dcn30_optc.h" #include "dcn30/dcn30_resource.h" -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include "dcn20/dcn20_dsc.h" -#endif #include "dcn20/dcn20_resource.h" #include "dml/dcn30/dcn30_fpu.h" @@ -131,9 +129,7 @@ static const struct resource_caps res_cap_dcn302 = { .num_ddc = 5, .num_vmid = 16, .num_mpc_3dlut = 2, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .num_dsc = 5, -#endif }; static const struct dc_plane_cap plane_cap = { @@ -662,7 +658,6 @@ static struct mpc *dcn302_mpc_create(struct dc_context *ctx, int num_mpcc, int n return &mpc30->base; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #define dsc_regsDCN20(id)\ [id] = { DSC_REG_LIST_DCN20(id) } @@ -694,7 +689,6 @@ static struct display_stream_compressor *dcn302_dsc_create(struct dc_context *ct dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); return &dsc->base; } -#endif #define dwbc_regs_dcn3(id)\ [id] = { DWBC_COMMON_REG_LIST_DCN30(id) } @@ -1010,12 +1004,10 @@ static void dcn302_resource_destruct(struct resource_pool *pool) } } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->res_cap->num_dsc; i++) { if (pool->dscs[i] != NULL) dcn20_dsc_destroy(&pool->dscs[i]); } -#endif if (pool->mpc != NULL) { kfree(TO_DCN20_MPC(pool->mpc)); @@ -1150,9 +1142,7 @@ static struct resource_funcs dcn302_res_pool_funcs = { .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, .add_stream_to_ctx = dcn30_add_stream_to_ctx, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, -#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, .set_mcif_arb_params = dcn30_set_mcif_arb_params, @@ -1438,7 +1428,6 @@ static bool dcn302_resource_construct( goto create_fail; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->res_cap->num_dsc; i++) { pool->dscs[i] = dcn302_dsc_create(ctx, i); if (pool->dscs[i] == NULL) { @@ -1447,7 +1436,6 @@ static bool dcn302_resource_construct( goto create_fail; } } -#endif /* DWB and MMHUBBUB */ if (!dcn302_dwbc_create(ctx, pool)) { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c index 38053ce302cd4..63f0f882c8610 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c @@ -127,9 +127,7 @@ static const struct resource_caps res_cap_dcn303 = { .num_ddc = 2, .num_vmid = 16, .num_mpc_3dlut = 1, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .num_dsc = 2, -#endif }; static const struct dc_plane_cap plane_cap = { @@ -625,7 +623,6 @@ static struct mpc *dcn303_mpc_create(struct dc_context *ctx, int num_mpcc, int n return &mpc30->base; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #define dsc_regsDCN20(id)\ [id] = { DSC_REG_LIST_DCN20(id) } @@ -654,7 +651,6 @@ static struct display_stream_compressor *dcn303_dsc_create(struct dc_context *ct dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); return &dsc->base; } -#endif #define dwbc_regs_dcn3(id)\ [id] = { DWBC_COMMON_REG_LIST_DCN30(id) } @@ -953,12 +949,10 @@ static void dcn303_resource_destruct(struct resource_pool *pool) } } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->res_cap->num_dsc; i++) { if (pool->dscs[i] != NULL) dcn20_dsc_destroy(&pool->dscs[i]); } -#endif if (pool->mpc != NULL) { kfree(TO_DCN20_MPC(pool->mpc)); @@ -1093,9 +1087,7 @@ static struct resource_funcs dcn303_res_pool_funcs = { .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, .add_stream_to_ctx = dcn30_add_stream_to_ctx, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, -#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, .set_mcif_arb_params = dcn30_set_mcif_arb_params, @@ -1369,7 +1361,6 @@ static bool dcn303_resource_construct( goto create_fail; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->res_cap->num_dsc; i++) { pool->dscs[i] = dcn303_dsc_create(ctx, i); if (pool->dscs[i] == NULL) { @@ -1378,7 +1369,6 @@ static bool dcn303_resource_construct( goto create_fail; } } -#endif /* DWB and MMHUBBUB */ if (!dcn303_dwbc_create(ctx, pool)) { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c index bd452d8d5f4aa..ac8cb20e2e3b6 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c @@ -563,7 +563,6 @@ static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) }; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #define dsc_regsDCN20(id)\ [id] = {\ DSC_REG_LIST_DCN20(id)\ @@ -582,7 +581,6 @@ static const struct dcn20_dsc_shift dsc_shift = { static const struct dcn20_dsc_mask dsc_mask = { DSC_REG_LIST_SH_MASK_DCN20(_MASK) }; -#endif static const struct dcn30_mpc_registers mpc_regs = { MPC_REG_LIST_DCN3_0(0), @@ -826,9 +824,7 @@ static const struct resource_caps res_cap_dcn31 = { .num_ddc = 5, .num_vmid = 16, .num_mpc_3dlut = 2, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .num_dsc = 3, -#endif }; static const struct dc_plane_cap plane_cap = { @@ -1387,12 +1383,10 @@ static void dcn31_resource_destruct(struct dcn31_resource_pool *pool) } } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } -#endif if (pool->base.mpc != NULL) { kfree(TO_DCN20_MPC(pool->base.mpc)); @@ -1567,7 +1561,6 @@ static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool * return true; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static struct display_stream_compressor *dcn31_dsc_create( struct dc_context *ctx, uint32_t inst) { @@ -1582,7 +1575,6 @@ static struct display_stream_compressor *dcn31_dsc_create( dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); return &dsc->base; } -#endif static void dcn31_destroy_resource_pool(struct resource_pool **pool) { @@ -1841,9 +1833,7 @@ static struct resource_funcs dcn31_res_pool_funcs = { .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, .add_stream_to_ctx = dcn30_add_stream_to_ctx, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, -#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .populate_dml_writeback_from_context = dcn31_populate_dml_writeback_from_context, .set_mcif_arb_params = dcn31_set_mcif_arb_params, @@ -2137,7 +2127,6 @@ static bool dcn31_resource_construct( goto create_fail; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { pool->base.dscs[i] = dcn31_dsc_create(ctx, i); if (pool->base.dscs[i] == NULL) { @@ -2146,7 +2135,6 @@ static bool dcn31_resource_construct( goto create_fail; } } -#endif /* DWB and MMHUBBUB */ if (!dcn31_dwbc_create(ctx, &pool->base)) { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c index 2b10c2c1d3683..169924d0a8393 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c @@ -574,7 +574,6 @@ static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { DSC_REG_LIST_DCN20(id)\ } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static const struct dcn20_dsc_registers dsc_regs[] = { dsc_regsDCN314(0), dsc_regsDCN314(1), @@ -589,7 +588,6 @@ static const struct dcn20_dsc_shift dsc_shift = { static const struct dcn20_dsc_mask dsc_mask = { DSC_REG_LIST_SH_MASK_DCN20(_MASK) }; -#endif static const struct dcn30_mpc_registers mpc_regs = { MPC_REG_LIST_DCN3_0(0), @@ -1442,12 +1440,10 @@ static void dcn314_resource_destruct(struct dcn314_resource_pool *pool) } } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } -#endif if (pool->base.mpc != NULL) { kfree(TO_DCN20_MPC(pool->base.mpc)); @@ -1621,7 +1617,6 @@ static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool * return true; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static struct display_stream_compressor *dcn314_dsc_create( struct dc_context *ctx, uint32_t inst) { @@ -1636,7 +1631,6 @@ static struct display_stream_compressor *dcn314_dsc_create( dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); return &dsc->base; } -#endif static void dcn314_destroy_resource_pool(struct resource_pool **pool) { @@ -1773,9 +1767,7 @@ static struct resource_funcs dcn314_res_pool_funcs = { .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, .add_stream_to_ctx = dcn30_add_stream_to_ctx, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, -#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, .set_mcif_arb_params = dcn30_set_mcif_arb_params, @@ -2063,7 +2055,6 @@ static bool dcn314_resource_construct( goto create_fail; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { pool->base.dscs[i] = dcn314_dsc_create(ctx, i); if (pool->base.dscs[i] == NULL) { @@ -2072,7 +2063,6 @@ static bool dcn314_resource_construct( goto create_fail; } } -#endif /* DWB and MMHUBBUB */ if (!dcn31_dwbc_create(ctx, &pool->base)) { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c index 65d9bc4c262ea..3f4b9dba41124 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c @@ -49,9 +49,7 @@ #include "dcn30/dcn30_hwseq.h" #include "dce110/dce110_hwseq.h" #include "dcn30/dcn30_opp.h" -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include "dcn20/dcn20_dsc.h" -#endif #include "dcn30/dcn30_vpg.h" #include "dcn30/dcn30_afmt.h" #include "dcn30/dcn30_dio_stream_encoder.h" @@ -568,7 +566,6 @@ static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { MCIF_WB_COMMON_MASK_SH_LIST_DCN30(_MASK) }; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #define dsc_regsDCN20(id)\ [id] = {\ DSC_REG_LIST_DCN20(id)\ @@ -587,7 +584,6 @@ static const struct dcn20_dsc_shift dsc_shift = { static const struct dcn20_dsc_mask dsc_mask = { DSC_REG_LIST_SH_MASK_DCN20(_MASK) }; -#endif static const struct dcn30_mpc_registers mpc_regs = { MPC_REG_LIST_DCN3_0(0), @@ -827,9 +823,7 @@ static const struct resource_caps res_cap_dcn31 = { .num_ddc = 5, .num_vmid = 16, .num_mpc_3dlut = 2, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .num_dsc = 3, -#endif }; static const struct dc_plane_cap plane_cap = { @@ -1389,12 +1383,10 @@ static void dcn315_resource_destruct(struct dcn315_resource_pool *pool) } } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } -#endif if (pool->base.mpc != NULL) { kfree(TO_DCN20_MPC(pool->base.mpc)); @@ -1569,7 +1561,6 @@ static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool * return true; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static struct display_stream_compressor *dcn31_dsc_create( struct dc_context *ctx, uint32_t inst) { @@ -1584,7 +1575,6 @@ static struct display_stream_compressor *dcn31_dsc_create( dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); return &dsc->base; } -#endif static void dcn315_destroy_resource_pool(struct resource_pool **pool) { @@ -1840,9 +1830,7 @@ static struct resource_funcs dcn315_res_pool_funcs = { .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, .add_stream_to_ctx = dcn30_add_stream_to_ctx, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, -#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .populate_dml_writeback_from_context = dcn31_populate_dml_writeback_from_context, .set_mcif_arb_params = dcn31_set_mcif_arb_params, @@ -2093,7 +2081,6 @@ static bool dcn315_resource_construct( goto create_fail; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { pool->base.dscs[i] = dcn31_dsc_create(ctx, i); if (pool->base.dscs[i] == NULL) { @@ -2102,7 +2089,6 @@ static bool dcn315_resource_construct( goto create_fail; } } -#endif /* DWB and MMHUBBUB */ if (!dcn31_dwbc_create(ctx, &pool->base)) { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c index 405661e66d4b9..bed951e7da867 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c @@ -49,9 +49,7 @@ #include "dcn30/dcn30_hwseq.h" #include "dce110/dce110_hwseq.h" #include "dcn30/dcn30_opp.h" -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #include "dcn20/dcn20_dsc.h" -#endif #include "dcn30/dcn30_vpg.h" #include "dcn30/dcn30_afmt.h" #include "dcn30/dcn30_dio_stream_encoder.h" @@ -560,7 +558,6 @@ static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { }; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT #define dsc_regsDCN20(id)\ [id] = {\ DSC_REG_LIST_DCN20(id)\ @@ -579,7 +576,6 @@ static const struct dcn20_dsc_shift dsc_shift = { static const struct dcn20_dsc_mask dsc_mask = { DSC_REG_LIST_SH_MASK_DCN20(_MASK) }; -#endif static const struct dcn30_mpc_registers mpc_regs = { MPC_REG_LIST_DCN3_0(0), @@ -823,9 +819,7 @@ static const struct resource_caps res_cap_dcn31 = { .num_ddc = 5, .num_vmid = 16, .num_mpc_3dlut = 2, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .num_dsc = 3, -#endif }; static const struct dc_plane_cap plane_cap = { @@ -1386,12 +1380,10 @@ static void dcn316_resource_destruct(struct dcn316_resource_pool *pool) } } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } -#endif if (pool->base.mpc != NULL) { kfree(TO_DCN20_MPC(pool->base.mpc)); @@ -1563,7 +1555,6 @@ static bool dcn31_mmhubbub_create(struct dc_context *ctx, struct resource_pool * return true; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static struct display_stream_compressor *dcn31_dsc_create( struct dc_context *ctx, uint32_t inst) { @@ -1578,7 +1569,6 @@ static struct display_stream_compressor *dcn31_dsc_create( dsc2_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask); return &dsc->base; } -#endif static void dcn316_destroy_resource_pool(struct resource_pool **pool) { @@ -1721,9 +1711,7 @@ static struct resource_funcs dcn316_res_pool_funcs = { .acquire_free_pipe_as_secondary_dpp_pipe = dcn20_acquire_free_pipe_for_layer, .release_pipe = dcn20_release_pipe, .add_stream_to_ctx = dcn30_add_stream_to_ctx, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, -#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .populate_dml_writeback_from_context = dcn31_populate_dml_writeback_from_context, .set_mcif_arb_params = dcn31_set_mcif_arb_params, @@ -1966,7 +1954,6 @@ static bool dcn316_resource_construct( goto create_fail; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { pool->base.dscs[i] = dcn31_dsc_create(ctx, i); if (pool->base.dscs[i] == NULL) { @@ -1975,7 +1962,6 @@ static bool dcn316_resource_construct( goto create_fail; } } -#endif /* DWB and MMHUBBUB */ if (!dcn31_dwbc_create(ctx, &pool->base)) { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c index 8695579c4a702..a124ad9bd108c 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c @@ -437,7 +437,6 @@ static const struct dcn30_mmhubbub_mask mcif_wb30_mask = { #define dsc_regsDCN20_init(id)\ DSC_REG_LIST_DCN20_RI(id) -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static struct dcn20_dsc_registers dsc_regs[4]; static const struct dcn20_dsc_shift dsc_shift = { @@ -447,7 +446,6 @@ static const struct dcn20_dsc_shift dsc_shift = { static const struct dcn20_dsc_mask dsc_mask = { DSC_REG_LIST_SH_MASK_DCN20(_MASK) }; -#endif static struct dcn30_mpc_registers mpc_regs; @@ -1389,12 +1387,10 @@ static void dcn32_resource_destruct(struct dcn32_resource_pool *pool) } } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT for (i = 0; i < pool->base.res_cap->num_dsc; i++) { if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } -#endif if (pool->base.mpc != NULL) { kfree(TO_DCN20_MPC(pool->base.mpc)); @@ -1562,7 +1558,6 @@ static bool dcn32_mmhubbub_create(struct dc_context *ctx, struct resource_pool * return true; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static struct display_stream_compressor *dcn32_dsc_create( struct dc_context *ctx, uint32_t inst) { @@ -1587,7 +1582,6 @@ static struct display_stream_compressor *dcn32_dsc_create( return &dsc->base; } -#endif static void dcn32_destroy_resource_pool(struct resource_pool **pool) { @@ -2056,9 +2050,7 @@ static struct resource_funcs dcn32_res_pool_funcs = { .acquire_free_pipe_as_secondary_opp_head = dcn32_acquire_free_pipe_as_secondary_opp_head, .release_pipe = dcn20_release_pipe, .add_stream_to_ctx = dcn30_add_stream_to_ctx, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource, -#endif .remove_stream_from_ctx = dcn20_remove_stream_from_ctx, .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context, .set_mcif_arb_params = dcn30_set_mcif_arb_params, @@ -2401,7 +2393,6 @@ static bool dcn32_resource_construct( goto create_fail; } -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT /* DSCs */ for (i = 0; i < pool->base.res_cap->num_dsc; i++) { pool->base.dscs[i] = dcn32_dsc_create(ctx, i); @@ -2411,7 +2402,6 @@ static bool dcn32_resource_construct( goto create_fail; } } -#endif /* DWB */ if (!dcn32_dwbc_create(ctx, &pool->base)) { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c index eb78191838c7c..f5a4e97c40ced 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c @@ -128,10 +128,8 @@ void dcn32_merge_pipes_for_subvp(struct dc *dc, pipe->stream = NULL; pipe->top_pipe = NULL; pipe->prev_odm_pipe = NULL; -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT if (pipe->stream_res.dsc) dcn20_release_dsc(&context->res_ctx, dc->res_pool, &pipe->stream_res.dsc); -#endif memset(&pipe->plane_res, 0, sizeof(pipe->plane_res)); memset(&pipe->stream_res, 0, sizeof(pipe->stream_res)); } else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c index 827a94f84f100..c401d713ada51 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c @@ -445,7 +445,6 @@ static const struct dcn20_dsc_shift dsc_shift = { static const struct dcn20_dsc_mask dsc_mask = { DSC_REG_LIST_SH_MASK_DCN20(_MASK) }; - static struct dcn30_mpc_registers mpc_regs; #define dcn_mpc_regs_init()\ MPC_REG_LIST_DCN3_2_RI(0),\ @@ -1374,7 +1373,6 @@ static void dcn321_resource_destruct(struct dcn321_resource_pool *pool) if (pool->base.dscs[i] != NULL) dcn20_dsc_destroy(&pool->base.dscs[i]); } - if (pool->base.mpc != NULL) { kfree(TO_DCN20_MPC(pool->base.mpc)); pool->base.mpc = NULL; diff --git a/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c index 0e2688067f329..ad088d70e1893 100644 --- a/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/virtual/virtual_stream_encoder.c @@ -83,12 +83,10 @@ static void virtual_stream_encoder_reset_hdmi_stream_attribute( struct stream_encoder *enc) {} -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static void virtual_enc_dp_set_odm_combine( struct stream_encoder *enc, bool odm_combine) {} -#endif static void virtual_dig_connect_to_otg( struct stream_encoder *enc, @@ -101,20 +99,16 @@ static void virtual_setup_stereo_sync( bool enable) {} -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT static void virtual_stream_encoder_set_dsc_pps_info_packet( struct stream_encoder *enc, bool enable, uint8_t *dsc_packed_pps, bool immediate_update) {} -#endif static const struct stream_encoder_funcs virtual_str_enc_funcs = { -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .dp_set_odm_combine = virtual_enc_dp_set_odm_combine, -#endif .dp_set_stream_attribute = virtual_stream_encoder_dp_set_stream_attribute, .hdmi_set_stream_attribute = @@ -141,9 +135,7 @@ static const struct stream_encoder_funcs virtual_str_enc_funcs = { .hdmi_reset_stream_attribute = virtual_stream_encoder_reset_hdmi_stream_attribute, .dig_connect_to_otg = virtual_dig_connect_to_otg, .setup_stereo_sync = virtual_setup_stereo_sync, -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT .dp_set_dsc_pps_info_packet = virtual_stream_encoder_set_dsc_pps_info_packet, -#endif }; bool virtual_stream_encoder_construct( diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index a0e67352e5b38..c90d2e3182c23 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -204,9 +204,6 @@ ifndef CONFIG_ARM64 ifeq ($(filter %core2, $(KBUILD_CFLAGS)),) export CONFIG_DRM_AMD_DC_DCN=y subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN - -export CONFIG_DRM_AMD_DC_DSC_SUPPORT=y -subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DSC_SUPPORT endif endif diff --git a/include/kcl/kcl_drm_dsc_helper.h b/include/kcl/kcl_drm_dsc_helper.h index 207bc76eb1195..0c61de575753d 100644 --- a/include/kcl/kcl_drm_dsc_helper.h +++ b/include/kcl/kcl_drm_dsc_helper.h @@ -3,8 +3,6 @@ #ifndef _KCL_KCL_DRM_DSC_HELPER_H #define _KCL_KCL_DRM_DSC_HELPER_H -#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT - #include #include @@ -17,6 +15,5 @@ void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp, int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg); #endif -#endif /* CONFIG_DRM_AMD_DC_DSC_SUPPORT */ #endif /* _KCL_KCL_DRM_DSC_HELPER_H */ From 3f239b4dfb564a0665520856887afd54a9649b08 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Fri, 17 Feb 2023 12:44:59 +0800 Subject: [PATCH 0935/1868] drm/amdkcl: kcl-cleanup HAVE_DRM_FRAMEBUFFER_FORMAT Signed-off-by: Leslie Shi Reviewed-by: Ma Jun --- drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 4 ---- drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 17 -------------- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 17 -------------- drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 17 -------------- drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 17 -------------- drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c | 6 +---- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 12 ---------- .../amd/display/amdgpu_dm/amdgpu_dm_plane.c | 23 +------------------ drivers/gpu/drm/amd/dkms/config/config.h | 3 --- .../drm/amd/dkms/m4/drm-framebuffer-format.m4 | 21 ----------------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - 11 files changed, 2 insertions(+), 136 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-framebuffer-format.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c index 1d531c41fa5e6..fa30102663de1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c @@ -276,11 +276,7 @@ static int amdgpufb_create(struct drm_fb_helper *helper, DRM_INFO("fb mappable at 0x%lX\n", info->fix.smem_start); DRM_INFO("vram apper at 0x%lX\n", (unsigned long)adev->gmc.aper_base); DRM_INFO("size %lu\n", (unsigned long)amdgpu_bo_size(abo)); -#if !defined(HAVE_DRM_FRAMEBUFFER_FORMAT) - DRM_INFO("fb depth is %d\n", fb->depth); -#else DRM_INFO("fb depth is %d\n", fb->format->depth); -#endif DRM_INFO("pitch is %d\n", fb->pitches[0]); vga_switcheroo_client_fb_set(adev->pdev, info); diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index 064de11565190..9ab3c77f72034 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -244,13 +244,8 @@ static void dce_v10_0_page_flip(struct amdgpu_device *adev, GRPH_SURFACE_UPDATE_H_RETRACE_EN, async ? 1 : 0); WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); /* update pitch */ -#if defined(HAVE_DRM_FRAMEBUFFER_FORMAT) WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb->pitches[0] / fb->format->cpp[0]); -#else - WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, - fb->pitches[0] / (fb->bits_per_pixel / 8)); -#endif /* update the primary scanout address */ WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, upper_32_bits(crtc_base)); @@ -1905,11 +1900,7 @@ static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc, pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); -#if !defined(HAVE_DRM_FRAMEBUFFER_FORMAT) - switch (target_fb->pixel_format) { -#else switch (target_fb->format->format) { -#endif case DRM_FORMAT_C8: fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0); fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); @@ -1993,11 +1984,7 @@ static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc, break; default: DRM_ERROR("Unsupported screen format %p4cc\n", -#if defined(HAVE_DRM_FRAMEBUFFER_FORMAT) &target_fb->format->format); -#else - &target_fb->pixel_format); -#endif return -EINVAL; } @@ -2072,11 +2059,7 @@ static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc, WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); -#if !defined(HAVE_DRM_FRAMEBUFFER_FORMAT) - fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); -#else fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0]; -#endif WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); dce_v10_0_grph_enable(crtc, true); diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index 5f3afd026394b..612c6c88ef845 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -268,13 +268,8 @@ static void dce_v11_0_page_flip(struct amdgpu_device *adev, GRPH_SURFACE_UPDATE_IMMEDIATE_EN, async ? 1 : 0); WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp); /* update pitch */ -#if defined(HAVE_DRM_FRAMEBUFFER_FORMAT) WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb->pitches[0] / fb->format->cpp[0]); -#else - WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, - fb->pitches[0] / (fb->bits_per_pixel / 8)); -#endif /* update the scanout addresses */ WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, upper_32_bits(crtc_base)); @@ -1955,11 +1950,7 @@ static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc, pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); -#if !defined(HAVE_DRM_FRAMEBUFFER_FORMAT) - switch (target_fb->pixel_format) { -#else switch (target_fb->format->format) { -#endif case DRM_FORMAT_C8: fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0); fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); @@ -2043,11 +2034,7 @@ static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc, break; default: DRM_ERROR("Unsupported screen format %p4cc\n", -#if defined(HAVE_DRM_FRAMEBUFFER_FORMAT) &target_fb->format->format); -#else - &target_fb->pixel_format); -#endif return -EINVAL; } @@ -2122,11 +2109,7 @@ static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc, WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); -#if !defined(HAVE_DRM_FRAMEBUFFER_FORMAT) - fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); -#else fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0]; -#endif WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); dce_v11_0_grph_enable(crtc, true); diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c index db87c4ae6c863..850bad398d140 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c @@ -201,13 +201,8 @@ static void dce_v6_0_page_flip(struct amdgpu_device *adev, WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ? GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0); /* update pitch */ -#if defined(HAVE_DRM_FRAMEBUFFER_FORMAT) WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb->pitches[0] / fb->format->cpp[0]); -#else - WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, - fb->pitches[0] / (fb->bits_per_pixel / 8)); -#endif /* update the scanout addresses */ WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, upper_32_bits(crtc_base)); @@ -1883,11 +1878,7 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc, amdgpu_bo_get_tiling_flags(abo, &tiling_flags); amdgpu_bo_unreserve(abo); -#if !defined(HAVE_DRM_FRAMEBUFFER_FORMAT) - switch (target_fb->pixel_format) { -#else switch (target_fb->format->format) { -#endif case DRM_FORMAT_C8: fb_format = (GRPH_DEPTH(GRPH_DEPTH_8BPP) | GRPH_FORMAT(GRPH_FORMAT_INDEXED)); @@ -1963,11 +1954,7 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc, break; default: DRM_ERROR("Unsupported screen format %p4cc\n", -#if defined(HAVE_DRM_FRAMEBUFFER_FORMAT) &target_fb->format->format); -#else - &target_fb->pixel_format); -#endif return -EINVAL; } @@ -2030,11 +2017,7 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc, WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); -#if !defined(HAVE_DRM_FRAMEBUFFER_FORMAT) - fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); -#else fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0]; -#endif WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); dce_v6_0_grph_enable(crtc, true); diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index eb72dfd75ba03..8d032587fac5c 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -191,13 +191,8 @@ static void dce_v8_0_page_flip(struct amdgpu_device *adev, /* flip at hsync for async, default is vsync */ WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, async ? GRPH_FLIP_CONTROL__GRPH_SURFACE_UPDATE_H_RETRACE_EN_MASK : 0); -#if defined(HAVE_DRM_FRAMEBUFFER_FORMAT) WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb->pitches[0] / fb->format->cpp[0]); -#else - WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, - fb->pitches[0] / (fb->bits_per_pixel / 8)); -#endif /* update the primary scanout addresses */ WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset, upper_32_bits(crtc_base)); @@ -1851,11 +1846,7 @@ static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc, pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); -#if !defined(HAVE_DRM_FRAMEBUFFER_FORMAT) - switch (target_fb->pixel_format) { -#else switch (target_fb->format->format) { -#endif case DRM_FORMAT_C8: fb_format = ((GRPH_DEPTH_8BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | (GRPH_FORMAT_INDEXED << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); @@ -1931,11 +1922,7 @@ static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc, break; default: DRM_ERROR("Unsupported screen format %p4cc\n", -#if defined(HAVE_DRM_FRAMEBUFFER_FORMAT) &target_fb->format->format); -#else - &target_fb->pixel_format); -#endif return -EINVAL; } @@ -1998,11 +1985,7 @@ static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc, WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width); WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height); -#if !defined(HAVE_DRM_FRAMEBUFFER_FORMAT) - fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8); -#else fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0]; -#endif WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels); dce_v8_0_grph_enable(crtc, true); diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c index bdd63a1cc9b36..11e5390896f68 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_fb.c @@ -42,11 +42,7 @@ void drm_fb_helper_fill_info(struct fb_info *info, { struct drm_framebuffer *fb = fb_helper->fb; -#ifdef HAVE_DRM_FRAMEBUFFER_FORMAT drm_fb_helper_fill_fix(info, fb->pitches[0], fb->format->depth); -#else - drm_fb_helper_fill_fix(info, fb->pitches[0], fb->depth); -#endif drm_fb_helper_fill_var(info, fb_helper, sizes->fb_width, sizes->fb_height); @@ -56,4 +52,4 @@ void drm_fb_helper_fill_info(struct fb_info *info, } EXPORT_SYMBOL(drm_fb_helper_fill_info); -#endif \ No newline at end of file +#endif diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index c93c60861d51d..01c455960f318 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -5457,11 +5457,7 @@ fill_dc_plane_info_and_addr(struct amdgpu_device *adev, memset(plane_info, 0, sizeof(*plane_info)); -#ifndef HAVE_DRM_FRAMEBUFFER_FORMAT - switch (fb->pixel_format) { -#else switch (fb->format->format) { -#endif case DRM_FORMAT_C8: plane_info->format = SURFACE_PIXEL_FORMAT_GRPH_PALETA_256_COLORS; @@ -5517,11 +5513,7 @@ fill_dc_plane_info_and_addr(struct amdgpu_device *adev, default: DRM_ERROR( "Unsupported screen format %p4cc\n", -#ifdef HAVE_DRM_FRAMEBUFFER_FORMAT &fb->format->format); -#else - &fb->pixel_format); -#endif return -EINVAL; } @@ -10808,11 +10800,7 @@ static bool should_reset_plane(struct drm_atomic_state *state, continue; /* Pixel format changes can require bandwidth updates. */ -#ifndef HAVE_DRM_FRAMEBUFFER_FORMAT - if (old_other_state->fb->pixel_format != new_other_state->fb->pixel_format) -#else if (old_other_state->fb->format != new_other_state->fb->format) -#endif return true; old_afb = (struct amdgpu_framebuffer *)old_other_state->fb; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 113de4559a861..ff64d9a7ba4bc 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -925,11 +925,7 @@ int amdgpu_dm_plane_fill_plane_buffer_attributes(struct amdgpu_device *adev, plane_size->surface_size.width = fb->width; plane_size->surface_size.height = fb->height; plane_size->surface_pitch = -#ifndef HAVE_DRM_FRAMEBUFFER_FORMAT - fb->pitches[0] / (fb->bits_per_pixel / 8); -#else fb->pitches[0] / fb->format->cpp[0]; -#endif address->type = PLN_ADDR_TYPE_GRAPHICS; address->grph.addr.low_part = lower_32_bits(addr); @@ -943,11 +939,7 @@ int amdgpu_dm_plane_fill_plane_buffer_attributes(struct amdgpu_device *adev, plane_size->surface_size.width = fb->width; plane_size->surface_size.height = fb->height; plane_size->surface_pitch = -#ifndef HAVE_DRM_FRAMEBUFFER_FORMAT - fb->pitches[0] / (fb->bits_per_pixel / 8); -#else fb->pitches[0] / fb->format->cpp[0]; -#endif plane_size->chroma_size.x = 0; plane_size->chroma_size.y = 0; @@ -956,11 +948,7 @@ int amdgpu_dm_plane_fill_plane_buffer_attributes(struct amdgpu_device *adev, plane_size->chroma_size.height = fb->height / 2; plane_size->chroma_pitch = -#ifndef HAVE_DRM_FRAMEBUFFER_FORMAT - fb->pitches[1] / (fb->bits_per_pixel / 8)/2; -#else fb->pitches[1] / fb->format->cpp[1]; -#endif address->type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE; address->video_progressive.luma_addr.low_part = @@ -1137,11 +1125,7 @@ static void amdgpu_dm_plane_get_min_max_dc_plane_scaling(struct drm_device *dev, /* Caps for all supported planes are the same on DCE and DCN 1 - 3 */ struct dc_plane_cap *plane_cap = &dc->caps.planes[0]; -#ifndef HAVE_DRM_FRAMEBUFFER_FORMAT - switch (fb->pixel_format) { -#else switch (fb->format->format) { -#endif case DRM_FORMAT_P010: case DRM_FORMAT_NV12: case DRM_FORMAT_NV21: @@ -1254,12 +1238,7 @@ int amdgpu_dm_plane_fill_dc_scaling_info(struct amdgpu_device *adev, */ if (((amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 0)) || (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 1))) && - (state->fb && -#ifndef HAVE_DRM_FRAMEBUFFER_FORMAT - state->fb->pixel_format == DRM_FORMAT_NV12 && -#else - state->fb->format->format == DRM_FORMAT_NV12 && -#endif + (state->fb && state->fb->format->format == DRM_FORMAT_NV12 && (scaling_info->src_rect.x != 0 || scaling_info->src_rect.y != 0))) return -EINVAL; diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 53515c3c8863f..61a02fdc77a24 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -575,9 +575,6 @@ /* drm_format_info.block_w and rm_format_info.block_h is available */ #define HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED 1 -/* whether struct drm_framebuffer have format */ -#define HAVE_DRM_FRAMEBUFFER_FORMAT 1 - /* drm_gem_plane_helper_prepare_fb() is available */ #define HAVE_DRM_GEM_PLANE_HELPER_PREPARE_FB 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-framebuffer-format.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-framebuffer-format.m4 deleted file mode 100644 index 5a219b26d81bb..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm-framebuffer-format.m4 +++ /dev/null @@ -1,21 +0,0 @@ -dnl # -dnl # commit e14c23c647abfc1fed96a55ba376cd9675a54098 -dnl # drm: Store a pointer to drm_format_info under drm_framebuffer -dnl # -AC_DEFUN([AC_AMDGPU_DRM_FRAMEBUFFER_FORMAT], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DRMP_H - struct vm_area_struct; - #include - #endif - #include - ], [ - struct drm_framebuffer *foo = NULL; - foo->format = NULL; - ], [ - AC_DEFINE(HAVE_DRM_FRAMEBUFFER_FORMAT, 1, - [whether struct drm_framebuffer have format]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 04ccd6c58277e..b732071b448e8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -93,7 +93,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER AC_AMDGPU_DRM_MODE_IS_420_XXX AC_AMDGPU_DRM_MODE_INIT - AC_AMDGPU_DRM_FRAMEBUFFER_FORMAT AC_AMDGPU_DRM_DP_MST_TOPOLOGY AC_AMDGPU_DRM_HDMI_VENDOR_INFOFRAME_FROM_DISPLAY_MODE AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS From c34b2ba012dd585820ee60e6ccd52a3804c16c5a Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 20 Feb 2023 10:46:05 +0800 Subject: [PATCH 0936/1868] drm/amdkcl: kcl-cleanup HAVE_DRM_GET_FORMAT_INFO Signed-off-by: Leslie Shi Reviewed-by: Ma Jun --- drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 6 ------ drivers/gpu/drm/amd/dkms/config/config.h | 6 ------ drivers/gpu/drm/amd/dkms/m4/drm-get-format-info.m4 | 13 ------------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - 4 files changed, 26 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-get-format-info.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c index fa30102663de1..09b60070309e1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c @@ -123,9 +123,7 @@ static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev, struct drm_mode_fb_cmd2 *mode_cmd, struct drm_gem_object **gobj_p) { -#ifdef HAVE_DRM_GET_FORMAT_INFO const struct drm_format_info *info; -#endif struct amdgpu_device *adev = rfbdev->adev; struct drm_gem_object *gobj = NULL; struct amdgpu_bo *abo = NULL; @@ -139,12 +137,8 @@ static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev, AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | AMDGPU_GEM_CREATE_VRAM_CLEARED; -#ifdef HAVE_DRM_GET_FORMAT_INFO info = drm_get_format_info(adev_to_drm(adev), mode_cmd); cpp = info->cpp[0]; -#else - cpp = drm_format_plane_cpp(mode_cmd->pixel_format, 0); -#endif /* need to align pitch with crtc limits */ mode_cmd->pitches[0] = amdgpu_align_pitch(adev, mode_cmd->width, cpp, diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 61a02fdc77a24..d0b6c2afb0dbd 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -599,12 +599,6 @@ /* drm_gen_fb_init_with_funcs() is available */ #define HAVE_DRM_GEN_FB_INIT_WITH_FUNCS 1 -/* drm_get_format_info() is available */ -#define HAVE_DRM_GET_FORMAT_INFO 1 - -/* drm_get_format_name() has i,p interface */ -/* #undef HAVE_DRM_GET_FORMAT_NAME_I_P */ - /* drm_hdcp_update_content_protection is available */ #define HAVE_DRM_HDCP_UPDATE_CONTENT_PROTECTION 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-get-format-info.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-get-format-info.m4 deleted file mode 100644 index 5c797f77620f5..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm-get-format-info.m4 +++ /dev/null @@ -1,13 +0,0 @@ -dnl # -dnl # commit v4.11-rc1-237-g6a0f9ebfc5e7 -dnl # drm: Add mode_config .get_format_info() hook -dnl # -AC_DEFUN([AC_AMDGPU_DRM_GET_FORMAT_INFO], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([drm_get_format_info], - [drivers/gpu/drm/drm_fourcc.c], [ - AC_DEFINE(HAVE_DRM_GET_FORMAT_INFO, 1, - [drm_get_format_info() is available]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index b732071b448e8..54a234fa6af3a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -84,7 +84,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_FB_HELPER_FILL_INFO AC_AMDGPU_DRM_HELPER_MODE_FILL_FB_STRUCT AC_AMDGPU_DRM_FB_HELPER_INIT - AC_AMDGPU_DRM_GET_FORMAT_INFO AC_AMDGPU_DRM_HELPER_FORCE_DISABLE_ALL AC_AMDGPU_DRM_EDID_TO_ELD AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS From 340823611561761b50cb21ee94e57372517fbc13 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 20 Feb 2023 10:50:09 +0800 Subject: [PATCH 0937/1868] drm/amdkcl: kcl-cleanup HAVE_DRM_HDMI_VENDOR_INFOFRAME_FROM_DISPLAY_MODE_P_P_P Signed-off-by: Leslie Shi Reviewed-by: Ma Jun --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ---- drivers/gpu/drm/amd/dkms/config/config.h | 3 --- ...drm-hdmi-vendor-infoframe-from-display-mode.m4 | 15 --------------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - 4 files changed, 23 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-hdmi-vendor-infoframe-from-display-mode.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 01c455960f318..339f33cb63f65 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -6088,11 +6088,7 @@ static void fill_stream_properties_from_drm_display_mode( drm_hdmi_avi_infoframe_from_display_mode(&avi_frame, mode_in); #endif /* HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_P */ timing_out->vic = avi_frame.video_code; -#if defined(HAVE_DRM_HDMI_VENDOR_INFOFRAME_FROM_DISPLAY_MODE_P_P_P) drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, (struct drm_connector *)connector, mode_in); -#else - drm_hdmi_vendor_infoframe_from_display_mode(&hv_frame, mode_in); -#endif timing_out->hdmi_vic = hv_frame.vic; } diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index d0b6c2afb0dbd..11b31dd4a0d9b 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -608,9 +608,6 @@ /* drm_hdmi_avi_infoframe_from_display_mode() has p,p,p interface */ #define HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_P 1 -/* drm_hdmi_vendor_infoframe_from_display_mode() has p,p,p interface */ -#define HAVE_DRM_HDMI_VENDOR_INFOFRAME_FROM_DISPLAY_MODE_P_P_P 1 - /* drm_helper_force_disable_all() is available */ #define HAVE_DRM_HELPER_FORCE_DISABLE_ALL 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-hdmi-vendor-infoframe-from-display-mode.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-hdmi-vendor-infoframe-from-display-mode.m4 deleted file mode 100644 index c9f2c8a635e43..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm-hdmi-vendor-infoframe-from-display-mode.m4 +++ /dev/null @@ -1,15 +0,0 @@ -dnl f1781e9bb2dd2305d8d7ffbede1888ae22119557 -dnl # drm/edid: Allow HDMI infoframe without VIC or S3D -dnl # -AC_DEFUN([AC_AMDGPU_DRM_HDMI_VENDOR_INFOFRAME_FROM_DISPLAY_MODE], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include - ], [ - drm_hdmi_vendor_infoframe_from_display_mode(NULL, NULL, NULL); - ], [drm_hdmi_vendor_infoframe_from_display_mode], [drivers/gpu/drm/drm_edid.c], [ - AC_DEFINE(HAVE_DRM_HDMI_VENDOR_INFOFRAME_FROM_DISPLAY_MODE_P_P_P, 1, - [drm_hdmi_vendor_infoframe_from_display_mode() has p,p,p interface]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 54a234fa6af3a..40d639ad04a8e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -93,7 +93,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_MODE_IS_420_XXX AC_AMDGPU_DRM_MODE_INIT AC_AMDGPU_DRM_DP_MST_TOPOLOGY - AC_AMDGPU_DRM_HDMI_VENDOR_INFOFRAME_FROM_DISPLAY_MODE AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS AC_AMDGPU_DRM_ATOMIC_PRIVATE_OBJ_INIT AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS From 2fa35bc133eb55b9eec84f67f4bdee08aeb7d0b5 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 20 Feb 2023 10:55:32 +0800 Subject: [PATCH 0938/1868] drm/amdkcl: kcl-cleanup HAVE_DRM_HELPER_MODE_FILL_FB_STRUCT_DEV Signed-off-by: Leslie Shi Reviewed-by: Ma Jun --- drivers/gpu/drm/amd/dkms/config/config.h | 6 ------ .../dkms/m4/drm_helper_mode_fill_fb_struct.m4 | 16 ---------------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - include/kcl/backport/kcl_drm_fb.h | 13 ------------- 4 files changed, 36 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_helper_mode_fill_fb_struct.m4 diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 11b31dd4a0d9b..15bc49bb3a655 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -611,12 +611,6 @@ /* drm_helper_force_disable_all() is available */ #define HAVE_DRM_HELPER_FORCE_DISABLE_ALL 1 -/* drm_helper_mode_fill_fb_struct() wants dev arg */ -#define HAVE_DRM_HELPER_MODE_FILL_FB_STRUCT_DEV 1 - -/* drm_is_current_master() is available */ -#define HAVE_DRM_IS_CURRENT_MASTER 1 - /* drm_kms_helper_connector_hotplug_event() function is available */ #define HAVE_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_helper_mode_fill_fb_struct.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_helper_mode_fill_fb_struct.m4 deleted file mode 100644 index 3d662319c8e11..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm_helper_mode_fill_fb_struct.m4 +++ /dev/null @@ -1,16 +0,0 @@ -dnl # -dnl # v4.9-rc8-1647-g95bce7601581 drm: Populate fb->dev from drm_helper_mode_fill_fb_struct() -dnl # v4.9-rc8-1643-ga3f913ca9892 drm: Pass 'dev' to drm_helper_mode_fill_fb_struct() -dnl # -AC_DEFUN([AC_AMDGPU_DRM_HELPER_MODE_FILL_FB_STRUCT], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - drm_helper_mode_fill_fb_struct(NULL, NULL, NULL); - ], [ - AC_DEFINE(HAVE_DRM_HELPER_MODE_FILL_FB_STRUCT_DEV, 1, - [drm_helper_mode_fill_fb_struct() wants dev arg]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 40d639ad04a8e..cc45431daa6ed 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -82,7 +82,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_PCI_PR3_PRESENT AC_AMDGPU_KTHREAD_USE_MM AC_AMDGPU_DRM_FB_HELPER_FILL_INFO - AC_AMDGPU_DRM_HELPER_MODE_FILL_FB_STRUCT AC_AMDGPU_DRM_FB_HELPER_INIT AC_AMDGPU_DRM_HELPER_FORCE_DISABLE_ALL AC_AMDGPU_DRM_EDID_TO_ELD diff --git a/include/kcl/backport/kcl_drm_fb.h b/include/kcl/backport/kcl_drm_fb.h index 1269be6e2d9c9..e14f228fc86fb 100644 --- a/include/kcl/backport/kcl_drm_fb.h +++ b/include/kcl/backport/kcl_drm_fb.h @@ -25,19 +25,6 @@ #include #include -#ifndef HAVE_DRM_HELPER_MODE_FILL_FB_STRUCT_DEV -static inline -void _kcl_drm_helper_mode_fill_fb_struct(struct drm_device *dev, - struct drm_framebuffer *fb, - const struct drm_mode_fb_cmd2 *mode_cmd) -{ - fb->dev = dev; - drm_helper_mode_fill_fb_struct(fb, mode_cmd); -} - -#define drm_helper_mode_fill_fb_struct _kcl_drm_helper_mode_fill_fb_struct -#endif - #if defined(HAVE_DRM_FBDEV_GENERIC_SETUP) #define AMDKCL_DRM_FBDEV_GENERIC #endif From 24d314ec79c527d1e2a1b1d41dc84a90fc4261fd Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 2 Jan 2024 16:53:11 +0800 Subject: [PATCH 0939/1868] drm/amdkcl: kcl-cleanup HAVE_DRM_KMS_HELPER_IS_POLL_WORKER Signed-off-by: Leslie Shi Reviewed-by: Ma Jun Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c | 7 ------- drivers/gpu/drm/amd/dkms/config/config.h | 3 --- .../amd/dkms/m4/drm_kms_helper_is_poll_worker.m4 | 13 ------------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - 4 files changed, 24 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_kms_helper_is_poll_worker.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c index f5745929571f6..2c9621a3a1fc2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.c @@ -40,13 +40,6 @@ #include -#ifndef HAVE_DRM_KMS_HELPER_IS_POLL_WORKER -bool inline drm_kms_helper_is_poll_worker(void) -{ - return false; -} -#endif - void amdgpu_connector_hotplug(struct drm_connector *connector) { struct drm_device *dev = connector->dev; diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 15bc49bb3a655..a67c93931bc7b 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -614,9 +614,6 @@ /* drm_kms_helper_connector_hotplug_event() function is available */ #define HAVE_DRM_KMS_HELPER_CONNECTOR_HOTPLUG_EVENT 1 -/* drm_kms_helper_is_poll_worker() is available */ -#define HAVE_DRM_KMS_HELPER_IS_POLL_WORKER 1 - /* drm_memcpy_from_wc() is availablea */ /* #undef HAVE_DRM_MEMCPY_FROM_WC */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_kms_helper_is_poll_worker.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_kms_helper_is_poll_worker.m4 deleted file mode 100644 index dda9b0e2e2c79..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm_kms_helper_is_poll_worker.m4 +++ /dev/null @@ -1,13 +0,0 @@ -dnl # -dnl # commit v4.15-rc8-13-g25c058ccaf2e -dnl # drm: Allow determining if current task is output poll worker -dnl # -AC_DEFUN([AC_AMDGPU_DRM_KMS_HELPER_IS_POLL_WORKER], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([drm_kms_helper_is_poll_worker], - [drivers/gpu/drm/drm_probe_helper.c], [ - AC_DEFINE(HAVE_DRM_KMS_HELPER_IS_POLL_WORKER, 1, - [drm_kms_helper_is_poll_worker() is available]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index cc45431daa6ed..88dfabe71238d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -87,7 +87,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_EDID_TO_ELD AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS AC_AMDGPU_DRM_EDID - AC_AMDGPU_DRM_KMS_HELPER_IS_POLL_WORKER AC_AMDGPU_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER AC_AMDGPU_DRM_MODE_IS_420_XXX AC_AMDGPU_DRM_MODE_INIT From ea93eed9994ce62fcfde61df84d1ae2ca2aded25 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 20 Feb 2023 11:58:45 +0800 Subject: [PATCH 0940/1868] drm/amdkcl: kcl-cleanup HAVE_DRM_MM_INSERT_MODE This patch also removes macro HAVE_DRM_MM_INSERT_NODE_THREE_PARAMETERS Signed-off-by: Leslie Shi Reviewed-by: Ma Jun --- drivers/gpu/drm/amd/backport/backport.h | 1 - drivers/gpu/drm/amd/dkms/config/config.h | 6 -- .../gpu/drm/amd/dkms/m4/drm-mm-insert-mode.m4 | 17 ----- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - drivers/gpu/drm/ttm/backport/backport.h | 2 - include/kcl/backport/kcl_drm_mm_backport.h | 27 -------- include/kcl/kcl_drm_mm.h | 68 ------------------- 7 files changed, 122 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-mm-insert-mode.m4 delete mode 100644 include/kcl/backport/kcl_drm_mm_backport.h delete mode 100644 include/kcl/kcl_drm_mm.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index e913c8e92c80c..81237794ee36b 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -65,7 +65,6 @@ #include #include #include -#include #include #include #include "kcl/kcl_amdgpu_drm_fb_helper.h" diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index a67c93931bc7b..312a9b3b1451c 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -620,12 +620,6 @@ /* drm_memcpy_from_wc() is availablea and has struct iosys_map* arg */ #define HAVE_DRM_MEMCPY_FROM_WC_IOSYS_MAP_ARG 1 -/* whether drm_mm_insert_mode is available */ -#define HAVE_DRM_MM_INSERT_MODE 1 - -/* drm_mm_insert_node has three parameters */ -#define HAVE_DRM_MM_INSERT_NODE_THREE_PARAMETERS 1 - /* drm_mode_config->dp_subconnector_property is available */ #define HAVE_DRM_MODE_CONFIG_DP_SUBCONNECTOR_PROPERTY 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-mm-insert-mode.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-mm-insert-mode.m4 deleted file mode 100644 index 633f7925b0aec..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm-mm-insert-mode.m4 +++ /dev/null @@ -1,17 +0,0 @@ -dnl # -dnl # commit 4e64e5539d152e202ad6eea2b6f65f3ab58d9428 -dnl # Author: Chris Wilson -dnl # Date: Thu Feb 2 21:04:38 2017 +0000 -dnl # -AC_DEFUN([AC_AMDGPU_DRM_MM_INSERT_MODE], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ],[ - enum drm_mm_insert_mode mode = DRM_MM_INSERT_BEST; - ],[ - AC_DEFINE(HAVE_DRM_MM_INSERT_MODE, 1, - [whether drm_mm_insert_mode is available]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 88dfabe71238d..2b96434501b82 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -73,7 +73,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DRIVER_GEM_PRIME_RES_OBJ AC_AMDGPU_DRM_DRV_GEM_PRIME_EXPORT AC_AMDGPU_DRM_PRINT_BITS - AC_AMDGPU_DRM_MM_INSERT_MODE AC_AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES AC_AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL AC_AMDGPU_STRUCT_DRM_DEVICE diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index 23eea49ccf6ae..57158f3fc9465 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -12,8 +12,6 @@ #include #include #include -#include -#include #include #include #include diff --git a/include/kcl/backport/kcl_drm_mm_backport.h b/include/kcl/backport/kcl_drm_mm_backport.h deleted file mode 100644 index 1a2614d47ab59..0000000000000 --- a/include/kcl/backport/kcl_drm_mm_backport.h +++ /dev/null @@ -1,27 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -#ifndef AMDKCL_DRM_MM_H -#define AMDKCL_DRM_MM_H - -/** - * interface change in mainline kernel 4.10 - * v4.10-rc5-1060-g4e64e5539d15 drm: Improve drm_mm search (and fix topdown allocation) - * with rbtrees - */ - -#include - -#ifndef HAVE_DRM_MM_INSERT_NODE_THREE_PARAMETERS -static inline int _kcl_drm_mm_insert_node(struct drm_mm *mm, - struct drm_mm_node *node, - u64 size) -{ - return drm_mm_insert_node(mm, node, size, 0, DRM_MM_SEARCH_DEFAULT); -} -#define drm_mm_insert_node _kcl_drm_mm_insert_node -#endif /* HAVE_DRM_MM_INSERT_NODE_THREE_PARAMETERS */ - -#ifndef HAVE_DRM_MM_INSERT_MODE -#define drm_mm_insert_node_in_range _kcl_drm_mm_insert_node_in_range -#endif - -#endif /* AMDKCL_DRM_MM_H */ diff --git a/include/kcl/kcl_drm_mm.h b/include/kcl/kcl_drm_mm.h deleted file mode 100644 index 5387e6c05bc65..0000000000000 --- a/include/kcl/kcl_drm_mm.h +++ /dev/null @@ -1,68 +0,0 @@ -/************************************************************************** - * - * Copyright 2006-2008 Tungsten Graphics, Inc., Cedar Park, TX. USA. - * Copyright 2016 Intel Corporation - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sub license, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR - * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE - * USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * - **************************************************************************/ -/* - * Authors: - * Thomas Hellstrom - */ -#ifndef _KCL_KCL_DRM_MM_H_H_ -#define _KCL_KCL_DRM_MM_H_H_ -#include - -#ifndef HAVE_DRM_MM_INSERT_MODE -/* Copied from 4e64e5539d15 include/drm/drm_mm.h */ -enum drm_mm_insert_mode { - DRM_MM_INSERT_BEST = 0, - DRM_MM_INSERT_LOW, - DRM_MM_INSERT_HIGH, - DRM_MM_INSERT_EVICT, -}; - -static inline -int _kcl_drm_mm_insert_node_in_range(struct drm_mm * const mm, - struct drm_mm_node * const node, - u64 size, u64 alignment, - unsigned long color, - u64 range_start, u64 range_end, - enum drm_mm_insert_mode mode) -{ - enum drm_mm_search_flags sflags = DRM_MM_SEARCH_BEST; - enum drm_mm_allocator_flags aflags = DRM_MM_CREATE_DEFAULT; - - if (mode == DRM_MM_INSERT_HIGH) { - sflags = DRM_MM_SEARCH_BELOW; - aflags = DRM_MM_CREATE_TOP; - } - - return drm_mm_insert_node_in_range_generic(mm, node, size, - alignment, color, range_start, range_end, - sflags, aflags); -} -#endif /* HAVE_DRM_MM_INSERT_MODE */ - -#endif From 93b0baa25d5dd921fde624fe2fe06d1d123e751a Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 20 Feb 2023 12:07:53 +0800 Subject: [PATCH 0941/1868] drm/amdkcl: kcl-cleanup HAVE_DRM_MODE_CONFIG_HELPER_SUSPEND Signed-off-by: Leslie Shi Reviewed-by: Ma Jun --- drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 3 - drivers/gpu/drm/amd/backport/Makefile | 2 +- drivers/gpu/drm/amd/backport/backport.h | 1 - .../kcl/kcl_amdgpu_drm_modeset_helper.h | 31 ------- .../drm/amd/backport/kcl_drm_modeset_helper.c | 89 ------------------- drivers/gpu/drm/amd/dkms/config/config.h | 3 - .../dkms/m4/drm_mode_config_helper_suspend.m4 | 13 --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - 8 files changed, 1 insertion(+), 142 deletions(-) delete mode 100644 drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_modeset_helper.h delete mode 100644 drivers/gpu/drm/amd/backport/kcl_drm_modeset_helper.c delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_mode_config_helper_suspend.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index b4b19cae03c71..e75f17f79e0da 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -360,9 +360,6 @@ struct amdgpu_mode_info { int disp_priority; const struct amdgpu_display_funcs *funcs; const enum drm_plane_type *plane_type; -#ifndef HAVE_DRM_MODE_CONFIG_HELPER_SUSPEND - struct drm_atomic_state *suspend_state; -#endif /* Driver-private color mgmt props */ diff --git a/drivers/gpu/drm/amd/backport/Makefile b/drivers/gpu/drm/amd/backport/Makefile index 335363b5b8ee5..f5b5d3b9a2d33 100644 --- a/drivers/gpu/drm/amd/backport/Makefile +++ b/drivers/gpu/drm/amd/backport/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: MIT BACKPORT_OBJS := kcl_drm_drv.o kcl_drm_gem_ttm_helper.o \ - kcl_drm_gem.o kcl_drm_modeset_helper.o + kcl_drm_gem.o amdgpu-y += $(addprefix ../backport/,$(BACKPORT_OBJS)) diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 81237794ee36b..04a3b11a3931a 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -72,7 +72,6 @@ #include "kcl/kcl_amdgpu_drm_drv.h" #include "kcl/kcl_amdgpu_drm_gem.h" #include "kcl/kcl_drm_gem_ttm_helper.h" -#include "kcl/kcl_amdgpu_drm_modeset_helper.h" #include "kcl/kcl_mce.h" #include "kcl/kcl_drm_aperture.h" #include diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_modeset_helper.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_modeset_helper.h deleted file mode 100644 index 611d801aa6c33..0000000000000 --- a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_modeset_helper.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright (c) 2016 Intel Corporation - * - * Permission to use, copy, modify, distribute, and sell this software and its - * documentation for any purpose is hereby granted without fee, provided that - * the above copyright notice appear in all copies and that both that copyright - * notice and this permission notice appear in supporting documentation, and - * that the name of the copyright holders not be used in advertising or - * publicity pertaining to distribution of the software without specific, - * written prior permission. The copyright holders make no representations - * about the suitability of this software for any purpose. It is provided "as - * is" without express or implied warranty. - * - * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, - * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO - * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR - * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, - * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER - * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE - * OF THIS SOFTWARE. - */ - -#ifndef AMDGPU_BACKPORT_KCL_AMDGPU_DRM_MODESET_HELPER_H -#define AMDGPU_BACKPORT_KCL_AMDGPU_DRM_MODESET_HELPER_H - -#ifndef HAVE_DRM_MODE_CONFIG_HELPER_SUSPEND -int drm_mode_config_helper_suspend(struct drm_device *dev); -int drm_mode_config_helper_resume(struct drm_device *dev); -#endif - -#endif diff --git a/drivers/gpu/drm/amd/backport/kcl_drm_modeset_helper.c b/drivers/gpu/drm/amd/backport/kcl_drm_modeset_helper.c deleted file mode 100644 index e6015f0a7efce..0000000000000 --- a/drivers/gpu/drm/amd/backport/kcl_drm_modeset_helper.c +++ /dev/null @@ -1,89 +0,0 @@ -/* - * Copyright (c) 2016 Intel Corporation - * - * Permission to use, copy, modify, distribute, and sell this software and its - * documentation for any purpose is hereby granted without fee, provided that - * the above copyright notice appear in all copies and that both that copyright - * notice and this permission notice appear in supporting documentation, and - * that the name of the copyright holders not be used in advertising or - * publicity pertaining to distribution of the software without specific, - * written prior permission. The copyright holders make no representations - * about the suitability of this software for any purpose. It is provided "as - * is" without express or implied warranty. - * - * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, - * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO - * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR - * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, - * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER - * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE - * OF THIS SOFTWARE. - */ - -#include -#include "amdgpu.h" - -/* Copied from drivers/gpu/drm/drm_modeset_helper.c and modified for KCL */ -#ifndef HAVE_DRM_MODE_CONFIG_HELPER_SUSPEND -int drm_mode_config_helper_suspend(struct drm_device *dev) -{ - struct drm_atomic_state *state; - struct amdgpu_device *adev; - struct amdgpu_fbdev *afbdev; - struct drm_fb_helper *fb_helper; - - if (!dev) - return 0; - - adev = drm_to_adev(dev); - afbdev = adev->mode_info.rfbdev; - if (!afbdev) - return 0; - - fb_helper = &afbdev->helper; - - drm_kms_helper_poll_disable(dev); - drm_fb_helper_set_suspend_unlocked(fb_helper, 1); - state = drm_atomic_helper_suspend(dev); - if (IS_ERR(state)) { - drm_fb_helper_set_suspend_unlocked(fb_helper, 0); - drm_kms_helper_poll_enable(dev); - return PTR_ERR(state); - } - - adev->mode_info.suspend_state = state; - - return 0; -} - -int drm_mode_config_helper_resume(struct drm_device *dev) -{ - int ret; - struct amdgpu_device *adev; - struct amdgpu_fbdev *afbdev; - struct drm_fb_helper *fb_helper; - - if (!dev) - return 0; - - adev = drm_to_adev(dev); - afbdev = adev->mode_info.rfbdev; - if (!afbdev) - return 0; - - fb_helper = &afbdev->helper; - - if (WARN_ON(!adev->mode_info.suspend_state)) - return -EINVAL; - - ret = drm_atomic_helper_resume(dev, adev->mode_info.suspend_state); - if (ret) - DRM_ERROR("Failed to resume (%d)\n", ret); - adev->mode_info.suspend_state = NULL; - - drm_fb_helper_set_suspend_unlocked(fb_helper, 0); - drm_kms_helper_poll_enable(dev); - - return ret; -} -#endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 312a9b3b1451c..3f901df088e3b 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -632,9 +632,6 @@ /* drm_mode_config_funcs->atomic_state_alloc() is available */ #define HAVE_DRM_MODE_CONFIG_FUNCS_ATOMIC_STATE_ALLOC 1 -/* drm_mode_config_helper_{suspend/resume}() is available */ -#define HAVE_DRM_MODE_CONFIG_HELPER_SUSPEND 1 - /* drm_mode_get_hv_timing is available */ #define HAVE_DRM_MODE_GET_HV_TIMING 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_mode_config_helper_suspend.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_mode_config_helper_suspend.m4 deleted file mode 100644 index 8d30e1afba578..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm_mode_config_helper_suspend.m4 +++ /dev/null @@ -1,13 +0,0 @@ -dnl # -dnl # v4.14-rc7-1626-gca038cfb5cfa -dnl # drm/modeset-helper: Add simple modeset suspend/resume helpers -dnl # -AC_DEFUN([AC_AMDGPU_DRM_MODE_CONFIG_HELPER_SUSPEND], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([drm_mode_config_helper_suspend drm_mode_config_helper_resume], - [drivers/gpu/drm/drm_modeset_helper.c],[ - AC_DEFINE(HAVE_DRM_MODE_CONFIG_HELPER_SUSPEND, 1, - [drm_mode_config_helper_{suspend/resume}() is available]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 2b96434501b82..fe8d35b60b68d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -145,7 +145,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DEVICE_PDEV AC_AMDGPU_DRM_CONNECTOR_SET_PANEL_ORIENTATION_WITH_QUIRK AC_AMDGPU_DRM_SIMPLE_ENCODER_INIT - AC_AMDGPU_DRM_MODE_CONFIG_HELPER_SUSPEND AC_AMDGPU_DRM_FBDEV_GENERIC_SETUP AC_AMDGPU_DRM_DP_UPDATE_PAYLOAD_PART1_START_SLOT_ARG AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS From 41fd37faf550f8ab098fb2405c6788d319d20dcf Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 14 Jun 2023 17:17:10 +0800 Subject: [PATCH 0942/1868] drm/amdkcl: kcl-cleanup HAVE_DRM_MODE_IS_420_XXX Signed-off-by: Leslie Shi Reviewed-by: Ma Jun Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdkcl/kcl_drm_modes.c | 7 ------- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 -- drivers/gpu/drm/amd/dkms/config/config.h | 6 ------ .../gpu/drm/amd/dkms/m4/drm_mode_is_420_xxx.m4 | 17 ----------------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - include/kcl/kcl_drm_modes.h | 7 ------- 6 files changed, 40 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_mode_is_420_xxx.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_modes.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_modes.c index e01b01bd4ae09..a7963c347e685 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_modes.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_modes.c @@ -33,13 +33,6 @@ #include #include -#ifndef HAVE_DRM_MODE_IS_420_XXX -amdkcl_dummy_symbol(drm_mode_is_420_only, bool, return false, - const struct drm_display_info *display, const struct drm_display_mode *mode) -amdkcl_dummy_symbol(drm_mode_is_420_also, bool, return false, - const struct drm_display_info *display, const struct drm_display_mode *mode) -#endif - #ifndef HAVE_DRM_MODE_INIT void drm_mode_init(struct drm_display_mode *dst, const struct drm_display_mode *src) { diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 339f33cb63f65..3e60388c507cf 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -5848,7 +5848,6 @@ convert_color_depth_from_display_info(const struct drm_connector *connector, /* Assume 8 bpc by default if no bpc is specified. */ bpc = bpc ? bpc : 8; -#ifdef HAVE_DRM_MODE_IS_420_XXX if (is_y420) { bpc = 8; @@ -5860,7 +5859,6 @@ convert_color_depth_from_display_info(const struct drm_connector *connector, else if (connector->display_info.hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30) bpc = 10; } -#endif if (requested_bpc > 0) { /* diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 3f901df088e3b..a0a97d77544c1 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -632,12 +632,6 @@ /* drm_mode_config_funcs->atomic_state_alloc() is available */ #define HAVE_DRM_MODE_CONFIG_FUNCS_ATOMIC_STATE_ALLOC 1 -/* drm_mode_get_hv_timing is available */ -#define HAVE_DRM_MODE_GET_HV_TIMING 1 - -/* drm_mode_is_420_xxx() is available */ -#define HAVE_DRM_MODE_IS_420_XXX 1 - /* drm_mode_init() is available */ #define HAVE_DRM_MODE_INTT 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_mode_is_420_xxx.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_mode_is_420_xxx.m4 deleted file mode 100644 index 65c9ec9268e1b..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm_mode_is_420_xxx.m4 +++ /dev/null @@ -1,17 +0,0 @@ -dnl # -dnl # commit 2570fe2586254ff174c2ba5a20dabbde707dbb9b -dnl # drm: add helper functions for YCBCR420 handling -dnl # -AC_DEFUN([AC_AMDGPU_DRM_MODE_IS_420_XXX], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include - ], [ - drm_mode_is_420_only(NULL, NULL); - drm_mode_is_420_also(NULL, NULL); - ], [drm_mode_is_420_only drm_mode_is_420_also],[drivers/gpu/drm/drm_modes.c],[ - AC_DEFINE(HAVE_DRM_MODE_IS_420_XXX, 1, - [drm_mode_is_420_xxx() is available]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index fe8d35b60b68d..99df8fc9f9986 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -87,7 +87,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS AC_AMDGPU_DRM_EDID AC_AMDGPU_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER - AC_AMDGPU_DRM_MODE_IS_420_XXX AC_AMDGPU_DRM_MODE_INIT AC_AMDGPU_DRM_DP_MST_TOPOLOGY AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS diff --git a/include/kcl/kcl_drm_modes.h b/include/kcl/kcl_drm_modes.h index efd58502aad15..d3a387bad9988 100644 --- a/include/kcl/kcl_drm_modes.h +++ b/include/kcl/kcl_drm_modes.h @@ -29,13 +29,6 @@ #include -#ifndef HAVE_DRM_MODE_IS_420_XXX -bool drm_mode_is_420_only(const struct drm_display_info *display, - const struct drm_display_mode *mode); -bool drm_mode_is_420_also(const struct drm_display_info *display, - const struct drm_display_mode *mode); -#endif - #ifndef HAVE_DRM_MODE_INIT void drm_mode_init(struct drm_display_mode *dst, const struct drm_display_mode *src); #endif From 3823fa3f6ad65d83cd78087152750e3fbc9e0656 Mon Sep 17 00:00:00 2001 From: bobzhou Date: Wed, 1 Mar 2023 12:17:08 +0800 Subject: [PATCH 0943/1868] drm/amdkcl: check if fsleep() is available It's caused by b1121d678231324d281db891755aa547506457a9 "drm/amd/display: Reduce CPU busy-waiting for long delays" Signed-off-by: bobzhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/fsleep.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_delay.h | 18 ++++++++++++++++++ 5 files changed, 40 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/fsleep.m4 create mode 100644 include/kcl/kcl_delay.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 04a3b11a3931a..e9ad69f3afd3d 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -104,4 +104,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index a0a97d77544c1..3e11ac15e0b35 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -149,6 +149,9 @@ /* down_write_killable() is available */ #define HAVE_DOWN_WRITE_KILLABLE 1 +/* fsleep() is available */ +#define HAVE_FSLEEP 1 + /* drm_dp_mst_connector_early_unregister() is available */ #define HAVE_DRM_DP_MST_CONNECTOR_EARLY_UNREGISTER 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/fsleep.m4 b/drivers/gpu/drm/amd/dkms/m4/fsleep.m4 new file mode 100644 index 0000000000000..782402a16e6a4 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/fsleep.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # v5.7-rc2-1263-gc6af13d33475 +dnl # timer: add fsleep for flexible sleeping +dnl # +AC_DEFUN([AC_AMDGPU_FSLEEP], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + unsigned long usecs = 0; + fsleep(usecs); + ], [ + AC_DEFINE(HAVE_FSLEEP, 1, + [fsleep() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 99df8fc9f9986..5e3406d0bd1be 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -35,6 +35,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_MEMALLOC_NOFS_SAVE AC_AMDGPU_ZONE_MANAGED_PAGES AC_AMDGPU_FAULT_FLAG_ALLOW_RETRY_FIRST + AC_AMDGPU_FSLEEP AC_AMDGPU_VMF_INSERT AC_AMDGPU_VMF_INSERT_MIXED_PROT AC_AMDGPU_VMF_INSERT_PFN_PROT diff --git a/include/kcl/kcl_delay.h b/include/kcl/kcl_delay.h new file mode 100644 index 0000000000000..f5f2962c6bb6d --- /dev/null +++ b/include/kcl/kcl_delay.h @@ -0,0 +1,18 @@ +#ifndef AMDKCL_DELAY_H +#define AMDKCL_DELAY_H + +#ifndef HAVE_FSLEEP +static inline void _kcl_fsleep(unsigned long usecs) +{ + if (usecs <= 10) + udelay(usecs); + else if (usecs <= 20000) + usleep_range(usecs, 2 * usecs); + else + msleep(DIV_ROUND_UP(usecs, 1000)); +} + +#define fsleep _kcl_fsleep + +#endif +#endif From 0f47ea6699cdf54e27cbdff5695c85dd172debf4 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 20 Feb 2023 16:16:42 +0800 Subject: [PATCH 0944/1868] drm/amdkcl: kcl-cleanup HAVE_KREF_READ Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_chain.c | 1 - drivers/gpu/drm/amd/backport/backport.h | 1 - drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - drivers/gpu/drm/amd/dkms/m4/kref-read.m4 | 16 ---------------- drivers/gpu/drm/scheduler/backport/backport.h | 1 - drivers/gpu/drm/ttm/backport/backport.h | 1 - include/kcl/kcl_kref.h | 7 ------- 7 files changed, 28 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/kref-read.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_chain.c b/drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_chain.c index d19d8b3733657..aef948cfe4ad2 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_chain.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_dma_fence_chain.c @@ -9,7 +9,6 @@ #if !defined(HAVE_STRUCT_DMA_FENCE_CHAIN) -#include #include #include diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index e9ad69f3afd3d..b4c60325bd5d0 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 5e3406d0bd1be..c2857d739d836 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -9,7 +9,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_KALLSYMS_LOOKUP_NAME AC_KERNEL_SUPPORTED_AMD_CHIPS AC_AMDGPU_IDR - AC_AMDGPU_KREF_READ AC_AMDGPU_TYPE__POLL_T AC_AMDGPU_DMA_MAP_SGTABLE AC_AMDGPU_I2C_NEW_CLIENT_DEVICE diff --git a/drivers/gpu/drm/amd/dkms/m4/kref-read.m4 b/drivers/gpu/drm/amd/dkms/m4/kref-read.m4 deleted file mode 100644 index da7e2bf0aac37..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/kref-read.m4 +++ /dev/null @@ -1,16 +0,0 @@ -dnl # -dnl # commit 2c935bc57221cc2edc787c72ea0e2d30cdcd3d5e -dnl # locking/atomic, kref: Add kref_read() -dnl # -AC_DEFUN([AC_AMDGPU_KREF_READ], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - kref_read(NULL); - ], [ - AC_DEFINE(HAVE_KREF_READ, 1, - [kref_read() function is available]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/scheduler/backport/backport.h b/drivers/gpu/drm/scheduler/backport/backport.h index 3327879e06a15..25460de490b35 100644 --- a/drivers/gpu/drm/scheduler/backport/backport.h +++ b/drivers/gpu/drm/scheduler/backport/backport.h @@ -8,6 +8,5 @@ #include #include #include -#include #endif diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index 57158f3fc9465..e6cab104d2b34 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -3,7 +3,6 @@ #define AMDTTM_BACKPORT_H #include -#include #include #include #include diff --git a/include/kcl/kcl_kref.h b/include/kcl/kcl_kref.h index 0cc53e385e8db..491ce5398137b 100644 --- a/include/kcl/kcl_kref.h +++ b/include/kcl/kcl_kref.h @@ -15,11 +15,4 @@ #include /* Copied from include/linux/kref.h */ -#if !defined(HAVE_KREF_READ) -static inline unsigned int kref_read(const struct kref *kref) -{ - return atomic_read(&kref->refcount); -} -#endif - #endif /* AMDKCL_KREF_H */ From 75f91d5fc31a0c3f501d3800729091d74a5791d8 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 20 Feb 2023 16:30:12 +0800 Subject: [PATCH 0945/1868] drm/amdkcl: kcl-cleanup HAVE_KTIME_GET_REAL_SECONDS Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/config/config.h | 3 --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - .../drm/amd/dkms/m4/ktime-get-real-seconds.m4 | 20 ------------------- include/kcl/kcl_timekeeping.h | 10 ---------- 4 files changed, 34 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/ktime-get-real-seconds.m4 diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 3e11ac15e0b35..3eaaad793a8a0 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -813,9 +813,6 @@ /* ktime_get_raw_ns is available */ #define HAVE_KTIME_GET_RAW_NS 1 -/* ktime_get_real_seconds() is available */ -#define HAVE_KTIME_GET_REAL_SECONDS 1 - /* ktime_t is union */ /* #undef HAVE_KTIME_IS_UNION */ diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index c2857d739d836..962b431cf49fb 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -30,7 +30,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_PCI_REBAR_BYTES_TO_SIZE AC_AMDGPU_KTIME_GET_BOOTTIME_NS AC_AMDGPU_KTIME_GET_RAW_NS - AC_AMDGPU_KTIME_GET_REAL_SECONDS AC_AMDGPU_MEMALLOC_NOFS_SAVE AC_AMDGPU_ZONE_MANAGED_PAGES AC_AMDGPU_FAULT_FLAG_ALLOW_RETRY_FIRST diff --git a/drivers/gpu/drm/amd/dkms/m4/ktime-get-real-seconds.m4 b/drivers/gpu/drm/amd/dkms/m4/ktime-get-real-seconds.m4 deleted file mode 100644 index 6ba2dff0aca08..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/ktime-get-real-seconds.m4 +++ /dev/null @@ -1,20 +0,0 @@ -AC_DEFUN([AC_AMDGPU_KTIME_GET_REAL_SECONDS], [ - AC_KERNEL_DO_BACKGROUND([ - dnl # - dnl # commit dbe7aa622db96b5cd601f59d09c4f00b98b76079 - dnl # timekeeping: Provide y2038 safe accessor to the seconds portion of CLOCK_REALTIME - dnl # - AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DRM_BACKPORT_H - #include - #endif - #include - #include - ], [ - ktime_get_real_seconds(); - ], [ - AC_DEFINE(HAVE_KTIME_GET_REAL_SECONDS, 1, - [ktime_get_real_seconds() is available]) - ]) - ]) -]) diff --git a/include/kcl/kcl_timekeeping.h b/include/kcl/kcl_timekeeping.h index 90e1b1c045a75..644228c997baf 100644 --- a/include/kcl/kcl_timekeeping.h +++ b/include/kcl/kcl_timekeeping.h @@ -37,16 +37,6 @@ static inline u64 ktime_get_raw_ns(void) } #endif -#ifndef HAVE_KTIME_GET_REAL_SECONDS -static inline time64_t ktime_get_real_seconds(void) -{ - struct timeval ts; - - do_gettimeofday(&ts); - return (time64_t)ts.tv_sec; -} -#endif - #ifndef HAVE_JIFFIES64_TO_MSECS extern u64 jiffies64_to_msecs(u64 j); #endif From 2571e972033a9249db971a5299cb5cdcf9698ceb Mon Sep 17 00:00:00 2001 From: bobzhou Date: Thu, 2 Mar 2023 13:15:42 +0800 Subject: [PATCH 0946/1868] drm/amdkcl: wrap code under macro HAVE_STRUCT_XARRAY It's caused by 1d34dd584ae816e858b1177294262e80efe7d932 "drm/scheduler: rework entity flush, kill and fini" Signed-off-by: bobzhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/scheduler/sched_entity.c | 100 ++++++++++++++++++++++- 1 file changed, 97 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/scheduler/sched_entity.c b/drivers/gpu/drm/scheduler/sched_entity.c index 934687f6f7d37..2a5f2a17dcf44 100644 --- a/drivers/gpu/drm/scheduler/sched_entity.c +++ b/drivers/gpu/drm/scheduler/sched_entity.c @@ -192,6 +192,7 @@ static void drm_sched_entity_kill_jobs_work(struct work_struct *wrk) job->sched->ops->free_job(job); } +#ifdef HAVE_STRUCT_XARRAY /* Signal the scheduler finished fence when the entity in question is killed. */ static void drm_sched_entity_kill_jobs_cb(struct dma_fence *f, struct dma_fence_cb *cb) @@ -265,7 +266,7 @@ static void drm_sched_entity_kill(struct drm_sched_entity *entity) } dma_fence_put(prev); } - +#endif /** * drm_sched_entity_flush - Flush a context entity * @@ -305,14 +306,75 @@ long drm_sched_entity_flush(struct drm_sched_entity *entity, long timeout) /* For killed process disable any more IBs enqueue right now */ last_user = cmpxchg(&entity->last_user, current->group_leader, NULL); +#ifdef HAVE_STRUCT_XARRAY if ((!last_user || last_user == current->group_leader) && (current->flags & PF_EXITING) && (current->exit_code == SIGKILL)) drm_sched_entity_kill(entity); - +#else + if ((!last_user || last_user == current->group_leader) && + (current->flags & PF_EXITING) && (current->exit_code == SIGKILL)) { + spin_lock(&entity->rq_lock); + entity->stopped = true; + drm_sched_rq_remove_entity(entity->rq, entity); + spin_unlock(&entity->rq_lock); + } +#endif return ret; } EXPORT_SYMBOL(drm_sched_entity_flush); +#ifndef HAVE_STRUCT_XARRAY +/* Signal the scheduler finished fence when the entity in question is killed. */ +static void drm_sched_entity_kill_jobs_cb(struct dma_fence *f, + struct dma_fence_cb *cb) +{ + struct drm_sched_job *job = container_of(cb, struct drm_sched_job, + finish_cb); + + dma_fence_put(f); + INIT_WORK(&job->work, drm_sched_entity_kill_jobs_work); + schedule_work(&job->work); +} + +static void drm_sched_entity_kill_jobs(struct drm_sched_entity *entity) +{ + struct drm_sched_job *job; + struct dma_fence *f; + int r; + + while ((job = to_drm_sched_job(spsc_queue_pop(&entity->job_queue)))) { + struct drm_sched_fence *s_fence = job->s_fence; + + /* Wait for all dependencies to avoid data corruptions */ + while ((f = job->sched->ops->dependency(job, entity))) { + dma_fence_wait(f, false); + dma_fence_put(f); + } + + drm_sched_fence_scheduled(s_fence, f); + dma_fence_set_error(&s_fence->finished, -ESRCH); + + /* + * When pipe is hanged by older entity, new entity might + * not even have chance to submit it's first job to HW + * and so entity->last_scheduled will remain NULL + */ + if (!entity->last_scheduled) { + drm_sched_entity_kill_jobs_cb(NULL, &job->finish_cb); + continue; + } + + dma_fence_get(entity->last_scheduled); + r = dma_fence_add_callback(entity->last_scheduled, + &job->finish_cb, + drm_sched_entity_kill_jobs_cb); + if (r == -ENOENT) + drm_sched_entity_kill_jobs_cb(NULL, &job->finish_cb); + else if (r) + DRM_ERROR("fence add callback failed (%d)\n", r); + } +} +#endif /** * drm_sched_entity_fini - Destroy a context entity * @@ -326,6 +388,36 @@ EXPORT_SYMBOL(drm_sched_entity_flush); */ void drm_sched_entity_fini(struct drm_sched_entity *entity) { +#ifndef HAVE_STRUCT_XARRAY + struct drm_gpu_scheduler *sched = NULL; + + if (entity->rq) { + sched = entity->rq->sched; + drm_sched_rq_remove_entity(entity->rq, entity); + } + + /* Consumption of existing IBs wasn't completed. Forcefully + * remove them here. + */ + if (spsc_queue_count(&entity->job_queue)) { + if (sched) { + /* + * Wait for thread to idle to make sure it isn't processing + * this entity. + */ + wait_for_completion(&entity->entity_idle); + + } + if (entity->dependency) { + dma_fence_remove_callback(entity->dependency, + &entity->cb); + dma_fence_put(entity->dependency); + entity->dependency = NULL; + } + + drm_sched_entity_kill_jobs(entity); + } +#else /* * If consumption of existing IBs wasn't completed. Forcefully remove * them here. Also makes sure that the scheduler won't touch this entity @@ -338,7 +430,7 @@ void drm_sched_entity_fini(struct drm_sched_entity *entity) dma_fence_put(entity->dependency); entity->dependency = NULL; } - +#endif dma_fence_put(rcu_dereference_check(entity->last_scheduled, true)); RCU_INIT_POINTER(entity->last_scheduled, NULL); } @@ -449,6 +541,7 @@ static bool drm_sched_entity_add_dependency_cb(struct drm_sched_entity *entity) return false; } +#ifdef HAVE_STRUCT_XARRAY static struct dma_fence * drm_sched_job_dependency(struct drm_sched_job *job, struct drm_sched_entity *entity) @@ -470,6 +563,7 @@ drm_sched_job_dependency(struct drm_sched_job *job, return NULL; } +#endif struct drm_sched_job *drm_sched_entity_pop_job(struct drm_sched_entity *entity) { From 4ddc830e7a47499d292a42816bdbb525fdae0dee Mon Sep 17 00:00:00 2001 From: bobzhou Date: Thu, 2 Mar 2023 13:19:09 +0800 Subject: [PATCH 0947/1868] drm/amdkcl: rename dependency callback into prepare_job It's caused by a25fe9259b68c90033850033ad1b0f20b41e8980 "drm/scheduler: rename dependency callback into prepare_job" Signed-off-by: bobzhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/scheduler/sched_entity.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/scheduler/sched_entity.c b/drivers/gpu/drm/scheduler/sched_entity.c index 2a5f2a17dcf44..6b278e18dabea 100644 --- a/drivers/gpu/drm/scheduler/sched_entity.c +++ b/drivers/gpu/drm/scheduler/sched_entity.c @@ -346,7 +346,7 @@ static void drm_sched_entity_kill_jobs(struct drm_sched_entity *entity) struct drm_sched_fence *s_fence = job->s_fence; /* Wait for all dependencies to avoid data corruptions */ - while ((f = job->sched->ops->dependency(job, entity))) { + while ((f = job->sched->ops->prepare_job(job, entity))) { dma_fence_wait(f, false); dma_fence_put(f); } @@ -580,7 +580,7 @@ struct drm_sched_job *drm_sched_entity_pop_job(struct drm_sched_entity *entity) #ifdef HAVE_STRUCT_XARRAY drm_sched_job_dependency(sched_job, entity))) { #else - sched->ops->dependency(sched_job, entity))) { + sched->ops->prepare_job(sched_job, entity))) { #endif trace_drm_sched_job_wait_dep(sched_job, entity->dependency); From b77e7a3c77a68f3745ebd496fdef0fafb393b341 Mon Sep 17 00:00:00 2001 From: Daniel Phillips Date: Sun, 5 Mar 2023 22:54:35 -0800 Subject: [PATCH 0948/1868] amdkfd: Fix memory availability double accounting of kfd pinned objects Pinned objects that are not kfd objects reduce the total vram available to kfd, so we subtract the total size of pinned objects from kdf vram availability. However this double counts objects pinned by kfd itself, because they are counted both as used and pinned. So track the total size of objects pinned by kfd and add it back to kfd availability to remove the double accounting. Signed-off-by: Daniel Phillips Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 11 +++++++++++ 2 files changed, 12 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index 6b4bf3c61b3d7..e77475d87b264 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -109,6 +109,7 @@ struct amdgpu_kfd_dev { struct kfd_dev *dev; int64_t vram_used[MAX_XCP]; uint64_t vram_used_aligned[MAX_XCP]; + atomic64_t vram_pinned; bool init_complete; struct work_struct reset_work; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index e433d2db53b13..3cb85b5c6c599 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -1596,6 +1596,11 @@ int amdgpu_amdkfd_gpuvm_pin_bo(struct amdgpu_bo *bo, u32 domain) pr_err("Error in Pinning BO to domain: %d\n", domain); amdgpu_bo_sync_wait(bo, AMDGPU_FENCE_OWNER_KFD, false); + + if (!ret && bo->tbo.resource->mem_type == TTM_PL_VRAM) + atomic64_add(amdgpu_bo_size(bo), + &amdgpu_ttm_adev(bo->tbo.bdev)->kfd.vram_pinned); + out: amdgpu_bo_unreserve(bo); return ret; @@ -1618,6 +1623,11 @@ void amdgpu_amdkfd_gpuvm_unpin_bo(struct amdgpu_bo *bo) return; amdgpu_bo_unpin(bo); + + if (bo->tbo.resource->mem_type == TTM_PL_VRAM) + atomic64_sub(amdgpu_bo_size(bo), + &amdgpu_ttm_adev(bo->tbo.bdev)->kfd.vram_pinned); + amdgpu_bo_unreserve(bo); } @@ -1777,6 +1787,7 @@ size_t amdgpu_amdkfd_get_available_memory(struct amdgpu_device *adev, vram_available = KFD_XCP_MEMORY_SIZE(adev, xcp_id) - adev->kfd.vram_used_aligned[xcp_id] - atomic64_read(&adev->vram_pin_size) + + atomic64_read(&adev->kfd.vram_pinned) - reserved_for_pt - reserved_for_ras; From bcc5a1285b34e9d23090aa465d307c4c42617efc Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Mon, 6 Mar 2023 17:16:56 +0800 Subject: [PATCH 0949/1868] drm/amdkcl: Using include_next to reference the drm_gem_atomic_helper.h Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 2 -- include/kcl/header/drm/drm_gem_atomic_helper.h | 9 +++++++++ 2 files changed, 9 insertions(+), 2 deletions(-) create mode 100644 include/kcl/header/drm/drm_gem_atomic_helper.h diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index ff64d9a7ba4bc..82a3dd396037a 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -26,9 +26,7 @@ #include #include -#ifdef HAVE_DRM_GEM_PLANE_HELPER_PREPARE_FB #include -#endif #include #include diff --git a/include/kcl/header/drm/drm_gem_atomic_helper.h b/include/kcl/header/drm/drm_gem_atomic_helper.h new file mode 100644 index 0000000000000..ba17f457edc4f --- /dev/null +++ b/include/kcl/header/drm/drm_gem_atomic_helper.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DRM_GEM_ATOMIC_HELPER_PREPARE_H_H_ +#define _KCL_HEADER_DRM_GEM_ATOMIC_HELPER_PREPARE_H_H_ + +#if defined(HAVE_DRM_GEM_PLANE_HELPER_PREPARE_FB) +#include_next +#endif + +#endif From 3d7ba61d74c36b54d527d8d158818441eec04c1b Mon Sep 17 00:00:00 2001 From: bobzhou Date: Wed, 15 Mar 2023 14:20:22 +0800 Subject: [PATCH 0950/1868] drm/amdkcl: Rename DCN config to FP It's cauesd by 284c5833d58fd8c267d2d0858528e8a997183352 "drm/amd/display: Rename DCN config to FP" Signed-off-by: bobzhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 2 +- drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +- .../drm/amd/display/dc/link/protocols/link_dp_capability.c | 6 +++--- drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c | 2 +- drivers/gpu/drm/amd/dkms/Makefile | 4 ++-- 5 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index 6235e8de87805..0a5625f8e878a 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -403,7 +403,7 @@ bool dm_helpers_dp_mst_write_payload_allocation_table( mst_port = aconnector->mst_output_port; -#if defined(CONFIG_DRM_AMD_DC_DCN) +#if defined(CONFIG_DRM_AMD_DC_FP) link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link); #endif diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index f50ae8e8cbf73..74a1d9d286663 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1279,7 +1279,7 @@ static void disable_dangling_plane(struct dc *dc, struct dc_state *context) * The OTG is set to disable on falling edge of VUPDATE so the plane disable * will still get it's double buffer update. */ -#ifdef CONFIG_DRM_AMD_DC_DCN +#ifdef CONFIG_DRM_AMD_DC_FP if (is_phantom) { if (tg->funcs->disable_phantom_crtc) tg->funcs->disable_phantom_crtc(tg); diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c index 70dc293aa11ad..8c1c1b1be90b3 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c @@ -157,7 +157,7 @@ uint8_t dp_parse_lttpr_repeater_count(uint8_t lttpr_repeater_count) return 0; // invalid value } -#if defined(CONFIG_DRM_AMD_DC_DCN) +#if defined(CONFIG_DRM_AMD_DC_FP) uint32_t link_bw_kbps_from_raw_frl_link_rate_data(uint8_t bw) { switch (bw) { @@ -235,7 +235,7 @@ static union dp_cable_id intersect_cable_id( return out; } -#if defined(CONFIG_DRM_AMD_DC_DCN) +#if defined(CONFIG_DRM_AMD_DC_FP) /* * Return PCON's post FRL link training supported BW if its non-zero, otherwise return max_supported_frl_bw. */ @@ -1158,7 +1158,7 @@ static void get_active_converter_info( translate_dpcd_max_bpc( hdmi_color_caps.bits.MAX_BITS_PER_COLOR_COMPONENT); -#if defined(CONFIG_DRM_AMD_DC_DCN) +#if defined(CONFIG_DRM_AMD_DC_FP) if (link->dc->caps.dp_hdmi21_pcon_support) { union hdmi_encoded_link_bw hdmi_encoded_link_bw; diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c index 8c5727d81c1c4..bba4d8cb1fc74 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c @@ -319,7 +319,7 @@ static struct timing_generator_funcs dcn32_tg_funcs = { .enable_crtc = optc32_enable_crtc, .disable_crtc = optc32_disable_crtc, .phantom_crtc_post_enable = optc32_phantom_crtc_post_enable, -#ifdef CONFIG_DRM_AMD_DC_DCN +#ifdef CONFIG_DRM_AMD_DC_FP .disable_phantom_crtc = optc32_disable_phantom_otg, #endif /* used by enable_timing_synchronization. Not need for FPGA */ diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index c90d2e3182c23..b4e3343fd05d5 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -202,8 +202,8 @@ endif # if core2 isn't in the compiler flags ifndef CONFIG_ARM64 ifeq ($(filter %core2, $(KBUILD_CFLAGS)),) -export CONFIG_DRM_AMD_DC_DCN=y -subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_DCN +export CONFIG_DRM_AMD_DC_FP=y +subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_FP endif endif From bc1847cc4bc5064e3a2624bfadedee457cdbdbf3 Mon Sep 17 00:00:00 2001 From: bobzhou Date: Tue, 14 Mar 2023 20:45:51 +0800 Subject: [PATCH 0951/1868] drm/amdkcl: wrap code under macro HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS It's caused by c602664a579de061dba08beb690f2718e4fb1b52 "drm/amd/display: Pass the right info to drm_dp_remove_payload" Signed-off-by: bobzhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index 0a5625f8e878a..eb025ed21e72f 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -295,7 +295,7 @@ void dm_helpers_dp_update_branch_info( struct dc_context *ctx, const struct dc_link *link) {} - +#if defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS) static void dm_helpers_construct_old_payload( struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_topology_state *mst_state, @@ -327,6 +327,7 @@ static void dm_helpers_construct_old_payload( old_payload->time_slots = allocated_time_slots; old_payload->pbn = allocated_time_slots * pbn_per_slot; } +#endif /* * Writes payload allocation table in immediate downstream device. From 799073ad8f6e0f435a723da9389f5dd0d2ee7e79 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Fri, 17 Mar 2023 10:45:23 +0800 Subject: [PATCH 0952/1868] drm/amdkcl: kcl-cleanup DEFINE_SRCU for legacy os Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkfd/kfd_module.c | 9 --------- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 13 ------------- 2 files changed, 22 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_module.c b/drivers/gpu/drm/amd/amdkfd/kfd_module.c index ea7aca6d9d874..5f8093e03d340 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_module.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_module.c @@ -26,11 +26,6 @@ #include "kfd_priv.h" #include "amdgpu_amdkfd.h" -#ifndef DEFINE_SRCU -void kfd_init_processes_srcu(void); -void kfd_cleanup_processes_srcu(void); -#endif - static int kfd_init(void) { int err; @@ -75,10 +70,6 @@ static int kfd_init(void) kfd_debugfs_init(); -#ifndef DEFINE_SRCU - kfd_init_processes_srcu(); -#endif - return 0; err_create_wq: diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index f6fb824acc54d..32118d07a9a7f 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -52,20 +52,7 @@ struct mm_struct; DEFINE_HASHTABLE(kfd_processes_table, KFD_PROCESS_TABLE_SIZE); DEFINE_MUTEX(kfd_processes_mutex); -#ifndef DEFINE_SRCU -struct srcu_struct kfd_processes_srcu; -void kfd_init_processes_srcu(void) -{ - init_srcu_struct(&kfd_processes_srcu); -} - -void kfd_cleanup_processes_srcu(void) -{ - cleanup_srcu_struct(&kfd_processes_srcu); -} -#else DEFINE_SRCU(kfd_processes_srcu); -#endif /* For process termination handling */ static struct workqueue_struct *kfd_process_wq; From 0d91daae2fd8a885ab475584a6d0cbe8afbd0202 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Fri, 17 Mar 2023 10:08:24 +0800 Subject: [PATCH 0953/1868] drm/amdkcl: kcl-cleanup HAVE_DRM_EDID_TO_ELD Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 6 -- .../gpu/drm/amd/dkms/m4/drm-edid-to-eld.m4 | 19 ------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - include/kcl/backport/kcl_drm_encoder.h | 57 ------------------- 4 files changed, 83 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-edid-to-eld.m4 delete mode 100644 include/kcl/backport/kcl_drm_encoder.h diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 3eaaad793a8a0..fee63b65eb502 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -541,12 +541,6 @@ /* drm_dsc_compute_rc_parameters() is available */ #define HAVE_DRM_DSC_COMPUTE_RC_PARAMETERS 1 -/* drm_edid_to_eld() are available */ -/* #undef HAVE_DRM_EDID_TO_ELD */ - -/* drm_encoder_find() wants file_priv */ -#define HAVE_DRM_ENCODER_FIND_VALID_WITH_FILE 1 - /* drm_fbdev_generic_setup() is available */ /* #undef HAVE_DRM_FBDEV_GENERIC_SETUP */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-edid-to-eld.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-edid-to-eld.m4 deleted file mode 100644 index f0efb113db67b..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm-edid-to-eld.m4 +++ /dev/null @@ -1,19 +0,0 @@ -dnl # -dnl # commit v4.14-rc3-594-g79436a1c9bcc -dnl # drm/edid: make drm_edid_to_eld() static -dnl # -dnl # commit v3.1-rc6-139-g76adaa34db40 -dnl # drm: support routines for HDMI/DP ELD -dnl # -AC_DEFUN([AC_AMDGPU_DRM_EDID_TO_ELD], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include - ], [ - drm_edid_to_eld(NULL, NULL); - ], [drm_edid_to_eld], [drivers/gpu/drm/drm_edid.c], [ - AC_DEFINE(HAVE_DRM_EDID_TO_ELD, 1, - [drm_edid_to_eld() are available]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 962b431cf49fb..f112bfa431c28 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -82,7 +82,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_FB_HELPER_FILL_INFO AC_AMDGPU_DRM_FB_HELPER_INIT AC_AMDGPU_DRM_HELPER_FORCE_DISABLE_ALL - AC_AMDGPU_DRM_EDID_TO_ELD AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS AC_AMDGPU_DRM_EDID AC_AMDGPU_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER diff --git a/include/kcl/backport/kcl_drm_encoder.h b/include/kcl/backport/kcl_drm_encoder.h deleted file mode 100644 index 0efc8f747defd..0000000000000 --- a/include/kcl/backport/kcl_drm_encoder.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright (c) 2006 Luc Verhaegen (quirks list) - * Copyright (c) 2007-2008 Intel Corporation - * Jesse Barnes - * Copyright 2010 Red Hat, Inc. - * - * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from - * FB layer. - * Copyright (C) 2006 Dennis Munsie - * For codes copied from drivers/gpu/drm/drm_edid.c - * - * Copyright (c) 2016 Intel Corporation - * For codes copied from include/drm/drm_encoder.h - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sub license, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ -#ifndef KCL_BACKPORT_KCL_DRM_ENCODER_H -#define KCL_BACKPORT_KCL_DRM_ENCODER_H - -#include -#include - -/* Copied from drivers/gpu/drm/drm_edid.c and modified for KCL */ -#if defined(HAVE_DRM_EDID_TO_ELD) -static inline -int _kcl_drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) -{ - int ret; - - ret = drm_add_edid_modes(connector, edid); - - if (drm_edid_is_valid(edid)) - drm_edid_to_eld(connector, edid); - - return ret; -} -#define drm_add_edid_modes _kcl_drm_add_edid_modes -#endif - -#endif From 68b446665ac44f2534f9dbd14f305b5238fe9db1 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Fri, 17 Mar 2023 13:30:18 +0800 Subject: [PATCH 0954/1868] drm/amdkcl: Remove the temp build directory Sometimes there are temp build directory left after execute the command "make -f dirvers/gpu/drm/amd/dkms/Makefile.config". So remove them all. Signed-off-by: Ma Jun Reviewd-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Makefile.config | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/Makefile.config b/drivers/gpu/drm/amd/dkms/Makefile.config index f6d23defbaae6..211fd393987e3 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile.config +++ b/drivers/gpu/drm/amd/dkms/Makefile.config @@ -15,7 +15,7 @@ config: force clean: force @( \ cd $(srctree)/$(dkmstree); \ - rm -f aclocal.m4 config.* configure config/*.in* \ + rm -rf aclocal.m4 config.* configure config/*.in* build_*\ ) .PHONY: all force From 5033088a2909b017009122eabfeb0f9408964274 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Fri, 17 Mar 2023 13:41:41 +0800 Subject: [PATCH 0955/1868] drm/amdkcl: Fix the bug when check luminance_range Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 2 +- drivers/gpu/drm/amd/dkms/m4/drm-display-info.m4 | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index fee63b65eb502..b6b56a4ce5d32 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -350,7 +350,7 @@ #define HAVE_DRM_DISPLAY_INFO_MONITOR_RANGE 1 /* display_info->luminance_range is available */ -/* #undef HAVE_DRM_DISPLAY_INFO_LUMINANCE_RANGE */ +#define HAVE_DRM_DISPLAY_INFO_LUMINANCE_RANGE 1 /* display_info->max_dsc_bpp is available */ /* #undef HAVE_DRM_DISPLAY_INFO_MAX_DSC_BPP */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-display-info.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-display-info.m4 index f72df7f1ac808..ad9ebac619d6e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-display-info.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-display-info.m4 @@ -64,7 +64,8 @@ AC_DEFUN([AC_AMDGPU_DRM_DISPLAY_INFO_LUMINANCE_RANGE], [ #include ],[ struct drm_display_info *display_info = NULL; - display_info->luminance_range=NULL; + struct drm_luminance_range_info *luminance_range; + luminance_range = &display_info->luminance_range; ],[ AC_DEFINE(HAVE_DRM_DISPLAY_INFO_LUMINANCE_RANGE, 1, [display_info->luminance_range is available]) From 65113178dd1a073699540c9b9d052aa2ac38a8d9 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Fri, 17 Mar 2023 10:53:00 +0800 Subject: [PATCH 0956/1868] drm/amdkcl: Fix the return value of idr_init_base Signed-off-by: Ma Jun Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 6 ++++++ drivers/gpu/drm/amd/dkms/m4/idr.m4 | 3 +-- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index b6b56a4ce5d32..7540db90261f8 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -756,6 +756,9 @@ /* i2c_new_client_device() is enabled */ #define HAVE_I2C_NEW_CLIENT_DEVICE 1 +/* idr_init_base() is available */ +#define HAVE_IDR_INIT_BASE 1 + /* idr_remove return void pointer */ #define HAVE_IDR_REMOVE_RETURN_VOID_POINTER 1 @@ -1075,6 +1078,9 @@ /* drm_plane_helper_funcs->prepare_fb() wants p,p arg */ #define HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_PREPARE_FB_PP 1 +/* ide->idr_base is available */ +#define HAVE_STRUCT_IDE_IDR_BASE 1 + /* struct smca_bank is available */ /* #undef HAVE_STRUCT_SMCA_BANK */ diff --git a/drivers/gpu/drm/amd/dkms/m4/idr.m4 b/drivers/gpu/drm/amd/dkms/m4/idr.m4 index 7816e84901c5a..1c678e3c401b7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/idr.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/idr.m4 @@ -27,8 +27,7 @@ AC_DEFUN([AC_AMDGPU_IDR_INIT_BASE], [ AC_KERNEL_TRY_COMPILE([ #include ], [ - void *i; - i = idr_init_base(NULL, 0); + idr_init_base(NULL, 0); ], [ AC_DEFINE(HAVE_IDR_INIT_BASE, 1, [idr_init_base() is available]) From d42a2217202cee19961b4e0636d06804112300ca Mon Sep 17 00:00:00 2001 From: bobzhou Date: Fri, 17 Mar 2023 10:13:24 +0800 Subject: [PATCH 0957/1868] drm/amdkcl: fix macro for amdgpu_acpi_should_gpu_reset() It's caused by ed199fb30b0178ed82311c4f0d5515b0718c9cc4 "drm/amdgpu: reposition the gpu reset checking for reuse" The amdgpu_acpi_should_gpu_reset() is moved, but the kcl macro haven't been include, so fix the kcl macro in new amdgpu_acpi_should_gpu_reset(). Signed-off-by: bobzhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c index 36de0c9788bbf..d987b9b16e798 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c @@ -1378,7 +1378,11 @@ bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) return false; #if IS_ENABLED(CONFIG_SUSPEND) +#ifdef HAVE_PM_SUSPEND_TARGET_STATE return pm_suspend_target_state != PM_SUSPEND_TO_IDLE; +#else + return false; +#endif #else return true; #endif From d6615f6bc779677c46d1bc33ba44fdefb1059a31 Mon Sep 17 00:00:00 2001 From: bobzhou Date: Fri, 17 Mar 2023 11:00:18 +0800 Subject: [PATCH 0958/1868] drm/amdkcl: wrap code under macro HAVE_MMU_NOTIFIER_PUT It's caused by 0e9398dcb6ecc5a2cde03a1224cd806278ac13e4 "drm/amdkfd: Fixed kfd_process cleanup on module exit." The non-upstream code in kfd_process_notifier_release() is moved into kfd_process_notifier_release_internal(). Signed-off-by: bobzhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 32118d07a9a7f..4084a71289876 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -1174,6 +1174,7 @@ static void kfd_process_destroy_delayed(struct rcu_head *rcu) static void kfd_process_notifier_release_internal(struct kfd_process *p) { int i; + struct mm_struct *mm = p->mm; cancel_delayed_work_sync(&p->eviction_work); cancel_delayed_work_sync(&p->restore_work); @@ -1208,7 +1209,12 @@ static void kfd_process_notifier_release_internal(struct kfd_process *p) srcu_read_unlock(&kfd_processes_srcu, idx); } +#ifdef HAVE_MMU_NOTIFIER_PUT mmu_notifier_put(&p->mmu_notifier); +#else + mmu_notifier_unregister_no_release(&p->mmu_notifier, mm); + mmu_notifier_call_srcu(&p->rcu, &kfd_process_destroy_delayed); +#endif } static void kfd_process_notifier_release(struct mmu_notifier *mn, From 77fe4d36d3f6c7165f3d13cb87c4d1473aee1869 Mon Sep 17 00:00:00 2001 From: bobzhou Date: Fri, 17 Mar 2023 11:04:11 +0800 Subject: [PATCH 0959/1868] drm/amdkcl: open the macro HAVE_DRM_DISPLAY_INFO_MAX_DSC_BPP In dkms-6.0 the HAVE_DRM_DISPLAY_INFO_MAX_DSC_BPP has been support, so open the macro. Signed-off-by: bobzhou Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/dkms/config/config.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 7540db90261f8..e814815c1e0d8 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -353,7 +353,7 @@ #define HAVE_DRM_DISPLAY_INFO_LUMINANCE_RANGE 1 /* display_info->max_dsc_bpp is available */ -/* #undef HAVE_DRM_DISPLAY_INFO_MAX_DSC_BPP */ +#define HAVE_DRM_DISPLAY_INFO_MAX_DSC_BPP 1 /* drm_dp_atomic_find_time_slots() is available */ #define HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS 1 From f8a4d68b25d720628d207cd5ded3efa679fa5acf Mon Sep 17 00:00:00 2001 From: bobzhou Date: Mon, 20 Mar 2023 14:41:20 +0800 Subject: [PATCH 0960/1868] drm/amdkcl: fake drm_warn macro It's caused by 2b7cb41b58aa950da4a61b21cfa9a62a49127edf "drm/amd/display/amdgpu_dm: Refactor register_backlight_device()" Signed-off-by: bobzhou Reviewed-by: Guchun Chen Reviewed-by: Leslie Shi --- include/kcl/kcl_drm_print.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index 71a5b6f419e46..c71867326f13b 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -79,6 +79,11 @@ void kcl_drm_err(const char *format, ...); #define HAVE_DRM_ERR_MACRO #endif /* drm_err */ +#ifndef drm_warn +#define drm_warn(drm, fmt, ...) \ + dev_warn((drm)->dev, "[drm] " fmt, ##__VA_ARGS__) +#endif /* drm_warn */ + #if !defined(DRM_UT_VBL) #define DRM_UT_VBL 0x20 #endif From e3c4def959ba916aa1b012f8f9648b7fb3b58d56 Mon Sep 17 00:00:00 2001 From: bobzhou Date: Mon, 20 Mar 2023 16:09:13 +0800 Subject: [PATCH 0961/1868] drm/amdkcl: Drop unnecessary FP guards [Why & How] drm-next branch code drop unnecessary FP guards, so clean up FP guards under kcl macro. Signed-off-by: bobzhou Reviewed-by: majun --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 2 -- drivers/gpu/drm/amd/display/dc/core/dc.c | 2 -- .../drm/amd/display/dc/link/protocols/link_dp_capability.c | 6 ------ drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c | 2 -- 4 files changed, 12 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index eb025ed21e72f..2f51d94082cf1 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -404,9 +404,7 @@ bool dm_helpers_dp_mst_write_payload_allocation_table( mst_port = aconnector->mst_output_port; -#if defined(CONFIG_DRM_AMD_DC_FP) link_coding_cap = dc_link_dp_mst_decide_link_encoding_format(aconnector->dc_link); -#endif if (enable) { diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 74a1d9d286663..92b2a679f1663 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1279,12 +1279,10 @@ static void disable_dangling_plane(struct dc *dc, struct dc_state *context) * The OTG is set to disable on falling edge of VUPDATE so the plane disable * will still get it's double buffer update. */ -#ifdef CONFIG_DRM_AMD_DC_FP if (is_phantom) { if (tg->funcs->disable_phantom_crtc) tg->funcs->disable_phantom_crtc(tg); } -#endif } } diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c index 8c1c1b1be90b3..3434b69ca6826 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c @@ -157,7 +157,6 @@ uint8_t dp_parse_lttpr_repeater_count(uint8_t lttpr_repeater_count) return 0; // invalid value } -#if defined(CONFIG_DRM_AMD_DC_FP) uint32_t link_bw_kbps_from_raw_frl_link_rate_data(uint8_t bw) { switch (bw) { @@ -177,7 +176,6 @@ uint32_t link_bw_kbps_from_raw_frl_link_rate_data(uint8_t bw) return 0; } -#endif static enum dc_link_rate linkRateInKHzToLinkRateMultiplier(uint32_t link_rate_in_khz) { @@ -235,7 +233,6 @@ static union dp_cable_id intersect_cable_id( return out; } -#if defined(CONFIG_DRM_AMD_DC_FP) /* * Return PCON's post FRL link training supported BW if its non-zero, otherwise return max_supported_frl_bw. */ @@ -263,7 +260,6 @@ static uint32_t intersect_frl_link_bw_support( return supported_bw_in_kbps; } -#endif static enum clock_source_id get_clock_source_id(struct dc_link *link) { @@ -1158,7 +1154,6 @@ static void get_active_converter_info( translate_dpcd_max_bpc( hdmi_color_caps.bits.MAX_BITS_PER_COLOR_COMPONENT); -#if defined(CONFIG_DRM_AMD_DC_FP) if (link->dc->caps.dp_hdmi21_pcon_support) { union hdmi_encoded_link_bw hdmi_encoded_link_bw; @@ -1179,7 +1174,6 @@ static void get_active_converter_info( if (link->dpcd_caps.dongle_caps.dp_hdmi_frl_max_link_bw_in_kbps > 0) link->dpcd_caps.dongle_caps.extendedCapValid = true; } -#endif if (link->dpcd_caps.dongle_caps.dp_hdmi_max_pixel_clk_in_khz != 0) link->dpcd_caps.dongle_caps.extendedCapValid = true; diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c index bba4d8cb1fc74..00094f0e84706 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c @@ -319,9 +319,7 @@ static struct timing_generator_funcs dcn32_tg_funcs = { .enable_crtc = optc32_enable_crtc, .disable_crtc = optc32_disable_crtc, .phantom_crtc_post_enable = optc32_phantom_crtc_post_enable, -#ifdef CONFIG_DRM_AMD_DC_FP .disable_phantom_crtc = optc32_disable_phantom_otg, -#endif /* used by enable_timing_synchronization. Not need for FPGA */ .is_counter_moving = optc1_is_counter_moving, .get_position = optc1_get_position, From 44af5c7c67911aa1e197a2fa83d19ebcbb1c94fe Mon Sep 17 00:00:00 2001 From: bobzhou Date: Wed, 22 Mar 2023 17:13:54 +0800 Subject: [PATCH 0962/1868] drm/amdkcl: wrap unused variable under HAVE_MMU_NOTIFIER_PUT When HAVE_MMU_NOTIFIER_PUT is closed, mm variable isn't used. So move it into macro HAVE_MMU_NOTIFIER_PUT. Signed-off-by: bobzhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 4084a71289876..af4848f0511fc 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -1174,7 +1174,9 @@ static void kfd_process_destroy_delayed(struct rcu_head *rcu) static void kfd_process_notifier_release_internal(struct kfd_process *p) { int i; +#ifndef HAVE_MMU_NOTIFIER_PUT struct mm_struct *mm = p->mm; +#endif cancel_delayed_work_sync(&p->eviction_work); cancel_delayed_work_sync(&p->restore_work); From 43af37f697f3d628c83a74720bcfc85a040e9727 Mon Sep 17 00:00:00 2001 From: bobzhou Date: Tue, 21 Mar 2023 11:09:10 +0800 Subject: [PATCH 0963/1868] drm/amdkcl: modify the C standard to gnu99 for legacy gcc [Why & How] Upstream patches now uses gnu11/gnu99 as the default C standard version. However, gcc in legacy OS still uses gnu89, which will introduce a standard build gap leading to a DKMS build failure possibly. Add KBUILD_CFLAGS check to move gnu89 to gnu99 if KBUILD_CFLAGS still uses gnu89. Signed-off-by: bobzhou Reviewed-by: Guchun Chen Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Makefile | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index b4e3343fd05d5..ff21ca820d731 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -207,6 +207,16 @@ subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_FP endif endif +# v5.17-rc4-3-ge8c07082a810 (Kbuild: move to -std=gnu11) +# Upstream patches now uses gnu11/gnu99 as the default C standard version. +# However, gcc in legacy OS still uses gnu89, which will introduce a standard +# build gap leading to a DKMS build failure possibly. So add below check to +# move gnu89 to gnu99 if KBUILD_CFLAGS still uses gnu89. +ifeq ($(findstring gnu89,$(KBUILD_CFLAGS)),gnu89) +KBUILD_CFLAGS := $(subst gnu89,gnu99,$(KBUILD_CFLAGS)) +$(warning "The local C standard(gnu89) doesn't match kernel default C standard(gnu11/gnu99)") +endif + include $(src)/amd/dkms/Makefile.drm_ttm_helper include $(src)/amd/dkms/Makefile.drm_buddy From 81826272e221a70ec5659f630be5385d80dbf67d Mon Sep 17 00:00:00 2001 From: Rodrigo Siqueira Date: Tue, 21 Mar 2023 11:37:33 -0600 Subject: [PATCH 0964/1868] drm/display: Add missing OLED Vesa brightnesses definitions Reviewed-by: Harry Wentland Signed-off-by: Rodrigo Siqueira --- include/drm/display/drm_dp.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h index 173548c6473a9..a78d23c91c8d4 100644 --- a/include/drm/display/drm_dp.h +++ b/include/drm/display/drm_dp.h @@ -1016,6 +1016,8 @@ # define DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP (1 << 5) # define DP_EDP_DYNAMIC_BACKLIGHT_CAP (1 << 6) # define DP_EDP_VBLANK_BACKLIGHT_UPDATE_CAP (1 << 7) +#define DP_EDP_OLED_VESA_BRIGHTNESS_ON 0x80 +# define DP_EDP_OLED_VESA_CAP (1 << 4) #define DP_EDP_GENERAL_CAP_2 0x703 # define DP_EDP_OVERDRIVE_ENGINE_ENABLED (1 << 0) From bcb28f3822664d8d4bb65d21e51d9bff652852c7 Mon Sep 17 00:00:00 2001 From: bobzhou Date: Mon, 20 Mar 2023 16:30:48 +0800 Subject: [PATCH 0965/1868] drm/amdkcl: wrap code under macro HAVE_DRM_DISPLAY_INFO_MAX_DSC_BPP v2 It's caused by c88ea46c1474c09939bf1546d5a44e8e42c23361 "drm/amd/display: Add height granularity limitation for dsc slice height calculation" v2: add support for struct dsc_options and reuse legacy data fill it. Signed-off-by: bobzhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index c71e8534b36c0..ad522f0eb1ba0 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -958,7 +958,11 @@ static void set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params *p drm_connector = ¶ms[i].aconnector->base; dc_dsc_get_default_config_option(params[i].sink->ctx->dc, &dsc_options); +#ifdef HAVE_DRM_DISPLAY_INFO_MAX_DSC_BPP dsc_options.max_target_bpp_limit_override_x16 = drm_connector->display_info.max_dsc_bpp * 16; +#else + dsc_options.max_target_bpp_limit_override_x16 = params[i].sink->edid_caps.panel_patch.max_dsc_target_bpp_limit * 16; +#endif memset(¶ms[i].timing->dsc_cfg, 0, sizeof(params[i].timing->dsc_cfg)); if (vars[i + k].dsc_enabled && dc_dsc_compute_config( From 3eb6e6b6612fc43b8fe4544df87a57d4701d9f71 Mon Sep 17 00:00:00 2001 From: bobzhou Date: Thu, 23 Mar 2023 15:19:56 +0800 Subject: [PATCH 0966/1868] drm/amdkcl: wrap code under macro HAVE_HDR_SINK_METADATA It's caused by a5465aa219a1c3ef1365a12b00e2d51e110af538 "drm/amd/display/amdgpu_dm: Move most backlight setup into setup_backlight_device()" Signed-off-by: bobzhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 3e60388c507cf..39f901c88e98a 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4775,8 +4775,9 @@ static void setup_backlight_device(struct amdgpu_display_manager *dm, dm->brightness[bl_idx] = AMDGPU_MAX_BL_LEVEL; dm->backlight_link[bl_idx] = link; dm->num_of_edps++; - +#ifdef HAVE_HDR_SINK_METADATA update_connector_ext_caps(aconnector); +#endif } static void amdgpu_set_panel_orientation(struct drm_connector *connector); From 62910beb5be36be2f62102c09a04fc27207da204 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Sat, 1 Apr 2023 12:01:56 +0800 Subject: [PATCH 0967/1868] drm/amdgpu: [hybrid] remove sync obj in the job It's caused by 1728baa7e4e60054bf13dd9b1212d133cbd53b3f "drm/amdgpu: use scheduler dependencies for CS" Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 4e3f55f8a0d41..6ed00405bdd5c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -650,7 +650,7 @@ static int amdgpu_cs_pass2(struct amdgpu_cs_parser *p) } for (i = 0; i < p->gang_size; ++i) { - r = amdgpu_sem_add_cs(p->ctx, p->entities[i], &p->jobs[i]->sync); + r = amdgpu_sem_add_cs(p->ctx, p->entities[i], &p->sync); if (r) return r; } From fc3389bd68390a1195e7113143ed63c3ddc47928 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 3 Apr 2023 16:07:11 +0800 Subject: [PATCH 0968/1868] drm/amdkcl: change included file from ttm_bo_api.h to ttm_bo.h It's caused by a3185f91d0579b61a0a0dce3df1c67d6e324ebc8 "drm/ttm: merge ttm_bo_api.h and ttm_bo_driver.h v2" Signed-off-by: Asher Song --- drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c b/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c index 04b308171928f..3f3a70274a81c 100644 --- a/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c +++ b/drivers/gpu/drm/amd/backport/kcl_drm_gem_ttm_helper.c @@ -4,8 +4,7 @@ #include #include -#include -#include +#include #include #include #include From 5d08a15771f5801640518c73a7ecbfdb389e441b Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 11 Oct 2023 14:44:21 +0800 Subject: [PATCH 0969/1868] drm/amdkcl: test whether apple_gmux.h is available and fake apple_gmux_detect() It's caused by 1e98231de4609b9e4597b52d0f29bb664e4938d2 "drm/amdgpu: register a vga_switcheroo client for MacBooks with apple-gmux" Signed-off-by: bobzhou Reviewed-by: Leslie Shi Reviewed-by: Flora Cui Signed-off-by: Asher Song --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 16 +++++--------- .../gpu/drm/amd/dkms/m4/apple_gmux_detect.m4 | 16 ++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 | 5 +++++ include/kcl/header/linux/apple-gmux.h | 9 ++++++++ include/kcl/kcl_apple-gmux.h | 21 +++++++++++++++++++ 7 files changed, 58 insertions(+), 11 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/apple_gmux_detect.m4 create mode 100644 include/kcl/header/linux/apple-gmux.h create mode 100644 include/kcl/kcl_apple-gmux.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index b4c60325bd5d0..98902bf9e06b1 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -104,4 +104,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index e814815c1e0d8..3f5868501c740 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -373,6 +373,9 @@ /* struct drm_dp_aux has member named 'drm_dev' */ #define HAVE_DRM_DP_AUX_DRM_DEV 1 +/* apple_gmux_detect() is available */ +#define HAVE_APPLE_GMUX_DETECT 1 + /* drm_dp_calc_pbn_mode() wants 3args */ #define HAVE_DRM_DP_CALC_PBN_MODE_3ARGS 1 @@ -813,17 +816,8 @@ /* ktime_t is union */ /* #undef HAVE_KTIME_IS_UNION */ -/* kvcalloc() is available */ -#define HAVE_KVCALLOC 1 - -/* kvfree() is available */ -#define HAVE_KVFREE 1 - -/* kvmalloc_array() is available */ -#define HAVE_KVMALLOC_ARRAY 1 - -/* kv[mz]alloc() are available */ -#define HAVE_KVZALLOC_KVMALLOC 1 +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_APPLE_GMUX_H 1 /* Define to 1 if you have the header file. */ #define HAVE_LINUX_BITS_H 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/apple_gmux_detect.m4 b/drivers/gpu/drm/amd/dkms/m4/apple_gmux_detect.m4 new file mode 100644 index 0000000000000..defc80545265e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/apple_gmux_detect.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v6.1-2256-gbd100f492c7e +dnl # platform/x86: apple-gmux: Add apple_gmux_detect() helper +dnl # +AC_DEFUN([AC_AMDGPU_APPLE_GMUX_DETECT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + apple_gmux_detect(NULL, NULL); + ],[ + AC_DEFINE(HAVE_APPLE_GMUX_DETECT, 1, + [apple_gmux_detect() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index f112bfa431c28..e62dff78afd7f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -193,6 +193,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV AC_AMDGPU_MIGRATE_VMA_FAULT_PAGE AC_AMDGPU_RB_ADD_CACHED + AC_AMDGPU_APPLE_GMUX_DETECT AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 index 2c9f72c524583..f99ed5020b2e7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 @@ -114,4 +114,9 @@ AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ dnl # dma-mapping: split dnl # AC_KERNEL_CHECK_HEADERS([linux/dma-map-ops.h]) + + dnl #v4.5-rc3-203-g2413306c2566 + dnl #apple-gmux: Add helper for presence detect + dnl + AC_KERNEL_CHECK_HEADERS([linux/apple-gmux.h]) ]) diff --git a/include/kcl/header/linux/apple-gmux.h b/include/kcl/header/linux/apple-gmux.h new file mode 100644 index 0000000000000..19c858a0be836 --- /dev/null +++ b/include/kcl/header/linux/apple-gmux.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_LINUX_APPLE_GMUX_H_H +#define _KCL_HEADER_LINUX_APPLE_GMUX_H_H + +#ifdef HAVE_LINUX_APPLE_GMUX_H +#include_next +#endif + +#endif diff --git a/include/kcl/kcl_apple-gmux.h b/include/kcl/kcl_apple-gmux.h new file mode 100644 index 0000000000000..27d96810046e7 --- /dev/null +++ b/include/kcl/kcl_apple-gmux.h @@ -0,0 +1,21 @@ +#ifndef AMDKCL_APPLE_GMUX_H +#define AMDKCL_APPLE_GMUX_H + +#include + +#ifndef HAVE_APPLE_GMUX_DETECT +#if IS_ENABLED(CONFIG_APPLE_GMUX) +static inline bool apple_gmux_detect(struct pnp_dev *pnp_dev, bool *indexed_ret) +{ + pr_warn_once("legacy kernel without apple_gmux_detect()\n"); + return false; +} +#else +static inline bool apple_gmux_detect(struct pnp_dev *pnp_dev, bool *indexed_ret) +{ + return false; +} +#endif +#endif + +#endif /* AMDKCL_APPLE_GMUX_H */ From 0d8115f42ed1a80d385b89ffcb539e541b4ee8b0 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 12 Apr 2023 16:52:08 +0800 Subject: [PATCH 0970/1868] drm/amdkcl: include linux/dma-resv.h in ttm_bo.h It's caused by a3185f91d0579b61a0a0dce3df1c67d6e324ebc8 "drm/ttm: merge ttm_bo_api.h and ttm_bo_driver.h v2" Signed-off-by: Asher Song --- include/drm/ttm/ttm_bo.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/drm/ttm/ttm_bo.h b/include/drm/ttm/ttm_bo.h index 977b6fd2404d2..168c0a3c57d88 100644 --- a/include/drm/ttm/ttm_bo.h +++ b/include/drm/ttm/ttm_bo.h @@ -35,6 +35,7 @@ #include #include +#include #include "ttm_device.h" #ifndef HAVE_CONFIG_H From 530047c312b8b4c664e14e2832e93d75843d6be8 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 12 Apr 2023 17:12:30 +0800 Subject: [PATCH 0971/1868] drm/amdkcl:Use amdkcl_ttm_resvp to check whether drm_gem_object->resv is available Signed-off-by: Asher Song --- drivers/gpu/drm/ttm/ttm_bo_util.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c index f2b0bf7747f5f..c6524f4574cf2 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_util.c +++ b/drivers/gpu/drm/ttm/ttm_bo_util.c @@ -578,7 +578,7 @@ static int ttm_bo_wait_free_node(struct ttm_buffer_object *bo, { long ret; - ret = dma_resv_wait_timeout(bo->base.resv, DMA_RESV_USAGE_BOOKKEEP, + ret = dma_resv_wait_timeout(amdkcl_ttm_resvp(bo), DMA_RESV_USAGE_BOOKKEEP, false, 15 * HZ); if (ret == 0) return -EBUSY; @@ -737,7 +737,7 @@ int ttm_bo_pipeline_gutting(struct ttm_buffer_object *bo) int ret; /* If already idle, no need for ghost object dance. */ - if (dma_resv_test_signaled(bo->base.resv, DMA_RESV_USAGE_BOOKKEEP)) { + if (dma_resv_test_signaled(amdkcl_ttm_resvp(bo), DMA_RESV_USAGE_BOOKKEEP)) { if (!bo->ttm) { /* See comment below about clearing. */ ret = ttm_tt_create(bo, true); @@ -774,7 +774,7 @@ int ttm_bo_pipeline_gutting(struct ttm_buffer_object *bo) ret = dma_resv_copy_fences(&amdkcl_ttm_resv(ghost), amdkcl_ttm_resvp(bo)); /* Last resort, wait for the BO to be idle when we are OOM */ if (ret) { - dma_resv_wait_timeout(bo->base.resv, DMA_RESV_USAGE_BOOKKEEP, + dma_resv_wait_timeout(amdkcl_ttm_resvp(bo), DMA_RESV_USAGE_BOOKKEEP, false, MAX_SCHEDULE_TIMEOUT); } From d541f28bccd0f9c4dc0d47a564283360485228c0 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 12 Apr 2023 21:28:19 +0800 Subject: [PATCH 0972/1868] drm/amdkcl: wrap code under macro HAVE_STRUCT_XARRAY It's caused by 4f91790b42ffba72d80434d901548979ab41dc7c "drm/amdgpu: use drm_sched_job_add_resv_dependencies for moves" Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c | 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 4 ++++ drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 2 ++ 5 files changed, 12 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 6ed00405bdd5c..eefb5bf2b6484 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -1409,11 +1409,13 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, fence = &p->jobs[i]->base.s_fence->scheduled; dma_fence_get(fence); +#ifdef HAVE_STRUCT_XARRAY r = drm_sched_job_add_dependency(&leader->base, fence); if (r) { dma_fence_put(fence); return r; } +#endif } if (p->gang_size > 1) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c index 13b401905d68f..97ead0dbffab0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c @@ -389,11 +389,13 @@ int amdgpu_sync_push_to_job(struct amdgpu_sync *sync, struct amdgpu_job *job) } dma_fence_get(f); +#ifdef HAVE_STRUCT_XARRAY r = drm_sched_job_add_dependency(&job->base, f); if (r) { dma_fence_put(f); return r; } +#endif } return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 069947f864f73..dd8e680d9b896 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -2562,11 +2562,15 @@ static int amdgpu_ttm_prepare_job(struct amdgpu_device *adev, adev->gart.bo); (*job)->vm_needs_flush = true; } +#ifndef HAVE_STRUCT_XARRAY + return 0; +#else if (!resv) return 0; return drm_sched_job_add_resv_dependencies(&(*job)->base, resv, DMA_RESV_USAGE_BOOKKEEP); +#endif } #ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c index b7a0be93bde7e..cc536b13f4e7f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c @@ -1167,11 +1167,13 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo, if (r) goto err_free; } else { +#ifdef HAVE_STRUCT_XARRAY r = drm_sched_job_add_resv_dependencies(&job->base, amdkcl_ttm_resvp(&bo->tbo), DMA_RESV_USAGE_KERNEL); if (r) goto err_free; +#endif f = amdgpu_job_submit(job); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c index 40f464a46e12f..07ce990fc9573 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c @@ -248,12 +248,14 @@ static int amdgpu_vm_sdma_update(struct amdgpu_vm_update_params *p, dma_resv_iter_begin(&cursor, amdkcl_ttm_resvp(&bo->tbo), DMA_RESV_USAGE_KERNEL); dma_resv_for_each_fence_unlocked(&cursor, fence) { dma_fence_get(fence); + #ifdef HAVE_STRUCT_XARRAY r = drm_sched_job_add_dependency(&p->job->base, fence); if (r) { dma_fence_put(fence); dma_resv_iter_end(&cursor); return r; } +#endif } dma_resv_iter_end(&cursor); From 2b6316ec7d67f66df70b9c69e7fdf7b2037015cb Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 14 Apr 2023 15:10:32 +0800 Subject: [PATCH 0973/1868] drm/amdkcl: define macro VM_ACCESS_FLAGS It's caused by cc03817c0e8417419ede18a8e0749c5b9699b135 "amdgpu: use VM_ACCESS_FLAGS" Signed-off-by: Asher Song --- include/kcl/kcl_mm.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/kcl/kcl_mm.h b/include/kcl/kcl_mm.h index a3fb87d51aa61..112aeb2591136 100644 --- a/include/kcl/kcl_mm.h +++ b/include/kcl/kcl_mm.h @@ -86,4 +86,10 @@ struct vm_area_struct *vma_lookup(struct mm_struct *mm, unsigned long addr) } #endif /* HAVE_VMA_LOOKUP */ +#ifndef VM_ACCESS_FLAGS +/* Copied from v5.6-12367-g6cb4d9a2870d mm/vma: introduce VM_ACCESS_FLAGS*/ +/* VMA basic access permission flags */ +#define VM_ACCESS_FLAGS (VM_READ | VM_WRITE | VM_EXEC) +#endif + #endif /* AMDKCL_MM_H */ From e0eb45477793fb8ad1fcc0e9454b443f0e3b52cb Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 6 Apr 2023 18:17:24 +0800 Subject: [PATCH 0974/1868] drm/amdkcl: clean-up HAVE_IS_FIRMWARE_FRAMEBUFFER Signed-off-by: Asher Song Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c | 23 ------------------- .../amd/dkms/m4/is-firmware-framebuffer.m4 | 13 ----------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - include/kcl/kcl_drm_fb.h | 4 ---- 5 files changed, 1 insertion(+), 42 deletions(-) delete mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c delete mode 100644 drivers/gpu/drm/amd/dkms/m4/is-firmware-framebuffer.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 0f953fafc56ab..306044881cd3d 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -8,7 +8,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_kthread.o kcl_io.o kcl_seq_file.o \ kcl_suspend.o kcl_pci.o kcl_mm.o kcl_memory.o kcl_sched.o \ kcl_fence.o kcl_reservation.o kcl_drm_cache.o \ - kcl_drm_fb.o kcl_drm_print.o kcl_fbmem.o \ + kcl_drm_fb.o kcl_drm_print.o \ kcl_drm_crtc.o kcl_drm_connector.o kcl_drm_atomic_helper.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_fs_read_write.o kcl_drm_aperture.o \ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c b/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c deleted file mode 100644 index 920cf50033339..0000000000000 --- a/drivers/gpu/drm/amd/amdkcl/kcl_fbmem.c +++ /dev/null @@ -1,23 +0,0 @@ -/* - * linux/drivers/video/fbmem.c - * - * Copyright (C) 1994 Martin Schaller - * - * 2001 - Documented with DocBook - * - Brad Douglas - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file COPYING in the main directory of this archive - * for more details. - */ - -#include - -#ifndef HAVE_IS_FIRMWARE_FRAMEBUFFER -bool is_firmware_framebuffer(struct apertures_struct *a) -{ - pr_warn_once("%s:enable the runtime pm\n", __func__); - return false; -} -EXPORT_SYMBOL(is_firmware_framebuffer); -#endif diff --git a/drivers/gpu/drm/amd/dkms/m4/is-firmware-framebuffer.m4 b/drivers/gpu/drm/amd/dkms/m4/is-firmware-framebuffer.m4 deleted file mode 100644 index 44d0db303a161..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/is-firmware-framebuffer.m4 +++ /dev/null @@ -1,13 +0,0 @@ -dnl # -dnl # commit a99952170b19db855b7b45fba8e263ddc5205a0c -dnl # drm/amdgpu: disable runpm if we are the primary adapter -dnl # - -AC_DEFUN([AC_AMDGPU_IS_FIRMWARE_FRAMEBUFFER], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([is_firmware_framebuffer], [include/linux/fb.h], [ - AC_DEFINE(HAVE_IS_FIRMWARE_FRAMEBUFFER, 1, [is_firmware_framebuffer() is available]) - ],[ - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index e62dff78afd7f..e6f277db256ca 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -149,7 +149,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_BITMAP_FUNCS AC_AMDGPU_STRUCT_KOBJ_TYPE AC_AMDGPU_CLOSE_FD - AC_AMDGPU_IS_FIRMWARE_FRAMEBUFFER AC_AMDGPU_DRM_VMA_OFFSET_NODE_READONLY_FIELD AC_AMDGPU_WW_MUTEX_TRYLOCK_CONTEXT_ARG AC_AMDGPU_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ARG diff --git a/include/kcl/kcl_drm_fb.h b/include/kcl/kcl_drm_fb.h index 795395d696484..9c0341fca3043 100644 --- a/include/kcl/kcl_drm_fb.h +++ b/include/kcl/kcl_drm_fb.h @@ -61,8 +61,4 @@ void drm_fb_helper_fill_info(struct fb_info *info, struct drm_fb_helper_surface_size *sizes); #endif -#ifndef HAVE_IS_FIRMWARE_FRAMEBUFFER -extern bool is_firmware_framebuffer(struct apertures_struct *a); -#endif - #endif From 0750a3f70f72beec0ae220d191a07e18c7765c99 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 23 Feb 2023 11:06:01 +0800 Subject: [PATCH 0975/1868] drm/amdkcl:kcl-cleanup HAVE_DRM_FBDEV_GENERIC_SETUP Change-Id: I77e289c6ba211d528916193ed2b37ff9759368fb Signed-off-by: Ma Jun Reviewed-by: Leslie Reviewed-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/Makefile | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 22 --------------- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 14 +--------- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 8 +----- drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h | 28 ------------------- drivers/gpu/drm/amd/dkms/config/config.h | 3 -- .../amd/dkms/m4/drm-fbdev-generic-setup.m4 | 16 ----------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - include/kcl/backport/kcl_drm_fb.h | 4 --- 9 files changed, 3 insertions(+), 95 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-fbdev-generic-setup.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index e275c73f81c68..37347b2d30374 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -66,7 +66,7 @@ amdgpu-y += amdgpu_device.o amdgpu_doorbell_mgr.o amdgpu_kms.o \ amdgpu_atombios.o atombios_crtc.o amdgpu_connectors.o \ atom.o amdgpu_fence.o amdgpu_ttm.o amdgpu_object.o amdgpu_gart.o \ amdgpu_encoders.o amdgpu_display.o amdgpu_i2c.o \ - amdgpu_fb.o amdgpu_gem.o amdgpu_ring.o \ + amdgpu_gem.o amdgpu_ring.o \ amdgpu_cs.o amdgpu_bios.o amdgpu_benchmark.o \ atombios_dp.o amdgpu_afmt.o amdgpu_trace_points.o \ atombios_encoders.o amdgpu_sa.o atombios_i2c.o \ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 7ce394921e6e0..b9ae7f8d50d5c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -4362,9 +4362,6 @@ int amdgpu_device_init(struct amdgpu_device *adev, /* Get a log2 for easy divisions. */ adev->mm_stats.log2_max_MBps = ilog2(max(1u, max_MBps)); -#ifndef AMDKCL_DRM_FBDEV_GENERIC - amdgpu_fbdev_init(adev); -#endif /* * Register gpu instance before amdgpu_device_enable_mgpu_fan_boost. * Otherwise the mgpu fan boost feature will be skipped due to the @@ -4553,9 +4550,6 @@ void amdgpu_device_fini_hw(struct amdgpu_device *adev) amdgpu_reg_state_sysfs_fini(adev); -#ifndef AMDKCL_DRM_FBDEV_GENERIC - amdgpu_fbdev_fini(adev); -#endif /* disable ras feature must before hw fini */ amdgpu_ras_pre_fini(adev); @@ -4738,11 +4732,7 @@ int amdgpu_device_suspend(struct drm_device *dev, bool fbcon) DRM_WARN("smart shift update failed\n"); if (fbcon) -#ifdef AMDKCL_DRM_FBDEV_GENERIC drm_fb_helper_set_suspend_unlocked(adev_to_drm(adev)->fb_helper, true); -#else - amdgpu_fbdev_set_suspend(adev, 1); -#endif cancel_delayed_work_sync(&adev->delayed_init_work); @@ -4840,11 +4830,7 @@ int amdgpu_device_resume(struct drm_device *dev, bool fbcon) flush_delayed_work(&adev->delayed_init_work); if (fbcon) -#ifdef AMDKCL_DRM_FBDEV_GENERIC drm_fb_helper_set_suspend_unlocked(adev_to_drm(adev)->fb_helper, false); -#else - amdgpu_fbdev_set_suspend(adev, 0); -#endif amdgpu_ras_resume(adev); @@ -5534,11 +5520,7 @@ int amdgpu_do_asic_reset(struct list_head *device_list_handle, if (r) goto out; -#ifdef AMDKCL_DRM_FBDEV_GENERIC drm_fb_helper_set_suspend_unlocked(adev_to_drm(tmp_adev)->fb_helper, false); -#else - amdgpu_fbdev_set_suspend(tmp_adev, 0); -#endif /* * The GPU enters bad state once faulty pages @@ -5826,11 +5808,7 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, */ amdgpu_unregister_gpu_instance(tmp_adev); -#ifdef AMDKCL_DRM_FBDEV_GENERIC drm_fb_helper_set_suspend_unlocked(adev_to_drm(tmp_adev)->fb_helper, true); -#else - amdgpu_fbdev_set_suspend(tmp_adev, 1); -#endif /* disable ras on ALL IPs */ if (!need_emergency_restart && diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index 30355ac19d4dd..c63056043b0db 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1739,7 +1739,6 @@ bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc, stime, etime, mode); } -#ifdef AMDKCL_DRM_FBDEV_GENERIC static bool amdgpu_display_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj) { @@ -1754,7 +1753,6 @@ amdgpu_display_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj) return true; } -#endif int amdgpu_display_suspend_helper(struct amdgpu_device *adev) { @@ -1796,16 +1794,7 @@ int amdgpu_display_suspend_helper(struct amdgpu_device *adev) continue; robj = gem_to_amdgpu_bo(drm_gem_fb_get_obj(fb, 0)); -#ifndef AMDKCL_DRM_FBDEV_GENERIC - /* don't unpin kernel fb objects */ - if (!amdgpu_fbdev_robj_is_fb(adev, robj)) { - r = amdgpu_bo_reserve(robj, true); - if (r == 0) { - amdgpu_bo_unpin(robj); - amdgpu_bo_unreserve(robj); - } - } -#else + if (!amdgpu_display_robj_is_fb(adev, robj)) { r = amdgpu_bo_reserve(robj, true); if (r == 0) { @@ -1813,7 +1802,6 @@ int amdgpu_display_suspend_helper(struct amdgpu_device *adev) amdgpu_bo_unreserve(robj); } } -#endif } return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index 9faf83dfa5ba5..96b3577c49356 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -1055,7 +1055,6 @@ int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data, return r; } -#ifdef AMDKCL_DRM_FBDEV_GENERIC static int amdgpu_gem_align_pitch(struct amdgpu_device *adev, int width, int cpp, @@ -1081,7 +1080,6 @@ static int amdgpu_gem_align_pitch(struct amdgpu_device *adev, aligned &= ~pitch_mask; return aligned * cpp; } -#endif int amdgpu_mode_dumb_create(struct drm_file *file_priv, struct drm_device *dev, @@ -1105,13 +1103,9 @@ int amdgpu_mode_dumb_create(struct drm_file *file_priv, if (adev->mman.buffer_funcs_enabled) flags |= AMDGPU_GEM_CREATE_VRAM_CLEARED; -#ifdef AMDKCL_DRM_FBDEV_GENERIC args->pitch = amdgpu_gem_align_pitch(adev, args->width, DIV_ROUND_UP(args->bpp, 8), 0); -#else - args->pitch = amdgpu_align_pitch(adev, args->width, - DIV_ROUND_UP(args->bpp, 8), 0); -#endif + args->size = (u64)args->pitch * args->height; args->size = ALIGN(args->size, PAGE_SIZE); domain = amdgpu_bo_get_preferred_domain(adev, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h index e75f17f79e0da..b913f3f7ed95c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h @@ -231,11 +231,6 @@ struct amdgpu_i2c_chan { struct mutex mutex; }; - -#ifndef AMDKCL_DRM_FBDEV_GENERIC -struct amdgpu_fbdev; -#endif - struct amdgpu_afmt { bool enabled; int offset; @@ -312,15 +307,6 @@ struct amdgpu_framebuffer { uint64_t address; }; -#ifndef AMDKCL_DRM_FBDEV_GENERIC -struct amdgpu_fbdev { - struct drm_fb_helper helper; - struct amdgpu_framebuffer rfb; - struct list_head fbdev_list; - struct amdgpu_device *adev; -}; -#endif - struct amdgpu_mode_info { struct atom_context *atom_context; struct card_info *atom_card_info; @@ -343,10 +329,6 @@ struct amdgpu_mode_info { /* hardcoded DFP edid from BIOS */ const struct drm_edid *bios_hardcoded_edid; -#ifndef AMDKCL_DRM_FBDEV_GENERIC - /* pointer to fbdev info structure */ - struct amdgpu_fbdev *rfbdev; -#endif /* firmware flags */ u32 firmware_flags; /* pointer to backlight encoder */ @@ -720,16 +702,6 @@ bool amdgpu_crtc_get_scanout_position(struct drm_crtc *crtc, int *hpos, ktime_t *stime, ktime_t *etime, const struct drm_display_mode *mode); -#ifndef AMDKCL_DRM_FBDEV_GENERIC -/* fbdev layer */ -int amdgpu_fbdev_init(struct amdgpu_device *adev); -void amdgpu_fbdev_fini(struct amdgpu_device *adev); -void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state); -int amdgpu_fbdev_total_size(struct amdgpu_device *adev); -bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj); - -int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int bpp, bool tiled); -#endif /* amdgpu_display.c */ void amdgpu_display_print_display_setup(struct drm_device *dev); diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 3f5868501c740..9959948abe497 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -544,9 +544,6 @@ /* drm_dsc_compute_rc_parameters() is available */ #define HAVE_DRM_DSC_COMPUTE_RC_PARAMETERS 1 -/* drm_fbdev_generic_setup() is available */ -/* #undef HAVE_DRM_FBDEV_GENERIC_SETUP */ - /* drm_fb_helper_single_add_all_connectors() && drm_fb_helper_remove_one_connector() are symbol */ /* #undef HAVE_DRM_FB_HELPER_ADD_REMOVE_CONNECTORS */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-fbdev-generic-setup.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-fbdev-generic-setup.m4 deleted file mode 100644 index cfd16b033ccbf..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/drm-fbdev-generic-setup.m4 +++ /dev/null @@ -1,16 +0,0 @@ -dnl # -dnl # commit v4.18-rc3-614-g9060d7f49376 -dnl # drm/fb-helper: Finish the generic fbdev emulation -dnl # -AC_DEFUN([AC_AMDGPU_DRM_FBDEV_GENERIC_SETUP], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include - ], [ - drm_fbdev_generic_setup(NULL, 0); - ], [drm_fbdev_generic_setup], [drivers/gpu/drm/drm_fb_helper.c],[ - AC_DEFINE(HAVE_DRM_FBDEV_GENERIC_SETUP, 1, - [drm_fbdev_generic_setup() is available]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index e6f277db256ca..0bdfff8475e34 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -142,7 +142,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DEVICE_PDEV AC_AMDGPU_DRM_CONNECTOR_SET_PANEL_ORIENTATION_WITH_QUIRK AC_AMDGPU_DRM_SIMPLE_ENCODER_INIT - AC_AMDGPU_DRM_FBDEV_GENERIC_SETUP AC_AMDGPU_DRM_DP_UPDATE_PAYLOAD_PART1_START_SLOT_ARG AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS AC_AMDGPU_DRM_DISPLAY_INFO_IS_HDMI diff --git a/include/kcl/backport/kcl_drm_fb.h b/include/kcl/backport/kcl_drm_fb.h index e14f228fc86fb..4b869a664735f 100644 --- a/include/kcl/backport/kcl_drm_fb.h +++ b/include/kcl/backport/kcl_drm_fb.h @@ -25,8 +25,4 @@ #include #include -#if defined(HAVE_DRM_FBDEV_GENERIC_SETUP) -#define AMDKCL_DRM_FBDEV_GENERIC -#endif - #endif From adbb9b339974ab6f71558740188629442c381bff Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 3 Apr 2023 15:01:11 +0800 Subject: [PATCH 0976/1868] drm/amdkcl: remove unexpected comma Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index ff21ca820d731..ab6ae33fa71b6 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -8,7 +8,7 @@ GCCSTR=$(shell printf "%d%02d%02d" $(GCCMAJ) $(GCCMIN) $(GCCPAT)) KERNEL_MAJ=$(VERSION) KERNEL_PATCHLEVEL=$(PATCHLEVEL) KERNEL_SUBLEVEL=$(SUBLEVEL) -KERNEL_VER=$(shell printf "%d%02d%02d" $(KERNEL_MAJ) $(KERNEL_PATCHLEVEL), $(KERNEL_SUBLEVEL)) +KERNEL_VER=$(shell printf "%d%02d%02d" $(KERNEL_MAJ) $(KERNEL_PATCHLEVEL) $(KERNEL_SUBLEVEL)) kernel-version = $(shell [ $(KERNEL_VER)0 $(1) $(2)000 ] && echo $(3) || echo $(4)) From 2a66c0447854b97f1f632c7e4b3cb2646aa8637e Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Mon, 3 Apr 2023 15:12:00 +0800 Subject: [PATCH 0977/1868] drm/amdkcl: use gcc-min-version macro to test gcc version This is caused by following commit: 88b61e3bff93 "Makefile.compiler: replace cc-ifversion with compiler-specific macros" Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/Makefile | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index ab6ae33fa71b6..a6b1568f0b0c8 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -12,13 +12,6 @@ KERNEL_VER=$(shell printf "%d%02d%02d" $(KERNEL_MAJ) $(KERNEL_PATCHLEVEL) $(KERN kernel-version = $(shell [ $(KERNEL_VER)0 $(1) $(2)000 ] && echo $(3) || echo $(4)) -# gcc 4.8.5 is too old for kernel >= 5.4, which will cause the compile failure. -ifeq ($(call cc-ifversion, -le, 0408, y), y) -ifeq ($(call kernel-version, -ge, 0504, y), y) -$(error "The GCC is too old for this kernel, please update the GCC to higher than 9.3") -endif -endif - ifdef CONFIG_CC_IS_GCC ifeq ($(shell [ $(CONFIG_GCC_VERSION) -ne $(GCCSTR) ] && echo y), y) $(warning "Local GCC version $(GCCSTR) does not match kernel compiler GCC version $(CONFIG_GCC_VERSION)") @@ -32,6 +25,17 @@ endif endif +ifndef gcc-min-version +export gcc-min-version=$(shell [ $(CONFIG_GCC_VERSION)0 -ge $(1)0 ] && echo y) +endif + +# gcc 4.8.5 is too old for kernel >= 5.4, which will cause the compile failure. +ifneq ($(call gcc-min-version, 40805), y) +ifeq ($(call kernel-version, -ge, 0504, y), y) +$(error "The GCC is too old for this kernel, please update the GCC to higher than 9.3") +endif +endif + ifndef CONFIG_DRM $(error CONFIG_DRM disabled, exit...) endif From 9414804d6941482a3131209ead4670486ceeef9b Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 4 Apr 2023 13:16:06 +0800 Subject: [PATCH 0978/1868] drm/amdkcl: Explicitly define gcc-min-version in separate file If we export gcc-min-version in dkms/Makefile, the function gcc-min-version cannot output correct value with gcc version 40805 in file display/dc/dml/Makefile for distro RHEL7.9. Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/display/dc/dml/Makefile | 2 ++ drivers/gpu/drm/amd/dkms/Makefile | 4 +--- drivers/gpu/drm/amd/dkms/Makefile.compiler | 3 +++ 3 files changed, 6 insertions(+), 3 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/Makefile.compiler diff --git a/drivers/gpu/drm/amd/display/dc/dml/Makefile b/drivers/gpu/drm/amd/display/dc/dml/Makefile index 46f9c05de16e8..9182c5f1fc98d 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dml/Makefile @@ -28,6 +28,8 @@ dml_ccflags := $(CC_FLAGS_FPU) dml_rcflags := $(CC_FLAGS_NO_FPU) +include $(src)/../dkms/Makefile.compiler + ifneq ($(CONFIG_FRAME_WARN),0) ifeq ($(filter y,$(CONFIG_KASAN)$(CONFIG_KCSAN)),y) frame_warn_flag := -Wframe-larger-than=3072 diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index a6b1568f0b0c8..0c7477083f0ec 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -25,9 +25,7 @@ endif endif -ifndef gcc-min-version -export gcc-min-version=$(shell [ $(CONFIG_GCC_VERSION)0 -ge $(1)0 ] && echo y) -endif +include $(src)/amd/dkms/Makefile.compiler # gcc 4.8.5 is too old for kernel >= 5.4, which will cause the compile failure. ifneq ($(call gcc-min-version, 40805), y) diff --git a/drivers/gpu/drm/amd/dkms/Makefile.compiler b/drivers/gpu/drm/amd/dkms/Makefile.compiler new file mode 100644 index 0000000000000..9c546ebcbee5a --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/Makefile.compiler @@ -0,0 +1,3 @@ +ifndef gcc-min-version +gcc-min-version = $(shell [ $(CONFIG_GCC_VERSION)0 -ge $(1)0 ] && echo y) +endif From b01498eddceb8cb2223e3570f7d54f8b7e202a3d Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 21 Apr 2023 14:12:37 +0800 Subject: [PATCH 0979/1868] drm/amdkcl: kcl-cleanup remove amdgpu/amdgpu_fb.c file Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c | 409 ------------------------- 1 file changed, 409 deletions(-) delete mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c deleted file mode 100644 index 09b60070309e1..0000000000000 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c +++ /dev/null @@ -1,409 +0,0 @@ -/* - * Copyright © 2007 David Airlie - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the next - * paragraph) shall be included in all copies or substantial portions of the - * Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - * - * Authors: - * David Airlie - */ - -#ifndef AMDKCL_DRM_FBDEV_GENERIC - -#include -#include -#include -#include - -#include -#include -#include -#include -#include - -#include "amdgpu.h" -#include "cikd.h" -#include "amdgpu_gem.h" - -#include "amdgpu_display.h" - -/* object hierarchy - - this contains a helper + a amdgpu fb - the helper contains a pointer to amdgpu framebuffer baseclass. -*/ - -static int -amdgpufb_open(struct fb_info *info, int user) -{ - struct drm_fb_helper *fb_helper = info->par; - int ret = pm_runtime_get_sync(fb_helper->dev->dev); - if (ret < 0 && ret != -EACCES) { - pm_runtime_mark_last_busy(fb_helper->dev->dev); - pm_runtime_put_autosuspend(fb_helper->dev->dev); - return ret; - } - return 0; -} - -static int -amdgpufb_release(struct fb_info *info, int user) -{ - struct drm_fb_helper *fb_helper = info->par; - - pm_runtime_mark_last_busy(fb_helper->dev->dev); - pm_runtime_put_autosuspend(fb_helper->dev->dev); - return 0; -} - -static const struct fb_ops amdgpufb_ops = { - .owner = THIS_MODULE, - DRM_FB_HELPER_DEFAULT_OPS, - .fb_open = amdgpufb_open, - .fb_release = amdgpufb_release, - .fb_fillrect = drm_fb_helper_cfb_fillrect, - .fb_copyarea = drm_fb_helper_cfb_copyarea, - .fb_imageblit = drm_fb_helper_cfb_imageblit, -}; - - -int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int cpp, bool tiled) -{ - int aligned = width; - int pitch_mask = 0; - - switch (cpp) { - case 1: - pitch_mask = 255; - break; - case 2: - pitch_mask = 127; - break; - case 3: - case 4: - pitch_mask = 63; - break; - } - - aligned += pitch_mask; - aligned &= ~pitch_mask; - return aligned * cpp; -} - -static void amdgpufb_destroy_pinned_object(struct drm_gem_object *gobj) -{ - struct amdgpu_bo *abo = gem_to_amdgpu_bo(gobj); - int ret; - - ret = amdgpu_bo_reserve(abo, true); - if (likely(ret == 0)) { - amdgpu_bo_kunmap(abo); - amdgpu_bo_unpin(abo); - amdgpu_bo_unreserve(abo); - } - drm_gem_object_put(gobj); -} - -static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev, - struct drm_mode_fb_cmd2 *mode_cmd, - struct drm_gem_object **gobj_p) -{ - const struct drm_format_info *info; - struct amdgpu_device *adev = rfbdev->adev; - struct drm_gem_object *gobj = NULL; - struct amdgpu_bo *abo = NULL; - bool fb_tiled = false; /* useful for testing */ - u32 tiling_flags = 0, domain; - int ret; - int aligned_size, size; - int height = mode_cmd->height; - u32 cpp; - u64 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | - AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | - AMDGPU_GEM_CREATE_VRAM_CLEARED; - - info = drm_get_format_info(adev_to_drm(adev), mode_cmd); - cpp = info->cpp[0]; - - /* need to align pitch with crtc limits */ - mode_cmd->pitches[0] = amdgpu_align_pitch(adev, mode_cmd->width, cpp, - fb_tiled); - domain = amdgpu_display_supported_domains(adev, flags); - height = ALIGN(mode_cmd->height, 8); - size = mode_cmd->pitches[0] * height; - aligned_size = ALIGN(size, PAGE_SIZE); - ret = amdgpu_gem_object_create(adev, aligned_size, 0, domain, flags, - ttm_bo_type_device, NULL, &gobj); - if (ret) { - pr_err("failed to allocate framebuffer (%d)\n", aligned_size); - return -ENOMEM; - } - abo = gem_to_amdgpu_bo(gobj); - - if (fb_tiled) - tiling_flags = AMDGPU_TILING_SET(ARRAY_MODE, GRPH_ARRAY_2D_TILED_THIN1); - - ret = amdgpu_bo_reserve(abo, false); - if (unlikely(ret != 0)) - goto out_unref; - - if (tiling_flags) { - ret = amdgpu_bo_set_tiling_flags(abo, - tiling_flags); - if (ret) - dev_err(adev->dev, "FB failed to set tiling flags\n"); - } - - ret = amdgpu_bo_pin(abo, domain); - if (ret) { - amdgpu_bo_unreserve(abo); - goto out_unref; - } - - ret = amdgpu_ttm_alloc_gart(&abo->tbo); - if (ret) { - amdgpu_bo_unreserve(abo); - dev_err(adev->dev, "%p bind failed\n", abo); - goto out_unref; - } - - ret = amdgpu_bo_kmap(abo, NULL); - amdgpu_bo_unreserve(abo); - if (ret) { - goto out_unref; - } - - *gobj_p = gobj; - return 0; -out_unref: - amdgpufb_destroy_pinned_object(gobj); - *gobj_p = NULL; - return ret; -} - -static int amdgpufb_create(struct drm_fb_helper *helper, - struct drm_fb_helper_surface_size *sizes) -{ - struct amdgpu_fbdev *rfbdev = (struct amdgpu_fbdev *)helper; - struct amdgpu_device *adev = rfbdev->adev; - struct fb_info *info; - struct drm_framebuffer *fb = NULL; - struct drm_mode_fb_cmd2 mode_cmd; - struct drm_gem_object *gobj = NULL; - struct amdgpu_bo *abo = NULL; - int ret; - - memset(&mode_cmd, 0, sizeof(mode_cmd)); - mode_cmd.width = sizes->surface_width; - mode_cmd.height = sizes->surface_height; - - if (sizes->surface_bpp == 24) - sizes->surface_bpp = 32; - - mode_cmd.pixel_format = drm_mode_legacy_fb_format(sizes->surface_bpp, - sizes->surface_depth); - - ret = amdgpufb_create_pinned_object(rfbdev, &mode_cmd, &gobj); - if (ret) { - DRM_ERROR("failed to create fbcon object %d\n", ret); - return ret; - } - - abo = gem_to_amdgpu_bo(gobj); - - /* okay we have an object now allocate the framebuffer */ - info = drm_fb_helper_alloc_fbi(helper); - if (IS_ERR(info)) { - ret = PTR_ERR(info); - goto out; - } - - ret = amdgpu_display_gem_fb_init(adev_to_drm(adev), &rfbdev->rfb, - &mode_cmd, gobj); - if (ret) { - DRM_ERROR("failed to initialize framebuffer %d\n", ret); - goto out; - } - - fb = &rfbdev->rfb.base; - - /* setup helper */ - rfbdev->helper.fb = fb; - - info->fbops = &amdgpufb_ops; - - info->fix.smem_start = amdgpu_gmc_vram_cpu_pa(adev, abo); - info->fix.smem_len = amdgpu_bo_size(abo); - info->screen_base = amdgpu_bo_kptr(abo); - info->screen_size = amdgpu_bo_size(abo); - - drm_fb_helper_fill_info(info, &rfbdev->helper, sizes); - - /* setup aperture base/size for vesafb takeover */ -#ifdef HAVE_DRM_MODE_CONFIG_FB_BASE - info->apertures->ranges[0].base = adev_to_drm(adev)->mode_config.fb_base; -#endif - info->apertures->ranges[0].size = adev->gmc.aper_size; - - /* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */ - - if (info->screen_base == NULL) { - ret = -ENOSPC; - goto out; - } - - DRM_INFO("fb mappable at 0x%lX\n", info->fix.smem_start); - DRM_INFO("vram apper at 0x%lX\n", (unsigned long)adev->gmc.aper_base); - DRM_INFO("size %lu\n", (unsigned long)amdgpu_bo_size(abo)); - DRM_INFO("fb depth is %d\n", fb->format->depth); - DRM_INFO("pitch is %d\n", fb->pitches[0]); - - vga_switcheroo_client_fb_set(adev->pdev, info); - return 0; - -out: - if (abo) { - - } - if (fb && ret) { - drm_gem_object_put(gobj); - drm_framebuffer_unregister_private(fb); - drm_framebuffer_cleanup(fb); - kfree(fb); - } - return ret; -} - -static int amdgpu_fbdev_destroy(struct drm_device *dev, struct amdgpu_fbdev *rfbdev) -{ - struct amdgpu_framebuffer *rfb = &rfbdev->rfb; - struct drm_gem_object *obj = NULL; - int i; - - drm_fb_helper_unregister_fbi(&rfbdev->helper); - obj = drm_gem_fb_get_obj(&rfb->base, 0); - - if (obj) { -#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED - for (i = 0; i < rfb->base.format->num_planes; i++) - drm_gem_object_put(obj); -#endif - amdgpufb_destroy_pinned_object(obj); - rfb->base.obj[0] = NULL; - drm_framebuffer_unregister_private(&rfb->base); - drm_framebuffer_cleanup(&rfb->base); - } - drm_fb_helper_fini(&rfbdev->helper); - - return 0; -} - -static const struct drm_fb_helper_funcs amdgpu_fb_helper_funcs = { - .fb_probe = amdgpufb_create, -}; - -int amdgpu_fbdev_init(struct amdgpu_device *adev) -{ - struct amdgpu_fbdev *rfbdev; - int bpp_sel = 32; - int ret; - - /* don't init fbdev on hw without DCE */ - if (!adev->mode_info.mode_config_initialized) - return 0; - - /* don't init fbdev if there are no connectors */ - if (list_empty(&adev_to_drm(adev)->mode_config.connector_list)) - return 0; - - /* select 8 bpp console on low vram cards */ - if (adev->gmc.real_vram_size <= (32*1024*1024)) - bpp_sel = 8; - - rfbdev = kzalloc(sizeof(struct amdgpu_fbdev), GFP_KERNEL); - if (!rfbdev) - return -ENOMEM; - - rfbdev->adev = adev; - adev->mode_info.rfbdev = rfbdev; - - drm_fb_helper_prepare(adev_to_drm(adev), &rfbdev->helper, - &amdgpu_fb_helper_funcs); - -#if defined(HAVE_DRM_FB_HELPER_INIT_2ARGS) - ret = drm_fb_helper_init(adev_to_drm(adev), &rfbdev->helper); -#elif defined(HAVE_DRM_FB_HELPER_INIT_3ARGS) - ret = drm_fb_helper_init(adev_to_drm(adev), &rfbdev->helper, - AMDGPUFB_CONN_LIMIT); -#else - ret = drm_fb_helper_init(adev_to_drm(adev), &rfbdev->helper, - adev->mode_info.num_crtc, AMDGPUFB_CONN_LIMIT); -#endif - - if (ret) { - kfree(rfbdev); - return ret; - } - - /* disable all the possible outputs/crtcs before entering KMS mode */ - if (!drm_drv_uses_atomic_modeset(adev_to_drm(adev))) - drm_helper_disable_unused_functions(adev_to_drm(adev)); - - drm_fb_helper_initial_config(&rfbdev->helper, bpp_sel); - return 0; -} - -void amdgpu_fbdev_fini(struct amdgpu_device *adev) -{ - if (!adev->mode_info.rfbdev) - return; - - amdgpu_fbdev_destroy(adev_to_drm(adev), adev->mode_info.rfbdev); - kfree(adev->mode_info.rfbdev); - adev->mode_info.rfbdev = NULL; -} - -void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state) -{ - if (adev->mode_info.rfbdev) - drm_fb_helper_set_suspend_unlocked(&adev->mode_info.rfbdev->helper, - state); -} - -int amdgpu_fbdev_total_size(struct amdgpu_device *adev) -{ - struct amdgpu_bo *robj; - int size = 0; - - if (!adev->mode_info.rfbdev) - return 0; - - robj = gem_to_amdgpu_bo(drm_gem_fb_get_obj(&adev->mode_info.rfbdev->rfb.base, 0)); - size += amdgpu_bo_size(robj); - return size; -} - -bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj) -{ - if (!adev->mode_info.rfbdev) - return false; - if (robj == gem_to_amdgpu_bo(drm_gem_fb_get_obj(&adev->mode_info.rfbdev->rfb.base, 0))) - return true; - return false; -} -#endif From 5a18d0f98ce20a2e7e9935672a47a307c13a58f9 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Fri, 7 Apr 2023 10:01:43 +0800 Subject: [PATCH 0980/1868] drm/amdkcl: Add missing macro definition in config.h Signed-off-by: Ma Jun Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/config/config.h | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 9959948abe497..158a4c3b26d45 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -520,11 +520,8 @@ /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_BUDDY_H 1 -/* Define to 1 if you have the header file. */ -#define HAVE_DRM_DRM_UTIL_H 1 - -/* Define to 1 if you have the header file. */ -#define HAVE_DRM_DRM_VBLANK_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_FBDEV_GENERIC_H 1 /* drm_driver_feature DRIVER_IRQ_SHARED is available */ /* #undef HAVE_DRM_DRV_DRIVER_IRQ_SHARED */ From edf220a34e7f3a9908a1c1016e8591522b7bfcb1 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Tue, 4 Apr 2023 10:04:12 +0800 Subject: [PATCH 0981/1868] drm/amdkcl: kcl-cleanup HAVE_DRM_DRM_BUDDY_H Signed-off-by: Leslie Shi Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/config/config.h | 3 --- drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 6 ------ 2 files changed, 9 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 158a4c3b26d45..9b472b08b3e0b 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -517,9 +517,6 @@ /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_PROBE_HELPER_H 1 -/* Define to 1 if you have the header file. */ -#define HAVE_DRM_DRM_BUDDY_H 1 - /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_FBDEV_GENERIC_H 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index 5004222733f88..a88e31ef833a7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -81,12 +81,6 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # AC_KERNEL_CHECK_HEADERS([linux/pgtable.h]) - dnl # - dnl # v5.19-rc1- c9cad937c0 - dnl # drm/amdgpu: add drm buddy support to amdgpu - dnl # - AC_KERNEL_CHECK_HEADERS([drm/drm_buddy.h]) - dnl # dnl # v6.1-rc2-542-g8ab59da26bc0 dnl # drm/fb-helper: Move generic fbdev emulation into separate source file From b8f40790cb59998941496afa2347f7cde9277b19 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 28 Jun 2023 11:01:55 +0800 Subject: [PATCH 0982/1868] drm/amdkcl: Update config.h Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/config/config.h | 90 ------------------------ 1 file changed, 90 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 9b472b08b3e0b..6fa3fc2a29017 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -177,51 +177,12 @@ drm_driver* */ #define HAVE_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ARG 1 -/* drm_atomic_get_old_crtc_state() and drm_atomic_get_new_crtc_state() are - available */ -#define HAVE_DRM_ATOMIC_GET_CRTC_STATE 1 - -/* drm_atomic_get_new_plane_state() is available */ -#define HAVE_DRM_ATOMIC_GET_NEW_PLANE_STATE 1 - /* drm_atomic_helper_calc_timestamping_constants() is available */ #define HAVE_DRM_ATOMIC_HELPER_CALC_TIMESTAMPING_CONSTANTS 1 -/* drm_atomic_helper_check_plane_state() is available */ -#define HAVE_DRM_ATOMIC_HELPER_CHECK_PLANE_STATE 1 - -/* drm_atomic_helper_shutdown() is available */ -#define HAVE_DRM_ATOMIC_HELPER_SHUTDOWN 1 - -/* drm_atomic_helper_wait_for_flip_done() is available */ -#define HAVE_DRM_ATOMIC_HELPER_WAIT_FOR_FLIP_DONE 1 - -/* {drm_atomic_helper_crtc_set_property, drm_atomic_helper_plane_set_property, - drm_atomic_helper_connector_set_property, drm_atomic_helper_connector_dpms} - is available */ -/* #undef HAVE_DRM_ATOMIC_HELPER_XXX_SET_PROPERTY */ - -/* drm_atomic_nonblocking_commit() is available */ -#define HAVE_DRM_ATOMIC_NONBLOCKING_COMMIT 1 - -/* drm_atomic_plane_disabling() wants drm_plane_state * arg */ -#define HAVE_DRM_ATOMIC_PLANE_DISABLING_DRM_PLANE_STATE 1 - -/* drm_atomic_private_obj_init() is available */ -#define HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT 1 - /* drm_atomic_private_obj_init() wants 4 args */ #define HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT_4ARGS 1 -/* whether struct drm_atomic_state have async_update */ -#define HAVE_DRM_ATOMIC_STATE_ASYNC_UPDATE 1 - -/* drm_atomic_state_put() is available */ -#define HAVE_DRM_ATOMIC_STATE_PUT 1 - -/* drm_color_lut_size() is available */ -#define HAVE_DRM_COLOR_LUT_SIZE 1 - /* drm_connector_atomic_hdr_metadata_equal() is available */ #define HAVE_DRM_CONNECTOR_ATOMIC_HDR_METADATA_EQUAL 1 @@ -289,9 +250,6 @@ drm_atomic_state arg */ #define HAVE_DRM_CRTC_HELPER_FUNCS_ATOMIC_ENABLE_ARG_DRM_ATOMIC_STATE 1 -/* drm_crtc_init_with_planes() wants name */ -#define HAVE_DRM_CRTC_INIT_WITH_PLANES_VALID_WITH_NAME 1 - /* drm_debug_enabled() is available */ #define HAVE_DRM_DEBUG_ENABLED 1 @@ -532,9 +490,6 @@ /* drm_gem_prime_export() with p,i arg is available */ #define HAVE_DRM_DRV_GEM_PRIME_EXPORT_PI 1 -/* drm_drv_uses_atomic_modeset() is available */ -#define HAVE_DRM_DRV_USES_ATOMIC_MODESET 1 - /* drm_dsc_compute_rc_parameters() is available */ #define HAVE_DRM_DSC_COMPUTE_RC_PARAMETERS 1 @@ -575,9 +530,6 @@ /* drm_gem_object_funcs.vmap hsa iosys_map arg */ #define HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_HAS_IOSYS_MAP_ARG 1 -/* drm_gem_object_lookup() wants 2 args */ -#define HAVE_DRM_GEM_OBJECT_LOOKUP_2ARGS 1 - /* drm_gem_object_put() is available */ #define HAVE_DRM_GEM_OBJECT_PUT 1 @@ -629,12 +581,6 @@ /* drm_need_swiotlb() is availablea */ #define HAVE_DRM_NEED_SWIOTLB 1 -/* drm atomic nonblocking commit support is available */ -#define HAVE_DRM_NONBLOCKING_COMMIT_SUPPORT 1 - -/* drm_plane_helper_check_state is available */ -/* #undef HAVE_DRM_PLANE_HELPER_CHECK_STATE */ - /* drm_plane_helper_destroy() is available */ /* #undef HAVE_DRM_PLANE_HELPER_DESTROY */ @@ -666,42 +612,12 @@ /* drm_simple_encoder is available */ #define HAVE_DRM_SIMPLE_ENCODER_INIT 1 -/* drm_syncobj_fence_get() is available */ -/* #undef HAVE_DRM_SYNCOBJ_FENCE_GET */ - -/* drm_syncobj_find_fence() is available */ -#define HAVE_DRM_SYNCOBJ_FIND_FENCE 1 - -/* whether drm_syncobj_find_fence() wants 3 args */ -/* #undef HAVE_DRM_SYNCOBJ_FIND_FENCE_3ARGS */ - -/* whether drm_syncobj_find_fence() wants 4 args */ -/* #undef HAVE_DRM_SYNCOBJ_FIND_FENCE_4ARGS */ - -/* whether drm_syncobj_find_fence() wants 5 args */ -#define HAVE_DRM_SYNCOBJ_FIND_FENCE_5ARGS 1 - /* Define to 1 if you have the header file. */ #define HAVE_DRM_TASK_BARRIER_H 1 -/* drm_universal_plane_init() wants 7 args */ -/* #undef HAVE_DRM_UNIVERSAL_PLANE_INIT_7ARGS */ - -/* drm_universal_plane_init() wants 8 args */ -/* #undef HAVE_DRM_UNIVERSAL_PLANE_INIT_8ARGS */ - -/* drm_universal_plane_init() wants 9 args */ -#define HAVE_DRM_UNIVERSAL_PLANE_INIT_9ARGS 1 - /* drm_vblank->time uses ktime_t type */ #define HAVE_DRM_VBLANK_USE_KTIME_T 1 -/* drm_vma_node_verify_access() 2nd argument is drm_file */ -#define HAVE_DRM_VMA_NODE_VERIFY_ACCESS_HAS_DRM_FILE 1 - -/* Variable refresh rate(vrr) is supported */ -#define HAVE_DRM_VRR_SUPPORTED 1 - /* fault_flag_allow_retry_first() is available */ #define HAVE_FAULT_FLAG_ALLOW_RETRY_FIRST 1 @@ -930,9 +846,6 @@ /* release_pages() wants 2 args */ #define HAVE_MM_RELEASE_PAGES_2ARGS 1 -/* num_u32_u32 is available */ -#define HAVE_MUL_U32_U32 1 - /* pcie_aspm_enabled() is available */ #define HAVE_PCIE_ASPM_ENABLED 1 @@ -1029,9 +942,6 @@ /* struct drm_connector_state->self_refresh_aware is available */ #define HAVE_STRUCT_DRM_CONNECTOR_STATE_SELF_REFRESH_AWARE 1 -/* drm_connector->ycbcr_420_allowed is available */ -#define HAVE_STRUCT_DRM_CONNECTOR_YCBCR_420_ALLOWED 1 - /* HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL is available */ #define HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL 1 From 7e61f9878d9c582472929c698f09f207c56b889f Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 11 Apr 2023 18:18:49 +0800 Subject: [PATCH 0983/1868] drm/amdkcl: fake drm_dp_atomic_release_time_slots() It's caused by df78f7f660cdd5974b68649a95dbb34da4d4dfa7 "drm/display/dp_mst: Call them time slots, not VCPI slots" Signed-off-by: Asher Song Reviewed-by: Perry Yuan Reviewed-by: Guchun Chen Reviewed-by: Leslie Shi Reviewed-by: bobzhou --- .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 4 -- drivers/gpu/drm/amd/dkms/config/config.h | 11 +-- .../drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 | 69 +++++++++++++------ .../backport/kcl_drm_dp_mst_helper_backport.h | 16 ++++- 4 files changed, 71 insertions(+), 29 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index ad522f0eb1ba0..4377b0efc0f9c 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -558,15 +558,11 @@ dm_dp_mst_detect(struct drm_connector *connector, static int dm_dp_mst_atomic_check(struct drm_connector *connector, struct drm_atomic_state *state) { -#ifdef HAVE_DRM_DP_ATOMIC_RELEASE_TIME_SLOTS struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); struct drm_dp_mst_topology_mgr *mst_mgr = &aconnector->mst_root->mst_mgr; struct drm_dp_mst_port *mst_port = aconnector->mst_output_port; return drm_dp_atomic_release_time_slots(state, mst_mgr, mst_port); -#else - return 0; -#endif } #endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 6fa3fc2a29017..68d55b0a646ad 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -316,6 +316,12 @@ /* drm_dp_atomic_find_time_slots() is available */ #define HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS 1 +/* drm_dp_atomic_find_vcpi_slots() wants 5args */ +/* #undef HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS_5ARGS */ + +/* drm_dp_atomic_release_vcpi_slots() with drm_dp_mst_port argument is available */ +/* #undef HAVE_DRM_DP_ATOMIC_RELEASE_VCPI_SLOTS_MST_PORT */ + /* drm_dp_mst_atomic_setup_commit() is available */ /* #undef HAVE_DRM_DP_ATOMIC_SETUP_COMMIT */ @@ -323,10 +329,7 @@ /* #undef HAVE_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES */ /* drm_dp_atomic_release_time_slots() is available */ -/* #undef HAVE_DRM_DP_ATOMIC_RELEASE_TIME_SLOTS */ - -/* drm_dp_atomic_find_vcpi_slots() wants 5args */ -#define HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS_5ARGS 1 +#define HAVE_DRM_DP_ATOMIC_RELEASE_TIME_SLOTS /* struct drm_dp_aux has member named 'drm_dev' */ #define HAVE_DRM_DP_AUX_DRM_DEV 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 index c89bcdbf10edd..d50c35a4fd1bc 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 @@ -22,8 +22,55 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS], [ ]) ]) + dnl # -dnl # commit v6.1-rc1~27-df78f7f660cd +dnl # commit v5.19-rc6-1758-gdf78f7f660cd +dnl # drm/display/dp_mst: Call them time slots, not VCPI slots +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_RELEASE_VCPI_SLOTS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) + #include + #else + #include + #endif + ],[ + int ret; + ret = drm_dp_atomic_release_time_slots(NULL, NULL, NULL); + ],[ + AC_DEFINE(HAVE_DRM_DP_ATOMIC_RELEASE_TIME_SLOTS, 1, + [drm_dp_atomic_release_time_slots() is available]) + ],[ + dnl # + dnl # commit v4.20-rc4-1031-geceae1472467 + dnl # drm/dp_mst: Start tracking per-port VCPI allocations + dnl # + AC_KERNEL_TRY_COMPILE([ + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) + #include + #else + #include + #endif + ],[ + int ret; + struct drm_dp_mst_port *port; + ret = drm_dp_atomic_release_vcpi_slots(NULL, NULL, port); + ],[ + AC_DEFINE(HAVE_DRM_DP_ATOMIC_RELEASE_VCPI_SLOTS_MST_PORT, 1, + [drm_dp_atomic_release_vcpi_slots() with drm_dp_mst_port argument is available]) + ]) + ]) + ]) +]) + + +dnl # +dnl # commit v5.19-rc6-1758-gdf78f7f660cd dnl # drm/display/dp_mst: Call them time slots, not VCPI slots dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FIND_TIME_SLOTS], [ @@ -102,29 +149,11 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_MST_ROOT_CONN_ATOMIC_CHECK], [ ]) ]) -dnl # -dnl # commit v6.1-rc1~27-df78f7f660cd -dnl # drm/display/dp_mst: Call them time slots, not VCPI slots -dnl # -AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_RELEASE_TIME_SLOTS], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE([ - #include - ],[ - int ret; - ret = drm_dp_atomic_release_time_slots(NULL, NULL, NULL); - ],[ - AC_DEFINE(HAVE_DRM_DP_ATOMIC_RELEASE_TIME_SLOTS, 1, - [drm_dp_atomic_release_time_slots() is available]) - ]) - ]) -]) - AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FUNCS], [ AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS + AC_AMDGPU_DRM_DP_ATOMIC_RELEASE_VCPI_SLOTS AC_AMDGPU_DRM_DP_ATOMIC_FIND_TIME_SLOTS AC_AMDGPU_DRM_DP_ATOMIC_SETUP_COMMIT AC_AMDGPU_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES AC_AMDGPU_DRM_DP_MST_ROOT_CONN_ATOMIC_CHECK - AC_AMDGPU_DRM_DP_ATOMIC_RELEASE_TIME_SLOTS ]) diff --git a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h index 97af03bd3e628..c6de78678e856 100644 --- a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h +++ b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h @@ -38,6 +38,8 @@ int _kcl_drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc) #define drm_dp_calc_pbn_mode _kcl_drm_dp_calc_pbn_mode #endif + +#if !defined(HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS) #if !defined(HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS_5ARGS) static inline int _kcl_drm_dp_atomic_find_vcpi_slots(struct drm_atomic_state *state, @@ -63,7 +65,6 @@ int _kcl_drm_dp_atomic_find_vcpi_slots(struct drm_atomic_state *state, #define drm_dp_atomic_find_vcpi_slots _kcl_drm_dp_atomic_find_vcpi_slots #endif /* HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS_5ARGS */ -#if !defined(HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS) static inline int _kcl_drm_dp_atomic_find_time_slots(struct drm_atomic_state *state, struct drm_dp_mst_topology_mgr *mgr, @@ -73,6 +74,19 @@ int _kcl_drm_dp_atomic_find_time_slots(struct drm_atomic_state *state, return drm_dp_atomic_find_vcpi_slots(state, mgr, port, pbn, pbn_div); } #define drm_dp_atomic_find_time_slots _kcl_drm_dp_atomic_find_time_slots +#endif /* HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS */ + +#if !defined(HAVE_DRM_DP_ATOMIC_RELEASE_TIME_SLOTS) +#ifdef HAVE_DRM_DP_ATOMIC_RELEASE_VCPI_SLOTS_MST_PORT +static inline +int _kcl_drm_dp_atomic_release_time_slots(struct drm_atomic_state *state, + struct drm_dp_mst_topology_mgr *mgr, + struct drm_dp_mst_port *port) +{ + return drm_dp_atomic_release_vcpi_slots(state, mgr, port); +} +#define drm_dp_atomic_release_time_slots _kcl_drm_dp_atomic_release_time_slots +#endif #endif #ifndef HAVE_DRM_DP_MST_TOPOLOGY_MGR_RESUME_2ARGS From ec5309c4f24790dcd31bf0b95c9382a0ced772a1 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 12 Apr 2023 14:29:08 +0800 Subject: [PATCH 0984/1868] drm/amdkcl: Bump amdgpu dkms package version to 6.1.0 Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/configure.ac | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/configure.ac b/drivers/gpu/drm/amd/dkms/configure.ac index 15e057582c3c1..219acb6ca1b39 100644 --- a/drivers/gpu/drm/amd/dkms/configure.ac +++ b/drivers/gpu/drm/amd/dkms/configure.ac @@ -1,4 +1,4 @@ -AC_INIT(amdgpu-dkms, 6.0.0) +AC_INIT(amdgpu-dkms, 6.1.0) AC_LANG(C) AC_CONFIG_AUX_DIR([config]) From 1e5d2d5f905682f36de98998936b69f75bafb505 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 6 Apr 2023 17:10:27 +0800 Subject: [PATCH 0985/1868] drm/amdkcl: update dkms/config/config.h Signed-off-by: Asher Song Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 189 +++++++++-------------- 1 file changed, 71 insertions(+), 118 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 68d55b0a646ad..51a2740c25a07 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -15,11 +15,10 @@ /* struct acpi_srat_generic_affinity is available */ #define HAVE_ACPI_SRAT_GENERIC_AFFINITY 1 - + /* acpi_video_backlight_use_native() is available */ #define HAVE_ACPI_VIDEO_BACKLIGHT_USE_NATIVE 1 - /* acpi_video_register_backlight() is available */ #define HAVE_ACPI_VIDEO_REGISTER_BACKLIGHT 1 @@ -47,6 +46,9 @@ /* amd_iommu_pc_supported() is available */ #define HAVE_AMD_IOMMU_PC_SUPPORTED 1 +/* apple_gmux_detect() is available */ +#define HAVE_APPLE_GMUX_DETECT 1 + /* arch_io_{reserve/free}_memtype_wc() are available */ #define HAVE_ARCH_IO_RESERVE_FREE_MEMTYPE_WC 1 @@ -59,7 +61,7 @@ /* backlight_device_set_brightness() is available */ #define HAVE_BACKLIGHT_DEVICE_SET_BRIGHTNESS 1 -/* bitmap_free() is available */ +/* bitmap_free(),bitmap_alloc(),bitmap_zalloc is available */ #define HAVE_BITMAP_FUNCS 1 /* bitmap_to_arr32() is available */ @@ -80,6 +82,9 @@ /* debugfs_create_file_size() is available */ #define HAVE_DEBUGFS_CREATE_FILE_SIZE 1 +/* kobj_type->default_groups is available */ +#define HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE 1 + /* devcgroup_check_permission() is available */ #define HAVE_DEVCGROUP_CHECK_PERMISSION 1 @@ -110,6 +115,9 @@ /* dma_fence_chain_alloc() is available */ #define HAVE_DMA_FENCE_CHAIN_ALLOC 1 +/* dma_fence_chain_contained() is available */ +#define HAVE_DMA_FENCE_CHAIN_CONTAINED 1 + /* dma_fence_describe() is available */ #define HAVE_DMA_FENCE_DESCRIBE 1 @@ -140,7 +148,7 @@ /* dma_resv->seq is seqcount_ww_mutex_t */ /* #undef HAVE_DMA_RESV_SEQCOUNT_WW_MUTEX_T */ -/* bug for missing dma_resv->seq */ +/* Reporting dma_resv->seq bug */ /* #undef HAVE_DMA_RESV_SEQ_BUG */ /* down_read_killable() is available */ @@ -149,30 +157,12 @@ /* down_write_killable() is available */ #define HAVE_DOWN_WRITE_KILLABLE 1 -/* fsleep() is available */ -#define HAVE_FSLEEP 1 - -/* drm_dp_mst_connector_early_unregister() is available */ -#define HAVE_DRM_DP_MST_CONNECTOR_EARLY_UNREGISTER 1 - -/* drm_dp_mst_connector_late_register() is available */ -#define HAVE_DRM_DP_MST_CONNECTOR_LATE_REGISTER 1 - -/* drm_accurate_vblank_count() is available */ -/* #undef HAVE_DRM_ACCURATE_VBLANK_COUNT */ - -/* DRM_AMDGPU_FENCE_TO_HANDLE is defined */ -#define HAVE_DRM_AMDGPU_FENCE_TO_HANDLE 1 - /* Define to 1 if you have the header file. */ /* #undef HAVE_DRM_AMDGPU_PCIID_H */ /* Define to 1 if you have the header file. */ #define HAVE_DRM_AMD_ASIC_TYPE_H 1 -/* drm_aperture_remove_* is availablea */ -#define HAVE_DRM_APERTURE 1 - /* drm_aperture_remove_conflicting_pci_framebuffers() second arg is drm_driver* */ #define HAVE_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ARG 1 @@ -274,7 +264,8 @@ /* Define to 1 if you have the header file. */ #define HAVE_DRM_DISPLAY_DRM_DP_HELPER_H 1 -/* Define to 1 if you have the header file. */ +/* Define to 1 if you have the header file. + */ #define HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H 1 /* Define to 1 if you have the header file. */ @@ -301,25 +292,26 @@ /* display_info->is_hdmi is available */ #define HAVE_DRM_DISPLAY_INFO_IS_HDMI 1 -/* display_info->max_tmds_clock is available */ -#define HAVE_DRM_DISPLAY_INFO_MAX_TMDS_CLOCK 1 - -/* struct drm_display_info has monitor_range member */ -#define HAVE_DRM_DISPLAY_INFO_MONITOR_RANGE 1 - /* display_info->luminance_range is available */ #define HAVE_DRM_DISPLAY_INFO_LUMINANCE_RANGE 1 /* display_info->max_dsc_bpp is available */ #define HAVE_DRM_DISPLAY_INFO_MAX_DSC_BPP 1 +/* struct drm_display_info has monitor_range member */ +#define HAVE_DRM_DISPLAY_INFO_MONITOR_RANGE 1 + /* drm_dp_atomic_find_time_slots() is available */ #define HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS 1 /* drm_dp_atomic_find_vcpi_slots() wants 5args */ /* #undef HAVE_DRM_DP_ATOMIC_FIND_VCPI_SLOTS_5ARGS */ -/* drm_dp_atomic_release_vcpi_slots() with drm_dp_mst_port argument is available */ +/* drm_dp_atomic_release_time_slots() is available */ +#define HAVE_DRM_DP_ATOMIC_RELEASE_TIME_SLOTS 1 + +/* drm_dp_atomic_release_vcpi_slots() with drm_dp_mst_port argument is + available */ /* #undef HAVE_DRM_DP_ATOMIC_RELEASE_VCPI_SLOTS_MST_PORT */ /* drm_dp_mst_atomic_setup_commit() is available */ @@ -328,15 +320,9 @@ /* drm_dp_mst_atomic_wait_for_dependencies() is available */ /* #undef HAVE_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES */ -/* drm_dp_atomic_release_time_slots() is available */ -#define HAVE_DRM_DP_ATOMIC_RELEASE_TIME_SLOTS - /* struct drm_dp_aux has member named 'drm_dev' */ #define HAVE_DRM_DP_AUX_DRM_DEV 1 -/* apple_gmux_detect() is available */ -#define HAVE_APPLE_GMUX_DETECT 1 - /* drm_dp_calc_pbn_mode() wants 3args */ #define HAVE_DRM_DP_CALC_PBN_MODE_3ARGS 1 @@ -367,6 +353,12 @@ /* drm_dp_mst_atomic_enable_dsc() wants 5args */ /* #undef HAVE_DRM_DP_MST_ATOMIC_ENABLE_DSC_WITH_5_ARGS */ +/* drm_dp_mst_connector_early_unregister() is available */ +#define HAVE_DRM_DP_MST_CONNECTOR_EARLY_UNREGISTER 1 + +/* drm_dp_mst_connector_late_register() is available */ +#define HAVE_DRM_DP_MST_CONNECTOR_LATE_REGISTER 1 + /* drm_dp_mst_detect_port() wants p,p,p,p args */ #define HAVE_DRM_DP_MST_DETECT_PORT_PPPP 1 @@ -376,15 +368,15 @@ /* drm_dp_mst_{get,put}_port_malloc() is available */ #define HAVE_DRM_DP_MST_GET_PUT_PORT_MALLOC 1 +/* drm_dp_mst_port struct has full_pbn member */ +#define HAVE_DRM_DP_MST_PORT_FULL_PBN 1 + /* struct drm_dp_mst_port has passthrough_aux member */ -/* #undef HAVE_DRM_DP_MST_PORT_PASSTHROUGH_AUX */ +#define HAVE_DRM_DP_MST_PORT_PASSTHROUGH_AUX 1 /* drm_dp_mst_root_conn_atomic_check() is available */ /* #undef HAVE_DRM_DP_MST_ROOT_CONN_ATOMIC_CHECK */ -/* drm_dp_mst_port struct has full_pbn member */ -#define HAVE_DRM_DP_MST_PORT_FULL_PBN 1 - /* struct drm_dp_mst_topology_cbs->destroy_connector is available */ /* #undef HAVE_DRM_DP_MST_TOPOLOGY_CBS_DESTROY_CONNECTOR */ @@ -422,14 +414,11 @@ #define HAVE_DRM_DP_START_CRC 1 /* drm_dp_update_payload_part1() function has start_slot argument */ -#define HAVE_DRM_DP_UPDATE_PAYLOAD_PART1_START_SLOT_ARG 1 +/* #undef HAVE_DRM_DP_UPDATE_PAYLOAD_PART1_START_SLOT_ARG */ -/* drm_driver->gem_prime_res_obj() is available */ +/* drm_driver->gem_prime_res_obj() is availab/le */ /* #undef HAVE_DRM_DRIVER_GEM_PRIME_RES_OBJ */ -/* drm_vblank struct use ktime_t for time field */ -#define HAVE_DRM_VBLANK_USE_KTIME_T 1 - /* Define to 1 if you have the header file. */ /* #undef HAVE_DRM_DRMP_H */ @@ -448,26 +437,8 @@ /* Define to 1 if you have the header file. */ /* #undef HAVE_DRM_DRM_BACKPORT_H */ -/* Define to 1 if you have the header file. */ -#define HAVE_DRM_DRM_CONNECTOR_H 1 - -/* Define to 1 if you have the header file. */ -#define HAVE_DRM_DRM_DEBUGFS_H 1 - -/* Define to 1 if you have the header file. */ -#define HAVE_DRM_DRM_DEVICE_H 1 - -/* Define to 1 if you have the header file. */ -#define HAVE_DRM_DRM_DRV_H 1 - -/* Define to 1 if you have the header file. */ -#define HAVE_DRM_DRM_HDCP_H 1 - -/* Define to 1 if you have the header file. */ -#define HAVE_DRM_DRM_IOCTL_H 1 - -/* Define to 1 if you have the header file. */ -/* #undef HAVE_DRM_DRM_IRQ_H */ +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_FBDEV_GENERIC_H 1 /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_MANAGED_H 1 @@ -478,9 +449,6 @@ /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_PROBE_HELPER_H 1 -/* Define to 1 if you have the header file. */ -#define HAVE_DRM_DRM_FBDEV_GENERIC_H 1 - /* drm_driver_feature DRIVER_IRQ_SHARED is available */ /* #undef HAVE_DRM_DRV_DRIVER_IRQ_SHARED */ @@ -496,6 +464,12 @@ /* drm_dsc_compute_rc_parameters() is available */ #define HAVE_DRM_DSC_COMPUTE_RC_PARAMETERS 1 +/* struct drm_dsc_config has member simple_422 */ +#define HAVE_DRM_DSC_CONFIG_SIMPLE_422 1 + +/* drm_dsc_pps_payload_pack() is available */ +#define HAVE_DRM_DSC_PPS_PAYLOAD_PACK 1 + /* drm_fb_helper_single_add_all_connectors() && drm_fb_helper_remove_one_connector() are symbol */ /* #undef HAVE_DRM_FB_HELPER_ADD_REMOVE_CONNECTORS */ @@ -524,9 +498,6 @@ /* drm_format_info.block_w and rm_format_info.block_h is available */ #define HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED 1 - /* drm_gem_plane_helper_prepare_fb() is available */ - #define HAVE_DRM_GEM_PLANE_HELPER_PREPARE_FB 1 - /* drm_gem_object_funcs->vmap() has 2 args */ #define HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_2ARGS 1 @@ -542,8 +513,8 @@ /* ttm_buffer_object->base is available */ #define HAVE_DRM_GEM_OBJECT_RESV 1 -/* drm_gen_fb_init_with_funcs() is available */ -#define HAVE_DRM_GEN_FB_INIT_WITH_FUNCS 1 +/* drm_gem_plane_helper_prepare_fb() is available */ +#define HAVE_DRM_GEM_PLANE_HELPER_PREPARE_FB 1 /* drm_hdcp_update_content_protection is available */ #define HAVE_DRM_HDCP_UPDATE_CONTENT_PROTECTION 1 @@ -566,6 +537,9 @@ /* drm_memcpy_from_wc() is availablea and has struct iosys_map* arg */ #define HAVE_DRM_MEMCPY_FROM_WC_IOSYS_MAP_ARG 1 +/* drm_modeset_backoff() has int return */ +#define HAVE_DRM_MODESET_BACKOFF_RETURN_INT 1 + /* drm_mode_config->dp_subconnector_property is available */ #define HAVE_DRM_MODE_CONFIG_DP_SUBCONNECTOR_PROPERTY 1 @@ -575,11 +549,8 @@ /* drm_mode_config->fb_modifiers_not_supported is available */ #define HAVE_DRM_MODE_CONFIG_FB_MODIFIERS_NOT_SUPPORTED 1 -/* drm_mode_config_funcs->atomic_state_alloc() is available */ -#define HAVE_DRM_MODE_CONFIG_FUNCS_ATOMIC_STATE_ALLOC 1 - /* drm_mode_init() is available */ -#define HAVE_DRM_MODE_INTT 1 +#define HAVE_DRM_MODE_INIT 1 /* drm_need_swiotlb() is availablea */ #define HAVE_DRM_NEED_SWIOTLB 1 @@ -621,11 +592,14 @@ /* drm_vblank->time uses ktime_t type */ #define HAVE_DRM_VBLANK_USE_KTIME_T 1 +/* struct drm_vma_offset_node has readonly field */ +/* #undef HAVE_DRM_VMA_OFFSET_NODE_READONLY_FIELD */ + /* fault_flag_allow_retry_first() is available */ #define HAVE_FAULT_FLAG_ALLOW_RETRY_FIRST 1 -/* drm_mode_object->free_cb is available */ -/* #undef HAVE_FREE_CB_IN_STRUCT_DRM_MODE_OBJECT */ +/* fsleep() is available */ +#define HAVE_FSLEEP 1 /* fs_reclaim_acquire() is available */ #define HAVE_FS_RECLAIM_ACQUIRE 1 @@ -663,6 +637,9 @@ /* hmm_range_fault() wants 1 arg */ #define HAVE_HMM_RANGE_FAULT_1ARG 1 +/* hypervisor_is_type() is available */ +#define HAVE_HYPERVISOR_IS_TYPE 1 + /* struct i2c_lock_operations is defined */ #define HAVE_I2C_LOCK_OPERATIONS_STRUCT 1 @@ -696,6 +673,9 @@ /* kallsyms_lookup_name is available */ /* #undef HAVE_KALLSYMS_LOOKUP_NAME */ +/* close_fd() is available */ +#define HAVE_KERNEL_CLOSE_FD 1 + /* kernel_write() take arg type of position as pointer */ #define HAVE_KERNEL_WRITE_PPOS 1 @@ -705,8 +685,8 @@ /* krealloc_array() is available */ #define HAVE_KREALLOC_ARRAY 1 -/* kref_read() function is available */ -#define HAVE_KREF_READ 1 +/* ksys_fd() is available */ +/* #undef HAVE_KSYS_CLOSE_FD */ /* ksys_sync_helper() is available */ #define HAVE_KSYS_SYNC_HELPER 1 @@ -810,9 +790,6 @@ /* list_rotate_to_front() is available */ #define HAVE_LIST_ROTATE_TO_FRONT 1 -/* strurct pci_dev->ltr_path is available */ -#define HAVE_PCI_DEV_LTR_PATH 1 - /* enum MCE_PRIO_UC is available */ #define HAVE_MCE_PRIO_UC 1 @@ -822,6 +799,9 @@ /* memalloc_noreclaim_save() is available */ #define HAVE_MEMALLOC_NORECLAIM_SAVE 1 +/* struct migrate_vma has fault_page */ +#define HAVE_MIGRATE_VMA_FAULT_PAGE 1 + /* migrate_vma->pgmap_owner is available */ #define HAVE_MIGRATE_VMA_PGMAP_OWNER 1 @@ -858,6 +838,9 @@ /* pci_dev_id() is available */ #define HAVE_PCI_DEV_ID 1 +/* strurct pci_dev->ltr_path is available */ +#define HAVE_PCI_DEV_LTR_PATH 1 + /* struct pci_driver has field dev_groups */ #define HAVE_PCI_DRIVER_DEV_GROUPS 1 @@ -879,8 +862,8 @@ /* vm_insert_mixed() wants pfn_t arg */ /* #undef HAVE_PFN_T_VM_INSERT_MIXED */ -/* pm_genpd_remove_device() wants 2 arguments */ -/* #undef HAVE_PM_GENPD_REMOVE_DEVICE_2ARGS */ +/* pm_suspend_target_state is available */ +#define HAVE_PM_SUSPEND_TARGET_STATE 1 /* pm_suspend_via_firmware() is available */ #define HAVE_PM_SUSPEND_VIA_FIRMWARE 1 @@ -921,9 +904,6 @@ /* is_smca_umc_v2() is available */ /* #undef HAVE_SMCA_UMC_V2 */ -/* struct dma_buf_ops->allow_peer2peer is available */ -#define HAVE_STRUCT_DMA_BUF_OPS_ALLOW_PEER2PEER 1 - /* struct dma_buf_attach_ops->allow_peer2peer is available */ #define HAVE_STRUCT_DMA_BUF_ATTACH_OPS_ALLOW_PEER2PEER 1 @@ -933,9 +913,6 @@ /* struct dma_fence_chain is available */ #define HAVE_STRUCT_DMA_FENCE_CHAIN 1 -/* dma_fence_chain_contained() is available */ -#define HAVE_DMA_FENCE_CHAIN_CONTAINED 1 - /* struct drm_connector_state->duplicated is available */ #define HAVE_STRUCT_DRM_ATOMIC_STATE_DUPLICATED 1 @@ -1048,8 +1025,8 @@ /* ww_mutex_trylock() has context arg */ #define HAVE_WW_MUTEX_TRYLOCK_CONTEXT_ARG 1 -/* is_device_page is available */ -/* #undef HAVE_ZONE_DEVICE_PUBLIC */ +/* enum x86_hypervisor_type is available */ +#define HAVE_X86_HYPERVISOR_TYPE 1 /* zone_managed_pages() is available */ #define HAVE_ZONE_MANAGED_PAGES 1 @@ -1060,36 +1037,12 @@ /* __dma_fence_is_later() is available and has ops arg */ #define HAVE__DMA_FENCE_IS_LATER_WITH_OPS_ARG 1 -/* struct drm_dsc_config has member simple_422 */ -#define HAVE_DRM_DSC_CONFIG_SIMPLE_422 1 - -/* drm_dsc_pps_payload_pack() is available */ -#define HAVE_DRM_DSC_PPS_PAYLOAD_PACK 1 - /* __drm_atomic_helper_crtc_reset() is available */ #define HAVE___DRM_ATOMIC_HELPER_CRTC_RESET 1 /* __kthread_should_park() is available */ #define HAVE___KTHREAD_SHOULD_PARK 1 -/* kobj_type->default_groups is available */ -#define HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE 1 - -/* close_fd() is available */ -#define HAVE_KERNEL_CLOSE_FD 1 - -/* ksys_close() is available */ -#define HAVE_KSYS_CLOSE_FD 1 - -/* pm_suspend_target_state is available */ -#define HAVE_PM_SUSPEND_TARGET_STATE 1 - -/* enum x86_hypervisor_type is available */ -#define HAVE_X86_HYPERVISOR_TYPE 1 - -/* hypervisor_is_type() is available */ -#define HAVE_HYPERVISOR_IS_TYPE 1 - /* Define to the address where bug reports for this package should be sent. */ #define PACKAGE_BUGREPORT "" From ad17e51113c45d79b36ff6e0829661f3254e1b68 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 3 Apr 2023 13:46:08 +0800 Subject: [PATCH 0986/1868] drm/amdkcl: fake kcl copy of zone_device_page_init Signed-off-by: Flora Cui Reviewed-by: Felix Kuehling Reviewed-by: Asher Song --- drivers/gpu/drm/amd/amdkcl/kcl_mm.c | 14 ++++++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../gpu/drm/amd/dkms/m4/zone_device_page_init.m4 | 12 ++++++++++++ include/kcl/kcl_mm.h | 4 ++++ 5 files changed, 34 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/zone_device_page_init.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_mm.c b/drivers/gpu/drm/amd/amdkcl/kcl_mm.c index 9d7534002b7e1..d151a6db046cc 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_mm.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_mm.c @@ -5,6 +5,7 @@ * Copyright (C) 1991, 1992 Linus Torvalds */ #include +#include #ifndef HAVE_MMPUT_ASYNC void (*_kcl_mmput_async)(struct mm_struct *mm); @@ -16,6 +17,19 @@ void __kcl_mmput_async(struct mm_struct *mm) } #endif +#ifndef HAVE_ZONE_DEVICE_PAGE_INIT +/* copied from v6.0-rc3-597-g0dc45ca1ce18 mm/memremap.c and modified for kcl usage */ +void zone_device_page_init(struct page *page) +{ +/* v5.17-rc4-75-g27674ef6c73f mm: remove the extra ZONE_DEVICE struct page refcount */ +#if IS_ENABLED(CONFIG_DEV_PAGEMAP_OPS) + get_page(page); +#endif + lock_page(page); +} +EXPORT_SYMBOL_GPL(zone_device_page_init); +#endif + void amdkcl_mm_init(void) { #ifndef HAVE_MMPUT_ASYNC diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 51a2740c25a07..e48dc12357e04 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1028,6 +1028,9 @@ /* enum x86_hypervisor_type is available */ #define HAVE_X86_HYPERVISOR_TYPE 1 +/* zone_device_page_init() is available */ +#define HAVE_ZONE_DEVICE_PAGE_INIT 1 + /* zone_managed_pages() is available */ #define HAVE_ZONE_MANAGED_PAGES 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 0bdfff8475e34..e9849ce7afbbb 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -192,6 +192,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_MIGRATE_VMA_FAULT_PAGE AC_AMDGPU_RB_ADD_CACHED AC_AMDGPU_APPLE_GMUX_DETECT + AC_AMDGPU_ZONE_DEVICE_PAGE_INIT AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/zone_device_page_init.m4 b/drivers/gpu/drm/amd/dkms/m4/zone_device_page_init.m4 new file mode 100644 index 0000000000000..d73aab950a652 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/zone_device_page_init.m4 @@ -0,0 +1,12 @@ +dnl # +dnl # v6.0-rc3-597-g0dc45ca1ce18 mm/memremap.c: take a pgmap reference on page allocation +dnl # v6.0-rc3-596-gef233450898f mm: free device private pages have zero refcount +dnl # v5.17-rc4-75-g27674ef6c73f mm: remove the extra ZONE_DEVICE struct page refcount +dnl # +AC_DEFUN([AC_AMDGPU_ZONE_DEVICE_PAGE_INIT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([zone_device_page_init], [mm/memremap.c], [ + AC_DEFINE(HAVE_ZONE_DEVICE_PAGE_INIT, 1, [zone_device_page_init() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_mm.h b/include/kcl/kcl_mm.h index 112aeb2591136..2379879ed9932 100644 --- a/include/kcl/kcl_mm.h +++ b/include/kcl/kcl_mm.h @@ -26,6 +26,10 @@ extern void (*_kcl_mmput_async)(struct mm_struct *mm); #endif +#ifndef HAVE_ZONE_DEVICE_PAGE_INIT +void zone_device_page_init(struct page *page); +#endif + #ifndef HAVE_FAULT_FLAG_ALLOW_RETRY_FIRST static inline bool fault_flag_allow_retry_first(unsigned int flags) { From e536c68b394ecac55d7606cfa27d76d783e37edf Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Wed, 29 Mar 2023 18:50:38 -0400 Subject: [PATCH 0987/1868] drm/amdkfd: Remove deprecated references to ZONE_DEVICE_PUBLIC This was replaced by ZONE_DEVICE_COHERENT in the final upstream version. Signed-off-by: Felix Kuehling Reviewed-by: Alex Sierra --- drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c index 5521b6b70290d..051c6fff10b7d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@ -221,13 +221,8 @@ svm_migrate_get_vram_page(struct svm_range *prange, unsigned long pfn) page = pfn_to_page(pfn); svm_range_bo_ref(prange->svm_bo); page->zone_device_data = prange->svm_bo; -#ifdef HAVE_ZONE_DEVICE_PUBLIC - VM_BUG_ON_PAGE(page_ref_count(page), page); - init_page_count(page); -#else #if IS_ENABLED(CONFIG_DEV_PAGEMAP_OPS) get_page(page); -#endif #endif lock_page(page); } From 8dc657740e747d5e43b9070919b42017c12e93b3 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Wed, 29 Mar 2023 19:19:38 -0400 Subject: [PATCH 0988/1868] drm/amdkfd: Fix HMM migrations on monolithic builds Use the new zone_device_page_init KCL helper, which encapsulates all the logic around locking and reference counting device pages. This makes the DKMS branch code in svm_migrate_get_vram_page look the same as upstream. Cc: Flora Cui Signed-off-by: Felix Kuehling Reviewed-and-tested-by: Guchun Chen --- drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c index 051c6fff10b7d..297d365b57bc7 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c @@ -221,10 +221,7 @@ svm_migrate_get_vram_page(struct svm_range *prange, unsigned long pfn) page = pfn_to_page(pfn); svm_range_bo_ref(prange->svm_bo); page->zone_device_data = prange->svm_bo; -#if IS_ENABLED(CONFIG_DEV_PAGEMAP_OPS) - get_page(page); -#endif - lock_page(page); + zone_device_page_init(page); } static void From fa5ff1ccd51cd5051b8931a1d2a4125a09a25650 Mon Sep 17 00:00:00 2001 From: bobzhou Date: Mon, 17 Apr 2023 16:30:57 +0800 Subject: [PATCH 0989/1868] drm/amdkcl: convert gfx.kiq to array type It's caused by 81a6a08325e46b446a249fca7f76b77937b3f77d "drm/amdgpu: convert gfx.kiq to array type (v3)" After modifying the struct amdgpu_gfx, some non-upstream code need to be updated. Signed-off-by: bobzhou Reviewed-by: Guchun Chen --- .../drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c | 24 +++++++++---------- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 8 +++---- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 8 +++---- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 8 +++---- 4 files changed, 24 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c index 1dd189536c764..f58291c1fd40b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c @@ -27,32 +27,32 @@ void amdgpu_amdkfd_rlc_spm_cntl(struct amdgpu_device *adev, bool cntl) { - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; - spin_lock(&adev->gfx.kiq.ring_lock); + spin_lock(&adev->gfx.kiq[0].ring_lock); amdgpu_ring_alloc(kiq_ring, adev->gfx.spmfuncs->set_spm_config_size); if (cntl) adev->gfx.spmfuncs->start(adev); else adev->gfx.spmfuncs->stop(adev); amdgpu_ring_commit(kiq_ring); - spin_unlock(&adev->gfx.kiq.ring_lock); + spin_unlock(&adev->gfx.kiq[0].ring_lock); } void amdgpu_amdkfd_rlc_spm_set_rdptr(struct amdgpu_device *adev, u32 rptr) { - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; - spin_lock(&adev->gfx.kiq.ring_lock); + spin_lock(&adev->gfx.kiq[0].ring_lock); amdgpu_ring_alloc(kiq_ring, adev->gfx.spmfuncs->set_spm_config_size); adev->gfx.spmfuncs->set_rdptr(adev, rptr); amdgpu_ring_commit(kiq_ring); - spin_unlock(&adev->gfx.kiq.ring_lock); + spin_unlock(&adev->gfx.kiq[0].ring_lock); } int amdgpu_amdkfd_rlc_spm_acquire(struct amdgpu_device *adev, struct amdgpu_vm *vm, u64 gpu_addr, u32 size) { - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; int r; if (!adev->gfx.rlc.funcs->update_spm_vmid) @@ -66,24 +66,24 @@ int amdgpu_amdkfd_rlc_spm_acquire(struct amdgpu_device *adev, struct amdgpu_vm * adev->gfx.rlc.funcs->update_spm_vmid(adev, 0); /* set spm ring registers */ - spin_lock(&adev->gfx.kiq.ring_lock); + spin_lock(&adev->gfx.kiq[0].ring_lock); amdgpu_ring_alloc(kiq_ring, adev->gfx.spmfuncs->set_spm_config_size); adev->gfx.spmfuncs->set_spm_perfmon_ring_buf(adev, gpu_addr, size); amdgpu_ring_commit(kiq_ring); - spin_unlock(&adev->gfx.kiq.ring_lock); + spin_unlock(&adev->gfx.kiq[0].ring_lock); return r; } void amdgpu_amdkfd_rlc_spm_release(struct amdgpu_device *adev, struct amdgpu_vm *vm) { - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; /* stop spm stream and interrupt */ - spin_lock(&adev->gfx.kiq.ring_lock); + spin_lock(&adev->gfx.kiq[0].ring_lock); amdgpu_ring_alloc(kiq_ring, adev->gfx.spmfuncs->set_spm_config_size); adev->gfx.spmfuncs->stop(adev); amdgpu_ring_commit(kiq_ring); - spin_unlock(&adev->gfx.kiq.ring_lock); + spin_unlock(&adev->gfx.kiq[0].ring_lock); amdgpu_vmid_free_reserved(adev, vm, AMDGPU_GFXHUB_0); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 73abab6b4dde5..f9f346c9d4bda 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -7687,7 +7687,7 @@ static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring, static void gfx_v10_0_spm_start(struct amdgpu_device *adev) { - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; uint32_t data = 0; data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, 0); @@ -7717,7 +7717,7 @@ static void gfx_v10_0_spm_start(struct amdgpu_device *adev) static void gfx_v10_0_spm_stop(struct amdgpu_device *adev) { - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; uint32_t data = 0; data = REG_SET_FIELD(0, CP_PERFMON_CNTL, PERFMON_STATE, @@ -7733,7 +7733,7 @@ static void gfx_v10_0_spm_stop(struct amdgpu_device *adev) static void gfx_v10_0_spm_set_rdptr(struct amdgpu_device *adev, u32 rptr) { - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; gfx_v10_0_write_data_to_reg(kiq_ring, 0, false, SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_RING_RDPTR), rptr); @@ -7742,7 +7742,7 @@ static void gfx_v10_0_spm_set_rdptr(struct amdgpu_device *adev, u32 rptr) static void gfx_v10_0_set_spm_perfmon_ring_buf(struct amdgpu_device *adev, u64 gpu_addr, u32 size) { - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; gfx_v10_0_write_data_to_reg(kiq_ring, 0, false, SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_PERFMON_RING_BASE_LO), lower_32_bits(gpu_addr)); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index e463628eddd87..4b3a022dec87c 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -5275,7 +5275,7 @@ static void gfx_v8_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel, static void gfx_v8_0_spm_start(struct amdgpu_device *adev) { - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; uint32_t data = 0; data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, 0); @@ -5300,7 +5300,7 @@ static void gfx_v8_0_spm_start(struct amdgpu_device *adev) static void gfx_v8_0_spm_stop(struct amdgpu_device *adev) { - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; uint32_t data = 0; data = REG_SET_FIELD(0, CP_PERFMON_CNTL, @@ -5314,7 +5314,7 @@ static void gfx_v8_0_spm_stop(struct amdgpu_device *adev) static void gfx_v8_0_spm_set_rdptr(struct amdgpu_device *adev, u32 rptr) { - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; gfx_v8_0_write_data_to_reg(kiq_ring, 0, false, mmRLC_SPM_RING_RDPTR, rptr); } @@ -5322,7 +5322,7 @@ static void gfx_v8_0_spm_set_rdptr(struct amdgpu_device *adev, u32 rptr) static void gfx_v8_0_set_spm_perfmon_ring_buf(struct amdgpu_device *adev, u64 gpu_addr, u32 size) { - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; gfx_v8_0_write_data_to_reg(kiq_ring, 0, false, mmRLC_SPM_PERFMON_RING_BASE_LO, lower_32_bits(gpu_addr)); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index e96beb4358783..792de29387508 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -4692,7 +4692,7 @@ static int gfx_v9_0_do_edc_gpr_workarounds(struct amdgpu_device *adev) static void gfx_v9_0_spm_start(struct amdgpu_device *adev) { - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; uint32_t data = 0; data = RREG32_SOC15(GC, 0, mmRLC_SPM_PERFMON_CNTL); @@ -4716,7 +4716,7 @@ static void gfx_v9_0_spm_start(struct amdgpu_device *adev) static void gfx_v9_0_spm_stop(struct amdgpu_device *adev) { - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; uint32_t data = 0; data = REG_SET_FIELD(0, CP_PERFMON_CNTL, SPM_PERFMON_STATE, @@ -4732,7 +4732,7 @@ static void gfx_v9_0_spm_stop(struct amdgpu_device *adev) static void gfx_v9_0_spm_set_rdptr(struct amdgpu_device *adev, u32 rptr) { - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_RING_RDPTR), rptr); @@ -4740,7 +4740,7 @@ static void gfx_v9_0_spm_set_rdptr(struct amdgpu_device *adev, u32 rptr) static void gfx_v9_0_set_spm_perfmon_ring_buf(struct amdgpu_device *adev, u64 gpu_addr, u32 size) { - struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring; + struct amdgpu_ring *kiq_ring = &adev->gfx.kiq[0].ring; gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_PERFMON_RING_BASE_LO), lower_32_bits(gpu_addr)); From 157035532afa0060ff98bb0346d55fc79cd72c81 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 17 Apr 2023 15:13:41 +0800 Subject: [PATCH 0990/1868] drm/amdkcl: drop obsolete file symbols not needed anymore Signed-off-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/symbols | 1 - drivers/gpu/drm/amd/dkms/pre-build.sh | 9 --------- 3 files changed, 1 insertion(+), 11 deletions(-) delete mode 100644 drivers/gpu/drm/amd/amdkcl/symbols diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 306044881cd3d..a444ae80f06af 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -1,5 +1,5 @@ # SPDX-License-Identifier: MIT -amdkcl-y += main.o symbols.o kcl_common.o +amdkcl-y += main.o kcl_common.o amdkcl-y += kcl_kernel_params.o amdkcl-y += dma-buf/dma-resv.o diff --git a/drivers/gpu/drm/amd/amdkcl/symbols b/drivers/gpu/drm/amd/amdkcl/symbols deleted file mode 100644 index fe167314985be..0000000000000 --- a/drivers/gpu/drm/amd/amdkcl/symbols +++ /dev/null @@ -1 +0,0 @@ -SYMS="" diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index 07df3f07ea532..3d7f2084cae3e 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -27,17 +27,8 @@ version_le () { [ "$KERNELVER_BASE" = "$oldest" ] } -source $KCL/symbols source $KCL/files -# lookup symbol address. obsolete. -echo '// auto generated by DKMS pre-build.sh' > $KCL/symbols.c -for sym in $SYMS; do - awk -v sym=$sym '$3 == sym { - print "void *_kcl_" $3 " = (void *)0x" $1 ";" - }' /boot/System.map-$KERNELVER >>$KCL/symbols.c -done - sed -i -e '/DEFINE_WD_CLASS(reservation_ww_class)/,/EXPORT_SYMBOL(reservation_ww_class)/d' \ -e '/dma_resv_lockdep/,/subsys_initcall/d' $KCL/dma-buf/dma-resv.c sed -i -e '/extern struct ww_class reservation_ww_class/i #include ' \ From 88c8b40f93c9f67dd364908ddd459601731e4a01 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 19 Apr 2023 10:27:09 +0800 Subject: [PATCH 0991/1868] drm/amdkcl: fix warning for kcl_apple-gmux.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit add linux/pnp.h for build warning include/kcl/kcl_apple-gmux.h:8:45: warning: ‘struct pnp_dev’ declared inside parameter list will not be visible outside of this definition or declaration static inline bool apple_gmux_detect(struct pnp_dev *pnp_dev, bool *indexed_ret) ^~~~~~~ Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- include/kcl/kcl_apple-gmux.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/kcl/kcl_apple-gmux.h b/include/kcl/kcl_apple-gmux.h index 27d96810046e7..4e478cb3a1e87 100644 --- a/include/kcl/kcl_apple-gmux.h +++ b/include/kcl/kcl_apple-gmux.h @@ -2,6 +2,7 @@ #define AMDKCL_APPLE_GMUX_H #include +#include #ifndef HAVE_APPLE_GMUX_DETECT #if IS_ENABLED(CONFIG_APPLE_GMUX) From 18e014ac34bae838c3ec34dd722f23c21ca3dec1 Mon Sep 17 00:00:00 2001 From: bobzhou Date: Tue, 18 Apr 2023 15:06:01 +0800 Subject: [PATCH 0992/1868] drm/amdkcl: add fake macros for link_edp_panel_control.c It's caused by 200199ae9a64ad94e42ea995f9a9d4d362b3ff99 "drm/amd/display: Adding support for VESA SCR" Signed-off-by: bobzhou Reviewed-by: Leslie Shi --- include/kcl/kcl_drm_dp_helper.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/include/kcl/kcl_drm_dp_helper.h b/include/kcl/kcl_drm_dp_helper.h index 9f921c3d9db24..532d8160eba9d 100644 --- a/include/kcl/kcl_drm_dp_helper.h +++ b/include/kcl/kcl_drm_dp_helper.h @@ -350,4 +350,18 @@ enum drm_dp_phy { #define DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1 0x2214 /* 2.0 E11 */ #endif +/* + * v6.1-4885-g200199ae9a64 + * drm/amd/display: Adding support for VESA SCR + */ +#ifndef DP_EDP_PANEL_LUMINANCE_CONTROL_CAPABLE +#define DP_EDP_PANEL_LUMINANCE_CONTROL_CAPABLE (1 << 4) +#endif +#ifndef DP_EDP_PANEL_LUMINANCE_CONTROL_ENABLE +#define DP_EDP_PANEL_LUMINANCE_CONTROL_ENABLE (1 << 7) +#endif +#ifndef DP_EDP_PANEL_TARGET_LUMINANCE_VALUE +#define DP_EDP_PANEL_TARGET_LUMINANCE_VALUE 0x734 +#endif + #endif /* _KCL_DRM_DP_HELPER_H_ */ From 395e743df703607fbd3970c7b4a570937a7370a0 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 19 Apr 2023 10:47:22 +0800 Subject: [PATCH 0993/1868] drm/amdkcl: include string_helpers.h for str_yes_no() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit dkms build on some distro system reports amd/amdgpu/../display/dc/link/protocols/link_dp_capability.c:1708:47: error: implicit declaration of function ‘str_yes_no’; did you mean ‘strcspn’? [-Werror=implicit-function-declaration] these distro systems need linux/string_helpers.h, so include it. Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- include/kcl/kcl_string_helpers.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/kcl/kcl_string_helpers.h b/include/kcl/kcl_string_helpers.h index ceac153f44bfd..e02c0059b3ade 100644 --- a/include/kcl/kcl_string_helpers.h +++ b/include/kcl/kcl_string_helpers.h @@ -2,7 +2,7 @@ #ifndef AMDKCL_STRING_HELPERS_H #define AMDKCL_STRING_HELPERS_H - +#include /* Copied from v5.17-rc2-224-gea4692c75e1c linux/string_helpers.h */ #ifndef HAVE_STR_YES_NO From ff2bbde231d89fd976039703fe4348a5dd4d3b38 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Thu, 2 Mar 2023 17:11:25 +0530 Subject: [PATCH 0994/1868] drm/amdgpu: Use correct mask for legacy pci check For legacy PCI compatibility check, use the mask which was set during gmc init rather than hardcoding to 44 bits width. Signed-off-by: Lijo Lazar Reviewed-by: Harish Kasiviswanathan --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index dd8e680d9b896..fe997c0768f78 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -2244,7 +2244,7 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) * IGP - can handle 44-bits * PCI - dma32 for legacy pci gart */ - need_dma32 = !!pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(44)); + need_dma32 = !!pci_set_dma_mask(adev->pdev, dma_get_mask(adev->dev)); #else need_dma32 = dma_addressing_limited(adev->dev); #endif From 7c137dc781001c7f93196ec1fe9eb77ac7e8d837 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 21 Apr 2023 15:37:15 +0800 Subject: [PATCH 0995/1868] drm/amdkcl: fake migrate_enable/disable() It's caused by 71c32def3700558ae3ecbb0e8aaea2378651b59c "drm/amd/display: Disable migration to ensure consistency of per-CPU variable" Signed-off-by: Bob Zhou Reviewed-by: Guchun Chen Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/migrate_disable.m4 | 16 ++++++++++++++++ include/kcl/kcl_preempt.h | 11 +++++++++++ 4 files changed, 31 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/migrate_disable.m4 diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index e48dc12357e04..097ad9a6c831e 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -477,6 +477,9 @@ /* drm_fb_helper_alloc_info() is available */ #define HAVE_DRM_FB_HELPER_ALLOC_INFO 1 +/* migrate_disable() is available */ +#define HAVE_MIGRATE_DISABLE 1 + /* drm_fb_helper_fill_info() is available */ #define HAVE_DRM_FB_HELPER_FILL_INFO 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index e9849ce7afbbb..f309b5e42c1ae 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -147,6 +147,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DISPLAY_INFO_IS_HDMI AC_AMDGPU_DRM_BITMAP_FUNCS AC_AMDGPU_STRUCT_KOBJ_TYPE + AC_AMDGPU_MIGRATE_DISABLE AC_AMDGPU_CLOSE_FD AC_AMDGPU_DRM_VMA_OFFSET_NODE_READONLY_FIELD AC_AMDGPU_WW_MUTEX_TRYLOCK_CONTEXT_ARG diff --git a/drivers/gpu/drm/amd/dkms/m4/migrate_disable.m4 b/drivers/gpu/drm/amd/dkms/m4/migrate_disable.m4 new file mode 100644 index 0000000000000..5ffb95e258143 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/migrate_disable.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v5.6-rc2-1-g66630058e56b +dnl # sched/rt: Provide migrate_disable/enable() inlines +dnl # +AC_DEFUN([AC_AMDGPU_MIGRATE_DISABLE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + migrate_disable(); + ],[ + AC_DEFINE(HAVE_MIGRATE_DISABLE, 1, + [migrate_disable() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_preempt.h b/include/kcl/kcl_preempt.h index 1e59cbca1bf73..cc861beb098ae 100644 --- a/include/kcl/kcl_preempt.h +++ b/include/kcl/kcl_preempt.h @@ -53,4 +53,15 @@ (NMI_MASK | HARDIRQ_MASK | SOFTIRQ_OFFSET))) #endif +#ifndef HAVE_MIGRATE_DISABLE +static __always_inline void migrate_disable(void) +{ + preempt_disable(); +} +static __always_inline void migrate_enable(void) +{ + preempt_enable(); +} +#endif /* HAVE_MIGRATE_DISABLE */ + #endif /* AMDKCL_PREEMPT_H */ From 93d71d1a0159edd1cda669c074ec2990caf5bcba Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 9 Jul 2024 16:25:06 +0800 Subject: [PATCH 0996/1868] drm/amdkcl: test whether drm_edid_override_connector_update() is available It's caused by 068553e14f869664ca66e63e5200b69db8ae8990 "drm/amd/display: assign edid_blob_ptr with edid from debugfs" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 6 +++++ drivers/gpu/drm/amd/dkms/m4/drm-edid.m4 | 32 ++++++++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/backport/kcl_drm_edid.h | 20 +++++++++++++++ 5 files changed, 60 insertions(+) create mode 100644 include/kcl/backport/kcl_drm_edid.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 98902bf9e06b1..97a361d50c76d 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -105,4 +105,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 097ad9a6c831e..c109b41e2303d 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -522,6 +522,12 @@ /* drm_hdcp_update_content_protection is available */ #define HAVE_DRM_HDCP_UPDATE_CONTENT_PROTECTION 1 +/* drm_edid_override_connector_update() is available */ +#define HAVE_DRM_EDID_OVERRIDE_CONNECTOR_UPDATE 1 + +/* drm_add_override_edid_modes() is available */ +/* #undef HAVE_DRM_ADD_OVERRIDE_EDID_MODES */ + /* drm_hdmi_avi_infoframe_from_display_mode() has p,p,b interface */ /* #undef HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_B */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-edid.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-edid.m4 index 02a5a8a2b5875..e2a939c448834 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-edid.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-edid.m4 @@ -33,3 +33,35 @@ AC_DEFUN([AC_AMDGPU_DRM_EDID], [ ]) ]) ]) + +dnl # +dnl # v6.1-rc1-143-g019b93874834 +dnl # drm/edid: rename drm_add_override_edid_modes() to drm_edid_override_connector_update() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_EDID_OVERRIDE_CONNECTOR_UPDATE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + int ret; + ret = drm_edid_override_connector_update(NULL); + ],[ + AC_DEFINE(HAVE_DRM_EDID_OVERRIDE_CONNECTOR_UPDATE, 1, + [drm_edid_override_connector_update() is available]) + ],[ + dnl # + dnl # v5.2-rc2-25-g48eaeb7664c7 + dnl # drm: add fallback override/firmware EDID modes workaround + dnl # + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + int ret; + ret = drm_add_override_edid_modes(NULL); + ],[ + AC_DEFINE(HAVE_DRM_ADD_OVERRIDE_EDID_MODES, 1, + [drm_add_override_edid_modes() is available]) + ]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index f309b5e42c1ae..0bea321f57e40 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -85,6 +85,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS AC_AMDGPU_DRM_EDID AC_AMDGPU_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER + AC_AMDGPU_DRM_EDID_OVERRIDE_CONNECTOR_UPDATE AC_AMDGPU_DRM_MODE_INIT AC_AMDGPU_DRM_DP_MST_TOPOLOGY AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS diff --git a/include/kcl/backport/kcl_drm_edid.h b/include/kcl/backport/kcl_drm_edid.h new file mode 100644 index 0000000000000..2076f6fe8b2b2 --- /dev/null +++ b/include/kcl/backport/kcl_drm_edid.h @@ -0,0 +1,20 @@ +#ifndef AMDKCL_BACKPORT_DRM_EDID_H +#define AMDKCL_BACKPORT_DRM_EDID_H + +#include + +#if !defined(HAVE_DRM_EDID_OVERRIDE_CONNECTOR_UPDATE) +#ifdef HAVE_DRM_ADD_OVERRIDE_EDID_MODES +static inline int _kcl_drm_edid_override_connector_update(struct drm_connector *connector) +{ + int ret; + + ret = drm_add_override_edid_modes(connector); + return ret; +} + +#define drm_edid_override_connector_update _kcl_drm_edid_override_connector_update +#endif +#endif + +#endif From 3f8201d0c38066eabe36319885699d74afd4123d Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Sun, 23 Apr 2023 10:56:25 +0800 Subject: [PATCH 0997/1868] drm/amdkcl: wrap code under macro HAVE_AMDKCL_HMM_MIRROR_ENABLED It's caused by 529960ba2a622107c0115345f648de441048e244 "drm/amdkfd: Fix an issue at userptr buffer validation process." Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 3cb85b5c6c599..1695c73f49f15 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -3013,7 +3013,9 @@ static int update_invalid_user_pages(struct amdkfd_process_info *process_info, goto unlock_out; } /* set mem valid if mem has hmm range associated */ +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED if (mem->range) +#endif mem->invalid = 0; } From 8b67d86e51e9d2ce5094f185a66423c24f4d4dab Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Sun, 23 Apr 2023 11:29:55 +0800 Subject: [PATCH 0998/1868] drm/amdkcl: test whether drm_connector->edid_override is available It's caused by 4596e8af5f3d520dcd2edf009aa785ad4cdc50e8 "drm/amd/display: implement force function in amdgpu_dm_connector_funcs" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/drm-connector.m4 | 20 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 28 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-connector.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 39f901c88e98a..b0dc359c7539b 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -7133,6 +7133,7 @@ amdgpu_dm_connector_late_register(struct drm_connector *connector) return 0; } +#ifdef HAVE_DRM_CONNECTOR_EDID_OVERRIDE static void amdgpu_dm_connector_funcs_force(struct drm_connector *connector) { struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); @@ -7170,6 +7171,7 @@ static void amdgpu_dm_connector_funcs_force(struct drm_connector *connector) &dc_em_sink->edid_caps); } } +#endif static const struct drm_connector_funcs amdgpu_dm_connector_funcs = { .reset = amdgpu_dm_connector_funcs_reset, @@ -7182,7 +7184,9 @@ static const struct drm_connector_funcs amdgpu_dm_connector_funcs = { .atomic_get_property = amdgpu_dm_connector_atomic_get_property, .late_register = amdgpu_dm_connector_late_register, .early_unregister = amdgpu_dm_connector_unregister, +#ifdef HAVE_DRM_CONNECTOR_EDID_OVERRIDE .force = amdgpu_dm_connector_funcs_force +#endif }; static int get_modes(struct drm_connector *connector) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index c109b41e2303d..795ceaf0b887b 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -808,6 +808,9 @@ /* memalloc_noreclaim_save() is available */ #define HAVE_MEMALLOC_NORECLAIM_SAVE 1 +/* drm_connector->edid_override is available */ +#define HAVE_DRM_CONNECTOR_EDID_OVERRIDE 1 + /* struct migrate_vma has fault_page */ #define HAVE_MIGRATE_VMA_FAULT_PAGE 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector.m4 new file mode 100644 index 0000000000000..43fb1565aabc0 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector.m4 @@ -0,0 +1,20 @@ +dnl # +dnl # v6.1-rc1-146-g90b575f52c6a +dnl # drm/edid: detach debugfs EDID override from EDID property update +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_EDID_OVERRIDE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_connector *connector = NULL; + connector->edid_override = NULL; + ],[ + AC_DEFINE(HAVE_DRM_CONNECTOR_EDID_OVERRIDE, 1, + [drm_connector->edid_override is available]) + ]) + ]) +]) + + + diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 0bea321f57e40..bc3b56f261023 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -94,6 +94,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_ATOMIC_CHECK AC_AMDGPU_DRM_DP_MST_ATOMIC_ENABLE_DSC AC_AMDGPU_DRM_CONNECTOR_HELPER_FUNCS + AC_AMDGPU_DRM_CONNECTOR_EDID_OVERRIDE AC_AMDGPU_DRM_DP_MST_DETECT_PORT AC_AMDGPU_STRUCT_DRM_CRTC_STATE AC_AMDGPU_DRM_DP_MST_DSC_AUX_FOR_PORT From 0f300184349b4ba027c845d1e4abf996d9e2c095 Mon Sep 17 00:00:00 2001 From: tiancyin Date: Wed, 26 Apr 2023 11:45:08 +0800 Subject: [PATCH 0999/1868] drm/amdkcl: fix display dp mst malfunction It's caused by ffac9721939dca3f0ac7bfa90f3dc484b19c2706 "drm/display/dp_mst: Don't open code modeset checks for releasing time slots" Reviewed-by: Flora Cui Signed-off-by: tiancyin --- .../amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 4377b0efc0f9c..87b6b60d9d111 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -561,7 +561,24 @@ static int dm_dp_mst_atomic_check(struct drm_connector *connector, struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector); struct drm_dp_mst_topology_mgr *mst_mgr = &aconnector->mst_root->mst_mgr; struct drm_dp_mst_port *mst_port = aconnector->mst_output_port; +#ifndef HAVE_DRM_DP_ATOMIC_RELEASE_TIME_SLOTS + struct drm_connector_state *new_conn_state = + drm_atomic_get_new_connector_state(state, connector); + struct drm_connector_state *old_conn_state = + drm_atomic_get_old_connector_state(state, connector); + struct drm_crtc_state *new_crtc_state; + + if (!old_conn_state->crtc) + return 0; + if (new_conn_state->crtc) { + new_crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc); + if (!new_crtc_state || + !drm_atomic_crtc_needs_modeset(new_crtc_state) || + new_crtc_state->enable) + return 0; + } +#endif return drm_dp_atomic_release_time_slots(state, mst_mgr, mst_port); } #endif From 2efec77848530501959b31e0782619e5a6d46480 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 27 Apr 2023 17:30:43 +0800 Subject: [PATCH 1000/1868] drm/amdkcl: fake macro DEFINE_DEBUGFS_ATTRIBUTE_SIGNED It's caused by 891d215cff04e230777a4b2b8611df31e7b822d2 "drm/amdgpu: add amdgpu_error_* debugfs file" Signed-off-by: Flora Cui Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c | 6 +- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_debugfs_file.c | 97 +++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_debugfs.h | 56 +++++++++++ 5 files changed, 159 insertions(+), 3 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_debugfs_file.c create mode 100644 include/kcl/kcl_debugfs.h diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c index 690976665cf69..5b83c87389072 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c @@ -589,6 +589,7 @@ static const struct file_operations amdgpu_debugfs_mqd_fops = { .llseek = default_llseek }; +#ifdef DEFINE_DEBUGFS_ATTRIBUTE static int amdgpu_debugfs_ring_error(void *data, u64 val) { struct amdgpu_ring *ring = data; @@ -599,7 +600,7 @@ static int amdgpu_debugfs_ring_error(void *data, u64 val) DEFINE_DEBUGFS_ATTRIBUTE_SIGNED(amdgpu_debugfs_error_fops, NULL, amdgpu_debugfs_ring_error, "%lld\n"); - +#endif #endif void amdgpu_debugfs_ring_init(struct amdgpu_device *adev, @@ -622,10 +623,11 @@ void amdgpu_debugfs_ring_init(struct amdgpu_device *adev, ring->mqd_size); } +#ifdef DEFINE_DEBUGFS_ATTRIBUTE sprintf(name, "amdgpu_error_%s", ring->name); debugfs_create_file(name, 0200, root, ring, &amdgpu_debugfs_error_fops); - +#endif #endif } diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index a444ae80f06af..5c0d3f39cf2f1 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -17,7 +17,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o -amdkcl-$(CONFIG_DEBUG_FS) += kcl_debugfs_inode.o +amdkcl-$(CONFIG_DEBUG_FS) += kcl_debugfs_inode.o kcl_debugfs_file.o amdkcl-$(CONFIG_SYSFS) += kcl_sysfs_emit.o CFLAGS_kcl_fence.o := -I$(src) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_debugfs_file.c b/drivers/gpu/drm/amd/amdkcl/kcl_debugfs_file.c new file mode 100644 index 0000000000000..def9db4463a22 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_debugfs_file.c @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * inode.c - part of debugfs, a tiny little debug file system + * + * Copyright (C) 2004,2019 Greg Kroah-Hartman + * Copyright (C) 2004 IBM Inc. + * Copyright (C) 2019 Linux Foundation + * + * debugfs is for people to use instead of /proc or /sys. + * See ./Documentation/core-api/kernel-api.rst for more details. + */ + +#include +#include +#include + +#ifdef KCL_FAKE_DEBUGFS_ATTRIBUTE_SIGNED +/* Copied from fs/libfs.c */ +struct simple_attr { + int (*get)(void *, u64 *); + int (*set)(void *, u64); + char get_buf[24]; /* enough to store a u64 and "\n\0" */ + char set_buf[24]; + void *data; + const char *fmt; /* format for read operation */ + struct mutex mutex; /* protects access to these buffers */ +}; + +static ssize_t simple_attr_write_xsigned(struct file *file, const char __user *buf, + size_t len, loff_t *ppos, bool is_signed) +{ + struct simple_attr *attr; + unsigned long long val; + size_t size; + ssize_t ret; + + attr = file->private_data; + if (!attr->set) + return -EACCES; + + ret = mutex_lock_interruptible(&attr->mutex); + if (ret) + return ret; + + ret = -EFAULT; + size = min(sizeof(attr->set_buf) - 1, len); + if (copy_from_user(attr->set_buf, buf, size)) + goto out; + + attr->set_buf[size] = '\0'; + if (is_signed) + ret = kstrtoll(attr->set_buf, 0, &val); + else + ret = kstrtoull(attr->set_buf, 0, &val); + if (ret) + goto out; + ret = attr->set(attr->data, val); + if (ret == 0) + ret = len; /* on success, claim we got the whole input */ +out: + mutex_unlock(&attr->mutex); + return ret; +} + +ssize_t simple_attr_write_signed(struct file *file, const char __user *buf, + size_t len, loff_t *ppos) +{ + return simple_attr_write_xsigned(file, buf, len, ppos, true); +} +EXPORT_SYMBOL_GPL(simple_attr_write_signed); + +/* Copied from fs/debugfs/file.c */ +#define F_DENTRY(filp) ((filp)->f_path.dentry) +static ssize_t debugfs_attr_write_xsigned(struct file *file, const char __user *buf, + size_t len, loff_t *ppos, bool is_signed) +{ + struct dentry *dentry = F_DENTRY(file); + ssize_t ret; + + ret = debugfs_file_get(dentry); + if (unlikely(ret)) + return ret; + if (is_signed) + ret = simple_attr_write_signed(file, buf, len, ppos); + else + ret = simple_attr_write(file, buf, len, ppos); + debugfs_file_put(dentry); + return ret; +} + +ssize_t debugfs_attr_write_signed(struct file *file, const char __user *buf, + size_t len, loff_t *ppos) +{ + return debugfs_attr_write_xsigned(file, buf, len, ppos, true); +} +EXPORT_SYMBOL_GPL(debugfs_attr_write_signed); +#endif diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 97a361d50c76d..40a3fb993aa29 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -106,4 +106,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_debugfs.h b/include/kcl/kcl_debugfs.h new file mode 100644 index 0000000000000..ca6a8d391da78 --- /dev/null +++ b/include/kcl/kcl_debugfs.h @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * debugfs.h - a tiny little debug file system + * + * Copyright (C) 2004 Greg Kroah-Hartman + * Copyright (C) 2004 IBM Inc. + * + * debugfs is for people to use instead of /proc or /sys. + * See Documentation/filesystems/ for more details. + */ + +#ifndef KCL_DEBUGFS_H_ +#define KCL_DEBUGFS_H_ + +#include +#include +#include + +#include +#include + +#if defined(DEFINE_DEBUGFS_ATTRIBUTE) && !defined(DEFINE_DEBUGFS_ATTRIBUTE_SIGNED) +#define KCL_FAKE_DEBUGFS_ATTRIBUTE_SIGNED +#define DEFINE_DEBUGFS_ATTRIBUTE_XSIGNED(__fops, __get, __set, __fmt, __is_signed) \ +static int __fops ## _open(struct inode *inode, struct file *file) \ +{ \ + __simple_attr_check_format(__fmt, 0ull); \ + return simple_attr_open(inode, file, __get, __set, __fmt); \ +} \ +static const struct file_operations __fops = { \ + .owner = THIS_MODULE, \ + .open = __fops ## _open, \ + .release = simple_attr_release, \ + .read = debugfs_attr_read, \ + .write = (__is_signed) ? debugfs_attr_write_signed : debugfs_attr_write, \ + .llseek = no_llseek, \ +} + +#define DEFINE_DEBUGFS_ATTRIBUTE_SIGNED(__fops, __get, __set, __fmt) \ + DEFINE_DEBUGFS_ATTRIBUTE_XSIGNED(__fops, __get, __set, __fmt, true) + +#if defined(CONFIG_DEBUG_FS) +ssize_t debugfs_attr_write_signed(struct file *file, const char __user *buf, + size_t len, loff_t *ppos); +#else +static inline ssize_t debugfs_attr_write_signed(struct file *file, + const char __user *buf, + size_t len, loff_t *ppos) +{ + return -ENODEV; +} +#endif /* CONFIG_DEBUG_FS */ + +#endif /* DEFINE_DEBUGFS_ATTRIBUTE_SIGNED */ + +#endif From eb64147aea528fa8adb78541f07bf4cedb97bd1e Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 10 May 2023 17:39:34 +0800 Subject: [PATCH 1001/1868] Revert "drm/amdgpu: mark force completed fences with -ECANCELED" This reverts commit 44c41d7de74acbfec110ea28e400e051c1333f0d. This reverted patch causes a modprobe issue. (SWDEV-398339) Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c index b64821da99e84..d4f3fb3519c81 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c @@ -759,7 +759,6 @@ void amdgpu_fence_driver_set_error(struct amdgpu_ring *ring, int error) */ void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring) { - amdgpu_fence_driver_set_error(ring, -ECANCELED); amdgpu_fence_write(ring, ring->fence_drv.sync_seq); amdgpu_fence_process(ring); } From 84e123e868647d73cac3e9f2381b1e08b3df5464 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 12 May 2023 12:13:14 +0800 Subject: [PATCH 1002/1868] Bump AMDGPU version to 6.2.0 Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/configure.ac | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/configure.ac b/drivers/gpu/drm/amd/dkms/configure.ac index 219acb6ca1b39..77f27bca72e24 100644 --- a/drivers/gpu/drm/amd/dkms/configure.ac +++ b/drivers/gpu/drm/amd/dkms/configure.ac @@ -1,4 +1,4 @@ -AC_INIT(amdgpu-dkms, 6.1.0) +AC_INIT(amdgpu-dkms, 6.2.0) AC_LANG(C) AC_CONFIG_AUX_DIR([config]) From a83663d4a17f2d1f62400f71a627b49006fe776e Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 20 Apr 2023 15:07:57 +0800 Subject: [PATCH 1003/1868] drm/amdkcl: fake kmalloc_size_roundup Signed-off-by: Flora Cui Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_mm.c | 12 +++++ drivers/gpu/drm/amd/amdkcl/kcl_mm_slab.c | 44 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../amd/dkms/m4/mm-kmalloc_size_roundup.m4 | 17 +++++++ include/kcl/kcl_slab.h | 4 ++ 7 files changed, 82 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_mm_slab.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/mm-kmalloc_size_roundup.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 5c0d3f39cf2f1..ac231fe69b8ac 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -13,7 +13,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_fs_read_write.o kcl_drm_aperture.o \ kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o \ - kcl_mce_amd.o kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o + kcl_mce_amd.o kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o kcl_mm_slab.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_mm.c b/drivers/gpu/drm/amd/amdkcl/kcl_mm.c index d151a6db046cc..637ecefbb9773 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_mm.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_mm.c @@ -30,9 +30,21 @@ void zone_device_page_init(struct page *page) EXPORT_SYMBOL_GPL(zone_device_page_init); #endif +#ifndef HAVE_KMALLOC_SIZE_ROUNDUP +#ifndef CONFIG_SLOB +extern struct kmem_cache *(*_kcl_kmalloc_slab)(size_t size, gfp_t flags); +#endif +#endif /* HAVE_KMALLOC_SIZE_ROUNDUP */ + void amdkcl_mm_init(void) { #ifndef HAVE_MMPUT_ASYNC _kcl_mmput_async = amdkcl_fp_setup("mmput_async", __kcl_mmput_async); #endif + +#ifndef HAVE_KMALLOC_SIZE_ROUNDUP +#ifndef CONFIG_SLOB + _kcl_kmalloc_slab = amdkcl_fp_setup("kmalloc_slab", NULL); +#endif +#endif } diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_mm_slab.c b/drivers/gpu/drm/amd/amdkcl/kcl_mm_slab.c new file mode 100644 index 0000000000000..3de9dfff5d0df --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_mm_slab.c @@ -0,0 +1,44 @@ +#include +#include +#include + +#if !defined(HAVE_KMALLOC_SIZE_ROUNDUP) +#ifdef CONFIG_SLOB +/* copy from mm/slob.c */ +size_t kmalloc_size_roundup(size_t size) +{ + /* Short-circuit the 0 size case. */ + if (unlikely(size == 0)) + return 0; + /* Short-circuit saturated "too-large" case. */ + if (unlikely(size == SIZE_MAX)) + return SIZE_MAX; + + return ALIGN(size, ARCH_KMALLOC_MINALIGN); +} + +EXPORT_SYMBOL(kmalloc_size_roundup); +#else +/* copy from mm/slab_common.c and modified for KCL usage. */ +struct kmem_cache *(*_kcl_kmalloc_slab)(size_t size, gfp_t flags); +size_t kmalloc_size_roundup(size_t size) +{ + struct kmem_cache *c; + + /* Short-circuit the 0 size case. */ + if (unlikely(size == 0)) + return 0; + /* Short-circuit saturated "too-large" case. */ + if (unlikely(size == SIZE_MAX)) + return SIZE_MAX; + /* Above the smaller buckets, size is a multiple of page size. */ + if (size > KMALLOC_MAX_CACHE_SIZE) + return PAGE_SIZE << get_order(size); + + /* The flags don't matter since size_index is common to all. */ + c = _kcl_kmalloc_slab(size, GFP_KERNEL); + return c ? kmem_cache_size(c) : 0; +} +EXPORT_SYMBOL(kmalloc_size_roundup); +#endif +#endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 795ceaf0b887b..3628b5e7ecc6c 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -688,6 +688,9 @@ /* kernel_write() take arg type of position as pointer */ #define HAVE_KERNEL_WRITE_PPOS 1 +/* kmalloc_size_roundup is available */ +#define HAVE_KMALLOC_SIZE_ROUNDUP 1 + /* kmap_local_* is available */ #define HAVE_KMAP_LOCAL 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index bc3b56f261023..9d61eb812f767 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -195,6 +195,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_MIGRATE_VMA_FAULT_PAGE AC_AMDGPU_RB_ADD_CACHED AC_AMDGPU_APPLE_GMUX_DETECT + AC_AMDGPU_MM_KMALLOC_SIZE_ROUNDUP AC_AMDGPU_ZONE_DEVICE_PAGE_INIT AC_KERNEL_WAIT diff --git a/drivers/gpu/drm/amd/dkms/m4/mm-kmalloc_size_roundup.m4 b/drivers/gpu/drm/amd/dkms/m4/mm-kmalloc_size_roundup.m4 new file mode 100644 index 0000000000000..ab6586797229a --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/mm-kmalloc_size_roundup.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v6.0-rc2-7-g05a940656e1e +dnl # slab: Introduce kmalloc_size_roundup() +dnl # +AC_DEFUN([AC_AMDGPU_MM_KMALLOC_SIZE_ROUNDUP], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + size_t a, b; + a = kmalloc_size_roundup(b); + ], [ + AC_DEFINE(HAVE_KMALLOC_SIZE_ROUNDUP, 1, + [kmalloc_size_roundup is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_slab.h b/include/kcl/kcl_slab.h index e095f8a46088e..a23a565eab992 100644 --- a/include/kcl/kcl_slab.h +++ b/include/kcl/kcl_slab.h @@ -34,4 +34,8 @@ krealloc_array(void *p, size_t new_n, size_t new_size, gfp_t flags) } #endif +#ifndef HAVE_KMALLOC_SIZE_ROUNDUP +size_t kmalloc_size_roundup(size_t size); +#endif + #endif From 8d8ff8adccccfaa60c3b20cdd139c9076c271d54 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Tue, 9 May 2023 17:16:23 -0400 Subject: [PATCH 1004/1868] Fix unsteady amdgpu dkms build against 5.x kernels Make rules robust against "Argument list too long" error. SWDEV-397841 Change-Id: Ib7e26359097e275801658c1a865831060b11bc51 Signed-off-by: Slava Grigorev Reviewed-by: Jeremy Newton Reviewed-by: Slava Abramov --- drivers/gpu/drm/amd/dkms/dkms.conf | 2 ++ drivers/gpu/drm/amd/dkms/post-build.sh | 23 +++++++++++++++++ drivers/gpu/drm/amd/dkms/pre-build.sh | 34 ++++++++++++++++++++++++++ 3 files changed, 59 insertions(+) create mode 100755 drivers/gpu/drm/amd/dkms/post-build.sh diff --git a/drivers/gpu/drm/amd/dkms/dkms.conf b/drivers/gpu/drm/amd/dkms/dkms.conf index bf06588ea6b9c..ec2c979254b55 100644 --- a/drivers/gpu/drm/amd/dkms/dkms.conf +++ b/drivers/gpu/drm/amd/dkms/dkms.conf @@ -2,6 +2,8 @@ PACKAGE_NAME="amdgpu" PACKAGE_VERSION="1.0" AUTOINSTALL="yes" PRE_BUILD="amd/dkms/pre-build.sh $kernelver" +POST_BUILD="amd/dkms/post-build.sh $kernelver" +POST_REMOVE="amd/dkms/post-build.sh $kernelver" # not all OS supports weak module updates NO_WEAK_MODULES="yes" diff --git a/drivers/gpu/drm/amd/dkms/post-build.sh b/drivers/gpu/drm/amd/dkms/post-build.sh new file mode 100755 index 0000000000000..962903db89aca --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/post-build.sh @@ -0,0 +1,23 @@ +#!/bin/bash + +KERNELVER=$1 + +# +# Restore original kernel 5.x scripts/Makefile.build modified by post-add.sh +# +if [[ ${KERNELVER%%.*} -eq 5 ]]; then + moddir="/lib/modules/$KERNELVER" + mkfile="scripts/Makefile.build" + + if [[ -d "$moddir/source" ]]; then + mkfile="$moddir/source/$mkfile" + else + mkfile="$moddir/build/$mkfile" + fi + + mkfile=$(readlink -f $mkfile) + + if [[ -f "$mkfile~" ]]; then + mv -f $mkfile{~,} + fi +fi diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index 3d7f2084cae3e..cdbac6500036c 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -55,6 +55,40 @@ for config in $AMDGPU_CONFIG $TTM_CONFIG $SCHED_CONFIG; do sed -i "/${config}$/s/$/_AMDKCL/" amd/dkms/Makefile done +#!/bin/bash + +KERNELVER=$1 + +# +# Kernel 5.x scripts/Makefile.build patch +# The patch makes rules robust against "Argument list too long" error +# +if [[ ${KERNELVER%%.*} -eq 5 ]]; then + moddir="/lib/modules/$KERNELVER" + mkfile="scripts/Makefile.build" + + if [[ -d "$moddir/source" ]]; then + mkfile="$moddir/source/$mkfile" + else + mkfile="$moddir/build/$mkfile" + fi + + mkfile=$(readlink -e $mkfile) + + if [[ "$?" -eq 0 ]] && [[ ! -f "$mkfile~" ]]; then + cp -a ${mkfile}{,~} + sed -i -e "/^cmd_mod = {/,/} > \$@$/c"` + `"cmd_mod = printf '%s\x5Cn' \$(call real-search, \$*.o, .o, -objs -y -m) | \\\\\n"` + `"\t\$(AWK) '!x[\$\$0]++ { print(\"\$(obj)\/\"\$\$0) }' > \$@" \ + -e "s/^[[:space:]]\+cmd_link_multi-m =.*$/"` + `"cmd_link_multi-m = \\\\\n"` + `"\t\$(file >\$@.in,\$(filter %.o,$^)) \\\\\n"` + `"\t\$(LD) \$(ld_flags) -r -o \$@ @\$@.in; \\\\\n"` + `"\trm -f \$@.in/" \ + $mkfile + fi +fi + export KERNELVER (cd $SRC && ./configure) From fdd60b6e0f08f82143936250ce50bcff85059d2a Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 17 May 2023 15:07:40 +0800 Subject: [PATCH 1005/1868] drm/amdkcl: modify AMDGPU_GFXHUB_0 to AMDGPU_GFXHUB(0) It's caused by 43ca920837c4ec57875b51272fe66421a4d24666 "drm/amdgpu: introduce vmhub definition for multi-partition cases (v3)" Signed-off-by: Bob Zhou Reviewed-by: majun --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c index f58291c1fd40b..82c270b3a6946 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c @@ -58,7 +58,7 @@ int amdgpu_amdkfd_rlc_spm_acquire(struct amdgpu_device *adev, struct amdgpu_vm * if (!adev->gfx.rlc.funcs->update_spm_vmid) return -EINVAL; - r = amdgpu_vmid_alloc_reserved(adev, vm, AMDGPU_GFXHUB_0); + r = amdgpu_vmid_alloc_reserved(adev, vm, AMDGPU_GFXHUB(0)); if (r) return r; @@ -85,7 +85,7 @@ void amdgpu_amdkfd_rlc_spm_release(struct amdgpu_device *adev, struct amdgpu_vm amdgpu_ring_commit(kiq_ring); spin_unlock(&adev->gfx.kiq[0].ring_lock); - amdgpu_vmid_free_reserved(adev, vm, AMDGPU_GFXHUB_0); + amdgpu_vmid_free_reserved(adev, vm, AMDGPU_GFXHUB(0)); /* revert spm vmid with 0xf */ if (adev->gfx.rlc.funcs->update_spm_vmid) From 4e774ff6bdc110e8bc571a39765fa4e58afea6f6 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 25 May 2023 16:26:31 +0800 Subject: [PATCH 1006/1868] drm/amdkcl: add mem_id_plus1 argument when invoke amdgpu_gem_object_create It's caused by 4a31ec3828d09618e496bbf16c15e05a2eeaf1ed drm/amdgpu: Add memory partition mem_id to amdgpu_bo Due to mem_id_plus1 is added as a parameter, modify the argument when invoke amdgpu_gem_object_create. Signed-off-by: Asher Song Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index 96b3577c49356..63bbe580e1f52 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -583,6 +583,7 @@ int amdgpu_gem_dgma_ioctl(struct drm_device *dev, void *data, { struct amdgpu_device *adev = drm_to_adev(dev); struct drm_amdgpu_gem_dgma *args = data; + struct amdgpu_fpriv *fpriv = filp->driver_priv; struct drm_gem_object *gobj; struct amdgpu_bo *abo; dma_addr_t *dma_addr; @@ -594,7 +595,7 @@ int amdgpu_gem_dgma_ioctl(struct drm_device *dev, void *data, /* create a gem object to contain this object in */ r = amdgpu_gem_object_create(adev, args->size, 0, AMDGPU_GEM_DOMAIN_DGMA_IMPORT, 0, - 0, NULL, &gobj); + 0, NULL, &gobj, fpriv->xcp_id + 1); if (r) return r; From 926b1902f0377572f7533906cdeed3f21c8b9793 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 18 May 2023 13:38:44 +0800 Subject: [PATCH 1007/1868] drm/amdkcl: wrap code under macro HAVE_DRM_DRV_DRIVER_SYNCOBJ_TIMELINE It's caused by 8764cee060df560171cf9ac266fa93366200e209 "drm/amdgpu: support partition drm devices" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index ee5267f916c5e..a3378ba6bdfe4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3089,8 +3089,11 @@ static struct drm_driver amdgpu_kms_driver = { const struct drm_driver amdgpu_partition_driver = { .driver_features = - DRIVER_GEM | DRIVER_RENDER | DRIVER_SYNCOBJ | - DRIVER_SYNCOBJ_TIMELINE, + DRIVER_GEM | DRIVER_RENDER | DRIVER_SYNCOBJ +#ifdef HAVE_DRM_DRV_DRIVER_SYNCOBJ_TIMELINE + | DRIVER_SYNCOBJ_TIMELINE +#endif /* HAVE_DRM_DRV_DRIVER_SYNCOBJ_TIMELINE */ + , .open = amdgpu_driver_open_kms, .postclose = amdgpu_driver_postclose_kms, .lastclose = amdgpu_driver_lastclose_kms, From 958ac64976071bc5f5edc348c4b52503977ae370 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 18 May 2023 13:50:38 +0800 Subject: [PATCH 1008/1868] drm/amdkcl: fake page_to_virt() It's caused by 5a3a28ac173e5dab4f4c3533693bd76596a5ae0e "drm/amdgpu: Allocate GART table in RAM for AMD APU" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- include/kcl/kcl_mm.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/kcl/kcl_mm.h b/include/kcl/kcl_mm.h index 2379879ed9932..a230fc776153a 100644 --- a/include/kcl/kcl_mm.h +++ b/include/kcl/kcl_mm.h @@ -96,4 +96,8 @@ struct vm_area_struct *vma_lookup(struct mm_struct *mm, unsigned long addr) #define VM_ACCESS_FLAGS (VM_READ | VM_WRITE | VM_EXEC) #endif +#ifndef page_to_virt +#define page_to_virt(x) __va(PFN_PHYS(page_to_pfn(x))) +#endif + #endif /* AMDKCL_MM_H */ From dd0b777092c2793b65081c0428e225e81ce1f80e Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 18 May 2023 15:27:33 +0800 Subject: [PATCH 1009/1868] drm/amdkcl: use amdkcl_ttm_resv to get resv It's caused by 33403d2365e4710712ac8575dd83bd6df61186c0 "drm/amdgpu: Add memory partition mem_id to amdgpu_bo" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 1695c73f49f15..7578e1823bf87 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -331,7 +331,7 @@ create_dmamap_sg_bo(struct amdgpu_device *adev, ret = amdgpu_gem_object_create(adev, mem->bo->tbo.base.size, 1, AMDGPU_GEM_DOMAIN_CPU, AMDGPU_GEM_CREATE_PREEMPTIBLE | flags, - ttm_bo_type_sg, mem->bo->tbo.base.resv, &gem_obj, 0); + ttm_bo_type_sg, amdkcl_ttm_resvp(&mem->bo->tbo), &gem_obj, 0); amdgpu_bo_unreserve(mem->bo); From c3da2abd8634aa2df334bb87045a5e24de5a3b44 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 18 May 2023 17:03:33 +0800 Subject: [PATCH 1010/1868] drm/amdkcl: fix non-upstream code for modifing kfd_dev to kfd_node It's caused by b0be1be09f5e15f00125940937bbab98c0dbc59d "drm/amdkfd: Introduce kfd_node struct (v5)" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_device.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c | 6 +++--- drivers/gpu/drm/amd/amdkfd/kfd_ipc.c | 8 ++++---- drivers/gpu/drm/amd/amdkfd/kfd_ipc.h | 8 ++++---- drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_spm.c | 5 +++-- drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 2 +- 9 files changed, 19 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 9d136d6b88849..4d72611a491ce 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -2381,7 +2381,7 @@ static int criu_restore_memory_of_gpu_ipc(struct kfd_process_device *pdd, struct kgd_mem **kgd_mem) { uint64_t alloc_handle = MAKE_HANDLE(pdd->user_gpu_id, bo_priv->idr_handle); - struct kfd_dev *dev = pdd->dev; + struct kfd_node *dev = pdd->dev; struct kfd_bo *kfd_bo; int ret, idr_handle; uint64_t offset; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index 8bb91d9c63057..b301a5b3d4cf8 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -584,7 +584,7 @@ static int kfd_gws_init(struct kfd_node *node) && kfd->mec2_fw_version < 0x30) || (KFD_GC_VERSION(kfd) >= IP_VERSION(11, 0, 0) && KFD_GC_VERSION(kfd) < IP_VERSION(12, 0, 0))) - kfd->gws_debug_workaround = true; + node->gws_debug_workaround = true; return ret; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c b/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c index cbd0d109ea883..3368779e354af 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c @@ -174,7 +174,7 @@ void kfd_doorbell_unmap_locked(struct kfd_process_device *pdd) pr_debug("Process %d unmapping doorbell 0x%lx\n", process->pasid, vma->vm_start); - size = kfd_doorbell_process_slice(pdd->dev); + size = kfd_doorbell_process_slice(pdd->dev->kfd); zap_vma_ptes(vma, vma->vm_start, size); pdd->qpd.doorbell_mapped = 0; } @@ -201,7 +201,7 @@ int kfd_doorbell_remap(struct kfd_process_device *pdd) /* Calculate physical address of doorbell */ address = kfd_get_process_doorbells(pdd); vma = pdd->qpd.doorbell_vma; - size = kfd_doorbell_process_slice(pdd->dev); + size = kfd_doorbell_process_slice(pdd->dev->kfd); pr_debug("Process %d remap doorbell 0x%lx\n", process->pasid, vma->vm_start); @@ -251,7 +251,7 @@ int kfd_doorbell_mmap(struct kfd_node *dev, struct kfd_process *process, " vm_flags == 0x%04lX\n" " size == 0x%04lX\n", process->pasid, (unsigned long long) vma->vm_start, - address, vma->vm_flags, kfd_doorbell_process_slice(dev)); + address, vma->vm_flags, kfd_doorbell_process_slice(dev->kfd)); pdd = kfd_get_process_device_data(dev, process); if (WARN_ON_ONCE(!pdd)) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c index 9cb5155809752..ab5769b0fe078 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c @@ -130,7 +130,7 @@ int kfd_ipc_init(void) return 0; } -static int kfd_import_dmabuf_create_kfd_bo(struct kfd_dev *dev, +static int kfd_import_dmabuf_create_kfd_bo(struct kfd_node *dev, struct kfd_process *p, uint32_t gpu_id, struct dma_buf *dmabuf, struct kfd_ipc_obj *ipc_obj, @@ -180,7 +180,7 @@ static int kfd_import_dmabuf_create_kfd_bo(struct kfd_dev *dev, return r; } -int kfd_ipc_import_dmabuf(struct kfd_dev *dev, +int kfd_ipc_import_dmabuf(struct kfd_node *dev, struct kfd_process *p, uint32_t gpu_id, int dmabuf_fd, uint64_t va_addr, uint64_t *handle, @@ -202,7 +202,7 @@ int kfd_ipc_import_dmabuf(struct kfd_dev *dev, return r; } -int kfd_ipc_import_handle(struct kfd_dev *dev, struct kfd_process *p, +int kfd_ipc_import_handle(struct kfd_node *dev, struct kfd_process *p, uint32_t gpu_id, uint32_t *share_handle, uint64_t va_addr, uint64_t *handle, uint64_t *mmap_offset, uint32_t *pflags, bool restore) @@ -253,7 +253,7 @@ int kfd_ipc_import_handle(struct kfd_dev *dev, struct kfd_process *p, return r; } -int kfd_ipc_export_as_handle(struct kfd_dev *dev, struct kfd_process *p, +int kfd_ipc_export_as_handle(struct kfd_node *dev, struct kfd_process *p, uint64_t handle, uint32_t *ipc_handle, uint32_t flags) { diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h index be0bf2b388194..6e92cce265d9e 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h @@ -28,7 +28,7 @@ #include /* avoid including kfd_priv.h */ -struct kfd_dev; +struct kfd_node; struct kfd_process; struct kfd_ipc_obj { @@ -39,15 +39,15 @@ struct kfd_ipc_obj { uint32_t flags; }; -int kfd_ipc_import_handle(struct kfd_dev *dev, struct kfd_process *p, +int kfd_ipc_import_handle(struct kfd_node *dev, struct kfd_process *p, uint32_t gpu_id, uint32_t *share_handle, uint64_t va_addr, uint64_t *handle, uint64_t *mmap_offset, uint32_t *pflags, bool restore); -int kfd_ipc_import_dmabuf(struct kfd_dev *kfd, struct kfd_process *p, +int kfd_ipc_import_dmabuf(struct kfd_node *kfd, struct kfd_process *p, uint32_t gpu_id, int dmabuf_fd, uint64_t va_addr, uint64_t *handle, uint64_t *mmap_offset); -int kfd_ipc_export_as_handle(struct kfd_dev *dev, struct kfd_process *p, +int kfd_ipc_export_as_handle(struct kfd_node *dev, struct kfd_process *p, uint64_t handle, uint32_t *ipc_handle, uint32_t flags); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c b/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c index 09cf783e460d3..50541b1dac44a 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c @@ -140,7 +140,7 @@ struct amd_mem_context { uint64_t size; unsigned long offset; struct amdgpu_bo *bo; - struct kfd_dev *dev; + struct kfd_node *dev; struct sg_table *pages; struct device *dma_dev; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index c16abbe5f6314..11a44f24120b8 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -396,7 +396,7 @@ struct kfd_ipc_obj; struct kfd_bo { void *mem; struct interval_tree_node it; - struct kfd_dev *dev; + struct kfd_node *dev; /* page-aligned VA address */ uint64_t cpuva; unsigned int mem_type; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c index b1fc5ace4015d..00da1cabcbd45 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c @@ -403,7 +403,7 @@ static int kfd_set_dest_buffer(struct kfd_process_device *pdd, struct amdgpu_dev int kfd_rlc_spm(struct kfd_process *p, void *data) { struct kfd_ioctl_spm_args *args = data; - struct kfd_dev *dev; + struct kfd_node *dev; struct kfd_process_device *pdd; dev = kfd_device_by_id(args->gpu_id); @@ -434,9 +434,10 @@ int kfd_rlc_spm(struct kfd_process *p, void *data) return -EINVAL; } -void kgd2kfd_spm_interrupt(struct kfd_dev *dev) +void kgd2kfd_spm_interrupt(struct kfd_dev *kfd) { struct kfd_process_device *pdd; + struct kfd_node *dev = kfd->nodes[0]; uint16_t pasid = dev->spm_pasid; struct kfd_process *p = kfd_lookup_process_by_pasid(pasid); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index 99deebdcac0d4..3fe374ecd6917 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -1291,7 +1291,7 @@ static void kfd_set_iolink_no_atomics(struct kfd_topology_device *dev, return; /* checkout source dev has atomics support on root. */ - if (dev->gpu && (!dev->gpu->pci_atomic_requested || + if (dev->gpu && (!dev->gpu->kfd->pci_atomic_requested || dev->gpu->adev->asic_type == CHIP_HAWAII)) { link->flags |= CRAT_IOLINK_FLAGS_NO_ATOMICS_32_BIT | CRAT_IOLINK_FLAGS_NO_ATOMICS_64_BIT; From 199dc156d798455a7d07ab53f640b1cd770db208 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 18 May 2023 17:21:50 +0800 Subject: [PATCH 1011/1868] drm/amdkcl: test whether acpi_dev_get_first_match_dev() is available It's caused by 69262b1d049af914e2adfd8faf4ea5a78c08d908 "drm/amdgpu: Add parsing of acpi xcc objects" 43a69a6ca2479df6fd52dd7f87ca764c986d791b "drm/amdgpu: Add API to get numa information of XCC" fd6a842cd66540bc7f3cea1c4239a8c3f6cad72f "drm/amdgpu: Store additional numa node information" a5cee52fba51789e4e71c25cbdeab89edbd0b397 "drm/amdgpu: Read discovery info from system memory" 72c23d1ee0f3b22f840f3f6c5f7b87870f62029c "drm/amdgpu: Add API to get tmr info from acpi" 042b4635e82a13f0467b4aa0f800039bdb22531b "drm/amdgpu: Add fallback path for discovery info" Signed-off-by: Bob Zhou Acked-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 11 ++++++++++- drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c | 8 ++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 6 ++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 ++ drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c | 4 ++++ drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 8 ++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../drm/amd/dkms/m4/acpi_dev_get_first_match_dev.m4 | 13 +++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 9 files changed, 55 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/acpi_dev_get_first_match_dev.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index d62396deb6ff1..cbea1bb3425ca 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1539,12 +1539,13 @@ struct amdgpu_afmt_acr { struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock); /* amdgpu_acpi.c */ - +#ifdef HAVE_ACPI_DEV_GET_FIRST_MATCH_DEV struct amdgpu_numa_info { uint64_t size; int pxm; int nid; }; +#endif /* ATCS Device/Driver State */ #define AMDGPU_ATCS_PSC_DEV_STATE_D0 0 @@ -1563,17 +1564,22 @@ int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, u8 dev_state, bool drv_state); int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum amdgpu_ss ss_state); int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev); +#ifdef HAVE_ACPI_DEV_GET_FIRST_MATCH_DEV int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, u64 *tmr_offset, u64 *tmr_size); int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, int xcc_id, struct amdgpu_numa_info *numa_info); +#endif void amdgpu_acpi_get_backlight_caps(struct amdgpu_dm_backlight_caps *caps); bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev); void amdgpu_acpi_detect(void); +#ifdef HAVE_ACPI_DEV_GET_FIRST_MATCH_DEV void amdgpu_acpi_release(void); +#endif #else static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; } +#ifdef HAVE_ACPI_DEV_GET_FIRST_MATCH_DEV static inline int amdgpu_acpi_get_tmr_info(struct amdgpu_device *adev, u64 *tmr_offset, u64 *tmr_size) { @@ -1585,10 +1591,13 @@ static inline int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, { return -EINVAL; } +#endif static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { } static inline bool amdgpu_acpi_should_gpu_reset(struct amdgpu_device *adev) { return false; } static inline void amdgpu_acpi_detect(void) { } +#ifdef HAVE_ACPI_DEV_GET_FIRST_MATCH_DEV static inline void amdgpu_acpi_release(void) { } +#endif static inline bool amdgpu_acpi_is_power_shift_control_supported(void) { return false; } static inline int amdgpu_acpi_power_shift_control(struct amdgpu_device *adev, u8 dev_state, bool drv_state) { return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c index d987b9b16e798..92634e1675267 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c @@ -39,6 +39,7 @@ #include "amd_acpi.h" #include "atom.h" +#ifdef HAVE_ACPI_DEV_GET_FIRST_MATCH_DEV /* Declare GUID for AMD _DSM method for XCCs */ static const guid_t amd_xcc_dsm_guid = GUID_INIT(0x8267f5d5, 0xa556, 0x44f2, 0xb8, 0xb4, 0x45, 0x56, 0x2e, @@ -77,6 +78,7 @@ struct amdgpu_acpi_dev_info { }; struct list_head amdgpu_acpi_dev_list; +#endif struct amdgpu_atif_notification_cfg { bool enabled; @@ -843,6 +845,7 @@ int amdgpu_acpi_smart_shift_update(struct drm_device *dev, enum amdgpu_ss ss_sta return r; } +#ifdef HAVE_ACPI_DEV_GET_FIRST_MATCH_DEV #ifdef CONFIG_ACPI_NUMA static inline uint64_t amdgpu_acpi_get_numa_size(int nid) { @@ -1183,6 +1186,7 @@ int amdgpu_acpi_get_mem_info(struct amdgpu_device *adev, int xcc_id, return -ENOENT; } +#endif /* HAVE_ACPI_DEV_GET_FIRST_MATCH_DEV */ /** * amdgpu_acpi_event - handle notify events @@ -1441,9 +1445,12 @@ void amdgpu_acpi_detect(void) atif->backlight_caps.caps_valid = false; } +#ifdef HAVE_ACPI_DEV_GET_FIRST_MATCH_DEV amdgpu_acpi_enumerate_xcc(); +#endif } +#ifdef HAVE_ACPI_DEV_GET_FIRST_MATCH_DEV void amdgpu_acpi_release(void) { struct amdgpu_acpi_dev_info *dev_info, *dev_tmp; @@ -1471,6 +1478,7 @@ void amdgpu_acpi_release(void) kfree(dev_info); } } +#endif #if IS_ENABLED(CONFIG_SUSPEND) /** diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index de5adc9c3cf9d..12d1e971e236c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -232,6 +232,7 @@ static int hw_id_map[MAX_HWIP] = { [ISP_HWIP] = ISP_HWID, }; +#ifdef HAVE_ACPI_DEV_GET_FIRST_MATCH_DEV static int amdgpu_discovery_read_binary_from_sysmem(struct amdgpu_device *adev, uint8_t *binary) { u64 tmr_offset, tmr_size, pos; @@ -254,6 +255,7 @@ static int amdgpu_discovery_read_binary_from_sysmem(struct amdgpu_device *adev, return -ENOENT; } +#endif #define IP_DISCOVERY_V2 2 #define IP_DISCOVERY_V4 4 @@ -284,13 +286,17 @@ static int amdgpu_discovery_read_binary_from_mem(struct amdgpu_device *adev, vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20; +#ifdef HAVE_ACPI_DEV_GET_FIRST_MATCH_DEV if (vram_size) { +#endif uint64_t pos = vram_size - DISCOVERY_TMR_OFFSET; amdgpu_device_vram_access(adev, pos, (uint32_t *)binary, adev->mman.discovery_tmr_size, false); +#ifdef HAVE_ACPI_DEV_GET_FIRST_MATCH_DEV } else { ret = amdgpu_discovery_read_binary_from_sysmem(adev, binary); } +#endif return ret; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index a3378ba6bdfe4..beaf92c30c8a0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3184,7 +3184,9 @@ static void __exit amdgpu_exit(void) amdgpu_amdkfd_fini(); pci_unregister_driver(&amdgpu_kms_pci_driver); amdgpu_unregister_atpx_handler(); +#ifdef HAVE_ACPI_DEV_GET_FIRST_MATCH_DEV amdgpu_acpi_release(); +#endif amdgpu_sync_fini(); amdgpu_fence_slab_fini(); #ifdef HAVE_MMU_NOTIFIER_SYNCHRONIZE diff --git a/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c b/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c index 228fd4dd32f13..77f20d9cddde2 100644 --- a/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c +++ b/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c @@ -587,6 +587,7 @@ static int aqua_vanjaram_switch_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr, return ret; } +#ifdef HAVE_ACPI_DEV_GET_FIRST_MATCH_DEV static int __aqua_vanjaram_get_xcp_mem_id(struct amdgpu_device *adev, int xcc_id, uint8_t *mem_id) { @@ -643,6 +644,7 @@ static int aqua_vanjaram_get_xcp_mem_id(struct amdgpu_xcp_mgr *xcp_mgr, return r; } +#endif static int aqua_vanjaram_get_xcp_ip_details(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id, enum AMDGPU_XCP_IP_BLOCK ip_id, @@ -658,7 +660,9 @@ struct amdgpu_xcp_mgr_funcs aqua_vanjaram_xcp_funcs = { .switch_partition_mode = &aqua_vanjaram_switch_partition_mode, .query_partition_mode = &aqua_vanjaram_query_partition_mode, .get_ip_details = &aqua_vanjaram_get_xcp_ip_details, +#ifdef HAVE_ACPI_DEV_GET_FIRST_MATCH_DEV .get_xcp_mem_id = &aqua_vanjaram_get_xcp_mem_id, +#endif .select_scheds = &aqua_vanjaram_select_scheds, .update_partition_sched_list = &aqua_vanjaram_update_partition_sched_list }; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index b73136d390cc0..4db0efcd0926a 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -78,7 +78,9 @@ #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2 0x05ea #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2_BASE_IDX 2 +#ifdef HAVE_ACPI_DEV_GET_FIRST_MATCH_DEV #define MAX_MEM_RANGES 8 +#endif static const char * const gfxhub_client_ids[] = { "CB", @@ -1806,6 +1808,7 @@ static void gmc_v9_0_save_registers(struct amdgpu_device *adev) adev->gmc.sdpif_register = RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0); } +#ifdef HAVE_ACPI_DEV_GET_FIRST_MATCH_DEV static bool gmc_v9_0_validate_partition_info(struct amdgpu_device *adev) { enum amdgpu_memory_partition mode; @@ -1980,6 +1983,7 @@ static int gmc_v9_0_init_mem_ranges(struct amdgpu_device *adev) return 0; } +#endif static void gmc_v9_4_3_init_vram_info(struct amdgpu_device *adev) { @@ -2149,12 +2153,14 @@ static int gmc_v9_0_sw_init(void *handle) amdgpu_gmc_get_vbios_allocations(adev); +#ifdef HAVE_ACPI_DEV_GET_FIRST_MATCH_DEV if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) { r = gmc_v9_0_init_mem_ranges(adev); if (r) return r; } +#endif /* Memory manager */ r = amdgpu_bo_init(adev); @@ -2218,8 +2224,10 @@ static int gmc_v9_0_sw_fini(void *handle) amdgpu_bo_free_kernel(&adev->gmc.pdb0_bo, NULL, &adev->gmc.ptr_pdb0); amdgpu_bo_fini(adev); +#ifdef HAVE_ACPI_DEV_GET_FIRST_MATCH_DEV adev->gmc.num_mem_partitions = 0; kfree(adev->gmc.mem_partitions); +#endif return 0; } diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 3628b5e7ecc6c..2ce17973f8f3d 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -320,6 +320,9 @@ /* drm_dp_mst_atomic_wait_for_dependencies() is available */ /* #undef HAVE_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES */ +/* acpi_dev_get_first_match_dev() is available */ +#define HAVE_ACPI_DEV_GET_FIRST_MATCH_DEV 1 + /* struct drm_dp_aux has member named 'drm_dev' */ #define HAVE_DRM_DP_AUX_DRM_DEV 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/acpi_dev_get_first_match_dev.m4 b/drivers/gpu/drm/amd/dkms/m4/acpi_dev_get_first_match_dev.m4 new file mode 100644 index 0000000000000..f83c2733ac2e1 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/acpi_dev_get_first_match_dev.m4 @@ -0,0 +1,13 @@ +dnl # +dnl # commit: v5.1-rc3-1-g817b4d64da03 +dnl # ACPI / utils: Introduce acpi_dev_get_first_match_dev() helper +dnl # +AC_DEFUN([AC_AMDGPU_ACPI_DEV_GET_FIRST_MATCH_DEV], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([acpi_dev_get_first_match_dev], + [drivers/acpi/utils.c], [ + AC_DEFINE(HAVE_ACPI_DEV_GET_FIRST_MATCH_DEV, 1, + [acpi_dev_get_first_match_dev() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 9d61eb812f767..aba70db2b1033 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -106,6 +106,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION AC_AMDGPU_JIFFIES64_TO_MSECS AC_AMDGPU_ACPI_PUT_TABLE + AC_AMDGPU_ACPI_DEV_GET_FIRST_MATCH_DEV AC_AMDGPU_DRM_ATOMIC_HELPER_CALC_TIMESTAMPING_CONSTANTS AC_AMDGPU_DRM_FORMAT_INFO AC_AMDGPU_STRUCT_DRM_CONNECTOR_STATE_COLORSPACE From f1682a34bedeb61ad83000686099e6ff77045b3d Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 30 May 2023 16:28:19 +0800 Subject: [PATCH 1012/1868] drm/amdkcl: amdxcp module add kcl support It's caused by 7dd353a7623ec9a10f9bfde53b19982f760995a2 "drm/amdxcp: add platform device driver for amdxcp" Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdxcp/Makefile | 3 + drivers/gpu/drm/amd/amdxcp/backport/Makefile | 10 +++ .../gpu/drm/amd/amdxcp/backport/backport.h | 1 + .../amdxcp/backport/include/kcl/kcl_drm_drv.h | 42 +++++++++ .../gpu/drm/amd/amdxcp/backport/kcl_drm_drv.c | 85 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/Makefile | 2 +- drivers/gpu/drm/amd/dkms/dkms.conf | 4 + 7 files changed, 146 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdxcp/backport/Makefile create mode 100644 drivers/gpu/drm/amd/amdxcp/backport/backport.h create mode 100644 drivers/gpu/drm/amd/amdxcp/backport/include/kcl/kcl_drm_drv.h create mode 100644 drivers/gpu/drm/amd/amdxcp/backport/kcl_drm_drv.c diff --git a/drivers/gpu/drm/amd/amdxcp/Makefile b/drivers/gpu/drm/amd/amdxcp/Makefile index 870501a4bb8c0..5790475464f02 100644 --- a/drivers/gpu/drm/amd/amdxcp/Makefile +++ b/drivers/gpu/drm/amd/amdxcp/Makefile @@ -23,3 +23,6 @@ amdxcp-y := amdgpu_xcp_drv.o obj-$(CONFIG_DRM_AMDGPU) += amdxcp.o + +AMD_XCP_PATH := $(src) +include $(AMD_XCP_PATH)/backport/Makefile diff --git a/drivers/gpu/drm/amd/amdxcp/backport/Makefile b/drivers/gpu/drm/amd/amdxcp/backport/Makefile new file mode 100644 index 0000000000000..4217ff962b225 --- /dev/null +++ b/drivers/gpu/drm/amd/amdxcp/backport/Makefile @@ -0,0 +1,10 @@ +BACKPORT_OBJS := kcl_drm_drv.o + +amdxcp-y += $(addprefix ./backport/,$(BACKPORT_OBJS)) + +ccflags-y += \ + -I$(AMD_XCP_PATH)/ \ + -I$(AMD_XCP_PATH)/backport/include \ + -I$(AMD_XCP_PATH)/../dkms \ + -include config/config.h \ + -include backport/backport.h diff --git a/drivers/gpu/drm/amd/amdxcp/backport/backport.h b/drivers/gpu/drm/amd/amdxcp/backport/backport.h new file mode 100644 index 0000000000000..9550a63357fb7 --- /dev/null +++ b/drivers/gpu/drm/amd/amdxcp/backport/backport.h @@ -0,0 +1 @@ +#include "kcl/kcl_drm_drv.h" \ No newline at end of file diff --git a/drivers/gpu/drm/amd/amdxcp/backport/include/kcl/kcl_drm_drv.h b/drivers/gpu/drm/amd/amdxcp/backport/include/kcl/kcl_drm_drv.h new file mode 100644 index 0000000000000..c331d7f60606b --- /dev/null +++ b/drivers/gpu/drm/amd/amdxcp/backport/include/kcl/kcl_drm_drv.h @@ -0,0 +1,42 @@ +/* + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * Copyright (c) 2009-2010, Code Aurora Forum. + * Copyright 2016 Intel Corp. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#ifndef __AMDXCP_BACKPORT_KCL_DRM_DRV_H__ +#define __AMDXCP_BACKPORT_KCL_DRM_DRV_H__ + +#include + +/* Copied from v5.7-rc1-343-gb0b5849e0cc0 include/drm/drm_drv.h */ +#ifndef devm_drm_dev_alloc +#define AMDKCL_DEVM_DRM_DEV_ALLOC 1 +void *__devm_drm_dev_alloc(struct device *parent, struct drm_driver *driver, + size_t size, size_t offset); +#define devm_drm_dev_alloc(parent, driver, type, member) \ + ((type *) __devm_drm_dev_alloc(parent, driver, sizeof(type), \ + offsetof(type, member))) + +#endif + +#endif diff --git a/drivers/gpu/drm/amd/amdxcp/backport/kcl_drm_drv.c b/drivers/gpu/drm/amd/amdxcp/backport/kcl_drm_drv.c new file mode 100644 index 0000000000000..4b2d043f4665a --- /dev/null +++ b/drivers/gpu/drm/amd/amdxcp/backport/kcl_drm_drv.c @@ -0,0 +1,85 @@ +/* + * Created: Fri Jan 19 10:48:35 2001 by faith@acm.org + * + * Copyright 2001 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Author Rickard E. (Rik) Faith + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#include +#include +#include + +#ifdef AMDKCL_DEVM_DRM_DEV_ALLOC +static void devm_drm_dev_init_release(void *data) +{ + drm_dev_put(data); + +#ifndef HAVE_DRM_DRM_MANAGED_H + if(data){ + struct drm_device *dev = data; + if(!kref_read(&dev->ref)) + kfree(dev->dev_private); + } +#endif +} +/* Copied from v5.7-rc1-343-gb0b5849e0cc0 drivers/gpu/drm/drm_drv.c and modified for KCL */ +static int devm_drm_dev_init(struct device *parent, + struct drm_device *dev, + const struct drm_driver *driver) +{ + int ret; + + ret = drm_dev_init(dev, driver, parent); + if (ret) + return ret; + + return devm_add_action_or_reset(parent, + devm_drm_dev_init_release, dev); +} + +void *__devm_drm_dev_alloc(struct device *parent, struct drm_driver *driver, + size_t size, size_t offset) +{ + void *container; + struct drm_device *drm; + int ret; + + container = kzalloc(size, GFP_KERNEL); + if (!container) + return ERR_PTR(-ENOMEM); + + drm = container + offset; + ret = devm_drm_dev_init(parent, drm, driver); + if (ret) { + kfree(container); + return ERR_PTR(ret); + } +#ifdef HAVE_DRM_DRM_MANAGED_H + drmm_add_final_kfree(drm, container); +#else + drm->dev_private = container; +#endif + return container; +} + +#endif diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 0c7477083f0ec..39facc822b351 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -223,4 +223,4 @@ include $(src)/amd/dkms/Makefile.drm_ttm_helper include $(src)/amd/dkms/Makefile.drm_buddy -obj-m += scheduler/ amd/amdgpu/ ttm/ amd/amdkcl/ +obj-m += scheduler/ amd/amdgpu/ amd/amdxcp/ ttm/ amd/amdkcl/ diff --git a/drivers/gpu/drm/amd/dkms/dkms.conf b/drivers/gpu/drm/amd/dkms/dkms.conf index ec2c979254b55..78cc07704d491 100644 --- a/drivers/gpu/drm/amd/dkms/dkms.conf +++ b/drivers/gpu/drm/amd/dkms/dkms.conf @@ -34,6 +34,10 @@ BUILT_MODULE_NAME[5]="amddrm_buddy" BUILT_MODULE_LOCATION[5]="." DEST_MODULE_LOCATION[5]="/kernel/drivers/gpu/drm" +BUILT_MODULE_NAME[6]="amdxcp" +BUILT_MODULE_LOCATION[6]="amd/amdxcp" +DEST_MODULE_LOCATION[6]="/kernel/drivers/gpu/drm/amd/amdxcp" + MAKE[0]="make TTM_NAME=${BUILT_MODULE_NAME[1]} \ SCHED_NAME=${BUILT_MODULE_NAME[3]} \ -C $kernel_source_dir \ From 57767566712137de4aa53c6a261f1c3ee99192b2 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 5 Jun 2023 13:51:23 +0800 Subject: [PATCH 1013/1868] drm/amdkcl: fake macro DECLARE_FLEX_ARRAY It's caused by 46ca366ec5b07937357d6c0aaecf706b3b762abd "drm/amdgpu/discovery: Replace fake flex-arrays with flexible-array members" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- include/kcl/kcl_stddef.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/include/kcl/kcl_stddef.h b/include/kcl/kcl_stddef.h index dc455e1423ab1..2656ab3239f48 100644 --- a/include/kcl/kcl_stddef.h +++ b/include/kcl/kcl_stddef.h @@ -13,4 +13,22 @@ #define sizeof_field(TYPE, MEMBER) sizeof((((TYPE *)0)->MEMBER)) #endif +#ifndef DECLARE_FLEX_ARRAY +/** + * DECLARE_FLEX_ARRAY() - Declare a flexible array usable in a union + * + * @TYPE: The type of each flexible array element + * @NAME: The name of the flexible array member + * + * In order to have a flexible array member in a union or alone in a + * struct, it needs to be wrapped in an anonymous struct with at least 1 + * named member, but that member can be empty. + */ +#define DECLARE_FLEX_ARRAY(TYPE, NAME) \ + struct { \ + struct { } __empty_ ## NAME; \ + TYPE NAME[]; \ + } +#endif + #endif From 075b874be22af08b9a689fd904ddfe435eede41a Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 7 Jun 2023 14:13:26 +0800 Subject: [PATCH 1014/1868] drm/amdkcl: check whether drm_gem_object->resv is available It's caused by c7cc29bdccb3ba26fe4de78df70c4c9c8a279af8 "drm/amdgpu: Add a low priority scheduler for VRAM clearing" Signed-off-by: Asher Song Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index 4a3aea629d6dd..c6d3ea93acdc1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -656,7 +656,7 @@ int amdgpu_bo_create(struct amdgpu_device *adev, bo->tbo.resource->mem_type == TTM_PL_VRAM) { struct dma_fence *fence; - r = amdgpu_ttm_clear_buffer(bo, bo->tbo.base.resv, &fence); + r = amdgpu_ttm_clear_buffer(bo, amdkcl_ttm_resvp(&bo->tbo), &fence); if (unlikely(r)) goto fail_unreserve; @@ -1409,7 +1409,7 @@ void amdgpu_bo_release_notify(struct ttm_buffer_object *bo) if (WARN_ON_ONCE(!dma_resv_trylock(amdkcl_ttm_resvp(bo)))) return; - r = amdgpu_fill_buffer(abo, 0, bo->base.resv, &fence, true); + r = amdgpu_fill_buffer(abo, 0, amdkcl_ttm_resvp(bo), &fence, true); if (!WARN_ON(r)) { amdgpu_vram_mgr_set_cleared(bo->resource); amdgpu_bo_fence(abo, fence, false); From 226e00087c85cccf6e5bb026990d1a251a350b8e Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 1 Aug 2023 17:10:04 +0800 Subject: [PATCH 1015/1868] drm/amdkcl: kcl-cleanup for_each_{old/new/oldnew}_{plane/connector/crtc}_in_state Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi Signed-off-by: Asher Song --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 31 ------------------- 2 files changed, 35 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index b0dc359c7539b..aa257beebe764 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -11653,11 +11653,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, goto fail; } -#if !defined(for_each_new_crtc_in_state) - for_each_crtc_in_state(state, crtc, new_crtc_state, i) { -#else for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) { -#endif dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); if (dm_new_crtc_state->mpo_requested) drm_dbg_atomic(dev, "MPO enablement requested on crtc:[%p]\n", crtc); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index b3d6443b8cd59..861f9c03af65e 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -201,31 +201,6 @@ struct amdgpu_dm_backlight_caps { u8 dc_level; }; -/** - * for_each_oldnew_plane_in_state_reverse - iterate over all planes in an atomic - * update in reverse order - * @__state: &struct drm_atomic_state pointer - * @plane: &struct drm_plane iteration cursor - * @old_plane_state: &struct drm_plane_state iteration cursor for the old state - * @new_plane_state: &struct drm_plane_state iteration cursor for the new state - * @__i: int iteration cursor, for macro-internal use - * - * This iterates over all planes in an atomic update in reverse order, - * tracking both old and new state. This is useful in places where the - * state delta needs to be considered, for example in atomic check functions. - */ -#if !defined(for_each_oldnew_plane_in_state_reverse) && \ - defined(for_each_oldnew_plane_in_state) -#define for_each_oldnew_plane_in_state_reverse(__state, plane, old_plane_state, new_plane_state, __i) \ - for ((__i) = ((__state)->dev->mode_config.num_total_plane - 1); \ - (__i) >= 0; \ - (__i)--) \ - for_each_if ((__state)->planes[__i].ptr && \ - ((plane) = (__state)->planes[__i].ptr, \ - (old_plane_state) = (__state)->planes[__i].old_state,\ - (new_plane_state) = (__state)->planes[__i].new_state, 1)) -#endif - /** * struct dal_allocation - Tracks mapped FB memory for SMU communication * @list: list of dal allocations @@ -240,7 +215,6 @@ struct dal_allocation { u64 gpu_addr; }; - /** * struct hpd_rx_irq_offload_work_queue - Work queue to handle hpd_rx_irq * offload work @@ -1034,12 +1008,7 @@ int dm_atomic_get_state(struct drm_atomic_state *state, struct drm_connector * amdgpu_dm_find_first_crtc_matching_connector(struct drm_atomic_state *state, -#ifndef for_each_new_connector_in_state - struct drm_crtc *crtc, - bool from_state_var); -#else struct drm_crtc *crtc); -#endif int convert_dc_color_depth_into_bpc(enum dc_color_depth display_color_depth); struct idle_workqueue *idle_create_workqueue(struct amdgpu_device *adev); From 2709c8eec88e5793fecc16c54e4ec11aa942a154 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 7 Jun 2023 18:46:51 +0800 Subject: [PATCH 1016/1868] drm/amdkcl: Optimize the interrupt the process function Fake the generic_handle_domain_irq function to optimize the irq process function Signed-off-by: Ma Jun Reviewed-by: Flora.Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 5 ---- drivers/gpu/drm/amd/amdkcl/Makefile | 3 +- drivers/gpu/drm/amd/amdkcl/kcl_irqdesc.c | 38 ++++++++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_irqdesc.h | 11 +++++++ 5 files changed, 52 insertions(+), 6 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_irqdesc.c create mode 100644 include/kcl/kcl_irqdesc.h diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c index 0c9da161205f9..c7aedaa69ea4e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c @@ -476,12 +476,7 @@ void amdgpu_irq_dispatch(struct amdgpu_device *adev, } else if (((client_id == AMDGPU_IRQ_CLIENTID_LEGACY) || (client_id == SOC15_IH_CLIENTID_ISP)) && adev->irq.virq[src_id]) { -#ifdef HAVE_GENERIC_HANDLE_DOMAIN_IRQ generic_handle_domain_irq(adev->irq.domain, src_id); -#else - generic_handle_irq(irq_find_mapping(adev->irq.domain, src_id)); -#endif - } else if (!adev->irq.client[client_id].sources) { DRM_DEBUG("Unregistered interrupt client_id: %d src_id: %d\n", client_id, src_id); diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index ac231fe69b8ac..08b2e37192c57 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -13,7 +13,8 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_fs_read_write.o kcl_drm_aperture.o \ kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o \ - kcl_mce_amd.o kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o kcl_mm_slab.o + kcl_mce_amd.o kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o kcl_mm_slab.o \ + kcl_irqdesc.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_irqdesc.c b/drivers/gpu/drm/amd/amdkcl/kcl_irqdesc.c new file mode 100644 index 0000000000000..e53a60dbb71f0 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_irqdesc.c @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 1992, 1998-2006 Linus Torvalds, Ingo Molnar + * Copyright (C) 2005-2006, Thomas Gleixner, Russell King + * + * This file contains the interrupt descriptor management code. Detailed + * information is available in Documentation/core-api/genericirq.rst + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +/** + * generic_handle_irq - Invoke the handler for a particular irq + * @irq: The irq number to handle + * + * Returns: 0 on success, or -EINVAL if conversion has failed + * + * This function must be called from an IRQ context with irq regs + * initialized. + */ +#ifndef HAVE_GENERIC_HANDLE_DOMAIN_IRQ +int kcl_generic_handle_domain_irq(struct irq_domain *domain, unsigned int hwirq) +{ + int irq; + irq = irq_find_mapping(domain, hwirq); + + return generic_handle_irq(irq); +} +EXPORT_SYMBOL_GPL(kcl_generic_handle_domain_irq); +#endif \ No newline at end of file diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 40a3fb993aa29..259c928e8a2f5 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -107,4 +107,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_irqdesc.h b/include/kcl/kcl_irqdesc.h new file mode 100644 index 0000000000000..1e439ea146d7c --- /dev/null +++ b/include/kcl/kcl_irqdesc.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMDKCL_IRQDESC_H +#define AMDKCL_IRQDESC_H + +#ifndef HAVE_GENERIC_HANDLE_DOMAIN_IRQ +int kcl_generic_handle_domain_irq(struct irq_domain *domain, unsigned int hwirq); +#define generic_handle_domain_irq kcl_generic_handle_domain_irq +#endif /* HAVE_GENERIC_HANDLE_DOMAIN_IRQ */ + +#endif From e6a8e236f8e1a4df6fd1e574fbabc09a7bde0622 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 29 May 2023 16:08:12 +0800 Subject: [PATCH 1017/1868] drm/amdkcl:drop redundant sched job cleanup It's caused by e9cc9cd75f2ce58751619436133cf44617268060 "drm/amdgpu: drop redundant sched job cleanup when cs is aborted" Signed-off-by: Asher Song Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index eefb5bf2b6484..472af355eeff3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -1452,7 +1452,8 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm)) { r = -ERESTARTSYS; - goto error_unlock; + amdgpu_mn_unlock(p->mn); + return r; } } #endif From d9f2ed02f1da69b8c2fce8a5fb562731f86c4eed Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 9 Jun 2023 15:13:26 +0800 Subject: [PATCH 1018/1868] drm/amdkcl: fake macro PCI_CLASS_ACCELERATOR_PROCESSING It's caused by 186e61eda3749bf2ec669f73fa7c10bdf049a7ce "drm/amdgpu: add the accelerator PCIe class" Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_pci_ids.h | 10 ++++++++++ 2 files changed, 11 insertions(+) create mode 100644 include/kcl/kcl_pci_ids.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 259c928e8a2f5..e69fb1878b8b7 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -108,4 +108,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_pci_ids.h b/include/kcl/kcl_pci_ids.h new file mode 100644 index 0000000000000..e56bf58438f5b --- /dev/null +++ b/include/kcl/kcl_pci_ids.h @@ -0,0 +1,10 @@ +#ifndef AMDKCL_PCI_IDS_H +#define AMDKCL_PCI_IDS_H + +#include + +#ifndef PCI_CLASS_ACCELERATOR_PROCESSING +#define PCI_CLASS_ACCELERATOR_PROCESSING 0x1200 +#endif + +#endif \ No newline at end of file From 080bd34228fd4fd61a6145e9cdec7e70c4e72bc3 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 9 Jun 2023 13:39:20 +0800 Subject: [PATCH 1019/1868] drm/amdkcl: fake drm_mode_create_colorspace_property functions It's cauesd by a9fa9b21c98f7ebeb76897c1f9c6796508aed5a5 "drm/amd/display: Register Colorspace property for DP and HDMI" Signed-off-by: Bob Zhou --- .../gpu/drm/amd/amdkcl/kcl_drm_connector.c | 163 ++++++++++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 9 + ...rm_mode_create_hdmi_colorspace_property.m4 | 49 ++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_connector.h | 50 ++++++ 5 files changed, 272 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_mode_create_hdmi_colorspace_property.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c index a4a4e8d2e9acf..559b2610f2966 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c @@ -89,3 +89,166 @@ int _kcl_drm_connector_set_panel_orientation_with_quirk( } EXPORT_SYMBOL(_kcl_drm_connector_set_panel_orientation_with_quirk); #endif + +#ifndef HAVE_DRM_CONNECT_ATTACH_COLORSPACE_PROPERTY +struct drm_property *prop = NULL; +int _kcl_drm_connector_attach_colorspace_property(struct drm_connector *connector) +{ + if(prop) + drm_object_attach_property(&connector->base, prop, DRM_MODE_COLORIMETRY_DEFAULT); + + return 0; +} +EXPORT_SYMBOL(_kcl_drm_connector_attach_colorspace_property); +#endif + +#ifdef KCL_DRM_MODE_CREATE_COLORSPACE_PROPERTY +/* copy from drivers/gpu/drm/drm_connector.c (v6.1-5788-gac3470b13f0d) */ +static const char * const colorspace_names[] = { + /* For Default case, driver will set the colorspace */ + [DRM_MODE_COLORIMETRY_DEFAULT] = "Default", + /* Standard Definition Colorimetry based on CEA 861 */ + [DRM_MODE_COLORIMETRY_SMPTE_170M_YCC] = "SMPTE_170M_YCC", + [DRM_MODE_COLORIMETRY_BT709_YCC] = "BT709_YCC", + /* Standard Definition Colorimetry based on IEC 61966-2-4 */ + [DRM_MODE_COLORIMETRY_XVYCC_601] = "XVYCC_601", + /* High Definition Colorimetry based on IEC 61966-2-4 */ + [DRM_MODE_COLORIMETRY_XVYCC_709] = "XVYCC_709", + /* Colorimetry based on IEC 61966-2-1/Amendment 1 */ + [DRM_MODE_COLORIMETRY_SYCC_601] = "SYCC_601", + /* Colorimetry based on IEC 61966-2-5 [33] */ + [DRM_MODE_COLORIMETRY_OPYCC_601] = "opYCC_601", + /* Colorimetry based on IEC 61966-2-5 */ + [DRM_MODE_COLORIMETRY_OPRGB] = "opRGB", + /* Colorimetry based on ITU-R BT.2020 */ + [DRM_MODE_COLORIMETRY_BT2020_CYCC] = "BT2020_CYCC", + /* Colorimetry based on ITU-R BT.2020 */ + [DRM_MODE_COLORIMETRY_BT2020_RGB] = "BT2020_RGB", + /* Colorimetry based on ITU-R BT.2020 */ + [DRM_MODE_COLORIMETRY_BT2020_YCC] = "BT2020_YCC", + /* Added as part of Additional Colorimetry Extension in 861.G */ + [DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65] = "DCI-P3_RGB_D65", + [DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER] = "DCI-P3_RGB_Theater", + [DRM_MODE_COLORIMETRY_RGB_WIDE_FIXED] = "RGB_WIDE_FIXED", + /* Colorimetry based on scRGB (IEC 61966-2-2) */ + [DRM_MODE_COLORIMETRY_RGB_WIDE_FLOAT] = "RGB_WIDE_FLOAT", + [DRM_MODE_COLORIMETRY_BT601_YCC] = "BT601_YCC", +}; + +static const u32 hdmi_colorspaces = + BIT(DRM_MODE_COLORIMETRY_SMPTE_170M_YCC) | + BIT(DRM_MODE_COLORIMETRY_BT709_YCC) | + BIT(DRM_MODE_COLORIMETRY_XVYCC_601) | + BIT(DRM_MODE_COLORIMETRY_XVYCC_709) | + BIT(DRM_MODE_COLORIMETRY_SYCC_601) | + BIT(DRM_MODE_COLORIMETRY_OPYCC_601) | + BIT(DRM_MODE_COLORIMETRY_OPRGB) | + BIT(DRM_MODE_COLORIMETRY_BT2020_CYCC) | + BIT(DRM_MODE_COLORIMETRY_BT2020_RGB) | + BIT(DRM_MODE_COLORIMETRY_BT2020_YCC) | + BIT(DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65) | + BIT(DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER); + +static const u32 dp_colorspaces = + BIT(DRM_MODE_COLORIMETRY_RGB_WIDE_FIXED) | + BIT(DRM_MODE_COLORIMETRY_RGB_WIDE_FLOAT) | + BIT(DRM_MODE_COLORIMETRY_OPRGB) | + BIT(DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65) | + BIT(DRM_MODE_COLORIMETRY_BT2020_RGB) | + BIT(DRM_MODE_COLORIMETRY_BT601_YCC) | + BIT(DRM_MODE_COLORIMETRY_BT709_YCC) | + BIT(DRM_MODE_COLORIMETRY_XVYCC_601) | + BIT(DRM_MODE_COLORIMETRY_XVYCC_709) | + BIT(DRM_MODE_COLORIMETRY_SYCC_601) | + BIT(DRM_MODE_COLORIMETRY_OPYCC_601) | + BIT(DRM_MODE_COLORIMETRY_BT2020_CYCC) | + BIT(DRM_MODE_COLORIMETRY_BT2020_YCC); + +static int drm_mode_create_colorspace_property(struct drm_connector *connector, + u32 supported_colorspaces) +{ + struct drm_device *dev = connector->dev; + u32 colorspaces = supported_colorspaces | BIT(DRM_MODE_COLORIMETRY_DEFAULT); + struct drm_prop_enum_list enum_list[DRM_MODE_COLORIMETRY_COUNT]; + int i, len; + +#ifdef HAVE_DRM_CONNECT_ATTACH_COLORSPACE_PROPERTY + if (connector->colorspace_property) +#else + if (prop) +#endif + return 0; + + + if (!supported_colorspaces) { + drm_err(dev, "No supported colorspaces provded on [CONNECTOR:%d:%s]\n", + connector->base.id, connector->name); + return -EINVAL; + } + + if ((supported_colorspaces & -BIT(DRM_MODE_COLORIMETRY_COUNT)) != 0) { + drm_err(dev, "Unknown colorspace provded on [CONNECTOR:%d:%s]\n", + connector->base.id, connector->name); + return -EINVAL; + } + + len = 0; + for (i = 0; i < DRM_MODE_COLORIMETRY_COUNT; i++) { + if ((colorspaces & BIT(i)) == 0) + continue; + + enum_list[len].type = i; + enum_list[len].name = colorspace_names[i]; + len++; + } +#ifdef HAVE_DRM_CONNECT_ATTACH_COLORSPACE_PROPERTY + connector->colorspace_property = +#else + prop = +#endif + drm_property_create_enum(dev, DRM_MODE_PROP_ENUM, "Colorspace", + enum_list, + len); + +#ifdef HAVE_DRM_CONNECT_ATTACH_COLORSPACE_PROPERTY + if (!connector->colorspace_property) +#else + if (!prop) +#endif + return -ENOMEM; + + return 0; +} +#endif /* KCL_DRM_MODE_CREATE_COLORSPACE_PROPERTY */ + +#ifndef HAVE_DRM_MODE_CREATE_HDMI_COLORSPACE_PROPERTY_2ARGS +int _kcl_drm_mode_create_hdmi_colorspace_property(struct drm_connector *connector, + u32 supported_colorspaces) +{ + u32 colorspaces; + + if (supported_colorspaces) + colorspaces = supported_colorspaces & hdmi_colorspaces; + else + colorspaces = hdmi_colorspaces; + + return drm_mode_create_colorspace_property(connector, colorspaces); +} +EXPORT_SYMBOL(_kcl_drm_mode_create_hdmi_colorspace_property); +#endif + +#ifndef HAVE_DRM_MODE_CREATE_DP_COLORSPACE_PROPERTY_2ARGS +int _kcl_drm_mode_create_dp_colorspace_property(struct drm_connector *connector, + u32 supported_colorspaces) +{ + u32 colorspaces; + + if (supported_colorspaces) + colorspaces = supported_colorspaces & dp_colorspaces; + else + colorspaces = dp_colorspaces; + + return drm_mode_create_colorspace_property(connector, colorspaces); +} +EXPORT_SYMBOL(_kcl_drm_mode_create_dp_colorspace_property); +#endif \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 2ce17973f8f3d..4cc4547ffd552 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -467,6 +467,15 @@ /* drm_dsc_compute_rc_parameters() is available */ #define HAVE_DRM_DSC_COMPUTE_RC_PARAMETERS 1 +/* drm_connector_attach_colorspace_property() is available */ +#define HAVE_DRM_CONNECT_ATTACH_COLORSPACE_PROPERTY 1 + +/* drm_mode_create_hdmi_colorspace_property() has 2 args */ +#define HAVE_DRM_MODE_CREATE_HDMI_COLORSPACE_PROPERTY_2ARGS 1 + +/* drm_mode_create_dp_colorspace_property() has 2 args */ +#define HAVE_DRM_MODE_CREATE_DP_COLORSPACE_PROPERTY_2ARGS 1 + /* struct drm_dsc_config has member simple_422 */ #define HAVE_DRM_DSC_CONFIG_SIMPLE_422 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_mode_create_hdmi_colorspace_property.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_mode_create_hdmi_colorspace_property.m4 new file mode 100644 index 0000000000000..7a8fe049ac51b --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_mode_create_hdmi_colorspace_property.m4 @@ -0,0 +1,49 @@ +dnl # +dnl # commit v5.3-rc1-675-g8806cd3aa025 +dnl # drm: Rename HDMI colorspace property creation function +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECT_ATTACH_COLORSPACE_PROPERTY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([drm_connector_attach_colorspace_property], [drivers/gpu/drm/drm_connector.c], [ + AC_DEFINE(HAVE_DRM_CONNECT_ATTACH_COLORSPACE_PROPERTY, 1, + [drm_connector_attach_colorspace_property() is available]) + ]) + ]) +]) + +dnl # +dnl # commit v6.1-5783-g08383039cd19 +dnl # drm/connector: Allow drivers to pass list of supported colorspaces +dnl # +AC_DEFUN([AC_AMDGPU_DRM_MODE_CREATE_HDMI_COLORSPACE_PROPERTY], [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_mode_create_hdmi_colorspace_property(NULL, 0); + ], [drm_mode_create_hdmi_colorspace_property], [drivers/gpu/drm/drm_connector.c], [ + AC_DEFINE(HAVE_DRM_MODE_CREATE_HDMI_COLORSPACE_PROPERTY_2ARGS, 1, + [drm_mode_create_hdmi_colorspace_property() has 2 args]) + ]) +]) + +dnl # +dnl # commit v6.1-5783-g08383039cd19 +dnl # drm/connector: Allow drivers to pass list of supported colorspaces +dnl # +AC_DEFUN([AC_AMDGPU_DRM_MODE_CREATE_DP_COLORSPACE_PROPERTY], [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_mode_create_dp_colorspace_property(NULL, 0); + ], [drm_mode_create_dp_colorspace_property], [drivers/gpu/drm/drm_connector.c], [ + AC_DEFINE(HAVE_DRM_MODE_CREATE_DP_COLORSPACE_PROPERTY_2ARGS, 1, + [drm_mode_create_dp_colorspace_property() has 2 args]) + ]) +]) + + +AC_DEFUN([AC_AMDGPU_DRM_MODE_CREATE_COLORSPACE_PROPERTY_FUNCS], [ + AC_AMDGPU_DRM_CONNECT_ATTACH_COLORSPACE_PROPERTY + AC_AMDGPU_DRM_MODE_CREATE_HDMI_COLORSPACE_PROPERTY + AC_AMDGPU_DRM_MODE_CREATE_DP_COLORSPACE_PROPERTY +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index aba70db2b1033..352bbb7a5746c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -104,6 +104,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_MODE_CONFIG AC_AMDGPU_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION + AC_AMDGPU_DRM_MODE_CREATE_COLORSPACE_PROPERTY_FUNCS AC_AMDGPU_JIFFIES64_TO_MSECS AC_AMDGPU_ACPI_PUT_TABLE AC_AMDGPU_ACPI_DEV_GET_FIRST_MATCH_DEV diff --git a/include/kcl/kcl_drm_connector.h b/include/kcl/kcl_drm_connector.h index ee8d72d7a4d72..9e95e282f458a 100644 --- a/include/kcl/kcl_drm_connector.h +++ b/include/kcl/kcl_drm_connector.h @@ -25,6 +25,7 @@ #include #include #include +#include /* * commit v4.9-rc4-949-g949f08862d66 @@ -108,6 +109,29 @@ int drm_connector_set_panel_orientation_with_quirk( } #endif +#ifndef HAVE_DRM_CONNECT_ATTACH_COLORSPACE_PROPERTY +int _kcl_drm_connector_attach_colorspace_property(struct drm_connector *connector); +#define drm_connector_attach_colorspace_property _kcl_drm_connector_attach_colorspace_property +#endif /* HAVE_DRM_CONNECT_ATTACH_COLORSPACE_PROPERTY */ + +#ifndef HAVE_DRM_MODE_CREATE_HDMI_COLORSPACE_PROPERTY_2ARGS +#define KCL_DRM_MODE_CREATE_COLORSPACE_PROPERTY +int _kcl_drm_mode_create_hdmi_colorspace_property(struct drm_connector *connector, + u32 supported_colorspaces); +#define drm_mode_create_hdmi_colorspace_property _kcl_drm_mode_create_hdmi_colorspace_property +#endif /* HAVE_DRM_MODE_CREATE_HDMI_COLORSPACE_PROPERTY_2ARGS */ + +#ifndef HAVE_DRM_MODE_CREATE_DP_COLORSPACE_PROPERTY_2ARGS +#define KCL_DRM_MODE_CREATE_COLORSPACE_PROPERTY +int _kcl_drm_mode_create_dp_colorspace_property(struct drm_connector *connector, + u32 supported_colorspaces); +#define drm_mode_create_dp_colorspace_property _kcl_drm_mode_create_dp_colorspace_property +#endif /* HAVE_DRM_MODE_CREATE_DP_COLORSPACE_PROPERTY_2ARGS */ + +#ifdef KCL_DRM_MODE_CREATE_COLORSPACE_PROPERTY +#define DRM_MODE_COLORIMETRY_COUNT 16 +#endif + #ifndef DRM_COLOR_FORMAT_YCBCR444 #define DRM_COLOR_FORMAT_YCBCR444 (1<<1) #endif @@ -120,4 +144,30 @@ int drm_connector_set_panel_orientation_with_quirk( #define DRM_COLOR_FORMAT_YCBCR420 (1<<3) #endif +/* For Default case, driver will set the colorspace */ +#ifndef DRM_MODE_COLORIMETRY_DEFAULT +/* For Default case, driver will set the colorspace */ +#define DRM_MODE_COLORIMETRY_DEFAULT 0 +/* CEA 861 Normal Colorimetry options */ +#define DRM_MODE_COLORIMETRY_NO_DATA 0 +#define DRM_MODE_COLORIMETRY_SMPTE_170M_YCC 1 +#define DRM_MODE_COLORIMETRY_BT709_YCC 2 +/* CEA 861 Extended Colorimetry Options */ +#define DRM_MODE_COLORIMETRY_XVYCC_601 3 +#define DRM_MODE_COLORIMETRY_XVYCC_709 4 +#define DRM_MODE_COLORIMETRY_SYCC_601 5 +#define DRM_MODE_COLORIMETRY_OPYCC_601 6 +#define DRM_MODE_COLORIMETRY_OPRGB 7 +#define DRM_MODE_COLORIMETRY_BT2020_CYCC 8 +#define DRM_MODE_COLORIMETRY_BT2020_RGB 9 +#define DRM_MODE_COLORIMETRY_BT2020_YCC 10 +/* Additional Colorimetry extension added as part of CTA 861.G */ +#define DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65 11 +#define DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER 12 +/* Additional Colorimetry Options added for DP 1.4a VSC Colorimetry Format */ +#define DRM_MODE_COLORIMETRY_RGB_WIDE_FIXED 13 +#define DRM_MODE_COLORIMETRY_RGB_WIDE_FLOAT 14 +#define DRM_MODE_COLORIMETRY_BT601_YCC 15 +#endif /* DRM_MODE_COLORIMETRY_DEFAULT */ + #endif /* AMDKCL_DRM_CONNECTOR_H */ From 4cf3caf111b8f09e353c7e94bcc91d72e362db80 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 13 Jun 2023 15:44:45 +0800 Subject: [PATCH 1020/1868] drm/amdkcl: fix non-upsteam code for amdgpu_vmid_alloc/free_reserved() It's caused by b43f292541814d06ee154d16cd0eae0d80a81ab6 "drm/amdgpu: add option params to enforce process isolation between graphics and compute" Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c index 82c270b3a6946..0d1007d6f146b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c @@ -58,9 +58,12 @@ int amdgpu_amdkfd_rlc_spm_acquire(struct amdgpu_device *adev, struct amdgpu_vm * if (!adev->gfx.rlc.funcs->update_spm_vmid) return -EINVAL; - r = amdgpu_vmid_alloc_reserved(adev, vm, AMDGPU_GFXHUB(0)); + if (!vm->reserved_vmid[AMDGPU_GFXHUB(0)]) { + r = amdgpu_vmid_alloc_reserved(adev, AMDGPU_GFXHUB(0)); if (r) return r; + vm->reserved_vmid[AMDGPU_GFXHUB(0)] = true; + } /* init spm vmid with 0x0 */ adev->gfx.rlc.funcs->update_spm_vmid(adev, 0); @@ -85,7 +88,10 @@ void amdgpu_amdkfd_rlc_spm_release(struct amdgpu_device *adev, struct amdgpu_vm amdgpu_ring_commit(kiq_ring); spin_unlock(&adev->gfx.kiq[0].ring_lock); - amdgpu_vmid_free_reserved(adev, vm, AMDGPU_GFXHUB(0)); + if (vm->reserved_vmid[AMDGPU_GFXHUB(0)]) { + amdgpu_vmid_free_reserved(adev,AMDGPU_GFXHUB(0)); + vm->reserved_vmid[AMDGPU_GFXHUB(0)] = false; + } /* revert spm vmid with 0xf */ if (adev->gfx.rlc.funcs->update_spm_vmid) From e2891bda3bf9ce70228a19ac9b861d2d1e32d846 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 14 Jun 2023 19:21:19 +0800 Subject: [PATCH 1021/1868] Revert "Revert "drm/amdgpu: remove TOPDOWN flags when allocating VRAM" This reverts commit a56a0c9058b69133897ad4b54c1e76b2efc8fe5b. This patch causes a jira issue: SWDEV-405451 Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index c6d3ea93acdc1..6d9fd3d26a14e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -169,7 +169,7 @@ void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain) if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED) places[c].lpfn = min_not_zero(places[c].lpfn, visible_pfn); - else + else if (adev->gmc.real_vram_size != adev->gmc.visible_vram_size) places[c].flags |= TTM_PL_FLAG_TOPDOWN; if (abo->tbo.type == ttm_bo_type_kernel && From 27effc205c5e611fe40bc5dc04515ee350bdd123 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 19 Jun 2023 12:25:00 +0800 Subject: [PATCH 1022/1868] drm/amdkcl: wrap code under macro HAVE_PCI_DRIVER_DEV_GROUPS It's caused by 93ca881fcda746abc14b5c5794b456d4a9977977 "drm/amdgpu: Add vbios attribute only if supported" Signed-off-by: Bob Zhou Reviewed-by: Ma Jun --- drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h | 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 ++ 3 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c index 5e2dab49f52e7..4414b55605359 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c @@ -1808,7 +1808,6 @@ static struct attribute *amdgpu_vbios_version_attrs[] = { const struct attribute_group amdgpu_vbios_version_attr_group = { .attrs = amdgpu_vbios_version_attrs }; -#endif int amdgpu_atombios_sysfs_init(struct amdgpu_device *adev) { @@ -1818,6 +1817,7 @@ int amdgpu_atombios_sysfs_init(struct amdgpu_device *adev) return 0; } +#endif /** * amdgpu_atombios_fini - free the driver info and callbacks for atombios diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h index 0811474e8fd33..b2f13ad336af2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h @@ -214,6 +214,8 @@ int amdgpu_atombios_get_data_table(struct amdgpu_device *adev, void amdgpu_atombios_fini(struct amdgpu_device *adev); int amdgpu_atombios_init(struct amdgpu_device *adev); +#ifdef HAVE_PCI_DRIVER_DEV_GROUPS int amdgpu_atombios_sysfs_init(struct amdgpu_device *adev); +#endif #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index b9ae7f8d50d5c..8e8ad52b4a0e9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -4395,10 +4395,12 @@ int amdgpu_device_init(struct amdgpu_device *adev, * operations performed in `late_init` might affect the sysfs * interfaces creating. */ +#ifdef HAVE_PCI_DRIVER_DEV_GROUPS r = amdgpu_atombios_sysfs_init(adev); if (r) drm_err(&adev->ddev, "registering atombios sysfs failed (%d).\n", r); +#endif r = amdgpu_pm_sysfs_init(adev); if (r) From 2dbfd8d7dbbd80aa19c202b7bcfaadb006bbd106 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 19 Jun 2023 13:25:52 +0800 Subject: [PATCH 1023/1868] drm/amdkcl: wrap code under macro HAVE_DRM_DP_MST_TOPOLOGY_MGR_BASE It's caused by 4d291ee797a2d278d1af143e9d94b4deaecb930e "drm/amd/display: Add MST Preferred Link Setting Entry" Signed-off-by: Bob Zhou Reviewed-by: Ma Jun --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index 7f6e7e6679060..de241d886a483 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -338,6 +338,7 @@ static ssize_t dp_link_settings_write(struct file *f, const char __user *buf, return size; } +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_MGR_BASE static bool dp_mst_is_end_device(struct amdgpu_dm_connector *aconnector) { bool is_end_device = false; @@ -484,7 +485,7 @@ static ssize_t dp_mst_link_setting(struct file *f, const char __user *buf, kfree(wr_buf); return size; } - +#endif /* function: get current DP PHY settings: voltage swing, pre-emphasis, * post-cursor2 (defined by VESA DP specification) * @@ -2973,12 +2974,13 @@ static const struct file_operations dp_dsc_disable_passthrough_debugfs_fops = { .write = dp_dsc_passthrough_set, .llseek = default_llseek }; - +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_MGR_BASE static const struct file_operations dp_mst_link_settings_debugfs_fops = { .owner = THIS_MODULE, .write = dp_mst_link_setting, .llseek = default_llseek }; +#endif static const struct { char *name; @@ -3008,7 +3010,9 @@ static const struct { #endif {"mst_progress_status", &dp_mst_progress_status_fops}, {"is_dpia_link", &is_dpia_link_fops}, +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_MGR_BASE {"mst_link_settings", &dp_mst_link_settings_debugfs_fops} +#endif }; static const struct { From c799d56cf1ccaf56a8f598f74d2f8bec09c8aced Mon Sep 17 00:00:00 2001 From: Mukul Joshi Date: Mon, 17 Apr 2023 18:52:54 -0400 Subject: [PATCH 1024/1868] drm/ttm: Update TTM memory limit for GFX9.4.3 APU This patch sets the TTM memory limit to be 3/4th of system memory for GFX 9.4.3 APU. This patch is only intended for DKMS branch. Signed-off-by: Mukul Joshi Reviewed-by: Felix Kuehling --- drivers/gpu/drm/ttm/ttm_device.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/gpu/drm/ttm/ttm_device.c b/drivers/gpu/drm/ttm/ttm_device.c index a6dafce0aafc5..c23005e14555d 100644 --- a/drivers/gpu/drm/ttm/ttm_device.c +++ b/drivers/gpu/drm/ttm/ttm_device.c @@ -77,6 +77,9 @@ static int ttm_global_init(void) { struct ttm_global *glob = &ttm_glob; unsigned long num_pages, num_dma32; +#if IS_ENABLED(CONFIG_X86) + struct cpuinfo_x86 *c = &cpu_data(0); +#endif struct sysinfo si; int ret = 0; @@ -95,7 +98,17 @@ static int ttm_global_init(void) * system memory. */ num_pages = ((u64)si.totalram * si.mem_unit) >> PAGE_SHIFT; +#if IS_ENABLED(CONFIG_X86) + /* For GFX 9.4.3 APU, set mem limit to be 3/4th of + * system memory. + */ + if (c->x86 == 0x19 && c->x86_model == 0x90) + num_pages = (num_pages * 3) / 4; + else + num_pages /= 2; +#else num_pages /= 2; +#endif /* But for DMA32 we limit ourself to only use 2GiB maximum. */ num_dma32 = (u64)(si.totalram - si.totalhigh) * si.mem_unit From 83e946f0359d92c5f2cacc65026cd25f2f22f9bd Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 16 Jun 2023 10:48:18 +0800 Subject: [PATCH 1025/1868] drm/amdkcl: test whether drm_connector_state->colorspace is available It's caused by 95f27fa77de8dbc1e277af8dbb7d6f8640f650d1 "drm/amd/display: Send correct DP colorspace infopacket" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 46 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 ++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../amd/dkms/m4/struct_drm_connector_state.m4 | 21 +++++++++ 4 files changed, 71 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/struct_drm_connector_state.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index aa257beebe764..f12fe927fc52e 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -5908,6 +5908,7 @@ get_aspect_ratio(const struct drm_display_mode *mode_in) return (enum dc_aspect_ratio) mode_in->picture_aspect_ratio; } +#ifdef HAVE_DRM_CONNECTOR_STATE_COLORSPACE static enum dc_color_space get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing, const struct drm_connector_state *connector_state) @@ -5964,6 +5965,51 @@ get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing, return color_space; } +#else +static enum dc_color_space +get_output_color_space(const struct dc_crtc_timing *dc_crtc_timing, + const struct drm_connector_state *connector_state) +{ + enum dc_color_space color_space = COLOR_SPACE_SRGB; + + switch (dc_crtc_timing->pixel_encoding) { + case PIXEL_ENCODING_YCBCR422: + case PIXEL_ENCODING_YCBCR444: + case PIXEL_ENCODING_YCBCR420: + { + /* + * 27030khz is the separation point between HDTV and SDTV + * according to HDMI spec, we use YCbCr709 and YCbCr601 + * respectively + */ + if (dc_crtc_timing->pix_clk_100hz > 270300) { + if (dc_crtc_timing->flags.Y_ONLY) + color_space = + COLOR_SPACE_YCBCR709_LIMITED; + else + color_space = COLOR_SPACE_YCBCR709; + } else { + if (dc_crtc_timing->flags.Y_ONLY) + color_space = + COLOR_SPACE_YCBCR601_LIMITED; + else + color_space = COLOR_SPACE_YCBCR601; + } + + } + break; + case PIXEL_ENCODING_RGB: + color_space = COLOR_SPACE_SRGB; + break; + + default: + WARN_ON(1); + break; + } + + return color_space; +} +#endif static enum display_content_type get_output_content_type(const struct drm_connector_state *connector_state) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 4cc4547ffd552..8e6a35d87d64a 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -476,6 +476,9 @@ /* drm_mode_create_dp_colorspace_property() has 2 args */ #define HAVE_DRM_MODE_CREATE_DP_COLORSPACE_PROPERTY_2ARGS 1 +/* drm_connector_state->colorspace is available */ +#define HAVE_DRM_CONNECTOR_STATE_COLORSPACE 1 + /* struct drm_dsc_config has member simple_422 */ #define HAVE_DRM_DSC_CONFIG_SIMPLE_422 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 352bbb7a5746c..d8c113ad31917 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -105,6 +105,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION AC_AMDGPU_DRM_MODE_CREATE_COLORSPACE_PROPERTY_FUNCS + AC_AMDGPU_STRUCT_DRM_CONNECTOR_STATE AC_AMDGPU_JIFFIES64_TO_MSECS AC_AMDGPU_ACPI_PUT_TABLE AC_AMDGPU_ACPI_DEV_GET_FIRST_MATCH_DEV diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_connector_state.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_connector_state.m4 new file mode 100644 index 0000000000000..845426d6fe7bf --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_connector_state.m4 @@ -0,0 +1,21 @@ +dnl # +dnl # commit v5.0-rc7-1020-gd2c6a405846c +dnl # drm: Add HDMI colorspace property +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_STATE_COLORSPACE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_connector_state *connector_state = NULL; + connector_state->colorspace = 0; + ],[ + AC_DEFINE(HAVE_DRM_CONNECTOR_STATE_COLORSPACE, 1, + [drm_connector_state->colorspace is available]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CONNECTOR_STATE], [ + AC_AMDGPU_DRM_CONNECTOR_STATE_COLORSPACE +]) \ No newline at end of file From 8f5ee22c7582f4c420f06ad996f3610b6a41da9a Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Tue, 20 Jun 2023 14:42:14 +0800 Subject: [PATCH 1026/1868] drm/amdkcl: Optimize the vma init function Rename the vma init funciton and initialize the vma manager only if the vam space less than 16T Signed-off-by: Ma Jun Reviewed-by: Flora Cui Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++- .../kcl/backport/kcl_drm_vma_manager_backport.h | 15 ++++++++++++--- 2 files changed, 14 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index beaf92c30c8a0..205f568c849f5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2328,7 +2328,8 @@ static int amdgpu_pci_probe(struct pci_dev *pdev, adev->pdev = pdev; ddev = adev_to_drm(adev); - kcl_drm_vma_offset_manager_init(ddev->vma_offset_manager); + /* Check and increase the vma range */ + kcl_drm_vma_offset_manager_adjust(ddev->vma_offset_manager); if (!supports_atomic) ddev->driver_features &= ~DRIVER_ATOMIC; diff --git a/include/kcl/backport/kcl_drm_vma_manager_backport.h b/include/kcl/backport/kcl_drm_vma_manager_backport.h index 9893688f6fac2..b7b16df2f6d2c 100644 --- a/include/kcl/backport/kcl_drm_vma_manager_backport.h +++ b/include/kcl/backport/kcl_drm_vma_manager_backport.h @@ -42,16 +42,25 @@ #define DRM_FILE_PAGE_OFFSET_SIZE ((0xFFFFFFFFULL >> PAGE_SHIFT) * 4096) static inline void -kcl_drm_vma_offset_manager_init(struct drm_vma_offset_manager *mgr) +kcl_drm_vma_offset_manager_adjust(struct drm_vma_offset_manager *mgr) { - drm_vma_offset_manager_destroy(mgr); + u64 size; + + BUG_ON(!mgr); + + size = mgr->vm_addr_space_mm.head_node.hole_size; + if (size < DRM_FILE_PAGE_OFFSET_SIZE) + drm_vma_offset_manager_destroy(mgr); + else + return; + drm_vma_offset_manager_init(mgr, DRM_FILE_PAGE_OFFSET_START, DRM_FILE_PAGE_OFFSET_SIZE); } #else static inline void -kcl_drm_vma_offset_manager_init(struct drm_vma_offset_manager *mgr) +kcl_drm_vma_offset_manager_adjust(struct drm_vma_offset_manager *mgr) { } #endif From 2bf15cc236ceed914523bcec8dd18cfb7c02d30d Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 17 Jul 2023 16:22:47 +0800 Subject: [PATCH 1027/1868] drm/amdkcl: fake suballoc* It's caused by 849ee8a2f0df7a4ed4d281e19d3c9824b8e60bc2 drm/suballoc: Extract amdgpu_sa.c as generic suballocation helper Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_drm_suballoc.c | 461 ++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + .../include/kcl/kcl_amdgpu_drm_fb_helper.h | 1 + drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 5 + drivers/gpu/drm/amd/dkms/m4/drm_suballoc.m4 | 17 + drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/header/drm/drm_suballoc.h | 10 + include/kcl/kcl_drm_suballoc.h | 113 +++++ 9 files changed, 610 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_suballoc.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_suballoc.m4 create mode 100644 include/kcl/header/drm/drm_suballoc.h create mode 100644 include/kcl/kcl_drm_suballoc.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 08b2e37192c57..f8e0cdb1dd258 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -14,7 +14,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_fs_read_write.o kcl_drm_aperture.o \ kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o \ kcl_mce_amd.o kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o kcl_mm_slab.o \ - kcl_irqdesc.o + kcl_irqdesc.o kcl_drm_suballoc.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_suballoc.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_suballoc.c new file mode 100644 index 0000000000000..8ad6e3d9b60eb --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_suballoc.c @@ -0,0 +1,461 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright 2011 Red Hat Inc. + * Copyright 2023 Intel Corporation. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE + * USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + */ +/* Algorithm: + * + * We store the last allocated bo in "hole", we always try to allocate + * after the last allocated bo. Principle is that in a linear GPU ring + * progression was is after last is the oldest bo we allocated and thus + * the first one that should no longer be in use by the GPU. + * + * If it's not the case we skip over the bo after last to the closest + * done bo if such one exist. If none exist and we are not asked to + * block we report failure to allocate. + * + * If we are asked to block we wait on all the oldest fence of all + * rings. We just wait for any of those fence to complete. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#ifndef HAVE_DRM_SUBALLOC_MANAGER_INIT +static void drm_suballoc_remove_locked(struct drm_suballoc *sa); +static void drm_suballoc_try_free(struct drm_suballoc_manager *sa_manager); + +/** + * drm_suballoc_manager_init() - Initialise the drm_suballoc_manager + * @sa_manager: pointer to the sa_manager + * @size: number of bytes we want to suballocate + * @align: alignment for each suballocated chunk + * + * Prepares the suballocation manager for suballocations. + */ +void drm_suballoc_manager_init(struct drm_suballoc_manager *sa_manager, + size_t size, size_t align) +{ + unsigned int i; + + BUILD_BUG_ON(!is_power_of_2(DRM_SUBALLOC_MAX_QUEUES)); + + if (!align) + align = 1; + + /* alignment must be a power of 2 */ + if (WARN_ON_ONCE(align & (align - 1))) + align = roundup_pow_of_two(align); + + init_waitqueue_head(&sa_manager->wq); + sa_manager->size = size; + sa_manager->align = align; + sa_manager->hole = &sa_manager->olist; + INIT_LIST_HEAD(&sa_manager->olist); + for (i = 0; i < DRM_SUBALLOC_MAX_QUEUES; ++i) + INIT_LIST_HEAD(&sa_manager->flist[i]); +} +EXPORT_SYMBOL(drm_suballoc_manager_init); + +/** + * drm_suballoc_manager_fini() - Destroy the drm_suballoc_manager + * @sa_manager: pointer to the sa_manager + * + * Cleans up the suballocation manager after use. All fences added + * with drm_suballoc_free() must be signaled, or we cannot clean up + * the entire manager. + */ +void drm_suballoc_manager_fini(struct drm_suballoc_manager *sa_manager) +{ + struct drm_suballoc *sa, *tmp; + + if (!sa_manager->size) + return; + + if (!list_empty(&sa_manager->olist)) { + sa_manager->hole = &sa_manager->olist; + drm_suballoc_try_free(sa_manager); + if (!list_empty(&sa_manager->olist)) + DRM_ERROR("sa_manager is not empty, clearing anyway\n"); + } + list_for_each_entry_safe(sa, tmp, &sa_manager->olist, olist) { + drm_suballoc_remove_locked(sa); + } + + sa_manager->size = 0; +} +EXPORT_SYMBOL(drm_suballoc_manager_fini); + +static void drm_suballoc_remove_locked(struct drm_suballoc *sa) +{ + struct drm_suballoc_manager *sa_manager = sa->manager; + + if (sa_manager->hole == &sa->olist) + sa_manager->hole = sa->olist.prev; + + list_del_init(&sa->olist); + list_del_init(&sa->flist); + dma_fence_put(sa->fence); + kfree(sa); +} + +static void drm_suballoc_try_free(struct drm_suballoc_manager *sa_manager) +{ + struct drm_suballoc *sa, *tmp; + + if (sa_manager->hole->next == &sa_manager->olist) + return; + + sa = list_entry(sa_manager->hole->next, struct drm_suballoc, olist); + list_for_each_entry_safe_from(sa, tmp, &sa_manager->olist, olist) { + if (!sa->fence || !dma_fence_is_signaled(sa->fence)) + return; + + drm_suballoc_remove_locked(sa); + } +} + +static size_t drm_suballoc_hole_soffset(struct drm_suballoc_manager *sa_manager) +{ + struct list_head *hole = sa_manager->hole; + + if (hole != &sa_manager->olist) + return list_entry(hole, struct drm_suballoc, olist)->eoffset; + + return 0; +} + +static size_t drm_suballoc_hole_eoffset(struct drm_suballoc_manager *sa_manager) +{ + struct list_head *hole = sa_manager->hole; + + if (hole->next != &sa_manager->olist) + return list_entry(hole->next, struct drm_suballoc, olist)->soffset; + return sa_manager->size; +} + +static bool drm_suballoc_try_alloc(struct drm_suballoc_manager *sa_manager, + struct drm_suballoc *sa, + size_t size, size_t align) +{ + size_t soffset, eoffset, wasted; + + soffset = drm_suballoc_hole_soffset(sa_manager); + eoffset = drm_suballoc_hole_eoffset(sa_manager); + wasted = round_up(soffset, align) - soffset; + + if ((eoffset - soffset) >= (size + wasted)) { + soffset += wasted; + + sa->manager = sa_manager; + sa->soffset = soffset; + sa->eoffset = soffset + size; + list_add(&sa->olist, sa_manager->hole); + INIT_LIST_HEAD(&sa->flist); + sa_manager->hole = &sa->olist; + return true; + } + return false; +} + +static bool __drm_suballoc_event(struct drm_suballoc_manager *sa_manager, + size_t size, size_t align) +{ + size_t soffset, eoffset, wasted; + unsigned int i; + + for (i = 0; i < DRM_SUBALLOC_MAX_QUEUES; ++i) + if (!list_empty(&sa_manager->flist[i])) + return true; + + soffset = drm_suballoc_hole_soffset(sa_manager); + eoffset = drm_suballoc_hole_eoffset(sa_manager); + wasted = round_up(soffset, align) - soffset; + + return ((eoffset - soffset) >= (size + wasted)); +} + +/** + * drm_suballoc_event() - Check if we can stop waiting + * @sa_manager: pointer to the sa_manager + * @size: number of bytes we want to allocate + * @align: alignment we need to match + * + * Return: true if either there is a fence we can wait for or + * enough free memory to satisfy the allocation directly. + * false otherwise. + */ +static bool drm_suballoc_event(struct drm_suballoc_manager *sa_manager, + size_t size, size_t align) +{ + bool ret; + + spin_lock(&sa_manager->wq.lock); + ret = __drm_suballoc_event(sa_manager, size, align); + spin_unlock(&sa_manager->wq.lock); + return ret; +} + +static bool drm_suballoc_next_hole(struct drm_suballoc_manager *sa_manager, + struct dma_fence **fences, + unsigned int *tries) +{ + struct drm_suballoc *best_bo = NULL; + unsigned int i, best_idx; + size_t soffset, best, tmp; + + /* if hole points to the end of the buffer */ + if (sa_manager->hole->next == &sa_manager->olist) { + /* try again with its beginning */ + sa_manager->hole = &sa_manager->olist; + return true; + } + + soffset = drm_suballoc_hole_soffset(sa_manager); + /* to handle wrap around we add sa_manager->size */ + best = sa_manager->size * 2; + /* go over all fence list and try to find the closest sa + * of the current last + */ + for (i = 0; i < DRM_SUBALLOC_MAX_QUEUES; ++i) { + struct drm_suballoc *sa; + + fences[i] = NULL; + + if (list_empty(&sa_manager->flist[i])) + continue; + + sa = list_first_entry(&sa_manager->flist[i], + struct drm_suballoc, flist); + + if (!dma_fence_is_signaled(sa->fence)) { + fences[i] = sa->fence; + continue; + } + + /* limit the number of tries each freelist gets */ + if (tries[i] > 2) + continue; + + tmp = sa->soffset; + if (tmp < soffset) { + /* wrap around, pretend it's after */ + tmp += sa_manager->size; + } + tmp -= soffset; + if (tmp < best) { + /* this sa bo is the closest one */ + best = tmp; + best_idx = i; + best_bo = sa; + } + } + + if (best_bo) { + ++tries[best_idx]; + sa_manager->hole = best_bo->olist.prev; + + /* + * We know that this one is signaled, + * so it's safe to remove it. + */ + drm_suballoc_remove_locked(best_bo); + return true; + } + return false; +} + +/** + * drm_suballoc_new() - Make a suballocation. + * @sa_manager: pointer to the sa_manager + * @size: number of bytes we want to suballocate. + * @gfp: gfp flags used for memory allocation. Typically GFP_KERNEL but + * the argument is provided for suballocations from reclaim context or + * where the caller wants to avoid pipelining rather than wait for + * reclaim. + * @intr: Whether to perform waits interruptible. This should typically + * always be true, unless the caller needs to propagate a + * non-interruptible context from above layers. + * @align: Alignment. Must not exceed the default manager alignment. + * If @align is zero, then the manager alignment is used. + * + * Try to make a suballocation of size @size, which will be rounded + * up to the alignment specified in specified in drm_suballoc_manager_init(). + * + * Return: a new suballocated bo, or an ERR_PTR. + */ +struct drm_suballoc * +drm_suballoc_new(struct drm_suballoc_manager *sa_manager, size_t size, + gfp_t gfp, bool intr, size_t align) +{ + struct dma_fence *fences[DRM_SUBALLOC_MAX_QUEUES]; + unsigned int tries[DRM_SUBALLOC_MAX_QUEUES]; + unsigned int count; + int i, r; + struct drm_suballoc *sa; + + if (WARN_ON_ONCE(align > sa_manager->align)) + return ERR_PTR(-EINVAL); + if (WARN_ON_ONCE(size > sa_manager->size || !size)) + return ERR_PTR(-EINVAL); + + if (!align) + align = sa_manager->align; + + sa = kmalloc(sizeof(*sa), gfp); + if (!sa) + return ERR_PTR(-ENOMEM); + sa->manager = sa_manager; + sa->fence = NULL; + INIT_LIST_HEAD(&sa->olist); + INIT_LIST_HEAD(&sa->flist); + + spin_lock(&sa_manager->wq.lock); + do { + for (i = 0; i < DRM_SUBALLOC_MAX_QUEUES; ++i) + tries[i] = 0; + + do { + drm_suballoc_try_free(sa_manager); + + if (drm_suballoc_try_alloc(sa_manager, sa, + size, align)) { + spin_unlock(&sa_manager->wq.lock); + return sa; + } + + /* see if we can skip over some allocations */ + } while (drm_suballoc_next_hole(sa_manager, fences, tries)); + + for (i = 0, count = 0; i < DRM_SUBALLOC_MAX_QUEUES; ++i) + if (fences[i]) + fences[count++] = dma_fence_get(fences[i]); + + if (count) { + long t; + + spin_unlock(&sa_manager->wq.lock); + t = dma_fence_wait_any_timeout(fences, count, intr, + MAX_SCHEDULE_TIMEOUT, + NULL); + for (i = 0; i < count; ++i) + dma_fence_put(fences[i]); + + r = (t > 0) ? 0 : t; + spin_lock(&sa_manager->wq.lock); + } else if (intr) { + /* if we have nothing to wait for block */ + r = wait_event_interruptible_locked + (sa_manager->wq, + __drm_suballoc_event(sa_manager, size, align)); + } else { + spin_unlock(&sa_manager->wq.lock); + wait_event(sa_manager->wq, + drm_suballoc_event(sa_manager, size, align)); + r = 0; + spin_lock(&sa_manager->wq.lock); + } + } while (!r); + + spin_unlock(&sa_manager->wq.lock); + kfree(sa); + return ERR_PTR(r); +} +EXPORT_SYMBOL(drm_suballoc_new); + +/** + * drm_suballoc_free - Free a suballocation + * @suballoc: pointer to the suballocation + * @fence: fence that signals when suballocation is idle + * + * Free the suballocation. The suballocation can be re-used after @fence signals. + */ +void drm_suballoc_free(struct drm_suballoc *suballoc, + struct dma_fence *fence) +{ + struct drm_suballoc_manager *sa_manager; + + if (!suballoc) + return; + + sa_manager = suballoc->manager; + + spin_lock(&sa_manager->wq.lock); + if (fence && !dma_fence_is_signaled(fence)) { + u32 idx; + + suballoc->fence = dma_fence_get(fence); + idx = fence->context & (DRM_SUBALLOC_MAX_QUEUES - 1); + list_add_tail(&suballoc->flist, &sa_manager->flist[idx]); + } else { + drm_suballoc_remove_locked(suballoc); + } + wake_up_all_locked(&sa_manager->wq); + spin_unlock(&sa_manager->wq.lock); +} +EXPORT_SYMBOL(drm_suballoc_free); + +#ifdef CONFIG_DEBUG_FS +void drm_suballoc_dump_debug_info(struct drm_suballoc_manager *sa_manager, + struct drm_printer *p, + unsigned long long suballoc_base) +{ + struct drm_suballoc *i; + + spin_lock(&sa_manager->wq.lock); + list_for_each_entry(i, &sa_manager->olist, olist) { + unsigned long long soffset = i->soffset; + unsigned long long eoffset = i->eoffset; + + if (&i->olist == sa_manager->hole) + drm_puts(p, ">"); + else + drm_puts(p, " "); + + drm_printf(p, "[0x%010llx 0x%010llx] size %8lld", + suballoc_base + soffset, suballoc_base + eoffset, + eoffset - soffset); + + if (i->fence) + drm_printf(p, " protected by 0x%016llx on context %llu", + (unsigned long long)i->fence->seqno, + (unsigned long long)i->fence->context); + + drm_puts(p, "\n"); + } + spin_unlock(&sa_manager->wq.lock); +} +EXPORT_SYMBOL(drm_suballoc_dump_debug_info); +#endif +MODULE_AUTHOR("Multiple"); +MODULE_DESCRIPTION("Range suballocator helper"); +MODULE_LICENSE("Dual MIT/GPL"); +#endif /*HAVE_DRM_SUBALLOC_MANAGER_INIT*/ diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index e69fb1878b8b7..2a284365ba73c 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -109,4 +109,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h index b67bfda700d77..5abb5cf97824c 100644 --- a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h @@ -32,6 +32,7 @@ #include #include +#include #include "amdgpu.h" #ifndef HAVE_DRM_FB_HELPER_LASTCLOSE diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index a88e31ef833a7..642993ebcc9cb 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -87,4 +87,9 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # AC_KERNEL_CHECK_HEADERS([drm/drm_fbdev_generic.h]) + dnl # + dnl # v6.2-rc6-1265-g849ee8a2f0df + dnl # drm/suballoc: Extract amdgpu_sa.c as generic suballocation helper + dnl # + AC_KERNEL_CHECK_HEADERS([drm/drm_suballoc.h]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_suballoc.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_suballoc.m4 new file mode 100644 index 0000000000000..bcb026ad2c36d --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_suballoc.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v6.2-rc6-1265-g849ee8a2f0df +dnl # drm/suballoc: Extract amdgpu_sa.c as generic suballocation helper +dnl # +AC_DEFUN([AC_AMDGPU_DRM_SUBALLOC_MANAGER_INIT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_suballoc_manager_init(NULL, 0, 0); + ], [ + AC_DEFINE(HAVE_DRM_SUBALLOC_MANAGER_INIT, 1, + [Has function drm_suballoc_manager_init()]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index d8c113ad31917..9eaeac070adc3 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -200,6 +200,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_APPLE_GMUX_DETECT AC_AMDGPU_MM_KMALLOC_SIZE_ROUNDUP AC_AMDGPU_ZONE_DEVICE_PAGE_INIT + AC_AMDGPU_DRM_SUBALLOC_MANAGER_INIT AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/header/drm/drm_suballoc.h b/include/kcl/header/drm/drm_suballoc.h new file mode 100644 index 0000000000000..3eca4a8774ac4 --- /dev/null +++ b/include/kcl/header/drm/drm_suballoc.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DRM_SUBALLOC_H_H_ +#define _KCL_HEADER_DRM_SUBALLOC_H_H_ + +#ifdef HAVE_DRM_DRM_SUBALLOC_H +#include_next +#endif + +#endif + diff --git a/include/kcl/kcl_drm_suballoc.h b/include/kcl/kcl_drm_suballoc.h new file mode 100644 index 0000000000000..46c61883e392f --- /dev/null +++ b/include/kcl/kcl_drm_suballoc.h @@ -0,0 +1,113 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* + * Copyright 2011 Red Hat Inc. + * Copyright © 2022 Intel Corporation + */ +#ifndef _KCL_DRM_SUBALLOC_H_ +#define _KCL_DRM_SUBALLOC_H_ + +#include + +#ifndef HAVE_DRM_DRM_SUBALLOC_H + +#include + +#include +#include + +#define DRM_SUBALLOC_MAX_QUEUES 32 +/** + * struct drm_suballoc_manager - fenced range allocations + * @wq: Wait queue for sleeping allocations on contention. + * @hole: Pointer to first hole node. + * @olist: List of allocated ranges. + * @flist: Array[fence context hash] of queues of fenced allocated ranges. + * @size: Size of the managed range. + * @align: Default alignment for the managed range. + */ +struct drm_suballoc_manager { + wait_queue_head_t wq; + struct list_head *hole; + struct list_head olist; + struct list_head flist[DRM_SUBALLOC_MAX_QUEUES]; + size_t size; + size_t align; +}; + +/** + * struct drm_suballoc - Sub-allocated range + * @olist: List link for list of allocated ranges. + * @flist: List linkk for the manager fenced allocated ranges queues. + * @manager: The drm_suballoc_manager. + * @soffset: Start offset. + * @eoffset: End offset + 1 so that @eoffset - @soffset = size. + * @dma_fence: The fence protecting the allocation. + */ +struct drm_suballoc { + struct list_head olist; + struct list_head flist; + struct drm_suballoc_manager *manager; + size_t soffset; + size_t eoffset; + struct dma_fence *fence; +}; + +void drm_suballoc_manager_init(struct drm_suballoc_manager *sa_manager, + size_t size, size_t align); + +void drm_suballoc_manager_fini(struct drm_suballoc_manager *sa_manager); + +struct drm_suballoc * +drm_suballoc_new(struct drm_suballoc_manager *sa_manager, size_t size, + gfp_t gfp, bool intr, size_t align); + +void drm_suballoc_free(struct drm_suballoc *sa, struct dma_fence *fence); + +/** + * drm_suballoc_soffset - Range start. + * @sa: The struct drm_suballoc. + * + * Return: The start of the allocated range. + */ +static inline size_t drm_suballoc_soffset(struct drm_suballoc *sa) +{ + return sa->soffset; +} + +/** + * drm_suballoc_eoffset - Range end. + * @sa: The struct drm_suballoc. + * + * Return: The end of the allocated range + 1. + */ +static inline size_t drm_suballoc_eoffset(struct drm_suballoc *sa) +{ + return sa->eoffset; +} + +/** + * drm_suballoc_size - Range size. + * @sa: The struct drm_suballoc. + * + * Return: The size of the allocated range. + */ +static inline size_t drm_suballoc_size(struct drm_suballoc *sa) +{ + return sa->eoffset - sa->soffset; +} + +#ifdef CONFIG_DEBUG_FS +void drm_suballoc_dump_debug_info(struct drm_suballoc_manager *sa_manager, + struct drm_printer *p, + unsigned long long suballoc_base); +#else +static inline void +drm_suballoc_dump_debug_info(struct drm_suballoc_manager *sa_manager, + struct drm_printer *p, + unsigned long long suballoc_base) +{ } + +#endif +#endif /*HAVE_DRM_DRM_SUBALLOC_H*/ + +#endif /* _KCL_DRM_SUBALLOC_H_ */ From 32e66ca108b7b1793f9bb768e2f5ca80b4cf891c Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 17 Jul 2023 17:32:49 +0800 Subject: [PATCH 1028/1868] drm/amdkcl: drop include path include/kcl/header/uapi in dkms Makefile The file include/kcl/header/uapi has been clean up, so remove it from include path of dkms package. Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/Makefile | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 39facc822b351..a73a7f7227df2 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -161,7 +161,6 @@ LINUXINCLUDE := \ -include $(src)/amd/dkms/config/config.h \ $(LINUX_SRCTREE_INCLUDE) \ -I$(src)/include/uapi \ - -I$(src)/include/kcl/header/uapi \ $(USER_INCLUDE) export CONFIG_HSA_AMD=y From 69387bf70f1bf9a35323e27257e9d0a55643aca3 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 17 Jul 2023 18:14:23 +0800 Subject: [PATCH 1029/1868] drm/amdkcl: fake vm_flags_{set, clear} It's caused by v6.2-rc4-446-gbc292ab00f6c mm: introduce vma->vm_flags wrapper functions Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 ++ .../amd/dkms/m4/mmap_assert_write_locked.m4 | 17 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/vma-lookup.m4 | 18 +++++++++++++++++ include/kcl/kcl_mm.h | 20 +++++++++++++++++++ 4 files changed, 57 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/mmap_assert_write_locked.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 9eaeac070adc3..f0d4fef367451 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -201,6 +201,8 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_MM_KMALLOC_SIZE_ROUNDUP AC_AMDGPU_ZONE_DEVICE_PAGE_INIT AC_AMDGPU_DRM_SUBALLOC_MANAGER_INIT + AC_AMDGPU_VM_FLAGS_SET + AC_AMDGPU_MMAP_ASSERT_WRITE_LOCKED AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/mmap_assert_write_locked.m4 b/drivers/gpu/drm/amd/dkms/m4/mmap_assert_write_locked.m4 new file mode 100644 index 0000000000000..e79d2af6625ec --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/mmap_assert_write_locked.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit 7dea19f9ee636cb244109a4dba426bbb3e5304b7 +dnl # mm: introduce memalloc_nofs_{save,restore} API +dnl # +AC_DEFUN([AC_AMDGPU_MMAP_ASSERT_WRITE_LOCKED], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + mmap_assert_write_locked(NULL); + ], [ + AC_DEFINE(HAVE_MMAP_ASSERT_WRITE_LOCKED, 1, + [mmap_assert_write_locked() is available]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/vma-lookup.m4 b/drivers/gpu/drm/amd/dkms/m4/vma-lookup.m4 index 1eb0129ff303c..74cd3b8edd7ce 100644 --- a/drivers/gpu/drm/amd/dkms/m4/vma-lookup.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/vma-lookup.m4 @@ -14,3 +14,21 @@ AC_DEFUN([AC_AMDGPU_VMA_LOOKUP], [ ]) ]) ]) + +dnl # +dnl # v6.2-rc4-446-gbc292ab00f6c +dnl # mm: introduce vma->vm_flags wrapper functions +dnl # +AC_DEFUN([AC_AMDGPU_VM_FLAGS_SET], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + vm_flags_set(NULL, 0); + vm_flags_clear(NULL, 0); + ], [ + AC_DEFINE(HAVE_VM_FLAGS_SET, 1, + [vm_flags_{set, clear} is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_mm.h b/include/kcl/kcl_mm.h index a230fc776153a..9d6df88ddf9fb 100644 --- a/include/kcl/kcl_mm.h +++ b/include/kcl/kcl_mm.h @@ -100,4 +100,24 @@ struct vm_area_struct *vma_lookup(struct mm_struct *mm, unsigned long addr) #define page_to_virt(x) __va(PFN_PHYS(page_to_pfn(x))) #endif +#ifndef HAVE_VM_FLAGS_SET +static inline void vm_flags_set(struct vm_area_struct *vma, + vm_flags_t flags) +{ +#ifdef HAVE_MMAP_ASSERT_WRITE_LOCKED + mmap_assert_write_locked(vma->vm_mm); +#endif + vma->vm_flags |= flags; +} + +static inline void vm_flags_clear(struct vm_area_struct *vma, + vm_flags_t flags) +{ +#ifdef HAVE_MMAP_ASSERT_WRITE_LOCKED + mmap_assert_write_locked(vma->vm_mm); +#endif + vma->vm_flags &= ~flags; +} +#endif + #endif /* AMDKCL_MM_H */ From 66c08a4d9df7d201f3b4c3d8f20946d11a7b1fef Mon Sep 17 00:00:00 2001 From: Jonathan Kim Date: Mon, 12 Jun 2023 12:05:28 -0400 Subject: [PATCH 1030/1868] drm/amdkfd: remove old debugger Remove the old debugger to make way for the upstreamed debugger. Signed-off-by: Jonathan Kim --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 11 +++++++++++ include/uapi/linux/kfd_ioctl.h | 4 +++- 2 files changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 4d72611a491ce..cdc2f62b22076 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1739,6 +1739,14 @@ static int kfd_ioctl_export_dmabuf(struct file *filep, return ret; } +/* Place holder for deprecated DBG API */ +static int kfd_ioctl_dbg_set_debug_trap_deprecated(struct file *filep, + struct kfd_process *p, void *data) +{ + dev_dbg(kfd_device, "AMDKFD_IOC_DBG_TRAP is deprecated.\n"); + return -EINVAL; +} + /* Place holder for deprecated CMA API */ static int kfd_ioctl_cross_memory_copy_deprecated(struct file *filep, struct kfd_process *local_p, void *data) { @@ -3424,6 +3432,9 @@ static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = { AMDKFD_IOCTL_DEF(AMDKFD_IOC_IPC_EXPORT_HANDLE, kfd_ioctl_ipc_export_handle, 0), + AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_TRAP_DEPRECATED, + kfd_ioctl_dbg_set_debug_trap_deprecated, 0), + AMDKFD_IOCTL_DEF(AMDKFD_IOC_RLC_SPM, kfd_ioctl_rlc_spm, 0), diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h index 35a8850d12fa8..13950b2930d8c 100644 --- a/include/uapi/linux/kfd_ioctl.h +++ b/include/uapi/linux/kfd_ioctl.h @@ -242,7 +242,7 @@ struct kfd_ioctl_dbg_wave_control_args { #define KFD_INVALID_FD 0xffffffff -struct kfd_ioctl_dbg_trap_args { +struct kfd_ioctl_dbg_trap_args_deprecated { __u64 exception_mask; /* to KFD */ __u64 ptr; /* to KFD -- used for pointer arguments: queue arrays */ __u32 pid; /* to KFD */ @@ -1713,6 +1713,8 @@ struct kfd_ioctl_dbg_trap_args { #define AMDKFD_IOC_IPC_EXPORT_HANDLE \ AMDKFD_IOWR(0x81, struct kfd_ioctl_ipc_export_handle_args) +#define AMDKFD_IOC_DBG_TRAP_DEPRECATED \ + AMDKFD_IOWR(0x82, struct kfd_ioctl_dbg_trap_args_deprecated) #define AMDKFD_IOC_CROSS_MEMORY_COPY_DEPRECATED \ AMDKFD_IOWR(0x83, struct kfd_ioctl_cross_memory_copy_deprecated_args) From d85155912e7913502e8c370974f4a2af190825d0 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 18 Jul 2023 15:32:09 +0800 Subject: [PATCH 1031/1868] drm/amdkcl: test whether drm_dp_mst_hpd_irq_handle_event() is available It's caused by 55970ce5015265eb0985f518995aa8fc4b3fa384 "drm/dp_mst: Clear MSG_RDY flag before sending new message" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 24 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../m4/drm_dp_mst_hpd_irq_handle_event.m4 | 16 +++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 44 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_hpd_irq_handle_event.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 87b6b60d9d111..885c1cc0efc53 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -774,6 +774,7 @@ void dm_handle_mst_sideband_msg_ready_event( /* handle MST irq */ if (aconnector->mst_mgr.mst_state) +#ifdef HAVE_DRM_DP_MST_HPD_IRQ_HANDLE_EVENT drm_dp_mst_hpd_irq_handle_event(&aconnector->mst_mgr, esi, ack, @@ -797,6 +798,29 @@ void dm_handle_mst_sideband_msg_ready_event( } drm_dp_mst_hpd_irq_send_new_request(&aconnector->mst_mgr); +#else + drm_dp_mst_hpd_irq( + &aconnector->mst_mgr, + esi, + &new_irq_handled); + + if (new_irq_handled) { + /* ACK at DPCD to notify down stream */ + const int ack_dpcd_bytes_to_write = + dpcd_bytes_to_read - 1; + + for (retry = 0; retry < 3; retry++) { + u8 wret; + + wret = drm_dp_dpcd_write( + &aconnector->dm_dp_aux.aux, + dpcd_addr + 1, + &esi[1], + ack_dpcd_bytes_to_write); + if (wret == ack_dpcd_bytes_to_write) + break; + } +#endif new_irq_handled = false; } else { diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 8e6a35d87d64a..4564a73bc991b 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -371,6 +371,9 @@ /* drm_dp_mst_{get,put}_port_malloc() is available */ #define HAVE_DRM_DP_MST_GET_PUT_PORT_MALLOC 1 +/* drm_dp_mst_hpd_irq_handle_event() is available */ +#define HAVE_DRM_DP_MST_HPD_IRQ_HANDLE_EVENT 1 + /* drm_dp_mst_port struct has full_pbn member */ #define HAVE_DRM_DP_MST_PORT_FULL_PBN 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_hpd_irq_handle_event.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_hpd_irq_handle_event.m4 new file mode 100644 index 0000000000000..a70fd97681104 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_hpd_irq_handle_event.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v6.2-4472-g55970ce50152 +dnl # drm/dp_mst: Clear MSG_RDY flag before sending new message +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_HPD_IRQ_HANDLE_EVENT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_dp_mst_hpd_irq_handle_event(NULL, NULL, NULL, NULL); + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_HPD_IRQ_HANDLE_EVENT, 1, + [drm_dp_mst_hpd_irq_handle_event() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index f0d4fef367451..a1f94f0b0064e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -154,6 +154,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_STRUCT_KOBJ_TYPE AC_AMDGPU_MIGRATE_DISABLE AC_AMDGPU_CLOSE_FD + AC_AMDGPU_DRM_DP_MST_HPD_IRQ_HANDLE_EVENT AC_AMDGPU_DRM_VMA_OFFSET_NODE_READONLY_FIELD AC_AMDGPU_WW_MUTEX_TRYLOCK_CONTEXT_ARG AC_AMDGPU_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_DRM_DRIVER_ARG From 900583dec4df24d46f4246b14dd9c23426839e0d Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 18 Jul 2023 16:55:33 +0800 Subject: [PATCH 1032/1868] drm/amdkcl: test whether drm_dp_mst_topology_cbs->poll_hpd_irq is available It's caused by ed8496801ab71fdfb9c9fdcbef058aa20a549ebd "drm/amd/display: Add polling method to handle MST reply packet" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 4 ++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../amd/dkms/m4/drm-dp-mst-topology-cbs.m4 | 23 +++++++++++++++++++ 3 files changed, 30 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 885c1cc0efc53..40d6f94250b71 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -834,10 +834,12 @@ void dm_handle_mst_sideband_msg_ready_event( DRM_DEBUG_DRIVER("Loop exceeded max iterations\n"); } +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_CBS_POLL_HPD_IRQ static void dm_handle_mst_down_rep_msg_ready(struct drm_dp_mst_topology_mgr *mgr) { dm_handle_mst_sideband_msg_ready_event(mgr, DOWN_REP_MSG_RDY_EVENT); } +#endif #ifdef HAVE_DRM_DP_MST_TOPOLOGY_CBS_DESTROY_CONNECTOR static void dm_dp_destroy_mst_connector(struct drm_dp_mst_topology_mgr *mgr, @@ -898,7 +900,9 @@ static const struct drm_dp_mst_topology_cbs dm_mst_cbs = { #ifdef HAVE_DRM_DP_MST_TOPOLOGY_CBS_REGISTER_CONNECTOR .register_connector = dm_dp_mst_register_connector #endif +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_CBS_POLL_HPD_IRQ .poll_hpd_irq = dm_handle_mst_down_rep_msg_ready, +#endif }; void amdgpu_dm_initialize_dp_connector(struct amdgpu_display_manager *dm, diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 4564a73bc991b..e801fe62cc49b 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -389,6 +389,9 @@ /* struct drm_dp_mst_topology_cbs has hotplug member */ /* #undef HAVE_DRM_DP_MST_TOPOLOGY_CBS_HOTPLUG */ +/* struct drm_dp_mst_topology_cbs->poll_hpd_irq is available */ +#define HAVE_DRM_DP_MST_TOPOLOGY_CBS_POLL_HPD_IRQ 1 + /* struct drm_dp_mst_topology_cbs->register_connector is available */ /* #undef HAVE_DRM_DP_MST_TOPOLOGY_CBS_REGISTER_CONNECTOR */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 index 683d563cfc7bb..02dac4390e913 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 @@ -68,10 +68,33 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_DESTROY_CONNECTOR], [ ]) ]) +dnl # +dnl # commit v5.7-rc1-646-g471bdd0df0d5 +dnl # drm/i915/dp_mst: Work around out-of-spec adapters filtering short pulses +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_POLL_HPD_IRQ], [ + AC_KERNEL_TRY_COMPILE([ + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) + #include + #else + #include + #endif + ], [ + struct drm_dp_mst_topology_cbs *dp_mst_cbs = NULL; + dp_mst_cbs->poll_hpd_irq(NULL); + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_TOPOLOGY_CBS_POLL_HPD_IRQ, 1, + [struct drm_dp_mst_topology_cbs->poll_hpd_irq is available]) + ]) +]) + AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS], [ AC_KERNEL_DO_BACKGROUND([ AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_HOTPLUG AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_REGISTER_CONNECTOR AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_DESTROY_CONNECTOR + AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_POLL_HPD_IRQ ]) ]) From 4226ba4c99273cfbb97a70b53b668729cdb9bb36 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 21 Jul 2023 14:13:55 +0800 Subject: [PATCH 1033/1868] drm/amdkcl: check PIDTYPE_PID whether exits It's caused by 6883f81aac6f44e7df70a6af189b3689ff52cbfb pid: Implement PIDTYPE_TGID Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 7 ++++++- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/pid_type.m4 | 17 +++++++++++++++++ 3 files changed, 24 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/pid_type.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index 63bbe580e1f52..1e7c5d4c709f0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -1152,7 +1152,12 @@ static int amdgpu_debugfs_gem_info_show(struct seq_file *m, void *unused) */ rcu_read_lock(); pid = rcu_dereference(file->pid); - task = pid_task(pid, PIDTYPE_TGID); + task = pid_task(pid, +#ifdef HAVE_PIDTYPE_TGID + PIDTYPE_TGID); +#else + PIDTYPE_PID); +#endif seq_printf(m, "pid %8d command %s:\n", pid_nr(pid), task ? task->comm : ""); rcu_read_unlock(); diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index a1f94f0b0064e..d2be3b705ce5a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -204,6 +204,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_SUBALLOC_MANAGER_INIT AC_AMDGPU_VM_FLAGS_SET AC_AMDGPU_MMAP_ASSERT_WRITE_LOCKED + AC_AMDGPU_PID_TYPE AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/pid_type.m4 b/drivers/gpu/drm/amd/dkms/m4/pid_type.m4 new file mode 100644 index 0000000000000..da986da3833f3 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/pid_type.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # v4.18-rc1-6-g6883f81aac6f +dnl # pid: Implement PIDTYPE_TGID +dnl # +AC_DEFUN([AC_AMDGPU_PID_TYPE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + enum pid_type a; + a = PIDTYPE_TGID; + ], [ + AC_DEFINE(HAVE_PIDTYPE_TGID, 1, + [PIDTYPE is availablea]) + ]) + ]) +]) From fe75b6f780b0be4b2335ef8b2649a2d735996ba2 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 24 Jul 2023 14:40:22 +0800 Subject: [PATCH 1034/1868] drm/amdkcl: Test struct dma_fence_ops whether has set_deadline It's caused by v6.3-rc2-1-gaec11c8d7cb3 dma-buf/dma-fence: Add deadline awareness Signed-off-by: Asher Song --- drivers/dma-buf/dma-resv.c | 2 ++ drivers/gpu/drm/amd/dkms/m4/dma-fence-ops.m4 | 21 ++++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/scheduler/sched_fence.c | 11 +++++++++- 4 files changed, 34 insertions(+), 1 deletion(-) diff --git a/drivers/dma-buf/dma-resv.c b/drivers/dma-buf/dma-resv.c index 5f8d010516f07..0645c83e42b02 100644 --- a/drivers/dma-buf/dma-resv.c +++ b/drivers/dma-buf/dma-resv.c @@ -705,6 +705,7 @@ EXPORT_SYMBOL_GPL(dma_resv_wait_timeout); * May be called without holding the dma_resv lock. Sets @deadline on * all fences filtered by @usage. */ +#ifdef HAVE_DMA_FENCE_OPS_SET_DEADLINE void dma_resv_set_deadline(struct dma_resv *obj, enum dma_resv_usage usage, ktime_t deadline) { @@ -718,6 +719,7 @@ void dma_resv_set_deadline(struct dma_resv *obj, enum dma_resv_usage usage, dma_resv_iter_end(&cursor); } EXPORT_SYMBOL_GPL(dma_resv_set_deadline); +#endif /** * dma_resv_test_signaled - Test if a reservation object's fences have been diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-fence-ops.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-fence-ops.m4 index c10c92dfb503e..5fd3aeec58e80 100644 --- a/drivers/gpu/drm/amd/dkms/m4/dma-fence-ops.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/dma-fence-ops.m4 @@ -15,3 +15,24 @@ AC_DEFUN([AC_AMDGPU_DMA_FENCE_OPS_USE_64BIT_SEQNO], [ ]) ]) ]) + + +dnl # +dnl # v6.3-rc2-1-gaec11c8d7cb3 +dnl # dma-buf/dma-fence: Add deadline awareness +dnl # +AC_DEFUN([AC_AMDGPU_DMA_FENCE_OPS_SET_DEADLINE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + ktime_t deadline = 0; + struct dma_fence_ops *ops = NULL; + ops->set_deadline(NULL, deadline); + ], [ + AC_DEFINE(HAVE_DMA_FENCE_OPS_SET_DEADLINE, 1, + [struct dma_fence_ops has callback set_deadline]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index d2be3b705ce5a..198f416c881ad 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -205,6 +205,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_VM_FLAGS_SET AC_AMDGPU_MMAP_ASSERT_WRITE_LOCKED AC_AMDGPU_PID_TYPE + AC_AMDGPU_DMA_FENCE_OPS_SET_DEADLINE AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/scheduler/sched_fence.c b/drivers/gpu/drm/scheduler/sched_fence.c index 59aa91e73d733..7893cb8345a57 100644 --- a/drivers/gpu/drm/scheduler/sched_fence.c +++ b/drivers/gpu/drm/scheduler/sched_fence.c @@ -46,6 +46,7 @@ static void __exit drm_sched_fence_slab_fini(void) kmem_cache_destroy(sched_fence_slab); } +#ifdef HAVE_DMA_FENCE_OPS_SET_DEADLINE static void drm_sched_fence_set_parent(struct drm_sched_fence *s_fence, struct dma_fence *fence) { @@ -59,6 +60,7 @@ static void drm_sched_fence_set_parent(struct drm_sched_fence *s_fence, &s_fence->finished.flags)) dma_fence_set_deadline(fence, s_fence->deadline); } +#endif void drm_sched_fence_scheduled(struct drm_sched_fence *fence, struct dma_fence *parent) @@ -70,8 +72,11 @@ void drm_sched_fence_scheduled(struct drm_sched_fence *fence, * up. */ if (!IS_ERR_OR_NULL(parent)) +#ifdef HAVE_DMA_FENCE_OPS_SET_DEADLINE drm_sched_fence_set_parent(fence, parent); - +#else + fence->parent = dma_fence_get(parent); +#endif dma_fence_signal(&fence->scheduled); } @@ -147,6 +152,7 @@ static void drm_sched_fence_release_finished(struct dma_fence *f) dma_fence_put(&fence->scheduled); } +#ifdef HAVE_DMA_FENCE_OPS_SET_DEADLINE static void drm_sched_fence_set_deadline_finished(struct dma_fence *f, ktime_t deadline) { @@ -177,6 +183,7 @@ static void drm_sched_fence_set_deadline_finished(struct dma_fence *f, if (parent) dma_fence_set_deadline(parent, deadline); } +#endif static const struct dma_fence_ops drm_sched_fence_ops_scheduled = { .get_driver_name = drm_sched_fence_get_driver_name, @@ -192,7 +199,9 @@ static const struct dma_fence_ops drm_sched_fence_ops_finished = { AMDKCL_DMA_FENCE_OPS_ENABLE_SIGNALING_OPTIONAL AMDKCL_DMA_FENCE_OPS_WAIT_OPTIONAL .release = drm_sched_fence_release_finished, +#ifdef HAVE_DMA_FENCE_OPS_SET_DEADLINE .set_deadline = drm_sched_fence_set_deadline_finished, +#endif }; struct drm_sched_fence *to_drm_sched_fence(struct dma_fence *f) From b858071d90479cdfe647077873c48ccd048128f4 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 11 Oct 2023 16:57:45 +0800 Subject: [PATCH 1035/1868] drm/amdkcl: update config.h Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/config/config.h | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index e801fe62cc49b..e4cf2284f3c2a 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -127,6 +127,9 @@ /* dma_fence_is_container() is available */ #define HAVE_DMA_FENCE_IS_CONTAINER 1 +/* struct dma_fence_ops has callback set_deadline */ +#define HAVE_DMA_FENCE_OPS_SET_DEADLINE 1 + /* struct dma_fence_ops has use_64bit_seqno field */ #define HAVE_DMA_FENCE_OPS_USE_64BIT_SEQNO 1 @@ -458,6 +461,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_PROBE_HELPER_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_SUBALLOC_H 1 + /* drm_driver_feature DRIVER_IRQ_SHARED is available */ /* #undef HAVE_DRM_DRV_DRIVER_IRQ_SHARED */ @@ -616,6 +622,9 @@ /* drm_simple_encoder is available */ #define HAVE_DRM_SIMPLE_ENCODER_INIT 1 +/* Has function drm_suballoc_manager_init() */ +#define HAVE_DRM_SUBALLOC_MANAGER_INIT 1 + /* Define to 1 if you have the header file. */ #define HAVE_DRM_TASK_BARRIER_H 1 @@ -841,8 +850,8 @@ /* migrate_vma->pgmap_owner is available */ #define HAVE_MIGRATE_VMA_PGMAP_OWNER 1 -/* mmgrab() is available */ -#define HAVE_MMGRAB 1 +/* mmap_assert_write_locked() is available */ +#define HAVE_MMAP_ASSERT_WRITE_LOCKED 1 /* mmput_async() is available */ #define HAVE_MMPUT_ASYNC 1 @@ -898,6 +907,9 @@ /* vm_insert_mixed() wants pfn_t arg */ /* #undef HAVE_PFN_T_VM_INSERT_MIXED */ +/* PIDTYPE is availablea */ +#define HAVE_PIDTYPE_TGID 1 + /* pm_suspend_target_state is available */ #define HAVE_PM_SUSPEND_TARGET_STATE 1 @@ -1049,6 +1061,9 @@ /* vm_fault->{address/vam} is available */ #define HAVE_VM_FAULT_ADDRESS_VMA 1 +/* vm_flags_{set, clear} is available */ +#define HAVE_VM_FLAGS_SET 1 + /* vm_insert_pfn_prot() is available */ /* #undef HAVE_VM_INSERT_PFN_PROT */ From 060f45e21d062cb0900637fa5e5828a926da7011 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 26 Jul 2023 13:38:15 +0800 Subject: [PATCH 1036/1868] drm/amdkcl: use vm_flags function to set vm_flags It's caused by bc292ab00f6c7a661a8a605c714e8a148f629ef6 "mm: introduce vma->vm_flags wrapper functions" Signed-off-by: Asher Song --- drivers/gpu/drm/amd/backport/kcl_drm_gem.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/backport/kcl_drm_gem.c b/drivers/gpu/drm/amd/backport/kcl_drm_gem.c index 359099cb8af9e..84ffb99293e93 100644 --- a/drivers/gpu/drm/amd/backport/kcl_drm_gem.c +++ b/drivers/gpu/drm/amd/backport/kcl_drm_gem.c @@ -70,7 +70,7 @@ static int _kcl_drm_gem_mmap_obj(struct drm_gem_object *obj, unsigned long obj_s goto err_drm_gem_object_put; } - vma->vm_flags |= VM_IO | VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP; + vm_flags_set(vma, VM_IO | VM_PFNMAP | VM_DONTEXPAND | VM_DONTDUMP); vma->vm_page_prot = pgprot_writecombine(vm_get_page_prot(vma->vm_flags)); vma->vm_page_prot = pgprot_decrypted(vma->vm_page_prot); } From 3774437bef052440b20ebabe66c04d5c3eb0a9b3 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 27 Jul 2023 01:05:14 +0800 Subject: [PATCH 1037/1868] drm/amdkfd: fix a build issue fix the following compile error: 2023-07-26T03:35:53.838Z] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_doorbell.c:194:6: error: no previous prototype for 'kfd_doorbell_unmap_locked' [-Werror=missing-prototypes] [2023-07-26T03:35:53.838Z] void kfd_doorbell_unmap_locked(struct kfd_process_device *pdd) [2023-07-26T03:35:53.838Z] ^~~~~~~~~~~~~~~~~~~~~~~~~ Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c b/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c index 3368779e354af..99e0d445ff2d9 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_doorbell.c @@ -156,7 +156,7 @@ static const struct vm_operations_struct kfd_doorbell_vm_ops = { .fault = kfd_doorbell_vm_fault, }; -void kfd_doorbell_unmap_locked(struct kfd_process_device *pdd) +static void kfd_doorbell_unmap_locked(struct kfd_process_device *pdd) { struct kfd_process *process = pdd->process; struct vm_area_struct *vma; From c5ed4bb24efc5d0a8b0312ea393f5578156b4e46 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 28 Jul 2023 15:15:50 +0800 Subject: [PATCH 1038/1868] drm/amdkcl: change the test for HMM support in kernel Because mmu_notifier_range.vma field is removed in kernel 6.3 by commit 7d4a8be0c4b2b7ffb367 (mm/mmu_notifier: remove unused mmu_notifier_range_update_to_read_only export), We should change the test for HMM support. Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/m4/hmm.m4 | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/hmm.m4 b/drivers/gpu/drm/amd/dkms/m4/hmm.m4 index 72147cbe68a28..72a1a8260873a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/hmm.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/hmm.m4 @@ -49,6 +49,7 @@ dnl # 107e899874e9 - mm/hmm: define the pre-processor related parts of hmm.h eve dnl # v5.4-rc5-20-g04ec32fbc2b2 - mm/hmm: allow hmm_range to be used with a mmu_interval_notifier or hmm_mirror 2019-11-23 19:56:44 -0400 dnl # 99cb252f5e68 - mm/mmu_notifier: add an interval tree notifier 2019-11-23 19:56:44 -0400 dnl # 56f434f40f05 - mm/mmu_notifier: define the header pre-processor parts even if disabled 2019-11-12 20:18:27 -0400 +dnl # 7d4a8be0c4b2 - mm/mmu_notifier: remove unused mmu_notifier_range_update_to_read_only export dnl # AC_DEFUN([AC_AMDGPU_HMM], [ AC_KERNEL_DO_BACKGROUND([ @@ -61,7 +62,7 @@ AC_DEFUN([AC_AMDGPU_HMM], [ struct mmu_notifier_range *mmu_range = NULL; range->notifier = NULL; - mmu_range->vma = NULL; + mmu_range->event = 0; #else #error CONFIG_HMM_MIRROR not enabled #endif From a1d4aaf61ac9315d01c8540e5926788844ac4870 Mon Sep 17 00:00:00 2001 From: Jonathan Kim Date: Wed, 1 Sep 2021 17:02:38 -0400 Subject: [PATCH 1039/1868] drm/amdkfd: set conditional trap_en on aldebaran To ensure performance benchmarks remain suitable for non-debugged processes on aldebaran, make the per-vmid SPI debug TRAP_EN bit conditional on the HSA_ENABLE_DEBUG ENV variable for running processes. For single process debug devices, TRAP_EN will always be on but by spec, the KFD should still report the ttmp setup status set by runtime through the ENV variable. The debugger can choose to ignore this status from its own device lookup. Note: some of the functions that refresh the runlist can be cleaned up now that the dispatch index save is no longer toggled in the initialization or updating of the MQD and there will be a follow on set of patches to do this since they are not functional critical at the moment. Signed-off-by: Jonathan Kim Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c index 3f4fd2f08163d..e3ed568eaacc8 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.c @@ -760,7 +760,7 @@ void gfx_v9_4_2_debug_trap_config_init(struct amdgpu_device *adev, for (i = first_vmid; i < last_vmid; i++) { data = 0; soc15_grbm_select(adev, 0, 0, 0, i, 0); - data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); + data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 0); data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_EN, 0); data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, EXCP_REPLACE, 0); From f902ad3c53ecff0f5acfcbfb8d81528aeed46c26 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 28 Jun 2023 10:21:20 +0800 Subject: [PATCH 1040/1868] drm/amkcl: fake drm_edid_encode_panel_id() It's caused by de1da2f7fe25828288af8ca287a21fb8f0172c3e "drm/amd/display: Add monitor specific edid quirk" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_drm_edid.h | 14 ++++++++++++++ 2 files changed, 15 insertions(+) create mode 100644 include/kcl/kcl_drm_edid.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 2a284365ba73c..0f775ed076173 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -110,4 +110,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_drm_edid.h b/include/kcl/kcl_drm_edid.h new file mode 100644 index 0000000000000..dd472225c0477 --- /dev/null +++ b/include/kcl/kcl_drm_edid.h @@ -0,0 +1,14 @@ +#ifndef AMDKCL_DRM_EDID_H +#define AMDKCL_DRM_EDID_H + +#include + +#ifndef drm_edid_encode_panel_id +#define drm_edid_encode_panel_id(vend_chr_0, vend_chr_1, vend_chr_2, product_id) \ + ((((u32)(vend_chr_0) - '@') & 0x1f) << 26 | \ + (((u32)(vend_chr_1) - '@') & 0x1f) << 21 | \ + (((u32)(vend_chr_2) - '@') & 0x1f) << 16 | \ + ((product_id) & 0xffff)) +#endif /* drm_edid_encode_panel_id */ + +#endif From 6dac8322891a69f37845f6fac342a65a57d19598 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Wed, 28 Jun 2023 17:59:26 -0400 Subject: [PATCH 1041/1868] drm/amdkcl: Some tests fix Fix tests that produce invalid results. AC_KERNEL_TRY_COMPILE_SYMBOL macro requires all possible locations of .c files to search for exported symbols. If file locations either missing or invalid the tests always return 'false'. Change-Id: I717cdfb283c3e7fe81c397d9ef3702b9593e5662 Signed-off-by: Slava Grigorev --- .../gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 | 2 +- .../drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 | 2 +- drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 index 5dc461c4db3df..fd42b70c0fd97 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 @@ -16,7 +16,7 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_LINK_TRAIN_CHANNEL_EQ_DELAY], [ struct drm_dp_aux *aux = NULL; const u8 dpcd[DP_RECEIVER_CAP_SIZE]; drm_dp_link_train_channel_eq_delay(aux, dpcd); - ], [drm_dp_link_train_channel_eq_delay],[drm/drm_dp_helper.c],[ + ], [drm_dp_link_train_channel_eq_delay],[drivers/gpu/drm/drm_dp_helper.c drivers/gpu/drm/display/drm_dp_helper.c],[ AC_DEFINE(HAVE_DRM_DP_LINK_TRAIN_CHANNEL_EQ_DELAY_2ARGS, 1, [drm_dp_link_train_channel_eq_delay() has 2 args]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 index 4d0c1a7e21313..dbd7be4543404 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 @@ -16,7 +16,7 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_LINK_TRAIN_CLOCK_RECOVERY_DELAY], [ struct drm_dp_aux *aux = NULL; const u8 dpcd[DP_RECEIVER_CAP_SIZE]; drm_dp_link_train_clock_recovery_delay(aux, dpcd); - ], [drm_dp_link_train_clock_recovery_delay],[drm/drm_dp_helper.c],[ + ], [drm_dp_link_train_clock_recovery_delay],[drivers/gpu/drm/drm_dp_helper.c drivers/gpu/drm/display/drm_dp_helper.c],[ AC_DEFINE(HAVE_DRM_DP_LINK_TRAIN_CLOCK_RECOVERY_DELAY_2ARGS, 1, [drm_dp_link_train_clock_recovery_delay() has 2 args]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 index 318f729096712..883dc5867886e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 @@ -15,7 +15,7 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_MST_ATOMIC_CHECK], [ ], [ int ret; ret = drm_dp_mst_atomic_check(NULL); - ], [drm_dp_mst_atomic_check], [drivers/gpu/drm/drm_dp_mst_topology.c], [ + ], [drm_dp_mst_atomic_check], [drivers/gpu/drm/drm_dp_mst_topology.c drivers/gpu/drm/display/drm_dp_mst_topology.c], [ AC_DEFINE(HAVE_DRM_DP_MST_ATOMIC_CHECK, 1, [drm_dp_mst_atomic_check() is available]) ]) From 54978586eb3727e87e7d901c379524599ec80ac4 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Thu, 29 Jun 2023 12:37:25 -0400 Subject: [PATCH 1042/1868] drm/amdkcl: Add including of a missing header file This fixes the build against older kernels that don't have drm/display/drm_hdcp_helper.h in their source trees. Change-Id: I25338fac38453a8bc7ee8adac9381000d2b4424d Signed-off-by: Slava Grigorev Reviewed-by: Slava Abramov --- include/kcl/header/drm/display/drm_hdcp_helper.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/kcl/header/drm/display/drm_hdcp_helper.h b/include/kcl/header/drm/display/drm_hdcp_helper.h index 047decb7fc695..8805018a9a244 100644 --- a/include/kcl/header/drm/display/drm_hdcp_helper.h +++ b/include/kcl/header/drm/display/drm_hdcp_helper.h @@ -4,6 +4,8 @@ #if defined(HAVE_DRM_DISPLAY_DRM_HDCP_HELPER_H) #include_next +#else +#include #endif #endif From 1e7f244de15cab1a15fbfb969d6ce7db4c349f2e Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 4 Jul 2023 11:13:36 +0800 Subject: [PATCH 1043/1868] drm/amdkcl: Test whether amdgpu_attr_group->is_bin_visible is available It's caused by fd536660bcbdbb15d6b715f2104d59fa1de50260 "drm/amd: Detect IFWI or PD upgrade support in psp_early_init()" Signed-off-by: Bob Zhou Reviewed-by: Ma Jun --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 4 ++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../drm/amd/dkms/m4/struct_attribute_group.m4 | 17 +++++++++++++++++ 4 files changed, 25 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/struct_attribute_group.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 189574d53ebd3..d6aeb53563ed0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -3981,6 +3981,7 @@ static umode_t amdgpu_flash_attr_is_visible(struct kobject *kobj, struct attribu return adev->psp.sup_ifwi_up ? 0440 : 0; } +#ifdef HAVE_ATTRIBUTE_GROUP_IS_BIN_VISIBLE static umode_t amdgpu_bin_flash_attr_is_visible(struct kobject *kobj, struct bin_attribute *attr, int idx) @@ -3991,11 +3992,14 @@ static umode_t amdgpu_bin_flash_attr_is_visible(struct kobject *kobj, return adev->psp.sup_ifwi_up ? 0660 : 0; } +#endif const struct attribute_group amdgpu_flash_attr_group = { .attrs = flash_attrs, .bin_attrs = bin_flash_attrs, +#ifdef HAVE_ATTRIBUTE_GROUP_IS_BIN_VISIBLE .is_bin_visible = amdgpu_bin_flash_attr_is_visible, +#endif .is_visible = amdgpu_flash_attr_is_visible, }; diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index e4cf2284f3c2a..d331c46364718 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -58,6 +58,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_ASM_SET_MEMORY_H 1 +/* amdgpu_attr_group->is_bin_visible is available */ +#define HAVE_ATTRIBUTE_GROUP_IS_BIN_VISIBLE 1 + /* backlight_device_set_brightness() is available */ #define HAVE_BACKLIGHT_DEVICE_SET_BRIGHTNESS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 198f416c881ad..6fd1f0c92b13c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -152,6 +152,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DISPLAY_INFO_IS_HDMI AC_AMDGPU_DRM_BITMAP_FUNCS AC_AMDGPU_STRUCT_KOBJ_TYPE + AC_AMDGPU_ATTRIBUTE_GROUP_IS_BIN_VISIBLE AC_AMDGPU_MIGRATE_DISABLE AC_AMDGPU_CLOSE_FD AC_AMDGPU_DRM_DP_MST_HPD_IRQ_HANDLE_EVENT diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_attribute_group.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_attribute_group.m4 new file mode 100644 index 0000000000000..80990947459d3 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/struct_attribute_group.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v4.3-rc4-9-g7f5028cf6190 +dnl # sysfs: Support is_visible() on binary attributes +dnl # +AC_DEFUN([AC_AMDGPU_ATTRIBUTE_GROUP_IS_BIN_VISIBLE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct attribute_group *amdgpu_attr_group = NULL; + amdgpu_attr_group->is_bin_visible = NULL; + ],[ + AC_DEFINE(HAVE_ATTRIBUTE_GROUP_IS_BIN_VISIBLE, 1, + [amdgpu_attr_group->is_bin_visible is available]) + ]) + ]) +]) \ No newline at end of file From b24ac378fe7d65d4381fe34cdd7bd8841b5c3c34 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 29 Jun 2023 14:45:41 +0800 Subject: [PATCH 1044/1868] drm/amdkcl: fix m4 issue and update config.h Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/config/config.h | 88 +++++++------------ drivers/gpu/drm/amd/dkms/m4/cancel_work.m4 | 2 +- drivers/gpu/drm/amd/dkms/m4/drm-connector.m4 | 2 +- .../m4/drm-hdcp-update-content-protection.m4 | 5 +- 4 files changed, 37 insertions(+), 60 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index d331c46364718..4e0de41dd1f3a 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -10,6 +10,9 @@ /* whether access_ok(x, x) is available */ #define HAVE_ACCESS_OK_WITH_TWO_ARGUMENTS 1 +/* acpi_dev_get_first_match_dev() is available */ +#define HAVE_ACPI_DEV_GET_FIRST_MATCH_DEV 1 + /* acpi_put_table() is available */ #define HAVE_ACPI_PUT_TABLE 1 @@ -163,6 +166,9 @@ /* down_write_killable() is available */ #define HAVE_DOWN_WRITE_KILLABLE 1 +/* drm_add_override_edid_modes() is available */ +/* #undef HAVE_DRM_ADD_OVERRIDE_EDID_MODES */ + /* Define to 1 if you have the header file. */ /* #undef HAVE_DRM_AMDGPU_PCIID_H */ @@ -185,6 +191,9 @@ /* drm_connector_attach_hdr_output_metadata_property() is available */ #define HAVE_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY 1 +/* drm_connector->edid_override is available */ +#define HAVE_DRM_CONNECTOR_EDID_OVERRIDE 1 + /* drm_connector_for_each_possible_encoder() wants 2 arguments */ #define HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS 1 @@ -214,29 +223,17 @@ /* drm_connector_set_panel_orientation_with_quirk() is available */ #define HAVE_DRM_CONNECTOR_SET_PANEL_ORIENTATION_WITH_QUIRK 1 +/* drm_connector_state->colorspace is available */ +#define HAVE_DRM_CONNECTOR_STATE_COLORSPACE 1 + /* struct drm_connector_state has hdcp_content_type member */ #define HAVE_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE 1 /* struct drm_connector_state has hdr_output_metadata member */ #define HAVE_DRM_CONNECTOR_STATE_HDR_OUTPUT_METADATA 1 -/* drm_connector_unreference() is available */ -/* #undef HAVE_DRM_CONNECTOR_UNREFERENCE */ - -/* drm_connector_xxx() drop _mode_ */ -#define HAVE_DRM_CONNECTOR_XXX_DROP_MODE 1 - -/* ddrm_atomic_stat has __drm_crtcs_state */ -/* #undef HAVE_DRM_CRTCS_STATE_MEMBER */ - -/* drm_crtc_accurate_vblank_count() is available */ -#define HAVE_DRM_CRTC_ACCURATE_VBLANK_COUNT 1 - -/* drm_crtc_enable_color_mgmt() is available */ -#define HAVE_DRM_CRTC_ENABLE_COLOR_MGMT 1 - -/* drm_crtc_from_index() is available */ -#define HAVE_DRM_CRTC_FROM_INDEX 1 +/* drm_connector_attach_colorspace_property() is available */ +#define HAVE_DRM_CONNECT_ATTACH_COLORSPACE_PROPERTY 1 /* drm_crtc_helper_funcs->atomic_check()/atomic_flush()/atomic_begin() wants struct drm_atomic_state arg */ @@ -326,9 +323,6 @@ /* drm_dp_mst_atomic_wait_for_dependencies() is available */ /* #undef HAVE_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES */ -/* acpi_dev_get_first_match_dev() is available */ -#define HAVE_ACPI_DEV_GET_FIRST_MATCH_DEV 1 - /* struct drm_dp_aux has member named 'drm_dev' */ #define HAVE_DRM_DP_AUX_DRM_DEV 1 @@ -431,7 +425,7 @@ /* drm_dp_update_payload_part1() function has start_slot argument */ /* #undef HAVE_DRM_DP_UPDATE_PAYLOAD_PART1_START_SLOT_ARG */ -/* drm_driver->gem_prime_res_obj() is availab/le */ +/* drm_driver->gem_prime_res_obj() is available */ /* #undef HAVE_DRM_DRIVER_GEM_PRIME_RES_OBJ */ /* Define to 1 if you have the header file. */ @@ -482,24 +476,15 @@ /* drm_dsc_compute_rc_parameters() is available */ #define HAVE_DRM_DSC_COMPUTE_RC_PARAMETERS 1 -/* drm_connector_attach_colorspace_property() is available */ -#define HAVE_DRM_CONNECT_ATTACH_COLORSPACE_PROPERTY 1 - -/* drm_mode_create_hdmi_colorspace_property() has 2 args */ -#define HAVE_DRM_MODE_CREATE_HDMI_COLORSPACE_PROPERTY_2ARGS 1 - -/* drm_mode_create_dp_colorspace_property() has 2 args */ -#define HAVE_DRM_MODE_CREATE_DP_COLORSPACE_PROPERTY_2ARGS 1 - -/* drm_connector_state->colorspace is available */ -#define HAVE_DRM_CONNECTOR_STATE_COLORSPACE 1 - /* struct drm_dsc_config has member simple_422 */ #define HAVE_DRM_DSC_CONFIG_SIMPLE_422 1 /* drm_dsc_pps_payload_pack() is available */ #define HAVE_DRM_DSC_PPS_PAYLOAD_PACK 1 +/* drm_edid_override_connector_update() is available */ +#define HAVE_DRM_EDID_OVERRIDE_CONNECTOR_UPDATE 1 + /* drm_fb_helper_single_add_all_connectors() && drm_fb_helper_remove_one_connector() are symbol */ /* #undef HAVE_DRM_FB_HELPER_ADD_REMOVE_CONNECTORS */ @@ -507,9 +492,6 @@ /* drm_fb_helper_alloc_info() is available */ #define HAVE_DRM_FB_HELPER_ALLOC_INFO 1 -/* migrate_disable() is available */ -#define HAVE_MIGRATE_DISABLE 1 - /* drm_fb_helper_fill_info() is available */ #define HAVE_DRM_FB_HELPER_FILL_INFO 1 @@ -552,12 +534,6 @@ /* drm_hdcp_update_content_protection is available */ #define HAVE_DRM_HDCP_UPDATE_CONTENT_PROTECTION 1 -/* drm_edid_override_connector_update() is available */ -#define HAVE_DRM_EDID_OVERRIDE_CONNECTOR_UPDATE 1 - -/* drm_add_override_edid_modes() is available */ -/* #undef HAVE_DRM_ADD_OVERRIDE_EDID_MODES */ - /* drm_hdmi_avi_infoframe_from_display_mode() has p,p,b interface */ /* #undef HAVE_DRM_HDMI_AVI_INFOFRAME_FROM_DISPLAY_MODE_P_P_B */ @@ -577,7 +553,7 @@ #define HAVE_DRM_MEMCPY_FROM_WC_IOSYS_MAP_ARG 1 /* drm_modeset_backoff() has int return */ -#define HAVE_DRM_MODESET_BACKOFF_RETURN_INT 1 +/* #undef HAVE_DRM_MODESET_BACKOFF_RETURN_INT */ /* drm_mode_config->dp_subconnector_property is available */ #define HAVE_DRM_MODE_CONFIG_DP_SUBCONNECTOR_PROPERTY 1 @@ -588,6 +564,12 @@ /* drm_mode_config->fb_modifiers_not_supported is available */ #define HAVE_DRM_MODE_CONFIG_FB_MODIFIERS_NOT_SUPPORTED 1 +/* drm_mode_create_dp_colorspace_property() has 2 args */ +#define HAVE_DRM_MODE_CREATE_DP_COLORSPACE_PROPERTY_2ARGS 1 + +/* drm_mode_create_hdmi_colorspace_property() has 2 args */ +#define HAVE_DRM_MODE_CREATE_HDMI_COLORSPACE_PROPERTY_2ARGS 1 + /* drm_mode_init() is available */ #define HAVE_DRM_MODE_INIT 1 @@ -811,14 +793,8 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_PROCESSOR_H 1 -/* Define to 1 if you have the header file. */ -#define HAVE_LINUX_SCHED_MM_H 1 - -/* Define to 1 if you have the header file. */ -#define HAVE_LINUX_SCHED_SIGNAL_H 1 - -/* Define to 1 if you have the header file. */ -#define HAVE_LINUX_SCHED_TASK_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_RBTREE_TYPES_H 1 /* Define to 1 if you have the header file. */ #define HAVE_LINUX_STDARG_H 1 @@ -844,8 +820,8 @@ /* memalloc_noreclaim_save() is available */ #define HAVE_MEMALLOC_NORECLAIM_SAVE 1 -/* drm_connector->edid_override is available */ -#define HAVE_DRM_CONNECTOR_EDID_OVERRIDE 1 +/* migrate_disable() is available */ +#define HAVE_MIGRATE_DISABLE 1 /* struct migrate_vma has fault_page */ #define HAVE_MIGRATE_VMA_FAULT_PAGE 1 @@ -872,7 +848,7 @@ #define HAVE_MMU_NOTIFIER_SYNCHRONIZE 1 /* mm_access() is available */ -#define HAVE_MM_ACCESS 1 +/* #undef HAVE_MM_ACCESS */ /* release_pages() wants 2 args */ #define HAVE_MM_RELEASE_PAGES_2ARGS 1 @@ -1107,7 +1083,7 @@ #define PACKAGE_NAME "amdgpu-dkms" /* Define to the full name and version of this package. */ -#define PACKAGE_STRING "amdgpu-dkms 6.1.0" +#define PACKAGE_STRING "amdgpu-dkms 6.2.0" /* Define to the one symbol short name of this package. */ #define PACKAGE_TARNAME "amdgpu-dkms" @@ -1116,7 +1092,7 @@ #define PACKAGE_URL "" /* Define to the version of this package. */ -#define PACKAGE_VERSION "6.1.0" +#define PACKAGE_VERSION "6.2.0" #include "config-amd-chips.h" diff --git a/drivers/gpu/drm/amd/dkms/m4/cancel_work.m4 b/drivers/gpu/drm/amd/dkms/m4/cancel_work.m4 index b0cabe1643a14..063fdc3d8f23b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/cancel_work.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/cancel_work.m4 @@ -9,7 +9,7 @@ AC_DEFUN([AC_AMDGPU_CANCEL_WORK], [ #include ], [ cancel_work(NULL); - ], [ + ], [cancel_work], [], [ AC_DEFINE(HAVE_CANCEL_WORK, 1, [cancel_work() is available]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector.m4 index 43fb1565aabc0..653c3e1e1ec98 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-connector.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector.m4 @@ -5,7 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_EDID_OVERRIDE], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #include + #include ],[ struct drm_connector *connector = NULL; connector->edid_override = NULL; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-hdcp-update-content-protection.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-hdcp-update-content-protection.m4 index f91f55f90ced8..e79473b4902ab 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-hdcp-update-content-protection.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-hdcp-update-content-protection.m4 @@ -5,7 +5,8 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DISPLAY_DRM_HDCP_H + #ifdef HAVE_DRM_DISPLAY_DRM_HDCP_H + #include #include #else #include @@ -17,4 +18,4 @@ AC_DEFUN([AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION], [ [drm_hdcp_update_content_protection is available]) ]) ]) -]) +]) \ No newline at end of file From 61fe0936026cf803d0bd5ad71ec7ace2491a1d99 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Tue, 11 Jul 2023 12:14:26 -0400 Subject: [PATCH 1045/1868] drm/amdkcl: Add including of a missing header file This fixes the build against older kernels that don't have linux/iosys-map.h in their source trees. Change-Id: Ibffc262ec70c63220b92573119749fd6cccaba58 Signed-off-by: Slava Grigorev Reviewed-by: Slava Abramov --- include/kcl/header/linux/iosys-map.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/include/kcl/header/linux/iosys-map.h b/include/kcl/header/linux/iosys-map.h index a96b1547378c6..9ce52ad756e1d 100644 --- a/include/kcl/header/linux/iosys-map.h +++ b/include/kcl/header/linux/iosys-map.h @@ -3,7 +3,8 @@ #ifdef HAVE_LINUX_IOSYS_MAP_H #include_next +#else +#include #endif #endif - From e355200b2dcf913e15ddd617326c0fb2e3c6020e Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 7 Jul 2023 14:26:32 +0800 Subject: [PATCH 1046/1868] drm/amdkcl: kcl-cleanup AMDKCL_AMDGPU_DRM_CONNECTOR_STATUS_DETECT_MANDATORY Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- include/kcl/kcl_drm_connector.h | 8 -------- 1 file changed, 8 deletions(-) diff --git a/include/kcl/kcl_drm_connector.h b/include/kcl/kcl_drm_connector.h index 9e95e282f458a..c0e2b217ddcc5 100644 --- a/include/kcl/kcl_drm_connector.h +++ b/include/kcl/kcl_drm_connector.h @@ -27,14 +27,6 @@ #include #include -/* - * commit v4.9-rc4-949-g949f08862d66 - * drm: Make the connector .detect() callback optional - */ -#if DRM_VERSION_CODE < DRM_VERSION(4, 10, 0) -#define AMDKCL_AMDGPU_DRM_CONNECTOR_STATUS_DETECT_MANDATORY -#endif - /** * drm_connector_for_each_possible_encoder - iterate connector's possible encoders * @connector: &struct drm_connector pointer From c5420920a520db4f7c0854ff1acae6fc7a7b9a1e Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 12 Jul 2023 10:21:55 +0800 Subject: [PATCH 1047/1868] drm/amdkcl: wrap code under macro HAVE_STRUCT_DRM_CRTC_STATE_ASYNC_FLIP It's caused by 3f86b60691e60c57ad4ccc87a9b81e059c10af7e "drm/amd/display: only accept async flips for fast updates" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index f12fe927fc52e..4e059036a0425 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -9112,7 +9112,12 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state, * dm_crtc_helper_atomic_check() only accepts async flips with * fast updates. */ +#if defined(HAVE_STRUCT_DRM_CRTC_STATE_ASYNC_FLIP) if (crtc->state->async_flip && +#else + if ((crtc->state->pageflip_flags & + DRM_MODE_PAGE_FLIP_ASYNC) != 0 && +#endif (acrtc_state->update_type != UPDATE_TYPE_FAST || get_mem_type(old_plane_state->fb) != get_mem_type(fb))) drm_warn_once(state->dev, From 671c9e0c1b7dc553d539fff70fea6ad2414d6d04 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 13 Jul 2023 11:59:54 +0800 Subject: [PATCH 1048/1868] drm/amdkcl: fake drm_warn_once() It's caused by 3f86b60691e60c57ad4ccc87a9b81e059c10af7e "drm/amd/display: only accept async flips for fast updates" Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- include/kcl/kcl_drm_print.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index c71867326f13b..15abde9faeb53 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -84,6 +84,11 @@ void kcl_drm_err(const char *format, ...); dev_warn((drm)->dev, "[drm] " fmt, ##__VA_ARGS__) #endif /* drm_warn */ +#ifndef drm_warn_once +#define drm_warn_once(drm, fmt, ...) \ + dev_warn_once((drm)->dev, "[drm] " fmt, ##__VA_ARGS__) +#endif /* drm_warn_once */ + #if !defined(DRM_UT_VBL) #define DRM_UT_VBL 0x20 #endif From e415bdc0f612dae0ba6fae1ee0843649ab4733b2 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 14 Jul 2023 10:53:22 +0800 Subject: [PATCH 1049/1868] drm/amdkcl: fake want_init_on_free() It's caused by 88181f344c9156ee111013c7e38187803b15612c "drm/ttm: Use init_on_free to delay release TTM BOs" Signed-off-by: Bob Zhou Change-Id: I56137fef24020b8ab3c341cff07b2d4b7d5db8b9 --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/want_init_on_free.m4 | 16 ++++++++++++++++ include/kcl/kcl_mm.h | 8 ++++++++ 4 files changed, 28 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/want_init_on_free.m4 diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 4e0de41dd1f3a..c92c20fe63a20 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1052,6 +1052,9 @@ /* wait_queue_entry_t exists */ #define HAVE_WAIT_QUEUE_ENTRY 1 +/* want_init_on_free() is available */ +#define HAVE_WANT_INIT_ON_FREE 1 + /* ww_mutex_trylock() has context arg */ #define HAVE_WW_MUTEX_TRYLOCK_CONTEXT_ARG 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 6fd1f0c92b13c..a94d947b25ec9 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -199,6 +199,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV AC_AMDGPU_MIGRATE_VMA_FAULT_PAGE AC_AMDGPU_RB_ADD_CACHED + AC_AMDGPU_WANT_INIT_ON_FREE AC_AMDGPU_APPLE_GMUX_DETECT AC_AMDGPU_MM_KMALLOC_SIZE_ROUNDUP AC_AMDGPU_ZONE_DEVICE_PAGE_INIT diff --git a/drivers/gpu/drm/amd/dkms/m4/want_init_on_free.m4 b/drivers/gpu/drm/amd/dkms/m4/want_init_on_free.m4 new file mode 100644 index 0000000000000..8503b32aeee1e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/want_init_on_free.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v5.2-5754-g6471384af2a6 +dnl # mm: security: introduce init_on_alloc=1 and init_on_free=1 boot options +dnl # +AC_DEFUN([AC_AMDGPU_WANT_INIT_ON_FREE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + bool r = want_init_on_free(); + ], [ + AC_DEFINE(HAVE_WANT_INIT_ON_FREE, 1, + [want_init_on_free() is available]) + ]) + ]) +]) \ No newline at end of file diff --git a/include/kcl/kcl_mm.h b/include/kcl/kcl_mm.h index 9d6df88ddf9fb..9151bdbed8785 100644 --- a/include/kcl/kcl_mm.h +++ b/include/kcl/kcl_mm.h @@ -120,4 +120,12 @@ static inline void vm_flags_clear(struct vm_area_struct *vma, } #endif +#ifndef HAVE_WANT_INIT_ON_FREE +static inline bool want_init_on_free(void) +{ + pr_warn_once("legacy kernel without want_init_on_free()\n"); + return false; +} +#endif + #endif /* AMDKCL_MM_H */ From 891b11a35e4ba760ae0714fed194cc8d7f7ede4d Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 17 Jul 2023 10:45:58 +0800 Subject: [PATCH 1050/1868] drm/amdkcl: fake macros DRM_FORMAT_ARG* It's caused by fb69732876d0ef8e6252fed2585a2acb4f75f121 "drm/amd/display: Expose more formats for overlay planes on DCN" Signed-off-by: Bob Zhou Reviewed-by: Guchun Chen Reviewed-by: Flora Cui --- include/kcl/kcl_drm_fourcc.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/kcl/kcl_drm_fourcc.h b/include/kcl/kcl_drm_fourcc.h index 959f64bb803a6..f28a041070a75 100644 --- a/include/kcl/kcl_drm_fourcc.h +++ b/include/kcl/kcl_drm_fourcc.h @@ -222,4 +222,10 @@ #define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */ #endif +#ifndef DRM_FORMAT_ARGB16161616 +#define DRM_FORMAT_ARGB16161616 fourcc_code('A', 'R', '4', '8') /* [63:0] A:R:G:B 16:16:16:16 little endian */ +#define DRM_FORMAT_ABGR16161616 fourcc_code('A', 'B', '4', '8') /* [63:0] A:B:G:R 16:16:16:16 little endian */ +#define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */ +#endif + #endif /* KCL_KCL_DRM_FOURCC_H */ From 3b878847b8f3c92ac5f76a8a0affcd8c2dc718a0 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 17 Jul 2023 12:26:55 +0800 Subject: [PATCH 1051/1868] drm/amdkcl: wrap code under macro HAVE_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES It's caused by 6027cda96685ed287140febe7926a78c26a8ece4 "drm/amd/display: Fix race condition when turning off an output alone" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 4e059036a0425..fde5bf65b89cd 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -9800,7 +9800,9 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) trace_amdgpu_dm_atomic_commit_tail_begin(state); drm_atomic_helper_update_legacy_modeset_state(dev, state); +#ifdef HAVE_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES drm_dp_mst_atomic_wait_for_dependencies(state); +#endif dm_state = dm_atomic_get_new_state(state); if (dm_state && dm_state->context) { From bf40250a924d8393e33cdb5dd514e0598adc21ae Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Thu, 20 Jul 2023 09:13:54 -0400 Subject: [PATCH 1052/1868] drm/amdkcl: Fix tests for exported symbols Fix tests that produce invalid results. AC_KERNEL_TRY_COMPILE_SYMBOL macro requires all possible locations of .c files to search for exported symbols. If file locations either missing or invalid the tests always return 'false'. Change-Id: I3ef01cece3da727bfdd912b616b486f9ee407bdb Signed-off-by: Slava Grigorev --- drivers/gpu/drm/amd/dkms/m4/acpi-put-table.m4 | 7 +++++-- .../amd/dkms/m4/drm-connector-atomic-hdr-metadata-equal.m4 | 2 +- .../drm-connector-attach-hdr-output-metadata-property.m4 | 2 +- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 +- 4 files changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/acpi-put-table.m4 b/drivers/gpu/drm/amd/dkms/m4/acpi-put-table.m4 index 27001acd98f95..83a0b1e027b9b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/acpi-put-table.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/acpi-put-table.m4 @@ -4,8 +4,11 @@ dnl # ACPICA: Tables: Back port acpi_get_table_with_size() and dnl # early_acpi_os_unmap_memory() from Linux kernel AC_DEFUN([AC_AMDGPU_ACPI_PUT_TABLE], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([acpi_put_table], - [drivers/acpi/acpica/tbxface.c], [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + acpi_put_table(NULL); + ], [acpi_put_table], [drivers/acpi/acpica/tbxface.c], [ AC_DEFINE(HAVE_ACPI_PUT_TABLE, 1, [acpi_put_table() is available]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-atomic-hdr-metadata-equal.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-atomic-hdr-metadata-equal.m4 index 7ae2c3fd78efd..211e6fdd63702 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-connector-atomic-hdr-metadata-equal.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector-atomic-hdr-metadata-equal.m4 @@ -8,7 +8,7 @@ AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_ATOMIC_HDR_METADATA_EQUAL], [ #include ], [ drm_connector_atomic_hdr_metadata_equal(NULL, NULL); - ], [drm_connector_atomic_hdr_metadata_equal], [drm/drm_connector.c], [ + ], [drm_connector_atomic_hdr_metadata_equal], [drivers/gpu/drm/drm_connector.c], [ AC_DEFINE(HAVE_DRM_CONNECTOR_ATOMIC_HDR_METADATA_EQUAL, 1, [drm_connector_atomic_hdr_metadata_equal() is available]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-attach-hdr-output-metadata-property.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-attach-hdr-output-metadata-property.m4 index fccf8755fc7fe..7ea380c7d60eb 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-connector-attach-hdr-output-metadata-property.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector-attach-hdr-output-metadata-property.m4 @@ -8,7 +8,7 @@ AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY], [ #include ], [ drm_connector_attach_hdr_output_metadata_property(NULL); - ], [drm_connector_attach_hdr_output_metadata_property], [drm/drm_connector.c], [ + ], [drm_connector_attach_hdr_output_metadata_property], [drivers/gpu/drm/drm_connector.c], [ AC_DEFINE(HAVE_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY, 1, [drm_connector_attach_hdr_output_metadata_property() is available]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index a94d947b25ec9..cc29352f1c0be 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -520,7 +520,7 @@ AC_DEFUN([AC_KERNEL_CHECK_SYMBOL_EXPORT], [ split(s, symbols, " ") } { for (i in symbols) { - s="EXPORT_SYMBOL.*\\("symbols[[i]]"\\);" + s="EXPORT_SYMBOL.*\\("symbols[[i]]"\\)" if ($[0] ~ s) n++ } From 219ec10100b718d6b91fa5dd4935afacbc90cc63 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 24 Jul 2023 11:58:23 +0800 Subject: [PATCH 1053/1868] drm/amdkcl: apply amdkcl_ttm_resvp to dma_resv_trylock() It's caused by d769528e46493d56f9151fdecf25091b74c4eb49 "drm/amdgpu: add VISIBLE info in amdgpu_bo_print_info" Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index 6d9fd3d26a14e..5dcbd13ee7557 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -1635,7 +1635,7 @@ u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo, struct seq_file *m) unsigned int pin_count; u64 size; - if (dma_resv_trylock(bo->tbo.base.resv)) { + if (dma_resv_trylock(amdkcl_ttm_resvp(&bo->tbo))) { if (!bo->tbo.resource) { placement = "NONE"; } else { @@ -1676,7 +1676,7 @@ u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo, struct seq_file *m) break; } } - dma_resv_unlock(bo->tbo.base.resv); + dma_resv_unlock(amdkcl_ttm_resvp(&bo->tbo)); } else { placement = "UNKNOWN"; } From 8f6d5692830b047d626e91aee727764fc10a0ac7 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 26 Jul 2023 10:19:59 +0800 Subject: [PATCH 1054/1868] drm/amdkcl: fake _dynamic_func_call_no_desc() It's caused by 3f4e4c813a265803029c1c7e1a9915ceb0fc5da4 "drm/amdkfd: avoid svm dump when dynamic debug disabled" Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- include/kcl/kcl_dynamic_debug.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/include/kcl/kcl_dynamic_debug.h b/include/kcl/kcl_dynamic_debug.h index 6c6f7296eba94..0d5ad3a9d2d52 100644 --- a/include/kcl/kcl_dynamic_debug.h +++ b/include/kcl/kcl_dynamic_debug.h @@ -3,6 +3,8 @@ #ifndef AMDKCL_DYNAMIC_DEBUG_H #define AMDKCL_DYNAMIC_DEBUG_H +#include + #ifndef DECLARE_DYNDBG_CLASSMAP enum class_map_type { DD_CLASS_TYPE_DISJOINT_BITS, @@ -61,4 +63,16 @@ struct ddebug_class_map { #endif +#if IS_ENABLED(CONFIG_DYNAMIC_DEBUG) +#ifndef _dynamic_func_call_no_desc +#define __dynamic_func_call_no_desc(id, fmt, func, ...) do { \ + DEFINE_DYNAMIC_DEBUG_METADATA(id, fmt); \ + if (DYNAMIC_DEBUG_BRANCH(id)) \ + func(__VA_ARGS__); \ +} while (0) + +#define _dynamic_func_call_no_desc(fmt, func, ...) \ + __dynamic_func_call_no_desc(__UNIQUE_ID(ddebug), fmt, func, ##__VA_ARGS__) +#endif /* _dynamic_func_call_no_desc */ +#endif /* CONFIG_DYNAMIC_DEBUG */ #endif /* AMDKCL_DYNAMIC_DEBUG_H */ From 0616340523dfac1ab14c9b68d9b6c1953ea7e25e Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 28 Jul 2023 14:31:36 +0800 Subject: [PATCH 1055/1868] drm/amdkcl: update KCL M4 find path for drm_dp_mst_helper.h The file path of drm_dp_mst_helper.h has been modify to 'drm/display/', some old KCL script path is invalid. So update new path and fix m4 test issue for drm_dp_mst_atomic_wait_for_dependencies. Fixes: 7607389cc536 ("drm/amdkcl: Check if drm_dp_mst_atomic_wait_for_dependencies() is available") Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/config/config.h | 6 +++--- .../drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 | 21 +++++++++++++++++-- 2 files changed, 22 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index c92c20fe63a20..a778ec84c6bfd 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -318,10 +318,10 @@ /* #undef HAVE_DRM_DP_ATOMIC_RELEASE_VCPI_SLOTS_MST_PORT */ /* drm_dp_mst_atomic_setup_commit() is available */ -/* #undef HAVE_DRM_DP_ATOMIC_SETUP_COMMIT */ +#define HAVE_DRM_DP_ATOMIC_SETUP_COMMIT 1 /* drm_dp_mst_atomic_wait_for_dependencies() is available */ -/* #undef HAVE_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES */ +#define HAVE_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES 1 /* struct drm_dp_aux has member named 'drm_dev' */ #define HAVE_DRM_DP_AUX_DRM_DEV 1 @@ -381,7 +381,7 @@ #define HAVE_DRM_DP_MST_PORT_PASSTHROUGH_AUX 1 /* drm_dp_mst_root_conn_atomic_check() is available */ -/* #undef HAVE_DRM_DP_MST_ROOT_CONN_ATOMIC_CHECK */ +#define HAVE_DRM_DP_MST_ROOT_CONN_ATOMIC_CHECK 1 /* struct drm_dp_mst_topology_cbs->destroy_connector is available */ /* #undef HAVE_DRM_DP_MST_TOPOLOGY_CBS_DESTROY_CONNECTOR */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 index d50c35a4fd1bc..96acc6bf42724 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 @@ -100,7 +100,13 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_SETUP_COMMIT], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) + #include + #else #include + #endif ],[ int ret; ret = drm_dp_mst_atomic_setup_commit(NULL); @@ -120,10 +126,15 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) + #include + #else #include + #endif ],[ - int ret; - ret = drm_dp_mst_atomic_wait_for_dependencies(NULL); + drm_dp_mst_atomic_wait_for_dependencies(NULL); ],[ AC_DEFINE(HAVE_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES, 1, [drm_dp_mst_atomic_wait_for_dependencies() is available]) @@ -138,7 +149,13 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_ROOT_CONN_ATOMIC_CHECK], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ + #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) + #include + #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) + #include + #else #include + #endif ],[ int ret; ret = drm_dp_mst_root_conn_atomic_check(NULL, NULL); From 66580089b4a7a277993427d030c6b8dfadc56564 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 4 Aug 2023 11:44:51 +0800 Subject: [PATCH 1056/1868] Bump AMDGPU version to 6.3.0 Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/config/config.h | 2 +- drivers/gpu/drm/amd/dkms/configure.ac | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index a778ec84c6bfd..044383927258f 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1095,7 +1095,7 @@ #define PACKAGE_URL "" /* Define to the version of this package. */ -#define PACKAGE_VERSION "6.2.0" +#define PACKAGE_VERSION "6.3.0" #include "config-amd-chips.h" diff --git a/drivers/gpu/drm/amd/dkms/configure.ac b/drivers/gpu/drm/amd/dkms/configure.ac index 77f27bca72e24..c6b7d1e343742 100644 --- a/drivers/gpu/drm/amd/dkms/configure.ac +++ b/drivers/gpu/drm/amd/dkms/configure.ac @@ -1,4 +1,4 @@ -AC_INIT(amdgpu-dkms, 6.2.0) +AC_INIT(amdgpu-dkms, 6.3.0) AC_LANG(C) AC_CONFIG_AUX_DIR([config]) From cfdb57638b9ade141455f25f31356a5e9a75597d Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 28 Jul 2023 15:07:56 +0800 Subject: [PATCH 1057/1868] drm/amdkcl: test whether drm_gem_atomic_helper.h is available Signed-off-by: Bob Zhou Reviewed-by: Ma Jun --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 8 +++++++- include/kcl/header/drm/drm_gem_atomic_helper.h | 2 +- 3 files changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 044383927258f..58563f4ab3706 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -449,6 +449,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_FBDEV_GENERIC_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_GEM_ATOMIC_HELPER_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_MANAGED_H 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index 642993ebcc9cb..38a64fd0deb08 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -55,7 +55,13 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # drm/dp: Move public DisplayPort headers into dp/ dnl # AC_KERNEL_CHECK_HEADERS([drm/dp/drm_dp_mst_helper.h]) - + + dnl # + dnl # v5.11-rc2-620-g6dd7b6ce43ac + dnl # drm: Add additional atomic helpers for shadow-buffered planes + dnl # + AC_KERNEL_CHECK_HEADERS([drm/drm_gem_atomic_helper.h]) + dnl # dnl # v5.18-rc2-594-gda68386d9edb dnl # drm: Rename dp/ to display/ diff --git a/include/kcl/header/drm/drm_gem_atomic_helper.h b/include/kcl/header/drm/drm_gem_atomic_helper.h index ba17f457edc4f..1eb467c2c3327 100644 --- a/include/kcl/header/drm/drm_gem_atomic_helper.h +++ b/include/kcl/header/drm/drm_gem_atomic_helper.h @@ -2,7 +2,7 @@ #ifndef _KCL_HEADER_DRM_GEM_ATOMIC_HELPER_PREPARE_H_H_ #define _KCL_HEADER_DRM_GEM_ATOMIC_HELPER_PREPARE_H_H_ -#if defined(HAVE_DRM_GEM_PLANE_HELPER_PREPARE_FB) +#if defined(HAVE_DRM_DRM_GEM_ATOMIC_HELPER_H) #include_next #endif From 8a999c592735b21705e70af1893effbd694473ce Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 2 Aug 2023 10:33:07 +0800 Subject: [PATCH 1058/1868] drm/amdkcl: Fix typo in m4 file Signed-off-by: Ma Jun --- drivers/gpu/drm/amd/dkms/m4/ttm_buffer_object.m4 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/ttm_buffer_object.m4 b/drivers/gpu/drm/amd/dkms/m4/ttm_buffer_object.m4 index 6bf4a39e9679c..ed0b163902c11 100644 --- a/drivers/gpu/drm/amd/dkms/m4/ttm_buffer_object.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/ttm_buffer_object.m4 @@ -17,7 +17,7 @@ AC_DEFUN([AC_AMDGPU_TTM_BUFFER_OBJECT], [ gem_obj->resv = &gem_obj->_resv; ], [ AC_DEFINE(HAVE_DRM_GEM_OBJECT_RESV, 1, - [ttm_buffer_object->base is available]) + [drm_gem_object->resv/_resv is available]) ]) ]) ]) From f535fabb18d89ea0b2064ffb7e7ba2533293c9f3 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 28 Jul 2023 17:34:58 +0800 Subject: [PATCH 1059/1868] drm/amdkcl: add kcl_header support for dkms m4 All of m4 script is using the same code block to verify if the header file is available, So add fake kcl header file and cleanup the verify for header files The M4 script will ben't blocked by the header file. Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- .../gpu/drm/amd/dkms/m4/drm-device-pdev.m4 | 2 - .../drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 | 44 +------------------ .../gpu/drm/amd/dkms/m4/drm-dp-aux-drm-dev.m4 | 8 +--- .../drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 | 6 --- .../m4/drm-dp-cec-correlation-functions.m4 | 6 --- .../m4/drm-dp-link-train-channel-eq-delay.m4 | 8 +--- .../drm-dp-link-train-clock-recovery-delay.m4 | 6 --- .../m4/drm-dp-mst-add-affected-dsc-crtcs.m4 | 6 --- .../amd/dkms/m4/drm-dp-mst-atomic-check.m4 | 6 --- .../dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 | 12 ----- .../drm/amd/dkms/m4/drm-dp-mst-detect-port.m4 | 6 --- .../dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 | 6 --- .../amd/dkms/m4/drm-dp-mst-port-full-pbn.m4 | 6 --- .../gpu/drm/amd/dkms/m4/drm-dp-mst-port.m4 | 6 --- .../amd/dkms/m4/drm-dp-mst-topology-cbs.m4 | 24 ---------- .../dkms/m4/drm-dp-mst-topology-mgr-resume.m4 | 6 --- .../amd/dkms/m4/drm-dp-mst-topology-state.m4 | 18 -------- .../drm/amd/dkms/m4/drm-dp-mst-topology.m4 | 12 ----- .../dkms/m4/drm-dp-send-real-edid-checksum.m4 | 8 +--- .../gpu/drm/amd/dkms/m4/drm-driver-feature.m4 | 9 ---- .../amd/dkms/m4/drm-driver-gem-open-object.m4 | 4 -- .../dkms/m4/drm-driver-gem-prime-res-obj.m4 | 4 -- .../amd/dkms/m4/drm-fb-helper-fill-info.m4 | 3 -- .../m4/drm-hdcp-update-content-protection.m4 | 5 --- ...-up-update-payload-part1-start-slot-arg.m4 | 6 --- .../amd/dkms/m4/drm_dp_mst_topology_mgr.m4 | 6 --- .../dkms/m4/drm_dp_mst_topology_mgr_init.m4 | 6 --- .../dkms/m4/drm_dsc_compute_rc_parameters.m4 | 6 +-- drivers/gpu/drm/amd/dkms/m4/drm_dsc_config.m4 | 4 -- .../amd/dkms/m4/drm_dsc_pps_payload_pack.m4 | 4 -- .../gpu/drm/amd/dkms/m4/drm_fb_helper_init.m4 | 4 -- .../drm/amd/dkms/m4/kernel_single_target.m4 | 3 ++ .../amd/dkms/tiny_wrapper/include/drm/drmP.h | 10 +++++ .../tiny_wrapper/include/drm/drm_aperture.h | 9 ++++ .../tiny_wrapper/include/drm/drm_dp_helper.h | 14 ++++++ .../include/drm/drm_dp_mst_helper.h | 14 ++++++ .../dkms/tiny_wrapper/include/drm/drm_dsc.h | 17 +++++++ .../dkms/tiny_wrapper/include/drm/drm_hdcp.h | 12 +++++ 38 files changed, 84 insertions(+), 252 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drmP.h create mode 100644 drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_aperture.h create mode 100644 drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_dp_helper.h create mode 100644 drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_dp_mst_helper.h create mode 100644 drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_dsc.h create mode 100644 drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_hdcp.h diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-device-pdev.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-device-pdev.m4 index 25f5b1ca72eca..7bbbd70aab907 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-device-pdev.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-device-pdev.m4 @@ -5,9 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DEVICE_PDEV], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DRMP_H #include - #endif #include ], [ struct drm_device *pdd = NULL; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 index 96acc6bf42724..2e5156f632700 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 @@ -5,13 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FIND_VCPI_SLOTS], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ], [ int retval; retval = drm_dp_atomic_find_vcpi_slots(NULL, NULL, NULL, 0, 0); @@ -30,13 +24,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_RELEASE_VCPI_SLOTS], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else - #include - #endif + #include ],[ int ret; ret = drm_dp_atomic_release_time_slots(NULL, NULL, NULL); @@ -49,13 +37,7 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_RELEASE_VCPI_SLOTS], [ dnl # drm/dp_mst: Start tracking per-port VCPI allocations dnl # AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ],[ int ret; struct drm_dp_mst_port *port; @@ -76,13 +58,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_FIND_TIME_SLOTS], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ],[ int ret; ret = drm_dp_atomic_find_time_slots(NULL, NULL, NULL, 0); @@ -100,13 +76,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_SETUP_COMMIT], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ],[ int ret; ret = drm_dp_mst_atomic_setup_commit(NULL); @@ -126,13 +96,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_WAIT_FOR_DEPENDENCIES], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ],[ drm_dp_mst_atomic_wait_for_dependencies(NULL); ],[ @@ -149,13 +113,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_ROOT_CONN_ATOMIC_CHECK], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ],[ int ret; ret = drm_dp_mst_root_conn_atomic_check(NULL, NULL); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-aux-drm-dev.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-aux-drm-dev.m4 index a20efecd2b022..cef22c56ee51c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-aux-drm-dev.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-aux-drm-dev.m4 @@ -5,13 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_AUX_DRM_DEV], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_HELPER_H) - #include - #else - #include - #endif + #include ], [ struct drm_dp_aux dda; dda.drm_dev = NULL; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 index eabc0261dd0be..d168a591bcd23 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 @@ -5,13 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_CALC_PBN_MODE], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ], [ drm_dp_calc_pbn_mode(0, 0, 0); ], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-cec-correlation-functions.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-cec-correlation-functions.m4 index 3ba925a8e076f..3ded1ff2015a2 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-cec-correlation-functions.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-cec-correlation-functions.m4 @@ -5,13 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_CEC_CORRELATION_FUNCTIONS], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_HELPER_H) - #include - #else #include - #endif ], [ drm_dp_cec_register_connector(NULL, NULL); ], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 index fd42b70c0fd97..32db29f7c3936 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-channel-eq-delay.m4 @@ -5,13 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_LINK_TRAIN_CHANNEL_EQ_DELAY], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_HELPER_H) - #include - #else - #include - #endif + #include ], [ struct drm_dp_aux *aux = NULL; const u8 dpcd[DP_RECEIVER_CAP_SIZE]; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 index dbd7be4543404..327cd21b0200c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-link-train-clock-recovery-delay.m4 @@ -5,13 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_LINK_TRAIN_CLOCK_RECOVERY_DELAY], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_HELPER_H) - #include - #else #include - #endif ], [ struct drm_dp_aux *aux = NULL; const u8 dpcd[DP_RECEIVER_CAP_SIZE]; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 index 42d7b5595403a..1d4564270d065 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 @@ -5,13 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_ADD_AFFECTED_DSC_CRTCS], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ], [ int ret; ret = drm_dp_mst_add_affected_dsc_crtcs(NULL, NULL); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 index 883dc5867886e..e56284f5a5a2c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-check.m4 @@ -5,13 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_ATOMIC_CHECK], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ], [ int ret; ret = drm_dp_mst_atomic_check(NULL); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 index 0019f393b38f3..ad901210aeaba 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-atomic-enable-dsc.m4 @@ -5,13 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_ATOMIC_ENABLE_DSC], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ], [ drm_dp_mst_atomic_enable_dsc(NULL, NULL, 0, 0, false); ], [drm_dp_mst_atomic_enable_dsc], [drivers/gpu/drm/drm_dp_mst_topology.c], [ @@ -25,13 +19,7 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_MST_ATOMIC_ENABLE_DSC], [ dnl # drm/display/dp_mst: Move all payload info into the atomic state dnl # AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ], [ int vcpi; vcpi = drm_dp_mst_atomic_enable_dsc(NULL, NULL, 0, false); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-detect-port.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-detect-port.m4 index 7c01c0479075e..4198140ed6a0e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-detect-port.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-detect-port.m4 @@ -5,13 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_DETECT_PORT], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ], [ int ret; ret = drm_dp_mst_detect_port(NULL, NULL, NULL, NULL); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 index 522d9e0e4b565..06d77b61ab828 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 @@ -5,13 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_DSC_AUX_FOR_PORT], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ], [ drm_dp_mst_dsc_aux_for_port(NULL); ], [drm_dp_mst_dsc_aux_for_port], [drivers/gpu/drm/drm_dp_mst_topology.c], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-port-full-pbn.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-port-full-pbn.m4 index dc2ce8bd06835..e45e020edc7fc 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-port-full-pbn.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-port-full-pbn.m4 @@ -5,13 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_PORT_FULL_PBN], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ], [ struct drm_dp_mst_port *mst_port = NULL; mst_port->full_pbn = 0; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-port.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-port.m4 index a1f26ca53e149..c66ffa1496233 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-port.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-port.m4 @@ -5,13 +5,7 @@ dnl AC_DEFUN([AC_AMDGPU_DRM_DP_MST_POST_PASSTHROUGH_AUX], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ], [ struct drm_dp_mst_port *dp_mst_port = NULL; dp_mst_port->passthrough_aux = NULL; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 index 02dac4390e913..4e54d919e6a3c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-cbs.m4 @@ -4,13 +4,7 @@ dnl # drm/dp-mst-helper: Remove hotplug callback dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_HOTPLUG], [ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ], [ struct drm_dp_mst_topology_cbs *dp_mst_cbs = NULL; dp_mst_cbs->hotplug(NULL); @@ -30,13 +24,7 @@ dnl # drm/dp/mst: split connector registration into two parts (v2) dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_REGISTER_CONNECTOR], [ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ], [ struct drm_dp_mst_topology_cbs *dp_mst_cbs = NULL; dp_mst_cbs->register_connector(NULL); @@ -52,13 +40,7 @@ dnl # drm/dp_mst: Remove drm_dp_mst_topology_cbs.destroy_connector dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_DESTROY_CONNECTOR], [ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ], [ struct drm_dp_mst_topology_cbs *dp_mst_cbs = NULL; dp_mst_cbs->destroy_connector(NULL, NULL); @@ -74,13 +56,7 @@ dnl # drm/i915/dp_mst: Work around out-of-spec adapters filtering short pulses dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS_POLL_HPD_IRQ], [ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ], [ struct drm_dp_mst_topology_cbs *dp_mst_cbs = NULL; dp_mst_cbs->poll_hpd_irq(NULL); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-mgr-resume.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-mgr-resume.m4 index 961c150fe148e..3c491e182062e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-mgr-resume.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-mgr-resume.m4 @@ -5,13 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_RESUME], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ], [ int ret; ret = drm_dp_mst_topology_mgr_resume(NULL, 0); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 index 717d2d88653c3..5ac79129a86fe 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 @@ -5,13 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ], [ struct drm_dp_mst_topology_state * mst_state = NULL; mst_state->total_avail_slots = 0; @@ -30,13 +24,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ], [ struct drm_dp_mst_topology_state * mst_state = NULL; struct list_head payloads; @@ -56,13 +44,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ], [ struct drm_dp_mst_topology_state * mst_state = NULL; int pbn_div; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 index cf4afe7538011..6de9a34aa627d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology.m4 @@ -15,13 +15,7 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY], [ dnl # AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ], [ drm_dp_mst_get_port_malloc(NULL); drm_dp_mst_put_port_malloc(NULL); @@ -36,13 +30,7 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY], [ dnl # AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ], [ drm_dp_mst_connector_early_unregister(NULL, NULL); drm_dp_mst_connector_late_register(NULL, NULL); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 index 27b63066be2dc..f09bb93dd8a35 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 @@ -5,13 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_SEND_REAL_EDID_CHECKSUM], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_HELPER_H) - #include - #else - #include - #endif + #include ], [ drm_dp_send_real_edid_checksum(NULL, 0); ], [drm_dp_send_real_edid_checksum], [drivers/gpu/drm/drm_dp_helper.c], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-driver-feature.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-driver-feature.m4 index d10e0fcde3942..e480396741ffe 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-driver-feature.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-driver-feature.m4 @@ -9,10 +9,7 @@ AC_DEFUN([AC_AMDGPU_DRM_DRIVER_FEATURE], [ dnl # AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DRMP_H - struct vm_area_struct; #include - #endif #include ],[ int _ = DRIVER_SYNCOBJ_TIMELINE; @@ -28,10 +25,7 @@ AC_DEFUN([AC_AMDGPU_DRM_DRIVER_FEATURE], [ dnl # AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DRMP_H - struct vm_area_struct; #include - #endif #include ],[ int _ = DRIVER_IRQ_SHARED; @@ -47,10 +41,7 @@ AC_DEFUN([AC_AMDGPU_DRM_DRIVER_FEATURE], [ dnl # AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DRMP_H - struct vm_area_struct; #include - #endif #include ],[ int _ = DRIVER_PRIME; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-open-object.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-open-object.m4 index 6631ba066edcf..0030f68fac152 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-open-object.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-open-object.m4 @@ -15,12 +15,8 @@ AC_DEFUN([AC_AMDGPU_DRM_DRIVER_GEM_OPEN_OBJECT], [ dnl # commit v5.9-rc5-1077-gd693def4fd1c dnl # drm: Remove obsolete GEM and PRIME callbacks from struct drm_driver AC_KERNEL_TRY_COMPILE([ - struct vm_area_struct; - #ifdef HAVE_DRM_DRMP_H #include - #else #include - #endif ],[ struct drm_driver *drv = NULL; drv->gem_open_object = NULL; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-prime-res-obj.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-prime-res-obj.m4 index cf63fed2c4727..226e89eebe85c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-prime-res-obj.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-prime-res-obj.m4 @@ -5,12 +5,8 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DRIVER_GEM_PRIME_RES_OBJ], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DRMP_H - struct vm_area_struct; #include - #else #include - #endif ], [ struct drm_driver *drv = NULL; drv->gem_prime_res_obj(NULL); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-fill-info.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-fill-info.m4 index bf7fcc83d14df..7eddabe7c8387 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-fill-info.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-fb-helper-fill-info.m4 @@ -5,10 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_FB_HELPER_FILL_INFO], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DRMP_H - struct vm_area_struct; #include - #endif #include ], [ drm_fb_helper_fill_info(NULL, NULL, NULL); diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-hdcp-update-content-protection.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-hdcp-update-content-protection.m4 index e79473b4902ab..55570026acaff 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-hdcp-update-content-protection.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-hdcp-update-content-protection.m4 @@ -5,12 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #ifdef HAVE_DRM_DISPLAY_DRM_HDCP_H - #include - #include - #else #include - #endif ], [ drm_hdcp_update_content_protection(NULL, 0); ], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-up-update-payload-part1-start-slot-arg.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-up-update-payload-part1-start-slot-arg.m4 index 7839b7b00baee..1b341003bb985 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-up-update-payload-part1-start-slot-arg.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-up-update-payload-part1-start-slot-arg.m4 @@ -5,13 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_UPDATE_PAYLOAD_PART1_START_SLOT_ARG], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ], [ drm_dp_update_payload_part1(NULL, 0); ], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr.m4 index 06cdbe40de8cf..c674432e635f2 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr.m4 @@ -5,13 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_BASE], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif #include ], [ struct drm_dp_mst_topology_mgr *mst_mgr = 0; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr_init.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr_init.m4 index 66d1beb0b8a34..98d2982594b7c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr_init.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dp_mst_topology_mgr_init.m4 @@ -5,13 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_INIT], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) - #include - #elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) - #include - #else #include - #endif ], [ drm_dp_mst_topology_mgr_init(NULL, (struct drm_device *)NULL, NULL, 0, 0, 0, 0, 0); ], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dsc_compute_rc_parameters.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dsc_compute_rc_parameters.m4 index 57d179067d66b..a6f72c8fe6ba9 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_dsc_compute_rc_parameters.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dsc_compute_rc_parameters.m4 @@ -5,11 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DSC_COMPUTE_RC_PARAMETERS], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DSC_HELPER_H) - #include - #else - #include - #endif + #include ], [ drm_dsc_compute_rc_parameters(NULL); ], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dsc_config.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dsc_config.m4 index c5c3c2c4418bb..e10e43c6dfe6c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_dsc_config.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dsc_config.m4 @@ -5,11 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DSC_CONFIG_SIMPLE_422], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DSC_H) - #include - #else #include - #endif ], [ struct drm_dsc_config *conf = NULL; conf->simple_422 = true; diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dsc_pps_payload_pack.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dsc_pps_payload_pack.m4 index 624e489e45e3a..b85668160976c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_dsc_pps_payload_pack.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dsc_pps_payload_pack.m4 @@ -5,11 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DSC_PPS_PAYLOAD_PACK], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #if defined(HAVE_DRM_DISPLAY_DRM_DSC_HELPER_H) - #include - #else #include - #endif ], [ drm_dsc_pps_payload_pack(NULL, NULL); ], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_fb_helper_init.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_fb_helper_init.m4 index 8c0d4b9e932ea..5bbcaa354dfde 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_fb_helper_init.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_fb_helper_init.m4 @@ -5,9 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_FB_HELPER_INIT], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ - #ifdef HAVE_DRM_DRMP_H #include - #endif #include ], [ drm_fb_helper_init(NULL, NULL); @@ -20,9 +18,7 @@ AC_DEFUN([AC_AMDGPU_DRM_FB_HELPER_INIT], [ dnl # drm: Rely on mode_config data for fb_helper initialization dnl # AC_KERNEL_TRY_COMPILE_SYMBOL([ - #ifdef HAVE_DRM_DRMP_H #include - #endif #include ], [ drm_fb_helper_init(NULL, NULL, 0); diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 index 7fd86cef1e099..91b36b22a7824 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel_single_target.m4 @@ -22,6 +22,9 @@ AC_DEFUN([AC_KERNEL_SINGLE_TARGET_CFLAGS], [ -e '/-I/p; /-include/p; /-isystem/p; /-D/p' | \ xargs) + CFLAGS=$(echo $CFLAGS | \ + sed -e "s|nostdinc|nostdinc -I../tiny_wrapper/include|") + AC_SUBST(CC) AC_SUBST(CFLAGS) AC_SUBST(CPPFLAGS) diff --git a/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drmP.h b/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drmP.h new file mode 100644 index 0000000000000..c616e0e2c1798 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drmP.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DRMP_H_H_ +#define _KCL_HEADER_DRMP_H_H_ + +#ifdef HAVE_DRM_DRMP_H +struct vm_area_struct; +#include_next +#endif + +#endif diff --git a/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_aperture.h b/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_aperture.h new file mode 100644 index 0000000000000..9197d9538fc69 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_aperture.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DRM_APERTURE_H_H_ +#define _KCL_HEADER_DRM_APERTURE_H_H_ + +#if defined(HAVE_DRM_DRM_APERTURE_H) +#include_next +#endif + +#endif diff --git a/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_dp_helper.h b/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_dp_helper.h new file mode 100644 index 0000000000000..820228761e24b --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_dp_helper.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DISPLAY_DRM_DP_HELPER_H_H_ +#define _KCL_HEADER_DISPLAY_DRM_DP_HELPER_H_H_ + +#if defined(HAVE_DRM_DISPLAY_DRM_DP_HELPER_H) +#include +#elif defined(HAVE_DRM_DP_DRM_DP_HELPER_H) +#include +#else +#include_next +#endif + +#endif + diff --git a/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_dp_mst_helper.h b/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_dp_mst_helper.h new file mode 100644 index 0000000000000..8a1cf0f4f9e33 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_dp_mst_helper.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DISPLAY_DRM_DP_MST_HELPER_H_H_ +#define _KCL_HEADER_DISPLAY_DRM_DP_MST_HELPER_H_H_ + +#if defined(HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H) +#include +#elif defined(HAVE_DRM_DP_DRM_DP_MST_HELPER_H) +#include +#else +#include_next +#endif + +#endif + diff --git a/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_dsc.h b/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_dsc.h new file mode 100644 index 0000000000000..dfc77f48cef83 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_dsc.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DISPLAY_DRM_DSC_H_H_ +#define _KCL_HEADER_DISPLAY_DRM_DSC_H_H_ + + +#if defined(HAVE_DRM_DISPLAY_DRM_DSC_HELPER_H) +#include +#endif + +#if defined(HAVE_DRM_DISPLAY_DRM_DSC_H) +#include +#else +#include_next +#endif + +#endif + diff --git a/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_hdcp.h b/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_hdcp.h new file mode 100644 index 0000000000000..309ffe3820d70 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/tiny_wrapper/include/drm/drm_hdcp.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DRM_DISPLAY_HDCP_H_INCLUDED_H_ +#define _KCL_HEADER_DRM_DISPLAY_HDCP_H_INCLUDED_H_ + +#ifdef HAVE_DRM_DISPLAY_DRM_HDCP_H +#include +#include +#else +#include_next +#endif + +#endif From f0da8171f1bbe818bb4aa503485c2afed67f4bac Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 1 Aug 2023 14:43:21 +0800 Subject: [PATCH 1060/1868] drm/amdkcl: fake totalram_pages() It's caused by 83c53bcd07ebbd0dd213049a5abd799dee842775 "drm/amd: Disable S/G for APUs when 64GB or more host memory" Signed-off-by: Bob Zhou Reviewed-by: Ma Jun --- drivers/gpu/drm/amd/amdkcl/kcl_mm.c | 9 +++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/totalram_pages.m4 | 17 +++++++++++++++++ include/kcl/kcl_mm.h | 8 ++++++++ 5 files changed, 38 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/totalram_pages.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_mm.c b/drivers/gpu/drm/amd/amdkcl/kcl_mm.c index 637ecefbb9773..6357e5db55df3 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_mm.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_mm.c @@ -36,6 +36,11 @@ extern struct kmem_cache *(*_kcl_kmalloc_slab)(size_t size, gfp_t flags); #endif #endif /* HAVE_KMALLOC_SIZE_ROUNDUP */ +#ifndef HAVE_TOTALRAM_PAGES +unsigned long *_kcl_totalram_pages; +EXPORT_SYMBOL(_kcl_totalram_pages); +#endif /* HAVE_TOTALRAM_PAGES */ + void amdkcl_mm_init(void) { #ifndef HAVE_MMPUT_ASYNC @@ -47,4 +52,8 @@ void amdkcl_mm_init(void) _kcl_kmalloc_slab = amdkcl_fp_setup("kmalloc_slab", NULL); #endif #endif + +#ifndef HAVE_TOTALRAM_PAGES + _kcl_totalram_pages = (unsigned long *) amdkcl_fp_setup("totalram_pages", NULL); +#endif } diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 58563f4ab3706..22e1afa78e1dd 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1004,6 +1004,9 @@ /* sysfs_emit() and sysfs_emit_at() are available */ #define HAVE_SYSFS_EMIT 1 +/* totalram_pages() is available */ +#define HAVE_TOTALRAM_PAGES 1 + /* interval_tree_insert have struct rb_root_cached */ #define HAVE_TREE_INSERT_HAVE_RB_ROOT_CACHED 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index cc29352f1c0be..1a35c42fc80e2 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -181,6 +181,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_CANCEL_WORK AC_AMDGPU_DMA_FENCE_IS_CONTAINER AC_AMDGPU_STR_YES_NO + AC_AMDGPU_TOTALRAM_PAGES AC_AMDGPU_DMA_FENCE_CHAIN_CONTAINED AC_AMDGPU_DRM_GEM_OBJECT_FUNCS_VMAP_HAS_IOSYS_MAP_ARG AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_BASE diff --git a/drivers/gpu/drm/amd/dkms/m4/totalram_pages.m4 b/drivers/gpu/drm/amd/dkms/m4/totalram_pages.m4 new file mode 100644 index 0000000000000..f57daa513df71 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/totalram_pages.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # v4.20-6506-gca79b0c211af +dnl # mm: convert totalram_pages and totalhigh_pages variables to atomic +dnl # +AC_DEFUN([AC_AMDGPU_TOTALRAM_PAGES], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + unsigned long ret; + ret = totalram_pages(); + ], [ + AC_DEFINE(HAVE_TOTALRAM_PAGES, 1, + [totalram_pages() is available]) + ]) + ]) +]) diff --git a/include/kcl/kcl_mm.h b/include/kcl/kcl_mm.h index 9151bdbed8785..892cd2805e432 100644 --- a/include/kcl/kcl_mm.h +++ b/include/kcl/kcl_mm.h @@ -128,4 +128,12 @@ static inline bool want_init_on_free(void) } #endif +#ifndef HAVE_TOTALRAM_PAGES +extern unsigned long *_kcl_totalram_pages; +static inline unsigned long totalram_pages(void) +{ + return *_kcl_totalram_pages; +} +#endif /* HAVE_TOTALRAM_PAGES */ + #endif /* AMDKCL_MM_H */ From 77154de590e4d17b7b711d58b9c5470af9f56aeb Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 3 Aug 2023 14:08:16 +0800 Subject: [PATCH 1061/1868] drm/amdkcl: fix 'totalram_pages' redeclared as different kind of symbol cleanup _kcl_totalram_pages symbol and replace totalram_pages to _totalram_pages Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/kcl_mm.c | 9 --------- include/kcl/kcl_mm.h | 8 +++++--- 2 files changed, 5 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_mm.c b/drivers/gpu/drm/amd/amdkcl/kcl_mm.c index 6357e5db55df3..637ecefbb9773 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_mm.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_mm.c @@ -36,11 +36,6 @@ extern struct kmem_cache *(*_kcl_kmalloc_slab)(size_t size, gfp_t flags); #endif #endif /* HAVE_KMALLOC_SIZE_ROUNDUP */ -#ifndef HAVE_TOTALRAM_PAGES -unsigned long *_kcl_totalram_pages; -EXPORT_SYMBOL(_kcl_totalram_pages); -#endif /* HAVE_TOTALRAM_PAGES */ - void amdkcl_mm_init(void) { #ifndef HAVE_MMPUT_ASYNC @@ -52,8 +47,4 @@ void amdkcl_mm_init(void) _kcl_kmalloc_slab = amdkcl_fp_setup("kmalloc_slab", NULL); #endif #endif - -#ifndef HAVE_TOTALRAM_PAGES - _kcl_totalram_pages = (unsigned long *) amdkcl_fp_setup("totalram_pages", NULL); -#endif } diff --git a/include/kcl/kcl_mm.h b/include/kcl/kcl_mm.h index 892cd2805e432..188cff38d5db6 100644 --- a/include/kcl/kcl_mm.h +++ b/include/kcl/kcl_mm.h @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -129,11 +130,12 @@ static inline bool want_init_on_free(void) #endif #ifndef HAVE_TOTALRAM_PAGES -extern unsigned long *_kcl_totalram_pages; -static inline unsigned long totalram_pages(void) +extern unsigned long totalram_pages; +static inline unsigned long _kcl_totalram_pages(void) { - return *_kcl_totalram_pages; + return totalram_pages; } +#define totalram_pages _kcl_totalram_pages #endif /* HAVE_TOTALRAM_PAGES */ #endif /* AMDKCL_MM_H */ From 3c2805940c9edad3d271dfdc270ecc9e5e7cdc8e Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Wed, 2 Aug 2023 13:53:34 +0800 Subject: [PATCH 1062/1868] drm/amdkcl: Fix the compile warnnings in m4 files Fix the compile warnnings of "-Wunused-variable" and "-Wuninitialized" in m4 files Signed-off-by: Ma Jun Reviewed-by: Bob Zhou --- .../gpu/drm/amd/dkms/m4/amd_iommu_invalidate_ctx.m4 | 7 +++++-- drivers/gpu/drm/amd/dkms/m4/dma-fence-chain.m4 | 3 ++- drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 | 4 ++-- drivers/gpu/drm/amd/dkms/m4/drm-driver-feature.m4 | 9 ++++++--- drivers/gpu/drm/amd/dkms/m4/drm_format_info.m4 | 10 +++++----- drivers/gpu/drm/amd/dkms/m4/ltr_path.m4 | 2 +- drivers/gpu/drm/amd/dkms/m4/memremap-enum.m4 | 5 +++-- drivers/gpu/drm/amd/dkms/m4/mm-kmalloc_size_roundup.m4 | 2 +- drivers/gpu/drm/amd/dkms/m4/str_yes_no.m4 | 3 ++- drivers/gpu/drm/amd/dkms/m4/type--poll-t.m4 | 3 ++- drivers/gpu/drm/amd/dkms/m4/want_init_on_free.m4 | 3 ++- drivers/gpu/drm/amd/dkms/m4/ww_mutex_trylock.m4 | 3 ++- 12 files changed, 33 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/amd_iommu_invalidate_ctx.m4 b/drivers/gpu/drm/amd/dkms/m4/amd_iommu_invalidate_ctx.m4 index ff2bf9c8949ad..7255ba02bca92 100644 --- a/drivers/gpu/drm/amd/dkms/m4/amd_iommu_invalidate_ctx.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/amd_iommu_invalidate_ctx.m4 @@ -7,8 +7,11 @@ AC_DEFUN([AC_AMDGPU_AMD_IOMMU_INVALIDATE_CTX], [ AC_KERNEL_TRY_COMPILE([ #include ], [ - void (*f)(struct pci_dev *pdev, u32 pasid); - amd_iommu_invalidate_ctx callback = f; + struct pci_dev *pdev = NULL; + u32 pasid = 0; + amd_iommu_invalidate_ctx callback = NULL; + + callback(pdev, pasid); ], [ AC_DEFINE(HAVE_AMD_IOMMU_INVALIDATE_CTX_PASID_U32, 1, [amd_iommu_invalidate_ctx take arg type of pasid as u32]) diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-fence-chain.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-fence-chain.m4 index 7867a6283d95f..1627d69677f9e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/dma-fence-chain.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/dma-fence-chain.m4 @@ -24,7 +24,8 @@ AC_DEFUN([AC_AMDGPU_DMA_FENCE_CHAIN_STRUCT], [ AC_KERNEL_TRY_COMPILE([ #include ], [ - struct dma_fence_chain *chain = NULL; + struct dma_fence_chain *chain; + chain = NULL; ], [ AC_DEFINE(HAVE_STRUCT_DMA_FENCE_CHAIN, 1, [struct dma_fence_chain is available]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 index 2e5156f632700..c0441f45a7861 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-atomic-funcs.m4 @@ -40,11 +40,11 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_ATOMIC_RELEASE_VCPI_SLOTS], [ #include ],[ int ret; - struct drm_dp_mst_port *port; + struct drm_dp_mst_port *port = NULL; ret = drm_dp_atomic_release_vcpi_slots(NULL, NULL, port); ],[ AC_DEFINE(HAVE_DRM_DP_ATOMIC_RELEASE_VCPI_SLOTS_MST_PORT, 1, - [drm_dp_atomic_release_vcpi_slots() with drm_dp_mst_port argument is available]) + [drm_dp_atomic_release_vcpi_slots() with drm_dp_mst_port argument is available]) ]) ]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-driver-feature.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-driver-feature.m4 index e480396741ffe..5ca66e8289bc1 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-driver-feature.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-driver-feature.m4 @@ -12,7 +12,8 @@ AC_DEFUN([AC_AMDGPU_DRM_DRIVER_FEATURE], [ #include #include ],[ - int _ = DRIVER_SYNCOBJ_TIMELINE; + int flag; + flag = DRIVER_SYNCOBJ_TIMELINE; ],[ AC_DEFINE(HAVE_DRM_DRV_DRIVER_SYNCOBJ_TIMELINE, 1, [ drm_driver_feature DRIVER_SYNCOBJ_TIMELINE is available]) @@ -28,7 +29,8 @@ AC_DEFUN([AC_AMDGPU_DRM_DRIVER_FEATURE], [ #include #include ],[ - int _ = DRIVER_IRQ_SHARED; + int flag; + flag = DRIVER_IRQ_SHARED; ],[ AC_DEFINE(HAVE_DRM_DRV_DRIVER_IRQ_SHARED, 1, [ drm_driver_feature DRIVER_IRQ_SHARED is available]) @@ -44,7 +46,8 @@ AC_DEFUN([AC_AMDGPU_DRM_DRIVER_FEATURE], [ #include #include ],[ - int _ = DRIVER_PRIME; + int flag; + flag = DRIVER_PRIME; ],[ AC_DEFINE(HAVE_DRM_DRV_DRIVER_PRIME, 1, [ drm_driver_feature DRIVER_PRIME is available]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_format_info.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_format_info.m4 index 95a45563d402e..54d06ba68400f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_format_info.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_format_info.m4 @@ -7,11 +7,11 @@ AC_DEFUN([AC_AMDGPU_DRM_FORMAT_INFO], [ AC_KERNEL_TRY_COMPILE([ #include ], [ - struct drm_format_info format = { - .format = DRM_FORMAT_XRGB16161616F, - .block_w = {0}, - .block_h = {0}, - }; + struct drm_format_info format; + + format.format = DRM_FORMAT_XRGB16161616F; + format.block_w[0] = 0; + format.block_h[0] = 0; ], [ AC_DEFINE(HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED, 1, [drm_format_info.block_w and rm_format_info.block_h is available]) diff --git a/drivers/gpu/drm/amd/dkms/m4/ltr_path.m4 b/drivers/gpu/drm/amd/dkms/m4/ltr_path.m4 index a629dac5f4aad..bb3cf8a0beff9 100644 --- a/drivers/gpu/drm/amd/dkms/m4/ltr_path.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/ltr_path.m4 @@ -8,7 +8,7 @@ AC_DEFUN([AC_AMDGPU_PCI_DEV_LTR_PATH], [ AC_KERNEL_TRY_COMPILE([ #include ], [ - struct pci_dev *dev; + struct pci_dev *dev = NULL; dev->ltr_path = 0; ], [ AC_DEFINE(HAVE_PCI_DEV_LTR_PATH, 1, diff --git a/drivers/gpu/drm/amd/dkms/m4/memremap-enum.m4 b/drivers/gpu/drm/amd/dkms/m4/memremap-enum.m4 index 786ce2c5590ac..53d34285e3b83 100644 --- a/drivers/gpu/drm/amd/dkms/m4/memremap-enum.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/memremap-enum.m4 @@ -11,8 +11,9 @@ AC_DEFUN([AC_AMDGPU_MEMORY_DEVICE_COHERENT], [ #include #include ], [ - int v = MEMORY_DEVICE_COHERENT; - int w = MIGRATE_VMA_SELECT_DEVICE_COHERENT; + int v, w; + v = MEMORY_DEVICE_COHERENT; + w = MIGRATE_VMA_SELECT_DEVICE_COHERENT; ], [ AC_DEFINE(HAVE_DEVICE_COHERENT, 1, [MEMORY_DEVICE_COHERENT is availablea]) diff --git a/drivers/gpu/drm/amd/dkms/m4/mm-kmalloc_size_roundup.m4 b/drivers/gpu/drm/amd/dkms/m4/mm-kmalloc_size_roundup.m4 index ab6586797229a..108c7086638bd 100644 --- a/drivers/gpu/drm/amd/dkms/m4/mm-kmalloc_size_roundup.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/mm-kmalloc_size_roundup.m4 @@ -7,7 +7,7 @@ AC_DEFUN([AC_AMDGPU_MM_KMALLOC_SIZE_ROUNDUP], [ AC_KERNEL_TRY_COMPILE([ #include ], [ - size_t a, b; + size_t a, b = 0; a = kmalloc_size_roundup(b); ], [ AC_DEFINE(HAVE_KMALLOC_SIZE_ROUNDUP, 1, diff --git a/drivers/gpu/drm/amd/dkms/m4/str_yes_no.m4 b/drivers/gpu/drm/amd/dkms/m4/str_yes_no.m4 index 9ca6f08ae00e7..5aefabf94021b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/str_yes_no.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/str_yes_no.m4 @@ -7,7 +7,8 @@ AC_DEFUN([AC_AMDGPU_STR_YES_NO], [ AC_KERNEL_TRY_COMPILE([ #include ], [ - const char *str = str_yes_no(true); + const char *str; + str = str_yes_no(true); ], [ AC_DEFINE(HAVE_STR_YES_NO, 1, [str_yes_no() is defined]) diff --git a/drivers/gpu/drm/amd/dkms/m4/type--poll-t.m4 b/drivers/gpu/drm/amd/dkms/m4/type--poll-t.m4 index a5744a51a8ffb..3ac6f9d5a31ea 100644 --- a/drivers/gpu/drm/amd/dkms/m4/type--poll-t.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/type--poll-t.m4 @@ -7,7 +7,8 @@ AC_DEFUN([AC_AMDGPU_TYPE__POLL_T], [ AC_KERNEL_TRY_COMPILE([ #include ],[ - __poll_t mask = 0; + __poll_t mask; + mask = 0; ],[ AC_DEFINE(HAVE_TYPE__POLL_T, 1, [__poll_t is available]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/want_init_on_free.m4 b/drivers/gpu/drm/amd/dkms/m4/want_init_on_free.m4 index 8503b32aeee1e..47463793e94b1 100644 --- a/drivers/gpu/drm/amd/dkms/m4/want_init_on_free.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/want_init_on_free.m4 @@ -7,7 +7,8 @@ AC_DEFUN([AC_AMDGPU_WANT_INIT_ON_FREE], [ AC_KERNEL_TRY_COMPILE([ #include ], [ - bool r = want_init_on_free(); + bool r; + r = want_init_on_free(); ], [ AC_DEFINE(HAVE_WANT_INIT_ON_FREE, 1, [want_init_on_free() is available]) diff --git a/drivers/gpu/drm/amd/dkms/m4/ww_mutex_trylock.m4 b/drivers/gpu/drm/amd/dkms/m4/ww_mutex_trylock.m4 index e3018a1b798e0..9d87289b3bfc8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/ww_mutex_trylock.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/ww_mutex_trylock.m4 @@ -7,7 +7,8 @@ AC_DEFUN([AC_AMDGPU_WW_MUTEX_TRYLOCK_CONTEXT_ARG], [ AC_KERNEL_TRY_COMPILE([ #include ], [ - int r = ww_mutex_trylock(NULL, NULL); + int r; + r = ww_mutex_trylock(NULL, NULL); ], [ AC_DEFINE(HAVE_WW_MUTEX_TRYLOCK_CONTEXT_ARG, 1, [ww_mutex_trylock() has context arg]) From d11b2d2a4c1d9c37ffd7709b7d43b2989556fe41 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 3 Aug 2023 11:08:58 +0800 Subject: [PATCH 1063/1868] drm/amdkcl: Optimize the code wrapped in the macro HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG [1] Fix the typo. [2] The fault function is not used here, so remove it. [3] Optimize the code wrapped in this macro. Only the vm_operations_struct->falut() function needs this macro Signed-off-by: Ma Jun Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 8 ----- drivers/gpu/drm/amd/dkms/config/config.h | 5 +-- .../drm/amd/dkms/m4/vm_operations_struct.m4 | 5 ++- drivers/gpu/drm/ttm/ttm_bo_vm.c | 35 ++----------------- include/drm/ttm/ttm_bo.h | 12 ++----- 5 files changed, 7 insertions(+), 58 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index fe997c0768f78..81b26eda28752 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -2585,11 +2585,7 @@ static vm_fault_t amdgpu_ttm_fault(struct vm_fault *vmf) #endif vm_fault_t ret; -#ifndef HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG - ret = ttm_bo_vm_reserve(bo, vmf, vma); -#else ret = ttm_bo_vm_reserve(bo, vmf); -#endif if (ret) return ret; @@ -2597,12 +2593,8 @@ static vm_fault_t amdgpu_ttm_fault(struct vm_fault *vmf) if (ret) goto unlock; -#ifndef HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG - ret = ttm_bo_vm_fault_reserved(vmf, vma, vma->vm_page_prot, TTM_BO_VM_NUM_PREFAULT); -#else ret = ttm_bo_vm_fault_reserved(vmf, vmf->vma->vm_page_prot, TTM_BO_VM_NUM_PREFAULT); -#endif if (ret == VM_FAULT_RETRY && !(vmf->flags & FAULT_FLAG_RETRY_NOWAIT)) return ret; diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 22e1afa78e1dd..f37a26f5fd2cb 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1040,10 +1040,7 @@ /* vmf_insert_pfn_prot() is available */ #define HAVE_VMF_INSERT_PFN_PROT 1 -/* vmf_insert_pfn_pud() is available */ -/* #undef HAVE_VMF_INSERT_PFN_PUD */ - -/* vm_fault->{address/vam} is available */ +/* vm_fault->{address/vma} is available */ #define HAVE_VM_FAULT_ADDRESS_VMA 1 /* vm_flags_{set, clear} is available */ diff --git a/drivers/gpu/drm/amd/dkms/m4/vm_operations_struct.m4 b/drivers/gpu/drm/amd/dkms/m4/vm_operations_struct.m4 index 9e01b9fb9f36b..111d006f1ac28 100644 --- a/drivers/gpu/drm/amd/dkms/m4/vm_operations_struct.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/vm_operations_struct.m4 @@ -7,14 +7,13 @@ AC_DEFUN([AC_AMDGPU_VM_OPERATIONS_STRUCT_FAULT], [ AC_KERNEL_TRY_COMPILE([ #include ], [ - int (*fault)(struct vm_area_struct *vma, struct vm_fault *vmf) = 0; struct vm_operations_struct *vm_ops = NULL; vm_ops->fault(NULL); ], [ AC_DEFINE(HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG, 1, [vm_operations_struct->fault() wants 1 arg]) AC_DEFINE(HAVE_VM_FAULT_ADDRESS_VMA, 1, - [vm_fault->{address/vam} is available]) + [vm_fault->{address/vma} is available]) ], [ dnl # dnl # commit v4.9-7746-g82b0f8c39a38 @@ -28,7 +27,7 @@ AC_DEFUN([AC_AMDGPU_VM_OPERATIONS_STRUCT_FAULT], [ ptest->vma = NULL; ], [ AC_DEFINE(HAVE_VM_FAULT_ADDRESS_VMA, 1, - [vm_fault->{address/vam} is available]) + [vm_fault->{address/vma} is available]) ]) ]) ]) diff --git a/drivers/gpu/drm/ttm/ttm_bo_vm.c b/drivers/gpu/drm/ttm/ttm_bo_vm.c index 98d61fd7d6ddd..edfbf49e55107 100644 --- a/drivers/gpu/drm/ttm/ttm_bo_vm.c +++ b/drivers/gpu/drm/ttm/ttm_bo_vm.c @@ -117,17 +117,10 @@ static unsigned long ttm_bo_io_mem_pfn(struct ttm_buffer_object *bo, * VM_FAULT_RETRY if blocking wait. * VM_FAULT_NOPAGE if blocking wait and retrying was not allowed. */ -#ifndef HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG -vm_fault_t ttm_bo_vm_reserve(struct ttm_buffer_object *bo, - struct vm_fault *vmf, - struct vm_area_struct *vma) -{ -#else vm_fault_t ttm_bo_vm_reserve(struct ttm_buffer_object *bo, struct vm_fault *vmf) { struct vm_area_struct *vma = vmf->vma; -#endif /* * Work around locking order reversal in fault / nopfn * between mmap_lock and bo_reserve: Perform a trylock operation @@ -190,19 +183,11 @@ EXPORT_SYMBOL(ttm_bo_vm_reserve); * VM_FAULT_OOM on out-of-memory * VM_FAULT_RETRY if retryable wait */ -#ifndef HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG -vm_fault_t ttm_bo_vm_fault_reserved(struct vm_fault *vmf, - struct vm_area_struct *vma, - pgprot_t prot, - pgoff_t num_prefault) -{ -#else vm_fault_t ttm_bo_vm_fault_reserved(struct vm_fault *vmf, pgprot_t prot, pgoff_t num_prefault) { struct vm_area_struct *vma = vmf->vma; -#endif struct ttm_buffer_object *bo = vma->vm_private_data; struct ttm_device *bdev = bo->bdev; unsigned long page_offset; @@ -314,14 +299,9 @@ static void ttm_bo_release_dummy_page(struct drm_device *dev, void *res) __free_page(dummy_page); } -#ifndef HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG -vm_fault_t ttm_bo_vm_dummy_page(struct vm_fault *vmf, struct vm_area_struct *vma, pgprot_t prot) -{ -#else vm_fault_t ttm_bo_vm_dummy_page(struct vm_fault *vmf, pgprot_t prot) { struct vm_area_struct *vma = vmf->vma; -#endif struct ttm_buffer_object *bo = vma->vm_private_data; struct drm_device *ddev = bo->base.dev; vm_fault_t ret = VM_FAULT_NOPAGE; @@ -365,30 +345,19 @@ vm_fault_t ttm_bo_vm_fault(struct vm_fault *vmf) vm_fault_t ret; int idx; -#ifndef HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG - ret = ttm_bo_vm_reserve(bo, vmf, vma); -#else ret = ttm_bo_vm_reserve(bo, vmf); -#endif if (ret) return ret; prot = vma->vm_page_prot; - if (drm_dev_enter(ddev, &idx)) { -#ifndef HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG - ret = ttm_bo_vm_fault_reserved(vmf, vma, prot, TTM_BO_VM_NUM_PREFAULT); -#else + if (drm_dev_enter(ddev, &idx)) { ret = ttm_bo_vm_fault_reserved(vmf, prot, TTM_BO_VM_NUM_PREFAULT); -#endif drm_dev_exit(idx); } else { -#ifndef HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG - ret = ttm_bo_vm_dummy_page(vmf, vma, prot); -#else ret = ttm_bo_vm_dummy_page(vmf, prot); -#endif } + if (ret == VM_FAULT_RETRY && !(vmf->flags & FAULT_FLAG_RETRY_NOWAIT)) return ret; diff --git a/include/drm/ttm/ttm_bo.h b/include/drm/ttm/ttm_bo.h index 168c0a3c57d88..d7d772e160110 100644 --- a/include/drm/ttm/ttm_bo.h +++ b/include/drm/ttm/ttm_bo.h @@ -428,23 +428,15 @@ int ttm_mem_evict_first(struct ttm_device *bdev, /* Default number of pre-faulted pages in the TTM fault handler */ #define TTM_BO_VM_NUM_PREFAULT 16 -#if defined(HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG) vm_fault_t ttm_bo_vm_reserve(struct ttm_buffer_object *bo, struct vm_fault *vmf); vm_fault_t ttm_bo_vm_fault_reserved(struct vm_fault *vmf, pgprot_t prot, pgoff_t num_prefault); + +#if defined(HAVE_VM_OPERATIONS_STRUCT_FAULT_1ARG) vm_fault_t ttm_bo_vm_fault(struct vm_fault *vmf); #else -vm_fault_t ttm_bo_vm_reserve(struct ttm_buffer_object *bo, - struct vm_fault *vmf, - struct vm_area_struct *vma); - -vm_fault_t ttm_bo_vm_fault_reserved(struct vm_fault *vmf, - struct vm_area_struct *vma, - pgprot_t prot, - pgoff_t num_prefault); - vm_fault_t ttm_bo_vm_fault(struct vm_area_struct *vma, struct vm_fault *vmf); #endif From b6fb4dd530f64547916fa8aa4ecef0a5c4bcb992 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 3 Aug 2023 13:10:47 +0800 Subject: [PATCH 1064/1868] drm/amdkcl: Modify compile CFLAGS for m4 files Removing "-Wno-error=uninitialized -Wno-error=unused-variable" to make these two kinds of warnning as error when compile m4 files. Signed-off-by: Ma Jun Reviewed-by: Bob Zhou Reviewed-by: Guchun Chen --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 1a35c42fc80e2..68bff1224ec80 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -419,7 +419,7 @@ AC_DEFUN([AC_KERNEL_COMPILE_MODULE_IFELSE], [ test "x$enable_linux_builtin" = xyes && kbuild_src_flag='KBUILD_SRC=' # override KBUILD_SRC test "x$enable_linux_builtin" = xyes && kbuild_workaround_flag='sub_make_done=' # override sub_make_done AS_IF( - [AC_TRY_COMMAND(make [$2] -C $LINUX_OBJ EXTRA_CFLAGS="-Werror -Wno-error=uninitialized -Wno-error=unused-variable -Wno-error=array-bounds" M=$PWD $kbuild_src_flag $kbuild_workaround_flag $kbuild_modpost_flag) >/dev/null && AC_TRY_COMMAND([$3])], + [AC_TRY_COMMAND(make [$2] -C $LINUX_OBJ EXTRA_CFLAGS="-Werror -Wno-error=array-bounds" M=$PWD $kbuild_src_flag $kbuild_workaround_flag $kbuild_modpost_flag) >/dev/null && AC_TRY_COMMAND([$3])], [$4], [_AC_MSG_LOG_CONFTEST m4_ifvaln([$5],[$5])] ) From 0c82db20ba17fe29560e1c188fc9048aa87b3432 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 8 Aug 2023 10:10:19 +0800 Subject: [PATCH 1065/1868] drm/amdkcl: wrap code under macro HAVE_STRUCT_DRM_CRTC_STATE_ASYNC_FLIP It's caused by 6fb5589425ee17f732aaae462532d5034b096212 "drm/amd/display: ensure async flips are only accepted for fast updates" Signed-off-by: Bob Zhou Reviewed-by: Ma Jun --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index fde5bf65b89cd..57d4ac81b81e7 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -11954,7 +11954,13 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, * Only allow async flips for fast updates that don't change * the FB pitch, the DCC state, rotation, etc. */ - if (new_crtc_state->async_flip && lock_and_validation_needed) { +#if defined(HAVE_STRUCT_DRM_CRTC_STATE_ASYNC_FLIP) + if (new_crtc_state->async_flip && +#else + if ((new_crtc_state->pageflip_flags & + DRM_MODE_PAGE_FLIP_ASYNC) != 0 && +#endif + lock_and_validation_needed) { drm_dbg_atomic(crtc->dev, "[CRTC:%d:%s] async flips are only supported for fast updates\n", crtc->base.id, crtc->name); From c404a84069cc7fe8fdc3fad5475880c4a599adee Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Fri, 11 Aug 2023 13:42:06 +0800 Subject: [PATCH 1066/1868] drm/amdkcl: Fix the uninitialized warning in m4 Signed-off-by: Ma Jun Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/m4/migrate_vma_fault_page.m4 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/migrate_vma_fault_page.m4 b/drivers/gpu/drm/amd/dkms/m4/migrate_vma_fault_page.m4 index 406fa50e310c5..f989b29503c45 100644 --- a/drivers/gpu/drm/amd/dkms/m4/migrate_vma_fault_page.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/migrate_vma_fault_page.m4 @@ -8,7 +8,7 @@ AC_DEFUN([AC_AMDGPU_MIGRATE_VMA_FAULT_PAGE], [ #include ], [ struct migrate_vma mig = {0}; - struct page *fault_page; + struct page *fault_page = NULL; mig.fault_page = fault_page; ], [ AC_DEFINE(HAVE_MIGRATE_VMA_FAULT_PAGE, 1, From f98fa45c26d128741230747703e1285895a7f3e0 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 14 Aug 2023 11:11:40 +0800 Subject: [PATCH 1067/1868] drm/amdkcl: fix file search path for m4 script Some file path has been modified, so update these file search path. Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/m4/cancel_work.m4 | 2 +- .../gpu/drm/amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 | 2 +- drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 | 2 +- drivers/gpu/drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 | 4 ++-- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/cancel_work.m4 b/drivers/gpu/drm/amd/dkms/m4/cancel_work.m4 index 063fdc3d8f23b..1f0558d0ade28 100644 --- a/drivers/gpu/drm/amd/dkms/m4/cancel_work.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/cancel_work.m4 @@ -9,7 +9,7 @@ AC_DEFUN([AC_AMDGPU_CANCEL_WORK], [ #include ], [ cancel_work(NULL); - ], [cancel_work], [], [ + ], [cancel_work], [kernel/workqueue.c], [ AC_DEFINE(HAVE_CANCEL_WORK, 1, [cancel_work() is available]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 index 1d4564270d065..c9127ca8d82c3 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-add-affected-dsc-crtcs.m4 @@ -9,7 +9,7 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_MST_ADD_AFFECTED_DSC_CRTCS], [ ], [ int ret; ret = drm_dp_mst_add_affected_dsc_crtcs(NULL, NULL); - ], [drm_dp_mst_dsc_aux_for_port], [drivers/gpu/drm/drm_dp_mst_topology.c], [ + ], [drm_dp_mst_dsc_aux_for_port], [drivers/gpu/drm/drm_dp_mst_topology.c drivers/gpu/drm/display/drm_dp_mst_topology.c], [ AC_DEFINE(HAVE_DRM_DP_MST_ADD_AFFECTED_DSC_CRTCS, 1, [drm_dp_mst_add_affected_dsc_crtcs() is available]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 index 06d77b61ab828..6d83fb019062d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-dsc-aux-for-port.m4 @@ -8,7 +8,7 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_MST_DSC_AUX_FOR_PORT], [ #include ], [ drm_dp_mst_dsc_aux_for_port(NULL); - ], [drm_dp_mst_dsc_aux_for_port], [drivers/gpu/drm/drm_dp_mst_topology.c], [ + ], [drm_dp_mst_dsc_aux_for_port], [drivers/gpu/drm/drm_dp_mst_topology.c drivers/gpu/drm/display/drm_dp_mst_topology.c], [ AC_DEFINE(HAVE_DRM_DP_MST_DSC_AUX_FOR_PORT, 1, [drm_dp_mst_dsc_aux_for_port() is available]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 index f09bb93dd8a35..44343cb753bbe 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-send-real-edid-checksum.m4 @@ -5,10 +5,10 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_SEND_REAL_EDID_CHECKSUM], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include + #include ], [ drm_dp_send_real_edid_checksum(NULL, 0); - ], [drm_dp_send_real_edid_checksum], [drivers/gpu/drm/drm_dp_helper.c], [ + ], [drm_dp_send_real_edid_checksum], [drivers/gpu/drm/drm_dp_helper.c drivers/gpu/drm/display/drm_dp_helper.c], [ AC_DEFINE(HAVE_DRM_DP_SEND_REAL_EDID_CHECKSUM, 1, [drm_dp_send_real_edid_checksum() is available]) ]) From dd084005de57a28856270bdc3cfa2bf08fb36c71 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Tue, 15 Aug 2023 17:31:22 +0800 Subject: [PATCH 1068/1868] drm/amdkcl: Fix error in HAVE_AMD_IOMMU_INVALIDATE_CTX_PASID_U32 check The original code can't detect the wrong param type. Signed-off-by: Ma Jun --- drivers/gpu/drm/amd/dkms/m4/amd_iommu_invalidate_ctx.m4 | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/amd_iommu_invalidate_ctx.m4 b/drivers/gpu/drm/amd/dkms/m4/amd_iommu_invalidate_ctx.m4 index 7255ba02bca92..3ddbe27c03284 100644 --- a/drivers/gpu/drm/amd/dkms/m4/amd_iommu_invalidate_ctx.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/amd_iommu_invalidate_ctx.m4 @@ -7,11 +7,10 @@ AC_DEFUN([AC_AMDGPU_AMD_IOMMU_INVALIDATE_CTX], [ AC_KERNEL_TRY_COMPILE([ #include ], [ - struct pci_dev *pdev = NULL; - u32 pasid = 0; - amd_iommu_invalidate_ctx callback = NULL; + void (*f)(struct pci_dev *pdev, u32 pasid) = NULL; + amd_iommu_invalidate_ctx callback; - callback(pdev, pasid); + callback = f; ], [ AC_DEFINE(HAVE_AMD_IOMMU_INVALIDATE_CTX_PASID_U32, 1, [amd_iommu_invalidate_ctx take arg type of pasid as u32]) From 639e3c4941d57b7e8bb2588b5717805fdca15152 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 16 Aug 2023 11:48:36 +0800 Subject: [PATCH 1069/1868] drm/amdkfd: Correct some spacing errors introduced in rebase process Signed-off-by: Asher Song Reviewd-by: Kent Russell --- drivers/gpu/drm/amd/amdkfd/Makefile | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 16 ++++++++-------- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/Makefile b/drivers/gpu/drm/amd/amdkfd/Makefile index e883770ade3f4..a0e88355c1e12 100644 --- a/drivers/gpu/drm/amd/amdkfd/Makefile +++ b/drivers/gpu/drm/amd/amdkfd/Makefile @@ -60,7 +60,7 @@ AMDKFD_FILES := $(AMDKFD_PATH)/kfd_module.o \ $(AMDKFD_PATH)/kfd_smi_events.o \ $(AMDKFD_PATH)/kfd_crat.o \ $(AMDKFD_PATH)/kfd_peerdirect.o \ - $(AMDKFD_PATH)/kfd_ipc.o \ + $(AMDKFD_PATH)/kfd_ipc.o \ $(AMDKFD_PATH)/kfd_trace.o \ $(AMDKFD_PATH)/kfd_spm.o \ $(AMDKFD_PATH)/kfd_debug.o diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index cdc2f62b22076..557486b82559a 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1741,17 +1741,17 @@ static int kfd_ioctl_export_dmabuf(struct file *filep, /* Place holder for deprecated DBG API */ static int kfd_ioctl_dbg_set_debug_trap_deprecated(struct file *filep, - struct kfd_process *p, void *data) + struct kfd_process *p, void *data) { - dev_dbg(kfd_device, "AMDKFD_IOC_DBG_TRAP is deprecated.\n"); - return -EINVAL; + dev_dbg(kfd_device, "AMDKFD_IOC_DBG_TRAP is deprecated.\n"); + return -EINVAL; } /* Place holder for deprecated CMA API */ static int kfd_ioctl_cross_memory_copy_deprecated(struct file *filep, - struct kfd_process *local_p, void *data) { - dev_dbg(kfd_device, "AMDKFD_IOC_CROSS_MEMORY_COPY is deprecated.\n"); - return -EINVAL; + struct kfd_process *local_p, void *data) { + dev_dbg(kfd_device, "AMDKFD_IOC_CROSS_MEMORY_COPY is deprecated.\n"); + return -EINVAL; } /* Handle requests for watching SMI events */ @@ -3432,8 +3432,8 @@ static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = { AMDKFD_IOCTL_DEF(AMDKFD_IOC_IPC_EXPORT_HANDLE, kfd_ioctl_ipc_export_handle, 0), - AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_TRAP_DEPRECATED, - kfd_ioctl_dbg_set_debug_trap_deprecated, 0), + AMDKFD_IOCTL_DEF(AMDKFD_IOC_DBG_TRAP_DEPRECATED, + kfd_ioctl_dbg_set_debug_trap_deprecated, 0), AMDKFD_IOCTL_DEF(AMDKFD_IOC_RLC_SPM, kfd_ioctl_rlc_spm, 0), From de1d0c26e41b14e1037dfe3e26ed7bf8845a4373 Mon Sep 17 00:00:00 2001 From: hongao Date: Tue, 15 Aug 2023 14:54:45 +0800 Subject: [PATCH 1070/1868] drm/amdgpu/gmc6: fix in case the PCI BAR is larger than the actual amount of vram [why] limit visible_vram_size to real_vram_size in case the PCI BAR is larger than the actual amount of vram. Signed-off-by: hongao Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c index d36725666b54c..101a143a5f93f 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c @@ -314,6 +314,8 @@ static int gmc_v6_0_mc_init(struct amdgpu_device *adev) adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); adev->gmc.visible_vram_size = adev->gmc.aper_size; + if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) + adev->gmc.visible_vram_size = adev->gmc.real_vram_size; /* set the gart size */ if (amdgpu_gart_size == -1) { From e8364d844eda80cc338741eb7fd5637f997d8211 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 16 Aug 2023 10:27:03 -0400 Subject: [PATCH 1071/1868] Revert "drm/amdgpu/gmc6: fix in case the PCI BAR is larger than the actual amount of vram" This reverts commit 6194534d7d8be15f3e4e718dad8bbd3ec6f58b1e. This is unnecessary since the visible size is already checked in amdgpu_gmc_vram_location(). Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c index 101a143a5f93f..d36725666b54c 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c @@ -314,8 +314,6 @@ static int gmc_v6_0_mc_init(struct amdgpu_device *adev) adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); adev->gmc.visible_vram_size = adev->gmc.aper_size; - if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) - adev->gmc.visible_vram_size = adev->gmc.real_vram_size; /* set the gart size */ if (amdgpu_gart_size == -1) { From 21468d83ee80e435acb7c749251b5e63f09724f0 Mon Sep 17 00:00:00 2001 From: Kenneth Feng Date: Wed, 23 Aug 2023 10:32:16 +0800 Subject: [PATCH 1072/1868] drm/amd/pm: workaround for the wrong ac power detection on smu 13.0.0 Workaround for the wrong ac power detection on smu 13.0.0. This is a temporary solution and will be dropped in the future. Signed-off-by: Kenneth Feng Reviewed-by: Evan Quan Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 3 +-- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 1 - 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c index e17466cc19522..3e2dab43832ad 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c @@ -1022,8 +1022,7 @@ static int smu_v13_0_process_pending_interrupt(struct smu_context *smu) { int ret = 0; - if (smu->dc_controlled_by_gpio && - smu_cmn_feature_is_enabled(smu, SMU_FEATURE_ACDC_BIT)) + if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_ACDC_BIT)) ret = smu_v13_0_allow_ih_interrupt(smu); return ret; diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c index a887ab945dfa2..c9639141792f4 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c @@ -3071,7 +3071,6 @@ static const struct pptable_funcs smu_v13_0_0_ppt_funcs = { .enable_mgpu_fan_boost = smu_v13_0_0_enable_mgpu_fan_boost, .get_power_limit = smu_v13_0_0_get_power_limit, .set_power_limit = smu_v13_0_0_set_power_limit, - .set_power_source = smu_v13_0_set_power_source, .get_power_profile_mode = smu_v13_0_0_get_power_profile_mode, .set_power_profile_mode = smu_v13_0_0_set_power_profile_mode, .run_btc = smu_v13_0_run_btc, From 19cab89c2d3775ca883b0d9371db0f6d40c15c06 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 16 Aug 2023 10:12:07 +0800 Subject: [PATCH 1073/1868] drm/amdkcl: drop the direct call for AC_KERNEL_CHECK_SYMBOL_EXPORT [why] To support distros systems, AC_KERNEL_CHECK_SYMBOL_EXPORT create symbol config entry by parsing Modules.symvers. But Modules.symvers is unavailable for intree build, so that the AC_KERNEL_CHECK_SYMBOL_EXPORT is invalid. [how] The AC_KERNEL_TRY_COMPILE_SYMBOL adds function signatures check base on AC_KERNEL_CHECK_SYMBOL_EXPORT. So modify all of AC_KERNEL_CHECK_SYMBOL_EXPORT to AC_KERNEL_TRY_COMPILE_SYMBOL and conduct function signatures check for all symbol config entries to support intree build. Signed-off-by: Bob Zhou Reviewed-by: Tim Huang --- .../dkms/m4/__drm_atomic_helper_crtc_reset.m4 | 8 ++- .../drm/amd/dkms/m4/__kthread-should-park.m4 | 6 +- .../dkms/m4/acpi_dev_get_first_match_dev.m4 | 7 +- .../drm/amd/dkms/m4/amd-iommu-pc-supported.m4 | 7 +- drivers/gpu/drm/amd/dkms/m4/debugfs_inode.m4 | 7 +- .../gpu/drm/amd/dkms/m4/down-read-killable.m4 | 11 ++-- ...nector-set-panel-orientation-with-quirk.m4 | 9 ++- .../gpu/drm/amd/dkms/m4/drm-gem-object-ref.m4 | 11 ++-- ...omic_helper_calc_timestamping_constants.m4 | 7 +- .../dkms/m4/drm_helper_force_disable_all.m4 | 6 +- ...rm_mode_create_hdmi_colorspace_property.m4 | 8 ++- drivers/gpu/drm/amd/dkms/m4/drm_prime.m4 | 9 ++- drivers/gpu/drm/amd/dkms/m4/drm_print_bits.m4 | 7 +- .../drm/amd/dkms/m4/drm_simple_kms_helper.m4 | 8 ++- .../drm/amd/dkms/m4/get-user-pages-remote.m4 | 66 +++++++++---------- .../drm/amd/dkms/m4/i2c_new_client_device.m4 | 7 +- .../gpu/drm/amd/dkms/m4/jiffies64_to_msecs.m4 | 6 +- .../drm/amd/dkms/m4/kallsyms-lookup-name.m4 | 8 ++- drivers/gpu/drm/amd/dkms/m4/mmput_async.m4 | 6 +- .../gpu/drm/amd/dkms/m4/pci_pr3_present.m4 | 6 +- drivers/gpu/drm/amd/dkms/m4/pxm_to_node.m4 | 7 +- .../gpu/drm/amd/dkms/m4/sched_set_fifo_low.m4 | 7 +- .../drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 | 10 +-- .../drm/amd/dkms/m4/synchronize-shrinkers.m4 | 11 ++-- drivers/gpu/drm/amd/dkms/m4/sysfs_emit.m4 | 11 ++-- .../drm/amd/dkms/m4/zone_device_page_init.m4 | 9 ++- 26 files changed, 169 insertions(+), 96 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/__drm_atomic_helper_crtc_reset.m4 b/drivers/gpu/drm/amd/dkms/m4/__drm_atomic_helper_crtc_reset.m4 index 637a0bc453cd7..532031624b3a1 100644 --- a/drivers/gpu/drm/amd/dkms/m4/__drm_atomic_helper_crtc_reset.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/__drm_atomic_helper_crtc_reset.m4 @@ -4,9 +4,11 @@ dnl # drm/atomic: Create __drm_atomic_helper_crtc_reset() for subclassing crtc_s dnl # AC_DEFUN([AC_AMDGPU___DRM_ATOMIC_HELPER_CRTC_RESET], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([__drm_atomic_helper_crtc_reset], - [drivers/gpu/drm/drm_atomic_state_helper.c], - [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + __drm_atomic_helper_crtc_reset(NULL, NULL); + ],[__drm_atomic_helper_crtc_reset], [drivers/gpu/drm/drm_atomic_state_helper.c],[ AC_DEFINE(HAVE___DRM_ATOMIC_HELPER_CRTC_RESET, 1, [__drm_atomic_helper_crtc_reset() is available]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/__kthread-should-park.m4 b/drivers/gpu/drm/amd/dkms/m4/__kthread-should-park.m4 index 2cb67699eef67..e4b111dff02e1 100644 --- a/drivers/gpu/drm/amd/dkms/m4/__kthread-should-park.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/__kthread-should-park.m4 @@ -4,7 +4,11 @@ dnl # kthread: Add __kthread_should_park() dnl # AC_DEFUN([AC_AMDGPU___KTHREAD_SHOULD_PARK], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([__kthread_should_park],[kernel/kthread.c],[ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + __kthread_should_park(NULL); + ],[__kthread_should_park],[kernel/kthread.c],[ AC_DEFINE(HAVE___KTHREAD_SHOULD_PARK, 1, [__kthread_should_park() is available]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/acpi_dev_get_first_match_dev.m4 b/drivers/gpu/drm/amd/dkms/m4/acpi_dev_get_first_match_dev.m4 index f83c2733ac2e1..5668a2d728b89 100644 --- a/drivers/gpu/drm/amd/dkms/m4/acpi_dev_get_first_match_dev.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/acpi_dev_get_first_match_dev.m4 @@ -4,8 +4,11 @@ dnl # ACPI / utils: Introduce acpi_dev_get_first_match_dev() helper dnl # AC_DEFUN([AC_AMDGPU_ACPI_DEV_GET_FIRST_MATCH_DEV], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([acpi_dev_get_first_match_dev], - [drivers/acpi/utils.c], [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + acpi_dev_get_first_match_dev(NULL, NULL, 0); + ],[acpi_dev_get_first_match_dev],[drivers/acpi/utils.c], [ AC_DEFINE(HAVE_ACPI_DEV_GET_FIRST_MATCH_DEV, 1, [acpi_dev_get_first_match_dev() is available]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/amd-iommu-pc-supported.m4 b/drivers/gpu/drm/amd/dkms/m4/amd-iommu-pc-supported.m4 index 67cbbec8cac3e..c42fcb583b362 100644 --- a/drivers/gpu/drm/amd/dkms/m4/amd-iommu-pc-supported.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/amd-iommu-pc-supported.m4 @@ -12,8 +12,11 @@ AC_DEFUN([AC_AMDGPU_AMD_IOMMU_PC_GET_MAX_BANKS], [ AC_DEFINE(HAVE_AMD_IOMMU_PC_GET_MAX_BANKS_DECLARED, 1, [amd_iommu_pc_get_max_banks() declared]) ], [ - AC_KERNEL_CHECK_SYMBOL_EXPORT([get_amd_iommu], - [drivers/iommu/amd/init.c], [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + get_amd_iommu(0); + ],[get_amd_iommu],[drivers/iommu/amd/init.c], [ AC_DEFINE(HAVE_AMD_IOMMU_PC_GET_MAX_BANKS_UINT, 1, [amd_iommu_pc_get_max_banks() arg is unsigned int]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/debugfs_inode.m4 b/drivers/gpu/drm/amd/dkms/m4/debugfs_inode.m4 index 3f4be7129b920..29b066233e0d4 100644 --- a/drivers/gpu/drm/amd/dkms/m4/debugfs_inode.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/debugfs_inode.m4 @@ -4,8 +4,11 @@ dnl # debugfs: Provide a file creation function dnl # that also takes an initial size AC_DEFUN([AC_AMDGPU_DEBUGFS_CREATE_FILE_SIZE], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([debugfs_create_file_size], - [fs/debugfs/inode.c], [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + debugfs_create_file_size(NULL, 0, NULL, NULL, NULL, 0); + ],[debugfs_create_file_size], [fs/debugfs/inode.c], [ AC_DEFINE(HAVE_DEBUGFS_CREATE_FILE_SIZE, 1, [debugfs_create_file_size() is available]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/down-read-killable.m4 b/drivers/gpu/drm/amd/dkms/m4/down-read-killable.m4 index 6de71b3c0a40d..7a74bd4d25889 100644 --- a/drivers/gpu/drm/amd/dkms/m4/down-read-killable.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/down-read-killable.m4 @@ -4,10 +4,13 @@ #dnl AC_DEFUN([AC_AMDGPU_DOWN_READ_KILLABLE], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT( - [down_read_killable], - [kernel/locking/rwsem.c], - [AC_DEFINE(HAVE_DOWN_READ_KILLABLE, 1, + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + int ret; + ret = down_read_killable(NULL); + ],[down_read_killable], [kernel/locking/rwsem.c],[ + AC_DEFINE(HAVE_DOWN_READ_KILLABLE, 1, [down_read_killable() is available])] ) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-connector-set-panel-orientation-with-quirk.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-connector-set-panel-orientation-with-quirk.m4 index 463767cb7e3a6..0ae5de382dec8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-connector-set-panel-orientation-with-quirk.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-connector-set-panel-orientation-with-quirk.m4 @@ -3,9 +3,12 @@ dnl # commit v5.5-rc2-1360-g69654c632d80 dnl # drm/connector: Split out orientation quirk detection (v2) dnl # AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_SET_PANEL_ORIENTATION_WITH_QUIRK], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([drm_connector_set_panel_orientation_with_quirk], - [drivers/gpu/drm/drm_connector.c], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + drm_connector_set_panel_orientation_with_quirk(NULL, 0, 0, 0); + ],[drm_connector_set_panel_orientation_with_quirk], [drivers/gpu/drm/drm_connector.c], [ AC_DEFINE(HAVE_DRM_CONNECTOR_SET_PANEL_ORIENTATION_WITH_QUIRK, 1, [drm_connector_set_panel_orientation_with_quirk() is available]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-gem-object-ref.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-gem-object-ref.m4 index c4d2a03ec81c0..36c0a786c849f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-gem-object-ref.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-gem-object-ref.m4 @@ -13,10 +13,13 @@ AC_DEFUN([AC_AMDGPU_DRM_GEM_OBJECT_PUT], [ AC_DEFINE(HAVE_DRM_GEM_OBJECT_PUT, 1, [drm_gem_object_put() is available]) - AC_KERNEL_CHECK_SYMBOL_EXPORT([drm_gem_object_put], - [drivers/gpu/drm/drm_gem.c], [ - AC_DEFINE(HAVE_DRM_GEM_OBJECT_PUT_SYMBOL, 1, - [drm_gem_object_put() is exported]) + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + drm_gem_object_put(NULL); + ],[drm_gem_object_put],[drivers/gpu/drm/drm_gem.c], [ + AC_DEFINE(HAVE_DRM_GEM_OBJECT_PUT_SYMBOL, 1, + [drm_gem_object_put() is exported]) ]) ]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_atomic_helper_calc_timestamping_constants.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_atomic_helper_calc_timestamping_constants.m4 index 79ab39b5802f3..7b6d31518fe3c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_atomic_helper_calc_timestamping_constants.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_atomic_helper_calc_timestamping_constants.m4 @@ -4,8 +4,11 @@ dnl # Extract drm_atomic_helper_calc_timestamping_constants() dnl # AC_DEFUN([AC_AMDGPU_DRM_ATOMIC_HELPER_CALC_TIMESTAMPING_CONSTANTS], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([drm_atomic_helper_calc_timestamping_constants], - [drivers/gpu/drm/drm_atomic_helper.c], [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + drm_atomic_helper_calc_timestamping_constants(NULL); + ],[drm_atomic_helper_calc_timestamping_constants], [drivers/gpu/drm/drm_atomic_helper.c], [ AC_DEFINE(HAVE_DRM_ATOMIC_HELPER_CALC_TIMESTAMPING_CONSTANTS, 1, [drm_atomic_helper_calc_timestamping_constants() is available]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_helper_force_disable_all.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_helper_force_disable_all.m4 index f52b3c10ccd43..69513e0cacc39 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_helper_force_disable_all.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_helper_force_disable_all.m4 @@ -7,7 +7,11 @@ dnl # drm: Move the legacy kms disable_all helper to crtc helpers dnl # AC_DEFUN([AC_AMDGPU_DRM_HELPER_FORCE_DISABLE_ALL], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([drm_helper_force_disable_all], [drivers/gpu/drm/drm_crtc_helper.c],[ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + drm_helper_force_disable_all(NULL); + ],[drm_helper_force_disable_all], [drivers/gpu/drm/drm_crtc_helper.c],[ AC_DEFINE(HAVE_DRM_HELPER_FORCE_DISABLE_ALL, 1, [drm_helper_force_disable_all() is available]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_mode_create_hdmi_colorspace_property.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_mode_create_hdmi_colorspace_property.m4 index 7a8fe049ac51b..ecc33db72dcbd 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_mode_create_hdmi_colorspace_property.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_mode_create_hdmi_colorspace_property.m4 @@ -4,8 +4,12 @@ dnl # drm: Rename HDMI colorspace property creation function dnl # AC_DEFUN([AC_AMDGPU_DRM_CONNECT_ATTACH_COLORSPACE_PROPERTY], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([drm_connector_attach_colorspace_property], [drivers/gpu/drm/drm_connector.c], [ - AC_DEFINE(HAVE_DRM_CONNECT_ATTACH_COLORSPACE_PROPERTY, 1, + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + drm_connector_attach_colorspace_property(NULL); + ],[drm_connector_attach_colorspace_property], [drivers/gpu/drm/drm_connector.c], [ + AC_DEFINE(HAVE_DRM_CONNECT_ATTACH_COLORSPACE_PROPERTY, 1, [drm_connector_attach_colorspace_property() is available]) ]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_prime.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_prime.m4 index 4a1160753c960..bae97886408be 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_prime.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_prime.m4 @@ -4,8 +4,13 @@ dnl # drm/prime: split array import functions v4 dnl # AC_DEFUN([AC_AMDGPU_DRM_PRIME_SG_TO_DMA_ADDR_ARRAY], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([drm_prime_sg_to_dma_addr_array], [drivers/gpu/drm/drm_prime.c], [ - AC_DEFINE(HAVE_DRM_PRIME_SG_TO_DMA_ADDR_ARRAY, 1, [drm_prime_sg_to_dma_addr_array() is available]) + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + drm_prime_sg_to_dma_addr_array(NULL, NULL, 0); + ],[drm_prime_sg_to_dma_addr_array], [drivers/gpu/drm/drm_prime.c], [ + AC_DEFINE(HAVE_DRM_PRIME_SG_TO_DMA_ADDR_ARRAY, 1, + [drm_prime_sg_to_dma_addr_array() is available]) ]) ]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_print_bits.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_print_bits.m4 index 62209f24b90e0..fb7266321075c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_print_bits.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_print_bits.m4 @@ -16,8 +16,11 @@ AC_DEFUN([AC_AMDGPU_DRM_PRINT_BITS], [ ], [ dnl # v5.3-rc1-622-g2dc5d44ccc5e dnl # drm: add drm_print_bits - AC_KERNEL_CHECK_SYMBOL_EXPORT([drm_print_bits], - [drivers/gpu/drm/drm_print.c], [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + drm_print_bits(NULL, 0, NULL, 0, 0); + ],[drm_print_bits], [drivers/gpu/drm/drm_print.c], [ AC_DEFINE(HAVE_DRM_PRINT_BITS, 1, [drm_print_bits() is available]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_simple_kms_helper.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_simple_kms_helper.m4 index 0ffcd218e5a99..7f8cf4e9ad0a1 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_simple_kms_helper.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_simple_kms_helper.m4 @@ -3,9 +3,11 @@ dnl # v5.6-rc2-359-g63170ac6f2e8 dnl # drm/simple-kms: Add drm_simple_encoder_{init,create}() dnl # AC_DEFUN([AC_AMDGPU_DRM_SIMPLE_ENCODER_INIT], [ - AC_KERNEL_CHECK_SYMBOL_EXPORT( - [drm_simple_encoder_init], - [drivers/gpu/drm/drm_simple_kms_helper.c],[ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + drm_simple_encoder_init(NULL, NULL, 0); + ],[drm_simple_encoder_init], [drivers/gpu/drm/drm_simple_kms_helper.c],[ AC_DEFINE(HAVE_DRM_SIMPLE_ENCODER_INIT, 1, [drm_simple_encoder is available]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/get-user-pages-remote.m4 b/drivers/gpu/drm/amd/dkms/m4/get-user-pages-remote.m4 index 8f70124da00f0..e2fe781b7d7dc 100644 --- a/drivers/gpu/drm/amd/dkms/m4/get-user-pages-remote.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/get-user-pages-remote.m4 @@ -1,53 +1,47 @@ AC_DEFUN([AC_AMDGPU_GET_USER_PAGES_REMOTE], [ AC_KERNEL_DO_BACKGROUND([ dnl # - dnl # v4.5-rc4-71-g1e9877902dc7 - dnl # mm/gup: Introduce get_user_pages_remote() + dnl # v5.8-12463-g64019a2e467a + dnl # mm/gup: remove task_struct pointer for all gup code dnl # - AC_KERNEL_CHECK_SYMBOL_EXPORT([get_user_pages_remote],[mm/gup.c], - [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + get_user_pages_remote(NULL, 0, 0, 0, NULL, NULL, NULL); + ], [get_user_pages_remote],[mm/gup.c],[ + AC_DEFINE(HAVE_GET_USER_PAGES_REMOTE_REMOVE_TASK_STRUCT, 1, + [get_user_pages_remote() remove task_struct pointer]) + ], [ dnl # - dnl # v5.8-12463-g64019a2e467a - dnl # mm/gup: remove task_struct pointer for all gup code + dnl # commit v4.9-7744-g5b56d49fc31d + dnl # mm: add locked parameter to get_user_pages_remote() dnl # - AC_KERNEL_TRY_COMPILE([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ #include ], [ - get_user_pages_remote(NULL, 0, 0, 0, NULL, NULL, NULL); - ], [ - AC_DEFINE(HAVE_GET_USER_PAGES_REMOTE_REMOVE_TASK_STRUCT, 1, - [get_user_pages_remote() remove task_struct pointer]) - ], [ + get_user_pages_remote(NULL, NULL, 0, 0, 0, NULL, NULL, NULL); + ], [get_user_pages_remote],[mm/gup.c],[ + AC_DEFINE(HAVE_GET_USER_PAGES_REMOTE_LOCKED, 1, + [get_user_pages_remote() wants locked parameter]) + ],[ dnl # - dnl # commit v4.9-7744-g5b56d49fc31d - dnl # mm: add locked parameter to get_user_pages_remote() + dnl # commit v4.8-14096-g9beae1ea8930 + dnl # mm: replace get_user_pages_remote() write/force parameters + dnl # with gup_flags dnl # - AC_KERNEL_TRY_COMPILE([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ #include ], [ - get_user_pages_remote(NULL, NULL, 0, 0, 0, NULL, NULL, NULL); - ], [ - AC_DEFINE(HAVE_GET_USER_PAGES_REMOTE_LOCKED, 1, - [get_user_pages_remote() wants locked parameter]) - ], [ - dnl # - dnl # commit v4.8-14096-g9beae1ea8930 - dnl # mm: replace get_user_pages_remote() write/force parameters - dnl # with gup_flags - dnl # - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - get_user_pages_remote(NULL, NULL, 0, 0, 0, NULL, NULL); - ], [ - AC_DEFINE(HAVE_GET_USER_PAGES_REMOTE_GUP_FLAGS, 1, - [get_user_pages_remote() wants gup_flags parameter]) - ],[ - AC_DEFINE(HAVE_GET_USER_PAGES_REMOTE_INTRODUCED, 1, - [get_user_pages_remote() is introduced with initial prototype]) - ]) + get_user_pages_remote(NULL, NULL, 0, 0, 0, NULL, NULL); + ], [get_user_pages_remote],[mm/gup.c],[ + AC_DEFINE(HAVE_GET_USER_PAGES_REMOTE_GUP_FLAGS, 1, + [get_user_pages_remote() wants gup_flags parameter]) + ],[ + AC_DEFINE(HAVE_GET_USER_PAGES_REMOTE_INTRODUCED, 1, + [get_user_pages_remote() is introduced with initial prototype]) ]) ]) ]) ]) ]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/i2c_new_client_device.m4 b/drivers/gpu/drm/amd/dkms/m4/i2c_new_client_device.m4 index cedd29e0fe70e..a4d3e37bfa38c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/i2c_new_client_device.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/i2c_new_client_device.m4 @@ -4,8 +4,11 @@ dnl # i2c: core: improve return value handling of i2c_new_device and i2c_new_dum dnl # AC_DEFUN([AC_AMDGPU_I2C_NEW_CLIENT_DEVICE], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([i2c_new_client_device], [drivers/i2c/i2c-core-base.c], - [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + i2c_new_client_device(NULL, NULL); + ],[i2c_new_client_device], [drivers/i2c/i2c-core-base.c],[ AC_DEFINE(HAVE_I2C_NEW_CLIENT_DEVICE, 1, [i2c_new_client_device() is enabled]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/jiffies64_to_msecs.m4 b/drivers/gpu/drm/amd/dkms/m4/jiffies64_to_msecs.m4 index e44504998e830..29cc9b9271330 100644 --- a/drivers/gpu/drm/amd/dkms/m4/jiffies64_to_msecs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/jiffies64_to_msecs.m4 @@ -4,7 +4,11 @@ dnl # time: Introduce jiffies64_to_msecs() dnl # AC_DEFUN([AC_AMDGPU_JIFFIES64_TO_MSECS], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([jiffies64_to_msecs], [kernel/time/time.c], [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + jiffies64_to_msecs(0); + ],[jiffies64_to_msecs], [kernel/time/time.c], [ AC_DEFINE(HAVE_JIFFIES64_TO_MSECS, 1, [jiffies64_to_msecs() is available]) ]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kallsyms-lookup-name.m4 b/drivers/gpu/drm/amd/dkms/m4/kallsyms-lookup-name.m4 index 62e540f41a7df..4e123cddf2838 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kallsyms-lookup-name.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kallsyms-lookup-name.m4 @@ -4,9 +4,11 @@ dnl # v2.6.32-rc4-272-gf60d24d2ad04 hw-breakpoints: Fix broken hw-breakpoint sam dnl # AC_DEFUN([AC_AMDGPU_KALLSYMS_LOOKUP_NAME], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([kallsyms_lookup_name], - [kernel/kallsyms.c], - [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + kallsyms_lookup_name(NULL); + ],[kallsyms_lookup_name],[kernel/kallsyms.c],[ AC_DEFINE(HAVE_KALLSYMS_LOOKUP_NAME, 1, [kallsyms_lookup_name is available]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/mmput_async.m4 b/drivers/gpu/drm/amd/dkms/m4/mmput_async.m4 index 2c8863597781f..bdfb1256a9ccb 100644 --- a/drivers/gpu/drm/amd/dkms/m4/mmput_async.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/mmput_async.m4 @@ -5,7 +5,11 @@ dnl # v4.6-6601-gec8d7c14ea14 mm, oom_reaper: do not mmput synchronously from th dnl # AC_DEFUN([AC_AMDGPU_MMPUT_ASYNC], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([mmput_async], [kernel/fork.c], [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + mmput_async(NULL); + ],[mmput_async], [kernel/fork.c], [ AC_DEFINE(HAVE_MMPUT_ASYNC, 1, [mmput_async() is available]) ]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/pci_pr3_present.m4 b/drivers/gpu/drm/amd/dkms/m4/pci_pr3_present.m4 index 38e50b2c0766f..e0fbc073caf06 100644 --- a/drivers/gpu/drm/amd/dkms/m4/pci_pr3_present.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/pci_pr3_present.m4 @@ -4,7 +4,11 @@ dnl # PCI: Add a helper to check Power Resource Requirements _PR3 existence dnl # AC_DEFUN([AC_AMDGPU_PCI_PR3_PRESENT], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([pci_pr3_present], [drivers/pci/pci.c], [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + pci_pr3_present(NULL); + ],[pci_pr3_present], [drivers/pci/pci.c], [ AC_DEFINE(HAVE_PCI_PR3_PRESENT, 1, [pci_pr3_present() is available]) ]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/pxm_to_node.m4 b/drivers/gpu/drm/amd/dkms/m4/pxm_to_node.m4 index 35651096f8e2a..a69d9f2264f6c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/pxm_to_node.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/pxm_to_node.m4 @@ -4,8 +4,11 @@ dnl # virtio-mem: Allow to specify an ACPI PXM as nid dnl # AC_DEFUN([AC_AMDGPU_PXM_TO_NODE], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([pxm_to_node], - [drivers/acpi/numa/srat.c], [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + pxm_to_node(0); + ],[pxm_to_node], [drivers/acpi/numa/srat.c], [ AC_DEFINE(HAVE_PXM_TO_NODE, 1, [pxm_to_node() is available]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/sched_set_fifo_low.m4 b/drivers/gpu/drm/amd/dkms/m4/sched_set_fifo_low.m4 index 422b5d833b653..6a7fdf55ded70 100644 --- a/drivers/gpu/drm/amd/dkms/m4/sched_set_fifo_low.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/sched_set_fifo_low.m4 @@ -4,8 +4,11 @@ dnl # sched: Provide sched_set_fifo() dnl # AC_DEFUN([AC_AMDGPU_SCHED_SET_FIFO_LOW], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([sched_set_fifo_low], - [kernel/sched/core.c], [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + sched_set_fifo_low(NULL); + ], [sched_set_fifo_low], [kernel/sched/core.c], [ AC_DEFINE(HAVE_SCHED_SET_FIFO_LOW, 1, [sched_set_fifo_low() is available]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 index 8ad24bc40f5fb..6b53674fb88bc 100644 --- a/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_crtc_funcs.m4 @@ -23,12 +23,14 @@ dnl # dnl # v5.10-1961-g6ca2ab8086af drm: automatic legacy gamma support dnl # AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL], [ - AC_KERNEL_CHECK_SYMBOL_EXPORT( - [drm_atomic_helper_legacy_gamma_set], [drivers/gpu/drm/drm_atomic_helper.c], [], - [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_atomic_helper_legacy_gamma_set(NULL, NULL, NULL, NULL, 0, NULL); + ], [drm_atomic_helper_legacy_gamma_set], [drivers/gpu/drm/drm_atomic_helper.c],[],[ AC_DEFINE(HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL, 1, [HAVE_STRUCT_DRM_CRTC_FUNCS_GAMMA_SET_OPTIONAL is available]) - ]) + ]) ]) AC_DEFUN([AC_AMDGPU_STRUCT_DRM_CRTC_FUNCS], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/synchronize-shrinkers.m4 b/drivers/gpu/drm/amd/dkms/m4/synchronize-shrinkers.m4 index 3abf21e7f2b67..3033e4be5a17c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/synchronize-shrinkers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/synchronize-shrinkers.m4 @@ -4,10 +4,13 @@ dnl # mm/vmscan: add sync_shrinkers function v3 dnl # AC_DEFUN([AC_AMDGPU_SYNCHRONIZE_SHRINKERS], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([synchronize_shrinkers], - [mm/vmscan.c], [ - AC_DEFINE(HAVE_SYNCHRONIZE_SHRINKERS, 1, - [synchronize_shrinkers() is available]) + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + synchronize_shrinkers(); + ], [synchronize_shrinkers], [mm/vmscan.c], [ + AC_DEFINE(HAVE_SYNCHRONIZE_SHRINKERS, 1, + [synchronize_shrinkers() is available]) ]) ]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/sysfs_emit.m4 b/drivers/gpu/drm/amd/dkms/m4/sysfs_emit.m4 index c1dc1717cc324..7c355cae6ed01 100644 --- a/drivers/gpu/drm/amd/dkms/m4/sysfs_emit.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/sysfs_emit.m4 @@ -4,13 +4,14 @@ dnl # sysfs: Add sysfs_emit and sysfs_emit_at dnl # to format sysfs output AC_DEFUN([AC_AMDGPU_SYSFS_EMIT], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([sysfs_emit sysfs_emit_at], - [fs/sysfs/file.c], [ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + sysfs_emit(NULL, NULL); + sysfs_emit_at(NULL, 0, NULL); + ],[sysfs_emit sysfs_emit_at],[fs/sysfs/file.c], [ AC_DEFINE(HAVE_SYSFS_EMIT, 1, [sysfs_emit() and sysfs_emit_at() are available]) ]) ]) ]) - - -) diff --git a/drivers/gpu/drm/amd/dkms/m4/zone_device_page_init.m4 b/drivers/gpu/drm/amd/dkms/m4/zone_device_page_init.m4 index d73aab950a652..56eaeb4b6d888 100644 --- a/drivers/gpu/drm/amd/dkms/m4/zone_device_page_init.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/zone_device_page_init.m4 @@ -5,8 +5,13 @@ dnl # v5.17-rc4-75-g27674ef6c73f mm: remove the extra ZONE_DEVICE struct page re dnl # AC_DEFUN([AC_AMDGPU_ZONE_DEVICE_PAGE_INIT], [ AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([zone_device_page_init], [mm/memremap.c], [ - AC_DEFINE(HAVE_ZONE_DEVICE_PAGE_INIT, 1, [zone_device_page_init() is available]) + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + zone_device_page_init(NULL); + ], [zone_device_page_init], [mm/memremap.c], [ + AC_DEFINE(HAVE_ZONE_DEVICE_PAGE_INIT, 1, + [zone_device_page_init() is available]) ]) ]) ]) From 39613aea78bdec0852c7fc0d878a98bd39ea0f3c Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 21 Aug 2023 17:47:36 +0800 Subject: [PATCH 1074/1868] drm/amdkcl: fix m4 include for HAVE_SYNCHRONIZE_SHRINKERS To support difference version shrinkers.h in distro systems, including mmzone.h header file make m4 script detect success. Signed-off-by: Bob Zhou Reviewed-by: Asher Song Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/m4/synchronize-shrinkers.m4 | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/synchronize-shrinkers.m4 b/drivers/gpu/drm/amd/dkms/m4/synchronize-shrinkers.m4 index 3033e4be5a17c..9429112a66d2b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/synchronize-shrinkers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/synchronize-shrinkers.m4 @@ -5,6 +5,7 @@ dnl # AC_DEFUN([AC_AMDGPU_SYNCHRONIZE_SHRINKERS], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include #include ], [ synchronize_shrinkers(); From 2a7fc6a1d48b8df1d3b5ffdb979897dba3ad3e79 Mon Sep 17 00:00:00 2001 From: Ma Jun Date: Thu, 24 Aug 2023 17:59:02 +0800 Subject: [PATCH 1075/1868] drm/amdkcl: Include kcl_rbtree.h in the backport.h Include kcl_rbtree.h in the backport.h instead of gpu_scheduler.h Signed-off-by: Ma Jun Reviewed-by: Flora Cui --- drivers/gpu/drm/scheduler/backport/backport.h | 2 +- include/drm/gpu_scheduler.h | 1 - 2 files changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/scheduler/backport/backport.h b/drivers/gpu/drm/scheduler/backport/backport.h index 25460de490b35..8b9c265bf8bce 100644 --- a/drivers/gpu/drm/scheduler/backport/backport.h +++ b/drivers/gpu/drm/scheduler/backport/backport.h @@ -8,5 +8,5 @@ #include #include #include - +#include #endif diff --git a/include/drm/gpu_scheduler.h b/include/drm/gpu_scheduler.h index cfaa5ff144e5a..150c5906c590f 100644 --- a/include/drm/gpu_scheduler.h +++ b/include/drm/gpu_scheduler.h @@ -29,7 +29,6 @@ #include #include #include -#include #define MAX_WAIT_SCHED_ENTITY_Q_EMPTY msecs_to_jiffies(1000) From e106afa852ed750dd856b200dd29402160a9ede7 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 28 Aug 2023 11:23:40 +0800 Subject: [PATCH 1076/1868] drm/amdkcl: update include sequence for kcl_rbtree.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit the kcl_amdgpu_drm_fb_helper.h should includes kcl_rbtree.h to avoid the below issue about struct lack. In file included from /var/lib/dkms/amdgpu-pro/1.0/build/amd/amdgpu/amdgpu_ring.h:28:0, from /var/lib/dkms/amdgpu-pro/1.0/build/amd/amdgpu/amdgpu_ctx.h:29, from /var/lib/dkms/amdgpu-pro/1.0/build/amd/amdgpu/amdgpu.h:43, from /var/lib/dkms/amdgpu-pro/1.0/build/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h:36, from /var/lib/dkms/amdgpu-pro/1.0/build/amd/backport/backport.h:69, from :0: /var/lib/dkms/amdgpu-pro/1.0/build/include/drm/gpu_scheduler.h:262:25: error: field ‘rb_tree_root’ has incomplete type struct rb_root_cached rb_tree_root; Signed-off-by: Bob Zhou Reviewed-by: Ma Jun --- .../gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h index 5abb5cf97824c..8c75bfc4e993b 100644 --- a/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_amdgpu_drm_fb_helper.h @@ -33,6 +33,7 @@ #include #include #include +#include #include "amdgpu.h" #ifndef HAVE_DRM_FB_HELPER_LASTCLOSE From a952f5d8c0f78fd1a3a37d24d4e41c5b217076a0 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 25 Aug 2023 11:29:55 +0800 Subject: [PATCH 1077/1868] drm/amdkcl: change the order of the judgment for mem_type To avoid the following Null pointer dereference error, change the order of the judgment for old_mem->mem_type Signed-off-by: Asher Song Acked-by: Bob Zhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 81b26eda28752..5c938ff0bf488 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -527,10 +527,6 @@ static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict, abo = ttm_to_amdgpu_bo(bo); - if (old_mem->mem_type == AMDGPU_GEM_DOMAIN_DGMA || - old_mem->mem_type == AMDGPU_GEM_DOMAIN_DGMA_IMPORT) - return -EINVAL; - adev = amdgpu_ttm_adev(bo->bdev); if (!old_mem || (old_mem->mem_type == TTM_PL_SYSTEM && @@ -539,6 +535,10 @@ static int amdgpu_bo_move(struct ttm_buffer_object *bo, bool evict, ttm_bo_move_null(bo, new_mem); return 0; } + if (old_mem->mem_type == AMDGPU_GEM_DOMAIN_DGMA || + old_mem->mem_type == AMDGPU_GEM_DOMAIN_DGMA_IMPORT) + return -EINVAL; + if (old_mem->mem_type == TTM_PL_SYSTEM && (new_mem->mem_type == TTM_PL_TT || new_mem->mem_type == AMDGPU_PL_PREEMPT)) { From e9f4979e757ed023384fe27e389ab061ba28cca9 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 13 Sep 2023 14:57:49 +0800 Subject: [PATCH 1078/1868] drm/amdkcl: fake drm_show_fdinfo It's caused v6.4-rc1-190-g3f09a0cd4ea3 drm: Add common fdinfo helper Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 + drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_drm_file.c | 68 +++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + .../gpu/drm/amd/dkms/m4/drm-show-fdinfo.m4 | 37 ++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_file.h | 8 +++ 7 files changed, 118 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_file.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-show-fdinfo.m4 create mode 100644 include/kcl/kcl_drm_file.h diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 205f568c849f5..4a78aaadde6ba 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3050,9 +3050,11 @@ static struct drm_driver amdgpu_kms_driver = { .dumb_map_offset = amdgpu_mode_dumb_mmap, .fops = &amdgpu_driver_kms_fops, .release = &amdgpu_driver_release_kms, +#ifdef HAVE_DRM_DRIVER_SHOW_FDINFO #ifdef CONFIG_PROC_FS .show_fdinfo = amdgpu_show_fdinfo, #endif +#endif #ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK .gem_prime_export = amdgpu_gem_prime_export, diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index f8e0cdb1dd258..bd294b351ebe7 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -14,7 +14,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_fs_read_write.o kcl_drm_aperture.o \ kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o \ kcl_mce_amd.o kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o kcl_mm_slab.o \ - kcl_irqdesc.o kcl_drm_suballoc.o + kcl_irqdesc.o kcl_drm_suballoc.o kcl_drm_file.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_file.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_file.c new file mode 100644 index 0000000000000..7ddc32cafc5b7 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_file.c @@ -0,0 +1,68 @@ +/* + * \author Rickard E. (Rik) Faith + * \author Daryll Strauss + * \author Gareth Hughes + */ + +/* + * Created: Mon Jan 4 08:58:31 1999 by faith@valinux.com + * + * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. + * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include +#include +#include +#include +#include +#include +#include +#ifndef HAVE_DRM_SHOW_FDINFO +/** + * drm_show_fdinfo - helper for drm file fops + * @m: output stream + * @f: the device file instance + * + * Helper to implement fdinfo, for userspace to query usage stats, etc, of a + * process using the GPU. See also &drm_driver.show_fdinfo. + * + * For text output format description please see Documentation/gpu/drm-usage-stats.rst + */ +void drm_show_fdinfo(struct seq_file *m, struct file *f) +{ + struct drm_file *file = f->private_data; + struct drm_device *dev = file->minor->dev; + struct drm_printer p = drm_seq_file_printer(m); + + drm_printf(&p, "drm-driver:\t%s\n", dev->driver->name); + + if (dev_is_pci(dev->dev)) { + struct pci_dev *pdev = to_pci_dev(dev->dev); + + drm_printf(&p, "drm-pdev:\t%04x:%02x:%02x.%d\n", + pci_domain_nr(pdev->bus), pdev->bus->number, + PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); + } +} +EXPORT_SYMBOL(drm_show_fdinfo); +#endif diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 0f775ed076173..27819f54eea30 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -111,4 +111,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-show-fdinfo.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-show-fdinfo.m4 new file mode 100644 index 0000000000000..a144bfa3967d4 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-show-fdinfo.m4 @@ -0,0 +1,37 @@ +dnl # +dnl # v6.4-rc1-190-g3f09a0cd4ea3:drm: Add common fdinfo helper +dnl # +AC_DEFUN([AC_AMDGPU_DRM_FILE_DRM_SHOW_FDINFO], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + drm_show_fdinfo(NULL, NULL); + ],[drm_show_fdinfo], [drivers/gpu/drm/drm_file.c], [ + AC_DEFINE(HAVE_DRM_SHOW_FDINFO, 1, [drm_show_fdinfo() is available]) + ]) + ]) +]) + +dnl # +dnl # v6.4-rc1-190-g3f09a0cd4ea3:drm: Add common fdinfo helper +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DRIVER_SHOW_FDINFO], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_driver *drm_driver = NULL; + + drm_driver->show_fdinfo(NULL, NULL); + ], [ + AC_DEFINE(HAVE_DRM_DRIVER_SHOW_FDINFO, 1, + [drm_driver->show_fdinfo() is available]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_DRM_SHOW_FDINFO], [ + AC_AMDGPU_DRM_FILE_DRM_SHOW_FDINFO + AC_AMDGPU_DRM_DRIVER_SHOW_FDINFO +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 68bff1224ec80..9edd0c3fb97d4 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -209,6 +209,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_MMAP_ASSERT_WRITE_LOCKED AC_AMDGPU_PID_TYPE AC_AMDGPU_DMA_FENCE_OPS_SET_DEADLINE + AC_AMDGPU_DRM_SHOW_FDINFO AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_file.h b/include/kcl/kcl_drm_file.h new file mode 100644 index 0000000000000..d23292e37dc25 --- /dev/null +++ b/include/kcl/kcl_drm_file.h @@ -0,0 +1,8 @@ +#ifndef __AMDKCL_KCL_DRM_DRV_H__ +#define __AMDKCL_KCL_DRM_DRV_H__ +#include + +#ifndef HAVE_DRM_SHOW_FDINFO +void drm_show_fdinfo(struct seq_file *m, struct file *f); +#endif +#endif From 13f2572c8f99b46e884132fa0cc7d2301a265aeb Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 18 Sep 2023 17:03:05 +0800 Subject: [PATCH 1079/1868] drm/amdkcl: fake drm_exec_* It's caused by v6.4-rc7-2018-g09593216bff1 drm: execution context for GEM buffers v7 Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_drm_exec.c | 334 +++++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 7 + include/kcl/header/drm/drm_exec.h | 9 + include/kcl/kcl_drm_exec.h | 124 ++++++++ 6 files changed, 476 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_exec.c create mode 100644 include/kcl/header/drm/drm_exec.h create mode 100644 include/kcl/kcl_drm_exec.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index bd294b351ebe7..f1367b6447788 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -14,7 +14,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_fs_read_write.o kcl_drm_aperture.o \ kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o \ kcl_mce_amd.o kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o kcl_mm_slab.o \ - kcl_irqdesc.o kcl_drm_suballoc.o kcl_drm_file.o + kcl_irqdesc.o kcl_drm_suballoc.o kcl_drm_file.o kcl_drm_exec.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_exec.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_exec.c new file mode 100644 index 0000000000000..8fc292da898b0 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_exec.c @@ -0,0 +1,334 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT + +#include +#include +#include +#include + +#ifndef HAVE_DRM_DRM_EXEC_H +/** + * DOC: Overview + * + * This component mainly abstracts the retry loop necessary for locking + * multiple GEM objects while preparing hardware operations (e.g. command + * submissions, page table updates etc..). + * + * If a contention is detected while locking a GEM object the cleanup procedure + * unlocks all previously locked GEM objects and locks the contended one first + * before locking any further objects. + * + * After an object is locked fences slots can optionally be reserved on the + * dma_resv object inside the GEM object. + * + * A typical usage pattern should look like this:: + * + * struct drm_gem_object *obj; + * struct drm_exec exec; + * unsigned long index; + * int ret; + * + * drm_exec_init(&exec, DRM_EXEC_INTERRUPTIBLE_WAIT); + * drm_exec_until_all_locked(&exec) { + * ret = drm_exec_prepare_obj(&exec, boA, 1); + * drm_exec_retry_on_contention(&exec); + * if (ret) + * goto error; + * + * ret = drm_exec_prepare_obj(&exec, boB, 1); + * drm_exec_retry_on_contention(&exec); + * if (ret) + * goto error; + * } + * + * drm_exec_for_each_locked_object(&exec, index, obj) { + * dma_resv_add_fence(obj->resv, fence, DMA_RESV_USAGE_READ); + * ... + * } + * drm_exec_fini(&exec); + * + * See struct dma_exec for more details. + */ + +/* Dummy value used to initially enter the retry loop */ +#define DRM_EXEC_DUMMY ((void *)~0) + +/* Unlock all objects and drop references */ +static void drm_exec_unlock_all(struct drm_exec *exec) +{ + struct drm_gem_object *obj; + unsigned long index; + + drm_exec_for_each_locked_object(exec, index, obj) { + dma_resv_unlock(obj->resv); + drm_gem_object_put(obj); + } + + drm_gem_object_put(exec->prelocked); + exec->prelocked = NULL; +} + +/** + * drm_exec_init - initialize a drm_exec object + * @exec: the drm_exec object to initialize + * @flags: controls locking behavior, see DRM_EXEC_* defines + * + * Initialize the object and make sure that we can track locked objects. + */ +void drm_exec_init(struct drm_exec *exec, uint32_t flags) +{ + exec->flags = flags; + exec->objects = kmalloc(PAGE_SIZE, GFP_KERNEL); + + /* If allocation here fails, just delay that till the first use */ + exec->max_objects = exec->objects ? PAGE_SIZE / sizeof(void *) : 0; + exec->num_objects = 0; + exec->contended = DRM_EXEC_DUMMY; + exec->prelocked = NULL; +} +EXPORT_SYMBOL(drm_exec_init); + +/** + * drm_exec_fini - finalize a drm_exec object + * @exec: the drm_exec object to finalize + * + * Unlock all locked objects, drop the references to objects and free all memory + * used for tracking the state. + */ +void drm_exec_fini(struct drm_exec *exec) +{ + drm_exec_unlock_all(exec); + kvfree(exec->objects); + if (exec->contended != DRM_EXEC_DUMMY) { + drm_gem_object_put(exec->contended); + ww_acquire_fini(&exec->ticket); + } +} +EXPORT_SYMBOL(drm_exec_fini); + +/** + * drm_exec_cleanup - cleanup when contention is detected + * @exec: the drm_exec object to cleanup + * + * Cleanup the current state and return true if we should stay inside the retry + * loop, false if there wasn't any contention detected and we can keep the + * objects locked. + */ +bool drm_exec_cleanup(struct drm_exec *exec) +{ + if (likely(!exec->contended)) { + ww_acquire_done(&exec->ticket); + return false; + } + + if (likely(exec->contended == DRM_EXEC_DUMMY)) { + exec->contended = NULL; + ww_acquire_init(&exec->ticket, &reservation_ww_class); + return true; + } + + drm_exec_unlock_all(exec); + exec->num_objects = 0; + return true; +} +EXPORT_SYMBOL(drm_exec_cleanup); + +/* Track the locked object in the array */ +static int drm_exec_obj_locked(struct drm_exec *exec, + struct drm_gem_object *obj) +{ + if (unlikely(exec->num_objects == exec->max_objects)) { + size_t size = exec->max_objects * sizeof(void *); + void *tmp; + + tmp = kvrealloc(exec->objects, size, size + PAGE_SIZE, + GFP_KERNEL); + if (!tmp) + return -ENOMEM; + + exec->objects = tmp; + exec->max_objects += PAGE_SIZE / sizeof(void *); + } + drm_gem_object_get(obj); + exec->objects[exec->num_objects++] = obj; + + return 0; +} + +/* Make sure the contended object is locked first */ +static int drm_exec_lock_contended(struct drm_exec *exec) +{ + struct drm_gem_object *obj = exec->contended; + int ret; + + if (likely(!obj)) + return 0; + + /* Always cleanup the contention so that error handling can kick in */ + exec->contended = NULL; + if (exec->flags & DRM_EXEC_INTERRUPTIBLE_WAIT) { + ret = dma_resv_lock_slow_interruptible(obj->resv, + &exec->ticket); + if (unlikely(ret)) + goto error_dropref; + } else { + dma_resv_lock_slow(obj->resv, &exec->ticket); + } + + ret = drm_exec_obj_locked(exec, obj); + if (unlikely(ret)) + goto error_unlock; + + exec->prelocked = obj; + return 0; + +error_unlock: + dma_resv_unlock(obj->resv); + +error_dropref: + drm_gem_object_put(obj); + return ret; +} + +/** + * drm_exec_lock_obj - lock a GEM object for use + * @exec: the drm_exec object with the state + * @obj: the GEM object to lock + * + * Lock a GEM object for use and grab a reference to it. + * + * Returns: -EDEADLK if a contention is detected, -EALREADY when object is + * already locked (can be suppressed by setting the DRM_EXEC_IGNORE_DUPLICATES + * flag), -ENOMEM when memory allocation failed and zero for success. + */ +int drm_exec_lock_obj(struct drm_exec *exec, struct drm_gem_object *obj) +{ + int ret; + + ret = drm_exec_lock_contended(exec); + if (unlikely(ret)) + return ret; + + if (exec->prelocked == obj) { + drm_gem_object_put(exec->prelocked); + exec->prelocked = NULL; + return 0; + } + + if (exec->flags & DRM_EXEC_INTERRUPTIBLE_WAIT) + ret = dma_resv_lock_interruptible(obj->resv, &exec->ticket); + else + ret = dma_resv_lock(obj->resv, &exec->ticket); + + if (unlikely(ret == -EDEADLK)) { + drm_gem_object_get(obj); + exec->contended = obj; + return -EDEADLK; + } + + if (unlikely(ret == -EALREADY) && + exec->flags & DRM_EXEC_IGNORE_DUPLICATES) + return 0; + + if (unlikely(ret)) + return ret; + + ret = drm_exec_obj_locked(exec, obj); + if (ret) + goto error_unlock; + + return 0; + +error_unlock: + dma_resv_unlock(obj->resv); + return ret; +} +EXPORT_SYMBOL(drm_exec_lock_obj); + +/** + * drm_exec_unlock_obj - unlock a GEM object in this exec context + * @exec: the drm_exec object with the state + * @obj: the GEM object to unlock + * + * Unlock the GEM object and remove it from the collection of locked objects. + * Should only be used to unlock the most recently locked objects. It's not time + * efficient to unlock objects locked long ago. + */ +void drm_exec_unlock_obj(struct drm_exec *exec, struct drm_gem_object *obj) +{ + unsigned int i; + + for (i = exec->num_objects; i--;) { + if (exec->objects[i] == obj) { + dma_resv_unlock(obj->resv); + for (++i; i < exec->num_objects; ++i) + exec->objects[i - 1] = exec->objects[i]; + --exec->num_objects; + drm_gem_object_put(obj); + return; + } + + } +} +EXPORT_SYMBOL(drm_exec_unlock_obj); + +/** + * drm_exec_prepare_obj - prepare a GEM object for use + * @exec: the drm_exec object with the state + * @obj: the GEM object to prepare + * @num_fences: how many fences to reserve + * + * Prepare a GEM object for use by locking it and reserving fence slots. + * + * Returns: -EDEADLK if a contention is detected, -EALREADY when object is + * already locked, -ENOMEM when memory allocation failed and zero for success. + */ +int drm_exec_prepare_obj(struct drm_exec *exec, struct drm_gem_object *obj, + unsigned int num_fences) +{ + int ret; + + ret = drm_exec_lock_obj(exec, obj); + if (ret) + return ret; + + ret = dma_resv_reserve_fences(obj->resv, num_fences); + if (ret) { + drm_exec_unlock_obj(exec, obj); + return ret; + } + + return 0; +} +EXPORT_SYMBOL(drm_exec_prepare_obj); + +/** + * drm_exec_prepare_array - helper to prepare an array of objects + * @exec: the drm_exec object with the state + * @objects: array of GEM object to prepare + * @num_objects: number of GEM objects in the array + * @num_fences: number of fences to reserve on each GEM object + * + * Prepares all GEM objects in an array, aborts on first error. + * Reserves @num_fences on each GEM object after locking it. + * + * Returns: -EDEADLOCK on contention, -EALREADY when object is already locked, + * -ENOMEM when memory allocation failed and zero for success. + */ +int drm_exec_prepare_array(struct drm_exec *exec, + struct drm_gem_object **objects, + unsigned int num_objects, + unsigned int num_fences) +{ + int ret; + + for (unsigned int i = 0; i < num_objects; ++i) { + ret = drm_exec_prepare_obj(exec, objects[i], num_fences); + if (unlikely(ret)) + return ret; + } + + return 0; +} +EXPORT_SYMBOL(drm_exec_prepare_array); + +#endif diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 27819f54eea30..1b3c7daede330 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -112,4 +112,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index 38a64fd0deb08..76f76c549528a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -98,4 +98,11 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # drm/suballoc: Extract amdgpu_sa.c as generic suballocation helper dnl # AC_KERNEL_CHECK_HEADERS([drm/drm_suballoc.h]) + + dnl # + dnl # v6.4-rc7-2018-g09593216bff1 + dnl # drm: execution context for GEM buffers v7 + dnl # + AC_KERNEL_CHECK_HEADERS([drm/drm_exec.h]) + ]) diff --git a/include/kcl/header/drm/drm_exec.h b/include/kcl/header/drm/drm_exec.h new file mode 100644 index 0000000000000..62aff24d17425 --- /dev/null +++ b/include/kcl/header/drm/drm_exec.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DRM_EXEC_H_H_ +#define _KCL_HEADER_DRM_EXEC_H_H_ + +#ifdef HAVE_DRM_DRM_EXEC_H +#include_next +#endif + +#endif diff --git a/include/kcl/kcl_drm_exec.h b/include/kcl/kcl_drm_exec.h new file mode 100644 index 0000000000000..90cd2a6a4f1c8 --- /dev/null +++ b/include/kcl/kcl_drm_exec.h @@ -0,0 +1,124 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ + +#ifndef AMDKCL_DRM_EXEC_H +#define AMDKCL_DRM_EXEC_H + +#include +#include + +#ifndef HAVE_DRM_DRM_EXEC_H +#define DRM_EXEC_INTERRUPTIBLE_WAIT BIT(0) +#define DRM_EXEC_IGNORE_DUPLICATES BIT(1) + +struct drm_gem_object; + +/** + * struct drm_exec - Execution context + */ +struct drm_exec { + /** + * @flags: Flags to control locking behavior + */ + uint32_t flags; + + /** + * @ticket: WW ticket used for acquiring locks + */ + struct ww_acquire_ctx ticket; + + /** + * @num_objects: number of objects locked + */ + unsigned int num_objects; + + /** + * @max_objects: maximum objects in array + */ + unsigned int max_objects; + + /** + * @objects: array of the locked objects + */ + struct drm_gem_object **objects; + + /** + * @contended: contended GEM object we backed off for + */ + struct drm_gem_object *contended; + + /** + * @prelocked: already locked GEM object due to contention + */ + struct drm_gem_object *prelocked; +}; + +/** + * drm_exec_for_each_locked_object - iterate over all the locked objects + * @exec: drm_exec object + * @index: unsigned long index for the iteration + * @obj: the current GEM object + * + * Iterate over all the locked GEM objects inside the drm_exec object. + */ +#define drm_exec_for_each_locked_object(exec, index, obj) \ + for (index = 0, obj = (exec)->objects[0]; \ + index < (exec)->num_objects; \ + ++index, obj = (exec)->objects[index]) + +/** + * drm_exec_until_all_locked - loop until all GEM objects are locked + * @exec: drm_exec object + * + * Core functionality of the drm_exec object. Loops until all GEM objects are + * locked and no more contention exists. At the beginning of the loop it is + * guaranteed that no GEM object is locked. + * + * Since labels can't be defined local to the loops body we use a jump pointer + * to make sure that the retry is only used from within the loops body. + */ +#define drm_exec_until_all_locked(exec) \ +__PASTE(__drm_exec_, __LINE__): \ + for (void *__drm_exec_retry_ptr; ({ \ + __drm_exec_retry_ptr = &&__PASTE(__drm_exec_, __LINE__);\ + (void)__drm_exec_retry_ptr; \ + drm_exec_cleanup(exec); \ + });) + +/** + * drm_exec_retry_on_contention - restart the loop to grap all locks + * @exec: drm_exec object + * + * Control flow helper to continue when a contention was detected and we need to + * clean up and re-start the loop to prepare all GEM objects. + */ +#define drm_exec_retry_on_contention(exec) \ + do { \ + if (unlikely(drm_exec_is_contended(exec))) \ + goto *__drm_exec_retry_ptr; \ + } while (0) + +/** + * drm_exec_is_contended - check for contention + * @exec: drm_exec object + * + * Returns true if the drm_exec object has run into some contention while + * locking a GEM object and needs to clean up. + */ +static inline bool drm_exec_is_contended(struct drm_exec *exec) +{ + return !!exec->contended; +} + +void drm_exec_init(struct drm_exec *exec, uint32_t flags); +void drm_exec_fini(struct drm_exec *exec); +bool drm_exec_cleanup(struct drm_exec *exec); +int drm_exec_lock_obj(struct drm_exec *exec, struct drm_gem_object *obj); +void drm_exec_unlock_obj(struct drm_exec *exec, struct drm_gem_object *obj); +int drm_exec_prepare_obj(struct drm_exec *exec, struct drm_gem_object *obj, + unsigned int num_fences); +int drm_exec_prepare_array(struct drm_exec *exec, + struct drm_gem_object **objects, + unsigned int num_objects, + unsigned int num_fences); +#endif +#endif From eab61b2b057c9ca80b93f15182dd50ed0d1577b1 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 13 Sep 2023 17:38:41 +0800 Subject: [PATCH 1080/1868] drm/amdkcl: fake local64_try_cmpxchg It's caused by 8fc4fddaf9a184eea7da21290236a1764e608a01 locking/generic: Wire up local{,64}_try_cmpxchg() Signed-off-by: Asher Song --- drivers/gpu/drm/amd/backport/backport.h | 1 + .../amd/dkms/m4/atomic-long-try-cmpxchg.m4 | 37 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 + include/kcl/kcl_local64.h | 33 +++++++++++++++++ 4 files changed, 73 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/atomic-long-try-cmpxchg.m4 create mode 100644 include/kcl/kcl_local64.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 1b3c7daede330..a11eebffea589 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -113,4 +113,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/atomic-long-try-cmpxchg.m4 b/drivers/gpu/drm/amd/dkms/m4/atomic-long-try-cmpxchg.m4 new file mode 100644 index 0000000000000..5d20db398bf97 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/atomic-long-try-cmpxchg.m4 @@ -0,0 +1,37 @@ +dnl # +dnl # v5.13-rc1-138-g67d1b0de258a locking/atomic: add arch_atomic_long*() +dnl # +AC_DEFUN([AC_AMDGPU_LINUX_ATOMIC_LONG_TRY_CMPXCHG], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + bool t; + long r = 0; + t = atomic_long_try_cmpxchg(NULL, NULL, r); + ], [ + AC_DEFINE(HAVE_LINUX_ATOMIC_LONG_TRY_CMPXCHG, 1, + [atomic_long_try_cmpxchg() is available]) + ]) + ]) +]) + +dnl # +dnl # v6.3-rc1-6-g8fc4fddaf9a1 +dnl # locking/generic: Wire up local{,64}_try_cmpxchg() +dnl # +AC_DEFUN([AC_AMDGPU_LINUX_LOCAL_TRY_CMPXCHG], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + bool t; + s64 r = 0; + local_t *l = NULL; + t = local_try_cmpxchg(l, NULL, r); + ], [ + AC_DEFINE(HAVE_LINUX_LOCAL_TRY_CMPXCHG, 1, + [local_try_cmpchg() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 9edd0c3fb97d4..f33d77f190ae7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -210,6 +210,8 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_PID_TYPE AC_AMDGPU_DMA_FENCE_OPS_SET_DEADLINE AC_AMDGPU_DRM_SHOW_FDINFO + AC_AMDGPU_LINUX_ATOMIC_LONG_TRY_CMPXCHG + AC_AMDGPU_LINUX_LOCAL_TRY_CMPXCHG AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_local64.h b/include/kcl/kcl_local64.h new file mode 100644 index 0000000000000..0b374fef81d85 --- /dev/null +++ b/include/kcl/kcl_local64.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_ASM_GENERIC_LOCAL64_H +#define AMDKCL_ASM_GENERIC_LOCAL64_H + +#include +#include +#include + +/* + * A signed long type for operations which are atomic for a single CPU. + * Usually used in combination with per-cpu variables. + * + * This is the default implementation, which uses atomic64_t. Which is + * rather pointless. The whole point behind local64_t is that some processors + * can perform atomic adds and subtracts in a manner which is atomic wrt IRQs + * running on this CPU. local64_t allows exploitation of such capabilities. + */ + +/* Implement in terms of atomics. */ + +#if !defined HAVE_LINUX_LOCAL_TRY_CMPXCHG && defined HAVE_LINUX_ATOMIC_LONG_TRY_CMPXCHG +#define local_try_cmpxchg(l, po, n) atomic_long_try_cmpxchg((&(l)->a), (po), (n)) +#if BITS_PER_LONG == 64 + +static inline bool local64_try_cmpxchg(local64_t *l, s64 *old, s64 new) +{ + return local_try_cmpxchg(&l->a, (long *)old, new); +} +#else +#define local64_try_cmpxchg(l, po, n) atomic64_try_cmpxchg((&(l)->a), (po), (n)) +#endif +#endif +#endif From 5e5dd08602922cb38a04a6feb6305e3425c4b20f Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 19 Sep 2023 14:54:33 +0800 Subject: [PATCH 1081/1868] drm/amdkcl: test whether atomoic_long_try_cmpxchg() exist It's caused by v6.5-rc2-955-g9e761bff03e1 drm/amdgpu: Use local64_try_cmpxchg in amdgpu_perf_read Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c index 6e91ea1de5aaf..1017a30d3687d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c @@ -275,9 +275,13 @@ static void amdgpu_perf_read(struct perf_event *event) if ((!pe->adev->df.funcs) || (!pe->adev->df.funcs->pmc_get_count)) return; - +#ifdef HAVE_LINUX_ATOMIC_LONG_TRY_CMPXCHG prev = local64_read(&hwc->prev_count); +#endif do { +#ifndef HAVE_LINUX_ATOMIC_LONG_TRY_CMPXCHG + prev = local64_read(&hwc->prev_count); +#endif switch (hwc->config_base) { case AMDGPU_PMU_EVENT_CONFIG_TYPE_DF: case AMDGPU_PMU_EVENT_CONFIG_TYPE_XGMI: @@ -288,8 +292,11 @@ static void amdgpu_perf_read(struct perf_event *event) count = 0; break; } +#ifdef HAVE_LINUX_ATOMIC_LONG_TRY_CMPXCHG } while (!local64_try_cmpxchg(&hwc->prev_count, &prev, count)); - +#else + } while (local64_cmpxchg(&hwc->prev_count, prev, count) != prev); +#endif local64_add(count - prev, &event->count); } From a075576bafe39b1daff56f6700500d65c6aaab52 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 20 Sep 2023 17:04:21 +0800 Subject: [PATCH 1082/1868] drm/amdkcl: test create_class's argument quantity It's caused by v6.3-rc1-13-g1aaba11da9aa driver core: class: remove module * from class_create() Signed-off-by: Asher Song --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/create_class.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 | 5 +++++ include/kcl/header/linux/class.h | 10 ++++++++++ include/kcl/kcl_class.h | 17 +++++++++++++++++ 6 files changed, 50 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/create_class.m4 create mode 100644 include/kcl/header/linux/class.h create mode 100644 include/kcl/kcl_class.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index a11eebffea589..b6546e738c026 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -114,4 +114,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/create_class.m4 b/drivers/gpu/drm/amd/dkms/m4/create_class.m4 new file mode 100644 index 0000000000000..bb9bd7bd2d13d --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/create_class.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v6.3-rc1-13-g1aaba11da9aa driver core: class: remove module * from class_create() +dnl # +AC_DEFUN([AC_AMDGPU_LINUX_DEVICE_CLASS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct class* class = NULL; + class = class_create(NULL); + ], [ + AC_DEFINE(HAVE_ONE_ARGUMENT_OF_CLASS_CREATE, 1, + [class_create has one argument]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index f33d77f190ae7..700bfc26381f9 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -212,6 +212,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_SHOW_FDINFO AC_AMDGPU_LINUX_ATOMIC_LONG_TRY_CMPXCHG AC_AMDGPU_LINUX_LOCAL_TRY_CMPXCHG + AC_AMDGPU_LINUX_DEVICE_CLASS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 index f99ed5020b2e7..557b1a1589e6d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 @@ -119,4 +119,9 @@ AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ dnl #apple-gmux: Add helper for presence detect dnl AC_KERNEL_CHECK_HEADERS([linux/apple-gmux.h]) + + dnl #v5.5-rc2-6-ga8ae608529ab + dnl #device.h: move 'struct class' stuff out to device/class.h + dnl + AC_KERNEL_CHECK_HEADERS([linux/device/class.h]) ]) diff --git a/include/kcl/header/linux/class.h b/include/kcl/header/linux/class.h new file mode 100644 index 0000000000000..595b34ca30dbe --- /dev/null +++ b/include/kcl/header/linux/class.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_LINUX_CLASS_H_H_ +#define _KCL_HEADER_LINUX_CLASS_H_H_ + +#ifdef HAVE_LINUX_DEVICE_CLASS_H +#include_next +#endif + +#endif + diff --git a/include/kcl/kcl_class.h b/include/kcl/kcl_class.h new file mode 100644 index 0000000000000..fbce818309960 --- /dev/null +++ b/include/kcl/kcl_class.h @@ -0,0 +1,17 @@ +#ifndef __AMDKCL_CLASS_H__ +#define __AMDKCL_CLASS_H__ + +#ifdef HAVE_LINUX_DEVICE_CLASS_H +#include +#endif +#include +static inline struct class* kcl_class_create(struct module *owner, const char* name) +{ +#ifdef HAVE_ONE_ARGUMENT_OF_CLASS_CREATE + return class_create(name); +#else + return class_create(owner, name); +#endif +} +#endif + From ecb51aae91eaa23b2f1a59473ed9e8b497a03702 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 19 Sep 2023 17:32:53 +0800 Subject: [PATCH 1083/1868] drm/amdkcl: test drm_gem_object->resv whether exist It's caused by v6.4-rc7-2018-g09593216bff1 drm: execution context for GEM buffers v7 Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdkcl/kcl_drm_exec.c | 18 +++++++++--------- include/kcl/kcl_drm_exec.h | 7 +++++++ 2 files changed, 16 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_exec.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_exec.c index 8fc292da898b0..4bf8c653fa2f4 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_exec.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_exec.c @@ -59,7 +59,7 @@ static void drm_exec_unlock_all(struct drm_exec *exec) unsigned long index; drm_exec_for_each_locked_object(exec, index, obj) { - dma_resv_unlock(obj->resv); + dma_resv_unlock(amdkcl_gem_resvp(obj)); drm_gem_object_put(obj); } @@ -166,12 +166,12 @@ static int drm_exec_lock_contended(struct drm_exec *exec) /* Always cleanup the contention so that error handling can kick in */ exec->contended = NULL; if (exec->flags & DRM_EXEC_INTERRUPTIBLE_WAIT) { - ret = dma_resv_lock_slow_interruptible(obj->resv, + ret = dma_resv_lock_slow_interruptible(amdkcl_gem_resvp(obj), &exec->ticket); if (unlikely(ret)) goto error_dropref; } else { - dma_resv_lock_slow(obj->resv, &exec->ticket); + dma_resv_lock_slow(amdkcl_gem_resvp(obj), &exec->ticket); } ret = drm_exec_obj_locked(exec, obj); @@ -182,7 +182,7 @@ static int drm_exec_lock_contended(struct drm_exec *exec) return 0; error_unlock: - dma_resv_unlock(obj->resv); + dma_resv_unlock(amdkcl_gem_resvp(obj)); error_dropref: drm_gem_object_put(obj); @@ -215,9 +215,9 @@ int drm_exec_lock_obj(struct drm_exec *exec, struct drm_gem_object *obj) } if (exec->flags & DRM_EXEC_INTERRUPTIBLE_WAIT) - ret = dma_resv_lock_interruptible(obj->resv, &exec->ticket); + ret = dma_resv_lock_interruptible(amdkcl_gem_resvp(obj), &exec->ticket); else - ret = dma_resv_lock(obj->resv, &exec->ticket); + ret = dma_resv_lock(amdkcl_gem_resvp(obj), &exec->ticket); if (unlikely(ret == -EDEADLK)) { drm_gem_object_get(obj); @@ -239,7 +239,7 @@ int drm_exec_lock_obj(struct drm_exec *exec, struct drm_gem_object *obj) return 0; error_unlock: - dma_resv_unlock(obj->resv); + dma_resv_unlock(amdkcl_gem_resvp(obj)); return ret; } EXPORT_SYMBOL(drm_exec_lock_obj); @@ -259,7 +259,7 @@ void drm_exec_unlock_obj(struct drm_exec *exec, struct drm_gem_object *obj) for (i = exec->num_objects; i--;) { if (exec->objects[i] == obj) { - dma_resv_unlock(obj->resv); + dma_resv_unlock(amdkcl_gem_resvp(obj)); for (++i; i < exec->num_objects; ++i) exec->objects[i - 1] = exec->objects[i]; --exec->num_objects; @@ -291,7 +291,7 @@ int drm_exec_prepare_obj(struct drm_exec *exec, struct drm_gem_object *obj, if (ret) return ret; - ret = dma_resv_reserve_fences(obj->resv, num_fences); + ret = dma_resv_reserve_fences(amdkcl_gem_resvp(obj), num_fences); if (ret) { drm_exec_unlock_obj(exec, obj); return ret; diff --git a/include/kcl/kcl_drm_exec.h b/include/kcl/kcl_drm_exec.h index 90cd2a6a4f1c8..8a3f47f0520f6 100644 --- a/include/kcl/kcl_drm_exec.h +++ b/include/kcl/kcl_drm_exec.h @@ -6,7 +6,14 @@ #include #include +#ifdef HAVE_DRM_GEM_OBJECT_RESV +#define amdkcl_gem_resvp(bo) (bo->resv) +#else +#define amdkcl_gem_resvp(bo) (container_of(bo, struct ttm_buffer_object, base)->resv) +#endif #ifndef HAVE_DRM_DRM_EXEC_H +#include +#include #define DRM_EXEC_INTERRUPTIBLE_WAIT BIT(0) #define DRM_EXEC_IGNORE_DUPLICATES BIT(1) From 5765b2700badb397a0429c11671c2d96bd153a83 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 19 Sep 2023 17:39:12 +0800 Subject: [PATCH 1084/1868] drm/amdkcl: add dkms support for hmm using new drm_exec object It's caused by v6.4-rc7-2018-g09593216bff1 drm: execution context for GEM buffers v7 Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h | 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 93 ++++++++++++--------- 2 files changed, 55 insertions(+), 40 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h index 204bee0e32562..2458bbed8cc5b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h @@ -24,6 +24,7 @@ #define __AMDGPU_BO_LIST_H__ #include +#include struct hmm_range; @@ -44,6 +45,7 @@ struct amdgpu_bo_list_entry { bool user_invalidated; #else int user_invalidated; + struct ttm_validate_buffer tv; #endif }; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 472af355eeff3..0bf32f39b5ad6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -944,21 +944,62 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, goto out_free_user_pages; } } + amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) { + struct mm_struct *usermm; + + usermm = amdgpu_ttm_tt_get_usermm(e->bo->tbo.ttm); + if (usermm && usermm != current->mm) { + r = -EPERM; + goto out_free_user_pages; + } + + if (amdgpu_ttm_tt_is_userptr(e->bo->tbo.ttm) && + e->user_invalidated && e->user_pages) { + amdgpu_bo_placement_from_domain(e->bo, + AMDGPU_GEM_DOMAIN_CPU); + r = ttm_bo_validate(&e->bo->tbo, &e->bo->placement, + &ctx); + if (r) + goto out_free_user_pages; + + amdgpu_ttm_tt_set_user_pages(e->bo->tbo.ttm, + e->user_pages); + } + + kvfree(e->user_pages); + e->user_pages = NULL; + } #else while (1) { struct list_head need_pages; + drm_exec_until_all_locked(&p->exec) { + r = amdgpu_vm_lock_pd(&fpriv->vm, &p->exec, 1 + p->gang_size); + drm_exec_retry_on_contention(&p->exec); + if (unlikely(r)) + goto error_free_pages; - r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true, - &duplicates); - if (unlikely(r != 0)) { - if (r != -ERESTARTSYS) - DRM_ERROR("ttm_eu_reserve_buffers failed.\n"); - goto error_free_pages; - } + amdgpu_bo_list_for_each_entry(e, p->bo_list) { + /* One fence for TTM and one for each CS job */ + r = drm_exec_prepare_obj(&p->exec, &e->bo->tbo.base, + 1 + p->gang_size); + drm_exec_retry_on_contention(&p->exec); + if (unlikely(r)) + goto error_free_pages; + + e->bo_va = amdgpu_vm_bo_find(vm, e->bo); + } + if (p->uf_bo) { + r = drm_exec_prepare_obj(&p->exec, &p->uf_bo->tbo.base, + 1 + p->gang_size); + drm_exec_retry_on_contention(&p->exec); + if (unlikely(r)) + goto error_free_pages; + } + } INIT_LIST_HEAD(&need_pages); amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) { - struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo); + struct amdgpu_bo *bo = e->bo; if (amdgpu_ttm_tt_userptr_invalidated(bo->tbo.ttm, &e->user_invalidated) && e->user_pages) { @@ -985,7 +1026,7 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, break; /* Unreserve everything again. */ - ttm_eu_backoff_reservation(&p->ticket, &p->validated); + drm_exec_fini(&p->exec); /* We tried too many times, just abort */ if (!--tries) { @@ -1015,37 +1056,9 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, goto error_free_pages; } } - - /* And try again. */ - list_splice(&need_pages, &p->validated); } #endif - amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) { - struct mm_struct *usermm; - - usermm = amdgpu_ttm_tt_get_usermm(e->bo->tbo.ttm); - if (usermm && usermm != current->mm) { - r = -EPERM; - goto out_free_user_pages; - } - - if (amdgpu_ttm_tt_is_userptr(e->bo->tbo.ttm) && - e->user_invalidated && e->user_pages) { - amdgpu_bo_placement_from_domain(e->bo, - AMDGPU_GEM_DOMAIN_CPU); - r = ttm_bo_validate(&e->bo->tbo, &e->bo->placement, - &ctx); - if (r) - goto out_free_user_pages; - - amdgpu_ttm_tt_set_user_pages(e->bo->tbo.ttm, - e->user_pages); - } - - kvfree(e->user_pages); - e->user_pages = NULL; - } amdgpu_cs_get_threshold_for_moves(p->adev, &p->bytes_moved_threshold, &p->bytes_moved_vis_threshold); @@ -1083,8 +1096,8 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p, return 0; -#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED out_free_user_pages: +#ifdef HAVE_AMDKCL_HMM_MIRROR_ENABLED amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) { struct amdgpu_bo *bo = e->bo; @@ -1468,13 +1481,13 @@ static int amdgpu_cs_submit(struct amdgpu_cs_parser *p, if (p->jobs[i] == leader) continue; - dma_resv_add_fence(gobj->resv, + dma_resv_add_fence(amdkcl_gem_resvp(gobj), &p->jobs[i]->base.s_fence->finished, DMA_RESV_USAGE_READ); } /* The gang leader as remembered as writer */ - dma_resv_add_fence(gobj->resv, p->fence, DMA_RESV_USAGE_WRITE); + dma_resv_add_fence(amdkcl_gem_resvp(gobj), p->fence, DMA_RESV_USAGE_WRITE); } seq = amdgpu_ctx_add_fence(p->ctx, p->entities[p->gang_leader_idx], From 3f5c24823639bb0accf14cac63d1048327df03a9 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 4 Sep 2023 17:12:58 +0800 Subject: [PATCH 1085/1868] drm/amdkcl: fake macro static_assert() It's caused by ff6320eb2b5616b4843588b066652837e6972666 "drm/amdgpu: add UMSCH 4.0 api definition" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_build_bug.h | 10 ++++++++++ 2 files changed, 11 insertions(+) create mode 100644 include/kcl/kcl_build_bug.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index b6546e738c026..4744c221f7df3 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -115,4 +115,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_build_bug.h b/include/kcl/kcl_build_bug.h new file mode 100644 index 0000000000000..eb39ce95a8d7d --- /dev/null +++ b/include/kcl/kcl_build_bug.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_LINUX_BUILD_BUG_H +#define AMDKCL_LINUX_BUILD_BUG_H + +#ifndef static_assert +#define static_assert(expr, ...) __static_assert(expr, ##__VA_ARGS__, #expr) +#define __static_assert(expr, msg, ...) _Static_assert(expr, msg) +#endif + +#endif /* AMDKCL_LINUX_BUILD_BUG_H */ \ No newline at end of file From ff292ca25507c40d00b7ddbb088a208eff588977 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Sun, 17 Sep 2023 12:16:17 +0800 Subject: [PATCH 1086/1868] drm/amdkcl: fake kvrealloc It's caused by 5f5b3abc312ec75134dd2e18aedcdf85e512d669 drm/amdkcl: fake drm_exec_* Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdkcl/kcl_mm.c | 19 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/krealloc-array.m4 | 22 +++++++++++++++++++ include/kcl/kcl_slab.h | 4 ++++ 4 files changed, 46 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_mm.c b/drivers/gpu/drm/amd/amdkcl/kcl_mm.c index 637ecefbb9773..d2836f42adf31 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_mm.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_mm.c @@ -6,6 +6,7 @@ */ #include #include +#include #ifndef HAVE_MMPUT_ASYNC void (*_kcl_mmput_async)(struct mm_struct *mm); @@ -36,6 +37,24 @@ extern struct kmem_cache *(*_kcl_kmalloc_slab)(size_t size, gfp_t flags); #endif #endif /* HAVE_KMALLOC_SIZE_ROUNDUP */ +#ifndef HAVE_KVREALLOC +void *kvrealloc(const void *p, size_t oldsize, size_t newsize, gfp_t flags) +{ + void *newp; + + if (oldsize >= newsize) + return (void *)p; + newp = kvmalloc(newsize, flags); + if (!newp) + return NULL; + memcpy(newp, p, oldsize); + kvfree(p); + return newp; +} +EXPORT_SYMBOL(kvrealloc); +#endif + + void amdkcl_mm_init(void) { #ifndef HAVE_MMPUT_ASYNC diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 700bfc26381f9..6d8b9f86551ed 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -213,6 +213,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_LINUX_ATOMIC_LONG_TRY_CMPXCHG AC_AMDGPU_LINUX_LOCAL_TRY_CMPXCHG AC_AMDGPU_LINUX_DEVICE_CLASS + AC_AMDGPU_KVREALLOC AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/krealloc-array.m4 b/drivers/gpu/drm/amd/dkms/m4/krealloc-array.m4 index f9f0fa0a1862f..0cd6663de85ce 100644 --- a/drivers/gpu/drm/amd/dkms/m4/krealloc-array.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/krealloc-array.m4 @@ -16,3 +16,25 @@ AC_DEFUN([AC_AMDGPU_KREALLOC_ARRAY], [ ]) ]) ]) + +dnl # +dnl # +dnl #v5.15-11-g8587ca6f3415 mm: move kvmalloc-related functions to slab.h +dnl #v5.14-rc4-23-gde2860f46362 mm: Add kvrealloc() +dnl # +AC_DEFUN([AC_AMDGPU_KVREALLOC], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + #include + ], [ + void *p = NULL; + p = kvrealloc(NULL, 0, 0, GFP_KERNEL); + ], [ + AC_DEFINE(HAVE_KVREALLOC, 1, + [kvrealloc() is available]) + ]) + ]) +]) + diff --git a/include/kcl/kcl_slab.h b/include/kcl/kcl_slab.h index a23a565eab992..640242253c588 100644 --- a/include/kcl/kcl_slab.h +++ b/include/kcl/kcl_slab.h @@ -38,4 +38,8 @@ krealloc_array(void *p, size_t new_n, size_t new_size, gfp_t flags) size_t kmalloc_size_roundup(size_t size); #endif +#ifndef HAVE_KVREALLOC +extern void *kvrealloc(const void *p, size_t oldsize, size_t newsize, gfp_t flags); +#endif + #endif From e5a77298256cf57749f666f8e4cc1480ad5e0dfc Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 20 Sep 2023 15:43:50 +0800 Subject: [PATCH 1087/1868] drm/amdkcl: Test whether get_user_{pages/pages_remote}() wants {6/4} args It's caused by v6.4-rc4-55-gca5e863233e8 mm/gup: remove vmas parameter from get_user_pages_remote() v6.4-rc4-53-g54d020692b34 mm/gup: remove unused vmas parameter from get_user_pages() Signed-off-by: Asher Song --- .../drm/amd/dkms/m4/get-user-pages-remote.m4 | 17 +++++++++++++++-- drivers/gpu/drm/amd/dkms/m4/get-user-pages.m4 | 19 ++++++++++++++++--- include/kcl/backport/kcl_mm_backport.h | 4 ++++ 3 files changed, 35 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/get-user-pages-remote.m4 b/drivers/gpu/drm/amd/dkms/m4/get-user-pages-remote.m4 index e2fe781b7d7dc..d538ceb02d6b2 100644 --- a/drivers/gpu/drm/amd/dkms/m4/get-user-pages-remote.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/get-user-pages-remote.m4 @@ -37,8 +37,21 @@ AC_DEFUN([AC_AMDGPU_GET_USER_PAGES_REMOTE], [ AC_DEFINE(HAVE_GET_USER_PAGES_REMOTE_GUP_FLAGS, 1, [get_user_pages_remote() wants gup_flags parameter]) ],[ - AC_DEFINE(HAVE_GET_USER_PAGES_REMOTE_INTRODUCED, 1, - [get_user_pages_remote() is introduced with initial prototype]) + dnl # + dnl # commit v6.4-rc4-55-gca5e863233e8 + dnl # mm/gup: remove vmas parameter from get_user_pages_remote() + dnl # + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + get_user_pages_remote(NULL, 0, 0, 0, NULL, NULL); + ], [get_user_pages_remote],[mm/gup.c],[ + AC_DEFINE(HAVE_GET_USER_PAGES_REMOTE_REMOVE_VMAS, 1, + [get_user_pages_remote() remove argument vmas]) + ],[ + AC_DEFINE(HAVE_GET_USER_PAGES_REMOTE_INTRODUCED, 1, + [get_user_pages_remote() is introduced with initial prototype]) + ]) ]) ]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/get-user-pages.m4 b/drivers/gpu/drm/amd/dkms/m4/get-user-pages.m4 index 7f9931fdf453f..8042f69a0228e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/get-user-pages.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/get-user-pages.m4 @@ -24,7 +24,20 @@ AC_DEFUN([AC_AMDGPU_GET_USER_PAGES], [ ], [get_user_pages], [mm/gup.c], [ AC_DEFINE(HAVE_GET_USER_PAGES_6ARGS, 1, [get_user_pages() wants 6 args]) - ]) - ]) - ]) + ],[ + dnl # + dnl # commit v6.4-rc4-53-g54d020692b34 + dnl # mm/gup: remove unused vmas parameter from get_user_pages() + dnl # + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + get_user_pages(0, 0, 0, NULL); + ], [get_user_pages], [mm/gup.c], [ + AC_DEFINE(HAVE_GET_USER_PAGES_REMOVE_VMAS, 1, + [get_user_pages() remove vmas argument]) + ]) + ]) + ]) + ]) ]) diff --git a/include/kcl/backport/kcl_mm_backport.h b/include/kcl/backport/kcl_mm_backport.h index 48312d64e5869..27c77cd60bbea 100644 --- a/include/kcl/backport/kcl_mm_backport.h +++ b/include/kcl/backport/kcl_mm_backport.h @@ -31,6 +31,8 @@ long kcl_get_user_pages_remote(struct task_struct *tsk, struct mm_struct *mm, #elif defined(HAVE_GET_USER_PAGES_REMOTE_INTRODUCED) return get_user_pages_remote(tsk, mm, start, nr_pages, !!(gup_flags & FOLL_WRITE), !!(gup_flags & FOLL_FORCE), pages, vmas); +#elif defined(HAVE_GET_USER_PAGES_REMOTE_REMOVE_VMAS) + return get_user_pages_remote(mm, start, nr_pages, gup_flags, pages, locked); #else return get_user_pages(tsk, mm, start, nr_pages, !!(gup_flags & FOLL_WRITE), !!(gup_flags & FOLL_FORCE), pages, vmas); @@ -46,6 +48,8 @@ long _kcl_get_user_pages(unsigned long start, unsigned long nr_pages, #if defined(HAVE_GET_USER_PAGES_6ARGS) return get_user_pages(start, nr_pages, !!(gup_flags & FOLL_WRITE), !!(gup_flags & FOLL_FORCE), pages, vmas); +#elif defined(HAVE_GET_USER_PAGES_REMOVE_VMAS) + return get_user_pages(start, nr_pages, gup_flags, pages); #else return get_user_pages(current, current->mm, start, nr_pages, !!(gup_flags & FOLL_WRITE), !!(gup_flags & FOLL_FORCE), pages, vmas); From eb3dc2fbc5ffdbdee8b49ba19620bbac616aa7e6 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 20 Sep 2023 16:20:08 +0800 Subject: [PATCH 1088/1868] drm/amdkcl: Test struct drm_driver whether has member gem_prime_mmap It's caused by v6.4-rc2-425-g0adec22702d4 drm: Remove struct drm_driver.gem_prime_mmap Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 5 +++++ .../dkms/m4/drm-driver-gem-prime-res-obj.m4 | 20 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 26 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 4a78aaadde6ba..586c24c0f93e6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3080,7 +3080,9 @@ static struct drm_driver amdgpu_kms_driver = { .gem_prime_vunmap = amdgpu_gem_prime_vunmap, #endif +#ifdef HAVE_DRM_DRIVER_GEM_PRIME_MMAP .gem_prime_mmap = amdkcl_drm_gem_prime_mmap, +#endif .name = DRIVER_NAME, .desc = DRIVER_DESC, @@ -3108,6 +3110,9 @@ const struct drm_driver amdgpu_partition_driver = { .release = &amdgpu_driver_release_kms, .gem_prime_import = amdgpu_gem_prime_import, +#ifdef HAVE_DRM_DRIVER_GEM_PRIME_MMAP + .gem_prime_mmap = drm_gem_prime_mmap, +#endif .name = DRIVER_NAME, .desc = DRIVER_DESC, diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-prime-res-obj.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-prime-res-obj.m4 index 226e89eebe85c..80cba3a5a1459 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-prime-res-obj.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-driver-gem-prime-res-obj.m4 @@ -16,3 +16,23 @@ AC_DEFUN([AC_AMDGPU_DRM_DRIVER_GEM_PRIME_RES_OBJ], [ ]) ]) ]) +dnl # +dnl # commit 4.9-rc4-834-g85e634bce01a +dnl # drm: Extract drm_drv.h +dnl # +dnl # commit v6.4-rc2-425-g0adec22702d4 +dnl # drm: Remove struct drm_driver.gem_prime_mmap +AC_DEFUN([AC_AMDGPU_DRM_DRIVER_GEM_PRIME_MMAP], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + struct drm_driver *drv = NULL; + drv->gem_prime_mmap(NULL, NULL); + ], [ + AC_DEFINE(HAVE_DRM_DRIVER_GEM_PRIME_MMAP, 1, + [drm_driver->gem_prime_mmap() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 6d8b9f86551ed..d34597f9223d3 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -214,6 +214,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_LINUX_LOCAL_TRY_CMPXCHG AC_AMDGPU_LINUX_DEVICE_CLASS AC_AMDGPU_KVREALLOC + AC_AMDGPU_DRM_DRIVER_GEM_PRIME_MMAP AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 34aedff499fed639f3c1a91f8815f456648546b4 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 20 Sep 2023 18:26:24 +0800 Subject: [PATCH 1089/1868] drm/amdkcl: update config.h Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/config/config.h | 49 ++++++++++++++++++------ drivers/gpu/drm/amd/dkms/configure.ac | 2 +- 2 files changed, 39 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index f37a26f5fd2cb..790db3b7f5844 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -25,9 +25,6 @@ /* acpi_video_register_backlight() is available */ #define HAVE_ACPI_VIDEO_REGISTER_BACKLIGHT 1 -/* acpi_video_report_nolcd() is available */ -#define HAVE_ACPI_VIDEO_REPORT_NOLCD 1 - /* whether AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES is defined */ #define HAVE_AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 1 @@ -425,9 +422,15 @@ /* drm_dp_update_payload_part1() function has start_slot argument */ /* #undef HAVE_DRM_DP_UPDATE_PAYLOAD_PART1_START_SLOT_ARG */ +/* drm_driver->gem_prime_mmap() is available */ +/* #undef HAVE_DRM_DRIVER_GEM_PRIME_MMAP */ + /* drm_driver->gem_prime_res_obj() is available */ /* #undef HAVE_DRM_DRIVER_GEM_PRIME_RES_OBJ */ +/* drm_driver->show_fdinfo() is available */ +#define HAVE_DRM_DRIVER_SHOW_FDINFO 1 + /* Define to 1 if you have the header file. */ /* #undef HAVE_DRM_DRMP_H */ @@ -446,6 +449,9 @@ /* Define to 1 if you have the header file. */ /* #undef HAVE_DRM_DRM_BACKPORT_H */ +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_EXEC_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_FBDEV_GENERIC_H 1 @@ -528,7 +534,7 @@ /* drm_gem_object_put() is exported */ /* #undef HAVE_DRM_GEM_OBJECT_PUT_SYMBOL */ -/* ttm_buffer_object->base is available */ +/* drm_gem_object->resv/_resv is available */ #define HAVE_DRM_GEM_OBJECT_RESV 1 /* drm_gem_plane_helper_prepare_fb() is available */ @@ -607,6 +613,9 @@ /* drm_print_bits() has 4 args */ #define HAVE_DRM_PRINT_BITS_4ARGS 1 +/* drm_show_fdinfo() is available */ +#define HAVE_DRM_SHOW_FDINFO 1 + /* drm_simple_encoder is available */ #define HAVE_DRM_SIMPLE_ENCODER_INIT 1 @@ -641,7 +650,7 @@ /* #undef HAVE_GET_USER_PAGES_6ARGS */ /* get_user_pages() wants gup_flags parameter */ -#define HAVE_GET_USER_PAGES_GUP_FLAGS 1 +/* #undef HAVE_GET_USER_PAGES_GUP_FLAGS */ /* get_user_pages_remote() wants gup_flags parameter */ /* #undef HAVE_GET_USER_PAGES_REMOTE_GUP_FLAGS */ @@ -653,7 +662,13 @@ /* #undef HAVE_GET_USER_PAGES_REMOTE_LOCKED */ /* get_user_pages_remote() remove task_struct pointer */ -#define HAVE_GET_USER_PAGES_REMOTE_REMOVE_TASK_STRUCT 1 +/* #undef HAVE_GET_USER_PAGES_REMOTE_REMOVE_TASK_STRUCT */ + +/* get_user_pages_remote() remove argument vmas */ +#define HAVE_GET_USER_PAGES_REMOTE_REMOVE_VMAS 1 + +/* get_user_pages() remove vmas argument */ +#define HAVE_GET_USER_PAGES_REMOVE_VMAS 1 /* drm_connector_hdr_sink_metadata() is available */ #define HAVE_HDR_SINK_METADATA 1 @@ -736,9 +751,15 @@ /* ktime_t is union */ /* #undef HAVE_KTIME_IS_UNION */ +/* kvrealloc() is available */ +#define HAVE_KVREALLOC 1 + /* Define to 1 if you have the header file. */ #define HAVE_LINUX_APPLE_GMUX_H 1 +/* atomic_long_try_cmpxchg() is available */ +#define HAVE_LINUX_ATOMIC_LONG_TRY_CMPXCHG 1 + /* Define to 1 if you have the header file. */ #define HAVE_LINUX_BITS_H 1 @@ -751,6 +772,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_CONTAINER_OF_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_DEVICE_CLASS_H 1 + /* Define to 1 if you have the header file. */ /* #undef HAVE_LINUX_DMA_ATTRS_H */ @@ -775,8 +799,8 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_IO_64_NONATOMIC_LO_HI_H 1 -/* Define to 1 if you have the header file. */ -#define HAVE_LINUX_MEM_ENCRYPT_H 1 +/* local_try_cmpchg() is available */ +#define HAVE_LINUX_LOCAL_TRY_CMPXCHG 1 /* Define to 1 if you have the header file. */ #define HAVE_LINUX_MMAP_LOCK_H 1 @@ -856,6 +880,9 @@ /* release_pages() wants 2 args */ #define HAVE_MM_RELEASE_PAGES_2ARGS 1 +/* class_create has one argument */ +#define HAVE_ONE_ARGUMENT_OF_CLASS_CREATE 1 + /* pcie_aspm_enabled() is available */ #define HAVE_PCIE_ASPM_ENABLED 1 @@ -1029,7 +1056,7 @@ #define HAVE_VMF_INSERT 1 /* vmf_insert_mixed_prot() is available */ -#define HAVE_VMF_INSERT_MIXED_PROT 1 +/* #undef HAVE_VMF_INSERT_MIXED_PROT */ /* vmf_insert_pfn_{pmd,pud}() wants 3 args */ /* #undef HAVE_VMF_INSERT_PFN_PMD_3ARGS */ @@ -1089,7 +1116,7 @@ #define PACKAGE_NAME "amdgpu-dkms" /* Define to the full name and version of this package. */ -#define PACKAGE_STRING "amdgpu-dkms 6.2.0" +#define PACKAGE_STRING "amdgpu-dkms 6.5.0" /* Define to the one symbol short name of this package. */ #define PACKAGE_TARNAME "amdgpu-dkms" @@ -1098,7 +1125,7 @@ #define PACKAGE_URL "" /* Define to the version of this package. */ -#define PACKAGE_VERSION "6.3.0" +#define PACKAGE_VERSION "6.5.0" #include "config-amd-chips.h" diff --git a/drivers/gpu/drm/amd/dkms/configure.ac b/drivers/gpu/drm/amd/dkms/configure.ac index c6b7d1e343742..666a4766a10b2 100644 --- a/drivers/gpu/drm/amd/dkms/configure.ac +++ b/drivers/gpu/drm/amd/dkms/configure.ac @@ -1,4 +1,4 @@ -AC_INIT(amdgpu-dkms, 6.3.0) +AC_INIT(amdgpu-dkms, 6.5.0) AC_LANG(C) AC_CONFIG_AUX_DIR([config]) From 65a96c4495c0241f4d723d8cdb7cb0a8fa9ebc29 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 27 Sep 2023 17:01:59 +0800 Subject: [PATCH 1090/1868] drm/amdkcl: assign to .prime_handle_to_fd and .prime_fd_to_handle of amdgpu_kms_driver It's caused by v6.4-rc7-1904-g71a7974ac701 drm/prime: Unexport helpers for fd/handle conversion Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 9 +++++++++ drivers/gpu/drm/amd/dkms/m4/drm_prime.m4 | 20 ++++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 30 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 586c24c0f93e6..a0a615e76984b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3056,6 +3056,11 @@ static struct drm_driver amdgpu_kms_driver = { #endif #endif +#ifdef HAVE_DRM_GEM_PRIME_HANDLE_TO_FD + .prime_handle_to_fd = drm_gem_prime_handle_to_fd, + .prime_fd_to_handle = drm_gem_prime_fd_to_handle, +#endif + #ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK .gem_prime_export = amdgpu_gem_prime_export, #endif @@ -3109,6 +3114,10 @@ const struct drm_driver amdgpu_partition_driver = { .fops = &amdgpu_driver_kms_fops, .release = &amdgpu_driver_release_kms, +#ifdef HAVE_DRM_GEM_PRIME_HANDLE_TO_FD + .prime_handle_to_fd = drm_gem_prime_handle_to_fd, + .prime_fd_to_handle = drm_gem_prime_fd_to_handle, +#endif .gem_prime_import = amdgpu_gem_prime_import, #ifdef HAVE_DRM_DRIVER_GEM_PRIME_MMAP .gem_prime_mmap = drm_gem_prime_mmap, diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_prime.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_prime.m4 index bae97886408be..5d14a0d6b877a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_prime.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_prime.m4 @@ -14,3 +14,23 @@ AC_DEFUN([AC_AMDGPU_DRM_PRIME_SG_TO_DMA_ADDR_ARRAY], [ ]) ]) ]) + +dnl # +dnl # commit v3.3-9296-g3248877ea179 +dnl # drm: base prime/dma-buf support (v5) +dnl # +dnl # commit v6.4-rc7-1904-g71a7974ac701 +dnl # drm/prime: Unexport helpers for fd/handle conversion +dnl # +AC_DEFUN([AC_AMDGPU_DRM_GEM_PRIME_HANDLE_TO_FD], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + drm_gem_prime_handle_to_fd(NULL, NULL, 0, 0, NULL); + ],[drm_gem_prime_handle_to_fd], [drivers/gpu/drm/drm_prime.c], [ + AC_DEFINE(HAVE_DRM_GEM_PRIME_HANDLE_TO_FD, 1, + [drm_gem_prime_handle_to_fd() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index d34597f9223d3..b7a9e72d6c850 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -215,6 +215,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_LINUX_DEVICE_CLASS AC_AMDGPU_KVREALLOC AC_AMDGPU_DRM_DRIVER_GEM_PRIME_MMAP + AC_AMDGPU_DRM_GEM_PRIME_HANDLE_TO_FD AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ From 55ec0fc3d0f2e88b395968b7569c78c25dc2010a Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 4 Sep 2023 15:39:25 +0800 Subject: [PATCH 1091/1868] drm/amdkcl: Fix unsteady amdgpu dkms build against 4.x kernels The error "Argument list too long" occur on rhel8.*, So extend the previous workaround to fix the error. Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/dkms/post-build.sh | 4 ++-- drivers/gpu/drm/amd/dkms/pre-build.sh | 6 +++--- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/post-build.sh b/drivers/gpu/drm/amd/dkms/post-build.sh index 962903db89aca..59ccb1bf481e6 100755 --- a/drivers/gpu/drm/amd/dkms/post-build.sh +++ b/drivers/gpu/drm/amd/dkms/post-build.sh @@ -3,9 +3,9 @@ KERNELVER=$1 # -# Restore original kernel 5.x scripts/Makefile.build modified by post-add.sh +# Restore original kernel 5.x and Kernel 4.x scripts/Makefile.build modified by post-add.sh # -if [[ ${KERNELVER%%.*} -eq 5 ]]; then +if [ ${KERNELVER%%.*} -eq 5 -o ${KERNELVER%%.*} -eq 4 ]; then moddir="/lib/modules/$KERNELVER" mkfile="scripts/Makefile.build" diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index cdbac6500036c..1eba510fa6eb1 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -60,10 +60,10 @@ done KERNELVER=$1 # -# Kernel 5.x scripts/Makefile.build patch +# Kernel 5.x and Kernel 4.x scripts/Makefile.build patch # The patch makes rules robust against "Argument list too long" error # -if [[ ${KERNELVER%%.*} -eq 5 ]]; then +if [ ${KERNELVER%%.*} -eq 5 -o ${KERNELVER%%.*} -eq 4 ]; then moddir="/lib/modules/$KERNELVER" mkfile="scripts/Makefile.build" @@ -80,7 +80,7 @@ if [[ ${KERNELVER%%.*} -eq 5 ]]; then sed -i -e "/^cmd_mod = {/,/} > \$@$/c"` `"cmd_mod = printf '%s\x5Cn' \$(call real-search, \$*.o, .o, -objs -y -m) | \\\\\n"` `"\t\$(AWK) '!x[\$\$0]++ { print(\"\$(obj)\/\"\$\$0) }' > \$@" \ - -e "s/^[[:space:]]\+cmd_link_multi-m =.*$/"` + -e "s/^[[:space:]]*cmd_link_multi-m = \$(LD).*$/"` `"cmd_link_multi-m = \\\\\n"` `"\t\$(file >\$@.in,\$(filter %.o,$^)) \\\\\n"` `"\t\$(LD) \$(ld_flags) -r -o \$@ @\$@.in; \\\\\n"` From 84c412ca2bba47f58f4ed2aa272bb8a446071857 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 27 Sep 2023 12:13:29 +0800 Subject: [PATCH 1092/1868] drm/amdkcl: eliminate the repetitive code Due to the following patch submmit twice, some code is repetitive, remove them. drm/amd/display: only accept async flips for fast updates Signed-off-by: Asher Song --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 12 ------------ 1 file changed, 12 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c index 2368505c3d9ae..cc86f8fb5b0a8 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c @@ -661,18 +661,6 @@ static int amdgpu_dm_crtc_helper_atomic_check(struct drm_crtc *crtc, return -EINVAL; } - /* - * Only allow async flips for fast updates that don't change the FB - * pitch, the DCC state, rotation, etc. - */ - if (crtc_state->async_flip && - dm_crtc_state->update_type != UPDATE_TYPE_FAST) { - drm_dbg_atomic(crtc->dev, - "[CRTC:%d:%s] async flips are only supported for fast updates\n", - crtc->base.id, crtc->name); - return -EINVAL; - } - /* In some use cases, like reset, no stream is attached */ if (!dm_crtc_state->stream) return 0; From bdd60dce876493d1f336da110775a80dd7b4baec Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 6 Sep 2023 11:15:25 +0800 Subject: [PATCH 1093/1868] drm/amdkcl: fix the missing build_bug.h and update config.h It's caused by ff6320eb2b5616b4843588b066652837e6972666 "drm/amdgpu: add UMSCH 4.0 api definition" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 | 7 ++++++- include/kcl/header/linux/build_bug.h | 9 +++++++++ include/kcl/kcl_build_bug.h | 2 ++ 4 files changed, 20 insertions(+), 1 deletion(-) create mode 100644 include/kcl/header/linux/build_bug.h diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 790db3b7f5844..bf6e58f5a9cbb 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -763,6 +763,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_BITS_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_BUILD_BUG_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_LINUX_CC_PLATFORM_H 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 index 557b1a1589e6d..a9a77d3a9cdf4 100644 --- a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 @@ -114,7 +114,7 @@ AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ dnl # dma-mapping: split dnl # AC_KERNEL_CHECK_HEADERS([linux/dma-map-ops.h]) - + dnl #v4.5-rc3-203-g2413306c2566 dnl #apple-gmux: Add helper for presence detect dnl @@ -124,4 +124,9 @@ AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ dnl #device.h: move 'struct class' stuff out to device/class.h dnl AC_KERNEL_CHECK_HEADERS([linux/device/class.h]) + + dnl #v4.12-10499-gbc6245e5efd7 + dnl #bug: split BUILD_BUG stuff out into + dnl + AC_KERNEL_CHECK_HEADERS([linux/build_bug.h]) ]) diff --git a/include/kcl/header/linux/build_bug.h b/include/kcl/header/linux/build_bug.h new file mode 100644 index 0000000000000..d97f9812224e1 --- /dev/null +++ b/include/kcl/header/linux/build_bug.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_LINUX_BUG_BUILD_H_H +#define _KCL_HEADER_LINUX_BUG_BUILD_H_H + +#ifdef HAVE_LINUX_BUILD_BUG_H +#include_next +#endif + +#endif \ No newline at end of file diff --git a/include/kcl/kcl_build_bug.h b/include/kcl/kcl_build_bug.h index eb39ce95a8d7d..7abac2512a33d 100644 --- a/include/kcl/kcl_build_bug.h +++ b/include/kcl/kcl_build_bug.h @@ -2,6 +2,8 @@ #ifndef AMDKCL_LINUX_BUILD_BUG_H #define AMDKCL_LINUX_BUILD_BUG_H +#include + #ifndef static_assert #define static_assert(expr, ...) __static_assert(expr, ##__VA_ARGS__, #expr) #define __static_assert(expr, msg, ...) _Static_assert(expr, msg) From 922fd2003a01112e228d98b0c2742568828a0754 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 8 Sep 2023 12:30:39 +0800 Subject: [PATCH 1094/1868] drm/amdkcl: kcl cleanup macro PCI_IRQ_MSI It's caused by df9155c8fe089418a999d7c0d188897cb694645c "drm/amd: Fix the flag setting code for interrupt request" The macro is included for fixing build for centos7.4 3.10.0-693.el7.x86_64. The latest system is rhel7.9 with kernel 3.10, so clean up the KCL macro. Signed-off-by: Bob Zhou Reviewed-by: Ma Jun --- drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c index c7aedaa69ea4e..0e890f2785b18 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c @@ -335,11 +335,7 @@ void amdgpu_irq_fini_hw(struct amdgpu_device *adev) free_irq(adev->irq.irq, adev_to_drm(adev)); adev->irq.installed = false; if (adev->irq.msi_enabled) -#ifdef PCI_IRQ_MSI pci_free_irq_vectors(adev->pdev); -#else - pci_disable_msi(adev->pdev); -#endif } amdgpu_ih_ring_fini(adev, &adev->irq.ih_soft); From a1ef05e4e122d6ee002816fa0f679e052944dc09 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 11 Sep 2023 14:50:39 +0800 Subject: [PATCH 1095/1868] drm/amdkcl: fake drm_dp_read_dpcd_caps() It's caused by 58b80b00d4e27a08ea10a281b7e79a4553b70557 "drm/amd/display: Adjust the MST resume flow" Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- .../gpu/drm/amd/amdkcl/kcl_drm_dp_helper.c | 118 ++++++++++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 + .../drm/amd/dkms/m4/drm_dp_read_dpcd_caps.m4 | 16 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../kcl/backport/kcl_drm_dp_helper_backport.h | 10 ++ 6 files changed, 149 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_dp_helper.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_dp_read_dpcd_caps.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index f1367b6447788..49b0fe52e6ddc 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -14,7 +14,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_fs_read_write.o kcl_drm_aperture.o \ kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o \ kcl_mce_amd.o kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o kcl_mm_slab.o \ - kcl_irqdesc.o kcl_drm_suballoc.o kcl_drm_file.o kcl_drm_exec.o + kcl_irqdesc.o kcl_drm_suballoc.o kcl_drm_file.o kcl_drm_exec.o kcl_drm_dp_helper.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_dp_helper.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_dp_helper.c new file mode 100644 index 0000000000000..c27581210a3d6 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_dp_helper.c @@ -0,0 +1,118 @@ +/* + * Copyright © 2009 Keith Packard + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE. + */ + +#include +#include +#include + +#ifndef HAVE_DRM_DP_READ_DPCD_CAPS +static int _kcl_drm_dp_read_extended_dpcd_caps(struct drm_dp_aux *aux, + u8 dpcd[DP_RECEIVER_CAP_SIZE]) +{ + u8 dpcd_ext[DP_RECEIVER_CAP_SIZE]; + int ret; + struct drm_device *drm_dev = NULL; + + if (aux) { + struct drm_dp_mst_topology_mgr *mgr = + container_of(&aux, struct drm_dp_mst_topology_mgr, aux); + drm_dev = mgr->dev; + } + /* + * Prior to DP1.3 the bit represented by + * DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT was reserved. + * If it is set DP_DPCD_REV at 0000h could be at a value less than + * the true capability of the panel. The only way to check is to + * then compare 0000h and 2200h. + */ + if (!(dpcd[DP_TRAINING_AUX_RD_INTERVAL] & + DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT)) + return 0; + + ret = drm_dp_dpcd_read(aux, DP_DP13_DPCD_REV, &dpcd_ext, + sizeof(dpcd_ext)); + if (ret < 0) + return ret; + if (ret != sizeof(dpcd_ext)) + return -EIO; + + if (dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV]) { + drm_dbg_kms( + drm_dev, + "%s: Extended DPCD rev less than base DPCD rev (%d > %d)\n", + aux->name, dpcd[DP_DPCD_REV], dpcd_ext[DP_DPCD_REV]); + return 0; + } + + if (!memcmp(dpcd, dpcd_ext, sizeof(dpcd_ext))) + return 0; + + drm_dbg_kms(drm_dev, "%s: Base DPCD: %*ph\n", aux->name, + DP_RECEIVER_CAP_SIZE, dpcd); + + memcpy(dpcd, dpcd_ext, sizeof(dpcd_ext)); + + return 0; +} + +/** + * drm_dp_read_dpcd_caps() - read DPCD caps and extended DPCD caps if + * available + * @aux: DisplayPort AUX channel + * @dpcd: Buffer to store the resulting DPCD in + * + * Attempts to read the base DPCD caps for @aux. Additionally, this function + * checks for and reads the extended DPRX caps (%DP_DP13_DPCD_REV) if + * present. + * + * Returns: %0 if the DPCD was read successfully, negative error code + * otherwise. + */ +int _kcl_drm_dp_read_dpcd_caps(struct drm_dp_aux *aux, + u8 dpcd[DP_RECEIVER_CAP_SIZE]) +{ + int ret; + struct drm_device *drm_dev = NULL; + + if (aux) { + struct drm_dp_mst_topology_mgr *mgr = + container_of(&aux, struct drm_dp_mst_topology_mgr, aux); + drm_dev = mgr->dev; + } + + ret = drm_dp_dpcd_read(aux, DP_DPCD_REV, dpcd, DP_RECEIVER_CAP_SIZE); + if (ret < 0) + return ret; + if (ret != DP_RECEIVER_CAP_SIZE || dpcd[DP_DPCD_REV] == 0) + return -EIO; + + ret = _kcl_drm_dp_read_extended_dpcd_caps(aux, dpcd); + if (ret < 0) + return ret; + + drm_dbg_kms(drm_dev, "%s: DPCD: %*ph\n", aux->name, + DP_RECEIVER_CAP_SIZE, dpcd); + + return ret; +} +EXPORT_SYMBOL(_kcl_drm_dp_read_dpcd_caps); +#endif \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index bf6e58f5a9cbb..18d7b3f34011d 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -413,6 +413,9 @@ /* struct drm_dp_mst_topology_state has member total_avail_slots */ #define HAVE_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS 1 +/* drm_dp_read_dpcd_caps() is available */ +#define HAVE_DRM_DP_READ_DPCD_CAPS 1 + /* drm_dp_send_real_edid_checksum() is available */ #define HAVE_DRM_DP_SEND_REAL_EDID_CHECKSUM 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dp_read_dpcd_caps.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dp_read_dpcd_caps.m4 new file mode 100644 index 0000000000000..dbd64ba5dbbe8 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dp_read_dpcd_caps.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.9-rc1-294-gb9936121d95b +dnl # drm/i915/dp: Extract drm_dp_read_dpcd_caps() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_READ_DPCD_CAPS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_dp_read_dpcd_caps(NULL, NULL); + ], [drm_dp_read_dpcd_caps], [drivers/gpu/drm/display/drm_dp_helper.c], [ + AC_DEFINE(HAVE_DRM_DP_READ_DPCD_CAPS, 1, + [drm_dp_read_dpcd_caps() is available]) + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index b7a9e72d6c850..ebfa588608087 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -186,6 +186,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_GEM_OBJECT_FUNCS_VMAP_HAS_IOSYS_MAP_ARG AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_BASE AC_AMDGPU_DRM_DSC_CONFIG_SIMPLE_422 + AC_AMDGPU_DRM_DP_READ_DPCD_CAPS AC_AMDGPU_DRM_DSC_PPS_PAYLOAD_PACK AC_AMDGPU_DRM_DSC_COMPUTE_RC_PARAMETERS AC_AMDGPU_DRM_GEM_PLANE_HELPER_PREPARE_FB diff --git a/include/kcl/backport/kcl_drm_dp_helper_backport.h b/include/kcl/backport/kcl_drm_dp_helper_backport.h index 4c541b78127d7..61b4a14bb0151 100644 --- a/include/kcl/backport/kcl_drm_dp_helper_backport.h +++ b/include/kcl/backport/kcl_drm_dp_helper_backport.h @@ -17,4 +17,14 @@ #if !defined(HAVE_DRM_DP_CEC_REGISTER_CONNECTOR_PP) #define drm_dp_cec_register_connector _kcl_drm_dp_cec_register_connector #endif + +#if !defined(HAVE_DRM_DP_READ_DPCD_CAPS) +int _kcl_drm_dp_read_dpcd_caps(struct drm_dp_aux *aux, + u8 dpcd[DP_RECEIVER_CAP_SIZE]); +static inline int drm_dp_read_dpcd_caps(struct drm_dp_aux *aux, + u8 dpcd[DP_RECEIVER_CAP_SIZE]) +{ + return _kcl_drm_dp_read_dpcd_caps(aux, dpcd); +} +#endif #endif From 52236cb3299746926b100a57f1db7a2195ff0377 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 14 Sep 2023 15:39:05 +0800 Subject: [PATCH 1096/1868] drm/amdkcl: fake drm_dp_add_payload_part{1,2}() It's caused by 7c5343f2a75336d865edea2d15f5f0234eaf8054 "drm/mst: Refactor the flow for payload allocation/removement" The function drm_dp_remove_payload() has been splited to two subfuctions, so add kcl macro bypass the new feature. Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 5 ++++- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../amd/dkms/m4/drm-dp-remove-payload-part.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 24 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-dp-remove-payload-part.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index 2f51d94082cf1..f25de432f8fa7 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -385,8 +385,11 @@ bool dm_helpers_dp_mst_write_payload_allocation_table( dm_helpers_construct_old_payload(mst_mgr, mst_state, new_payload, &old_payload); target_payload = &old_payload; - +#ifdef HAVE_DRM_DP_REMOVE_RAYLOAD_PART drm_dp_remove_payload_part1(mst_mgr, mst_state, new_payload); +#else + drm_dp_remove_payload(mst_mgr, mst_state, &old_payload, new_payload); +#endif } /* mst_mgr->->payloads are VC payload notify MST branch using DPCD or diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 18d7b3f34011d..c7e0f1f4fe7ff 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -416,6 +416,9 @@ /* drm_dp_read_dpcd_caps() is available */ #define HAVE_DRM_DP_READ_DPCD_CAPS 1 +/* drm_dp_remove_payload_part{1,2}() is available */ +#define HAVE_DRM_DP_REMOVE_RAYLOAD_PART 1 + /* drm_dp_send_real_edid_checksum() is available */ #define HAVE_DRM_DP_SEND_REAL_EDID_CHECKSUM 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-remove-payload-part.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-remove-payload-part.m4 new file mode 100644 index 0000000000000..10468731e64f9 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-remove-payload-part.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v6.3-5135-g7c5343f2a753 +dnl # "drm/mst: Refactor the flow for payload allocation/removement" +dnl +AC_DEFUN([AC_AMDGPU_DRM_DP_REMOVE_RAYLOAD_PART], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_dp_remove_payload_part1(NULL, NULL, NULL); + ], [drm_dp_remove_payload_part1],[drivers/gpu/drm/display/drm_dp_mst_topology.c],[ + AC_DEFINE(HAVE_DRM_DP_REMOVE_RAYLOAD_PART, 1, + [drm_dp_remove_payload_part{1,2}() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index ebfa588608087..708726cd3db51 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -187,6 +187,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_BASE AC_AMDGPU_DRM_DSC_CONFIG_SIMPLE_422 AC_AMDGPU_DRM_DP_READ_DPCD_CAPS + AC_AMDGPU_DRM_DP_REMOVE_RAYLOAD_PART AC_AMDGPU_DRM_DSC_PPS_PAYLOAD_PACK AC_AMDGPU_DRM_DSC_COMPUTE_RC_PARAMETERS AC_AMDGPU_DRM_GEM_PLANE_HELPER_PREPARE_FB From 9f35f908cff69859181e9834650d2a368f38837d Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 15 Sep 2023 15:24:23 +0800 Subject: [PATCH 1097/1868] drm/amdkcl: wrap code under macro DEFINE_DEBUGFS_ATTRIBUTE It's caused by 402742b54302cbf0faf126cdf2c7c01265ffb586 "drm/amdgpu: add amdgpu mca debug sysfs support" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c index 18ee60378727f..e1ce65d097394 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c @@ -594,8 +594,10 @@ static const struct file_operations mca_ue_dump_debug_fops = { .release = single_release, }; +#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(mca_debug_mode_fops, NULL, amdgpu_mca_smu_debug_mode_set, "%llu\n"); #endif +#endif void amdgpu_mca_smu_debugfs_init(struct amdgpu_device *adev, struct dentry *root) { @@ -603,7 +605,9 @@ void amdgpu_mca_smu_debugfs_init(struct amdgpu_device *adev, struct dentry *root if (!root) return; +#ifdef DEFINE_DEBUGFS_ATTRIBUTE debugfs_create_file("mca_debug_mode", 0200, root, adev, &mca_debug_mode_fops); +#endif debugfs_create_file("mca_ue_dump", 0400, root, adev, &mca_ue_dump_debug_fops); debugfs_create_file("mca_ce_dump", 0400, root, adev, &mca_ce_dump_debug_fops); #endif From 849f799c5138d01dcbe9121fdeaadbf9f15d39ba Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 18 Sep 2023 13:39:35 +0800 Subject: [PATCH 1098/1868] drm/amdkcl: fix function return in HAVE_DMA_FENCE_CHAIN_ALLOC To support rhel9.3, add function return verify in M4 HAVE_DMA_FENCE_CHAIN_ALLOC Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/m4/dma-fence-chain.m4 | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-fence-chain.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-fence-chain.m4 index 1627d69677f9e..f35b2f8d404ca 100644 --- a/drivers/gpu/drm/amd/dkms/m4/dma-fence-chain.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/dma-fence-chain.m4 @@ -7,7 +7,8 @@ AC_DEFUN([AC_AMDGPU_DMA_FENCE_CHAIN_ALLOC], [ AC_KERNEL_TRY_COMPILE([ #include ], [ - dma_fence_chain_alloc(); + struct dma_fence_chain *chain = NULL; + chain = dma_fence_chain_alloc(); ], [ AC_DEFINE(HAVE_DMA_FENCE_CHAIN_ALLOC, 1, [dma_fence_chain_alloc() is available]) From ce90598ceacfc407c11fe0656e78452212138f06 Mon Sep 17 00:00:00 2001 From: Vignesh Chander Date: Tue, 12 Sep 2023 23:43:38 -0500 Subject: [PATCH 1099/1868] drm/amdgpu/jpeg - skip set pg for sriov Change-Id: I098a39c590502f675b7174f20f3cc17e510451d0 Signed-off-by: Vignesh Chander --- drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c index 6ae5a784e1874..c30c4cc3bb991 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c @@ -363,10 +363,8 @@ static int jpeg_v4_0_3_hw_fini(void *handle) cancel_delayed_work_sync(&adev->jpeg.idle_work); - if (!amdgpu_sriov_vf(adev)) { - if (adev->jpeg.cur_state != AMD_PG_STATE_GATE) - ret = jpeg_v4_0_3_set_powergating_state(adev, AMD_PG_STATE_GATE); - } + if (adev->jpeg.cur_state != AMD_PG_STATE_GATE) + ret = jpeg_v4_0_3_set_powergating_state(adev, AMD_PG_STATE_GATE); return ret; } From dd13731ca324c98ace75174a8a7ed9bb8abb6e70 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 25 Sep 2023 12:48:51 +0800 Subject: [PATCH 1100/1868] drm/amdkcl: fake drm_dbg_dp() It's caused by ec1e3bdbb037d7d4397cb8c14db801cc3b839860 "drm/amd/display: switch DC over to the new DRM logging macros" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- include/kcl/kcl_drm_print.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index 15abde9faeb53..c1aa05a71ff23 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -137,6 +137,11 @@ void kcl_drm_err(const char *format, ...); drm_dev_dbg((drm)->dev, 0x04, fmt, ##__VA_ARGS__) #endif +#if !defined(drm_dbg_dp) +#define drm_dbg_dp(drm, fmt, ...) \ + drm_dev_dbg((drm) ? (drm)->dev : NULL, DRM_UT_DP, fmt, ##__VA_ARGS__) +#endif + #ifndef HAVE_DRM_DEBUG_ENABLED /* Copied from v5.3-rc1-708-gf0a8f533adc2 include/drm/drm_print.h */ static inline bool drm_debug_enabled(unsigned int category) From 946e5886b9664650251a7c505819f1a8af129084 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 25 Sep 2023 12:50:14 +0800 Subject: [PATCH 1101/1868] drm/amdkcl: wrap code under macro HAVE_DRM_DP_AUX_DRM_DEV and HAVE_KTIME_IS_UNION It's caused by ec1e3bdbb037d7d4397cb8c14db801cc3b839860 "drm/amd/display: switch DC over to the new DRM logging macros" the old macro DC_LOG_DC has been modified, so update DC_LOG_DC to DRM_DEBUG_KMS. Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++-- .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 23 ++++++++++++++----- 2 files changed, 19 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 57d4ac81b81e7..a3b6a798bd94f 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -540,8 +540,8 @@ static void dm_vupdate_high_irq(void *interrupt_params) struct common_irq_params *irq_params = interrupt_params; struct amdgpu_device *adev = irq_params->adev; struct amdgpu_crtc *acrtc; -#ifndef HAVE_KTIME_IS_UNION struct drm_device *drm_dev; +#ifndef HAVE_KTIME_IS_UNION struct drm_vblank_crtc *vblank; ktime_t frame_duration_ns, previous_timestamp; #endif @@ -552,8 +552,8 @@ static void dm_vupdate_high_irq(void *interrupt_params) if (acrtc) { vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc); -#ifndef HAVE_KTIME_IS_UNION drm_dev = acrtc->base.dev; +#ifndef HAVE_KTIME_IS_UNION vblank = drm_crtc_vblank_crtc(&acrtc->base); previous_timestamp = atomic64_read(&irq_params->previous_timestamp); frame_duration_ns = get_drm_vblank_crtc_time(vblank) - previous_timestamp; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index f25de432f8fa7..be20e9b61c304 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -872,8 +872,11 @@ static bool execute_synaptics_rc_command(struct drm_dp_aux *aux, // read rc data drm_dp_dpcd_read(aux, SYNAPTICS_RC_DATA, data, length); } - +#ifdef HAVE_DRM_DP_AUX_DRM_DEV drm_dbg_dp(aux->drm_dev, "success = %d\n", success); +#else + DRM_DEBUG_KMS("%s: success = %d\n", __func__, success); +#endif return success; } @@ -881,9 +884,11 @@ static bool execute_synaptics_rc_command(struct drm_dp_aux *aux, static void apply_synaptics_fifo_reset_wa(struct drm_dp_aux *aux) { unsigned char data[16] = {0}; - +#ifdef HAVE_DRM_DP_AUX_DRM_DEV drm_dbg_dp(aux->drm_dev, "Start\n"); - +#else + DRM_DEBUG_KMS("Start %s\n", __func__); +#endif // Step 2 data[0] = 'P'; data[1] = 'R'; @@ -939,8 +944,11 @@ static void apply_synaptics_fifo_reset_wa(struct drm_dp_aux *aux) // Step 6 if (!execute_synaptics_rc_command(aux, true, 0x02, 0, 0, NULL)) return; - +#ifdef HAVE_DRM_DP_AUX_DRM_DEV drm_dbg_dp(aux->drm_dev, "Done\n"); +#else + DRM_DEBUG_KMS("Done %s\n", __func__); +#endif } /* MST Dock */ @@ -952,9 +960,12 @@ static uint8_t write_dsc_enable_synaptics_non_virtual_dpcd_mst( bool enable) { uint8_t ret = 0; - +#ifdef HAVE_DRM_DP_AUX_DRM_DEV drm_dbg_dp(aux->drm_dev, "Configure DSC to non-virtual dpcd synaptics\n"); +#else + DRM_DEBUG_KMS("Configure DSC to non-virtual dpcd synaptics\n"); +#endif if (enable) { /* When DSC is enabled on previous boot and reboot with the hub, @@ -1054,7 +1065,7 @@ bool dm_helpers_dp_write_dsc_enable( } #else ret = drm_dp_dpcd_write(aconnector->dsc_aux, DP_DSC_ENABLE, &enable_dsc, 1); - DC_LOG_DC("Send DSC %s to MST RX\n", enable_dsc ? "enable" : "disable"); + DRM_DEBUG_KMS("Send DSC %s to MST RX\n", enable_dsc ? "enable" : "disable"); #endif } From 83a025a7215a44fbcee80456f6f3ead822352952 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 9 Oct 2023 14:03:46 +0800 Subject: [PATCH 1102/1868] drm/amdkcl: keep drm DPCD declarations for KCL It's caused by f53df85fbe6576ea111f11333ae3fbcd9d9220f3 "drm/amd/display: Remove unused DPCD declarations" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_drm_dp.h | 67 +++++++++++++++++++++++++ 2 files changed, 68 insertions(+) create mode 100644 include/kcl/kcl_drm_dp.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 4744c221f7df3..e2331135ef531 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -116,4 +116,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_drm_dp.h b/include/kcl/kcl_drm_dp.h new file mode 100644 index 0000000000000..1f277a16b5874 --- /dev/null +++ b/include/kcl/kcl_drm_dp.h @@ -0,0 +1,67 @@ +/* + * Copyright © 2008 Keith Packard + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that copyright + * notice and this permission notice appear in supporting documentation, and + * that the name of the copyright holders not be used in advertising or + * publicity pertaining to distribution of the software without specific, + * written prior permission. The copyright holders make no representations + * about the suitability of this software for any purpose. It is provided "as + * is" without express or implied warranty. + * + * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE + * OF THIS SOFTWARE. + */ +#ifndef _KCL_DRM_DP_H +#define _KCL_DRM_DP_H + +#ifndef DP_SINK_VIDEO_FALLBACK_FORMATS +#define DP_SINK_VIDEO_FALLBACK_FORMATS 0x020 +#endif +#ifndef DP_FEC_CAPABILITY_1 +#define DP_FEC_CAPABILITY_1 0x091 +#endif + +#ifndef DP_DSC_CONFIGURATION +#define DP_DSC_CONFIGURATION 0x161 +#endif +#ifndef DP_PHY_SQUARE_PATTERN +#define DP_PHY_SQUARE_PATTERN 0x249 +#endif + +#ifndef DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0 +#define DP_DSC_MAX_SLICE_COUNT_AND_AGGREGATION_0 0x2270 +#endif +#ifndef DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK +#define DP_DSC_DECODER_0_MAXIMUM_SLICE_COUNT_MASK (1 << 0) +#endif +#ifndef DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK +#define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_MASK (0b111 << 1) +#endif +#ifndef DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT +#define DP_DSC_DECODER_0_AGGREGATION_SUPPORT_SHIFT 1 +#endif +#ifndef DP_DSC_DECODER_COUNT_MASK +#define DP_DSC_DECODER_COUNT_MASK (0b111 << 5) +#endif +#ifndef DP_DSC_DECODER_COUNT_SHIFT +#define DP_DSC_DECODER_COUNT_SHIFT 5 +#endif +#ifndef DP_MAIN_LINK_CHANNEL_CODING_SET +#define DP_MAIN_LINK_CHANNEL_CODING_SET 0x108 +#endif +#ifndef DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER +#define DP_MAIN_LINK_CHANNEL_CODING_PHY_REPEATER 0xF0006 +#endif +#ifndef DP_INTRA_HOP_AUX_REPLY_INDICATION +#define DP_INTRA_HOP_AUX_REPLY_INDICATION (1 << 3) +#endif + +#endif \ No newline at end of file From 0340ac0cac4aa6621fee55346f231c3b0802a45a Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 9 Oct 2023 14:12:29 +0800 Subject: [PATCH 1103/1868] drm/amdkcl: test whether drm_connector_helper_funcs->prepare_writeback_job is available It's caused by 457ca82075a522bc5655d0abe363761d05ab2609 "drm/amd/display: Initialize writeback connector" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../amd/dkms/m4/drm_connector_helper_funcs.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 3 files changed, 21 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_connector_helper_funcs.m4 diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index c7e0f1f4fe7ff..6636f86146199 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -205,6 +205,9 @@ arg */ #define HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_CHECK_ARG_DRM_ATOMIC_STATE 1 +/* drm_connector_helper_funcs->prepare_writeback_job is available */ +#define HAVE_DRM_CONNECTOR_HELPER_FUNCS_PREPARE_WRITEBACK_JOB 1 + /* drm_connector_init_with_ddc() is available */ #define HAVE_DRM_CONNECTOR_INIT_WITH_DDC 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_connector_helper_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_connector_helper_funcs.m4 new file mode 100644 index 0000000000000..fe75c0300c099 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_connector_helper_funcs.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # v5.1-rc1-14-g9d2230dc1351 +dnl # drm: writeback: Add job prepare and cleanup operations +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_HELPER_FUNCS_PREPARE_WRITEBACK_JOB], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_connector_helper_funcs *funcs; + funcs->prepare_writeback_job = NULL; + ],[ + AC_DEFINE(HAVE_DRM_CONNECTOR_HELPER_FUNCS_PREPARE_WRITEBACK_JOB, 1, + [drm_connector_helper_funcs->prepare_writeback_job is available]) + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 708726cd3db51..b9c4235a0b357 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -79,6 +79,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU___DRM_ATOMIC_HELPER_CRTC_RESET AC_AMDGPU_PCI_PR3_PRESENT AC_AMDGPU_KTHREAD_USE_MM + AC_AMDGPU_DRM_CONNECTOR_HELPER_FUNCS_PREPARE_WRITEBACK_JOB AC_AMDGPU_DRM_FB_HELPER_FILL_INFO AC_AMDGPU_DRM_FB_HELPER_INIT AC_AMDGPU_DRM_HELPER_FORCE_DISABLE_ALL From 0a303a8c972287014ac35d614e7bd24651f16885 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 9 Oct 2023 14:13:50 +0800 Subject: [PATCH 1104/1868] drm/amdkcl: test whether drm_writeback_connector_init() has 7 args It's caused by 457ca82075a522bc5655d0abe363761d05ab2609 "drm/amd/display: Initialize writeback connector" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 ++ .../dkms/m4/drm_writeback_connector_init.m4 | 16 ++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_writeback.h | 31 +++++++++++++++++++ 5 files changed, 52 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_writeback_connector_init.m4 create mode 100644 include/kcl/kcl_drm_writeback.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index e2331135ef531..a504ed69b614e 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -117,4 +117,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 6636f86146199..15b79f7fc344f 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -640,6 +640,9 @@ /* struct drm_vma_offset_node has readonly field */ /* #undef HAVE_DRM_VMA_OFFSET_NODE_READONLY_FIELD */ +/* drm_writeback_connector_init() has 7 args */ +#define HAVE_DRM_WRITEBACK_CONNECTOR_INIT_7_ARGS 1 + /* fault_flag_allow_retry_first() is available */ #define HAVE_FAULT_FLAG_ALLOW_RETRY_FIRST 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_writeback_connector_init.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_writeback_connector_init.m4 new file mode 100644 index 0000000000000..7f2c208c36f96 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_writeback_connector_init.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v5.18-rc2-67-g57b8280a0a41 +dnl # drm: allow passing possible_crtcs to drm_writeback_connector_init() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_WRITEBACK_CONNECTOR_INIT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + drm_writeback_connector_init(NULL, NULL, NULL, NULL, NULL, 0, 0); + ],[drm_writeback_connector_init], [drivers/gpu/drm/drm_writeback.c],[ + AC_DEFINE(HAVE_DRM_WRITEBACK_CONNECTOR_INIT_7_ARGS, 1, + [drm_writeback_connector_init() has 7 args]) + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index b9c4235a0b357..44aec9ad47137 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -79,6 +79,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU___DRM_ATOMIC_HELPER_CRTC_RESET AC_AMDGPU_PCI_PR3_PRESENT AC_AMDGPU_KTHREAD_USE_MM + AC_AMDGPU_DRM_WRITEBACK_CONNECTOR_INIT AC_AMDGPU_DRM_CONNECTOR_HELPER_FUNCS_PREPARE_WRITEBACK_JOB AC_AMDGPU_DRM_FB_HELPER_FILL_INFO AC_AMDGPU_DRM_FB_HELPER_INIT diff --git a/include/kcl/kcl_drm_writeback.h b/include/kcl/kcl_drm_writeback.h new file mode 100644 index 0000000000000..14b6d63f4b4b3 --- /dev/null +++ b/include/kcl/kcl_drm_writeback.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * (C) COPYRIGHT 2016 ARM Limited. All rights reserved. + * Author: Brian Starkey + * + * This program is free software and is provided to you under the terms of the + * GNU General Public License version 2 as published by the Free Software + * Foundation, and any use by you of this program is subject to the terms + * of such GNU licence. + */ +#ifndef AMDKCL_DRM_WRITEBACK_H +#define AMDKCL_DRM_WRITEBACK_H + +#include + +#ifndef HAVE_DRM_WRITEBACK_CONNECTOR_INIT_7_ARGS +static inline int _kcl_drm_writeback_connector_init(struct drm_device *dev, + struct drm_writeback_connector *wb_connector, + const struct drm_connector_funcs *con_funcs, + const struct drm_encoder_helper_funcs *enc_helper_funcs, + const u32 *formats, int n_formats, + u32 possible_crtcs) +{ + wb_connector->encoder.possible_crtcs = possible_crtcs; + + return drm_writeback_connector_init(dev, wb_connector, con_funcs, enc_helper_funcs, formats, n_formats); +} +#define drm_writeback_connector_init _kcl_drm_writeback_connector_init +#endif + +#endif \ No newline at end of file From 0bb782da7c31b91353179fd4c59a22537ce95a6c Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 9 Oct 2023 14:29:36 +0800 Subject: [PATCH 1105/1868] drm/amdkcl: wrap code under macro HAVE_STRUCT_XARRAY It's caused by ed5694767b668f36d80b2c986af8703ed9c51a5f "drm/amdgpu: add cached GPU fault structure to vm struct" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 3 +++ drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 3 ++- drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 3 ++- drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 4 ++-- 6 files changed, 13 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index e27d0e8c9dca0..b0b928445ca52 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -3046,6 +3046,7 @@ void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m) * * Cache the fault info for later use by userspace in debugging. */ +#ifdef HAVE_STRUCT_XARRAY void amdgpu_vm_update_fault_cache(struct amdgpu_device *adev, unsigned int pasid, uint64_t addr, @@ -3092,6 +3093,7 @@ void amdgpu_vm_update_fault_cache(struct amdgpu_device *adev, } xa_unlock_irqrestore(&adev->vm_manager.pasids, flags); } +#endif /** * amdgpu_vm_is_bo_always_valid - check if the BO is VM always valid diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h index 082db0f3fbaf9..ec8eaae4d7c81 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h @@ -654,11 +654,14 @@ static inline void amdgpu_vm_eviction_unlock(struct amdgpu_vm *vm) mutex_unlock(&vm->eviction_lock); } +#ifdef HAVE_STRUCT_XARRAY void amdgpu_vm_update_fault_cache(struct amdgpu_device *adev, unsigned int pasid, uint64_t addr, uint32_t status, unsigned int vmhub); +#endif + void amdgpu_vm_tlb_fence_create(struct amdgpu_device *adev, struct amdgpu_vm *vm, struct dma_fence **fence); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c index f0ceab3ce5bfa..1475a9ca25596 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c @@ -149,9 +149,10 @@ static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev, status = RREG32(hub->vm_l2_pro_fault_status); WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); - +#ifdef HAVE_STRUCT_XARRAY amdgpu_vm_update_fault_cache(adev, entry->pasid, addr, status, entry->vmid_src ? AMDGPU_MMHUB0(0) : AMDGPU_GFXHUB(0)); +#endif } if (!printk_ratelimit()) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c index 2797fd84432b2..132c124ef1c95 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c @@ -120,9 +120,10 @@ static int gmc_v11_0_process_interrupt(struct amdgpu_device *adev, status = RREG32(hub->vm_l2_pro_fault_status); WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); - +#ifdef HAVE_STRUCT_XARRAY amdgpu_vm_update_fault_cache(adev, entry->pasid, addr, status, entry->vmid_src ? AMDGPU_MMHUB0(0) : AMDGPU_GFXHUB(0)); +#endif } if (printk_ratelimit()) { diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c index 994432fb57eaf..fd9156c2871fe 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c @@ -1266,10 +1266,10 @@ static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev, if (!addr && !status) return 0; - +#ifdef HAVE_STRUCT_XARRAY amdgpu_vm_update_fault_cache(adev, entry->pasid, ((u64)addr) << AMDGPU_GPU_PAGE_SHIFT, status, AMDGPU_GFXHUB(0)); - +#endif if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST) gmc_v7_0_set_fault_enable_default(adev, false); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index 380a6b5f8bdbb..f69b65063a498 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -1440,10 +1440,10 @@ static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev, if (!addr && !status) return 0; - +#ifdef HAVE_STRUCT_XARRAY amdgpu_vm_update_fault_cache(adev, entry->pasid, ((u64)addr) << AMDGPU_GPU_PAGE_SHIFT, status, AMDGPU_GFXHUB(0)); - +#endif if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST) gmc_v8_0_set_fault_enable_default(adev, false); From a15ad796e04e6fe654f908a34ebe9676234aef89 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 9 Oct 2023 14:32:52 +0800 Subject: [PATCH 1106/1868] drm/amdkcl: wrap code under macro HAVE_STRUCT_XARRAY It's caused by 2b332c97042ed499b7f04d2648736848c8f007a4 "drm/amdgpu: add new INFO ioctl query for the last GPU page fault" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index 8d4e0015c156a..4ec312b65a7d5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -1303,6 +1303,7 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) return copy_to_user(out, max_ibs, min((size_t)size, sizeof(max_ibs))) ? -EFAULT : 0; } +#ifdef HAVE_STRUCT_XARRAY case AMDGPU_INFO_GPUVM_FAULT: { struct amdgpu_fpriv *fpriv = filp->driver_priv; struct amdgpu_vm *vm = &fpriv->vm; @@ -1323,6 +1324,7 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) return copy_to_user(out, &gpuvm_fault, min((size_t)size, sizeof(gpuvm_fault))) ? -EFAULT : 0; } +#endif default: DRM_DEBUG_KMS("Invalid request %d\n", info->query); return -EINVAL; From f26d191f6b0156cc7d6c3f907594c2a67033d33c Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 9 Oct 2023 14:39:02 +0800 Subject: [PATCH 1107/1868] drm/amdkcl: wrap code under macro HAVE_PCI_DRIVER_DEV_GROUPS It's caused by 442a478469621f459834b27d5ac1c392bacd9c25 "drm/amdgpu: Add sysfs attribute to get board info" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 8e8ad52b4a0e9..dce68436d020e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -244,7 +244,7 @@ void amdgpu_reg_state_sysfs_fini(struct amdgpu_device *adev) * - "unknown" - Not known * */ - +#ifdef HAVE_PCI_DRIVER_DEV_GROUPS static ssize_t amdgpu_device_get_board_info(struct device *dev, struct device_attribute *attr, char *buf) @@ -296,6 +296,7 @@ static const struct attribute_group amdgpu_board_attrs_group = { .attrs = amdgpu_board_attrs, .is_visible = amdgpu_board_attrs_is_visible }; +#endif static void amdgpu_device_get_pcie_info(struct amdgpu_device *adev); @@ -4416,11 +4417,12 @@ int amdgpu_device_init(struct amdgpu_device *adev, r = sysfs_create_files(&adev->dev->kobj, amdgpu_dev_attributes); if (r) dev_err(adev->dev, "Could not create amdgpu device attr\n"); - +#ifdef HAVE_PCI_DRIVER_DEV_GROUPS r = devm_device_add_group(adev->dev, &amdgpu_board_attrs_group); if (r) dev_err(adev->dev, "Could not create amdgpu board attributes\n"); +#endif amdgpu_fru_sysfs_init(adev); amdgpu_reg_state_sysfs_init(adev); From 4447ad1171ea4920fe749bde52a7747bf5a8d06a Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 12 Oct 2023 11:01:39 +0800 Subject: [PATCH 1108/1868] drm/amdkcl: add return statements for KCL It's caused by 0da86105f4b82253e4521281aa377bd1a2c989b1 "drm/amdgpu: Drop unnecessary return statements" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/atombios_encoders.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c index 3ed9f74a2c49d..c19af05dab725 100644 --- a/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c +++ b/drivers/gpu/drm/amd/amdgpu/atombios_encoders.c @@ -232,6 +232,8 @@ void amdgpu_atombios_encoder_init_backlight(struct amdgpu_encoder *amdgpu_encode /* Try registering an ACPI video backlight device instead. */ #ifdef HAVE_ACPI_VIDEO_REGISTER_BACKLIGHT acpi_video_register_backlight(); +#else + return; #endif } From 44611d8b82a7f652a45364ec440c8d65d1048e81 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 24 Oct 2023 14:03:17 +0800 Subject: [PATCH 1109/1868] drm/amdkcl: update config.h Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/config/config.h | 24 +++--------------------- 1 file changed, 3 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 15b79f7fc344f..537d559cc3650 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -255,12 +255,6 @@ /* struct drm_device has pdev member */ /* #undef HAVE_DRM_DEVICE_PDEV */ -/* drm_dev_put() is available */ -#define HAVE_DRM_DEV_PUT 1 - -/* drm_dev_unplug() is available */ -#define HAVE_DRM_DEV_UNPLUG 1 - /* Define to 1 if you have the header file. */ #define HAVE_DRM_DISPLAY_DRM_DP_H 1 @@ -425,9 +419,6 @@ /* drm_dp_send_real_edid_checksum() is available */ #define HAVE_DRM_DP_SEND_REAL_EDID_CHECKSUM 1 -/* drm_dp_start_crc() is available */ -#define HAVE_DRM_DP_START_CRC 1 - /* drm_dp_update_payload_part1() function has start_slot argument */ /* #undef HAVE_DRM_DP_UPDATE_PAYLOAD_PART1_START_SLOT_ARG */ @@ -549,6 +540,9 @@ /* drm_gem_plane_helper_prepare_fb() is available */ #define HAVE_DRM_GEM_PLANE_HELPER_PREPARE_FB 1 +/* drm_gem_prime_handle_to_fd() is available */ +/* #undef HAVE_DRM_GEM_PRIME_HANDLE_TO_FD */ + /* drm_hdcp_update_content_protection is available */ #define HAVE_DRM_HDCP_UPDATE_CONTENT_PROTECTION 1 @@ -652,9 +646,6 @@ /* fs_reclaim_acquire() is available */ #define HAVE_FS_RECLAIM_ACQUIRE 1 -/* drm_driver->gem_free_object_unlocked() is available */ -/* #undef HAVE_GEM_FREE_OBJECT_UNLOCKED_IN_DRM_DRIVER */ - /* generic_handle_domain_irq() is available */ #define HAVE_GENERIC_HANDLE_DOMAIN_IRQ 1 @@ -961,12 +952,6 @@ /* seq_hex_dump() is available */ #define HAVE_SEQ_HEX_DUMP 1 -/* drm_driver->set_busid is available */ -/* #undef HAVE_SET_BUSID_IN_STRUCT_DRM_DRIVER */ - -/* whether si_mem_available() is available */ -#define HAVE_SI_MEM_AVAILABLE 1 - /* smca_get_bank_type(x) is available */ /* #undef HAVE_SMCA_GET_BANK_TYPE_WITH_ONE_ARGUMENT */ @@ -1012,9 +997,6 @@ /* drm_gem_open_object is defined in struct drm_drv */ /* #undef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK */ -/* drm_pending_vblank_event->sequence is available */ -#define HAVE_STRUCT_DRM_PENDING_VBLANK_EVENT_SEQUENCE 1 - /* drm_plane_helper_funcs->atomic_check() second param wants drm_atomic_state arg */ #define HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS 1 From 63030dd10100b4b3dc107e26206a432b2286003e Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 24 Oct 2023 16:42:09 +0800 Subject: [PATCH 1110/1868] drm/amdgpu: add missing null check for tbo.resource It's caused by 2e6dcc672567d7ffe913fac226ad1f4bd139e88e "drm/ttm: stop allocating dummy resources during BO creation" The latest ttm beable to handle the move without a resource, so some tbo.resource is null when bo release. Then add null pointer chec when adding AMDGPU_PL_DGMA support. Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index 1e7c5d4c709f0..c2d3215463e8d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -108,10 +108,10 @@ static void amdgpu_gem_object_free(struct drm_gem_object *gobj) } } - if (robj->tbo.resource->mem_type == AMDGPU_PL_DGMA) + if (robj->tbo.resource && robj->tbo.resource->mem_type == AMDGPU_PL_DGMA) atomic64_sub(amdgpu_bo_size(robj), &adev->direct_gma.vram_usage); - else if (robj->tbo.resource->mem_type == AMDGPU_PL_DGMA_IMPORT) + else if (robj->tbo.resource && robj->tbo.resource->mem_type == AMDGPU_PL_DGMA_IMPORT) atomic64_sub(amdgpu_bo_size(robj), &adev->direct_gma.gart_usage); From aa1f12a5aebf5cdb8593fcd5a07e486f5ad3fd71 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 27 Oct 2023 14:44:27 +0800 Subject: [PATCH 1111/1868] drm/amdkcl: align M4 format Update some M4 to align the format. Signed-off-by: Bob Zhou Reviewed-by: Ma Jun --- .../drm/amd/dkms/m4/drm-prime-pages-to-sg.m4 | 16 +++++++++------- .../drm/amd/dkms/m4/drm_simple_kms_helper.m4 | 16 +++++++++------- .../gpu/drm/amd/dkms/m4/mce_notifier_prios.m4 | 18 ++++++++++-------- 3 files changed, 28 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-prime-pages-to-sg.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-prime-pages-to-sg.m4 index 5854aa864fd2e..cae3e54d7c7f7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-prime-pages-to-sg.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-prime-pages-to-sg.m4 @@ -3,12 +3,14 @@ dnl # commit 707d561f77b5e2a6f90c9786bee44ee7a8dedc7e dnl # drm: allow limiting the scatter list size. dnl # AC_DEFUN([AC_AMDGPU_DRM_PRIME_PAGES_TO_SG], [ - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include - ], [ - drm_prime_pages_to_sg(NULL, NULL, 0); - ], [drm_prime_pages_to_sg], [drivers/gpu/drm/drm_prime.c], [ - AC_DEFINE(HAVE_DRM_PRIME_PAGES_TO_SG_3ARGS, 1, - [drm_prime_pages_to_sg() wants 3 arguments]) + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + drm_prime_pages_to_sg(NULL, NULL, 0); + ], [drm_prime_pages_to_sg], [drivers/gpu/drm/drm_prime.c], [ + AC_DEFINE(HAVE_DRM_PRIME_PAGES_TO_SG_3ARGS, 1, + [drm_prime_pages_to_sg() wants 3 arguments]) + ]) ]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_simple_kms_helper.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_simple_kms_helper.m4 index 7f8cf4e9ad0a1..837e690cc9c32 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_simple_kms_helper.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_simple_kms_helper.m4 @@ -3,12 +3,14 @@ dnl # v5.6-rc2-359-g63170ac6f2e8 dnl # drm/simple-kms: Add drm_simple_encoder_{init,create}() dnl # AC_DEFUN([AC_AMDGPU_DRM_SIMPLE_ENCODER_INIT], [ - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include - ],[ - drm_simple_encoder_init(NULL, NULL, 0); - ],[drm_simple_encoder_init], [drivers/gpu/drm/drm_simple_kms_helper.c],[ - AC_DEFINE(HAVE_DRM_SIMPLE_ENCODER_INIT, 1, - [drm_simple_encoder is available]) + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + drm_simple_encoder_init(NULL, NULL, 0); + ],[drm_simple_encoder_init], [drivers/gpu/drm/drm_simple_kms_helper.c],[ + AC_DEFINE(HAVE_DRM_SIMPLE_ENCODER_INIT, 1, + [drm_simple_encoder is available]) + ]) ]) ]) diff --git a/drivers/gpu/drm/amd/dkms/m4/mce_notifier_prios.m4 b/drivers/gpu/drm/amd/dkms/m4/mce_notifier_prios.m4 index ac2a78006ea2e..e3d33a862d7fb 100644 --- a/drivers/gpu/drm/amd/dkms/m4/mce_notifier_prios.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/mce_notifier_prios.m4 @@ -3,13 +3,15 @@ dnl # dnl # v5.5-rc2-5-g8438b84ab42d x86/mce: Take action on UCNA/Deferred errors again dnl # AC_DEFUN([AC_AMDGPU_MCE_PRIO_UC], [ - AC_KERNEL_TRY_COMPILE([ - #include - ], [ - enum mce_notifier_prios pri; - pri = MCE_PRIO_UC; - ], [ - AC_DEFINE(HAVE_MCE_PRIO_UC, 1, - [enum MCE_PRIO_UC is available]) + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + enum mce_notifier_prios pri; + pri = MCE_PRIO_UC; + ], [ + AC_DEFINE(HAVE_MCE_PRIO_UC, 1, + [enum MCE_PRIO_UC is available]) + ]) ]) ]) From b64ff14c13942f0d344489c0e69a66c0159c5468 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 27 Oct 2023 14:45:50 +0800 Subject: [PATCH 1112/1868] drm/amdkcl: update prepare_writeback_job to limit param The latest HAVE_DRM_CONNECTOR_HELPER_FUNCS_PREPARE_WRITEBACK_JOB hasn't been defined, so update M4 to fix the issue and limit params. Signed-off-by: Bob Zhou Reviewed-by: Ma Jun --- drivers/gpu/drm/amd/dkms/m4/drm_connector_helper_funcs.m4 | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_connector_helper_funcs.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_connector_helper_funcs.m4 index fe75c0300c099..11f356754b2c5 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_connector_helper_funcs.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_connector_helper_funcs.m4 @@ -7,8 +7,8 @@ AC_DEFUN([AC_AMDGPU_DRM_CONNECTOR_HELPER_FUNCS_PREPARE_WRITEBACK_JOB], [ AC_KERNEL_TRY_COMPILE([ #include ],[ - struct drm_connector_helper_funcs *funcs; - funcs->prepare_writeback_job = NULL; + struct drm_connector_helper_funcs *funcs = NULL; + funcs->prepare_writeback_job((struct drm_writeback_connector *)NULL, (struct drm_writeback_job *)NULL); ],[ AC_DEFINE(HAVE_DRM_CONNECTOR_HELPER_FUNCS_PREPARE_WRITEBACK_JOB, 1, [drm_connector_helper_funcs->prepare_writeback_job is available]) From 4b542b35f904e91663ee102e89e0fa64eecbe5b0 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Tue, 24 Oct 2023 12:47:03 -0400 Subject: [PATCH 1113/1868] Shorten path to DKMS module build directory Make the build robust against too long argument error Change-Id: Ifb3f146f55d645bb1809f79751902690f937b096 Signed-off-by: Slava Grigorev --- drivers/gpu/drm/amd/dkms/dkms.conf | 8 +++--- drivers/gpu/drm/amd/dkms/post-build.sh | 23 ++------------- drivers/gpu/drm/amd/dkms/pre-build.sh | 39 ++++---------------------- 3 files changed, 11 insertions(+), 59 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/dkms.conf b/drivers/gpu/drm/amd/dkms/dkms.conf index 78cc07704d491..6067de790980c 100644 --- a/drivers/gpu/drm/amd/dkms/dkms.conf +++ b/drivers/gpu/drm/amd/dkms/dkms.conf @@ -1,9 +1,9 @@ PACKAGE_NAME="amdgpu" PACKAGE_VERSION="1.0" AUTOINSTALL="yes" -PRE_BUILD="amd/dkms/pre-build.sh $kernelver" -POST_BUILD="amd/dkms/post-build.sh $kernelver" -POST_REMOVE="amd/dkms/post-build.sh $kernelver" +module_build_dir="$(mktemp -ut amd.XXXXXXXX)" +PRE_BUILD="amd/dkms/pre-build.sh $kernelver $dkms_tree $module $module_version $module_build_dir" +POST_BUILD="amd/dkms/post-build.sh $module_build_dir" # not all OS supports weak module updates NO_WEAK_MODULES="yes" @@ -41,4 +41,4 @@ DEST_MODULE_LOCATION[6]="/kernel/drivers/gpu/drm/amd/amdxcp" MAKE[0]="make TTM_NAME=${BUILT_MODULE_NAME[1]} \ SCHED_NAME=${BUILT_MODULE_NAME[3]} \ -C $kernel_source_dir \ - M=$dkms_tree/$module/$module_version/build" + M=$module_build_dir" diff --git a/drivers/gpu/drm/amd/dkms/post-build.sh b/drivers/gpu/drm/amd/dkms/post-build.sh index 59ccb1bf481e6..0c600db277937 100755 --- a/drivers/gpu/drm/amd/dkms/post-build.sh +++ b/drivers/gpu/drm/amd/dkms/post-build.sh @@ -1,23 +1,4 @@ #!/bin/bash -KERNELVER=$1 - -# -# Restore original kernel 5.x and Kernel 4.x scripts/Makefile.build modified by post-add.sh -# -if [ ${KERNELVER%%.*} -eq 5 -o ${KERNELVER%%.*} -eq 4 ]; then - moddir="/lib/modules/$KERNELVER" - mkfile="scripts/Makefile.build" - - if [[ -d "$moddir/source" ]]; then - mkfile="$moddir/source/$mkfile" - else - mkfile="$moddir/build/$mkfile" - fi - - mkfile=$(readlink -f $mkfile) - - if [[ -f "$mkfile~" ]]; then - mv -f $mkfile{~,} - fi -fi +MODULE_BUILD_DIR=$1 +rm -rf $MODULE_BUILD_DIR diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index 1eba510fa6eb1..ca64bd8c9fc66 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -5,6 +5,10 @@ INC="include" SRC="amd/dkms" KERNELVER=$1 +DKMS_TREE=$2 +MODULE=$3 +MODULE_VERSION=$4 +MODULE_BUILD_DIR=$5 KERNELVER_BASE=${KERNELVER%%-*} version_lt () { @@ -55,41 +59,8 @@ for config in $AMDGPU_CONFIG $TTM_CONFIG $SCHED_CONFIG; do sed -i "/${config}$/s/$/_AMDKCL/" amd/dkms/Makefile done -#!/bin/bash - -KERNELVER=$1 - -# -# Kernel 5.x and Kernel 4.x scripts/Makefile.build patch -# The patch makes rules robust against "Argument list too long" error -# -if [ ${KERNELVER%%.*} -eq 5 -o ${KERNELVER%%.*} -eq 4 ]; then - moddir="/lib/modules/$KERNELVER" - mkfile="scripts/Makefile.build" - - if [[ -d "$moddir/source" ]]; then - mkfile="$moddir/source/$mkfile" - else - mkfile="$moddir/build/$mkfile" - fi - - mkfile=$(readlink -e $mkfile) - - if [[ "$?" -eq 0 ]] && [[ ! -f "$mkfile~" ]]; then - cp -a ${mkfile}{,~} - sed -i -e "/^cmd_mod = {/,/} > \$@$/c"` - `"cmd_mod = printf '%s\x5Cn' \$(call real-search, \$*.o, .o, -objs -y -m) | \\\\\n"` - `"\t\$(AWK) '!x[\$\$0]++ { print(\"\$(obj)\/\"\$\$0) }' > \$@" \ - -e "s/^[[:space:]]*cmd_link_multi-m = \$(LD).*$/"` - `"cmd_link_multi-m = \\\\\n"` - `"\t\$(file >\$@.in,\$(filter %.o,$^)) \\\\\n"` - `"\t\$(LD) \$(ld_flags) -r -o \$@ @\$@.in; \\\\\n"` - `"\trm -f \$@.in/" \ - $mkfile - fi -fi - export KERNELVER +ln -s $DKMS_TREE/$MODULE/$MODULE_VERSION/build $MODULE_BUILD_DIR (cd $SRC && ./configure) # rename CFLAGS_target.o / CFLAGS_REMOVE_ to CFLAGS_target.o From c866fb8be0ef346c46798f5f619e4b6f77661cc0 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 25 Oct 2023 17:51:12 +0800 Subject: [PATCH 1114/1868] drm/amd/display: update function name for amdgpu_dm_plane.c It's caused by 2a2133cf7d3344b986c2a9aab4bd4b46e914be3f "drm/amd/display: Add prefix for plane functions" Signed-off-by: Bob Zhou Reviewed-by: Ma Jun --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 82a3dd396037a..6e9721994a018 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -348,13 +348,13 @@ fill_gfx9_plane_attributes_from_flags(struct amdgpu_device *adev, { int ret; - fill_gfx9_tiling_info_from_device(adev, tiling_info); + amdgpu_dm_plane_fill_gfx9_tiling_info_from_device(adev, tiling_info); tiling_info->gfx9.swizzle = AMDGPU_TILING_GET(tiling_flags, SWIZZLE_MODE); fill_dcc_params_from_flags(afb, dcc, address, tiling_flags, force_disable_dcc); - ret = validate_dcc(adev, format, rotation, tiling_info, dcc, address, plane_size); + ret = amdgpu_dm_plane_validate_dcc(adev, format, rotation, tiling_info, dcc, address, plane_size); if (ret) return ret; From 815aade36c2ea6de9525b8f873494e4ef7feaf72 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Mon, 30 Oct 2023 22:20:57 -0400 Subject: [PATCH 1115/1868] Fix dkms driver build on Oracle Linux 8.x Change-Id: I953c377749fb2d7cec6dbb4b1bbf8211454cc19d Signed-off-by: Slava Grigorev --- drivers/gpu/drm/amd/dkms/Makefile | 1 + drivers/gpu/drm/amd/dkms/dkms.conf | 2 +- drivers/gpu/drm/amd/dkms/pre-build.sh | 12 ++++++++++++ 3 files changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index a73a7f7227df2..0e41d5633a6f9 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -179,6 +179,7 @@ subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_CIK subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_SI subdir-ccflags-y += -DCONFIG_DRM_AMDGPU_USERPTR subdir-ccflags-y += -DCONFIG_DRM_AMD_DC +subdir-ccflags-y += -Wno-error ifeq ($(call _is_kcl_macro_defined,HAVE_AMDKCL_HMM_MIRROR_ENABLED),y) ifdef CONFIG_DEVICE_PRIVATE diff --git a/drivers/gpu/drm/amd/dkms/dkms.conf b/drivers/gpu/drm/amd/dkms/dkms.conf index 6067de790980c..1006d000952ed 100644 --- a/drivers/gpu/drm/amd/dkms/dkms.conf +++ b/drivers/gpu/drm/amd/dkms/dkms.conf @@ -38,7 +38,7 @@ BUILT_MODULE_NAME[6]="amdxcp" BUILT_MODULE_LOCATION[6]="amd/amdxcp" DEST_MODULE_LOCATION[6]="/kernel/drivers/gpu/drm/amd/amdxcp" -MAKE[0]="make TTM_NAME=${BUILT_MODULE_NAME[1]} \ +MAKE[0]=". $module_build_dir/.env && make TTM_NAME=${BUILT_MODULE_NAME[1]} \ SCHED_NAME=${BUILT_MODULE_NAME[3]} \ -C $kernel_source_dir \ M=$module_build_dir" diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index ca64bd8c9fc66..796020ae1570f 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -61,6 +61,18 @@ done export KERNELVER ln -s $DKMS_TREE/$MODULE/$MODULE_VERSION/build $MODULE_BUILD_DIR + +# Enable gcc-toolset for kernels that are built with non-default compiler +if [[ -d /opt/rh ]]; then + for f in $(find /opt/rh -type f -a -name gcc); do + if strings /boot/vmlinuz-$KERNELVER | grep -q "$($f --version | head -1)"; then + . ${f%/*}/../../../enable + break + fi + done +fi +echo "PATH=$PATH" >$MODULE_BUILD_DIR/.env + (cd $SRC && ./configure) # rename CFLAGS_target.o / CFLAGS_REMOVE_ to CFLAGS_target.o From 9df7b61c8d34a2b049a915579319dd58af9db878 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 2 Nov 2023 11:18:00 +0800 Subject: [PATCH 1116/1868] drm/amdkcl: fake dev_is_removable() repalce pci_is_thunderbolt_attached() It's caused by 99abe09a40d2c87d849a2cb1930c2792fc5e3396 "drm/amdgpu: don't use pci_is_thunderbolt_attached()" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/config/config.h | 7 ++----- drivers/gpu/drm/amd/dkms/m4/dev_is_removable.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_device.h | 8 ++++++++ 4 files changed, 28 insertions(+), 5 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/dev_is_removable.m4 diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 537d559cc3650..32a92704bd98d 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -94,11 +94,8 @@ /* MEMORY_DEVICE_COHERENT is availablea */ #define HAVE_DEVICE_COHERENT 1 -/* devm_memremap_pages() wants struct dev_pagemap */ -#define HAVE_DEVM_MEMREMAP_PAGES_DEV_PAGEMAP 1 - -/* devm_memremap_pages() wants p,p,p,p interface */ -/* #undef HAVE_DEVM_MEMREMAP_PAGES_P_P_P_P */ +/* dev_is_removable() is available */ +#define HAVE_DEV_IS_REMOVABLE 1 /* dev_pagemap->owner is available */ #define HAVE_DEV_PAGEMAP_OWNER 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/dev_is_removable.m4 b/drivers/gpu/drm/amd/dkms/m4/dev_is_removable.m4 new file mode 100644 index 0000000000000..14ddb4989bbac --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dev_is_removable.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v5.13-rc2-70-g70f400d4d957 +dnl # driver core: Move the "removable" attribute from USB to core +dnl # +AC_DEFUN([AC_AMDGPU_DEV_IS_REMOVABLE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + bool res = 0; + res = dev_is_removable(NULL); + ], [ + AC_DEFINE(HAVE_DEV_IS_REMOVABLE, 1, + [dev_is_removable() is available]) + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 44aec9ad47137..a0cac602f4207 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -149,6 +149,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DEVICE_PDEV AC_AMDGPU_DRM_CONNECTOR_SET_PANEL_ORIENTATION_WITH_QUIRK AC_AMDGPU_DRM_SIMPLE_ENCODER_INIT + AC_AMDGPU_DEV_IS_REMOVABLE AC_AMDGPU_DRM_DP_UPDATE_PAYLOAD_PART1_START_SLOT_ARG AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS AC_AMDGPU_DRM_DISPLAY_INFO_IS_HDMI diff --git a/include/kcl/kcl_device.h b/include/kcl/kcl_device.h index a4d0dfbb334bc..a6480630d0ab2 100644 --- a/include/kcl/kcl_device.h +++ b/include/kcl/kcl_device.h @@ -60,4 +60,12 @@ static inline void dev_pm_set_driver_flags(struct device *dev, u32 flags) } #endif +#ifndef HAVE_DEV_IS_REMOVABLE +static inline bool _kcl_dev_is_removable(struct device *dev) +{ + return false; +} +#define dev_is_removable _kcl_dev_is_removable +#endif + #endif /* AMDKCL_DEVICE_H */ From f502d12fb3c244b2e14d00206bd9dd83c45f05cf Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 3 Nov 2023 15:38:40 +0800 Subject: [PATCH 1117/1868] drm/amdkcl: wrap code under amdkcl_ttm_resvp() It's caused by 0c0e51e78d7697be597eefb1e2dcbec3c3bf801d "drm/amdgpu: Attach eviction fence on alloc" Signed-off-by: Bob Zhou Reviewed-by: Ma Jun --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 7578e1823bf87..03f45c099f22c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -447,11 +447,11 @@ int amdgpu_amdkfd_bo_validate_and_fence(struct amdgpu_bo *bo, if (ret) goto unreserve_out; - ret = dma_resv_reserve_fences(bo->tbo.base.resv, 1); + ret = dma_resv_reserve_fences(amdkcl_ttm_resvp(&bo->tbo), 1); if (ret) goto unreserve_out; - dma_resv_add_fence(bo->tbo.base.resv, fence, + dma_resv_add_fence(amdkcl_ttm_resvp(&bo->tbo), fence, DMA_RESV_USAGE_BOOKKEEP); unreserve_out: From b379f6c09eb4e9809bd66522d9e3d3137c793cfa Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Fri, 3 Nov 2023 19:43:26 -0400 Subject: [PATCH 1118/1868] Fix dkms parrallel build 'dkms' has a bug and can't substitute 'make' command if it is not the first word in the command line. So, we restore -j option that used to be in dkms.conf before it was integrated into dkms. Change-Id: I39653f4bace4832bb110e3debcee89c51b106bf0 Signed-off-by: Slava Grigorev --- drivers/gpu/drm/amd/dkms/dkms.conf | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/dkms.conf b/drivers/gpu/drm/amd/dkms/dkms.conf index 1006d000952ed..ceef7d15a7c26 100644 --- a/drivers/gpu/drm/amd/dkms/dkms.conf +++ b/drivers/gpu/drm/amd/dkms/dkms.conf @@ -38,7 +38,17 @@ BUILT_MODULE_NAME[6]="amdxcp" BUILT_MODULE_LOCATION[6]="amd/amdxcp" DEST_MODULE_LOCATION[6]="/kernel/drivers/gpu/drm/amd/amdxcp" -MAKE[0]=". $module_build_dir/.env && make TTM_NAME=${BUILT_MODULE_NAME[1]} \ +num_cpu_cores() +{ + if [ -x /usr/bin/nproc ]; then + nproc + else + echo "1" + fi +} + +MAKE[0]=". $module_build_dir/.env && make -j$(num_cpu_cores) KERNELRELEASE=$kernelver \ + TTM_NAME=${BUILT_MODULE_NAME[1]} \ SCHED_NAME=${BUILT_MODULE_NAME[3]} \ -C $kernel_source_dir \ M=$module_build_dir" From d05b725abf37fb01aeee93c4a34bc9617e23bb91 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Fri, 10 Nov 2023 16:34:53 -0500 Subject: [PATCH 1119/1868] drm/amdkcl: fix DRM_DP_READ_DPCD_CAPS test Add another location to search for drm_dp_read_dpcd_caps exported symbol to cover older kernels. Change-Id: I216e6ffcb1f66947974acd0d4ef1b9477826852c Signed-off-by: Slava Grigorev --- drivers/gpu/drm/amd/dkms/m4/drm_dp_read_dpcd_caps.m4 | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_dp_read_dpcd_caps.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_dp_read_dpcd_caps.m4 index dbd64ba5dbbe8..8306568c2e0ca 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_dp_read_dpcd_caps.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_dp_read_dpcd_caps.m4 @@ -8,9 +8,9 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_READ_DPCD_CAPS], [ #include ], [ drm_dp_read_dpcd_caps(NULL, NULL); - ], [drm_dp_read_dpcd_caps], [drivers/gpu/drm/display/drm_dp_helper.c], [ + ], [drm_dp_read_dpcd_caps], [drivers/gpu/drm/display/drm_dp_helper.c drivers/gpu/drm/drm_dp_helper.c], [ AC_DEFINE(HAVE_DRM_DP_READ_DPCD_CAPS, 1, [drm_dp_read_dpcd_caps() is available]) ]) ]) -]) \ No newline at end of file +]) From 61bc8fc7474265a2b737a971df2402f037be027f Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 14 Nov 2023 19:06:19 +0800 Subject: [PATCH 1120/1868] Revert "drm/amdgpu: fix AGP init order" The reverted patch cause a page fault error on navi32 when modprobe. Temporarily revert it. This reverts commit 00ee8d37fae64ce4e6d01bf83707e7e39d6a6398. Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 3 +++ drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 1 - drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 1 - drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 1 - drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 1 - drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 1 - drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 -- 7 files changed, 3 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index 5dcbd13ee7557..6a84cd130d677 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -1103,6 +1103,9 @@ static const char * const amdgpu_vram_names[] = { */ int amdgpu_bo_init(struct amdgpu_device *adev) { + /* set the default AGP aperture state */ + amdgpu_gmc_set_agp_default(adev, &adev->gmc); + /* On A+A platform, VRAM can be mapped as WB */ if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu) { /* reserve PAT memory space to WC for VRAM */ diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c index 1475a9ca25596..c336ae015694b 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c @@ -677,7 +677,6 @@ static void gmc_v10_0_vram_gtt_location(struct amdgpu_device *adev, /* add the xgmi offset of the physical node */ base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; - amdgpu_gmc_set_agp_default(adev, mc); amdgpu_gmc_vram_location(adev, &adev->gmc, base); amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_BEST_FIT); if (!amdgpu_sriov_vf(adev) && (amdgpu_agp == 1)) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c index 132c124ef1c95..3d697c79db7ca 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c @@ -646,7 +646,6 @@ static void gmc_v11_0_vram_gtt_location(struct amdgpu_device *adev, base = adev->mmhub.funcs->get_fb_location(adev); - amdgpu_gmc_set_agp_default(adev, mc); amdgpu_gmc_vram_location(adev, &adev->gmc, base); amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_HIGH); if (!amdgpu_sriov_vf(adev) && diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c index d36725666b54c..edd3b826c277b 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c @@ -205,7 +205,6 @@ static void gmc_v6_0_vram_gtt_location(struct amdgpu_device *adev, base <<= 24; - amdgpu_gmc_set_agp_default(adev, mc); amdgpu_gmc_vram_location(adev, mc, base); amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_BEST_FIT); } diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c index fd9156c2871fe..3a21d4a3c3069 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c @@ -236,7 +236,6 @@ static void gmc_v7_0_vram_gtt_location(struct amdgpu_device *adev, base <<= 24; - amdgpu_gmc_set_agp_default(adev, mc); amdgpu_gmc_vram_location(adev, mc, base); amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_BEST_FIT); } diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index f69b65063a498..dbb59e63c5720 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -411,7 +411,6 @@ static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev, base = RREG32(mmMC_VM_FB_LOCATION) & 0xFFFF; base <<= 24; - amdgpu_gmc_set_agp_default(adev, mc); amdgpu_gmc_vram_location(adev, mc, base); amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_BEST_FIT); } diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index 4db0efcd0926a..4c5a076b37a1b 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -1642,8 +1642,6 @@ static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev, { u64 base = adev->mmhub.funcs->get_fb_location(adev); - amdgpu_gmc_set_agp_default(adev, mc); - /* add the xgmi offset of the physical node */ base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; if (adev->gmc.xgmi.connected_to_cpu) { From fe0ed1618afc1fae62c85d1a285741ff2b5f9983 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 14 Nov 2023 13:36:34 +0800 Subject: [PATCH 1121/1868] drm/amdkcl: wrap code under macro DEFINE_DEBUGFS_ATTRIBUTE It's caused by f8340195642eae0367646d59fbc046a380ccce9e "drm/amd/display: add a debugfs interface for the DMUB trace mask" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index de241d886a483..d07f25f611b47 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -3125,6 +3125,7 @@ static int allow_edp_hotplug_detection_set(void *data, u64 val) return 0; } +#if defined(DEFINE_DEBUGFS_ATTRIBUTE) /* check if kernel disallow eDP enter psr state * cat /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_psr * 0: allow edp enter psr; 1: disallow @@ -3250,7 +3251,7 @@ static int dmub_trace_mask_show(void *data, u64 *val) DEFINE_DEBUGFS_ATTRIBUTE(dmub_trace_mask_fops, dmub_trace_mask_show, dmub_trace_mask_set, "0x%llx\n"); - +#endif /* * Set dmcub trace event IRQ enable or disable. * Usage to enable dmcub trace event IRQ: echo 1 > /sys/kernel/debug/dri/0/amdgpu_dm_dmcub_trace_event_en From c3a378e75f903a57e3360295acd09722499c70d7 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Thu, 9 Nov 2023 13:08:13 +0530 Subject: [PATCH 1122/1868] drm/amdgpu: Skip execution of pending reset jobs cancel_work is not backported to all custom kernels. Add a workaround to skip execution of already queued recovery jobs, if the device is already reset. Signed-off-by: Lijo Lazar Reviewed-by: Asad Kamal --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 +++++ drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c | 9 +++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h | 16 ++++++++++++++++ 3 files changed, 30 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index dce68436d020e..b4001e6272ba2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -5666,6 +5666,8 @@ static inline void amdgpu_device_stop_pending_resets(struct amdgpu_device *adev) { struct amdgpu_ras *con = amdgpu_ras_get_context(adev); + amdgpu_reset_domain_clear_pending(adev->reset_domain); + #if defined(CONFIG_DEBUG_FS) if (!amdgpu_sriov_vf(adev)) cancel_work(&adev->reset_work); @@ -5724,6 +5726,9 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, bool audio_suspended = false; int retry_limit = AMDGPU_MAX_RETRY_LIMIT; + if (amdgpu_reset_domain_in_drain_mode(adev->reset_domain)) + return 0; + /* * Special case: RAS triggered and full reset isn't supported */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c index 66c1a868c0e16..91531e3563827 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c @@ -119,6 +119,14 @@ void amdgpu_reset_destroy_reset_domain(struct kref *ref) kvfree(reset_domain); } +static void amdgpu_reset_domain_cancel_all_work(struct work_struct *work) +{ + struct amdgpu_reset_domain *reset_domain = + container_of(work, struct amdgpu_reset_domain, clear); + + reset_domain->drain = false; +} + struct amdgpu_reset_domain *amdgpu_reset_create_reset_domain(enum amdgpu_reset_domain_type type, char *wq_name) { @@ -141,6 +149,7 @@ struct amdgpu_reset_domain *amdgpu_reset_create_reset_domain(enum amdgpu_reset_d } + INIT_WORK(&reset_domain->clear, amdgpu_reset_domain_cancel_all_work); atomic_set(&reset_domain->in_gpu_reset, 0); atomic_set(&reset_domain->reset_res, 0); init_rwsem(&reset_domain->sem); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h index 4ae581f3fcb54..7882e6dc24432 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h @@ -98,6 +98,8 @@ struct amdgpu_reset_domain { struct rw_semaphore sem; atomic_t in_gpu_reset; atomic_t reset_res; + struct work_struct clear; + bool drain; }; int amdgpu_reset_init(struct amdgpu_device *adev); @@ -136,6 +138,20 @@ static inline bool amdgpu_reset_domain_schedule(struct amdgpu_reset_domain *doma return queue_work(domain->wq, work); } +static inline void amdgpu_reset_domain_clear_pending(struct amdgpu_reset_domain *domain) +{ + domain->drain = true; + /* queue one more work to the domain queue. Till this work is finished, + * domain is in drain mode. + */ + queue_work(domain->wq, &domain->clear); +} + +static inline bool amdgpu_reset_domain_in_drain_mode(struct amdgpu_reset_domain *domain) +{ + return domain->drain; +} + void amdgpu_device_lock_reset_domain(struct amdgpu_reset_domain *reset_domain); void amdgpu_device_unlock_reset_domain(struct amdgpu_reset_domain *reset_domain); From b89b95fc6292a047d667a111fca1f9adddf3219e Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 23 Nov 2023 12:18:21 +0800 Subject: [PATCH 1123/1868] drm/amdkcl: wrap code under macro HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS It's caused by 1b6d631dea0b57f564722f78c144ee621691d5be "drm/amd/display: adjust flow for deallocation mst payload" Signed-off-by: Bob Zhou Reviewed-by: Asher Song Reviewed-by: Ma Jun Reviewed-by: Slava Abramov --- .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index be20e9b61c304..0c480199d3bf7 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -536,9 +536,7 @@ void dm_helpers_dp_mst_send_payload_allocation( struct drm_dp_mst_topology_mgr *mst_mgr; enum mst_progress_status set_flag = MST_ALLOCATE_NEW_PAYLOAD; enum mst_progress_status clr_flag = MST_CLEAR_ALLOCATED_PAYLOAD; -#if defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS) int ret = 0; -#endif aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; @@ -577,9 +575,13 @@ void dm_helpers_dp_mst_update_mst_mgr_for_deallocation( const struct dc_stream_state *stream) { struct amdgpu_dm_connector *aconnector; - struct drm_dp_mst_topology_state *mst_state; struct drm_dp_mst_topology_mgr *mst_mgr; +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS + struct drm_dp_mst_topology_state *mst_state; struct drm_dp_mst_atomic_payload *new_payload, old_payload; +#else + struct drm_dp_mst_port *mst_port; +#endif enum mst_progress_status set_flag = MST_CLEAR_ALLOCATED_PAYLOAD; enum mst_progress_status clr_flag = MST_ALLOCATE_NEW_PAYLOAD; @@ -589,15 +591,26 @@ void dm_helpers_dp_mst_update_mst_mgr_for_deallocation( return; mst_mgr = &aconnector->mst_root->mst_mgr; +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS mst_state = to_drm_dp_mst_topology_state(mst_mgr->base.state); new_payload = drm_atomic_get_mst_payload_state(mst_state, aconnector->mst_output_port); +#ifdef HAVE_DRM_DP_REMOVE_RAYLOAD_PART dm_helpers_construct_old_payload(mst_mgr, mst_state, new_payload, &old_payload); drm_dp_remove_payload_part2(mst_mgr, mst_state, &old_payload, new_payload); +#endif +#else + mst_port = aconnector->mst_output_port; + if (!mst_mgr->mst_state) + return; +#endif amdgpu_dm_set_mst_status(&aconnector->mst_status, set_flag, true); amdgpu_dm_set_mst_status(&aconnector->mst_status, clr_flag, false); +#ifndef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS + drm_dp_mst_deallocate_vcpi(mst_mgr, mst_port); +#endif } void dm_dtn_log_begin(struct dc_context *ctx, From 2692420b0ef3c00c8ded558af9b1630dda8828e1 Mon Sep 17 00:00:00 2001 From: Slava Grigorev Date: Fri, 24 Nov 2023 16:17:56 -0500 Subject: [PATCH 1124/1868] drm/amdkcl: compare only gcc version Compare only CONFIG_GCC_VERSION kernel build option with gcc version. "gcc --version" line embedded into the kernel binary could be different. For example the kernel 5.15 in Oracle 8 contains this version string: gcc (GCC) 11.2.1 20220127 (Red Hat 11.2.1-9.1.0.6) but gcc-toolset-11 prints gcc (GCC) 11.2.1 20220127 (Red Hat 11.2.1-9.2.0.1) Regardless the gcc versions are identical the compiler vendor portion is different. To avoid mismatching we compare only actual gcc version. SWDEV-427914 Change-Id: I7903db72f01b3880d9ce8514c6a841f573c241cd Signed-off-by: Slava Grigorev --- drivers/gpu/drm/amd/dkms/pre-build.sh | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index 796020ae1570f..5f922ec16986c 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -65,7 +65,11 @@ ln -s $DKMS_TREE/$MODULE/$MODULE_VERSION/build $MODULE_BUILD_DIR # Enable gcc-toolset for kernels that are built with non-default compiler if [[ -d /opt/rh ]]; then for f in $(find /opt/rh -type f -a -name gcc); do - if strings /boot/vmlinuz-$KERNELVER | grep -q "$($f --version | head -1)"; then + [[ -f /boot/config-$KERNELVER ]] || continue + config_gcc_version=$(. /boot/config-$KERNELVER && echo $CONFIG_GCC_VERSION) + IFS='.' read -ra ver <<<$($f -dumpfullversion) + gcc_version=$(printf "%d%02d%02d\n" ${ver[@]}) + if [[ "$config_gcc_version" = "$gcc_version" ]]; then . ${f%/*}/../../../enable break fi From 7130cfadac70861f2a303103544fe74b66802ecd Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 30 Nov 2023 18:09:19 +0800 Subject: [PATCH 1125/1868] drm/amdkcl: fake dma_fence_timestamp Signed-off-by: Asher Song --- .../drm/amd/dkms/m4/dma-fence-timestamp.m4 | 17 +++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_dma_fence.h | 21 +++++++++++++++++++ 3 files changed, 39 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/dma-fence-timestamp.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-fence-timestamp.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-fence-timestamp.m4 new file mode 100644 index 0000000000000..8054979dd1b6a --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dma-fence-timestamp.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # commit v6.6-rc1-33-gb83ce9cb4a46 +dnl # dma-buf: add dma_fence_timestamp helper +dnl # +AC_DEFUN([AC_AMDGPU_DMA_FENCE_TIMESTAMP], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + ktime_t time; + time = dma_fence_timestamp(NULL); + ], [ + AC_DEFINE(HAVE_DMA_FENCE_TIMESTAMP, 1, [dma_fence_TIMESTAMP() is available]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index a0cac602f4207..11e0894a4c3d6 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -221,6 +221,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_KVREALLOC AC_AMDGPU_DRM_DRIVER_GEM_PRIME_MMAP AC_AMDGPU_DRM_GEM_PRIME_HANDLE_TO_FD + AC_AMDGPU_DMA_FENCE_TIMESTAMP AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_dma_fence.h b/include/kcl/kcl_dma_fence.h index 20a014352f967..ae63b65466e00 100644 --- a/include/kcl/kcl_dma_fence.h +++ b/include/kcl/kcl_dma_fence.h @@ -45,4 +45,25 @@ static inline bool dma_fence_is_container(struct dma_fence *fence) #endif /* HAVE_DMA_FENCE_IS_CONTAINER */ +#ifndef HAVE_DMA_FENCE_TIMESTAMP +/** + * dma_fence_timestamp - helper to get the completion timestamp of a fence + * @fence: fence to get the timestamp from. + * + * After a fence is signaled the timestamp is updated with the signaling time, + * but setting the timestamp can race with tasks waiting for the signaling. This + * helper busy waits for the correct timestamp to appear. + */ +static inline ktime_t dma_fence_timestamp(struct dma_fence *fence) +{ + if (WARN_ON(!test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags))) + return ktime_get(); + + while (!test_bit(DMA_FENCE_FLAG_TIMESTAMP_BIT, &fence->flags)) + cpu_relax(); + + return fence->timestamp; +} +#endif + #endif From f817177146815398487edd2aaee5c4805be7b0ee Mon Sep 17 00:00:00 2001 From: Asher Song Date: Sun, 3 Dec 2023 17:21:54 +0800 Subject: [PATCH 1126/1868] drm/amdkcl: test macro __counted_by whether is defined It's caused by v6.5-rc2-17-gc8248faf3ca2 Compiler Attributes: counted_by: Adjust name and identifier expansion Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h | 6 +++++- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 4 ++++ drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h | 6 +++++- 3 files changed, 14 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h index 2458bbed8cc5b..47734741388fa 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.h @@ -61,8 +61,12 @@ struct amdgpu_bo_list { /* Protect access during command submission. */ struct mutex bo_list_mutex; - +#ifdef __counted_by struct amdgpu_bo_list_entry entries[] __counted_by(num_entries); +#else + struct amdgpu_bo_list_entry entries[]; +#endif + }; int amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index 12d1e971e236c..774f54789c215 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -748,7 +748,11 @@ struct ip_hw_instance { u8 harvest; int num_base_addresses; +#ifdef __counted_by u32 base_addr[] __counted_by(num_base_addresses); +#else + u32 base_addr[]; +#endif }; struct ip_hw_id { diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h index 42adc2a3dcbc1..ec6cec793c25c 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu10_hwmgr.h @@ -192,7 +192,11 @@ struct smu10_clock_voltage_dependency_record { struct smu10_voltage_dependency_table { uint32_t count; - struct smu10_clock_voltage_dependency_record entries[] __counted_by(count); + struct smu10_clock_voltage_dependency_record entries[] +#ifdef __counted_by + __counted_by(count) +#endif + ; }; struct smu10_clock_voltage_information { From 81e362a87f82948d7d65ff40ae88a05f1908f4fa Mon Sep 17 00:00:00 2001 From: Asher Song Date: Sun, 3 Dec 2023 20:03:38 +0800 Subject: [PATCH 1127/1868] drm/amdkcl:test whether shrinker_register exists It's caused by v6.6-rc4-53-gc42d50aefd17 mm: shrinker: add infrastructure for dynamically allocating shrinker Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 +- .../gpu/drm/amd/dkms/m4/register_shrinker.m4 | 22 ++++++++++++ drivers/gpu/drm/ttm/ttm_pool.c | 36 ++++++++++++++++--- include/kcl/kcl_shrinker.h | 2 ++ 4 files changed, 57 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 11e0894a4c3d6..d73ccf3818682 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -195,7 +195,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DSC_COMPUTE_RC_PARAMETERS AC_AMDGPU_DRM_GEM_PLANE_HELPER_PREPARE_FB AC_AMDGPU_BITMAP_TO_ARR32 - AC_AMDGPU_REGISTER_SHRINKER + AC_AMDGPU_SHRINKER AC_AMDGPU_DRM_DP_MST_POST_PASSTHROUGH_AUX AC_AMDGPU_DRM_DP_MST_PORT_FULL_PBN AC_AMDGPU_ACPI_VIDEO_FUNCS diff --git a/drivers/gpu/drm/amd/dkms/m4/register_shrinker.m4 b/drivers/gpu/drm/amd/dkms/m4/register_shrinker.m4 index 903f100bf18bd..98c49b53ddc6f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/register_shrinker.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/register_shrinker.m4 @@ -17,3 +17,25 @@ AC_DEFUN([AC_AMDGPU_REGISTER_SHRINKER], [ ]) ]) ]) + +dnl # +dnl # commit: v6.6-rc4-53-gc42d50aefd17 +dnl # mm: shrinker: add infrastructure for dynamically allocating shrinker +dnl # +AC_DEFUN([AC_AMDGPU_SHRINKER_REGISTER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + shrinker_register(NULL); + ], [shrinker_register], [mm/shrinker.c], [ + AC_DEFINE(HAVE_SHRINKER_REGISTER, 1, + [shrinker_register() is available]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_SHRINKER], [ + AC_AMDGPU_REGISTER_SHRINKER + AC_AMDGPU_SHRINKER_REGISTER +]) diff --git a/drivers/gpu/drm/ttm/ttm_pool.c b/drivers/gpu/drm/ttm/ttm_pool.c index 49ca26b933b60..7af5ad8e1b7af 100644 --- a/drivers/gpu/drm/ttm/ttm_pool.c +++ b/drivers/gpu/drm/ttm/ttm_pool.c @@ -73,7 +73,12 @@ static struct ttm_pool_type global_dma32_uncached[NR_PAGE_ORDERS]; static spinlock_t shrinker_lock; static struct list_head shrinker_list; -static struct shrinker *mm_shrinker; +static struct shrinker +#ifdef HAVE_SHRINKER_REGISTER +*mm_shrinker; +#else +mm_shrinker; +#endif static DECLARE_RWSEM(pool_shrink_rwsem); /* Allocate pages of size 1 << order with the given gfp_flags */ @@ -767,8 +772,20 @@ static int ttm_pool_debugfs_shrink_show(struct seq_file *m, void *data) struct shrink_control sc = { .gfp_mask = GFP_NOFS }; fs_reclaim_acquire(GFP_KERNEL); - seq_printf(m, "%lu/%lu\n", ttm_pool_shrinker_count(mm_shrinker, &sc), - ttm_pool_shrinker_scan(mm_shrinker, &sc)); + seq_printf(m, "%lu/%lu\n", ttm_pool_shrinker_count( +#ifdef HAVE_SHRINKER_REGISTER + mm_shrinker, +#else + &mm_shrinker, +#endif + &sc), + ttm_pool_shrinker_scan( +#ifdef HAVE_SHRINKER_REGISTER + mm_shrinker +#else + &mm_shrinker +#endif + , &sc)); fs_reclaim_release(GFP_KERNEL); return 0; @@ -812,6 +829,7 @@ int ttm_pool_mgr_init(unsigned long num_pages) &ttm_pool_debugfs_shrink_fops); #endif +#ifdef HAVE_SHRINKER_REGISTER mm_shrinker = shrinker_alloc(0, "drm-ttm_pool"); if (!mm_shrinker) return -ENOMEM; @@ -821,8 +839,14 @@ int ttm_pool_mgr_init(unsigned long num_pages) mm_shrinker->seeks = 1; shrinker_register(mm_shrinker); - return 0; +#else + mm_shrinker.count_objects = ttm_pool_shrinker_count; + mm_shrinker.scan_objects = ttm_pool_shrinker_scan; + mm_shrinker.seeks = 1; + + return kcl_register_shrinker(&mm_shrinker, "drm-ttm_pool"); +#endif } /** @@ -842,6 +866,10 @@ void ttm_pool_mgr_fini(void) ttm_pool_type_fini(&global_dma32_uncached[i]); } +#ifdef HAVE_SHRINKER_REGISTER shrinker_free(mm_shrinker); +#else + unregister_shrinker(&mm_shrinker); +#endif WARN_ON(!list_empty(&shrinker_list)); } diff --git a/include/kcl/kcl_shrinker.h b/include/kcl/kcl_shrinker.h index c237de4b867cf..ca93cd0197f9f 100644 --- a/include/kcl/kcl_shrinker.h +++ b/include/kcl/kcl_shrinker.h @@ -7,6 +7,7 @@ extern void synchronize_shrinkers(void); #endif +#ifndef HAVE_SHRINKER_REGISTER static inline int __printf(2, 3) kcl_register_shrinker(struct shrinker *shrinker, const char *fmt, ...) { @@ -16,5 +17,6 @@ static inline int __printf(2, 3) kcl_register_shrinker(struct shrinker *shrinker return register_shrinker(shrinker); #endif } +#endif #endif From ead0c9518614e8ee068e8a7c66202b1d157e43de Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 6 Dec 2023 13:29:14 +0800 Subject: [PATCH 1128/1868] drm/amdkcl: fake pci_get_base_class It's caused by v6.6-rc1-1-gd427da2323b0 PCI: Add pci_get_base_class() helper Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdkcl/kcl_pci.c | 57 +++++++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 +- drivers/gpu/drm/amd/dkms/m4/pci-dev-id.m4 | 22 +++++++++ include/kcl/kcl_pci.h | 10 ++++ 4 files changed, 90 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_pci.c b/drivers/gpu/drm/amd/amdkcl/kcl_pci.c index c62f0a2f9d6e9..742ba33ab1884 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_pci.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_pci.c @@ -249,3 +249,60 @@ u32 _kcl_pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar) EXPORT_SYMBOL(_kcl_pci_rebar_get_possible_sizes); #endif /* HAVE_PCI_REBAR_BYTES_TO_SIZE */ #endif /* AMDKCL_ENABLE_RESIZE_FB_BAR */ + +/* Copied from drivers/pci/pci.c */ +#ifndef HAVE_PCI_GET_BASE_CLASS +static inline const struct pci_device_id * +pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev) +{ + if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) && + (id->device == PCI_ANY_ID || id->device == dev->device) && + (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) && + (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) && + !((id->class ^ dev->class) & id->class_mask)) + return id; + return NULL; +} + +static int match_pci_dev_by_id(struct device *dev, const void *data) +{ + struct pci_dev *pdev = to_pci_dev(dev); + const struct pci_device_id *id = data; + + if (pci_match_one_device(id, pdev)) + return 1; + return 0; +} + +static struct pci_dev *pci_get_dev_by_id(const struct pci_device_id *id, + struct pci_dev *from) +{ + struct device *dev; + struct device *dev_start = NULL; + struct pci_dev *pdev = NULL; + + if (from) + dev_start = &from->dev; + dev = bus_find_device(&pci_bus_type, dev_start, (void *)id, + match_pci_dev_by_id); + if (dev) + pdev = to_pci_dev(dev); + pci_dev_put(from); + return pdev; +} + +struct pci_dev *pci_get_base_class(unsigned int class, struct pci_dev *from) +{ + struct pci_device_id id = { + .vendor = PCI_ANY_ID, + .device = PCI_ANY_ID, + .subvendor = PCI_ANY_ID, + .subdevice = PCI_ANY_ID, + .class_mask = 0xFF0000, + .class = class << 16, + }; + + return pci_get_dev_by_id(&id, from); +} +EXPORT_SYMBOL(pci_get_base_class); +#endif /*HAVE_PCI_GET_BASE_CLASS*/ diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index d73ccf3818682..86c380cefcb5b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -26,7 +26,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_KSYS_SYNC_HELPER AC_AMDGPU_PCI_UPSTREAM_BRIDGE AC_AMDGPU_PCI_CONFIGURE_EXTENDED_TAGS - AC_AMDGPU_PCI_DEV_ID + AC_AMDGPU_PCI AC_AMDGPU_PCI_REBAR_BYTES_TO_SIZE AC_AMDGPU_KTIME_GET_BOOTTIME_NS AC_AMDGPU_KTIME_GET_RAW_NS diff --git a/drivers/gpu/drm/amd/dkms/m4/pci-dev-id.m4 b/drivers/gpu/drm/amd/dkms/m4/pci-dev-id.m4 index 29c0928f6bd40..0138c0b995d3c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/pci-dev-id.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/pci-dev-id.m4 @@ -14,3 +14,25 @@ AC_DEFUN([AC_AMDGPU_PCI_DEV_ID], [ ]) ]) ]) + +dnl # +dnl # commit: v6.6-rc1-1-gd427da2323b0 +dnl # PCI: Add pci_get_base_class() helper +dnl # +AC_DEFUN([AC_AMDGPU_PCI_GET_BASE_CLASS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + pci_get_base_class(0, NULL); + ], [pci_get_base_class], [drivers/pci/search.c], [ + AC_DEFINE(HAVE_PCI_GET_BASE_CLASS, 1, + [pci_get_base_class() is available]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_PCI], [ + AC_AMDGPU_PCI_DEV_ID + AC_AMDGPU_PCI_GET_BASE_CLASS +]) diff --git a/include/kcl/kcl_pci.h b/include/kcl/kcl_pci.h index 62e8d734fdf5c..26bb0043066a0 100644 --- a/include/kcl/kcl_pci.h +++ b/include/kcl/kcl_pci.h @@ -206,4 +206,14 @@ u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar) #endif /* PCI_REBAR_CTRL_BAR_SHIFT */ +/* Copied from include/linux/pci.h */ +#ifndef HAVE_PCI_GET_BASE_CLASS +#ifdef CONFIG_PCI +struct pci_dev *pci_get_base_class(unsigned int class, struct pci_dev *from); +#else /*CONFIG_PCI*/ +static inline struct pci_dev *pci_get_base_class(unsigned int class, + struct pci_dev *from) +{ return NULL; } +#endif /*CONFIG_PCI*/ +#endif /*HAVE_PCI_GET_BASE_CLASS*/ #endif /* AMDKCL_PCI_H */ From 4f3e04912df81d164cfd663121b76207945aa691 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Sun, 3 Dec 2023 21:26:06 +0800 Subject: [PATCH 1129/1868] drm/amdkcl:fake vma_is_init_{heap, stack} It's caused by v6.5-rc4-265-g11250fd12eb8 mm: factor out VMA stack and heap checks Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/vma-lookup.m4 | 19 +++++++++++++++ include/kcl/kcl_mm.h | 28 +++++++++++++++++++++++ 3 files changed, 48 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 86c380cefcb5b..02488e9e21a83 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -222,6 +222,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DRIVER_GEM_PRIME_MMAP AC_AMDGPU_DRM_GEM_PRIME_HANDLE_TO_FD AC_AMDGPU_DMA_FENCE_TIMESTAMP + AC_AMDGPU_VMA_IS_INITIAL AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/vma-lookup.m4 b/drivers/gpu/drm/amd/dkms/m4/vma-lookup.m4 index 74cd3b8edd7ce..537ee8180393a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/vma-lookup.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/vma-lookup.m4 @@ -32,3 +32,22 @@ AC_DEFUN([AC_AMDGPU_VM_FLAGS_SET], [ ]) ]) ]) + +dnl # +dnl # v6.5-rc4-265-g11250fd12eb8 +dnl # mm: factor out VMA stack and heap checks +dnl # +AC_DEFUN([AC_AMDGPU_VMA_IS_INITIAL], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + vma_is_initial_heap(NULL); + vma_is_initial_stack(NULL); + ], [ + AC_DEFINE(HAVE_VMA_IS_INITIAL_HEAP, 1, + [vma_is_initial_{heap, stack} is available]) + ]) + ]) +]) + diff --git a/include/kcl/kcl_mm.h b/include/kcl/kcl_mm.h index 188cff38d5db6..646ba0d687544 100644 --- a/include/kcl/kcl_mm.h +++ b/include/kcl/kcl_mm.h @@ -138,4 +138,32 @@ static inline unsigned long _kcl_totalram_pages(void) #define totalram_pages _kcl_totalram_pages #endif /* HAVE_TOTALRAM_PAGES */ +/*copy from include/linux/mm.h */ +#ifndef HAVE_VMA_IS_INITIAL_HEAP +/* + * Indicate if the VMA is a heap for the given task; for + * /proc/PID/maps that is the heap of the main task. + */ +static inline bool vma_is_initial_heap(const struct vm_area_struct *vma) +{ + return vma->vm_start <= vma->vm_mm->brk && + vma->vm_end >= vma->vm_mm->start_brk; +} + +/* + * Indicate if the VMA is a stack for the given task; for + * /proc/PID/maps that is the stack of the main task. + */ +static inline bool vma_is_initial_stack(const struct vm_area_struct *vma) +{ + /* + * We make no effort to guess what a given thread considers to be + * its "stack". It's not even well-defined for programs written + * languages like Go. + */ + return vma->vm_start <= vma->vm_mm->start_stack && + vma->vm_end >= vma->vm_mm->start_stack; +} +#endif + #endif /* AMDKCL_MM_H */ From c45238a5870c2c73d50cad444f26c22acf0eb296 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Sun, 3 Dec 2023 21:26:57 +0800 Subject: [PATCH 1130/1868] drm/amdkcl: test struct x86 whether has member topo Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 4 ++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/processor.m4 | 18 ++++++++++++++++++ 3 files changed, 23 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/processor.m4 diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index 3fe374ecd6917..763ce65a441a8 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -2404,7 +2404,11 @@ static int kfd_cpumask_to_apic_id(const struct cpumask *cpumask) if (first_cpu_of_numa_node >= nr_cpu_ids) return -1; #ifdef CONFIG_X86_64 +#ifdef HAVE_CPUINFO_TOPOLOGY_IN_CPUINFO_X86_STRUCT return cpu_data(first_cpu_of_numa_node).topo.apicid; +#else + return cpu_data(first_cpu_of_numa_node).apicid; +#endif #else return first_cpu_of_numa_node; #endif diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 02488e9e21a83..aaedb9970f46f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -223,6 +223,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_GEM_PRIME_HANDLE_TO_FD AC_AMDGPU_DMA_FENCE_TIMESTAMP AC_AMDGPU_VMA_IS_INITIAL + AC_AMDGPU_CPUINFO_X86 AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/processor.m4 b/drivers/gpu/drm/amd/dkms/m4/processor.m4 new file mode 100644 index 0000000000000..66dececcd8989 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/processor.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit v6.6-rc1-4-gb9655e702dc5 +dnl # x86/cpu: Encapsulate topology information in cpuinfo_x86 +dnl # +AC_DEFUN([AC_AMDGPU_CPUINFO_X86], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct cpuinfo_x86* cpuinfo = NULL; + struct cpuinfo_topology topo; + topo = cpuinfo -> topo; + ],[ + AC_DEFINE(HAVE_CPUINFO_TOPOLOGY_IN_CPUINFO_X86_STRUCT, 1, + [ cpuinfo_x86.topo is available]) + ]) + ]) +]) From 6c60ac453314f8c43270732e7eab3d100439fb08 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 6 Dec 2023 17:53:42 +0800 Subject: [PATCH 1131/1868] drm/amdkcl: update config.h Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/config/config.h | 28 ++++++++++++++---------- 1 file changed, 17 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 32a92704bd98d..8e7ea0ecdee47 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -35,7 +35,7 @@ #define HAVE_AMDKCL_HMM_MIRROR_ENABLED 1 /* amd_iommu_invalidate_ctx take arg type of pasid as u32 */ -#define HAVE_AMD_IOMMU_INVALIDATE_CTX_PASID_U32 1 +/* #undef HAVE_AMD_IOMMU_INVALIDATE_CTX_PASID_U32 */ /* amd_iommu_pc_get_max_banks() declared */ #define HAVE_AMD_IOMMU_PC_GET_MAX_BANKS_DECLARED 1 @@ -82,6 +82,9 @@ /* compat_ptr_ioctl() is available */ #define HAVE_COMPAT_PTR_IOCTL 1 +/* cpuinfo_x86.topo is available */ +#define HAVE_CPUINFO_TOPOLOGY_IN_CPUINFO_X86_STRUCT 1 + /* debugfs_create_file_size() is available */ #define HAVE_DEBUGFS_CREATE_FILE_SIZE 1 @@ -133,11 +136,8 @@ /* struct dma_fence_ops has use_64bit_seqno field */ #define HAVE_DMA_FENCE_OPS_USE_64BIT_SEQNO 1 -/* dma_fence_set_error() is available */ -#define HAVE_DMA_FENCE_SET_ERROR 1 - -/* dma_map_resource() is enabled */ -#define HAVE_DMA_MAP_RESOURCE 1 +/* dma_fence_TIMESTAMP() is available */ +#define HAVE_DMA_FENCE_TIMESTAMP 1 /* dma_map_sgtable() is enabled */ #define HAVE_DMA_MAP_SGTABLE 1 @@ -901,8 +901,8 @@ /* struct pci_driver has field dev_groups */ #define HAVE_PCI_DRIVER_DEV_GROUPS 1 -/* pci_is_thunderbolt_attached() is available */ -#define HAVE_PCI_IS_THUNDERBOLD_ATTACHED 1 +/* pci_get_base_class() is available */ +#define HAVE_PCI_GET_BASE_CLASS 1 /* pci_pr3_present() is available */ #define HAVE_PCI_PR3_PRESENT 1 @@ -938,7 +938,7 @@ #define HAVE_RB_ROOT_CACHED 1 /* whether register_shrinker(x, x) is available */ -#define HAVE_REGISTER_SHRINKER_WITH_TWO_ARGUMENTS 1 +/* #undef HAVE_REGISTER_SHRINKER_WITH_TWO_ARGUMENTS */ /* remove_conflicting_pci_framebuffers() wants p,p args */ /* #undef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP */ @@ -949,6 +949,9 @@ /* seq_hex_dump() is available */ #define HAVE_SEQ_HEX_DUMP 1 +/* shrinker_register() is available */ +#define HAVE_SHRINKER_REGISTER 1 + /* smca_get_bank_type(x) is available */ /* #undef HAVE_SMCA_GET_BANK_TYPE_WITH_ONE_ARGUMENT */ @@ -1020,7 +1023,7 @@ #define HAVE_STR_YES_NO 1 /* synchronize_shrinkers() is available */ -#define HAVE_SYNCHRONIZE_SHRINKERS 1 +/* #undef HAVE_SYNCHRONIZE_SHRINKERS */ /* sysfs_emit() and sysfs_emit_at() are available */ #define HAVE_SYSFS_EMIT 1 @@ -1043,6 +1046,9 @@ /* vga_switcheroo_set_dynamic_switch() exist */ /* #undef HAVE_VGA_SWITCHEROO_SET_DYNAMIC_SWITCH */ +/* vma_is_initial_{heap, stack} is available */ +#define HAVE_VMA_IS_INITIAL_HEAP 1 + /* vma_lookup() is available */ #define HAVE_VMA_LOOKUP 1 @@ -1101,7 +1107,7 @@ #define HAVE___DRM_ATOMIC_HELPER_CRTC_RESET 1 /* __kthread_should_park() is available */ -#define HAVE___KTHREAD_SHOULD_PARK 1 +/* #undef HAVE___KTHREAD_SHOULD_PARK */ /* Define to the address where bug reports for this package should be sent. */ #define PACKAGE_BUGREPORT "" From e21c3e4048d660b25a8ac55cac72c7f4c656dd34 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 7 Dec 2023 17:40:47 +0800 Subject: [PATCH 1132/1868] Bump dkms version to 6.7.0 Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/config/config.h | 2 +- drivers/gpu/drm/amd/dkms/configure.ac | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 8e7ea0ecdee47..8c1db7a2a5698 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -1125,7 +1125,7 @@ #define PACKAGE_URL "" /* Define to the version of this package. */ -#define PACKAGE_VERSION "6.5.0" +#define PACKAGE_VERSION "6.7.0" #include "config-amd-chips.h" diff --git a/drivers/gpu/drm/amd/dkms/configure.ac b/drivers/gpu/drm/amd/dkms/configure.ac index 666a4766a10b2..61264904932e5 100644 --- a/drivers/gpu/drm/amd/dkms/configure.ac +++ b/drivers/gpu/drm/amd/dkms/configure.ac @@ -1,4 +1,4 @@ -AC_INIT(amdgpu-dkms, 6.5.0) +AC_INIT(amdgpu-dkms, 6.7.0) AC_LANG(C) AC_CONFIG_AUX_DIR([config]) From 51371552cbd98660a02c97c7be7a9933bfbcb26e Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 7 Dec 2023 17:25:32 +0800 Subject: [PATCH 1133/1868] drm/amdkcl: fake dma_fence_is_later_or_same It's caused by v6.7-rc1-17-g95ba893c9f4f dma-buf: fix check in dma_resv_add_fence Signed-off-by: Asher Song --- .../gpu/drm/amd/dkms/m4/dma-fence-is-later.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_dma_fence.h | 8 ++++++++ 3 files changed, 25 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-fence-is-later.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-fence-is-later.m4 index bbc3eb8117f9c..0523264d08807 100644 --- a/drivers/gpu/drm/amd/dkms/m4/dma-fence-is-later.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/dma-fence-is-later.m4 @@ -28,3 +28,19 @@ AC_DEFUN([AC_AMDGPU__DMA_FENCE_IS_LATER], [ ]) ]) ]) + +dnl # +dnl # v6.7-rc1-17-g95ba893c9f4f +dnl # dma-buf: fix check in dma_resv_add_fence +dnl # +AC_DEFUN([AC_AMDGPU_DMA_FENCE_IS_LATER_OR_SAME], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + dma_fence_is_later_or_same(NULL, NULL); + ], [ + AC_DEFINE(HAVE_DMA_FENCE_IS_LATER_OR_SAME, 1, [dma_fence_is_later_or_same() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index aaedb9970f46f..79c29cad5f3fd 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -224,6 +224,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DMA_FENCE_TIMESTAMP AC_AMDGPU_VMA_IS_INITIAL AC_AMDGPU_CPUINFO_X86 + AC_AMDGPU_DMA_FENCE_IS_LATER_OR_SAME AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_dma_fence.h b/include/kcl/kcl_dma_fence.h index ae63b65466e00..a24278c214244 100644 --- a/include/kcl/kcl_dma_fence.h +++ b/include/kcl/kcl_dma_fence.h @@ -66,4 +66,12 @@ static inline ktime_t dma_fence_timestamp(struct dma_fence *fence) } #endif +/* copy from include/linux/dma-fence.h*/ +#ifndef HAVE_DMA_FENCE_IS_LATER_OR_SAME +static inline bool dma_fence_is_later_or_same(struct dma_fence *f1, + struct dma_fence *f2) +{ + return f1 == f2 || dma_fence_is_later(f1, f2); +} +#endif /*HAVE_DMA_FENCE_IS_LATER_OR_SAME*/ #endif From bc5448f62d181539dd57515f549e4a4a614e650c Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 5 Dec 2023 15:23:43 +0800 Subject: [PATCH 1134/1868] drm/amdkcl: tset whether list_cmp_func is const param It's caused by 93de84df60bc71c5f0d95de84a71eb119b51afe1 "drm/amdgpu: optimize the printing order of error data" Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 4 ++++ drivers/gpu/drm/amd/dkms/config/config.h | 4 ++-- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/list-sort.m4 | 18 ++++++++++++++++++ 4 files changed, 25 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/list-sort.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index f5b67adb65ae7..501fbd2de31ff 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -4589,7 +4589,11 @@ static struct ras_err_node *amdgpu_ras_error_node_new(void) return err_node; } +#ifdef HAVE_LIST_CMP_FUNC_IS_CONST_PARAM static int ras_err_info_cmp(void *priv, const struct list_head *a, const struct list_head *b) +#else +static int ras_err_info_cmp(void *priv, struct list_head *a, struct list_head *b) +#endif { struct ras_err_node *nodea = container_of(a, struct ras_err_node, node); struct ras_err_node *nodeb = container_of(b, struct ras_err_node, node); diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 8c1db7a2a5698..3cbf22a50195d 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -832,8 +832,8 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_XARRAY_H 1 -/* list_bulk_move_tail() is available */ -#define HAVE_LIST_BULK_MOVE_TAIL 1 +/* list_cmp_func() is const param */ +#define HAVE_LIST_CMP_FUNC_IS_CONST_PARAM 1 /* list_is_first() is available */ #define HAVE_LIST_IS_FIRST 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 79c29cad5f3fd..58aa30bb1487b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -213,6 +213,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_VM_FLAGS_SET AC_AMDGPU_MMAP_ASSERT_WRITE_LOCKED AC_AMDGPU_PID_TYPE + AC_AMDGPU_LIST_CMP_FUNC_IS_CONST_PARAM AC_AMDGPU_DMA_FENCE_OPS_SET_DEADLINE AC_AMDGPU_DRM_SHOW_FDINFO AC_AMDGPU_LINUX_ATOMIC_LONG_TRY_CMPXCHG diff --git a/drivers/gpu/drm/amd/dkms/m4/list-sort.m4 b/drivers/gpu/drm/amd/dkms/m4/list-sort.m4 new file mode 100644 index 0000000000000..aa7b739d04961 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/list-sort.m4 @@ -0,0 +1,18 @@ +dnl # +dnl # commit v5.12-rc6-9-g4f0f586bf0c8 +dnl # treewide: Change list_sort to use const pointers +dnl # +AC_DEFUN([AC_AMDGPU_LIST_CMP_FUNC_IS_CONST_PARAM], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + list_cmp_func_t cmp = NULL; + struct list_head a, b; + cmp(NULL, &a, &b); + ], [ + AC_DEFINE(HAVE_LIST_CMP_FUNC_IS_CONST_PARAM, 1, + [list_cmp_func() is const param]) + ]) + ]) +]) \ No newline at end of file From 0ae61040e707cf2f6c6ed6130e0774a4de137d85 Mon Sep 17 00:00:00 2001 From: Yang Wang Date: Tue, 21 Nov 2023 16:47:57 +0800 Subject: [PATCH 1135/1868] drm/amd/kcl: fix issue of missing mca-debug-mode debugfs node v1: fix issue of missing mca-debug-mode debugfs node. v2: using helper macro DEFINE_SIMPLE_ATTRIBUTE to simple code Fixes: 96e2072e93c0 ("drm/amdkcl: wrap code under macro DEFINE_DEBUGFS_ATTRIBUTE") Signed-off-by: Yang Wang Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c index e1ce65d097394..7f62c72a69653 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mca.c @@ -596,6 +596,8 @@ static const struct file_operations mca_ue_dump_debug_fops = { #ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(mca_debug_mode_fops, NULL, amdgpu_mca_smu_debug_mode_set, "%llu\n"); +#else +DEFINE_SIMPLE_ATTRIBUTE(mca_debug_mode_fops, NULL, amdgpu_mca_smu_debug_mode_set, "%llu\n"); #endif #endif @@ -605,9 +607,7 @@ void amdgpu_mca_smu_debugfs_init(struct amdgpu_device *adev, struct dentry *root if (!root) return; -#ifdef DEFINE_DEBUGFS_ATTRIBUTE debugfs_create_file("mca_debug_mode", 0200, root, adev, &mca_debug_mode_fops); -#endif debugfs_create_file("mca_ue_dump", 0400, root, adev, &mca_ue_dump_debug_fops); debugfs_create_file("mca_ce_dump", 0400, root, adev, &mca_ce_dump_debug_fops); #endif From 12cb1249a2b4b98e92b73a9d91f4349c83268207 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 4 Dec 2023 15:54:47 +0800 Subject: [PATCH 1136/1868] drm/amdkcl: reduce argunemts of kgd2kfd_resume To aliagn with kgd2kfd_resume prototype, reduce arguments of dummy kgd2kfd_resume. Signed-off-by: Asher Song Reviewed-by: Ma Jun --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index e77475d87b264..ada20ca54dec5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -530,7 +530,7 @@ static inline void kgd2kfd_suspend(struct kfd_dev *kfd, bool run_pm, bool force) { } -static inline int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm, bool sync) +static inline int kgd2kfd_resume(struct kfd_dev *kfd, bool run_pm) { return 0; } From 013689e8ebb08a230c4be6ed14ea8c41f90787f7 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 7 Dec 2023 13:46:52 +0800 Subject: [PATCH 1137/1868] drm/amdkcl: update config.h It's caused by 9a893b4afa61a72b3a81dd334c210fdb4ca93154 Revert "drm/prime: Unexport helpers for fd/handle conversion" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/dkms/config/config.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 3cbf22a50195d..78dad82271a67 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -538,7 +538,7 @@ #define HAVE_DRM_GEM_PLANE_HELPER_PREPARE_FB 1 /* drm_gem_prime_handle_to_fd() is available */ -/* #undef HAVE_DRM_GEM_PRIME_HANDLE_TO_FD */ +#define HAVE_DRM_GEM_PRIME_HANDLE_TO_FD 1 /* drm_hdcp_update_content_protection is available */ #define HAVE_DRM_HDCP_UPDATE_CONTENT_PROTECTION 1 From b792c16ba40c6a2df80d75c26ed39ce507c89b11 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 7 Dec 2023 11:13:44 +0800 Subject: [PATCH 1138/1868] drm/amdkcl: fake drm_client_register() It's caused by 6a56a446d0dfd620c451772f742c20dafa9fe83b "drm/amdkfd: Export DMABufs from KFD using GEM handles" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../gpu/drm/amd/dkms/m4/drm_client_register.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_client.h | 14 ++++++++++++++ 5 files changed, 35 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_client_register.m4 create mode 100644 include/kcl/kcl_drm_client.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index a504ed69b614e..a5442efc9dcbe 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -118,4 +118,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 78dad82271a67..0c31fb3b4882a 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -179,6 +179,9 @@ /* drm_atomic_private_obj_init() wants 4 args */ #define HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT_4ARGS 1 +/* drm_client_register() is available */ +#define HAVE_DRM_CLIENT_REGISTER 1 + /* drm_connector_atomic_hdr_metadata_equal() is available */ #define HAVE_DRM_CONNECTOR_ATOMIC_HDR_METADATA_EQUAL 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_client_register.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_client_register.m4 new file mode 100644 index 0000000000000..ef060260bee20 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_client_register.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v5.1-rc2-1103-ge33898a20744 +dnl # drm/client: Rename drm_client_add() to drm_client_register() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CLIENT_REGISTER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + drm_client_register(NULL); + ],[ + AC_DEFINE(HAVE_DRM_CLIENT_REGISTER, 1, + [drm_client_register() is available]) + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 58aa30bb1487b..91cd90b9323c8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -220,6 +220,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_LINUX_LOCAL_TRY_CMPXCHG AC_AMDGPU_LINUX_DEVICE_CLASS AC_AMDGPU_KVREALLOC + AC_AMDGPU_DRM_CLIENT_REGISTER AC_AMDGPU_DRM_DRIVER_GEM_PRIME_MMAP AC_AMDGPU_DRM_GEM_PRIME_HANDLE_TO_FD AC_AMDGPU_DMA_FENCE_TIMESTAMP diff --git a/include/kcl/kcl_drm_client.h b/include/kcl/kcl_drm_client.h new file mode 100644 index 0000000000000..0857e2fc2cd65 --- /dev/null +++ b/include/kcl/kcl_drm_client.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef KCL_KCL_DRM_CLIENT_H +#define KCL_KCL_DRM_CLIENT_H + +#include + +#ifndef HAVE_DRM_CLIENT_REGISTER +static inline void drm_client_register(struct drm_client_dev *client) +{ + drm_client_add(client); +} +#endif /* HAVE_DRM_CLIENT_REGISTER */ + +#endif From db88cd7ea6722b860faa3272d76acdb30ca4bf16 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 15 Dec 2023 10:57:13 +0800 Subject: [PATCH 1139/1868] drm/amdkcl: fake drm_dbg_driver() It's casued by eb826a227c7d72fecb1b40d49d1d6ec611fa4219 "drm/amd/display: add plane shaper LUT support" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- include/kcl/kcl_drm_print.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index c1aa05a71ff23..e2855aa2a299d 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -142,6 +142,11 @@ void kcl_drm_err(const char *format, ...); drm_dev_dbg((drm) ? (drm)->dev : NULL, DRM_UT_DP, fmt, ##__VA_ARGS__) #endif +#if !defined(drm_dbg_driver) +#define drm_dbg_driver(drm, fmt, ...) \ + drm_dev_dbg((drm) ? (drm)->dev : NULL, DRM_UT_DRIVER, fmt, ##__VA_ARGS__) +#endif + #ifndef HAVE_DRM_DEBUG_ENABLED /* Copied from v5.3-rc1-708-gf0a8f533adc2 include/drm/drm_print.h */ static inline bool drm_debug_enabled(unsigned int category) From 408e8baec1bcba9f50e886db30e46bafcb8795ef Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 23 Aug 2024 18:54:39 +0800 Subject: [PATCH 1140/1868] drm/amdkcl: check whether acpi_amd_wbrf.h exist It's caused by v6.7-rc1-2-g58e82a62669d platform/x86/amd: Add support for AMD ACPI based Wifi band RFI mitigation feature Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_wbrf.c | 319 +++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 | 5 + include/kcl/header/linux/acpi_amd_wbrf.h | 9 + include/kcl/kcl_acpi_amd_wbrf.h | 94 ++++++ 6 files changed, 429 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_wbrf.c create mode 100644 include/kcl/header/linux/acpi_amd_wbrf.h create mode 100644 include/kcl/kcl_acpi_amd_wbrf.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 49b0fe52e6ddc..d5a8a1db57bac 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -20,7 +20,7 @@ amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o amdkcl-$(CONFIG_DEBUG_FS) += kcl_debugfs_inode.o kcl_debugfs_file.o amdkcl-$(CONFIG_SYSFS) += kcl_sysfs_emit.o - +amdkcl-$(CONFIG_AMD_WBRF) += kcl_wbrf.o CFLAGS_kcl_fence.o := -I$(src) ccflags-y += \ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_wbrf.c b/drivers/gpu/drm/amd/amdkcl/kcl_wbrf.c new file mode 100644 index 0000000000000..3299b4e78c7a7 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_wbrf.c @@ -0,0 +1,319 @@ +//SPDX-License-Identifier: GPL-2.0 +/* + * Wifi Frequency Band Manage Interface + * Copyright (C) 2023 Advanced Micro Devices + */ + +#include +#include + +#ifndef HAVE_LINUX_ACPI_AMD_WBRF_H +/* + * Functions bit vector for WBRF method + * + * Bit 0: WBRF supported. + * Bit 1: Function 1 (Add / Remove frequency) is supported. + * Bit 2: Function 2 (Get frequency list) is supported. + */ +#define WBRF_ENABLED 0x0 +#define WBRF_RECORD 0x1 +#define WBRF_RETRIEVE 0x2 + +#define WBRF_REVISION 0x1 + +/* + * The data structure used for WBRF_RETRIEVE is not naturally aligned. + * And unfortunately the design has been settled down. + */ +struct amd_wbrf_ranges_out { + u32 num_of_ranges; + struct freq_band_range band_list[MAX_NUM_OF_WBRF_RANGES]; +} __packed; + +static const guid_t wifi_acpi_dsm_guid = + GUID_INIT(0x7b7656cf, 0xdc3d, 0x4c1c, + 0x83, 0xe9, 0x66, 0xe7, 0x21, 0xde, 0x30, 0x70); + +/* + * Used to notify consumer (amdgpu driver currently) about + * the wifi frequency is change. + */ +static BLOCKING_NOTIFIER_HEAD(wbrf_chain_head); + +static int wbrf_record(struct acpi_device *adev, uint8_t action, struct wbrf_ranges_in_out *in) +{ + union acpi_object argv4; + union acpi_object *tmp; + union acpi_object *obj; + u32 num_of_ranges = 0; + u32 num_of_elements; + u32 arg_idx = 0; + int ret; + u32 i; + + if (!in) + return -EINVAL; + + for (i = 0; i < ARRAY_SIZE(in->band_list); i++) { + if (in->band_list[i].start && in->band_list[i].end) + num_of_ranges++; + } + + /* + * The num_of_ranges value in the "in" object supplied by + * the caller is required to be equal to the number of + * entries in the band_list array in there. + */ + if (num_of_ranges != in->num_of_ranges) + return -EINVAL; + + /* + * Every input frequency band comes with two end points(start/end) + * and each is accounted as an element. Meanwhile the range count + * and action type are accounted as an element each. + * So, the total element count = 2 * num_of_ranges + 1 + 1. + */ + num_of_elements = 2 * num_of_ranges + 2; + + tmp = kcalloc(num_of_elements, sizeof(*tmp), GFP_KERNEL); + if (!tmp) + return -ENOMEM; + + argv4.package.type = ACPI_TYPE_PACKAGE; + argv4.package.count = num_of_elements; + argv4.package.elements = tmp; + + /* save the number of ranges*/ + tmp[0].integer.type = ACPI_TYPE_INTEGER; + tmp[0].integer.value = num_of_ranges; + + /* save the action(WBRF_RECORD_ADD/REMOVE/RETRIEVE) */ + tmp[1].integer.type = ACPI_TYPE_INTEGER; + tmp[1].integer.value = action; + + arg_idx = 2; + for (i = 0; i < ARRAY_SIZE(in->band_list); i++) { + if (!in->band_list[i].start || !in->band_list[i].end) + continue; + + tmp[arg_idx].integer.type = ACPI_TYPE_INTEGER; + tmp[arg_idx++].integer.value = in->band_list[i].start; + tmp[arg_idx].integer.type = ACPI_TYPE_INTEGER; + tmp[arg_idx++].integer.value = in->band_list[i].end; + } + + obj = acpi_evaluate_dsm(adev->handle, &wifi_acpi_dsm_guid, + WBRF_REVISION, WBRF_RECORD, &argv4); + + if (!obj) + return -EINVAL; + + if (obj->type != ACPI_TYPE_INTEGER) { + ret = -EINVAL; + goto out; + } + + ret = obj->integer.value; + if (ret) + ret = -EINVAL; + +out: + ACPI_FREE(obj); + kfree(tmp); + + return ret; +} + +/** + * acpi_amd_wbrf_add_remove - add or remove the frequency band the device is using + * + * @dev: device pointer + * @action: remove or add the frequency band into bios + * @in: input structure containing the frequency band the device is using + * + * Broadcast to other consumers the frequency band the device starts + * to use. Underneath the surface the information is cached into an + * internal buffer first. Then a notification is sent to all those + * registered consumers. So then they can retrieve that buffer to + * know the latest active frequency bands. Consumers that haven't + * yet been registered can retrieve the information from the cache + * when they register. + * + * Return: + * 0 for success add/remove wifi frequency band. + * Returns a negative error code for failure. + */ +int acpi_amd_wbrf_add_remove(struct device *dev, uint8_t action, struct wbrf_ranges_in_out *in) +{ + struct acpi_device *adev; + int ret; + + adev = ACPI_COMPANION(dev); + if (!adev) + return -ENODEV; + + ret = wbrf_record(adev, action, in); + if (ret) + return ret; + + blocking_notifier_call_chain(&wbrf_chain_head, WBRF_CHANGED, NULL); + + return 0; +} +EXPORT_SYMBOL_GPL(acpi_amd_wbrf_add_remove); + +/** + * acpi_amd_wbrf_supported_producer - determine if the WBRF can be enabled + * for the device as a producer + * + * @dev: device pointer + * + * Check if the platform equipped with necessary implementations to + * support WBRF for the device as a producer. + * + * Return: + * true if WBRF is supported, otherwise returns false + */ +bool acpi_amd_wbrf_supported_producer(struct device *dev) +{ + struct acpi_device *adev; + + adev = ACPI_COMPANION(dev); + if (!adev) + return false; + + return acpi_check_dsm(adev->handle, &wifi_acpi_dsm_guid, + WBRF_REVISION, BIT(WBRF_RECORD)); +} +EXPORT_SYMBOL_GPL(acpi_amd_wbrf_supported_producer); + +/** + * acpi_amd_wbrf_supported_consumer - determine if the WBRF can be enabled + * for the device as a consumer + * + * @dev: device pointer + * + * Determine if the platform equipped with necessary implementations to + * support WBRF for the device as a consumer. + * + * Return: + * true if WBRF is supported, otherwise returns false. + */ +bool acpi_amd_wbrf_supported_consumer(struct device *dev) +{ + struct acpi_device *adev; + + adev = ACPI_COMPANION(dev); + if (!adev) + return false; + + return acpi_check_dsm(adev->handle, &wifi_acpi_dsm_guid, + WBRF_REVISION, BIT(WBRF_RETRIEVE)); +} +EXPORT_SYMBOL_GPL(acpi_amd_wbrf_supported_consumer); + +/** + * amd_wbrf_retrieve_freq_band - retrieve current active frequency bands + * + * @dev: device pointer + * @out: output structure containing all the active frequency bands + * + * Retrieve the current active frequency bands which were broadcasted + * by other producers. The consumer who calls this API should take + * proper actions if any of the frequency band may cause RFI with its + * own frequency band used. + * + * Return: + * 0 for getting wifi freq band successfully. + * Returns a negative error code for failure. + */ +int amd_wbrf_retrieve_freq_band(struct device *dev, struct wbrf_ranges_in_out *out) +{ + struct amd_wbrf_ranges_out acpi_out = {0}; + struct acpi_device *adev; + union acpi_object *obj; + union acpi_object param; + int ret = 0; + + adev = ACPI_COMPANION(dev); + if (!adev) + return -ENODEV; + + param.type = ACPI_TYPE_STRING; + param.string.length = 0; + param.string.pointer = NULL; + + obj = acpi_evaluate_dsm(adev->handle, &wifi_acpi_dsm_guid, + WBRF_REVISION, WBRF_RETRIEVE, ¶m); + if (!obj) + return -EINVAL; + + /* + * The return buffer is with variable length and the format below: + * number_of_entries(1 DWORD): Number of entries + * start_freq of 1st entry(1 QWORD): Start frequency of the 1st entry + * end_freq of 1st entry(1 QWORD): End frequency of the 1st entry + * ... + * ... + * start_freq of the last entry(1 QWORD) + * end_freq of the last entry(1 QWORD) + * + * Thus the buffer length is determined by the number of entries. + * - For zero entry scenario, the buffer length will be 4 bytes. + * - For one entry scenario, the buffer length will be 20 bytes. + */ + if (obj->buffer.length > sizeof(acpi_out) || obj->buffer.length < 4) { + dev_err(dev, "Wrong sized WBRT information"); + ret = -EINVAL; + goto out; + } + memcpy(&acpi_out, obj->buffer.pointer, obj->buffer.length); + + out->num_of_ranges = acpi_out.num_of_ranges; + memcpy(out->band_list, acpi_out.band_list, sizeof(acpi_out.band_list)); + +out: + ACPI_FREE(obj); + return ret; +} +EXPORT_SYMBOL_GPL(amd_wbrf_retrieve_freq_band); + +/** + * amd_wbrf_register_notifier - register for notifications of frequency + * band update + * + * @nb: driver notifier block + * + * The consumer should register itself via this API so that it can get + * notified on the frequency band updates from other producers. + * + * Return: + * 0 for registering a consumer driver successfully. + * Returns a negative error code for failure. + */ +int amd_wbrf_register_notifier(struct notifier_block *nb) +{ + return blocking_notifier_chain_register(&wbrf_chain_head, nb); +} +EXPORT_SYMBOL_GPL(amd_wbrf_register_notifier); + +/** + * amd_wbrf_unregister_notifier - unregister for notifications of + * frequency band update + * + * @nb: driver notifier block + * + * The consumer should call this API when it is longer interested with + * the frequency band updates from other producers. Usually, this should + * be performed during driver cleanup. + * + * Return: + * 0 for unregistering a consumer driver. + * Returns a negative error code for failure. + */ +int amd_wbrf_unregister_notifier(struct notifier_block *nb) +{ + return blocking_notifier_chain_unregister(&wbrf_chain_head, nb); +} +EXPORT_SYMBOL_GPL(amd_wbrf_unregister_notifier); +#endif /*HAVE_LINUX_ACPI_AMD_WBRF_H*/ diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index a5442efc9dcbe..f82375d7f8f10 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -119,4 +119,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 index a9a77d3a9cdf4..88fa953aa980a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 @@ -129,4 +129,9 @@ AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ dnl #bug: split BUILD_BUG stuff out into dnl AC_KERNEL_CHECK_HEADERS([linux/build_bug.h]) + + dnl #v6.7-rc1-2-g58e82a62669d + dnl #platform/x86/amd: Add support for AMD ACPI based Wifi band RFI mitigation feature + dnl + AC_KERNEL_CHECK_HEADERS([linux/acpi_amd_wbrf.h]) ]) diff --git a/include/kcl/header/linux/acpi_amd_wbrf.h b/include/kcl/header/linux/acpi_amd_wbrf.h new file mode 100644 index 0000000000000..ecf5be29494d4 --- /dev/null +++ b/include/kcl/header/linux/acpi_amd_wbrf.h @@ -0,0 +1,9 @@ +#ifndef _KCL_HEADER___ACPI_AMD_WBRF_H___H_ +#define _KCL_HEADER___ACPI_AMD_WBRF_H___H_ + +#ifdef HAVE_LINUX_ACPI_AMD_WBRF_H +#include_next +#endif + +#endif + diff --git a/include/kcl/kcl_acpi_amd_wbrf.h b/include/kcl/kcl_acpi_amd_wbrf.h new file mode 100644 index 0000000000000..b8178e740f171 --- /dev/null +++ b/include/kcl/kcl_acpi_amd_wbrf.h @@ -0,0 +1,94 @@ +/*Copy from include/linux/acpi_amd_wbrf.h*/ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Wifi Band Exclusion Interface (AMD ACPI Implementation) + * Copyright (C) 2023 Advanced Micro Devices + */ + +#ifndef _KCL_ACPI_AMD_WBRF_H +#define _KCL_ACPI_AMD_WBRF_H + +#ifndef HAVE_LINUX_ACPI_AMD_WBRF_H +#include +#include + +/* The maximum number of frequency band ranges */ +#define MAX_NUM_OF_WBRF_RANGES 11 + +/* Record actions */ +#define WBRF_RECORD_ADD 0x0 +#define WBRF_RECORD_REMOVE 0x1 + +/** + * struct freq_band_range - Wifi frequency band range definition + * @start: start frequency point (in Hz) + * @end: end frequency point (in Hz) + */ +struct freq_band_range { + u64 start; + u64 end; +}; + +/** + * struct wbrf_ranges_in_out - wbrf ranges info + * @num_of_ranges: total number of band ranges in this struct + * @band_list: array of Wifi band ranges + */ +struct wbrf_ranges_in_out { + u64 num_of_ranges; + struct freq_band_range band_list[MAX_NUM_OF_WBRF_RANGES]; +}; + +/** + * enum wbrf_notifier_actions - wbrf notifier actions index + * @WBRF_CHANGED: there was some frequency band updates. The consumers + * should retrieve the latest active frequency bands. + */ +enum wbrf_notifier_actions { + WBRF_CHANGED, +}; + +#if IS_ENABLED(CONFIG_AMD_WBRF) +bool acpi_amd_wbrf_supported_producer(struct device *dev); +int acpi_amd_wbrf_add_remove(struct device *dev, uint8_t action, struct wbrf_ranges_in_out *in); +bool acpi_amd_wbrf_supported_consumer(struct device *dev); +int amd_wbrf_retrieve_freq_band(struct device *dev, struct wbrf_ranges_in_out *out); +int amd_wbrf_register_notifier(struct notifier_block *nb); +int amd_wbrf_unregister_notifier(struct notifier_block *nb); +#else +static inline +bool acpi_amd_wbrf_supported_consumer(struct device *dev) +{ + return false; +} + +static inline +int acpi_amd_wbrf_add_remove(struct device *dev, uint8_t action, struct wbrf_ranges_in_out *in) +{ + return -ENODEV; +} + +static inline +bool acpi_amd_wbrf_supported_producer(struct device *dev) +{ + return false; +} +static inline +int amd_wbrf_retrieve_freq_band(struct device *dev, struct wbrf_ranges_in_out *out) +{ + return -ENODEV; +} +static inline +int amd_wbrf_register_notifier(struct notifier_block *nb) +{ + return -ENODEV; +} +static inline +int amd_wbrf_unregister_notifier(struct notifier_block *nb) +{ + return -ENODEV; +} +#endif /* CONFIG_AMD_WBRF */ + +#endif /* HAVE_LINUX_ACPI_AMD_WBRF */ +#endif /* _KCL_ACPI_AMD_WBRF_H */ From 905b9add0f0fb415be9ebea628024bf40cf67b4a Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 20 Dec 2023 17:15:52 +0800 Subject: [PATCH 1141/1868] drm/amdkcl: check whether drm/drm_eld.h exist It's caused by v6.6-rc2-771-g8eb80946ab0c drm/edid: split out drm_eld.h from drm_edid.h Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 5 +++++ include/kcl/header/drm/drm_eld.h | 9 +++++++++ 2 files changed, 14 insertions(+) create mode 100644 include/kcl/header/drm/drm_eld.h diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index 76f76c549528a..6dd1ab847b3bb 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -105,4 +105,9 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # AC_KERNEL_CHECK_HEADERS([drm/drm_exec.h]) + dnl # + dnl # v6.6-rc2-771-g8eb80946ab0c + dnl # drm/edid: split out drm_eld.h from drm_edid.h + dnl # + AC_KERNEL_CHECK_HEADERS([drm/drm_eld.h]) ]) diff --git a/include/kcl/header/drm/drm_eld.h b/include/kcl/header/drm/drm_eld.h new file mode 100644 index 0000000000000..e531edccae0d7 --- /dev/null +++ b/include/kcl/header/drm/drm_eld.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DRM_ELD_H_ +#define _KCL_HEADER_DRM_ELD_H_H_ + +#ifdef HAVE_DRM_DRM_ELD_H +#include_next +#endif + +#endif From 3e3f54b0412c961fb17c52b0cc46ddc73078cd11 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 21 Dec 2023 14:19:22 +0800 Subject: [PATCH 1142/1868] drm/amdkcl: test drm_dp_calc_pbn_mode whether has two argument It's caused by v6.6-rc2-668-g7707dd602259 drm/dp_mst: Fix fractional DSC bpp handling Signed-off-by: Asher Song --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 | 7 +++++-- include/kcl/backport/kcl_drm_dp_mst_helper_backport.h | 11 ++++++++--- 3 files changed, 14 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index a3b6a798bd94f..06833f87d107c 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -7717,7 +7717,7 @@ static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, max_bpc); bpp = convert_dc_color_depth_into_bpc(color_depth) * 3; clock = adjusted_mode->clock; - dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp << 4); + dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false); } dm_new_connector_state->vcpi_slots = diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 index d168a591bcd23..7261c98f40b18 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-calc-pbn-mode.m4 @@ -1,7 +1,10 @@ dnl # -dnl # commit 9a7c0da823fd4e65098bd466a996503cc8309c0e +dnl # commit v5.5-rc2-902-gdc48529fb14e dnl # drm/dp_mst: Add PBN calculation for DSC modes dnl # +dnl #v6.6-rc2-668-g7707dd602259 +dnl #drm/dp_mst: Fix fractional DSC bpp handling +dnl AC_DEFUN([AC_AMDGPU_DRM_DP_CALC_PBN_MODE], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ @@ -10,7 +13,7 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_CALC_PBN_MODE], [ drm_dp_calc_pbn_mode(0, 0, 0); ], [ AC_DEFINE(HAVE_DRM_DP_CALC_PBN_MODE_3ARGS, 1, - [drm_dp_calc_pbn_mode() wants 3args]) + [drm_dp_calc_pbn_mode() wants 3 args]) ]) ]) ]) diff --git a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h index c6de78678e856..9791910ed58b0 100644 --- a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h +++ b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h @@ -25,15 +25,20 @@ #include /* Copied from drivers/gpu/drm/drm_dp_mst_topology.c and modified for KCL */ -#if !defined(HAVE_DRM_DP_CALC_PBN_MODE_3ARGS) +#ifndef HAVE_DRM_DP_CALC_PBN_MODE_3ARGS static inline int _kcl_drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc) { +#ifndef HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H if (dsc) return DIV_ROUND_UP_ULL(mul_u32_u32(clock * (bpp / 16), 64 * 1006), 8 * 54 * 1000 * 1000); - - return drm_dp_calc_pbn_mode(clock, bpp); +#endif + return drm_dp_calc_pbn_mode(clock, bpp +#ifdef HAVE_DRM_DISPLAY_DRM_DP_MST_HELPER_H + << 4 +#endif + ); } #define drm_dp_calc_pbn_mode _kcl_drm_dp_calc_pbn_mode #endif From 2840882b0c513e5cf22b3b954c1e93fb2809fb5c Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 21 Dec 2023 16:14:20 +0800 Subject: [PATCH 1143/1868] drm/amdkcl: test struct drm_dp_mst_topology_state whether has union member pbn_div It's caused by v6.6-rc2-733-g191dc43935d1 drm/dp_mst: Store the MST PBN divider value in fixed point format Signed-off-by: Asher Song --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 11 +++++++---- .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 5 +++++ .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 12 ++++++++---- .../amd/dkms/m4/drm-dp-mst-topology-state.m4 | 19 +++++++++++++++---- 4 files changed, 35 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 06833f87d107c..d99d1250ef991 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -7683,7 +7683,7 @@ static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, const struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; struct drm_dp_mst_topology_mgr *mst_mgr; struct drm_dp_mst_port *mst_port; -#ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV +#if defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_INT) || defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_UNION) struct drm_dp_mst_topology_state *mst_state; #endif enum dc_color_depth color_depth; @@ -7699,12 +7699,15 @@ static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder, if (!crtc_state->connectors_changed && !crtc_state->mode_changed) return 0; -#ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV +#if defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_INT) || defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_UNION) mst_state = drm_atomic_get_mst_topology_state(state, mst_mgr); if (IS_ERR(mst_state)) return PTR_ERR(mst_state); - +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_UNION mst_state->pbn_div.full = dfixed_const(dm_mst_get_pbn_divider(aconnector->mst_root->dc_link)); +#else + mst_state->pbn_div = dm_mst_get_pbn_divider(aconnector->mst_root->dc_link); +#endif #endif if (!state->duplicated) { @@ -11816,7 +11819,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, struct drm_connector_list_iter iter; u8 link_coding_cap; -#ifndef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV +#if !defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_INT) && !defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_UNION) if (!mgr->mst_state ) continue; #endif diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index 0c480199d3bf7..fc314a96b302a 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -303,7 +303,12 @@ static void dm_helpers_construct_old_payload( struct drm_dp_mst_atomic_payload *old_payload) { struct drm_dp_mst_atomic_payload *pos; +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_UNION int pbn_per_slot = dfixed_trunc(mst_state->pbn_div); +#elif HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_INT + int pbn_per_slot = mst_state->pbn_div; +#endif + u8 next_payload_vc_start = mgr->next_start_slot; u8 payload_vc_start = new_payload->vc_start_slot; u8 allocated_time_slots; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 40d6f94250b71..2f4aecf1c1d42 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -1088,7 +1088,7 @@ static int increase_dsc_bpp(struct drm_atomic_state *state, int min_initial_slack; int next_index; int remaining_to_increase = 0; -#ifndef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV +#if !defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_INT) && !defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_UNION) int pbn_per_timeslot; #endif int link_timeslots_used; @@ -1096,7 +1096,7 @@ static int increase_dsc_bpp(struct drm_atomic_state *state, int ret = 0; uint16_t fec_overhead_multiplier_x1000 = get_fec_overhead_multiplier(dc_link); -#ifndef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV +#if !defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_INT) && !defined(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_UNION) pbn_per_timeslot = dm_mst_get_pbn_divider(dc_link); #endif @@ -1131,8 +1131,10 @@ static int increase_dsc_bpp(struct drm_atomic_state *state, for (i = 0; i < count; i++) link_timeslots_used += DIV_ROUND_UP(vars[i + k].pbn, -#ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_UNION dfixed_trunc(mst_state->pbn_div) +#elif HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_INT + mst_state->pbn_div #else pbn_per_timeslot #endif @@ -1140,8 +1142,10 @@ static int increase_dsc_bpp(struct drm_atomic_state *state, fair_pbn_alloc = (63 - link_timeslots_used) / remaining_to_increase * -#ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV +#ifdef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_UNION dfixed_trunc(mst_state->pbn_div); +#elif HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_INT + mst_state->pbn_div; #else pbn_per_timeslot; #endif diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 index 5ac79129a86fe..424778ea6606b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 @@ -44,14 +44,25 @@ dnl # AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV], [ AC_KERNEL_DO_BACKGROUND([ AC_KERNEL_TRY_COMPILE([ - #include + #include ], [ struct drm_dp_mst_topology_state * mst_state = NULL; - int pbn_div; - pbn_div = mst_state->pbn_div; + mst_state->pbn_div = 0; ], [ - AC_DEFINE(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV, 1, + AC_DEFINE(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_INT, 1, [struct drm_dp_mst_topology_state has member pbn_div]) + ]) + ]) + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + struct drm_dp_mst_topology_state * mst_state = NULL; + fixed20_12 pbn_div; + pbn_div = mst_state->pbn_div; + ], [ + AC_DEFINE(HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_UNION, 1, + [struct drm_dp_mst_topology_state has union member pbn_div]) ]) ]) ]) From 83b308d7c53a10fa3ccee97e914aa3d99636af4c Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 22 Dec 2023 10:50:30 +0800 Subject: [PATCH 1144/1868] drm/amdkcl: fake drm_WARN_ON It's caused by a78422e9dff366b3a46ae44caf6ec8ded9c9fc2f drm/sched: implement dynamic job-flow control Signed-off-by: Asher Song --- drivers/gpu/drm/scheduler/backport/backport.h | 1 + include/kcl/kcl_drm_print.h | 13 +++++++++++++ 2 files changed, 14 insertions(+) diff --git a/drivers/gpu/drm/scheduler/backport/backport.h b/drivers/gpu/drm/scheduler/backport/backport.h index 8b9c265bf8bce..04ad51ff373e2 100644 --- a/drivers/gpu/drm/scheduler/backport/backport.h +++ b/drivers/gpu/drm/scheduler/backport/backport.h @@ -9,4 +9,5 @@ #include #include #include +#include #endif diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index e2855aa2a299d..888592871d7ca 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -54,6 +54,19 @@ dev_name((drm)->dev), ## arg) #endif +#ifndef drm_WARN +#define drm_WARN(drm, condition, format, arg...) \ + WARN(condition, "%s %s: " format, \ + dev_driver_string((drm)->dev), \ + dev_name((drm)->dev), ## arg) +#endif + +#ifndef drm_WARN_ON +#define drm_WARN_ON(drm, x) \ + drm_WARN((drm), (x), "%s", \ + "drm_WARN_ON(" __stringify(x) ")") +#endif + #ifndef DRM_NOTE #define DRM_NOTE(fmt, ...) \ _DRM_PRINTK(, NOTICE, fmt, ##__VA_ARGS__) From 4a3cbd9231ef35f79674dfe32d8f451c7cecc445 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 25 Mar 2024 17:15:20 +0800 Subject: [PATCH 1145/1868] drm/amdkcl: fake queue_work_node It's caused by v6.7-rc1-196-gb0a7ce53d494 drm/ttm: Schedule delayed_delete worker closer Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/m4/cancel_work.m4 | 22 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 +- drivers/gpu/drm/ttm/backport/backport.h | 1 + include/kcl/backport/kcl_workqueue_backport.h | 10 +++++++++ 4 files changed, 34 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/cancel_work.m4 b/drivers/gpu/drm/amd/dkms/m4/cancel_work.m4 index 1f0558d0ade28..a9167fe9d15c0 100644 --- a/drivers/gpu/drm/amd/dkms/m4/cancel_work.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/cancel_work.m4 @@ -15,3 +15,25 @@ AC_DEFUN([AC_AMDGPU_CANCEL_WORK], [ ]) ]) ]) + +dnl # +dnl # commit id:v5.0-rc2-28-g8204e0c1113d +dnl # workqueue: Provide queue_work_node to queue work near a given NUMA node +dnl # +AC_DEFUN([AC_AMDGPU_QUEUE_WORK_NODE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ], [ + queue_work_node(0,NULL, NULL); + ], [queue_work_node], [kernel/workqueue.c], [ + AC_DEFINE(HAVE_QUEUE_WORK_NODE, 1, + [queue_work_node() is available]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_WORKQUEUE], [ + AC_AMDGPU_CANCEL_WORK + AC_AMDGPU_QUEUE_WORK_NODE +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 91cd90b9323c8..2cb4d0ea90f5e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -181,7 +181,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_X86_HYPERVISOR_TYPE AC_AMDGPU_HYPERVISOR_IS_TYPE AC_AMDGPU_PCI_DEV_LTR_PATH - AC_AMDGPU_CANCEL_WORK AC_AMDGPU_DMA_FENCE_IS_CONTAINER AC_AMDGPU_STR_YES_NO AC_AMDGPU_TOTALRAM_PAGES @@ -227,6 +226,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_VMA_IS_INITIAL AC_AMDGPU_CPUINFO_X86 AC_AMDGPU_DMA_FENCE_IS_LATER_OR_SAME + AC_AMDGPU_WORKQUEUE AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index e6cab104d2b34..032baf13deb03 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -19,5 +19,6 @@ #include #include #include +#include #endif diff --git a/include/kcl/backport/kcl_workqueue_backport.h b/include/kcl/backport/kcl_workqueue_backport.h index ac9ffbddd468c..db95877443f53 100644 --- a/include/kcl/backport/kcl_workqueue_backport.h +++ b/include/kcl/backport/kcl_workqueue_backport.h @@ -10,4 +10,14 @@ extern bool kcl_cancel_work(struct work_struct *work); #define cancel_work kcl_cancel_work #endif +/* Copied from kernel/workqueue.c and modified for KCL */ +#ifndef HAVE_QUEUE_WORK_NODE +static inline +bool _kcl_queue_work_node(int node, struct workqueue_struct *wq, + struct work_struct *work) +{ + return queue_work(wq, work); +} +#define queue_work_node _kcl_queue_work_node +#endif #endif /* KCL_LINUX_WORKQUEUE_BACKPORT_H */ From 158778f0091e153fc5a73d31281808492789a45a Mon Sep 17 00:00:00 2001 From: Asher Song Date: Sat, 23 Dec 2023 14:19:16 +0800 Subject: [PATCH 1146/1868] drm/amdkcl: test linux/units.h whether exists It's caused by v6.7-rc5-897-g18df969b44a0 drm/amd/pm: enable Wifi RFI mitigation feature support for SMU13.0.0 Signed-off-by: Asher Song --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 | 5 +++++ include/kcl/header/linux/units.h | 10 ++++++++++ include/kcl/kcl_units.h | 12 ++++++++++++ 4 files changed, 28 insertions(+) create mode 100644 include/kcl/header/linux/units.h create mode 100644 include/kcl/kcl_units.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index f82375d7f8f10..56f3b083e931b 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -120,4 +120,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 index 88fa953aa980a..4df530c27442c 100644 --- a/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/linux-headers.m4 @@ -134,4 +134,9 @@ AC_DEFUN([AC_AMDGPU_LINUX_HEADERS], [ dnl #platform/x86/amd: Add support for AMD ACPI based Wifi band RFI mitigation feature dnl AC_KERNEL_CHECK_HEADERS([linux/acpi_amd_wbrf.h]) + + dnl #v5.5-5479-g23331e489361 + dnl #include/linux/units.h: add helpers for kelvin to/from Celsius conversion + dnl + AC_KERNEL_CHECK_HEADERS([linux/units.h]) ]) diff --git a/include/kcl/header/linux/units.h b/include/kcl/header/linux/units.h new file mode 100644 index 0000000000000..228273e685fc1 --- /dev/null +++ b/include/kcl/header/linux/units.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +#ifndef _KCL_HEADER_LINUX_UNITS_H_H +#define _KCL_HEADER_LINUX_UNITS_H_H + +#ifdef HAVE_LINUX_UNITS_H +#include_next +#endif + +#endif + diff --git a/include/kcl/kcl_units.h b/include/kcl/kcl_units.h new file mode 100644 index 0000000000000..21d9f45fb1c5e --- /dev/null +++ b/include/kcl/kcl_units.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef KCL_KCL_LINUX_UNITS_H +#define KCL_KCL_LINUX_UNITS_H + +#include + +#ifndef HZ_PER_MHZ +#define HZ_PER_MHZ 1000000UL +#endif + +#endif + From 23a55595d5d8cc62dc6379731e4b8cd48a0edc4f Mon Sep 17 00:00:00 2001 From: Asher Song Date: Sat, 23 Dec 2023 16:16:43 +0800 Subject: [PATCH 1147/1868] drm/amdkcl: test whether drm_gem_object->resv whether exist It's caused by v6.7-rc3-500-gdfc03588cf8c drm/amd/display: Initialize writeback connector Signed-off-by: Asher Song --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c index 08c494a7a21ba..73f55ce4dee3d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c @@ -106,7 +106,7 @@ static int amdgpu_dm_wb_prepare_job(struct drm_writeback_connector *wb_connector return r; } - r = dma_resv_reserve_fences(rbo->tbo.base.resv, 1); + r = dma_resv_reserve_fences(amdkcl_ttm_resvp(&rbo->tbo), 1); if (r) { dev_err(adev->dev, "reserving fence slot failed (%d)\n", r); goto error_unlock; From 06b4308b7973d4ae59bc39e8af992aeecbe5a15f Mon Sep 17 00:00:00 2001 From: Asher Song Date: Sat, 23 Dec 2023 16:35:19 +0800 Subject: [PATCH 1148/1868] drm/amdkcl: wrap code under macro HAVE_DRM_CONNECTOR_HELPER_FUNCS_PREPARE_WRITEBACK_JOB It's caused by v6.7-rc3-500-gdfc03588cf8c drm/amd/display: Initialize writeback connector Signed-off-by: Asher Song --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c index 73f55ce4dee3d..14ddb3850582d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c @@ -80,6 +80,7 @@ static int amdgpu_dm_wb_connector_get_modes(struct drm_connector *connector) return drm_add_modes_noedid(connector, 3840, 2160); } +#ifdef HAVE_DRM_CONNECTOR_HELPER_FUNCS_PREPARE_WRITEBACK_JOB static int amdgpu_dm_wb_prepare_job(struct drm_writeback_connector *wb_connector, struct drm_writeback_job *job) { @@ -163,6 +164,7 @@ static void amdgpu_dm_wb_cleanup_job(struct drm_writeback_connector *connector, amdgpu_bo_unreserve(rbo); amdgpu_bo_unref(&rbo); } +#endif static const struct drm_encoder_helper_funcs amdgpu_dm_wb_encoder_helper_funcs = { .atomic_check = amdgpu_dm_wb_encoder_atomic_check, @@ -178,8 +180,10 @@ static const struct drm_connector_funcs amdgpu_dm_wb_connector_funcs = { static const struct drm_connector_helper_funcs amdgpu_dm_wb_conn_helper_funcs = { .get_modes = amdgpu_dm_wb_connector_get_modes, +#ifdef HAVE_DRM_CONNECTOR_HELPER_FUNCS_PREPARE_WRITEBACK_JOB .prepare_writeback_job = amdgpu_dm_wb_prepare_job, .cleanup_writeback_job = amdgpu_dm_wb_cleanup_job, +#endif }; int amdgpu_dm_wb_connector_init(struct amdgpu_display_manager *dm, From 7038ec9f4f38938c24b68a407e46d392ce9ccdfd Mon Sep 17 00:00:00 2001 From: Asher Song Date: Sat, 23 Dec 2023 20:02:46 +0800 Subject: [PATCH 1149/1868] drm/amdgpu: [hybrid] remove DRM_UNLOCKED flag This is caused by v6.7-rc3-559-g2798ffcc1d6a drm: Remove locking for legacy ioctls and DRM_UNLOCKED Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index a0a615e76984b..5dd5aa5ae5f25 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3000,7 +3000,7 @@ const struct drm_ioctl_desc amdgpu_ioctls_kms[] = { DRM_IOCTL_DEF_DRV(AMDGPU_GEM_OP, amdgpu_gem_op_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(AMDGPU_GEM_USERPTR, amdgpu_gem_userptr_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(AMDGPU_GEM_DGMA, amdgpu_gem_dgma_ioctl, DRM_AUTH|DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(AMDGPU_SEM, amdgpu_sem_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW) + DRM_IOCTL_DEF_DRV(AMDGPU_SEM, amdgpu_sem_ioctl, DRM_AUTH|DRM_RENDER_ALLOW) }; static struct drm_driver amdgpu_kms_driver = { From fd2f4201eee2d41136bf5d71d6a53ce4a1851d51 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Sun, 24 Dec 2023 11:12:29 +0800 Subject: [PATCH 1150/1868] drm/amdkcl: update config.h Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/config/config.h | 26 ++++++++++++++++++++---- 1 file changed, 22 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 0c31fb3b4882a..f3e1c08b0e895 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -130,6 +130,9 @@ /* dma_fence_is_container() is available */ #define HAVE_DMA_FENCE_IS_CONTAINER 1 +/* dma_fence_is_later_or_same() is available */ +#define HAVE_DMA_FENCE_IS_LATER_OR_SAME 1 + /* struct dma_fence_ops has callback set_deadline */ #define HAVE_DMA_FENCE_OPS_SET_DEADLINE 1 @@ -320,8 +323,8 @@ /* struct drm_dp_aux has member named 'drm_dev' */ #define HAVE_DRM_DP_AUX_DRM_DEV 1 -/* drm_dp_calc_pbn_mode() wants 3args */ -#define HAVE_DRM_DP_CALC_PBN_MODE_3ARGS 1 +/* drm_dp_calc_pbn_mode() wants 3 args */ +/* #undef HAVE_DRM_DP_CALC_PBN_MODE_3ARGS */ /* drm_dp_cec_register_connector() wants p,p interface */ #define HAVE_DRM_DP_CEC_REGISTER_CONNECTOR_PP 1 @@ -405,7 +408,10 @@ #define HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS 1 /* struct drm_dp_mst_topology_state has member pbn_div */ -#define HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV 1 +/* #undef HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_INT */ + +/* struct drm_dp_mst_topology_state has union member pbn_div */ +#define HAVE_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV_UNION 1 /* struct drm_dp_mst_topology_state has member total_avail_slots */ #define HAVE_DRM_DP_MST_TOPOLOGY_STATE_TOTAL_AVAIL_SLOTS 1 @@ -449,6 +455,9 @@ /* Define to 1 if you have the header file. */ /* #undef HAVE_DRM_DRM_BACKPORT_H */ +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_ELD_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_EXEC_H 1 @@ -757,6 +766,9 @@ /* kvrealloc() is available */ #define HAVE_KVREALLOC 1 +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_ACPI_AMD_WBRF_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_LINUX_APPLE_GMUX_H 1 @@ -832,6 +844,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_STDARG_H 1 +/* Define to 1 if you have the header file. */ +#define HAVE_LINUX_UNITS_H 1 + /* Define to 1 if you have the header file. */ #define HAVE_LINUX_XARRAY_H 1 @@ -934,6 +949,9 @@ /* pxm_to_node() is available */ #define HAVE_PXM_TO_NODE 1 +/* queue_work_node() is available */ +#define HAVE_QUEUE_WORK_NODE 1 + /* rb_add_cached is available */ #define HAVE_RB_ADD_CACHED 1 @@ -1119,7 +1137,7 @@ #define PACKAGE_NAME "amdgpu-dkms" /* Define to the full name and version of this package. */ -#define PACKAGE_STRING "amdgpu-dkms 6.5.0" +#define PACKAGE_STRING "amdgpu-dkms 6.7.0" /* Define to the one symbol short name of this package. */ #define PACKAGE_TARNAME "amdgpu-dkms" From daae8c05bbea22ea6fcfcc6959aaba93cb451d7f Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 28 Dec 2023 18:13:37 +0800 Subject: [PATCH 1151/1868] drm/amdkcl: add clang support Signed-off-by: Flora Cui --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 2cb4d0ea90f5e..f03dbfbef72e7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -434,10 +434,16 @@ AC_DEFUN([AC_KERNEL_COMPILE_MODULE_IFELSE], [ kbuild_src_flag='' kbuild_modpost_flag='KBUILD_MODPOST_NOFINAL=1 KBUILD_MODPOST_WARN=1' kbuild_workaround_flag='' + kbuild_cc='' + if test -s ${LINUX_OBJ}/.config; then + if grep -q 'CONFIG_CC_IS_CLANG=y' "${LINUX_OBJ}/.config"; then + kbuild_cc='CC=clang' + fi + fi test "x$enable_linux_builtin" = xyes && kbuild_src_flag='KBUILD_SRC=' # override KBUILD_SRC test "x$enable_linux_builtin" = xyes && kbuild_workaround_flag='sub_make_done=' # override sub_make_done AS_IF( - [AC_TRY_COMMAND(make [$2] -C $LINUX_OBJ EXTRA_CFLAGS="-Werror -Wno-error=array-bounds" M=$PWD $kbuild_src_flag $kbuild_workaround_flag $kbuild_modpost_flag) >/dev/null && AC_TRY_COMMAND([$3])], + [AC_TRY_COMMAND(make [$2] -C $LINUX_OBJ EXTRA_CFLAGS="-Werror -Wno-error=array-bounds" M=$PWD $kbuild_src_flag $kbuild_workaround_flag $kbuild_modpost_flag $kbuild_cc) >/dev/null && AC_TRY_COMMAND([$3])], [$4], [_AC_MSG_LOG_CONFTEST m4_ifvaln([$5],[$5])] ) From 9585afd9ad50f5e4c74306975c1a665c7dd4a646 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 4 Jan 2024 19:44:03 +0800 Subject: [PATCH 1152/1868] drm/amdkcl: initialize the variables in m4. Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/m4/highmem-internal.m4 | 2 +- drivers/gpu/drm/amd/dkms/m4/vmf_insert_pfn_prot.m4 | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/m4/highmem-internal.m4 b/drivers/gpu/drm/amd/dkms/m4/highmem-internal.m4 index 326a3fc8e64c4..4527ccd0a9659 100644 --- a/drivers/gpu/drm/amd/dkms/m4/highmem-internal.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/highmem-internal.m4 @@ -7,7 +7,7 @@ AC_DEFUN([AC_AMDGPU_KMAP_LOCAL], [ AC_KERNEL_TRY_COMPILE([ #include ], [ - pgprot_t prot; + pgprot_t prot = {0}; kmap_local_page_prot(NULL, prot); ], [ AC_DEFINE(HAVE_KMAP_LOCAL, 1, [kmap_local_* is available]) diff --git a/drivers/gpu/drm/amd/dkms/m4/vmf_insert_pfn_prot.m4 b/drivers/gpu/drm/amd/dkms/m4/vmf_insert_pfn_prot.m4 index d1f869507e4dd..192bb1767dda5 100644 --- a/drivers/gpu/drm/amd/dkms/m4/vmf_insert_pfn_prot.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/vmf_insert_pfn_prot.m4 @@ -8,7 +8,7 @@ AC_DEFUN([AC_AMDGPU_VMF_INSERT_PFN_PROT], [ #include #include ],[ - pgprot_t prot; + pgprot_t prot = {0}; vmf_insert_pfn_prot(NULL, 0, 0, prot); ],[ AC_DEFINE(HAVE_VMF_INSERT_PFN_PROT, @@ -23,7 +23,7 @@ AC_DEFUN([AC_AMDGPU_VMF_INSERT_PFN_PROT], [ #include #include ],[ - pgprot_t prot; + pgprot_t prot = {0}; vm_insert_pfn_prot(NULL, 0, 0, prot); ],[ AC_DEFINE(HAVE_VM_INSERT_PFN_PROT, From 63495243931fcb037d2488effa765ddf3eaca0d6 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 9 Jan 2024 13:32:34 +0800 Subject: [PATCH 1153/1868] drm/amdkcl: test whether dma_buf_is_dynamic() is available It's caused by 79e7fdec71f255c9961fae19619532bb4493742a "drm/amdgpu: Auto-validate DMABuf imports in compute VMs" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../gpu/drm/amd/dkms/m4/dma_buf_is_dynamic.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_dma-buf.h | 18 ++++++++++++++++++ 5 files changed, 39 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/dma_buf_is_dynamic.m4 create mode 100644 include/kcl/kcl_dma-buf.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 56f3b083e931b..e51f3d7932a86 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -121,4 +121,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index f3e1c08b0e895..8186552931858 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -109,6 +109,9 @@ /* dev_pm_set_driver_flags() is available */ #define HAVE_DEV_PM_SET_DRIVER_FLAGS 1 +/* dma_buf_is_dynamic() is available */ +#define HAVE_DMA_BUF_IS_DYNAMIC 1 + /* dma_buf->dynamic_mapping is available */ /* #undef HAVE_DMA_BUF_OPS_DYNAMIC_MAPPING */ diff --git a/drivers/gpu/drm/amd/dkms/m4/dma_buf_is_dynamic.m4 b/drivers/gpu/drm/amd/dkms/m4/dma_buf_is_dynamic.m4 new file mode 100644 index 0000000000000..0b5844f8c43dc --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/dma_buf_is_dynamic.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v5.4-rc4-863-g15fd552d186c +dnl # dma-buf: change DMA-buf locking convention v3 +dnl # +AC_DEFUN([AC_AMDGPU_DMA_BUF_IS_DYNAMIC], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + dma_buf_is_dynamic(NULL); + ],[ + AC_DEFINE(HAVE_DMA_BUF_IS_DYNAMIC, 1, + [dma_buf_is_dynamic() is available]) + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index f03dbfbef72e7..7e530e8780083 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -219,6 +219,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_LINUX_LOCAL_TRY_CMPXCHG AC_AMDGPU_LINUX_DEVICE_CLASS AC_AMDGPU_KVREALLOC + AC_AMDGPU_DMA_BUF_IS_DYNAMIC AC_AMDGPU_DRM_CLIENT_REGISTER AC_AMDGPU_DRM_DRIVER_GEM_PRIME_MMAP AC_AMDGPU_DRM_GEM_PRIME_HANDLE_TO_FD diff --git a/include/kcl/kcl_dma-buf.h b/include/kcl/kcl_dma-buf.h new file mode 100644 index 0000000000000..fe7094bc3071e --- /dev/null +++ b/include/kcl/kcl_dma-buf.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Pointer to dma-buf-mapped memory, plus helpers. + * Copied from include/kcl/dma-buf.h + */ +#ifndef _KCL_KCL__DMA_BUF_H__H__ +#define _KCL_KCL__DMA_BUF_H__H__ + +#include + +#ifndef HAVE_DMA_BUF_IS_DYNAMIC +static inline bool dma_buf_is_dynamic(struct dma_buf *dmabuf) +{ + return false; +} +#endif + +#endif \ No newline at end of file From f19d5a33adfc177a2665cae3faaf5eca72a0eb98 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 9 Jan 2024 11:36:56 +0800 Subject: [PATCH 1154/1868] drm/amdkcl: wrap code under amdkcl_ttm_resvp() It's caused by 79e7fdec71f255c9961fae19619532bb4493742a "drm/amdgpu: Auto-validate DMABuf imports in compute VMs" Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index b0b928445ca52..18833975bb043 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -528,7 +528,7 @@ int amdgpu_vm_validate(struct amdgpu_device *adev, struct amdgpu_vm *vm, bo = bo_base->bo; - if (dma_resv_locking_ctx(bo->tbo.base.resv) != ticket) { + if (dma_resv_locking_ctx(amdkcl_ttm_resvp(&bo->tbo)) != ticket) { struct amdgpu_task_info *ti = amdgpu_vm_get_task_info_vm(vm); pr_warn_ratelimited("Evicted user BO is not reserved\n"); From 9c4213b49d302aa2bb4f1bb847cb8b158f6f21d5 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 10 Jan 2024 14:01:23 +0800 Subject: [PATCH 1155/1868] drm/amdkcl: wrap code under macro DEFINE_DEBUGFS_ATTRIBUTE It's caused by 455b15748da59235d86edd764c0fcc35b71d6b69 "drm/amdgpu: add ACA bank dump debugfs support" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c index 929095a2e0886..fa8245f326a64 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c @@ -889,7 +889,11 @@ static const struct file_operations aca_ue_dump_debug_fops = { .release = single_release, }; +#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(aca_debug_mode_fops, NULL, amdgpu_aca_smu_debug_mode_set, "%llu\n"); +#else +DEFINE_SIMPLE_ATTRIBUTE(aca_debug_mode_fops, NULL, amdgpu_aca_smu_debug_mode_set, "%llu\n"); +#endif #endif void amdgpu_aca_smu_debugfs_init(struct amdgpu_device *adev, struct dentry *root) From cde3bd8f9db3d75bc48ef4bdd4db16629efe0f75 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 17 Jan 2024 14:07:56 +0800 Subject: [PATCH 1156/1868] drm/amdgpu: Synchronize after mapping into a compute VM Compute VMs use user mode queues for command submission. They cannot use a CS ioctl to synchronize with pending PTE updates and flush TLBs. Do this synchronization in amdgpu_gem_va_ioctl for compute VMs. Signed-off-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c index c2d3215463e8d..55f80f94e3926 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c @@ -782,10 +782,11 @@ int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data, * vital here, so they are not reported back to userspace. */ static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev, - struct amdgpu_vm *vm, + struct amdgpu_fpriv *fpriv, struct amdgpu_bo_va *bo_va, uint32_t operation) { + struct amdgpu_vm *vm = &fpriv->vm; int r; if (!amdgpu_vm_ready(vm)) @@ -803,6 +804,25 @@ static void amdgpu_gem_va_update_vm(struct amdgpu_device *adev, } r = amdgpu_vm_update_pdes(adev, vm, false); + if (r) + goto error; + + if (vm->is_compute_context) { + if (bo_va->last_pt_update) + r = dma_fence_wait(bo_va->last_pt_update, true); + if (!r && vm->last_update) + r = dma_fence_wait(vm->last_update, true); + if (!r) { + uint32_t xcc_mask = (!adev->xcp_mgr || + fpriv->xcp_id == ~0) ? 1 : + adev->xcp_mgr->xcp[fpriv->xcp_id] + .ip[AMDGPU_XCP_GFX].inst_mask; + + r = amdgpu_vm_flush_compute_tlb(adev, vm, + TLB_FLUSH_LEGACY, + xcc_mask); + } + } error: if (r && r != -ERESTARTSYS) @@ -970,7 +990,7 @@ int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data, break; } if (!r && !(args->flags & AMDGPU_VM_DELAY_UPDATE) && !adev->debug_vm) - amdgpu_gem_va_update_vm(adev, &fpriv->vm, bo_va, + amdgpu_gem_va_update_vm(adev, fpriv, bo_va, args->operation); error: From c31f759668cb45a30651fc2581816e8716e50682 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 18 Jan 2024 11:40:44 +0800 Subject: [PATCH 1157/1868] drm/amdgpu: update update_spm_vmid() param for non-upstream code It's caused by 3a260e1feaa636b3d718055a3259228fbd1d6bb4 "drm/amd/amdgpu: Update RLC_SPM_MC_CNT by ring wreg in guest" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c index 0d1007d6f146b..037e9aea2b691 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_rlc_spm.c @@ -66,7 +66,7 @@ int amdgpu_amdkfd_rlc_spm_acquire(struct amdgpu_device *adev, struct amdgpu_vm * } /* init spm vmid with 0x0 */ - adev->gfx.rlc.funcs->update_spm_vmid(adev, 0); + adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0); /* set spm ring registers */ spin_lock(&adev->gfx.kiq[0].ring_lock); @@ -95,7 +95,7 @@ void amdgpu_amdkfd_rlc_spm_release(struct amdgpu_device *adev, struct amdgpu_vm /* revert spm vmid with 0xf */ if (adev->gfx.rlc.funcs->update_spm_vmid) - adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf); + adev->gfx.rlc.funcs->update_spm_vmid(adev, NULL, 0xf); } void amdgpu_amdkfd_rlc_spm_interrupt(struct amdgpu_device *adev) From 7d7b68b22ca485b626d57fad8c771ebcc6a534c1 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 19 Jan 2024 14:47:53 +0800 Subject: [PATCH 1158/1868] drm/amdkcl: include fake drm_gem_object_put() for kcl_drm_exec.c In RHEL7.9, drm_gem_object_put will not check obj pointer that cause null point issue. So kcl_drm_exex.c need use fake drm_gem_object_put(). Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/amdkcl/kcl_drm_exec.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_exec.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_exec.c index 4bf8c653fa2f4..1ce1651265c24 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_exec.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_exec.c @@ -4,6 +4,7 @@ #include #include #include +#include #ifndef HAVE_DRM_DRM_EXEC_H /** From 617f60bb6b8502e15e327e8eefeda8ddb9e3dfa9 Mon Sep 17 00:00:00 2001 From: Hawking Zhang Date: Thu, 1 Feb 2024 15:06:27 +0800 Subject: [PATCH 1159/1868] Revert "drm/amdkfd: Fix sparse __rcu annotation warnings" This reverts commit bc98fce83f90bf1e2190a9351202ec1df1c2e45c. To resolve server rebooting issue observed while running rocGDB UT on MI100/MI200. Signed-off-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 4 ++-- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 7 ++----- 4 files changed, 6 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index ada20ca54dec5..41e6651f86a90 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -341,7 +341,7 @@ void amdgpu_amdkfd_gpuvm_unmap_gtt_bo_from_kernel(struct kgd_mem *mem); int amdgpu_amdkfd_map_gtt_bo_to_gart(struct amdgpu_bo *bo, struct amdgpu_bo **bo_gart); int amdgpu_amdkfd_gpuvm_restore_process_bos(void *process_info, - struct dma_fence __rcu **ef); + struct dma_fence **ef); int amdgpu_amdkfd_gpuvm_get_vm_fault_info(struct amdgpu_device *adev, struct kfd_vm_fault_info *info); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 03f45c099f22c..4faae9595da97 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -3275,7 +3275,7 @@ static void amdgpu_amdkfd_restore_userptr_worker(struct work_struct *work) put_task_struct(usertask); } -static void replace_eviction_fence(struct dma_fence __rcu **ef, +static void replace_eviction_fence(struct dma_fence **ef, struct dma_fence *new_ef) { struct dma_fence *old_ef = rcu_replace_pointer(*ef, new_ef, true @@ -3310,7 +3310,7 @@ static void replace_eviction_fence(struct dma_fence __rcu **ef, * 7. Add fence to all PD and PT BOs. * 8. Unreserve all BOs */ -int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence __rcu **ef) +int amdgpu_amdkfd_gpuvm_restore_process_bos(void *info, struct dma_fence **ef) { struct amdkfd_process_info *process_info = info; struct amdgpu_vm *peer_vm; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 11a44f24120b8..92fd00d0811f8 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -995,7 +995,7 @@ struct kfd_process { * fence will be triggered during eviction and new one will be created * during restore */ - struct dma_fence __rcu *ef; + struct dma_fence *ef; /* Work items for evicting and restoring BOs */ struct delayed_work eviction_work; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index af4848f0511fc..314c46aeafe54 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -1107,7 +1107,6 @@ static void kfd_process_wq_release(struct work_struct *work) { struct kfd_process *p = container_of(work, struct kfd_process, release_work); - struct dma_fence *ef; kfd_process_dequeue_from_all_devices(p); pqm_uninit(&p->pqm); @@ -1116,9 +1115,7 @@ static void kfd_process_wq_release(struct work_struct *work) * destroyed. This allows any BOs to be freed without * triggering pointless evictions or waiting for fences. */ - synchronize_rcu(); - ef = rcu_access_pointer(p->ef); - dma_fence_signal(ef); + dma_fence_signal(p->ef); kfd_process_remove_sysfs(p); @@ -1127,7 +1124,7 @@ static void kfd_process_wq_release(struct work_struct *work) svm_range_list_fini(p); kfd_process_destroy_pdds(p); - dma_fence_put(ef); + dma_fence_put(p->ef); kfd_event_free_process(p); From 822b50224edf9d5104ec82f7b1c748cbc361e8a8 Mon Sep 17 00:00:00 2001 From: Hawking Zhang Date: Tue, 6 Feb 2024 12:18:45 +0800 Subject: [PATCH 1160/1868] Revert "drm/amdkfd: Add cache line sizes to KFD topology" This reverts commit 559617656df0bce97a7570544684d4c185230aa8. The change causes transferbench, babelstream and hip catch2 test fail Signed-off-by: Hawking Zhang --- drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 93 +---------------------- drivers/gpu/drm/amd/amdkfd/kfd_crat.h | 1 - drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 2 - 3 files changed, 2 insertions(+), 94 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c index 6e1e8e4625221..dd37a8c173812 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c @@ -55,7 +55,6 @@ static struct kfd_gpu_cache_info kaveri_cache_info[] = { /* TCP L1 Cache per CU */ .cache_size = 16, .cache_level = 1, - .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -65,7 +64,6 @@ static struct kfd_gpu_cache_info kaveri_cache_info[] = { /* Scalar L1 Instruction Cache (in SQC module) per bank */ .cache_size = 16, .cache_level = 1, - .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_INST_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -75,7 +73,6 @@ static struct kfd_gpu_cache_info kaveri_cache_info[] = { /* Scalar L1 Data Cache (in SQC module) per bank */ .cache_size = 8, .cache_level = 1, - .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -91,7 +88,6 @@ static struct kfd_gpu_cache_info carrizo_cache_info[] = { /* TCP L1 Cache per CU */ .cache_size = 16, .cache_level = 1, - .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -99,9 +95,8 @@ static struct kfd_gpu_cache_info carrizo_cache_info[] = { }, { /* Scalar L1 Instruction Cache (in SQC module) per bank */ - .cache_size = 32, + .cache_size = 8, .cache_level = 1, - .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_INST_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -109,9 +104,8 @@ static struct kfd_gpu_cache_info carrizo_cache_info[] = { }, { /* Scalar L1 Data Cache (in SQC module) per bank. */ - .cache_size = 16, + .cache_size = 4, .cache_level = 1, - .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -141,7 +135,6 @@ static struct kfd_gpu_cache_info vega10_cache_info[] = { /* TCP L1 Cache per CU */ .cache_size = 16, .cache_level = 1, - .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -151,7 +144,6 @@ static struct kfd_gpu_cache_info vega10_cache_info[] = { /* Scalar L1 Instruction Cache per SQC */ .cache_size = 32, .cache_level = 1, - .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_INST_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -161,7 +153,6 @@ static struct kfd_gpu_cache_info vega10_cache_info[] = { /* Scalar L1 Data Cache per SQC */ .cache_size = 16, .cache_level = 1, - .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -171,7 +162,6 @@ static struct kfd_gpu_cache_info vega10_cache_info[] = { /* L2 Data Cache per GPU (Total Tex Cache) */ .cache_size = 4096, .cache_level = 2, - .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -184,7 +174,6 @@ static struct kfd_gpu_cache_info raven_cache_info[] = { /* TCP L1 Cache per CU */ .cache_size = 16, .cache_level = 1, - .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -194,7 +183,6 @@ static struct kfd_gpu_cache_info raven_cache_info[] = { /* Scalar L1 Instruction Cache per SQC */ .cache_size = 32, .cache_level = 1, - .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_INST_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -204,7 +192,6 @@ static struct kfd_gpu_cache_info raven_cache_info[] = { /* Scalar L1 Data Cache per SQC */ .cache_size = 16, .cache_level = 1, - .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -214,7 +201,6 @@ static struct kfd_gpu_cache_info raven_cache_info[] = { /* L2 Data Cache per GPU (Total Tex Cache) */ .cache_size = 1024, .cache_level = 2, - .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -227,7 +213,6 @@ static struct kfd_gpu_cache_info renoir_cache_info[] = { /* TCP L1 Cache per CU */ .cache_size = 16, .cache_level = 1, - .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -237,7 +222,6 @@ static struct kfd_gpu_cache_info renoir_cache_info[] = { /* Scalar L1 Instruction Cache per SQC */ .cache_size = 32, .cache_level = 1, - .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_INST_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -247,7 +231,6 @@ static struct kfd_gpu_cache_info renoir_cache_info[] = { /* Scalar L1 Data Cache per SQC */ .cache_size = 16, .cache_level = 1, - .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -257,7 +240,6 @@ static struct kfd_gpu_cache_info renoir_cache_info[] = { /* L2 Data Cache per GPU (Total Tex Cache) */ .cache_size = 1024, .cache_level = 2, - .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -270,7 +252,6 @@ static struct kfd_gpu_cache_info vega12_cache_info[] = { /* TCP L1 Cache per CU */ .cache_size = 16, .cache_level = 1, - .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -280,7 +261,6 @@ static struct kfd_gpu_cache_info vega12_cache_info[] = { /* Scalar L1 Instruction Cache per SQC */ .cache_size = 32, .cache_level = 1, - .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_INST_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -290,7 +270,6 @@ static struct kfd_gpu_cache_info vega12_cache_info[] = { /* Scalar L1 Data Cache per SQC */ .cache_size = 16, .cache_level = 1, - .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -300,7 +279,6 @@ static struct kfd_gpu_cache_info vega12_cache_info[] = { /* L2 Data Cache per GPU (Total Tex Cache) */ .cache_size = 2048, .cache_level = 2, - .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -313,7 +291,6 @@ static struct kfd_gpu_cache_info vega20_cache_info[] = { /* TCP L1 Cache per CU */ .cache_size = 16, .cache_level = 1, - .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -323,7 +300,6 @@ static struct kfd_gpu_cache_info vega20_cache_info[] = { /* Scalar L1 Instruction Cache per SQC */ .cache_size = 32, .cache_level = 1, - .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_INST_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -333,7 +309,6 @@ static struct kfd_gpu_cache_info vega20_cache_info[] = { /* Scalar L1 Data Cache per SQC */ .cache_size = 16, .cache_level = 1, - .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -343,7 +318,6 @@ static struct kfd_gpu_cache_info vega20_cache_info[] = { /* L2 Data Cache per GPU (Total Tex Cache) */ .cache_size = 8192, .cache_level = 2, - .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -356,7 +330,6 @@ static struct kfd_gpu_cache_info aldebaran_cache_info[] = { /* TCP L1 Cache per CU */ .cache_size = 16, .cache_level = 1, - .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -366,7 +339,6 @@ static struct kfd_gpu_cache_info aldebaran_cache_info[] = { /* Scalar L1 Instruction Cache per SQC */ .cache_size = 32, .cache_level = 1, - .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_INST_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -376,7 +348,6 @@ static struct kfd_gpu_cache_info aldebaran_cache_info[] = { /* Scalar L1 Data Cache per SQC */ .cache_size = 16, .cache_level = 1, - .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -386,7 +357,6 @@ static struct kfd_gpu_cache_info aldebaran_cache_info[] = { /* L2 Data Cache per GPU (Total Tex Cache) */ .cache_size = 8192, .cache_level = 2, - .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -399,7 +369,6 @@ static struct kfd_gpu_cache_info navi10_cache_info[] = { /* TCP L1 Cache per CU */ .cache_size = 16, .cache_level = 1, - .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -409,7 +378,6 @@ static struct kfd_gpu_cache_info navi10_cache_info[] = { /* Scalar L1 Instruction Cache per SQC */ .cache_size = 32, .cache_level = 1, - .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_INST_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -419,7 +387,6 @@ static struct kfd_gpu_cache_info navi10_cache_info[] = { /* Scalar L1 Data Cache per SQC */ .cache_size = 16, .cache_level = 1, - .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -429,7 +396,6 @@ static struct kfd_gpu_cache_info navi10_cache_info[] = { /* GL1 Data Cache per SA */ .cache_size = 128, .cache_level = 1, - .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -439,7 +405,6 @@ static struct kfd_gpu_cache_info navi10_cache_info[] = { /* L2 Data Cache per GPU (Total Tex Cache) */ .cache_size = 4096, .cache_level = 2, - .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -452,7 +417,6 @@ static struct kfd_gpu_cache_info vangogh_cache_info[] = { /* TCP L1 Cache per CU */ .cache_size = 16, .cache_level = 1, - .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -462,7 +426,6 @@ static struct kfd_gpu_cache_info vangogh_cache_info[] = { /* Scalar L1 Instruction Cache per SQC */ .cache_size = 32, .cache_level = 1, - .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_INST_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -472,7 +435,6 @@ static struct kfd_gpu_cache_info vangogh_cache_info[] = { /* Scalar L1 Data Cache per SQC */ .cache_size = 16, .cache_level = 1, - .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -482,7 +444,6 @@ static struct kfd_gpu_cache_info vangogh_cache_info[] = { /* GL1 Data Cache per SA */ .cache_size = 128, .cache_level = 1, - .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -492,7 +453,6 @@ static struct kfd_gpu_cache_info vangogh_cache_info[] = { /* L2 Data Cache per GPU (Total Tex Cache) */ .cache_size = 1024, .cache_level = 2, - .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -505,7 +465,6 @@ static struct kfd_gpu_cache_info navi14_cache_info[] = { /* TCP L1 Cache per CU */ .cache_size = 16, .cache_level = 1, - .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -515,7 +474,6 @@ static struct kfd_gpu_cache_info navi14_cache_info[] = { /* Scalar L1 Instruction Cache per SQC */ .cache_size = 32, .cache_level = 1, - .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_INST_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -525,7 +483,6 @@ static struct kfd_gpu_cache_info navi14_cache_info[] = { /* Scalar L1 Data Cache per SQC */ .cache_size = 16, .cache_level = 1, - .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -535,7 +492,6 @@ static struct kfd_gpu_cache_info navi14_cache_info[] = { /* GL1 Data Cache per SA */ .cache_size = 128, .cache_level = 1, - .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -545,7 +501,6 @@ static struct kfd_gpu_cache_info navi14_cache_info[] = { /* L2 Data Cache per GPU (Total Tex Cache) */ .cache_size = 2048, .cache_level = 2, - .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -558,7 +513,6 @@ static struct kfd_gpu_cache_info sienna_cichlid_cache_info[] = { /* TCP L1 Cache per CU */ .cache_size = 16, .cache_level = 1, - .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -568,7 +522,6 @@ static struct kfd_gpu_cache_info sienna_cichlid_cache_info[] = { /* Scalar L1 Instruction Cache per SQC */ .cache_size = 32, .cache_level = 1, - .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_INST_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -578,7 +531,6 @@ static struct kfd_gpu_cache_info sienna_cichlid_cache_info[] = { /* Scalar L1 Data Cache per SQC */ .cache_size = 16, .cache_level = 1, - .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -588,7 +540,6 @@ static struct kfd_gpu_cache_info sienna_cichlid_cache_info[] = { /* GL1 Data Cache per SA */ .cache_size = 128, .cache_level = 1, - .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -598,7 +549,6 @@ static struct kfd_gpu_cache_info sienna_cichlid_cache_info[] = { /* L2 Data Cache per GPU (Total Tex Cache) */ .cache_size = 4096, .cache_level = 2, - .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -608,7 +558,6 @@ static struct kfd_gpu_cache_info sienna_cichlid_cache_info[] = { /* L3 Data Cache per GPU */ .cache_size = 128*1024, .cache_level = 3, - .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -621,7 +570,6 @@ static struct kfd_gpu_cache_info navy_flounder_cache_info[] = { /* TCP L1 Cache per CU */ .cache_size = 16, .cache_level = 1, - .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -631,7 +579,6 @@ static struct kfd_gpu_cache_info navy_flounder_cache_info[] = { /* Scalar L1 Instruction Cache per SQC */ .cache_size = 32, .cache_level = 1, - .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_INST_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -641,7 +588,6 @@ static struct kfd_gpu_cache_info navy_flounder_cache_info[] = { /* Scalar L1 Data Cache per SQC */ .cache_size = 16, .cache_level = 1, - .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -651,7 +597,6 @@ static struct kfd_gpu_cache_info navy_flounder_cache_info[] = { /* GL1 Data Cache per SA */ .cache_size = 128, .cache_level = 1, - .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -661,7 +606,6 @@ static struct kfd_gpu_cache_info navy_flounder_cache_info[] = { /* L2 Data Cache per GPU (Total Tex Cache) */ .cache_size = 3072, .cache_level = 2, - .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -671,7 +615,6 @@ static struct kfd_gpu_cache_info navy_flounder_cache_info[] = { /* L3 Data Cache per GPU */ .cache_size = 96*1024, .cache_level = 3, - .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -684,7 +627,6 @@ static struct kfd_gpu_cache_info dimgrey_cavefish_cache_info[] = { /* TCP L1 Cache per CU */ .cache_size = 16, .cache_level = 1, - .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -694,7 +636,6 @@ static struct kfd_gpu_cache_info dimgrey_cavefish_cache_info[] = { /* Scalar L1 Instruction Cache per SQC */ .cache_size = 32, .cache_level = 1, - .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_INST_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -704,7 +645,6 @@ static struct kfd_gpu_cache_info dimgrey_cavefish_cache_info[] = { /* Scalar L1 Data Cache per SQC */ .cache_size = 16, .cache_level = 1, - .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -714,7 +654,6 @@ static struct kfd_gpu_cache_info dimgrey_cavefish_cache_info[] = { /* GL1 Data Cache per SA */ .cache_size = 128, .cache_level = 1, - .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -724,7 +663,6 @@ static struct kfd_gpu_cache_info dimgrey_cavefish_cache_info[] = { /* L2 Data Cache per GPU (Total Tex Cache) */ .cache_size = 2048, .cache_level = 2, - .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -734,7 +672,6 @@ static struct kfd_gpu_cache_info dimgrey_cavefish_cache_info[] = { /* L3 Data Cache per GPU */ .cache_size = 32*1024, .cache_level = 3, - .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -747,7 +684,6 @@ static struct kfd_gpu_cache_info beige_goby_cache_info[] = { /* TCP L1 Cache per CU */ .cache_size = 16, .cache_level = 1, - .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -757,7 +693,6 @@ static struct kfd_gpu_cache_info beige_goby_cache_info[] = { /* Scalar L1 Instruction Cache per SQC */ .cache_size = 32, .cache_level = 1, - .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_INST_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -767,7 +702,6 @@ static struct kfd_gpu_cache_info beige_goby_cache_info[] = { /* Scalar L1 Data Cache per SQC */ .cache_size = 16, .cache_level = 1, - .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -777,7 +711,6 @@ static struct kfd_gpu_cache_info beige_goby_cache_info[] = { /* GL1 Data Cache per SA */ .cache_size = 128, .cache_level = 1, - .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -787,7 +720,6 @@ static struct kfd_gpu_cache_info beige_goby_cache_info[] = { /* L2 Data Cache per GPU (Total Tex Cache) */ .cache_size = 1024, .cache_level = 2, - .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -797,7 +729,6 @@ static struct kfd_gpu_cache_info beige_goby_cache_info[] = { /* L3 Data Cache per GPU */ .cache_size = 16*1024, .cache_level = 3, - .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -810,7 +741,6 @@ static struct kfd_gpu_cache_info yellow_carp_cache_info[] = { /* TCP L1 Cache per CU */ .cache_size = 16, .cache_level = 1, - .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -820,7 +750,6 @@ static struct kfd_gpu_cache_info yellow_carp_cache_info[] = { /* Scalar L1 Instruction Cache per SQC */ .cache_size = 32, .cache_level = 1, - .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_INST_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -830,7 +759,6 @@ static struct kfd_gpu_cache_info yellow_carp_cache_info[] = { /* Scalar L1 Data Cache per SQC */ .cache_size = 16, .cache_level = 1, - .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -840,7 +768,6 @@ static struct kfd_gpu_cache_info yellow_carp_cache_info[] = { /* GL1 Data Cache per SA */ .cache_size = 128, .cache_level = 1, - .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -850,7 +777,6 @@ static struct kfd_gpu_cache_info yellow_carp_cache_info[] = { /* L2 Data Cache per GPU (Total Tex Cache) */ .cache_size = 2048, .cache_level = 2, - .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -863,7 +789,6 @@ static struct kfd_gpu_cache_info gfx1037_cache_info[] = { /* TCP L1 Cache per CU */ .cache_size = 16, .cache_level = 1, - .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -873,7 +798,6 @@ static struct kfd_gpu_cache_info gfx1037_cache_info[] = { /* Scalar L1 Instruction Cache per SQC */ .cache_size = 32, .cache_level = 1, - .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_INST_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -883,7 +807,6 @@ static struct kfd_gpu_cache_info gfx1037_cache_info[] = { /* Scalar L1 Data Cache per SQC */ .cache_size = 16, .cache_level = 1, - .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -893,7 +816,6 @@ static struct kfd_gpu_cache_info gfx1037_cache_info[] = { /* GL1 Data Cache per SA */ .cache_size = 128, .cache_level = 1, - .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -903,7 +825,6 @@ static struct kfd_gpu_cache_info gfx1037_cache_info[] = { /* L2 Data Cache per GPU (Total Tex Cache) */ .cache_size = 256, .cache_level = 2, - .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -916,7 +837,6 @@ static struct kfd_gpu_cache_info gc_10_3_6_cache_info[] = { /* TCP L1 Cache per CU */ .cache_size = 16, .cache_level = 1, - .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -926,7 +846,6 @@ static struct kfd_gpu_cache_info gc_10_3_6_cache_info[] = { /* Scalar L1 Instruction Cache per SQC */ .cache_size = 32, .cache_level = 1, - .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_INST_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -936,7 +855,6 @@ static struct kfd_gpu_cache_info gc_10_3_6_cache_info[] = { /* Scalar L1 Data Cache per SQC */ .cache_size = 16, .cache_level = 1, - .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -946,7 +864,6 @@ static struct kfd_gpu_cache_info gc_10_3_6_cache_info[] = { /* GL1 Data Cache per SA */ .cache_size = 128, .cache_level = 1, - .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -956,7 +873,6 @@ static struct kfd_gpu_cache_info gc_10_3_6_cache_info[] = { /* L2 Data Cache per GPU (Total Tex Cache) */ .cache_size = 256, .cache_level = 2, - .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -969,7 +885,6 @@ static struct kfd_gpu_cache_info dummy_cache_info[] = { /* TCP L1 Cache per CU */ .cache_size = 16, .cache_level = 1, - .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -979,7 +894,6 @@ static struct kfd_gpu_cache_info dummy_cache_info[] = { /* Scalar L1 Instruction Cache per SQC */ .cache_size = 32, .cache_level = 1, - .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_INST_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -989,7 +903,6 @@ static struct kfd_gpu_cache_info dummy_cache_info[] = { /* Scalar L1 Data Cache per SQC */ .cache_size = 16, .cache_level = 1, - .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -999,7 +912,6 @@ static struct kfd_gpu_cache_info dummy_cache_info[] = { /* GL1 Data Cache per SA */ .cache_size = 128, .cache_level = 1, - .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -1009,7 +921,6 @@ static struct kfd_gpu_cache_info dummy_cache_info[] = { /* L2 Data Cache per GPU (Total Tex Cache) */ .cache_size = 2048, .cache_level = 2, - .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.h b/drivers/gpu/drm/amd/amdkfd/kfd_crat.h index a8ca7ecb6d271..2f54ee08f2696 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.h @@ -301,7 +301,6 @@ struct kfd_node; struct kfd_gpu_cache_info { uint32_t cache_size; uint32_t cache_level; - uint32_t cache_line_size; uint32_t flags; /* Indicates how many Compute Units share this cache * within a SA. Value = 1 indicates the cache is not shared diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index 763ce65a441a8..c885b0576e1c5 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -1729,7 +1729,6 @@ static int fill_in_l1_pcache(struct kfd_cache_properties **props_ext, pcache->processor_id_low = cu_processor_id + (first_active_cu - 1); pcache->cache_level = pcache_info[cache_type].cache_level; pcache->cache_size = pcache_info[cache_type].cache_size; - pcache->cacheline_size = pcache_info[cache_type].cache_line_size; if (pcache_info[cache_type].flags & CRAT_CACHE_FLAGS_DATA_CACHE) pcache->cache_type |= HSA_CACHE_TYPE_DATA; @@ -1798,7 +1797,6 @@ static int fill_in_l2_l3_pcache(struct kfd_cache_properties **props_ext, pcache->processor_id_low = cu_processor_id + (first_active_cu - 1); pcache->cache_level = pcache_info[cache_type].cache_level; - pcache->cacheline_size = pcache_info[cache_type].cache_line_size; if (KFD_GC_VERSION(knode) == IP_VERSION(9, 4, 3) || KFD_GC_VERSION(knode) == IP_VERSION(9, 4, 4)) From 6f428512f3ce0f3d66e216851c9df29ebd780dad Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 6 Feb 2024 19:14:59 +0800 Subject: [PATCH 1161/1868] drm/amdkcl: export drm_gem_prime_handle_to_fd and drm_gem_prime_fd_to_handle On rhel9.4 which using kernel 6.4, drm_gem_prime_handle_to_fd and drm_gem_prime_fd_to_handle are unexported, so export it. It's caused by v6.4-rc7-1904-g71a7974ac701 drm/prime: Unexport helpers for fd/handle conversion eec9e451b drm/amdkfd: Export DMABufs from KFD using GEM handles Signed-off-by: Asher Song Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 6 ----- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_drm_prime.c | 28 ++++++++++++++++++++++ drivers/gpu/drm/amd/amdkcl/main.c | 2 ++ include/kcl/backport/kcl_drm_prime.h | 13 ++++++++++ 5 files changed, 44 insertions(+), 7 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_prime.c diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 5dd5aa5ae5f25..cd95055f5b7c0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -3055,12 +3055,8 @@ static struct drm_driver amdgpu_kms_driver = { .show_fdinfo = amdgpu_show_fdinfo, #endif #endif - -#ifdef HAVE_DRM_GEM_PRIME_HANDLE_TO_FD .prime_handle_to_fd = drm_gem_prime_handle_to_fd, .prime_fd_to_handle = drm_gem_prime_fd_to_handle, -#endif - #ifdef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK .gem_prime_export = amdgpu_gem_prime_export, #endif @@ -3114,10 +3110,8 @@ const struct drm_driver amdgpu_partition_driver = { .fops = &amdgpu_driver_kms_fops, .release = &amdgpu_driver_release_kms, -#ifdef HAVE_DRM_GEM_PRIME_HANDLE_TO_FD .prime_handle_to_fd = drm_gem_prime_handle_to_fd, .prime_fd_to_handle = drm_gem_prime_fd_to_handle, -#endif .gem_prime_import = amdgpu_gem_prime_import, #ifdef HAVE_DRM_DRIVER_GEM_PRIME_MMAP .gem_prime_mmap = drm_gem_prime_mmap, diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index d5a8a1db57bac..82abb89903b8c 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -14,7 +14,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_fs_read_write.o kcl_drm_aperture.o \ kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o \ kcl_mce_amd.o kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o kcl_mm_slab.o \ - kcl_irqdesc.o kcl_drm_suballoc.o kcl_drm_file.o kcl_drm_exec.o kcl_drm_dp_helper.o + kcl_irqdesc.o kcl_drm_suballoc.o kcl_drm_file.o kcl_drm_exec.o kcl_drm_dp_helper.o kcl_drm_prime.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_prime.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_prime.c new file mode 100644 index 0000000000000..36ca9dec40c2b --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_prime.c @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * driver/drm/drm_prime.c + * + * Copyright (C) 1991, 1992 Linus Torvalds + */ +#include + +#ifndef HAVE_DRM_GEM_PRIME_HANDLE_TO_FD +int (*_kcl_drm_gem_prime_handle_to_fd)(struct drm_device *dev, + struct drm_file *file_priv, uint32_t handle, + uint32_t flags, + int *prime_fd); +EXPORT_SYMBOL(_kcl_drm_gem_prime_handle_to_fd); + +int (*_kcl_drm_gem_prime_fd_to_handle)(struct drm_device *dev, + struct drm_file *file_priv, int prime_fd, + uint32_t *handle); +EXPORT_SYMBOL(_kcl_drm_gem_prime_fd_to_handle); +#endif + +void amdkcl_prime_init(void) +{ +#ifndef HAVE_DRM_GEM_PRIME_HANDLE_TO_FD + _kcl_drm_gem_prime_handle_to_fd = amdkcl_fp_setup("drm_gem_prime_handle_to_fd", NULL); + _kcl_drm_gem_prime_fd_to_handle = amdkcl_fp_setup("drm_gem_prime_fd_to_handle", NULL); +#endif +} diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c index d33b1db010e1a..7ede3a4fa2a6f 100644 --- a/drivers/gpu/drm/amd/amdkcl/main.c +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -12,6 +12,7 @@ extern void amdkcl_suspend_init(void); extern void amdkcl_sched_init(void); extern void amdkcl_numa_init(void); extern void amdkcl_workqueue_init(void); +extern void amdkcl_prime_init(void); int __init amdkcl_init(void) { @@ -25,6 +26,7 @@ int __init amdkcl_init(void) amdkcl_sched_init(); amdkcl_numa_init(); amdkcl_workqueue_init(); + amdkcl_prime_init(); return 0; } diff --git a/include/kcl/backport/kcl_drm_prime.h b/include/kcl/backport/kcl_drm_prime.h index 33187c1891d71..de796e551b712 100644 --- a/include/kcl/backport/kcl_drm_prime.h +++ b/include/kcl/backport/kcl_drm_prime.h @@ -50,4 +50,17 @@ struct sg_table *_kcl_drm_prime_pages_to_sg(struct drm_device *dev, #define drm_prime_pages_to_sg _kcl_drm_prime_pages_to_sg #endif +#ifndef HAVE_DRM_GEM_PRIME_HANDLE_TO_FD +int _kcl_drm_gem_prime_handle_to_fd(struct drm_device *dev, + struct drm_file *file_priv, uint32_t handle, + uint32_t flags, + int *prime_fd); +#define drm_gem_prime_handle_to_fd _kcl_drm_gem_prime_handle_to_fd + +int _kcl_drm_gem_prime_fd_to_handle(struct drm_device *dev, + struct drm_file *file_priv, int prime_fd, + uint32_t *handle); +#define drm_gem_prime_fd_to_handle _kcl_drm_gem_prime_fd_to_handle +#endif + #endif From 3de9630e8ae1f1cd9418c32089acefde248369dd Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 26 Feb 2024 21:24:54 +0800 Subject: [PATCH 1162/1868] drm/amdkcl: Check MAX_ORDER whether defined It's caused by 5e0a760b44417f7cadd79de2204d6247109558a0 mm, treewide: rename MAX_ORDER to MAX_PAGE_ORDER On kernel 6.8, macro MAX_ORDER is renamed to MAX_PAGE_ORDER. Signed-off-by: Asher Song Reviewed-by: Leslie Shi Reviewed-by: Flora Cui Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/ttm/backport/backport.h | 1 + include/kcl/kcl_drm_exec.h | 1 + include/kcl/kcl_mmzone.h | 21 +++++++++++++++++++++ 4 files changed, 24 insertions(+) create mode 100644 include/kcl/kcl_mmzone.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index e51f3d7932a86..a7011ba5a34a6 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -66,6 +66,7 @@ #include #include #include +#include #include "kcl/kcl_amdgpu_drm_fb_helper.h" #include "kcl/kcl_amdgpu.h" #include "kcl/kcl_amdgpu_drm_drv.h" diff --git a/drivers/gpu/drm/ttm/backport/backport.h b/drivers/gpu/drm/ttm/backport/backport.h index 032baf13deb03..f9e3e75824090 100644 --- a/drivers/gpu/drm/ttm/backport/backport.h +++ b/drivers/gpu/drm/ttm/backport/backport.h @@ -20,5 +20,6 @@ #include #include #include +#include #endif diff --git a/include/kcl/kcl_drm_exec.h b/include/kcl/kcl_drm_exec.h index 8a3f47f0520f6..2ffba4ce2fef7 100644 --- a/include/kcl/kcl_drm_exec.h +++ b/include/kcl/kcl_drm_exec.h @@ -13,6 +13,7 @@ #endif #ifndef HAVE_DRM_DRM_EXEC_H #include +#include #include #define DRM_EXEC_INTERRUPTIBLE_WAIT BIT(0) #define DRM_EXEC_IGNORE_DUPLICATES BIT(1) diff --git a/include/kcl/kcl_mmzone.h b/include/kcl/kcl_mmzone.h new file mode 100644 index 0000000000000..7cd5ea05d5af8 --- /dev/null +++ b/include/kcl/kcl_mmzone.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _KCL_MMZONE_H +#define _KCL_MMZONE_H + +#include + +#ifndef __ASSEMBLY__ +#ifndef __GENERATING_BOUNDS_H + +#ifndef MAX_PAGE_ORDER +#define MAX_PAGE_ORDER MAX_ORDER +#endif + +#ifndef NR_PAGE_ORDERS +#define NR_PAGE_ORDERS (MAX_PAGE_ORDER + 1) +#endif + +#endif +#endif + +#endif From 7104a6d4596e17606a4e1fda4f574e7826b388b0 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 27 Feb 2024 12:22:07 +0800 Subject: [PATCH 1163/1868] drm/amdkcl: test drm_exec_init whether has three arguments It's caused by 05d249352f1ae909230c230767ca8f4e9fdf8e7b drm/exec: Pass in initial # of objects On kenrel 6.8, drm_exec_init has three arguments. Signed-off-by: Asher Song Reviewed-by: Leslie Shi Reviewed-by: Ma Jun --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 8 ++------ drivers/gpu/drm/amd/dkms/m4/drm-exec.m4 | 20 ++++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/backport/kcl_drm_exec.h | 18 ++++++++++++++++++ 5 files changed, 42 insertions(+), 6 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-exec.m4 create mode 100644 include/kcl/backport/kcl_drm_exec.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index a7011ba5a34a6..70898b45f1388 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -123,4 +123,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 8186552931858..77e80cd5ee5cc 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -506,12 +506,8 @@ /* drm_edid_override_connector_update() is available */ #define HAVE_DRM_EDID_OVERRIDE_CONNECTOR_UPDATE 1 -/* drm_fb_helper_single_add_all_connectors() && - drm_fb_helper_remove_one_connector() are symbol */ -/* #undef HAVE_DRM_FB_HELPER_ADD_REMOVE_CONNECTORS */ - -/* drm_fb_helper_alloc_info() is available */ -#define HAVE_DRM_FB_HELPER_ALLOC_INFO 1 +/* drm_exec() has 3 arguments */ +#define HAVE_DRM_EXEC_INIT_3_ARGUMENTS /* drm_fb_helper_fill_info() is available */ #define HAVE_DRM_FB_HELPER_FILL_INFO 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-exec.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-exec.m4 new file mode 100644 index 0000000000000..b481cf6b7945e --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-exec.m4 @@ -0,0 +1,20 @@ +dnl # +dnl # commit 05d249352f1ae909230c230767ca8f4e9fdf8e7b +dnl # drm/exec: Pass in initial # of objects +dnl # +AC_DEFUN([AC_AMDGPU_DRM_EXEC_INIT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_exec_init(NULL, 0, 0); + ], [ + AC_DEFINE(HAVE_DRM_EXEC_INIT_3_ARGUMENTS, 1, + [drm_exec() has 3 arguments]) + ]) + ]) +]) + +AC_DEFUN([AC_AMDGPU_DRM_EXEC], [ + AC_AMDGPU_DRM_EXEC_INIT +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 7e530e8780083..331ffdd6d037d 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -228,6 +228,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_CPUINFO_X86 AC_AMDGPU_DMA_FENCE_IS_LATER_OR_SAME AC_AMDGPU_WORKQUEUE + AC_AMDGPU_DRM_EXEC_INIT AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/backport/kcl_drm_exec.h b/include/kcl/backport/kcl_drm_exec.h new file mode 100644 index 0000000000000..0d86a455cabdc --- /dev/null +++ b/include/kcl/backport/kcl_drm_exec.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef AMDKCL_BACKPORT_KCL_DRM_EXEC_H +#define AMDKCL_BACKPORT_KCL_DRM_EXEC_H + +#include +#include + +#ifndef HAVE_DRM_EXEC_INIT_3_ARGUMENTS +static inline +void _kcl_drm_exec_init(struct drm_exec *exec, uint32_t flags, unsigned nr) +{ + return drm_exec_init(exec, flags); +} + +#define drm_exec_init _kcl_drm_exec_init +#endif /* HAVE_DRM_EXEC_INIT_3_ARGUMENTS */ + +#endif From aeb39df452b57f708c91bd807228dc4a7e9198be Mon Sep 17 00:00:00 2001 From: David Yat Sin Date: Fri, 21 Jul 2023 11:16:56 -0400 Subject: [PATCH 1164/1868] drm/amdkfd/kfd_ioctl: add pc sampling support Add pc sampling support in kfd_ioctl. The user mode code which uses this new kfd_ioctl is linked to https://github.com/RadeonOpenCompute/ROCT-Thunk-Interface with master branch. Co-developed-by: James Zhu Signed-off-by: James Zhu Signed-off-by: David Yat Sin Tested-by: Vladimir Indic --- include/uapi/linux/kfd_ioctl.h | 61 +++++++++++++++++++++++++++++++++- 1 file changed, 60 insertions(+), 1 deletion(-) diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h index 13950b2930d8c..9798594ea3f37 100644 --- a/include/uapi/linux/kfd_ioctl.h +++ b/include/uapi/linux/kfd_ioctl.h @@ -1583,6 +1583,62 @@ struct kfd_ioctl_dbg_trap_args { }; }; +/** + * kfd_ioctl_pc_sample_op - PC Sampling ioctl operations + * + * @KFD_IOCTL_PCS_OP_QUERY_CAPABILITIES: Query device PC Sampling capabilities + * @KFD_IOCTL_PCS_OP_CREATE: Register this process with a per-device PC sampler instance + * @KFD_IOCTL_PCS_OP_DESTROY: Unregister from a previously registered PC sampler instance + * @KFD_IOCTL_PCS_OP_START: Process begins taking samples from a previously registered PC sampler instance + * @KFD_IOCTL_PCS_OP_STOP: Process stops taking samples from a previously registered PC sampler instance + */ +enum kfd_ioctl_pc_sample_op { + KFD_IOCTL_PCS_OP_QUERY_CAPABILITIES, + KFD_IOCTL_PCS_OP_CREATE, + KFD_IOCTL_PCS_OP_DESTROY, + KFD_IOCTL_PCS_OP_START, + KFD_IOCTL_PCS_OP_STOP, +}; + +/* Values have to be a power of 2*/ +#define KFD_IOCTL_PCS_FLAG_POWER_OF_2 0x00000001 + +enum kfd_ioctl_pc_sample_method { + KFD_IOCTL_PCS_METHOD_HOSTTRAP = 1, + KFD_IOCTL_PCS_METHOD_STOCHASTIC, +}; + +enum kfd_ioctl_pc_sample_type { + KFD_IOCTL_PCS_TYPE_TIME_US, + KFD_IOCTL_PCS_TYPE_CLOCK_CYCLES, + KFD_IOCTL_PCS_TYPE_INSTRUCTIONS +}; + +struct kfd_pc_sample_info { + __u64 interval; /* [IN] if PCS_TYPE_INTERVAL_US: sample interval in us + * if PCS_TYPE_CLOCK_CYCLES: sample interval in graphics core clk cycles + * if PCS_TYPE_INSTRUCTIONS: sample interval in instructions issued by + * graphics compute units + */ + __u64 interval_min; /* [OUT] */ + __u64 interval_max; /* [OUT] */ + __u64 flags; /* [OUT] indicate potential restrictions e.g FLAG_POWER_OF_2 */ + __u32 method; /* [IN/OUT] kfd_ioctl_pc_sample_method */ + __u32 type; /* [IN/OUT] kfd_ioctl_pc_sample_type */ +}; + +#define KFD_IOCTL_PCS_QUERY_TYPE_FULL (1 << 0) /* If not set, return current */ + +struct kfd_ioctl_pc_sample_args { + __u64 sample_info_ptr; /* array of kfd_pc_sample_info */ + __u32 num_sample_info; + __u32 op; /* kfd_ioctl_pc_sample_op */ + __u32 gpu_id; + __u32 trace_id; + __u32 flags; /* kfd_ioctl_pcs_query flags */ + __u32 reserved; +}; + #define AMDKFD_IOCTL_BASE 'K' #define AMDKFD_IO(nr) _IO(AMDKFD_IOCTL_BASE, nr) #define AMDKFD_IOR(nr, type) _IOR(AMDKFD_IOCTL_BASE, nr, type) @@ -1722,7 +1778,10 @@ struct kfd_ioctl_dbg_trap_args { #define AMDKFD_IOC_RLC_SPM \ AMDKFD_IOWR(0x84, struct kfd_ioctl_spm_args) +#define AMDKFD_IOC_PC_SAMPLE \ + AMDKFD_IOWR(0x85, struct kfd_ioctl_pc_sample_args) + #define AMDKFD_COMMAND_START_2 0x80 -#define AMDKFD_COMMAND_END_2 0x85 +#define AMDKFD_COMMAND_END_2 0x86 #endif From fccc004d0b985d118db5829db0761300ed78c3a5 Mon Sep 17 00:00:00 2001 From: David Yat Sin Date: Fri, 21 Jul 2023 12:09:14 -0400 Subject: [PATCH 1165/1868] drm/amdkfd: add pc sampling support Add pc sampling functions in amdkfd. Co-developed-by: James Zhu Signed-off-by: James Zhu Signed-off-by: David Yat Sin Tested-by: Vladimir Indic --- drivers/gpu/drm/amd/amdkfd/Makefile | 3 +- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 46 ++++++++++++ drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 78 ++++++++++++++++++++ drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.h | 34 +++++++++ drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 13 ++++ 5 files changed, 173 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c create mode 100644 drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.h diff --git a/drivers/gpu/drm/amd/amdkfd/Makefile b/drivers/gpu/drm/amd/amdkfd/Makefile index a0e88355c1e12..ede9e5afa301d 100644 --- a/drivers/gpu/drm/amd/amdkfd/Makefile +++ b/drivers/gpu/drm/amd/amdkfd/Makefile @@ -63,7 +63,8 @@ AMDKFD_FILES := $(AMDKFD_PATH)/kfd_module.o \ $(AMDKFD_PATH)/kfd_ipc.o \ $(AMDKFD_PATH)/kfd_trace.o \ $(AMDKFD_PATH)/kfd_spm.o \ - $(AMDKFD_PATH)/kfd_debug.o + $(AMDKFD_PATH)/kfd_debug.o \ + $(AMDKFD_PATH)/kfd_pc_sampling.o ifneq ($(CONFIG_DEBUG_FS),) AMDKFD_FILES += $(AMDKFD_PATH)/kfd_debugfs.o diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 557486b82559a..eb6e461f968b0 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -43,6 +43,7 @@ #include "kfd_svm.h" #include "kfd_ipc.h" #include "kfd_trace.h" +#include "kfd_pc_sampling.h" #include "amdgpu_amdkfd.h" #include "kfd_smi_events.h" @@ -1842,6 +1843,39 @@ static int kfd_ioctl_rlc_spm(struct file *filep, return kfd_rlc_spm(p, data); } +static int kfd_ioctl_pc_sample(struct file *filep, + struct kfd_process *p, void __user *data) +{ + struct kfd_ioctl_pc_sample_args *args = data; + struct kfd_process_device *pdd; + int ret = 0; + + if (sched_policy == KFD_SCHED_POLICY_NO_HWS) { + pr_err("PC Sampling does not support sched_policy %i", sched_policy); + return -EINVAL; + } + + mutex_lock(&p->mutex); + pdd = kfd_process_device_data_by_id(p, args->gpu_id); + + if (!pdd) { + pr_debug("could not find gpu id 0x%x.", args->gpu_id); + ret = -EINVAL; + } else if (args->op == KFD_IOCTL_PCS_OP_START) { + pdd = kfd_bind_process_to_device(pdd->dev, p); + if (IS_ERR(pdd)) { + pr_debug("failed to bind process %p with gpu id 0x%x", p, args->gpu_id); + ret = -ESRCH; + } + } + + if (!ret) + ret = kfd_pc_sample(pdd, args); + mutex_unlock(&p->mutex); + + return ret; +} + static int criu_checkpoint_process(struct kfd_process *p, uint8_t __user *user_priv_data, uint64_t *priv_offset) @@ -3440,6 +3474,10 @@ static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = { AMDKFD_IOCTL_DEF(AMDKFD_IOC_CROSS_MEMORY_COPY_DEPRECATED, kfd_ioctl_cross_memory_copy_deprecated, 0), + + /* TODO: KFD_IOC_FLAG_PERFMON is not required for host-trap, disable first */ + AMDKFD_IOCTL_DEF(AMDKFD_IOC_PC_SAMPLE, + kfd_ioctl_pc_sample, 0), }; static long kfd_ioctl(struct file *filep, unsigned int cmd, unsigned long arg) @@ -3512,6 +3550,14 @@ static long kfd_ioctl(struct file *filep, unsigned int cmd, unsigned long arg) } } + /* PC Sampling Monitor */ + if (unlikely(ioctl->flags & KFD_IOC_FLAG_PERFMON)) { + if (!capable(CAP_PERFMON) && !capable(CAP_SYS_ADMIN)) { + retcode = -EACCES; + goto err_i1; + } + } + if (cmd & (IOC_IN | IOC_OUT)) { if (asize <= sizeof(stack_kdata)) { kdata = stack_kdata; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c new file mode 100644 index 0000000000000..a7e78ff42d079 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -0,0 +1,78 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright 2023 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "kfd_priv.h" +#include "amdgpu_amdkfd.h" +#include "kfd_pc_sampling.h" + +static int kfd_pc_sample_query_cap(struct kfd_process_device *pdd, + struct kfd_ioctl_pc_sample_args __user *user_args) +{ + return -EINVAL; +} + +static int kfd_pc_sample_start(struct kfd_process_device *pdd) +{ + return -EINVAL; +} + +static int kfd_pc_sample_stop(struct kfd_process_device *pdd) +{ + return -EINVAL; + +} + +static int kfd_pc_sample_create(struct kfd_process_device *pdd, + struct kfd_ioctl_pc_sample_args __user *user_args) +{ + return -EINVAL; +} + +static int kfd_pc_sample_destroy(struct kfd_process_device *pdd, uint32_t trace_id) +{ + return -EINVAL; + +} + +int kfd_pc_sample(struct kfd_process_device *pdd, + struct kfd_ioctl_pc_sample_args __user *args) +{ + switch (args->op) { + case KFD_IOCTL_PCS_OP_QUERY_CAPABILITIES: + return kfd_pc_sample_query_cap(pdd, args); + + case KFD_IOCTL_PCS_OP_CREATE: + return kfd_pc_sample_create(pdd, args); + + case KFD_IOCTL_PCS_OP_DESTROY: + return kfd_pc_sample_destroy(pdd, args->trace_id); + + case KFD_IOCTL_PCS_OP_START: + return kfd_pc_sample_start(pdd); + + case KFD_IOCTL_PCS_OP_STOP: + return kfd_pc_sample_stop(pdd); + } + + return -EINVAL; +} diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.h b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.h new file mode 100644 index 0000000000000..4eeded4ea5b6c --- /dev/null +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* + * Copyright 2023 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef KFD_PC_SAMPLING_H_ +#define KFD_PC_SAMPLING_H_ + +#include "amdgpu.h" +#include "kfd_priv.h" + +int kfd_pc_sample(struct kfd_process_device *pdd, + struct kfd_ioctl_pc_sample_args __user *args); + +#endif /* KFD_PC_SAMPLING_H_ */ diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 92fd00d0811f8..f56a1a1d5d9d5 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -149,6 +149,19 @@ enum kfd_ioctl_flags { * we also allow ioctls with SYS_ADMIN capability. */ KFD_IOC_FLAG_CHECKPOINT_RESTORE = BIT(0), + + /* + * @KFD_IOC_FLAG_PERFMON: + * Performance monitoring feature, GPU performance monitoring can allow users + * to gather some information about other processes. PC sampling can allow + * users to infer information about wavefronts from other processes that are + * running on the same CUs, such as which execution units they are using. As + * such, this type of performance monitoring should be protected and only + * available to users with sufficient capabilities: either CAP_PERFMON, or, + * for backwards compatibility, CAP_SYS_ADMIN. + */ + + KFD_IOC_FLAG_PERFMON = BIT(1), }; /* * Kernel module parameter to specify maximum number of supported queues per From 8cfd0a000fa84227c303d4b5af3e9960687e4e60 Mon Sep 17 00:00:00 2001 From: David Yat Sin Date: Fri, 21 Jul 2023 12:24:13 -0400 Subject: [PATCH 1166/1868] drm/amdkfd: enable pc sampling query Enable pc sampling to query system capability. Co-developed-by: James Zhu Signed-off-by: James Zhu Signed-off-by: David Yat Sin Tested-by: Vladimir Indic --- drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 65 +++++++++++++++++++- 1 file changed, 64 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index a7e78ff42d079..e9277c9beec73 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -25,10 +25,73 @@ #include "amdgpu_amdkfd.h" #include "kfd_pc_sampling.h" +struct supported_pc_sample_info { + uint32_t ip_version; + const struct kfd_pc_sample_info *sample_info; +}; + +const struct kfd_pc_sample_info sample_info_hosttrap_9_0_0 = { + 0, 1, ~0ULL, 0, KFD_IOCTL_PCS_METHOD_HOSTTRAP, KFD_IOCTL_PCS_TYPE_TIME_US }; + +struct supported_pc_sample_info supported_formats[] = { + { IP_VERSION(9, 4, 1), &sample_info_hosttrap_9_0_0 }, + { IP_VERSION(9, 4, 2), &sample_info_hosttrap_9_0_0 }, +}; + static int kfd_pc_sample_query_cap(struct kfd_process_device *pdd, struct kfd_ioctl_pc_sample_args __user *user_args) { - return -EINVAL; + uint64_t sample_offset; + int num_method = 0; + int ret; + int i; + + for (i = 0; i < ARRAY_SIZE(supported_formats); i++) + if (KFD_GC_VERSION(pdd->dev) == supported_formats[i].ip_version) + num_method++; + + if (!num_method) { + pr_debug("PC Sampling not supported on GC_HWIP:0x%x.", + pdd->dev->adev->ip_versions[GC_HWIP][0]); + return -EOPNOTSUPP; + } + + ret = 0; + mutex_lock(&pdd->dev->pcs_data.mutex); + if (user_args->flags != KFD_IOCTL_PCS_QUERY_TYPE_FULL && + pdd->dev->pcs_data.hosttrap_entry.base.use_count) { + /* If we already have a session, restrict returned list to current method */ + user_args->num_sample_info = 1; + + if (user_args->sample_info_ptr) + ret = copy_to_user((void __user *) user_args->sample_info_ptr, + &pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_info, + sizeof(struct kfd_pc_sample_info)); + mutex_unlock(&pdd->dev->pcs_data.mutex); + return ret ? -EFAULT : 0; + } + mutex_unlock(&pdd->dev->pcs_data.mutex); + + if (!user_args->sample_info_ptr || user_args->num_sample_info < num_method) { + user_args->num_sample_info = num_method; + pr_debug("ASIC requires space for %d kfd_pc_sample_info entries.", num_method); + return -ENOSPC; + } + + sample_offset = user_args->sample_info_ptr; + for (i = 0; i < ARRAY_SIZE(supported_formats); i++) { + if (KFD_GC_VERSION(pdd->dev) == supported_formats[i].ip_version) { + ret = copy_to_user((void __user *) sample_offset, + supported_formats[i].sample_info, sizeof(struct kfd_pc_sample_info)); + if (ret) { + pr_debug("Failed to copy PC sampling info to user."); + return -EFAULT; + } + sample_offset += sizeof(struct kfd_pc_sample_info); + } + } + + return 0; } static int kfd_pc_sample_start(struct kfd_process_device *pdd) From 4c83366edbee359957b0ecb0a2ef6a3f98c5235d Mon Sep 17 00:00:00 2001 From: James Zhu Date: Sun, 6 Aug 2023 16:26:26 -0400 Subject: [PATCH 1167/1868] drm/amdkfd: add pc sampling mutex Add pc sampling mutex per node, and do init/destroy in node init. Signed-off-by: James Zhu Tested-by: Vladimir Indic --- drivers/gpu/drm/amd/amdkfd/kfd_device.c | 12 ++++++++++++ drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 7 +++++++ 2 files changed, 19 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index b301a5b3d4cf8..e9bd8d13afa34 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -595,6 +595,16 @@ static void kfd_smi_init(struct kfd_node *dev) spin_lock_init(&dev->smi_lock); } +static void kfd_pc_sampling_init(struct kfd_node *dev) +{ + mutex_init(&dev->pcs_data.mutex); +} + +static void kfd_pc_sampling_exit(struct kfd_node *dev) +{ + mutex_destroy(&dev->pcs_data.mutex); +} + static int kfd_init_node(struct kfd_node *node) { int err = -1; @@ -625,6 +635,7 @@ static int kfd_init_node(struct kfd_node *node) } kfd_smi_init(node); + kfd_pc_sampling_init(node); return 0; @@ -655,6 +666,7 @@ static void kfd_cleanup_nodes(struct kfd_dev *kfd, unsigned int num_nodes) kfd_topology_remove_device(knode); if (knode->gws) amdgpu_amdkfd_free_gws(knode->adev, knode->gws); + kfd_pc_sampling_exit(knode); kfree(knode); kfd->nodes[i] = NULL; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index f56a1a1d5d9d5..80e57544d69d0 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -285,6 +285,11 @@ struct kfd_vmid_info { struct kfd_dev; +/* Per device PC Sampling data */ +struct kfd_dev_pc_sampling { + struct mutex mutex; +}; + struct kfd_node { unsigned int node_id; struct amdgpu_device *adev; /* Duplicated here along with keeping @@ -342,6 +347,8 @@ struct kfd_node { /* Track per device allocated watch points */ uint32_t alloc_watch_ids; spinlock_t watch_points_lock; + + struct kfd_dev_pc_sampling pcs_data; }; struct kfd_dev { From f8244d7cdf70e1e5de1bde02040279f54e3fd0f8 Mon Sep 17 00:00:00 2001 From: David Yat Sin Date: Fri, 21 Jul 2023 14:43:49 -0400 Subject: [PATCH 1168/1868] drm/amdkfd: enable pc sampling create Enable pc sampling create. Co-developed-by: James Zhu Signed-off-by: James Zhu Signed-off-by: David Yat Sin Tested-by: Vladimir Indic --- drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 59 +++++++++++++++++++- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 10 ++++ 2 files changed, 68 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index e9277c9beec73..9267de0bbdac3 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -108,7 +108,64 @@ static int kfd_pc_sample_stop(struct kfd_process_device *pdd) static int kfd_pc_sample_create(struct kfd_process_device *pdd, struct kfd_ioctl_pc_sample_args __user *user_args) { - return -EINVAL; + struct kfd_pc_sample_info *supported_format = NULL; + struct kfd_pc_sample_info user_info; + int ret; + int i; + + if (user_args->num_sample_info != 1) + return -EINVAL; + + ret = copy_from_user(&user_info, (void __user *) user_args->sample_info_ptr, + sizeof(struct kfd_pc_sample_info)); + if (ret) { + pr_debug("Failed to copy PC sampling info from user\n"); + return -EFAULT; + } + + if (user_info.flags & KFD_IOCTL_PCS_FLAG_POWER_OF_2 && + user_info.interval & (user_info.interval - 1)) { + pr_debug("Sampling interval's power is unmatched!"); + return -EINVAL; + } + + for (i = 0; i < ARRAY_SIZE(supported_formats); i++) { + if (KFD_GC_VERSION(pdd->dev) == supported_formats[i].ip_version + && user_info.method == supported_formats[i].sample_info->method + && user_info.type == supported_formats[i].sample_info->type + && user_info.interval <= supported_formats[i].sample_info->interval_max + && user_info.interval >= supported_formats[i].sample_info->interval_min) { + supported_format = + (struct kfd_pc_sample_info *)supported_formats[i].sample_info; + break; + } + } + + if (!supported_format) { + pr_debug("Sampling format is not supported!"); + return -EOPNOTSUPP; + } + + mutex_lock(&pdd->dev->pcs_data.mutex); + if (pdd->dev->pcs_data.hosttrap_entry.base.use_count && + memcmp(&pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_info, + &user_info, sizeof(user_info))) { + ret = copy_to_user((void __user *) user_args->sample_info_ptr, + &pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_info, + sizeof(struct kfd_pc_sample_info)); + mutex_unlock(&pdd->dev->pcs_data.mutex); + return ret ? -EFAULT : -EEXIST; + } + + /* TODO: add trace_id return */ + + if (!pdd->dev->pcs_data.hosttrap_entry.base.use_count) + pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_info = user_info; + + pdd->dev->pcs_data.hosttrap_entry.base.use_count++; + mutex_unlock(&pdd->dev->pcs_data.mutex); + + return 0; } static int kfd_pc_sample_destroy(struct kfd_process_device *pdd, uint32_t trace_id) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 80e57544d69d0..8469b56b78fb8 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -285,9 +285,19 @@ struct kfd_vmid_info { struct kfd_dev; +struct kfd_dev_pc_sampling_data { + uint32_t use_count; /* Num of PC sampling sessions */ + struct kfd_pc_sample_info pc_sample_info; +}; + +struct kfd_dev_pcs_hosttrap { + struct kfd_dev_pc_sampling_data base; +}; + /* Per device PC Sampling data */ struct kfd_dev_pc_sampling { struct mutex mutex; + struct kfd_dev_pcs_hosttrap hosttrap_entry; }; struct kfd_node { From 2a77f916bb15de332550626c1fb372d41de4bb86 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Tue, 8 Aug 2023 16:13:46 -0400 Subject: [PATCH 1169/1868] drm/amdkfd: add trace_id return Add trace_id return for new pc sampling creation per device, Use IDR to quickly locate pc_sampling_entry for reference. Signed-off-by: James Zhu Tested-by: Vladimir Indic --- drivers/gpu/drm/amd/amdkfd/kfd_device.c | 2 ++ drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 20 +++++++++++++++++++- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 6 ++++++ 3 files changed, 27 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index e9bd8d13afa34..b10417a9df17d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -598,10 +598,12 @@ static void kfd_smi_init(struct kfd_node *dev) static void kfd_pc_sampling_init(struct kfd_node *dev) { mutex_init(&dev->pcs_data.mutex); + idr_init_base(&dev->pcs_data.hosttrap_entry.base.pc_sampling_idr, 1); } static void kfd_pc_sampling_exit(struct kfd_node *dev) { + idr_destroy(&dev->pcs_data.hosttrap_entry.base.pc_sampling_idr); mutex_destroy(&dev->pcs_data.mutex); } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index 9267de0bbdac3..a607fc1489587 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -110,6 +110,7 @@ static int kfd_pc_sample_create(struct kfd_process_device *pdd, { struct kfd_pc_sample_info *supported_format = NULL; struct kfd_pc_sample_info user_info; + struct pc_sampling_entry *pcs_entry; int ret; int i; @@ -157,7 +158,19 @@ static int kfd_pc_sample_create(struct kfd_process_device *pdd, return ret ? -EFAULT : -EEXIST; } - /* TODO: add trace_id return */ + pcs_entry = kzalloc(sizeof(*pcs_entry), GFP_KERNEL); + if (!pcs_entry) { + mutex_unlock(&pdd->dev->pcs_data.mutex); + return -ENOMEM; + } + + i = idr_alloc_cyclic(&pdd->dev->pcs_data.hosttrap_entry.base.pc_sampling_idr, + pcs_entry, 1, 0, GFP_KERNEL); + if (i < 0) { + mutex_unlock(&pdd->dev->pcs_data.mutex); + kfree(pcs_entry); + return i; + } if (!pdd->dev->pcs_data.hosttrap_entry.base.use_count) pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_info = user_info; @@ -165,6 +178,11 @@ static int kfd_pc_sample_create(struct kfd_process_device *pdd, pdd->dev->pcs_data.hosttrap_entry.base.use_count++; mutex_unlock(&pdd->dev->pcs_data.mutex); + pcs_entry->pdd = pdd; + user_args->trace_id = (uint32_t)i; + + pr_debug("alloc pcs_entry = %p, trace_id = 0x%x on gpu 0x%x", pcs_entry, i, pdd->dev->id); + return 0; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 8469b56b78fb8..d3120fdb82f36 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -287,6 +287,7 @@ struct kfd_dev; struct kfd_dev_pc_sampling_data { uint32_t use_count; /* Num of PC sampling sessions */ + struct idr pc_sampling_idr; struct kfd_pc_sample_info pc_sample_info; }; @@ -813,6 +814,11 @@ enum kfd_pdd_bound { */ #define SDMA_ACTIVITY_DIVISOR 100 +struct pc_sampling_entry { + bool enabled; + struct kfd_process_device *pdd; +}; + /* Data that is per-process-per device. */ struct kfd_process_device { /* The device that owns this data. */ From 2b06402d926559b65d8a22d4ccd202da9f736a96 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Tue, 8 Aug 2023 16:28:47 -0400 Subject: [PATCH 1170/1868] drm/amdkfd: check pcs_entry valid Check pcs_entry valid for pc sampling ioctl. Signed-off-by: James Zhu Tested-by: Vladimir Indic --- drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 33 ++++++++++++++++++-- 1 file changed, 30 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index a607fc1489587..72c66d4bd24f9 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -195,6 +195,24 @@ static int kfd_pc_sample_destroy(struct kfd_process_device *pdd, uint32_t trace_ int kfd_pc_sample(struct kfd_process_device *pdd, struct kfd_ioctl_pc_sample_args __user *args) { + struct pc_sampling_entry *pcs_entry; + + if (args->op != KFD_IOCTL_PCS_OP_QUERY_CAPABILITIES && + args->op != KFD_IOCTL_PCS_OP_CREATE) { + + mutex_lock(&pdd->dev->pcs_data.mutex); + pcs_entry = idr_find(&pdd->dev->pcs_data.hosttrap_entry.base.pc_sampling_idr, + args->trace_id); + mutex_unlock(&pdd->dev->pcs_data.mutex); + + /* pcs_entry is only for this pc sampling process, + * which has kfd_process->mutex protected here. + */ + if (!pcs_entry || + pcs_entry->pdd != pdd) + return -EINVAL; + } + switch (args->op) { case KFD_IOCTL_PCS_OP_QUERY_CAPABILITIES: return kfd_pc_sample_query_cap(pdd, args); @@ -203,13 +221,22 @@ int kfd_pc_sample(struct kfd_process_device *pdd, return kfd_pc_sample_create(pdd, args); case KFD_IOCTL_PCS_OP_DESTROY: - return kfd_pc_sample_destroy(pdd, args->trace_id); + if (pcs_entry->enabled) + return -EBUSY; + else + return kfd_pc_sample_destroy(pdd, args->trace_id); case KFD_IOCTL_PCS_OP_START: - return kfd_pc_sample_start(pdd); + if (pcs_entry->enabled) + return -EALREADY; + else + return kfd_pc_sample_start(pdd); case KFD_IOCTL_PCS_OP_STOP: - return kfd_pc_sample_stop(pdd); + if (!pcs_entry->enabled) + return -EALREADY; + else + return kfd_pc_sample_stop(pdd); } return -EINVAL; From ea65a821eb68041db08a1baa7763a4654be73488 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Fri, 21 Jul 2023 14:50:00 -0400 Subject: [PATCH 1171/1868] drm/amdkfd: enable pc sampling destroy Enable pc sampling destroy. Signed-off-by: James Zhu Tested-by: Vladimir Indic --- drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index 72c66d4bd24f9..b46caa52fbe83 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -186,10 +186,24 @@ static int kfd_pc_sample_create(struct kfd_process_device *pdd, return 0; } -static int kfd_pc_sample_destroy(struct kfd_process_device *pdd, uint32_t trace_id) +static int kfd_pc_sample_destroy(struct kfd_process_device *pdd, uint32_t trace_id, + struct pc_sampling_entry *pcs_entry) { - return -EINVAL; + pr_debug("free pcs_entry = %p, trace_id = 0x%x on gpu 0x%x", + pcs_entry, trace_id, pdd->dev->id); + + mutex_lock(&pdd->dev->pcs_data.mutex); + pdd->dev->pcs_data.hosttrap_entry.base.use_count--; + idr_remove(&pdd->dev->pcs_data.hosttrap_entry.base.pc_sampling_idr, trace_id); + if (!pdd->dev->pcs_data.hosttrap_entry.base.use_count) + memset(&pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_info, 0x0, + sizeof(struct kfd_pc_sample_info)); + mutex_unlock(&pdd->dev->pcs_data.mutex); + + kfree(pcs_entry); + + return 0; } int kfd_pc_sample(struct kfd_process_device *pdd, @@ -224,7 +238,7 @@ int kfd_pc_sample(struct kfd_process_device *pdd, if (pcs_entry->enabled) return -EBUSY; else - return kfd_pc_sample_destroy(pdd, args->trace_id); + return kfd_pc_sample_destroy(pdd, args->trace_id, pcs_entry); case KFD_IOCTL_PCS_OP_START: if (pcs_entry->enabled) From 21ab4d9a5d3f9ebffe6ffcc21bb347707940775b Mon Sep 17 00:00:00 2001 From: James Zhu Date: Fri, 21 Jul 2023 14:11:56 -0400 Subject: [PATCH 1172/1868] drm/amdkfd: add interface to trigger pc sampling trap Add interface to trigger pc sampling trap. -v6: add multiple instances support Signed-off-by: James Zhu Tested-by: Vladimir Indic --- drivers/gpu/drm/amd/include/kgd_kfd_interface.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h index 1243d4e2dd5ce..27454731b3e04 100644 --- a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h +++ b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h @@ -31,6 +31,8 @@ #include #include #include +#include + #include "amdgpu_irq.h" #include "amdgpu_gfx.h" @@ -329,6 +331,12 @@ struct kfd2kgd_calls { uint64_t (*hqd_reset)(struct amdgpu_device *adev, uint32_t pipe_id, uint32_t queue_id, uint32_t inst, unsigned int utimeout); + uint32_t (*trigger_pc_sample_trap)(struct amdgpu_device *adev, + uint32_t vmid, + uint32_t *target_simd, + uint32_t *target_wave_slot, + enum kfd_ioctl_pc_sample_method method, + uint32_t inst); }; #endif /* KGD_KFD_INTERFACE_H_INCLUDED */ From 498c73626c455c1a6450ecf71bec94c29b781aae Mon Sep 17 00:00:00 2001 From: James Zhu Date: Sun, 6 Aug 2023 12:41:03 -0400 Subject: [PATCH 1173/1868] drm/amdkfd: trigger pc sampling trap for gfx v9 Implement trigger pc sampling trap for gfx v9. -v6: add multiple instances support Signed-off-by: James Zhu Tested-by: Vladimir Indic --- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 37 +++++++++++++++++++ .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h | 8 ++++ 2 files changed, 45 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c index c63528a4e8941..628812a583582 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c @@ -1243,6 +1243,43 @@ uint64_t kgd_gfx_v9_hqd_reset(struct amdgpu_device *adev, return queue_addr; } +uint32_t kgd_gfx_v9_trigger_pc_sample_trap(struct amdgpu_device *adev, + uint32_t vmid, + uint32_t max_wave_slot, + uint32_t max_simd, + uint32_t *target_simd, + uint32_t *target_wave_slot, + enum kfd_ioctl_pc_sample_method method, + uint32_t inst) +{ + if (method == KFD_IOCTL_PCS_METHOD_HOSTTRAP) { + uint32_t value = 0; + + value = REG_SET_FIELD(value, SQ_CMD, CMD, SQ_IND_CMD_CMD_TRAP); + value = REG_SET_FIELD(value, SQ_CMD, MODE, SQ_IND_CMD_MODE_SINGLE); + + /* select *target_simd */ + value = REG_SET_FIELD(value, SQ_CMD, SIMD_ID, *target_simd); + /* select *target_wave_slot */ + value = REG_SET_FIELD(value, SQ_CMD, WAVE_ID, (*target_wave_slot)++); + + mutex_lock(&adev->grbm_idx_mutex); + amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, inst); + WREG32_SOC15(GC, GET_INST(GC, inst), mmSQ_CMD, value); + mutex_unlock(&adev->grbm_idx_mutex); + + *target_wave_slot %= max_wave_slot; + if (!(*target_wave_slot)) { + (*target_simd)++; + *target_simd %= max_simd; + } + } else { + pr_debug("PC Sampling method %d not supported.", method); + return -EOPNOTSUPP; + } + return 0; +} + const struct kfd2kgd_calls gfx_v9_kfd2kgd = { .program_sh_mem_settings = kgd_gfx_v9_program_sh_mem_settings, .set_pasid_vmid_mapping = kgd_gfx_v9_set_pasid_vmid_mapping, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h index 988c50ac3be01..41eae07e7c195 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h @@ -110,3 +110,11 @@ uint64_t kgd_gfx_v9_hqd_reset(struct amdgpu_device *adev, uint32_t queue_id, uint32_t inst, unsigned int utimeout); +uint32_t kgd_gfx_v9_trigger_pc_sample_trap(struct amdgpu_device *adev, + uint32_t vmid, + uint32_t max_wave_slot, + uint32_t max_simd, + uint32_t *target_simd, + uint32_t *target_wave_slot, + enum kfd_ioctl_pc_sample_method method, + uint32_t inst); From 472bef769a81ce380bcb1b123b6777ff32d8faa4 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Sat, 12 Aug 2023 14:46:44 -0400 Subject: [PATCH 1174/1868] drm/amdkfd/gfx9: enable host trap Enable host trap. Signed-off-by: James Zhu Tested-by: Vladimir Indic --- .../gpu/drm/amd/amdkfd/cwsr_trap_handler.h | 63 +++++++++++-------- .../drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm | 24 ++++--- 2 files changed, 52 insertions(+), 35 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h index 02f7ba8c93cd4..c9d1be90985ed 100644 --- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h +++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h @@ -274,14 +274,14 @@ static const uint32_t cwsr_trap_gfx8_hex[] = { static const uint32_t cwsr_trap_gfx9_hex[] = { - 0xbf820001, 0xbf820258, + 0xbf820001, 0xbf82025e, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, 0x866eff78, 0x00002000, 0xbf840009, 0x866eff6d, 0x00ff0000, 0xbf85001e, 0x866eff7b, 0x00000400, - 0xbf850055, 0xbf8e0010, + 0xbf85005b, 0xbf8e0010, 0xb8fbf803, 0xbf82fffa, 0x866eff7b, 0x03c00900, 0xbf850015, 0x866eff7b, @@ -294,7 +294,7 @@ static const uint32_t cwsr_trap_gfx9_hex[] = { 0xbf850007, 0xb8eef801, 0x866eff6e, 0x00000800, 0xbf850003, 0x866eff7b, - 0x00000400, 0xbf85003a, + 0x00000400, 0xbf850040, 0xb8faf807, 0x867aff7a, 0x001f8000, 0x8e7a8b7a, 0x8977ff77, 0xfc000000, @@ -303,13 +303,16 @@ static const uint32_t cwsr_trap_gfx9_hex[] = { 0xb8fbf813, 0x8efa887a, 0xbf0d8f7b, 0xbf840002, 0x877bff7b, 0xffff0000, - 0xc0031bbd, 0x00000010, - 0xbf8cc07f, 0x8e6e976e, - 0x8977ff77, 0x00800000, - 0x87776e77, 0xc0071bbd, - 0x00000000, 0xbf8cc07f, + 0xc0031c3d, 0x00000010, + 0xc0071bbd, 0x00000000, 0xc0071ebd, 0x00000008, - 0xbf8cc07f, 0x86ee6e6e, + 0xbf8cc07f, 0x8671ff6d, + 0x01000000, 0xbf840004, + 0x92f1ff70, 0x00010001, + 0xbf840016, 0xbf820005, + 0x86708170, 0x8e709770, + 0x8977ff77, 0x00800000, + 0x87777077, 0x86ee6e6e, 0xbf840001, 0xbe801d6e, 0x866eff6d, 0x01ff0000, 0xbf850005, 0x8778ff78, @@ -1302,14 +1305,14 @@ static const uint32_t cwsr_trap_nv1x_hex[] = { }; static const uint32_t cwsr_trap_arcturus_hex[] = { - 0xbf820001, 0xbf8202d4, + 0xbf820001, 0xbf8202da, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, 0x866eff78, 0x00002000, 0xbf840009, 0x866eff6d, 0x00ff0000, 0xbf85001e, 0x866eff7b, 0x00000400, - 0xbf850055, 0xbf8e0010, + 0xbf85005b, 0xbf8e0010, 0xb8fbf803, 0xbf82fffa, 0x866eff7b, 0x03c00900, 0xbf850015, 0x866eff7b, @@ -1322,7 +1325,7 @@ static const uint32_t cwsr_trap_arcturus_hex[] = { 0xbf850007, 0xb8eef801, 0x866eff6e, 0x00000800, 0xbf850003, 0x866eff7b, - 0x00000400, 0xbf85003a, + 0x00000400, 0xbf850040, 0xb8faf807, 0x867aff7a, 0x001f8000, 0x8e7a8b7a, 0x8977ff77, 0xfc000000, @@ -1331,13 +1334,16 @@ static const uint32_t cwsr_trap_arcturus_hex[] = { 0xb8fbf813, 0x8efa887a, 0xbf0d8f7b, 0xbf840002, 0x877bff7b, 0xffff0000, - 0xc0031bbd, 0x00000010, - 0xbf8cc07f, 0x8e6e976e, - 0x8977ff77, 0x00800000, - 0x87776e77, 0xc0071bbd, - 0x00000000, 0xbf8cc07f, + 0xc0031c3d, 0x00000010, + 0xc0071bbd, 0x00000000, 0xc0071ebd, 0x00000008, - 0xbf8cc07f, 0x86ee6e6e, + 0xbf8cc07f, 0x8671ff6d, + 0x01000000, 0xbf840004, + 0x92f1ff70, 0x00010001, + 0xbf840016, 0xbf820005, + 0x86708170, 0x8e709770, + 0x8977ff77, 0x00800000, + 0x87777077, 0x86ee6e6e, 0xbf840001, 0xbe801d6e, 0x866eff6d, 0x01ff0000, 0xbf850005, 0x8778ff78, @@ -1782,14 +1788,14 @@ static const uint32_t cwsr_trap_arcturus_hex[] = { }; static const uint32_t cwsr_trap_aldebaran_hex[] = { - 0xbf820001, 0xbf8202df, + 0xbf820001, 0xbf8202e5, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, 0x866eff78, 0x00002000, 0xbf840009, 0x866eff6d, 0x00ff0000, 0xbf85001e, 0x866eff7b, 0x00000400, - 0xbf850055, 0xbf8e0010, + 0xbf85005b, 0xbf8e0010, 0xb8fbf803, 0xbf82fffa, 0x866eff7b, 0x03c00900, 0xbf850015, 0x866eff7b, @@ -1802,7 +1808,7 @@ static const uint32_t cwsr_trap_aldebaran_hex[] = { 0xbf850007, 0xb8eef801, 0x866eff6e, 0x00000800, 0xbf850003, 0x866eff7b, - 0x00000400, 0xbf85003a, + 0x00000400, 0xbf850040, 0xb8faf807, 0x867aff7a, 0x001f8000, 0x8e7a8b7a, 0x8977ff77, 0xfc000000, @@ -1811,13 +1817,16 @@ static const uint32_t cwsr_trap_aldebaran_hex[] = { 0xb8fbf813, 0x8efa887a, 0xbf0d8f7b, 0xbf840002, 0x877bff7b, 0xffff0000, - 0xc0031bbd, 0x00000010, - 0xbf8cc07f, 0x8e6e976e, - 0x8977ff77, 0x00800000, - 0x87776e77, 0xc0071bbd, - 0x00000000, 0xbf8cc07f, + 0xc0031c3d, 0x00000010, + 0xc0071bbd, 0x00000000, 0xc0071ebd, 0x00000008, - 0xbf8cc07f, 0x86ee6e6e, + 0xbf8cc07f, 0x8671ff6d, + 0x01000000, 0xbf840004, + 0x92f1ff70, 0x00010001, + 0xbf840016, 0xbf820005, + 0x86708170, 0x8e709770, + 0x8977ff77, 0x00800000, + 0x87777077, 0x86ee6e6e, 0xbf840001, 0xbe801d6e, 0x866eff6d, 0x01ff0000, 0xbf850005, 0x8778ff78, diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm index bb26338204f4b..991fe6bb1726d 100644 --- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm +++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm @@ -104,6 +104,10 @@ var SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK = 0x1F8000 var SQ_WAVE_MODE_DEBUG_EN_MASK = 0x800 +var TMA_HOST_TRAP_EN_SHIFT = 1 +var TMA_HOST_TRAP_EN_SIZE = 1 +var TMA_HOST_TRAP_EN_BFE = (TMA_HOST_TRAP_EN_SHIFT | (TMA_HOST_TRAP_EN_SIZE << 16)) + var TTMP_SAVE_RCNT_FIRST_REPLAY_SHIFT = 26 // bits [31:26] unused by SPI debug data var TTMP_SAVE_RCNT_FIRST_REPLAY_MASK = 0xFC000000 var TTMP_DEBUG_TRAP_ENABLED_SHIFT = 23 @@ -288,17 +292,21 @@ L_FETCH_2ND_TRAP: s_or_b32 ttmp15, ttmp15, 0xFFFF0000 L_NO_SIGN_EXTEND_TMA: - s_load_dword ttmp2, [ttmp14, ttmp15], 0x10 glc:1 // debug trap enabled flag - s_waitcnt lgkmcnt(0) - s_lshl_b32 ttmp2, ttmp2, TTMP_DEBUG_TRAP_ENABLED_SHIFT - s_andn2_b32 s_save_ib_sts, s_save_ib_sts, TTMP_DEBUG_TRAP_ENABLED_MASK - s_or_b32 s_save_ib_sts, s_save_ib_sts, ttmp2 - + s_load_dword ttmp4, [ttmp14, ttmp15], 0x10 glc:1 // enable flags from 1st level TMA s_load_dwordx2 [ttmp2, ttmp3], [ttmp14, ttmp15], 0x0 glc:1 // second-level TBA - s_waitcnt lgkmcnt(0) s_load_dwordx2 [ttmp14, ttmp15], [ttmp14, ttmp15], 0x8 glc:1 // second-level TMA s_waitcnt lgkmcnt(0) - + s_and_b32 ttmp5, s_save_pc_hi, S_SAVE_PC_HI_HT_MASK // host trap request + s_cbranch_scc0 L_NOT_HT + s_bfe_u32 ttmp5, ttmp4, TMA_HOST_TRAP_EN_BFE // extract host_trap_en to ttmp5[0] + s_cbranch_scc0 L_EXIT_TRAP // HT requested, but host traps not enabled + s_branch L_GOTO_2ND_TRAP +L_NOT_HT: + s_and_b32 ttmp4, ttmp4, 0x1 // debug_enable bit left over + s_lshl_b32 ttmp4, ttmp4, TTMP_DEBUG_TRAP_ENABLED_SHIFT + s_andn2_b32 s_save_ib_sts, s_save_ib_sts, TTMP_DEBUG_TRAP_ENABLED_MASK + s_or_b32 s_save_ib_sts, s_save_ib_sts, ttmp4 +L_GOTO_2ND_TRAP: s_and_b64 [ttmp2, ttmp3], [ttmp2, ttmp3], [ttmp2, ttmp3] s_cbranch_scc0 L_NO_NEXT_TRAP // second-level trap handler not been set s_setpc_b64 [ttmp2, ttmp3] // jump to second-level trap handler From 1eca98c0d4c975ce6b76892a2649b7e4dda94849 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Wed, 27 Sep 2023 11:01:18 -0400 Subject: [PATCH 1175/1868] drm/amdgpu: use trapID 4 for host trap Since TRAPSTS.HOST_TRAP won't work pre-gfx943, so use TTMP1 (bit 24: HT) and (bit 16-23: trapID) to identify the host trap. Signed-off-by: James Zhu Tested-by: Vladimir Indic --- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 2 + .../gpu/drm/amd/amdkfd/cwsr_trap_handler.h | 2115 +++++++++-------- .../drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm | 5 + 3 files changed, 1069 insertions(+), 1053 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c index 628812a583582..e00aace9ac8d8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c @@ -1262,6 +1262,8 @@ uint32_t kgd_gfx_v9_trigger_pc_sample_trap(struct amdgpu_device *adev, value = REG_SET_FIELD(value, SQ_CMD, SIMD_ID, *target_simd); /* select *target_wave_slot */ value = REG_SET_FIELD(value, SQ_CMD, WAVE_ID, (*target_wave_slot)++); + /* set TrapID 4 for HOSTTRAP */ + value = REG_SET_FIELD(value, SQ_CMD, DATA, 0x4); mutex_lock(&adev->grbm_idx_mutex); amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, inst); diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h index c9d1be90985ed..8086764080878 100644 --- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h +++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h @@ -274,155 +274,263 @@ static const uint32_t cwsr_trap_gfx8_hex[] = { static const uint32_t cwsr_trap_gfx9_hex[] = { - 0xbf820001, 0xbf82025e, + 0xbf820001, 0xbf820263, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, 0x866eff78, 0x00002000, 0xbf840009, 0x866eff6d, - 0x00ff0000, 0xbf85001e, + 0x00ff0000, 0xbf850023, 0x866eff7b, 0x00000400, - 0xbf85005b, 0xbf8e0010, + 0xbf850060, 0xbf8e0010, 0xb8fbf803, 0xbf82fffa, 0x866eff7b, 0x03c00900, - 0xbf850015, 0x866eff7b, - 0x000071ff, 0xbf840008, - 0x866fff7b, 0x00007080, - 0xbf840001, 0xbeee1a87, - 0xb8eff801, 0x8e6e8c6e, - 0x866e6f6e, 0xbf85000a, - 0x866eff6d, 0x00ff0000, - 0xbf850007, 0xb8eef801, - 0x866eff6e, 0x00000800, - 0xbf850003, 0x866eff7b, - 0x00000400, 0xbf850040, - 0xb8faf807, 0x867aff7a, - 0x001f8000, 0x8e7a8b7a, - 0x8977ff77, 0xfc000000, - 0x87777a77, 0xba7ff807, - 0x00000000, 0xb8faf812, - 0xb8fbf813, 0x8efa887a, - 0xbf0d8f7b, 0xbf840002, - 0x877bff7b, 0xffff0000, - 0xc0031c3d, 0x00000010, - 0xc0071bbd, 0x00000000, - 0xc0071ebd, 0x00000008, - 0xbf8cc07f, 0x8671ff6d, - 0x01000000, 0xbf840004, - 0x92f1ff70, 0x00010001, - 0xbf840016, 0xbf820005, - 0x86708170, 0x8e709770, - 0x8977ff77, 0x00800000, - 0x87777077, 0x86ee6e6e, - 0xbf840001, 0xbe801d6e, - 0x866eff6d, 0x01ff0000, - 0xbf850005, 0x8778ff78, - 0x00002000, 0x80ec886c, - 0x82ed806d, 0xbf820005, - 0x866eff6d, 0x01000000, - 0xbf850002, 0x806c846c, - 0x826d806d, 0x866dff6d, - 0x0000ffff, 0x8f7a8b77, + 0xbf85001a, 0x866eff6d, + 0x01ff0000, 0xbf06ff6e, + 0x01040000, 0xbf850015, + 0x866eff7b, 0x000071ff, + 0xbf840008, 0x866fff7b, + 0x00007080, 0xbf840001, + 0xbeee1a87, 0xb8eff801, + 0x8e6e8c6e, 0x866e6f6e, + 0xbf85000a, 0x866eff6d, + 0x00ff0000, 0xbf850007, + 0xb8eef801, 0x866eff6e, + 0x00000800, 0xbf850003, + 0x866eff7b, 0x00000400, + 0xbf850040, 0xb8faf807, 0x867aff7a, 0x001f8000, - 0xb97af807, 0x86fe7e7e, - 0x86ea6a6a, 0x8f6e8378, - 0xb96ee0c2, 0xbf800002, - 0xb9780002, 0xbe801f6c, + 0x8e7a8b7a, 0x8977ff77, + 0xfc000000, 0x87777a77, + 0xba7ff807, 0x00000000, + 0xb8faf812, 0xb8fbf813, + 0x8efa887a, 0xbf0d8f7b, + 0xbf840002, 0x877bff7b, + 0xffff0000, 0xc0031c3d, + 0x00000010, 0xc0071bbd, + 0x00000000, 0xc0071ebd, + 0x00000008, 0xbf8cc07f, + 0x8671ff6d, 0x01000000, + 0xbf840004, 0x92f1ff70, + 0x00010001, 0xbf840016, + 0xbf820005, 0x86708170, + 0x8e709770, 0x8977ff77, + 0x00800000, 0x87777077, + 0x86ee6e6e, 0xbf840001, + 0xbe801d6e, 0x866eff6d, + 0x01ff0000, 0xbf850005, + 0x8778ff78, 0x00002000, + 0x80ec886c, 0x82ed806d, + 0xbf820005, 0x866eff6d, + 0x01000000, 0xbf850002, + 0x806c846c, 0x826d806d, 0x866dff6d, 0x0000ffff, - 0xbefa0080, 0xb97a0283, - 0xb8faf807, 0x867aff7a, - 0x001f8000, 0x8e7a8b7a, - 0x8977ff77, 0xfc000000, - 0x87777a77, 0xba7ff807, - 0x00000000, 0xbeee007e, - 0xbeef007f, 0xbefe0180, - 0xbf900004, 0x877a8478, - 0xb97af802, 0xbf8e0002, - 0xbf88fffe, 0xb8fa2a05, - 0x807a817a, 0x8e7a8a7a, - 0xb8fb1605, 0x807b817b, - 0x8e7b867b, 0x807a7b7a, - 0x807a7e7a, 0x827b807f, - 0x867bff7b, 0x0000ffff, - 0xc04b1c3d, 0x00000050, - 0xbf8cc07f, 0xc04b1d3d, - 0x00000060, 0xbf8cc07f, - 0xc0431e7d, 0x00000074, - 0xbf8cc07f, 0xbef4007e, - 0x8675ff7f, 0x0000ffff, - 0x8775ff75, 0x00040000, - 0xbef60080, 0xbef700ff, - 0x00807fac, 0xbef1007c, - 0xbef00080, 0xb8f02a05, - 0x80708170, 0x8e708a70, - 0xb8fa1605, 0x807a817a, - 0x8e7a867a, 0x80707a70, - 0xbef60084, 0xbef600ff, - 0x01000000, 0xbefe007c, - 0xbefc0070, 0xc0611c7a, - 0x0000007c, 0xbf8cc07f, - 0x80708470, 0xbefc007e, + 0x8f7a8b77, 0x867aff7a, + 0x001f8000, 0xb97af807, + 0x86fe7e7e, 0x86ea6a6a, + 0x8f6e8378, 0xb96ee0c2, + 0xbf800002, 0xb9780002, + 0xbe801f6c, 0x866dff6d, + 0x0000ffff, 0xbefa0080, + 0xb97a0283, 0xb8faf807, + 0x867aff7a, 0x001f8000, + 0x8e7a8b7a, 0x8977ff77, + 0xfc000000, 0x87777a77, + 0xba7ff807, 0x00000000, + 0xbeee007e, 0xbeef007f, + 0xbefe0180, 0xbf900004, + 0x877a8478, 0xb97af802, + 0xbf8e0002, 0xbf88fffe, + 0xb8fa2a05, 0x807a817a, + 0x8e7a8a7a, 0xb8fb1605, + 0x807b817b, 0x8e7b867b, + 0x807a7b7a, 0x807a7e7a, + 0x827b807f, 0x867bff7b, + 0x0000ffff, 0xc04b1c3d, + 0x00000050, 0xbf8cc07f, + 0xc04b1d3d, 0x00000060, + 0xbf8cc07f, 0xc0431e7d, + 0x00000074, 0xbf8cc07f, + 0xbef4007e, 0x8675ff7f, + 0x0000ffff, 0x8775ff75, + 0x00040000, 0xbef60080, + 0xbef700ff, 0x00807fac, + 0xbef1007c, 0xbef00080, + 0xb8f02a05, 0x80708170, + 0x8e708a70, 0xb8fa1605, + 0x807a817a, 0x8e7a867a, + 0x80707a70, 0xbef60084, + 0xbef600ff, 0x01000000, 0xbefe007c, 0xbefc0070, - 0xc0611b3a, 0x0000007c, + 0xc0611c7a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611b7a, + 0xbefc0070, 0xc0611b3a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, 0xbefc0070, - 0xc0611bba, 0x0000007c, + 0xc0611b7a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611bfa, + 0xbefc0070, 0xc0611bba, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, 0xbefc0070, - 0xc0611e3a, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xb8fbf803, - 0xbefe007c, 0xbefc0070, - 0xc0611efa, 0x0000007c, + 0xc0611bfa, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611a3a, + 0xbefc0070, 0xc0611e3a, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0xb8fbf803, 0xbefe007c, + 0xbefc0070, 0xc0611efa, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, 0xbefc0070, - 0xc0611a7a, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xb8f1f801, - 0xbefe007c, 0xbefc0070, - 0xc0611c7a, 0x0000007c, + 0xc0611a3a, 0x0000007c, 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0x867aff7f, - 0x04000000, 0xbeef0080, - 0x876f6f7a, 0xb8f02a05, + 0xbefc007e, 0xbefe007c, + 0xbefc0070, 0xc0611a7a, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0xb8f1f801, 0xbefe007c, + 0xbefc0070, 0xc0611c7a, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0x867aff7f, 0x04000000, + 0xbeef0080, 0x876f6f7a, + 0xb8f02a05, 0x80708170, + 0x8e708a70, 0xb8fb1605, + 0x807b817b, 0x8e7b847b, + 0x8e76827b, 0xbef600ff, + 0x01000000, 0xbef20174, + 0x80747074, 0x82758075, + 0xbefc0080, 0xbf800000, + 0xbe802b00, 0xbe822b02, + 0xbe842b04, 0xbe862b06, + 0xbe882b08, 0xbe8a2b0a, + 0xbe8c2b0c, 0xbe8e2b0e, + 0xc06b003a, 0x00000000, + 0xbf8cc07f, 0xc06b013a, + 0x00000010, 0xbf8cc07f, + 0xc06b023a, 0x00000020, + 0xbf8cc07f, 0xc06b033a, + 0x00000030, 0xbf8cc07f, + 0x8074c074, 0x82758075, + 0x807c907c, 0xbf0a7b7c, + 0xbf85ffe7, 0xbef40172, + 0xbef00080, 0xbefe00c1, + 0xbeff00c1, 0xbee80080, + 0xbee90080, 0xbef600ff, + 0x01000000, 0x867aff78, + 0x00400000, 0xbf850003, + 0xb8faf803, 0x897a7aff, + 0x10000000, 0xbf85004d, + 0xbe840080, 0xd2890000, + 0x00000900, 0x80048104, + 0xd2890001, 0x00000900, + 0x80048104, 0xd2890002, + 0x00000900, 0x80048104, + 0xd2890003, 0x00000900, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000901, + 0x80048104, 0xd2890001, + 0x00000901, 0x80048104, + 0xd2890002, 0x00000901, + 0x80048104, 0xd2890003, + 0x00000901, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbe840080, 0xd2890000, + 0x00000902, 0x80048104, + 0xd2890001, 0x00000902, + 0x80048104, 0xd2890002, + 0x00000902, 0x80048104, + 0xd2890003, 0x00000902, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000903, + 0x80048104, 0xd2890001, + 0x00000903, 0x80048104, + 0xd2890002, 0x00000903, + 0x80048104, 0xd2890003, + 0x00000903, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbf820008, 0xe0724000, + 0x701d0000, 0xe0724100, + 0x701d0100, 0xe0724200, + 0x701d0200, 0xe0724300, + 0x701d0300, 0xbefe00c1, + 0xbeff00c1, 0xb8fb4306, + 0x867bc17b, 0xbf840063, + 0xbf8a0000, 0x867aff6f, + 0x04000000, 0xbf84005f, + 0x8e7b867b, 0x8e7b827b, + 0xbef6007b, 0xb8f02a05, 0x80708170, 0x8e708a70, - 0xb8fb1605, 0x807b817b, - 0x8e7b847b, 0x8e76827b, + 0xb8fa1605, 0x807a817a, + 0x8e7a867a, 0x80707a70, + 0x8070ff70, 0x00000080, 0xbef600ff, 0x01000000, - 0xbef20174, 0x80747074, - 0x82758075, 0xbefc0080, - 0xbf800000, 0xbe802b00, - 0xbe822b02, 0xbe842b04, - 0xbe862b06, 0xbe882b08, - 0xbe8a2b0a, 0xbe8c2b0c, - 0xbe8e2b0e, 0xc06b003a, - 0x00000000, 0xbf8cc07f, - 0xc06b013a, 0x00000010, - 0xbf8cc07f, 0xc06b023a, - 0x00000020, 0xbf8cc07f, - 0xc06b033a, 0x00000030, - 0xbf8cc07f, 0x8074c074, - 0x82758075, 0x807c907c, - 0xbf0a7b7c, 0xbf85ffe7, - 0xbef40172, 0xbef00080, - 0xbefe00c1, 0xbeff00c1, - 0xbee80080, 0xbee90080, + 0xbefc0080, 0xd28c0002, + 0x000100c1, 0xd28d0003, + 0x000204c1, 0x867aff78, + 0x00400000, 0xbf850003, + 0xb8faf803, 0x897a7aff, + 0x10000000, 0xbf850030, + 0x24040682, 0xd86e4000, + 0x00000002, 0xbf8cc07f, + 0xbe840080, 0xd2890000, + 0x00000900, 0x80048104, + 0xd2890001, 0x00000900, + 0x80048104, 0xd2890002, + 0x00000900, 0x80048104, + 0xd2890003, 0x00000900, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000901, + 0x80048104, 0xd2890001, + 0x00000901, 0x80048104, + 0xd2890002, 0x00000901, + 0x80048104, 0xd2890003, + 0x00000901, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0x680404ff, 0x00000200, + 0xd0c9006a, 0x0000f702, + 0xbf87ffd2, 0xbf820015, + 0xd1060002, 0x00011103, + 0x7e0602ff, 0x00000200, + 0xbefc00ff, 0x00010000, + 0xbe800077, 0x8677ff77, + 0xff7fffff, 0x8777ff77, + 0x00058000, 0xd8ec0000, + 0x00000002, 0xbf8cc07f, + 0xe0765000, 0x701d0002, + 0x68040702, 0xd0c9006a, + 0x0000f702, 0xbf87fff7, + 0xbef70000, 0xbef000ff, + 0x00000400, 0xbefe00c1, + 0xbeff00c1, 0xb8fb2a05, + 0x807b817b, 0x8e7b827b, 0xbef600ff, 0x01000000, + 0xbefc0084, 0xbf0a7b7c, + 0xbf84006d, 0xbf11017c, + 0x807bff7b, 0x00001000, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, 0x10000000, - 0xbf85004d, 0xbe840080, + 0xbf850051, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, 0x80048104, @@ -460,224 +568,119 @@ static const uint32_t cwsr_trap_gfx9_hex[] = { 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbf820008, + 0xbf84ffee, 0x807c847c, + 0xbf0a7b7c, 0xbf85ffb1, + 0xbf9c0000, 0xbf820012, + 0x7e000300, 0x7e020301, + 0x7e040302, 0x7e060303, 0xe0724000, 0x701d0000, 0xe0724100, 0x701d0100, 0xe0724200, 0x701d0200, 0xe0724300, 0x701d0300, + 0x807c847c, 0x8070ff70, + 0x00000400, 0xbf0a7b7c, + 0xbf85ffef, 0xbf9c0000, + 0xbf8200c7, 0xbef4007e, + 0x8675ff7f, 0x0000ffff, + 0x8775ff75, 0x00040000, + 0xbef60080, 0xbef700ff, + 0x00807fac, 0x866eff7f, + 0x04000000, 0xbf84001e, 0xbefe00c1, 0xbeff00c1, - 0xb8fb4306, 0x867bc17b, - 0xbf840063, 0xbf8a0000, - 0x867aff6f, 0x04000000, - 0xbf84005f, 0x8e7b867b, - 0x8e7b827b, 0xbef6007b, - 0xb8f02a05, 0x80708170, - 0x8e708a70, 0xb8fa1605, - 0x807a817a, 0x8e7a867a, - 0x80707a70, 0x8070ff70, + 0xb8ef4306, 0x866fc16f, + 0xbf840019, 0x8e6f866f, + 0x8e6f826f, 0xbef6006f, + 0xb8f82a05, 0x80788178, + 0x8e788a78, 0xb8ee1605, + 0x806e816e, 0x8e6e866e, + 0x80786e78, 0x8078ff78, 0x00000080, 0xbef600ff, 0x01000000, 0xbefc0080, - 0xd28c0002, 0x000100c1, - 0xd28d0003, 0x000204c1, - 0x867aff78, 0x00400000, - 0xbf850003, 0xb8faf803, - 0x897a7aff, 0x10000000, - 0xbf850030, 0x24040682, - 0xd86e4000, 0x00000002, - 0xbf8cc07f, 0xbe840080, - 0xd2890000, 0x00000900, - 0x80048104, 0xd2890001, - 0x00000900, 0x80048104, - 0xd2890002, 0x00000900, - 0x80048104, 0xd2890003, - 0x00000900, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0xbe840080, 0xd2890000, - 0x00000901, 0x80048104, - 0xd2890001, 0x00000901, - 0x80048104, 0xd2890002, - 0x00000901, 0x80048104, - 0xd2890003, 0x00000901, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0x680404ff, - 0x00000200, 0xd0c9006a, - 0x0000f702, 0xbf87ffd2, - 0xbf820015, 0xd1060002, - 0x00011103, 0x7e0602ff, - 0x00000200, 0xbefc00ff, - 0x00010000, 0xbe800077, - 0x8677ff77, 0xff7fffff, - 0x8777ff77, 0x00058000, - 0xd8ec0000, 0x00000002, - 0xbf8cc07f, 0xe0765000, - 0x701d0002, 0x68040702, - 0xd0c9006a, 0x0000f702, - 0xbf87fff7, 0xbef70000, - 0xbef000ff, 0x00000400, + 0xe0510000, 0x781d0000, + 0xe0510100, 0x781d0000, + 0x807cff7c, 0x00000200, + 0x8078ff78, 0x00000200, + 0xbf0a6f7c, 0xbf85fff6, 0xbefe00c1, 0xbeff00c1, - 0xb8fb2a05, 0x807b817b, - 0x8e7b827b, 0xbef600ff, - 0x01000000, 0xbefc0084, - 0xbf0a7b7c, 0xbf84006d, - 0xbf11017c, 0x807bff7b, - 0x00001000, 0x867aff78, - 0x00400000, 0xbf850003, - 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf850051, - 0xbe840080, 0xd2890000, - 0x00000900, 0x80048104, - 0xd2890001, 0x00000900, - 0x80048104, 0xd2890002, - 0x00000900, 0x80048104, - 0xd2890003, 0x00000900, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000901, - 0x80048104, 0xd2890001, - 0x00000901, 0x80048104, - 0xd2890002, 0x00000901, - 0x80048104, 0xd2890003, - 0x00000901, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0xbe840080, 0xd2890000, - 0x00000902, 0x80048104, - 0xd2890001, 0x00000902, - 0x80048104, 0xd2890002, - 0x00000902, 0x80048104, - 0xd2890003, 0x00000902, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000903, - 0x80048104, 0xd2890001, - 0x00000903, 0x80048104, - 0xd2890002, 0x00000903, - 0x80048104, 0xd2890003, - 0x00000903, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0x807c847c, 0xbf0a7b7c, - 0xbf85ffb1, 0xbf9c0000, - 0xbf820012, 0x7e000300, - 0x7e020301, 0x7e040302, - 0x7e060303, 0xe0724000, - 0x701d0000, 0xe0724100, - 0x701d0100, 0xe0724200, - 0x701d0200, 0xe0724300, - 0x701d0300, 0x807c847c, - 0x8070ff70, 0x00000400, - 0xbf0a7b7c, 0xbf85ffef, - 0xbf9c0000, 0xbf8200c7, - 0xbef4007e, 0x8675ff7f, - 0x0000ffff, 0x8775ff75, - 0x00040000, 0xbef60080, - 0xbef700ff, 0x00807fac, - 0x866eff7f, 0x04000000, - 0xbf84001e, 0xbefe00c1, - 0xbeff00c1, 0xb8ef4306, - 0x866fc16f, 0xbf840019, - 0x8e6f866f, 0x8e6f826f, - 0xbef6006f, 0xb8f82a05, + 0xbef600ff, 0x01000000, + 0xb8ef2a05, 0x806f816f, + 0x8e6f826f, 0x806fff6f, + 0x00008000, 0xbef80080, + 0xbeee0078, 0x8078ff78, + 0x00000400, 0xbefc0084, + 0xbf11087c, 0xe0524000, + 0x781d0000, 0xe0524100, + 0x781d0100, 0xe0524200, + 0x781d0200, 0xe0524300, + 0x781d0300, 0xbf8c0f70, + 0x7e000300, 0x7e020301, + 0x7e040302, 0x7e060303, + 0x807c847c, 0x8078ff78, + 0x00000400, 0xbf0a6f7c, + 0xbf85ffee, 0xbf9c0000, + 0xe0524000, 0x6e1d0000, + 0xe0524100, 0x6e1d0100, + 0xe0524200, 0x6e1d0200, + 0xe0524300, 0x6e1d0300, + 0xbf8c0f70, 0xb8f82a05, 0x80788178, 0x8e788a78, 0xb8ee1605, 0x806e816e, 0x8e6e866e, 0x80786e78, - 0x8078ff78, 0x00000080, - 0xbef600ff, 0x01000000, - 0xbefc0080, 0xe0510000, - 0x781d0000, 0xe0510100, - 0x781d0000, 0x807cff7c, - 0x00000200, 0x8078ff78, - 0x00000200, 0xbf0a6f7c, - 0xbf85fff6, 0xbefe00c1, - 0xbeff00c1, 0xbef600ff, - 0x01000000, 0xb8ef2a05, - 0x806f816f, 0x8e6f826f, - 0x806fff6f, 0x00008000, - 0xbef80080, 0xbeee0078, - 0x8078ff78, 0x00000400, - 0xbefc0084, 0xbf11087c, - 0xe0524000, 0x781d0000, - 0xe0524100, 0x781d0100, - 0xe0524200, 0x781d0200, - 0xe0524300, 0x781d0300, - 0xbf8c0f70, 0x7e000300, - 0x7e020301, 0x7e040302, - 0x7e060303, 0x807c847c, - 0x8078ff78, 0x00000400, - 0xbf0a6f7c, 0xbf85ffee, - 0xbf9c0000, 0xe0524000, - 0x6e1d0000, 0xe0524100, - 0x6e1d0100, 0xe0524200, - 0x6e1d0200, 0xe0524300, - 0x6e1d0300, 0xbf8c0f70, + 0x80f8c078, 0xb8ef1605, + 0x806f816f, 0x8e6f846f, + 0x8e76826f, 0xbef600ff, + 0x01000000, 0xbefc006f, + 0xc031003a, 0x00000078, + 0x80f8c078, 0xbf8cc07f, + 0x80fc907c, 0xbf800000, + 0xbe802d00, 0xbe822d02, + 0xbe842d04, 0xbe862d06, + 0xbe882d08, 0xbe8a2d0a, + 0xbe8c2d0c, 0xbe8e2d0e, + 0xbf06807c, 0xbf84fff0, 0xb8f82a05, 0x80788178, 0x8e788a78, 0xb8ee1605, 0x806e816e, 0x8e6e866e, - 0x80786e78, 0x80f8c078, - 0xb8ef1605, 0x806f816f, - 0x8e6f846f, 0x8e76826f, + 0x80786e78, 0xbef60084, 0xbef600ff, 0x01000000, - 0xbefc006f, 0xc031003a, - 0x00000078, 0x80f8c078, - 0xbf8cc07f, 0x80fc907c, - 0xbf800000, 0xbe802d00, - 0xbe822d02, 0xbe842d04, - 0xbe862d06, 0xbe882d08, - 0xbe8a2d0a, 0xbe8c2d0c, - 0xbe8e2d0e, 0xbf06807c, - 0xbf84fff0, 0xb8f82a05, - 0x80788178, 0x8e788a78, - 0xb8ee1605, 0x806e816e, - 0x8e6e866e, 0x80786e78, - 0xbef60084, 0xbef600ff, - 0x01000000, 0xc0211bfa, + 0xc0211bfa, 0x00000078, + 0x80788478, 0xc0211b3a, 0x00000078, 0x80788478, - 0xc0211b3a, 0x00000078, - 0x80788478, 0xc0211b7a, + 0xc0211b7a, 0x00000078, + 0x80788478, 0xc0211c3a, 0x00000078, 0x80788478, - 0xc0211c3a, 0x00000078, - 0x80788478, 0xc0211c7a, + 0xc0211c7a, 0x00000078, + 0x80788478, 0xc0211eba, 0x00000078, 0x80788478, - 0xc0211eba, 0x00000078, - 0x80788478, 0xc0211efa, + 0xc0211efa, 0x00000078, + 0x80788478, 0xc0211a3a, 0x00000078, 0x80788478, - 0xc0211a3a, 0x00000078, - 0x80788478, 0xc0211a7a, + 0xc0211a7a, 0x00000078, + 0x80788478, 0xc0211cfa, 0x00000078, 0x80788478, - 0xc0211cfa, 0x00000078, - 0x80788478, 0xbf8cc07f, - 0xbefc006f, 0xbefe0070, - 0xbeff0071, 0x866f7bff, - 0x000003ff, 0xb96f4803, - 0x866f7bff, 0xfffff800, - 0x8f6f8b6f, 0xb96fa2c3, - 0xb973f801, 0xb8ee2a05, - 0x806e816e, 0x8e6e8a6e, - 0xb8ef1605, 0x806f816f, - 0x8e6f866f, 0x806e6f6e, - 0x806e746e, 0x826f8075, - 0x866fff6f, 0x0000ffff, - 0xc00b1c37, 0x00000050, - 0xc00b1d37, 0x00000060, - 0xc0031e77, 0x00000074, - 0xbf8cc07f, 0x8f6e8b77, - 0x866eff6e, 0x001f8000, - 0xb96ef807, 0x866dff6d, - 0x0000ffff, 0x86fe7e7e, - 0x86ea6a6a, 0x8f6e837a, - 0xb96ee0c2, 0xbf800002, - 0xb97a0002, 0xbf8a0000, - 0xbe801f6c, 0xbf9b0000, + 0xbf8cc07f, 0xbefc006f, + 0xbefe0070, 0xbeff0071, + 0x866f7bff, 0x000003ff, + 0xb96f4803, 0x866f7bff, + 0xfffff800, 0x8f6f8b6f, + 0xb96fa2c3, 0xb973f801, + 0xb8ee2a05, 0x806e816e, + 0x8e6e8a6e, 0xb8ef1605, + 0x806f816f, 0x8e6f866f, + 0x806e6f6e, 0x806e746e, + 0x826f8075, 0x866fff6f, + 0x0000ffff, 0xc00b1c37, + 0x00000050, 0xc00b1d37, + 0x00000060, 0xc0031e77, + 0x00000074, 0xbf8cc07f, + 0x8f6e8b77, 0x866eff6e, + 0x001f8000, 0xb96ef807, + 0x866dff6d, 0x0000ffff, + 0x86fe7e7e, 0x86ea6a6a, + 0x8f6e837a, 0xb96ee0c2, + 0xbf800002, 0xb97a0002, + 0xbf8a0000, 0xbe801f6c, + 0xbf810000, 0x00000000, }; static const uint32_t cwsr_trap_nv1x_hex[] = { @@ -1305,219 +1308,159 @@ static const uint32_t cwsr_trap_nv1x_hex[] = { }; static const uint32_t cwsr_trap_arcturus_hex[] = { - 0xbf820001, 0xbf8202da, + 0xbf820001, 0xbf8202df, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, 0x866eff78, 0x00002000, 0xbf840009, 0x866eff6d, - 0x00ff0000, 0xbf85001e, + 0x00ff0000, 0xbf850023, 0x866eff7b, 0x00000400, - 0xbf85005b, 0xbf8e0010, + 0xbf850060, 0xbf8e0010, 0xb8fbf803, 0xbf82fffa, 0x866eff7b, 0x03c00900, - 0xbf850015, 0x866eff7b, - 0x000071ff, 0xbf840008, - 0x866fff7b, 0x00007080, - 0xbf840001, 0xbeee1a87, - 0xb8eff801, 0x8e6e8c6e, - 0x866e6f6e, 0xbf85000a, - 0x866eff6d, 0x00ff0000, - 0xbf850007, 0xb8eef801, - 0x866eff6e, 0x00000800, - 0xbf850003, 0x866eff7b, - 0x00000400, 0xbf850040, - 0xb8faf807, 0x867aff7a, - 0x001f8000, 0x8e7a8b7a, - 0x8977ff77, 0xfc000000, - 0x87777a77, 0xba7ff807, - 0x00000000, 0xb8faf812, - 0xb8fbf813, 0x8efa887a, - 0xbf0d8f7b, 0xbf840002, - 0x877bff7b, 0xffff0000, - 0xc0031c3d, 0x00000010, - 0xc0071bbd, 0x00000000, - 0xc0071ebd, 0x00000008, - 0xbf8cc07f, 0x8671ff6d, - 0x01000000, 0xbf840004, - 0x92f1ff70, 0x00010001, - 0xbf840016, 0xbf820005, - 0x86708170, 0x8e709770, - 0x8977ff77, 0x00800000, - 0x87777077, 0x86ee6e6e, - 0xbf840001, 0xbe801d6e, - 0x866eff6d, 0x01ff0000, - 0xbf850005, 0x8778ff78, - 0x00002000, 0x80ec886c, - 0x82ed806d, 0xbf820005, - 0x866eff6d, 0x01000000, - 0xbf850002, 0x806c846c, - 0x826d806d, 0x866dff6d, - 0x0000ffff, 0x8f7a8b77, + 0xbf85001a, 0x866eff6d, + 0x01ff0000, 0xbf06ff6e, + 0x01040000, 0xbf850015, + 0x866eff7b, 0x000071ff, + 0xbf840008, 0x866fff7b, + 0x00007080, 0xbf840001, + 0xbeee1a87, 0xb8eff801, + 0x8e6e8c6e, 0x866e6f6e, + 0xbf85000a, 0x866eff6d, + 0x00ff0000, 0xbf850007, + 0xb8eef801, 0x866eff6e, + 0x00000800, 0xbf850003, + 0x866eff7b, 0x00000400, + 0xbf850040, 0xb8faf807, 0x867aff7a, 0x001f8000, - 0xb97af807, 0x86fe7e7e, - 0x86ea6a6a, 0x8f6e8378, - 0xb96ee0c2, 0xbf800002, - 0xb9780002, 0xbe801f6c, + 0x8e7a8b7a, 0x8977ff77, + 0xfc000000, 0x87777a77, + 0xba7ff807, 0x00000000, + 0xb8faf812, 0xb8fbf813, + 0x8efa887a, 0xbf0d8f7b, + 0xbf840002, 0x877bff7b, + 0xffff0000, 0xc0031c3d, + 0x00000010, 0xc0071bbd, + 0x00000000, 0xc0071ebd, + 0x00000008, 0xbf8cc07f, + 0x8671ff6d, 0x01000000, + 0xbf840004, 0x92f1ff70, + 0x00010001, 0xbf840016, + 0xbf820005, 0x86708170, + 0x8e709770, 0x8977ff77, + 0x00800000, 0x87777077, + 0x86ee6e6e, 0xbf840001, + 0xbe801d6e, 0x866eff6d, + 0x01ff0000, 0xbf850005, + 0x8778ff78, 0x00002000, + 0x80ec886c, 0x82ed806d, + 0xbf820005, 0x866eff6d, + 0x01000000, 0xbf850002, + 0x806c846c, 0x826d806d, 0x866dff6d, 0x0000ffff, - 0xbefa0080, 0xb97a0283, - 0xb8faf807, 0x867aff7a, - 0x001f8000, 0x8e7a8b7a, - 0x8977ff77, 0xfc000000, - 0x87777a77, 0xba7ff807, - 0x00000000, 0xbeee007e, - 0xbeef007f, 0xbefe0180, - 0xbf900004, 0x877a8478, - 0xb97af802, 0xbf8e0002, - 0xbf88fffe, 0xb8fa2a05, - 0x807a817a, 0x8e7a8a7a, - 0x8e7a817a, 0xb8fb1605, - 0x807b817b, 0x8e7b867b, - 0x807a7b7a, 0x807a7e7a, - 0x827b807f, 0x867bff7b, - 0x0000ffff, 0xc04b1c3d, - 0x00000050, 0xbf8cc07f, - 0xc04b1d3d, 0x00000060, - 0xbf8cc07f, 0xc0431e7d, - 0x00000074, 0xbf8cc07f, - 0xbef4007e, 0x8675ff7f, - 0x0000ffff, 0x8775ff75, - 0x00040000, 0xbef60080, - 0xbef700ff, 0x00807fac, - 0xbef1007c, 0xbef00080, - 0xb8f02a05, 0x80708170, - 0x8e708a70, 0x8e708170, - 0xb8fa1605, 0x807a817a, - 0x8e7a867a, 0x80707a70, - 0xbef60084, 0xbef600ff, - 0x01000000, 0xbefe007c, - 0xbefc0070, 0xc0611c7a, - 0x0000007c, 0xbf8cc07f, - 0x80708470, 0xbefc007e, + 0x8f7a8b77, 0x867aff7a, + 0x001f8000, 0xb97af807, + 0x86fe7e7e, 0x86ea6a6a, + 0x8f6e8378, 0xb96ee0c2, + 0xbf800002, 0xb9780002, + 0xbe801f6c, 0x866dff6d, + 0x0000ffff, 0xbefa0080, + 0xb97a0283, 0xb8faf807, + 0x867aff7a, 0x001f8000, + 0x8e7a8b7a, 0x8977ff77, + 0xfc000000, 0x87777a77, + 0xba7ff807, 0x00000000, + 0xbeee007e, 0xbeef007f, + 0xbefe0180, 0xbf900004, + 0x877a8478, 0xb97af802, + 0xbf8e0002, 0xbf88fffe, + 0xb8fa2a05, 0x807a817a, + 0x8e7a8a7a, 0x8e7a817a, + 0xb8fb1605, 0x807b817b, + 0x8e7b867b, 0x807a7b7a, + 0x807a7e7a, 0x827b807f, + 0x867bff7b, 0x0000ffff, + 0xc04b1c3d, 0x00000050, + 0xbf8cc07f, 0xc04b1d3d, + 0x00000060, 0xbf8cc07f, + 0xc0431e7d, 0x00000074, + 0xbf8cc07f, 0xbef4007e, + 0x8675ff7f, 0x0000ffff, + 0x8775ff75, 0x00040000, + 0xbef60080, 0xbef700ff, + 0x00807fac, 0xbef1007c, + 0xbef00080, 0xb8f02a05, + 0x80708170, 0x8e708a70, + 0x8e708170, 0xb8fa1605, + 0x807a817a, 0x8e7a867a, + 0x80707a70, 0xbef60084, + 0xbef600ff, 0x01000000, 0xbefe007c, 0xbefc0070, - 0xc0611b3a, 0x0000007c, + 0xc0611c7a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611b7a, + 0xbefc0070, 0xc0611b3a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, 0xbefc0070, - 0xc0611bba, 0x0000007c, + 0xc0611b7a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611bfa, + 0xbefc0070, 0xc0611bba, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, 0xbefc0070, - 0xc0611e3a, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xb8fbf803, - 0xbefe007c, 0xbefc0070, - 0xc0611efa, 0x0000007c, + 0xc0611bfa, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611a3a, + 0xbefc0070, 0xc0611e3a, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0xb8fbf803, 0xbefe007c, + 0xbefc0070, 0xc0611efa, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, 0xbefc0070, - 0xc0611a7a, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xb8f1f801, - 0xbefe007c, 0xbefc0070, - 0xc0611c7a, 0x0000007c, + 0xc0611a3a, 0x0000007c, 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0x867aff7f, - 0x04000000, 0xbeef0080, - 0x876f6f7a, 0xb8f02a05, - 0x80708170, 0x8e708a70, - 0x8e708170, 0xb8fb1605, - 0x807b817b, 0x8e7b847b, - 0x8e76827b, 0xbef600ff, - 0x01000000, 0xbef20174, - 0x80747074, 0x82758075, - 0xbefc0080, 0xbf800000, - 0xbe802b00, 0xbe822b02, - 0xbe842b04, 0xbe862b06, - 0xbe882b08, 0xbe8a2b0a, - 0xbe8c2b0c, 0xbe8e2b0e, - 0xc06b003a, 0x00000000, - 0xbf8cc07f, 0xc06b013a, - 0x00000010, 0xbf8cc07f, - 0xc06b023a, 0x00000020, - 0xbf8cc07f, 0xc06b033a, - 0x00000030, 0xbf8cc07f, - 0x8074c074, 0x82758075, - 0x807c907c, 0xbf0a7b7c, - 0xbf85ffe7, 0xbef40172, - 0xbef00080, 0xbefe00c1, - 0xbeff00c1, 0xbee80080, - 0xbee90080, 0xbef600ff, - 0x01000000, 0x867aff78, - 0x00400000, 0xbf850003, - 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf85004d, - 0xbe840080, 0xd2890000, - 0x00000900, 0x80048104, - 0xd2890001, 0x00000900, - 0x80048104, 0xd2890002, - 0x00000900, 0x80048104, - 0xd2890003, 0x00000900, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000901, - 0x80048104, 0xd2890001, - 0x00000901, 0x80048104, - 0xd2890002, 0x00000901, - 0x80048104, 0xd2890003, - 0x00000901, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0xbe840080, 0xd2890000, - 0x00000902, 0x80048104, - 0xd2890001, 0x00000902, - 0x80048104, 0xd2890002, - 0x00000902, 0x80048104, - 0xd2890003, 0x00000902, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000903, - 0x80048104, 0xd2890001, - 0x00000903, 0x80048104, - 0xd2890002, 0x00000903, - 0x80048104, 0xd2890003, - 0x00000903, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0xbf820008, 0xe0724000, - 0x701d0000, 0xe0724100, - 0x701d0100, 0xe0724200, - 0x701d0200, 0xe0724300, - 0x701d0300, 0xbefe00c1, - 0xbeff00c1, 0xb8fb4306, - 0x867bc17b, 0xbf840064, - 0xbf8a0000, 0x867aff6f, - 0x04000000, 0xbf840060, - 0x8e7b867b, 0x8e7b827b, - 0xbef6007b, 0xb8f02a05, - 0x80708170, 0x8e708a70, - 0x8e708170, 0xb8fa1605, - 0x807a817a, 0x8e7a867a, - 0x80707a70, 0x8070ff70, - 0x00000080, 0xbef600ff, - 0x01000000, 0xbefc0080, - 0xd28c0002, 0x000100c1, - 0xd28d0003, 0x000204c1, + 0xbefc007e, 0xbefe007c, + 0xbefc0070, 0xc0611a7a, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0xb8f1f801, 0xbefe007c, + 0xbefc0070, 0xc0611c7a, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0x867aff7f, 0x04000000, + 0xbeef0080, 0x876f6f7a, + 0xb8f02a05, 0x80708170, + 0x8e708a70, 0x8e708170, + 0xb8fb1605, 0x807b817b, + 0x8e7b847b, 0x8e76827b, + 0xbef600ff, 0x01000000, + 0xbef20174, 0x80747074, + 0x82758075, 0xbefc0080, + 0xbf800000, 0xbe802b00, + 0xbe822b02, 0xbe842b04, + 0xbe862b06, 0xbe882b08, + 0xbe8a2b0a, 0xbe8c2b0c, + 0xbe8e2b0e, 0xc06b003a, + 0x00000000, 0xbf8cc07f, + 0xc06b013a, 0x00000010, + 0xbf8cc07f, 0xc06b023a, + 0x00000020, 0xbf8cc07f, + 0xc06b033a, 0x00000030, + 0xbf8cc07f, 0x8074c074, + 0x82758075, 0x807c907c, + 0xbf0a7b7c, 0xbf85ffe7, + 0xbef40172, 0xbef00080, + 0xbefe00c1, 0xbeff00c1, + 0xbee80080, 0xbee90080, + 0xbef600ff, 0x01000000, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, 0x10000000, - 0xbf850030, 0x24040682, - 0xd86e4000, 0x00000002, - 0xbf8cc07f, 0xbe840080, + 0xbf85004d, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, 0x80048104, @@ -1536,31 +1479,50 @@ static const uint32_t cwsr_trap_arcturus_hex[] = { 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, - 0xbf84ffee, 0x680404ff, - 0x00000200, 0xd0c9006a, - 0x0000f702, 0xbf87ffd2, - 0xbf820015, 0xd1060002, - 0x00011103, 0x7e0602ff, - 0x00000200, 0xbefc00ff, - 0x00010000, 0xbe800077, - 0x8677ff77, 0xff7fffff, - 0x8777ff77, 0x00058000, - 0xd8ec0000, 0x00000002, - 0xbf8cc07f, 0xe0765000, - 0x701d0002, 0x68040702, - 0xd0c9006a, 0x0000f702, - 0xbf87fff7, 0xbef70000, - 0xbef000ff, 0x00000400, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000902, + 0x80048104, 0xd2890001, + 0x00000902, 0x80048104, + 0xd2890002, 0x00000902, + 0x80048104, 0xd2890003, + 0x00000902, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbe840080, 0xd2890000, + 0x00000903, 0x80048104, + 0xd2890001, 0x00000903, + 0x80048104, 0xd2890002, + 0x00000903, 0x80048104, + 0xd2890003, 0x00000903, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbf820008, + 0xe0724000, 0x701d0000, + 0xe0724100, 0x701d0100, + 0xe0724200, 0x701d0200, + 0xe0724300, 0x701d0300, 0xbefe00c1, 0xbeff00c1, - 0xb8fb2a05, 0x807b817b, - 0x8e7b827b, 0xbef600ff, - 0x01000000, 0xbefc0084, - 0xbf0a7b7c, 0xbf84006d, - 0xbf11017c, 0x807bff7b, - 0x00001000, 0x867aff78, + 0xb8fb4306, 0x867bc17b, + 0xbf840064, 0xbf8a0000, + 0x867aff6f, 0x04000000, + 0xbf840060, 0x8e7b867b, + 0x8e7b827b, 0xbef6007b, + 0xb8f02a05, 0x80708170, + 0x8e708a70, 0x8e708170, + 0xb8fa1605, 0x807a817a, + 0x8e7a867a, 0x80707a70, + 0x8070ff70, 0x00000080, + 0xbef600ff, 0x01000000, + 0xbefc0080, 0xd28c0002, + 0x000100c1, 0xd28d0003, + 0x000204c1, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf850051, + 0x10000000, 0xbf850030, + 0x24040682, 0xd86e4000, + 0x00000002, 0xbf8cc07f, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, @@ -1580,427 +1542,411 @@ static const uint32_t cwsr_trap_arcturus_hex[] = { 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, - 0xbe840080, 0xd2890000, - 0x00000902, 0x80048104, - 0xd2890001, 0x00000902, - 0x80048104, 0xd2890002, - 0x00000902, 0x80048104, - 0xd2890003, 0x00000902, + 0x680404ff, 0x00000200, + 0xd0c9006a, 0x0000f702, + 0xbf87ffd2, 0xbf820015, + 0xd1060002, 0x00011103, + 0x7e0602ff, 0x00000200, + 0xbefc00ff, 0x00010000, + 0xbe800077, 0x8677ff77, + 0xff7fffff, 0x8777ff77, + 0x00058000, 0xd8ec0000, + 0x00000002, 0xbf8cc07f, + 0xe0765000, 0x701d0002, + 0x68040702, 0xd0c9006a, + 0x0000f702, 0xbf87fff7, + 0xbef70000, 0xbef000ff, + 0x00000400, 0xbefe00c1, + 0xbeff00c1, 0xb8fb2a05, + 0x807b817b, 0x8e7b827b, + 0xbef600ff, 0x01000000, + 0xbefc0084, 0xbf0a7b7c, + 0xbf84006d, 0xbf11017c, + 0x807bff7b, 0x00001000, + 0x867aff78, 0x00400000, + 0xbf850003, 0xb8faf803, + 0x897a7aff, 0x10000000, + 0xbf850051, 0xbe840080, + 0xd2890000, 0x00000900, + 0x80048104, 0xd2890001, + 0x00000900, 0x80048104, + 0xd2890002, 0x00000900, + 0x80048104, 0xd2890003, + 0x00000900, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbe840080, 0xd2890000, + 0x00000901, 0x80048104, + 0xd2890001, 0x00000901, + 0x80048104, 0xd2890002, + 0x00000901, 0x80048104, + 0xd2890003, 0x00000901, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000903, + 0xd2890000, 0x00000902, 0x80048104, 0xd2890001, - 0x00000903, 0x80048104, - 0xd2890002, 0x00000903, + 0x00000902, 0x80048104, + 0xd2890002, 0x00000902, 0x80048104, 0xd2890003, - 0x00000903, 0x80048104, + 0x00000902, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, - 0x807c847c, 0xbf0a7b7c, - 0xbf85ffb1, 0xbf9c0000, - 0xbf820012, 0x7e000300, - 0x7e020301, 0x7e040302, - 0x7e060303, 0xe0724000, - 0x701d0000, 0xe0724100, - 0x701d0100, 0xe0724200, - 0x701d0200, 0xe0724300, - 0x701d0300, 0x807c847c, - 0x8070ff70, 0x00000400, - 0xbf0a7b7c, 0xbf85ffef, - 0xbf9c0000, 0xbefc0080, - 0xbf11017c, 0x867aff78, - 0x00400000, 0xbf850003, - 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf850059, - 0xd3d84000, 0x18000100, - 0xd3d84001, 0x18000101, - 0xd3d84002, 0x18000102, - 0xd3d84003, 0x18000103, 0xbe840080, 0xd2890000, - 0x00000900, 0x80048104, - 0xd2890001, 0x00000900, + 0x00000903, 0x80048104, + 0xd2890001, 0x00000903, 0x80048104, 0xd2890002, - 0x00000900, 0x80048104, - 0xd2890003, 0x00000900, + 0x00000903, 0x80048104, + 0xd2890003, 0x00000903, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000901, + 0xbf84ffee, 0x807c847c, + 0xbf0a7b7c, 0xbf85ffb1, + 0xbf9c0000, 0xbf820012, + 0x7e000300, 0x7e020301, + 0x7e040302, 0x7e060303, + 0xe0724000, 0x701d0000, + 0xe0724100, 0x701d0100, + 0xe0724200, 0x701d0200, + 0xe0724300, 0x701d0300, + 0x807c847c, 0x8070ff70, + 0x00000400, 0xbf0a7b7c, + 0xbf85ffef, 0xbf9c0000, + 0xbefc0080, 0xbf11017c, + 0x867aff78, 0x00400000, + 0xbf850003, 0xb8faf803, + 0x897a7aff, 0x10000000, + 0xbf850059, 0xd3d84000, + 0x18000100, 0xd3d84001, + 0x18000101, 0xd3d84002, + 0x18000102, 0xd3d84003, + 0x18000103, 0xbe840080, + 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, - 0x00000901, 0x80048104, - 0xd2890002, 0x00000901, + 0x00000900, 0x80048104, + 0xd2890002, 0x00000900, 0x80048104, 0xd2890003, - 0x00000901, 0x80048104, + 0x00000900, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, 0xd2890000, - 0x00000902, 0x80048104, - 0xd2890001, 0x00000902, + 0x00000901, 0x80048104, + 0xd2890001, 0x00000901, 0x80048104, 0xd2890002, - 0x00000902, 0x80048104, - 0xd2890003, 0x00000902, + 0x00000901, 0x80048104, + 0xd2890003, 0x00000901, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000903, + 0xd2890000, 0x00000902, 0x80048104, 0xd2890001, - 0x00000903, 0x80048104, - 0xd2890002, 0x00000903, + 0x00000902, 0x80048104, + 0xd2890002, 0x00000902, 0x80048104, 0xd2890003, - 0x00000903, 0x80048104, + 0x00000902, 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, - 0x807c847c, 0xbf0a7b7c, - 0xbf85ffa9, 0xbf9c0000, - 0xbf820016, 0xd3d84000, - 0x18000100, 0xd3d84001, - 0x18000101, 0xd3d84002, - 0x18000102, 0xd3d84003, - 0x18000103, 0xe0724000, - 0x701d0000, 0xe0724100, - 0x701d0100, 0xe0724200, - 0x701d0200, 0xe0724300, - 0x701d0300, 0x807c847c, - 0x8070ff70, 0x00000400, - 0xbf0a7b7c, 0xbf85ffeb, - 0xbf9c0000, 0xbf8200e3, - 0xbef4007e, 0x8675ff7f, - 0x0000ffff, 0x8775ff75, - 0x00040000, 0xbef60080, - 0xbef700ff, 0x00807fac, - 0x866eff7f, 0x04000000, - 0xbf84001f, 0xbefe00c1, - 0xbeff00c1, 0xb8ef4306, - 0x866fc16f, 0xbf84001a, - 0x8e6f866f, 0x8e6f826f, - 0xbef6006f, 0xb8f82a05, - 0x80788178, 0x8e788a78, - 0x8e788178, 0xb8ee1605, - 0x806e816e, 0x8e6e866e, - 0x80786e78, 0x8078ff78, - 0x00000080, 0xbef600ff, - 0x01000000, 0xbefc0080, - 0xe0510000, 0x781d0000, - 0xe0510100, 0x781d0000, - 0x807cff7c, 0x00000200, - 0x8078ff78, 0x00000200, - 0xbf0a6f7c, 0xbf85fff6, + 0xbe840080, 0xd2890000, + 0x00000903, 0x80048104, + 0xd2890001, 0x00000903, + 0x80048104, 0xd2890002, + 0x00000903, 0x80048104, + 0xd2890003, 0x00000903, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0x807c847c, + 0xbf0a7b7c, 0xbf85ffa9, + 0xbf9c0000, 0xbf820016, + 0xd3d84000, 0x18000100, + 0xd3d84001, 0x18000101, + 0xd3d84002, 0x18000102, + 0xd3d84003, 0x18000103, + 0xe0724000, 0x701d0000, + 0xe0724100, 0x701d0100, + 0xe0724200, 0x701d0200, + 0xe0724300, 0x701d0300, + 0x807c847c, 0x8070ff70, + 0x00000400, 0xbf0a7b7c, + 0xbf85ffeb, 0xbf9c0000, + 0xbf8200e3, 0xbef4007e, + 0x8675ff7f, 0x0000ffff, + 0x8775ff75, 0x00040000, + 0xbef60080, 0xbef700ff, + 0x00807fac, 0x866eff7f, + 0x04000000, 0xbf84001f, 0xbefe00c1, 0xbeff00c1, + 0xb8ef4306, 0x866fc16f, + 0xbf84001a, 0x8e6f866f, + 0x8e6f826f, 0xbef6006f, + 0xb8f82a05, 0x80788178, + 0x8e788a78, 0x8e788178, + 0xb8ee1605, 0x806e816e, + 0x8e6e866e, 0x80786e78, + 0x8078ff78, 0x00000080, 0xbef600ff, 0x01000000, - 0xb8ef2a05, 0x806f816f, - 0x8e6f826f, 0x806fff6f, - 0x00008000, 0xbef80080, - 0xbeee0078, 0x8078ff78, - 0x00000400, 0xbefc0084, - 0xbf11087c, 0xe0524000, - 0x781d0000, 0xe0524100, - 0x781d0100, 0xe0524200, - 0x781d0200, 0xe0524300, - 0x781d0300, 0xbf8c0f70, - 0x7e000300, 0x7e020301, - 0x7e040302, 0x7e060303, - 0x807c847c, 0x8078ff78, - 0x00000400, 0xbf0a6f7c, - 0xbf85ffee, 0xbefc0080, - 0xbf11087c, 0xe0524000, - 0x781d0000, 0xe0524100, - 0x781d0100, 0xe0524200, - 0x781d0200, 0xe0524300, - 0x781d0300, 0xbf8c0f70, - 0xd3d94000, 0x18000100, - 0xd3d94001, 0x18000101, - 0xd3d94002, 0x18000102, - 0xd3d94003, 0x18000103, - 0x807c847c, 0x8078ff78, - 0x00000400, 0xbf0a6f7c, - 0xbf85ffea, 0xbf9c0000, - 0xe0524000, 0x6e1d0000, - 0xe0524100, 0x6e1d0100, - 0xe0524200, 0x6e1d0200, - 0xe0524300, 0x6e1d0300, - 0xbf8c0f70, 0xb8f82a05, - 0x80788178, 0x8e788a78, - 0x8e788178, 0xb8ee1605, - 0x806e816e, 0x8e6e866e, - 0x80786e78, 0x80f8c078, - 0xb8ef1605, 0x806f816f, - 0x8e6f846f, 0x8e76826f, - 0xbef600ff, 0x01000000, - 0xbefc006f, 0xc031003a, - 0x00000078, 0x80f8c078, - 0xbf8cc07f, 0x80fc907c, - 0xbf800000, 0xbe802d00, - 0xbe822d02, 0xbe842d04, - 0xbe862d06, 0xbe882d08, - 0xbe8a2d0a, 0xbe8c2d0c, - 0xbe8e2d0e, 0xbf06807c, - 0xbf84fff0, 0xb8f82a05, - 0x80788178, 0x8e788a78, - 0x8e788178, 0xb8ee1605, - 0x806e816e, 0x8e6e866e, - 0x80786e78, 0xbef60084, - 0xbef600ff, 0x01000000, - 0xc0211bfa, 0x00000078, - 0x80788478, 0xc0211b3a, + 0xbefc0080, 0xe0510000, + 0x781d0000, 0xe0510100, + 0x781d0000, 0x807cff7c, + 0x00000200, 0x8078ff78, + 0x00000200, 0xbf0a6f7c, + 0xbf85fff6, 0xbefe00c1, + 0xbeff00c1, 0xbef600ff, + 0x01000000, 0xb8ef2a05, + 0x806f816f, 0x8e6f826f, + 0x806fff6f, 0x00008000, + 0xbef80080, 0xbeee0078, + 0x8078ff78, 0x00000400, + 0xbefc0084, 0xbf11087c, + 0xe0524000, 0x781d0000, + 0xe0524100, 0x781d0100, + 0xe0524200, 0x781d0200, + 0xe0524300, 0x781d0300, + 0xbf8c0f70, 0x7e000300, + 0x7e020301, 0x7e040302, + 0x7e060303, 0x807c847c, + 0x8078ff78, 0x00000400, + 0xbf0a6f7c, 0xbf85ffee, + 0xbefc0080, 0xbf11087c, + 0xe0524000, 0x781d0000, + 0xe0524100, 0x781d0100, + 0xe0524200, 0x781d0200, + 0xe0524300, 0x781d0300, + 0xbf8c0f70, 0xd3d94000, + 0x18000100, 0xd3d94001, + 0x18000101, 0xd3d94002, + 0x18000102, 0xd3d94003, + 0x18000103, 0x807c847c, + 0x8078ff78, 0x00000400, + 0xbf0a6f7c, 0xbf85ffea, + 0xbf9c0000, 0xe0524000, + 0x6e1d0000, 0xe0524100, + 0x6e1d0100, 0xe0524200, + 0x6e1d0200, 0xe0524300, + 0x6e1d0300, 0xbf8c0f70, + 0xb8f82a05, 0x80788178, + 0x8e788a78, 0x8e788178, + 0xb8ee1605, 0x806e816e, + 0x8e6e866e, 0x80786e78, + 0x80f8c078, 0xb8ef1605, + 0x806f816f, 0x8e6f846f, + 0x8e76826f, 0xbef600ff, + 0x01000000, 0xbefc006f, + 0xc031003a, 0x00000078, + 0x80f8c078, 0xbf8cc07f, + 0x80fc907c, 0xbf800000, + 0xbe802d00, 0xbe822d02, + 0xbe842d04, 0xbe862d06, + 0xbe882d08, 0xbe8a2d0a, + 0xbe8c2d0c, 0xbe8e2d0e, + 0xbf06807c, 0xbf84fff0, + 0xb8f82a05, 0x80788178, + 0x8e788a78, 0x8e788178, + 0xb8ee1605, 0x806e816e, + 0x8e6e866e, 0x80786e78, + 0xbef60084, 0xbef600ff, + 0x01000000, 0xc0211bfa, 0x00000078, 0x80788478, - 0xc0211b7a, 0x00000078, - 0x80788478, 0xc0211c3a, + 0xc0211b3a, 0x00000078, + 0x80788478, 0xc0211b7a, 0x00000078, 0x80788478, - 0xc0211c7a, 0x00000078, - 0x80788478, 0xc0211eba, + 0xc0211c3a, 0x00000078, + 0x80788478, 0xc0211c7a, 0x00000078, 0x80788478, - 0xc0211efa, 0x00000078, - 0x80788478, 0xc0211a3a, + 0xc0211eba, 0x00000078, + 0x80788478, 0xc0211efa, 0x00000078, 0x80788478, - 0xc0211a7a, 0x00000078, - 0x80788478, 0xc0211cfa, + 0xc0211a3a, 0x00000078, + 0x80788478, 0xc0211a7a, 0x00000078, 0x80788478, - 0xbf8cc07f, 0xbefc006f, - 0xbefe0070, 0xbeff0071, - 0x866f7bff, 0x000003ff, - 0xb96f4803, 0x866f7bff, - 0xfffff800, 0x8f6f8b6f, - 0xb96fa2c3, 0xb973f801, - 0xb8ee2a05, 0x806e816e, - 0x8e6e8a6e, 0x8e6e816e, - 0xb8ef1605, 0x806f816f, - 0x8e6f866f, 0x806e6f6e, - 0x806e746e, 0x826f8075, - 0x866fff6f, 0x0000ffff, - 0xc00b1c37, 0x00000050, - 0xc00b1d37, 0x00000060, - 0xc0031e77, 0x00000074, - 0xbf8cc07f, 0x8f6e8b77, - 0x866eff6e, 0x001f8000, - 0xb96ef807, 0x866dff6d, - 0x0000ffff, 0x86fe7e7e, - 0x86ea6a6a, 0x8f6e837a, - 0xb96ee0c2, 0xbf800002, - 0xb97a0002, 0xbf8a0000, - 0xbe801f6c, 0xbf9b0000, + 0xc0211cfa, 0x00000078, + 0x80788478, 0xbf8cc07f, + 0xbefc006f, 0xbefe0070, + 0xbeff0071, 0x866f7bff, + 0x000003ff, 0xb96f4803, + 0x866f7bff, 0xfffff800, + 0x8f6f8b6f, 0xb96fa2c3, + 0xb973f801, 0xb8ee2a05, + 0x806e816e, 0x8e6e8a6e, + 0x8e6e816e, 0xb8ef1605, + 0x806f816f, 0x8e6f866f, + 0x806e6f6e, 0x806e746e, + 0x826f8075, 0x866fff6f, + 0x0000ffff, 0xc00b1c37, + 0x00000050, 0xc00b1d37, + 0x00000060, 0xc0031e77, + 0x00000074, 0xbf8cc07f, + 0x8f6e8b77, 0x866eff6e, + 0x001f8000, 0xb96ef807, + 0x866dff6d, 0x0000ffff, + 0x86fe7e7e, 0x86ea6a6a, + 0x8f6e837a, 0xb96ee0c2, + 0xbf800002, 0xb97a0002, + 0xbf8a0000, 0xbe801f6c, + 0xbf810000, 0x00000000, }; static const uint32_t cwsr_trap_aldebaran_hex[] = { - 0xbf820001, 0xbf8202e5, + 0xbf820001, 0xbf8202ea, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, 0x866eff78, 0x00002000, 0xbf840009, 0x866eff6d, - 0x00ff0000, 0xbf85001e, + 0x00ff0000, 0xbf850023, 0x866eff7b, 0x00000400, - 0xbf85005b, 0xbf8e0010, + 0xbf850060, 0xbf8e0010, 0xb8fbf803, 0xbf82fffa, 0x866eff7b, 0x03c00900, - 0xbf850015, 0x866eff7b, - 0x000071ff, 0xbf840008, - 0x866fff7b, 0x00007080, - 0xbf840001, 0xbeee1a87, - 0xb8eff801, 0x8e6e8c6e, - 0x866e6f6e, 0xbf85000a, - 0x866eff6d, 0x00ff0000, - 0xbf850007, 0xb8eef801, - 0x866eff6e, 0x00000800, - 0xbf850003, 0x866eff7b, - 0x00000400, 0xbf850040, - 0xb8faf807, 0x867aff7a, - 0x001f8000, 0x8e7a8b7a, - 0x8977ff77, 0xfc000000, - 0x87777a77, 0xba7ff807, - 0x00000000, 0xb8faf812, - 0xb8fbf813, 0x8efa887a, - 0xbf0d8f7b, 0xbf840002, - 0x877bff7b, 0xffff0000, - 0xc0031c3d, 0x00000010, - 0xc0071bbd, 0x00000000, - 0xc0071ebd, 0x00000008, - 0xbf8cc07f, 0x8671ff6d, - 0x01000000, 0xbf840004, - 0x92f1ff70, 0x00010001, - 0xbf840016, 0xbf820005, - 0x86708170, 0x8e709770, - 0x8977ff77, 0x00800000, - 0x87777077, 0x86ee6e6e, - 0xbf840001, 0xbe801d6e, - 0x866eff6d, 0x01ff0000, - 0xbf850005, 0x8778ff78, - 0x00002000, 0x80ec886c, - 0x82ed806d, 0xbf820005, - 0x866eff6d, 0x01000000, - 0xbf850002, 0x806c846c, - 0x826d806d, 0x866dff6d, - 0x0000ffff, 0x8f7a8b77, - 0x867aff7a, 0x001f8000, - 0xb97af807, 0x86fe7e7e, - 0x86ea6a6a, 0x8f6e8378, - 0xb96ee0c2, 0xbf800002, - 0xb9780002, 0xbe801f6c, - 0x866dff6d, 0x0000ffff, - 0xbefa0080, 0xb97a0283, - 0xb8faf807, 0x867aff7a, - 0x001f8000, 0x8e7a8b7a, - 0x8977ff77, 0xfc000000, - 0x87777a77, 0xba7ff807, - 0x00000000, 0xbeee007e, - 0xbeef007f, 0xbefe0180, - 0xbf900004, 0x877a8478, - 0xb97af802, 0xbf8e0002, - 0xbf88fffe, 0xb8fa2985, - 0x807a817a, 0x8e7a8a7a, - 0x8e7a817a, 0xb8fb1605, - 0x807b817b, 0x8e7b867b, - 0x807a7b7a, 0x807a7e7a, - 0x827b807f, 0x867bff7b, - 0x0000ffff, 0xc04b1c3d, - 0x00000050, 0xbf8cc07f, - 0xc04b1d3d, 0x00000060, - 0xbf8cc07f, 0xc0431e7d, - 0x00000074, 0xbf8cc07f, - 0xbef4007e, 0x8675ff7f, - 0x0000ffff, 0x8775ff75, - 0x00040000, 0xbef60080, - 0xbef700ff, 0x00807fac, - 0xbef1007c, 0xbef00080, - 0xb8f02985, 0x80708170, - 0x8e708a70, 0x8e708170, - 0xb8fa1605, 0x807a817a, - 0x8e7a867a, 0x80707a70, - 0xbef60084, 0xbef600ff, - 0x01000000, 0xbefe007c, - 0xbefc0070, 0xc0611c7a, - 0x0000007c, 0xbf8cc07f, - 0x80708470, 0xbefc007e, + 0xbf85001a, 0x866eff6d, + 0x01ff0000, 0xbf06ff6e, + 0x01040000, 0xbf850015, + 0x866eff7b, 0x000071ff, + 0xbf840008, 0x866fff7b, + 0x00007080, 0xbf840001, + 0xbeee1a87, 0xb8eff801, + 0x8e6e8c6e, 0x866e6f6e, + 0xbf85000a, 0x866eff6d, + 0x00ff0000, 0xbf850007, + 0xb8eef801, 0x866eff6e, + 0x00000800, 0xbf850003, + 0x866eff7b, 0x00000400, + 0xbf850040, 0xb8faf807, + 0x867aff7a, 0x001f8000, + 0x8e7a8b7a, 0x8977ff77, + 0xfc000000, 0x87777a77, + 0xba7ff807, 0x00000000, + 0xb8faf812, 0xb8fbf813, + 0x8efa887a, 0xbf0d8f7b, + 0xbf840002, 0x877bff7b, + 0xffff0000, 0xc0031c3d, + 0x00000010, 0xc0071bbd, + 0x00000000, 0xc0071ebd, + 0x00000008, 0xbf8cc07f, + 0x8671ff6d, 0x01000000, + 0xbf840004, 0x92f1ff70, + 0x00010001, 0xbf840016, + 0xbf820005, 0x86708170, + 0x8e709770, 0x8977ff77, + 0x00800000, 0x87777077, + 0x86ee6e6e, 0xbf840001, + 0xbe801d6e, 0x866eff6d, + 0x01ff0000, 0xbf850005, + 0x8778ff78, 0x00002000, + 0x80ec886c, 0x82ed806d, + 0xbf820005, 0x866eff6d, + 0x01000000, 0xbf850002, + 0x806c846c, 0x826d806d, + 0x866dff6d, 0x0000ffff, + 0x8f7a8b77, 0x867aff7a, + 0x001f8000, 0xb97af807, + 0x86fe7e7e, 0x86ea6a6a, + 0x8f6e8378, 0xb96ee0c2, + 0xbf800002, 0xb9780002, + 0xbe801f6c, 0x866dff6d, + 0x0000ffff, 0xbefa0080, + 0xb97a0283, 0xb8faf807, + 0x867aff7a, 0x001f8000, + 0x8e7a8b7a, 0x8977ff77, + 0xfc000000, 0x87777a77, + 0xba7ff807, 0x00000000, + 0xbeee007e, 0xbeef007f, + 0xbefe0180, 0xbf900004, + 0x877a8478, 0xb97af802, + 0xbf8e0002, 0xbf88fffe, + 0xb8fa2985, 0x807a817a, + 0x8e7a8a7a, 0x8e7a817a, + 0xb8fb1605, 0x807b817b, + 0x8e7b867b, 0x807a7b7a, + 0x807a7e7a, 0x827b807f, + 0x867bff7b, 0x0000ffff, + 0xc04b1c3d, 0x00000050, + 0xbf8cc07f, 0xc04b1d3d, + 0x00000060, 0xbf8cc07f, + 0xc0431e7d, 0x00000074, + 0xbf8cc07f, 0xbef4007e, + 0x8675ff7f, 0x0000ffff, + 0x8775ff75, 0x00040000, + 0xbef60080, 0xbef700ff, + 0x00807fac, 0xbef1007c, + 0xbef00080, 0xb8f02985, + 0x80708170, 0x8e708a70, + 0x8e708170, 0xb8fa1605, + 0x807a817a, 0x8e7a867a, + 0x80707a70, 0xbef60084, + 0xbef600ff, 0x01000000, 0xbefe007c, 0xbefc0070, - 0xc0611b3a, 0x0000007c, + 0xc0611c7a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611b7a, + 0xbefc0070, 0xc0611b3a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, 0xbefc0070, - 0xc0611bba, 0x0000007c, + 0xc0611b7a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611bfa, + 0xbefc0070, 0xc0611bba, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, 0xbefc0070, - 0xc0611e3a, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xb8fbf803, - 0xbefe007c, 0xbefc0070, - 0xc0611efa, 0x0000007c, + 0xc0611bfa, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611a3a, + 0xbefc0070, 0xc0611e3a, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0xb8fbf803, 0xbefe007c, + 0xbefc0070, 0xc0611efa, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, 0xbefc0070, - 0xc0611a7a, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xb8f1f801, - 0xbefe007c, 0xbefc0070, - 0xc0611c7a, 0x0000007c, + 0xc0611a3a, 0x0000007c, 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0x867aff7f, - 0x04000000, 0xbeef0080, - 0x876f6f7a, 0xb8f02985, - 0x80708170, 0x8e708a70, - 0x8e708170, 0xb8fb1605, - 0x807b817b, 0x8e7b847b, - 0x8e76827b, 0xbef600ff, - 0x01000000, 0xbef20174, - 0x80747074, 0x82758075, - 0xbefc0080, 0xbf800000, - 0xbe802b00, 0xbe822b02, - 0xbe842b04, 0xbe862b06, - 0xbe882b08, 0xbe8a2b0a, - 0xbe8c2b0c, 0xbe8e2b0e, - 0xc06b003a, 0x00000000, - 0xbf8cc07f, 0xc06b013a, - 0x00000010, 0xbf8cc07f, - 0xc06b023a, 0x00000020, - 0xbf8cc07f, 0xc06b033a, - 0x00000030, 0xbf8cc07f, - 0x8074c074, 0x82758075, - 0x807c907c, 0xbf0a7b7c, - 0xbf85ffe7, 0xbef40172, - 0xbef00080, 0xbefe00c1, - 0xbeff00c1, 0xbee80080, - 0xbee90080, 0xbef600ff, - 0x01000000, 0x867aff78, - 0x00400000, 0xbf850003, - 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf85004d, - 0xbe840080, 0xd2890000, - 0x00000900, 0x80048104, - 0xd2890001, 0x00000900, - 0x80048104, 0xd2890002, - 0x00000900, 0x80048104, - 0xd2890003, 0x00000900, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000901, - 0x80048104, 0xd2890001, - 0x00000901, 0x80048104, - 0xd2890002, 0x00000901, - 0x80048104, 0xd2890003, - 0x00000901, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0xbe840080, 0xd2890000, - 0x00000902, 0x80048104, - 0xd2890001, 0x00000902, - 0x80048104, 0xd2890002, - 0x00000902, 0x80048104, - 0xd2890003, 0x00000902, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000903, - 0x80048104, 0xd2890001, - 0x00000903, 0x80048104, - 0xd2890002, 0x00000903, - 0x80048104, 0xd2890003, - 0x00000903, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0xbf820008, 0xe0724000, - 0x701d0000, 0xe0724100, - 0x701d0100, 0xe0724200, - 0x701d0200, 0xe0724300, - 0x701d0300, 0xbefe00c1, - 0xbeff00c1, 0xb8fb4306, - 0x867bc17b, 0xbf840064, - 0xbf8a0000, 0x867aff6f, - 0x04000000, 0xbf840060, - 0x8e7b867b, 0x8e7b827b, - 0xbef6007b, 0xb8f02985, - 0x80708170, 0x8e708a70, - 0x8e708170, 0xb8fa1605, - 0x807a817a, 0x8e7a867a, - 0x80707a70, 0x8070ff70, - 0x00000080, 0xbef600ff, - 0x01000000, 0xbefc0080, - 0xd28c0002, 0x000100c1, - 0xd28d0003, 0x000204c1, + 0xbefc007e, 0xbefe007c, + 0xbefc0070, 0xc0611a7a, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0xb8f1f801, 0xbefe007c, + 0xbefc0070, 0xc0611c7a, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0x867aff7f, 0x04000000, + 0xbeef0080, 0x876f6f7a, + 0xb8f02985, 0x80708170, + 0x8e708a70, 0x8e708170, + 0xb8fb1605, 0x807b817b, + 0x8e7b847b, 0x8e76827b, + 0xbef600ff, 0x01000000, + 0xbef20174, 0x80747074, + 0x82758075, 0xbefc0080, + 0xbf800000, 0xbe802b00, + 0xbe822b02, 0xbe842b04, + 0xbe862b06, 0xbe882b08, + 0xbe8a2b0a, 0xbe8c2b0c, + 0xbe8e2b0e, 0xc06b003a, + 0x00000000, 0xbf8cc07f, + 0xc06b013a, 0x00000010, + 0xbf8cc07f, 0xc06b023a, + 0x00000020, 0xbf8cc07f, + 0xc06b033a, 0x00000030, + 0xbf8cc07f, 0x8074c074, + 0x82758075, 0x807c907c, + 0xbf0a7b7c, 0xbf85ffe7, + 0xbef40172, 0xbef00080, + 0xbefe00c1, 0xbeff00c1, + 0xbee80080, 0xbee90080, + 0xbef600ff, 0x01000000, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, 0x10000000, - 0xbf850030, 0x24040682, - 0xd86e4000, 0x00000002, - 0xbf8cc07f, 0xbe840080, + 0xbf85004d, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, 0x80048104, @@ -2019,31 +1965,50 @@ static const uint32_t cwsr_trap_aldebaran_hex[] = { 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, - 0xbf84ffee, 0x680404ff, - 0x00000200, 0xd0c9006a, - 0x0000f702, 0xbf87ffd2, - 0xbf820015, 0xd1060002, - 0x00011103, 0x7e0602ff, - 0x00000200, 0xbefc00ff, - 0x00010000, 0xbe800077, - 0x8677ff77, 0xff7fffff, - 0x8777ff77, 0x00058000, - 0xd8ec0000, 0x00000002, - 0xbf8cc07f, 0xe0765000, - 0x701d0002, 0x68040702, - 0xd0c9006a, 0x0000f702, - 0xbf87fff7, 0xbef70000, - 0xbef000ff, 0x00000400, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000902, + 0x80048104, 0xd2890001, + 0x00000902, 0x80048104, + 0xd2890002, 0x00000902, + 0x80048104, 0xd2890003, + 0x00000902, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbe840080, 0xd2890000, + 0x00000903, 0x80048104, + 0xd2890001, 0x00000903, + 0x80048104, 0xd2890002, + 0x00000903, 0x80048104, + 0xd2890003, 0x00000903, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbf820008, + 0xe0724000, 0x701d0000, + 0xe0724100, 0x701d0100, + 0xe0724200, 0x701d0200, + 0xe0724300, 0x701d0300, 0xbefe00c1, 0xbeff00c1, - 0xb8fb2b05, 0x807b817b, - 0x8e7b827b, 0xbef600ff, - 0x01000000, 0xbefc0084, - 0xbf0a7b7c, 0xbf84006d, - 0xbf11017c, 0x807bff7b, - 0x00001000, 0x867aff78, + 0xb8fb4306, 0x867bc17b, + 0xbf840064, 0xbf8a0000, + 0x867aff6f, 0x04000000, + 0xbf840060, 0x8e7b867b, + 0x8e7b827b, 0xbef6007b, + 0xb8f02985, 0x80708170, + 0x8e708a70, 0x8e708170, + 0xb8fa1605, 0x807a817a, + 0x8e7a867a, 0x80707a70, + 0x8070ff70, 0x00000080, + 0xbef600ff, 0x01000000, + 0xbefc0080, 0xd28c0002, + 0x000100c1, 0xd28d0003, + 0x000204c1, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf850051, + 0x10000000, 0xbf850030, + 0x24040682, 0xd86e4000, + 0x00000002, 0xbf8cc07f, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, @@ -2061,53 +2026,33 @@ static const uint32_t cwsr_trap_aldebaran_hex[] = { 0x80048104, 0xd2890003, 0x00000901, 0x80048104, 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0xbe840080, 0xd2890000, - 0x00000902, 0x80048104, - 0xd2890001, 0x00000902, - 0x80048104, 0xd2890002, - 0x00000902, 0x80048104, - 0xd2890003, 0x00000902, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000903, - 0x80048104, 0xd2890001, - 0x00000903, 0x80048104, - 0xd2890002, 0x00000903, - 0x80048104, 0xd2890003, - 0x00000903, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0x807c847c, 0xbf0a7b7c, - 0xbf85ffb1, 0xbf9c0000, - 0xbf820012, 0x7e000300, - 0x7e020301, 0x7e040302, - 0x7e060303, 0xe0724000, - 0x701d0000, 0xe0724100, - 0x701d0100, 0xe0724200, - 0x701d0200, 0xe0724300, - 0x701d0300, 0x807c847c, - 0x8070ff70, 0x00000400, - 0xbf0a7b7c, 0xbf85ffef, - 0xbf9c0000, 0xb8fb2985, - 0x807b817b, 0x8e7b837b, - 0xb8fa2b05, 0x807a817a, - 0x8e7a827a, 0x80fb7a7b, - 0x867b7b7b, 0xbf84007a, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0x680404ff, 0x00000200, + 0xd0c9006a, 0x0000f702, + 0xbf87ffd2, 0xbf820015, + 0xd1060002, 0x00011103, + 0x7e0602ff, 0x00000200, + 0xbefc00ff, 0x00010000, + 0xbe800077, 0x8677ff77, + 0xff7fffff, 0x8777ff77, + 0x00058000, 0xd8ec0000, + 0x00000002, 0xbf8cc07f, + 0xe0765000, 0x701d0002, + 0x68040702, 0xd0c9006a, + 0x0000f702, 0xbf87fff7, + 0xbef70000, 0xbef000ff, + 0x00000400, 0xbefe00c1, + 0xbeff00c1, 0xb8fb2b05, + 0x807b817b, 0x8e7b827b, + 0xbef600ff, 0x01000000, + 0xbefc0084, 0xbf0a7b7c, + 0xbf84006d, 0xbf11017c, 0x807bff7b, 0x00001000, - 0xbefc0080, 0xbf11017c, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, 0x10000000, - 0xbf850059, 0xd3d84000, - 0x18000100, 0xd3d84001, - 0x18000101, 0xd3d84002, - 0x18000102, 0xd3d84003, - 0x18000103, 0xbe840080, + 0xbf850051, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, 0x80048104, @@ -2146,139 +2091,203 @@ static const uint32_t cwsr_trap_aldebaran_hex[] = { 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0x807c847c, - 0xbf0a7b7c, 0xbf85ffa9, - 0xbf9c0000, 0xbf820016, - 0xd3d84000, 0x18000100, - 0xd3d84001, 0x18000101, - 0xd3d84002, 0x18000102, - 0xd3d84003, 0x18000103, + 0xbf0a7b7c, 0xbf85ffb1, + 0xbf9c0000, 0xbf820012, + 0x7e000300, 0x7e020301, + 0x7e040302, 0x7e060303, 0xe0724000, 0x701d0000, 0xe0724100, 0x701d0100, 0xe0724200, 0x701d0200, 0xe0724300, 0x701d0300, 0x807c847c, 0x8070ff70, 0x00000400, 0xbf0a7b7c, - 0xbf85ffeb, 0xbf9c0000, - 0xbf8200ee, 0xbef4007e, - 0x8675ff7f, 0x0000ffff, - 0x8775ff75, 0x00040000, - 0xbef60080, 0xbef700ff, - 0x00807fac, 0x866eff7f, - 0x04000000, 0xbf84001f, + 0xbf85ffef, 0xbf9c0000, + 0xb8fb2985, 0x807b817b, + 0x8e7b837b, 0xb8fa2b05, + 0x807a817a, 0x8e7a827a, + 0x80fb7a7b, 0x867b7b7b, + 0xbf84007a, 0x807bff7b, + 0x00001000, 0xbefc0080, + 0xbf11017c, 0x867aff78, + 0x00400000, 0xbf850003, + 0xb8faf803, 0x897a7aff, + 0x10000000, 0xbf850059, + 0xd3d84000, 0x18000100, + 0xd3d84001, 0x18000101, + 0xd3d84002, 0x18000102, + 0xd3d84003, 0x18000103, + 0xbe840080, 0xd2890000, + 0x00000900, 0x80048104, + 0xd2890001, 0x00000900, + 0x80048104, 0xd2890002, + 0x00000900, 0x80048104, + 0xd2890003, 0x00000900, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000901, + 0x80048104, 0xd2890001, + 0x00000901, 0x80048104, + 0xd2890002, 0x00000901, + 0x80048104, 0xd2890003, + 0x00000901, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbe840080, 0xd2890000, + 0x00000902, 0x80048104, + 0xd2890001, 0x00000902, + 0x80048104, 0xd2890002, + 0x00000902, 0x80048104, + 0xd2890003, 0x00000902, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000903, + 0x80048104, 0xd2890001, + 0x00000903, 0x80048104, + 0xd2890002, 0x00000903, + 0x80048104, 0xd2890003, + 0x00000903, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0x807c847c, 0xbf0a7b7c, + 0xbf85ffa9, 0xbf9c0000, + 0xbf820016, 0xd3d84000, + 0x18000100, 0xd3d84001, + 0x18000101, 0xd3d84002, + 0x18000102, 0xd3d84003, + 0x18000103, 0xe0724000, + 0x701d0000, 0xe0724100, + 0x701d0100, 0xe0724200, + 0x701d0200, 0xe0724300, + 0x701d0300, 0x807c847c, + 0x8070ff70, 0x00000400, + 0xbf0a7b7c, 0xbf85ffeb, + 0xbf9c0000, 0xbf8200ee, + 0xbef4007e, 0x8675ff7f, + 0x0000ffff, 0x8775ff75, + 0x00040000, 0xbef60080, + 0xbef700ff, 0x00807fac, + 0x866eff7f, 0x04000000, + 0xbf84001f, 0xbefe00c1, + 0xbeff00c1, 0xb8ef4306, + 0x866fc16f, 0xbf84001a, + 0x8e6f866f, 0x8e6f826f, + 0xbef6006f, 0xb8f82985, + 0x80788178, 0x8e788a78, + 0x8e788178, 0xb8ee1605, + 0x806e816e, 0x8e6e866e, + 0x80786e78, 0x8078ff78, + 0x00000080, 0xbef600ff, + 0x01000000, 0xbefc0080, + 0xe0510000, 0x781d0000, + 0xe0510100, 0x781d0000, + 0x807cff7c, 0x00000200, + 0x8078ff78, 0x00000200, + 0xbf0a6f7c, 0xbf85fff6, 0xbefe00c1, 0xbeff00c1, - 0xb8ef4306, 0x866fc16f, - 0xbf84001a, 0x8e6f866f, - 0x8e6f826f, 0xbef6006f, - 0xb8f82985, 0x80788178, - 0x8e788a78, 0x8e788178, - 0xb8ee1605, 0x806e816e, - 0x8e6e866e, 0x80786e78, - 0x8078ff78, 0x00000080, 0xbef600ff, 0x01000000, - 0xbefc0080, 0xe0510000, - 0x781d0000, 0xe0510100, - 0x781d0000, 0x807cff7c, - 0x00000200, 0x8078ff78, - 0x00000200, 0xbf0a6f7c, - 0xbf85fff6, 0xbefe00c1, - 0xbeff00c1, 0xbef600ff, - 0x01000000, 0xb8ef2b05, - 0x806f816f, 0x8e6f826f, - 0x806fff6f, 0x00008000, - 0xbef80080, 0xbeee0078, - 0x8078ff78, 0x00000400, - 0xbefc0084, 0xbf11087c, - 0xe0524000, 0x781d0000, - 0xe0524100, 0x781d0100, - 0xe0524200, 0x781d0200, - 0xe0524300, 0x781d0300, - 0xbf8c0f70, 0x7e000300, - 0x7e020301, 0x7e040302, - 0x7e060303, 0x807c847c, - 0x8078ff78, 0x00000400, - 0xbf0a6f7c, 0xbf85ffee, - 0xb8ef2985, 0x806f816f, - 0x8e6f836f, 0xb8f92b05, - 0x80798179, 0x8e798279, - 0x80ef796f, 0x866f6f6f, - 0xbf84001a, 0x806fff6f, - 0x00008000, 0xbefc0080, + 0xb8ef2b05, 0x806f816f, + 0x8e6f826f, 0x806fff6f, + 0x00008000, 0xbef80080, + 0xbeee0078, 0x8078ff78, + 0x00000400, 0xbefc0084, 0xbf11087c, 0xe0524000, 0x781d0000, 0xe0524100, 0x781d0100, 0xe0524200, 0x781d0200, 0xe0524300, 0x781d0300, 0xbf8c0f70, - 0xd3d94000, 0x18000100, - 0xd3d94001, 0x18000101, - 0xd3d94002, 0x18000102, - 0xd3d94003, 0x18000103, + 0x7e000300, 0x7e020301, + 0x7e040302, 0x7e060303, 0x807c847c, 0x8078ff78, 0x00000400, 0xbf0a6f7c, - 0xbf85ffea, 0xbf9c0000, - 0xe0524000, 0x6e1d0000, - 0xe0524100, 0x6e1d0100, - 0xe0524200, 0x6e1d0200, - 0xe0524300, 0x6e1d0300, - 0xbf8c0f70, 0xb8f82985, - 0x80788178, 0x8e788a78, - 0x8e788178, 0xb8ee1605, - 0x806e816e, 0x8e6e866e, - 0x80786e78, 0x80f8c078, - 0xb8ef1605, 0x806f816f, - 0x8e6f846f, 0x8e76826f, - 0xbef600ff, 0x01000000, - 0xbefc006f, 0xc031003a, - 0x00000078, 0x80f8c078, - 0xbf8cc07f, 0x80fc907c, - 0xbf800000, 0xbe802d00, - 0xbe822d02, 0xbe842d04, - 0xbe862d06, 0xbe882d08, - 0xbe8a2d0a, 0xbe8c2d0c, - 0xbe8e2d0e, 0xbf06807c, - 0xbf84fff0, 0xb8f82985, - 0x80788178, 0x8e788a78, - 0x8e788178, 0xb8ee1605, - 0x806e816e, 0x8e6e866e, - 0x80786e78, 0xbef60084, - 0xbef600ff, 0x01000000, - 0xc0211bfa, 0x00000078, - 0x80788478, 0xc0211b3a, + 0xbf85ffee, 0xb8ef2985, + 0x806f816f, 0x8e6f836f, + 0xb8f92b05, 0x80798179, + 0x8e798279, 0x80ef796f, + 0x866f6f6f, 0xbf84001a, + 0x806fff6f, 0x00008000, + 0xbefc0080, 0xbf11087c, + 0xe0524000, 0x781d0000, + 0xe0524100, 0x781d0100, + 0xe0524200, 0x781d0200, + 0xe0524300, 0x781d0300, + 0xbf8c0f70, 0xd3d94000, + 0x18000100, 0xd3d94001, + 0x18000101, 0xd3d94002, + 0x18000102, 0xd3d94003, + 0x18000103, 0x807c847c, + 0x8078ff78, 0x00000400, + 0xbf0a6f7c, 0xbf85ffea, + 0xbf9c0000, 0xe0524000, + 0x6e1d0000, 0xe0524100, + 0x6e1d0100, 0xe0524200, + 0x6e1d0200, 0xe0524300, + 0x6e1d0300, 0xbf8c0f70, + 0xb8f82985, 0x80788178, + 0x8e788a78, 0x8e788178, + 0xb8ee1605, 0x806e816e, + 0x8e6e866e, 0x80786e78, + 0x80f8c078, 0xb8ef1605, + 0x806f816f, 0x8e6f846f, + 0x8e76826f, 0xbef600ff, + 0x01000000, 0xbefc006f, + 0xc031003a, 0x00000078, + 0x80f8c078, 0xbf8cc07f, + 0x80fc907c, 0xbf800000, + 0xbe802d00, 0xbe822d02, + 0xbe842d04, 0xbe862d06, + 0xbe882d08, 0xbe8a2d0a, + 0xbe8c2d0c, 0xbe8e2d0e, + 0xbf06807c, 0xbf84fff0, + 0xb8f82985, 0x80788178, + 0x8e788a78, 0x8e788178, + 0xb8ee1605, 0x806e816e, + 0x8e6e866e, 0x80786e78, + 0xbef60084, 0xbef600ff, + 0x01000000, 0xc0211bfa, 0x00000078, 0x80788478, - 0xc0211b7a, 0x00000078, - 0x80788478, 0xc0211c3a, + 0xc0211b3a, 0x00000078, + 0x80788478, 0xc0211b7a, 0x00000078, 0x80788478, - 0xc0211c7a, 0x00000078, - 0x80788478, 0xc0211eba, + 0xc0211c3a, 0x00000078, + 0x80788478, 0xc0211c7a, 0x00000078, 0x80788478, - 0xc0211efa, 0x00000078, - 0x80788478, 0xc0211a3a, + 0xc0211eba, 0x00000078, + 0x80788478, 0xc0211efa, 0x00000078, 0x80788478, - 0xc0211a7a, 0x00000078, - 0x80788478, 0xc0211cfa, + 0xc0211a3a, 0x00000078, + 0x80788478, 0xc0211a7a, 0x00000078, 0x80788478, - 0xbf8cc07f, 0xbefc006f, - 0xbefe0070, 0xbeff0071, - 0x866f7bff, 0x000003ff, - 0xb96f4803, 0x866f7bff, - 0xfffff800, 0x8f6f8b6f, - 0xb96fa2c3, 0xb973f801, - 0xb8ee2985, 0x806e816e, - 0x8e6e8a6e, 0x8e6e816e, - 0xb8ef1605, 0x806f816f, - 0x8e6f866f, 0x806e6f6e, - 0x806e746e, 0x826f8075, - 0x866fff6f, 0x0000ffff, - 0xc00b1c37, 0x00000050, - 0xc00b1d37, 0x00000060, - 0xc0031e77, 0x00000074, - 0xbf8cc07f, 0x8f6e8b77, - 0x866eff6e, 0x001f8000, - 0xb96ef807, 0x866dff6d, - 0x0000ffff, 0x86fe7e7e, - 0x86ea6a6a, 0x8f6e837a, - 0xb96ee0c2, 0xbf800002, - 0xb97a0002, 0xbf8a0000, - 0xbe801f6c, 0xbf9b0000, + 0xc0211cfa, 0x00000078, + 0x80788478, 0xbf8cc07f, + 0xbefc006f, 0xbefe0070, + 0xbeff0071, 0x866f7bff, + 0x000003ff, 0xb96f4803, + 0x866f7bff, 0xfffff800, + 0x8f6f8b6f, 0xb96fa2c3, + 0xb973f801, 0xb8ee2985, + 0x806e816e, 0x8e6e8a6e, + 0x8e6e816e, 0xb8ef1605, + 0x806f816f, 0x8e6f866f, + 0x806e6f6e, 0x806e746e, + 0x826f8075, 0x866fff6f, + 0x0000ffff, 0xc00b1c37, + 0x00000050, 0xc00b1d37, + 0x00000060, 0xc0031e77, + 0x00000074, 0xbf8cc07f, + 0x8f6e8b77, 0x866eff6e, + 0x001f8000, 0xb96ef807, + 0x866dff6d, 0x0000ffff, + 0x86fe7e7e, 0x86ea6a6a, + 0x8f6e837a, 0xb96ee0c2, + 0xbf800002, 0xb97a0002, + 0xbf8a0000, 0xbe801f6c, + 0xbf810000, 0x00000000, }; static const uint32_t cwsr_trap_gfx10_hex[] = { diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm index 991fe6bb1726d..483ef6a45a831 100644 --- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm +++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm @@ -244,6 +244,11 @@ L_NOT_HALTED: SQ_WAVE_TRAPSTS_TRAP_AFTER_INST_MASK s_cbranch_scc1 L_FETCH_2ND_TRAP + // Check TTMP1 bits 24 (HT) and 23:16(trapID): HT == 1 & trapID == 4 + s_and_b32 ttmp2, s_save_pc_hi, (S_SAVE_PC_HI_TRAP_ID_MASK|S_SAVE_PC_HI_HT_MASK) + s_cmp_eq_u32 ttmp2, 0x1040000 + s_cbranch_scc1 L_FETCH_2ND_TRAP + // Check for maskable exceptions in trapsts.excp and trapsts.excp_hi. // Maskable exceptions only cause the wave to enter the trap handler if // their respective bit in mode.excp_en is set. From ca70b26ee50ff97f858acc1dcceacbc4b7a6cc99 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Wed, 27 Sep 2023 10:56:13 -0400 Subject: [PATCH 1176/1868] drm/amdgpu: add sq host trap status check Before fire a new host trap, check the host trap status. -v6: add multiple instances support Signed-off-by: James Zhu Tested-by: Vladimir Indic --- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 36 +++++++++++++++++++ .../amd/include/asic_reg/gc/gc_9_0_offset.h | 2 ++ .../amd/include/asic_reg/gc/gc_9_0_sh_mask.h | 5 +++ 3 files changed, 43 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c index e00aace9ac8d8..0b63b79a8d988 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c @@ -1243,6 +1243,36 @@ uint64_t kgd_gfx_v9_hqd_reset(struct amdgpu_device *adev, return queue_addr; } +static uint32_t kgd_aldebaran_get_hosttrap_status(struct amdgpu_device *adev, + uint32_t inst) +{ + uint32_t sq_hosttrap_status = 0x0; + int i, j; + + mutex_lock(&adev->grbm_idx_mutex); + for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { + for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { + amdgpu_gfx_select_se_sh(adev, i, j, 0xffffffff, inst); + sq_hosttrap_status = RREG32_SOC15(GC, GET_INST(GC, inst), mmSQ_HOSTTRAP_STATUS); + + if (sq_hosttrap_status & SQ_HOSTTRAP_STATUS__HTPENDING_OVERRIDE_MASK) { + WREG32_SOC15(GC, GET_INST(GC, inst), mmSQ_HOSTTRAP_STATUS, + SQ_HOSTTRAP_STATUS__HTPENDING_OVERRIDE_MASK); + sq_hosttrap_status = 0x0; + continue; + } + if (sq_hosttrap_status) + goto out; + } + } + +out: + amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, inst); + mutex_unlock(&adev->grbm_idx_mutex); + + return sq_hosttrap_status; +} + uint32_t kgd_gfx_v9_trigger_pc_sample_trap(struct amdgpu_device *adev, uint32_t vmid, uint32_t max_wave_slot, @@ -1254,6 +1284,12 @@ uint32_t kgd_gfx_v9_trigger_pc_sample_trap(struct amdgpu_device *adev, { if (method == KFD_IOCTL_PCS_METHOD_HOSTTRAP) { uint32_t value = 0; + uint32_t sq_hosttrap_status = 0x0; + + sq_hosttrap_status = kgd_aldebaran_get_hosttrap_status(adev, inst); + /* skip when last host trap request is still pending to complete */ + if (sq_hosttrap_status) + return 0; value = REG_SET_FIELD(value, SQ_CMD, CMD, SQ_IND_CMD_CMD_TRAP); value = REG_SET_FIELD(value, SQ_CMD, MODE, SQ_IND_CMD_MODE_SINGLE); diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h index 12d451e5475b7..5b17d90664524 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_offset.h @@ -462,6 +462,8 @@ #define mmSQ_IND_DATA_BASE_IDX 0 #define mmSQ_CMD 0x037b #define mmSQ_CMD_BASE_IDX 0 +#define mmSQ_HOSTTRAP_STATUS 0x0376 +#define mmSQ_HOSTTRAP_STATUS_BASE_IDX 0 #define mmSQ_TIME_HI 0x037c #define mmSQ_TIME_HI_BASE_IDX 0 #define mmSQ_TIME_LO 0x037d diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h index 2dfa0e5b1aa3e..3e0210c2bf369 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_9_0_sh_mask.h @@ -2616,6 +2616,11 @@ //SQ_CMD_TIMESTAMP #define SQ_CMD_TIMESTAMP__TIMESTAMP__SHIFT 0x0 #define SQ_CMD_TIMESTAMP__TIMESTAMP_MASK 0x000000FFL +//SQ_HOSTTRAP_STATUS +#define SQ_HOSTTRAP_STATUS__HTPENDINGCOUNT__SHIFT 0x0 +#define SQ_HOSTTRAP_STATUS__HTPENDING_OVERRIDE__SHIFT 0x8 +#define SQ_HOSTTRAP_STATUS__HTPENDINGCOUNT_MASK 0x000000FFL +#define SQ_HOSTTRAP_STATUS__HTPENDING_OVERRIDE_MASK 0x00000100L //SQ_IND_INDEX #define SQ_IND_INDEX__WAVE_ID__SHIFT 0x0 #define SQ_IND_INDEX__SIMD_ID__SHIFT 0x4 From d1d2b70c3c85e85bcd86d5c80a9a04421a72923c Mon Sep 17 00:00:00 2001 From: James Zhu Date: Sat, 12 Aug 2023 11:58:46 -0400 Subject: [PATCH 1177/1868] drm/amdkfd: trigger pc sampling trap for arcturus Implement trigger pc sampling trap for arcturus. -v6: add multiple instances support Signed-off-by: James Zhu Tested-by: Vladimir Indic --- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c index 017e8a3013aaa..2f2c71f5cb283 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c @@ -390,6 +390,18 @@ static uint32_t kgd_arcturus_disable_debug_trap(struct amdgpu_device *adev, return 0; } + +static uint32_t kgd_arcturus_trigger_pc_sample_trap(struct amdgpu_device *adev, + uint32_t vmid, + uint32_t *target_simd, + uint32_t *target_wave_slot, + enum kfd_ioctl_pc_sample_method method, + uint32_t inst) +{ + return kgd_gfx_v9_trigger_pc_sample_trap(adev, vmid, 10, 4, + target_simd, target_wave_slot, method, inst); +} + const struct kfd2kgd_calls arcturus_kfd2kgd = { .program_sh_mem_settings = kgd_gfx_v9_program_sh_mem_settings, .set_pasid_vmid_mapping = kgd_gfx_v9_set_pasid_vmid_mapping, @@ -420,5 +432,6 @@ const struct kfd2kgd_calls arcturus_kfd2kgd = { .get_cu_occupancy = kgd_gfx_v9_get_cu_occupancy, .program_trap_handler_settings = kgd_gfx_v9_program_trap_handler_settings, .hqd_get_pq_addr = kgd_gfx_v9_hqd_get_pq_addr, - .hqd_reset = kgd_gfx_v9_hqd_reset + .hqd_reset = kgd_gfx_v9_hqd_reset, + .trigger_pc_sample_trap = kgd_arcturus_trigger_pc_sample_trap }; From 2c71fcb2ae3f2bc4188fafbb68f111d054cb9fe4 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Fri, 21 Jul 2023 14:15:57 -0400 Subject: [PATCH 1178/1868] drm/amdkfd: trigger pc sampling trap for aldebaran Implement trigger pc sampling trap for aldebaran. -v6: add multiple instances support Signed-off-by: James Zhu Tested-by: Vladimir Indic --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c index ff1ac35561ff4..0fdd76692e3a6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c @@ -164,6 +164,17 @@ static uint32_t kgd_gfx_aldebaran_set_address_watch( return watch_address_cntl; } +static uint32_t kgd_aldebaran_trigger_pc_sample_trap(struct amdgpu_device *adev, + uint32_t vmid, + uint32_t *target_simd, + uint32_t *target_wave_slot, + enum kfd_ioctl_pc_sample_method method, + uint32_t inst) +{ + return kgd_gfx_v9_trigger_pc_sample_trap(adev, vmid, 8, 4, + target_simd, target_wave_slot, method, inst); +} + const struct kfd2kgd_calls aldebaran_kfd2kgd = { .program_sh_mem_settings = kgd_gfx_v9_program_sh_mem_settings, .set_pasid_vmid_mapping = kgd_gfx_v9_set_pasid_vmid_mapping, @@ -194,4 +205,5 @@ const struct kfd2kgd_calls aldebaran_kfd2kgd = { .program_trap_handler_settings = kgd_gfx_v9_program_trap_handler_settings, .hqd_get_pq_addr = kgd_gfx_v9_hqd_get_pq_addr, .hqd_reset = kgd_gfx_v9_hqd_reset, + .trigger_pc_sample_trap = kgd_aldebaran_trigger_pc_sample_trap, }; From 52c7fc409c5bb5f9a8fa08210e48cecb643bc125 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Thu, 27 Jul 2023 20:20:20 -0400 Subject: [PATCH 1179/1868] drm/amdkfd: use bit operation set debug trap 1st level TMA's 2nd byte which used for trap type setting, to use bit operation to change selected bit only. Signed-off-by: James Zhu Tested-by: Vladimir Indic --- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 314c46aeafe54..f7b5618dbf79e 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -1457,13 +1457,23 @@ bool kfd_process_xnack_mode(struct kfd_process *p, bool supported) return true; } +/* bit offset in 1st-level TMA's 2nd byte which used for KFD_TRAP_TYPE_BIT */ +enum KFD_TRAP_TYPE_BIT { + KFD_TRAP_TYPE_DEBUG = 0, /* bit 0 for debug trap */ + KFD_TRAP_TYPE_HOST, + KFD_TRAP_TYPE_STOCHASTIC, +}; + void kfd_process_set_trap_debug_flag(struct qcm_process_device *qpd, bool enabled) { if (qpd->cwsr_kaddr) { - uint64_t *tma = - (uint64_t *)(qpd->cwsr_kaddr + KFD_CWSR_TMA_OFFSET); - tma[2] = enabled; + volatile unsigned long *tma = + (volatile unsigned long *)(qpd->cwsr_kaddr + KFD_CWSR_TMA_OFFSET); + if (enabled) + set_bit(KFD_TRAP_TYPE_DEBUG, &tma[2]); + else + clear_bit(KFD_TRAP_TYPE_DEBUG, &tma[2]); } } From f516128e2c2c7416756b2c636d25d9b1847bf9e9 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Fri, 21 Jul 2023 14:58:57 -0400 Subject: [PATCH 1180/1868] drm/amdkfd: add setting trap pc sampling flag Add setting trap pc sampling flag. Signed-off-by: James Zhu Tested-by: Vladimir Indic --- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 2 ++ drivers/gpu/drm/amd/amdkfd/kfd_process.c | 13 +++++++++++++ 2 files changed, 15 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index d3120fdb82f36..c24b81c088f3c 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -1296,6 +1296,8 @@ void kfd_process_set_trap_handler(struct qcm_process_device *qpd, uint64_t tma_addr); void kfd_process_set_trap_debug_flag(struct qcm_process_device *qpd, bool enabled); +void kfd_process_set_trap_pc_sampling_flag(struct qcm_process_device *qpd, + enum kfd_ioctl_pc_sample_method method, bool enabled); /* CWSR initialization */ int kfd_process_init_cwsr_apu(struct kfd_process *process, struct file *filep); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index f7b5618dbf79e..e249c9b799be8 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -1477,6 +1477,19 @@ void kfd_process_set_trap_debug_flag(struct qcm_process_device *qpd, } } +void kfd_process_set_trap_pc_sampling_flag(struct qcm_process_device *qpd, + enum kfd_ioctl_pc_sample_method method, bool enabled) +{ + if (qpd->cwsr_kaddr) { + volatile unsigned long *tma = + (volatile unsigned long *)(qpd->cwsr_kaddr + KFD_CWSR_TMA_OFFSET); + if (enabled) + set_bit(method, &tma[2]); + else + clear_bit(method, &tma[2]); + } +} + /* * On return the kfd_process is fully operational and will be freed when the * mm is released From bd5d540852b15b1ecf8b6e5987a234e36f14df69 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Fri, 21 Jul 2023 17:10:08 -0400 Subject: [PATCH 1181/1868] drm/amdkfd: enable pc sampling stop Enable pc sampling stop. Signed-off-by: James Zhu Tested-by: Vladimir Indic --- drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 19 ++++++++++++++++--- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 3 +++ 2 files changed, 19 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index b46caa52fbe83..8796c6c28172e 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -99,10 +99,23 @@ static int kfd_pc_sample_start(struct kfd_process_device *pdd) return -EINVAL; } -static int kfd_pc_sample_stop(struct kfd_process_device *pdd) +static int kfd_pc_sample_stop(struct kfd_process_device *pdd, + struct pc_sampling_entry *pcs_entry) { - return -EINVAL; + bool pc_sampling_stop = false; + + pcs_entry->enabled = false; + mutex_lock(&pdd->dev->pcs_data.mutex); + pdd->dev->pcs_data.hosttrap_entry.base.active_count--; + if (!pdd->dev->pcs_data.hosttrap_entry.base.active_count) + pc_sampling_stop = true; + mutex_unlock(&pdd->dev->pcs_data.mutex); + + kfd_process_set_trap_pc_sampling_flag(&pdd->qpd, + pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_info.method, false); + + return 0; } static int kfd_pc_sample_create(struct kfd_process_device *pdd, @@ -250,7 +263,7 @@ int kfd_pc_sample(struct kfd_process_device *pdd, if (!pcs_entry->enabled) return -EALREADY; else - return kfd_pc_sample_stop(pdd); + return kfd_pc_sample_stop(pdd, pcs_entry); } return -EINVAL; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index c24b81c088f3c..62e254b5fcfaa 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -287,6 +287,9 @@ struct kfd_dev; struct kfd_dev_pc_sampling_data { uint32_t use_count; /* Num of PC sampling sessions */ + uint32_t active_count; /* Num of active sessions */ + uint32_t target_simd; /* target simd for trap */ + uint32_t target_wave_slot; /* target wave slot for trap */ struct idr pc_sampling_idr; struct kfd_pc_sample_info pc_sample_info; }; From 2fc6dec9bfab5c1eabea4d413b790203cf600d97 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Sun, 6 Aug 2023 13:07:28 -0400 Subject: [PATCH 1182/1868] drm/amdkfd: add queue remapping Add queue remapping to ensure that any waves executing the PC sampling part of the trap handler are done before kfd_pc_sample_stop returns, and that no new waves enter that part of the trap handler afterwards. This avoids race conditions that could lead to use-after-free. Unmapping and remapping the queues either waits for the waves to drain, or preempts them with CWSR, which itself executes a trap and waits for previous traps to finish. Signed-off-by: James Zhu Tested-by: Vladimir Indic --- drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 11 +++++++++++ drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h | 5 +++++ drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 3 +++ 3 files changed, 19 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index eae541b9b9deb..81bfa6eb7e093 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -3375,6 +3375,17 @@ int debug_refresh_runlist(struct device_queue_manager *dqm) return debug_map_and_unlock(dqm); } +void remap_queue(struct device_queue_manager *dqm, + enum kfd_unmap_queues_filter filter, + uint32_t filter_param, + uint32_t grace_period) +{ + dqm_lock(dqm); + if (!dqm->dev->kfd->shared_resources.enable_mes) + execute_queues_cpsch(dqm, filter, filter_param, grace_period); + dqm_unlock(dqm); +} + #if defined(CONFIG_DEBUG_FS) static void seq_reg_dump(struct seq_file *m, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h index e570abecb337a..710c9a53161eb 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h @@ -318,6 +318,11 @@ int debug_lock_and_unmap(struct device_queue_manager *dqm); int debug_map_and_unlock(struct device_queue_manager *dqm); int debug_refresh_runlist(struct device_queue_manager *dqm); +void remap_queue(struct device_queue_manager *dqm, + enum kfd_unmap_queues_filter filter, + uint32_t filter_param, + uint32_t grace_period); + static inline unsigned int get_sh_mem_bases_32(struct kfd_process_device *pdd) { return (pdd->lds_base >> 16) & 0xFF; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index 8796c6c28172e..5d78fb38620dd 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -24,6 +24,7 @@ #include "kfd_priv.h" #include "amdgpu_amdkfd.h" #include "kfd_pc_sampling.h" +#include "kfd_device_queue_manager.h" struct supported_pc_sample_info { uint32_t ip_version; @@ -114,6 +115,8 @@ static int kfd_pc_sample_stop(struct kfd_process_device *pdd, kfd_process_set_trap_pc_sampling_flag(&pdd->qpd, pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_info.method, false); + remap_queue(pdd->dev->dqm, + KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD); return 0; } From cb22aefa59d221f69de3792c0abb9f461ad70b6e Mon Sep 17 00:00:00 2001 From: James Zhu Date: Fri, 21 Jul 2023 17:03:13 -0400 Subject: [PATCH 1183/1868] drm/amdkfd: enable pc sampling start Enable pc sampling start. Signed-off-by: James Zhu Tested-by: Vladimir Indic --- drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index 5d78fb38620dd..e3512c6dec5e2 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -95,9 +95,23 @@ static int kfd_pc_sample_query_cap(struct kfd_process_device *pdd, return 0; } -static int kfd_pc_sample_start(struct kfd_process_device *pdd) +static int kfd_pc_sample_start(struct kfd_process_device *pdd, + struct pc_sampling_entry *pcs_entry) { - return -EINVAL; + bool pc_sampling_start = false; + + pcs_entry->enabled = true; + mutex_lock(&pdd->dev->pcs_data.mutex); + + kfd_process_set_trap_pc_sampling_flag(&pdd->qpd, + pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_info.method, true); + + if (!pdd->dev->pcs_data.hosttrap_entry.base.active_count) + pc_sampling_start = true; + pdd->dev->pcs_data.hosttrap_entry.base.active_count++; + mutex_unlock(&pdd->dev->pcs_data.mutex); + + return 0; } static int kfd_pc_sample_stop(struct kfd_process_device *pdd, @@ -260,7 +274,7 @@ int kfd_pc_sample(struct kfd_process_device *pdd, if (pcs_entry->enabled) return -EALREADY; else - return kfd_pc_sample_start(pdd); + return kfd_pc_sample_start(pdd, pcs_entry); case KFD_IOCTL_PCS_OP_STOP: if (!pcs_entry->enabled) From 57ec8637179a9ff25aa8a30f279d8ec73ff2fef3 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Fri, 21 Jul 2023 18:42:49 -0400 Subject: [PATCH 1184/1868] drm/amdkfd: add pc sampling thread to trigger trap Add a kthread to trigger pc sampling trap. -v6: add multiple instances support Signed-off-by: James Zhu Tested-by: Vladimir Indic --- drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 103 ++++++++++++++++++- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 1 + 2 files changed, 103 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index e3512c6dec5e2..fc991dd893b18 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -39,6 +39,92 @@ struct supported_pc_sample_info supported_formats[] = { { IP_VERSION(9, 4, 2), &sample_info_hosttrap_9_0_0 }, }; +static int kfd_pc_sample_thread(void *param) +{ + struct amdgpu_device *adev; + struct kfd_node *node = param; + uint32_t timeout = 0; + ktime_t next_trap_time; + bool need_wait; + + mutex_lock(&node->pcs_data.mutex); + if (node->pcs_data.hosttrap_entry.base.active_count && + node->pcs_data.hosttrap_entry.base.pc_sample_info.interval && + node->kfd2kgd->trigger_pc_sample_trap) { + switch (node->pcs_data.hosttrap_entry.base.pc_sample_info.type) { + case KFD_IOCTL_PCS_TYPE_TIME_US: + timeout = (uint32_t)node->pcs_data.hosttrap_entry.base.pc_sample_info.interval; + break; + default: + pr_debug("PC Sampling type %d not supported.", + node->pcs_data.hosttrap_entry.base.pc_sample_info.type); + } + } + mutex_unlock(&node->pcs_data.mutex); + if (!timeout) + return -EINVAL; + + adev = node->adev; + need_wait = false; + allow_signal(SIGKILL); + while (!kthread_should_stop() && + !signal_pending(node->pcs_data.hosttrap_entry.base.pc_sample_thread)) { + if (!need_wait) { + uint32_t inst; + + next_trap_time = ktime_add_us(ktime_get_raw(), timeout); + + for_each_inst(inst, node->xcc_mask) { + node->kfd2kgd->trigger_pc_sample_trap(adev, node->vm_info.last_vmid_kfd, + &node->pcs_data.hosttrap_entry.base.target_simd, + &node->pcs_data.hosttrap_entry.base.target_wave_slot, + node->pcs_data.hosttrap_entry.base.pc_sample_info.method, + inst); + } + pr_debug_ratelimited("triggered a host trap."); + need_wait = true; + } else { + ktime_t wait_time; + s64 wait_ns, wait_us; + + wait_time = ktime_sub(next_trap_time, ktime_get_raw()); + wait_ns = ktime_to_ns(wait_time); + wait_us = ktime_to_us(wait_time); + if (wait_ns >= 10000) + usleep_range(wait_us - 10, wait_us); + else if (wait_ns > 0) + schedule(); + else + need_wait = false; + } + } + + node->pcs_data.hosttrap_entry.base.target_simd = 0; + node->pcs_data.hosttrap_entry.base.target_wave_slot = 0; + node->pcs_data.hosttrap_entry.base.pc_sample_thread = NULL; + + return 0; +} + +static int kfd_pc_sample_thread_start(struct kfd_node *node) +{ + char thread_name[16]; + int ret = 0; + + snprintf(thread_name, 16, "pcs_%d", node->adev->ddev.render->index); + node->pcs_data.hosttrap_entry.base.pc_sample_thread = + kthread_run(kfd_pc_sample_thread, node, thread_name); + + if (IS_ERR(node->pcs_data.hosttrap_entry.base.pc_sample_thread)) { + ret = PTR_ERR(node->pcs_data.hosttrap_entry.base.pc_sample_thread); + node->pcs_data.hosttrap_entry.base.pc_sample_thread = NULL; + pr_debug("Failed to create pc sample thread for %s with ret = %d.", + thread_name, ret); + } + + return ret; +} + static int kfd_pc_sample_query_cap(struct kfd_process_device *pdd, struct kfd_ioctl_pc_sample_args __user *user_args) { @@ -99,6 +185,7 @@ static int kfd_pc_sample_start(struct kfd_process_device *pdd, struct pc_sampling_entry *pcs_entry) { bool pc_sampling_start = false; + int ret = 0; pcs_entry->enabled = true; mutex_lock(&pdd->dev->pcs_data.mutex); @@ -108,10 +195,21 @@ static int kfd_pc_sample_start(struct kfd_process_device *pdd, if (!pdd->dev->pcs_data.hosttrap_entry.base.active_count) pc_sampling_start = true; + pdd->dev->pcs_data.hosttrap_entry.base.active_count++; mutex_unlock(&pdd->dev->pcs_data.mutex); - return 0; + while (pc_sampling_start) { + /* true means pc_sample_thread stop is in progress */ + if (READ_ONCE(pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_thread)) { + usleep_range(1000, 2000); + } else { + ret = kfd_pc_sample_thread_start(pdd->dev); + break; + } + } + + return ret; } static int kfd_pc_sample_stop(struct kfd_process_device *pdd, @@ -132,6 +230,9 @@ static int kfd_pc_sample_stop(struct kfd_process_device *pdd, remap_queue(pdd->dev->dqm, KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0, USE_DEFAULT_GRACE_PERIOD); + if (pc_sampling_stop) + kthread_stop(pdd->dev->pcs_data.hosttrap_entry.base.pc_sample_thread); + return 0; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 62e254b5fcfaa..d018514e1dbce 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -291,6 +291,7 @@ struct kfd_dev_pc_sampling_data { uint32_t target_simd; /* target simd for trap */ uint32_t target_wave_slot; /* target wave slot for trap */ struct idr pc_sampling_idr; + struct task_struct *pc_sample_thread; struct kfd_pc_sample_info pc_sample_info; }; From 8ecbacc60fcc54772958d7edab01f3fdbb8279c6 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Fri, 21 Jul 2023 18:48:43 -0400 Subject: [PATCH 1185/1868] drm/amdkfd: add pc sampling release when process release Add pc sampling release when process release, it will force to stop all activate sessions with this process. Signed-off-by: James Zhu Tested-by: Vladimir Indic --- drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 25 ++++++++++++++++++++ drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.h | 1 + drivers/gpu/drm/amd/amdkfd/kfd_process.c | 3 +++ 3 files changed, 29 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index fc991dd893b18..94bd601129c1f 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -337,6 +337,31 @@ static int kfd_pc_sample_destroy(struct kfd_process_device *pdd, uint32_t trace_ return 0; } +void kfd_pc_sample_release(struct kfd_process_device *pdd) +{ + struct pc_sampling_entry *pcs_entry; + struct idr *idp; + uint32_t id; + + /* force to release all PC sampling task for this process */ + idp = &pdd->dev->pcs_data.hosttrap_entry.base.pc_sampling_idr; + do { + pcs_entry = NULL; + mutex_lock(&pdd->dev->pcs_data.mutex); + idr_for_each_entry(idp, pcs_entry, id) { + if (pcs_entry->pdd != pdd) + continue; + break; + } + mutex_unlock(&pdd->dev->pcs_data.mutex); + if (pcs_entry) { + if (pcs_entry->enabled) + kfd_pc_sample_stop(pdd, pcs_entry); + kfd_pc_sample_destroy(pdd, id, pcs_entry); + } + } while (pcs_entry); +} + int kfd_pc_sample(struct kfd_process_device *pdd, struct kfd_ioctl_pc_sample_args __user *args) { diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.h b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.h index 4eeded4ea5b6c..6175563ca9bea 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.h @@ -30,5 +30,6 @@ int kfd_pc_sample(struct kfd_process_device *pdd, struct kfd_ioctl_pc_sample_args __user *args); +void kfd_pc_sample_release(struct kfd_process_device *pdd); #endif /* KFD_PC_SAMPLING_H_ */ diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index e249c9b799be8..bccbdf951dfd1 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -44,6 +44,7 @@ struct mm_struct; #include "kfd_trace.h" #include "kfd_smi_events.h" #include "kfd_debug.h" +#include "kfd_pc_sampling.h" /* * List of struct kfd_process (field kfd_process). @@ -1017,6 +1018,8 @@ static void kfd_process_destroy_pdds(struct kfd_process *p) pr_debug("Releasing pdd (topology id %d) for process (pasid 0x%x)\n", pdd->dev->id, p->pasid); + kfd_pc_sample_release(pdd); + kfd_process_device_destroy_cwsr_dgpu(pdd); kfd_process_device_destroy_ib_mem(pdd); From 7311c95e898570d5cdff184e97d072047f04ed16 Mon Sep 17 00:00:00 2001 From: David Yat Sin Date: Thu, 14 Dec 2023 18:45:49 +0000 Subject: [PATCH 1186/1868] drm/amdkfd: Set debug trap bit when enabling PC Sampling We need the SPI_GDBG_PER_VMID_CNTL.TRAP_EN bit to be set during PC Sampling so that the TTMP registers are valid inside the sampling data. runtime_info.ttmp_setup will be cleared when the user application does the AMDKFD_IOC_RUNTIME_ENABLE ioctl without KFD_RUNTIME_ENABLE_MODE_ENABLE_MASK flag on exit. It is also not valid to have the debugger attached to a process while PC sampling is enabled so adding some checks to prevent this. Co-developed-by: James Zhu Signed-off-by: David Yat Sin Signed-off-by: James Zhu Tested-by: Vladimir Indic --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 30 ++++++-------------- drivers/gpu/drm/amd/amdkfd/kfd_debug.c | 26 +++++++++++++++++ drivers/gpu/drm/amd/amdkfd/kfd_debug.h | 3 ++ drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 13 +++++++++ drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 3 ++ 5 files changed, 54 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index eb6e461f968b0..e9ac473ee67c9 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -3009,26 +3009,9 @@ static int runtime_enable(struct kfd_process *p, uint64_t r_debug, p->runtime_info.runtime_state = DEBUG_RUNTIME_STATE_ENABLED; p->runtime_info.r_debug = r_debug; - p->runtime_info.ttmp_setup = enable_ttmp_setup; - if (p->runtime_info.ttmp_setup) { - for (i = 0; i < p->n_pdds; i++) { - struct kfd_process_device *pdd = p->pdds[i]; - - if (!kfd_dbg_is_rlc_restore_supported(pdd->dev)) { - amdgpu_gfx_off_ctrl(pdd->dev->adev, false); - pdd->dev->kfd2kgd->enable_debug_trap( - pdd->dev->adev, - true, - pdd->dev->vm_info.last_vmid_kfd); - } else if (kfd_dbg_is_per_vmid_supported(pdd->dev)) { - pdd->spi_dbg_override = pdd->dev->kfd2kgd->enable_debug_trap( - pdd->dev->adev, - false, - 0); - } - } - } + if (enable_ttmp_setup) + kfd_dbg_enable_ttmp_setup(p); retry: if (p->debug_trap_enabled) { @@ -3178,10 +3161,10 @@ static int kfd_ioctl_set_debug_trap(struct file *filep, struct kfd_process *p, v goto out; } - /* Check if target is still PTRACED. */ rcu_read_lock(); + /* Check if target is still PTRACED. */ if (target != p && args->op != KFD_IOC_DBG_TRAP_DISABLE - && ptrace_parent(target->lead_thread) != current) { + && ptrace_parent(target->lead_thread) != current) { pr_err("PID %i is not PTRACED and cannot be debugged\n", args->pid); r = -EPERM; } @@ -3191,6 +3174,11 @@ static int kfd_ioctl_set_debug_trap(struct file *filep, struct kfd_process *p, v goto out; mutex_lock(&target->mutex); + if (!!target->pc_sampling_ref) { + pr_debug("Cannot enable debug trap on PID:%d because PC Sampling active\n", args->pid); + r = -EBUSY; + goto unlock_out; + } if (args->op != KFD_IOC_DBG_TRAP_ENABLE && !target->debug_trap_enabled) { pr_err("PID %i not debug enabled for op %i\n", args->pid, args->op); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_debug.c b/drivers/gpu/drm/amd/amdkfd/kfd_debug.c index 312dfa84f29f8..dfb78d135e497 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_debug.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_debug.c @@ -1133,3 +1133,29 @@ void kfd_dbg_set_enabled_debug_exception_mask(struct kfd_process *target, mutex_unlock(&target->event_mutex); } + +void kfd_dbg_enable_ttmp_setup(struct kfd_process *p) +{ + int i; + + if (p->runtime_info.ttmp_setup) + return; + + p->runtime_info.ttmp_setup = true; + for (i = 0; i < p->n_pdds; i++) { + struct kfd_process_device *pdd = p->pdds[i]; + + if (!kfd_dbg_is_rlc_restore_supported(pdd->dev)) { + amdgpu_gfx_off_ctrl(pdd->dev->adev, false); + pdd->dev->kfd2kgd->enable_debug_trap( + pdd->dev->adev, + true, + pdd->dev->vm_info.last_vmid_kfd); + } else if (kfd_dbg_is_per_vmid_supported(pdd->dev)) { + pdd->spi_dbg_override = pdd->dev->kfd2kgd->enable_debug_trap( + pdd->dev->adev, + false, + 0); + } + } +} diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_debug.h b/drivers/gpu/drm/amd/amdkfd/kfd_debug.h index 924d0fd85dfb8..395fb3e1feb57 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_debug.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_debug.h @@ -91,6 +91,9 @@ int kfd_dbg_trap_device_snapshot(struct kfd_process *target, void kfd_dbg_set_enabled_debug_exception_mask(struct kfd_process *target, uint64_t exception_set_mask); + +void kfd_dbg_enable_ttmp_setup(struct kfd_process *p); + /* * If GFX off is enabled, chips that do not support RLC restore for the debug * registers will disable GFX off temporarily for the entire debug session. diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index 94bd601129c1f..fc5333603613b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -24,6 +24,7 @@ #include "kfd_priv.h" #include "amdgpu_amdkfd.h" #include "kfd_pc_sampling.h" +#include "kfd_debug.h" #include "kfd_device_queue_manager.h" struct supported_pc_sample_info { @@ -312,6 +313,14 @@ static int kfd_pc_sample_create(struct kfd_process_device *pdd, pcs_entry->pdd = pdd; user_args->trace_id = (uint32_t)i; + /* + * Set SPI_GDBG_PER_VMID_CNTL.TRAP_EN so that TTMP registers are valid in the sampling data + * p->runtime_info.ttmp_setup will be cleared when user application calls runtime_disable + * on exit. + */ + kfd_dbg_enable_ttmp_setup(pdd->process); + pdd->process->pc_sampling_ref++; + pr_debug("alloc pcs_entry = %p, trace_id = 0x%x on gpu 0x%x", pcs_entry, i, pdd->dev->id); return 0; @@ -323,6 +332,7 @@ static int kfd_pc_sample_destroy(struct kfd_process_device *pdd, uint32_t trace_ pr_debug("free pcs_entry = %p, trace_id = 0x%x on gpu 0x%x", pcs_entry, trace_id, pdd->dev->id); + pdd->process->pc_sampling_ref--; mutex_lock(&pdd->dev->pcs_data.mutex); pdd->dev->pcs_data.hosttrap_entry.base.use_count--; idr_remove(&pdd->dev->pcs_data.hosttrap_entry.base.pc_sampling_idr, trace_id); @@ -381,6 +391,9 @@ int kfd_pc_sample(struct kfd_process_device *pdd, if (!pcs_entry || pcs_entry->pdd != pdd) return -EINVAL; + } else if (pdd->process->debug_trap_enabled) { + pr_debug("Cannot have PC Sampling and debug trap simultaneously"); + return -EBUSY; } switch (args->op) { diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index d018514e1dbce..7ca3d626cd345 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -1099,6 +1099,9 @@ struct kfd_process { struct semaphore runtime_enable_sema; bool is_runtime_retry; struct kfd_runtime_info runtime_info; + + /* Indicates process' PC Sampling ref cnt*/ + uint32_t pc_sampling_ref; }; #define KFD_PROCESS_TABLE_SIZE 5 /* bits: 32 entries */ From 49c9868f3dd8d54c33d23606e81b3cf3e3971aa0 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 4 Mar 2024 16:05:46 +0800 Subject: [PATCH 1187/1868] drm/amdkcl: fake macros DRM_EDID_RANGE_OFFSET_{MIN/MAX}_{VFREQ/HFREQ} It's caused by 5f3e0476a2e2efe4595b4579e74a6028400abbfd "drm/amd/display: handle range offsets in VRR ranges" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- include/kcl/kcl_drm_edid.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/include/kcl/kcl_drm_edid.h b/include/kcl/kcl_drm_edid.h index dd472225c0477..b121281e6f45a 100644 --- a/include/kcl/kcl_drm_edid.h +++ b/include/kcl/kcl_drm_edid.h @@ -11,4 +11,11 @@ ((product_id) & 0xffff)) #endif /* drm_edid_encode_panel_id */ +#ifndef DRM_EDID_RANGE_OFFSET_MIN_VFREQ +#define DRM_EDID_RANGE_OFFSET_MIN_VFREQ (1 << 0) /* 1.4 */ +#define DRM_EDID_RANGE_OFFSET_MAX_VFREQ (1 << 1) /* 1.4 */ +#define DRM_EDID_RANGE_OFFSET_MIN_HFREQ (1 << 2) /* 1.4 */ +#define DRM_EDID_RANGE_OFFSET_MAX_HFREQ (1 << 3) /* 1.4 */ +#endif + #endif From b9a94495ac87ef298c65ac1867685a42ef75a5f8 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 4 Mar 2024 10:37:18 +0800 Subject: [PATCH 1188/1868] drm/amdkcl: modify kcl code under macro HAVE_STRUCT_XARRAY some kcl code under macro HAVE_STRUCT_XARRAY could be implemented by spin_lock_irqsave, so improve these code. Signed-off-by: Bob Zhou Reviewed-by: Asher Song Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 12 ++++++++++-- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 14 +++++++++++--- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 2 -- drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 2 -- drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 2 -- drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 4 ++-- 7 files changed, 25 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index 4ec312b65a7d5..cb12c0ca46450 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -1303,7 +1303,7 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) return copy_to_user(out, max_ibs, min((size_t)size, sizeof(max_ibs))) ? -EFAULT : 0; } -#ifdef HAVE_STRUCT_XARRAY + case AMDGPU_INFO_GPUVM_FAULT: { struct amdgpu_fpriv *fpriv = filp->driver_priv; struct amdgpu_vm *vm = &fpriv->vm; @@ -1315,16 +1315,24 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) memset(&gpuvm_fault, 0, sizeof(gpuvm_fault)); +#ifdef HAVE_STRUCT_XARRAY xa_lock_irqsave(&adev->vm_manager.pasids, flags); +#else + spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); +#endif gpuvm_fault.addr = vm->fault_info.addr; gpuvm_fault.status = vm->fault_info.status; gpuvm_fault.vmhub = vm->fault_info.vmhub; +#ifdef HAVE_STRUCT_XARRAY xa_unlock_irqrestore(&adev->vm_manager.pasids, flags); +#else + spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); +#endif return copy_to_user(out, &gpuvm_fault, min((size_t)size, sizeof(gpuvm_fault))) ? -EFAULT : 0; } -#endif + default: DRM_DEBUG_KMS("Invalid request %d\n", info->query); return -EINVAL; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 18833975bb043..66e8baaa12619 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -3046,7 +3046,7 @@ void amdgpu_debugfs_vm_bo_info(struct amdgpu_vm *vm, struct seq_file *m) * * Cache the fault info for later use by userspace in debugging. */ -#ifdef HAVE_STRUCT_XARRAY + void amdgpu_vm_update_fault_cache(struct amdgpu_device *adev, unsigned int pasid, uint64_t addr, @@ -3056,9 +3056,14 @@ void amdgpu_vm_update_fault_cache(struct amdgpu_device *adev, struct amdgpu_vm *vm; unsigned long flags; +#ifdef HAVE_STRUCT_XARRAY xa_lock_irqsave(&adev->vm_manager.pasids, flags); - vm = xa_load(&adev->vm_manager.pasids, pasid); +#else + spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); + vm = idr_find(&adev->vm_manager.pasid_idr, pasid); +#endif + /* Don't update the fault cache if status is 0. In the multiple * fault case, subsequent faults will return a 0 status which is * useless for userspace and replaces the useful fault status, so @@ -3091,9 +3096,12 @@ void amdgpu_vm_update_fault_cache(struct amdgpu_device *adev, WARN_ONCE(1, "Invalid vmhub %u\n", vmhub); } } +#ifdef HAVE_STRUCT_XARRAY xa_unlock_irqrestore(&adev->vm_manager.pasids, flags); -} +#else + spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); #endif +} /** * amdgpu_vm_is_bo_always_valid - check if the BO is VM always valid diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h index ec8eaae4d7c81..96e483bddd7bf 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h @@ -654,13 +654,11 @@ static inline void amdgpu_vm_eviction_unlock(struct amdgpu_vm *vm) mutex_unlock(&vm->eviction_lock); } -#ifdef HAVE_STRUCT_XARRAY void amdgpu_vm_update_fault_cache(struct amdgpu_device *adev, unsigned int pasid, uint64_t addr, uint32_t status, unsigned int vmhub); -#endif void amdgpu_vm_tlb_fence_create(struct amdgpu_device *adev, struct amdgpu_vm *vm, diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c index c336ae015694b..fe30dec1b8d74 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c @@ -149,10 +149,8 @@ static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev, status = RREG32(hub->vm_l2_pro_fault_status); WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); -#ifdef HAVE_STRUCT_XARRAY amdgpu_vm_update_fault_cache(adev, entry->pasid, addr, status, entry->vmid_src ? AMDGPU_MMHUB0(0) : AMDGPU_GFXHUB(0)); -#endif } if (!printk_ratelimit()) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c index 3d697c79db7ca..63ad403eb5fb5 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c @@ -120,10 +120,8 @@ static int gmc_v11_0_process_interrupt(struct amdgpu_device *adev, status = RREG32(hub->vm_l2_pro_fault_status); WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); -#ifdef HAVE_STRUCT_XARRAY amdgpu_vm_update_fault_cache(adev, entry->pasid, addr, status, entry->vmid_src ? AMDGPU_MMHUB0(0) : AMDGPU_GFXHUB(0)); -#endif } if (printk_ratelimit()) { diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c index 3a21d4a3c3069..f24ed94b2132c 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c @@ -1265,10 +1265,10 @@ static int gmc_v7_0_process_interrupt(struct amdgpu_device *adev, if (!addr && !status) return 0; -#ifdef HAVE_STRUCT_XARRAY + amdgpu_vm_update_fault_cache(adev, entry->pasid, ((u64)addr) << AMDGPU_GPU_PAGE_SHIFT, status, AMDGPU_GFXHUB(0)); -#endif + if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST) gmc_v7_0_set_fault_enable_default(adev, false); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index dbb59e63c5720..4da5125287b37 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -1439,10 +1439,10 @@ static int gmc_v8_0_process_interrupt(struct amdgpu_device *adev, if (!addr && !status) return 0; -#ifdef HAVE_STRUCT_XARRAY + amdgpu_vm_update_fault_cache(adev, entry->pasid, ((u64)addr) << AMDGPU_GPU_PAGE_SHIFT, status, AMDGPU_GFXHUB(0)); -#endif + if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_FIRST) gmc_v8_0_set_fault_enable_default(adev, false); From 8b794a513f200226a93445d30f48e64e27babd8a Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 8 Mar 2024 10:02:45 +0800 Subject: [PATCH 1189/1868] drm/amdkcl: fake macro CAP_PERFMON It's caused by 68592cff2583a71a6af1810a687bc5f86aaafea3 "drm/amdkfd: add pc sampling support" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- include/kcl/kcl_capability.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/kcl/kcl_capability.h b/include/kcl/kcl_capability.h index 2cc984db5ac19..52448ad625f96 100644 --- a/include/kcl/kcl_capability.h +++ b/include/kcl/kcl_capability.h @@ -28,4 +28,8 @@ #define CAP_CHECKPOINT_RESTORE CAP_SYS_ADMIN #endif +#ifndef CAP_PERFMON +#define CAP_PERFMON 38 +#endif + #endif From 7581477000c8faab42dc4c0d34ee270e7025e87b Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 8 Mar 2024 15:57:48 +0800 Subject: [PATCH 1190/1868] drm/amdkcl: modify struct kfd_class to non-const For some old kernel, the device_create and class_register APIs use the non-const param, so when define the struct kfd_class to const that causes unpredictable issue. v6.3-rc1-21-g2bd5c63978b7 "driver core: device: make device_create*() take a const struct class *" v6.3-rc5-105-g43a7206b0963 "driver core: class: make class_register() take a const *" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index e9ac473ee67c9..9f22c14e13b54 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -68,7 +68,7 @@ static const struct file_operations kfd_fops = { static int kfd_char_dev_major = -1; struct device *kfd_device; -static const struct class kfd_class = { +static struct class kfd_class = { .name = kfd_dev_name, }; From 7f32105fa3cea5931a704e515704f56f253cbbe6 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 11 Mar 2024 13:09:34 +0800 Subject: [PATCH 1191/1868] drm/amdkcl: fake macro DRM_EDID_FEATURE_CONTINUOUS_FREQ It's caused by db3e4f1cbb842e29999fa2dbc5cec4341aade464 "drm/amd/display: Use freesync when `DRM_EDID_FEATURE_CONTINUOUS_FREQ` found" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- include/kcl/kcl_drm_edid.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/include/kcl/kcl_drm_edid.h b/include/kcl/kcl_drm_edid.h index b121281e6f45a..0e5b0fab8f8e3 100644 --- a/include/kcl/kcl_drm_edid.h +++ b/include/kcl/kcl_drm_edid.h @@ -18,4 +18,8 @@ #define DRM_EDID_RANGE_OFFSET_MAX_HFREQ (1 << 3) /* 1.4 */ #endif +#ifndef DRM_EDID_FEATURE_CONTINUOUS_FREQ +#define DRM_EDID_FEATURE_CONTINUOUS_FREQ (1 << 0) /* 1.4 */ +#endif + #endif From 01b4d6450494372f30e2d079708130a8b75c68c1 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 15 Mar 2024 10:18:09 +0800 Subject: [PATCH 1192/1868] drm/amdkcl: fake macros PCI_ERROR_RESPONSE It's caused by bedb8766222115ae69345fe158eb3cd8027da3f7 "drm/amdgpu: Do a basic health check before reset" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- include/kcl/kcl_pci.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/kcl/kcl_pci.h b/include/kcl/kcl_pci.h index 26bb0043066a0..d9ea67cc3dee3 100644 --- a/include/kcl/kcl_pci.h +++ b/include/kcl/kcl_pci.h @@ -97,6 +97,12 @@ 0) #endif +#ifndef PCI_ERROR_RESPONSE +#define PCI_ERROR_RESPONSE (~0ULL) +#define PCI_SET_ERROR_RESPONSE(val) (*(val) = ((typeof(*(val))) PCI_ERROR_RESPONSE)) +#define PCI_POSSIBLE_ERROR(val) ((val) == ((typeof(val)) PCI_ERROR_RESPONSE)) +#endif + static inline enum pci_bus_speed kcl_pcie_get_speed_cap(struct pci_dev *dev) { return pcie_get_speed_cap(dev); From e2d85374f96ff3eea3703c599c0fb11f1a017e8b Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 22 Mar 2024 16:44:07 +0800 Subject: [PATCH 1193/1868] drm/amdkcl: check dgb_printer whether defined Signed-off-by: Asher Song --- .../gpu/drm/amd/dkms/m4/drm_debug_enabled.m4 | 18 ++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/backport/kcl_drm_print.h | 12 ++++++++++++ 3 files changed, 31 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_debug_enabled.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_debug_enabled.m4 index 0250d30115d15..38c1584359f8b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_debug_enabled.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_debug_enabled.m4 @@ -15,3 +15,21 @@ AC_DEFUN([AC_AMDGPU_DRM_DEBUG_ENABLED], [ ]) ]) ]) + +dnl # +dnl # commit v6.8-rc3-242-g9fd6f61a297e +dnl # drm/print: add drm_dbg_printer() for drm device specific printer +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DBG_PRINTER], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + drm_dbg_printer(NULL, 0, NULL); + ],[ + AC_DEFINE(HAVE_DRM_DBG_PRINTER, + 1, + [drm_dbg_printer() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 331ffdd6d037d..76406fca34fe7 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -229,6 +229,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DMA_FENCE_IS_LATER_OR_SAME AC_AMDGPU_WORKQUEUE AC_AMDGPU_DRM_EXEC_INIT + AC_AMDGPU_DRM_DBG_PRINTER AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/backport/kcl_drm_print.h b/include/kcl/backport/kcl_drm_print.h index 379308c2563d4..5dc86123ce523 100644 --- a/include/kcl/backport/kcl_drm_print.h +++ b/include/kcl/backport/kcl_drm_print.h @@ -48,4 +48,16 @@ void _kcl_drm_print_bits(struct drm_printer *p, unsigned long value, #define drm_print_bits _kcl_drm_print_bits #endif + +#ifndef HAVE_DRM_DBG_PRINTER +static inline +struct drm_printer _kcl_drm_dbg_printer(struct drm_device *drm, + enum drm_debug_category category, + const char *prefix) +{ + return drm_debug_printer(prefix); +} +#define drm_dbg_printer _kcl_drm_dbg_printer +#endif + #endif From 3fb5eba896f8bd1f3ef7e0910cccffe4eaa14e2e Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 22 Mar 2024 17:09:33 +0800 Subject: [PATCH 1194/1868] drm/amdkcl: check drm_gem_object_is_shared_for_memory_stats whether exits It's caused by v6.8-rc3-288-gba1a58d5b907 drm/amdgpu: add shared fdinfo stats Signed-off-by: Asher Song --- .../gpu/drm/amd/dkms/m4/drm-gem-object-ref.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_gem.h | 8 ++++++++ 3 files changed, 25 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-gem-object-ref.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-gem-object-ref.m4 index 36c0a786c849f..8f42e769f8845 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-gem-object-ref.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-gem-object-ref.m4 @@ -24,3 +24,19 @@ AC_DEFUN([AC_AMDGPU_DRM_GEM_OBJECT_PUT], [ ]) ]) ]) + +dnl # +dnl # v6.8-rc3-286-gb31f5eba32ae drm: add drm_gem_object_is_shared_for_memory_stats() helper +dnl # +AC_DEFUN([AC_AMDGPU_DRM_GEM_OBJECT_IS_SHARED_FOR_MEMORY_STATS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_gem_object_is_shared_for_memory_stats(NULL); + ], [ + AC_DEFINE(HAVE_DRM_GEM_OBJECT_IS_SHARED_FOR_MEMORY_STATS, 1, + [drm_gem_object_is_shared_for_memory_stats() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 76406fca34fe7..692457c5a93c1 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -230,6 +230,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_WORKQUEUE AC_AMDGPU_DRM_EXEC_INIT AC_AMDGPU_DRM_DBG_PRINTER + AC_AMDGPU_DRM_GEM_OBJECT_IS_SHARED_FOR_MEMORY_STATS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_gem.h b/include/kcl/kcl_drm_gem.h index cded9b424aa89..73518a8a22f8b 100644 --- a/include/kcl/kcl_drm_gem.h +++ b/include/kcl/kcl_drm_gem.h @@ -57,4 +57,12 @@ drm_gem_object_get(struct drm_gem_object *obj) } #endif /* HAVE_DRM_GEM_OBJECT_PUT */ +/* copy from include/drm/drm_gem.h */ +#ifndef HAVE_DRM_GEM_OBJECT_IS_SHARED_FOR_MEMORY_STATS +static inline bool drm_gem_object_is_shared_for_memory_stats(struct drm_gem_object *obj) +{ + return (obj->handle_count > 1) || obj->dma_buf; +} +#endif /* HAVE_DRM_GEM_OBJECT_IS_SHARED_FOR_MEMORY_STATS */ + #endif From c0f1d4a2d32105125c2d7a9282bba9881c1afa74 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 22 Mar 2024 18:11:20 +0800 Subject: [PATCH 1195/1868] drm/amdkcl: check enum drm_debug_category whether exits It's caused by v6.8-rc3-249-ge154c4fc7bf2 drm: remove drm_debug_printer in favor of drm_dbg_printer Signed-off-by: Asher Song --- .../gpu/drm/amd/dkms/m4/drm_debug_enabled.m4 | 19 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_print.h | 6 ++++++ 3 files changed, 26 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_debug_enabled.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_debug_enabled.m4 index 38c1584359f8b..88be95171ea7b 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm_debug_enabled.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm_debug_enabled.m4 @@ -33,3 +33,22 @@ AC_DEFUN([AC_AMDGPU_DRM_DBG_PRINTER], [ ]) ]) ]) + +dnl # +dnl # commit v5.4-rc4-974-g876905b8fe59 +dnl # drm/print: convert debug category macros into an enum +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DEBUG_CATEGORY], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + enum drm_debug_category category; + category = DRM_UT_CORE; + ],[ + AC_DEFINE(HAVE_DRM_DEBUG_CATEGORY, + 1, + [enum drm_debug_category is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 692457c5a93c1..4c3141f28cc1a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -231,6 +231,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_EXEC_INIT AC_AMDGPU_DRM_DBG_PRINTER AC_AMDGPU_DRM_GEM_OBJECT_IS_SHARED_FOR_MEMORY_STATS + AC_AMDGPU_DRM_DEBUG_CATEGORY AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index 888592871d7ca..4c7dd20cd01f8 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -179,4 +179,10 @@ void drm_print_bits(struct drm_printer *p, unsigned long value, const char * const bits[], unsigned int nbits); #endif +#ifndef HAVE_DRM_DEBUG_CATEGORY +enum drm_debug_category { + KCL_DRM_DEBUG_CATEGORY +}; +#endif + #endif From 55d6cf6ca262713186c2fcff5fa626d9512d7509 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 25 Mar 2024 15:38:11 +0800 Subject: [PATCH 1196/1868] drm/amdkcl: test drm_info whether exists Signed-off-by: Asher Song --- include/kcl/kcl_drm_print.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index 4c7dd20cd01f8..0546bd944b72c 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -185,4 +185,20 @@ enum drm_debug_category { }; #endif +#ifndef drm_info +/* + * struct drm_device based logging + * + * Prefer drm_device based logging over device or prink based logging. + */ + +/* Helper for struct drm_device based logging. */ +#define __drm_printk(drm, level, type, fmt, ...) \ + dev_##level##type((drm) ? (drm)->dev : NULL, "[drm] " fmt, ##__VA_ARGS__) + + +#define drm_info(drm, fmt, ...) \ + __drm_printk((drm), info,, fmt, ##__VA_ARGS__) +#endif + #endif From 76939534e9ef4057a72b2ac40a9ed8d5b7f25538 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 4 Mar 2024 10:29:57 +0800 Subject: [PATCH 1197/1868] drm/amdkcl: wrap code under macro HAVE_STRUCT_XARRAY It's caused by 0e70df0c1c78cfbaa632efc9e06ad1b62912026d "drm/amdgpu: change vm->task_info handling" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 66e8baaa12619..479391fc9a0ab 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -2335,9 +2335,15 @@ amdgpu_vm_get_vm_from_pasid(struct amdgpu_device *adev, u32 pasid) struct amdgpu_vm *vm; unsigned long flags; +#ifdef HAVE_STRUCT_XARRAY xa_lock_irqsave(&adev->vm_manager.pasids, flags); vm = xa_load(&adev->vm_manager.pasids, pasid); xa_unlock_irqrestore(&adev->vm_manager.pasids, flags); +#else + spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags); + vm = idr_find(&adev->vm_manager.pasid_idr, pasid); + spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags); +#endif return vm; } From f631b3742a3fac6a7a8c40f51bf876bdd7946b31 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 7 Mar 2024 10:07:44 +0800 Subject: [PATCH 1198/1868] drm/amdkcl: wrap code under macro HAVE_PCI_DEV_LTR_PATH It's caused by 93b9f1c838ae024313d9d96a910a864d1b87aa49 "drm/amdgpu: Add nbif v6_3_1 ip block support" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c b/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c index 39919e0892c14..f5b504979a331 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c +++ b/drivers/gpu/drm/amd/amdgpu/nbif_v6_3_1.c @@ -331,12 +331,14 @@ static void nbif_v6_3_1_program_ltr(struct amdgpu_device *adev) pcie_capability_read_word(adev->pdev, PCI_EXP_DEVCTL2, &devctl2); +#ifdef HAVE_PCI_DEV_LTR_PATH if (adev->pdev->ltr_path == (devctl2 & PCI_EXP_DEVCTL2_LTR_EN)) return; if (adev->pdev->ltr_path) pcie_capability_set_word(adev->pdev, PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_LTR_EN); else +#endif pcie_capability_clear_word(adev->pdev, PCI_EXP_DEVCTL2, PCI_EXP_DEVCTL2_LTR_EN); } #endif From d1e0c1ce822b83fb8cd96c25ddb28473dd69f3f6 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Mon, 1 Apr 2024 11:42:00 +0800 Subject: [PATCH 1199/1868] drm/amdkcl: update config.h Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/config/config.h | 89 +++--------------------- 1 file changed, 11 insertions(+), 78 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 77e80cd5ee5cc..233a1d736de14 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -76,9 +76,6 @@ /* whether CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL is defined */ #define HAVE_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT_SIGNAL 1 -/* whether CHUNK_ID_SYNOBJ_IN_OUT is defined */ -#define HAVE_CHUNK_ID_SYNOBJ_IN_OUT 1 - /* compat_ptr_ioctl() is available */ #define HAVE_COMPAT_PTR_IOCTL 1 @@ -200,9 +197,6 @@ /* drm_connector_for_each_possible_encoder() wants 2 arguments */ #define HAVE_DRM_CONNECTOR_FOR_EACH_POSSIBLE_ENCODER_2ARGS 1 -/* struct drm_connector_funcs has register members */ -#define HAVE_DRM_CONNECTOR_FUNCS_REGISTER 1 - /* atomic_best_encoder take 2nd arg type of state as struct drm_atomic_state */ #define HAVE_DRM_CONNECTOR_HELPER_FUNCS_ATOMIC_BEST_ENCODER_ARG_DRM_ATOMIC_STATE 1 @@ -249,6 +243,12 @@ drm_atomic_state arg */ #define HAVE_DRM_CRTC_HELPER_FUNCS_ATOMIC_ENABLE_ARG_DRM_ATOMIC_STATE 1 +/* drm_dbg_printer() is available */ +#define HAVE_DRM_DBG_PRINTER 1 + +/* enum drm_debug_category is available */ +#define HAVE_DRM_DEBUG_CATEGORY 1 + /* drm_debug_enabled() is available */ #define HAVE_DRM_DEBUG_ENABLED 1 @@ -398,9 +398,6 @@ /* struct drm_dp_mst_topology_mgr.base is available */ #define HAVE_DRM_DP_MST_TOPOLOGY_MGR_BASE 1 -/* drm_dp_mst_topology_mgr_init() wants drm_device arg */ -#define HAVE_DRM_DP_MST_TOPOLOGY_MGR_INIT_DRM_DEV 1 - /* drm_dp_mst_topology_mgr_init() has max_lane_count and max_link_rate */ /* #undef HAVE_DRM_DP_MST_TOPOLOGY_MGR_INIT_MAX_LANE_COUNT */ @@ -446,15 +443,6 @@ /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_APERTURE_H 1 -/* Define to 1 if you have the header file. */ -#define HAVE_DRM_DRM_ATOMIC_UAPI_H 1 - -/* Define to 1 if you have the header file. */ -#define HAVE_DRM_DRM_AUDIO_COMPONENT_H 1 - -/* Define to 1 if you have the header file. */ -#define HAVE_DRM_DRM_AUTH_H 1 - /* Define to 1 if you have the header file. */ /* #undef HAVE_DRM_DRM_BACKPORT_H */ @@ -473,9 +461,6 @@ /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_MANAGED_H 1 -/* Define to 1 if you have the header file. */ -#define HAVE_DRM_DRM_PLANE_H 1 - /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_PROBE_HELPER_H 1 @@ -507,7 +492,7 @@ #define HAVE_DRM_EDID_OVERRIDE_CONNECTOR_UPDATE 1 /* drm_exec() has 3 arguments */ -#define HAVE_DRM_EXEC_INIT_3_ARGUMENTS +#define HAVE_DRM_EXEC_INIT_3_ARGUMENTS 1 /* drm_fb_helper_fill_info() is available */ #define HAVE_DRM_FB_HELPER_FILL_INFO 1 @@ -518,12 +503,6 @@ /* drm_fb_helper_init() has 3 args */ /* #undef HAVE_DRM_FB_HELPER_INIT_3ARGS */ -/* whether drm_fb_helper_lastclose() is available */ -#define HAVE_DRM_FB_HELPER_LASTCLOSE 1 - -/* drm_fb_helper_unregister_info() is available */ -#define HAVE_DRM_FB_HELPER_UNREGISTER_INFO 1 - /* drm_firmware_drivers_only() is available */ #define HAVE_DRM_FIRMWARE_DRIVERS_ONLY 1 @@ -536,6 +515,9 @@ /* drm_gem_object_funcs.vmap hsa iosys_map arg */ #define HAVE_DRM_GEM_OBJECT_FUNCS_VMAP_HAS_IOSYS_MAP_ARG 1 +/* drm_gem_object_is_shared_for_memory_stats() is available */ +#define HAVE_DRM_GEM_OBJECT_IS_SHARED_FOR_MEMORY_STATS 1 + /* drm_gem_object_put() is available */ #define HAVE_DRM_GEM_OBJECT_PUT 1 @@ -572,9 +554,6 @@ /* drm_memcpy_from_wc() is availablea and has struct iosys_map* arg */ #define HAVE_DRM_MEMCPY_FROM_WC_IOSYS_MAP_ARG 1 -/* drm_modeset_backoff() has int return */ -/* #undef HAVE_DRM_MODESET_BACKOFF_RETURN_INT */ - /* drm_mode_config->dp_subconnector_property is available */ #define HAVE_DRM_MODE_CONFIG_DP_SUBCONNECTOR_PROPERTY 1 @@ -597,20 +576,7 @@ #define HAVE_DRM_NEED_SWIOTLB 1 /* drm_plane_helper_destroy() is available */ -/* #undef HAVE_DRM_PLANE_HELPER_DESTROY */ - -/* drm_plane_mask is available */ -#define HAVE_DRM_PLANE_MASK 1 - -/* drm_plane_create_alpha_property, drm_plane_create_blend_mode_property are - available */ -#define HAVE_DRM_PLANE_PROPERTY_ALPHA_BLEND_MODE 1 - -/* drm_plane_create_color_properties is available */ -#define HAVE_DRM_PLANE_PROPERTY_COLOR_ENCODING_RANGE 1 - -/* drm_plane_create_rotation_property is available */ -#define HAVE_DRM_PLANE_PROPERTY_ROTATION 1 +#define HAVE_DRM_PLANE_HELPER_DESTROY 1 /* drm_prime_pages_to_sg() wants 3 arguments */ #define HAVE_DRM_PRIME_PAGES_TO_SG_3ARGS 1 @@ -636,9 +602,6 @@ /* Define to 1 if you have the header file. */ #define HAVE_DRM_TASK_BARRIER_H 1 -/* drm_vblank->time uses ktime_t type */ -#define HAVE_DRM_VBLANK_USE_KTIME_T 1 - /* struct drm_vma_offset_node has readonly field */ /* #undef HAVE_DRM_VMA_OFFSET_NODE_READONLY_FIELD */ @@ -822,12 +785,6 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_MMAP_LOCK_H 1 -/* Define to 1 if you have the header file. */ -#define HAVE_LINUX_NOSPEC_H 1 - -/* Define to 1 if you have the header file. */ -#define HAVE_LINUX_OVERFLOW_H 1 - /* Define to 1 if you have the header file. */ #define HAVE_LINUX_PCI_P2PDMA_H 1 @@ -837,9 +794,6 @@ /* Define to 1 if you have the header file. */ #define HAVE_LINUX_PROCESSOR_H 1 -/* Define to 1 if you have the header file. */ -#define HAVE_LINUX_RBTREE_TYPES_H 1 - /* Define to 1 if you have the header file. */ #define HAVE_LINUX_STDARG_H 1 @@ -894,9 +848,6 @@ /* mmu_notifier_synchronize() is available */ #define HAVE_MMU_NOTIFIER_SYNCHRONIZE 1 -/* mm_access() is available */ -/* #undef HAVE_MM_ACCESS */ - /* release_pages() wants 2 args */ #define HAVE_MM_RELEASE_PAGES_2ARGS 1 @@ -954,9 +905,6 @@ /* rb_add_cached is available */ #define HAVE_RB_ADD_CACHED 1 -/* struct rb_root_cached is available */ -#define HAVE_RB_ROOT_CACHED 1 - /* whether register_shrinker(x, x) is available */ /* #undef HAVE_REGISTER_SHRINKER_WITH_TWO_ARGUMENTS */ @@ -1021,12 +969,6 @@ arg */ #define HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS 1 -/* drm_plane_helper_funcs->prepare_fb() wants const p arg */ -/* #undef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_PREPARE_FB_CONST */ - -/* drm_plane_helper_funcs->prepare_fb() wants p,p arg */ -#define HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_PREPARE_FB_PP 1 - /* ide->idr_base is available */ #define HAVE_STRUCT_IDE_IDR_BASE 1 @@ -1063,9 +1005,6 @@ /* vga_remove_vgacon() is available */ #define HAVE_VGA_REMOVE_VGACON 1 -/* vga_switcheroo_set_dynamic_switch() exist */ -/* #undef HAVE_VGA_SWITCHEROO_SET_DYNAMIC_SWITCH */ - /* vma_is_initial_{heap, stack} is available */ #define HAVE_VMA_IS_INITIAL_HEAP 1 @@ -1078,12 +1017,6 @@ /* vmf_insert_mixed_prot() is available */ /* #undef HAVE_VMF_INSERT_MIXED_PROT */ -/* vmf_insert_pfn_{pmd,pud}() wants 3 args */ -/* #undef HAVE_VMF_INSERT_PFN_PMD_3ARGS */ - -/* vmf_insert_pfn_{pmd,pud}_prot() is available */ -#define HAVE_VMF_INSERT_PFN_PMD_PROT 1 - /* vmf_insert_pfn_prot() is available */ #define HAVE_VMF_INSERT_PFN_PROT 1 From 8173a2d037e350fb9002e9118e4c39da949f4923 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 18 Mar 2024 15:19:12 +0800 Subject: [PATCH 1200/1868] drm/amdkcl: Fix mst hotplug issue It's caused by bd4e5321fb2237d50a1dcce5602fb3da40a4c506 "drm/amdkcl: wrap code under macro HAVE_DRM_DP_MST_TOPOLOGY_STATE_PAYLOADS" 02e1db74d7ba5b2607421fedce5fc002d4299459 "drm/amd/display: adjust flow for deallocation mst payload" For some old kernel, the asdn code need be keep. So wrap these code under HAVE_DRM_DP_REMOVE_RAYLOAD_PART to fix it. Signed-off-by: Wayne Lin Signed-off-by: Bob Zhou Reviewed-by: Jun Ma --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 19 +++++ drivers/gpu/drm/amd/display/dc/dc.h | 3 + .../gpu/drm/amd/display/dc/link/link_dpms.c | 83 +++++++++++++++++++ 3 files changed, 105 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index d99d1250ef991..b40cf47ae6914 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1936,6 +1936,25 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) /* TODO: Remove after DP2 receiver gets proper support of Cable ID feature */ adev->dm.dc->debug.ignore_cable_id = true; +#ifndef HAVE_DRM_DP_REMOVE_RAYLOAD_PART + /* TODO: There is a new drm mst change where the freedom of + * vc_next_start_slot update is revoked/moved into drm, instead of in + * driver. This forces us to make sure to get vc_next_start_slot updated + * in drm function each time without considering if mst_state is active + * or not. Otherwise, next time hotplug will give wrong start_slot + * number. We are implementing a temporary solution to even notify drm + * mst deallocation when link is no longer of MST type when uncommitting + * the stream so we will have more time to work on a proper solution. + * Ideally when dm_helpers_dp_mst_stop_top_mgr message is triggered, we + * should notify drm to do a complete "reset" of its states and stop + * calling further drm mst functions when link is no longer of an MST + * type. This could happen when we unplug an MST hubs/displays. When + * uncommit stream comes later after unplug, we should just reset + * hardware states only. + */ + adev->dm.dc->debug.temp_mst_deallocation_sequence = true; +#endif //HAVE_DRM_DP_REMOVE_RAYLOAD_PART + if (adev->dm.dc->caps.dp_hdmi21_pcon_support) DRM_INFO("DP-HDMI FRL PCON supported\n"); diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 6b036417a73ae..d556e55517829 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -1010,6 +1010,9 @@ struct dc_debug_options { unsigned int min_prefetch_in_strobe_ns; bool disable_unbounded_requesting; bool dig_fifo_off_in_blank; + #ifndef HAVE_DRM_DP_REMOVE_RAYLOAD_PART + bool temp_mst_deallocation_sequence; + #endif bool override_dispclk_programming; bool otg_crc_db; bool disallow_dispclk_dppclk_ds; diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c index 6ea0d9894741d..c53c9338c922d 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c @@ -1302,6 +1302,85 @@ static void remove_stream_from_alloc_table( } } +#ifndef HAVE_DRM_DP_REMOVE_RAYLOAD_PART +static enum dc_status deallocate_mst_payload_with_temp_drm_wa( + struct pipe_ctx *pipe_ctx) +{ + struct dc_stream_state *stream = pipe_ctx->stream; + struct dc_link *link = stream->link; + struct dc_dp_mst_stream_allocation_table proposed_table = {0}; + struct fixed31_32 avg_time_slots_per_mtp = dc_fixpt_from_int(0); + int i; + bool mst_mode = (link->type == dc_connection_mst_branch); + /* adjust for drm changes*/ + const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); + const struct dc_link_settings empty_link_settings = {0}; + DC_LOGGER_INIT(link->ctx->logger); + + if (link_hwss->ext.set_throttled_vcp_size) + link_hwss->ext.set_throttled_vcp_size(pipe_ctx, avg_time_slots_per_mtp); + if (link_hwss->ext.set_hblank_min_symbol_width) + link_hwss->ext.set_hblank_min_symbol_width(pipe_ctx, + &empty_link_settings, + avg_time_slots_per_mtp); + + if (dm_helpers_dp_mst_write_payload_allocation_table( + stream->ctx, + stream, + &proposed_table, + false)) + update_mst_stream_alloc_table( + link, + pipe_ctx->stream_res.stream_enc, + pipe_ctx->stream_res.hpo_dp_stream_enc, + &proposed_table); + else + DC_LOG_WARNING("Failed to update" + "MST allocation table for" + "pipe idx:%d\n", + pipe_ctx->pipe_idx); + + DC_LOG_MST("%s" + "stream_count: %d: ", + __func__, + link->mst_stream_alloc_table.stream_count); + + for (i = 0; i < MAX_CONTROLLER_NUM; i++) { + DC_LOG_MST("stream_enc[%d]: %p " + "stream[%d].hpo_dp_stream_enc: %p " + "stream[%d].vcp_id: %d " + "stream[%d].slot_count: %d\n", + i, + (void *) link->mst_stream_alloc_table.stream_allocations[i].stream_enc, + i, + (void *) link->mst_stream_alloc_table.stream_allocations[i].hpo_dp_stream_enc, + i, + link->mst_stream_alloc_table.stream_allocations[i].vcp_id, + i, + link->mst_stream_alloc_table.stream_allocations[i].slot_count); + } + + if (link_hwss->ext.update_stream_allocation_table == NULL || + link_dp_get_encoding_format(&link->cur_link_settings) == DP_UNKNOWN_ENCODING) { + DC_LOG_DEBUG("Unknown encoding format\n"); + return DC_ERROR_UNEXPECTED; + } + + link_hwss->ext.update_stream_allocation_table(link, &pipe_ctx->link_res, + &link->mst_stream_alloc_table); + + if (mst_mode) { + dm_helpers_dp_mst_poll_for_allocation_change_trigger( + stream->ctx, + stream); + } + + dm_helpers_dp_mst_update_mst_mgr_for_deallocation(stream->ctx, stream); + + return DC_OK; +} +#endif + static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) { struct dc_stream_state *stream = pipe_ctx->stream; @@ -1314,6 +1393,10 @@ static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx) const struct dc_link_settings empty_link_settings = {0}; DC_LOGGER_INIT(link->ctx->logger); +#ifndef HAVE_DRM_DP_REMOVE_RAYLOAD_PART + if (link->dc->debug.temp_mst_deallocation_sequence) + return deallocate_mst_payload_with_temp_drm_wa(pipe_ctx); +#endif /* deallocate_mst_payload is called before disable link. When mode or * disable/enable monitor, new stream is created which is not in link * stream[] yet. For this, payload is not allocated yet, so de-alloc From 354a3cbac8c62a5dc5c95af7d5cf68935db54684 Mon Sep 17 00:00:00 2001 From: Lancelot SIX Date: Tue, 12 Mar 2024 11:46:34 +0000 Subject: [PATCH 1201/1868] drm/amdkfd: handle masking host traps in cwsr_trap_handler This patch ensures that the 1st level trap handler for gfx9 (cwsr_trap_handler_gfx9.asm) can correctly handle the case where a non-driver-maskable exception and a host trap (driver maskable) are received simultaneously. It also fixes an issue with the current trap handler which uses ttmp4 temporally, overwriting information needed by the debugger. Tested on gfx90a and gfx942. Co-developed-by: Joseph Greathouse Signed-off-by: Lancelot SIX Signed-off-by: Joseph Greathouse Tested-by: Vladimir Indic Reviewed-by: Laurent Morichetti --- .../gpu/drm/amd/amdkfd/cwsr_trap_handler.h | 906 +++++++++--------- .../drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm | 100 +- 2 files changed, 529 insertions(+), 477 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h index 8086764080878..af92680597b22 100644 --- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h +++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler.h @@ -274,47 +274,49 @@ static const uint32_t cwsr_trap_gfx8_hex[] = { static const uint32_t cwsr_trap_gfx9_hex[] = { - 0xbf820001, 0xbf820263, + 0xbf820001, 0xbf820267, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, 0x866eff78, 0x00002000, - 0xbf840009, 0x866eff6d, - 0x00ff0000, 0xbf850023, - 0x866eff7b, 0x00000400, - 0xbf850060, 0xbf8e0010, - 0xb8fbf803, 0xbf82fffa, - 0x866eff7b, 0x03c00900, - 0xbf85001a, 0x866eff6d, - 0x01ff0000, 0xbf06ff6e, - 0x01040000, 0xbf850015, + 0xbf840008, 0xbf0d986d, + 0xbf850023, 0x866eff7b, + 0x00000400, 0xbf850065, + 0xbf8e0010, 0xb8fbf803, + 0xbf82fffa, 0x866eff7b, + 0x03800900, 0xbf850019, 0x866eff7b, 0x000071ff, 0xbf840008, 0x866fff7b, 0x00007080, 0xbf840001, 0xbeee1a87, 0xb8eff801, 0x8e6e8c6e, 0x866e6f6e, - 0xbf85000a, 0x866eff6d, - 0x00ff0000, 0xbf850007, + 0xbf85000e, 0xbf0d986d, + 0xbf850003, 0x866eff6d, + 0x00ff0000, 0xbf850009, 0xb8eef801, 0x866eff6e, - 0x00000800, 0xbf850003, + 0x00000800, 0xbf850005, + 0xbf0d986d, 0xbf850004, 0x866eff7b, 0x00000400, - 0xbf850040, 0xb8faf807, - 0x867aff7a, 0x001f8000, - 0x8e7a8b7a, 0x8977ff77, - 0xfc000000, 0x87777a77, - 0xba7ff807, 0x00000000, - 0xb8faf812, 0xb8fbf813, - 0x8efa887a, 0xbf0d8f7b, - 0xbf840002, 0x877bff7b, - 0xffff0000, 0xc0031c3d, - 0x00000010, 0xc0071bbd, - 0x00000000, 0xc0071ebd, - 0x00000008, 0xbf8cc07f, - 0x8671ff6d, 0x01000000, - 0xbf840004, 0x92f1ff70, - 0x00010001, 0xbf840016, - 0xbf820005, 0x86708170, - 0x8e709770, 0x8977ff77, - 0x00800000, 0x87777077, + 0xbf850046, 0xbeed1a9d, + 0xb8faf807, 0x867aff7a, + 0x001f8000, 0x8e7a8b7a, + 0x8977ff77, 0xfc000000, + 0x87777a77, 0xba7ff807, + 0x00000000, 0xb8faf812, + 0xb8fbf813, 0x8efa887a, + 0xbf0d8f7b, 0xbf840002, + 0x877bff7b, 0xffff0000, + 0xc0031e7d, 0x00000010, + 0xc0071bbd, 0x00000000, + 0xc0071ebd, 0x00000008, + 0xbf8cc07f, 0x8e799779, + 0x8977ff77, 0x01800000, + 0x87777977, 0xbf0d986d, + 0xbf840009, 0xbf0d9877, + 0xbf850007, 0x896dff6d, + 0x01ff0000, 0xba7f0583, + 0x00000000, 0xbf0d9d6d, + 0xbeed189d, 0xbf840012, + 0xbef71898, 0xbeed189d, 0x86ee6e6e, 0xbf840001, 0xbe801d6e, 0x866eff6d, 0x01ff0000, 0xbf850005, @@ -680,7 +682,7 @@ static const uint32_t cwsr_trap_gfx9_hex[] = { 0x8f6e837a, 0xb96ee0c2, 0xbf800002, 0xb97a0002, 0xbf8a0000, 0xbe801f6c, - 0xbf810000, 0x00000000, + 0xbf9b0000, 0x00000000, }; static const uint32_t cwsr_trap_nv1x_hex[] = { @@ -1308,47 +1310,49 @@ static const uint32_t cwsr_trap_nv1x_hex[] = { }; static const uint32_t cwsr_trap_arcturus_hex[] = { - 0xbf820001, 0xbf8202df, + 0xbf820001, 0xbf8202e3, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, 0x866eff78, 0x00002000, - 0xbf840009, 0x866eff6d, - 0x00ff0000, 0xbf850023, - 0x866eff7b, 0x00000400, - 0xbf850060, 0xbf8e0010, - 0xb8fbf803, 0xbf82fffa, - 0x866eff7b, 0x03c00900, - 0xbf85001a, 0x866eff6d, - 0x01ff0000, 0xbf06ff6e, - 0x01040000, 0xbf850015, + 0xbf840008, 0xbf0d986d, + 0xbf850023, 0x866eff7b, + 0x00000400, 0xbf850065, + 0xbf8e0010, 0xb8fbf803, + 0xbf82fffa, 0x866eff7b, + 0x03800900, 0xbf850019, 0x866eff7b, 0x000071ff, 0xbf840008, 0x866fff7b, 0x00007080, 0xbf840001, 0xbeee1a87, 0xb8eff801, 0x8e6e8c6e, 0x866e6f6e, - 0xbf85000a, 0x866eff6d, - 0x00ff0000, 0xbf850007, + 0xbf85000e, 0xbf0d986d, + 0xbf850003, 0x866eff6d, + 0x00ff0000, 0xbf850009, 0xb8eef801, 0x866eff6e, - 0x00000800, 0xbf850003, + 0x00000800, 0xbf850005, + 0xbf0d986d, 0xbf850004, 0x866eff7b, 0x00000400, - 0xbf850040, 0xb8faf807, - 0x867aff7a, 0x001f8000, - 0x8e7a8b7a, 0x8977ff77, - 0xfc000000, 0x87777a77, - 0xba7ff807, 0x00000000, - 0xb8faf812, 0xb8fbf813, - 0x8efa887a, 0xbf0d8f7b, - 0xbf840002, 0x877bff7b, - 0xffff0000, 0xc0031c3d, - 0x00000010, 0xc0071bbd, - 0x00000000, 0xc0071ebd, - 0x00000008, 0xbf8cc07f, - 0x8671ff6d, 0x01000000, - 0xbf840004, 0x92f1ff70, - 0x00010001, 0xbf840016, - 0xbf820005, 0x86708170, - 0x8e709770, 0x8977ff77, - 0x00800000, 0x87777077, + 0xbf850046, 0xbeed1a9d, + 0xb8faf807, 0x867aff7a, + 0x001f8000, 0x8e7a8b7a, + 0x8977ff77, 0xfc000000, + 0x87777a77, 0xba7ff807, + 0x00000000, 0xb8faf812, + 0xb8fbf813, 0x8efa887a, + 0xbf0d8f7b, 0xbf840002, + 0x877bff7b, 0xffff0000, + 0xc0031e7d, 0x00000010, + 0xc0071bbd, 0x00000000, + 0xc0071ebd, 0x00000008, + 0xbf8cc07f, 0x8e799779, + 0x8977ff77, 0x01800000, + 0x87777977, 0xbf0d986d, + 0xbf840009, 0xbf0d9877, + 0xbf850007, 0x896dff6d, + 0x01ff0000, 0xba7f0583, + 0x00000000, 0xbf0d9d6d, + 0xbeed189d, 0xbf840012, + 0xbef71898, 0xbeed189d, 0x86ee6e6e, 0xbf840001, 0xbe801d6e, 0x866eff6d, 0x01ff0000, 0xbf850005, @@ -1790,51 +1794,53 @@ static const uint32_t cwsr_trap_arcturus_hex[] = { 0x8f6e837a, 0xb96ee0c2, 0xbf800002, 0xb97a0002, 0xbf8a0000, 0xbe801f6c, - 0xbf810000, 0x00000000, + 0xbf9b0000, 0x00000000, }; static const uint32_t cwsr_trap_aldebaran_hex[] = { - 0xbf820001, 0xbf8202ea, + 0xbf820001, 0xbf8202ee, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, 0x866eff78, 0x00002000, - 0xbf840009, 0x866eff6d, - 0x00ff0000, 0xbf850023, - 0x866eff7b, 0x00000400, - 0xbf850060, 0xbf8e0010, - 0xb8fbf803, 0xbf82fffa, - 0x866eff7b, 0x03c00900, - 0xbf85001a, 0x866eff6d, - 0x01ff0000, 0xbf06ff6e, - 0x01040000, 0xbf850015, + 0xbf840008, 0xbf0d986d, + 0xbf850023, 0x866eff7b, + 0x00000400, 0xbf850065, + 0xbf8e0010, 0xb8fbf803, + 0xbf82fffa, 0x866eff7b, + 0x03800900, 0xbf850019, 0x866eff7b, 0x000071ff, 0xbf840008, 0x866fff7b, 0x00007080, 0xbf840001, 0xbeee1a87, 0xb8eff801, 0x8e6e8c6e, 0x866e6f6e, - 0xbf85000a, 0x866eff6d, - 0x00ff0000, 0xbf850007, + 0xbf85000e, 0xbf0d986d, + 0xbf850003, 0x866eff6d, + 0x00ff0000, 0xbf850009, 0xb8eef801, 0x866eff6e, - 0x00000800, 0xbf850003, + 0x00000800, 0xbf850005, + 0xbf0d986d, 0xbf850004, 0x866eff7b, 0x00000400, - 0xbf850040, 0xb8faf807, - 0x867aff7a, 0x001f8000, - 0x8e7a8b7a, 0x8977ff77, - 0xfc000000, 0x87777a77, - 0xba7ff807, 0x00000000, - 0xb8faf812, 0xb8fbf813, - 0x8efa887a, 0xbf0d8f7b, - 0xbf840002, 0x877bff7b, - 0xffff0000, 0xc0031c3d, - 0x00000010, 0xc0071bbd, - 0x00000000, 0xc0071ebd, - 0x00000008, 0xbf8cc07f, - 0x8671ff6d, 0x01000000, - 0xbf840004, 0x92f1ff70, - 0x00010001, 0xbf840016, - 0xbf820005, 0x86708170, - 0x8e709770, 0x8977ff77, - 0x00800000, 0x87777077, + 0xbf850046, 0xbeed1a9d, + 0xb8faf807, 0x867aff7a, + 0x001f8000, 0x8e7a8b7a, + 0x8977ff77, 0xfc000000, + 0x87777a77, 0xba7ff807, + 0x00000000, 0xb8faf812, + 0xb8fbf813, 0x8efa887a, + 0xbf0d8f7b, 0xbf840002, + 0x877bff7b, 0xffff0000, + 0xc0031e7d, 0x00000010, + 0xc0071bbd, 0x00000000, + 0xc0071ebd, 0x00000008, + 0xbf8cc07f, 0x8e799779, + 0x8977ff77, 0x01800000, + 0x87777977, 0xbf0d986d, + 0xbf840009, 0xbf0d9877, + 0xbf850007, 0x896dff6d, + 0x01ff0000, 0xba7f0583, + 0x00000000, 0xbf0d9d6d, + 0xbeed189d, 0xbf840012, + 0xbef71898, 0xbeed189d, 0x86ee6e6e, 0xbf840001, 0xbe801d6e, 0x866eff6d, 0x01ff0000, 0xbf850005, @@ -2287,7 +2293,7 @@ static const uint32_t cwsr_trap_aldebaran_hex[] = { 0x8f6e837a, 0xb96ee0c2, 0xbf800002, 0xb97a0002, 0xbf8a0000, 0xbe801f6c, - 0xbf810000, 0x00000000, + 0xbf9b0000, 0x00000000, }; static const uint32_t cwsr_trap_gfx10_hex[] = { @@ -3169,25 +3175,27 @@ static const uint32_t cwsr_trap_gfx11_hex[] = { }; static const uint32_t cwsr_trap_gfx9_4_3_hex[] = { - 0xbf820001, 0xbf8202db, + 0xbf820001, 0xbf8202ea, 0xb8f8f802, 0x8978ff78, 0x00020006, 0xb8fbf803, 0x866eff78, 0x00002000, - 0xbf840009, 0x866eff6d, - 0x00ff0000, 0xbf85001a, + 0xbf840008, 0xbf0d986d, + 0xbf85001f, 0x866eff7b, + 0x00000400, 0xbf850061, + 0xbf8e0010, 0xb8fbf803, + 0xbf82fffa, 0x866eff7b, + 0x03800900, 0xbf850015, + 0x866eff7b, 0x000071ff, + 0xbf840008, 0x866fff7b, + 0x00007080, 0xbf840001, + 0xbeee1a87, 0xb8eff801, + 0x8e6e8c6e, 0x866e6f6e, + 0xbf85000a, 0xbf0d986d, + 0xbf850003, 0x866eff6d, + 0x00ff0000, 0xbf850005, + 0xbf0d986d, 0xbf850004, 0x866eff7b, 0x00000400, - 0xbf850051, 0xbf8e0010, - 0xb8fbf803, 0xbf82fffa, - 0x866eff7b, 0x03c00900, - 0xbf850011, 0x866eff7b, - 0x000071ff, 0xbf840008, - 0x866fff7b, 0x00007080, - 0xbf840001, 0xbeee1a87, - 0xb8eff801, 0x8e6e8c6e, - 0x866e6f6e, 0xbf850006, - 0x866eff6d, 0x00ff0000, - 0xbf850003, 0x866eff7b, - 0x00000400, 0xbf85003a, + 0xbf850046, 0xbeed1a9d, 0xb8faf807, 0x867aff7a, 0x001f8000, 0x8e7a8b7a, 0x8979ff79, 0xfc000000, @@ -3196,187 +3204,130 @@ static const uint32_t cwsr_trap_gfx9_4_3_hex[] = { 0xb8fbf813, 0x8efa887a, 0xbf0d8f7b, 0xbf840002, 0x877bff7b, 0xffff0000, - 0xc0031bbd, 0x00000010, - 0xbf8cc07f, 0x8e6e976e, - 0x8979ff79, 0x00800000, - 0x87796e79, 0xc0071bbd, - 0x00000000, 0xbf8cc07f, + 0xc0031cfd, 0x00000010, + 0xc0071bbd, 0x00000000, 0xc0071ebd, 0x00000008, - 0xbf8cc07f, 0x86ee6e6e, - 0xbf840001, 0xbe801d6e, - 0x866eff6d, 0x01ff0000, - 0xbf850005, 0x8778ff78, - 0x00002000, 0x80ec886c, - 0x82ed806d, 0xbf820005, - 0x866eff6d, 0x01000000, - 0xbf850002, 0x806c846c, - 0x826d806d, 0x866dff6d, - 0x0000ffff, 0x8f7a8b79, - 0x867aff7a, 0x001f8000, - 0xb97af807, 0x86fe7e7e, - 0x86ea6a6a, 0x8f6e8378, - 0xb96ee0c2, 0xbf800002, - 0xb9780002, 0xbe801f6c, + 0xbf8cc07f, 0x8e739773, + 0x8979ff79, 0x01800000, + 0x87797379, 0xbf0d986d, + 0xbf840009, 0xbf0d9879, + 0xbf850007, 0x896dff6d, + 0x01ff0000, 0xba7f0583, + 0x00000000, 0xbf0d9d6d, + 0xbeed189d, 0xbf840012, + 0xbef91898, 0xbeed189d, + 0x86ee6e6e, 0xbf840001, + 0xbe801d6e, 0x866eff6d, + 0x01ff0000, 0xbf850005, + 0x8778ff78, 0x00002000, + 0x80ec886c, 0x82ed806d, + 0xbf820005, 0x866eff6d, + 0x01000000, 0xbf850002, + 0x806c846c, 0x826d806d, 0x866dff6d, 0x0000ffff, - 0xbefa0080, 0xb97a0283, - 0xb8faf807, 0x867aff7a, - 0x001f8000, 0x8e7a8b7a, - 0x8979ff79, 0xfc000000, - 0x87797a79, 0xba7ff807, - 0x00000000, 0xbeee007e, - 0xbeef007f, 0xbefe0180, - 0xbf900004, 0x877a8478, - 0xb97af802, 0xbf8e0002, - 0xbf88fffe, 0xb8fa2985, - 0x807a817a, 0x8e7a8a7a, - 0x8e7a817a, 0xb8fb1605, - 0x807b817b, 0x8e7b867b, - 0x807a7b7a, 0x807a7e7a, - 0x827b807f, 0x867bff7b, - 0x0000ffff, 0xc04b1c3d, - 0x00000050, 0xbf8cc07f, - 0xc04b1d3d, 0x00000060, - 0xbf8cc07f, 0xc0431e7d, - 0x00000074, 0xbf8cc07f, - 0xbef4007e, 0x8675ff7f, - 0x0000ffff, 0x8775ff75, - 0x00040000, 0xbef60080, - 0xbef700ff, 0x00807fac, - 0xbef1007c, 0xbef00080, - 0xb8f02985, 0x80708170, - 0x8e708a70, 0x8e708170, - 0xb8fa1605, 0x807a817a, - 0x8e7a867a, 0x80707a70, - 0xbef60084, 0xbef600ff, - 0x01000000, 0xbefe007c, - 0xbefc0070, 0xc0611c7a, - 0x0000007c, 0xbf8cc07f, - 0x80708470, 0xbefc007e, + 0x8f7a8b79, 0x867aff7a, + 0x001f8000, 0xb97af807, + 0x86fe7e7e, 0x86ea6a6a, + 0x8f6e8378, 0xb96ee0c2, + 0xbf800002, 0xb9780002, + 0xbe801f6c, 0x866dff6d, + 0x0000ffff, 0xbefa0080, + 0xb97a0283, 0xb8faf807, + 0x867aff7a, 0x001f8000, + 0x8e7a8b7a, 0x8979ff79, + 0xfc000000, 0x87797a79, + 0xba7ff807, 0x00000000, + 0xbeee007e, 0xbeef007f, + 0xbefe0180, 0xbf900004, + 0x877a8478, 0xb97af802, + 0xbf8e0002, 0xbf88fffe, + 0xb8fa2985, 0x807a817a, + 0x8e7a8a7a, 0x8e7a817a, + 0xb8fb1605, 0x807b817b, + 0x8e7b867b, 0x807a7b7a, + 0x807a7e7a, 0x827b807f, + 0x867bff7b, 0x0000ffff, + 0xc04b1c3d, 0x00000050, + 0xbf8cc07f, 0xc04b1d3d, + 0x00000060, 0xbf8cc07f, + 0xc0431e7d, 0x00000074, + 0xbf8cc07f, 0xbef4007e, + 0x8675ff7f, 0x0000ffff, + 0x8775ff75, 0x00040000, + 0xbef60080, 0xbef700ff, + 0x00807fac, 0xbef1007c, + 0xbef00080, 0xb8f02985, + 0x80708170, 0x8e708a70, + 0x8e708170, 0xb8fa1605, + 0x807a817a, 0x8e7a867a, + 0x80707a70, 0xbef60084, + 0xbef600ff, 0x01000000, 0xbefe007c, 0xbefc0070, - 0xc0611b3a, 0x0000007c, + 0xc0611c7a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611b7a, + 0xbefc0070, 0xc0611b3a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, 0xbefc0070, - 0xc0611bba, 0x0000007c, + 0xc0611b7a, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611bfa, + 0xbefc0070, 0xc0611bba, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, 0xbefc0070, - 0xc0611e3a, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xb8fbf803, - 0xbefe007c, 0xbefc0070, - 0xc0611efa, 0x0000007c, + 0xc0611bfa, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, - 0xbefc0070, 0xc0611a3a, + 0xbefc0070, 0xc0611e3a, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0xb8fbf803, 0xbefe007c, + 0xbefc0070, 0xc0611efa, 0x0000007c, 0xbf8cc07f, 0x80708470, 0xbefc007e, 0xbefe007c, 0xbefc0070, - 0xc0611a7a, 0x0000007c, - 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0xb8f1f801, - 0xbefe007c, 0xbefc0070, - 0xc0611c7a, 0x0000007c, + 0xc0611a3a, 0x0000007c, 0xbf8cc07f, 0x80708470, - 0xbefc007e, 0x867aff7f, - 0x04000000, 0xbeef0080, - 0x876f6f7a, 0xb8f02985, - 0x80708170, 0x8e708a70, - 0x8e708170, 0xb8fb1605, - 0x807b817b, 0x8e7b847b, - 0x8e76827b, 0xbef600ff, - 0x01000000, 0xbef20174, - 0x80747074, 0x82758075, - 0xbefc0080, 0xbf800000, - 0xbe802b00, 0xbe822b02, - 0xbe842b04, 0xbe862b06, - 0xbe882b08, 0xbe8a2b0a, - 0xbe8c2b0c, 0xbe8e2b0e, - 0xc06b003a, 0x00000000, - 0xbf8cc07f, 0xc06b013a, - 0x00000010, 0xbf8cc07f, - 0xc06b023a, 0x00000020, - 0xbf8cc07f, 0xc06b033a, - 0x00000030, 0xbf8cc07f, - 0x8074c074, 0x82758075, - 0x807c907c, 0xbf0a7b7c, - 0xbf85ffe7, 0xbef40172, - 0xbef00080, 0xbefe00c1, - 0xbeff00c1, 0xbee80080, - 0xbee90080, 0xbef600ff, - 0x01000000, 0x867aff78, - 0x00400000, 0xbf850003, - 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf85004d, - 0xbe840080, 0xd2890000, - 0x00000900, 0x80048104, - 0xd2890001, 0x00000900, - 0x80048104, 0xd2890002, - 0x00000900, 0x80048104, - 0xd2890003, 0x00000900, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000901, - 0x80048104, 0xd2890001, - 0x00000901, 0x80048104, - 0xd2890002, 0x00000901, - 0x80048104, 0xd2890003, - 0x00000901, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0xbe840080, 0xd2890000, - 0x00000902, 0x80048104, - 0xd2890001, 0x00000902, - 0x80048104, 0xd2890002, - 0x00000902, 0x80048104, - 0xd2890003, 0x00000902, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000903, - 0x80048104, 0xd2890001, - 0x00000903, 0x80048104, - 0xd2890002, 0x00000903, - 0x80048104, 0xd2890003, - 0x00000903, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0xbf820008, 0xe0724000, - 0x701d0000, 0xe0724100, - 0x701d0100, 0xe0724200, - 0x701d0200, 0xe0724300, - 0x701d0300, 0xbefe00c1, - 0xbeff00c1, 0xb8fb4306, - 0x867bc17b, 0xbf840064, - 0xbf8a0000, 0x867aff6f, - 0x04000000, 0xbf840060, - 0x8e7b867b, 0x8e7b827b, - 0xbef6007b, 0xb8f02985, - 0x80708170, 0x8e708a70, - 0x8e708170, 0xb8fa1605, - 0x807a817a, 0x8e7a867a, - 0x80707a70, 0x8070ff70, - 0x00000080, 0xbef600ff, - 0x01000000, 0xbefc0080, - 0xd28c0002, 0x000100c1, - 0xd28d0003, 0x000204c1, + 0xbefc007e, 0xbefe007c, + 0xbefc0070, 0xc0611a7a, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0xb8f1f801, 0xbefe007c, + 0xbefc0070, 0xc0611c7a, + 0x0000007c, 0xbf8cc07f, + 0x80708470, 0xbefc007e, + 0x867aff7f, 0x04000000, + 0xbeef0080, 0x876f6f7a, + 0xb8f02985, 0x80708170, + 0x8e708a70, 0x8e708170, + 0xb8fb1605, 0x807b817b, + 0x8e7b847b, 0x8e76827b, + 0xbef600ff, 0x01000000, + 0xbef20174, 0x80747074, + 0x82758075, 0xbefc0080, + 0xbf800000, 0xbe802b00, + 0xbe822b02, 0xbe842b04, + 0xbe862b06, 0xbe882b08, + 0xbe8a2b0a, 0xbe8c2b0c, + 0xbe8e2b0e, 0xc06b003a, + 0x00000000, 0xbf8cc07f, + 0xc06b013a, 0x00000010, + 0xbf8cc07f, 0xc06b023a, + 0x00000020, 0xbf8cc07f, + 0xc06b033a, 0x00000030, + 0xbf8cc07f, 0x8074c074, + 0x82758075, 0x807c907c, + 0xbf0a7b7c, 0xbf85ffe7, + 0xbef40172, 0xbef00080, + 0xbefe00c1, 0xbeff00c1, + 0xbee80080, 0xbee90080, + 0xbef600ff, 0x01000000, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, 0x10000000, - 0xbf850030, 0x24040682, - 0xd86e4000, 0x00000002, - 0xbf8cc07f, 0xbe840080, + 0xbf85004d, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, 0x80048104, @@ -3395,31 +3346,50 @@ static const uint32_t cwsr_trap_gfx9_4_3_hex[] = { 0x80048104, 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, - 0xbf84ffee, 0x680404ff, - 0x00000200, 0xd0c9006a, - 0x0000f702, 0xbf87ffd2, - 0xbf820015, 0xd1060002, - 0x00011103, 0x7e0602ff, - 0x00000200, 0xbefc00ff, - 0x00010000, 0xbe800077, - 0x8677ff77, 0xff7fffff, - 0x8777ff77, 0x00058000, - 0xd8ec0000, 0x00000002, - 0xbf8cc07f, 0xe0765000, - 0x701d0002, 0x68040702, - 0xd0c9006a, 0x0000f702, - 0xbf87fff7, 0xbef70000, - 0xbef000ff, 0x00000400, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000902, + 0x80048104, 0xd2890001, + 0x00000902, 0x80048104, + 0xd2890002, 0x00000902, + 0x80048104, 0xd2890003, + 0x00000902, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbe840080, 0xd2890000, + 0x00000903, 0x80048104, + 0xd2890001, 0x00000903, + 0x80048104, 0xd2890002, + 0x00000903, 0x80048104, + 0xd2890003, 0x00000903, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbf820008, + 0xe0724000, 0x701d0000, + 0xe0724100, 0x701d0100, + 0xe0724200, 0x701d0200, + 0xe0724300, 0x701d0300, 0xbefe00c1, 0xbeff00c1, - 0xb8fb2b05, 0x807b817b, - 0x8e7b827b, 0xbef600ff, - 0x01000000, 0xbefc0084, - 0xbf0a7b7c, 0xbf84006d, - 0xbf11017c, 0x807bff7b, - 0x00001000, 0x867aff78, + 0xb8fb4306, 0x867bc17b, + 0xbf840064, 0xbf8a0000, + 0x867aff6f, 0x04000000, + 0xbf840060, 0x8e7b867b, + 0x8e7b827b, 0xbef6007b, + 0xb8f02985, 0x80708170, + 0x8e708a70, 0x8e708170, + 0xb8fa1605, 0x807a817a, + 0x8e7a867a, 0x80707a70, + 0x8070ff70, 0x00000080, + 0xbef600ff, 0x01000000, + 0xbefc0080, 0xd28c0002, + 0x000100c1, 0xd28d0003, + 0x000204c1, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, - 0x10000000, 0xbf850051, + 0x10000000, 0xbf850030, + 0x24040682, 0xd86e4000, + 0x00000002, 0xbf8cc07f, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, @@ -3439,51 +3409,31 @@ static const uint32_t cwsr_trap_gfx9_4_3_hex[] = { 0xc069003a, 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, - 0xbe840080, 0xd2890000, - 0x00000902, 0x80048104, - 0xd2890001, 0x00000902, - 0x80048104, 0xd2890002, - 0x00000902, 0x80048104, - 0xd2890003, 0x00000902, - 0x80048104, 0xc069003a, - 0x00000070, 0xbf8cc07f, - 0x80709070, 0xbf06c004, - 0xbf84ffee, 0xbe840080, - 0xd2890000, 0x00000903, - 0x80048104, 0xd2890001, - 0x00000903, 0x80048104, - 0xd2890002, 0x00000903, - 0x80048104, 0xd2890003, - 0x00000903, 0x80048104, - 0xc069003a, 0x00000070, - 0xbf8cc07f, 0x80709070, - 0xbf06c004, 0xbf84ffee, - 0x807c847c, 0xbf0a7b7c, - 0xbf85ffb1, 0xbf9c0000, - 0xbf820012, 0x7e000300, - 0x7e020301, 0x7e040302, - 0x7e060303, 0xe0724000, - 0x701d0000, 0xe0724100, - 0x701d0100, 0xe0724200, - 0x701d0200, 0xe0724300, - 0x701d0300, 0x807c847c, - 0x8070ff70, 0x00000400, - 0xbf0a7b7c, 0xbf85ffef, - 0xbf9c0000, 0xb8fb2985, - 0x807b817b, 0x8e7b837b, - 0xb8fa2b05, 0x807a817a, - 0x8e7a827a, 0x80fb7a7b, - 0x867b7b7b, 0xbf84007a, + 0x680404ff, 0x00000200, + 0xd0c9006a, 0x0000f702, + 0xbf87ffd2, 0xbf820015, + 0xd1060002, 0x00011103, + 0x7e0602ff, 0x00000200, + 0xbefc00ff, 0x00010000, + 0xbe800077, 0x8677ff77, + 0xff7fffff, 0x8777ff77, + 0x00058000, 0xd8ec0000, + 0x00000002, 0xbf8cc07f, + 0xe0765000, 0x701d0002, + 0x68040702, 0xd0c9006a, + 0x0000f702, 0xbf87fff7, + 0xbef70000, 0xbef000ff, + 0x00000400, 0xbefe00c1, + 0xbeff00c1, 0xb8fb2b05, + 0x807b817b, 0x8e7b827b, + 0xbef600ff, 0x01000000, + 0xbefc0084, 0xbf0a7b7c, + 0xbf84006d, 0xbf11017c, 0x807bff7b, 0x00001000, - 0xbefc0080, 0xbf11017c, 0x867aff78, 0x00400000, 0xbf850003, 0xb8faf803, 0x897a7aff, 0x10000000, - 0xbf850059, 0xd3d84000, - 0x18000100, 0xd3d84001, - 0x18000101, 0xd3d84002, - 0x18000102, 0xd3d84003, - 0x18000103, 0xbe840080, + 0xbf850051, 0xbe840080, 0xd2890000, 0x00000900, 0x80048104, 0xd2890001, 0x00000900, 0x80048104, @@ -3522,139 +3472,203 @@ static const uint32_t cwsr_trap_gfx9_4_3_hex[] = { 0x00000070, 0xbf8cc07f, 0x80709070, 0xbf06c004, 0xbf84ffee, 0x807c847c, - 0xbf0a7b7c, 0xbf85ffa9, - 0xbf9c0000, 0xbf820016, - 0xd3d84000, 0x18000100, - 0xd3d84001, 0x18000101, - 0xd3d84002, 0x18000102, - 0xd3d84003, 0x18000103, + 0xbf0a7b7c, 0xbf85ffb1, + 0xbf9c0000, 0xbf820012, + 0x7e000300, 0x7e020301, + 0x7e040302, 0x7e060303, 0xe0724000, 0x701d0000, 0xe0724100, 0x701d0100, 0xe0724200, 0x701d0200, 0xe0724300, 0x701d0300, 0x807c847c, 0x8070ff70, 0x00000400, 0xbf0a7b7c, - 0xbf85ffeb, 0xbf9c0000, - 0xbf8200ee, 0xbef4007e, - 0x8675ff7f, 0x0000ffff, - 0x8775ff75, 0x00040000, - 0xbef60080, 0xbef700ff, - 0x00807fac, 0x866eff7f, - 0x04000000, 0xbf84001f, + 0xbf85ffef, 0xbf9c0000, + 0xb8fb2985, 0x807b817b, + 0x8e7b837b, 0xb8fa2b05, + 0x807a817a, 0x8e7a827a, + 0x80fb7a7b, 0x867b7b7b, + 0xbf84007a, 0x807bff7b, + 0x00001000, 0xbefc0080, + 0xbf11017c, 0x867aff78, + 0x00400000, 0xbf850003, + 0xb8faf803, 0x897a7aff, + 0x10000000, 0xbf850059, + 0xd3d84000, 0x18000100, + 0xd3d84001, 0x18000101, + 0xd3d84002, 0x18000102, + 0xd3d84003, 0x18000103, + 0xbe840080, 0xd2890000, + 0x00000900, 0x80048104, + 0xd2890001, 0x00000900, + 0x80048104, 0xd2890002, + 0x00000900, 0x80048104, + 0xd2890003, 0x00000900, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000901, + 0x80048104, 0xd2890001, + 0x00000901, 0x80048104, + 0xd2890002, 0x00000901, + 0x80048104, 0xd2890003, + 0x00000901, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0xbe840080, 0xd2890000, + 0x00000902, 0x80048104, + 0xd2890001, 0x00000902, + 0x80048104, 0xd2890002, + 0x00000902, 0x80048104, + 0xd2890003, 0x00000902, + 0x80048104, 0xc069003a, + 0x00000070, 0xbf8cc07f, + 0x80709070, 0xbf06c004, + 0xbf84ffee, 0xbe840080, + 0xd2890000, 0x00000903, + 0x80048104, 0xd2890001, + 0x00000903, 0x80048104, + 0xd2890002, 0x00000903, + 0x80048104, 0xd2890003, + 0x00000903, 0x80048104, + 0xc069003a, 0x00000070, + 0xbf8cc07f, 0x80709070, + 0xbf06c004, 0xbf84ffee, + 0x807c847c, 0xbf0a7b7c, + 0xbf85ffa9, 0xbf9c0000, + 0xbf820016, 0xd3d84000, + 0x18000100, 0xd3d84001, + 0x18000101, 0xd3d84002, + 0x18000102, 0xd3d84003, + 0x18000103, 0xe0724000, + 0x701d0000, 0xe0724100, + 0x701d0100, 0xe0724200, + 0x701d0200, 0xe0724300, + 0x701d0300, 0x807c847c, + 0x8070ff70, 0x00000400, + 0xbf0a7b7c, 0xbf85ffeb, + 0xbf9c0000, 0xbf8200ee, + 0xbef4007e, 0x8675ff7f, + 0x0000ffff, 0x8775ff75, + 0x00040000, 0xbef60080, + 0xbef700ff, 0x00807fac, + 0x866eff7f, 0x04000000, + 0xbf84001f, 0xbefe00c1, + 0xbeff00c1, 0xb8ef4306, + 0x866fc16f, 0xbf84001a, + 0x8e6f866f, 0x8e6f826f, + 0xbef6006f, 0xb8f82985, + 0x80788178, 0x8e788a78, + 0x8e788178, 0xb8ee1605, + 0x806e816e, 0x8e6e866e, + 0x80786e78, 0x8078ff78, + 0x00000080, 0xbef600ff, + 0x01000000, 0xbefc0080, + 0xe0510000, 0x781d0000, + 0xe0510100, 0x781d0000, + 0x807cff7c, 0x00000200, + 0x8078ff78, 0x00000200, + 0xbf0a6f7c, 0xbf85fff6, 0xbefe00c1, 0xbeff00c1, - 0xb8ef4306, 0x866fc16f, - 0xbf84001a, 0x8e6f866f, - 0x8e6f826f, 0xbef6006f, - 0xb8f82985, 0x80788178, - 0x8e788a78, 0x8e788178, - 0xb8ee1605, 0x806e816e, - 0x8e6e866e, 0x80786e78, - 0x8078ff78, 0x00000080, 0xbef600ff, 0x01000000, - 0xbefc0080, 0xe0510000, - 0x781d0000, 0xe0510100, - 0x781d0000, 0x807cff7c, - 0x00000200, 0x8078ff78, - 0x00000200, 0xbf0a6f7c, - 0xbf85fff6, 0xbefe00c1, - 0xbeff00c1, 0xbef600ff, - 0x01000000, 0xb8ef2b05, - 0x806f816f, 0x8e6f826f, - 0x806fff6f, 0x00008000, - 0xbef80080, 0xbeee0078, - 0x8078ff78, 0x00000400, - 0xbefc0084, 0xbf11087c, - 0xe0524000, 0x781d0000, - 0xe0524100, 0x781d0100, - 0xe0524200, 0x781d0200, - 0xe0524300, 0x781d0300, - 0xbf8c0f70, 0x7e000300, - 0x7e020301, 0x7e040302, - 0x7e060303, 0x807c847c, - 0x8078ff78, 0x00000400, - 0xbf0a6f7c, 0xbf85ffee, - 0xb8ef2985, 0x806f816f, - 0x8e6f836f, 0xb8f92b05, - 0x80798179, 0x8e798279, - 0x80ef796f, 0x866f6f6f, - 0xbf84001a, 0x806fff6f, - 0x00008000, 0xbefc0080, + 0xb8ef2b05, 0x806f816f, + 0x8e6f826f, 0x806fff6f, + 0x00008000, 0xbef80080, + 0xbeee0078, 0x8078ff78, + 0x00000400, 0xbefc0084, 0xbf11087c, 0xe0524000, 0x781d0000, 0xe0524100, 0x781d0100, 0xe0524200, 0x781d0200, 0xe0524300, 0x781d0300, 0xbf8c0f70, - 0xd3d94000, 0x18000100, - 0xd3d94001, 0x18000101, - 0xd3d94002, 0x18000102, - 0xd3d94003, 0x18000103, + 0x7e000300, 0x7e020301, + 0x7e040302, 0x7e060303, 0x807c847c, 0x8078ff78, 0x00000400, 0xbf0a6f7c, - 0xbf85ffea, 0xbf9c0000, - 0xe0524000, 0x6e1d0000, - 0xe0524100, 0x6e1d0100, - 0xe0524200, 0x6e1d0200, - 0xe0524300, 0x6e1d0300, - 0xbf8c0f70, 0xb8f82985, - 0x80788178, 0x8e788a78, - 0x8e788178, 0xb8ee1605, - 0x806e816e, 0x8e6e866e, - 0x80786e78, 0x80f8c078, - 0xb8ef1605, 0x806f816f, - 0x8e6f846f, 0x8e76826f, - 0xbef600ff, 0x01000000, - 0xbefc006f, 0xc031003a, - 0x00000078, 0x80f8c078, - 0xbf8cc07f, 0x80fc907c, - 0xbf800000, 0xbe802d00, - 0xbe822d02, 0xbe842d04, - 0xbe862d06, 0xbe882d08, - 0xbe8a2d0a, 0xbe8c2d0c, - 0xbe8e2d0e, 0xbf06807c, - 0xbf84fff0, 0xb8f82985, - 0x80788178, 0x8e788a78, - 0x8e788178, 0xb8ee1605, - 0x806e816e, 0x8e6e866e, - 0x80786e78, 0xbef60084, - 0xbef600ff, 0x01000000, - 0xc0211bfa, 0x00000078, - 0x80788478, 0xc0211b3a, + 0xbf85ffee, 0xb8ef2985, + 0x806f816f, 0x8e6f836f, + 0xb8f92b05, 0x80798179, + 0x8e798279, 0x80ef796f, + 0x866f6f6f, 0xbf84001a, + 0x806fff6f, 0x00008000, + 0xbefc0080, 0xbf11087c, + 0xe0524000, 0x781d0000, + 0xe0524100, 0x781d0100, + 0xe0524200, 0x781d0200, + 0xe0524300, 0x781d0300, + 0xbf8c0f70, 0xd3d94000, + 0x18000100, 0xd3d94001, + 0x18000101, 0xd3d94002, + 0x18000102, 0xd3d94003, + 0x18000103, 0x807c847c, + 0x8078ff78, 0x00000400, + 0xbf0a6f7c, 0xbf85ffea, + 0xbf9c0000, 0xe0524000, + 0x6e1d0000, 0xe0524100, + 0x6e1d0100, 0xe0524200, + 0x6e1d0200, 0xe0524300, + 0x6e1d0300, 0xbf8c0f70, + 0xb8f82985, 0x80788178, + 0x8e788a78, 0x8e788178, + 0xb8ee1605, 0x806e816e, + 0x8e6e866e, 0x80786e78, + 0x80f8c078, 0xb8ef1605, + 0x806f816f, 0x8e6f846f, + 0x8e76826f, 0xbef600ff, + 0x01000000, 0xbefc006f, + 0xc031003a, 0x00000078, + 0x80f8c078, 0xbf8cc07f, + 0x80fc907c, 0xbf800000, + 0xbe802d00, 0xbe822d02, + 0xbe842d04, 0xbe862d06, + 0xbe882d08, 0xbe8a2d0a, + 0xbe8c2d0c, 0xbe8e2d0e, + 0xbf06807c, 0xbf84fff0, + 0xb8f82985, 0x80788178, + 0x8e788a78, 0x8e788178, + 0xb8ee1605, 0x806e816e, + 0x8e6e866e, 0x80786e78, + 0xbef60084, 0xbef600ff, + 0x01000000, 0xc0211bfa, 0x00000078, 0x80788478, - 0xc0211b7a, 0x00000078, - 0x80788478, 0xc0211c3a, + 0xc0211b3a, 0x00000078, + 0x80788478, 0xc0211b7a, 0x00000078, 0x80788478, - 0xc0211c7a, 0x00000078, - 0x80788478, 0xc0211eba, + 0xc0211c3a, 0x00000078, + 0x80788478, 0xc0211c7a, 0x00000078, 0x80788478, - 0xc0211efa, 0x00000078, - 0x80788478, 0xc0211a3a, + 0xc0211eba, 0x00000078, + 0x80788478, 0xc0211efa, 0x00000078, 0x80788478, - 0xc0211a7a, 0x00000078, - 0x80788478, 0xc0211cfa, + 0xc0211a3a, 0x00000078, + 0x80788478, 0xc0211a7a, 0x00000078, 0x80788478, - 0xbf8cc07f, 0xbefc006f, - 0xbefe0070, 0xbeff0071, - 0x866f7bff, 0x000003ff, - 0xb96f4803, 0x866f7bff, - 0xfffff800, 0x8f6f8b6f, - 0xb96fa2c3, 0xb973f801, - 0xb8ee2985, 0x806e816e, - 0x8e6e8a6e, 0x8e6e816e, - 0xb8ef1605, 0x806f816f, - 0x8e6f866f, 0x806e6f6e, - 0x806e746e, 0x826f8075, - 0x866fff6f, 0x0000ffff, - 0xc00b1c37, 0x00000050, - 0xc00b1d37, 0x00000060, - 0xc0031e77, 0x00000074, - 0xbf8cc07f, 0x8f6e8b79, - 0x866eff6e, 0x001f8000, - 0xb96ef807, 0x866dff6d, - 0x0000ffff, 0x86fe7e7e, - 0x86ea6a6a, 0x8f6e837a, - 0xb96ee0c2, 0xbf800002, - 0xb97a0002, 0xbf8a0000, - 0xbe801f6c, 0xbf9b0000, + 0xc0211cfa, 0x00000078, + 0x80788478, 0xbf8cc07f, + 0xbefc006f, 0xbefe0070, + 0xbeff0071, 0x866f7bff, + 0x000003ff, 0xb96f4803, + 0x866f7bff, 0xfffff800, + 0x8f6f8b6f, 0xb96fa2c3, + 0xb973f801, 0xb8ee2985, + 0x806e816e, 0x8e6e8a6e, + 0x8e6e816e, 0xb8ef1605, + 0x806f816f, 0x8e6f866f, + 0x806e6f6e, 0x806e746e, + 0x826f8075, 0x866fff6f, + 0x0000ffff, 0xc00b1c37, + 0x00000050, 0xc00b1d37, + 0x00000060, 0xc0031e77, + 0x00000074, 0xbf8cc07f, + 0x8f6e8b79, 0x866eff6e, + 0x001f8000, 0xb96ef807, + 0x866dff6d, 0x0000ffff, + 0x86fe7e7e, 0x86ea6a6a, + 0x8f6e837a, 0xb96ee0c2, + 0xbf800002, 0xb97a0002, + 0xbf8a0000, 0xbe801f6c, + 0xbf9b0000, 0x00000000, }; static const uint32_t cwsr_trap_gfx12_hex[] = { diff --git a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm index 483ef6a45a831..e5887e58c3374 100644 --- a/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm +++ b/drivers/gpu/drm/amd/amdkfd/cwsr_trap_handler_gfx9.asm @@ -83,6 +83,7 @@ var SQ_WAVE_TRAPSTS_ADDR_WATCH_SHIFT = 7 var SQ_WAVE_TRAPSTS_MEM_VIOL_MASK = 0x100 var SQ_WAVE_TRAPSTS_MEM_VIOL_SHIFT = 8 var SQ_WAVE_TRAPSTS_HOST_TRAP_MASK = 0x400000 +var SQ_WAVE_TRAPSTS_HOST_TRAP_SHIFT = 22 var SQ_WAVE_TRAPSTS_WAVE_BEGIN_MASK = 0x800000 var SQ_WAVE_TRAPSTS_WAVE_END_MASK = 0x1000000 var SQ_WAVE_TRAPSTS_TRAP_AFTER_INST_MASK = 0x2000000 @@ -104,20 +105,25 @@ var SQ_WAVE_IB_STS_RCNT_FIRST_REPLAY_MASK = 0x1F8000 var SQ_WAVE_MODE_DEBUG_EN_MASK = 0x800 -var TMA_HOST_TRAP_EN_SHIFT = 1 -var TMA_HOST_TRAP_EN_SIZE = 1 -var TMA_HOST_TRAP_EN_BFE = (TMA_HOST_TRAP_EN_SHIFT | (TMA_HOST_TRAP_EN_SIZE << 16)) - var TTMP_SAVE_RCNT_FIRST_REPLAY_SHIFT = 26 // bits [31:26] unused by SPI debug data var TTMP_SAVE_RCNT_FIRST_REPLAY_MASK = 0xFC000000 var TTMP_DEBUG_TRAP_ENABLED_SHIFT = 23 var TTMP_DEBUG_TRAP_ENABLED_MASK = 0x800000 +var TTMP_HOST_TRAP_ENABLED_SHIFT = 24 +var TTMP_HOST_TRAP_ENABLED_MASK = 0x1000000 +var TTMP_FEATURES_ENABLED_FLAGS_SHIFT = TTMP_DEBUG_TRAP_ENABLED_SHIFT +var TTMP_FEATURES_ENABLED_FLAGS_MASK = TTMP_DEBUG_TRAP_ENABLED_MASK | TTMP_HOST_TRAP_ENABLED_MASK /* Save */ var S_SAVE_BUF_RSRC_WORD1_STRIDE = 0x00040000 //stride is 4 bytes var S_SAVE_BUF_RSRC_WORD3_MISC = 0x00807FAC //SQ_SEL_X/Y/Z/W, BUF_NUM_FORMAT_FLOAT, (0 for MUBUF stride[17:14] when ADD_TID_ENABLE and BUF_DATA_FORMAT_32 for MTBUF), ADD_TID_ENABLE var S_SAVE_PC_HI_TRAP_ID_MASK = 0x00FF0000 var S_SAVE_PC_HI_HT_MASK = 0x01000000 +var S_SAVE_PC_HI_HT_SHIFT = 24 +var S_SAVE_PC_HI_NON_DRIVER_MASKABLE_TRAP = 29 // Only used by the 1st level trap handler to remember if + // we saw a trap type that the driver could not mask, so that + // we can still go to the 2nd-level handler if we driver-mask another + // simultaneous trap. var S_SAVE_SPI_INIT_FIRST_WAVE_MASK = 0x04000000 //bit[26]: FirstWaveInTG var S_SAVE_SPI_INIT_FIRST_WAVE_SHIFT = 26 @@ -143,9 +149,15 @@ var s_save_m0 = ttmp5 var s_save_ttmps_lo = s_save_tmp //no conflict var s_save_ttmps_hi = s_save_trapsts //no conflict #if ASIC_FAMILY >= CHIP_GC_9_4_3 -var s_save_ib_sts = ttmp13 +var s_save_ib_sts = ttmp13 // bits 31:26 hold IB_STS, bit 23 to hold debug flag to 2nd-level, + // bit 24 to hold host-trap request + // so bits 22:0 are available for stashing next variable's backup. +var s_tma_flags = ttmp7 // free #else -var s_save_ib_sts = ttmp11 +var s_save_ib_sts = ttmp11 // bits 31:26 hold IB_STS, bit 23 to hold debug flag to 2nd-level, + // bit 24 to hold host-trap request, bit 6 is no-scratch, bits 5-0 are wave-in-wg + // so bits 22:7 are available for stashing next variable's backup +var s_tma_flags = ttmp13 // free #endif /* Restore */ @@ -214,8 +226,8 @@ L_SKIP_RESTORE: L_HALTED: // Host trap may occur while wave is halted. - s_and_b32 ttmp2, s_save_pc_hi, S_SAVE_PC_HI_TRAP_ID_MASK - s_cbranch_scc1 L_FETCH_2ND_TRAP + s_bitcmp1_b32 s_save_pc_hi, S_SAVE_PC_HI_HT_SHIFT + s_cbranch_scc1 L_FETCH_2ND_TRAP_DRIVER_MASKABLE L_CHECK_SAVE: s_and_b32 ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_SAVECTX_MASK //check whether this is for save @@ -233,22 +245,16 @@ L_NOT_HALTED: // Any concurrent SAVECTX will be handled upon re-entry once halted. // Check non-maskable exceptions. memory_violation, illegal_instruction - // and debugger (host trap, wave start/end, trap after instruction) - // exceptions always cause the wave to enter the trap handler. + // and debugger (wave start/end, trap after instruction) exceptions always + // cause the wave to enter the trap handler. s_and_b32 ttmp2, s_save_trapsts, \ SQ_WAVE_TRAPSTS_MEM_VIOL_MASK | \ SQ_WAVE_TRAPSTS_ILLEGAL_INST_MASK | \ - SQ_WAVE_TRAPSTS_HOST_TRAP_MASK | \ SQ_WAVE_TRAPSTS_WAVE_BEGIN_MASK | \ SQ_WAVE_TRAPSTS_WAVE_END_MASK | \ SQ_WAVE_TRAPSTS_TRAP_AFTER_INST_MASK s_cbranch_scc1 L_FETCH_2ND_TRAP - // Check TTMP1 bits 24 (HT) and 23:16(trapID): HT == 1 & trapID == 4 - s_and_b32 ttmp2, s_save_pc_hi, (S_SAVE_PC_HI_TRAP_ID_MASK|S_SAVE_PC_HI_HT_MASK) - s_cmp_eq_u32 ttmp2, 0x1040000 - s_cbranch_scc1 L_FETCH_2ND_TRAP - // Check for maskable exceptions in trapsts.excp and trapsts.excp_hi. // Maskable exceptions only cause the wave to enter the trap handler if // their respective bit in mode.excp_en is set. @@ -266,9 +272,15 @@ L_NOT_ADDR_WATCH: s_cbranch_scc1 L_FETCH_2ND_TRAP L_CHECK_TRAP_ID: - // Check trap_id != 0 + // Check trap_id != 0. If this is a host trap (ttmp1.HT == 1), trap_id is + // non 0, but we defer that part of the check until later as this exception + // is driver maskable. We need to make sure that all non-driver-maskable + // exceptions are accounted for before checking for driver-maskable ones. + s_bitcmp1_b32 s_save_pc_hi, S_SAVE_PC_HI_HT_SHIFT + s_cbranch_scc1 L_SKIP_CHECK_TRAP_ID s_and_b32 ttmp2, s_save_pc_hi, S_SAVE_PC_HI_TRAP_ID_MASK s_cbranch_scc1 L_FETCH_2ND_TRAP +L_SKIP_CHECK_TRAP_ID: if SINGLE_STEP_MISSED_WORKAROUND // Prioritize single step exception over context save. @@ -278,16 +290,22 @@ if SINGLE_STEP_MISSED_WORKAROUND s_cbranch_scc1 L_FETCH_2ND_TRAP end + // Check TTMP1 bits 24 (HT) == 1 + s_bitcmp1_b32 s_save_pc_hi, S_SAVE_PC_HI_HT_SHIFT + s_cbranch_scc1 L_FETCH_2ND_TRAP_DRIVER_MASKABLE + s_and_b32 ttmp2, s_save_trapsts, SQ_WAVE_TRAPSTS_SAVECTX_MASK s_cbranch_scc1 L_SAVE L_FETCH_2ND_TRAP: + s_bitset1_b32 s_save_pc_hi, S_SAVE_PC_HI_NON_DRIVER_MASKABLE_TRAP +L_FETCH_2ND_TRAP_DRIVER_MASKABLE: // Preserve and clear scalar XNACK state before issuing scalar reads. save_and_clear_ib_sts(ttmp14) // Read second-level TBA/TMA from first-level TMA and jump if available. - // ttmp[2:5] and ttmp12 can be used (others hold SPI-initialized debug data) - // ttmp12 holds SQ_WAVE_STATUS + // ttmp[2:5] and s_tma_flags can be used (others hold SPI-initialized debug + // data) ttmp12 holds SQ_WAVE_STATUS s_getreg_b32 ttmp14, hwreg(HW_REG_SQ_SHADER_TMA_LO) s_getreg_b32 ttmp15, hwreg(HW_REG_SQ_SHADER_TMA_HI) s_lshl_b64 [ttmp14, ttmp15], [ttmp14, ttmp15], 0x8 @@ -296,22 +314,42 @@ L_FETCH_2ND_TRAP: s_cbranch_scc0 L_NO_SIGN_EXTEND_TMA s_or_b32 ttmp15, ttmp15, 0xFFFF0000 L_NO_SIGN_EXTEND_TMA: - - s_load_dword ttmp4, [ttmp14, ttmp15], 0x10 glc:1 // enable flags from 1st level TMA + s_load_dword s_tma_flags, [ttmp14, ttmp15], 0x10 glc:1 //Load the debug enables and host trap enabled flags s_load_dwordx2 [ttmp2, ttmp3], [ttmp14, ttmp15], 0x0 glc:1 // second-level TBA s_load_dwordx2 [ttmp14, ttmp15], [ttmp14, ttmp15], 0x8 glc:1 // second-level TMA s_waitcnt lgkmcnt(0) - s_and_b32 ttmp5, s_save_pc_hi, S_SAVE_PC_HI_HT_MASK // host trap request - s_cbranch_scc0 L_NOT_HT - s_bfe_u32 ttmp5, ttmp4, TMA_HOST_TRAP_EN_BFE // extract host_trap_en to ttmp5[0] - s_cbranch_scc0 L_EXIT_TRAP // HT requested, but host traps not enabled - s_branch L_GOTO_2ND_TRAP -L_NOT_HT: - s_and_b32 ttmp4, ttmp4, 0x1 // debug_enable bit left over - s_lshl_b32 ttmp4, ttmp4, TTMP_DEBUG_TRAP_ENABLED_SHIFT - s_andn2_b32 s_save_ib_sts, s_save_ib_sts, TTMP_DEBUG_TRAP_ENABLED_MASK - s_or_b32 s_save_ib_sts, s_save_ib_sts, ttmp4 + + // Put debug enable bit and host trap bit into SAVE_IB_STS register, bits + // 23 and 24, respectively. + s_lshl_b32 s_tma_flags, s_tma_flags, TTMP_FEATURES_ENABLED_FLAGS_SHIFT + s_andn2_b32 s_save_ib_sts, s_save_ib_sts, TTMP_FEATURES_ENABLED_FLAGS_MASK + s_or_b32 s_save_ib_sts, s_save_ib_sts, s_tma_flags + + // If not a host trap, then driver cannot mask this. Go to the 2nd-level + // trap handler now. + s_bitcmp1_b32 s_save_pc_hi, S_SAVE_PC_HI_HT_SHIFT + s_cbranch_scc0 L_GOTO_2ND_TRAP + + // If driver said host traps are OK, go to the 2nd-level handler now. + s_bitcmp1_b32 s_save_ib_sts, TTMP_HOST_TRAP_ENABLED_SHIFT + s_cbranch_scc1 L_GOTO_2ND_TRAP + + // The driver said host traps are masked, zero out host trap and trapID. + s_andn2_b32 s_save_pc_hi, s_save_pc_hi, (S_SAVE_PC_HI_TRAP_ID_MASK|S_SAVE_PC_HI_HT_MASK) + s_setreg_imm32_b32 hwreg(HW_REG_TRAPSTS, SQ_WAVE_TRAPSTS_HOST_TRAP_SHIFT, 1), 0x0 + + // If there was another trap besides this masked host trap, go handle it in + // 2nd-level handler. + s_bitcmp1_b32 s_save_pc_hi, S_SAVE_PC_HI_NON_DRIVER_MASKABLE_TRAP + s_bitset0_b32 s_save_pc_hi, S_SAVE_PC_HI_NON_DRIVER_MASKABLE_TRAP // zero this out + s_cbranch_scc0 L_EXIT_TRAP // Otherwise, exit the trap handler + L_GOTO_2ND_TRAP: + // Reset bits used temporarily by 1st level trap handler so they do not + // leak to the 2nd level trap handler. + s_bitset0_b32 s_save_ib_sts, TTMP_HOST_TRAP_ENABLED_SHIFT + s_bitset0_b32 s_save_pc_hi, S_SAVE_PC_HI_NON_DRIVER_MASKABLE_TRAP + s_and_b64 [ttmp2, ttmp3], [ttmp2, ttmp3], [ttmp2, ttmp3] s_cbranch_scc0 L_NO_NEXT_TRAP // second-level trap handler not been set s_setpc_b64 [ttmp2, ttmp3] // jump to second-level trap handler From c00740202d7d587685fab70e273ba97e9d0c8262 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 19 Mar 2024 13:20:23 +0800 Subject: [PATCH 1202/1868] drm/amdkcl: wrap code under macro HAVE_DRM_DISPLAY_INFO_MONITOR_RANGE It's caused by 3c88b4c01ad1ca5fc725b96bcdb2cc04d2851305 "drm/amd/display: Get min/max vfreq from display_info" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index b40cf47ae6914..88d422b61b556 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -12321,11 +12321,13 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, if (amdgpu_dm_connector->dc_link && amdgpu_dm_connector->dc_link->dpcd_caps.allow_invalid_MSA_timing_param) { if (edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ) { +#ifdef HAVE_DRM_DISPLAY_INFO_MONITOR_RANGE amdgpu_dm_connector->min_vfreq = connector->display_info.monitor_range.min_vfreq; amdgpu_dm_connector->max_vfreq = connector->display_info.monitor_range.max_vfreq; if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) freesync_capable = true; +#endif } else { edid_check_required = edid->version > 1 || (edid->version == 1 && From 83e9a17b588c6efa4144003d461ec5fd7e1011b6 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 20 Mar 2024 12:14:20 +0800 Subject: [PATCH 1203/1868] drm/amdkcl: wrap code under amdkcl_ttm_resvp() It's caused by 0af3db3ac5b50b67ca88dda58de9b6c4637a8b9c "drm/amdgpu: implement TLB flush fence" Signed-off-by: Bob Zhou Reviewed-by: Jun Ma --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 479391fc9a0ab..44b57a7cb78e1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -934,7 +934,7 @@ amdgpu_vm_tlb_flush(struct amdgpu_vm_update_params *params, amdgpu_vm_tlb_fence_create(params->adev, vm, fence); /* Makes sure no PD/PT is freed before the flush */ - dma_resv_add_fence(vm->root.bo->tbo.base.resv, *fence, + dma_resv_add_fence(amdkcl_ttm_resvp(&vm->root.bo->tbo), *fence, DMA_RESV_USAGE_BOOKKEEP); } } From 038d19d216919cd17836dbe37e48cb2e20746366 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 20 Mar 2024 12:15:59 +0800 Subject: [PATCH 1204/1868] drm/amdkcl: wrap code undre macro HAVE_DMA_FENCE_OPS_USE_64BIT_SEQNO It's caused by 0af3db3ac5b50b67ca88dda58de9b6c4637a8b9c "drm/amdgpu: implement TLB flush fence" Signed-off-by: Bob Zhou Reviewed-by: Jun Ma --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm_tlb_fence.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_tlb_fence.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_tlb_fence.c index 51cddfa3f1e8f..1a7b5cbc52a8d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_tlb_fence.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_tlb_fence.c @@ -71,7 +71,9 @@ static void amdgpu_tlb_fence_work(struct work_struct *work) } static const struct dma_fence_ops amdgpu_tlb_fence_ops = { +#ifdef HAVE_DMA_FENCE_OPS_USE_64BIT_SEQNO .use_64bit_seqno = true, +#endif .get_driver_name = amdgpu_tlb_fence_get_driver_name, .get_timeline_name = amdgpu_tlb_fence_get_timeline_name }; From b4aebf7a80db48ef4674104838a6c43cad3bb0ad Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 2 Apr 2024 13:52:15 +0800 Subject: [PATCH 1205/1868] Bump AMDGPU version to 6.8.0 Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/configure.ac | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/configure.ac b/drivers/gpu/drm/amd/dkms/configure.ac index 61264904932e5..b7b164ae0201c 100644 --- a/drivers/gpu/drm/amd/dkms/configure.ac +++ b/drivers/gpu/drm/amd/dkms/configure.ac @@ -1,4 +1,4 @@ -AC_INIT(amdgpu-dkms, 6.7.0) +AC_INIT(amdgpu-dkms, 6.8.0) AC_LANG(C) AC_CONFIG_AUX_DIR([config]) From ad3011fda646d78499705561ca555fbb34f9cda3 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 29 Mar 2024 11:22:23 +0800 Subject: [PATCH 1206/1868] drm/amdkcl: fake macro function DIV64_U64_ROUND_UP It's caused by 1f0f4865388bd1d19701d1d65552535dd890e566 "drm/amd/display: Add timing pixel encoding for mst mode validation" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/kcl_math64.h | 11 +++++++++++ 2 files changed, 12 insertions(+) create mode 100644 include/kcl/kcl_math64.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 70898b45f1388..5b6a4ed692d8d 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -124,4 +124,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/kcl_math64.h b/include/kcl/kcl_math64.h new file mode 100644 index 0000000000000..f1d04dee6b8c5 --- /dev/null +++ b/include/kcl/kcl_math64.h @@ -0,0 +1,11 @@ +#ifndef AMDKCL_MATH64_H +#define AMDKCL_MATH64_H + +#include + +#ifndef DIV64_U64_ROUND_UP +#define DIV64_U64_ROUND_UP(ll, d) \ + ({ u64 _tmp = (d); div64_u64((ll) + _tmp - 1, _tmp); }) +#endif + +#endif \ No newline at end of file From 99e02a60d4187b743e78b42ebf8d96a86fab3b8b Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 29 Mar 2024 11:29:47 +0800 Subject: [PATCH 1207/1868] drm/amdkcl: wrap code out of macro HAVE_DRM_DP_MST_ATOMIC_CHECK It's caused by 1f0f4865388bd1d19701d1d65552535dd890e566 "drm/amd/display: Add timing pixel encoding for mst mode validation" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 2f4aecf1c1d42..0eb1617fcc513 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -962,6 +962,7 @@ struct dsc_mst_fairness_params { uint32_t bpp_overwrite; struct amdgpu_dm_connector *aconnector; }; +#endif #if defined(CONFIG_DRM_AMD_DC_FP) static uint16_t get_fec_overhead_multiplier(struct dc_link *dc_link) @@ -986,6 +987,7 @@ static int kbps_to_peak_pbn(int kbps, uint16_t fec_overhead_multiplier_x1000) return (int) DIV64_U64_ROUND_UP(peak_kbps * 64, (54 * 8 * 1000)); } +#if defined(HAVE_DRM_DP_MST_ATOMIC_CHECK) static void set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params *params, struct dsc_mst_fairness_vars *vars, int count, From 9635d12fc57007e64bef6c105974c31a6fe52db5 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 1 Apr 2024 17:53:57 +0800 Subject: [PATCH 1208/1868] drm/amdkcl: fake display legacy macros It's caused by fd4faa19ceb32ed720c818570e5a01d0da456396 "drm/amd/display: Drop legacy code" Signed-off-by: Bob Zhou Reviewed-by: Ma Jun --- include/kcl/kcl_drm_dp.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/include/kcl/kcl_drm_dp.h b/include/kcl/kcl_drm_dp.h index 1f277a16b5874..25c848be0df94 100644 --- a/include/kcl/kcl_drm_dp.h +++ b/include/kcl/kcl_drm_dp.h @@ -22,6 +22,8 @@ #ifndef _KCL_DRM_DP_H #define _KCL_DRM_DP_H +#include + #ifndef DP_SINK_VIDEO_FALLBACK_FORMATS #define DP_SINK_VIDEO_FALLBACK_FORMATS 0x020 #endif @@ -64,4 +66,14 @@ #define DP_INTRA_HOP_AUX_REPLY_INDICATION (1 << 3) #endif +#ifndef DP_DFP_CAPABILITY_EXTENSION_SUPPORT +#define DP_DFP_CAPABILITY_EXTENSION_SUPPORT 0x0A3 +#endif +#ifndef DP_TEST_264BIT_CUSTOM_PATTERN_7_0 +#define DP_TEST_264BIT_CUSTOM_PATTERN_7_0 0X2230 +#endif +#ifndef DP_TEST_264BIT_CUSTOM_PATTERN_263_256 +#define DP_TEST_264BIT_CUSTOM_PATTERN_263_256 0X2250 +#endif + #endif \ No newline at end of file From 0c873c5ae22d8a3b9055b1f1df015801bf8fefca Mon Sep 17 00:00:00 2001 From: David Yat Sin Date: Mon, 1 Apr 2024 13:30:38 +0000 Subject: [PATCH 1209/1868] drm/amdkfd: return success when no buffer provided For PC Sampling, when user application queries current device capabilities and does not provide buffer, this is used to query the size of buffer needed. Return success instead of error. Return the number of valid samples to the user in case the user provided a larger buffer than needed. Signed-off-by: David Yat Sin Acked-by: Felix Kuehling Reviewed-by: Jonathan Kim --- drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index fc5333603613b..4572ac447ee4b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -133,6 +133,7 @@ static int kfd_pc_sample_query_cap(struct kfd_process_device *pdd, int num_method = 0; int ret; int i; + const uint32_t user_num_sample_info = user_args->num_sample_info; for (i = 0; i < ARRAY_SIZE(supported_formats); i++) if (KFD_GC_VERSION(pdd->dev) == supported_formats[i].ip_version) @@ -160,8 +161,15 @@ static int kfd_pc_sample_query_cap(struct kfd_process_device *pdd, } mutex_unlock(&pdd->dev->pcs_data.mutex); - if (!user_args->sample_info_ptr || user_args->num_sample_info < num_method) { - user_args->num_sample_info = num_method; + user_args->num_sample_info = num_method; + + if (!user_args->sample_info_ptr || !user_num_sample_info) { + /* + * User application is querying the size of buffer needed. Application will + * allocate required buffer size and send a second query. + */ + return 0; + } else if (user_num_sample_info < num_method) { pr_debug("ASIC requires space for %d kfd_pc_sample_info entries.", num_method); return -ENOSPC; } From 7807461714b39436c8d4cb79b04b856e55104a72 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Fri, 19 Apr 2024 12:13:48 +0800 Subject: [PATCH 1210/1868] drm/amdkcl: Fix missing underline of CONFIG_DMABUF_MOVENOTIFY Signed-off-by: Leslie Shi Reviewed-by: Ma Jun --- drivers/gpu/drm/amd/dkms/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 0e41d5633a6f9..1586454860bc7 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -192,7 +192,7 @@ export CONFIG_DRM_AMD_DC_HDCP=y subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_HDCP ifeq (y,$(CONFIG_PCI_P2PDMA)) - ifeq (y,$(CONFIG_DMABUF_MOVENOTIFY)) + ifeq (y,$(CONFIG_DMABUF_MOVE_NOTIFY)) export CONFIG_HSA_AMD_P2P=y subdir-ccflags-y += -DCONFIG_HSA_AMD_P2P endif From 45d20f69e055fcba6d5e6fe0d3ee0d5c9dd4b9d7 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 22 Apr 2024 10:53:24 +0800 Subject: [PATCH 1211/1868] drm/amdkcl: fake macro AMD_FMT_MOD_TILE_VER_GFX12 and AMD_FMT_MOD_TILE_GFX12_64K_2D It's caused by 2de480179f2a5cbb54e970ba1312f3aac246f33a "drm/amd/display: Add gfx12 modifiers" Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- include/kcl/kcl_drm_fourcc.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/kcl/kcl_drm_fourcc.h b/include/kcl/kcl_drm_fourcc.h index f28a041070a75..9b1a99ec6d52b 100644 --- a/include/kcl/kcl_drm_fourcc.h +++ b/include/kcl/kcl_drm_fourcc.h @@ -100,6 +100,11 @@ #define AMD_FMT_MOD_TILE_VER_GFX11 4 #endif +#ifndef AMD_FMT_MOD_TILE_VER_GFX12 +#define AMD_FMT_MOD_TILE_VER_GFX12 5 +#define AMD_FMT_MOD_TILE_GFX12_64K_2D 3 +#endif + #ifndef AMD_FMT_MOD_TILE_GFX11_256K_R_X #define AMD_FMT_MOD_TILE_GFX11_256K_R_X 31 #endif From f5e25a23a4464fc868ebb86e8de642488406cf2b Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 22 Apr 2024 14:34:46 +0800 Subject: [PATCH 1212/1868] drm/amdkcl: fix __devm_drm_dev_alloc in amdxcp/backport Signed-off-by: Flora Cui Reviewed-by: Bob Zhou --- .../gpu/drm/amd/amdxcp/backport/kcl_drm_drv.c | 33 ++----------------- 1 file changed, 3 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/amd/amdxcp/backport/kcl_drm_drv.c b/drivers/gpu/drm/amd/amdxcp/backport/kcl_drm_drv.c index 4b2d043f4665a..cc1da02e06e84 100644 --- a/drivers/gpu/drm/amd/amdxcp/backport/kcl_drm_drv.c +++ b/drivers/gpu/drm/amd/amdxcp/backport/kcl_drm_drv.c @@ -30,33 +30,7 @@ #include #ifdef AMDKCL_DEVM_DRM_DEV_ALLOC -static void devm_drm_dev_init_release(void *data) -{ - drm_dev_put(data); - -#ifndef HAVE_DRM_DRM_MANAGED_H - if(data){ - struct drm_device *dev = data; - if(!kref_read(&dev->ref)) - kfree(dev->dev_private); - } -#endif -} /* Copied from v5.7-rc1-343-gb0b5849e0cc0 drivers/gpu/drm/drm_drv.c and modified for KCL */ -static int devm_drm_dev_init(struct device *parent, - struct drm_device *dev, - const struct drm_driver *driver) -{ - int ret; - - ret = drm_dev_init(dev, driver, parent); - if (ret) - return ret; - - return devm_add_action_or_reset(parent, - devm_drm_dev_init_release, dev); -} - void *__devm_drm_dev_alloc(struct device *parent, struct drm_driver *driver, size_t size, size_t offset) { @@ -69,16 +43,15 @@ void *__devm_drm_dev_alloc(struct device *parent, struct drm_driver *driver, return ERR_PTR(-ENOMEM); drm = container + offset; - ret = devm_drm_dev_init(parent, drm, driver); + ret = drm_dev_init(drm, driver, parent); if (ret) { - kfree(container); + drm_dev_put(drm); return ERR_PTR(ret); } #ifdef HAVE_DRM_DRM_MANAGED_H drmm_add_final_kfree(drm, container); -#else - drm->dev_private = container; #endif + drm->dev_private = container; return container; } From c6f8925c5bcde7d9f001c7c64596a177b8721088 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 22 Apr 2024 14:48:35 +0800 Subject: [PATCH 1213/1868] drm/amdkcl: seperate check for DRM_MODE_COLORIMETRY_RGB_WIDE_FIXED as they're introduced in another commit 45cf0e91df8c("drm: Add DisplayPort colorspace property creation function") Signed-off-by: Flora Cui Reviewed-by: Jun Ma --- include/kcl/kcl_drm_connector.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/include/kcl/kcl_drm_connector.h b/include/kcl/kcl_drm_connector.h index c0e2b217ddcc5..c0a969519be7f 100644 --- a/include/kcl/kcl_drm_connector.h +++ b/include/kcl/kcl_drm_connector.h @@ -156,10 +156,14 @@ int _kcl_drm_mode_create_dp_colorspace_property(struct drm_connector *connector, /* Additional Colorimetry extension added as part of CTA 861.G */ #define DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65 11 #define DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER 12 +#endif /* DRM_MODE_COLORIMETRY_DEFAULT */ + +/* v5.3-rc1-676-g45cf0e91df8c */ +#ifndef DRM_MODE_COLORIMETRY_RGB_WIDE_FIXED /* Additional Colorimetry Options added for DP 1.4a VSC Colorimetry Format */ #define DRM_MODE_COLORIMETRY_RGB_WIDE_FIXED 13 #define DRM_MODE_COLORIMETRY_RGB_WIDE_FLOAT 14 #define DRM_MODE_COLORIMETRY_BT601_YCC 15 -#endif /* DRM_MODE_COLORIMETRY_DEFAULT */ +#endif #endif /* AMDKCL_DRM_CONNECTOR_H */ From ecab72b04166533a103529e2159f0dfd14bb466d Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Mon, 22 Apr 2024 15:07:10 +0800 Subject: [PATCH 1214/1868] drm/amdkcl: rename kcl copy drm_mode_create_colorspace_property to avoid conflict with the drm counterpart Signed-off-by: Flora Cui Reviewed-by: Jun Ma --- drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c index 559b2610f2966..7616f113d4afb 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_connector.c @@ -164,7 +164,7 @@ static const u32 dp_colorspaces = BIT(DRM_MODE_COLORIMETRY_BT2020_CYCC) | BIT(DRM_MODE_COLORIMETRY_BT2020_YCC); -static int drm_mode_create_colorspace_property(struct drm_connector *connector, +static int _kcl_drm_mode_create_colorspace_property(struct drm_connector *connector, u32 supported_colorspaces) { struct drm_device *dev = connector->dev; @@ -232,7 +232,7 @@ int _kcl_drm_mode_create_hdmi_colorspace_property(struct drm_connector *connecto else colorspaces = hdmi_colorspaces; - return drm_mode_create_colorspace_property(connector, colorspaces); + return _kcl_drm_mode_create_colorspace_property(connector, colorspaces); } EXPORT_SYMBOL(_kcl_drm_mode_create_hdmi_colorspace_property); #endif @@ -248,7 +248,7 @@ int _kcl_drm_mode_create_dp_colorspace_property(struct drm_connector *connector, else colorspaces = dp_colorspaces; - return drm_mode_create_colorspace_property(connector, colorspaces); + return _kcl_drm_mode_create_colorspace_property(connector, colorspaces); } EXPORT_SYMBOL(_kcl_drm_mode_create_dp_colorspace_property); #endif \ No newline at end of file From b72e646d7e55a8309642483601b476a536caef9b Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 26 Apr 2024 13:57:08 +0800 Subject: [PATCH 1215/1868] drm/amdkcl: Support fdinfo interface for older drm version Fake a drm_show_fdinfo for old kernel version which should print gpu memory stat. Signed-off-by: Philip Yang Signed-off-by: Asher Song Reviewed-by: Philip Yang --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/backport/Makefile | 2 +- .../gpu/drm/amd/backport/include}/kcl/kcl_drm_file.h | 4 ++-- drivers/gpu/drm/amd/{amdkcl => backport}/kcl_drm_file.c | 4 +++- 4 files changed, 7 insertions(+), 5 deletions(-) rename {include => drivers/gpu/drm/amd/backport/include}/kcl/kcl_drm_file.h (60%) rename drivers/gpu/drm/amd/{amdkcl => backport}/kcl_drm_file.c (97%) diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 82abb89903b8c..90398c82f9c30 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -14,7 +14,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_fs_read_write.o kcl_drm_aperture.o \ kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o \ kcl_mce_amd.o kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o kcl_mm_slab.o \ - kcl_irqdesc.o kcl_drm_suballoc.o kcl_drm_file.o kcl_drm_exec.o kcl_drm_dp_helper.o kcl_drm_prime.o + kcl_irqdesc.o kcl_drm_suballoc.o kcl_drm_exec.o kcl_drm_dp_helper.o kcl_drm_prime.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/backport/Makefile b/drivers/gpu/drm/amd/backport/Makefile index f5b5d3b9a2d33..8bc3adedebc57 100644 --- a/drivers/gpu/drm/amd/backport/Makefile +++ b/drivers/gpu/drm/amd/backport/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: MIT BACKPORT_OBJS := kcl_drm_drv.o kcl_drm_gem_ttm_helper.o \ - kcl_drm_gem.o + kcl_drm_gem.o kcl_drm_file.o amdgpu-y += $(addprefix ../backport/,$(BACKPORT_OBJS)) diff --git a/include/kcl/kcl_drm_file.h b/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_file.h similarity index 60% rename from include/kcl/kcl_drm_file.h rename to drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_file.h index d23292e37dc25..a067b59578b6c 100644 --- a/include/kcl/kcl_drm_file.h +++ b/drivers/gpu/drm/amd/backport/include/kcl/kcl_drm_file.h @@ -1,5 +1,5 @@ -#ifndef __AMDKCL_KCL_DRM_DRV_H__ -#define __AMDKCL_KCL_DRM_DRV_H__ +#ifndef __AMDGPU_BACKPORT_KCL_DRM_DRV_H__ +#define __AMDGPU_BACKPORT_KCL_DRM_DRV_H__ #include #ifndef HAVE_DRM_SHOW_FDINFO diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_file.c b/drivers/gpu/drm/amd/backport/kcl_drm_file.c similarity index 97% rename from drivers/gpu/drm/amd/amdkcl/kcl_drm_file.c rename to drivers/gpu/drm/amd/backport/kcl_drm_file.c index 7ddc32cafc5b7..5bc74f05d555e 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_drm_file.c +++ b/drivers/gpu/drm/amd/backport/kcl_drm_file.c @@ -37,6 +37,7 @@ #include #include #include +#include "amdgpu_fdinfo.h" #ifndef HAVE_DRM_SHOW_FDINFO /** * drm_show_fdinfo - helper for drm file fops @@ -63,6 +64,7 @@ void drm_show_fdinfo(struct seq_file *m, struct file *f) pci_domain_nr(pdev->bus), pdev->bus->number, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); } + + amdgpu_show_fdinfo(&p, file); } -EXPORT_SYMBOL(drm_show_fdinfo); #endif From cd382a9cdcb916ef689c15a6488e8a35556484dd Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 26 Apr 2024 11:18:20 +0800 Subject: [PATCH 1216/1868] drm/amdkcl: Test whether radix_tree_iter_delete() is available It's caused by e760d0b2a1c1613f1a0e2ecf77ba6023d4f7bcdf "drm/amdgpu: prepare for logging ecc errors" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 6 ++++++ drivers/gpu/drm/amd/dkms/config/config.h | 7 +++++-- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../drm/amd/dkms/m4/radix-tree-iter-delete.m4 | 16 ++++++++++++++++ 4 files changed, 28 insertions(+), 2 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/radix-tree-iter-delete.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 501fbd2de31ff..b26dee57d077a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -2881,6 +2881,7 @@ static int amdgpu_ras_get_poison_req(struct amdgpu_device *adev, return kfifo_get(&con->poison_fifo, poison_msg); } +#ifdef HAVE_RADIX_TREE_ITER_DELETE static void amdgpu_ras_ecc_log_init(struct ras_ecc_log_info *ecc_log) { mutex_init(&ecc_log->lock); @@ -2909,6 +2910,7 @@ static void amdgpu_ras_ecc_log_fini(struct ras_ecc_log_info *ecc_log) ecc_log->de_queried_count = 0; ecc_log->prev_de_queried_count = 0; } +#endif static bool amdgpu_ras_schedule_retirement_dwork(struct amdgpu_ras *con, uint32_t delayed_ms) @@ -3226,7 +3228,9 @@ int amdgpu_ras_recovery_init(struct amdgpu_device *adev) } INIT_DELAYED_WORK(&con->page_retirement_dwork, amdgpu_ras_do_page_retirement); +#ifdef HAVE_RADIX_TREE_ITER_DELETE amdgpu_ras_ecc_log_init(&con->umc_ecc_log); +#endif #ifdef CONFIG_X86_MCE_AMD #ifdef HAVE_SMCA_UMC_V2 if ((adev->asic_type == CHIP_ALDEBARAN) && @@ -3285,7 +3289,9 @@ static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev) cancel_delayed_work_sync(&con->page_retirement_dwork); +#ifdef HAVE_RADIX_TREE_ITER_DELETE amdgpu_ras_ecc_log_fini(&con->umc_ecc_log); +#endif mutex_lock(&con->recovery_lock); con->eh_data = NULL; diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 233a1d736de14..2ef01185df612 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -902,6 +902,9 @@ /* queue_work_node() is available */ #define HAVE_QUEUE_WORK_NODE 1 +/* radix_tree_iter_delete() is available */ +#define HAVE_RADIX_TREE_ITER_DELETE 1 + /* rb_add_cached is available */ #define HAVE_RB_ADD_CACHED 1 @@ -1069,7 +1072,7 @@ #define PACKAGE_NAME "amdgpu-dkms" /* Define to the full name and version of this package. */ -#define PACKAGE_STRING "amdgpu-dkms 6.7.0" +#define PACKAGE_STRING "amdgpu-dkms 6.8.0" /* Define to the one symbol short name of this package. */ #define PACKAGE_TARNAME "amdgpu-dkms" @@ -1078,7 +1081,7 @@ #define PACKAGE_URL "" /* Define to the version of this package. */ -#define PACKAGE_VERSION "6.7.0" +#define PACKAGE_VERSION "6.8.0" #include "config-amd-chips.h" diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 4c3141f28cc1a..8eb7b2dd4c124 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -220,6 +220,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_LINUX_DEVICE_CLASS AC_AMDGPU_KVREALLOC AC_AMDGPU_DMA_BUF_IS_DYNAMIC + AC_AMDGPU_RADIX_TREE_ITER_DELETE AC_AMDGPU_DRM_CLIENT_REGISTER AC_AMDGPU_DRM_DRIVER_GEM_PRIME_MMAP AC_AMDGPU_DRM_GEM_PRIME_HANDLE_TO_FD diff --git a/drivers/gpu/drm/amd/dkms/m4/radix-tree-iter-delete.m4 b/drivers/gpu/drm/amd/dkms/m4/radix-tree-iter-delete.m4 new file mode 100644 index 0000000000000..ed747fab8a781 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/radix-tree-iter-delete.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v4.10-rc5-380-g0ac398ef391b +dnl # radix-tree: Add radix_tree_iter_delete +dnl # +AC_DEFUN([AC_AMDGPU_RADIX_TREE_ITER_DELETE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + radix_tree_iter_delete(NULL,NULL,NULL); + ], [ + AC_DEFINE(HAVE_RADIX_TREE_ITER_DELETE, 1, + [radix_tree_iter_delete() is available]) + ]) + ]) +]) From a464b56cada633efacb07a0987e1be501d35341f Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 26 Apr 2024 15:03:08 +0800 Subject: [PATCH 1217/1868] drm/amdkcl: Test wehther kfifo_put() use non pointer parameter It's caused by 8a61ce30f4b3c9b100c0e74fb082a23da7002c74 "drm/amdgpu: add message fifo to handle RAS poison events" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 6 ++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c | 4 ++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/amd/dkms/m4/kfifo_put.m4 | 20 ++++++++++++++++++++ 5 files changed, 34 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/kfifo_put.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index b26dee57d077a..047da1bb1e5e1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -2184,6 +2184,7 @@ static void amdgpu_ras_interrupt_poison_creation_handler(struct ras_manager *obj event_id = amdgpu_ras_acquire_event_id(adev, type); RAS_EVENT_LOG(adev, event_id, "Poison is created\n"); +#ifdef HAVE_KFIFO_PUT_NON_POINTER if (amdgpu_ip_version(obj->adev, UMC_HWIP, 0) >= IP_VERSION(12, 0, 0)) { struct amdgpu_ras *con = amdgpu_ras_get_context(obj->adev); @@ -2192,6 +2193,7 @@ static void amdgpu_ras_interrupt_poison_creation_handler(struct ras_manager *obj wake_up(&con->page_retirement_wq); } +#endif } static void amdgpu_ras_interrupt_umc_handler(struct ras_manager *obj, @@ -2849,6 +2851,7 @@ static void amdgpu_ras_validate_threshold(struct amdgpu_device *adev, } } +#ifdef HAVE_KFIFO_PUT_NON_POINTER int amdgpu_ras_put_poison_req(struct amdgpu_device *adev, enum amdgpu_ras_block block, uint16_t pasid, pasid_notify pasid_fn, void *data, uint32_t reset) @@ -2880,6 +2883,7 @@ static int amdgpu_ras_get_poison_req(struct amdgpu_device *adev, return kfifo_get(&con->poison_fifo, poison_msg); } +#endif #ifdef HAVE_RADIX_TREE_ITER_DELETE static void amdgpu_ras_ecc_log_init(struct ras_ecc_log_info *ecc_log) @@ -3105,6 +3109,7 @@ static int amdgpu_ras_page_retirement_thread(void *param) } } while (atomic_read(&con->poison_creation_count)); +#ifdef HAVE_KFIFO_PUT_NON_POINTER if (ret != -EIO) { msg_count = kfifo_len(&con->poison_fifo); if (msg_count) { @@ -3147,6 +3152,7 @@ static int amdgpu_ras_page_retirement_thread(void *param) /* Wake up work to save bad pages to eeprom */ schedule_delayed_work(&con->page_retirement_dwork, 0); } +#endif } return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c index bb7b9b2eaac1a..9e70a7b3aa64f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c @@ -247,12 +247,16 @@ int amdgpu_umc_pasid_poison_handler(struct amdgpu_device *adev, struct amdgpu_ras *con = amdgpu_ras_get_context(adev); int ret; +#ifdef HAVE_KFIFO_PUT_NON_POINTER ret = amdgpu_ras_put_poison_req(adev, block, pasid, pasid_fn, data, reset); if (!ret) { +#endif atomic_inc(&con->page_retirement_req_cnt); wake_up(&con->page_retirement_wq); +#ifdef HAVE_KFIFO_PUT_NON_POINTER } +#endif } } else { if (adev->virt.ops && adev->virt.ops->ras_poison_handler) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 2ef01185df612..808cd37a40668 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -695,6 +695,9 @@ /* kernel_write() take arg type of position as pointer */ #define HAVE_KERNEL_WRITE_PPOS 1 +/* kfifo_put() have non pointer parameter */ +#define HAVE_KFIFO_PUT_NON_POINTER 1 + /* kmalloc_size_roundup is available */ #define HAVE_KMALLOC_SIZE_ROUNDUP 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 8eb7b2dd4c124..13d9829605c14 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -221,6 +221,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_KVREALLOC AC_AMDGPU_DMA_BUF_IS_DYNAMIC AC_AMDGPU_RADIX_TREE_ITER_DELETE + AC_AMDGPU_KFIFO_PUT AC_AMDGPU_DRM_CLIENT_REGISTER AC_AMDGPU_DRM_DRIVER_GEM_PRIME_MMAP AC_AMDGPU_DRM_GEM_PRIME_HANDLE_TO_FD diff --git a/drivers/gpu/drm/amd/dkms/m4/kfifo_put.m4 b/drivers/gpu/drm/amd/dkms/m4/kfifo_put.m4 new file mode 100644 index 0000000000000..6668ba3281246 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/kfifo_put.m4 @@ -0,0 +1,20 @@ +dnl # +dnl # v3.12-8403-g498d319bb512 +dnl # kfifo API type safety +dnl # +AC_DEFUN([AC_AMDGPU_KFIFO_PUT], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + static DEFINE_KFIFO(fifo, int, 2); + kfifo_put(&fifo, 0); + ],[ + AC_DEFINE(HAVE_KFIFO_PUT_NON_POINTER, 1, + [kfifo_put() have non pointer parameter]) + ]) + ]) +]) + + + From f305b237fa3b97e1e4c337b4cf2f34f675c254a5 Mon Sep 17 00:00:00 2001 From: Jesse Zhang Date: Mon, 6 May 2024 14:40:21 +0800 Subject: [PATCH 1218/1868] drm/amd/pm: fix the uninitialized scalar variable warning Fix warning for using uninitialized values sclk_mask, mclk_mask and soc_mask. v2:Set default variable to UMD PSTATE(Tim Huang) Signed-off-by: Jesse Zhang Acked-by: Yang Wang Signed-off-by: Jesse Zhang --- .../gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c | 29 ++++++++++++++++--- 1 file changed, 25 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c index cc0504b063fa3..60939e2e732a3 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c @@ -833,10 +833,20 @@ static int renoir_force_clk_levels(struct smu_context *smu, ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_max_level, &max_freq); if (ret) return ret; - ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxSocclkByFreq, max_freq, NULL); + /* = 0: min_freq + * = 1: UMD_PSTATE_CLK + * >= 2: max_freq + */ + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxSocclkByFreq, + soft_max_level == 0 ? min_freq : + soft_max_level == 1 ? RENOIR_UMD_PSTATE_SOCCLK : max_freq, + NULL); if (ret) return ret; - ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinSocclkByFreq, min_freq, NULL); + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinSocclkByFreq, + soft_min_level == 0 ? min_freq : + soft_min_level == 1 ? RENOIR_UMD_PSTATE_SOCCLK : max_freq, + NULL); if (ret) return ret; break; @@ -848,10 +858,21 @@ static int renoir_force_clk_levels(struct smu_context *smu, ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_max_level, &max_freq); if (ret) return ret; - ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxFclkByFreq, max_freq, NULL); + /* mclk levels are in reverse order + * = 0: max_freq + * = 1: UMD_PSTATE_CLK + * >= 2: min_freq + */ + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxFclkByFreq, + soft_max_level >= 2 ? min_freq : + soft_max_level == 1 ? RENOIR_UMD_PSTATE_FCLK : max_freq, + NULL); if (ret) return ret; - ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinFclkByFreq, min_freq, NULL); + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinFclkByFreq, + soft_min_level >= 2 ? min_freq : + soft_min_level == 1 ? RENOIR_UMD_PSTATE_SOCCLK : max_freq, + NULL); if (ret) return ret; break; From 1e2cec6be6e2e75e1e749c5b953fa8a08d4a9b3d Mon Sep 17 00:00:00 2001 From: Jesse Zhang Date: Tue, 7 May 2024 13:17:32 +0800 Subject: [PATCH 1219/1868] drm/amd/pm: revert "drm/amd/pm: fix the uninitialized scalar variable warning" Revert commit 576bffd10d01 ("drm/amd/pm: fix the uninitialized scalar variable warning") and will update new patch. Signed-off-by: Jesse Zhang Reviewed-by: Tim Huang Signed-off-by: Jesse Zhang --- .../gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c | 29 +++---------------- 1 file changed, 4 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c index 60939e2e732a3..cc0504b063fa3 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu12/renoir_ppt.c @@ -833,20 +833,10 @@ static int renoir_force_clk_levels(struct smu_context *smu, ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_max_level, &max_freq); if (ret) return ret; - /* = 0: min_freq - * = 1: UMD_PSTATE_CLK - * >= 2: max_freq - */ - ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxSocclkByFreq, - soft_max_level == 0 ? min_freq : - soft_max_level == 1 ? RENOIR_UMD_PSTATE_SOCCLK : max_freq, - NULL); + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxSocclkByFreq, max_freq, NULL); if (ret) return ret; - ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinSocclkByFreq, - soft_min_level == 0 ? min_freq : - soft_min_level == 1 ? RENOIR_UMD_PSTATE_SOCCLK : max_freq, - NULL); + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinSocclkByFreq, min_freq, NULL); if (ret) return ret; break; @@ -858,21 +848,10 @@ static int renoir_force_clk_levels(struct smu_context *smu, ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_max_level, &max_freq); if (ret) return ret; - /* mclk levels are in reverse order - * = 0: max_freq - * = 1: UMD_PSTATE_CLK - * >= 2: min_freq - */ - ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxFclkByFreq, - soft_max_level >= 2 ? min_freq : - soft_max_level == 1 ? RENOIR_UMD_PSTATE_FCLK : max_freq, - NULL); + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxFclkByFreq, max_freq, NULL); if (ret) return ret; - ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinFclkByFreq, - soft_min_level >= 2 ? min_freq : - soft_min_level == 1 ? RENOIR_UMD_PSTATE_SOCCLK : max_freq, - NULL); + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinFclkByFreq, min_freq, NULL); if (ret) return ret; break; From d797207e709437c164c98fe951dcc2746eee3a8b Mon Sep 17 00:00:00 2001 From: Philip Yang Date: Fri, 5 Apr 2024 17:59:53 -0400 Subject: [PATCH 1220/1868] drm/amdgpu: Skip dma map resource for null RDMA device To test RDMA using dummy driver on the system without NIC/RDMA device, the get/put dma pages pass in null device pointer, skip the dma map/unmap resource and sg table to avoid null pointer access. Signed-off-by: Philip Yang Reviewed-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c | 33 +++++++++++--------- 1 file changed, 19 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c index 52ffa82db94df..e53d3a1c33c37 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c @@ -721,12 +721,15 @@ int amdgpu_vram_mgr_alloc_sgt(struct amdgpu_device *adev, unsigned long size = min(cursor.size, AMDGPU_MAX_SG_SEGMENT_SIZE); dma_addr_t addr; - addr = dma_map_resource(dev, phys, size, dir, - DMA_ATTR_SKIP_CPU_SYNC); - r = dma_mapping_error(dev, addr); - if (r) - goto error_unmap; - + if (dev) { + addr = dma_map_resource(dev, phys, size, dir, + DMA_ATTR_SKIP_CPU_SYNC); + r = dma_mapping_error(dev, addr); + if (r) + goto error_unmap; + } else { + addr = phys; + } sg_set_page(sg, NULL, size, 0); sg_dma_address(sg) = addr; sg_dma_len(sg) = size; @@ -740,10 +743,10 @@ int amdgpu_vram_mgr_alloc_sgt(struct amdgpu_device *adev, for_each_sgtable_sg((*sgt), sg, i) { if (!sg->length) continue; - - dma_unmap_resource(dev, sg->dma_address, - sg->length, dir, - DMA_ATTR_SKIP_CPU_SYNC); + if (dev) + dma_unmap_resource(dev, sg->dma_address, + sg->length, dir, + DMA_ATTR_SKIP_CPU_SYNC); } sg_free_table(*sgt); @@ -768,10 +771,12 @@ void amdgpu_vram_mgr_free_sgt(struct device *dev, struct scatterlist *sg; int i; - for_each_sgtable_sg(sgt, sg, i) - dma_unmap_resource(dev, sg->dma_address, - sg->length, dir, - DMA_ATTR_SKIP_CPU_SYNC); + if (dev) { + for_each_sgtable_sg(sgt, sg, i) + dma_unmap_resource(dev, sg->dma_address, + sg->length, dir, + DMA_ATTR_SKIP_CPU_SYNC); + } sg_free_table(sgt); kfree(sgt); } From a2100dbe7c3decfb4401ba8a5ec063aab2dd67da Mon Sep 17 00:00:00 2001 From: Philip Yang Date: Fri, 5 Apr 2024 18:54:51 -0400 Subject: [PATCH 1221/1868] drm/amdkfd: Allow peer direct dma map with null RDMA device To test KFD peer direct RDMA functions on system without NIC/RDMA device. Add dynamic debug message to dump sg table segments address and size, to help debug contiguous VRAM peer direct RDMA. Signed-off-by: Philip Yang Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 11 +++++++---- drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c | 13 ++++++++++--- 2 files changed, 17 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 4faae9595da97..004bef6645e38 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -2649,9 +2649,11 @@ int amdgpu_amdkfd_gpuvm_get_sg_table(struct amdgpu_device *adev, cur_page++; } - ret = dma_map_sgtable(dma_dev, sg, dir, DMA_ATTR_SKIP_CPU_SYNC); - if (ret) - goto out_of_range; + if (dma_dev) { + ret = dma_map_sgtable(dma_dev, sg, dir, DMA_ATTR_SKIP_CPU_SYNC); + if (ret) + goto out_of_range; + } *ret_sg = sg; return 0; @@ -2675,7 +2677,8 @@ void amdgpu_amdkfd_gpuvm_put_sg_table(struct amdgpu_bo *bo, } /* Unmap system memory */ - dma_unmap_sgtable(dma_dev, sgt, dir, DMA_ATTR_SKIP_CPU_SYNC); + if (dma_dev) + dma_unmap_sgtable(dma_dev, sgt, dir, DMA_ATTR_SKIP_CPU_SYNC); sg_free_table(sgt); kfree(sgt); } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c b/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c index 50541b1dac44a..637a6ceaffefe 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c @@ -281,7 +281,9 @@ static int amd_dma_map(struct sg_table *sg_head, void *client_context, struct device *dma_device, int dmasync, int *nmap) { struct sg_table *sg_table_tmp; + struct scatterlist *sg; int ret; + int i; /* * NOTE/TODO: @@ -308,7 +310,7 @@ static int amd_dma_map(struct sg_table *sg_head, void *client_context, pr_debug("Client context: 0x%p, sg_head: 0x%p\n", client_context, sg_head); - if (!mem_context || !mem_context->bo || !mem_context->dev) { + if (!mem_context || !mem_context->bo) { pr_warn("Invalid client context"); return -EINVAL; } @@ -328,6 +330,11 @@ static int amd_dma_map(struct sg_table *sg_head, void *client_context, return ret; } + pr_debug("size 0x%llx nents %d\n", mem_context->size, sg_table_tmp->nents); + for_each_sgtable_sg(sg_table_tmp, sg, i) + pr_debug("segment_%d dma_address 0x%llx length 0x%x dma_length 0x%x\n", + i, sg->dma_address, sg->length, sg->dma_length); + /* Maintain a copy of the handle to sg_table */ mem_context->pages = sg_table_tmp; mem_context->dma_dev = dma_device; @@ -335,7 +342,7 @@ static int amd_dma_map(struct sg_table *sg_head, void *client_context, /* Copy information about previosly allocated sg_table */ *sg_head = *mem_context->pages; - /* Return number of pages */ + /* Return number of sg table segments */ *nmap = mem_context->pages->nents; return ret; @@ -350,7 +357,7 @@ static int amd_dma_unmap(struct sg_table *sg_head, void *client_context, pr_debug("Client context: 0x%p, sg_table: 0x%p\n", client_context, sg_head); - if (!mem_context || !mem_context->bo || !mem_context->dma_dev) { + if (!mem_context || !mem_context->bo) { pr_warn("Invalid client context"); return -EINVAL; } From b73f72c31c1555878bd4502ece69c4240b0d4d36 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 15 May 2024 11:02:55 +0800 Subject: [PATCH 1222/1868] drm/amdkcl: wrap code under macro HAVE_HDR_SINK_METADATA It's caused by e559239eabe628d65d3fbe184890f73477fca0f9 "drm/amd/display: Don't register panel_power_savings on OLED panels" Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 88d422b61b556..b186f01a514a4 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -7047,6 +7047,7 @@ amdgpu_dm_should_create_sysfs(struct amdgpu_dm_connector *amdgpu_dm_connector) if (amdgpu_dm_connector->base.connector_type != DRM_MODE_CONNECTOR_eDP) return false; +#ifdef HAVE_HDR_SINK_METADATA /* check for OLED panels */ if (amdgpu_dm_connector->bl_idx >= 0) { struct drm_device *drm = amdgpu_dm_connector->base.dev; @@ -7057,6 +7058,7 @@ amdgpu_dm_should_create_sysfs(struct amdgpu_dm_connector *amdgpu_dm_connector) if (caps->aux_support) return false; } +#endif return true; } From 9354e276946394f8d48a71b2e8deee77cd83e067 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Thu, 9 May 2024 15:52:44 -0400 Subject: [PATCH 1223/1868] drm/amdkfd: clear soft lockup issue with host trap When user sets an interval less than what driver can handle, soft lockup arises. To clear this soft lockup with adding a schedule before trigger a new host trap. [ 2896.405488] watchdog: BUG: soft lockup - CPU#22 stuck for 26s! [pcs_130:38057] [ 2896.405676] Supported: No, Unsupported modules are loaded [ 2896.405678] CPU: 22 PID: 38057 Comm: pcs_130 Kdump: loaded Tainted: G OE X N 5.14.21-150500.55.59-default #1 SLE15-SP5 3a8569df5696e57cdcb648c7e890af33bdc23f85 [ 2896.405683] Hardware name: Dell Inc. PowerEdge R7525/0590KW, BIOS 2.6.6 01/13/2022 [ 2896.405684] RIP: 0010:amdgpu_device_rreg.part.42+0x57/0x1d0 [amdgpu] [ 2896.405978] Code: 6f 4c 9c 00 4c 8b 83 b8 08 00 00 4d 01 e0 85 c9 74 15 65 48 8b 04 25 00 1c 02 00 3b 88 b8 09 00 00 0f 85 52 01 00 00 41 8b 28 <8b> 05 43 4c 9c 00 85 c0 74 56 65 48 8b 14 25 00 1c 02 00 39 82 b8 [ 2896.405981] RSP: 0018:ffffb7a6ecc33e30 EFLAGS: 00000246 [ 2896.405984] RAX: ffff949389f18000 RBX: ffff94d3d1100000 RCX: 00000000000094a9 [ 2896.405985] RDX: 0000000000000000 RSI: 0000000000002376 RDI: ffff94d3d1100000 [ 2896.405987] RBP: 0000000000000000 R08: ffffb7a6e2b88dd8 R09: ffff94d30e3b1f14 [ 2896.405989] R10: ffffb7a6c0427d88 R11: ffffb7a6ecc33c80 R12: 0000000000008dd8 [ 2896.405990] R13: 0000000000002376 R14: ffff94d30e3b1f14 R15: ffff94d3d1100000 [ 2896.405992] FS: 0000000000000000(0000) GS:ffff9512ff580000(0000) knlGS:0000000000000000 [ 2896.405994] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 2896.405996] CR2: 00007f5b2b732000 CR3: 0000006a1ee10003 CR4: 0000000000770ee0 [ 2896.405998] PKRU: 55555554 [ 2896.405999] Call Trace: [ 2896.406004] [ 2896.406007] kgd_gfx_v9_trigger_pc_sample_trap+0x1d6/0x4f0 [amdgpu 75bb93fc913928fc00917a1c71d5c2dca258175d] Signed-off-by: James Zhu Tested-by: Vladimir Indic Reviewed-by: Vladimir Indic --- drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index 4572ac447ee4b..2a9a7a9bb6e6d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -91,12 +91,13 @@ static int kfd_pc_sample_thread(void *param) wait_time = ktime_sub(next_trap_time, ktime_get_raw()); wait_ns = ktime_to_ns(wait_time); wait_us = ktime_to_us(wait_time); - if (wait_ns >= 10000) + if (wait_ns >= 10000) { usleep_range(wait_us - 10, wait_us); - else if (wait_ns > 0) + } else { schedule(); - else - need_wait = false; + if (wait_ns <= 0) + need_wait = false; + } } } From 776141b0484a9f50d6b52ffdbe326cf36e827950 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 22 Aug 2024 15:45:53 +0800 Subject: [PATCH 1224/1868] drm/amdkfd: [WA] disable SQ core clock gate When host trap pc sampling is activted. Since Command bus from SPI/SQG to SQ may have some conflict with SQ internal clock gating, when we have many host trap command it will trigger qcm fence timeout. Signed-off-by: James Zhu Tested-by: Vladimir Indic Reviewed-by: Vladimir Indic Signed-off-by: Asher Song --- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c | 1 + .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c | 3 ++- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 16 ++++++++++++++++ .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h | 3 +++ drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 11 +++++++++-- drivers/gpu/drm/amd/include/kgd_kfd_interface.h | 3 +++ 6 files changed, 34 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c index 0fdd76692e3a6..d3fb05521580e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.c @@ -206,4 +206,5 @@ const struct kfd2kgd_calls aldebaran_kfd2kgd = { .hqd_get_pq_addr = kgd_gfx_v9_hqd_get_pq_addr, .hqd_reset = kgd_gfx_v9_hqd_reset, .trigger_pc_sample_trap = kgd_aldebaran_trigger_pc_sample_trap, + .override_core_cg = kgd_gfx_v9_override_core_cg, }; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c index 2f2c71f5cb283..b9bf273289dd5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c @@ -433,5 +433,6 @@ const struct kfd2kgd_calls arcturus_kfd2kgd = { .program_trap_handler_settings = kgd_gfx_v9_program_trap_handler_settings, .hqd_get_pq_addr = kgd_gfx_v9_hqd_get_pq_addr, .hqd_reset = kgd_gfx_v9_hqd_reset, - .trigger_pc_sample_trap = kgd_arcturus_trigger_pc_sample_trap + .trigger_pc_sample_trap = kgd_arcturus_trigger_pc_sample_trap, + .override_core_cg = kgd_gfx_v9_override_core_cg }; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c index 0b63b79a8d988..610cbcfbe9e0d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c @@ -1273,6 +1273,22 @@ static uint32_t kgd_aldebaran_get_hosttrap_status(struct amdgpu_device *adev, return sq_hosttrap_status; } +void kgd_gfx_v9_override_core_cg(struct amdgpu_device *adev, + uint32_t value, + uint32_t inst) +{ + uint32_t clk_cntl; + + mutex_lock(&adev->grbm_idx_mutex); + amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, inst); + + RREG32_SOC15(GC, GET_INST(GC, inst), mmCGTT_SQ_CLK_CTRL); + clk_cntl = REG_SET_FIELD(clk_cntl, CGTT_SQ_CLK_CTRL, CORE_OVERRIDE, value); + WREG32_SOC15(GC, GET_INST(GC, inst), mmCGTT_SQ_CLK_CTRL, clk_cntl); + + mutex_unlock(&adev->grbm_idx_mutex); +} + uint32_t kgd_gfx_v9_trigger_pc_sample_trap(struct amdgpu_device *adev, uint32_t vmid, uint32_t max_wave_slot, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h index 41eae07e7c195..d2eba1a137407 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h @@ -118,3 +118,6 @@ uint32_t kgd_gfx_v9_trigger_pc_sample_trap(struct amdgpu_device *adev, uint32_t *target_wave_slot, enum kfd_ioctl_pc_sample_method method, uint32_t inst); +void kgd_gfx_v9_override_core_cg(struct amdgpu_device *adev, + uint32_t value, + uint32_t inst); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index 2a9a7a9bb6e6d..72042277cc2b8 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -47,6 +47,7 @@ static int kfd_pc_sample_thread(void *param) uint32_t timeout = 0; ktime_t next_trap_time; bool need_wait; + uint32_t inst; mutex_lock(&node->pcs_data.mutex); if (node->pcs_data.hosttrap_entry.base.active_count && @@ -68,11 +69,14 @@ static int kfd_pc_sample_thread(void *param) adev = node->adev; need_wait = false; allow_signal(SIGKILL); + + if (node->kfd2kgd->override_core_cg) + for_each_inst(inst, node->xcc_mask) + node->kfd2kgd->override_core_cg(adev, 1, inst); + while (!kthread_should_stop() && !signal_pending(node->pcs_data.hosttrap_entry.base.pc_sample_thread)) { if (!need_wait) { - uint32_t inst; - next_trap_time = ktime_add_us(ktime_get_raw(), timeout); for_each_inst(inst, node->xcc_mask) { @@ -100,6 +104,9 @@ static int kfd_pc_sample_thread(void *param) } } } + if (node->kfd2kgd->override_core_cg) + for_each_inst(inst, node->xcc_mask) + node->kfd2kgd->override_core_cg(adev, 0, inst); node->pcs_data.hosttrap_entry.base.target_simd = 0; node->pcs_data.hosttrap_entry.base.target_wave_slot = 0; diff --git a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h index 27454731b3e04..3393b9c80bd2f 100644 --- a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h +++ b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h @@ -337,6 +337,9 @@ struct kfd2kgd_calls { uint32_t *target_wave_slot, enum kfd_ioctl_pc_sample_method method, uint32_t inst); + void (*override_core_cg)(struct amdgpu_device *adev, + uint32_t value, + uint32_t inst); }; #endif /* KGD_KFD_INTERFACE_H_INCLUDED */ From f162c904dba3a50635e813f845799e3bbad3688e Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 16 May 2024 14:00:18 +0800 Subject: [PATCH 1225/1868] drm/amdkcl: kcl-cleanup HAVE_SMCA_UMC_V2 is_smca_umc_v2 function never occurs in upstream kernel, macro HAVE_SMCA_UMC_V2 is undefined all the time, which cause MCE notifications is not handled on MI200 A+A platform. So we drop macro HAVE_SMCA_UMC_V2. On the other hand, on Centos 7.9, SMCA_UMC_V2 is not defined in arch/x86/include/asm/mce.h, we don't care umc_v2 error notification on centos 7.9. Signed-off-by: Asher Song Reviewed-by: Flora Cui Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 10 ++-------- drivers/gpu/drm/amd/dkms/config/config.h | 4 ++-- .../gpu/drm/amd/dkms/m4/check_smca_umc_v2.m4 | 13 ------------- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 2 +- .../gpu/drm/amd/dkms/m4/mce_notifier_prios.m4 | 17 +++++++++++++++++ 5 files changed, 22 insertions(+), 24 deletions(-) delete mode 100644 drivers/gpu/drm/amd/dkms/m4/check_smca_umc_v2.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 047da1bb1e5e1..ebabcc84c9d35 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -44,10 +44,8 @@ #ifdef CONFIG_X86_MCE_AMD #include -#ifdef HAVE_SMCA_UMC_V2 static bool notifier_registered; #endif -#endif static const char *RAS_FS_NAME = "ras"; const char *ras_error_string[] = { @@ -141,7 +139,6 @@ static bool amdgpu_ras_check_bad_page_unlock(struct amdgpu_ras *con, static bool amdgpu_ras_check_bad_page(struct amdgpu_device *adev, uint64_t addr); #ifdef CONFIG_X86_MCE_AMD -#ifdef HAVE_SMCA_UMC_V2 static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev); struct mce_notifier_adev_list { struct amdgpu_device *devs[MAX_GPU_INSTANCE]; @@ -149,7 +146,6 @@ struct mce_notifier_adev_list { }; static struct mce_notifier_adev_list mce_adev_list; #endif -#endif void amdgpu_ras_set_error_query_ready(struct amdgpu_device *adev, bool ready) { @@ -3238,11 +3234,9 @@ int amdgpu_ras_recovery_init(struct amdgpu_device *adev) amdgpu_ras_ecc_log_init(&con->umc_ecc_log); #endif #ifdef CONFIG_X86_MCE_AMD -#ifdef HAVE_SMCA_UMC_V2 if ((adev->asic_type == CHIP_ALDEBARAN) && (adev->gmc.xgmi.connected_to_cpu)) amdgpu_register_bad_pages_mca_notifier(adev); -#endif #endif return 0; @@ -4149,7 +4143,6 @@ void amdgpu_release_ras_context(struct amdgpu_device *adev) } #ifdef CONFIG_X86_MCE_AMD -#ifdef HAVE_SMCA_UMC_V2 static struct amdgpu_device *find_adev(uint32_t node_id) { int i; @@ -4185,8 +4178,10 @@ static int amdgpu_bad_page_notifier(struct notifier_block *nb, * and error occurred in DramECC (Extended error code = 0) then only * process the error, else bail out. */ +#ifdef HAVE_SMCA_UMC_V2 if (!m || !((kcl_smca_get_bank_type(m->extcpu, m->bank) == SMCA_UMC_V2) && (XEC(m->status, 0x3f) == 0x0))) +#endif return NOTIFY_DONE; /* @@ -4250,7 +4245,6 @@ static void amdgpu_register_bad_pages_mca_notifier(struct amdgpu_device *adev) } } #endif -#endif struct amdgpu_ras *amdgpu_ras_get_context(struct amdgpu_device *adev) { diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 808cd37a40668..5e0eae0e92ff5 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -932,8 +932,8 @@ /* whether smca_get_bank_type(x, x) is available */ #define HAVE_SMCA_GET_BANK_TYPE_WITH_TWO_ARGUMENTS 1 -/* is_smca_umc_v2() is available */ -/* #undef HAVE_SMCA_UMC_V2 */ +/* enum SMCA_UMC_V2 is available */ +#define HAVE_SMCA_UMC_V2 1 /* struct dma_buf_attach_ops->allow_peer2peer is available */ #define HAVE_STRUCT_DMA_BUF_ATTACH_OPS_ALLOW_PEER2PEER 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/check_smca_umc_v2.m4 b/drivers/gpu/drm/amd/dkms/m4/check_smca_umc_v2.m4 deleted file mode 100644 index 28eda1decdae2..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/check_smca_umc_v2.m4 +++ /dev/null @@ -1,13 +0,0 @@ -dnl # -dnl # -dnl # is_smca_umc_v2() -dnl # -AC_DEFUN([AC_AMDGPU_CHECK_SMCA_UMC_V2], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_CHECK_SYMBOL_EXPORT([is_smca_umc_v2], - [arch/x86/kernel/cpu/mce/amd.c], [ - AC_DEFINE(HAVE_SMCA_UMC_V2, 1, - [is_smca_umc_v2() is available]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 13d9829605c14..4313f0bb37f1a 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -126,7 +126,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_PM_SUSPEND_VIA_FIRMWARE AC_AMDGPU_SYSFS_EMIT AC_AMDGPU_KTIME_IS_UNION - AC_AMDGPU_CHECK_SMCA_UMC_V2 AC_AMDGPU_PXM_TO_NODE AC_AMDGPU_ACPI_SRAT_GENERIC_AFFINITY AC_AMDGPU_KERNEL_WRITE @@ -234,6 +233,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DBG_PRINTER AC_AMDGPU_DRM_GEM_OBJECT_IS_SHARED_FOR_MEMORY_STATS AC_AMDGPU_DRM_DEBUG_CATEGORY + AC_AMDGPU_SMCA_UMC_V2 AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/dkms/m4/mce_notifier_prios.m4 b/drivers/gpu/drm/amd/dkms/m4/mce_notifier_prios.m4 index e3d33a862d7fb..de3f546345a28 100644 --- a/drivers/gpu/drm/amd/dkms/m4/mce_notifier_prios.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/mce_notifier_prios.m4 @@ -15,3 +15,20 @@ AC_DEFUN([AC_AMDGPU_MCE_PRIO_UC], [ ]) ]) ]) +dnl # +dnl # v5.13-rc3-1-g94a311ce248e +dnl # x86/MCE/AMD, EDAC/mce_amd: Add new SMCA bank types +dnl # +AC_DEFUN([AC_AMDGPU_SMCA_UMC_V2], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + enum smca_bank_types bank_type; + bank_type = SMCA_UMC_V2; + ], [ + AC_DEFINE(HAVE_SMCA_UMC_V2, 1, + [enum SMCA_UMC_V2 is available]) + ]) + ]) +]) From b6a9ae6bd5fe9db4241b3de5ba10bbbe39fb1526 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 17 May 2024 11:52:59 +0800 Subject: [PATCH 1226/1868] drm/amdkcl: fake smca_get_bank_type When redefining HAVE_SMCA_UMC_V2, the fake function smca_get_bank_type is called by amdgpu_bad_page_notifier. However origin fake function can not be referenced when making intree build as it defined in amdkcl modules. So we make a macro for the fake function in backport/kcl_mce.h Signed-off-by: Asher Song Reviewed-by: Flora Cui Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_mce_amd.c | 37 +++++------------------- drivers/gpu/drm/amd/backport/backport.h | 1 + include/kcl/backport/kcl_mce.h | 13 +++++++++ include/kcl/kcl_mce.h | 26 +++++++++++++---- 5 files changed, 42 insertions(+), 37 deletions(-) create mode 100644 include/kcl/backport/kcl_mce.h diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index ebabcc84c9d35..bb61f68c3818e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -4179,7 +4179,7 @@ static int amdgpu_bad_page_notifier(struct notifier_block *nb, * process the error, else bail out. */ #ifdef HAVE_SMCA_UMC_V2 - if (!m || !((kcl_smca_get_bank_type(m->extcpu, m->bank) == SMCA_UMC_V2) && + if (!m || !((smca_get_bank_type(m->extcpu, m->bank) == SMCA_UMC_V2) && (XEC(m->status, 0x3f) == 0x0))) #endif return NOTIFY_DONE; diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_mce_amd.c b/drivers/gpu/drm/amd/amdkcl/kcl_mce_amd.c index bd90d447713f5..e2cd6191d7171 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_mce_amd.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_mce_amd.c @@ -7,24 +7,11 @@ * * All MC4_MISCi registers are shared between cores on a node. */ - - #ifdef CONFIG_X86_MCE_AMD #include -#if defined(HAVE_SMCA_GET_BANK_TYPE_WITH_TWO_ARGUMENTS) -enum smca_bank_types kcl_smca_get_bank_type(unsigned int cpu, unsigned int bank) -{ - return smca_get_bank_type(cpu, bank); -} -#elif defined(HAVE_SMCA_GET_BANK_TYPE_WITH_ONE_ARGUMENT) -enum smca_bank_types kcl_smca_get_bank_type(unsigned int cpu, unsigned int bank) -{ - return smca_get_bank_type(bank); -} - -/* Copied from v5.15-rc2-452-gf38ce910d8df:arch/x86/kernel/cpu/mce/amd.c and modified for KCL */ -#elif defined(HAVE_STRUCT_SMCA_BANK) +#if !defined(HAVE_SMCA_GET_BANK_TYPE_WITH_TWO_ARGUMENTS) && !defined(HAVE_SMCA_GET_BANK_TYPE_WITH_ONE_ARGUMENT) +#if defined(HAVE_STRUCT_SMCA_BANK) enum smca_bank_types smca_get_bank_type(unsigned int bank) { struct smca_bank *b; @@ -38,24 +25,14 @@ enum smca_bank_types smca_get_bank_type(unsigned int bank) return b->hwid->bank_type; } -enum smca_bank_types kcl_smca_get_bank_type(unsigned int cpu, unsigned int bank) -{ - return smca_get_bank_type(bank); -} - #else int smca_get_bank_type(unsigned int bank) { - pr_warn_once("smca_get_bank_type is not supported\n"); - return 0; + pr_warn_once("smca_get_bank_type is not supported\n"); + return 0; } - -int kcl_smca_get_bank_type(unsigned int cpu, unsigned int bank) -{ - return smca_get_bank_type(bank); -} - -#endif -EXPORT_SYMBOL_GPL(kcl_smca_get_bank_type); +#endif +EXPORT_SYMBOL_GPL(smca_get_bank_type); +#endif #endif /* CONFIG_X86_MCE_AMD */ diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 5b6a4ed692d8d..78ab1d617f6b3 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -125,4 +125,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/include/kcl/backport/kcl_mce.h b/include/kcl/backport/kcl_mce.h new file mode 100644 index 0000000000000..08c69209a1a49 --- /dev/null +++ b/include/kcl/backport/kcl_mce.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _KCL_BACKPORT_KCL_MCE_H +#define _KCL_BACKPORT_KCL_MCE_H + +#include + +#ifdef CONFIG_X86_MCE_AMD +#ifndef HAVE_SMCA_GET_BANK_TYPE_WITH_TWO_ARGUMENTS +#define smca_get_bank_type _kcl_smca_get_bank_type +#endif /* HAVE_SMCA_GET_BANK_TYPE_WITH_TWO_ARGUMENTS */ +#endif /* CONFIG_X86_MCE_AMD */ + +#endif /* _KCL_BACKPORT_KCL_MCE_H */ diff --git a/include/kcl/kcl_mce.h b/include/kcl/kcl_mce.h index fd6098c99a240..223c2bd03bb87 100644 --- a/include/kcl/kcl_mce.h +++ b/include/kcl/kcl_mce.h @@ -11,15 +11,29 @@ #define XEC(x, mask) (((x) >> 16) & mask) #endif -#if defined(HAVE_SMCA_GET_BANK_TYPE_WITH_TWO_ARGUMENTS) || defined(HAVE_SMCA_GET_BANK_TYPE_WITH_ONE_ARGUMENT) || defined(HAVE_STRUCT_SMCA_BANK) -enum smca_bank_types kcl_smca_get_bank_type(unsigned int cpu, unsigned int bank); -#else -int kcl_smca_get_bank_type(unsigned int cpu, unsigned int bank); -#endif - #ifndef HAVE_MCE_PRIO_UC #define MCE_PRIO_UC MCE_PRIO_SRAO #endif +#if !defined(HAVE_SMCA_GET_BANK_TYPE_WITH_TWO_ARGUMENTS) +#if defined(HAVE_SMCA_GET_BANK_TYPE_WITH_ONE_ARGUMENT) || defined(HAVE_STRUCT_SMCA_BANK) +#if defined(HAVE_STRUCT_SMCA_BANK) +enum smca_bank_types smca_get_bank_type(unsigned int bank); +#endif +static inline +enum smca_bank_types _kcl_smca_get_bank_type(unsigned int cpu, unsigned int bank) +{ + return smca_get_bank_type(bank); +} +#else +int smca_get_bank_type(unsigned int bank); +static inline +int _kcl_smca_get_bank_type(unsigned int cpu, unsigned int bank) +{ + return smca_get_bank_type(bank); +} +#endif +#endif + #endif /* CONFIG_X86_MCE_AMD */ #endif From 9adba6069826c217077b617ccf95e2d74ba017eb Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 22 May 2024 21:00:34 +0800 Subject: [PATCH 1227/1868] drm/amdkcl:test topology_num_cores_per_package whether exist It's caused by v6.8-rc4-71-g89b0f15f408f x86/cpu/topology: Get rid of cpuinfo::x86_max_cores Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/m4/asm_topology.m4 | 19 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c | 4 ++++ 3 files changed, 24 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/asm_topology.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/asm_topology.m4 b/drivers/gpu/drm/amd/dkms/m4/asm_topology.m4 new file mode 100644 index 0000000000000..ec603c4bd1a9b --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/asm_topology.m4 @@ -0,0 +1,19 @@ +dnl # +dnl # v6.8-rc4-70-gfd43b8ae76e9 +dnl # x86/cpu/topology: Provide __num_[cores|threads]_per_package +dnl # +AC_DEFUN([AC_AMDGPU_TOPOLOGY_NUM_CORES_PER_PACKAGE], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + #include + ], [ + int a = 0; + a = topology_num_cores_per_package(); + ], [ + AC_DEFINE(HAVE_TOPOLOGY_NUM_CORES_PER_PACKAGE, 1, + [topology_num_cores_per_package is availablea]) + ]) + ]) +]) + diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 4313f0bb37f1a..5581b3dbffb12 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -234,6 +234,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_GEM_OBJECT_IS_SHARED_FOR_MEMORY_STATS AC_AMDGPU_DRM_DEBUG_CATEGORY AC_AMDGPU_SMCA_UMC_V2 + AC_AMDGPU_TOPOLOGY_NUM_CORES_PER_PACKAGE AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c index 22737b11b1bfb..0bb9636d14c38 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c @@ -451,7 +451,11 @@ static int vangogh_init_smc_tables(struct smu_context *smu) #ifdef CONFIG_X86 /* AMD x86 APU only */ +#ifdef HAVE_TOPOLOGY_NUM_CORES_PER_PACKAGE smu->cpu_core_num = topology_num_cores_per_package(); +#else + smu->cpu_core_num = boot_cpu_data.x86_max_cores; +#endif #else smu->cpu_core_num = 4; #endif From ff6fe7ac7f9e7a0fa64b583fec7add218f5789ab Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 23 May 2024 13:59:58 +0800 Subject: [PATCH 1228/1868] drm/amdkcl: fake linux/pgtable.h header It's caused by v6.8-rc6-1469-g2c6f6831876a drm/ttm: make ttm_caching.h self-contained Signed-off-by: Asher Song --- include/kcl/header/linux/pgtable.h | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 include/kcl/header/linux/pgtable.h diff --git a/include/kcl/header/linux/pgtable.h b/include/kcl/header/linux/pgtable.h new file mode 100644 index 0000000000000..27198a089c730 --- /dev/null +++ b/include/kcl/header/linux/pgtable.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_LINUX_PGTABLE_H_H_ +#define _KCL_HEADER_LINUX_PGTABLE_H_H_ + +#ifdef HAVE_LINUX_PGTABLE_H +#include_next +#else +#include +#endif + +#endif From 09e9636e2333dd8db797d4acd4fa7b4f4c49a237 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 23 May 2024 14:41:31 +0800 Subject: [PATCH 1229/1868] drm/amdkcl: fake drm_info_once It's caused by v6.9-rc1-50-g27906e5d7824 drm/ttm: Print the memory decryption status just once Signed-off-by: Asher Song --- include/kcl/kcl_drm_print.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/kcl/kcl_drm_print.h b/include/kcl/kcl_drm_print.h index 0546bd944b72c..0506b7a41f121 100644 --- a/include/kcl/kcl_drm_print.h +++ b/include/kcl/kcl_drm_print.h @@ -201,4 +201,10 @@ enum drm_debug_category { __drm_printk((drm), info,, fmt, ##__VA_ARGS__) #endif +#ifndef drm_info_once +/* copied from include/drm/drm_print.h */ +#define drm_info_once(drm, fmt, ...) \ + __drm_printk((drm), info, _once, fmt, ##__VA_ARGS__) +#endif + #endif From 6312a8098a38cd2ea52a9730c64d2855cafdacf1 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 23 May 2024 14:58:19 +0800 Subject: [PATCH 1230/1868] drm/amdkcl: Test whether drm_gem_object->resv is available It's caused by v6.8-rc6-1519-g5a95f39d9b21 drm/ttm: warn when resv objs are mixed in a bulk_move v6.4-rc2-1582-ge2ad8e2df432 drm/amdgpu: make sure BOs are locked in amdgpu_vm_get_memory Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 4 ++-- drivers/gpu/drm/ttm/ttm_resource.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 44b57a7cb78e1..e4721b2a17b2e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -1132,12 +1132,12 @@ static void amdgpu_vm_bo_get_memory(struct amdgpu_bo_va *bo_va, * changing their location. */ if (!amdgpu_vm_is_bo_always_valid(vm, bo) && - !dma_resv_trylock(bo->tbo.base.resv)) + !dma_resv_trylock(amdkcl_ttm_resvp(&bo->tbo))) return; amdgpu_bo_get_memory(bo, stats); if (!amdgpu_vm_is_bo_always_valid(vm, bo)) - dma_resv_unlock(bo->tbo.base.resv); + dma_resv_unlock(amdkcl_ttm_resvp(&bo->tbo)); } void amdgpu_vm_get_memory(struct amdgpu_vm *vm, diff --git a/drivers/gpu/drm/ttm/ttm_resource.c b/drivers/gpu/drm/ttm/ttm_resource.c index 3caa24dcf1c51..996324bbd5b12 100644 --- a/drivers/gpu/drm/ttm/ttm_resource.c +++ b/drivers/gpu/drm/ttm/ttm_resource.c @@ -107,7 +107,7 @@ static void ttm_lru_bulk_move_add(struct ttm_lru_bulk_move *bulk, pos->first = res; pos->last = res; } else { - WARN_ON(pos->first->bo->base.resv != res->bo->base.resv); + WARN_ON(amdkcl_ttm_resvp(pos->first->bo) != amdkcl_ttm_resvp(res->bo)); ttm_lru_bulk_move_pos_tail(pos, res); } } From ba788ccb5288b1d2760fdbd9ced1e3e3fd607b8c Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 29 May 2024 17:39:47 +0800 Subject: [PATCH 1231/1868] drm/amdkcl: remove macro HAVE_AMD_IOMMU_PC_SUPPORTED Due IOMMUv2 support have been removed, this macro is not required. c99a2e7ae291e5b19b60443eb drm/amdkfd: drop IOMMUv2 support Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 18 ------------------ drivers/gpu/drm/amd/amdkfd/kfd_topology.h | 6 ------ 2 files changed, 24 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index c885b0576e1c5..bd692eefec616 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -133,9 +133,7 @@ static void kfd_release_topology_device(struct kfd_topology_device *dev) struct kfd_cache_properties *cache; struct kfd_iolink_properties *iolink; struct kfd_iolink_properties *p2plink; -#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED struct kfd_perf_properties *perf; -#endif list_del(&dev->list); @@ -167,14 +165,12 @@ static void kfd_release_topology_device(struct kfd_topology_device *dev) kfree(p2plink); } -#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED while (dev->perf_props.next != &dev->perf_props) { perf = container_of(dev->perf_props.next, struct kfd_perf_properties, list); list_del(&perf->list); kfree(perf); } -#endif kfree(dev); } @@ -211,9 +207,7 @@ struct kfd_topology_device *kfd_create_topology_device( INIT_LIST_HEAD(&dev->cache_props); INIT_LIST_HEAD(&dev->io_link_props); INIT_LIST_HEAD(&dev->p2p_link_props); -#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED INIT_LIST_HEAD(&dev->perf_props); -#endif list_add_tail(&dev->list, device_list); @@ -407,7 +401,6 @@ static const struct kobj_type cache_type = { .sysfs_ops = &cache_ops, }; -#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED /****** Sysfs of Performance Counters ******/ struct kfd_perf_attr { @@ -441,7 +434,6 @@ static struct kfd_perf_attr perf_attr_iommu[] = { KFD_PERF_DESC(counter_ids, 0), }; /****************************************/ -#endif static ssize_t node_show(struct kobject *kobj, struct attribute *attr, char *buffer) @@ -597,9 +589,7 @@ static void kfd_remove_sysfs_node_entry(struct kfd_topology_device *dev) struct kfd_iolink_properties *iolink; struct kfd_cache_properties *cache; struct kfd_mem_properties *mem; -#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED struct kfd_perf_properties *perf; -#endif if (dev->kobj_p2plink) { list_for_each_entry(p2plink, &dev->p2p_link_props, list) @@ -665,7 +655,6 @@ static void kfd_remove_sysfs_node_entry(struct kfd_topology_device *dev) dev->kobj_mem = NULL; } -#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED if (dev->kobj_perf) { list_for_each_entry(perf, &dev->perf_props, list) { kfree(perf->attr_group); @@ -675,7 +664,6 @@ static void kfd_remove_sysfs_node_entry(struct kfd_topology_device *dev) kobject_put(dev->kobj_perf); dev->kobj_perf = NULL; } -#endif if (dev->kobj_node) { sysfs_remove_file(dev->kobj_node, &dev->attr_gpuid); @@ -694,11 +682,9 @@ static int kfd_build_sysfs_node_entry(struct kfd_topology_device *dev, struct kfd_iolink_properties *iolink; struct kfd_cache_properties *cache; struct kfd_mem_properties *mem; -#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED struct kfd_perf_properties *perf; uint32_t num_attrs; struct attribute **attrs; -#endif int ret; uint32_t i; @@ -735,11 +721,9 @@ static int kfd_build_sysfs_node_entry(struct kfd_topology_device *dev, if (!dev->kobj_p2plink) return -ENOMEM; -#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED dev->kobj_perf = kobject_create_and_add("perf", dev->kobj_node); if (!dev->kobj_perf) return -ENOMEM; -#endif /* * Creating sysfs files for node properties @@ -858,7 +842,6 @@ static int kfd_build_sysfs_node_entry(struct kfd_topology_device *dev, i++; } -#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED /* All hardware blocks have the same number of attributes. */ num_attrs = ARRAY_SIZE(perf_attr_iommu); list_for_each_entry(perf, &dev->perf_props, list) { @@ -884,7 +867,6 @@ static int kfd_build_sysfs_node_entry(struct kfd_topology_device *dev, if (ret < 0) return ret; } -#endif return 0; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h index d83a41dce7d60..22e4b2cca1fe4 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.h @@ -133,14 +133,12 @@ struct kfd_iolink_properties { struct attribute attr; }; -#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED struct kfd_perf_properties { struct list_head list; char block_name[16]; uint32_t max_concurrent; struct attribute_group *attr_group; }; -#endif struct kfd_topology_device { struct list_head list; @@ -151,18 +149,14 @@ struct kfd_topology_device { struct list_head cache_props; struct list_head io_link_props; struct list_head p2p_link_props; -#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED struct list_head perf_props; -#endif struct kfd_node *gpu; struct kobject *kobj_node; struct kobject *kobj_mem; struct kobject *kobj_cache; struct kobject *kobj_iolink; struct kobject *kobj_p2plink; -#ifdef HAVE_AMD_IOMMU_PC_SUPPORTED struct kobject *kobj_perf; -#endif struct attribute attr_gpuid; struct attribute attr_name; struct attribute attr_props; From 5805f66a4a363293dbbd09643718fd9f5ff69e11 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 17 May 2024 15:18:01 +0800 Subject: [PATCH 1232/1868] drm/amdgpu: fix the used uninitialized issue The vailable clk_cntl is used uninitialized, so initialize it to fix intree build issue. Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c index 610cbcfbe9e0d..3679afa017baf 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c @@ -1277,7 +1277,7 @@ void kgd_gfx_v9_override_core_cg(struct amdgpu_device *adev, uint32_t value, uint32_t inst) { - uint32_t clk_cntl; + uint32_t clk_cntl = 0; mutex_lock(&adev->grbm_idx_mutex); amdgpu_gfx_select_se_sh(adev, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, inst); From b809ef179a51ffa1424e51772542cf39b433cca7 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Thu, 30 May 2024 16:35:26 +0800 Subject: [PATCH 1233/1868] Bump AMDGPU version to 6.9.0 Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/config/config.h | 38 +++++------------------- drivers/gpu/drm/amd/dkms/configure.ac | 2 +- 2 files changed, 8 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 5e0eae0e92ff5..1f9c2640c5a13 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -38,13 +38,13 @@ /* #undef HAVE_AMD_IOMMU_INVALIDATE_CTX_PASID_U32 */ /* amd_iommu_pc_get_max_banks() declared */ -#define HAVE_AMD_IOMMU_PC_GET_MAX_BANKS_DECLARED 1 +/* #undef HAVE_AMD_IOMMU_PC_GET_MAX_BANKS_DECLARED */ /* amd_iommu_pc_get_max_banks() arg is unsigned int */ /* #undef HAVE_AMD_IOMMU_PC_GET_MAX_BANKS_UINT */ /* amd_iommu_pc_supported() is available */ -#define HAVE_AMD_IOMMU_PC_SUPPORTED 1 +/* #undef HAVE_AMD_IOMMU_PC_SUPPORTED */ /* apple_gmux_detect() is available */ #define HAVE_APPLE_GMUX_DETECT 1 @@ -124,9 +124,6 @@ /* dma_fence_describe() is available */ #define HAVE_DMA_FENCE_DESCRIBE 1 -/* whether dma_fence_get_stub exits */ -#define HAVE_DMA_FENCE_GET_STUB 1 - /* dma_fence_is_container() is available */ #define HAVE_DMA_FENCE_IS_CONTAINER 1 @@ -211,15 +208,6 @@ /* drm_connector_init_with_ddc() is available */ #define HAVE_DRM_CONNECTOR_INIT_WITH_DDC 1 -/* connector property "max bpc" is available */ -#define HAVE_DRM_CONNECTOR_PROPERTY_MAX_BPC 1 - -/* drm_connector_put() is available */ -#define HAVE_DRM_CONNECTOR_PUT 1 - -/* connector reference counting is available */ -#define HAVE_DRM_CONNECTOR_REFERENCE_COUNTING_SUPPORTED 1 - /* drm_connector_set_panel_orientation_with_quirk() is available */ #define HAVE_DRM_CONNECTOR_SET_PANEL_ORIENTATION_WITH_QUIRK 1 @@ -252,9 +240,6 @@ /* drm_debug_enabled() is available */ #define HAVE_DRM_DEBUG_ENABLED 1 -/* drm_device->filelist_mutex is available */ -#define HAVE_DRM_DEVICE_FILELIST_MUTEX 1 - /* drm_device->open_count is int */ /* #undef HAVE_DRM_DEVICE_OPEN_COUNT_INT */ @@ -289,9 +274,6 @@ /* display_info->edid_hdmi_rgb444_dc_modes is available */ #define HAVE_DRM_DISPLAY_INFO_EDID_HDMI_RGB444_DC_MODES 1 -/* display_info->hdmi.scdc.scrambling are available */ -#define HAVE_DRM_DISPLAY_INFO_HDMI_SCDC_SCRAMBLING 1 - /* display_info->is_hdmi is available */ #define HAVE_DRM_DISPLAY_INFO_IS_HDMI 1 @@ -674,9 +656,6 @@ /* io_mapping_map_local_wc() is available */ #define HAVE_IO_MAPPING_MAP_LOCAL_WC 1 -/* io_mapping_map_wc() has size argument */ -#define HAVE_IO_MAPPING_MAP_WC_HAS_SIZE_ARG 1 - /* io_mapping_unmap_local() is available */ #define HAVE_IO_MAPPING_UNMAP_LOCAL 1 @@ -962,12 +941,6 @@ /* struct drm_crtc_state->async_flip is available */ #define HAVE_STRUCT_DRM_CRTC_STATE_ASYNC_FLIP 1 -/* struct drm_crtc_state has flag for flip */ -#define HAVE_STRUCT_DRM_CRTC_STATE_FLIP_FLAG 1 - -/* struct drm_crtc_state->pageflip_flags is available */ -/* #undef HAVE_STRUCT_DRM_CRTC_STATE_PAGEFLIP_FLAGS */ - /* drm_gem_open_object is defined in struct drm_drv */ /* #undef HAVE_STRUCT_DRM_DRV_GEM_OPEN_OBJECT_CALLBACK */ @@ -996,6 +969,9 @@ /* sysfs_emit() and sysfs_emit_at() are available */ #define HAVE_SYSFS_EMIT 1 +/* topology_num_cores_per_package is availablea */ +#define HAVE_TOPOLOGY_NUM_CORES_PER_PACKAGE 1 + /* totalram_pages() is available */ #define HAVE_TOTALRAM_PAGES 1 @@ -1075,7 +1051,7 @@ #define PACKAGE_NAME "amdgpu-dkms" /* Define to the full name and version of this package. */ -#define PACKAGE_STRING "amdgpu-dkms 6.8.0" +#define PACKAGE_STRING "amdgpu-dkms 6.9.0" /* Define to the one symbol short name of this package. */ #define PACKAGE_TARNAME "amdgpu-dkms" @@ -1084,7 +1060,7 @@ #define PACKAGE_URL "" /* Define to the version of this package. */ -#define PACKAGE_VERSION "6.8.0" +#define PACKAGE_VERSION "6.9.0" #include "config-amd-chips.h" diff --git a/drivers/gpu/drm/amd/dkms/configure.ac b/drivers/gpu/drm/amd/dkms/configure.ac index b7b164ae0201c..e49b5ff073bd2 100644 --- a/drivers/gpu/drm/amd/dkms/configure.ac +++ b/drivers/gpu/drm/amd/dkms/configure.ac @@ -1,4 +1,4 @@ -AC_INIT(amdgpu-dkms, 6.8.0) +AC_INIT(amdgpu-dkms, 6.9.0) AC_LANG(C) AC_CONFIG_AUX_DIR([config]) From eb53d448f593895ae7ae68dff6709dadbc94d371 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 20 May 2024 10:57:42 +0800 Subject: [PATCH 1234/1868] drm/amdkcl: wrap code under macro HAVE_PCI_DRIVER_DEV_GROUPS It's caused by 7535d371a27cc788d8f41394a22e3fd492ee5d2c "drm/amd/pm: Add support for DPM policies" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/pm/amdgpu_pm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c index d5d6ab484e5ad..847f678f1cc8c 100644 --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c @@ -4531,6 +4531,7 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev) dev_info(adev->dev, "overdrive feature is not supported\n"); } +#ifdef HAVE_PCI_DRIVER_DEV_GROUPS if (amdgpu_dpm_get_pm_policy_info(adev, PP_PM_POLICY_NONE, NULL) != -EOPNOTSUPP) { ret = devm_device_add_group(adev->dev, @@ -4538,6 +4539,7 @@ int amdgpu_pm_sysfs_init(struct amdgpu_device *adev) if (ret) goto err_out0; } +#endif adev->pm.sysfs_initialized = true; From 24b124d97d46aec68f82e8a763495f8366d819f6 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Thu, 23 May 2024 12:06:52 +0800 Subject: [PATCH 1235/1868] Revert "drm/amdkcl: Fix missing underline of CONFIG_DMABUF_MOVENOTIFY" This reverts commit 0f7a49009bddfc5ad1ef7aebd3a0536035a5a503. This reverted patch casues a jira issue SWDEV-459972 Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 1586454860bc7..0e41d5633a6f9 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -192,7 +192,7 @@ export CONFIG_DRM_AMD_DC_HDCP=y subdir-ccflags-y += -DCONFIG_DRM_AMD_DC_HDCP ifeq (y,$(CONFIG_PCI_P2PDMA)) - ifeq (y,$(CONFIG_DMABUF_MOVE_NOTIFY)) + ifeq (y,$(CONFIG_DMABUF_MOVENOTIFY)) export CONFIG_HSA_AMD_P2P=y subdir-ccflags-y += -DCONFIG_HSA_AMD_P2P endif From 19d361bafa20259e409afa3da503a9d1acab90b2 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 27 May 2024 10:54:39 +0800 Subject: [PATCH 1236/1868] drm/amdkcl: wrap code under macro HAVE_DRM_CONNECT_ATTACH_COLORSPACE_PROPERTY It's caused by e3a473ed04f7f1b061860437876a269073dc302d "drm/amd/display: Enable colorspace property for MST connectors" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 0eb1617fcc513..1b50f05d124f2 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -687,10 +687,12 @@ dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr, &connector->base, dev->mode_config.tile_property, 0); + +#ifdef HAVE_DRM_CONNECT_ATTACH_COLORSPACE_PROPERTY connector->colorspace_property = master->base.colorspace_property; if (connector->colorspace_property) drm_connector_attach_colorspace_property(connector); - +#endif drm_connector_set_path_property(connector, pathprop); /* From cd26ab5941d5b2dfeec288e91d5ff19c48e289db Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 27 May 2024 10:56:52 +0800 Subject: [PATCH 1237/1868] drm/amdkcl: fake macro fuction __counted_by() It's caused by d4fa69b7bd8a7c950a0b838ca0c1feef2bb03d84 "drm/amdgpu: silence UBSAN warning" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- include/kcl/kcl_compiler_attributes.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/include/kcl/kcl_compiler_attributes.h b/include/kcl/kcl_compiler_attributes.h index 34d035352059c..e844e68139479 100644 --- a/include/kcl/kcl_compiler_attributes.h +++ b/include/kcl/kcl_compiler_attributes.h @@ -10,4 +10,16 @@ #define fallthrough do {} while (0) /* fallthrough */ #endif +#ifndef __has_attribute +#define __has_attribute(x) 0 +#endif + +#ifndef __counted_by +#if __has_attribute(__counted_by__) +# define __counted_by(member) __attribute__((__counted_by__(member))) +#else +# define __counted_by(member) +#endif +#endif + #endif /* AMDKCL_COMPILER_ATTRIBUTES_H */ From e52868ba190c533aa8f3e8dcc23e8f4b0e01eaf5 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 28 May 2024 14:45:06 +0800 Subject: [PATCH 1238/1868] drm/amd/display: add judge condition to fix intree build issue Due to dkms backport includes ASSERT macro, so add judge condition to avoid redefined macro. Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- .../dml2/dml21/src/dml2_standalone_libraries/lib_float_math.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_standalone_libraries/lib_float_math.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_standalone_libraries/lib_float_math.c index e17b5ceba4471..3bb835b5585ac 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_standalone_libraries/lib_float_math.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_standalone_libraries/lib_float_math.c @@ -4,7 +4,9 @@ #include "lib_float_math.h" +#ifndef ASSERT #define ASSERT(condition) +#endif #define isNaN(number) ((number) != (number)) From 6cde9469442125d9dab083da89fc6f6426790324 Mon Sep 17 00:00:00 2001 From: Bing Ma Date: Thu, 30 May 2024 14:07:15 -0700 Subject: [PATCH 1239/1868] drm/amdkfd: Fix various crash, hang and corruption issues for KFD SPM support 1. Need to convert drm_priv to amdgpu_vm when calling amdgpu_amdkfd_rlc_spm_*() functions. 2. Per RLC spec, ring_wptr = 0 and ring_rptr = 0 point to mmRLC_SPM_PERFMON_RING_BASE+0x20, change code accordingly. Signed-off-by: Bing Ma Reviewed-by: Harish Kasiviwanathan --- drivers/gpu/drm/amd/amdkfd/kfd_spm.c | 26 ++++++++------------------ 1 file changed, 8 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c index 00da1cabcbd45..6480e9c49f608 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c @@ -39,7 +39,6 @@ struct kfd_spm_cntr { struct mutex spm_worker_mutex; u64 gpu_addr; u32 ring_size; - u32 ring_mask; u32 ring_rptr; u32 size_copied; u32 has_data_loss; @@ -63,7 +62,8 @@ static int kfd_spm_data_copy(struct kfd_process_device *pdd, u32 size_to_copy) return -EFAULT; user_address = (uint64_t *)((uint64_t)spm->ubuf.user_addr + spm->size_copied); - ring_buf = (uint64_t *)((uint64_t)spm->cpu_addr + spm->ring_rptr); + // From RLC spec, ring_rptr = 0 points to spm->cpu_addr+0x20 + ring_buf = (uint64_t *)((uint64_t)spm->cpu_addr + spm->ring_rptr + 0x20); if (user_address == NULL) return -EFAULT; @@ -101,7 +101,7 @@ static int kfd_spm_read_ring_buffer(struct kfd_process_device *pdd) int ret = 0; u32 ring_wptr; - ring_wptr = READ_ONCE(spm->cpu_addr[0]) & spm->ring_mask; + ring_wptr = READ_ONCE(spm->cpu_addr[0]); /* keep SPM ring buffer running */ if (!spm->has_user_buf || spm->is_user_buf_filled) { @@ -118,13 +118,6 @@ static int kfd_spm_read_ring_buffer(struct kfd_process_device *pdd) if (spm->ring_rptr == ring_wptr) goto exit; - if ((spm->ring_rptr >= 0) && (spm->ring_rptr < 0x20)) { - /* - * First 8DW, only use for WritePtr, it is not Counter data - */ - spm->ring_rptr = 0x20; - } - if (ring_wptr > spm->ring_rptr) { size_to_copy = ring_wptr - spm->ring_rptr; ret = kfd_spm_data_copy(pdd, size_to_copy); @@ -139,7 +132,7 @@ static int kfd_spm_read_ring_buffer(struct kfd_process_device *pdd) spm->ring_rptr = ring_wptr; goto exit; } - spm->ring_rptr = 0x20; + spm->ring_rptr = 0; size_to_copy = ring_wptr - spm->ring_rptr; if (!ret) ret = kfd_spm_data_copy(pdd, size_to_copy); @@ -192,12 +185,10 @@ static int kfd_acquire_spm(struct kfd_process_device *pdd, struct amdgpu_device mutex_unlock(&pdd->spm_mutex); return -ENOMEM; } - mutex_unlock(&pdd->spm_mutex); /* git spm ring buffer 4M */ pdd->spm_cntr->ring_size = order_base_2(4 * 1024 * 1024/4); - pdd->spm_cntr->ring_size = (1 << pdd->spm_cntr->ring_size) * 4 - 0xff; - pdd->spm_cntr->ring_mask = pdd->spm_cntr->ring_size - 1; + pdd->spm_cntr->ring_size = (1 << pdd->spm_cntr->ring_size) * 4; pdd->spm_cntr->has_user_buf = false; ret = amdgpu_amdkfd_alloc_gtt_mem(adev, @@ -208,7 +199,7 @@ static int kfd_acquire_spm(struct kfd_process_device *pdd, struct amdgpu_device if (ret) goto alloc_gtt_mem_failure; - ret = amdgpu_amdkfd_rlc_spm_acquire(adev, pdd->drm_priv, + ret = amdgpu_amdkfd_rlc_spm_acquire(adev, drm_priv_to_vm(pdd->drm_priv), pdd->spm_cntr->gpu_addr, pdd->spm_cntr->ring_size); /* @@ -233,12 +224,11 @@ static int kfd_acquire_spm(struct kfd_process_device *pdd, struct amdgpu_device amdgpu_amdkfd_free_gtt_mem(adev, pdd->spm_cntr->spm_obj); alloc_gtt_mem_failure: - mutex_lock(&pdd->spm_mutex); kfree(pdd->spm_cntr); pdd->spm_cntr = NULL; - mutex_unlock(&pdd->spm_mutex); out: + mutex_unlock(&pdd->spm_mutex); return ret; } @@ -259,7 +249,7 @@ static int kfd_release_spm(struct kfd_process_device *pdd, struct amdgpu_device flush_work(&pdd->spm_work); wake_up_all(&pdd->spm_cntr->spm_buf_wq); - amdgpu_amdkfd_rlc_spm_release(adev, pdd->drm_priv); + amdgpu_amdkfd_rlc_spm_release(adev, drm_priv_to_vm(pdd->drm_priv)); amdgpu_amdkfd_free_gtt_mem(adev, pdd->spm_cntr->spm_obj); spin_lock_irqsave(&pdd->spm_irq_lock, flags); From 37d9a70ce6e2f23f41bc82875d2ae0cacd721102 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 13 Jun 2024 15:49:57 +0800 Subject: [PATCH 1240/1868] drm/amdkcl: wrap code under macro HAVE_DRM_DP_MST_PORT_PASSTHROUGH_AUX It's caused by 25561e6d31d0ea9ba953b6f41958be3a70d2313b "drm/amd/display: Don't refer to dc_sink in is_dsc_need_re_compute" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 1b50f05d124f2..71e1019c3d2cc 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -206,7 +206,9 @@ amdgpu_dm_mst_connector_early_unregister(struct drm_connector *connector) aconnector->dc_sink = NULL; aconnector->edid = NULL; aconnector->dsc_aux = NULL; +#ifdef HAVE_DRM_DP_MST_PORT_PASSTHROUGH_AUX port->passthrough_aux = NULL; +#endif } aconnector->mst_status = MST_STATUS_DEFAULT; @@ -543,7 +545,9 @@ dm_dp_mst_detect(struct drm_connector *connector, aconnector->dc_sink = NULL; aconnector->edid = NULL; aconnector->dsc_aux = NULL; +#ifdef HAVE_DRM_DP_MST_PORT_PASSTHROUGH_AUX port->passthrough_aux = NULL; +#endif amdgpu_dm_set_mst_status(&aconnector->mst_status, MST_REMOTE_EDID | MST_ALLOCATE_NEW_PAYLOAD | MST_CLEAR_ALLOCATED_PAYLOAD, From e517b56fab41179f9c6c027eef60f1bcd8135dbf Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 13 Jun 2024 13:39:28 +0800 Subject: [PATCH 1241/1868] drm/amdkcl: Test drm_atomic_plane_enabling() is available It's caused by 1d0c9ded451944ef616149be5fe4a7d9a9d428da "drm/amd/display: Introduce overlay cursor mode" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../drm/amd/dkms/m4/drm_atomic_plane_enabling.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_atomic_helper.h | 16 ++++++++++++++++ 4 files changed, 36 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_atomic_plane_enabling.m4 diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 1f9c2640c5a13..03d785eef8a0b 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -176,6 +176,9 @@ /* drm_atomic_helper_calc_timestamping_constants() is available */ #define HAVE_DRM_ATOMIC_HELPER_CALC_TIMESTAMPING_CONSTANTS 1 +/* drm_atomic_plane_enabling() is available */ +#define HAVE_DRM_ATOMIC_PLANE_ENABLING 1 + /* drm_atomic_private_obj_init() wants 4 args */ #define HAVE_DRM_ATOMIC_PRIVATE_OBJ_INIT_4ARGS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_atomic_plane_enabling.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_atomic_plane_enabling.m4 new file mode 100644 index 0000000000000..5fe466630d8dd --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_atomic_plane_enabling.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v6.2-rc6-1230-g169b9182f192 +dnl # drm/atomic-helper: Add atomic_enable plane-helper callback +dnl # +AC_DEFUN([AC_AMDGPU_DRM_ATOMIC_PLANE_ENABLING], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + drm_atomic_plane_enabling(NULL, NULL); + ], [ + AC_DEFINE(HAVE_DRM_ATOMIC_PLANE_ENABLING, 1, + [drm_atomic_plane_enabling() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 5581b3dbffb12..059cb91e908e1 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -92,6 +92,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DP_MST_TOPOLOGY AC_AMDGPU_DRM_DP_MST_TOPOLOGY_CBS AC_AMDGPU_DRM_ATOMIC_PRIVATE_OBJ_INIT + AC_AMDGPU_DRM_ATOMIC_PLANE_ENABLING AC_AMDGPU_STRUCT_DRM_PLANE_HELPER_FUNCS AC_AMDGPU_DRM_DP_MST_ATOMIC_CHECK AC_AMDGPU_DRM_DP_MST_ATOMIC_ENABLE_DSC diff --git a/include/kcl/kcl_drm_atomic_helper.h b/include/kcl/kcl_drm_atomic_helper.h index 7bedeace08ad0..3af6d075cbe99 100644 --- a/include/kcl/kcl_drm_atomic_helper.h +++ b/include/kcl/kcl_drm_atomic_helper.h @@ -58,4 +58,20 @@ void __drm_atomic_helper_crtc_reset(struct drm_crtc *crtc, void drm_atomic_helper_calc_timestamping_constants(struct drm_atomic_state *state); #endif +#ifndef HAVE_DRM_ATOMIC_PLANE_ENABLING +static inline bool drm_atomic_plane_enabling(struct drm_plane_state *old_plane_state, + struct drm_plane_state *new_plane_state) +{ + /* + * When enabling a plane, CRTC and FB should always be set together. + * Anything else should be considered a bug in the atomic core, so we + * gently warn about it. + */ + WARN_ON((!new_plane_state->crtc && new_plane_state->fb) || + (new_plane_state->crtc && !new_plane_state->fb)); + + return !old_plane_state->crtc && new_plane_state->crtc; +} +#endif + #endif From 80789707ee1c1e6d6a6a91e6c4fea4e3ac797c55 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Mon, 17 Jun 2024 14:41:40 -0400 Subject: [PATCH 1242/1868] drm/amdkfd: remove gfx(9, 4, 1) pc sampling support Since it is not stable on stress test. Signed-off-by: James Zhu Reviewed-by: Felix Kuehling Reviewed-by: Vladimir Indic Tested-by: Vladimir Indic --- drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index 72042277cc2b8..de91e4e53df6a 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -36,7 +36,6 @@ const struct kfd_pc_sample_info sample_info_hosttrap_9_0_0 = { 0, 1, ~0ULL, 0, KFD_IOCTL_PCS_METHOD_HOSTTRAP, KFD_IOCTL_PCS_TYPE_TIME_US }; struct supported_pc_sample_info supported_formats[] = { - { IP_VERSION(9, 4, 1), &sample_info_hosttrap_9_0_0 }, { IP_VERSION(9, 4, 2), &sample_info_hosttrap_9_0_0 }, }; From 7298a559a3ae8292357cd5dbc6ec36b7e752476d Mon Sep 17 00:00:00 2001 From: James Zhu Date: Mon, 17 Jun 2024 15:12:30 -0400 Subject: [PATCH 1243/1868] drm/amdkfd: use version field to pass back pc sampling revision temporarily not for upstream. -v2: fix typo -v3: rename kfd_ioctl_pc_sample_args "reserved" to "version" Signed-off-by: James Zhu Reviewed-by: Felix Kuehling Reviewed-by: Vladimir Indic Tested-by: Vladimir Indic --- drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 11 +++++++++++ include/uapi/linux/kfd_ioctl.h | 2 +- 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index de91e4e53df6a..435ebba8c0de7 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -27,6 +27,14 @@ #include "kfd_debug.h" #include "kfd_device_queue_manager.h" +/* + * PC Sampling revision change log + * + * 0.1 - Initial revision + */ +#define KFD_IOCTL_PCS_MAJOR_VERSION 0 +#define KFD_IOCTL_PCS_MINOR_VERSION 1 + struct supported_pc_sample_info { uint32_t ip_version; const struct kfd_pc_sample_info *sample_info; @@ -142,6 +150,9 @@ static int kfd_pc_sample_query_cap(struct kfd_process_device *pdd, int i; const uint32_t user_num_sample_info = user_args->num_sample_info; + /* use version field to pass back pc sampling revision temporarily, not for upstream */ + user_args->version = KFD_IOCTL_PCS_MAJOR_VERSION << 16 | KFD_IOCTL_PCS_MINOR_VERSION; + for (i = 0; i < ARRAY_SIZE(supported_formats); i++) if (KFD_GC_VERSION(pdd->dev) == supported_formats[i].ip_version) num_method++; diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h index 9798594ea3f37..2b68c0c17313b 100644 --- a/include/uapi/linux/kfd_ioctl.h +++ b/include/uapi/linux/kfd_ioctl.h @@ -1636,7 +1636,7 @@ struct kfd_ioctl_pc_sample_args { __u32 gpu_id; __u32 trace_id; __u32 flags; /* kfd_ioctl_pcs_query flags */ - __u32 reserved; + __u32 version; }; #define AMDKFD_IOCTL_BASE 'K' From f06d5a340925339d9d741658e997a500f278246b Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 20 Jun 2024 17:46:17 +0800 Subject: [PATCH 1244/1868] drm/ttm: cleanup macro TTM_BO_VM_NUM_PREFAULT For fix intree build issue, cleanup the redefined macro TTM_BO_VM_NUM_PREFAULT included by old kcl patch. Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- include/drm/ttm/ttm_bo.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/include/drm/ttm/ttm_bo.h b/include/drm/ttm/ttm_bo.h index d7d772e160110..3ea0f0a7b0c93 100644 --- a/include/drm/ttm/ttm_bo.h +++ b/include/drm/ttm/ttm_bo.h @@ -425,9 +425,6 @@ int ttm_mem_evict_first(struct ttm_device *bdev, struct ttm_operation_ctx *ctx, struct ww_acquire_ctx *ticket); -/* Default number of pre-faulted pages in the TTM fault handler */ -#define TTM_BO_VM_NUM_PREFAULT 16 - vm_fault_t ttm_bo_vm_reserve(struct ttm_buffer_object *bo, struct vm_fault *vmf); vm_fault_t ttm_bo_vm_fault_reserved(struct vm_fault *vmf, From fa2aab75129c648e59e94bea2a86df4bd9f59138 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 26 Jun 2024 11:06:09 +0800 Subject: [PATCH 1245/1868] drm/amdkcl: wrap code under macro HAVE_KFIFO_PUT_NON_POINTER It's caused by 1470f94093b4b2ba5760b18fbd0e105b862af165 "drm/amdgpu: add gpu reset check and exception handling" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index bb61f68c3818e..dbfc41ddc3c71 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -3019,6 +3019,7 @@ static int amdgpu_ras_poison_creation_handler(struct amdgpu_device *adev, return 0; } +#ifdef HAVE_KFIFO_PUT_NON_POINTER static void amdgpu_ras_clear_poison_fifo(struct amdgpu_device *adev) { struct amdgpu_ras *con = amdgpu_ras_get_context(adev); @@ -3073,6 +3074,7 @@ static int amdgpu_ras_poison_consumption_handler(struct amdgpu_device *adev, return 0; } +#endif static int amdgpu_ras_page_retirement_thread(void *param) { From 8f35d682d8a0d4d135fa3d26c782804d6d5bfdb1 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 13 Jun 2024 13:28:41 +0800 Subject: [PATCH 1246/1868] drm/amdkcl: fake macros DP_LINK_BW_{10/13_5/20} It's caused by 13ba1f22181d90f4d62f9103351581b94d2442b2 "drm/amd/display: Refactor function dm_dp_mst_is_port_support_mode()" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- include/kcl/kcl_drm_dp.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/include/kcl/kcl_drm_dp.h b/include/kcl/kcl_drm_dp.h index 25c848be0df94..7f3607f89c6a4 100644 --- a/include/kcl/kcl_drm_dp.h +++ b/include/kcl/kcl_drm_dp.h @@ -76,4 +76,12 @@ #define DP_TEST_264BIT_CUSTOM_PATTERN_263_256 0X2250 #endif +/* v5.9-rc5-1031-g7d56927efac7 * + * drm/dp: add a number of DP 2.0 DPCD definitions */ +#ifndef DP_LINK_BW_10 +#define DP_LINK_BW_10 0x01 /* 2.0 128b/132b Link Layer */ +#define DP_LINK_BW_13_5 0x04 /* 2.0 128b/132b Link Layer */ +#define DP_LINK_BW_20 0x02 /* 2.0 128b/132b Link Layer */ +#endif + #endif \ No newline at end of file From dc10476f8addb77309cfb181d2a8b2c620546377 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 27 Jun 2024 16:46:37 +0800 Subject: [PATCH 1247/1868] drm/amdkcl: wrap code under macro HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS It's caused by 583ed0fe6bff86af2ce28a451f31cfa0c36013d1 "drm/amd/display: Introduce overlay cursor mode" Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 6e9721994a018..15fb1ae47a05d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -1359,8 +1359,12 @@ static int amdgpu_dm_plane_atomic_async_check(struct drm_plane *plane, if (plane->type != DRM_PLANE_TYPE_CURSOR) return -EINVAL; +#ifdef HAVE_STRUCT_DRM_PLANE_HELPER_FUNCS_ATOMIC_CHECK_DRM_ATOMIC_STATE_PARAMS new_plane_state = drm_atomic_get_new_plane_state(state, plane); new_crtc_state = drm_atomic_get_new_crtc_state(state, new_plane_state->crtc); +#else + new_crtc_state = drm_atomic_get_new_crtc_state(state->state, state->crtc); +#endif dm_new_crtc_state = to_dm_crtc_state(new_crtc_state); /* Reject overlay cursors for now*/ if (dm_new_crtc_state->cursor_mode == DM_CURSOR_OVERLAY_MODE) From 04f66c20ce49ab44f6dd7266a5177da3f93cdf87 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 1 Jul 2024 16:28:43 +0800 Subject: [PATCH 1248/1868] drm/amdkcl: wrap code under macro HAVE_DRM_DISPLAY_INFO_MONITOR_RANGE It's caused by f12e6db4a019bcb24dc99a909534dec35bcdd408 "drm/amd/display: Fix refresh rate range for some panel" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++++ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 2 -- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index b186f01a514a4..18201a2b44251 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -12146,6 +12146,7 @@ static bool parse_edid_cea(struct amdgpu_dm_connector *aconnector, return ret; } +#ifdef HAVE_DRM_DISPLAY_INFO_MONITOR_RANGE static void parse_edid_displayid_vrr(struct drm_connector *connector, struct edid *edid) { @@ -12188,6 +12189,7 @@ static void parse_edid_displayid_vrr(struct drm_connector *connector, j++; } } +#endif static int parse_amd_vsdb(struct amdgpu_dm_connector *aconnector, struct edid *edid, struct amdgpu_hdmi_vsdb_info *vsdb_info) @@ -12311,10 +12313,12 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, if (!adev->dm.freesync_module) goto update; +#ifdef HAVE_DRM_DISPLAY_INFO_MONITOR_RANGE /* Some eDP panels only have the refresh rate range info in DisplayID */ if ((connector->display_info.monitor_range.min_vfreq == 0 || connector->display_info.monitor_range.max_vfreq == 0)) parse_edid_displayid_vrr(connector, edid); +#endif if (edid && (sink->sink_signal == SIGNAL_TYPE_DISPLAY_PORT || sink->sink_signal == SIGNAL_TYPE_EDP)) { diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 15fb1ae47a05d..68d546ad61b09 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -166,12 +166,10 @@ static void amdgpu_dm_plane_add_modifier(uint64_t **mods, uint64_t *size, uint64 *size += 1; } -#ifdef HAVE_DRM_FORMAT_INFO_MODIFIER_SUPPORTED static bool amdgpu_dm_plane_modifier_has_dcc(uint64_t modifier) { return IS_AMD_FMT_MOD(modifier) && AMD_FMT_MOD_GET(DCC, modifier); } -#endif static unsigned int amdgpu_dm_plane_modifier_gfx9_swizzle_mode(uint64_t modifier) { From 788bbe2582fdb7201b6f8a7f3ca8b3cbac7d62f3 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 1 Jul 2024 16:27:27 +0800 Subject: [PATCH 1249/1868] drm/amdkcl: fake macro AMD_FMT_MOD_TILE_GFX12_* It's caused by 2146fa1d796c804c337ea2fee8f2628bda4eb2ab "drm/amdgpu/display: add all gfx12 modifiers" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- include/kcl/kcl_drm_fourcc.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/include/kcl/kcl_drm_fourcc.h b/include/kcl/kcl_drm_fourcc.h index 9b1a99ec6d52b..cc36737aafae0 100644 --- a/include/kcl/kcl_drm_fourcc.h +++ b/include/kcl/kcl_drm_fourcc.h @@ -233,4 +233,13 @@ #define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */ #endif +#ifndef AMD_FMT_MOD_TILE_GFX12_256B_2D +#define AMD_FMT_MOD_TILE_GFX12_256B_2D 1 +#define AMD_FMT_MOD_TILE_GFX12_4K_2D 2 +#endif + +#ifndef AMD_FMT_MOD_TILE_GFX12_256K_2D +#define AMD_FMT_MOD_TILE_GFX12_256K_2D 4 +#endif + #endif /* KCL_KCL_DRM_FOURCC_H */ From e2d19d574dac34dda957a42ee074ed100a849695 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Tue, 25 Jun 2024 11:00:46 +0530 Subject: [PATCH 1250/1868] drm/amd/pm: Add phase detect control support Add support to tune phase detect parameters. Signed-off-by: Lijo Lazar Reviewed-by: Hawking Zhang --- .../gpu/drm/amd/include/kgd_pp_interface.h | 9 ++++ drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 53 +++++++++++++++++++ drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 35 ++++++++++++ 3 files changed, 97 insertions(+) diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h index 19a48d98830a3..79020d17ac784 100644 --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h @@ -291,6 +291,15 @@ enum pp_policy_soc_pstate { #define PP_POLICY_MAX_LEVELS 5 +enum pp_pm_phase_det_param_id { + PP_PM_PHASE_DET_LO_FREQ = 0, + PP_PM_PHASE_DET_HI_FREQ = 1, + PP_PM_PHASE_DET_THRESH = 2, + PP_PM_PHASE_DET_ALPHA = 3, + PP_PM_PHASE_DET_HYST = 4, + PP_PM_PHASE_DET_ALL = 5, +}; + #define PP_GROUP_MASK 0xF0000000 #define PP_GROUP_SHIFT 28 diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 9d7454b3c3143..5007f03da1198 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -3818,3 +3818,56 @@ int smu_send_rma_reason(struct smu_context *smu) return ret; } + +int smu_set_phase_det_param(struct smu_context *smu, + enum pp_pm_phase_det_param_id id, uint32_t val) +{ + struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; + struct smu_phase_det_ctl *pd_ctl; + + pd_ctl = dpm_ctxt->pd_ctl; + if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !pd_ctl) + return -EOPNOTSUPP; + + if (!pd_ctl->ops || !pd_ctl->ops->set) + return -EOPNOTSUPP; + + if (pd_ctl->status == SMU_PHASE_DET_DISABLED) + return -EPERM; + + return pd_ctl->ops->set(smu, id, val); +} + +int smu_get_phase_det_param(struct smu_context *smu, + enum pp_pm_phase_det_param_id id, uint32_t *val) +{ + struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; + struct smu_phase_det_ctl *pd_ctl; + + pd_ctl = dpm_ctxt->pd_ctl; + if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !pd_ctl) + return -EOPNOTSUPP; + + if (!pd_ctl->ops || !pd_ctl->ops->get) + return -EOPNOTSUPP; + + return pd_ctl->ops->get(smu, id, val); +} + +int smu_phase_det_enable(struct smu_context *smu, bool enable) +{ + struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; + struct smu_phase_det_ctl *pd_ctl; + + pd_ctl = dpm_ctxt->pd_ctl; + if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !pd_ctl) + return -EOPNOTSUPP; + + if (!pd_ctl->ops || !pd_ctl->ops->enable) + return -EOPNOTSUPP; + + if (pd_ctl->status == SMU_PHASE_DET_DISABLED) + return -EPERM; + + return pd_ctl->ops->enable(smu, enable); +} diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h index b44a185d07e84..e3a4262b5d690 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h @@ -383,6 +383,34 @@ struct smu_dpm_policy_ctxt { unsigned long policy_mask; }; +struct smu_phase_det_params { + uint32_t freq_hi; + uint32_t freq_lo; + uint32_t thresh; + uint32_t hyst; + uint32_t alpha; +}; + +struct smu_phase_det_ops { + int (*set)(struct smu_context *smu, enum pp_pm_phase_det_param_id id, + uint32_t val); + int (*get)(struct smu_context *smu, enum pp_pm_phase_det_param_id id, + uint32_t *val); + int (*enable)(struct smu_context *smu, bool enable); +}; + +enum phase_det_state { + SMU_PHASE_DET_OFF = 0, + SMU_PHASE_DET_ON = 1, + SMU_PHASE_DET_DISABLED = -1, +}; + +struct smu_phase_det_ctl { + struct smu_phase_det_params params; + struct smu_phase_det_ops *ops; + enum phase_det_state status; +}; + struct smu_dpm_context { uint32_t dpm_context_size; void *dpm_context; @@ -394,6 +422,7 @@ struct smu_dpm_context { struct smu_power_state *dpm_current_power_state; struct mclock_latency_table *mclk_latency_table; struct smu_dpm_policy_ctxt *dpm_policies; + struct smu_phase_det_ctl *pd_ctl; }; struct smu_power_gate { @@ -1635,5 +1664,11 @@ int smu_set_pm_policy(struct smu_context *smu, enum pp_pm_policy p_type, ssize_t smu_get_pm_policy_info(struct smu_context *smu, enum pp_pm_policy p_type, char *sysbuf); +int smu_set_phase_det_param(struct smu_context *smu, + enum pp_pm_phase_det_param_id id, uint32_t val); +int smu_get_phase_det_param(struct smu_context *smu, + enum pp_pm_phase_det_param_id id, uint32_t *val); +int smu_phase_det_enable(struct smu_context *smu, bool enable); + #endif #endif From 77ab771fa793b29417cb00e4ea63e04f89bba8df Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Tue, 25 Jun 2024 16:35:36 +0530 Subject: [PATCH 1251/1868] drm/amd/pm: Add debugfs controls for phase detect Add debugfs nodes for enabling/disabling and tuning parameters used in phase detect. Signed-off-by: Lijo Lazar Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/pm/amdgpu_dpm.c | 8 ++ drivers/gpu/drm/amd/pm/amdgpu_pm.c | 1 + drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h | 1 + drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 96 +++++++++++++++++++ drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 1 + 5 files changed, 107 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c index 9dc82f4d7c937..10fd51553f68a 100644 --- a/drivers/gpu/drm/amd/pm/amdgpu_dpm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_dpm.c @@ -1884,3 +1884,11 @@ int amdgpu_dpm_get_dpm_clock_table(struct amdgpu_device *adev, return ret; } + +void amdgpu_dpm_phase_det_debugfs_init(struct amdgpu_device *adev) +{ + if (!is_support_sw_smu(adev)) + return; + + amdgpu_smu_phase_det_debugfs_init(adev); +} diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c index 847f678f1cc8c..8263e62023936 100644 --- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c +++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c @@ -4844,5 +4844,6 @@ void amdgpu_debugfs_pm_init(struct amdgpu_device *adev) adev->pm.smu_prv_buffer_size); amdgpu_dpm_stb_debug_fs_init(adev); + amdgpu_dpm_phase_det_debugfs_init(adev); #endif } diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h index f5bf41f21c412..618d56d9e005e 100644 --- a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h +++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h @@ -597,5 +597,6 @@ int amdgpu_dpm_set_pm_policy(struct amdgpu_device *adev, int policy_type, int policy_level); ssize_t amdgpu_dpm_get_pm_policy_info(struct amdgpu_device *adev, enum pp_pm_policy p_type, char *buf); +void amdgpu_dpm_phase_det_debugfs_init(struct amdgpu_device *adev); #endif diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 5007f03da1198..28415d1c54560 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -3871,3 +3871,99 @@ int smu_phase_det_enable(struct smu_context *smu, bool enable) return pd_ctl->ops->enable(smu, enable); } + +#if defined(CONFIG_DEBUG_FS) + +static int smu_phase_det_debugfs_status(void *data, u64 *val) +{ + struct smu_context *smu = (struct smu_context *)data; + struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; + struct smu_phase_det_ctl *pd_ctl; + + pd_ctl = dpm_ctxt->pd_ctl; + + *val = pd_ctl->status; + + return 0; +} + +static int smu_phase_det_debugfs_enable(void *data, u64 val) +{ + struct smu_context *smu = (struct smu_context *)data; + struct amdgpu_device *adev = smu->adev; + + if (amdgpu_in_reset(adev) || adev->in_suspend) + return -EPERM; + + return smu_phase_det_enable(smu, !!val); +} + +#define DEBUGFS_PHASE_DET_FOPS(param) \ + static int smu_phase_det_fops_##param##_get(void *data, u64 *val) \ + { \ + struct smu_context *smu = (struct smu_context *)data; \ + int r; \ + u32 v; \ + \ + r = smu_get_phase_det_param(smu, PP_PM_PHASE_DET_##param, &v); \ + *val = v; \ + return r; \ + } \ + \ + static int smu_phase_det_fops_##param##_set(void *data, u64 val) \ + { \ + struct smu_context *smu = (struct smu_context *)data; \ + struct amdgpu_device *adev = smu->adev; \ + \ + if (amdgpu_in_reset(adev) || adev->in_suspend) \ + return -EPERM; \ + \ + return smu_set_phase_det_param(smu, PP_PM_PHASE_DET_##param, \ + (u32)val); \ + } \ + DEFINE_DEBUGFS_ATTRIBUTE(smu_phase_det_fops_##param, \ + smu_phase_det_fops_##param##_get, \ + smu_phase_det_fops_##param##_set, "%llu\n") + +DEBUGFS_PHASE_DET_FOPS(LO_FREQ); +DEBUGFS_PHASE_DET_FOPS(HI_FREQ); +DEBUGFS_PHASE_DET_FOPS(THRESH); +DEBUGFS_PHASE_DET_FOPS(ALPHA); +DEBUGFS_PHASE_DET_FOPS(HYST); + +DEFINE_DEBUGFS_ATTRIBUTE(smu_phase_det_fops_en, smu_phase_det_debugfs_status, + smu_phase_det_debugfs_enable, "%llu\n"); + +#define DEBUGFS_CREATE_PHASE_DET_ATTR(name, param) \ + debugfs_create_file(#name, 0644, dir, smu, &smu_phase_det_fops_##param) + +#define AMDGPU_SMU_PHASE_DET "smu_phase_detect" +#endif + +void amdgpu_smu_phase_det_debugfs_init(struct amdgpu_device *adev) +{ +#if defined(CONFIG_DEBUG_FS) + + struct smu_context *smu = adev->powerplay.pp_handle; + struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; + struct smu_phase_det_ctl *pd_ctl; + struct dentry *dir; + + pd_ctl = dpm_ctxt->pd_ctl; + + if (!smu || !pd_ctl) + return; + + dir = debugfs_create_dir(AMDGPU_SMU_PHASE_DET, + adev_to_drm(adev)->primary->debugfs_root); + + debugfs_create_file("enable", 0644, dir, smu, &smu_phase_det_fops_en); + + DEBUGFS_CREATE_PHASE_DET_ATTR(freq_lo, LO_FREQ); + DEBUGFS_CREATE_PHASE_DET_ATTR(freq_hi, HI_FREQ); + DEBUGFS_CREATE_PHASE_DET_ATTR(threshold, THRESH); + DEBUGFS_CREATE_PHASE_DET_ATTR(alpha, ALPHA); + DEBUGFS_CREATE_PHASE_DET_ATTR(hyst, HYST); + +#endif +} diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h index e3a4262b5d690..5812d203bca75 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h @@ -1669,6 +1669,7 @@ int smu_set_phase_det_param(struct smu_context *smu, int smu_get_phase_det_param(struct smu_context *smu, enum pp_pm_phase_det_param_id id, uint32_t *val); int smu_phase_det_enable(struct smu_context *smu, bool enable); +void amdgpu_smu_phase_det_debugfs_init(struct amdgpu_device *adev); #endif #endif From 41564d34cecb8d84f3d6f6b958ec2db8c9f788c2 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Wed, 26 Jun 2024 13:15:32 +0530 Subject: [PATCH 1252/1868] drm/amd/pm: Add phase detect support to SMUv13.0.6 Add support for enabling phase detect and tuning params for SMUv13.0.6 SOCs. Signed-off-by: Lijo Lazar Reviewed-by: Hawking Zhang --- .../pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h | 8 +- drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h | 8 +- .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 1 + .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 148 ++++++++++++++++++ 4 files changed, 163 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h index 41cb681927e2f..f3dcc53f583d2 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h @@ -93,7 +93,13 @@ #define PPSMC_MSG_SelectPLPDMode 0x40 #define PPSMC_MSG_RmaDueToBadPageThreshold 0x43 #define PPSMC_MSG_SelectPstatePolicy 0x44 -#define PPSMC_Message_Count 0x45 +#define PPSMC_MSG_SetPhsDetWRbwThreshold 0x45 +#define PPSMC_MSG_SetPhsDetWRbwFreqHigh 0x46 +#define PPSMC_MSG_SetPhsDetWRbwFreqLow 0x47 +#define PPSMC_MSG_SetPhsDetWRbwHystDown 0x48 +#define PPSMC_MSG_SetPhsDetWRbwAlpha 0x49 +#define PPSMC_MSG_SetPhsDetOnOff 0x4A +#define PPSMC_Message_Count 0x4B //PPSMC Reset Types for driver msg argument #define PPSMC_RESET_TYPE_DRIVER_MODE_1_RESET 0x1 diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h index ac0dd6b97f8d5..2ad96aef057b4 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h @@ -275,7 +275,13 @@ __SMU_DUMMY_MAP(RmaDueToBadPageThreshold), \ __SMU_DUMMY_MAP(SelectPstatePolicy), \ __SMU_DUMMY_MAP(MALLPowerController), \ - __SMU_DUMMY_MAP(MALLPowerState), + __SMU_DUMMY_MAP(MALLPowerState), \ + __SMU_DUMMY_MAP(SetPhsDetWRbwThreshold), \ + __SMU_DUMMY_MAP(SetPhsDetWRbwFreqHigh), \ + __SMU_DUMMY_MAP(SetPhsDetWRbwFreqLow), \ + __SMU_DUMMY_MAP(SetPhsDetWRbwHystDown), \ + __SMU_DUMMY_MAP(SetPhsDetWRbwAlpha), \ + __SMU_DUMMY_MAP(SetPhsDetOnOff), #undef __SMU_DUMMY_MAP #define __SMU_DUMMY_MAP(type) SMU_MSG_##type diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c index 3e2dab43832ad..48f448b9bc4f5 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c @@ -527,6 +527,7 @@ int smu_v13_0_fini_smc_tables(struct smu_context *smu) smu_table->watermarks_table = NULL; smu_table->metrics_time = 0; + kfree(smu_dpm->pd_ctl); kfree(smu_dpm->dpm_policies); kfree(smu_dpm->dpm_context); kfree(smu_dpm->golden_dpm_context); diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index 78c3f94bb3ff6..4fe643b090f87 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -175,6 +175,12 @@ static const struct cmn2asic_msg_mapping smu_v13_0_6_message_map[SMU_MSG_MAX_COU MSG_MAP(SelectPLPDMode, PPSMC_MSG_SelectPLPDMode, 0), MSG_MAP(RmaDueToBadPageThreshold, PPSMC_MSG_RmaDueToBadPageThreshold, 0), MSG_MAP(SelectPstatePolicy, PPSMC_MSG_SelectPstatePolicy, 0), + MSG_MAP(SetPhsDetWRbwThreshold, PPSMC_MSG_SetPhsDetWRbwThreshold, 0), + MSG_MAP(SetPhsDetWRbwFreqHigh, PPSMC_MSG_SetPhsDetWRbwFreqHigh, 0), + MSG_MAP(SetPhsDetWRbwFreqLow, PPSMC_MSG_SetPhsDetWRbwFreqLow, 0), + MSG_MAP(SetPhsDetWRbwHystDown, PPSMC_MSG_SetPhsDetWRbwHystDown, 0), + MSG_MAP(SetPhsDetWRbwAlpha, PPSMC_MSG_SetPhsDetWRbwAlpha, 0), + MSG_MAP(SetPhsDetOnOff, PPSMC_MSG_SetPhsDetOnOff, 0), }; // clang-format on @@ -434,6 +440,112 @@ static int smu_v13_0_6_select_plpd_policy(struct smu_context *smu, int level) return ret; } +static int smu_v13_0_6_phase_det_set(struct smu_context *smu, + enum pp_pm_phase_det_param_id id, + uint32_t val) +{ + struct smu_dpm_context *smu_dpm = &smu->smu_dpm; + struct smu_phase_det_ctl *pd_ctl; + uint32_t *param; + int r, msg_id; + + pd_ctl = smu_dpm->pd_ctl; + if (!pd_ctl) + return -EINVAL; + + switch (id) { + case PP_PM_PHASE_DET_LO_FREQ: + msg_id = SMU_MSG_SetPhsDetWRbwFreqLow; + param = &pd_ctl->params.freq_lo; + break; + case PP_PM_PHASE_DET_HI_FREQ: + msg_id = SMU_MSG_SetPhsDetWRbwFreqHigh; + param = &pd_ctl->params.freq_hi; + break; + case PP_PM_PHASE_DET_THRESH: + msg_id = SMU_MSG_SetPhsDetWRbwThreshold; + param = &pd_ctl->params.thresh; + break; + case PP_PM_PHASE_DET_ALPHA: + msg_id = SMU_MSG_SetPhsDetWRbwAlpha; + param = &pd_ctl->params.alpha; + break; + case PP_PM_PHASE_DET_HYST: + msg_id = SMU_MSG_SetPhsDetWRbwHystDown; + param = &pd_ctl->params.hyst; + break; + default: + return -EINVAL; + } + + r = smu_cmn_send_smc_msg_with_param(smu, msg_id, val, NULL); + if (!r) + *param = val; + + return r; +} + +static int smu_v13_0_6_phase_det_get(struct smu_context *smu, + enum pp_pm_phase_det_param_id id, + uint32_t *val) +{ + struct smu_dpm_context *smu_dpm = &smu->smu_dpm; + struct smu_phase_det_ctl *pd_ctl; + + pd_ctl = smu_dpm->pd_ctl; + if (!pd_ctl || !val) + return -EINVAL; + + switch (id) { + case PP_PM_PHASE_DET_LO_FREQ: + *val = pd_ctl->params.freq_lo; + break; + case PP_PM_PHASE_DET_HI_FREQ: + *val = pd_ctl->params.freq_hi; + break; + case PP_PM_PHASE_DET_THRESH: + *val = pd_ctl->params.thresh; + break; + case PP_PM_PHASE_DET_ALPHA: + *val = pd_ctl->params.alpha; + break; + case PP_PM_PHASE_DET_HYST: + *val = pd_ctl->params.hyst; + break; + default: + return -EINVAL; + } + + return 0; +} + +static int smu_v13_0_6_phase_det_enable(struct smu_context *smu, bool enable) +{ + struct smu_dpm_context *smu_dpm = &smu->smu_dpm; + struct smu_phase_det_ctl *pd_ctl; + int r; + + pd_ctl = smu_dpm->pd_ctl; + r = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetPhsDetOnOff, enable, + NULL); + + if (!r) { + pd_ctl->status = enable ? SMU_PHASE_DET_ON : SMU_PHASE_DET_OFF; + } else { + dev_warn(smu->adev->dev, "Phase detect %s failed", + enable ? "enable" : "disable"); + pd_ctl->status = SMU_PHASE_DET_DISABLED; + } + + return r; +} + +static struct smu_phase_det_ops smu_v13_0_6_pd_ops = { + .set = smu_v13_0_6_phase_det_set, + .get = smu_v13_0_6_phase_det_get, + .enable = smu_v13_0_6_phase_det_enable, +}; + static int smu_v13_0_6_allocate_dpm_context(struct smu_context *smu) { struct smu_dpm_context *smu_dpm = &smu->smu_dpm; @@ -452,6 +564,17 @@ static int smu_v13_0_6_allocate_dpm_context(struct smu_context *smu) return -ENOMEM; } + smu_dpm->pd_ctl = kzalloc(sizeof(struct smu_phase_det_ctl), GFP_KERNEL); + if (!smu_dpm->pd_ctl) { + kfree(smu_dpm->dpm_policies); + kfree(smu_dpm->dpm_context); + return -ENOMEM; + } + smu_dpm->pd_ctl->ops = &smu_v13_0_6_pd_ops; + smu_dpm->pd_ctl->status = SMU_PHASE_DET_OFF; + /* Init to 0xFF to indicate that present values are unknown */ + memset(&smu_dpm->pd_ctl->params, 0xFF, sizeof(struct smu_phase_det_params)); + if (!(smu->adev->flags & AMD_IS_APU)) { policy = &(smu_dpm->dpm_policies->policies[0]); @@ -749,6 +872,7 @@ static int smu_v13_0_6_set_default_dpm_table(struct smu_context *smu) struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context; struct smu_table_context *smu_table = &smu->smu_table; struct smu_13_0_dpm_table *dpm_table = NULL; + struct smu_dpm_context *smu_dpm = &smu->smu_dpm; struct PPTable_t *pptable = (struct PPTable_t *)smu_table->driver_pptable; uint32_t gfxclkmin, gfxclkmax, levels; @@ -782,6 +906,12 @@ static int smu_v13_0_6_set_default_dpm_table(struct smu_context *smu) ~BIT(PP_PM_POLICY_SOC_PSTATE); } + if (smu_dpm->pd_ctl && !(smu->adev->flags & AMD_IS_APU) && + (smu->smc_fw_version < 0x00556E00)) { + kfree(smu_dpm->pd_ctl); + smu_dpm->pd_ctl = NULL; + } + smu_v13_0_6_pm_policy_init(smu); /* gfxclk dpm table setup */ dpm_table = &dpm_context->dpm_tables.gfx_table; @@ -2638,6 +2768,23 @@ static int smu_v13_0_6_send_rma_reason(struct smu_context *smu) return ret; } +static int smu_v13_0_6_post_init(struct smu_context *smu) +{ + struct smu_dpm_context *smu_dpm = &smu->smu_dpm; + struct smu_phase_det_ctl *pd_ctl; + bool enable; + + pd_ctl = smu_dpm->pd_ctl; + + if (!pd_ctl || pd_ctl->status == SMU_PHASE_DET_DISABLED) + return 0; + + enable = (pd_ctl->status == SMU_PHASE_DET_ON) ? true : false; + smu_v13_0_6_phase_det_enable(smu, enable); + + return 0; +} + static int mca_smu_set_debug_mode(struct amdgpu_device *adev, bool enable) { struct smu_context *smu = adev->powerplay.pp_handle; @@ -3283,6 +3430,7 @@ static const struct pptable_funcs smu_v13_0_6_ppt_funcs = { .i2c_fini = smu_v13_0_6_i2c_control_fini, .send_hbm_bad_pages_num = smu_v13_0_6_smu_send_hbm_bad_page_num, .send_rma_reason = smu_v13_0_6_send_rma_reason, + .post_init = smu_v13_0_6_post_init, }; void smu_v13_0_6_set_ppt_funcs(struct smu_context *smu) From 82cd5498da83f632d80e44f597e795c5a71ffbea Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 8 Jul 2024 16:14:55 +0800 Subject: [PATCH 1253/1868] drm/amdkcl: wrap code under macro DEFINE_DEBUGFS_ATTRIBUTE It's caused by 4134c8ebf636e6d2d5b43c1a246b21d833bf9651 "drm/amd/pm: Add debugfs controls for phase detect" Signed-off-by: Bob Zhou Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 34 +++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 28415d1c54560..bc8faa9d53e8f 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -3898,6 +3898,7 @@ static int smu_phase_det_debugfs_enable(void *data, u64 val) return smu_phase_det_enable(smu, !!val); } +#ifdef DEFINE_DEBUGFS_ATTRIBUTE #define DEBUGFS_PHASE_DET_FOPS(param) \ static int smu_phase_det_fops_##param##_get(void *data, u64 *val) \ { \ @@ -3924,6 +3925,34 @@ static int smu_phase_det_debugfs_enable(void *data, u64 val) DEFINE_DEBUGFS_ATTRIBUTE(smu_phase_det_fops_##param, \ smu_phase_det_fops_##param##_get, \ smu_phase_det_fops_##param##_set, "%llu\n") +#else +#define DEBUGFS_PHASE_DET_FOPS(param) \ + static int smu_phase_det_fops_##param##_get(void *data, u64 *val) \ + { \ + struct smu_context *smu = (struct smu_context *)data; \ + int r; \ + u32 v; \ + \ + r = smu_get_phase_det_param(smu, PP_PM_PHASE_DET_##param, &v); \ + *val = v; \ + return r; \ + } \ + \ + static int smu_phase_det_fops_##param##_set(void *data, u64 val) \ + { \ + struct smu_context *smu = (struct smu_context *)data; \ + struct amdgpu_device *adev = smu->adev; \ + \ + if (amdgpu_in_reset(adev) || adev->in_suspend) \ + return -EPERM; \ + \ + return smu_set_phase_det_param(smu, PP_PM_PHASE_DET_##param, \ + (u32)val); \ + } \ + DEFINE_SIMPLE_ATTRIBUTE(smu_phase_det_fops_##param, \ + smu_phase_det_fops_##param##_get, \ + smu_phase_det_fops_##param##_set, "%llu\n") +#endif DEBUGFS_PHASE_DET_FOPS(LO_FREQ); DEBUGFS_PHASE_DET_FOPS(HI_FREQ); @@ -3931,8 +3960,13 @@ DEBUGFS_PHASE_DET_FOPS(THRESH); DEBUGFS_PHASE_DET_FOPS(ALPHA); DEBUGFS_PHASE_DET_FOPS(HYST); +#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(smu_phase_det_fops_en, smu_phase_det_debugfs_status, smu_phase_det_debugfs_enable, "%llu\n"); +#else +DEFINE_SIMPLE_ATTRIBUTE(smu_phase_det_fops_en, smu_phase_det_debugfs_status, + smu_phase_det_debugfs_enable, "%llu\n"); +#endif #define DEBUGFS_CREATE_PHASE_DET_ATTR(name, param) \ debugfs_create_file(#name, 0644, dir, smu, &smu_phase_det_fops_##param) From f5b6440e82d574d8e8a1c4b8892b4f628822eef5 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Tue, 9 Jul 2024 17:45:27 +0530 Subject: [PATCH 1254/1868] drm/amd/pm: Restrict phase detect to SMUv13.0.6 Phase detect controls are only available for SMUv13.0.6 dGPUs. Create control object only on those. Signed-off-by: Lijo Lazar Reviewed-by: Feifei Xu Reviewed-by: Hawking Zhang --- .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 28 +++++++++++-------- 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index 4fe643b090f87..302783dd42829 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -564,17 +564,22 @@ static int smu_v13_0_6_allocate_dpm_context(struct smu_context *smu) return -ENOMEM; } - smu_dpm->pd_ctl = kzalloc(sizeof(struct smu_phase_det_ctl), GFP_KERNEL); - if (!smu_dpm->pd_ctl) { - kfree(smu_dpm->dpm_policies); - kfree(smu_dpm->dpm_context); - return -ENOMEM; - } - smu_dpm->pd_ctl->ops = &smu_v13_0_6_pd_ops; - smu_dpm->pd_ctl->status = SMU_PHASE_DET_OFF; - /* Init to 0xFF to indicate that present values are unknown */ - memset(&smu_dpm->pd_ctl->params, 0xFF, sizeof(struct smu_phase_det_params)); + if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 6) && + !(smu->adev->flags & AMD_IS_APU)) { + smu_dpm->pd_ctl = + kzalloc(sizeof(struct smu_phase_det_ctl), GFP_KERNEL); + if (!smu_dpm->pd_ctl) { + kfree(smu_dpm->dpm_policies); + kfree(smu_dpm->dpm_context); + return -ENOMEM; + } + smu_dpm->pd_ctl->ops = &smu_v13_0_6_pd_ops; + smu_dpm->pd_ctl->status = SMU_PHASE_DET_OFF; + /* Init to 0xFF to indicate that present values are unknown */ + memset(&smu_dpm->pd_ctl->params, 0xFF, + sizeof(struct smu_phase_det_params)); + } if (!(smu->adev->flags & AMD_IS_APU)) { policy = &(smu_dpm->dpm_policies->policies[0]); @@ -906,8 +911,7 @@ static int smu_v13_0_6_set_default_dpm_table(struct smu_context *smu) ~BIT(PP_PM_POLICY_SOC_PSTATE); } - if (smu_dpm->pd_ctl && !(smu->adev->flags & AMD_IS_APU) && - (smu->smc_fw_version < 0x00556E00)) { + if (smu_dpm->pd_ctl && (smu->smc_fw_version < 0x00556E00)) { kfree(smu_dpm->pd_ctl); smu_dpm->pd_ctl = NULL; } From 23ab0e79cf669550240f4f41273bb65696fd83d7 Mon Sep 17 00:00:00 2001 From: David Belanger Date: Tue, 2 Jul 2024 17:56:41 -0400 Subject: [PATCH 1255/1868] drm/amdgpu: Restore uncached behaviour on GFX12 Always use MTYPE_UC if UNCACHED flag is specified. This makes kernarg region uncached and it restores usermode cache disable debug flag functionality. Do not set MTYPE_UC for COHERENT flag, on GFX12 coherence is handled by shader code. Signed-off-by: David Belanger Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c | 21 ++------------------- drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 8 +------- 2 files changed, 3 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c index edcb5351f8cca..60acf676000b3 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c @@ -498,9 +498,6 @@ static void gmc_v12_0_get_vm_pte(struct amdgpu_device *adev, uint64_t *flags) { struct amdgpu_bo *bo = mapping->bo_va->base.bo; - struct amdgpu_device *bo_adev; - bool coherent, is_system; - *flags &= ~AMDGPU_PTE_EXECUTABLE; *flags |= mapping->flags & AMDGPU_PTE_EXECUTABLE; @@ -516,25 +513,11 @@ static void gmc_v12_0_get_vm_pte(struct amdgpu_device *adev, *flags &= ~AMDGPU_PTE_VALID; } - if (!bo) - return; - - if (bo->flags & (AMDGPU_GEM_CREATE_COHERENT | - AMDGPU_GEM_CREATE_UNCACHED)) - *flags = AMDGPU_PTE_MTYPE_GFX12(*flags, MTYPE_UC); - - bo_adev = amdgpu_ttm_adev(bo->tbo.bdev); - coherent = bo->flags & AMDGPU_GEM_CREATE_COHERENT; - is_system = (bo->tbo.resource->mem_type == TTM_PL_TT) || - (bo->tbo.resource->mem_type == AMDGPU_PL_PREEMPT); - if (bo && bo->flags & AMDGPU_GEM_CREATE_GFX12_DCC) *flags |= AMDGPU_PTE_DCC; - /* WA for HW bug */ - if (is_system || ((bo_adev != adev) && coherent)) - *flags = AMDGPU_PTE_MTYPE_GFX12(*flags, MTYPE_NC); - + if (bo && bo->flags & AMDGPU_GEM_CREATE_UNCACHED) + *flags = AMDGPU_PTE_MTYPE_GFX12(*flags, MTYPE_UC); } static unsigned gmc_v12_0_get_vbios_fb_size(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c index 47e128c728ff8..b55a0cce07fcf 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c @@ -1253,13 +1253,7 @@ svm_range_get_pte_flags(struct kfd_node *node, break; case IP_VERSION(12, 0, 0): case IP_VERSION(12, 0, 1): - if (domain == SVM_RANGE_VRAM_DOMAIN) { - if (bo_node != node) - mapping_flags |= AMDGPU_VM_MTYPE_NC; - } else { - mapping_flags |= coherent ? - AMDGPU_VM_MTYPE_UC : AMDGPU_VM_MTYPE_NC; - } + mapping_flags |= AMDGPU_VM_MTYPE_NC; break; default: mapping_flags |= coherent ? From 3ca18f42b5f69b2bcc4cfebef5992bf478e8c98b Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 18 Jul 2024 15:42:08 +0800 Subject: [PATCH 1256/1868] drm/amdkcl: cleanup dma-resv stuff Signed-off-by: Flora Cui Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c | 7 ++++--- drivers/gpu/drm/amd/dkms/pre-build.sh | 12 +++++------- 3 files changed, 10 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 90398c82f9c30..64dd31cf1bc84 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -2,7 +2,7 @@ amdkcl-y += main.o kcl_common.o amdkcl-y += kcl_kernel_params.o -amdkcl-y += dma-buf/dma-resv.o +amdkcl-y += dma-buf/dma-resv.o kcl_dma-resv.o amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_kthread.o kcl_io.o kcl_seq_file.o \ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c b/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c index dc92c2d10f23d..f2a2cdcbf3165 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_dma-resv.c @@ -32,6 +32,10 @@ /* * Authors: Thomas Hellstrom */ + +/* Copied from drivers/dma-buf/dma-resv.c */ +#ifndef HAVE_DMA_RESV_FENCES + #include #include #include @@ -41,9 +45,6 @@ #include #include -/* Copied from drivers/dma-buf/dma-resv.c */ -#ifndef HAVE_DMA_RESV_FENCES - /** * DOC: Reservation Object Overview * diff --git a/drivers/gpu/drm/amd/dkms/pre-build.sh b/drivers/gpu/drm/amd/dkms/pre-build.sh index 5f922ec16986c..ec0c41cd4411e 100755 --- a/drivers/gpu/drm/amd/dkms/pre-build.sh +++ b/drivers/gpu/drm/amd/dkms/pre-build.sh @@ -34,10 +34,12 @@ version_le () { source $KCL/files sed -i -e '/DEFINE_WD_CLASS(reservation_ww_class)/,/EXPORT_SYMBOL(reservation_ww_class)/d' \ - -e '/dma_resv_lockdep/,/subsys_initcall/d' $KCL/dma-buf/dma-resv.c + -e '/dma_resv_lockdep/,/subsys_initcall/d' \ + -e '1i\#ifdef HAVE_DMA_RESV_FENCES' \ + -e '$a\#endif' $KCL/dma-buf/dma-resv.c sed -i -e '/extern struct ww_class reservation_ww_class/i #include ' \ - -e '/struct dma_resv {/, /}/d' $INC/linux/dma-resv.h \ - -e '/struct dma_resv_iter {/, /}/d' $INC/linux/dma-resv.h \ + -e '/struct dma_resv {/, /}/d' \ + -e '/struct dma_resv_iter {/, /}/d' \ -e '/enum dma_resv_usage {/, /}/d' $INC/linux/dma-resv.h # add amd prefix to exported symbols @@ -86,7 +88,3 @@ if ! grep -q 'define HAVE_AMDKCL_FLAGS_TAKE_PATH' $SRC/config/config.h; then sed -i 's|\(CFLAGS_[A-Z_]*\)$(AMDDALPATH)/.*/\(.*\.o\)|\1\2|' $file done fi - -if ! grep -q 'define HAVE_DMA_RESV_FENCES' $SRC/config/config.h; then - sed -i 's|dma-buf/dma-resv.o|kcl_dma-resv.o|' amd/amdkcl/Makefile -fi From 765e8c782c563a50354f7ef2a9df9e3e37a1242a Mon Sep 17 00:00:00 2001 From: James Zhu Date: Fri, 1 Mar 2024 11:25:34 -0500 Subject: [PATCH 1257/1868] drm/amdkfd: add Host Trap Sampling support on gfx943 Add Host Trap Sampling support on gfx943. Signed-off-by: James Zhu Reviewed-by: Vladimir Indic Tested-by: Vladimir Indic --- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c index e2ae714a700f8..53b2df2a1637c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.c @@ -509,6 +509,17 @@ static uint32_t kgd_gfx_v9_4_3_clear_address_watch(struct amdgpu_device *adev, return 0; } +static uint32_t kgd_v9_4_3_trigger_pc_sample_trap(struct amdgpu_device *adev, + uint32_t vmid, + uint32_t *target_simd, + uint32_t *target_wave_slot, + enum kfd_ioctl_pc_sample_method method, + uint32_t inst) +{ + return kgd_gfx_v9_trigger_pc_sample_trap(adev, vmid, 8, 4, + target_simd, target_wave_slot, method, inst); +} + const struct kfd2kgd_calls gc_9_4_3_kfd2kgd = { .program_sh_mem_settings = kgd_gfx_v9_program_sh_mem_settings, .set_pasid_vmid_mapping = kgd_gfx_v9_4_3_set_pasid_vmid_mapping, @@ -543,5 +554,7 @@ const struct kfd2kgd_calls gc_9_4_3_kfd2kgd = { .set_address_watch = kgd_gfx_v9_4_3_set_address_watch, .clear_address_watch = kgd_gfx_v9_4_3_clear_address_watch, .hqd_get_pq_addr = kgd_gfx_v9_hqd_get_pq_addr, - .hqd_reset = kgd_gfx_v9_hqd_reset + .hqd_reset = kgd_gfx_v9_hqd_reset, + .trigger_pc_sample_trap = kgd_v9_4_3_trigger_pc_sample_trap, + .override_core_cg = kgd_gfx_v9_override_core_cg }; From 31310c1caf6ae7c6d408e6c152a2530e1ab0228b Mon Sep 17 00:00:00 2001 From: James Zhu Date: Thu, 25 Jul 2024 13:21:23 -0400 Subject: [PATCH 1258/1868] drm/amdkfd: enable Host Trap PC sampling for gfx943 Enable Host Trap PC sampling for gfx943. Signed-off-by: James Zhu Reviewed-by: Vladimir Indic Tested-by: Vladimir Indic --- drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c index 435ebba8c0de7..c829676d631a6 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pc_sampling.c @@ -31,9 +31,10 @@ * PC Sampling revision change log * * 0.1 - Initial revision + * 0.2 - Support gfx9_4_3 Host Trap PC sampling */ #define KFD_IOCTL_PCS_MAJOR_VERSION 0 -#define KFD_IOCTL_PCS_MINOR_VERSION 1 +#define KFD_IOCTL_PCS_MINOR_VERSION 2 struct supported_pc_sample_info { uint32_t ip_version; @@ -45,6 +46,7 @@ const struct kfd_pc_sample_info sample_info_hosttrap_9_0_0 = { struct supported_pc_sample_info supported_formats[] = { { IP_VERSION(9, 4, 2), &sample_info_hosttrap_9_0_0 }, + { IP_VERSION(9, 4, 3), &sample_info_hosttrap_9_0_0 }, }; static int kfd_pc_sample_thread(void *param) From 92c55d77330a19f31da76184d01a26ea28889812 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 30 Jul 2024 16:25:47 +0800 Subject: [PATCH 1259/1868] drm/amdkcl: fake drm_edid_{alloc/free/raw/valid}() It's caused by 1dc166feb7e808f16ec2289bf1da3adb7018248a "drm/amdgpu: convert bios_hardcoded_edid to drm_edid" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_drm_edid.c | 95 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 9 ++ drivers/gpu/drm/amd/dkms/m4/drm_edid_alloc.m4 | 57 +++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_edid.h | 34 +++++++ 6 files changed, 197 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_edid.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_edid_alloc.m4 diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 64dd31cf1bc84..3fbd585862102 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -8,7 +8,7 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_kthread.o kcl_io.o kcl_seq_file.o \ kcl_suspend.o kcl_pci.o kcl_mm.o kcl_memory.o kcl_sched.o \ kcl_fence.o kcl_reservation.o kcl_drm_cache.o \ - kcl_drm_fb.o kcl_drm_print.o \ + kcl_drm_fb.o kcl_drm_print.o kcl_drm_edid.o\ kcl_drm_crtc.o kcl_drm_connector.o kcl_drm_atomic_helper.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_fs_read_write.o kcl_drm_aperture.o \ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_edid.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_edid.c new file mode 100644 index 0000000000000..c5272121a0ab4 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_edid.c @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Intel Corporation. + * + * Authors: + * Ramalingam C + */ +#include +#include + +#ifndef HAVE_DRM_EDID_MALLOC +static const struct drm_edid *__kcl_drm_edid_alloc(const void *edid, size_t size) +{ + struct drm_edid *drm_edid; + + if (!edid || !size || size < EDID_LENGTH) + return NULL; + + drm_edid = kzalloc(sizeof(*drm_edid), GFP_KERNEL); + if (drm_edid) { + drm_edid->edid = edid; + drm_edid->size = size; + } + + return drm_edid; +} + +const struct drm_edid *_kcl_drm_edid_alloc(const void *edid, size_t size) +{ + const struct drm_edid *drm_edid; + + if (!edid || !size || size < EDID_LENGTH) + return NULL; + + edid = kmemdup(edid, size, GFP_KERNEL); + if (!edid) + return NULL; + + drm_edid = __kcl_drm_edid_alloc(edid, size); + if (!drm_edid) + kfree(edid); + + return drm_edid; +} +EXPORT_SYMBOL(_kcl_drm_edid_alloc); + +void _kcl_drm_edid_free(const struct drm_edid *drm_edid) +{ + if (!drm_edid) + return; + + kfree(drm_edid->edid); + kfree(drm_edid); +} +EXPORT_SYMBOL(_kcl_drm_edid_free); +#endif + +#ifndef HAVE_DRM_EDID_RAW +static int edid_extension_block_count(const struct edid *edid) +{ + return edid->extensions; +} + +static int edid_block_count(const struct edid *edid) +{ + return edid_extension_block_count(edid) + 1; +} + +static int edid_size_by_blocks(int num_blocks) +{ + return num_blocks * EDID_LENGTH; +} + +static int edid_size(const struct edid *edid) +{ + return edid_size_by_blocks(edid_block_count(edid)); +} + +const struct edid *_kcl_drm_edid_raw(const struct drm_edid *drm_edid) +{ + if (!drm_edid || !drm_edid->size) + return NULL; + + /* + * Do not return pointers where relying on EDID extension count would + * lead to buffer overflow. + */ + if (WARN_ON(edid_size(drm_edid->edid) > drm_edid->size)) + return NULL; + + return drm_edid->edid; +} +EXPORT_SYMBOL(_kcl_drm_edid_raw); +#endif + diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 03d785eef8a0b..e07aadfec8e58 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -473,9 +473,18 @@ /* drm_dsc_pps_payload_pack() is available */ #define HAVE_DRM_DSC_PPS_PAYLOAD_PACK 1 +/* drm_edid_alloc() is available */ +#define HAVE_DRM_EDID_MALLOC 1 + /* drm_edid_override_connector_update() is available */ #define HAVE_DRM_EDID_OVERRIDE_CONNECTOR_UPDATE 1 +/* drm_edid_raw() is available */ +#define HAVE_DRM_EDID_RAW 1 + +/* drm_edid_valid() is available */ +#define HAVE_DRM_EDID_VALID 1 + /* drm_exec() has 3 arguments */ #define HAVE_DRM_EXEC_INIT_3_ARGUMENTS 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_edid_alloc.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_edid_alloc.m4 new file mode 100644 index 0000000000000..86301a9a861f4 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_edid_alloc.m4 @@ -0,0 +1,57 @@ +dnl # +dnl # commit v5.18-rc5-1218-g6537f79a2aae +dnl # drm/edid: add new interfaces around struct drm_edid +dnl # +AC_DEFUN([AC_AMDGPU_DRM_EDID_MALLOC], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + drm_edid_alloc(NULL, 0); + ],[ + AC_DEFINE(HAVE_DRM_EDID_MALLOC, 1, + [drm_edid_alloc() is available]) + ]) + ]) +]) + +dnl # +dnl # commit v5.19-rc2-380-g3d1ab66e043f +dnl # drm/edid: add drm_edid_raw() to access the raw EDID data +dnl # +AC_DEFUN([AC_AMDGPU_DRM_EDID_RAW], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + drm_edid_raw(NULL); + ],[ + AC_DEFINE(HAVE_DRM_EDID_RAW, 1, + [drm_edid_raw() is available]) + ]) + ]) +]) + +dnl # +dnl # commit v6.1-rc1-145-g6c9b3db70aad +dnl # drm/edid: add function for checking drm_edid validity +dnl # +AC_DEFUN([AC_AMDGPU_DRM_EDID_VALID], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + drm_edid_valid(NULL); + ],[ + AC_DEFINE(HAVE_DRM_EDID_VALID, 1, + [drm_edid_valid() is available]) + ]) + ]) +]) + + +AC_DEFUN([AC_AMDGPU_STRUCT_DRM_EDID], [ + AC_AMDGPU_DRM_EDID_MALLOC + AC_AMDGPU_DRM_EDID_RAW + AC_AMDGPU_DRM_EDID_VALID +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 059cb91e908e1..d3355c7866a69 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -195,6 +195,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_GEM_PLANE_HELPER_PREPARE_FB AC_AMDGPU_BITMAP_TO_ARR32 AC_AMDGPU_SHRINKER + AC_AMDGPU_STRUCT_DRM_EDID AC_AMDGPU_DRM_DP_MST_POST_PASSTHROUGH_AUX AC_AMDGPU_DRM_DP_MST_PORT_FULL_PBN AC_AMDGPU_ACPI_VIDEO_FUNCS diff --git a/include/kcl/kcl_drm_edid.h b/include/kcl/kcl_drm_edid.h index 0e5b0fab8f8e3..05afadb754485 100644 --- a/include/kcl/kcl_drm_edid.h +++ b/include/kcl/kcl_drm_edid.h @@ -22,4 +22,38 @@ #define DRM_EDID_FEATURE_CONTINUOUS_FREQ (1 << 0) /* 1.4 */ #endif + +/* commit v5.18-rc5-1046-ge4ccf9a777d3 + drm/edid: add struct drm_edid container */ +#if !defined(HAVE_DRM_EDID_MALLOC) || !defined(HAVE_DRM_EDID_RAW) || !defined(HAVE_DRM_EDID_VALID) +struct drm_edid { + /* Size allocated for edid */ + size_t size; + const struct edid *edid; +}; +#endif + +#ifndef HAVE_DRM_EDID_MALLOC +const struct drm_edid *_kcl_drm_edid_alloc(const void *edid, size_t size); +void _kcl_drm_edid_free(const struct drm_edid *drm_edid); +#define drm_edid_alloc _kcl_drm_edid_alloc +#define drm_edid_free _kcl_drm_edid_free +#endif + +#ifndef HAVE_DRM_EDID_RAW +const struct edid *_kcl_drm_edid_raw(const struct drm_edid *drm_edid); +#define drm_edid_raw _kcl_drm_edid_raw +#endif + +#ifndef HAVE_DRM_EDID_VALID +static inline bool _kcl_drm_edid_valid(const struct drm_edid *drm_edid) +{ + if (!drm_edid) + return false; + + return drm_edid_is_valid(drm_edid->edid); +} +#define drm_edid_valid _kcl_drm_edid_valid +#endif + #endif From 5906be2bbe0b236ba1fa5c6eb0079385abdb6700 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Mon, 15 Jul 2024 15:46:30 +0530 Subject: [PATCH 1260/1868] drm/amd/pm: Add phase detect residency support Add support to get phase detect residency through debugfs Signed-off-by: Lijo Lazar Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 39 +++++++++++++++++++ drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h | 2 + 2 files changed, 41 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index bc8faa9d53e8f..53b7c27442edc 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -3872,8 +3872,40 @@ int smu_phase_det_enable(struct smu_context *smu, bool enable) return pd_ctl->ops->enable(smu, enable); } +static int smu_phase_det_get_residency(struct smu_context *smu, uint32_t *res) +{ + struct smu_dpm_context *dpm_ctxt = &smu->smu_dpm; + struct smu_phase_det_ctl *pd_ctl; + + pd_ctl = dpm_ctxt->pd_ctl; + if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled || !pd_ctl) + return -EOPNOTSUPP; + + if (!pd_ctl->ops || !pd_ctl->ops->get_residency) + return -EOPNOTSUPP; + + if (pd_ctl->status == SMU_PHASE_DET_DISABLED) + return -EPERM; + + return pd_ctl->ops->get_residency(smu, res); +} + #if defined(CONFIG_DEBUG_FS) +static int smu_phase_det_debugfs_get_residency(void *data, u64 *val) +{ + struct smu_context *smu = (struct smu_context *)data; + uint32_t res; + int r; + + r = smu_phase_det_get_residency(smu, &res); + if (r) + return r; + *val = res; + + return 0; +} + static int smu_phase_det_debugfs_status(void *data, u64 *val) { struct smu_context *smu = (struct smu_context *)data; @@ -3968,6 +4000,9 @@ DEFINE_SIMPLE_ATTRIBUTE(smu_phase_det_fops_en, smu_phase_det_debugfs_status, smu_phase_det_debugfs_enable, "%llu\n"); #endif +DEFINE_DEBUGFS_ATTRIBUTE(smu_phase_det_fops_res, + smu_phase_det_debugfs_get_residency, NULL, "%llu\n"); + #define DEBUGFS_CREATE_PHASE_DET_ATTR(name, param) \ debugfs_create_file(#name, 0644, dir, smu, &smu_phase_det_fops_##param) @@ -3993,6 +4028,10 @@ void amdgpu_smu_phase_det_debugfs_init(struct amdgpu_device *adev) debugfs_create_file("enable", 0644, dir, smu, &smu_phase_det_fops_en); + if (pd_ctl->ops->get_residency) + debugfs_create_file("residency", 0444, dir, smu, + &smu_phase_det_fops_res); + DEBUGFS_CREATE_PHASE_DET_ATTR(freq_lo, LO_FREQ); DEBUGFS_CREATE_PHASE_DET_ATTR(freq_hi, HI_FREQ); DEBUGFS_CREATE_PHASE_DET_ATTR(threshold, THRESH); diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h index 5812d203bca75..22670990e65f5 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/amdgpu_smu.h @@ -397,6 +397,7 @@ struct smu_phase_det_ops { int (*get)(struct smu_context *smu, enum pp_pm_phase_det_param_id id, uint32_t *val); int (*enable)(struct smu_context *smu, bool enable); + int (*get_residency)(struct smu_context *smu, uint32_t *res); }; enum phase_det_state { @@ -409,6 +410,7 @@ struct smu_phase_det_ctl { struct smu_phase_det_params params; struct smu_phase_det_ops *ops; enum phase_det_state status; + uint32_t residency; }; struct smu_dpm_context { From 61e6d596287b41c2208ba44fe19c74900943bb3f Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Mon, 15 Jul 2024 16:46:08 +0530 Subject: [PATCH 1261/1868] drm/amd/pm: Add SMUv13.0.6 phase detect residency Add support to get phase detect residency information on SMUv13.0.6 SOCs. Signed-off-by: Lijo Lazar Reviewed-by: Hawking Zhang --- .../pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h | 3 ++- drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h | 3 ++- .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 24 +++++++++++++++++++ 3 files changed, 28 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h index f3dcc53f583d2..fc7118b956774 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_ppsmc.h @@ -99,7 +99,8 @@ #define PPSMC_MSG_SetPhsDetWRbwHystDown 0x48 #define PPSMC_MSG_SetPhsDetWRbwAlpha 0x49 #define PPSMC_MSG_SetPhsDetOnOff 0x4A -#define PPSMC_Message_Count 0x4B +#define PPSMC_MSG_GetPhsDetResidency 0x4B +#define PPSMC_Message_Count 0x4C //PPSMC Reset Types for driver msg argument #define PPSMC_RESET_TYPE_DRIVER_MODE_1_RESET 0x1 diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h index 2ad96aef057b4..2b8233d2bdf32 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h @@ -281,7 +281,8 @@ __SMU_DUMMY_MAP(SetPhsDetWRbwFreqLow), \ __SMU_DUMMY_MAP(SetPhsDetWRbwHystDown), \ __SMU_DUMMY_MAP(SetPhsDetWRbwAlpha), \ - __SMU_DUMMY_MAP(SetPhsDetOnOff), + __SMU_DUMMY_MAP(SetPhsDetOnOff), \ + __SMU_DUMMY_MAP(GetPhsDetResidency), #undef __SMU_DUMMY_MAP #define __SMU_DUMMY_MAP(type) SMU_MSG_##type diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index 302783dd42829..63fa903b3889a 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -181,6 +181,7 @@ static const struct cmn2asic_msg_mapping smu_v13_0_6_message_map[SMU_MSG_MAX_COU MSG_MAP(SetPhsDetWRbwHystDown, PPSMC_MSG_SetPhsDetWRbwHystDown, 0), MSG_MAP(SetPhsDetWRbwAlpha, PPSMC_MSG_SetPhsDetWRbwAlpha, 0), MSG_MAP(SetPhsDetOnOff, PPSMC_MSG_SetPhsDetOnOff, 0), + MSG_MAP(GetPhsDetResidency, PPSMC_MSG_GetPhsDetResidency, 0), }; // clang-format on @@ -540,10 +541,30 @@ static int smu_v13_0_6_phase_det_enable(struct smu_context *smu, bool enable) return r; } +static int smu_v13_0_6_phase_det_get_residency(struct smu_context *smu, + uint32_t *res) +{ + struct smu_dpm_context *smu_dpm = &smu->smu_dpm; + struct smu_phase_det_ctl *pd_ctl; + + pd_ctl = smu_dpm->pd_ctl; + + if (!res) + return -EINVAL; + + if (pd_ctl->status != SMU_PHASE_DET_ON) { + *res = 0; + return 0; + } + + return smu_cmn_send_smc_msg(smu, SMU_MSG_GetPhsDetResidency, res); +} + static struct smu_phase_det_ops smu_v13_0_6_pd_ops = { .set = smu_v13_0_6_phase_det_set, .get = smu_v13_0_6_phase_det_get, .enable = smu_v13_0_6_phase_det_enable, + .get_residency = smu_v13_0_6_phase_det_get_residency, }; static int smu_v13_0_6_allocate_dpm_context(struct smu_context *smu) @@ -916,6 +937,9 @@ static int smu_v13_0_6_set_default_dpm_table(struct smu_context *smu) smu_dpm->pd_ctl = NULL; } + if (smu_dpm->pd_ctl && (smu->smc_fw_version < 0x00556F78)) + smu_dpm->pd_ctl->ops->get_residency = NULL; + smu_v13_0_6_pm_policy_init(smu); /* gfxclk dpm table setup */ dpm_table = &dpm_context->dpm_tables.gfx_table; From a884ce0685855df9ad884fee39778524ca272ec9 Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 8 Aug 2024 17:08:05 +0800 Subject: [PATCH 1262/1868] drm/amdkcl: add oot build support Signed-off-by: Flora Cui Signed-off-by: Bob Zhou Reviewed-by: Horatio Zhang --- drivers/gpu/drm/amd/dkms/oot/Makefile.oot | 41 ++++++++ drivers/gpu/drm/amd/dkms/oot/kmod-amdgpu.spec | 96 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/oot/pre-build.sh | 91 ++++++++++++++++++ 3 files changed, 228 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/oot/Makefile.oot create mode 100644 drivers/gpu/drm/amd/dkms/oot/kmod-amdgpu.spec create mode 100644 drivers/gpu/drm/amd/dkms/oot/pre-build.sh diff --git a/drivers/gpu/drm/amd/dkms/oot/Makefile.oot b/drivers/gpu/drm/amd/dkms/oot/Makefile.oot new file mode 100644 index 0000000000000..5c8c78df4e932 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/oot/Makefile.oot @@ -0,0 +1,41 @@ +ifneq ($(KERNELRELEASE),) +include $(src)/amd/dkms/Makefile +else +KERNELVER := $(shell uname -r) +kernel_build_dir := /lib/modules/$(KERNELVER)/build +PACKAGE_NAME := $(shell sed -n '/PACKAGE_NAME/s|.*=||p' amd/dkms/dkms.conf) +PACKAGE_VERSION := $(shell sed -n '/PACKAGE_VERSION/s|.*=||p' amd/dkms/dkms.conf) +module_src_dir := $(CURDIR) +module_build_dir := $(shell mktemp -ut amd.XXXXXXXX) +module_build_flags := +num_cpu_cores := $(shell nproc) +Q := @ + +ifeq ($(wildcard $(kernel_build_dir)/include/config/auto.conf),) +$(error "invalid kernel obj dir, is kernel-devel installed?") +endif + +.PHONY: modules pre-build + +include $(kernel_build_dir)/include/config/auto.conf + +ifneq ($(CONFIG_CC_IS_CLANG),) +module_build_flags += CC=clang +endif +ifneq ($(CONFIG_LD_IS_LLD),) +module_build_flags += LD=ld.lld +endif + +modules:pre-build + $(Q)make -j$(num_cpu_cores) KERNELRELEASE=$(KERNELVER) \ + TTM_NAME=amdttm \ + SCHED_NAME=amd-sched \ + -C $(kernel_build_dir) \ + M=$(module_build_dir) $(module_build_flags) + $(Q)unlink $(module_build_dir) + +pre-build: + $(Q)cp -f amd/dkms/oot/pre-build.sh amd/dkms + $(Q)amd/dkms/pre-build.sh $(KERNELVER) $(module_src_dir) $(PACKAGE_NAME) $(PACKAGE_VERSION) $(module_build_dir) + +endif diff --git a/drivers/gpu/drm/amd/dkms/oot/kmod-amdgpu.spec b/drivers/gpu/drm/amd/dkms/oot/kmod-amdgpu.spec new file mode 100644 index 0000000000000..dd92860353f46 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/oot/kmod-amdgpu.spec @@ -0,0 +1,96 @@ +%global pkg amdgpu +%global kernel kernel version +%define pkg_version 6.8.7 +%define osdb_version 1798298 +%define anolis_release 1 + +%global debug_package %{nil} + +Name: kmod-%{pkg} +Version: %(echo %{kernel} | sed -E 's/-/~/g; s/\.(an|al)[0-9]+$//g') +Release: %{pkg_version}_%{osdb_version}~%{anolis_release}%{?dist} +Summary: The amdgpu Linux kernel driver + +License: GPLv2 and Redistributable, no modification permitted +URL: http://www.amd.com/ +Source0: kmod-%{pkg}-%{pkg_version}.tar.gz + +BuildRequires: gcc +BuildRequires: make +Requires: kernel >= %{kernel} + +%description +The AMD display driver kernel module in DKMS format for AMD graphics S/W + +%prep +%autosetup -n kmod-%{pkg}-%{pkg_version} -p1 + +%build +pushd src +%{__make} -f amd/dkms/oot/Makefile.oot KERNELVER=%(uname -r) +popd + +%install +mkdir -p %{buildroot}/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu +%{__install} -D -t %{buildroot}/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu src/amddrm_buddy.ko src/amddrm_ttm_helper.ko src/scheduler/amd-sched.ko src/ttm/amdttm.ko src/amd/amdxcp/amdxcp.ko src/amd/amdgpu/amdgpu.ko src/amd/amdkcl/amdkcl.ko + +# Make .ko objects temporarily executable for automatic stripping +find %{buildroot}/lib/modules -type f -name \*.ko -exec chmod u+x \{\} \+ + +# Generate depmod.conf +%{__install} -d %{buildroot}/%{_sysconfdir}/depmod.d/ +for kmod in $(find %{buildroot}/lib/modules/%{kernel}.%{_arch}/extra -type f -name \*.ko -printf "%%P\n" | sort) +do + echo "override $(basename $kmod .ko) * weak-updates/$(dirname $kmod)" >> %{buildroot}/%{_sysconfdir}/depmod.d/%{pkg}.conf + echo "override $(basename $kmod .ko) * extra/$(dirname $kmod)" >> %{buildroot}/%{_sysconfdir}/depmod.d/%{pkg}.conf +done + +%clean +%{__rm} -rf %{buildroot} + +%post +depmod -a > /dev/null 2>&1 + +if [ -x "/usr/sbin/weak-modules" ]; then + printf '%s\n' "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amdgpu.ko" | /usr/sbin/weak-modules --no-initramfs --add-modules + printf '%s\n' "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amdkcl.ko" | /usr/sbin/weak-modules --no-initramfs --add-modules + printf '%s\n' "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amdxcp.ko" | /usr/sbin/weak-modules --no-initramfs --add-modules + printf '%s\n' "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amddrm_buddy.ko" | /usr/sbin/weak-modules --no-initramfs --add-modules + printf '%s\n' "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amddrm_ttm_helper.ko" | /usr/sbin/weak-modules --no-initramfs --add-modules + printf '%s\n' "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amd-sched.ko" | /usr/sbin/weak-modules --no-initramfs --add-modules + printf '%s\n' "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amdttm.ko" | /usr/sbin/weak-modules --no-initramfs --add-modules +fi + +%preun +echo "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amdgpu.ko" >> /var/run/rpm-%{pkg}-modules.list +echo "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amdkcl.ko" >> /var/run/rpm-%{pkg}-modules.list +echo "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amdxcp.ko" >> /var/run/rpm-%{pkg}-modules.list +echo "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amddrm_buddy.ko" >> /var/run/rpm-%{pkg}-modules.list +echo "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amddrm_ttm_helper.ko" >> /var/run/rpm-%{pkg}-modules.list +echo "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amd-sched.ko" >> /var/run/rpm-%{pkg}-modules.list +echo "/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amdttm.ko" >> /var/run/rpm-%{pkg}-modules.list + +%postun +depmod -a > /dev/null 2>&1 + +if [ -x "/usr/sbin/weak-modules" ]; then + modules=( $(cat /var/run/rpm-%{pkg}-modules.list) ) + printf '%s\n' "${modules[@]}" | /usr/sbin/weak-modules --no-initramfs --remove-modules +fi +rm /var/run/rpm-%{pkg}-modules.list + +%files +/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amdgpu.ko +/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amdkcl.ko +/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amdxcp.ko +/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amddrm_buddy.ko +/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amddrm_ttm_helper.ko +/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amd-sched.ko +/lib/modules/%{kernel}.%{_arch}/extra/drivers/gpu/drm/amdgpu/amdttm.ko +%defattr(644,root,root,755) +%license licenses +%config(noreplace) %{_sysconfdir}/depmod.d/%{pkg}.conf + +%changelog +* Thu Jul 18 2024 Bob Zhou - 6.8.7-1798298 +- diff --git a/drivers/gpu/drm/amd/dkms/oot/pre-build.sh b/drivers/gpu/drm/amd/dkms/oot/pre-build.sh new file mode 100644 index 0000000000000..7cb58df401aa8 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/oot/pre-build.sh @@ -0,0 +1,91 @@ +#!/bin/bash + +KCL="amd/amdkcl" +INC="include" +SRC="amd/dkms" + +KERNELVER=$1 +DKMS_TREE=$2 +MODULE=$3 +MODULE_VERSION=$4 +MODULE_BUILD_DIR=$5 +KERNELVER_BASE=${KERNELVER%%-*} + +version_lt () { + newest=$((echo "$KERNELVER_BASE"; echo "$1") | sort -V | tail -n1) + [ "$KERNELVER_BASE" != "$newest" ] +} + +version_ge () { + newest=$((echo "$KERNELVER_BASE"; echo "$1") | sort -V | tail -n1) + [ "$KERNELVER_BASE" = "$newest" ] +} + +version_gt () { + oldest=$((echo "$KERNELVER_BASE"; echo "$1") | sort -V | head -n1) + [ "$KERNELVER_BASE" != "$oldest" ] +} + +version_le () { + oldest=$((echo "$KERNELVER_BASE"; echo "$1") | sort -V | head -n1) + [ "$KERNELVER_BASE" = "$oldest" ] +} + +source $KCL/files + +sed -i -e '/DEFINE_WD_CLASS(reservation_ww_class)/,/EXPORT_SYMBOL(reservation_ww_class)/d' \ + -e '/dma_resv_lockdep/,/subsys_initcall/d' \ + -e '1i\#ifdef HAVE_DMA_RESV_FENCES' \ + -e '$a\#endif' $KCL/dma-buf/dma-resv.c +sed -i -e '/extern struct ww_class reservation_ww_class/i #include ' \ + -e '/struct dma_resv {/, /}/d' \ + -e '/struct dma_resv_iter {/, /}/d' \ + -e '/enum dma_resv_usage {/, /}/d' $INC/linux/dma-resv.h + +# add amd prefix to exported symbols +for file in $FILES; do + awk -F'[()]' '/EXPORT_SYMBOL/ { + print "#define "$2" amd"$2" //"$0 + }' $file | sort -u >>$INC/rename_symbol.h +done + +# rename CONFIG_xxx to CONFIG_xxx_AMDKCL +# otherwise kernel config would override dkms package config +AMDGPU_CONFIG=$(find -name Kconfig -exec grep -h '^config' {} + | sed 's/ /_/' | tr 'a-z' 'A-Z') +TTM_CONFIG=$(awk '/CONFIG_DRM/{gsub(".*\\(CONFIG_DRM","CONFIG_DRM");gsub("\\).*","");print $0}' ttm/Makefile) +SCHED_CONFIG=$(awk '/CONFIG_DRM/{gsub(".*\\(CONFIG_DRM","CONFIG_DRM");gsub("\\).*","");print $0}' scheduler/Makefile) +for config in $AMDGPU_CONFIG $TTM_CONFIG $SCHED_CONFIG; do + for file in $(grep -rl $config ./); do + sed -i "s/\<$config\>/&_AMDKCL/" $file + done + sed -i "/${config}$/s/$/_AMDKCL/" amd/dkms/Makefile +done + +export KERNELVER +ln -s $DKMS_TREE $MODULE_BUILD_DIR + +# Enable gcc-toolset for kernels that are built with non-default compiler +# perform this check only when permissions allow +if [[ -d /opt/rh && `id -u` -eq 0 ]]; then + for f in $(find /opt/rh -type f -a -name gcc); do + [[ -f /boot/config-$KERNELVER ]] || continue + config_gcc_version=$(. /boot/config-$KERNELVER && echo $CONFIG_GCC_VERSION) + IFS='.' read -ra ver <<<$($f -dumpfullversion) + gcc_version=$(printf "%d%02d%02d\n" ${ver[@]}) + if [[ "$config_gcc_version" = "$gcc_version" ]]; then + . ${f%/*}/../../../enable + break + fi + done +fi +echo "PATH=$PATH" >$MODULE_BUILD_DIR/.env + +(cd $SRC && ./configure) + +# rename CFLAGS_target.o / CFLAGS_REMOVE_ to CFLAGS_target.o +# for kernel version < 5.3 +if ! grep -q 'define HAVE_AMDKCL_FLAGS_TAKE_PATH' $SRC/config/config.h; then + for file in $(grep -rl 'CFLAGS_' amd/display/); do + sed -i 's|\(CFLAGS_[A-Z_]*\)$(AMDDALPATH)/.*/\(.*\.o\)|\1\2|' $file + done +fi From 847d96b4f3ce527076d75980bb167550bda7a605 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 12 Aug 2024 18:43:59 +0800 Subject: [PATCH 1263/1868] drm/amdkcl: wrap code under DEFINE_DEBUGFS_ATTRIBUTE It's caused by 7368b413ed6e5a98516b8018e8e47850f32cd1d3 "drm/amd/pm: Add phase detect residency support" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 53b7c27442edc..86de840d65409 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -4000,8 +4000,13 @@ DEFINE_SIMPLE_ATTRIBUTE(smu_phase_det_fops_en, smu_phase_det_debugfs_status, smu_phase_det_debugfs_enable, "%llu\n"); #endif +#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(smu_phase_det_fops_res, smu_phase_det_debugfs_get_residency, NULL, "%llu\n"); +#else +DEFINE_SIMPLE_ATTRIBUTE(smu_phase_det_fops_res, + smu_phase_det_debugfs_get_residency, NULL, "%llu\n"); +#endif #define DEBUGFS_CREATE_PHASE_DET_ATTR(name, param) \ debugfs_create_file(#name, 0644, dir, smu, &smu_phase_det_fops_##param) From 5abe20a12c5c7581aeef7ed7b5f378b1e90a963c Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 12 Aug 2024 18:56:27 +0800 Subject: [PATCH 1264/1868] drm/amdkcl: update kbps_to_peak_pbn param for non-upstream code It's caused by 4b6564cb120c9872ba6b2c108e634586acebc792 "drm/amd/display: Fix MST BW calculation Regression" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 71e1019c3d2cc..8d803993dc627 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -2027,11 +2027,13 @@ enum dc_status dm_dp_mst_is_port_support_mode( */ int pbn_div, slot_num, max_slot_num; enum dc_link_encoding_format link_encoding; + uint16_t fec_overhead_multiplier_x1000 = + get_fec_overhead_multiplier(stream->link); uint32_t stream_kbps = dc_bandwidth_in_kbps_from_timing( &stream->timing, dc_link_get_highest_encoding_format(stream->link)); - pbn = kbps_to_peak_pbn(stream_kbps); + pbn = kbps_to_peak_pbn(stream_kbps, fec_overhead_multiplier_x1000); pbn_div = dm_mst_get_pbn_divider(stream->link); slot_num = DIV_ROUND_UP(pbn, pbn_div); From 453f500f5f24467ca39287677d1d9bb8fed368fd Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Thu, 8 Aug 2024 14:09:06 +0530 Subject: [PATCH 1265/1868] drm/amdgpu: add cp queue registers for gfx9_4_3 ipdump Add gfx9 support of CP queue registers for all queues to be used by devcoredump. Signed-off-by: Sunil Khatri Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 98 ++++++++++++++++++++++++- 1 file changed, 95 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index 59417feac9a5d..5af4abca759de 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -151,6 +151,47 @@ static const struct amdgpu_hwip_reg_entry gc_reg_list_9_4_3[] = { SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE3) }; +static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_9_4_3[] = { + /* compute queue registers */ + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_VMID), + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ACTIVE), + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PERSISTENT_STATE), + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PIPE_PRIORITY), + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUEUE_PRIORITY), + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUANTUM), + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE), + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE_HI), + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR), + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR), + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI), + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL), + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL), + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR), + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR_HI), + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_RPTR), + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_CONTROL), + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST), + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR), + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI), + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL), + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_RPTR), + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR), + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_EVENTS), + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_LO), + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_HI), + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_CONTROL), + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET), + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_SIZE), + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET), + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_SIZE), + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GDS_RESOURCE_STATE), + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ERROR), + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM), + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO), + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI), + SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GFX_STATUS), +}; + struct amdgpu_gfx_ras gfx_v9_4_3_ras; static void gfx_v9_4_3_set_ring_funcs(struct amdgpu_device *adev); @@ -976,7 +1017,7 @@ static int gfx_v9_4_3_compute_ring_init(struct amdgpu_device *adev, int ring_id, static void gfx_v9_4_3_alloc_ip_dump(struct amdgpu_device *adev) { uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9_4_3); - uint32_t *ptr, num_xcc; + uint32_t *ptr, num_xcc, inst; num_xcc = NUM_XCC(adev->gfx.xcc_mask); @@ -987,6 +1028,19 @@ static void gfx_v9_4_3_alloc_ip_dump(struct amdgpu_device *adev) } else { adev->gfx.ip_dump_core = ptr; } + + /* Allocate memory for compute queue registers for all the instances */ + reg_count = ARRAY_SIZE(gc_cp_reg_list_9_4_3); + inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * + adev->gfx.mec.num_queue_per_pipe; + + ptr = kcalloc(reg_count * inst * num_xcc, sizeof(uint32_t), GFP_KERNEL); + if (!ptr) { + DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n"); + adev->gfx.ip_dump_compute_queues = NULL; + } else { + adev->gfx.ip_dump_compute_queues = ptr; + } } static int gfx_v9_4_3_sw_init(void *handle) @@ -1117,6 +1171,7 @@ static int gfx_v9_4_3_sw_fini(void *handle) amdgpu_gfx_sysfs_fini(adev); kfree(adev->gfx.ip_dump_core); + kfree(adev->gfx.ip_dump_compute_queues); return 0; } @@ -4329,8 +4384,9 @@ static void gfx_v9_4_3_ip_print(void *handle, struct drm_printer *p) static void gfx_v9_4_3_ip_dump(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; - uint32_t i; - uint32_t xcc_id, xcc_offset, num_xcc; + uint32_t i, j, k; + uint32_t num_xcc, reg, num_inst; + uint32_t xcc_id, xcc_offset, inst_offset; uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9_4_3); if (!adev->gfx.ip_dump_core) @@ -4347,6 +4403,42 @@ static void gfx_v9_4_3_ip_dump(void *handle) GET_INST(GC, xcc_id))); } amdgpu_gfx_off_ctrl(adev, true); + + /* dump compute queue registers for all instances */ + if (!adev->gfx.ip_dump_compute_queues) + return; + + num_inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * + adev->gfx.mec.num_queue_per_pipe; + reg_count = ARRAY_SIZE(gc_cp_reg_list_9_4_3); + amdgpu_gfx_off_ctrl(adev, false); + mutex_lock(&adev->srbm_mutex); + for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { + xcc_offset = xcc_id * reg_count * num_inst; + inst_offset = 0; + for (i = 0; i < adev->gfx.mec.num_mec; i++) { + for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { + for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { + /* ME0 is for GFX so start from 1 for CP */ + soc15_grbm_select(adev, 1 + i, j, k, 0, + GET_INST(GC, xcc_id)); + + for (reg = 0; reg < reg_count; reg++) { + adev->gfx.ip_dump_compute_queues + [xcc_offset + + inst_offset + reg] = + RREG32(SOC15_REG_ENTRY_OFFSET_INST( + gc_cp_reg_list_9_4_3[reg], + GET_INST(GC, xcc_id))); + } + inst_offset += reg_count; + } + } + } + } + soc15_grbm_select(adev, 0, 0, 0, 0, 0); + mutex_unlock(&adev->srbm_mutex); + amdgpu_gfx_off_ctrl(adev, true); } static const struct amd_ip_funcs gfx_v9_4_3_ip_funcs = { From 1542530c623280893a07368378579d5cb23a9101 Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Thu, 8 Aug 2024 14:23:07 +0530 Subject: [PATCH 1266/1868] drm/amdgpu: add cp queue registers print for gfx9_4_3 Add gfx9_4_3 print support of CP queue registers for all queues to be used by devcoredump. Signed-off-by: Sunil Khatri Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 42 +++++++++++++++++++++++-- 1 file changed, 40 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index 5af4abca759de..7b4ae197eb49b 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -4362,8 +4362,9 @@ static void gfx_v9_4_3_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_no static void gfx_v9_4_3_ip_print(void *handle, struct drm_printer *p) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; - uint32_t i; - uint32_t xcc_id, xcc_offset, num_xcc; + uint32_t i, j, k; + uint32_t xcc_id, xcc_offset, inst_offset; + uint32_t num_xcc, reg, num_inst; uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9_4_3); if (!adev->gfx.ip_dump_core) @@ -4379,6 +4380,43 @@ static void gfx_v9_4_3_ip_print(void *handle, struct drm_printer *p) gc_reg_list_9_4_3[i].reg_name, adev->gfx.ip_dump_core[xcc_offset + i]); } + + /* print compute queue registers for all instances */ + if (!adev->gfx.ip_dump_compute_queues) + return; + + num_inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * + adev->gfx.mec.num_queue_per_pipe; + + reg_count = ARRAY_SIZE(gc_cp_reg_list_9_4_3); + drm_printf(p, "\nnum_xcc: %d num_mec: %d num_pipe: %d num_queue: %d\n", + num_xcc, + adev->gfx.mec.num_mec, + adev->gfx.mec.num_pipe_per_mec, + adev->gfx.mec.num_queue_per_pipe); + + for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { + xcc_offset = xcc_id * reg_count * num_inst; + inst_offset = 0; + for (i = 0; i < adev->gfx.mec.num_mec; i++) { + for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { + for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { + drm_printf(p, + "\nxcc:%d mec:%d, pipe:%d, queue:%d\n", + xcc_id, i, j, k); + for (reg = 0; reg < reg_count; reg++) { + drm_printf(p, + "%-50s \t 0x%08x\n", + gc_cp_reg_list_9_4_3[reg].reg_name, + adev->gfx.ip_dump_compute_queues + [xcc_offset + inst_offset + + reg]); + } + inst_offset += reg_count; + } + } + } + } } static void gfx_v9_4_3_ip_dump(void *handle) From 8af430b2865bc5fb02c22cfeeea61cad65108711 Mon Sep 17 00:00:00 2001 From: Soham Dandapat Date: Mon, 29 Jul 2024 11:59:11 +0530 Subject: [PATCH 1267/1868] drm/amdgpu: Return earlier in amdgpu_sw_ring_ib_end if mcbp is off As we don't trigger preemption is sw ring muxer when mcbp is disabled,so return earlier in amdgpu_sw_ring_ib_end function if mcbp is disabled ,not required to call amdgpu_ring_mux_end_ib Change-Id: I8cc6490d96eb773e91e5de15d6b6135148579cc1 Signed-off-by: Soham Dandapat Acked-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c index d234b7ccfaafc..1c66da1c3fb42 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.c @@ -410,7 +410,7 @@ void amdgpu_sw_ring_ib_end(struct amdgpu_ring *ring) struct amdgpu_ring_mux *mux = &adev->gfx.muxer; WARN_ON(!ring->is_sw_ring); - if (ring->hw_prio > AMDGPU_RING_PRIO_DEFAULT) + if (adev->gfx.mcbp && ring->hw_prio > AMDGPU_RING_PRIO_DEFAULT) return; amdgpu_ring_mux_end_ib(mux, ring); } From dd14b6b1d27d090f1d8cff6e7728138c26819357 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 9 Apr 2024 13:11:53 -0400 Subject: [PATCH 1268/1868] drm/amdgpu: add new ring reset callback Use this to reset just a single ring. Acked-by: Vitaly Prosyak Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h index 582053f1cd565..c7f15edeb3679 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h @@ -235,6 +235,7 @@ struct amdgpu_ring_funcs { void (*patch_cntl)(struct amdgpu_ring *ring, unsigned offset); void (*patch_ce)(struct amdgpu_ring *ring, unsigned offset); void (*patch_de)(struct amdgpu_ring *ring, unsigned offset); + int (*reset)(struct amdgpu_ring *ring, unsigned int vmid); }; struct amdgpu_ring { @@ -334,6 +335,7 @@ struct amdgpu_ring { #define amdgpu_ring_patch_cntl(r, o) ((r)->funcs->patch_cntl((r), (o))) #define amdgpu_ring_patch_ce(r, o) ((r)->funcs->patch_ce((r), (o))) #define amdgpu_ring_patch_de(r, o) ((r)->funcs->patch_de((r), (o))) +#define amdgpu_ring_reset(r, v) (r)->funcs->reset((r), (v)) unsigned int amdgpu_ring_max_ibs(enum amdgpu_ring_type type); int amdgpu_ring_alloc(struct amdgpu_ring *ring, unsigned ndw); From 2ad599dbf7a475b668b58157f570496891c5d1d6 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 3 Jun 2024 14:38:20 -0400 Subject: [PATCH 1269/1868] drm/amdgpu: add per ring reset support (v5) If a specific job is hung, try and reset just the ring associated with the job. v2: move to amdgpu_job.c v3: fix drm_sched_stop() handling when ring reset fails v4: drop unnecessary amdgpu_fence_driver_clear_job_fences() and drm_sched_increase_karma() v5: rework sched_stop handling Acked-by: Vitaly Prosyak Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c index 908e134551523..c2de3fd172455 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c @@ -72,6 +72,25 @@ static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job) dma_fence_set_error(&s_job->s_fence->finished, -ETIME); + /* attempt a per ring reset */ + if (amdgpu_gpu_recovery && + ring->funcs->reset) { + /* stop the scheduler, but don't mess with the + * bad job yet because if ring reset fails + * we'll fall back to full GPU reset. + */ + drm_sched_wqueue_stop(&ring->sched); + r = amdgpu_ring_reset(ring, job->vmid); + if (!r) { + if (amdgpu_ring_sched_ready(ring)) + drm_sched_stop(&ring->sched, s_job); + amdgpu_fence_driver_force_completion(ring); + if (amdgpu_ring_sched_ready(ring)) + drm_sched_start(&ring->sched, true); + goto exit; + } + } + if (amdgpu_device_should_recover_gpu(ring->adev)) { struct amdgpu_reset_context reset_context; memset(&reset_context, 0, sizeof(reset_context)); From abd5601d040cf3f93fe8b3a7b8d45ac5f59e1201 Mon Sep 17 00:00:00 2001 From: Prike Liang Date: Wed, 12 Jun 2024 15:49:38 +0800 Subject: [PATCH 1270/1868] drm/amdgpu: increase the reset counter for the queue reset Update the reset counter for the amdgpu_cs_query_reset_state() Acked-by: Vitaly Prosyak Signed-off-by: Prike Liang Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c index c2de3fd172455..c6a1783fc9ef4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c @@ -84,6 +84,7 @@ static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job) if (!r) { if (amdgpu_ring_sched_ready(ring)) drm_sched_stop(&ring->sched, s_job); + atomic_inc(&ring->adev->gpu_reset_counter); amdgpu_fence_driver_force_completion(ring); if (amdgpu_ring_sched_ready(ring)) drm_sched_start(&ring->sched, true); From a81ce3b4f2513c9f041c9920f1189bc2e1ad2538 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 3 Jun 2024 17:23:14 -0400 Subject: [PATCH 1271/1868] drm/amdgpu/gfx9: add ring reset callback Add ring reset callback for compute. Acked-by: Vitaly Prosyak Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 38 +++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 792de29387508..47b528b74e3cb 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -7238,6 +7238,43 @@ static void gfx_v9_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop) amdgpu_ring_write(ring, ring->funcs->nop); } +static int gfx_v9_0_reset_kcq(struct amdgpu_ring *ring, + unsigned int vmid) +{ + struct amdgpu_device *adev = ring->adev; + struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; + struct amdgpu_ring *kiq_ring = &kiq->ring; + unsigned long flags; + int r; + + if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) + return -EINVAL; + + spin_lock_irqsave(&kiq->ring_lock, flags); + + if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { + spin_unlock_irqrestore(&kiq->ring_lock, flags); + return -ENOMEM; + } + + kiq->pmf->kiq_unmap_queues(kiq_ring, ring, RESET_QUEUES, + 0, 0); + amdgpu_ring_commit(kiq_ring); + + spin_unlock_irqrestore(&kiq->ring_lock, flags); + + r = amdgpu_ring_test_ring(kiq_ring); + if (r) + return r; + + /* reset the ring */ + ring->wptr = 0; + *ring->wptr_cpu_addr = 0; + amdgpu_ring_clear_ring(ring); + + return amdgpu_ring_test_ring(ring); +} + static void gfx_v9_ip_print(void *handle, struct drm_printer *p) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; @@ -7484,6 +7521,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = { .soft_recovery = gfx_v9_0_ring_soft_recovery, .emit_mem_sync = gfx_v9_0_emit_mem_sync, .emit_wave_limit = gfx_v9_0_emit_wave_limit, + .reset = gfx_v9_0_reset_kcq, }; static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = { From b6d418cd268655ed03c2d79ee9d4b14415b06fe9 Mon Sep 17 00:00:00 2001 From: Jiadong Zhu Date: Tue, 11 Jun 2024 18:06:44 +0800 Subject: [PATCH 1272/1868] drm/amdgpu/gfx9: remap queue after reset successfully Kiq command unmap_queues only does the dequeueing action. We have to map the queue back with clean mqd. Acked-by: Vitaly Prosyak Signed-off-by: Jiadong Zhu Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 36 ++++++++++++++++++++------- 1 file changed, 27 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 47b528b74e3cb..41f913651b876 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -3749,7 +3749,7 @@ static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring) return 0; } -static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring) +static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring, bool restore) { struct amdgpu_device *adev = ring->adev; struct v9_mqd *mqd = ring->mqd_ptr; @@ -3761,8 +3761,8 @@ static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring) */ tmp_mqd = (struct v9_mqd *)adev->gfx.mec.mqd_backup[mqd_idx]; - if (!tmp_mqd->cp_hqd_pq_control || - (!amdgpu_in_reset(adev) && !adev->in_suspend)) { + if (!restore && (!tmp_mqd->cp_hqd_pq_control || + (!amdgpu_in_reset(adev) && !adev->in_suspend))) { memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; @@ -3826,7 +3826,7 @@ static int gfx_v9_0_kcq_resume(struct amdgpu_device *adev) goto done; r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); if (!r) { - r = gfx_v9_0_kcq_init_queue(ring); + r = gfx_v9_0_kcq_init_queue(ring, false); amdgpu_bo_kunmap(ring->mqd_obj); ring->mqd_ptr = NULL; } @@ -7267,11 +7267,29 @@ static int gfx_v9_0_reset_kcq(struct amdgpu_ring *ring, if (r) return r; - /* reset the ring */ - ring->wptr = 0; - *ring->wptr_cpu_addr = 0; - amdgpu_ring_clear_ring(ring); - + r = amdgpu_bo_reserve(ring->mqd_obj, false); + if (unlikely(r != 0)){ + DRM_ERROR("fail to resv mqd_obj\n"); + return r; + } + r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); + if (!r) { + r = gfx_v9_0_kcq_init_queue(ring, true); + amdgpu_bo_kunmap(ring->mqd_obj); + ring->mqd_ptr = NULL; + } + amdgpu_bo_unreserve(ring->mqd_obj); + if (r){ + DRM_ERROR("fail to unresv mqd_obj\n"); + return r; + } + r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); + kiq->pmf->kiq_map_queues(kiq_ring, ring); + r = amdgpu_ring_test_ring(kiq_ring); + if (r){ + DRM_ERROR("fail to remap queue\n"); + return r; + } return amdgpu_ring_test_ring(ring); } From d9905a77848664e667931fe542ef0e675a7e1c5d Mon Sep 17 00:00:00 2001 From: Jiadong Zhu Date: Tue, 2 Jul 2024 09:03:49 +0800 Subject: [PATCH 1273/1868] drm/amdgpu/gfx9: wait for reset done before remap There is a racing condition that cp firmware modifies MQD in reset sequence after driver updates it for remapping. We have to wait till CP_HQD_ACTIVE becoming false then remap the queue. v2: fix KIQ locking (Alex) v3: fix KIQ locking harder Acked-by: Vitaly Prosyak Signed-off-by: Jiadong Zhu Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 36 +++++++++++++++++++++++---- 1 file changed, 31 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 41f913651b876..3a157b02d4907 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -7245,7 +7245,7 @@ static int gfx_v9_0_reset_kcq(struct amdgpu_ring *ring, struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; struct amdgpu_ring *kiq_ring = &kiq->ring; unsigned long flags; - int r; + int i, r; if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) return -EINVAL; @@ -7267,9 +7267,28 @@ static int gfx_v9_0_reset_kcq(struct amdgpu_ring *ring, if (r) return r; + /* make sure dequeue is complete*/ + gfx_v9_0_set_safe_mode(adev, 0); + mutex_lock(&adev->srbm_mutex); + soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, 0); + for (i = 0; i < adev->usec_timeout; i++) { + if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) + break; + udelay(1); + } + if (i >= adev->usec_timeout) + r = -ETIMEDOUT; + soc15_grbm_select(adev, 0, 0, 0, 0, 0); + mutex_unlock(&adev->srbm_mutex); + gfx_v9_0_unset_safe_mode(adev, 0); + if (r) { + dev_err(adev->dev, "fail to wait on hqd deactive\n"); + return r; + } + r = amdgpu_bo_reserve(ring->mqd_obj, false); if (unlikely(r != 0)){ - DRM_ERROR("fail to resv mqd_obj\n"); + dev_err(adev->dev, "fail to resv mqd_obj\n"); return r; } r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); @@ -7279,14 +7298,21 @@ static int gfx_v9_0_reset_kcq(struct amdgpu_ring *ring, ring->mqd_ptr = NULL; } amdgpu_bo_unreserve(ring->mqd_obj); - if (r){ - DRM_ERROR("fail to unresv mqd_obj\n"); + if (r) { + dev_err(adev->dev, "fail to unresv mqd_obj\n"); return r; } + spin_lock_irqsave(&kiq->ring_lock, flags); r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); + if (r) { + spin_unlock_irqrestore(&kiq->ring_lock, flags); + return -ENOMEM; + } kiq->pmf->kiq_map_queues(kiq_ring, ring); + amdgpu_ring_commit(kiq_ring); + spin_unlock_irqrestore(&kiq->ring_lock, flags); r = amdgpu_ring_test_ring(kiq_ring); - if (r){ + if (r) { DRM_ERROR("fail to remap queue\n"); return r; } From 94deb8e4182193a5f7e45eb4de8c166b2c53a0d1 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 3 Jun 2024 17:24:03 -0400 Subject: [PATCH 1274/1868] drm/amdgpu/gfx9.4.3: add ring reset callback Add ring reset callback for compute. Acked-by: Vitaly Prosyak Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 38 +++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index 7b4ae197eb49b..f1c73bc1bd95e 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -3426,6 +3426,43 @@ static void gfx_v9_4_3_emit_wave_limit(struct amdgpu_ring *ring, bool enable) } } +static int gfx_v9_4_3_reset_kcq(struct amdgpu_ring *ring, + unsigned int vmid) +{ + struct amdgpu_device *adev = ring->adev; + struct amdgpu_kiq *kiq = &adev->gfx.kiq[ring->xcc_id]; + struct amdgpu_ring *kiq_ring = &kiq->ring; + unsigned long flags; + int r; + + if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) + return -EINVAL; + + spin_lock_irqsave(&kiq->ring_lock, flags); + + if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { + spin_unlock_irqrestore(&kiq->ring_lock, flags); + return -ENOMEM; + } + + kiq->pmf->kiq_unmap_queues(kiq_ring, ring, RESET_QUEUES, + 0, 0); + amdgpu_ring_commit(kiq_ring); + + spin_unlock_irqrestore(&kiq->ring_lock, flags); + + r = amdgpu_ring_test_ring(kiq_ring); + if (r) + return r; + + /* reset the ring */ + ring->wptr = 0; + *ring->wptr_cpu_addr = 0; + amdgpu_ring_clear_ring(ring); + + return amdgpu_ring_test_ring(ring); +} + enum amdgpu_gfx_cp_ras_mem_id { AMDGPU_GFX_CP_MEM1 = 1, AMDGPU_GFX_CP_MEM2, @@ -4536,6 +4573,7 @@ static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_compute = { .soft_recovery = gfx_v9_4_3_ring_soft_recovery, .emit_mem_sync = gfx_v9_4_3_emit_mem_sync, .emit_wave_limit = gfx_v9_4_3_emit_wave_limit, + .reset = gfx_v9_4_3_reset_kcq, }; static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_kiq = { From f42d1fde38cf29b6f5fac8c284d939948652ba7c Mon Sep 17 00:00:00 2001 From: Jiadong Zhu Date: Fri, 14 Jun 2024 13:05:32 +0800 Subject: [PATCH 1275/1868] drm/amdgpu/gfx9.4.3: remap queue after reset successfully Kiq command unmap_queues only does the dequeueing action. We have to map the queue back with clean mqd. Acked-by: Vitaly Prosyak Signed-off-by: Jiadong Zhu Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 36 ++++++++++++++++++------- 1 file changed, 27 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index f1c73bc1bd95e..44c6e2d447220 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -2080,7 +2080,7 @@ static int gfx_v9_4_3_xcc_kiq_init_queue(struct amdgpu_ring *ring, int xcc_id) return 0; } -static int gfx_v9_4_3_xcc_kcq_init_queue(struct amdgpu_ring *ring, int xcc_id) +static int gfx_v9_4_3_xcc_kcq_init_queue(struct amdgpu_ring *ring, int xcc_id, bool restore) { struct amdgpu_device *adev = ring->adev; struct v9_mqd *mqd = ring->mqd_ptr; @@ -2092,8 +2092,8 @@ static int gfx_v9_4_3_xcc_kcq_init_queue(struct amdgpu_ring *ring, int xcc_id) */ tmp_mqd = (struct v9_mqd *)adev->gfx.mec.mqd_backup[mqd_idx]; - if (!tmp_mqd->cp_hqd_pq_control || - (!amdgpu_in_reset(adev) && !adev->in_suspend)) { + if (!restore && (!tmp_mqd->cp_hqd_pq_control || + (!amdgpu_in_reset(adev) && !adev->in_suspend))) { memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation)); ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF; ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF; @@ -2178,7 +2178,7 @@ static int gfx_v9_4_3_xcc_kcq_resume(struct amdgpu_device *adev, int xcc_id) goto done; r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); if (!r) { - r = gfx_v9_4_3_xcc_kcq_init_queue(ring, xcc_id); + r = gfx_v9_4_3_xcc_kcq_init_queue(ring, xcc_id, false); amdgpu_bo_kunmap(ring->mqd_obj); ring->mqd_ptr = NULL; } @@ -3455,11 +3455,29 @@ static int gfx_v9_4_3_reset_kcq(struct amdgpu_ring *ring, if (r) return r; - /* reset the ring */ - ring->wptr = 0; - *ring->wptr_cpu_addr = 0; - amdgpu_ring_clear_ring(ring); - + r = amdgpu_bo_reserve(ring->mqd_obj, false); + if (unlikely(r != 0)){ + DRM_ERROR("fail to resv mqd_obj\n"); + return r; + } + r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); + if (!r) { + r = gfx_v9_4_3_xcc_kcq_init_queue(ring, ring->xcc_id, true); + amdgpu_bo_kunmap(ring->mqd_obj); + ring->mqd_ptr = NULL; + } + amdgpu_bo_unreserve(ring->mqd_obj); + if (r){ + DRM_ERROR("fail to unresv mqd_obj\n"); + return r; + } + r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); + kiq->pmf->kiq_map_queues(kiq_ring, ring); + r = amdgpu_ring_test_ring(kiq_ring); + if (r){ + DRM_ERROR("fail to remap queue\n"); + return r; + } return amdgpu_ring_test_ring(ring); } From c38c11298626c5c0f914c2fc9706af76e2fca525 Mon Sep 17 00:00:00 2001 From: Jiadong Zhu Date: Fri, 28 Jun 2024 11:48:22 +0800 Subject: [PATCH 1276/1868] drm/amdgpu/gfx_9.4.3: wait for reset done before remap There is a racing condition that cp firmware modifies MQD in reset sequence after driver updates it for remapping. We have to wait till CP_HQD_ACTIVE becoming false then remap the queue. v2: fix KIQ locking (Alex) v3: fix KIQ locking harder Acked-by: Vitaly Prosyak Signed-off-by: Jiadong Zhu Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 39 +++++++++++++++++++++---- 1 file changed, 33 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index 44c6e2d447220..9a740020243d4 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -3433,7 +3433,7 @@ static int gfx_v9_4_3_reset_kcq(struct amdgpu_ring *ring, struct amdgpu_kiq *kiq = &adev->gfx.kiq[ring->xcc_id]; struct amdgpu_ring *kiq_ring = &kiq->ring; unsigned long flags; - int r; + int r, i; if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) return -EINVAL; @@ -3455,9 +3455,28 @@ static int gfx_v9_4_3_reset_kcq(struct amdgpu_ring *ring, if (r) return r; + /* make sure dequeue is complete*/ + gfx_v9_4_3_xcc_set_safe_mode(adev, ring->xcc_id); + mutex_lock(&adev->srbm_mutex); + soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, ring->xcc_id)); + for (i = 0; i < adev->usec_timeout; i++) { + if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) + break; + udelay(1); + } + if (i >= adev->usec_timeout) + r = -ETIMEDOUT; + soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, ring->xcc_id)); + mutex_unlock(&adev->srbm_mutex); + gfx_v9_4_3_xcc_unset_safe_mode(adev, ring->xcc_id); + if (r) { + dev_err(adev->dev, "fail to wait on hqd deactive\n"); + return r; + } + r = amdgpu_bo_reserve(ring->mqd_obj, false); if (unlikely(r != 0)){ - DRM_ERROR("fail to resv mqd_obj\n"); + dev_err(adev->dev, "fail to resv mqd_obj\n"); return r; } r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); @@ -3467,15 +3486,23 @@ static int gfx_v9_4_3_reset_kcq(struct amdgpu_ring *ring, ring->mqd_ptr = NULL; } amdgpu_bo_unreserve(ring->mqd_obj); - if (r){ - DRM_ERROR("fail to unresv mqd_obj\n"); + if (r) { + dev_err(adev->dev, "fail to unresv mqd_obj\n"); return r; } + spin_lock_irqsave(&kiq->ring_lock, flags); r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size); + if (r) { + spin_unlock_irqrestore(&kiq->ring_lock, flags); + return -ENOMEM; + } kiq->pmf->kiq_map_queues(kiq_ring, ring); + amdgpu_ring_commit(kiq_ring); + spin_unlock_irqrestore(&kiq->ring_lock, flags); + r = amdgpu_ring_test_ring(kiq_ring); - if (r){ - DRM_ERROR("fail to remap queue\n"); + if (r) { + dev_err(adev->dev, "fail to remap queue\n"); return r; } return amdgpu_ring_test_ring(ring); From a67a2d594c95b7ebab5f9c8c64f7b274045953d3 Mon Sep 17 00:00:00 2001 From: Jiadong Zhu Date: Thu, 4 Jul 2024 12:12:42 +0800 Subject: [PATCH 1277/1868] drm/amdgpu/gfx: add a new kiq_pm4_funcs callback for reset_hw_queue Add reset_hw_queue in kiq_pm4_funcs callbacks. Acked-by: Vitaly Prosyak Signed-off-by: Jiadong Zhu Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h index d35a095661329..4416843b2be16 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h @@ -138,6 +138,10 @@ struct kiq_pm4_funcs { void (*kiq_invalidate_tlbs)(struct amdgpu_ring *kiq_ring, uint16_t pasid, uint32_t flush_type, bool all_hub); + void (*kiq_reset_hw_queue)(struct amdgpu_ring *kiq_ring, + uint32_t queue_type, uint32_t me_id, + uint32_t pipe_id, uint32_t queue_id, + uint32_t xcc_id, uint32_t vmid); /* Packet sizes */ int set_resources_size; int map_queues_size; From 4c6c6cc0861d13617f64a6b9fa8d242c551280fd Mon Sep 17 00:00:00 2001 From: Jiadong Zhu Date: Thu, 4 Jul 2024 12:24:31 +0800 Subject: [PATCH 1278/1868] drm/amdgpu/gfx9: implement reset_hw_queue for gfx9 Using mmio to do queue reset. Enter safe mode when writing registers. Acked-by: Vitaly Prosyak Signed-off-by: Jiadong Zhu Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 37 +++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 3a157b02d4907..b9c8f75e07e58 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -893,6 +893,8 @@ static int gfx_v9_0_ras_error_inject(struct amdgpu_device *adev, static void gfx_v9_0_reset_ras_error_count(struct amdgpu_device *adev); static void gfx_v9_0_update_spm_vmid_internal(struct amdgpu_device *adev, unsigned int vmid); +static void gfx_v9_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id); +static void gfx_v9_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id); static void gfx_v9_0_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) @@ -1004,12 +1006,47 @@ static void gfx_v9_0_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); } + +static void gfx_v9_0_kiq_reset_hw_queue(struct amdgpu_ring *kiq_ring, uint32_t queue_type, + uint32_t me_id, uint32_t pipe_id, uint32_t queue_id, + uint32_t xcc_id, uint32_t vmid) +{ + struct amdgpu_device *adev = kiq_ring->adev; + unsigned i; + + /* enter save mode */ + gfx_v9_0_set_safe_mode(adev, xcc_id); + mutex_lock(&adev->srbm_mutex); + soc15_grbm_select(adev, me_id, pipe_id, queue_id, 0, 0); + + if (queue_type == AMDGPU_RING_TYPE_COMPUTE) { + WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 0x2); + WREG32_SOC15(GC, 0, mmSPI_COMPUTE_QUEUE_RESET, 0x1); + /* wait till dequeue take effects */ + for (i = 0; i < adev->usec_timeout; i++) { + if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) + break; + udelay(1); + } + if (i >= adev->usec_timeout) + dev_err(adev->dev, "fail to wait on hqd deactive\n"); + } else { + dev_err(adev->dev, "reset queue_type(%d) not supported\n", queue_type); + } + + soc15_grbm_select(adev, 0, 0, 0, 0, 0); + mutex_unlock(&adev->srbm_mutex); + /* exit safe mode */ + gfx_v9_0_unset_safe_mode(adev, xcc_id); +} + static const struct kiq_pm4_funcs gfx_v9_0_kiq_pm4_funcs = { .kiq_set_resources = gfx_v9_0_kiq_set_resources, .kiq_map_queues = gfx_v9_0_kiq_map_queues, .kiq_unmap_queues = gfx_v9_0_kiq_unmap_queues, .kiq_query_status = gfx_v9_0_kiq_query_status, .kiq_invalidate_tlbs = gfx_v9_0_kiq_invalidate_tlbs, + .kiq_reset_hw_queue = gfx_v9_0_kiq_reset_hw_queue, .set_resources_size = 8, .map_queues_size = 7, .unmap_queues_size = 6, From c8d3175d0397de87fe2e2b634a91e0103b895a04 Mon Sep 17 00:00:00 2001 From: Jiadong Zhu Date: Thu, 4 Jul 2024 14:51:58 +0800 Subject: [PATCH 1279/1868] drm/amdgpu/gfx9.4.3: implement reset_hw_queue for gfx9.4.3 Using mmio to do queue reset. Enter safe mode before writing mmio registers. v2: set register instance offset according to xcc id. Acked-by: Vitaly Prosyak Signed-off-by: Jiadong Zhu Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 36 +++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index 9a740020243d4..18cb6d45d54f2 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -200,6 +200,8 @@ static void gfx_v9_4_3_set_gds_init(struct amdgpu_device *adev); static void gfx_v9_4_3_set_rlc_funcs(struct amdgpu_device *adev); static int gfx_v9_4_3_get_cu_info(struct amdgpu_device *adev, struct amdgpu_cu_info *cu_info); +static void gfx_v9_4_3_xcc_set_safe_mode(struct amdgpu_device *adev, int xcc_id); +static void gfx_v9_4_3_xcc_unset_safe_mode(struct amdgpu_device *adev, int xcc_id); static void gfx_v9_4_3_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) @@ -311,12 +313,46 @@ static void gfx_v9_4_3_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring, PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type)); } +static void gfx_v9_4_3_kiq_reset_hw_queue(struct amdgpu_ring *kiq_ring, uint32_t queue_type, + uint32_t me_id, uint32_t pipe_id, uint32_t queue_id, + uint32_t xcc_id, uint32_t vmid) +{ + struct amdgpu_device *adev = kiq_ring->adev; + unsigned i; + + /* enter save mode */ + gfx_v9_4_3_xcc_set_safe_mode(adev, xcc_id); + mutex_lock(&adev->srbm_mutex); + soc15_grbm_select(adev, me_id, pipe_id, queue_id, 0, xcc_id); + + if (queue_type == AMDGPU_RING_TYPE_COMPUTE) { + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_DEQUEUE_REQUEST, 0x2); + WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_COMPUTE_QUEUE_RESET, 0x1); + /* wait till dequeue take effects */ + for (i = 0; i < adev->usec_timeout; i++) { + if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) + break; + udelay(1); + } + if (i >= adev->usec_timeout) + dev_err(adev->dev, "fail to wait on hqd deactive\n"); + } else { + dev_err(adev->dev, "reset queue_type(%d) not supported\n\n", queue_type); + } + + soc15_grbm_select(adev, 0, 0, 0, 0, 0); + mutex_unlock(&adev->srbm_mutex); + /* exit safe mode */ + gfx_v9_4_3_xcc_unset_safe_mode(adev, xcc_id); +} + static const struct kiq_pm4_funcs gfx_v9_4_3_kiq_pm4_funcs = { .kiq_set_resources = gfx_v9_4_3_kiq_set_resources, .kiq_map_queues = gfx_v9_4_3_kiq_map_queues, .kiq_unmap_queues = gfx_v9_4_3_kiq_unmap_queues, .kiq_query_status = gfx_v9_4_3_kiq_query_status, .kiq_invalidate_tlbs = gfx_v9_4_3_kiq_invalidate_tlbs, + .kiq_reset_hw_queue = gfx_v9_4_3_kiq_reset_hw_queue, .set_resources_size = 8, .map_queues_size = 7, .unmap_queues_size = 6, From 04c773993f037da9746c7d35c827e6174af2d016 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 18 Jul 2024 10:20:56 -0400 Subject: [PATCH 1280/1868] drm/amdgpu/gfx9: per queue reset only on bare metal It's not supported under SR-IOV at the moment. Acked-by: Vitaly Prosyak Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 3 +++ drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 3 +++ 2 files changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index b9c8f75e07e58..2b444ebc97f21 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -7284,6 +7284,9 @@ static int gfx_v9_0_reset_kcq(struct amdgpu_ring *ring, unsigned long flags; int i, r; + if (amdgpu_sriov_vf(adev)) + return -EINVAL; + if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) return -EINVAL; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index 18cb6d45d54f2..092e229f4097d 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -3471,6 +3471,9 @@ static int gfx_v9_4_3_reset_kcq(struct amdgpu_ring *ring, unsigned long flags; int r, i; + if (amdgpu_sriov_vf(adev)) + return -EINVAL; + if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) return -EINVAL; From 38a0d9d9b8a2b02665d18fb102e2a832c2e517b6 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 17 Jul 2024 19:02:50 -0400 Subject: [PATCH 1281/1868] drm/amdgpu/gfx9: add ring reset callback for gfx Add ring reset callback for gfx. Acked-by: Vitaly Prosyak Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 46 +++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 2b444ebc97f21..1f3f1f421fdb7 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -7275,6 +7275,51 @@ static void gfx_v9_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop) amdgpu_ring_write(ring, ring->funcs->nop); } +static int gfx_v9_0_reset_kgq(struct amdgpu_ring *ring, unsigned int vmid) +{ + struct amdgpu_device *adev = ring->adev; + struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; + struct amdgpu_ring *kiq_ring = &kiq->ring; + unsigned long flags; + u32 tmp; + int r; + + if (amdgpu_sriov_vf(adev)) + return -EINVAL; + + if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) + return -EINVAL; + + spin_lock_irqsave(&kiq->ring_lock, flags); + + if (amdgpu_ring_alloc(kiq_ring, 5)) { + spin_unlock_irqrestore(&kiq->ring_lock, flags); + return -ENOMEM; + } + + tmp = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid); + gfx_v9_0_ring_emit_wreg(kiq_ring, + SOC15_REG_OFFSET(GC, 0, mmCP_VMID_RESET), tmp); + amdgpu_ring_commit(kiq_ring); + + spin_unlock_irqrestore(&kiq->ring_lock, flags); + + r = amdgpu_ring_test_ring(kiq_ring); + if (r) + return r; + + if (amdgpu_ring_alloc(ring, 7 + 7 + 5)) + return -ENOMEM; + gfx_v9_0_ring_emit_fence(ring, ring->fence_drv.gpu_addr, + ring->fence_drv.sync_seq, AMDGPU_FENCE_FLAG_EXEC); + gfx_v9_0_ring_emit_reg_wait(ring, + SOC15_REG_OFFSET(GC, 0, mmCP_VMID_RESET), 0, 0xffff); + gfx_v9_0_ring_emit_wreg(ring, + SOC15_REG_OFFSET(GC, 0, mmCP_VMID_RESET), 0); + + return amdgpu_ring_test_ring(ring); +} + static int gfx_v9_0_reset_kcq(struct amdgpu_ring *ring, unsigned int vmid) { @@ -7511,6 +7556,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = { .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait, .soft_recovery = gfx_v9_0_ring_soft_recovery, .emit_mem_sync = gfx_v9_0_emit_mem_sync, + .reset = gfx_v9_0_reset_kgq, }; static const struct amdgpu_ring_funcs gfx_v9_0_sw_ring_funcs_gfx = { From a665daeabc3107ac10e6c9c0e17bb4a9a9bb50ac Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 24 Jul 2024 17:59:47 -0400 Subject: [PATCH 1282/1868] drm/amdgpu/gfx9: use proper rlc safe mode helpers Rather than open coding it for the queue reset. Acked-by: Vitaly Prosyak Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 1f3f1f421fdb7..04398bfd8ba8e 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -1015,7 +1015,7 @@ static void gfx_v9_0_kiq_reset_hw_queue(struct amdgpu_ring *kiq_ring, uint32_t q unsigned i; /* enter save mode */ - gfx_v9_0_set_safe_mode(adev, xcc_id); + amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); mutex_lock(&adev->srbm_mutex); soc15_grbm_select(adev, me_id, pipe_id, queue_id, 0, 0); @@ -1037,7 +1037,7 @@ static void gfx_v9_0_kiq_reset_hw_queue(struct amdgpu_ring *kiq_ring, uint32_t q soc15_grbm_select(adev, 0, 0, 0, 0, 0); mutex_unlock(&adev->srbm_mutex); /* exit safe mode */ - gfx_v9_0_unset_safe_mode(adev, xcc_id); + amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); } static const struct kiq_pm4_funcs gfx_v9_0_kiq_pm4_funcs = { @@ -7353,7 +7353,7 @@ static int gfx_v9_0_reset_kcq(struct amdgpu_ring *ring, return r; /* make sure dequeue is complete*/ - gfx_v9_0_set_safe_mode(adev, 0); + amdgpu_gfx_rlc_enter_safe_mode(adev, 0); mutex_lock(&adev->srbm_mutex); soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, 0); for (i = 0; i < adev->usec_timeout; i++) { @@ -7365,7 +7365,7 @@ static int gfx_v9_0_reset_kcq(struct amdgpu_ring *ring, r = -ETIMEDOUT; soc15_grbm_select(adev, 0, 0, 0, 0, 0); mutex_unlock(&adev->srbm_mutex); - gfx_v9_0_unset_safe_mode(adev, 0); + amdgpu_gfx_rlc_exit_safe_mode(adev, 0); if (r) { dev_err(adev->dev, "fail to wait on hqd deactive\n"); return r; From 8812efa5839881d88eafe34324c706542cf9b072 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 24 Jul 2024 18:04:44 -0400 Subject: [PATCH 1283/1868] drm/amdgpu/gfx9.4.3: use proper rlc safe mode helpers Rather than open coding it for the queue reset. Acked-by: Vitaly Prosyak Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index 092e229f4097d..9215666a6318a 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -321,7 +321,7 @@ static void gfx_v9_4_3_kiq_reset_hw_queue(struct amdgpu_ring *kiq_ring, uint32_t unsigned i; /* enter save mode */ - gfx_v9_4_3_xcc_set_safe_mode(adev, xcc_id); + amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); mutex_lock(&adev->srbm_mutex); soc15_grbm_select(adev, me_id, pipe_id, queue_id, 0, xcc_id); @@ -343,7 +343,7 @@ static void gfx_v9_4_3_kiq_reset_hw_queue(struct amdgpu_ring *kiq_ring, uint32_t soc15_grbm_select(adev, 0, 0, 0, 0, 0); mutex_unlock(&adev->srbm_mutex); /* exit safe mode */ - gfx_v9_4_3_xcc_unset_safe_mode(adev, xcc_id); + amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); } static const struct kiq_pm4_funcs gfx_v9_4_3_kiq_pm4_funcs = { @@ -3495,7 +3495,7 @@ static int gfx_v9_4_3_reset_kcq(struct amdgpu_ring *ring, return r; /* make sure dequeue is complete*/ - gfx_v9_4_3_xcc_set_safe_mode(adev, ring->xcc_id); + amdgpu_gfx_rlc_enter_safe_mode(adev, ring->xcc_id); mutex_lock(&adev->srbm_mutex); soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, ring->xcc_id)); for (i = 0; i < adev->usec_timeout; i++) { @@ -3507,7 +3507,7 @@ static int gfx_v9_4_3_reset_kcq(struct amdgpu_ring *ring, r = -ETIMEDOUT; soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, ring->xcc_id)); mutex_unlock(&adev->srbm_mutex); - gfx_v9_4_3_xcc_unset_safe_mode(adev, ring->xcc_id); + amdgpu_gfx_rlc_exit_safe_mode(adev, ring->xcc_id); if (r) { dev_err(adev->dev, "fail to wait on hqd deactive\n"); return r; From 41b20dad08be515da7b3b205c5f681f76db0da73 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 24 Jul 2024 18:20:44 -0400 Subject: [PATCH 1284/1868] drm/amdgpu/gfx9.4.3: use rlc safe mode for soft recovery Protect the MMIO access with safe mode. Acked-by: Vitaly Prosyak Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index 9215666a6318a..dd146322f2095 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -3054,7 +3054,9 @@ static void gfx_v9_4_3_ring_soft_recovery(struct amdgpu_ring *ring, value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); + amdgpu_gfx_rlc_enter_safe_mode(adev, ring->xcc_id); WREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regSQ_CMD, value); + amdgpu_gfx_rlc_exit_safe_mode(adev, ring->xcc_id); } static void gfx_v9_4_3_xcc_set_compute_eop_interrupt_state( From eaef2490b4d56b3d469f6d99cbdf3eb5455fd0c1 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 24 Jul 2024 18:20:57 -0400 Subject: [PATCH 1285/1868] drm/amdgpu/gfx9: use rlc safe mode for soft recovery Protect the MMIO access with safe mode. Acked-by: Vitaly Prosyak Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 04398bfd8ba8e..4cc2df31ee489 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -6001,7 +6001,9 @@ static void gfx_v9_0_ring_soft_recovery(struct amdgpu_ring *ring, unsigned vmid) value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); + amdgpu_gfx_rlc_enter_safe_mode(adev, 0); WREG32_SOC15(GC, 0, mmSQ_CMD, value); + amdgpu_gfx_rlc_exit_safe_mode(adev, 0); } static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev, From b77d8afe19cbc1d24a517b53fa06ad3e5c8944c9 Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Tue, 13 Aug 2024 22:34:26 +0530 Subject: [PATCH 1286/1868] drm/amdgpu: remove ME0 registers from mi300 dump Remove ME0 registers from MI300 gfx_9_4_3 ipdump MI300 does not have gfx ME and hence those register are just empty one and could be dropped. Signed-off-by: Sunil Khatri Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 37 ------------------------- 1 file changed, 37 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index dd146322f2095..619ff3ec2c863 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -75,42 +75,11 @@ static const struct amdgpu_hwip_reg_entry gc_reg_list_9_4_3[] = { SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT), SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS), SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR), - SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_BASE), - SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR), - SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR), - SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_BASE), - SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_RPTR), - SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_WPTR), - SOC15_REG_ENTRY_STR(GC, 0, regCP_RB1_BASE), - SOC15_REG_ENTRY_STR(GC, 0, regCP_RB1_RPTR), - SOC15_REG_ENTRY_STR(GC, 0, regCP_RB1_WPTR), - SOC15_REG_ENTRY_STR(GC, 0, regCP_RB2_BASE), - SOC15_REG_ENTRY_STR(GC, 0, regCP_RB2_WPTR), - SOC15_REG_ENTRY_STR(GC, 0, regCP_RB2_WPTR), - SOC15_REG_ENTRY_STR(GC, 0, regCP_CE_IB1_CMD_BUFSZ), - SOC15_REG_ENTRY_STR(GC, 0, regCP_CE_IB2_CMD_BUFSZ), - SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ), - SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_CMD_BUFSZ), - SOC15_REG_ENTRY_STR(GC, 0, regCP_CE_IB1_BASE_LO), - SOC15_REG_ENTRY_STR(GC, 0, regCP_CE_IB1_BASE_HI), - SOC15_REG_ENTRY_STR(GC, 0, regCP_CE_IB1_BUFSZ), - SOC15_REG_ENTRY_STR(GC, 0, regCP_CE_IB2_BASE_LO), - SOC15_REG_ENTRY_STR(GC, 0, regCP_CE_IB2_BASE_HI), - SOC15_REG_ENTRY_STR(GC, 0, regCP_CE_IB2_BUFSZ), - SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO), - SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI), - SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ), - SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_LO), - SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_HI), - SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BUFSZ), SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS), SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS), SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS), SOC15_REG_ENTRY_STR(GC, 0, regGDS_PROTECTION_FAULT), SOC15_REG_ENTRY_STR(GC, 0, regGDS_VM_PROTECTION_FAULT), - SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS), - SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_CNTL), - SOC15_REG_ENTRY_STR(GC, 0, regPA_CL_CNTL_STATUS), SOC15_REG_ENTRY_STR(GC, 0, regRLC_UTCL1_STATUS), SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS), SOC15_REG_ENTRY_STR(GC, 0, regSQC_DCACHE_UTCL1_STATUS), @@ -122,11 +91,8 @@ static const struct amdgpu_hwip_reg_entry gc_reg_list_9_4_3[] = { SOC15_REG_ENTRY_STR(GC, 0, regVM_L2_PROTECTION_FAULT_STATUS), SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG), SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL), - SOC15_REG_ENTRY_STR(GC, 0, regCP_CE_INSTR_PNTR), SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC1_INSTR_PNTR), SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC2_INSTR_PNTR), - SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_INSTR_PNTR), - SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_INSTR_PNTR), SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS), SOC15_REG_ENTRY_STR(GC, 0, regRLC_STAT), SOC15_REG_ENTRY_STR(GC, 0, regRLC_SMU_COMMAND), @@ -139,11 +105,8 @@ static const struct amdgpu_hwip_reg_entry gc_reg_list_9_4_3[] = { SOC15_REG_ENTRY_STR(GC, 0, regRLC_INT_STAT), SOC15_REG_ENTRY_STR(GC, 0, regRLC_GPM_GENERAL_6), /* cp header registers */ - SOC15_REG_ENTRY_STR(GC, 0, regCP_CE_HEADER_DUMP), SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME2_HEADER_DUMP), - SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_HEADER_DUMP), - SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_HEADER_DUMP), /* SE status registers */ SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0), SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1), From 5dff4a59fd2ba1dbebf8f2c73611bdb3d0b84c7a Mon Sep 17 00:00:00 2001 From: Yang Wang Date: Tue, 13 Aug 2024 13:51:48 +0800 Subject: [PATCH 1287/1868] drm/amdgpu: fixing rlc firmware loading failure issue Skip rlc firmware validation to ignore firmware header size mismatch issues. Refs: 49e133c973ce ("drm/amdgpu: Fix the null pointer when load rlc firmware") Fixes: e1c6c2c1099f ("drm/amdgpu: refine gfx10 firmware loading") Signed-off-by: Yang Wang Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index f9f346c9d4bda..56ad3f9bce0ad 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -4116,6 +4116,7 @@ static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev) static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) { + char fw_name[53]; char ucode_prefix[30]; const char *wks = ""; int err; @@ -4149,8 +4150,8 @@ static int gfx_v10_0_init_microcode(struct amdgpu_device *adev) amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_CE); if (!amdgpu_sriov_vf(adev)) { - err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, - "amdgpu/%s_rlc.bin", ucode_prefix); + snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", ucode_prefix); + err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev); if (err) goto out; From 6b35dff063de3f781d307e6780885328026285bf Mon Sep 17 00:00:00 2001 From: Zhang Zekun Date: Mon, 12 Aug 2024 20:24:15 +0800 Subject: [PATCH 1288/1868] drm/amd: Remove unused declarations amdgpu_gart_table_vram_pin() and amdgpu_gart_table_vram_unpin() has been removed since commit 575e55ee4fbc ("drm/amdgpu: recover gart table at resume") remain the declarations untouched in the header files. Besides, amdgpu_dm_display_resume() has also beed removed since commit a80aa93de1a0 ("drm/amd/display: Unify dm resume sequence into a single call"). So, let's remove this unused declarations. Signed-off-by: Zhang Zekun Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 7 ------- drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h | 2 -- 2 files changed, 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index cbea1bb3425ca..c28008f6f1e88 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1616,13 +1616,6 @@ static inline bool amdgpu_acpi_is_s3_active(struct amdgpu_device *adev) { return static inline void amdgpu_choose_low_power_state(struct amdgpu_device *adev) { } #endif -#if defined(CONFIG_DRM_AMD_DC) -int amdgpu_dm_display_resume(struct amdgpu_device *adev ); -#else -static inline int amdgpu_dm_display_resume(struct amdgpu_device *adev) { return 0; } -#endif - - void amdgpu_register_gpu_instance(struct amdgpu_device *adev); void amdgpu_unregister_gpu_instance(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h index 8283d682f543b..7cc980bf4725d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h @@ -55,8 +55,6 @@ int amdgpu_gart_table_ram_alloc(struct amdgpu_device *adev); void amdgpu_gart_table_ram_free(struct amdgpu_device *adev); int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev); void amdgpu_gart_table_vram_free(struct amdgpu_device *adev); -int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev); -void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev); int amdgpu_gart_init(struct amdgpu_device *adev); void amdgpu_gart_dummy_page_fini(struct amdgpu_device *adev); void amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset, From b2420702e19b62dc91edbf1d95544d35732324e0 Mon Sep 17 00:00:00 2001 From: David Yat Sin Date: Fri, 9 Apr 2021 12:30:43 -0400 Subject: [PATCH 1289/1868] drm/amdkfd: CRIU implement gpu_id remapping When doing a restore on a different node, the gpu_id's on the restore node may be different. But the user space application will still refer use the original gpu_id's in the ioctl calls. Adding code to create a gpu id mapping so that kfd can determine actual gpu_id during the user ioctl's. Reviewed-by: Felix Kuehling Signed-off-by: David Yat Sin Signed-off-by: Rajneesh Bhardwaj Change-Id: I89ca4a2f5e534391e0e13cbdaf58aafee2ba6021 --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 9f22c14e13b54..9e9ac4d289b21 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1650,14 +1650,16 @@ static int kfd_ioctl_ipc_export_handle(struct file *filep, void *data) { struct kfd_ioctl_ipc_export_handle_args *args = data; - struct kfd_dev *dev; + struct kfd_process_device *pdd; int r; - dev = kfd_device_by_id(args->gpu_id); - if (!dev) + mutex_lock(&p->mutex); + pdd = kfd_process_device_data_by_id(p, args->gpu_id); + mutex_unlock(&p->mutex); + if (!pdd) return -EINVAL; - r = kfd_ipc_export_as_handle(dev, p, args->handle, args->share_handle, + r = kfd_ipc_export_as_handle(pdd->dev, p, args->handle, args->share_handle, args->flags); if (r) pr_err("Failed to export IPC handle\n"); @@ -2715,7 +2717,7 @@ static int criu_restore_bos(struct kfd_process *p, exit: while (ret && i--) { if (bo_buckets[i].alloc_flags - & (KFD_IOC_ALLOC_MEM_FLAGS_VRAM | KFD_IOC_ALLOC_MEM_FLAGS_GTT)) + & (KFD_IOC_ALLOC_MEM_FLAGS_VRAM | KFD_IOC_ALLOC_MEM_FLAGS_GTT)) close_fd(bo_buckets[i].dmabuf_fd); } kvfree(bo_buckets); From 0a4bdf5bc51fadc32f635c0455325245de1faeb3 Mon Sep 17 00:00:00 2001 From: Alex Sierra Date: Wed, 1 Apr 2020 16:35:06 -0500 Subject: [PATCH 1290/1868] drm/amdgpu: replace per_device_list by array Remove per_device_list from kfd_process and replace it with a kfd_process_device pointers array of MAX_GPU_INSTANCES size. This helps to manage the kfd_process_devices binded to a specific kfd_process. Also, functions used by kfd_chardev to iterate over the list were removed, since they are not valid anymore. Instead, it was replaced by a local loop iterating the array. v2: This change aligns with 'commit 56096e4ac889 ("drm/amdgpu: replace per_device_list by array")' in amd-staging-drm-next. Signed-off-by: Alex Sierra Signed-off-by: Felix Kuehling Signed-off-by: Jonathan Kim Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index bccbdf951dfd1..f287e1d58c0e4 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -952,7 +952,6 @@ static void kfd_process_device_free_bos(struct kfd_process_device *pdd) * local memory object */ idr_for_each_entry(&pdd->alloc_idr, buf_obj, id) { - struct kfd_process_device *peer_pdd; for (i = 0; i < p->n_pdds; i++) { struct kfd_process_device *peer_pdd = p->pdds[i]; @@ -1649,6 +1648,7 @@ struct kfd_process_device *kfd_create_process_device_data(struct kfd_node *dev, pdd->sdma_past_activity_counter = 0; pdd->user_gpu_id = dev->id; atomic64_set(&pdd->evict_duration_counter, 0); + kfd_spm_init_process_device(pdd); if (dev->kfd->shared_resources.enable_mes) { retval = amdgpu_amdkfd_alloc_gtt_mem(dev->adev, @@ -2097,24 +2097,24 @@ void kfd_process_schedule_restore(struct kfd_process *p) static void kfd_process_unmap_doorbells(struct kfd_process *p) { - struct kfd_process_device *pdd; struct mm_struct *mm = p->mm; + int i; mmap_write_lock(mm); - list_for_each_entry(pdd, &p->per_device_data, per_device_list) - kfd_doorbell_unmap(pdd); + for (i = 0; i < p->n_pdds; i++) + kfd_doorbell_unmap(p->pdds[i]); mmap_write_unlock(mm); } int kfd_process_remap_doorbells_locked(struct kfd_process *p) { - struct kfd_process_device *pdd; int ret = 0; + int i; - list_for_each_entry(pdd, &p->per_device_data, per_device_list) - ret = kfd_doorbell_remap(pdd); + for (i = 0; i < p->n_pdds; i++) + ret = kfd_doorbell_remap(p->pdds[i]); return ret; } @@ -2139,8 +2139,8 @@ static int kfd_process_remap_doorbells(struct kfd_process *p) */ static bool kfd_process_unmap_doorbells_if_idle(struct kfd_process *p) { - struct kfd_process_device *pdd; bool busy = false; + int i; if (!keep_idle_process_evicted) return false; @@ -2151,7 +2151,9 @@ static bool kfd_process_unmap_doorbells_if_idle(struct kfd_process *p) */ kfd_process_unmap_doorbells(p); - list_for_each_entry(pdd, &p->per_device_data, per_device_list) { + for (i = 0; i < p->n_pdds; i++) { + struct kfd_process_device *pdd = p->pdds[i]; + busy = check_if_queues_active(pdd->qpd.dqm, &pdd->qpd); if (busy) break; From 65dcda478f0893e00933498a21baa87b7834370c Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Tue, 16 Nov 2021 23:15:55 -0500 Subject: [PATCH 1291/1868] drm/amdkfd: Implement DMA buf fd export from KFD MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Exports a DMA buf fd of a given KFD buffer handle. This is intended for being able to import KFD BOs into GEM contexts to leverage the amdgpu_bo_va API for more flexible virtual address mappings. It will also be used for the new upstreamable RDMA solution coming to UCX and RCCL. The corresponding user mode change (Thunk API and kfdtest) is here: https://github.com/fxkamd/ROCT-Thunk-Interface/commits/fxkamd/dmabuf Signed-off-by: Felix Kuehling Acked-by: Christian König Reviewed-by: Xiaogang Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 004bef6645e38..6608c8f192862 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -2830,11 +2830,12 @@ int amdgpu_amdkfd_gpuvm_export_ipc_obj(struct amdgpu_device *adev, void *vm, goto unlock_out; } - dmabuf = amdgpu_gem_prime_export(&mem->bo->tbo.base, 0); - if (IS_ERR(dmabuf)) { - r = PTR_ERR(dmabuf); + r = kfd_mem_export_dmabuf(mem); + if (r) goto unlock_out; - } + + get_dma_buf(mem->dmabuf); + dmabuf = mem->dmabuf; r = kfd_ipc_store_insert(dmabuf, &mem->ipc_obj, flags, restore_handle); if (r) From 17a07ff7e0747a4d179f5047fa05e2454723d2c4 Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Tue, 1 Mar 2022 22:28:53 +0800 Subject: [PATCH 1292/1868] drm/amdgpu: convert code name to ip version for noretry set Use IP version rather than codename for noretry set. Signed-off-by: Yifan Zhang Reviewed-by: Alex Deucher Change-Id: I171004a0b31f27903f2db30c66f21379294aba70 --- drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c index b49b3650fd621..1e7743b3f77d9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c @@ -893,6 +893,27 @@ void amdgpu_gmc_noretry_set(struct amdgpu_device *adev) gmc->noretry = 1; else gmc->noretry = (amdgpu_noretry == -1) ? noretry_default : amdgpu_noretry; + + /* keep this for kfd test fail */ + switch (adev->asic_type) { + case CHIP_VEGA10: + case CHIP_NAVI10: + case CHIP_NAVI14: + case CHIP_SIENNA_CICHLID: + case CHIP_NAVY_FLOUNDER: + case CHIP_DIMGREY_CAVEFISH: + /* + * noretry = 0 will cause kfd page fault tests fail + * for some ASICs, so set default to 1 for these ASICs. + */ + if (amdgpu_noretry == -1) + gmc->noretry = 1; + else + gmc->noretry = amdgpu_noretry; + break; + default: + break; + } } void amdgpu_gmc_set_vm_fault_masks(struct amdgpu_device *adev, int hub_type, From 6a62cccabf2d451e8015e35322d6a9f8d29b78cf Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 7 Dec 2023 10:39:06 +0800 Subject: [PATCH 1293/1868] drm/amdkfd: Import DMABufs for interop through DRM MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use drm_gem_prime_fd_to_handle to import DMABufs for interop. This ensures that a GEM handle is created on import and that obj->dma_buf will be set and remain set as long as the object is imported into KFD. Signed-off-by: Felix Kuehling Reviewed-by: Ramesh Errabolu Reviewed-by: Xiaogang.Chen Acked-by: Christian König Signed-off-by: Alex Deucher Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 2 +- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 43 ++++++++++++++++++- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_ipc.c | 24 +---------- drivers/gpu/drm/amd/amdkfd/kfd_ipc.h | 4 -- 5 files changed, 44 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index 41e6651f86a90..c5efe667f7ccf 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -381,7 +381,7 @@ void amdgpu_amdkfd_gpuvm_put_sg_table(struct amdgpu_bo *bo, struct device *dma_dev, enum dma_data_direction dir, struct sg_table *sg); -int amdgpu_amdkfd_gpuvm_import_dmabuf(struct amdgpu_device *adev, +int amdgpu_amdkfd_gpuvm_import_ipcobj(struct amdgpu_device *adev, struct dma_buf *dmabuf, struct kfd_ipc_obj *ipc_obj, uint64_t va, void *drm_priv, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 6608c8f192862..fcf151545c2b4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -2113,7 +2113,8 @@ int amdgpu_amdkfd_gpuvm_free_memory_of_gpu( /* Free the BO*/ drm_vma_node_revoke(&mem->bo->tbo.base.vma_node, drm_priv); - drm_gem_handle_delete(adev->kfd.client.file, mem->gem_handle); + if (!mem->ipc_obj) + drm_gem_handle_delete(adev->kfd.client.file, mem->gem_handle); if (mem->dmabuf) { dma_buf_put(mem->dmabuf); mem->dmabuf = NULL; @@ -2728,7 +2729,6 @@ static int import_obj_create(struct amdgpu_device *adev, get_dma_buf(dma_buf); (*mem)->dmabuf = dma_buf; (*mem)->bo = bo; - (*mem)->ipc_obj = ipc_obj; (*mem)->va = va; (*mem)->domain = (bo->preferred_domains & AMDGPU_GEM_DOMAIN_VRAM) && !(adev->flags & AMD_IS_APU) ? @@ -2759,6 +2759,45 @@ static int import_obj_create(struct amdgpu_device *adev, return ret; } +int amdgpu_amdkfd_gpuvm_import_ipcobj(struct amdgpu_device *adev, + struct dma_buf *dma_buf, + struct kfd_ipc_obj *ipc_obj, + uint64_t va, void *drm_priv, + struct kgd_mem **mem, uint64_t *size, + uint64_t *mmap_offset) +{ + struct drm_gem_object *obj; + int ret; + + if (WARN_ON(!ipc_obj)) + return -EINVAL; + +#ifdef AMDKCL_AMDGPU_DMABUF_OPS + obj = amdgpu_gem_prime_import(adev_to_drm(adev), dma_buf); + if (IS_ERR(obj)) + return PTR_ERR(obj); +#else + obj = dma_buf->priv; + if (drm_to_adev(obj->dev) != adev) + /* Can't handle buffers from other devices */ + return -EINVAL; + drm_gem_object_get(obj); +#endif + + ret = import_obj_create(adev, dma_buf, obj, va, drm_priv, mem, size, + mmap_offset); + if (ret) + goto err_put_obj; + + (*mem)->ipc_obj = ipc_obj; + + return 0; + +err_put_obj: + drm_gem_object_put(obj); + return ret; +} + int amdgpu_amdkfd_gpuvm_import_dmabuf_fd(struct amdgpu_device *adev, int fd, uint64_t va, void *drm_priv, struct kgd_mem **mem, uint64_t *size, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 9e9ac4d289b21..4ae65500bc167 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1639,7 +1639,7 @@ static int kfd_ioctl_import_dmabuf(struct file *filep, err_free: amdgpu_amdkfd_gpuvm_free_memory_of_gpu(pdd->dev->adev, (struct kgd_mem *)mem, - pdd->drm_priv, NULL); + pdd->drm_priv, NULL); err_unlock: mutex_unlock(&p->mutex); return r; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c index ab5769b0fe078..055a4c9364471 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.c @@ -158,7 +158,7 @@ static int kfd_import_dmabuf_create_kfd_bo(struct kfd_node *dev, if (IS_ERR(pdd)) return PTR_ERR(pdd); - r = amdgpu_amdkfd_gpuvm_import_dmabuf(dev->adev, dmabuf, ipc_obj, + r = amdgpu_amdkfd_gpuvm_import_ipcobj(dev->adev, dmabuf, ipc_obj, va_addr, pdd->drm_priv, &mem, &size, mmap_offset); if (r) @@ -180,28 +180,6 @@ static int kfd_import_dmabuf_create_kfd_bo(struct kfd_node *dev, return r; } -int kfd_ipc_import_dmabuf(struct kfd_node *dev, - struct kfd_process *p, - uint32_t gpu_id, int dmabuf_fd, - uint64_t va_addr, uint64_t *handle, - uint64_t *mmap_offset) -{ - int r; - struct dma_buf *dmabuf = dma_buf_get(dmabuf_fd); - - if (!dmabuf) - return -EINVAL; - - mutex_lock(&p->mutex); - - r = kfd_import_dmabuf_create_kfd_bo(dev, p, gpu_id, dmabuf, NULL, - va_addr, handle, mmap_offset, false); - - mutex_unlock(&p->mutex); - dma_buf_put(dmabuf); - return r; -} - int kfd_ipc_import_handle(struct kfd_node *dev, struct kfd_process *p, uint32_t gpu_id, uint32_t *share_handle, uint64_t va_addr, uint64_t *handle, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h index 6e92cce265d9e..ade507630818d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_ipc.h @@ -43,10 +43,6 @@ int kfd_ipc_import_handle(struct kfd_node *dev, struct kfd_process *p, uint32_t gpu_id, uint32_t *share_handle, uint64_t va_addr, uint64_t *handle, uint64_t *mmap_offset, uint32_t *pflags, bool restore); -int kfd_ipc_import_dmabuf(struct kfd_node *kfd, struct kfd_process *p, - uint32_t gpu_id, int dmabuf_fd, - uint64_t va_addr, uint64_t *handle, - uint64_t *mmap_offset); int kfd_ipc_export_as_handle(struct kfd_node *dev, struct kfd_process *p, uint64_t handle, uint32_t *ipc_handle, uint32_t flags); From a3b5f169a317d4219b0456bea4f30904a2bf30d3 Mon Sep 17 00:00:00 2001 From: Felix Kuehling Date: Wed, 17 Apr 2024 23:19:25 -0400 Subject: [PATCH 1294/1868] drm/amdkfd: Run restore_workers on freezable WQs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Make restore workers freezable so we don't have to explicitly flush them in suspend and GPU reset code paths, and we don't accidentally try to restore BOs while the GPU is suspended. Not having to flush restore_work also helps avoid lock/fence dependencies in the GPU reset case where we're not allowed to wait for fences. A side effect of this is, that we can now have multiple concurrent threads trying to signal the same eviction fence. Rework eviction fence signaling and replacement to account for that. The GPU reset path can no longer rely on restore_process_worker to resume queues because evict/restore workers can run independently of it. Instead call a new restore_process_helper directly. v2: - Reworked eviction fence signaling - Introduced restore_process_helper v3: - Handle unsignaled eviction fences in restore_process_bos v4: - Ported to DKMS branch and squashed with "drm/amdkfd: Fix eviction fence handling" Signed-off-by: Felix Kuehling Acked-by: Christian König Tested-by: Emily Deng Signed-off-by: Alex Deucher Tested-by: Gang BA Reviewed-by: Gang BA Tested-by: Vitaly Prosyak --- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index f287e1d58c0e4..4be8e0c99f84a 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -2077,7 +2077,6 @@ static int signal_eviction_fence(struct kfd_process *p) void kfd_process_schedule_restore(struct kfd_process *p) { - int ret; unsigned long evicted_jiffies; unsigned long delay_jiffies = msecs_to_jiffies(PROCESS_RESTORE_TIME_MS); @@ -2090,9 +2089,8 @@ void kfd_process_schedule_restore(struct kfd_process *p) delay_jiffies = 0; pr_debug("Process %d schedule restore work\n", p->pasid); - ret = queue_delayed_work(kfd_restore_wq, &p->restore_work, - delay_jiffies); - WARN(!ret, "Schedule restore work failed\n"); + if (mod_delayed_work(kfd_restore_wq, &p->restore_work, delay_jiffies)) + kfd_process_restore_queues(p); } static void kfd_process_unmap_doorbells(struct kfd_process *p) @@ -2213,7 +2211,6 @@ static int restore_process_helper(struct kfd_process *p) } ret = kfd_process_restore_queues(p); - trace_kfd_restore_process_worker_end(p, ret ? "Failed" : "Success"); if (!ret) pr_debug("Finished restoring pasid 0x%x\n", p->pasid); else @@ -2234,6 +2231,13 @@ static void restore_process_worker(struct work_struct *work) * lifetime of this thread, kfd_process p will be valid */ p = container_of(dwork, struct kfd_process, restore_work); + + if (kfd_process_unmap_doorbells_if_idle(p)) { + pr_debug("Process %d queues idle, doorbell unmapped\n", + p->pasid); + return; + } + pr_debug("Started restoring pasid 0x%x\n", p->pasid); trace_kfd_restore_process_worker_start(p); From 9aea123444168c25e540f037649b0d87e240b718 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Sun, 18 Aug 2024 13:48:05 +0800 Subject: [PATCH 1295/1868] drm/kcl: fake drm/drm_fbdev_ttm.h header It's caused by v6.9-rc6-1436-gaae4682e5d66 drm/fbdev-generic: Convert to fbdev-ttm v6.1-rc2-542-g8ab59da26bc0 drm/fb-helper: Move generic fbdev emulation into separate source file Signed-off-by: Asher Song --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 | 7 +++++++ include/kcl/backport/kcl_drm_fbdev_ttm.h | 16 ++++++++++++++++ include/kcl/header/drm/drm_fbdev_generic.h | 9 +++++++++ include/kcl/header/drm/drm_fbdev_ttm.h | 11 +++++++++++ 5 files changed, 44 insertions(+) create mode 100644 include/kcl/backport/kcl_drm_fbdev_ttm.h create mode 100644 include/kcl/header/drm/drm_fbdev_generic.h create mode 100644 include/kcl/header/drm/drm_fbdev_ttm.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 78ab1d617f6b3..2c85c76158ba5 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -126,4 +126,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 index 6dd1ab847b3bb..6b06ae6f73fef 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-headers.m4 @@ -110,4 +110,11 @@ AC_DEFUN([AC_AMDGPU_DRM_HEADERS], [ dnl # drm/edid: split out drm_eld.h from drm_edid.h dnl # AC_KERNEL_CHECK_HEADERS([drm/drm_eld.h]) + + dnl # + dnl # v6.9-rc6-1436-gaae4682e5d66 + dnl # drm/fbdev-generic: Convert to fbdev-ttm + dnl # + AC_KERNEL_CHECK_HEADERS([drm/drm_fbdev_ttm.h]) + ]) diff --git a/include/kcl/backport/kcl_drm_fbdev_ttm.h b/include/kcl/backport/kcl_drm_fbdev_ttm.h new file mode 100644 index 0000000000000..03ddc7699ddb1 --- /dev/null +++ b/include/kcl/backport/kcl_drm_fbdev_ttm.h @@ -0,0 +1,16 @@ +#ifndef __KCL_BACKPORT_KCL_DRM_DRV_H_ +#define __KCL_BACKPORT_KCL_DRM_DRV_H__ + +#include +#include + +#ifndef HAVE_DRM_DRM_FBDEV_TTM_H +static inline +void _kcl_drm_fbdev_ttm_setup(struct drm_device *dev, unsigned int preferred_bpp) +{ + return drm_fbdev_generic_setup(dev, preferred_bpp); +} +#define drm_fbdev_ttm_setup _kcl_drm_fbdev_ttm_setup +#endif + +#endif diff --git a/include/kcl/header/drm/drm_fbdev_generic.h b/include/kcl/header/drm/drm_fbdev_generic.h new file mode 100644 index 0000000000000..13b6f65c37f01 --- /dev/null +++ b/include/kcl/header/drm/drm_fbdev_generic.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DRM_DRM_FBDEV_GENERIC_H_H_ +#define _KCL_HEADER_DRM_DRM_FBDEV_GENERIC_H_H_ + +#ifdef HAVE_DRM_DRM_FBDEV_GENERIC_H +#include_next +#endif + +#endif diff --git a/include/kcl/header/drm/drm_fbdev_ttm.h b/include/kcl/header/drm/drm_fbdev_ttm.h new file mode 100644 index 0000000000000..dbf67afb91594 --- /dev/null +++ b/include/kcl/header/drm/drm_fbdev_ttm.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef _KCL_HEADER_DRM_DRM_FBDEV_TTM_H_H_ +#define _KCL_HEADER_DRM_DRM_FBDEV_TTM_H_H_ + +#ifdef HAVE_DRM_DRM_FBDEV_TTM_H +#include_next +#else +#include +#endif + +#endif From 9adc76b15bd0f08441fc0e2d481f2a06dd1c279c Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 23 Aug 2024 16:21:31 +0800 Subject: [PATCH 1296/1868] drm/amdkcl: fake drm_crtc_vblank_crtc It's caused by v6.9-rc2-247-gd12e36494dc2 drm/vblank: Introduce drm_crtc_vblank_crtc() Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdkcl/Makefile | 3 +- drivers/gpu/drm/amd/amdkcl/kcl_drm_vblank.c | 43 +++++++++++++++++++++ drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/m4/drm-vblank.m4 | 16 ++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_drm_vblank.h | 36 +++++++++++++++++ 6 files changed, 99 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_drm_vblank.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm-vblank.m4 create mode 100644 include/kcl/kcl_drm_vblank.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index 3fbd585862102..fd7c388cef2bf 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -14,7 +14,8 @@ amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_acpi_table.o kcl_page_alloc.o kcl_numa.o kcl_fs_read_write.o kcl_drm_aperture.o \ kcl_drm_simple_kms_helper.o kcl_bitmap.o kcl_vmscan.o kcl_dma_fence_chain.o \ kcl_mce_amd.o kcl_workqueue.o kcl_cpumask.o kcl_drm_dsc_helper.o kcl_mm_slab.o \ - kcl_irqdesc.o kcl_drm_suballoc.o kcl_drm_exec.o kcl_drm_dp_helper.o kcl_drm_prime.o + kcl_irqdesc.o kcl_drm_suballoc.o kcl_drm_exec.o kcl_drm_dp_helper.o kcl_drm_prime.o \ + kcl_drm_vblank.o amdkcl-$(CONFIG_DRM_AMD_DC_HDCP) += kcl_drm_hdcp.o amdkcl-$(CONFIG_MMU_NOTIFIER) += kcl_mn.o diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_drm_vblank.c b/drivers/gpu/drm/amd/amdkcl/kcl_drm_vblank.c new file mode 100644 index 0000000000000..f8d4ab7de31e3 --- /dev/null +++ b/drivers/gpu/drm/amd/amdkcl/kcl_drm_vblank.c @@ -0,0 +1,43 @@ +/* + * drm_irq.c IRQ and vblank support + * + * \author Rickard E. (Rik) Faith + * \author Gareth Hughes + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +#include + +/*copy from drivers/gpu/drm/drm_vblank.c */ +#ifndef HAVE_CRTC_DRM_VBLANK_CRTC +static struct drm_vblank_crtc * +drm_vblank_crtc(struct drm_device *dev, unsigned int pipe) +{ + return &dev->vblank[pipe]; +} + +struct drm_vblank_crtc * +drm_crtc_vblank_crtc(struct drm_crtc *crtc) +{ + return drm_vblank_crtc(crtc->dev, drm_crtc_index(crtc)); +} +EXPORT_SYMBOL(drm_crtc_vblank_crtc); +#endif + diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 2c85c76158ba5..7ce2f26657bf8 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -127,4 +127,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-vblank.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-vblank.m4 new file mode 100644 index 0000000000000..d2f9038b46063 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm-vblank.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v6.9-rc2-247-gd12e36494dc2 +dnl # drm/vblank: Introduce drm_crtc_vblank_crtc() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_CRTC_VBLANK_CRTC], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + drm_crtc_vblank_crtc(NULL); + ],[ + AC_DEFINE(HAVE_CRTC_DRM_VBLANK_CRTC, 1, + [drm_edid_raw() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index d3355c7866a69..29a4be897df1e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -237,6 +237,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_DEBUG_CATEGORY AC_AMDGPU_SMCA_UMC_V2 AC_AMDGPU_TOPOLOGY_NUM_CORES_PER_PACKAGE + AC_AMDGPU_DRM_CRTC_VBLANK_CRTC AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/kcl_drm_vblank.h b/include/kcl/kcl_drm_vblank.h new file mode 100644 index 0000000000000..4a74049654c92 --- /dev/null +++ b/include/kcl/kcl_drm_vblank.h @@ -0,0 +1,36 @@ +/* + * Copyright 2016 Intel Corp. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _KCL_KCL_DRM_VBLANK_H +#define _KCL_KCL_DRM_VBLANK_H + +#include +#include +#include + +/*copy from include/drm/drm_vblank.h */ +#ifndef HAVE_CRTC_DRM_VBLANK_CRTC +struct drm_vblank_crtc *drm_crtc_vblank_crtc(struct drm_crtc *crtc); +#endif + +#endif /*_KCL_KCL_DRM_VBLANK_H */ From c409da392f4ede84e8dcf6380533038b7f3705b5 Mon Sep 17 00:00:00 2001 From: Leo Li Date: Thu, 11 Jul 2024 10:24:50 -0400 Subject: [PATCH 1297/1868] Revert "drm/amd/display: Reset freesync config before update new state" This change caused PSR SU panels to not read from their remote fb, preventing us from entering self-refresh. It is a regression. This reverts commit f8ebe6341a6a3745ef02648b4b5c2c89fa4a9ace. Signed-off-by: Leo Li Acked-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 18201a2b44251..b8c22c77b3ae3 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -10732,7 +10732,6 @@ static int dm_update_crtc_state(struct amdgpu_display_manager *dm, } /* Update Freesync settings. */ - reset_freesync_config_for_crtc(dm_new_crtc_state); get_freesync_config_for_crtc(dm_new_crtc_state, dm_new_conn_state); From 528acb9461d049382cedfea7af9826f7d53b62db Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 21 Aug 2024 18:02:16 +0800 Subject: [PATCH 1298/1868] drm/amdkcl: modify the makefile for dml It's caused by v6.9-9706-g6cbd1d6d36c5 arch: add ARCH_HAS_KERNEL_FPU_SUPPORT`` Signed-off-by: Asher Song --- .../gpu/drm/amd/display/amdgpu_dm/dc_fpu.c | 35 +++++++++++++++++ drivers/gpu/drm/amd/display/dc/dml/Makefile | 38 ++++++++++++++++++- drivers/gpu/drm/amd/display/dc/dml2/Makefile | 38 +++++++++++++++++++ 3 files changed, 110 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c index e46f8ce41d871..dab8eb705cafa 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c @@ -26,7 +26,20 @@ #include "dc_trace.h" +#ifdef CONFIG_ARCH_HAS_KERNEL_FPU_SUPPORT #include +#else +#if defined(CONFIG_X86) +#include +#elif defined(CONFIG_PPC64) +#include +#include +#elif defined(CONFIG_ARM64) +#include +#elif defined(CONFIG_LOONGARCH) +#include +#endif +#endif /** * DOC: DC FPU manipulation overview @@ -79,8 +92,19 @@ void dc_fpu_begin(const char *function_name, const int line) preempt_disable(); depth = __this_cpu_inc_return(fpu_recursion_depth); if (depth == 1) { +#ifdef CONFIG_ARCH_HAS_KERNEL_FPU_SUPPORT BUG_ON(!kernel_fpu_available()); kernel_fpu_begin(); +#else +#if defined(CONFIG_X86) || defined(CONFIG_LOONGARCH) + kernel_fpu_begin(); +#elif defined(CONFIG_PPC64) + if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) + enable_kernel_fp(); +#elif defined(CONFIG_ARM64) + kernel_neon_begin(); +#endif +#endif } TRACE_DCN_FPU(true, function_name, line, depth); @@ -102,7 +126,18 @@ void dc_fpu_end(const char *function_name, const int line) depth = __this_cpu_dec_return(fpu_recursion_depth); if (depth == 0) { +#ifdef CONFIG_ARCH_HAS_KERNEL_FPU_SUPPORT + kernel_fpu_end(); +#else +#if defined(CONFIG_X86) || defined(CONFIG_LOONGARCH) kernel_fpu_end(); +#elif defined(CONFIG_PPC64) + if (!cpu_has_feature(CPU_FTR_FPU_UNAVAILABLE)) + disable_kernel_fp(); +#elif defined(CONFIG_ARM64) + kernel_neon_end(); +#endif +#endif } else { WARN_ON_ONCE(depth < 0); } diff --git a/drivers/gpu/drm/amd/display/dc/dml/Makefile b/drivers/gpu/drm/amd/display/dc/dml/Makefile index 9182c5f1fc98d..6ff29ecf047ef 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dml/Makefile @@ -24,12 +24,48 @@ # Makefile for the 'utils' sub-component of DAL. # It provides the general basic services required by other DAL # subcomponents. - +# +ifdef CONFIG_ARCH_HAS_KERNEL_FPU_SUPPORT dml_ccflags := $(CC_FLAGS_FPU) dml_rcflags := $(CC_FLAGS_NO_FPU) +else +ifdef CONFIG_X86 +dml_ccflags-$(CONFIG_CC_IS_GCC) := -mhard-float +dml_ccflags := $(dml_ccflags-y) -msse +endif + +ifdef CONFIG_PPC64 +dml_ccflags := -mhard-float -maltivec +endif + +ifdef CONFIG_ARM64 +dml_rcflags := -mgeneral-regs-only +endif + +ifdef CONFIG_LOONGARCH +dml_ccflags := -mfpu=64 +dml_rcflags := -msoft-float +endif include $(src)/../dkms/Makefile.compiler +ifneq ($(call gcc-min-version, 70100),y) +IS_OLD_GCC = 1 +endif + +ifdef CONFIG_X86 +ifdef IS_OLD_GCC +# Stack alignment mismatch, proceed with caution. +# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3 +# (8B stack alignment). +dml_ccflags += -mpreferred-stack-boundary=4 +else +dml_ccflags += -msse2 +endif +endif + +endif #CONFIG_ARCH_HAS_KERNEL_FPU_SUPPORT + ifneq ($(CONFIG_FRAME_WARN),0) ifeq ($(filter y,$(CONFIG_KASAN)$(CONFIG_KCSAN)),y) frame_warn_flag := -Wframe-larger-than=3072 diff --git a/drivers/gpu/drm/amd/display/dc/dml2/Makefile b/drivers/gpu/drm/amd/display/dc/dml2/Makefile index cf979ab172bdc..2817d92a402ae 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dml2/Makefile @@ -24,8 +24,46 @@ # # Makefile for dml2. +ifdef CONFIG_ARCH_HAS_KERNEL_FPU_SUPPORT dml2_ccflags := $(CC_FLAGS_FPU) dml2_rcflags := $(CC_FLAGS_NO_FPU) +else +ifdef CONFIG_X86 +dml2_ccflags-$(CONFIG_CC_IS_GCC) := -mhard-float +dml2_ccflags := $(dml2_ccflags-y) -msse +endif + +ifdef CONFIG_PPC64 +dml2_ccflags := -mhard-float -maltivec +endif + +ifdef CONFIG_ARM64 +dml2_rcflags := -mgeneral-regs-only +endif + +ifdef CONFIG_LOONGARCH +dml2_ccflags := -mfpu=64 +dml2_rcflags := -msoft-float +endif + +ifdef CONFIG_CC_IS_GCC +ifeq ($(call cc-ifversion, -lt, 0701, y), y) +IS_OLD_GCC = 1 +endif +endif + +ifdef CONFIG_X86 +ifdef IS_OLD_GCC +# Stack alignment mismatch, proceed with caution. +# GCC < 7.1 cannot compile code using `double` and -mpreferred-stack-boundary=3 +# (8B stack alignment). +dml2_ccflags += -mpreferred-stack-boundary=4 +else +dml2_ccflags += -msse2 +endif +endif + +endif #CONFIG_ARCH_HAS_KERNEL_FPU_SUPPORT ifneq ($(CONFIG_FRAME_WARN),0) ifeq ($(filter y,$(CONFIG_KASAN)$(CONFIG_KCSAN)),y) From cd7bb54a1c00d4e5cce83cbc225cc4a4ad6d0107 Mon Sep 17 00:00:00 2001 From: Leslie Shi Date: Wed, 19 Jan 2022 11:10:38 +0800 Subject: [PATCH 1299/1868] drm/amdkcl: include correct header when macro HAVE_ASM_FPU_API_H isn't defined Signed-off-by: Leslie Shi --- drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c b/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c index dab8eb705cafa..35066ae9acbce 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/dc_fpu.c @@ -30,7 +30,11 @@ #include #else #if defined(CONFIG_X86) +#if defined(HAVE_ASM_FPU_API_H) #include +#else +#include +#endif #elif defined(CONFIG_PPC64) #include #include From 4450ad73f56548563dd49d81d06cb3dafaf880e7 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 23 Aug 2024 17:02:07 +0800 Subject: [PATCH 1300/1868] drm/amdkcl: check PCI_IRQ_INTX whether exist It's caused by v6.7-rc1-1-g58ff9c5acb4a PCI: Rename PCI_IRQ_LEGACY to PCI_IRQ_INTX v6.9-rc1-32-g0e1fdd222f0 PCI: Remove PCI_IRQ_LEGACY Signed-off-by: Asher Song --- include/kcl/kcl_pci.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/kcl/kcl_pci.h b/include/kcl/kcl_pci.h index d9ea67cc3dee3..11dd0f05f5879 100644 --- a/include/kcl/kcl_pci.h +++ b/include/kcl/kcl_pci.h @@ -222,4 +222,10 @@ static inline struct pci_dev *pci_get_base_class(unsigned int class, { return NULL; } #endif /*CONFIG_PCI*/ #endif /*HAVE_PCI_GET_BASE_CLASS*/ + +/* Copied from include/linux/pci.h */ +#ifndef PCI_IRQ_INTX +#define PCI_IRQ_INTX PCI_IRQ_LEGACY +#endif + #endif /* AMDKCL_PCI_H */ From c42962c1ee7ddc6675e5de3390ebb9387fe466ff Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 18 Dec 2023 13:54:33 +0800 Subject: [PATCH 1301/1868] drm/amdkcl: test whether struct drm_color_ctm_3x4 is available It's caused by 2d4457c2d03ed0e2fcf4206a10c0bdfcab4fd03f "drm/amd/display: Add 3x4 CTM support for plane CTM" Signed-off-by: Bob Zhou Reviewed-by: Leslie Shi --- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../amd/dkms/m4/struct_drm_color_ctm_3x4.m4 | 20 +++++++++++++++++++ include/uapi/drm/amdgpu_drm.h | 2 ++ 3 files changed, 23 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/struct_drm_color_ctm_3x4.m4 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 29a4be897df1e..28f6cecf64724 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -224,6 +224,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_RADIX_TREE_ITER_DELETE AC_AMDGPU_KFIFO_PUT AC_AMDGPU_DRM_CLIENT_REGISTER + AC_AMDGPU_DRM_COLOR_CTM_3X4 AC_AMDGPU_DRM_DRIVER_GEM_PRIME_MMAP AC_AMDGPU_DRM_GEM_PRIME_HANDLE_TO_FD AC_AMDGPU_DMA_FENCE_TIMESTAMP diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_color_ctm_3x4.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_color_ctm_3x4.m4 new file mode 100644 index 0000000000000..cef143831f813 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_color_ctm_3x4.m4 @@ -0,0 +1,20 @@ +dnl # +dnl # v6.5-2548-g2d4457c2d03e +dnl # drm/amd/display: Add 3x4 CTM support for plane CTM +dnl # +AC_DEFUN([AC_AMDGPU_DRM_COLOR_CTM_3X4], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_color_ctm_3x4 *ctm = NULL; + ctm->matrix[0] = 0; + ],[ + AC_DEFINE(HAVE_DRM_COLOR_CTM_3X4, 1, + [struct drm_color_ctm_3x4 is available]) + ]) + ]) +]) + + + diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index 8376066a24e4b..03284eab9127a 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -1370,6 +1370,7 @@ struct drm_amdgpu_info_gpuvm_fault { #define AMDGPU_FAMILY_GC_11_5_0 150 /* GC 11.5.0 */ #define AMDGPU_FAMILY_GC_12_0_0 152 /* GC 12.0.0 */ +#ifndef HAVE_DRM_COLOR_CTM_3X4 /* FIXME wrong namespace! */ struct drm_color_ctm_3x4 { /* @@ -1378,6 +1379,7 @@ struct drm_color_ctm_3x4 { */ __u64 matrix[12]; }; +#endif /** * Definition of System Unified Address (SUA) apertures From 11d2faacb515afca6e2b0bc625d7c9889e3e9bb4 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 27 Aug 2024 09:35:42 +0800 Subject: [PATCH 1302/1868] drm/amdkcl: check drm_dp_add_payload_part2 whether requires three argunments It's caused by v6.9-rc6-1554-g8a0a7b98d4b6 drm/mst: Fix NULL pointer dereference at drm_dp_add_payload_part2 commit v5.19-rc6-1771-g4d07b0bc4034 drm/display/dp_mst: Move all payload info into the atomic state Signed-off-by: Asher Song --- .../amd/dkms/m4/drm-dp-mst-topology-state.m4 | 20 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../backport/kcl_drm_dp_mst_helper_backport.h | 13 ++++++++++++ 3 files changed, 34 insertions(+) diff --git a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 index 424778ea6606b..d5928adc09844 100644 --- a/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/drm-dp-mst-topology-state.m4 @@ -67,3 +67,23 @@ AC_DEFUN([AC_AMDGPU_DRM_DP_MST_TOPOLOGY_STATE_PBN_DIV], [ ]) ]) +dnl # +dnl # commit v6.9-rc6-1554-g8a0a7b98d4b6 +dnl # drm/mst: Fix NULL pointer dereference at drm_dp_add_payload_part2 +dnl # +dnl # commit v5.19-rc6-1771-g4d07b0bc4034 +dnl # drm/display/dp_mst: Move all payload info into the atomic state +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_ADD_PAYLOAD_PART2_THREE_ARGUMENTS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ], [ + int a = 0; + a = drm_dp_add_payload_part2(NULL, NULL, NULL); + ], [ + AC_DEFINE(HAVE_DRM_DP_ADD_PAYLOAD_PART2_THREE_ARGUMENTS, 1, + [drm_dp_add_payload_part2 has three arguments]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 28f6cecf64724..81f4e9e2015aa 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -239,6 +239,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_SMCA_UMC_V2 AC_AMDGPU_TOPOLOGY_NUM_CORES_PER_PACKAGE AC_AMDGPU_DRM_CRTC_VBLANK_CRTC + AC_AMDGPU_DRM_DP_ADD_PAYLOAD_PART2_THREE_ARGUMENTS AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h index 9791910ed58b0..a84cd2ac22cc2 100644 --- a/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h +++ b/include/kcl/backport/kcl_drm_dp_mst_helper_backport.h @@ -104,4 +104,17 @@ _kcl_drm_dp_mst_topology_mgr_resume(struct drm_dp_mst_topology_mgr *mgr, #define drm_dp_mst_topology_mgr_resume _kcl_drm_dp_mst_topology_mgr_resume #endif +#ifdef HAVE_DRM_DP_ADD_PAYLOAD_PART2_THREE_ARGUMENTS +static inline int +_kcl_drm_dp_add_payload_part2(struct drm_dp_mst_topology_mgr *mgr, + struct drm_dp_mst_atomic_payload *payload) +{ + struct drm_dp_mst_topology_state *mst_state; + + mst_state = to_drm_dp_mst_topology_state(mgr->base.state); + return drm_dp_add_payload_part2(mgr, mst_state->base.state, payload); +} +#define drm_dp_add_payload_part2 _kcl_drm_dp_add_payload_part2 +#endif + #endif From e90f09b30da636ca7c38bbf54d2d31130856e2d4 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 19 Jan 2024 10:02:14 +0800 Subject: [PATCH 1303/1868] drm/amdgpu: Fix possible null pointer dereference mem = bo->tbo.resource may be NULL in amdgpu_vm_bo_update. Fixes: 180253782038 ("drm/ttm: stop allocating dummy resources during BO creation") Signed-off-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index e4721b2a17b2e..f55e7dd8e6c21 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -1215,7 +1215,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va, if (mem && (mem->mem_type == TTM_PL_TT || mem->mem_type == AMDGPU_PL_PREEMPT)) pages_addr = bo->tbo.ttm->dma_address; - else if (mem->mem_type == AMDGPU_PL_DGMA_IMPORT) + else if (mem && mem->mem_type == AMDGPU_PL_DGMA_IMPORT) pages_addr = (dma_addr_t *)bo->dgma_addr; } From d2f522ee8a409abfb4dbcf220f294114ae6298a6 Mon Sep 17 00:00:00 2001 From: Hawking Zhang Date: Tue, 28 May 2024 13:52:46 +0800 Subject: [PATCH 1304/1868] drm/amdgpu: Estimate RAS reservation when report capacity v2 Add estimate of how much vram we need to reserve for RAS when caculating the total available vram. v2: apply the change to MP0 v13_0_2 and v13_0_14 Signed-off-by: Hawking Zhang Reviewed-by: Tao Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index fcf151545c2b4..15829496a87fe 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -223,7 +223,8 @@ int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device *adev, (kfd_mem_limit.ttm_mem_used + ttm_mem_needed > kfd_mem_limit.max_ttm_mem_limit) || (adev && xcp_id >= 0 && adev->kfd.vram_used[xcp_id] + vram_needed > - vram_size - reserved_for_pt - reserved_for_ras - atomic64_read(&adev->vram_pin_size))) { + vram_size - reserved_for_pt - reserved_for_ras - atomic64_read(&adev->vram_pin_size) + + atomic64_read(&adev->kfd.vram_pinned))) { ret = -ENOMEM; goto release; } From 843786f848aec8cfbe1c38d1f93e95fb4c6d53fe Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 27 Aug 2024 11:55:40 +0800 Subject: [PATCH 1305/1868] drm/amdkcl: udpate config.h Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/config/config.h | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index e07aadfec8e58..21af886e58b0c 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -185,6 +185,9 @@ /* drm_client_register() is available */ #define HAVE_DRM_CLIENT_REGISTER 1 +/* struct drm_color_ctm_3x4 is available */ +/* #undef HAVE_DRM_COLOR_CTM_3X4 */ + /* drm_connector_atomic_hdr_metadata_equal() is available */ #define HAVE_DRM_CONNECTOR_ATOMIC_HDR_METADATA_EQUAL 1 @@ -289,6 +292,9 @@ /* struct drm_display_info has monitor_range member */ #define HAVE_DRM_DISPLAY_INFO_MONITOR_RANGE 1 +/* drm_dp_add_payload_part2 has three arguments */ +/* #undef HAVE_DRM_DP_ADD_PAYLOAD_PART2_THREE_ARGUMENTS */ + /* drm_dp_atomic_find_time_slots() is available */ #define HAVE_DRM_DP_ATOMIC_FIND_TIME_SLOTS 1 @@ -438,7 +444,10 @@ #define HAVE_DRM_DRM_EXEC_H 1 /* Define to 1 if you have the header file. */ -#define HAVE_DRM_DRM_FBDEV_GENERIC_H 1 +/* #undef HAVE_DRM_DRM_FBDEV_GENERIC_H */ + +/* Define to 1 if you have the header file. */ +#define HAVE_DRM_DRM_FBDEV_TTM_H 1 /* Define to 1 if you have the header file. */ #define HAVE_DRM_DRM_GEM_ATOMIC_HELPER_H 1 From ef4528eb41fd1fd689a160cea2f3deebdf762574 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Tue, 27 Aug 2024 11:57:10 +0800 Subject: [PATCH 1306/1868] Bump AMDGPU version to 6.10.0 Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/configure.ac | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/configure.ac b/drivers/gpu/drm/amd/dkms/configure.ac index e49b5ff073bd2..e4dddf1c64de5 100644 --- a/drivers/gpu/drm/amd/dkms/configure.ac +++ b/drivers/gpu/drm/amd/dkms/configure.ac @@ -1,4 +1,4 @@ -AC_INIT(amdgpu-dkms, 6.9.0) +AC_INIT(amdgpu-dkms, 6.10.0) AC_LANG(C) AC_CONFIG_AUX_DIR([config]) From e14d6d86929f79347f0e9a831170d7a1e2b9eb86 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 28 Aug 2024 14:15:33 +0800 Subject: [PATCH 1307/1868] drm/amdkcl: test follow_pfn() is available It's caused by cb10c28ac82c9b7a5e9b3b1dc7157036c20c36dd "mm: remove follow_pfn" Signed-off-by: Bob Zhou Signed-off-by: Asher Song --- drivers/gpu/drm/amd/backport/Makefile | 2 +- drivers/gpu/drm/amd/backport/kcl_memory.c | 20 ++++++++++++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/follow_pfn.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_mm.h | 6 ++++++ 6 files changed, 47 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/backport/kcl_memory.c create mode 100644 drivers/gpu/drm/amd/dkms/m4/follow_pfn.m4 diff --git a/drivers/gpu/drm/amd/backport/Makefile b/drivers/gpu/drm/amd/backport/Makefile index 8bc3adedebc57..2d01094326e2c 100644 --- a/drivers/gpu/drm/amd/backport/Makefile +++ b/drivers/gpu/drm/amd/backport/Makefile @@ -1,6 +1,6 @@ # SPDX-License-Identifier: MIT BACKPORT_OBJS := kcl_drm_drv.o kcl_drm_gem_ttm_helper.o \ - kcl_drm_gem.o kcl_drm_file.o + kcl_drm_gem.o kcl_drm_file.o kcl_memory.o amdgpu-y += $(addprefix ../backport/,$(BACKPORT_OBJS)) diff --git a/drivers/gpu/drm/amd/backport/kcl_memory.c b/drivers/gpu/drm/amd/backport/kcl_memory.c new file mode 100644 index 0000000000000..153710b6883de --- /dev/null +++ b/drivers/gpu/drm/amd/backport/kcl_memory.c @@ -0,0 +1,20 @@ +#include + +#ifndef HAVE_FOLLOW_PFN +int _kcl_follow_pfn(struct vm_area_struct *vma, unsigned long address, + unsigned long *pfn) +{ + int ret = -EINVAL; + spinlock_t *ptl; + pte_t *ptep; + + ret = follow_pte(vma, address, &ptep, &ptl); + if (ret) + return ret; + *pfn = pte_pfn(ptep_get(ptep)); + pte_unmap_unlock(ptep, ptl); + return 0; +} + +EXPORT_SYMBOL(_kcl_follow_pfn); +#endif diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 21af886e58b0c..5257c02ec1eed 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -596,6 +596,9 @@ /* drm_show_fdinfo() is available */ #define HAVE_DRM_SHOW_FDINFO 1 +/* follow_pfn() is available */ +/* #undef HAVE_FOLLOW_PFN */ + /* drm_simple_encoder is available */ #define HAVE_DRM_SIMPLE_ENCODER_INIT 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/follow_pfn.m4 b/drivers/gpu/drm/amd/dkms/m4/follow_pfn.m4 new file mode 100644 index 0000000000000..ea2c47c00ab90 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/follow_pfn.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # v6.9-rc4-152-gcb10c28ac82c +dnl # mm: remove follow_pfn +dnl # +AC_DEFUN([AC_AMDGPU_FOLLOW_PFN], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + follow_pfn(NULL, 0, NULL); + ],[follow_pfn], [mm/memory.c],[ + AC_DEFINE(HAVE_FOLLOW_PFN, 1, + [follow_pfn() is available]) + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 81f4e9e2015aa..797f6573f1de8 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -213,6 +213,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_VM_FLAGS_SET AC_AMDGPU_MMAP_ASSERT_WRITE_LOCKED AC_AMDGPU_PID_TYPE + AC_AMDGPU_FOLLOW_PFN AC_AMDGPU_LIST_CMP_FUNC_IS_CONST_PARAM AC_AMDGPU_DMA_FENCE_OPS_SET_DEADLINE AC_AMDGPU_DRM_SHOW_FDINFO diff --git a/include/kcl/kcl_mm.h b/include/kcl/kcl_mm.h index 646ba0d687544..b502b239610ef 100644 --- a/include/kcl/kcl_mm.h +++ b/include/kcl/kcl_mm.h @@ -166,4 +166,10 @@ static inline bool vma_is_initial_stack(const struct vm_area_struct *vma) } #endif +#ifndef HAVE_FOLLOW_PFN +int _kcl_follow_pfn(struct vm_area_struct *vma, unsigned long address, + unsigned long *pfn); +#define follow_pfn _kcl_follow_pfn +#endif + #endif /* AMDKCL_MM_H */ From 0b8909984ba7d0ead3e21e56fb9cc4b9825f506b Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Wed, 28 Aug 2024 16:42:05 +0800 Subject: [PATCH 1308/1868] drm/amdkcl: test whether __assign_str() wants 1 arguments It's caused by 2c92ca849fcc6ee7d0c358e9959abc9f58661aea "tracing/treewide: Remove second parameter of __assign_str()" Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h | 14 +++++++------- drivers/gpu/drm/amd/amdkcl/kcl_fence_trace.h | 6 +++--- drivers/gpu/drm/amd/amdkfd/kfd_trace.h | 6 +++--- drivers/gpu/drm/amd/backport/backport.h | 1 + .../drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h | 2 +- drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/assign_str.m4 | 17 +++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + drivers/gpu/drm/scheduler/backport/backport.h | 1 + drivers/gpu/drm/scheduler/gpu_scheduler_trace.h | 4 ++-- include/kcl/kcl_tracepoint.h | 13 +++++++++++++ 11 files changed, 52 insertions(+), 16 deletions(-) create mode 100644 drivers/gpu/drm/amd/dkms/m4/assign_str.m4 create mode 100644 include/kcl/kcl_tracepoint.h diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h index 471c3ab919f1b..5a52e45f3ba50 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h @@ -178,10 +178,10 @@ TRACE_EVENT(amdgpu_cs_ioctl, TP_fast_assign( __entry->sched_job_id = job->base.id; - __assign_str(timeline); + __amdkcl_assign_str(timeline, AMDGPU_JOB_GET_TIMELINE_NAME(job)); __entry->context = job->base.s_fence->finished.context; __entry->seqno = job->base.s_fence->finished.seqno; - __assign_str(ring); + __amdkcl_assign_str(ring, to_amdgpu_ring(job->base.sched)->name); __entry->num_ibs = job->num_ibs; ), TP_printk("sched_job=%llu, timeline=%s, context=%u, seqno=%u, ring_name=%s, num_ibs=%u", @@ -203,10 +203,10 @@ TRACE_EVENT(amdgpu_sched_run_job, TP_fast_assign( __entry->sched_job_id = job->base.id; - __assign_str(timeline); + __amdkcl_assign_str(timeline, AMDGPU_JOB_GET_TIMELINE_NAME(job)); __entry->context = job->base.s_fence->finished.context; __entry->seqno = job->base.s_fence->finished.seqno; - __assign_str(ring); + __amdkcl_assign_str(ring, to_amdgpu_ring(job->base.sched)->name); __entry->num_ibs = job->num_ibs; ), TP_printk("sched_job=%llu, timeline=%s, context=%u, seqno=%u, ring_name=%s, num_ibs=%u", @@ -231,7 +231,7 @@ TRACE_EVENT(amdgpu_vm_grab_id, TP_fast_assign( __entry->pasid = vm->pasid; - __assign_str(ring); + __amdkcl_assign_str(ring, ring->name); __entry->vmid = job->vmid; __entry->vm_hub = ring->vm_hub, __entry->pd_addr = job->vm_pd_addr; @@ -425,7 +425,7 @@ TRACE_EVENT(amdgpu_vm_flush, ), TP_fast_assign( - __assign_str(ring); + __amdkcl_assign_str(ring, ring->name); __entry->vmid = vmid; __entry->vm_hub = ring->vm_hub; __entry->pd_addr = pd_addr; @@ -526,7 +526,7 @@ TRACE_EVENT(amdgpu_ib_pipe_sync, ), TP_fast_assign( - __assign_str(ring); + __amdkcl_assign_str(ring, sched_job->base.sched->name); __entry->id = sched_job->base.id; __entry->fence = fence; __entry->ctx = fence->context; diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fence_trace.h b/drivers/gpu/drm/amd/amdkcl/kcl_fence_trace.h index 7c857ba3c31c0..5a74e165c087f 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_fence_trace.h +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fence_trace.h @@ -3,7 +3,7 @@ #if !defined(_TRACE_KCL_FENCE_H) || defined(TRACE_HEADER_MULTI_READ) #define _TRACE_KCL_FENCE_H -#include +#include #undef TRACE_SYSTEM #define TRACE_SYSTEM kcl_fence @@ -25,8 +25,8 @@ DECLARE_EVENT_CLASS(kcl_fence, ), TP_fast_assign( - __assign_str(driver, fence->ops->get_driver_name(fence)) - __assign_str(timeline, fence->ops->get_timeline_name(fence)) + __amdkcl_assign_str(driver, fence->ops->get_driver_name(fence)); + __amdkcl_assign_str(timeline, fence->ops->get_timeline_name(fence)); __entry->context = fence->context; __entry->seqno = fence->seqno; ), diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_trace.h b/drivers/gpu/drm/amd/amdkfd/kfd_trace.h index 5d27a98055377..16470bec1c317 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_trace.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_trace.h @@ -61,7 +61,7 @@ TRACE_EVENT(kfd_map_memory_to_gpu_end, TP_fast_assign( __entry->pasid = p->pasid; __entry->array_size = array_size; - __assign_str(pStatusMsg, pStatusMsg); + __amdkcl_assign_str(pStatusMsg, pStatusMsg); ), TP_printk("pasid = %u, array_size = %u, StatusMsg=%s", __entry->pasid, @@ -109,7 +109,7 @@ TRACE_EVENT(kfd_evict_process_worker_end, ), TP_fast_assign( __entry->pasid = p->pasid; - __assign_str(pStatusMsg, pStatusMsg); + __amdkcl_assign_str(pStatusMsg, pStatusMsg); ), TP_printk("pasid=%u, StatusMsg=%s", __entry->pasid, __get_str(pStatusMsg)) @@ -137,7 +137,7 @@ TRACE_EVENT(kfd_restore_process_worker_end, ), TP_fast_assign( entry->pasid = p->pasid; - __assign_str(pStatusMsg, pStatusMsg); + __amdkcl_assign_str(pStatusMsg, pStatusMsg); ), TP_printk("pasid=%u, StatusMsg=%s", __entry->pasid, __get_str(pStatusMsg)) diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 7ce2f26657bf8..6ec330de9f4dd 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -128,4 +128,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h index e487f8c68f97a..0f969a7eb5aa5 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_trace.h @@ -88,7 +88,7 @@ TRACE_EVENT(amdgpu_dc_performance, __entry->writes = write_count; __entry->read_delta = read_count - *last_read; __entry->write_delta = write_count - *last_write; - __assign_str(func); + __amdkcl_assign_str(func, func); __entry->line = line; *last_read = read_count; *last_write = write_count; diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 5257c02ec1eed..e1ac8fe9c7a1e 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -596,6 +596,9 @@ /* drm_show_fdinfo() is available */ #define HAVE_DRM_SHOW_FDINFO 1 +/* __assign_str() wants 1 arguments */ +#define HAVE_ASSIGN_STR_ONE_ARGUMENT 1 + /* follow_pfn() is available */ /* #undef HAVE_FOLLOW_PFN */ diff --git a/drivers/gpu/drm/amd/dkms/m4/assign_str.m4 b/drivers/gpu/drm/amd/dkms/m4/assign_str.m4 new file mode 100644 index 0000000000000..477d281b98373 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/assign_str.m4 @@ -0,0 +1,17 @@ +dnl # +dnl # v6.9-11925-g2c92ca849fcc +dnl # tracing/treewide: Remove second parameter of __assign_str() +dnl # Due to trace system bases on runtime, so use script to handle specially +dnl # +AC_DEFUN([AC_AMDGPU_ASSIGN_STR], [ + AC_KERNEL_DO_BACKGROUND([ + header_file=stage6_event_callback.h + header_file_src=$LINUX/include/trace/stages/$header_file + AS_IF([test -f "$header_file_src"], [ + AS_IF([grep -q '^#define __assign_str(dst)' $header_file_src], [ + AC_DEFINE(HAVE_ASSIGN_STR_ONE_ARGUMENT, 1, + [__assign_str() wants 1 arguments]) + ]) + ]) + ]) +]) \ No newline at end of file diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 797f6573f1de8..1ac442785ee3f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -241,6 +241,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_TOPOLOGY_NUM_CORES_PER_PACKAGE AC_AMDGPU_DRM_CRTC_VBLANK_CRTC AC_AMDGPU_DRM_DP_ADD_PAYLOAD_PART2_THREE_ARGUMENTS + AC_AMDGPU_ASSIGN_STR AC_KERNEL_WAIT AS_IF([test "$LINUX_OBJ" != "$LINUX"], [ diff --git a/drivers/gpu/drm/scheduler/backport/backport.h b/drivers/gpu/drm/scheduler/backport/backport.h index 04ad51ff373e2..ead9183b08d56 100644 --- a/drivers/gpu/drm/scheduler/backport/backport.h +++ b/drivers/gpu/drm/scheduler/backport/backport.h @@ -10,4 +10,5 @@ #include #include #include +#include #endif diff --git a/drivers/gpu/drm/scheduler/gpu_scheduler_trace.h b/drivers/gpu/drm/scheduler/gpu_scheduler_trace.h index f512527364351..087b47fb976b1 100644 --- a/drivers/gpu/drm/scheduler/gpu_scheduler_trace.h +++ b/drivers/gpu/drm/scheduler/gpu_scheduler_trace.h @@ -48,7 +48,7 @@ DECLARE_EVENT_CLASS(drm_sched_job, __entry->entity = entity; __entry->id = sched_job->id; __entry->fence = &sched_job->s_fence->finished; - __assign_str(name); + __amdkcl_assign_str(name, sched_job->sched->name); __entry->job_count = spsc_queue_count(&entity->job_queue); __entry->hw_job_count = atomic_read( &sched_job->sched->credit_count); @@ -94,7 +94,7 @@ TRACE_EVENT(drm_sched_job_wait_dep, ), TP_fast_assign( - __assign_str(name); + __amdkcl_assign_str(name, sched_job->sched->name); __entry->id = sched_job->id; __entry->fence = fence; __entry->ctx = fence->context; diff --git a/include/kcl/kcl_tracepoint.h b/include/kcl/kcl_tracepoint.h new file mode 100644 index 0000000000000..10eafc91c9486 --- /dev/null +++ b/include/kcl/kcl_tracepoint.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _KCL_TRACEPOINT_H_ +#define _KCL_TRACEPOINT_H_ + +#include + +#ifdef HAVE_ASSIGN_STR_ONE_ARGUMENT +#define __amdkcl_assign_str(dst, src) __assign_str(dst) +#else +#define __amdkcl_assign_str(dst, src) __assign_str(dst, src) +#endif + +#endif From 97227fef1871903a8e6f72e84b4bbe7384c0fe86 Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Tue, 23 Jul 2024 13:08:55 +0530 Subject: [PATCH 1309/1868] drm/amdgpu: add vcn ip dump ptr in vcn global struct Add pointer to the vcn ip dump in the vcn global structure to be accessible for all vcn version via global adev. Signed-off-by: Sunil Khatri Acked-by: Leo Liu --- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h index c87d68d4be536..2a1f3dbb14d3f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h @@ -330,6 +330,9 @@ struct amdgpu_vcn { uint16_t inst_mask; uint8_t num_inst_per_aid; bool using_unified_queue; + + /* IP reg dump */ + uint32_t *ip_dump; }; struct amdgpu_fw_shared_rb_ptrs_struct { From 1c638ef4324bcffe032ff2ed38b845437d572752 Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Wed, 24 Jul 2024 16:35:41 +0530 Subject: [PATCH 1310/1868] drm/amdgpu: add vcn_v3_0 ip dump support Add support of vcn ip dump in the devcoredump for vcn_v3_0. Signed-off-by: Sunil Khatri Acked-by: Leo Liu --- drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 78 ++++++++++++++++++++++++++- 1 file changed, 77 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c index 24f947751c463..693eb676c01de 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c @@ -60,6 +60,42 @@ #define RDECODE_MSG_CREATE 0x00000000 #define RDECODE_MESSAGE_CREATE 0x00000001 +static const struct amdgpu_hwip_reg_entry vcn_reg_list_3_0[] = { + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_POWER_STATUS), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_STATUS), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID2), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA0), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA1), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_CMD), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI2), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO2), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI3), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO3), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI4), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO4), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR2), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR2), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR3), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR3), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR4), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR4), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE2), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE3), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE4), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_CONFIG), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_STATUS), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_CTL), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_DATA), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_MASK), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_PAUSE) +}; + static int amdgpu_ih_clientid_vcns[] = { SOC15_IH_CLIENTID_VCN, SOC15_IH_CLIENTID_VCN1 @@ -126,6 +162,8 @@ static int vcn_v3_0_sw_init(void *handle) struct amdgpu_ring *ring; int i, j, r; int vcn_doorbell_index = 0; + uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_3_0); + uint32_t *ptr; struct amdgpu_device *adev = (struct amdgpu_device *)handle; r = amdgpu_vcn_sw_init(adev); @@ -246,6 +284,15 @@ static int vcn_v3_0_sw_init(void *handle) if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) adev->vcn.pause_dpg_mode = vcn_v3_0_pause_dpg_mode; + /* Allocate memory for VCN IP Dump buffer */ + ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL); + if (ptr == NULL) { + DRM_ERROR("Failed to allocate memory for VCN IP Dump\n"); + adev->vcn.ip_dump = NULL; + } else { + adev->vcn.ip_dump = ptr; + } + return 0; } @@ -284,6 +331,7 @@ static int vcn_v3_0_sw_fini(void *handle) r = amdgpu_vcn_sw_fini(adev); + kfree(adev->vcn.ip_dump); return r; } @@ -2203,6 +2251,34 @@ static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev) } } +static void vcn_v3_0_dump_ip_state(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + int i, j; + bool is_powered; + uint32_t inst_off; + uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_3_0); + + if (!adev->vcn.ip_dump) + return; + + for (i = 0; i < adev->vcn.num_vcn_inst; i++) { + if (adev->vcn.harvest_config & (1 << i)) + continue; + + inst_off = i * reg_count; + /* mmUVD_POWER_STATUS is always readable and is first element of the array */ + adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, mmUVD_POWER_STATUS); + is_powered = (adev->vcn.ip_dump[inst_off] & + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; + + if (is_powered) + for (j = 1; j < reg_count; j++) + adev->vcn.ip_dump[inst_off + j] = + RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_3_0[j], i)); + } +} + static const struct amd_ip_funcs vcn_v3_0_ip_funcs = { .name = "vcn_v3_0", .early_init = vcn_v3_0_early_init, @@ -2221,7 +2297,7 @@ static const struct amd_ip_funcs vcn_v3_0_ip_funcs = { .post_soft_reset = NULL, .set_clockgating_state = vcn_v3_0_set_clockgating_state, .set_powergating_state = vcn_v3_0_set_powergating_state, - .dump_ip_state = NULL, + .dump_ip_state = vcn_v3_0_dump_ip_state, .print_ip_state = NULL, }; From 3e74307ec2e816895fed72d450d2e295d1184c98 Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Wed, 24 Jul 2024 16:48:28 +0530 Subject: [PATCH 1311/1868] drm/amdgpu: add print support for vcn_v3_0 ip dump Add support for logging the registers in devcoredump buffer for vcn_v3_0. Signed-off-by: Sunil Khatri Acked-by: Leo Liu --- drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 35 ++++++++++++++++++++++++++- 1 file changed, 34 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c index 693eb676c01de..65dd68b322806 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c @@ -2251,6 +2251,39 @@ static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev) } } +static void vcn_v3_0_print_ip_state(void *handle, struct drm_printer *p) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + int i, j; + uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_3_0); + uint32_t inst_off; + bool is_powered; + + if (!adev->vcn.ip_dump) + return; + + drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst); + for (i = 0; i < adev->vcn.num_vcn_inst; i++) { + if (adev->vcn.harvest_config & (1 << i)) { + drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i); + continue; + } + + inst_off = i * reg_count; + is_powered = (adev->vcn.ip_dump[inst_off] & + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; + + if (is_powered) { + drm_printf(p, "\nActive Instance:VCN%d\n", i); + for (j = 0; j < reg_count; j++) + drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_3_0[j].reg_name, + adev->vcn.ip_dump[inst_off + j]); + } else { + drm_printf(p, "\nInactive Instance:VCN%d\n", i); + } + } +} + static void vcn_v3_0_dump_ip_state(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; @@ -2298,7 +2331,7 @@ static const struct amd_ip_funcs vcn_v3_0_ip_funcs = { .set_clockgating_state = vcn_v3_0_set_clockgating_state, .set_powergating_state = vcn_v3_0_set_powergating_state, .dump_ip_state = vcn_v3_0_dump_ip_state, - .print_ip_state = NULL, + .print_ip_state = vcn_v3_0_print_ip_state, }; const struct amdgpu_ip_block_version vcn_v3_0_ip_block = { From 662bfc822cb581dad2a5d2db34102879fdee6a8f Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Thu, 1 Aug 2024 19:17:11 +0530 Subject: [PATCH 1312/1868] drm/amdgpu: add vcn_v5_0 ip dump support Add support of vcn ip dump in the devcoredump for vcn_v5_0. Signed-off-by: Sunil Khatri Acked-by: Leo Liu --- drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 76 ++++++++++++++++++++++++- 1 file changed, 75 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c index 68c97fcd539b9..a30a42b1ba03b 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c @@ -37,6 +37,40 @@ #include +static const struct amdgpu_hwip_reg_entry vcn_reg_list_5_0[] = { + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID2), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA0), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA1), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_CMD), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI2), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO2), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI3), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO3), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI4), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO4), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR2), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR2), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR3), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR3), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR4), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR4), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE2), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_DATA), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_MASK), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_PAUSE) +}; + static int amdgpu_ih_clientid_vcns[] = { SOC15_IH_CLIENTID_VCN, SOC15_IH_CLIENTID_VCN1 @@ -83,6 +117,8 @@ static int vcn_v5_0_0_sw_init(void *handle) struct amdgpu_ring *ring; struct amdgpu_device *adev = (struct amdgpu_device *)handle; int i, r; + uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_5_0); + uint32_t *ptr; r = amdgpu_vcn_sw_init(adev); if (r) @@ -137,6 +173,14 @@ static int vcn_v5_0_0_sw_init(void *handle) if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) adev->vcn.pause_dpg_mode = vcn_v5_0_0_pause_dpg_mode; + /* Allocate memory for VCN IP Dump buffer */ + ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL); + if (!ptr) { + DRM_ERROR("Failed to allocate memory for VCN IP Dump\n"); + adev->vcn.ip_dump = NULL; + } else { + adev->vcn.ip_dump = ptr; + } return 0; } @@ -173,6 +217,8 @@ static int vcn_v5_0_0_sw_fini(void *handle) r = amdgpu_vcn_sw_fini(adev); + kfree(adev->vcn.ip_dump); + return r; } @@ -1297,6 +1343,34 @@ static void vcn_v5_0_0_set_irq_funcs(struct amdgpu_device *adev) } } +static void vcn_v5_0_dump_ip_state(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + int i, j; + bool is_powered; + uint32_t inst_off; + uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_5_0); + + if (!adev->vcn.ip_dump) + return; + + for (i = 0; i < adev->vcn.num_vcn_inst; i++) { + if (adev->vcn.harvest_config & (1 << i)) + continue; + + inst_off = i * reg_count; + /* mmUVD_POWER_STATUS is always readable and is first element of the array */ + adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, regUVD_POWER_STATUS); + is_powered = (adev->vcn.ip_dump[inst_off] & + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; + + if (is_powered) + for (j = 1; j < reg_count; j++) + adev->vcn.ip_dump[inst_off + j] = + RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_5_0[j], i)); + } +} + static const struct amd_ip_funcs vcn_v5_0_0_ip_funcs = { .name = "vcn_v5_0_0", .early_init = vcn_v5_0_0_early_init, @@ -1315,7 +1389,7 @@ static const struct amd_ip_funcs vcn_v5_0_0_ip_funcs = { .post_soft_reset = NULL, .set_clockgating_state = vcn_v5_0_0_set_clockgating_state, .set_powergating_state = vcn_v5_0_0_set_powergating_state, - .dump_ip_state = NULL, + .dump_ip_state = vcn_v5_0_dump_ip_state, .print_ip_state = NULL, }; From b764cf9930cd2fecdf800dd7ab2d6ec2e9d8c676 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 18 Jul 2024 15:50:23 -0400 Subject: [PATCH 1313/1868] drm/amdgpu/gfx8: add ring reset callback for gfx Add ring reset callback for gfx. v2: fix operator precedence (kernel test robot) Acked-by: Vitaly Prosyak Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 75 ++++++++++++++++++++++++++- drivers/gpu/drm/amd/amdgpu/vid.h | 1 + 2 files changed, 75 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 4b3a022dec87c..b3dd8a532f1b5 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -6252,6 +6252,7 @@ static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr, { bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; + bool exec = flags & AMDGPU_FENCE_FLAG_EXEC; /* Workaround for cache flush problems. First send a dummy EOP * event down the pipe with seq one below. @@ -6275,7 +6276,8 @@ static void gfx_v8_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr, EOP_TC_ACTION_EN | EOP_TC_WB_ACTION_EN | EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | - EVENT_INDEX(5))); + EVENT_INDEX(5) | + (exec ? EOP_EXEC : 0))); amdgpu_ring_write(ring, addr & 0xfffffffc); amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); @@ -6483,6 +6485,34 @@ static void gfx_v8_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, amdgpu_ring_write(ring, val); } +static void gfx_v8_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, + int mem_space, int opt, uint32_t addr0, + uint32_t addr1, uint32_t ref, uint32_t mask, + uint32_t inv) +{ + amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); + amdgpu_ring_write(ring, + /* memory (1) or register (0) */ + (WAIT_REG_MEM_MEM_SPACE(mem_space) | + WAIT_REG_MEM_OPERATION(opt) | /* wait */ + WAIT_REG_MEM_FUNCTION(3) | /* equal */ + WAIT_REG_MEM_ENGINE(eng_sel))); + + if (mem_space) + BUG_ON(addr0 & 0x3); /* Dword align */ + amdgpu_ring_write(ring, addr0); + amdgpu_ring_write(ring, addr1); + amdgpu_ring_write(ring, ref); + amdgpu_ring_write(ring, mask); + amdgpu_ring_write(ring, inv); /* poll interval */ +} + +static void gfx_v8_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, + uint32_t val, uint32_t mask) +{ + gfx_v8_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); +} + static void gfx_v8_0_ring_soft_recovery(struct amdgpu_ring *ring, unsigned vmid) { struct amdgpu_device *adev = ring->adev; @@ -6983,6 +7013,48 @@ static void gfx_v8_0_emit_wave_limit(struct amdgpu_ring *ring, bool enable) } } +static int gfx_v8_0_reset_kgq(struct amdgpu_ring *ring, unsigned int vmid) +{ + struct amdgpu_device *adev = ring->adev; + struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; + struct amdgpu_ring *kiq_ring = &kiq->ring; + unsigned long flags; + u32 tmp; + int r; + + if (amdgpu_sriov_vf(adev)) + return -EINVAL; + + if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) + return -EINVAL; + + spin_lock_irqsave(&kiq->ring_lock, flags); + + if (amdgpu_ring_alloc(kiq_ring, 5)) { + spin_unlock_irqrestore(&kiq->ring_lock, flags); + return -ENOMEM; + } + + tmp = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid); + gfx_v8_0_ring_emit_wreg(kiq_ring, mmCP_VMID_RESET, tmp); + amdgpu_ring_commit(kiq_ring); + + spin_unlock_irqrestore(&kiq->ring_lock, flags); + + r = amdgpu_ring_test_ring(kiq_ring); + if (r) + return r; + + if (amdgpu_ring_alloc(ring, 7 + 12 + 5)) + return -ENOMEM; + gfx_v8_0_ring_emit_fence_gfx(ring, ring->fence_drv.gpu_addr, + ring->fence_drv.sync_seq, AMDGPU_FENCE_FLAG_EXEC); + gfx_v8_0_ring_emit_reg_wait(ring, mmCP_VMID_RESET, 0, 0xffff); + gfx_v8_0_ring_emit_wreg(ring, mmCP_VMID_RESET, 0); + + return amdgpu_ring_test_ring(ring); +} + static const struct amd_ip_funcs gfx_v8_0_ip_funcs = { .name = "gfx_v8_0", .early_init = gfx_v8_0_early_init, @@ -7050,6 +7122,7 @@ static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_gfx = { .emit_wreg = gfx_v8_0_ring_emit_wreg, .soft_recovery = gfx_v8_0_ring_soft_recovery, .emit_mem_sync = gfx_v8_0_emit_mem_sync, + .reset = gfx_v8_0_reset_kgq, }; static const struct amdgpu_ring_funcs gfx_v8_0_ring_funcs_compute = { diff --git a/drivers/gpu/drm/amd/amdgpu/vid.h b/drivers/gpu/drm/amd/amdgpu/vid.h index 80ce42aacc0cc..b61f6b838ec2c 100644 --- a/drivers/gpu/drm/amd/amdgpu/vid.h +++ b/drivers/gpu/drm/amd/amdgpu/vid.h @@ -246,6 +246,7 @@ * 1 - Stream * 2 - Bypass */ +#define EOP_EXEC (1 << 28) /* For Trailing Fence */ #define DATA_SEL(x) ((x) << 29) /* 0 - discard * 1 - send low 32bit data From 3f80895e980b8b88c4bfe3c84844fbcf4580cfcf Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 18 Jul 2024 15:59:20 -0400 Subject: [PATCH 1314/1868] drm/amdgpu/gfx7: add ring reset callback for gfx Add ring reset callback for gfx. v2: fix operator precedence (kernel test robot) Acked-by: Vitaly Prosyak Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/cikd.h | 1 + drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 76 ++++++++++++++++++++++++++- 2 files changed, 76 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/cikd.h b/drivers/gpu/drm/amd/amdgpu/cikd.h index 55982c0064b56..06088d52d81c4 100644 --- a/drivers/gpu/drm/amd/amdgpu/cikd.h +++ b/drivers/gpu/drm/amd/amdgpu/cikd.h @@ -364,6 +364,7 @@ * 1 - Stream * 2 - Bypass */ +#define EOP_EXEC (1 << 28) /* For Trailing Fence */ #define DATA_SEL(x) ((x) << 29) /* 0 - discard * 1 - send low 32bit data diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index 5fbdef04c9aae..f146806c4633b 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -2114,6 +2114,8 @@ static void gfx_v7_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr, { bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; + bool exec = flags & AMDGPU_FENCE_FLAG_EXEC; + /* Workaround for cache flush problems. First send a dummy EOP * event down the pipe with seq one below. */ @@ -2133,7 +2135,8 @@ static void gfx_v7_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr, amdgpu_ring_write(ring, (EOP_TCL1_ACTION_EN | EOP_TC_ACTION_EN | EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | - EVENT_INDEX(5))); + EVENT_INDEX(5) | + (exec ? EOP_EXEC : 0))); amdgpu_ring_write(ring, addr & 0xfffffffc); amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xffff) | DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); @@ -4921,6 +4924,76 @@ static void gfx_v7_0_emit_mem_sync_compute(struct amdgpu_ring *ring) amdgpu_ring_write(ring, 0x0000000A); /* poll interval */ } +static void gfx_v7_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, + int mem_space, int opt, uint32_t addr0, + uint32_t addr1, uint32_t ref, uint32_t mask, + uint32_t inv) +{ + amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); + amdgpu_ring_write(ring, + /* memory (1) or register (0) */ + (WAIT_REG_MEM_MEM_SPACE(mem_space) | + WAIT_REG_MEM_OPERATION(opt) | /* wait */ + WAIT_REG_MEM_FUNCTION(3) | /* equal */ + WAIT_REG_MEM_ENGINE(eng_sel))); + + if (mem_space) + BUG_ON(addr0 & 0x3); /* Dword align */ + amdgpu_ring_write(ring, addr0); + amdgpu_ring_write(ring, addr1); + amdgpu_ring_write(ring, ref); + amdgpu_ring_write(ring, mask); + amdgpu_ring_write(ring, inv); /* poll interval */ +} + +static void gfx_v7_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, + uint32_t val, uint32_t mask) +{ + gfx_v7_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); +} + +static int gfx_v7_0_reset_kgq(struct amdgpu_ring *ring, unsigned int vmid) +{ + struct amdgpu_device *adev = ring->adev; + struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; + struct amdgpu_ring *kiq_ring = &kiq->ring; + unsigned long flags; + u32 tmp; + int r; + + if (amdgpu_sriov_vf(adev)) + return -EINVAL; + + if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) + return -EINVAL; + + spin_lock_irqsave(&kiq->ring_lock, flags); + + if (amdgpu_ring_alloc(kiq_ring, 5)) { + spin_unlock_irqrestore(&kiq->ring_lock, flags); + return -ENOMEM; + } + + tmp = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid); + gfx_v7_0_ring_emit_wreg(kiq_ring, mmCP_VMID_RESET, tmp); + amdgpu_ring_commit(kiq_ring); + + spin_unlock_irqrestore(&kiq->ring_lock, flags); + + r = amdgpu_ring_test_ring(kiq_ring); + if (r) + return r; + + if (amdgpu_ring_alloc(ring, 7 + 12 + 5)) + return -ENOMEM; + gfx_v7_0_ring_emit_fence_gfx(ring, ring->fence_drv.gpu_addr, + ring->fence_drv.sync_seq, AMDGPU_FENCE_FLAG_EXEC); + gfx_v7_0_ring_emit_reg_wait(ring, mmCP_VMID_RESET, 0, 0xffff); + gfx_v7_0_ring_emit_wreg(ring, mmCP_VMID_RESET, 0); + + return amdgpu_ring_test_ring(ring); +} + static const struct amd_ip_funcs gfx_v7_0_ip_funcs = { .name = "gfx_v7_0", .early_init = gfx_v7_0_early_init, @@ -4972,6 +5045,7 @@ static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_gfx = { .emit_wreg = gfx_v7_0_ring_emit_wreg, .soft_recovery = gfx_v7_0_ring_soft_recovery, .emit_mem_sync = gfx_v7_0_emit_mem_sync, + .reset = gfx_v7_0_reset_kgq, }; static const struct amdgpu_ring_funcs gfx_v7_0_ring_funcs_compute = { From 874b1261eb59a36f4146df961d833d39f187bc74 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 12 Jul 2024 15:36:19 -0400 Subject: [PATCH 1315/1868] drm/amdgpu/gfx11: enter safe mode before touching CP_INT_CNTL Need to enter safe mode before touching GC MMIO. Acked-by: Vitaly Prosyak Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index 22bb352786917..98261000e0220 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -4781,6 +4781,8 @@ static int gfx_v11_0_soft_reset(void *handle) int r, i, j, k; struct amdgpu_device *adev = (struct amdgpu_device *)handle; + gfx_v11_0_set_safe_mode(adev, 0); + tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL); tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 0); tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 0); @@ -4788,8 +4790,6 @@ static int gfx_v11_0_soft_reset(void *handle) tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 0); WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp); - gfx_v11_0_set_safe_mode(adev, 0); - mutex_lock(&adev->srbm_mutex); for (i = 0; i < adev->gfx.mec.num_mec; ++i) { for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { From a0ef5f1f8d12ff82ffed5718738cbf8f275959d0 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 12 Jul 2024 16:37:33 -0400 Subject: [PATCH 1316/1868] drm/amdgpu/gfx11: add a mutex for the gfx semaphore This will be used in more places in the future so add a mutex. Acked-by: Vitaly Prosyak Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 2 ++ drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 10 +++++++--- 3 files changed, 10 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index b4001e6272ba2..2743528ef2521 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -4076,6 +4076,7 @@ int amdgpu_device_init(struct amdgpu_device *adev, #endif mutex_init(&adev->pm.stable_pstate_ctx_lock); mutex_init(&adev->benchmark_mutex); + mutex_init(&adev->gfx.reset_sem_mutex); amdgpu_device_init_apu_flags(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h index 4416843b2be16..a6c35d8e5deb1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h @@ -455,6 +455,8 @@ struct amdgpu_gfx { uint32_t *ip_dump_core; uint32_t *ip_dump_compute_queues; uint32_t *ip_dump_gfx_queues; + + struct mutex reset_sem_mutex; }; struct amdgpu_gfx_ras_reg_entry { diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index 98261000e0220..01f220ee45618 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -4743,10 +4743,12 @@ static int gfx_v11_0_wait_for_idle(void *handle) } static int gfx_v11_0_request_gfx_index_mutex(struct amdgpu_device *adev, - int req) + bool req) { u32 i, tmp, val; + if (req) + mutex_lock(&adev->gfx.reset_sem_mutex); for (i = 0; i < adev->usec_timeout; i++) { /* Request with MeId=2, PipeId=0 */ tmp = REG_SET_FIELD(0, CP_GFX_INDEX_MUTEX, REQUEST, req); @@ -4767,6 +4769,8 @@ static int gfx_v11_0_request_gfx_index_mutex(struct amdgpu_device *adev, } udelay(1); } + if (!req) + mutex_unlock(&adev->gfx.reset_sem_mutex); if (i >= adev->usec_timeout) return -EINVAL; @@ -4814,7 +4818,7 @@ static int gfx_v11_0_soft_reset(void *handle) mutex_unlock(&adev->srbm_mutex); /* Try to acquire the gfx mutex before access to CP_VMID_RESET */ - r = gfx_v11_0_request_gfx_index_mutex(adev, 1); + r = gfx_v11_0_request_gfx_index_mutex(adev, true); if (r) { DRM_ERROR("Failed to acquire the gfx mutex during soft reset\n"); return r; @@ -4829,7 +4833,7 @@ static int gfx_v11_0_soft_reset(void *handle) RREG32_SOC15(GC, 0, regCP_VMID_RESET); /* release the gfx mutex */ - r = gfx_v11_0_request_gfx_index_mutex(adev, 0); + r = gfx_v11_0_request_gfx_index_mutex(adev, false); if (r) { DRM_ERROR("Failed to release the gfx mutex during soft reset\n"); return r; From d7b921daef7d22d8a0230a3c88a9497caf006859 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 12 Jul 2024 16:39:30 -0400 Subject: [PATCH 1317/1868] drm/amdgpu/gfx11: export gfx_v11_0_request_gfx_index_mutex() It will be used by the queue reset code. Acked-by: Vitaly Prosyak Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.h | 3 +++ 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index 01f220ee45618..5685aee479dfc 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -4742,8 +4742,8 @@ static int gfx_v11_0_wait_for_idle(void *handle) return -ETIMEDOUT; } -static int gfx_v11_0_request_gfx_index_mutex(struct amdgpu_device *adev, - bool req) +int gfx_v11_0_request_gfx_index_mutex(struct amdgpu_device *adev, + bool req) { u32 i, tmp, val; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.h b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.h index 10cfc29c27c9a..157a5c812259d 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.h +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.h @@ -26,4 +26,7 @@ extern const struct amdgpu_ip_block_version gfx_v11_0_ip_block; +int gfx_v11_0_request_gfx_index_mutex(struct amdgpu_device *adev, + bool req); + #endif From 86531d28e6e2768cedbe7373115da0fb75cb14bf Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 3 Jun 2024 13:35:05 -0400 Subject: [PATCH 1318/1868] drm/amdgpu/mes: add API for user queue reset Add API for resetting user queues. Acked-by: Vitaly Prosyak Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 43 +++++++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 9 ++++++ 2 files changed, 52 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c index 0caf5abfb8ccc..2993df13613be 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c @@ -793,6 +793,49 @@ int amdgpu_mes_remove_hw_queue(struct amdgpu_device *adev, int queue_id) return 0; } +int amdgpu_mes_reset_hw_queue(struct amdgpu_device *adev, int queue_id) +{ + unsigned long flags; + struct amdgpu_mes_queue *queue; + struct amdgpu_mes_gang *gang; + struct mes_reset_queue_input queue_input; + int r; + + /* + * Avoid taking any other locks under MES lock to avoid circular + * lock dependencies. + */ + amdgpu_mes_lock(&adev->mes); + + /* remove the mes gang from idr list */ + spin_lock_irqsave(&adev->mes.queue_id_lock, flags); + + queue = idr_find(&adev->mes.queue_id_idr, queue_id); + if (!queue) { + spin_unlock_irqrestore(&adev->mes.queue_id_lock, flags); + amdgpu_mes_unlock(&adev->mes); + DRM_ERROR("queue id %d doesn't exist\n", queue_id); + return -EINVAL; + } + spin_unlock_irqrestore(&adev->mes.queue_id_lock, flags); + + DRM_DEBUG("try to reset queue, doorbell off = 0x%llx\n", + queue->doorbell_off); + + gang = queue->gang; + queue_input.doorbell_offset = queue->doorbell_off; + queue_input.gang_context_addr = gang->gang_ctx_gpu_addr; + + r = adev->mes.funcs->reset_hw_queue(&adev->mes, &queue_input); + if (r) + DRM_ERROR("failed to reset hardware queue, queue id = %d\n", + queue_id); + + amdgpu_mes_unlock(&adev->mes); + + return 0; +} + int amdgpu_mes_map_legacy_queue(struct amdgpu_device *adev, struct amdgpu_ring *ring) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h index 548e724e3a750..5c8867d2380af 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h @@ -248,6 +248,11 @@ struct mes_remove_queue_input { uint64_t gang_context_addr; }; +struct mes_reset_queue_input { + uint32_t doorbell_offset; + uint64_t gang_context_addr; +}; + struct mes_map_legacy_queue_input { uint32_t queue_type; uint32_t doorbell_offset; @@ -360,6 +365,9 @@ struct amdgpu_mes_funcs { int (*reset_legacy_queue)(struct amdgpu_mes *mes, struct mes_reset_legacy_queue_input *input); + + int (*reset_hw_queue)(struct amdgpu_mes *mes, + struct mes_reset_queue_input *input); }; #define amdgpu_mes_kiq_hw_init(adev) (adev)->mes.kiq_hw_init((adev)) @@ -387,6 +395,7 @@ int amdgpu_mes_add_hw_queue(struct amdgpu_device *adev, int gang_id, struct amdgpu_mes_queue_properties *qprops, int *queue_id); int amdgpu_mes_remove_hw_queue(struct amdgpu_device *adev, int queue_id); +int amdgpu_mes_reset_hw_queue(struct amdgpu_device *adev, int queue_id); int amdgpu_mes_map_legacy_queue(struct amdgpu_device *adev, struct amdgpu_ring *ring); From 5a22a71cf5b39d98cf9655196499ecda211c05ed Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 3 Jun 2024 13:48:07 -0400 Subject: [PATCH 1319/1868] drm/amdgpu/mes11: add API for user queue reset Add API for resetting user queues. Acked-by: Vitaly Prosyak Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c index c0340ee3dec04..6f5a80519af92 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c @@ -360,6 +360,26 @@ static int mes_v11_0_remove_hw_queue(struct amdgpu_mes *mes, offsetof(union MESAPI__REMOVE_QUEUE, api_status)); } +static int mes_v11_0_reset_hw_queue(struct amdgpu_mes *mes, + struct mes_reset_queue_input *input) +{ + union MESAPI__RESET mes_reset_queue_pkt; + + memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt)); + + mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; + mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET; + mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; + + mes_reset_queue_pkt.doorbell_offset = input->doorbell_offset; + mes_reset_queue_pkt.gang_context_addr = input->gang_context_addr; + /*mes_reset_queue_pkt.reset_queue_only = 1;*/ + + return mes_v11_0_submit_pkt_and_poll_completion(mes, + &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt), + offsetof(union MESAPI__REMOVE_QUEUE, api_status)); +} + static int mes_v11_0_map_legacy_queue(struct amdgpu_mes *mes, struct mes_map_legacy_queue_input *input) { @@ -636,6 +656,7 @@ static const struct amdgpu_mes_funcs mes_v11_0_funcs = { .resume_gang = mes_v11_0_resume_gang, .misc_op = mes_v11_0_misc_op, .reset_legacy_queue = mes_v11_0_reset_legacy_queue, + .reset_hw_queue = mes_v11_0_reset_hw_queue, }; static int mes_v11_0_allocate_ucode_buffer(struct amdgpu_device *adev, From 55bf311fa16f033bd572df3faad661f476886c68 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 3 Jun 2024 13:48:40 -0400 Subject: [PATCH 1320/1868] drm/amdgpu/mes12: add API for user queue reset Add API for resetting user queues. Acked-by: Vitaly Prosyak Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 27 ++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c index 35cd6ad73912d..47a73f6ae4dae 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c @@ -350,6 +350,32 @@ static int mes_v12_0_remove_hw_queue(struct amdgpu_mes *mes, offsetof(union MESAPI__REMOVE_QUEUE, api_status)); } +static int mes_v12_0_reset_hw_queue(struct amdgpu_mes *mes, + struct mes_reset_queue_input *input) +{ + union MESAPI__RESET mes_reset_queue_pkt; + int pipe; + + memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt)); + + mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; + mes_reset_queue_pkt.header.opcode = MES_SCH_API_RESET; + mes_reset_queue_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; + + mes_reset_queue_pkt.doorbell_offset = input->doorbell_offset; + mes_reset_queue_pkt.gang_context_addr = input->gang_context_addr; + /*mes_reset_queue_pkt.reset_queue_only = 1;*/ + + if (mes->adev->enable_uni_mes) + pipe = AMDGPU_MES_KIQ_PIPE; + else + pipe = AMDGPU_MES_SCHED_PIPE; + + return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe, + &mes_reset_queue_pkt, sizeof(mes_reset_queue_pkt), + offsetof(union MESAPI__REMOVE_QUEUE, api_status)); +} + static int mes_v12_0_map_legacy_queue(struct amdgpu_mes *mes, struct mes_map_legacy_queue_input *input) { @@ -723,6 +749,7 @@ static const struct amdgpu_mes_funcs mes_v12_0_funcs = { .resume_gang = mes_v12_0_resume_gang, .misc_op = mes_v12_0_misc_op, .reset_legacy_queue = mes_v12_0_reset_legacy_queue, + .reset_hw_queue = mes_v12_0_reset_hw_queue, }; static int mes_v12_0_allocate_ucode_buffer(struct amdgpu_device *adev, From 6102c7ba1228e7e7b289888aa2efb1daf28c2e1f Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Thu, 1 Aug 2024 19:19:27 +0530 Subject: [PATCH 1321/1868] drm/amdgpu: add print support for vcn_v5_0 ip dump Add support for logging the registers in devcoredump buffer for vcn_v5_0. Signed-off-by: Sunil Khatri Acked-by: Leo Liu --- drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 34 ++++++++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c index a30a42b1ba03b..c305386358b4b 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c @@ -1343,6 +1343,38 @@ static void vcn_v5_0_0_set_irq_funcs(struct amdgpu_device *adev) } } +static void vcn_v5_0_print_ip_state(void *handle, struct drm_printer *p) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + int i, j; + uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_5_0); + uint32_t inst_off, is_powered; + + if (!adev->vcn.ip_dump) + return; + + drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst); + for (i = 0; i < adev->vcn.num_vcn_inst; i++) { + if (adev->vcn.harvest_config & (1 << i)) { + drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i); + continue; + } + + inst_off = i * reg_count; + is_powered = (adev->vcn.ip_dump[inst_off] & + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; + + if (is_powered) { + drm_printf(p, "\nActive Instance:VCN%d\n", i); + for (j = 0; j < reg_count; j++) + drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_5_0[j].reg_name, + adev->vcn.ip_dump[inst_off + j]); + } else { + drm_printf(p, "\nInactive Instance:VCN%d\n", i); + } + } +} + static void vcn_v5_0_dump_ip_state(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; @@ -1390,7 +1422,7 @@ static const struct amd_ip_funcs vcn_v5_0_0_ip_funcs = { .set_clockgating_state = vcn_v5_0_0_set_clockgating_state, .set_powergating_state = vcn_v5_0_0_set_powergating_state, .dump_ip_state = vcn_v5_0_dump_ip_state, - .print_ip_state = NULL, + .print_ip_state = vcn_v5_0_print_ip_state, }; const struct amdgpu_ip_block_version vcn_v5_0_0_ip_block = { From 3dbf9515f5ae91ad7abf1a30f89e65513f161821 Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Mon, 5 Aug 2024 12:49:20 +0530 Subject: [PATCH 1322/1868] drm/amdgpu: add vcn_v4_0_3 ip dump support Add support of vcn ip dump in the devcoredump for vcn_v4_0_3. Signed-off-by: Sunil Khatri Acked-by: Leo Liu --- drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 81 ++++++++++++++++++++++++- 1 file changed, 80 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c index 9bae95538b628..77cc6807d1194 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c @@ -45,6 +45,42 @@ #define VCN_VID_SOC_ADDRESS_2_0 0x1fb00 #define VCN1_VID_SOC_ADDRESS_3_0 0x48300 +static const struct amdgpu_hwip_reg_entry vcn_reg_list_4_0_3[] = { + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID2), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA0), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA1), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_CMD), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI2), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO2), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI3), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO3), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI4), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO4), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR2), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR2), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR3), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR3), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR4), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR4), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE2), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_PGFSM_CONFIG), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_PGFSM_STATUS), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_DATA), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_MASK), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_PAUSE) +}; + #define NORMALIZE_VCN_REG_OFFSET(offset) \ (offset & 0x1FFFF) @@ -92,6 +128,8 @@ static int vcn_v4_0_3_sw_init(void *handle) struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct amdgpu_ring *ring; int i, r, vcn_inst; + uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_3); + uint32_t *ptr; r = amdgpu_vcn_sw_init(adev); if (r) @@ -159,6 +197,15 @@ static int vcn_v4_0_3_sw_init(void *handle) } } + /* Allocate memory for VCN IP Dump buffer */ + ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL); + if (!ptr) { + DRM_ERROR("Failed to allocate memory for VCN IP Dump\n"); + adev->vcn.ip_dump = NULL; + } else { + adev->vcn.ip_dump = ptr; + } + return 0; } @@ -194,6 +241,8 @@ static int vcn_v4_0_3_sw_fini(void *handle) r = amdgpu_vcn_sw_fini(adev); + kfree(adev->vcn.ip_dump); + return r; } @@ -1684,6 +1733,36 @@ static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev) adev->vcn.inst->irq.funcs = &vcn_v4_0_3_irq_funcs; } +static void vcn_v4_0_3_dump_ip_state(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + int i, j; + bool is_powered; + uint32_t inst_off, inst_id; + uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_3); + + if (!adev->vcn.ip_dump) + return; + + for (i = 0; i < adev->vcn.num_vcn_inst; i++) { + if (adev->vcn.harvest_config & (1 << i)) + continue; + + inst_id = GET_INST(VCN, i); + inst_off = i * reg_count; + /* mmUVD_POWER_STATUS is always readable and is first element of the array */ + adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, inst_id, regUVD_POWER_STATUS); + is_powered = (adev->vcn.ip_dump[inst_off] & + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; + + if (is_powered) + for (j = 1; j < reg_count; j++) + adev->vcn.ip_dump[inst_off + j] = + RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_4_0_3[j], + inst_id)); + } +} + static const struct amd_ip_funcs vcn_v4_0_3_ip_funcs = { .name = "vcn_v4_0_3", .early_init = vcn_v4_0_3_early_init, @@ -1702,7 +1781,7 @@ static const struct amd_ip_funcs vcn_v4_0_3_ip_funcs = { .post_soft_reset = NULL, .set_clockgating_state = vcn_v4_0_3_set_clockgating_state, .set_powergating_state = vcn_v4_0_3_set_powergating_state, - .dump_ip_state = NULL, + .dump_ip_state = vcn_v4_0_3_dump_ip_state, .print_ip_state = NULL, }; From a0430563b8af8d53b7b65cd35ae0dcf5417c1840 Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Mon, 5 Aug 2024 12:31:21 +0530 Subject: [PATCH 1323/1868] drm/amdgpu: add vcn_v4_0 ip dump support Add support of vcn ip dump in the devcoredump for vcn_v4_0. Signed-off-by: Sunil Khatri Acked-by: Leo Liu --- drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 80 ++++++++++++++++++++++++++- 1 file changed, 79 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c index 776c539bfddac..abd5a0793e586 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c @@ -52,6 +52,42 @@ #define RDECODE_MSG_CREATE 0x00000000 #define RDECODE_MESSAGE_CREATE 0x00000001 +static const struct amdgpu_hwip_reg_entry vcn_reg_list_4_0[] = { + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID2), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA0), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA1), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_CMD), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI2), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO2), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI3), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO3), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI4), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO4), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR2), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR2), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR3), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR3), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR4), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR4), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE2), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_PGFSM_CONFIG), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_PGFSM_STATUS), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_DATA), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_MASK), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_PAUSE) +}; + static int amdgpu_ih_clientid_vcns[] = { SOC15_IH_CLIENTID_VCN, SOC15_IH_CLIENTID_VCN1 @@ -137,6 +173,8 @@ static int vcn_v4_0_sw_init(void *handle) struct amdgpu_ring *ring; struct amdgpu_device *adev = (struct amdgpu_device *)handle; int i, r; + uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0); + uint32_t *ptr; r = amdgpu_vcn_sw_init(adev); if (r) @@ -200,6 +238,15 @@ static int vcn_v4_0_sw_init(void *handle) if (r) return r; + /* Allocate memory for VCN IP Dump buffer */ + ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL); + if (!ptr) { + DRM_ERROR("Failed to allocate memory for VCN IP Dump\n"); + adev->vcn.ip_dump = NULL; + } else { + adev->vcn.ip_dump = ptr; + } + return 0; } @@ -239,6 +286,8 @@ static int vcn_v4_0_sw_fini(void *handle) r = amdgpu_vcn_sw_fini(adev); + kfree(adev->vcn.ip_dump); + return r; } @@ -2109,6 +2158,35 @@ static void vcn_v4_0_set_irq_funcs(struct amdgpu_device *adev) } } +static void vcn_v4_0_dump_ip_state(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + int i, j; + bool is_powered; + uint32_t inst_off; + uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0); + + if (!adev->vcn.ip_dump) + return; + + for (i = 0; i < adev->vcn.num_vcn_inst; i++) { + if (adev->vcn.harvest_config & (1 << i)) + continue; + + inst_off = i * reg_count; + /* mmUVD_POWER_STATUS is always readable and is first element of the array */ + adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, regUVD_POWER_STATUS); + is_powered = (adev->vcn.ip_dump[inst_off] & + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; + + if (is_powered) + for (j = 1; j < reg_count; j++) + adev->vcn.ip_dump[inst_off + j] = + RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_4_0[j], + i)); + } +} + static const struct amd_ip_funcs vcn_v4_0_ip_funcs = { .name = "vcn_v4_0", .early_init = vcn_v4_0_early_init, @@ -2127,7 +2205,7 @@ static const struct amd_ip_funcs vcn_v4_0_ip_funcs = { .post_soft_reset = NULL, .set_clockgating_state = vcn_v4_0_set_clockgating_state, .set_powergating_state = vcn_v4_0_set_powergating_state, - .dump_ip_state = NULL, + .dump_ip_state = vcn_v4_0_dump_ip_state, .print_ip_state = NULL, }; From fca1d3b55a68a1fe1c7681cac68dbfd8de9f7481 Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Mon, 5 Aug 2024 12:57:09 +0530 Subject: [PATCH 1324/1868] drm/amdgpu: add vcn_v4_0_5 ip dump support Add support of vcn ip dump in the devcoredump for vcn_v4_0_5. Signed-off-by: Sunil Khatri Acked-by: Leo Liu --- drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 79 ++++++++++++++++++++++++- 1 file changed, 78 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c index 8d75061f9f384..b05bfe1dad758 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c @@ -52,6 +52,42 @@ #define RDECODE_MSG_CREATE 0x00000000 #define RDECODE_MESSAGE_CREATE 0x00000001 +static const struct amdgpu_hwip_reg_entry vcn_reg_list_4_0_5[] = { + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_POWER_STATUS), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_STATUS), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_CONTEXT_ID2), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA0), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_DATA1), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_GPCOM_VCPU_CMD), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI2), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO2), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI3), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO3), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_HI4), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_BASE_LO4), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR2), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR2), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR3), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR3), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_RPTR4), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_WPTR4), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE2), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE3), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_RB_SIZE4), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_PGFSM_CONFIG), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_PGFSM_STATUS), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_CTL), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_DATA), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_LMA_MASK), + SOC15_REG_ENTRY_STR(VCN, 0, regUVD_DPG_PAUSE) +}; + static int amdgpu_ih_clientid_vcns[] = { SOC15_IH_CLIENTID_VCN, SOC15_IH_CLIENTID_VCN1 @@ -97,6 +133,8 @@ static int vcn_v4_0_5_sw_init(void *handle) struct amdgpu_ring *ring; struct amdgpu_device *adev = (struct amdgpu_device *)handle; int i, r; + uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_5); + uint32_t *ptr; r = amdgpu_vcn_sw_init(adev); if (r) @@ -168,6 +206,14 @@ static int vcn_v4_0_5_sw_init(void *handle) if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) adev->vcn.pause_dpg_mode = vcn_v4_0_5_pause_dpg_mode; + /* Allocate memory for VCN IP Dump buffer */ + ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL); + if (!ptr) { + DRM_ERROR("Failed to allocate memory for VCN IP Dump\n"); + adev->vcn.ip_dump = NULL; + } else { + adev->vcn.ip_dump = ptr; + } return 0; } @@ -207,6 +253,8 @@ static int vcn_v4_0_5_sw_fini(void *handle) r = amdgpu_vcn_sw_fini(adev); + kfree(adev->vcn.ip_dump); + return r; } @@ -1733,6 +1781,35 @@ static void vcn_v4_0_5_set_irq_funcs(struct amdgpu_device *adev) } } +static void vcn_v4_0_5_dump_ip_state(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + int i, j; + bool is_powered; + uint32_t inst_off; + uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_5); + + if (!adev->vcn.ip_dump) + return; + + for (i = 0; i < adev->vcn.num_vcn_inst; i++) { + if (adev->vcn.harvest_config & (1 << i)) + continue; + + inst_off = i * reg_count; + /* mmUVD_POWER_STATUS is always readable and is first element of the array */ + adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, regUVD_POWER_STATUS); + is_powered = (adev->vcn.ip_dump[inst_off] & + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; + + if (is_powered) + for (j = 1; j < reg_count; j++) + adev->vcn.ip_dump[inst_off + j] = + RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_4_0_5[j], + i)); + } +} + static const struct amd_ip_funcs vcn_v4_0_5_ip_funcs = { .name = "vcn_v4_0_5", .early_init = vcn_v4_0_5_early_init, @@ -1751,7 +1828,7 @@ static const struct amd_ip_funcs vcn_v4_0_5_ip_funcs = { .post_soft_reset = NULL, .set_clockgating_state = vcn_v4_0_5_set_clockgating_state, .set_powergating_state = vcn_v4_0_5_set_powergating_state, - .dump_ip_state = NULL, + .dump_ip_state = vcn_v4_0_5_dump_ip_state, .print_ip_state = NULL, }; From e236070cb400eb47ff07591ea7b67389cd6093c4 Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Mon, 5 Aug 2024 12:52:27 +0530 Subject: [PATCH 1325/1868] drm/amdgpu: add print support for vcn_v4_0_3 ip dump Add support for logging the registers in devcoredump buffer for vcn_v4_0_3. Signed-off-by: Sunil Khatri Acked-by: Leo Liu --- drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 34 ++++++++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c index 77cc6807d1194..0fda703363004 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c @@ -1733,6 +1733,38 @@ static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev) adev->vcn.inst->irq.funcs = &vcn_v4_0_3_irq_funcs; } +static void vcn_v4_0_3_print_ip_state(void *handle, struct drm_printer *p) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + int i, j; + uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_3); + uint32_t inst_off, is_powered; + + if (!adev->vcn.ip_dump) + return; + + drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst); + for (i = 0; i < adev->vcn.num_vcn_inst; i++) { + if (adev->vcn.harvest_config & (1 << i)) { + drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i); + continue; + } + + inst_off = i * reg_count; + is_powered = (adev->vcn.ip_dump[inst_off] & + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; + + if (is_powered) { + drm_printf(p, "\nActive Instance:VCN%d\n", i); + for (j = 0; j < reg_count; j++) + drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_4_0_3[j].reg_name, + adev->vcn.ip_dump[inst_off + j]); + } else { + drm_printf(p, "\nInactive Instance:VCN%d\n", i); + } + } +} + static void vcn_v4_0_3_dump_ip_state(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; @@ -1782,7 +1814,7 @@ static const struct amd_ip_funcs vcn_v4_0_3_ip_funcs = { .set_clockgating_state = vcn_v4_0_3_set_clockgating_state, .set_powergating_state = vcn_v4_0_3_set_powergating_state, .dump_ip_state = vcn_v4_0_3_dump_ip_state, - .print_ip_state = NULL, + .print_ip_state = vcn_v4_0_3_print_ip_state, }; const struct amdgpu_ip_block_version vcn_v4_0_3_ip_block = { From db811f111b09094a77e3e931a50ddfcc3763e9b4 Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Mon, 5 Aug 2024 12:43:07 +0530 Subject: [PATCH 1326/1868] drm/amdgpu: add print support for vcn_v4_0 ip dump Add support for logging the registers in devcoredump buffer for vcn_v4_0. Signed-off-by: Sunil Khatri Acked-by: Leo Liu --- drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 34 ++++++++++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c index abd5a0793e586..26c6f10a8c8fa 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c @@ -2158,6 +2158,38 @@ static void vcn_v4_0_set_irq_funcs(struct amdgpu_device *adev) } } +static void vcn_v4_0_print_ip_state(void *handle, struct drm_printer *p) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + int i, j; + uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0); + uint32_t inst_off, is_powered; + + if (!adev->vcn.ip_dump) + return; + + drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst); + for (i = 0; i < adev->vcn.num_vcn_inst; i++) { + if (adev->vcn.harvest_config & (1 << i)) { + drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i); + continue; + } + + inst_off = i * reg_count; + is_powered = (adev->vcn.ip_dump[inst_off] & + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; + + if (is_powered) { + drm_printf(p, "\nActive Instance:VCN%d\n", i); + for (j = 0; j < reg_count; j++) + drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_4_0[j].reg_name, + adev->vcn.ip_dump[inst_off + j]); + } else { + drm_printf(p, "\nInactive Instance:VCN%d\n", i); + } + } +} + static void vcn_v4_0_dump_ip_state(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; @@ -2206,7 +2238,7 @@ static const struct amd_ip_funcs vcn_v4_0_ip_funcs = { .set_clockgating_state = vcn_v4_0_set_clockgating_state, .set_powergating_state = vcn_v4_0_set_powergating_state, .dump_ip_state = vcn_v4_0_dump_ip_state, - .print_ip_state = NULL, + .print_ip_state = vcn_v4_0_print_ip_state, }; const struct amdgpu_ip_block_version vcn_v4_0_ip_block = { From 66be4126bc0c3a57b73bfac1e5df0f475af4c33a Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Mon, 5 Aug 2024 12:58:46 +0530 Subject: [PATCH 1327/1868] drm/amdgpu: add print support for vcn_v4_0_5 ip dump Add support for logging the registers in devcoredump buffer for vcn_v4_0_5. Signed-off-by: Sunil Khatri Acked-by: Leo Liu --- drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 34 ++++++++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c index b05bfe1dad758..b1fd226b7efb4 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c @@ -1781,6 +1781,38 @@ static void vcn_v4_0_5_set_irq_funcs(struct amdgpu_device *adev) } } +static void vcn_v4_0_5_print_ip_state(void *handle, struct drm_printer *p) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + int i, j; + uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_5); + uint32_t inst_off, is_powered; + + if (!adev->vcn.ip_dump) + return; + + drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst); + for (i = 0; i < adev->vcn.num_vcn_inst; i++) { + if (adev->vcn.harvest_config & (1 << i)) { + drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i); + continue; + } + + inst_off = i * reg_count; + is_powered = (adev->vcn.ip_dump[inst_off] & + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; + + if (is_powered) { + drm_printf(p, "\nActive Instance:VCN%d\n", i); + for (j = 0; j < reg_count; j++) + drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_4_0_5[j].reg_name, + adev->vcn.ip_dump[inst_off + j]); + } else { + drm_printf(p, "\nInactive Instance:VCN%d\n", i); + } + } +} + static void vcn_v4_0_5_dump_ip_state(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; @@ -1829,7 +1861,7 @@ static const struct amd_ip_funcs vcn_v4_0_5_ip_funcs = { .set_clockgating_state = vcn_v4_0_5_set_clockgating_state, .set_powergating_state = vcn_v4_0_5_set_powergating_state, .dump_ip_state = vcn_v4_0_5_dump_ip_state, - .print_ip_state = NULL, + .print_ip_state = vcn_v4_0_5_print_ip_state, }; const struct amdgpu_ip_block_version vcn_v4_0_5_ip_block = { From 01da8d6d03a21392fbaad9fb38da5dc7004d41fb Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Mon, 5 Aug 2024 17:06:24 +0530 Subject: [PATCH 1328/1868] drm/amdgpu: add vcn_v1_0 ip dump support Add support of vcn ip dump in the devcoredump for vcn_v1_0. Signed-off-by: Sunil Khatri Acked-by: Leo Liu --- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 78 ++++++++++++++++++++++++++- 1 file changed, 77 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index 6d82504384e10..e317751d923b5 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c @@ -45,6 +45,42 @@ #define mmUVD_REG_XX_MASK_1_0 0x05ac #define mmUVD_REG_XX_MASK_1_0_BASE_IDX 1 +static const struct amdgpu_hwip_reg_entry vcn_reg_list_1_0[] = { + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_POWER_STATUS), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_STATUS), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID2), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA0), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA1), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_CMD), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI2), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO2), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI3), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO3), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI4), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO4), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR2), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR2), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR3), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR3), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR4), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR4), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE2), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE3), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE4), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_CONFIG), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_STATUS), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_CTL), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_DATA), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_MASK), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_PAUSE) +}; + static int vcn_v1_0_stop(struct amdgpu_device *adev); static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev); static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev); @@ -90,6 +126,8 @@ static int vcn_v1_0_sw_init(void *handle) { struct amdgpu_ring *ring; int i, r; + uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_1_0); + uint32_t *ptr; struct amdgpu_device *adev = (struct amdgpu_device *)handle; /* VCN DEC TRAP */ @@ -161,6 +199,14 @@ static int vcn_v1_0_sw_init(void *handle) r = jpeg_v1_0_sw_init(handle); + /* Allocate memory for VCN IP Dump buffer */ + ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL); + if (!ptr) { + DRM_ERROR("Failed to allocate memory for VCN IP Dump\n"); + adev->vcn.ip_dump = NULL; + } else { + adev->vcn.ip_dump = ptr; + } return r; } @@ -184,6 +230,8 @@ static int vcn_v1_0_sw_fini(void *handle) r = amdgpu_vcn_sw_fini(adev); + kfree(adev->vcn.ip_dump); + return r; } @@ -1877,6 +1925,34 @@ void vcn_v1_0_ring_end_use(struct amdgpu_ring *ring) mutex_unlock(&ring->adev->vcn.vcn1_jpeg1_workaround); } +static void vcn_v1_0_dump_ip_state(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + int i, j; + bool is_powered; + uint32_t inst_off; + uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_1_0); + + if (!adev->vcn.ip_dump) + return; + + for (i = 0; i < adev->vcn.num_vcn_inst; i++) { + if (adev->vcn.harvest_config & (1 << i)) + continue; + + inst_off = i * reg_count; + /* mmUVD_POWER_STATUS is always readable and is first element of the array */ + adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, mmUVD_POWER_STATUS); + is_powered = (adev->vcn.ip_dump[inst_off] & + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; + + if (is_powered) + for (j = 1; j < reg_count; j++) + adev->vcn.ip_dump[inst_off + j] = + RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_1_0[j], i)); + } +} + static const struct amd_ip_funcs vcn_v1_0_ip_funcs = { .name = "vcn_v1_0", .early_init = vcn_v1_0_early_init, @@ -1895,7 +1971,7 @@ static const struct amd_ip_funcs vcn_v1_0_ip_funcs = { .post_soft_reset = NULL /* vcn_v1_0_post_soft_reset */, .set_clockgating_state = vcn_v1_0_set_clockgating_state, .set_powergating_state = vcn_v1_0_set_powergating_state, - .dump_ip_state = NULL, + .dump_ip_state = vcn_v1_0_dump_ip_state, .print_ip_state = NULL, }; From 90927bbc48b5420a7da6145a0f803f0321bf8eff Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Mon, 5 Aug 2024 17:08:22 +0530 Subject: [PATCH 1329/1868] drm/amdgpu: add print support for vcn_v1_0 ip dump Add support for logging the registers in devcoredump buffer for vcn_v1_0. Signed-off-by: Sunil Khatri Acked-by: Leo Liu --- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 34 ++++++++++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index e317751d923b5..5d3bfc24609bf 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c @@ -1925,6 +1925,38 @@ void vcn_v1_0_ring_end_use(struct amdgpu_ring *ring) mutex_unlock(&ring->adev->vcn.vcn1_jpeg1_workaround); } +static void vcn_v1_0_print_ip_state(void *handle, struct drm_printer *p) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + int i, j; + uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_1_0); + uint32_t inst_off, is_powered; + + if (!adev->vcn.ip_dump) + return; + + drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst); + for (i = 0; i < adev->vcn.num_vcn_inst; i++) { + if (adev->vcn.harvest_config & (1 << i)) { + drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i); + continue; + } + + inst_off = i * reg_count; + is_powered = (adev->vcn.ip_dump[inst_off] & + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; + + if (is_powered) { + drm_printf(p, "\nActive Instance:VCN%d\n", i); + for (j = 0; j < reg_count; j++) + drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_1_0[j].reg_name, + adev->vcn.ip_dump[inst_off + j]); + } else { + drm_printf(p, "\nInactive Instance:VCN%d\n", i); + } + } +} + static void vcn_v1_0_dump_ip_state(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; @@ -1972,7 +2004,7 @@ static const struct amd_ip_funcs vcn_v1_0_ip_funcs = { .set_clockgating_state = vcn_v1_0_set_clockgating_state, .set_powergating_state = vcn_v1_0_set_powergating_state, .dump_ip_state = vcn_v1_0_dump_ip_state, - .print_ip_state = NULL, + .print_ip_state = vcn_v1_0_print_ip_state, }; /* From 861792447f73397f6aadda3a5dc74068b9bb52f0 Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Mon, 5 Aug 2024 17:18:09 +0530 Subject: [PATCH 1330/1868] drm/amdgpu: add vcn_v2_0 ip dump support Add support of vcn ip dump in the devcoredump for vcn_v2_0. Signed-off-by: Sunil Khatri Acked-by: Leo Liu --- drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 79 ++++++++++++++++++++++++++- 1 file changed, 78 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c index d3d096909a7f4..710d054e96f8b 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c @@ -53,6 +53,42 @@ #define mmUVD_LMI_RBC_IB_64BIT_BAR_LOW_INTERNAL_OFFSET 0x5a7 #define mmUVD_RBC_IB_SIZE_INTERNAL_OFFSET 0x1e2 +static const struct amdgpu_hwip_reg_entry vcn_reg_list_2_0[] = { + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_POWER_STATUS), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_STATUS), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID2), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA0), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA1), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_CMD), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI2), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO2), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI3), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO3), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI4), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO4), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR2), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR2), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR3), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR3), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR4), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR4), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE2), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE3), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE4), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_CONFIG), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_STATUS), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_CTL), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_DATA), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_MASK), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_PAUSE) +}; + static void vcn_v2_0_set_dec_ring_funcs(struct amdgpu_device *adev); static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev); static void vcn_v2_0_set_irq_funcs(struct amdgpu_device *adev); @@ -96,6 +132,8 @@ static int vcn_v2_0_sw_init(void *handle) { struct amdgpu_ring *ring; int i, r; + uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_0); + uint32_t *ptr; struct amdgpu_device *adev = (struct amdgpu_device *)handle; volatile struct amdgpu_fw_shared *fw_shared; @@ -184,6 +222,15 @@ static int vcn_v2_0_sw_init(void *handle) if (amdgpu_vcnfw_log) amdgpu_vcn_fwlog_init(adev->vcn.inst); + /* Allocate memory for VCN IP Dump buffer */ + ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL); + if (!ptr) { + DRM_ERROR("Failed to allocate memory for VCN IP Dump\n"); + adev->vcn.ip_dump = NULL; + } else { + adev->vcn.ip_dump = ptr; + } + return 0; } @@ -213,6 +260,8 @@ static int vcn_v2_0_sw_fini(void *handle) r = amdgpu_vcn_sw_fini(adev); + kfree(adev->vcn.ip_dump); + return r; } @@ -1985,6 +2034,34 @@ static int vcn_v2_0_start_sriov(struct amdgpu_device *adev) return vcn_v2_0_start_mmsch(adev, &adev->virt.mm_table); } +static void vcn_v2_0_dump_ip_state(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + int i, j; + bool is_powered; + uint32_t inst_off; + uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_0); + + if (!adev->vcn.ip_dump) + return; + + for (i = 0; i < adev->vcn.num_vcn_inst; i++) { + if (adev->vcn.harvest_config & (1 << i)) + continue; + + inst_off = i * reg_count; + /* mmUVD_POWER_STATUS is always readable and is first element of the array */ + adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, mmUVD_POWER_STATUS); + is_powered = (adev->vcn.ip_dump[inst_off] & + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; + + if (is_powered) + for (j = 1; j < reg_count; j++) + adev->vcn.ip_dump[inst_off + j] = + RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_2_0[j], i)); + } +} + static const struct amd_ip_funcs vcn_v2_0_ip_funcs = { .name = "vcn_v2_0", .early_init = vcn_v2_0_early_init, @@ -2003,7 +2080,7 @@ static const struct amd_ip_funcs vcn_v2_0_ip_funcs = { .post_soft_reset = NULL, .set_clockgating_state = vcn_v2_0_set_clockgating_state, .set_powergating_state = vcn_v2_0_set_powergating_state, - .dump_ip_state = NULL, + .dump_ip_state = vcn_v2_0_dump_ip_state, .print_ip_state = NULL, }; From c78ae486847c9f5e299063a89dc69be9376085ca Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Mon, 5 Aug 2024 17:19:42 +0530 Subject: [PATCH 1331/1868] drm/amdgpu: add print support for vcn_v2_0 ip dump Add support for logging the registers in devcoredump buffer for vcn_v2_0. Signed-off-by: Sunil Khatri Acked-by: Leo Liu --- drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 34 ++++++++++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c index 710d054e96f8b..bfd067e2d2f1d 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c @@ -2034,6 +2034,38 @@ static int vcn_v2_0_start_sriov(struct amdgpu_device *adev) return vcn_v2_0_start_mmsch(adev, &adev->virt.mm_table); } +static void vcn_v2_0_print_ip_state(void *handle, struct drm_printer *p) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + int i, j; + uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_0); + uint32_t inst_off, is_powered; + + if (!adev->vcn.ip_dump) + return; + + drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst); + for (i = 0; i < adev->vcn.num_vcn_inst; i++) { + if (adev->vcn.harvest_config & (1 << i)) { + drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i); + continue; + } + + inst_off = i * reg_count; + is_powered = (adev->vcn.ip_dump[inst_off] & + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; + + if (is_powered) { + drm_printf(p, "\nActive Instance:VCN%d\n", i); + for (j = 0; j < reg_count; j++) + drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_2_0[j].reg_name, + adev->vcn.ip_dump[inst_off + j]); + } else { + drm_printf(p, "\nInactive Instance:VCN%d\n", i); + } + } +} + static void vcn_v2_0_dump_ip_state(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; @@ -2081,7 +2113,7 @@ static const struct amd_ip_funcs vcn_v2_0_ip_funcs = { .set_clockgating_state = vcn_v2_0_set_clockgating_state, .set_powergating_state = vcn_v2_0_set_powergating_state, .dump_ip_state = vcn_v2_0_dump_ip_state, - .print_ip_state = NULL, + .print_ip_state = vcn_v2_0_print_ip_state, }; static const struct amdgpu_ring_funcs vcn_v2_0_dec_ring_vm_funcs = { From 4f55aa2eef88fe302112203a9e92bbab10910dba Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Mon, 5 Aug 2024 17:23:55 +0530 Subject: [PATCH 1332/1868] drm/amdgpu: add vcn_v2_5 ip dump support Add support of vcn ip dump in the devcoredump for vcn_v2_5. Signed-off-by: Sunil Khatri Acked-by: Leo Liu --- drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 80 ++++++++++++++++++++++++++- 1 file changed, 79 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c index 96f60c3031610..343a9667e03a7 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c @@ -55,6 +55,43 @@ #define VCN25_MAX_HW_INSTANCES_ARCTURUS 2 +static const struct amdgpu_hwip_reg_entry vcn_reg_list_2_5[] = { + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_POWER_STATUS), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_POWER_STATUS), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_STATUS), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_CONTEXT_ID2), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA0), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_DATA1), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_GPCOM_VCPU_CMD), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI2), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO2), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI3), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO3), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_HI4), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_BASE_LO4), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR2), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR2), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR3), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR3), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_RPTR4), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_WPTR4), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE2), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE3), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_RB_SIZE4), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_CONFIG), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_PGFSM_STATUS), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_CTL), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_DATA), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_LMA_MASK), + SOC15_REG_ENTRY_STR(VCN, 0, mmUVD_DPG_PAUSE) +}; + static void vcn_v2_5_set_dec_ring_funcs(struct amdgpu_device *adev); static void vcn_v2_5_set_enc_ring_funcs(struct amdgpu_device *adev); static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev); @@ -122,6 +159,8 @@ static int vcn_v2_5_sw_init(void *handle) { struct amdgpu_ring *ring; int i, j, r; + uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_5); + uint32_t *ptr; struct amdgpu_device *adev = (struct amdgpu_device *)handle; for (j = 0; j < adev->vcn.num_vcn_inst; j++) { @@ -241,6 +280,15 @@ static int vcn_v2_5_sw_init(void *handle) if (r) return r; + /* Allocate memory for VCN IP Dump buffer */ + ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL); + if (!ptr) { + DRM_ERROR("Failed to allocate memory for VCN IP Dump\n"); + adev->vcn.ip_dump = NULL; + } else { + adev->vcn.ip_dump = ptr; + } + return 0; } @@ -277,6 +325,8 @@ static int vcn_v2_5_sw_fini(void *handle) r = amdgpu_vcn_sw_fini(adev); + kfree(adev->vcn.ip_dump); + return r; } @@ -1876,6 +1926,34 @@ static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev) } } +static void vcn_v2_5_dump_ip_state(void *handle) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + int i, j; + bool is_powered; + uint32_t inst_off; + uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_5); + + if (!adev->vcn.ip_dump) + return; + + for (i = 0; i < adev->vcn.num_vcn_inst; i++) { + if (adev->vcn.harvest_config & (1 << i)) + continue; + + inst_off = i * reg_count; + /* mmUVD_POWER_STATUS is always readable and is first element of the array */ + adev->vcn.ip_dump[inst_off] = RREG32_SOC15(VCN, i, mmUVD_POWER_STATUS); + is_powered = (adev->vcn.ip_dump[inst_off] & + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; + + if (is_powered) + for (j = 1; j < reg_count; j++) + adev->vcn.ip_dump[inst_off + j] = + RREG32(SOC15_REG_ENTRY_OFFSET_INST(vcn_reg_list_2_5[j], i)); + } +} + static const struct amd_ip_funcs vcn_v2_5_ip_funcs = { .name = "vcn_v2_5", .early_init = vcn_v2_5_early_init, @@ -1894,7 +1972,7 @@ static const struct amd_ip_funcs vcn_v2_5_ip_funcs = { .post_soft_reset = NULL, .set_clockgating_state = vcn_v2_5_set_clockgating_state, .set_powergating_state = vcn_v2_5_set_powergating_state, - .dump_ip_state = NULL, + .dump_ip_state = vcn_v2_5_dump_ip_state, .print_ip_state = NULL, }; From d53ee5739daf14d91877b9f6328ddb39421df634 Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Mon, 5 Aug 2024 17:26:31 +0530 Subject: [PATCH 1333/1868] drm/amdgpu: add print support for vcn_v2_5 ip dump Add support for logging the registers in devcoredump buffer for vcn_v2_5. Signed-off-by: Sunil Khatri Acked-by: Leo Liu --- drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 34 ++++++++++++++++++++++++++- 1 file changed, 33 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c index 343a9667e03a7..661eef38aec94 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c @@ -1926,6 +1926,38 @@ static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev) } } +static void vcn_v2_5_print_ip_state(void *handle, struct drm_printer *p) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)handle; + int i, j; + uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_5); + uint32_t inst_off, is_powered; + + if (!adev->vcn.ip_dump) + return; + + drm_printf(p, "num_instances:%d\n", adev->vcn.num_vcn_inst); + for (i = 0; i < adev->vcn.num_vcn_inst; i++) { + if (adev->vcn.harvest_config & (1 << i)) { + drm_printf(p, "\nHarvested Instance:VCN%d Skipping dump\n", i); + continue; + } + + inst_off = i * reg_count; + is_powered = (adev->vcn.ip_dump[inst_off] & + UVD_POWER_STATUS__UVD_POWER_STATUS_MASK) != 1; + + if (is_powered) { + drm_printf(p, "\nActive Instance:VCN%d\n", i); + for (j = 0; j < reg_count; j++) + drm_printf(p, "%-50s \t 0x%08x\n", vcn_reg_list_2_5[j].reg_name, + adev->vcn.ip_dump[inst_off + j]); + } else { + drm_printf(p, "\nInactive Instance:VCN%d\n", i); + } + } +} + static void vcn_v2_5_dump_ip_state(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; @@ -1973,7 +2005,7 @@ static const struct amd_ip_funcs vcn_v2_5_ip_funcs = { .set_clockgating_state = vcn_v2_5_set_clockgating_state, .set_powergating_state = vcn_v2_5_set_powergating_state, .dump_ip_state = vcn_v2_5_dump_ip_state, - .print_ip_state = NULL, + .print_ip_state = vcn_v2_5_print_ip_state, }; static const struct amd_ip_funcs vcn_v2_6_ip_funcs = { From 954dda6bd3618160e135a6ae15ddb79160fd62f3 Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Mon, 5 Aug 2024 17:27:58 +0530 Subject: [PATCH 1334/1868] drm/amdgpu: add vcn ip dump support for vcn_v2_6 Add support for logging the registers in devcoredump buffer for vcn_v2_6. Signed-off-by: Sunil Khatri Acked-by: Leo Liu --- drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c index 661eef38aec94..04e9e806e3187 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c @@ -2026,8 +2026,8 @@ static const struct amd_ip_funcs vcn_v2_6_ip_funcs = { .post_soft_reset = NULL, .set_clockgating_state = vcn_v2_5_set_clockgating_state, .set_powergating_state = vcn_v2_5_set_powergating_state, - .dump_ip_state = NULL, - .print_ip_state = NULL, + .dump_ip_state = vcn_v2_5_dump_ip_state, + .print_ip_state = vcn_v2_5_print_ip_state, }; const struct amdgpu_ip_block_version vcn_v2_5_ip_block = From b2a9447d453b2434a4f59c285403ca9425c2f6ab Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 14 Aug 2024 10:28:24 -0400 Subject: [PATCH 1335/1868] drm/amdgpu/sdma5.2: limit wptr workaround to sdma 5.2.1 The workaround seems to cause stability issues on other SDMA 5.2.x IPs. Fixes: a03ebf116303 ("drm/amdgpu/sdma5.2: Update wptr registers as well as doorbell") Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3556 Acked-by: Ruijing Dong Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c index d740255edf5af..bc9b240a3488e 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c @@ -225,14 +225,16 @@ static void sdma_v5_2_ring_set_wptr(struct amdgpu_ring *ring) DRM_DEBUG("calling WDOORBELL64(0x%08x, 0x%016llx)\n", ring->doorbell_index, ring->wptr << 2); WDOORBELL64(ring->doorbell_index, ring->wptr << 2); - /* SDMA seems to miss doorbells sometimes when powergating kicks in. - * Updating the wptr directly will wake it. This is only safe because - * we disallow gfxoff in begin_use() and then allow it again in end_use(). - */ - WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR), - lower_32_bits(ring->wptr << 2)); - WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI), - upper_32_bits(ring->wptr << 2)); + if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) == IP_VERSION(5, 2, 1)) { + /* SDMA seems to miss doorbells sometimes when powergating kicks in. + * Updating the wptr directly will wake it. This is only safe because + * we disallow gfxoff in begin_use() and then allow it again in end_use(). + */ + WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR), + lower_32_bits(ring->wptr << 2)); + WREG32(sdma_v5_2_get_reg_offset(adev, ring->me, mmSDMA0_GFX_RB_WPTR_HI), + upper_32_bits(ring->wptr << 2)); + } } else { DRM_DEBUG("Not using doorbell -- " "mmSDMA%i_GFX_RB_WPTR == 0x%08x " From 98a962b239e9cba8934b914bf593d13e06a9130f Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 14 Aug 2024 19:06:36 -0400 Subject: [PATCH 1336/1868] drm/amdgpu: handle enforce isolation on non-0 gfxhub Some chips have more than one gfxhub so check if we are a gfxhub rather than just gfxhub 0. Acked-by: Srinivasan Shanmugam Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c index b6a8bddada4c3..6608eeb61e5a0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c @@ -484,7 +484,7 @@ int amdgpu_vmid_grab(struct amdgpu_vm *vm, struct amdgpu_ring *ring, bool amdgpu_vmid_uses_reserved(struct amdgpu_vm *vm, unsigned int vmhub) { return vm->reserved_vmid[vmhub] || - (enforce_isolation && (vmhub == AMDGPU_GFXHUB(0))); + (enforce_isolation && AMDGPU_IS_GFXHUB(vmhub)); } int amdgpu_vmid_alloc_reserved(struct amdgpu_device *adev, From 61662218a69a6080cdad57477ae935798a1494ab Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Thu, 6 Jun 2024 13:12:40 +0530 Subject: [PATCH 1337/1868] drm/amdgpu: Add infrastructure for Cleaner Shader feature MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The cleaner shader is used by the CP firmware to clean LDS and GPRs between processes on the CUs. This adds an internal API for GFX IP code to allocate and initialize the cleaner shader. Cc: Christian König Cc: Alex Deucher Signed-off-by: Alex Deucher Signed-off-by: Srinivasan Shanmugam Suggested-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 35 +++++++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 14 ++++++++++ 2 files changed, 49 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c index 9be8cafdcecc9..4ed69fcfe9c14 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c @@ -1416,3 +1416,38 @@ void amdgpu_gfx_sysfs_fini(struct amdgpu_device *adev) device_remove_file(adev->dev, &dev_attr_current_compute_partition); device_remove_file(adev->dev, &dev_attr_available_compute_partition); } + +int amdgpu_gfx_cleaner_shader_sw_init(struct amdgpu_device *adev, + unsigned int cleaner_shader_size) +{ + if (!adev->gfx.enable_cleaner_shader) + return -EOPNOTSUPP; + + return amdgpu_bo_create_kernel(adev, cleaner_shader_size, PAGE_SIZE, + AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT, + &adev->gfx.cleaner_shader_obj, + &adev->gfx.cleaner_shader_gpu_addr, + (void **)&adev->gfx.cleaner_shader_cpu_ptr); +} + +void amdgpu_gfx_cleaner_shader_sw_fini(struct amdgpu_device *adev) +{ + if (!adev->gfx.enable_cleaner_shader) + return; + + amdgpu_bo_free_kernel(&adev->gfx.cleaner_shader_obj, + &adev->gfx.cleaner_shader_gpu_addr, + (void **)&adev->gfx.cleaner_shader_cpu_ptr); +} + +void amdgpu_gfx_cleaner_shader_init(struct amdgpu_device *adev, + unsigned int cleaner_shader_size, + const void *cleaner_shader_ptr) +{ + if (!adev->gfx.enable_cleaner_shader) + return; + + if (adev->gfx.cleaner_shader_cpu_ptr && cleaner_shader_ptr) + memcpy_toio(adev->gfx.cleaner_shader_cpu_ptr, cleaner_shader_ptr, + cleaner_shader_size); +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h index a6c35d8e5deb1..057c07bfc6745 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h @@ -457,6 +457,14 @@ struct amdgpu_gfx { uint32_t *ip_dump_gfx_queues; struct mutex reset_sem_mutex; + + /* cleaner shader */ + struct amdgpu_bo *cleaner_shader_obj; + unsigned int cleaner_shader_size; + u64 cleaner_shader_gpu_addr; + void *cleaner_shader_cpu_ptr; + const void *cleaner_shader_ptr; + bool enable_cleaner_shader; }; struct amdgpu_gfx_ras_reg_entry { @@ -558,6 +566,12 @@ void amdgpu_gfx_ras_error_func(struct amdgpu_device *adev, void *ras_error_status, void (*func)(struct amdgpu_device *adev, void *ras_error_status, int xcc_id)); +int amdgpu_gfx_cleaner_shader_sw_init(struct amdgpu_device *adev, + unsigned int cleaner_shader_size); +void amdgpu_gfx_cleaner_shader_sw_fini(struct amdgpu_device *adev); +void amdgpu_gfx_cleaner_shader_init(struct amdgpu_device *adev, + unsigned int cleaner_shader_size, + const void *cleaner_shader_ptr); static inline const char *amdgpu_gfx_compute_mode_desc(int mode) { From d50e4ce4059c28e5513d942ae1e3ac44f4daf1d2 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 12 Mar 2024 14:22:26 -0400 Subject: [PATCH 1338/1868] drm/amdgpu: Emit cleaner shader at end of IB submission MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This commit introduces the emission of a cleaner shader at the end of the IB submission process. This is achieved by adding a new function pointer, `emit_cleaner_shader`, to the `amdgpu_ring_funcs` structure. If the `emit_cleaner_shader` function is set in the ring functions, it is called during the VM flush process. The cleaner shader is only emitted if the `enable_cleaner_shader` flag is set in the `amdgpu_device` structure. This allows the cleaner shader emission to be controlled on a per-device basis. By emitting a cleaner shader at the end of the IB submission, we can ensure that the VM state is properly cleaned up after each submission. Cc: Christian König Cc: Alex Deucher Signed-off-by: Alex Deucher Signed-off-by: Srinivasan Shanmugam Suggested-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h index c7f15edeb3679..f93f510022018 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h @@ -236,6 +236,7 @@ struct amdgpu_ring_funcs { void (*patch_ce)(struct amdgpu_ring *ring, unsigned offset); void (*patch_de)(struct amdgpu_ring *ring, unsigned offset); int (*reset)(struct amdgpu_ring *ring, unsigned int vmid); + void (*emit_cleaner_shader)(struct amdgpu_ring *ring); }; struct amdgpu_ring { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index f55e7dd8e6c21..ec2cc3b620cd2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -696,6 +696,10 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, pasid_mapping_needed &= adev->gmc.gmc_funcs->emit_pasid_mapping && ring->funcs->emit_wreg; + if (adev->gfx.enable_cleaner_shader && + ring->funcs->emit_cleaner_shader) + ring->funcs->emit_cleaner_shader(ring); + if (!vm_flush_needed && !gds_switch_needed && !need_pipe_sync) return 0; @@ -757,6 +761,7 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, amdgpu_ring_emit_switch_buffer(ring); amdgpu_ring_emit_switch_buffer(ring); } + amdgpu_ring_ib_end(ring); return 0; } From 5c69312a25fcc718fb457c4a24e330ce55bb8295 Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Mon, 29 Jul 2024 21:35:26 +0530 Subject: [PATCH 1339/1868] drm/amdgpu: Make enforce_isolation setting per GPU MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This commit makes enforce_isolation setting to be per GPU and per partition by adding the enforce_isolation array to the adev structure. The adev variable is set based on the global enforce_isolation module parameter during device initialization. In amdgpu_ids.c, the adev->enforce_isolation value for the current GPU is used to determine whether to enforce isolation between graphics and compute processes on that GPU. In amdgpu_ids.c, the adev->enforce_isolation value for the current GPU and partition is used to determine whether to enforce isolation between graphics and compute processes on that GPU and partition. This allows the enforce_isolation setting to be controlled individually for each GPU and each partition, which is useful in a system with multiple GPUs and partitions where different isolation settings might be desired for different GPUs and partitions. v2: fix loop in amdgpu_vmid_mgr_init() (Alex) Cc: Christian König Cc: Alex Deucher Signed-off-by: Srinivasan Shanmugam Signed-off-by: Alex Deucher Suggested-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 +++++ drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c | 17 +++++++++++------ drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h | 3 ++- 5 files changed, 21 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index c28008f6f1e88..32319891648d7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1186,6 +1186,8 @@ struct amdgpu_device { bool debug_disable_soft_recovery; bool debug_use_vram_fw_buf; bool debug_enable_ras_aca; + + bool enforce_isolation[MAX_XCP]; }; static inline uint32_t amdgpu_ip_version(const struct amdgpu_device *adev, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index 0bf32f39b5ad6..ff953cf6f97e1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -1232,7 +1232,7 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p) struct drm_gpu_scheduler *sched = entity->rq->sched; struct amdgpu_ring *ring = to_amdgpu_ring(sched); - if (amdgpu_vmid_uses_reserved(vm, ring->vm_hub)) + if (amdgpu_vmid_uses_reserved(adev, vm, ring->vm_hub)) return -EINVAL; } } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 2743528ef2521..cde4575fc2e29 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -1926,6 +1926,8 @@ static int amdgpu_device_init_apu_flags(struct amdgpu_device *adev) */ static int amdgpu_device_check_arguments(struct amdgpu_device *adev) { + int i; + if (amdgpu_sched_jobs < 4) { dev_warn(adev->dev, "sched jobs (%d) must be at least 4\n", amdgpu_sched_jobs); @@ -1981,6 +1983,9 @@ static int amdgpu_device_check_arguments(struct amdgpu_device *adev) adev->firmware.load_type = amdgpu_ucode_get_load_type(adev, amdgpu_fw_load_type); amdgpu_direct_gma_size = min(amdgpu_direct_gma_size, 96); + for (i = 0; i < MAX_XCP; i++) + adev->enforce_isolation[i] = !!enforce_isolation; + return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c index 6608eeb61e5a0..92d27d32de41b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c @@ -424,7 +424,7 @@ int amdgpu_vmid_grab(struct amdgpu_vm *vm, struct amdgpu_ring *ring, if (r || !idle) goto error; - if (amdgpu_vmid_uses_reserved(vm, vmhub)) { + if (amdgpu_vmid_uses_reserved(adev, vm, vmhub)) { r = amdgpu_vmid_grab_reserved(vm, ring, job, &id, fence); if (r || !id) goto error; @@ -476,15 +476,19 @@ int amdgpu_vmid_grab(struct amdgpu_vm *vm, struct amdgpu_ring *ring, /* * amdgpu_vmid_uses_reserved - check if a VM will use a reserved VMID + * @adev: amdgpu_device pointer * @vm: the VM to check * @vmhub: the VMHUB which will be used * * Returns: True if the VM will use a reserved VMID. */ -bool amdgpu_vmid_uses_reserved(struct amdgpu_vm *vm, unsigned int vmhub) +bool amdgpu_vmid_uses_reserved(struct amdgpu_device *adev, + struct amdgpu_vm *vm, unsigned int vmhub) { return vm->reserved_vmid[vmhub] || - (enforce_isolation && AMDGPU_IS_GFXHUB(vmhub)); + (adev->enforce_isolation[(vm->root.bo->xcp_id != AMDGPU_XCP_NO_PARTITION) ? + vm->root.bo->xcp_id : 0] && + AMDGPU_IS_GFXHUB(vmhub)); } int amdgpu_vmid_alloc_reserved(struct amdgpu_device *adev, @@ -600,9 +604,10 @@ void amdgpu_vmid_mgr_init(struct amdgpu_device *adev) } } /* alloc a default reserved vmid to enforce isolation */ - if (enforce_isolation) - amdgpu_vmid_alloc_reserved(adev, AMDGPU_GFXHUB(0)); - + for (i = 0; i < (adev->xcp_mgr ? adev->xcp_mgr->num_xcps : 1); i++) { + if (adev->enforce_isolation[i]) + amdgpu_vmid_alloc_reserved(adev, AMDGPU_GFXHUB(i)); + } } /** diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h index 240fa67512602..4012fb2dd08a5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.h @@ -78,7 +78,8 @@ void amdgpu_pasid_free_delayed(struct dma_resv *resv, bool amdgpu_vmid_had_gpu_reset(struct amdgpu_device *adev, struct amdgpu_vmid *id); -bool amdgpu_vmid_uses_reserved(struct amdgpu_vm *vm, unsigned int vmhub); +bool amdgpu_vmid_uses_reserved(struct amdgpu_device *adev, + struct amdgpu_vm *vm, unsigned int vmhub); int amdgpu_vmid_alloc_reserved(struct amdgpu_device *adev, unsigned vmhub); void amdgpu_vmid_free_reserved(struct amdgpu_device *adev, From 7858f04e91df62794a4b053b41238356d15fa09c Mon Sep 17 00:00:00 2001 From: Victor Skvortsov Date: Fri, 2 Aug 2024 14:22:26 -0400 Subject: [PATCH 1340/1868] drm/amdgpu: abort KIQ waits when there is a pending reset Stop waiting for the KIQ to return back when there is a reset pending. It's quite likely that the KIQ will never response. Signed-off-by: Koenig Christian Suggested-by: Lazar Lijo Tested-by: Victor Skvortsov Signed-off-by: Victor Skvortsov Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 3 ++- drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h | 6 ++++++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c index 1e7743b3f77d9..d571b20fe11d4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c @@ -786,7 +786,8 @@ void amdgpu_gmc_fw_reg_write_reg_wait(struct amdgpu_device *adev, goto failed_kiq; might_sleep(); - while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) { + while (r < 1 && cnt++ < MAX_KIQ_REG_TRY && + !amdgpu_reset_pending(adev->reset_domain)) { msleep(MAX_KIQ_REG_BAILOUT_INTERVAL); r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h index 7882e6dc24432..929d372fc3635 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h @@ -152,6 +152,12 @@ static inline bool amdgpu_reset_domain_in_drain_mode(struct amdgpu_reset_domain return domain->drain; } +static inline bool amdgpu_reset_pending(struct amdgpu_reset_domain *domain) +{ + lockdep_assert_held(&domain->sem); + return rwsem_is_contended(&domain->sem); +} + void amdgpu_device_lock_reset_domain(struct amdgpu_reset_domain *reset_domain); void amdgpu_device_unlock_reset_domain(struct amdgpu_reset_domain *reset_domain); From 8ff51d79a2b052ecc09de31496fb9c976b5bfeba Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Wed, 20 Mar 2024 06:42:38 +0530 Subject: [PATCH 1341/1868] drm/amdgpu: Enforce isolation as part of the job MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch adds a new parameter 'enforce_isolation' to the amdgpu_job structure. This parameter is used to determine whether shader isolation should be enforced for a job. The enforce_isolation parameter is then stored in the amdgpu_job structure and used when flushing the VM. The enforce_isolation field of the amdgpu_job structure is set directly after the job is allocated This change allows more fine-grained control over shader isolation, making it possible to enforce isolation on a per-job basis rather than globally. This can be useful in scenarios where only certain jobs require isolation. Cc: Christian König Cc: Alex Deucher Signed-off-by: Alex Deucher Signed-off-by: Srinivasan Shanmugam Suggested-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_job.h | 3 +++ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 3 ++- 3 files changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c index ff953cf6f97e1..b7746fda17f20 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c @@ -301,6 +301,7 @@ static int amdgpu_cs_pass1(struct amdgpu_cs_parser *p, num_ibs[i], &p->jobs[i]); if (ret) goto free_all_kdata; + p->jobs[i]->enforce_isolation = p->adev->enforce_isolation[fpriv->xcp_id]; } p->gang_leader = p->jobs[p->gang_leader_idx]; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h index a963a25ddd620..ce6b9ba967fff 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h @@ -76,6 +76,9 @@ struct amdgpu_job { /* job_run_counter >= 1 means a resubmit job */ uint32_t job_run_counter; + /* enforce isolation */ + bool enforce_isolation; + uint32_t num_ibs; struct amdgpu_ib ibs[]; }; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index ec2cc3b620cd2..96aa2aaa3eca0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -697,7 +697,8 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, ring->funcs->emit_wreg; if (adev->gfx.enable_cleaner_shader && - ring->funcs->emit_cleaner_shader) + ring->funcs->emit_cleaner_shader && + job->enforce_isolation) ring->funcs->emit_cleaner_shader(ring); if (!vm_flush_needed && !gds_switch_needed && !need_pipe_sync) From 06db8fcf03b80768e400a5fcb9e784dd64dc2acb Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Mon, 27 May 2024 07:30:47 +0530 Subject: [PATCH 1342/1868] drm/amdgpu: Add enforce_isolation sysfs attribute MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This commit adds a new sysfs attribute 'enforce_isolation' to control the 'enforce_isolation' setting per GPU. The attribute can be read and written, and accepts values 0 (disabled) and 1 (enabled). When 'enforce_isolation' is enabled, reserved VMIDs are allocated for each ring. When it's disabled, the reserved VMIDs are freed. The set function locks a mutex before changing the 'enforce_isolation' flag and the VMIDs, and unlocks it afterwards. This ensures that these operations are atomic and prevents race conditions and other concurrency issues. Cc: Christian König Cc: Alex Deucher Signed-off-by: Srinivasan Shanmugam Suggested-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 101 +++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 2 + 4 files changed, 107 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 32319891648d7..2e80e98447b6d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1188,6 +1188,8 @@ struct amdgpu_device { bool debug_enable_ras_aca; bool enforce_isolation[MAX_XCP]; + /* Added this mutex for cleaner shader isolation between GFX and compute processes */ + struct mutex enforce_isolation_mutex; }; static inline uint32_t amdgpu_ip_version(const struct amdgpu_device *adev, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index cde4575fc2e29..481122c895cfb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -4082,6 +4082,8 @@ int amdgpu_device_init(struct amdgpu_device *adev, mutex_init(&adev->pm.stable_pstate_ctx_lock); mutex_init(&adev->benchmark_mutex); mutex_init(&adev->gfx.reset_sem_mutex); + /* Initialize the mutex for cleaner shader isolation between GFX and compute processes */ + mutex_init(&adev->enforce_isolation_mutex); amdgpu_device_init_apu_flags(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c index 4ed69fcfe9c14..2e35fc2577f9b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c @@ -1391,6 +1391,88 @@ static ssize_t amdgpu_gfx_get_available_compute_partition(struct device *dev, return sysfs_emit(buf, "%s\n", supported_partition); } +static ssize_t amdgpu_gfx_get_enforce_isolation(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + struct drm_device *ddev = dev_get_drvdata(dev); + struct amdgpu_device *adev = drm_to_adev(ddev); + int i; + ssize_t size = 0; + + if (adev->xcp_mgr) { + for (i = 0; i < adev->xcp_mgr->num_xcps; i++) { + size += sysfs_emit_at(buf, size, "%u", adev->enforce_isolation[i]); + if (i < (adev->xcp_mgr->num_xcps - 1)) + size += sysfs_emit_at(buf, size, " "); + } + buf[size++] = '\n'; + } else { + size = sysfs_emit_at(buf, 0, "%u\n", adev->enforce_isolation[0]); + } + + return size; +} + +static ssize_t amdgpu_gfx_set_enforce_isolation(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct drm_device *ddev = dev_get_drvdata(dev); + struct amdgpu_device *adev = drm_to_adev(ddev); + long partition_values[MAX_XCP] = {0}; + int ret, i, num_partitions; + const char *input_buf = buf; + + for (i = 0; i < (adev->xcp_mgr ? adev->xcp_mgr->num_xcps : 1); i++) { + ret = sscanf(input_buf, "%ld", &partition_values[i]); + if (ret <= 0) + break; + + /* Move the pointer to the next value in the string */ + input_buf = strchr(input_buf, ' '); + if (input_buf) { + input_buf++; + } else { + i++; + break; + } + } + num_partitions = i; + + if (adev->xcp_mgr && num_partitions != adev->xcp_mgr->num_xcps) + return -EINVAL; + + if (!adev->xcp_mgr && num_partitions != 1) + return -EINVAL; + + for (i = 0; i < num_partitions; i++) { + if (partition_values[i] != 0 && partition_values[i] != 1) + return -EINVAL; + } + + mutex_lock(&adev->enforce_isolation_mutex); + + for (i = 0; i < num_partitions; i++) { + if (adev->enforce_isolation[i] && !partition_values[i]) { + /* Going from enabled to disabled */ + amdgpu_vmid_free_reserved(adev, AMDGPU_GFXHUB(i)); + } else if (!adev->enforce_isolation[i] && partition_values[i]) { + /* Going from disabled to enabled */ + amdgpu_vmid_alloc_reserved(adev, AMDGPU_GFXHUB(i)); + } + adev->enforce_isolation[i] = partition_values[i]; + } + + mutex_unlock(&adev->enforce_isolation_mutex); + + return count; +} + +static DEVICE_ATTR(enforce_isolation, 0644, + amdgpu_gfx_get_enforce_isolation, + amdgpu_gfx_set_enforce_isolation); + static DEVICE_ATTR(current_compute_partition, 0644, amdgpu_gfx_get_current_compute_partition, amdgpu_gfx_set_compute_partition); @@ -1417,6 +1499,25 @@ void amdgpu_gfx_sysfs_fini(struct amdgpu_device *adev) device_remove_file(adev->dev, &dev_attr_available_compute_partition); } +int amdgpu_gfx_sysfs_isolation_shader_init(struct amdgpu_device *adev) +{ + int r; + + if (!amdgpu_sriov_vf(adev)) { + r = device_create_file(adev->dev, &dev_attr_enforce_isolation); + if (r) + return r; + } + + return 0; +} + +void amdgpu_gfx_sysfs_isolation_shader_fini(struct amdgpu_device *adev) +{ + if (!amdgpu_sriov_vf(adev)) + device_remove_file(adev->dev, &dev_attr_enforce_isolation); +} + int amdgpu_gfx_cleaner_shader_sw_init(struct amdgpu_device *adev, unsigned int cleaner_shader_size) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h index 057c07bfc6745..89cc9c1c2d52c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h @@ -572,6 +572,8 @@ void amdgpu_gfx_cleaner_shader_sw_fini(struct amdgpu_device *adev); void amdgpu_gfx_cleaner_shader_init(struct amdgpu_device *adev, unsigned int cleaner_shader_size, const void *cleaner_shader_ptr); +int amdgpu_gfx_sysfs_isolation_shader_init(struct amdgpu_device *adev); +void amdgpu_gfx_sysfs_isolation_shader_fini(struct amdgpu_device *adev); static inline const char *amdgpu_gfx_compute_mode_desc(int mode) { From 7e045e78e5260ceaadbe851ec8f1e6a5aa0e9159 Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Mon, 27 May 2024 07:38:21 +0530 Subject: [PATCH 1343/1868] drm/amdgpu: Add sysfs interface for running cleaner shader MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch adds a new sysfs interface for running the cleaner shader on AMD GPUs. The cleaner shader is used to clear GPU memory before it's reused, which can help prevent data leakage between different processes. The new sysfs file is write-only and is named `run_cleaner_shader`. Write the number of the partition to this file to trigger the cleaner shader on that partition. There is only one partition on GPUs which do not support partitioning. Changes made in this patch: - Added `amdgpu_set_run_cleaner_shader` function to handle writes to the `run_cleaner_shader` sysfs file. - Added `run_cleaner_shader` to the list of device attributes in `amdgpu_device_attrs`. - Updated `default_attr_update` to handle `run_cleaner_shader`. - Added `AMDGPU_DEVICE_ATTR_WO` macro to create write-only device attributes. v2: fix error handling (Alex) Cc: Christian König Cc: Alex Deucher Signed-off-by: Alex Deucher Signed-off-by: Srinivasan Shanmugam --- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 134 ++++++++++++++++++++++++ 1 file changed, 134 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c index 2e35fc2577f9b..76f77cf562afc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c @@ -24,10 +24,13 @@ */ #include +#include + #include "amdgpu.h" #include "amdgpu_gfx.h" #include "amdgpu_rlc.h" #include "amdgpu_ras.h" +#include "amdgpu_reset.h" #include "amdgpu_xcp.h" #include "amdgpu_xgmi.h" @@ -1391,6 +1394,129 @@ static ssize_t amdgpu_gfx_get_available_compute_partition(struct device *dev, return sysfs_emit(buf, "%s\n", supported_partition); } +static int amdgpu_gfx_run_cleaner_shader_job(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + long timeout = msecs_to_jiffies(1000); + struct dma_fence *f = NULL; + struct amdgpu_job *job; + struct amdgpu_ib *ib; + int i, r; + + r = amdgpu_job_alloc_with_ib(adev, NULL, NULL, + 64, AMDGPU_IB_POOL_DIRECT, + &job); + if (r) + goto err; + + job->enforce_isolation = true; + + ib = &job->ibs[0]; + for (i = 0; i <= ring->funcs->align_mask; ++i) + ib->ptr[i] = ring->funcs->nop; + ib->length_dw = ring->funcs->align_mask + 1; + + r = amdgpu_job_submit_direct(job, ring, &f); + if (r) + goto err_free; + + r = dma_fence_wait_timeout(f, false, timeout); + if (r == 0) + r = -ETIMEDOUT; + else if (r > 0) + r = 0; + + amdgpu_ib_free(adev, ib, f); + dma_fence_put(f); + + return 0; + +err_free: + amdgpu_job_free(job); + amdgpu_ib_free(adev, ib, f); +err: + return r; +} + +static int amdgpu_gfx_run_cleaner_shader(struct amdgpu_device *adev, int xcp_id) +{ + int num_xcc = NUM_XCC(adev->gfx.xcc_mask); + struct amdgpu_ring *ring; + int num_xcc_to_clear; + int i, r, xcc_id; + + if (adev->gfx.num_xcc_per_xcp) + num_xcc_to_clear = adev->gfx.num_xcc_per_xcp; + else + num_xcc_to_clear = 1; + + for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { + for (i = 0; i < adev->gfx.num_compute_rings; i++) { + ring = &adev->gfx.compute_ring[i + xcc_id * adev->gfx.num_compute_rings]; + if ((ring->xcp_id == xcp_id) && ring->sched.ready) { + r = amdgpu_gfx_run_cleaner_shader_job(ring); + if (r) + return r; + num_xcc_to_clear--; + break; + } + } + } + + if (num_xcc_to_clear) + return -ENOENT; + + return 0; +} + +static ssize_t amdgpu_gfx_set_run_cleaner_shader(struct device *dev, + struct device_attribute *attr, + const char *buf, + size_t count) +{ + struct drm_device *ddev = dev_get_drvdata(dev); + struct amdgpu_device *adev = drm_to_adev(ddev); + int ret; + long value; + + if (amdgpu_in_reset(adev)) + return -EPERM; + if (adev->in_suspend && !adev->in_runpm) + return -EPERM; + + ret = kstrtol(buf, 0, &value); + + if (ret) + return -EINVAL; + + if (value < 0) + return -EINVAL; + + if (adev->xcp_mgr) { + if (value >= adev->xcp_mgr->num_xcps) + return -EINVAL; + } else { + if (value > 1) + return -EINVAL; + } + + ret = pm_runtime_get_sync(ddev->dev); + if (ret < 0) { + pm_runtime_put_autosuspend(ddev->dev); + return ret; + } + + ret = amdgpu_gfx_run_cleaner_shader(adev, value); + + pm_runtime_mark_last_busy(ddev->dev); + pm_runtime_put_autosuspend(ddev->dev); + + if (ret) + return ret; + + return count; +} + static ssize_t amdgpu_gfx_get_enforce_isolation(struct device *dev, struct device_attribute *attr, char *buf) @@ -1469,6 +1595,9 @@ static ssize_t amdgpu_gfx_set_enforce_isolation(struct device *dev, return count; } +static DEVICE_ATTR(run_cleaner_shader, 0200, + NULL, amdgpu_gfx_set_run_cleaner_shader); + static DEVICE_ATTR(enforce_isolation, 0644, amdgpu_gfx_get_enforce_isolation, amdgpu_gfx_set_enforce_isolation); @@ -1509,6 +1638,10 @@ int amdgpu_gfx_sysfs_isolation_shader_init(struct amdgpu_device *adev) return r; } + r = device_create_file(adev->dev, &dev_attr_run_cleaner_shader); + if (r) + return r; + return 0; } @@ -1516,6 +1649,7 @@ void amdgpu_gfx_sysfs_isolation_shader_fini(struct amdgpu_device *adev) { if (!amdgpu_sriov_vf(adev)) device_remove_file(adev->dev, &dev_attr_enforce_isolation); + device_remove_file(adev->dev, &dev_attr_run_cleaner_shader); } int amdgpu_gfx_cleaner_shader_sw_init(struct amdgpu_device *adev, From 22f7f65d0b77a4ad480e4e5a403ea14c5408c141 Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Sun, 7 Jul 2024 08:54:04 +0530 Subject: [PATCH 1344/1868] drm/amdgpu: Add PACKET3_RUN_CLEANER_SHADER for cleaner shader execution MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This commit adds the PACKET3_RUN_CLEANER_SHADER definition. This packet is a command packet used to instruct the GPU to execute the cleaner shader. The cleaner shader is a piece of GPU code that is used to clear or initialize certain GPU resources, such as Local Data Share (LDS), Vector General Purpose Registers (VGPRs), and Scalar General Purpose Registers (SGPRs). Clearing these resources is important for ensuring data isolation between different workloads running on the GPU. The PACKET3_RUN_CLEANER_SHADER packet is used to trigger the execution of the cleaner shader on the GPU. The packet consists of a header followed by a RESERVED field, which is programmed to zero. When the GPU receives this packet, it fetches and executes the cleaner shader instructions from the location specified in the packet. The cleaner shader feature helps to enhances security and reliability by preventing data leaks between workloads. Cc: Christian König Cc: Alex Deucher Signed-off-by: Srinivasan Shanmugam Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/soc15d.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/soc15d.h b/drivers/gpu/drm/amd/amdgpu/soc15d.h index e74e1983da53a..b9cbeb389edc1 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15d.h +++ b/drivers/gpu/drm/amd/amdgpu/soc15d.h @@ -413,6 +413,10 @@ # define PACKET3_QUERY_STATUS_DOORBELL_OFFSET(x) ((x) << 2) # define PACKET3_QUERY_STATUS_ENG_SEL(x) ((x) << 25) +#define PACKET3_RUN_CLEANER_SHADER 0xD2 +/* 1. header + * 2. RESERVED [31:0] + */ #define VCE_CMD_NO_OP 0x00000000 #define VCE_CMD_END 0x00000001 From 139eab53f517a6548874130f0f622f9fba7d02c2 Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Mon, 29 Jul 2024 21:56:57 +0530 Subject: [PATCH 1345/1868] drm/amdgpu/gfx9: Implement cleaner shader support for GFX9 hardware MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The patch modifies the gfx_v9_0_kiq_set_resources function to write the cleaner shader's memory controller address to the ring buffer. It also adds a new function, gfx_v9_0_ring_emit_cleaner_shader, which emits the PACKET3_RUN_CLEANER_SHADER packet to the ring buffer. This patch adds support for the PACKET3_RUN_CLEANER_SHADER packet in the gfx_v9_0 module. This packet is used to emit the cleaner shader, which is used to clear GPU memory before it's reused, helping to prevent data leakage between different processes. Finally, the patch updates the ring function structures to include the new gfx_v9_0_ring_emit_cleaner_shader function. This allows the cleaner shader to be emitted as part of the ring's operations. Cc: Christian König Cc: Alex Deucher Signed-off-by: Srinivasan Shanmugam Suggested-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 45 ++++++++++++++++--- .../drm/amd/amdgpu/gfx_v9_0_cleaner_shader.h | 26 +++++++++++ 2 files changed, 66 insertions(+), 5 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdgpu/gfx_v9_0_cleaner_shader.h diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 4cc2df31ee489..2b3ed54f440f4 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -50,6 +50,7 @@ #include "amdgpu_ring_mux.h" #include "gfx_v9_4.h" #include "gfx_v9_0.h" +#include "gfx_v9_0_cleaner_shader.h" #include "gfx_v9_4_2.h" #include "asic_reg/pwr/pwr_10_0_offset.h" @@ -899,6 +900,12 @@ static void gfx_v9_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id); static void gfx_v9_0_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) { + struct amdgpu_device *adev = kiq_ring->adev; + u64 shader_mc_addr; + + /* Cleaner shader MC address */ + shader_mc_addr = adev->gfx.cleaner_shader_gpu_addr >> 8; + amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | @@ -908,8 +915,8 @@ static void gfx_v9_0_kiq_set_resources(struct amdgpu_ring *kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ - amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ - amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ + amdgpu_ring_write(kiq_ring, lower_32_bits(shader_mc_addr)); /* cleaner shader addr lo */ + amdgpu_ring_write(kiq_ring, upper_32_bits(shader_mc_addr)); /* cleaner shader addr hi */ amdgpu_ring_write(kiq_ring, 0); /* oac mask */ amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ } @@ -2211,6 +2218,12 @@ static int gfx_v9_0_sw_init(void *handle) break; } + switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { + default: + adev->gfx.enable_cleaner_shader = false; + break; + } + adev->gfx.mec.num_pipe_per_mec = 4; adev->gfx.mec.num_queue_per_pipe = 8; @@ -2380,6 +2393,10 @@ static int gfx_v9_0_sw_init(void *handle) gfx_v9_0_alloc_ip_dump(adev); + r = amdgpu_gfx_sysfs_isolation_shader_init(adev); + if (r) + return r; + return 0; } @@ -2415,6 +2432,8 @@ static int gfx_v9_0_sw_fini(void *handle) } gfx_v9_0_free_microcode(adev); + amdgpu_gfx_sysfs_isolation_shader_fini(adev); + kfree(adev->gfx.ip_dump_core); kfree(adev->gfx.ip_dump_compute_queues); @@ -3959,6 +3978,9 @@ static int gfx_v9_0_hw_init(void *handle) int r; struct amdgpu_device *adev = (struct amdgpu_device *)handle; + amdgpu_gfx_cleaner_shader_init(adev, adev->gfx.cleaner_shader_size, + adev->gfx.cleaner_shader_ptr); + if (!amdgpu_sriov_vf(adev)) gfx_v9_0_init_golden_registers(adev); @@ -7488,6 +7510,13 @@ static void gfx_v9_ip_dump(void *handle) } +static void gfx_v9_0_ring_emit_cleaner_shader(struct amdgpu_ring *ring) +{ + /* Emit the cleaner shader */ + amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0)); + amdgpu_ring_write(ring, 0); /* RESERVED field, programmed to zero */ +} + static const struct amd_ip_funcs gfx_v9_0_ip_funcs = { .name = "gfx_v9_0", .early_init = gfx_v9_0_early_init, @@ -7537,7 +7566,8 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = { 5 + /* HDP_INVL */ 8 + 8 + /* FENCE x2 */ 2 + /* SWITCH_BUFFER */ - 7, /* gfx_v9_0_emit_mem_sync */ + 7 + /* gfx_v9_0_emit_mem_sync */ + 2, /* gfx_v9_0_ring_emit_cleaner_shader */ .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_gfx */ .emit_ib = gfx_v9_0_ring_emit_ib_gfx, .emit_fence = gfx_v9_0_ring_emit_fence, @@ -7559,6 +7589,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = { .soft_recovery = gfx_v9_0_ring_soft_recovery, .emit_mem_sync = gfx_v9_0_emit_mem_sync, .reset = gfx_v9_0_reset_kgq, + .emit_cleaner_shader = gfx_v9_0_ring_emit_cleaner_shader, }; static const struct amdgpu_ring_funcs gfx_v9_0_sw_ring_funcs_gfx = { @@ -7591,7 +7622,8 @@ static const struct amdgpu_ring_funcs gfx_v9_0_sw_ring_funcs_gfx = { 5 + /* HDP_INVL */ 8 + 8 + /* FENCE x2 */ 2 + /* SWITCH_BUFFER */ - 7, /* gfx_v9_0_emit_mem_sync */ + 7 + /* gfx_v9_0_emit_mem_sync */ + 2, /* gfx_v9_0_ring_emit_cleaner_shader */ .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_gfx */ .emit_ib = gfx_v9_0_ring_emit_ib_gfx, .emit_fence = gfx_v9_0_ring_emit_fence, @@ -7615,6 +7647,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_sw_ring_funcs_gfx = { .patch_cntl = gfx_v9_0_ring_patch_cntl, .patch_de = gfx_v9_0_ring_patch_de_meta, .patch_ce = gfx_v9_0_ring_patch_ce_meta, + .emit_cleaner_shader = gfx_v9_0_ring_emit_cleaner_shader, }; static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = { @@ -7635,7 +7668,8 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = { 8 + 8 + 8 + /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */ 7 + /* gfx_v9_0_emit_mem_sync */ 5 + /* gfx_v9_0_emit_wave_limit for updating mmSPI_WCL_PIPE_PERCENT_GFX register */ - 15, /* for updating 3 mmSPI_WCL_PIPE_PERCENT_CS registers */ + 15 + /* for updating 3 mmSPI_WCL_PIPE_PERCENT_CS registers */ + 2, /* gfx_v9_0_ring_emit_cleaner_shader */ .emit_ib_size = 7, /* gfx_v9_0_ring_emit_ib_compute */ .emit_ib = gfx_v9_0_ring_emit_ib_compute, .emit_fence = gfx_v9_0_ring_emit_fence, @@ -7654,6 +7688,7 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = { .emit_mem_sync = gfx_v9_0_emit_mem_sync, .emit_wave_limit = gfx_v9_0_emit_wave_limit, .reset = gfx_v9_0_reset_kcq, + .emit_cleaner_shader = gfx_v9_0_ring_emit_cleaner_shader, }; static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = { diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0_cleaner_shader.h b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0_cleaner_shader.h new file mode 100644 index 0000000000000..36c0292b51106 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0_cleaner_shader.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ +/* Define the cleaner shader gfx_9_0 */ +static const u32 __maybe_unused gfx_9_0_cleaner_shader_hex[] = { + /* Add the cleaner shader code here */ +}; From 1a2bf1996cf55f894cd30146df33fa61aae10c28 Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Mon, 29 Jul 2024 22:12:02 +0530 Subject: [PATCH 1346/1868] drm/amdgpu/gfx9: Implement cleaner shader support for GFX9.4.3 hardware MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The patch modifies the gfx_v9_4_3_kiq_set_resources function to write the cleaner shader's memory controller address to the ring buffer. It also adds a new function, gfx_v9_4_3_ring_emit_cleaner_shader, which emits the PACKET3_RUN_CLEANER_SHADER packet to the ring buffer. This patch adds support for the PACKET3_RUN_CLEANER_SHADER packet in the gfx_v9_4_3 module. This packet is used to emit the cleaner shader, which is used to clear GPU memory before it's reused, helping to prevent data leakage between different processes. Finally, the patch updates the ring function structures to include the new gfx_v9_4_3_ring_emit_cleaner_shader function. This allows the cleaner shader to be emitted as part of the ring's operations. Cc: Christian König Cc: Alex Deucher Signed-off-by: Srinivasan Shanmugam Suggested-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 57 +++++++++++++++++-- .../amd/amdgpu/gfx_v9_4_3_cleaner_shader.h | 26 +++++++++ 2 files changed, 78 insertions(+), 5 deletions(-) create mode 100644 drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3_cleaner_shader.h diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index 619ff3ec2c863..28f4212a8db26 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -37,6 +37,7 @@ #include "gc/gc_9_4_3_sh_mask.h" #include "gfx_v9_4_3.h" +#include "gfx_v9_4_3_cleaner_shader.h" #include "amdgpu_xcp.h" #include "amdgpu_aca.h" @@ -169,6 +170,12 @@ static void gfx_v9_4_3_xcc_unset_safe_mode(struct amdgpu_device *adev, int xcc_i static void gfx_v9_4_3_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask) { + struct amdgpu_device *adev = kiq_ring->adev; + u64 shader_mc_addr; + + /* Cleaner shader MC address */ + shader_mc_addr = adev->gfx.cleaner_shader_gpu_addr >> 8; + amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6)); amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) | @@ -178,8 +185,8 @@ static void gfx_v9_4_3_kiq_set_resources(struct amdgpu_ring *kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */ amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */ - amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */ - amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */ + amdgpu_ring_write(kiq_ring, lower_32_bits(shader_mc_addr)); /* cleaner shader addr lo */ + amdgpu_ring_write(kiq_ring, upper_32_bits(shader_mc_addr)); /* cleaner shader addr hi */ amdgpu_ring_write(kiq_ring, 0); /* oac mask */ amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */ } @@ -1047,6 +1054,24 @@ static int gfx_v9_4_3_sw_init(void *handle) int i, j, k, r, ring_id, xcc_id, num_xcc; struct amdgpu_device *adev = (struct amdgpu_device *)handle; + switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { + case IP_VERSION(9, 4, 3): + adev->gfx.cleaner_shader_ptr = gfx_9_4_3_cleaner_shader_hex; + adev->gfx.cleaner_shader_size = sizeof(gfx_9_4_3_cleaner_shader_hex); + if (adev->gfx.mec_fw_version >= 153) { + adev->gfx.enable_cleaner_shader = true; + r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size); + if (r) { + adev->gfx.enable_cleaner_shader = false; + dev_err(adev->dev, "Failed to initialize cleaner shader\n"); + } + } + break; + default: + adev->gfx.enable_cleaner_shader = false; + break; + } + adev->gfx.mec.num_mec = 2; adev->gfx.mec.num_pipe_per_mec = 4; adev->gfx.mec.num_queue_per_pipe = 8; @@ -1140,12 +1165,19 @@ static int gfx_v9_4_3_sw_init(void *handle) return r; - if (!amdgpu_sriov_vf(adev)) + if (!amdgpu_sriov_vf(adev)) { r = amdgpu_gfx_sysfs_init(adev); + if (r) + return r; + } gfx_v9_4_3_alloc_ip_dump(adev); - return r; + r = amdgpu_gfx_sysfs_isolation_shader_init(adev); + if (r) + return r; + + return 0; } static int gfx_v9_4_3_sw_fini(void *handle) @@ -1163,11 +1195,14 @@ static int gfx_v9_4_3_sw_fini(void *handle) amdgpu_gfx_kiq_fini(adev, i); } + amdgpu_gfx_cleaner_shader_sw_fini(adev); + gfx_v9_4_3_mec_fini(adev); amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj); gfx_v9_4_3_free_microcode(adev); if (!amdgpu_sriov_vf(adev)) amdgpu_gfx_sysfs_fini(adev); + amdgpu_gfx_sysfs_isolation_shader_fini(adev); kfree(adev->gfx.ip_dump_core); kfree(adev->gfx.ip_dump_compute_queues); @@ -2308,6 +2343,9 @@ static int gfx_v9_4_3_hw_init(void *handle) int r; struct amdgpu_device *adev = (struct amdgpu_device *)handle; + amdgpu_gfx_cleaner_shader_init(adev, adev->gfx.cleaner_shader_size, + adev->gfx.cleaner_shader_ptr); + if (!amdgpu_sriov_vf(adev)) gfx_v9_4_3_init_golden_registers(adev); @@ -4565,6 +4603,13 @@ static void gfx_v9_4_3_ip_dump(void *handle) amdgpu_gfx_off_ctrl(adev, true); } +static void gfx_v9_4_3_ring_emit_cleaner_shader(struct amdgpu_ring *ring) +{ + /* Emit the cleaner shader */ + amdgpu_ring_write(ring, PACKET3(PACKET3_RUN_CLEANER_SHADER, 0)); + amdgpu_ring_write(ring, 0); /* RESERVED field, programmed to zero */ +} + static const struct amd_ip_funcs gfx_v9_4_3_ip_funcs = { .name = "gfx_v9_4_3", .early_init = gfx_v9_4_3_early_init, @@ -4604,7 +4649,8 @@ static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_compute = { 8 + 8 + 8 + /* gfx_v9_4_3_ring_emit_fence x3 for user fence, vm fence */ 7 + /* gfx_v9_4_3_emit_mem_sync */ 5 + /* gfx_v9_4_3_emit_wave_limit for updating regSPI_WCL_PIPE_PERCENT_GFX register */ - 15, /* for updating 3 regSPI_WCL_PIPE_PERCENT_CS registers */ + 15 + /* for updating 3 regSPI_WCL_PIPE_PERCENT_CS registers */ + 2, /* gfx_v9_4_3_ring_emit_cleaner_shader */ .emit_ib_size = 7, /* gfx_v9_4_3_ring_emit_ib_compute */ .emit_ib = gfx_v9_4_3_ring_emit_ib_compute, .emit_fence = gfx_v9_4_3_ring_emit_fence, @@ -4623,6 +4669,7 @@ static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_compute = { .emit_mem_sync = gfx_v9_4_3_emit_mem_sync, .emit_wave_limit = gfx_v9_4_3_emit_wave_limit, .reset = gfx_v9_4_3_reset_kcq, + .emit_cleaner_shader = gfx_v9_4_3_ring_emit_cleaner_shader, }; static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_kiq = { diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3_cleaner_shader.h b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3_cleaner_shader.h new file mode 100644 index 0000000000000..042944ac75dfb --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3_cleaner_shader.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2024 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +/* Define the cleaner shader gfx_9_4_3 */ +static const u32 gfx_9_4_3_cleaner_shader_hex[] = { +}; From dcf4825edff3f2ca935e15922b54829308bfccc1 Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Mon, 29 Jul 2024 22:14:41 +0530 Subject: [PATCH 1347/1868] drm/amdgpu/gfx9: Add cleaner shader for GFX9.4.3 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This commit adds the cleaner shader microcode for GFX9.4.3 GPUs. The cleaner shader is a piece of GPU code that is used to clear or initialize certain GPU resources, such as Local Data Share (LDS), Vector General Purpose Registers (VGPRs), and Scalar General Purpose Registers (SGPRs). Clearing these resources is important for ensuring data isolation between different workloads running on the GPU. Without the cleaner shader, residual data from a previous workload could potentially be accessed by a subsequent workload, leading to data leaks and incorrect computation results. The cleaner shader microcode is represented as an array of 32-bit words (`gfx_9_4_3_cleaner_shader_hex`). This array is the binary representation of the cleaner shader code, which is written in a low-level GPU instruction set. When the cleaner shader feature is enabled, the AMDGPU driver loads this array into a specific location in the GPU memory. The GPU then reads this memory location to fetch and execute the cleaner shader instructions. The cleaner shader is executed automatically by the GPU at the end of each workload, before the next workload starts. This ensures that all GPU resources are in a clean state before the start of each workload. This addition is part of the cleaner shader feature implementation. The cleaner shader feature helps improve GPU performance and resource utilization by cleaning up GPU resources after they are used. It also enhances security and reliability by preventing data leaks between workloads. v2: fix copyright date (Alex) Cc: Christian König Cc: Alex Deucher Signed-off-by: Srinivasan Shanmugam Signed-off-by: Alex Deucher --- .../amd/amdgpu/gfx_v9_4_3_cleaner_shader.asm | 153 ++++++++++++++++++ .../amd/amdgpu/gfx_v9_4_3_cleaner_shader.h | 38 +++++ 2 files changed, 191 insertions(+) create mode 100644 drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3_cleaner_shader.asm diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3_cleaner_shader.asm b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3_cleaner_shader.asm new file mode 100644 index 0000000000000..d5325ef80ab02 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3_cleaner_shader.asm @@ -0,0 +1,153 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2024 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +// This shader is to clean LDS, SGPRs and VGPRs. It is first 64 Dwords or 256 bytes of 192 Dwords cleaner shader. +//To turn this shader program on for complitaion change this to main and lower shader main to main_1 + +// MI300 : Clear SGPRs, VGPRs and LDS +// Uses two kernels launched separately: +// 1. Clean VGPRs, LDS, and lower SGPRs +// Launches one workgroup per CU, each workgroup with 4x wave64 per SIMD in the CU +// Waves are "wave64" and have 128 VGPRs each, which uses all 512 VGPRs per SIMD +// Waves in the workgroup share the 64KB of LDS +// Each wave clears SGPRs 0 - 95. Because there are 4 waves/SIMD, this is physical SGPRs 0-383 +// Each wave clears 128 VGPRs, so all 512 in the SIMD +// The first wave of the workgroup clears its 64KB of LDS +// The shader starts with "S_BARRIER" to ensure SPI has launched all waves of the workgroup +// before any wave in the workgroup could end. Without this, it is possible not all SGPRs get cleared. +// 2. Clean remaining SGPRs +// Launches a workgroup with 24 waves per workgroup, yielding 6 waves per SIMD in each CU +// Waves are allocating 96 SGPRs +// CP sets up SPI_RESOURCE_RESERVE_* registers to prevent these waves from allocating SGPRs 0-223. +// As such, these 6 waves per SIMD are allocated physical SGPRs 224-799 +// Barriers do not work for >16 waves per workgroup, so we cannot start with S_BARRIER +// Instead, the shader starts with an S_SETHALT 1. Once all waves are launched CP will send unhalt command +// The shader then clears all SGPRs allocated to it, cleaning out physical SGPRs 224-799 + +shader main + asic(MI300) + type(CS) + wave_size(64) +// Note: original source code from SQ team + +// (theorhetical fastest = ~512clks vgpr + 1536 lds + ~128 sgpr = 2176 clks) + + s_cmp_eq_u32 s0, 1 // Bit0 is set, sgpr0 is set then clear VGPRS and LDS as FW set COMPUTE_USER_DATA_3 + s_cbranch_scc0 label_0023 // Clean VGPRs and LDS if sgpr0 of wave is set, scc = (s3 == 1) + S_BARRIER + + s_movk_i32 m0, 0x0000 + s_mov_b32 s2, 0x00000078 // Loop 128/8=16 times (loop unrolled for performance) + // + // CLEAR VGPRs + // + s_set_gpr_idx_on s2, 0x8 // enable Dest VGPR indexing +label_0005: + v_mov_b32 v0, 0 + v_mov_b32 v1, 0 + v_mov_b32 v2, 0 + v_mov_b32 v3, 0 + v_mov_b32 v4, 0 + v_mov_b32 v5, 0 + v_mov_b32 v6, 0 + v_mov_b32 v7, 0 + s_sub_u32 s2, s2, 8 + s_set_gpr_idx_idx s2 + s_cbranch_scc0 label_0005 + s_set_gpr_idx_off + + // + // + + s_mov_b32 s2, 0x80000000 // Bit31 is first_wave + s_and_b32 s2, s2, s1 // sgpr0 has tg_size (first_wave) term as in ucode only COMPUTE_PGM_RSRC2.tg_size_en is set + s_cbranch_scc0 label_clean_sgpr_1 // Clean LDS if its first wave of ThreadGroup/WorkGroup + // CLEAR LDS + // + s_mov_b32 exec_lo, 0xffffffff + s_mov_b32 exec_hi, 0xffffffff + v_mbcnt_lo_u32_b32 v1, exec_hi, 0 // Set V1 to thread-ID (0..63) + v_mbcnt_hi_u32_b32 v1, exec_lo, v1 // Set V1 to thread-ID (0..63) + v_mul_u32_u24 v1, 0x00000008, v1 // * 8, so each thread is a double-dword address (8byte) + s_mov_b32 s2, 0x00000003f // 64 loop iteraions + s_mov_b32 m0, 0xffffffff + // Clear all of LDS space + // Each FirstWave of WorkGroup clears 64kbyte block + +label_001F: + ds_write2_b64 v1, v[2:3], v[2:3] offset1:32 + ds_write2_b64 v1, v[4:5], v[4:5] offset0:64 offset1:96 + v_add_co_u32 v1, vcc, 0x00000400, v1 + s_sub_u32 s2, s2, 1 + s_cbranch_scc0 label_001F + // + // CLEAR SGPRs + // +label_clean_sgpr_1: + s_mov_b32 m0, 0x0000005c // Loop 96/4=24 times (loop unrolled for performance) + s_nop 0 +label_sgpr_loop: + s_movreld_b32 s0, 0 + s_movreld_b32 s1, 0 + s_movreld_b32 s2, 0 + s_movreld_b32 s3, 0 + s_sub_u32 m0, m0, 4 + s_cbranch_scc0 label_sgpr_loop + + //clear vcc, flat scratch + s_mov_b32 flat_scratch_lo, 0 //clear flat scratch lo SGPR + s_mov_b32 flat_scratch_hi, 0 //clear flat scratch hi SGPR + s_mov_b64 vcc, 0 //clear vcc + s_mov_b64 ttmp0, 0 //Clear ttmp0 and ttmp1 + s_mov_b64 ttmp2, 0 //Clear ttmp2 and ttmp3 + s_mov_b64 ttmp4, 0 //Clear ttmp4 and ttmp5 + s_mov_b64 ttmp6, 0 //Clear ttmp6 and ttmp7 + s_mov_b64 ttmp8, 0 //Clear ttmp8 and ttmp9 + s_mov_b64 ttmp10, 0 //Clear ttmp10 and ttmp11 + s_mov_b64 ttmp12, 0 //Clear ttmp12 and ttmp13 + s_mov_b64 ttmp14, 0 //Clear ttmp14 and ttmp15 +s_endpgm + +label_0023: + + s_sethalt 1 + + s_mov_b32 m0, 0x0000005c // Loop 96/4=24 times (loop unrolled for performance) + s_nop 0 +label_sgpr_loop1: + + s_movreld_b32 s0, 0 + s_movreld_b32 s1, 0 + s_movreld_b32 s2, 0 + s_movreld_b32 s3, 0 + s_sub_u32 m0, m0, 4 + s_cbranch_scc0 label_sgpr_loop1 + + //clear vcc, flat scratch + s_mov_b32 flat_scratch_lo, 0 //clear flat scratch lo SGPR + s_mov_b32 flat_scratch_hi, 0 //clear flat scratch hi SGPR + s_mov_b64 vcc, 0xee //clear vcc + +s_endpgm +end + diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3_cleaner_shader.h b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3_cleaner_shader.h index 042944ac75dfb..69aa567c6c1d1 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3_cleaner_shader.h +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3_cleaner_shader.h @@ -23,4 +23,42 @@ /* Define the cleaner shader gfx_9_4_3 */ static const u32 gfx_9_4_3_cleaner_shader_hex[] = { + 0xbf068100, 0xbf84003b, + 0xbf8a0000, 0xb07c0000, + 0xbe8200ff, 0x00000078, + 0xbf110802, 0x7e000280, + 0x7e020280, 0x7e040280, + 0x7e060280, 0x7e080280, + 0x7e0a0280, 0x7e0c0280, + 0x7e0e0280, 0x80828802, + 0xbe803202, 0xbf84fff5, + 0xbf9c0000, 0xbe8200ff, + 0x80000000, 0x86020102, + 0xbf840011, 0xbefe00c1, + 0xbeff00c1, 0xd28c0001, + 0x0001007f, 0xd28d0001, + 0x0002027e, 0x10020288, + 0xbe8200bf, 0xbefc00c1, + 0xd89c2000, 0x00020201, + 0xd89c6040, 0x00040401, + 0x320202ff, 0x00000400, + 0x80828102, 0xbf84fff8, + 0xbefc00ff, 0x0000005c, + 0xbf800000, 0xbe802c80, + 0xbe812c80, 0xbe822c80, + 0xbe832c80, 0x80fc847c, + 0xbf84fffa, 0xbee60080, + 0xbee70080, 0xbeea0180, + 0xbeec0180, 0xbeee0180, + 0xbef00180, 0xbef20180, + 0xbef40180, 0xbef60180, + 0xbef80180, 0xbefa0180, + 0xbf810000, 0xbf8d0001, + 0xbefc00ff, 0x0000005c, + 0xbf800000, 0xbe802c80, + 0xbe812c80, 0xbe822c80, + 0xbe832c80, 0x80fc847c, + 0xbf84fffa, 0xbee60080, + 0xbee70080, 0xbeea01ff, + 0x000000ee, 0xbf810000, }; From eb6ee4e2dd57ebb9163c293265969418c55e1327 Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Mon, 29 Jul 2024 22:18:45 +0530 Subject: [PATCH 1348/1868] drm/amdgpu/gfx9: Add cleaner shader support for GFX9.4.4 hardware MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This commit extends the cleaner shader feature to support GFX9.4.4 hardware. The cleaner shader feature is used to clear or initialize certain GPU resources, such as Local Data Share (LDS), Vector General Purpose Registers (VGPRs), and Scalar General Purpose Registers (SGPRs). This operation needs to be performed in isolation, while no other tasks should be running on the GPU at the same time. Previously, the cleaner shader feature was implemented for GFX9.4.3 hardware. This commit adds support for GFX9.4.4 hardware by allowing the cleaner shader to be used with this hardware version. Cc: Christian König Cc: Alex Deucher Signed-off-by: Srinivasan Shanmugam Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index 28f4212a8db26..fa6752585a729 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -1056,6 +1056,7 @@ static int gfx_v9_4_3_sw_init(void *handle) switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { case IP_VERSION(9, 4, 3): + case IP_VERSION(9, 4, 4): adev->gfx.cleaner_shader_ptr = gfx_9_4_3_cleaner_shader_hex; adev->gfx.cleaner_shader_size = sizeof(gfx_9_4_3_cleaner_shader_hex); if (adev->gfx.mec_fw_version >= 153) { From f9cef9fbabc09ecbb438a01be188890019604081 Mon Sep 17 00:00:00 2001 From: Amber Lin Date: Mon, 29 Jul 2024 14:22:30 -0400 Subject: [PATCH 1349/1868] drm/amdkfd: APIs to stop/start KFD scheduling Provide amdgpu_amdkfd_stop_sched() for amdgpu to stop KFD scheduling compute work on HIQ. amdgpu_amdkfd_start_sched() resumes the scheduling. When amdgpu_amdkfd_stop_sched is called, KFD will unmap queues from runlist. If users send ioctls to KFD to create queues, they'll be added but those queues won't be mapped to runlist (so not scheduled) until amdgpu_amdkfd_start_sched is called. v2: fix build (Alex) Signed-off-by: Amber Lin Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 18 ++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 14 +++++ drivers/gpu/drm/amd/amdkfd/kfd_device.c | 39 +++++++++++++ .../drm/amd/amdkfd/kfd_device_queue_manager.c | 58 ++++++++++++++++++- .../drm/amd/amdkfd/kfd_device_queue_manager.h | 9 +++ 5 files changed, 137 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c index 71e472d810f64..99db574389e88 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c @@ -899,3 +899,21 @@ int amdgpu_amdkfd_unmap_hiq(struct amdgpu_device *adev, u32 doorbell_off, return r; } + +/* Stop scheduling on KFD */ +int amdgpu_amdkfd_stop_sched(struct amdgpu_device *adev, uint32_t node_id) +{ + if (!adev->kfd.init_complete) + return 0; + + return kgd2kfd_stop_sched(adev->kfd.dev, node_id); +} + +/* Start scheduling on KFD */ +int amdgpu_amdkfd_start_sched(struct amdgpu_device *adev, uint32_t node_id) +{ + if (!adev->kfd.init_complete) + return 0; + + return kgd2kfd_start_sched(adev->kfd.dev, node_id); +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index c5efe667f7ccf..6f82764c9606e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -280,6 +280,8 @@ int amdgpu_amdkfd_send_close_event_drain_irq(struct amdgpu_device *adev, uint32_t *payload); int amdgpu_amdkfd_unmap_hiq(struct amdgpu_device *adev, u32 doorbell_off, u32 inst); +int amdgpu_amdkfd_start_sched(struct amdgpu_device *adev, uint32_t node_id); +int amdgpu_amdkfd_stop_sched(struct amdgpu_device *adev, uint32_t node_id); /* Read user wptr from a specified user address space with page fault * disabled. The memory must be pinned and mapped to the hardware when @@ -499,6 +501,8 @@ void kgd2kfd_set_sram_ecc_flag(struct kfd_dev *kfd); void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask); int kgd2kfd_check_and_lock_kfd(void); void kgd2kfd_unlock_kfd(void); +int kgd2kfd_start_sched(struct kfd_dev *kfd, uint32_t node_id); +int kgd2kfd_stop_sched(struct kfd_dev *kfd, uint32_t node_id); #else static inline int kgd2kfd_init(void) { @@ -569,5 +573,15 @@ static inline int kgd2kfd_check_and_lock_kfd(void) static inline void kgd2kfd_unlock_kfd(void) { } + +static inline int kgd2kfd_start_sched(struct kfd_dev *kfd, uint32_t node_id) +{ + return 0; +} + +static inline int kgd2kfd_stop_sched(struct kfd_dev *kfd, uint32_t node_id) +{ + return 0; +} #endif #endif /* AMDGPU_AMDKFD_H_INCLUDED */ diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index b10417a9df17d..b587dd8dc8988 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -1485,6 +1485,45 @@ void kgd2kfd_unlock_kfd(void) mutex_unlock(&kfd_processes_mutex); } +int kgd2kfd_start_sched(struct kfd_dev *kfd, uint32_t node_id) +{ + struct kfd_node *node; + int ret; + + if (!kfd->init_complete) + return 0; + + if (node_id >= kfd->num_nodes) { + dev_warn(kfd->adev->dev, "Invalid node ID: %u exceeds %u\n", + node_id, kfd->num_nodes - 1); + return -EINVAL; + } + node = kfd->nodes[node_id]; + + ret = node->dqm->ops.unhalt(node->dqm); + if (ret) + dev_err(kfd_device, "Error in starting scheduler\n"); + + return ret; +} + +int kgd2kfd_stop_sched(struct kfd_dev *kfd, uint32_t node_id) +{ + struct kfd_node *node; + + if (!kfd->init_complete) + return 0; + + if (node_id >= kfd->num_nodes) { + dev_warn(kfd->adev->dev, "Invalid node ID: %u exceeds %u\n", + node_id, kfd->num_nodes - 1); + return -EINVAL; + } + + node = kfd->nodes[node_id]; + return node->dqm->ops.halt(node->dqm); +} + #if defined(CONFIG_DEBUG_FS) /* This function will send a package to HIQ to hang the HWS diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index 81bfa6eb7e093..8f32147601871 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -1706,6 +1706,60 @@ static int initialize_cpsch(struct device_queue_manager *dqm) return 0; } +/* halt_cpsch: + * Unmap queues so the schedule doesn't continue remaining jobs in the queue. + * Then set dqm->sched_halt so queues don't map to runlist until unhalt_cpsch + * is called. + */ +static int halt_cpsch(struct device_queue_manager *dqm) +{ + int ret = 0; + + dqm_lock(dqm); + if (!dqm->sched_running) { + dqm_unlock(dqm); + return 0; + } + + WARN_ONCE(dqm->sched_halt, "Scheduling is already on halt\n"); + + if (!dqm->is_hws_hang) { + if (!dqm->dev->kfd->shared_resources.enable_mes) + ret = unmap_queues_cpsch(dqm, + KFD_UNMAP_QUEUES_FILTER_ALL_QUEUES, 0, + USE_DEFAULT_GRACE_PERIOD, false); + else + ret = remove_all_queues_mes(dqm); + } + dqm->sched_halt = true; + dqm_unlock(dqm); + + return ret; +} + +/* unhalt_cpsch + * Unset dqm->sched_halt and map queues back to runlist + */ +static int unhalt_cpsch(struct device_queue_manager *dqm) +{ + int ret = 0; + + dqm_lock(dqm); + if (!dqm->sched_running || !dqm->sched_halt) { + WARN_ONCE(!dqm->sched_halt, "Scheduling is not on halt.\n"); + dqm_unlock(dqm); + return 0; + } + dqm->sched_halt = false; + if (!dqm->dev->kfd->shared_resources.enable_mes) + ret = execute_queues_cpsch(dqm, + KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, + 0, USE_DEFAULT_GRACE_PERIOD); + dqm_unlock(dqm); + + return ret; +} + static int start_cpsch(struct device_queue_manager *dqm) { struct device *dev = dqm->dev->adev->dev; @@ -2011,7 +2065,7 @@ static int map_queues_cpsch(struct device_queue_manager *dqm) struct device *dev = dqm->dev->adev->dev; int retval; - if (!dqm->sched_running) + if (!dqm->sched_running || dqm->sched_halt) return 0; if (dqm->active_queue_count <= 0 || dqm->processes_count <= 0) return 0; @@ -2753,6 +2807,8 @@ struct device_queue_manager *device_queue_manager_init(struct kfd_node *dev) dqm->ops.initialize = initialize_cpsch; dqm->ops.start = start_cpsch; dqm->ops.stop = stop_cpsch; + dqm->ops.halt = halt_cpsch; + dqm->ops.unhalt = unhalt_cpsch; dqm->ops.destroy_queue = destroy_queue_cpsch; dqm->ops.update_queue = update_queue; dqm->ops.register_process = register_process; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h index 710c9a53161eb..596e8058cd855 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h @@ -106,6 +106,12 @@ union GRBM_GFX_INDEX_BITS { * @uninitialize: Destroys all the device queue manager resources allocated in * initialize routine. * + * @halt: This routine unmaps queues from runlist and set halt status to true + * so no more queues will be mapped to runlist until unhalt. + * + * @unhalt: This routine unset halt status to flase and maps queues back to + * runlist. + * * @create_kernel_queue: Creates kernel queue. Used for debug queue. * * @destroy_kernel_queue: Destroys kernel queue. Used for debug queue. @@ -153,6 +159,8 @@ struct device_queue_manager_ops { int (*start)(struct device_queue_manager *dqm); int (*stop)(struct device_queue_manager *dqm); void (*uninitialize)(struct device_queue_manager *dqm); + int (*halt)(struct device_queue_manager *dqm); + int (*unhalt)(struct device_queue_manager *dqm); int (*create_kernel_queue)(struct device_queue_manager *dqm, struct kernel_queue *kq, struct qcm_process_device *qpd); @@ -264,6 +272,7 @@ struct device_queue_manager { struct work_struct hw_exception_work; struct kfd_mem_obj hiq_sdma_mqd; bool sched_running; + bool sched_halt; /* used for GFX 9.4.3 only */ uint32_t current_logical_xcc_start; From b785e55539fe134ae1c1484e822c781c70faf4d1 Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Thu, 6 Jun 2024 13:28:02 +0530 Subject: [PATCH 1350/1868] drm/amdgpu: Implement Enforce Isolation Handler for KGD/KFD serialization MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This commit introduces the Enforce Isolation Handler designed to enforce shader isolation on AMD GPUs, which helps to prevent data leakage between different processes. The handler counts the number of emitted fences for each GFX and compute ring. If there are any fences, it schedules the `enforce_isolation_work` to be run after a delay of `GFX_SLICE_PERIOD`. If there are no fences, it signals the Kernel Fusion Driver (KFD) to resume the runqueue. The function is synchronized using the `enforce_isolation_mutex`. This commit also introduces a reference count mechanism (kfd_sch_req_count) to keep track of the number of requests to enable the KFD scheduler. When a request to enable the KFD scheduler is made, the reference count is decremented. When the reference count reaches zero, a delayed work is scheduled to enforce isolation after a delay of GFX_SLICE_PERIOD. When a request to disable the KFD scheduler is made, the function first checks if the reference count is zero. If it is, it cancels the delayed work for enforcing isolation and checks if the KFD scheduler is active. If the KFD scheduler is active, it sends a request to stop the KFD scheduler and sets the KFD scheduler state to inactive. Then, it increments the reference count. The function is synchronized using the kfd_sch_mutex to ensure that the KFD scheduler state and reference count are updated atomically. Cc: Christian König Cc: Alex Deucher Signed-off-by: Alex Deucher Signed-off-by: Srinivasan Shanmugam Suggested-by: Christian König Suggested-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 16 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 167 +++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 15 ++ 4 files changed, 200 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 2e80e98447b6d..911d24bc5cdf3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -119,6 +119,8 @@ #define MAX_GPU_INSTANCE 64 +#define GFX_SLICE_PERIOD msecs_to_jiffies(250) + struct amdgpu_gpu_instance { struct amdgpu_device *adev; int mgpu_fan_enabled; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 481122c895cfb..65dff728b7a08 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -4084,6 +4084,7 @@ int amdgpu_device_init(struct amdgpu_device *adev, mutex_init(&adev->gfx.reset_sem_mutex); /* Initialize the mutex for cleaner shader isolation between GFX and compute processes */ mutex_init(&adev->enforce_isolation_mutex); + mutex_init(&adev->gfx.kfd_sch_mutex); amdgpu_device_init_apu_flags(adev); @@ -4115,6 +4116,21 @@ int amdgpu_device_init(struct amdgpu_device *adev, amdgpu_device_delayed_init_work_handler); INIT_DELAYED_WORK(&adev->gfx.gfx_off_delay_work, amdgpu_device_delay_enable_gfx_off); + /* + * Initialize the enforce_isolation work structures for each XCP + * partition. This work handler is responsible for enforcing shader + * isolation on AMD GPUs. It counts the number of emitted fences for + * each GFX and compute ring. If there are any fences, it schedules + * the `enforce_isolation_work` to be run after a delay. If there are + * no fences, it signals the Kernel Fusion Driver (KFD) to resume the + * runqueue. + */ + for (i = 0; i < MAX_XCP; i++) { + INIT_DELAYED_WORK(&adev->gfx.enforce_isolation[i].work, + amdgpu_gfx_enforce_isolation_handler); + adev->gfx.enforce_isolation[i].adev = adev; + adev->gfx.enforce_isolation[i].xcp_id = i; + } INIT_WORK(&adev->xgmi_reset_work, amdgpu_device_xgmi_reset_func); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c index 76f77cf562afc..b4efeef848de7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c @@ -1686,3 +1686,170 @@ void amdgpu_gfx_cleaner_shader_init(struct amdgpu_device *adev, memcpy_toio(adev->gfx.cleaner_shader_cpu_ptr, cleaner_shader_ptr, cleaner_shader_size); } + +/** + * amdgpu_gfx_kfd_sch_ctrl - Control the KFD scheduler from the KGD (Graphics Driver) + * @adev: amdgpu_device pointer + * @idx: Index of the scheduler to control + * @enable: Whether to enable or disable the KFD scheduler + * + * This function is used to control the KFD (Kernel Fusion Driver) scheduler + * from the KGD. It is part of the cleaner shader feature. This function plays + * a key role in enforcing process isolation on the GPU. + * + * The function uses a reference count mechanism (kfd_sch_req_count) to keep + * track of the number of requests to enable the KFD scheduler. When a request + * to enable the KFD scheduler is made, the reference count is decremented. + * When the reference count reaches zero, a delayed work is scheduled to + * enforce isolation after a delay of GFX_SLICE_PERIOD. + * + * When a request to disable the KFD scheduler is made, the function first + * checks if the reference count is zero. If it is, it cancels the delayed work + * for enforcing isolation and checks if the KFD scheduler is active. If the + * KFD scheduler is active, it sends a request to stop the KFD scheduler and + * sets the KFD scheduler state to inactive. Then, it increments the reference + * count. + * + * The function is synchronized using the kfd_sch_mutex to ensure that the KFD + * scheduler state and reference count are updated atomically. + * + * Note: If the reference count is already zero when a request to enable the + * KFD scheduler is made, it means there's an imbalance bug somewhere. The + * function triggers a warning in this case. + */ +static void amdgpu_gfx_kfd_sch_ctrl(struct amdgpu_device *adev, u32 idx, + bool enable) +{ + mutex_lock(&adev->gfx.kfd_sch_mutex); + + if (enable) { + /* If the count is already 0, it means there's an imbalance bug somewhere. + * Note that the bug may be in a different caller than the one which triggers the + * WARN_ON_ONCE. + */ + if (WARN_ON_ONCE(adev->gfx.kfd_sch_req_count[idx] == 0)) { + dev_err(adev->dev, "Attempted to enable KFD scheduler when reference count is already zero\n"); + goto unlock; + } + + adev->gfx.kfd_sch_req_count[idx]--; + + if (adev->gfx.kfd_sch_req_count[idx] == 0 && + adev->gfx.kfd_sch_inactive[idx]) { + schedule_delayed_work(&adev->gfx.enforce_isolation[idx].work, + GFX_SLICE_PERIOD); + } + } else { + if (adev->gfx.kfd_sch_req_count[idx] == 0) { + cancel_delayed_work_sync(&adev->gfx.enforce_isolation[idx].work); + if (!adev->gfx.kfd_sch_inactive[idx]) { + amdgpu_amdkfd_stop_sched(adev, idx); + adev->gfx.kfd_sch_inactive[idx] = true; + } + } + + adev->gfx.kfd_sch_req_count[idx]++; + } + +unlock: + mutex_unlock(&adev->gfx.kfd_sch_mutex); +} + +/** + * amdgpu_gfx_enforce_isolation_handler - work handler for enforcing shader isolation + * + * @work: work_struct. + * + * This function is the work handler for enforcing shader isolation on AMD GPUs. + * It counts the number of emitted fences for each GFX and compute ring. If there + * are any fences, it schedules the `enforce_isolation_work` to be run after a + * delay of `GFX_SLICE_PERIOD`. If there are no fences, it signals the Kernel Fusion + * Driver (KFD) to resume the runqueue. The function is synchronized using the + * `enforce_isolation_mutex`. + */ +void amdgpu_gfx_enforce_isolation_handler(struct work_struct *work) +{ + struct amdgpu_isolation_work *isolation_work = + container_of(work, struct amdgpu_isolation_work, work.work); + struct amdgpu_device *adev = isolation_work->adev; + u32 i, idx, fences = 0; + + if (isolation_work->xcp_id == AMDGPU_XCP_NO_PARTITION) + idx = 0; + else + idx = isolation_work->xcp_id; + + if (idx >= MAX_XCP) + return; + + mutex_lock(&adev->enforce_isolation_mutex); + for (i = 0; i < AMDGPU_MAX_GFX_RINGS; ++i) { + if (isolation_work->xcp_id == adev->gfx.gfx_ring[i].xcp_id) + fences += amdgpu_fence_count_emitted(&adev->gfx.gfx_ring[i]); + } + for (i = 0; i < (AMDGPU_MAX_COMPUTE_RINGS * AMDGPU_MAX_GC_INSTANCES); ++i) { + if (isolation_work->xcp_id == adev->gfx.compute_ring[i].xcp_id) + fences += amdgpu_fence_count_emitted(&adev->gfx.compute_ring[i]); + } + if (fences) { + schedule_delayed_work(&adev->gfx.enforce_isolation[idx].work, + GFX_SLICE_PERIOD); + } else { + /* Tell KFD to resume the runqueue */ + if (adev->kfd.init_complete) { + WARN_ON_ONCE(!adev->gfx.kfd_sch_inactive[idx]); + WARN_ON_ONCE(adev->gfx.kfd_sch_req_count[idx]); + amdgpu_amdkfd_start_sched(adev, idx); + adev->gfx.kfd_sch_inactive[idx] = false; + } + } + mutex_unlock(&adev->enforce_isolation_mutex); +} + +void amdgpu_gfx_enforce_isolation_ring_begin_use(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + u32 idx; + + if (!adev->gfx.enable_cleaner_shader) + return; + + if (ring->xcp_id == AMDGPU_XCP_NO_PARTITION) + idx = 0; + else + idx = ring->xcp_id; + + if (idx >= MAX_XCP) + return; + + mutex_lock(&adev->enforce_isolation_mutex); + if (adev->enforce_isolation[idx]) { + if (adev->kfd.init_complete) + amdgpu_gfx_kfd_sch_ctrl(adev, idx, false); + } + mutex_unlock(&adev->enforce_isolation_mutex); +} + +void amdgpu_gfx_enforce_isolation_ring_end_use(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + u32 idx; + + if (!adev->gfx.enable_cleaner_shader) + return; + + if (ring->xcp_id == AMDGPU_XCP_NO_PARTITION) + idx = 0; + else + idx = ring->xcp_id; + + if (idx >= MAX_XCP) + return; + + mutex_lock(&adev->enforce_isolation_mutex); + if (adev->enforce_isolation[idx]) { + if (adev->kfd.init_complete) + amdgpu_gfx_kfd_sch_ctrl(adev, idx, true); + } + mutex_unlock(&adev->enforce_isolation_mutex); +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h index 89cc9c1c2d52c..3f3f50c1f6360 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h @@ -34,6 +34,7 @@ #include "soc15.h" #include "amdgpu_ras.h" #include "amdgpu_ring_mux.h" +#include "amdgpu_xcp.h" /* GFX current status */ #define AMDGPU_GFX_NORMAL_MODE 0x00000000L @@ -352,6 +353,12 @@ struct amdgpu_me { DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_GFX_QUEUES); }; +struct amdgpu_isolation_work { + struct amdgpu_device *adev; + u32 xcp_id; + struct delayed_work work; +}; + struct amdgpu_gfx { struct mutex gpu_clock_mutex; struct amdgpu_gfx_config config; @@ -465,6 +472,11 @@ struct amdgpu_gfx { void *cleaner_shader_cpu_ptr; const void *cleaner_shader_ptr; bool enable_cleaner_shader; + struct amdgpu_isolation_work enforce_isolation[MAX_XCP]; + /* Mutex for synchronizing KFD scheduler operations */ + struct mutex kfd_sch_mutex; + u64 kfd_sch_req_count[MAX_XCP]; + bool kfd_sch_inactive[MAX_XCP]; }; struct amdgpu_gfx_ras_reg_entry { @@ -574,6 +586,9 @@ void amdgpu_gfx_cleaner_shader_init(struct amdgpu_device *adev, const void *cleaner_shader_ptr); int amdgpu_gfx_sysfs_isolation_shader_init(struct amdgpu_device *adev); void amdgpu_gfx_sysfs_isolation_shader_fini(struct amdgpu_device *adev); +void amdgpu_gfx_enforce_isolation_handler(struct work_struct *work); +void amdgpu_gfx_enforce_isolation_ring_begin_use(struct amdgpu_ring *ring); +void amdgpu_gfx_enforce_isolation_ring_end_use(struct amdgpu_ring *ring); static inline const char *amdgpu_gfx_compute_mode_desc(int mode) { From 11f4469e5a5f7a47ff32a0d0b4b76f30b8d5ba1c Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Thu, 18 Jul 2024 18:22:35 +0530 Subject: [PATCH 1351/1868] drm/amdgpu/gfx9: Apply Isolation Enforcement to GFX & Compute rings MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This commit applies isolation enforcement to the GFX and Compute rings in the gfx_v9_0 module. The commit sets `amdgpu_gfx_enforce_isolation_ring_begin_use` and `amdgpu_gfx_enforce_isolation_ring_end_use` as the functions to be called when a ring begins and ends its use, respectively. `amdgpu_gfx_enforce_isolation_ring_begin_use` is called when a ring begins its use. This function cancels any scheduled `enforce_isolation_work` and, if necessary, signals the Kernel Fusion Driver (KFD) to stop the runqueue. `amdgpu_gfx_enforce_isolation_ring_end_use` is called when a ring ends its use. This function schedules `enforce_isolation_work` to be run after a delay. These functions are part of the Enforce Isolation Handler, which enforces shader isolation on AMD GPUs to prevent data leakage between different processes. Cc: Christian König Cc: Alex Deucher Signed-off-by: Srinivasan Shanmugam Signed-off-by: Alex Deucher Suggested-by: Christian König --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 2b3ed54f440f4..7b78e448adf9b 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -7590,6 +7590,8 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = { .emit_mem_sync = gfx_v9_0_emit_mem_sync, .reset = gfx_v9_0_reset_kgq, .emit_cleaner_shader = gfx_v9_0_ring_emit_cleaner_shader, + .begin_use = amdgpu_gfx_enforce_isolation_ring_begin_use, + .end_use = amdgpu_gfx_enforce_isolation_ring_end_use, }; static const struct amdgpu_ring_funcs gfx_v9_0_sw_ring_funcs_gfx = { @@ -7648,6 +7650,8 @@ static const struct amdgpu_ring_funcs gfx_v9_0_sw_ring_funcs_gfx = { .patch_de = gfx_v9_0_ring_patch_de_meta, .patch_ce = gfx_v9_0_ring_patch_ce_meta, .emit_cleaner_shader = gfx_v9_0_ring_emit_cleaner_shader, + .begin_use = amdgpu_gfx_enforce_isolation_ring_begin_use, + .end_use = amdgpu_gfx_enforce_isolation_ring_end_use, }; static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = { @@ -7689,6 +7693,8 @@ static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = { .emit_wave_limit = gfx_v9_0_emit_wave_limit, .reset = gfx_v9_0_reset_kcq, .emit_cleaner_shader = gfx_v9_0_ring_emit_cleaner_shader, + .begin_use = amdgpu_gfx_enforce_isolation_ring_begin_use, + .end_use = amdgpu_gfx_enforce_isolation_ring_end_use, }; static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = { From f328d7a2c6009c0d663c22a04e05b1159ba27f01 Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Tue, 14 May 2024 23:55:20 +0530 Subject: [PATCH 1352/1868] drm/amdgpu/gfx_v9_4_3: Apply Isolation Enforcement to GFX & Compute rings MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This commit applies isolation enforcement to the GFX and Compute rings in the gfx_v9_4_3 module. The commit sets `amdgpu_gfx_enforce_isolation_ring_begin_use` and `amdgpu_gfx_enforce_isolation_ring_end_use` as the functions to be called when a ring begins and ends its use, respectively. `amdgpu_gfx_enforce_isolation_ring_begin_use` is called when a ring begins its use. This function cancels any scheduled `enforce_isolation_work` and, if necessary, signals the Kernel Fusion Driver (KFD) to stop the runqueue. `amdgpu_gfx_enforce_isolation_ring_end_use` is called when a ring ends its use. This function schedules `enforce_isolation_work` to be run after a delay. These functions are part of the Enforce Isolation Handler, which enforces shader isolation on AMD GPUs to prevent data leakage between different processes. The commit also includes a check for the type of the ring. If the type of the ring is `AMDGPU_RING_TYPE_COMPUTE`, the `xcp_id` of the `enforce_isolation` structure in the `gfx` structure of the `amdgpu_device` is set to the `xcp_id` of the ring. This ensures that the correct `xcp_id` is used when enforcing isolation on compute rings. The `xcp_id` is an identifier for an XCP partition, and different rings can be associated with different XCP partitions. Cc: Christian König Cc: Alex Deucher Signed-off-by: Alex Deucher Signed-off-by: Srinivasan Shanmugam --- drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c | 4 ++++ drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 2 ++ 2 files changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c b/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c index 77f20d9cddde2..79cd14223c89c 100644 --- a/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c +++ b/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c @@ -75,6 +75,8 @@ static void aqua_vanjaram_set_xcp_id(struct amdgpu_device *adev, uint32_t inst_mask; ring->xcp_id = AMDGPU_XCP_NO_PARTITION; + if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) + adev->gfx.enforce_isolation[0].xcp_id = ring->xcp_id; if (adev->xcp_mgr->mode == AMDGPU_XCP_MODE_NONE) return; @@ -103,6 +105,8 @@ static void aqua_vanjaram_set_xcp_id(struct amdgpu_device *adev, for (xcp_id = 0; xcp_id < adev->xcp_mgr->num_xcps; xcp_id++) { if (adev->xcp_mgr->xcp[xcp_id].ip[ip_blk].inst_mask & inst_mask) { ring->xcp_id = xcp_id; + if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) + adev->gfx.enforce_isolation[xcp_id].xcp_id = xcp_id; break; } } diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index fa6752585a729..2067f26d3a9d8 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -4671,6 +4671,8 @@ static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_compute = { .emit_wave_limit = gfx_v9_4_3_emit_wave_limit, .reset = gfx_v9_4_3_reset_kcq, .emit_cleaner_shader = gfx_v9_4_3_ring_emit_cleaner_shader, + .begin_use = amdgpu_gfx_enforce_isolation_ring_begin_use, + .end_use = amdgpu_gfx_enforce_isolation_ring_end_use, }; static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_kiq = { From f08bc9337cb03e43db52721e1607bebb90b021f4 Mon Sep 17 00:00:00 2001 From: Amber Lin Date: Mon, 29 Apr 2024 16:40:44 -0400 Subject: [PATCH 1353/1868] drm/amdkfd: Enable processes isolation on gfx9 When amdgpu enable enforce_isolation, KFD enables single-process mode in HWS and sets exec_cleaner_shader bit in MAP_PROCESS. Signed-off-by: Amber Lin Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_v9.c | 14 +++++++++++++- drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h | 5 +++-- .../gpu/drm/amd/amdkfd/kfd_pm4_headers_aldebaran.h | 2 +- 3 files changed, 17 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_v9.c index 00776f08351c3..1f9f5bfeaf868 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_v9.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_packet_manager_v9.c @@ -37,11 +37,14 @@ static int pm_map_process_v9(struct packet_manager *pm, struct kfd_node *kfd = pm->dqm->dev; struct kfd_process_device *pdd = container_of(qpd, struct kfd_process_device, qpd); + struct amdgpu_device *adev = kfd->adev; packet = (struct pm4_mes_map_process *)buffer; memset(buffer, 0, sizeof(struct pm4_mes_map_process)); packet->header.u32All = pm_build_pm4_header(IT_MAP_PROCESS, sizeof(struct pm4_mes_map_process)); + if (adev->enforce_isolation[kfd->node_id]) + packet->bitfields2.exec_cleaner_shader = 1; packet->bitfields2.diq_enable = (qpd->is_debug) ? 1 : 0; packet->bitfields2.process_quantum = 10; packet->bitfields2.pasid = qpd->pqm->process->pasid; @@ -89,14 +92,18 @@ static int pm_map_process_aldebaran(struct packet_manager *pm, struct pm4_mes_map_process_aldebaran *packet; uint64_t vm_page_table_base_addr = qpd->page_table_base; struct kfd_dev *kfd = pm->dqm->dev->kfd; + struct kfd_node *knode = pm->dqm->dev; struct kfd_process_device *pdd = container_of(qpd, struct kfd_process_device, qpd); int i; + struct amdgpu_device *adev = kfd->adev; packet = (struct pm4_mes_map_process_aldebaran *)buffer; memset(buffer, 0, sizeof(struct pm4_mes_map_process_aldebaran)); packet->header.u32All = pm_build_pm4_header(IT_MAP_PROCESS, sizeof(struct pm4_mes_map_process_aldebaran)); + if (adev->enforce_isolation[knode->node_id]) + packet->bitfields2.exec_cleaner_shader = 1; packet->bitfields2.diq_enable = (qpd->is_debug) ? 1 : 0; packet->bitfields2.process_quantum = 10; packet->bitfields2.pasid = qpd->pqm->process->pasid; @@ -144,17 +151,22 @@ static int pm_runlist_v9(struct packet_manager *pm, uint32_t *buffer, int concurrent_proc_cnt = 0; struct kfd_node *kfd = pm->dqm->dev; + struct amdgpu_device *adev = kfd->adev; /* Determine the number of processes to map together to HW: * it can not exceed the number of VMIDs available to the * scheduler, and it is determined by the smaller of the number * of processes in the runlist and kfd module parameter * hws_max_conc_proc. + * However, if enforce_isolation is set (toggle LDS/VGPRs/SGPRs + * cleaner between process switch), enable single-process mode + * in HWS. * Note: the arbitration between the number of VMIDs and * hws_max_conc_proc has been done in * kgd2kfd_device_init(). */ - concurrent_proc_cnt = min(pm->dqm->processes_count, + concurrent_proc_cnt = adev->enforce_isolation[kfd->node_id] ? + 1 : min(pm->dqm->processes_count, kfd->max_proc_per_quantum); packet = (struct pm4_mes_runlist *)buffer; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h b/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h index 8b6b2bd5c148f..cd8611401a664 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_ai.h @@ -145,8 +145,9 @@ struct pm4_mes_map_process { union { struct { - uint32_t pasid:16; - uint32_t reserved1:2; + uint32_t pasid:16; /* 0 - 15 */ + uint32_t reserved1:1; /* 16 */ + uint32_t exec_cleaner_shader:1; /* 17 */ uint32_t debug_vmid:4; uint32_t new_debug:1; uint32_t reserved2:1; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_aldebaran.h b/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_aldebaran.h index 38f5cb6a222ab..e0ed62c4ade04 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_aldebaran.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_pm4_headers_aldebaran.h @@ -37,7 +37,7 @@ struct pm4_mes_map_process_aldebaran { struct { uint32_t pasid:16; /* 0 - 15 */ uint32_t single_memops:1; /* 16 */ - uint32_t reserved1:1; /* 17 */ + uint32_t exec_cleaner_shader:1; /* 17 */ uint32_t debug_vmid:4; /* 18 - 21 */ uint32_t new_debug:1; /* 22 */ uint32_t tmz:1; /* 23 */ From fea02aa2f245f6dbde07f6728126d23ee477bb44 Mon Sep 17 00:00:00 2001 From: Mukul Joshi Date: Mon, 3 Jun 2024 11:48:23 -0400 Subject: [PATCH 1354/1868] drm/amdgpu: Implement MES Suspend and Resume APIs for GFX11 Add implementation for MES Suspend and Resume APIs to unmap/map all queues for GFX11. Support for GFX12 will be added when the corresponding firmware support is in place. Signed-off-by: Mukul Joshi Reviewed-by: Alex Deucher Reviewed-by: Harish Kasiviswanathan --- drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 71 +++++++++++++------------ drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 2 + drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 32 ++++++++++- 3 files changed, 69 insertions(+), 36 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c index 2993df13613be..6d0cb6b5bf719 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c @@ -501,60 +501,50 @@ int amdgpu_mes_remove_gang(struct amdgpu_device *adev, int gang_id) int amdgpu_mes_suspend(struct amdgpu_device *adev) { - struct idr *idp; - struct amdgpu_mes_process *process; - struct amdgpu_mes_gang *gang; struct mes_suspend_gang_input input; - int r, pasid; + int r; + + if (!amdgpu_mes_suspend_resume_all_supported(adev)) + return 0; + + memset(&input, 0x0, sizeof(struct mes_suspend_gang_input)); + input.suspend_all_gangs = 1; /* * Avoid taking any other locks under MES lock to avoid circular * lock dependencies. */ amdgpu_mes_lock(&adev->mes); - - idp = &adev->mes.pasid_idr; - - idr_for_each_entry(idp, process, pasid) { - list_for_each_entry(gang, &process->gang_list, list) { - r = adev->mes.funcs->suspend_gang(&adev->mes, &input); - if (r) - DRM_ERROR("failed to suspend pasid %d gangid %d", - pasid, gang->gang_id); - } - } - + r = adev->mes.funcs->suspend_gang(&adev->mes, &input); amdgpu_mes_unlock(&adev->mes); - return 0; + if (r) + DRM_ERROR("failed to suspend all gangs"); + + return r; } int amdgpu_mes_resume(struct amdgpu_device *adev) { - struct idr *idp; - struct amdgpu_mes_process *process; - struct amdgpu_mes_gang *gang; struct mes_resume_gang_input input; - int r, pasid; + int r; + + if (!amdgpu_mes_suspend_resume_all_supported(adev)) + return 0; + + memset(&input, 0x0, sizeof(struct mes_resume_gang_input)); + input.resume_all_gangs = 1; /* * Avoid taking any other locks under MES lock to avoid circular * lock dependencies. */ amdgpu_mes_lock(&adev->mes); - - idp = &adev->mes.pasid_idr; - - idr_for_each_entry(idp, process, pasid) { - list_for_each_entry(gang, &process->gang_list, list) { - r = adev->mes.funcs->resume_gang(&adev->mes, &input); - if (r) - DRM_ERROR("failed to resume pasid %d gangid %d", - pasid, gang->gang_id); - } - } - + r = adev->mes.funcs->resume_gang(&adev->mes, &input); amdgpu_mes_unlock(&adev->mes); - return 0; + if (r) + DRM_ERROR("failed to resume all gangs"); + + return r; } static int amdgpu_mes_queue_alloc_mqd(struct amdgpu_device *adev, @@ -1650,6 +1640,19 @@ int amdgpu_mes_init_microcode(struct amdgpu_device *adev, int pipe) return r; } +bool amdgpu_mes_suspend_resume_all_supported(struct amdgpu_device *adev) +{ + uint32_t mes_rev = adev->mes.sched_version & AMDGPU_MES_VERSION_MASK; + bool is_supported = false; + + if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(11, 0, 0) && + amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(12, 0, 0) && + mes_rev >= 0x63) + is_supported = true; + + return is_supported; +} + #if defined(CONFIG_DEBUG_FS) static int amdgpu_debugfs_mes_event_log_show(struct seq_file *m, void *unused) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h index 5c8867d2380af..a5b1ea60cac8d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h @@ -503,4 +503,6 @@ static inline void amdgpu_mes_unlock(struct amdgpu_mes *mes) memalloc_noreclaim_restore(mes->saved_flags); mutex_unlock(&mes->mutex_hidden); } + +bool amdgpu_mes_suspend_resume_all_supported(struct amdgpu_device *adev); #endif /* __AMDGPU_MES_H__ */ diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c index 6f5a80519af92..8edcd85a1261f 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c @@ -441,13 +441,41 @@ static int mes_v11_0_unmap_legacy_queue(struct amdgpu_mes *mes, static int mes_v11_0_suspend_gang(struct amdgpu_mes *mes, struct mes_suspend_gang_input *input) { - return 0; + union MESAPI__SUSPEND mes_suspend_gang_pkt; + + memset(&mes_suspend_gang_pkt, 0, sizeof(mes_suspend_gang_pkt)); + + mes_suspend_gang_pkt.header.type = MES_API_TYPE_SCHEDULER; + mes_suspend_gang_pkt.header.opcode = MES_SCH_API_SUSPEND; + mes_suspend_gang_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; + + mes_suspend_gang_pkt.suspend_all_gangs = input->suspend_all_gangs; + mes_suspend_gang_pkt.gang_context_addr = input->gang_context_addr; + mes_suspend_gang_pkt.suspend_fence_addr = input->suspend_fence_addr; + mes_suspend_gang_pkt.suspend_fence_value = input->suspend_fence_value; + + return mes_v11_0_submit_pkt_and_poll_completion(mes, + &mes_suspend_gang_pkt, sizeof(mes_suspend_gang_pkt), + offsetof(union MESAPI__SUSPEND, api_status)); } static int mes_v11_0_resume_gang(struct amdgpu_mes *mes, struct mes_resume_gang_input *input) { - return 0; + union MESAPI__RESUME mes_resume_gang_pkt; + + memset(&mes_resume_gang_pkt, 0, sizeof(mes_resume_gang_pkt)); + + mes_resume_gang_pkt.header.type = MES_API_TYPE_SCHEDULER; + mes_resume_gang_pkt.header.opcode = MES_SCH_API_RESUME; + mes_resume_gang_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS; + + mes_resume_gang_pkt.resume_all_gangs = input->resume_all_gangs; + mes_resume_gang_pkt.gang_context_addr = input->gang_context_addr; + + return mes_v11_0_submit_pkt_and_poll_completion(mes, + &mes_resume_gang_pkt, sizeof(mes_resume_gang_pkt), + offsetof(union MESAPI__RESUME, api_status)); } static int mes_v11_0_query_sched_status(struct amdgpu_mes *mes) From 6f88eb0caf1179802fb28e92dad02cdf080333af Mon Sep 17 00:00:00 2001 From: Mukul Joshi Date: Mon, 3 Jun 2024 11:57:50 -0400 Subject: [PATCH 1355/1868] drm/amdkfd: Update queue unmap after VM fault with MES MEC FW expects MES to unmap all queues when a VM fault is observed on a queue and then resumed once the affected process is terminated. Use the MES Suspend and Resume APIs to achieve this. Signed-off-by: Mukul Joshi Acked-by: Alex Deucher Reviewed-by: Harish Kasiviswanathan Reviewed-by: Felix Kuehling --- .../drm/amd/amdkfd/kfd_device_queue_manager.c | 87 ++++++++++++++++++- 1 file changed, 85 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index 8f32147601871..02cdb5833bc91 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -345,6 +345,46 @@ static int remove_all_queues_mes(struct device_queue_manager *dqm) return retval; } +static int suspend_all_queues_mes(struct device_queue_manager *dqm) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)dqm->dev->adev; + int r = 0; + + if (!down_read_trylock(&adev->reset_domain->sem)) + return -EIO; + + r = amdgpu_mes_suspend(adev); + up_read(&adev->reset_domain->sem); + + if (r) { + dev_err(adev->dev, "failed to suspend gangs from MES\n"); + dev_err(adev->dev, "MES might be in unrecoverable state, issue a GPU reset\n"); + kfd_hws_hang(dqm); + } + + return r; +} + +static int resume_all_queues_mes(struct device_queue_manager *dqm) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)dqm->dev->adev; + int r = 0; + + if (!down_read_trylock(&adev->reset_domain->sem)) + return -EIO; + + r = amdgpu_mes_resume(adev); + up_read(&adev->reset_domain->sem); + + if (r) { + dev_err(adev->dev, "failed to resume gangs from MES\n"); + dev_err(adev->dev, "MES might be in unrecoverable state, issue a GPU reset\n"); + kfd_hws_hang(dqm); + } + + return r; +} + static void increment_queue_count(struct device_queue_manager *dqm, struct qcm_process_device *qpd, struct queue *q) @@ -2917,6 +2957,44 @@ void device_queue_manager_uninit(struct device_queue_manager *dqm) kfree(dqm); } +static int kfd_dqm_evict_pasid_mes(struct device_queue_manager *dqm, + struct qcm_process_device *qpd) +{ + struct device *dev = dqm->dev->adev->dev; + int ret = 0; + + /* Check if process is already evicted */ + dqm_lock(dqm); + if (qpd->evicted) { + /* Increment the evicted count to make sure the + * process stays evicted before its terminated. + */ + qpd->evicted++; + dqm_unlock(dqm); + goto out; + } + dqm_unlock(dqm); + + ret = suspend_all_queues_mes(dqm); + if (ret) { + dev_err(dev, "Suspending all queues failed"); + goto out; + } + + ret = dqm->ops.evict_process_queues(dqm, qpd); + if (ret) { + dev_err(dev, "Evicting process queues failed"); + goto out; + } + + ret = resume_all_queues_mes(dqm); + if (ret) + dev_err(dev, "Resuming all queues failed"); + +out: + return ret; +} + int kfd_dqm_evict_pasid(struct device_queue_manager *dqm, u32 pasid) { struct kfd_process_device *pdd; @@ -2927,8 +3005,13 @@ int kfd_dqm_evict_pasid(struct device_queue_manager *dqm, u32 pasid) return -EINVAL; WARN(debug_evictions, "Evicting pid %d", p->lead_thread->pid); pdd = kfd_get_process_device_data(dqm->dev, p); - if (pdd) - ret = dqm->ops.evict_process_queues(dqm, &pdd->qpd); + if (pdd) { + if (dqm->dev->kfd->shared_resources.enable_mes) + ret = kfd_dqm_evict_pasid_mes(dqm, &pdd->qpd); + else + ret = dqm->ops.evict_process_queues(dqm, &pdd->qpd); + } + kfd_unref_process(p); return ret; From 7c80da138e44fad3a5908fe7acbcf7d6f487a536 Mon Sep 17 00:00:00 2001 From: Mukul Joshi Date: Mon, 12 Aug 2024 11:11:28 -0400 Subject: [PATCH 1356/1868] drm/amdkfd: Update BadOpcode Interrupt handling with MES Based on the recommendation of MEC FW, update BadOpcode interrupt handling by unmapping all queues, removing the queue that got the interrupt from scheduling and remapping rest of the queues back when using MES scheduler. This is done to prevent the case where unmapping of the bad queue can fail thereby causing a GPU reset. Signed-off-by: Mukul Joshi Acked-by: Harish Kasiviswanathan Acked-by: Alex Deucher Reviewed-by: Felix Kuehling --- .../drm/amd/amdkfd/kfd_device_queue_manager.c | 51 +++++++++++++++++++ .../gpu/drm/amd/amdkfd/kfd_int_process_v11.c | 9 ++-- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 1 + 3 files changed, 58 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index 02cdb5833bc91..e96de444db64a 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -2957,6 +2957,57 @@ void device_queue_manager_uninit(struct device_queue_manager *dqm) kfree(dqm); } +int kfd_dqm_suspend_bad_queue_mes(struct kfd_node *knode, u32 pasid, u32 doorbell_id) +{ + struct kfd_process_device *pdd; + struct kfd_process *p = kfd_lookup_process_by_pasid(pasid); + struct device_queue_manager *dqm = knode->dqm; + struct device *dev = dqm->dev->adev->dev; + struct qcm_process_device *qpd; + struct queue *q = NULL; + int ret = 0; + + if (!p) + return -EINVAL; + + dqm_lock(dqm); + + pdd = kfd_get_process_device_data(dqm->dev, p); + if (pdd) { + qpd = &pdd->qpd; + + list_for_each_entry(q, &qpd->queues_list, list) { + if (q->doorbell_id == doorbell_id && q->properties.is_active) { + ret = suspend_all_queues_mes(dqm); + if (ret) { + dev_err(dev, "Suspending all queues failed"); + goto out; + } + + q->properties.is_evicted = true; + q->properties.is_active = false; + decrement_queue_count(dqm, qpd, q); + + ret = remove_queue_mes(dqm, q, qpd); + if (ret) { + dev_err(dev, "Removing bad queue failed"); + goto out; + } + + ret = resume_all_queues_mes(dqm); + if (ret) + dev_err(dev, "Resuming all queues failed"); + + break; + } + } + } + +out: + dqm_unlock(dqm); + return ret; +} + static int kfd_dqm_evict_pasid_mes(struct device_queue_manager *dqm, struct qcm_process_device *qpd) { diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v11.c b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v11.c index f524a55eee116..b3f988b275a88 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v11.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v11.c @@ -330,11 +330,14 @@ static void event_interrupt_wq_v11(struct kfd_node *dev, if (source_id == SOC15_INTSRC_CP_END_OF_PIPE) kfd_signal_event_interrupt(pasid, context_id0, 32); else if (source_id == SOC15_INTSRC_CP_BAD_OPCODE && - KFD_DBG_EC_TYPE_IS_PACKET(KFD_CTXID0_CP_BAD_OP_ECODE(context_id0))) - kfd_set_dbg_ev_from_interrupt(dev, pasid, - KFD_CTXID0_DOORBELL_ID(context_id0), + KFD_DBG_EC_TYPE_IS_PACKET(KFD_CTXID0_CP_BAD_OP_ECODE(context_id0))) { + u32 doorbell_id = KFD_CTXID0_DOORBELL_ID(context_id0); + + kfd_set_dbg_ev_from_interrupt(dev, pasid, doorbell_id, KFD_EC_MASK(KFD_CTXID0_CP_BAD_OP_ECODE(context_id0)), NULL, 0); + kfd_dqm_suspend_bad_queue_mes(dev, pasid, doorbell_id); + } /* SDMA */ else if (source_id == SOC21_INTSRC_SDMA_TRAP) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 7ca3d626cd345..a2a547f3d3cfb 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -1457,6 +1457,7 @@ struct kernel_queue *kernel_queue_init(struct kfd_node *dev, enum kfd_queue_type type); void kernel_queue_uninit(struct kernel_queue *kq); int kfd_dqm_evict_pasid(struct device_queue_manager *dqm, u32 pasid); +int kfd_dqm_suspend_bad_queue_mes(struct kfd_node *knode, u32 pasid, u32 doorbell_id); /* Process Queue Manager */ struct process_queue_node { From 430027cb370fcb52da26aabdecd8c498cd237f42 Mon Sep 17 00:00:00 2001 From: Candice Li Date: Thu, 15 Aug 2024 11:37:28 +0800 Subject: [PATCH 1357/1868] drm/amdgpu: Validate TA binary size Add TA binary size validation to avoid OOB write. Signed-off-by: Candice Li Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.c index 0c856005df6b9..38face981c3e3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.c @@ -166,6 +166,9 @@ static ssize_t ta_if_load_debugfs_write(struct file *fp, const char *buf, size_t if (ret) return -EFAULT; + if (ta_bin_len > PSP_1_MEG) + return -EINVAL; + copy_pos += sizeof(uint32_t); ta_bin = kzalloc(ta_bin_len, GFP_KERNEL); From 40ce4f8e6cd6a3f0ff6040ce8e546fe66746c222 Mon Sep 17 00:00:00 2001 From: Hansen Dsouza Date: Thu, 15 Aug 2024 18:45:13 -0400 Subject: [PATCH 1358/1868] Revert "drm/amd/display: Update to using new dccg callbacks" [Why] Revert updated DCCG wrappers due to regression [How] This reverts commit 28b190df7a8f43b39e13886d744742a74a2c162d. Reviewed-by: Chris Park Signed-off-by: Hansen Dsouza Signed-off-by: Roman Li Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c index 004c4fe3ddfc1..7f91e48902e22 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c @@ -2396,11 +2396,11 @@ struct dccg *dccg35_create( (void)&dccg35_disable_symclk_be_new; (void)&dccg35_set_symclk32_le_root_clock_gating; (void)&dccg35_set_smclk32_se_rcg; - (void)&dccg35_funcs; + (void)&dccg35_funcs_new; base = &dccg_dcn->base; base->ctx = ctx; - base->funcs = &dccg35_funcs_new; + base->funcs = &dccg35_funcs; dccg_dcn->regs = regs; dccg_dcn->dccg_shift = dccg_shift; From cdc09ed59ac5bd8f3674d8fbbd3b2ebf009369e6 Mon Sep 17 00:00:00 2001 From: Michael Strauss Date: Thu, 15 Aug 2024 18:45:14 -0400 Subject: [PATCH 1359/1868] drm/amd/display: Update HPO I/O When Handling Link Retrain Automation Request [WHY] Previous multi-display HPO fix moved where HPO I/O enable/disable is performed. The codepath now taken to enable/disable HPO I/O is not used for compliance test automation, meaning that if a compliance box being driven at a DP1 rate requests retrain at UHBR, HPO I/O will remain off if it was previously off. [HOW] Explicitly update HPO I/O after allocating encoders for test request. Reviewed-by: Charlene Liu Reviewed-by: Wenjing Liu Signed-off-by: Michael Strauss Signed-off-by: Roman Li Tested-by: Daniel Wheeler --- .../gpu/drm/amd/display/dc/core/dc_resource.c | 13 ++++++++++++ .../amd/display/dc/hwss/dce110/dce110_hwseq.c | 21 ++++--------------- .../amd/display/dc/hwss/dcn31/dcn31_init.c | 1 + .../amd/display/dc/hwss/dcn314/dcn314_init.c | 1 + .../amd/display/dc/hwss/dcn351/dcn351_init.c | 1 + .../drm/amd/display/dc/hwss/hw_sequencer.h | 1 + drivers/gpu/drm/amd/display/dc/inc/resource.h | 2 ++ .../display/dc/link/accessories/link_dp_cts.c | 8 +++++++ 8 files changed, 31 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index b38340c690c60..b6377efc62531 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -5303,3 +5303,16 @@ int resource_calculate_det_for_stream(struct dc_state *state, struct pipe_ctx *o } return det_segments; } + +bool resource_is_hpo_acquired(struct dc_state *context) +{ + int i; + + for (i = 0; i < MAX_HPO_DP2_ENCODERS; i++) { + if (context->res_ctx.is_hpo_dp_stream_enc_acquired[i]) { + return true; + } + } + + return false; +} diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c index 217344ccf6440..246fa300ee95c 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c @@ -2350,19 +2350,6 @@ static void dce110_setup_audio_dto( } } -static bool dce110_is_hpo_enabled(struct dc_state *context) -{ - int i; - - for (i = 0; i < MAX_HPO_DP2_ENCODERS; i++) { - if (context->res_ctx.is_hpo_dp_stream_enc_acquired[i]) { - return true; - } - } - - return false; -} - enum dc_status dce110_apply_ctx_to_hw( struct dc *dc, struct dc_state *context) @@ -2371,8 +2358,8 @@ enum dc_status dce110_apply_ctx_to_hw( struct dc_bios *dcb = dc->ctx->dc_bios; enum dc_status status; int i; - bool was_hpo_enabled = dce110_is_hpo_enabled(dc->current_state); - bool is_hpo_enabled = dce110_is_hpo_enabled(context); + bool was_hpo_acquired = resource_is_hpo_acquired(dc->current_state); + bool is_hpo_acquired = resource_is_hpo_acquired(context); /* reset syncd pipes from disabled pipes */ if (dc->config.use_pipe_ctx_sync_logic) @@ -2415,8 +2402,8 @@ enum dc_status dce110_apply_ctx_to_hw( dce110_setup_audio_dto(dc, context); - if (dc->hwseq->funcs.setup_hpo_hw_control && was_hpo_enabled != is_hpo_enabled) { - dc->hwseq->funcs.setup_hpo_hw_control(dc->hwseq, is_hpo_enabled); + if (dc->hwseq->funcs.setup_hpo_hw_control && was_hpo_acquired != is_hpo_acquired) { + dc->hwseq->funcs.setup_hpo_hw_control(dc->hwseq, is_hpo_acquired); } for (i = 0; i < dc->res_pool->pipe_count; i++) { diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c index b57dd45611f23..56f3c70d4b554 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_init.c @@ -111,6 +111,7 @@ static const struct hw_sequencer_funcs dcn31_funcs = { .optimize_pwr_state = dcn21_optimize_pwr_state, .exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state, .update_visual_confirm_color = dcn10_update_visual_confirm_color, + .setup_hpo_hw_control = dcn31_setup_hpo_hw_control, }; static const struct hwseq_private_funcs dcn31_private_funcs = { diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c index fe5495a8e7a2b..68e6de6b5758d 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_init.c @@ -114,6 +114,7 @@ static const struct hw_sequencer_funcs dcn314_funcs = { .exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state, .update_visual_confirm_color = dcn10_update_visual_confirm_color, .calculate_pix_rate_divider = dcn314_calculate_pix_rate_divider, + .setup_hpo_hw_control = dcn31_setup_hpo_hw_control, }; static const struct hwseq_private_funcs dcn314_private_funcs = { diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c index 5da3069fc1aba..d00822e8daa52 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c @@ -123,6 +123,7 @@ static const struct hw_sequencer_funcs dcn351_funcs = { .set_long_vtotal = dcn35_set_long_vblank, .calculate_pix_rate_divider = dcn32_calculate_pix_rate_divider, .program_outstanding_updates = dcn32_program_outstanding_updates, + .setup_hpo_hw_control = dcn35_setup_hpo_hw_control, }; static const struct hwseq_private_funcs dcn351_private_funcs = { diff --git a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h index 3268544898026..ac92056256233 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h @@ -461,6 +461,7 @@ struct hw_sequencer_funcs { void (*set_long_vtotal)(struct pipe_ctx **pipe_ctx, int num_pipes, uint32_t v_total_min, uint32_t v_total_max); void (*program_outstanding_updates)(struct dc *dc, struct dc_state *context); + void (*setup_hpo_hw_control)(const struct dce_hwseq *hws, bool enable); }; void color_space_to_black_color( diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h index 9cd80d3864c7b..cd1157d225abe 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/resource.h +++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h @@ -644,4 +644,6 @@ void resource_init_common_dml2_callbacks(struct dc *dc, struct dml2_configuratio *Calculate total DET allocated for all pipes for a given OTG_MASTER pipe */ int resource_calculate_det_for_stream(struct dc_state *state, struct pipe_ctx *otg_master); + +bool resource_is_hpo_acquired(struct dc_state *context); #endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_RESOURCE_H_ */ diff --git a/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c b/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c index df3781081da7a..ff8fe1a94965b 100644 --- a/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c +++ b/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c @@ -67,6 +67,8 @@ static void dp_retrain_link_dp_test(struct dc_link *link, { struct pipe_ctx *pipes[MAX_PIPES]; struct dc_state *state = link->dc->current_state; + bool was_hpo_acquired = resource_is_hpo_acquired(link->dc->current_state); + bool is_hpo_acquired; uint8_t count; int i; @@ -83,6 +85,12 @@ static void dp_retrain_link_dp_test(struct dc_link *link, pipes[i]); } + if (link->dc->hwss.setup_hpo_hw_control) { + is_hpo_acquired = resource_is_hpo_acquired(state); + if (was_hpo_acquired != is_hpo_acquired) + link->dc->hwss.setup_hpo_hw_control(link->dc->hwseq, is_hpo_acquired); + } + for (i = count-1; i >= 0; i--) link_set_dpms_on(state, pipes[i]); } From 1072c13e099020045b40f3cdbb1765861c4934d9 Mon Sep 17 00:00:00 2001 From: Aurabindo Pillai Date: Thu, 15 Aug 2024 18:45:15 -0400 Subject: [PATCH 1360/1868] drm/amd/display: remove an extraneous call for checking dchub clock when removing the amdgpu module and reinserting it, a call trace is triggered: [ 334.230602] RIP: 0010:hubbub2_get_dchub_ref_freq+0xbb/0xe0 [amdgpu] [ 334.230807] Code: 25 28 00 00 00 75 3c 48 8d 65 f0 5b 41 5c 5d 31 c0 31 d2 31 c9 31 f6 31 ff 45 31 c0 45 31 c9 45 31 d2 45 31 db e9 55 a1 ca de <0f> 0b eb c6 0f 0b eb c2 d1 eb 8d 83 c0 63 ff ff 3d 20 4e 00 00 76 [ 334.230809] RSP: 0018:ffffbc8b823fb540 EFLAGS: 00010246 [ 334.230811] RAX: 0000000000001000 RBX: 00000000000186a0 RCX: 0000000000000000 [ 334.230812] RDX: ffffbc8b823fb544 RSI: 0000000000000000 RDI: 0000000000000000 [ 334.230813] RBP: ffffbc8b823fb560 R08: 0000000000000000 R09: 0000000000000000 [ 334.230814] R10: 0000000000000000 R11: 000000000000000f R12: ffff9e644f1f2bb0 [ 334.230815] R13: ffff9e6451361300 R14: 0000000000000000 R15: ffff9e6452c00000 [ 334.230816] FS: 00007af7c8519000(0000) GS:ffff9e737dd00000(0000) knlGS:0000000000000000 [ 334.230817] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 334.230818] CR2: 0000703576b9cbd0 CR3: 00000001095a2000 CR4: 0000000000750ee0 [ 334.230819] PKRU: 55555554 [ 334.230820] Call Trace: [ 334.230822] [ 334.230824] ? show_regs+0x6d/0x80 [ 334.230828] ? __warn+0x89/0x160 [ 334.230832] ? hubbub2_get_dchub_ref_freq+0xbb/0xe0 [amdgpu] [ 334.231024] ? report_bug+0x17e/0x1b0 [ 334.231028] ? handle_bug+0x46/0x90 [ 334.231030] ? exc_invalid_op+0x18/0x80 [ 334.231032] ? asm_exc_invalid_op+0x1b/0x20 [ 334.231036] ? hubbub2_get_dchub_ref_freq+0xbb/0xe0 [amdgpu] [ 334.231217] dc_create_resource_pool+0xfd/0x320 [amdgpu] [ 334.231408] dc_create+0x256/0x700 [amdgpu] [ 334.231588] ? srso_alias_return_thunk+0x5/0x7f [ 334.231590] ? dmi_matches+0xa0/0x230 [ 334.231594] amdgpu_dm_init+0x28c/0x25f0 [amdgpu] [ 334.231791] ? prb_read_valid+0x1c/0x30 [ 334.231795] ? __irq_work_queue_local+0x43/0xf0 [ 334.231798] ? srso_alias_return_thunk+0x5/0x7f [ 334.231800] ? irq_work_queue+0x2f/0x70 [ 334.231802] ? srso_alias_return_thunk+0x5/0x7f [ 334.231803] ? __wake_up_klogd.part.0+0x40/0x70 [ 334.231805] ? srso_alias_return_thunk+0x5/0x7f [ 334.231807] ? vprintk_emit+0xd9/0x210 [ 334.231809] ? set_dev_info+0x130/0x1c0 [ 334.231812] ? srso_alias_return_thunk+0x5/0x7f [ 334.231813] ? dev_printk_emit+0xa1/0xe0 [ 334.231819] dm_hw_init+0x14/0x30 [amdgpu] [ 334.231993] amdgpu_device_init+0x23c7/0x2fc0 [amdgpu] [ 334.232134] ? pci_read_config_word+0x25/0x50 [ 334.232139] amdgpu_driver_load_kms+0x1a/0xd0 [amdgpu] [ 334.232284] amdgpu_pci_probe+0x1f9/0x620 [amdgpu] On DCN401, get_dchub_ref_freq() hook is called before init_hw() hook. Hence, it is expected to trigger an assert. Remove the extraneous call to get_dchub_ref_freq() to suppress the call trace Reviewed-by: Alvin Lee Signed-off-by: Aurabindo Pillai Signed-off-by: Roman Li Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index b6377efc62531..ef585a89847bf 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -342,11 +342,6 @@ struct resource_pool *dc_create_resource_pool(struct dc *dc, res_pool->ref_clocks.xtalin_clock_inKhz; res_pool->ref_clocks.dchub_ref_clock_inKhz = res_pool->ref_clocks.xtalin_clock_inKhz; - if (dc->debug.using_dml2) - if (res_pool->hubbub && res_pool->hubbub->funcs->get_dchub_ref_freq) - res_pool->hubbub->funcs->get_dchub_ref_freq(res_pool->hubbub, - res_pool->ref_clocks.dccg_ref_clock_inKhz, - &res_pool->ref_clocks.dchub_ref_clock_inKhz); } else ASSERT_CRITICAL(false); } From d0b6508a74c87a5b41de775a3cb00dcbd3dc5110 Mon Sep 17 00:00:00 2001 From: Nicholas Susanto Date: Thu, 15 Aug 2024 18:45:16 -0400 Subject: [PATCH 1361/1868] drm/amd/display: Remove redundant check in DCN35 hwseq Removing redundant condition. Reviewed-by: Hansen Dsouza Signed-off-by: Nicholas Susanto Signed-off-by: Roman Li Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c index 899e239352aa0..fbbb20b9dbee7 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c @@ -1024,9 +1024,6 @@ void dcn35_calc_blocks_to_gate(struct dc *dc, struct dc_state *context, if (!hpo_frl_stream_enc_acquired && !hpo_dp_stream_enc_acquired) update_state->pg_res_update[PG_HPO] = true; - if (hpo_frl_stream_enc_acquired) - update_state->pg_pipe_res_update[PG_HDMISTREAM][0] = true; - update_state->pg_res_update[PG_DWB] = true; for (i = 0; i < dc->res_pool->pipe_count; i++) { From d3c9f38e8014474a2de28aa7725a292000048d23 Mon Sep 17 00:00:00 2001 From: Michael Strauss Date: Thu, 15 Aug 2024 18:45:17 -0400 Subject: [PATCH 1362/1868] drm/amd/display: Allow UHBR Interop With eDP Supported Link Rates Table [WHY] eDP 2.0 is introducing support for UHBR link rates, however current eDP ILR link optimization does not account for UHBR capabilities. Either UHBR capabilities will be provided via the same 128b/132b rate DPCD caps that are currently used on DP2.1, or Table 4-13 may be updated to include UHBR rates. [HOW] Add extra Supported Link Rates table translations for UHBR10/13.5/20. Update eDP link setting optimization search to be aware of 128b/132b DPCD rate caps in order to unblock UHBR on panels with Supported Link Rates table. Reviewed-by: Wenjing Liu Signed-off-by: Michael Strauss Signed-off-by: Roman Li Tested-by: Daniel Wheeler --- .../drm/amd/display/dc/link/link_detection.c | 3 +- .../dc/link/protocols/link_dp_capability.c | 59 ++++++++++--------- .../link/protocols/link_edp_panel_control.c | 11 ++-- .../link/protocols/link_edp_panel_control.h | 2 +- 4 files changed, 40 insertions(+), 35 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/link/link_detection.c b/drivers/gpu/drm/amd/display/dc/link/link_detection.c index 391dbe81534da..d21ee9d12d269 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_detection.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_detection.c @@ -1189,8 +1189,7 @@ static bool detect_link_and_local_sink(struct dc_link *link, //sink only can use supported link rate table, we are foreced to enable it if (link->reported_link_cap.link_rate == LINK_RATE_UNKNOWN) link->panel_config.ilr.optimize_edp_link_rate = true; - if (edp_is_ilr_optimization_enabled(link)) - link->reported_link_cap.link_rate = get_max_link_rate_from_ilr_table(link); + link->reported_link_cap.link_rate = get_max_edp_link_rate(link); } } else { diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c index 3434b69ca6826..1b43d9a9d1b06 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c @@ -212,6 +212,13 @@ static enum dc_link_rate linkRateInKHzToLinkRateMultiplier(uint32_t link_rate_in case 10000000: link_rate = LINK_RATE_UHBR10; // UHBR10 - 10.0 Gbps/Lane break; + case 13500000: + link_rate = LINK_RATE_UHBR13_5; // UHBR13.5 - 13.5 Gbps/Lane + break; + case 20000000: + link_rate = LINK_RATE_UHBR20; // UHBR20 - 20.0 Gbps/Lane + break; + default: link_rate = LINK_RATE_UNKNOWN; break; @@ -541,6 +548,23 @@ static enum dc_link_rate increase_link_rate(struct dc_link *link, } } +static void increase_edp_link_rate(struct dc_link *link, + struct dc_link_settings *current_link_setting) +{ + if (current_link_setting->use_link_rate_set) { + if (current_link_setting->link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) { + current_link_setting->link_rate_set++; + current_link_setting->link_rate = + link->dpcd_caps.edp_supported_link_rates[current_link_setting->link_rate_set]; + } else { + current_link_setting->use_link_rate_set = false; + current_link_setting->link_rate = LINK_RATE_UHBR10; + } + } else { + current_link_setting->link_rate = increase_link_rate(link, current_link_setting->link_rate); + } +} + static bool decide_fallback_link_setting_max_bw_policy( struct dc_link *link, const struct dc_link_settings *max, @@ -759,14 +783,7 @@ bool edp_decide_link_settings(struct dc_link *link, increase_lane_count( current_link_setting.lane_count); } else { - if (current_link_setting.link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) { - current_link_setting.link_rate_set++; - current_link_setting.link_rate = - link->dpcd_caps.edp_supported_link_rates[current_link_setting.link_rate_set]; - current_link_setting.lane_count = - initial_link_setting.lane_count; - } else - break; + increase_edp_link_rate(link, ¤t_link_setting); } } return false; @@ -819,9 +836,7 @@ bool decide_edp_link_settings_with_dsc(struct dc_link *link, if (policy) { /* minimize lane */ if (current_link_setting.link_rate < max_link_rate) { - current_link_setting.link_rate = - increase_link_rate(link, - current_link_setting.link_rate); + increase_edp_link_rate(link, ¤t_link_setting); } else { if (current_link_setting.lane_count < link->verified_link_cap.lane_count) { @@ -840,9 +855,7 @@ bool decide_edp_link_settings_with_dsc(struct dc_link *link, increase_lane_count( current_link_setting.lane_count); } else { - current_link_setting.link_rate = - increase_link_rate(link, - current_link_setting.link_rate); + increase_edp_link_rate(link, ¤t_link_setting); current_link_setting.lane_count = initial_link_setting.lane_count; } @@ -875,18 +888,15 @@ bool decide_edp_link_settings_with_dsc(struct dc_link *link, } if (policy) { /* minimize lane */ - if (current_link_setting.link_rate_set < - link->dpcd_caps.edp_supported_link_rates_count - && current_link_setting.link_rate < max_link_rate) { - current_link_setting.link_rate_set++; - current_link_setting.link_rate = - link->dpcd_caps.edp_supported_link_rates[current_link_setting.link_rate_set]; + if (current_link_setting.link_rate < max_link_rate) { + increase_edp_link_rate(link, ¤t_link_setting); } else { if (current_link_setting.lane_count < link->verified_link_cap.lane_count) { current_link_setting.lane_count = increase_lane_count( current_link_setting.lane_count); current_link_setting.link_rate_set = initial_link_setting.link_rate_set; + current_link_setting.use_link_rate_set = initial_link_setting.use_link_rate_set; current_link_setting.link_rate = link->dpcd_caps.edp_supported_link_rates[current_link_setting.link_rate_set]; } else @@ -900,13 +910,8 @@ bool decide_edp_link_settings_with_dsc(struct dc_link *link, increase_lane_count( current_link_setting.lane_count); } else { - if (current_link_setting.link_rate_set < link->dpcd_caps.edp_supported_link_rates_count) { - current_link_setting.link_rate_set++; - current_link_setting.link_rate = - link->dpcd_caps.edp_supported_link_rates[current_link_setting.link_rate_set]; - current_link_setting.lane_count = - initial_link_setting.lane_count; - } else + increase_edp_link_rate(link, ¤t_link_setting); + if (current_link_setting.link_rate == LINK_RATE_UNKNOWN) break; } } diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c index bf820d2b4dc4a..070b6c8c1aef9 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c @@ -305,16 +305,17 @@ bool edp_is_ilr_optimization_enabled(struct dc_link *link) return true; } -enum dc_link_rate get_max_link_rate_from_ilr_table(struct dc_link *link) +enum dc_link_rate get_max_edp_link_rate(struct dc_link *link) { - enum dc_link_rate link_rate = link->reported_link_cap.link_rate; + enum dc_link_rate max_ilr_rate = LINK_RATE_UNKNOWN; + enum dc_link_rate max_non_ilr_rate = dp_get_max_link_cap(link).link_rate; for (int i = 0; i < link->dpcd_caps.edp_supported_link_rates_count; i++) { - if (link_rate < link->dpcd_caps.edp_supported_link_rates[i]) - link_rate = link->dpcd_caps.edp_supported_link_rates[i]; + if (max_ilr_rate < link->dpcd_caps.edp_supported_link_rates[i]) + max_ilr_rate = link->dpcd_caps.edp_supported_link_rates[i]; } - return link_rate; + return (max_ilr_rate > max_non_ilr_rate ? max_ilr_rate : max_non_ilr_rate); } bool edp_is_ilr_optimization_required(struct dc_link *link, diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.h b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.h index 8df8ac5bde5b1..30dc8c24c008c 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.h +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.h @@ -69,7 +69,7 @@ bool edp_wait_for_t12(struct dc_link *link); bool edp_is_ilr_optimization_required(struct dc_link *link, struct dc_crtc_timing *crtc_timing); bool edp_is_ilr_optimization_enabled(struct dc_link *link); -enum dc_link_rate get_max_link_rate_from_ilr_table(struct dc_link *link); +enum dc_link_rate get_max_edp_link_rate(struct dc_link *link); bool edp_backlight_enable_aux(struct dc_link *link, bool enable); void edp_add_delay_for_T9(struct dc_link *link); bool edp_receiver_ready_T9(struct dc_link *link); From 9b4a297b50a8fa7463bae59120e7517efa1419ab Mon Sep 17 00:00:00 2001 From: Nevenko Stupar Date: Thu, 15 Aug 2024 18:45:18 -0400 Subject: [PATCH 1363/1868] drm/amd/display: Hardware cursor changes color when switched to software cursor [Why & How] DCN4 Cursor has separate degamma block and should always do Cursor degamma for Cursor color modes. Reviewed-by: Chris Park Signed-off-by: Nevenko Stupar Signed-off-by: Roman Li Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c index 92b34fe47f740..3b6ca7974e188 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_cm.c @@ -120,11 +120,10 @@ void dpp401_set_cursor_attributes( enum dc_cursor_color_format color_format = cursor_attributes->color_format; int cur_rom_en = 0; + // DCN4 should always do Cursor degamma for Cursor Color modes if (color_format == CURSOR_MODE_COLOR_PRE_MULTIPLIED_ALPHA || color_format == CURSOR_MODE_COLOR_UN_PRE_MULTIPLIED_ALPHA) { - if (cursor_attributes->attribute_flags.bits.ENABLE_CURSOR_DEGAMMA) { - cur_rom_en = 1; - } + cur_rom_en = 1; } REG_UPDATE_3(CURSOR0_CONTROL, From 842841db1bf1c6a38217b76b6cd6f15f6d5af200 Mon Sep 17 00:00:00 2001 From: Sung Joon Kim Date: Thu, 15 Aug 2024 18:45:19 -0400 Subject: [PATCH 1364/1868] drm/amd/display: Support UHBR10 link rate on eDP [why] Supporting UHBR10 link rate on eDP leverages the existing DP2.0 code but need to add some small adjustments in code. [how] Acknowledge the given DPCD caps for UHBR10 link rate support and allow DP2.0 programming sequence and link training for eDP. Reviewed-by: Wenjing Liu Signed-off-by: Sung Joon Kim Signed-off-by: Roman Li Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/dc.h | 1 + .../amd/display/dc/hwss/dce110/dce110_hwseq.c | 23 ++++++++++--------- .../gpu/drm/amd/display/dc/link/link_dpms.c | 4 ++-- .../link/protocols/link_edp_panel_control.c | 3 +++ 4 files changed, 18 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index d556e55517829..697d615617847 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -1763,6 +1763,7 @@ struct dc_link { bool dongle_mode_timing_override; bool blank_stream_on_ocs_change; bool read_dpcd204h_on_irq_hpd; + bool disable_assr_for_uhbr; } wa_flags; struct link_mst_stream_allocation_table mst_stream_alloc_table; diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c index 246fa300ee95c..d52ce58c6a987 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c @@ -1232,20 +1232,21 @@ void dce110_blank_stream(struct pipe_ctx *pipe_ctx) * has changed or they enter protection state and hang. */ msleep(60); - } else if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP) { - if (!link->dc->config.edp_no_power_sequencing) { - /* - * Sometimes, DP receiver chip power-controlled externally by an - * Embedded Controller could be treated and used as eDP, - * if it drives mobile display. In this case, - * we shouldn't be doing power-sequencing, hence we can skip - * waiting for T9-ready. - */ - link->dc->link_srv->edp_receiver_ready_T9(link); - } } } + if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP && + !link->dc->config.edp_no_power_sequencing) { + /* + * Sometimes, DP receiver chip power-controlled externally by an + * Embedded Controller could be treated and used as eDP, + * if it drives mobile display. In this case, + * we shouldn't be doing power-sequencing, hence we can skip + * waiting for T9-ready. + */ + link->dc->link_srv->edp_receiver_ready_T9(link); + } + } diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c index c53c9338c922d..b4c206c20b458 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c @@ -2440,7 +2440,7 @@ void link_set_dpms_off(struct pipe_ctx *pipe_ctx) if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) deallocate_mst_payload(pipe_ctx); - else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && + else if (dc_is_dp_sst_signal(pipe_ctx->stream->signal) && dp_is_128b_132b_signal(pipe_ctx)) update_sst_payload(pipe_ctx, false); @@ -2672,7 +2672,7 @@ void link_set_dpms_on( if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) allocate_mst_payload(pipe_ctx); - else if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT && + else if (dc_is_dp_sst_signal(pipe_ctx->stream->signal) && dp_is_128b_132b_signal(pipe_ctx)) update_sst_payload(pipe_ctx, true); diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c index 070b6c8c1aef9..3aa05a2be6c09 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c @@ -1168,6 +1168,9 @@ static void edp_set_assr_enable(const struct dc *pDC, struct dc_link *link, link_enc_index = link->link_enc->transmitter - TRANSMITTER_UNIPHY_A; if (link_res->hpo_dp_link_enc) { + if (link->wa_flags.disable_assr_for_uhbr) + return; + link_enc_index = link_res->hpo_dp_link_enc->inst; use_hpo_dp_link_enc = true; } From aad839abe9972f815b645524da5420c72865eb8e Mon Sep 17 00:00:00 2001 From: Ilya Bakoulin Date: Thu, 15 Aug 2024 18:45:20 -0400 Subject: [PATCH 1365/1868] drm/amd/display: Fix construct_phy with MXM connector [Why/How] The call to construct_phy will fail in cases where connector type is MXM, and the dc_link won't be properly created/initialized. Reviewed-by: Wenjing Liu Signed-off-by: Ilya Bakoulin Signed-off-by: Roman Li Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/link/link_factory.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/display/dc/link/link_factory.c b/drivers/gpu/drm/amd/display/dc/link/link_factory.c index 8246006857b30..85fd6e4222380 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_factory.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_factory.c @@ -524,6 +524,7 @@ static bool construct_phy(struct dc_link *link, link->connector_signal = SIGNAL_TYPE_DVI_DUAL_LINK; break; case CONNECTOR_ID_DISPLAY_PORT: + case CONNECTOR_ID_MXM: case CONNECTOR_ID_USBC: link->connector_signal = SIGNAL_TYPE_DISPLAY_PORT; From a346ad12683c52b867d8824889628034e68a5b4b Mon Sep 17 00:00:00 2001 From: Nicholas Susanto Date: Thu, 15 Aug 2024 18:45:21 -0400 Subject: [PATCH 1366/1868] drm/amd/display: DCN35 set min dispclk to 50Mhz [Why] Causes hard hangs when resuming after display off on extended/duplicate modes [How] Set the min dispclk to 50Mhz for DCN35 Reviewed-by: Nicholas Kazlauskas Signed-off-by: Nicholas Susanto Signed-off-by: Roman Li Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c | 3 +++ drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c | 1 + 2 files changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c index e2d906327e2ed..0ce9b40dfc68d 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c @@ -305,6 +305,9 @@ void dcn35_update_clocks(struct clk_mgr *clk_mgr_base, if (new_clocks->dtbclk_en && !new_clocks->ref_dtbclk_khz) new_clocks->ref_dtbclk_khz = 600000; + if (dc->debug.min_disp_clk_khz > 0 && new_clocks->dispclk_khz < dc->debug.min_disp_clk_khz) + new_clocks->dispclk_khz = dc->debug.min_disp_clk_khz; + /* * if it is safe to lower, but we are already in the lower state, we don't have to do anything * also if safe to lower is false, we just go in the higher state diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c index 5f3705f97bd74..46ad684fe1920 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c @@ -786,6 +786,7 @@ static const struct dc_debug_options debug_defaults_drv = { .disable_dmub_reallow_idle = false, .static_screen_wait_frames = 2, .disable_timeout = true, + .min_disp_clk_khz = 50000, }; static const struct dc_panel_config panel_config_defaults = { From 705b43f2b771acf2c99a2a6ae2e796b6870e98e5 Mon Sep 17 00:00:00 2001 From: Tim Huang Date: Thu, 15 Aug 2024 18:45:22 -0400 Subject: [PATCH 1367/1868] drm/amd/display: fix double free issue during amdgpu module unload Flexible endpoints use DIGs from available inflexible endpoints, so only the encoders of inflexible links need to be freed. Otherwise, a double free issue may occur when unloading the amdgpu module. [ 279.190523] RIP: 0010:__slab_free+0x152/0x2f0 [ 279.190577] Call Trace: [ 279.190580] [ 279.190582] ? show_regs+0x69/0x80 [ 279.190590] ? die+0x3b/0x90 [ 279.190595] ? do_trap+0xc8/0xe0 [ 279.190601] ? do_error_trap+0x73/0xa0 [ 279.190605] ? __slab_free+0x152/0x2f0 [ 279.190609] ? exc_invalid_op+0x56/0x70 [ 279.190616] ? __slab_free+0x152/0x2f0 [ 279.190642] ? asm_exc_invalid_op+0x1f/0x30 [ 279.190648] ? dcn10_link_encoder_destroy+0x19/0x30 [amdgpu] [ 279.191096] ? __slab_free+0x152/0x2f0 [ 279.191102] ? dcn10_link_encoder_destroy+0x19/0x30 [amdgpu] [ 279.191469] kfree+0x260/0x2b0 [ 279.191474] dcn10_link_encoder_destroy+0x19/0x30 [amdgpu] [ 279.191821] link_destroy+0xd7/0x130 [amdgpu] [ 279.192248] dc_destruct+0x90/0x270 [amdgpu] [ 279.192666] dc_destroy+0x19/0x40 [amdgpu] [ 279.193020] amdgpu_dm_fini+0x16e/0x200 [amdgpu] [ 279.193432] dm_hw_fini+0x26/0x40 [amdgpu] [ 279.193795] amdgpu_device_fini_hw+0x24c/0x400 [amdgpu] [ 279.194108] amdgpu_driver_unload_kms+0x4f/0x70 [amdgpu] [ 279.194436] amdgpu_pci_remove+0x40/0x80 [amdgpu] [ 279.194632] pci_device_remove+0x3a/0xa0 [ 279.194638] device_remove+0x40/0x70 [ 279.194642] device_release_driver_internal+0x1ad/0x210 [ 279.194647] driver_detach+0x4e/0xa0 [ 279.194650] bus_remove_driver+0x6f/0xf0 [ 279.194653] driver_unregister+0x33/0x60 [ 279.194657] pci_unregister_driver+0x44/0x90 [ 279.194662] amdgpu_exit+0x19/0x1f0 [amdgpu] [ 279.194939] __do_sys_delete_module.isra.0+0x198/0x2f0 [ 279.194946] __x64_sys_delete_module+0x16/0x20 [ 279.194950] do_syscall_64+0x58/0x120 [ 279.194954] entry_SYSCALL_64_after_hwframe+0x6e/0x76 [ 279.194980] Reviewed-by: Rodrigo Siqueira Signed-off-by: Tim Huang Reviewed-by: Roman Li Signed-off-by: Roman Li Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/link/link_factory.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/link/link_factory.c b/drivers/gpu/drm/amd/display/dc/link/link_factory.c index 85fd6e4222380..5e1b5ab9fbc63 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_factory.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_factory.c @@ -385,7 +385,7 @@ static void link_destruct(struct dc_link *link) if (link->panel_cntl) link->panel_cntl->funcs->destroy(&link->panel_cntl); - if (link->link_enc) { + if (link->link_enc && !link->is_dig_mapping_flexible) { /* Update link encoder resource tracking variables. These are used for * the dynamic assignment of link encoders to streams. Virtual links * are not assigned encoder resources on creation. From ff815823112bf320b78cbea7b3c7eb24e8813f28 Mon Sep 17 00:00:00 2001 From: Austin Zheng Date: Thu, 15 Aug 2024 18:45:23 -0400 Subject: [PATCH 1368/1868] drm/amd/display: DML2.1 Reintegration for Various Fixes [Why and How] DML2.1 reintegration for several fixes and updates to the DML code. Reviewed-by: Dillon Varone Signed-off-by: Austin Zheng Signed-off-by: Roman Li --- drivers/gpu/drm/amd/display/dc/dml2/Makefile | 3 - .../dml21/inc/bounding_boxes/dcn4_soc_bb.h | 2 +- .../dml21/inc/dml_top_soc_parameter_types.h | 1 + .../dml2/dml21/src/dml2_core/dml2_core_dcn4.c | 1 - .../src/dml2_core/dml2_core_dcn4_calcs.c | 478 +++++++------ .../dml21/src/dml2_core/dml2_core_factory.c | 2 +- .../dml21/src/dml2_core/dml2_core_shared.h | 37 - .../src/dml2_core/dml2_core_shared_types.h | 22 +- .../dml21/src/dml2_core/dml2_core_utils.c | 631 ++++++++++++++++++ .../dml21/src/dml2_core/dml2_core_utils.h | 39 ++ .../dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c | 54 +- .../dml21/src/dml2_dpmm/dml2_dpmm_factory.c | 2 +- .../dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c | 20 +- .../dml21/src/dml2_pmo/dml2_pmo_factory.c | 2 +- 14 files changed, 1009 insertions(+), 285 deletions(-) delete mode 100644 drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared.h create mode 100644 drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c create mode 100644 drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.h diff --git a/drivers/gpu/drm/amd/display/dc/dml2/Makefile b/drivers/gpu/drm/amd/display/dc/dml2/Makefile index 2817d92a402ae..fe66c2ee676aa 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dml2/Makefile @@ -117,7 +117,6 @@ CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_top/dml2_top_optimization := $(dml2_ CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.o := $(dml2_ccflags) CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.o := $(dml2_ccflags) $(frame_warn_flag) CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_core/dml2_core_factory.o := $(dml2_ccflags) -CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_core/dml2_core_shared.o := $(dml2_ccflags) $(frame_warn_flag) CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.o := $(dml2_ccflags) CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_factory.o := $(dml2_ccflags) CFLAGS_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_dcn4.o := $(dml2_ccflags) @@ -139,7 +138,6 @@ CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_top/dml2_top_optimization.o : CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.o := $(dml2_rcflags) CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.o := $(dml2_rcflags) CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_core/dml2_core_factory.o := $(dml2_rcflags) -CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_core/dml2_core_shared.o := $(dml2_rcflags) CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.o := $(dml2_rcflags) CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_factory.o := $(dml2_rcflags) CFLAGS_REMOVE_$(AMDDALPATH)/dc/dml2/dml21/src/dml2_mcg/dml2_mcg_dcn4.o := $(dml2_rcflags) @@ -160,7 +158,6 @@ DML21 += src/inc/dml2_debug.o DML21 += src/dml2_core/dml2_core_dcn4.o DML21 += src/dml2_core/dml2_core_factory.o DML21 += src/dml2_core/dml2_core_dcn4_calcs.o -DML21 += src/dml2_core/dml2_core_shared.o DML21 += src/dml2_dpmm/dml2_dpmm_dcn4.o DML21 += src/dml2_dpmm/dml2_dpmm_factory.o DML21 += src/dml2_mcg/dml2_mcg_dcn4.o diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/bounding_boxes/dcn4_soc_bb.h b/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/bounding_boxes/dcn4_soc_bb.h index 898b1dd69edd8..8ef7977841de0 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/bounding_boxes/dcn4_soc_bb.h +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/bounding_boxes/dcn4_soc_bb.h @@ -355,7 +355,7 @@ static const struct dml2_ip_capabilities dml2_dcn401_max_ip_caps = { .fams2 = { .max_allow_delay_us = 100 * 1000, .scheduling_delay_us = 125, - .vertical_interrupt_ack_delay_us = 18, + .vertical_interrupt_ack_delay_us = 40, .allow_programming_delay_us = 18, .min_allow_width_us = 20, .subvp_df_throttle_delay_us = 100, diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_soc_parameter_types.h b/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_soc_parameter_types.h index 4a46b21c3e554..ebd8abe894a9a 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_soc_parameter_types.h +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_soc_parameter_types.h @@ -151,6 +151,7 @@ struct dml2_soc_bb { double phy_downspread_percent; double dcn_downspread_percent; double dispclk_dppclk_vco_speed_mhz; + bool no_dfs; bool do_urgent_latency_adjustment; unsigned int mem_word_bytes; unsigned int num_dcc_mcaches; diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c index 9375c6ae11475..698307f3ca39d 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c @@ -273,7 +273,6 @@ static void pack_mode_programming_params_with_implicit_subvp(struct dml2_core_in programming->fams2_required = display_cfg->stage3.fams2_required; dml2_core_calcs_get_global_fams2_programming(&core->clean_me_up.mode_lib, display_cfg, &programming->fams2_global_config); - programming->fams2_global_config.features.bits.enable = display_cfg->stage3.fams2_required; } // Only loop over all the main streams (the implicit svp streams will be packed as part of the main stream) diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c index c3c4d8d9525ce..e2c45e498664e 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c @@ -8,32 +8,55 @@ #include "dml2_debug.h" #include "lib_float_math.h" #include "dml_top_types.h" -#include "dml2_core_shared.h" -//#define DML_TVM_UPDATE_EN #define DML2_MAX_FMT_420_BUFFER_WIDTH 4096 #define DML_MAX_NUM_OF_SLICES_PER_DSC 4 -static void dml2_print_dml_mode_support_info(const struct dml2_core_internal_mode_support_info *support, bool fail_only) +const char *dml2_core_internal_bw_type_str(enum dml2_core_internal_bw_type bw_type) +{ + switch (bw_type) { + case (dml2_core_internal_bw_sdp): + return("dml2_core_internal_bw_sdp"); + case (dml2_core_internal_bw_dram): + return("dml2_core_internal_bw_dram"); + case (dml2_core_internal_bw_max): + return("dml2_core_internal_bw_max"); + default: + return("dml2_core_internal_bw_unknown"); + } +} + +const char *dml2_core_internal_soc_state_type_str(enum dml2_core_internal_soc_state_type dml2_core_internal_soc_state_type) +{ + switch (dml2_core_internal_soc_state_type) { + case (dml2_core_internal_soc_state_sys_idle): + return("dml2_core_internal_soc_state_sys_idle"); + case (dml2_core_internal_soc_state_sys_active): + return("dml2_core_internal_soc_state_sys_active"); + case (dml2_core_internal_soc_state_svp_prefetch): + return("dml2_core_internal_soc_state_svp_prefetch"); + case dml2_core_internal_soc_state_max: + default: + return("dml2_core_internal_soc_state_unknown"); + } +} + +static double dml2_core_div_rem(double dividend, unsigned int divisor, unsigned int *remainder) +{ + *remainder = ((dividend / divisor) - (int)(dividend / divisor) > 0); + return dividend / divisor; +} + +static void dml2_print_mode_support_info(const struct dml2_core_internal_mode_support_info *support, bool fail_only) { dml2_printf("DML: ===================================== \n"); dml2_printf("DML: DML_MODE_SUPPORT_INFO_ST\n"); - if (!fail_only || support->ImmediateFlipSupport == 0) - dml2_printf("DML: support: ImmediateFlipSupport = %d\n", support->ImmediateFlipSupport); - if (!fail_only || support->WritebackLatencySupport == 0) - dml2_printf("DML: support: WritebackLatencySupport = %d\n", support->WritebackLatencySupport); if (!fail_only || support->ScaleRatioAndTapsSupport == 0) dml2_printf("DML: support: ScaleRatioAndTapsSupport = %d\n", support->ScaleRatioAndTapsSupport); if (!fail_only || support->SourceFormatPixelAndScanSupport == 0) dml2_printf("DML: support: SourceFormatPixelAndScanSupport = %d\n", support->SourceFormatPixelAndScanSupport); - if (!fail_only || support->P2IWith420 == 1) - dml2_printf("DML: support: P2IWith420 = %d\n", support->P2IWith420); - if (!fail_only || support->DSCOnlyIfNecessaryWithBPP == 1) - dml2_printf("DML: support: DSCOnlyIfNecessaryWithBPP = %d\n", support->DSCOnlyIfNecessaryWithBPP); - if (!fail_only || support->DSC422NativeNotSupported == 1) - dml2_printf("DML: support: DSC422NativeNotSupported = %d\n", support->DSC422NativeNotSupported); - if (!fail_only || support->DSCSlicesODMModeSupported == 0) - dml2_printf("DML: support: DSCSlicesODMModeSupported = %d\n", support->DSCSlicesODMModeSupported); + if (!fail_only || support->ViewportSizeSupport == 0) + dml2_printf("DML: support: ViewportSizeSupport = %d\n", support->ViewportSizeSupport); if (!fail_only || support->LinkRateDoesNotMatchDPVersion == 1) dml2_printf("DML: support: LinkRateDoesNotMatchDPVersion = %d\n", support->LinkRateDoesNotMatchDPVersion); if (!fail_only || support->LinkRateForMultistreamNotIndicated == 1) @@ -42,74 +65,87 @@ static void dml2_print_dml_mode_support_info(const struct dml2_core_internal_mod dml2_printf("DML: support: BPPForMultistreamNotIndicated = %d\n", support->BPPForMultistreamNotIndicated); if (!fail_only || support->MultistreamWithHDMIOreDP == 1) dml2_printf("DML: support: MultistreamWithHDMIOreDP = %d\n", support->MultistreamWithHDMIOreDP); + if (!fail_only || support->ExceededMultistreamSlots == 1) + dml2_printf("DML: support: ExceededMultistreamSlots = %d\n", support->ExceededMultistreamSlots); if (!fail_only || support->MSOOrODMSplitWithNonDPLink == 1) dml2_printf("DML: support: MSOOrODMSplitWithNonDPLink = %d\n", support->MSOOrODMSplitWithNonDPLink); if (!fail_only || support->NotEnoughLanesForMSO == 1) dml2_printf("DML: support: NotEnoughLanesForMSO = %d\n", support->NotEnoughLanesForMSO); - if (!fail_only || support->NumberOfOTGSupport == 0) - dml2_printf("DML: support: NumberOfOTGSupport = %d\n", support->NumberOfOTGSupport); - if (!fail_only || support->NumberOfHDMIFRLSupport == 0) - dml2_printf("DML: support: NumberOfHDMIFRLSupport = %d\n", support->NumberOfHDMIFRLSupport); - if (!fail_only || support->NumberOfDP2p0Support == 0) - dml2_printf("DML: support: NumberOfDP2p0Support = %d\n", support->NumberOfDP2p0Support); - if (!fail_only || support->WritebackScaleRatioAndTapsSupport == 0) - dml2_printf("DML: support: WritebackScaleRatioAndTapsSupport = %d\n", support->WritebackScaleRatioAndTapsSupport); - if (!fail_only || support->CursorSupport == 0) - dml2_printf("DML: support: CursorSupport = %d\n", support->CursorSupport); - if (!fail_only || support->PitchSupport == 0) - dml2_printf("DML: support: PitchSupport = %d\n", support->PitchSupport); - if (!fail_only || support->ViewportExceedsSurface == 1) - dml2_printf("DML: support: ViewportExceedsSurface = %d\n", support->ViewportExceedsSurface); - if (!fail_only || support->ExceededMALLSize == 1) - dml2_printf("DML: support: ExceededMALLSize = %d\n", support->ExceededMALLSize); - if (!fail_only || support->EnoughWritebackUnits == 0) - dml2_printf("DML: support: EnoughWritebackUnits = %d\n", support->EnoughWritebackUnits); - if (!fail_only || support->ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe == 1) - dml2_printf("DML: support: ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe = %d\n", support->ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe); - if (!fail_only || support->InvalidCombinationOfMALLUseForPStateAndStaticScreen == 1) - dml2_printf("DML: support: InvalidCombinationOfMALLUseForPStateAndStaticScreen = %d\n", support->InvalidCombinationOfMALLUseForPStateAndStaticScreen); - if (!fail_only || support->InvalidCombinationOfMALLUseForPState == 1) - dml2_printf("DML: support: InvalidCombinationOfMALLUseForPState = %d\n", support->InvalidCombinationOfMALLUseForPState); - if (!fail_only || support->ExceededMultistreamSlots == 1) - dml2_printf("DML: support: ExceededMultistreamSlots = %d\n", support->ExceededMultistreamSlots); + if (!fail_only || support->P2IWith420 == 1) + dml2_printf("DML: support: P2IWith420 = %d\n", support->P2IWith420); + if (!fail_only || support->DSC422NativeNotSupported == 1) + dml2_printf("DML: support: DSC422NativeNotSupported = %d\n", support->DSC422NativeNotSupported); + if (!fail_only || support->DSCSlicesODMModeSupported == 0) + dml2_printf("DML: support: DSCSlicesODMModeSupported = %d\n", support->DSCSlicesODMModeSupported); if (!fail_only || support->NotEnoughDSCUnits == 1) dml2_printf("DML: support: NotEnoughDSCUnits = %d\n", support->NotEnoughDSCUnits); if (!fail_only || support->NotEnoughDSCSlices == 1) dml2_printf("DML: support: NotEnoughDSCSlices = %d\n", support->NotEnoughDSCSlices); - if (!fail_only || support->PixelsPerLinePerDSCUnitSupport == 0) - dml2_printf("DML: support: PixelsPerLinePerDSCUnitSupport = %d\n", support->PixelsPerLinePerDSCUnitSupport); + if (!fail_only || support->ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe == 1) + dml2_printf("DML: support: ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe = %d\n", support->ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe); + if (!fail_only || support->InvalidCombinationOfMALLUseForPStateAndStaticScreen == 1) + dml2_printf("DML: support: InvalidCombinationOfMALLUseForPStateAndStaticScreen = %d\n", support->InvalidCombinationOfMALLUseForPStateAndStaticScreen); if (!fail_only || support->DSCCLKRequiredMoreThanSupported == 1) dml2_printf("DML: support: DSCCLKRequiredMoreThanSupported = %d\n", support->DSCCLKRequiredMoreThanSupported); + if (!fail_only || support->PixelsPerLinePerDSCUnitSupport == 0) + dml2_printf("DML: support: PixelsPerLinePerDSCUnitSupport = %d\n", support->PixelsPerLinePerDSCUnitSupport); if (!fail_only || support->DTBCLKRequiredMoreThanSupported == 1) dml2_printf("DML: support: DTBCLKRequiredMoreThanSupported = %d\n", support->DTBCLKRequiredMoreThanSupported); - if (!fail_only || support->LinkCapacitySupport == 0) - dml2_printf("DML: support: LinkCapacitySupport = %d\n", support->LinkCapacitySupport); + if (!fail_only || support->InvalidCombinationOfMALLUseForPState == 1) + dml2_printf("DML: support: InvalidCombinationOfMALLUseForPState = %d\n", support->InvalidCombinationOfMALLUseForPState); if (!fail_only || support->ROBSupport == 0) dml2_printf("DML: support: ROBSupport = %d\n", support->ROBSupport); if (!fail_only || support->OutstandingRequestsSupport == 0) dml2_printf("DML: support: OutstandingRequestsSupport = %d\n", support->OutstandingRequestsSupport); if (!fail_only || support->OutstandingRequestsUrgencyAvoidance == 0) dml2_printf("DML: support: OutstandingRequestsUrgencyAvoidance = %d\n", support->OutstandingRequestsUrgencyAvoidance); - if (!fail_only || support->PTEBufferSizeNotExceeded == 0) - dml2_printf("DML: support: PTEBufferSizeNotExceeded = %d\n", support->PTEBufferSizeNotExceeded); - if (!fail_only || support->AvgBandwidthSupport == 0) - dml2_printf("DML: support: AvgBandwidthSupport = %d\n", support->AvgBandwidthSupport); - if (!fail_only || support->EnoughUrgentLatencyHidingSupport == 0) - dml2_printf("DML: support: EnoughUrgentLatencyHidingSupport = %d\n", support->EnoughUrgentLatencyHidingSupport); + if (!fail_only || support->DISPCLK_DPPCLK_Support == 0) + dml2_printf("DML: support: DISPCLK_DPPCLK_Support = %d\n", support->DISPCLK_DPPCLK_Support); + if (!fail_only || support->TotalAvailablePipesSupport == 0) + dml2_printf("DML: support: TotalAvailablePipesSupport = %d\n", support->TotalAvailablePipesSupport); + if (!fail_only || support->NumberOfOTGSupport == 0) + dml2_printf("DML: support: NumberOfOTGSupport = %d\n", support->NumberOfOTGSupport); + if (!fail_only || support->NumberOfHDMIFRLSupport == 0) + dml2_printf("DML: support: NumberOfHDMIFRLSupport = %d\n", support->NumberOfHDMIFRLSupport); + if (!fail_only || support->NumberOfDP2p0Support == 0) + dml2_printf("DML: support: NumberOfDP2p0Support = %d\n", support->NumberOfDP2p0Support); + if (!fail_only || support->EnoughWritebackUnits == 0) + dml2_printf("DML: support: EnoughWritebackUnits = %d\n", support->EnoughWritebackUnits); + if (!fail_only || support->WritebackScaleRatioAndTapsSupport == 0) + dml2_printf("DML: support: WritebackScaleRatioAndTapsSupport = %d\n", support->WritebackScaleRatioAndTapsSupport); + if (!fail_only || support->WritebackLatencySupport == 0) + dml2_printf("DML: support: WritebackLatencySupport = %d\n", support->WritebackLatencySupport); + if (!fail_only || support->CursorSupport == 0) + dml2_printf("DML: support: CursorSupport = %d\n", support->CursorSupport); + if (!fail_only || support->PitchSupport == 0) + dml2_printf("DML: support: PitchSupport = %d\n", support->PitchSupport); + if (!fail_only || support->ViewportExceedsSurface == 1) + dml2_printf("DML: support: ViewportExceedsSurface = %d\n", support->ViewportExceedsSurface); if (!fail_only || support->PrefetchSupported == 0) dml2_printf("DML: support: PrefetchSupported = %d\n", support->PrefetchSupported); + if (!fail_only || support->EnoughUrgentLatencyHidingSupport == 0) + dml2_printf("DML: support: EnoughUrgentLatencyHidingSupport = %d\n", support->EnoughUrgentLatencyHidingSupport); + if (!fail_only || support->AvgBandwidthSupport == 0) + dml2_printf("DML: support: AvgBandwidthSupport = %d\n", support->AvgBandwidthSupport); if (!fail_only || support->DynamicMetadataSupported == 0) dml2_printf("DML: support: DynamicMetadataSupported = %d\n", support->DynamicMetadataSupported); if (!fail_only || support->VRatioInPrefetchSupported == 0) dml2_printf("DML: support: VRatioInPrefetchSupported = %d\n", support->VRatioInPrefetchSupported); - if (!fail_only || support->DISPCLK_DPPCLK_Support == 0) - dml2_printf("DML: support: DISPCLK_DPPCLK_Support = %d\n", support->DISPCLK_DPPCLK_Support); - if (!fail_only || support->TotalAvailablePipesSupport == 0) - dml2_printf("DML: support: TotalAvailablePipesSupport = %d\n", support->TotalAvailablePipesSupport); + if (!fail_only || support->PTEBufferSizeNotExceeded == 1) + dml2_printf("DML: support: PTEBufferSizeNotExceeded = %d\n", support->PTEBufferSizeNotExceeded); + if (!fail_only || support->DCCMetaBufferSizeNotExceeded == 1) + dml2_printf("DML: support: DCCMetaBufferSizeNotExceeded = %d\n", support->DCCMetaBufferSizeNotExceeded); + if (!fail_only || support->ExceededMALLSize == 1) + dml2_printf("DML: support: ExceededMALLSize = %d\n", support->ExceededMALLSize); + if (!fail_only || support->g6_temp_read_support == 0) + dml2_printf("DML: support: g6_temp_read_support = %d\n", support->g6_temp_read_support); + if (!fail_only || support->ImmediateFlipSupport == 0) + dml2_printf("DML: support: ImmediateFlipSupport = %d\n", support->ImmediateFlipSupport); + if (!fail_only || support->LinkCapacitySupport == 0) + dml2_printf("DML: support: LinkCapacitySupport = %d\n", support->LinkCapacitySupport); + if (!fail_only || support->ModeSupport == 0) dml2_printf("DML: support: ModeSupport = %d\n", support->ModeSupport); - if (!fail_only || support->ViewportSizeSupport == 0) - dml2_printf("DML: support: ViewportSizeSupport = %d\n", support->ViewportSizeSupport); dml2_printf("DML: ===================================== \n"); } @@ -2849,16 +2885,9 @@ static void CalculateVMRowAndSwath(struct dml2_core_internal_scratch *scratch, s->HostVMDynamicLevels = CalculateHostVMDynamicLevels(p->display_cfg->gpuvm_enable, p->display_cfg->hostvm_enable, p->HostVMMinPageSize, p->display_cfg->hostvm_max_non_cached_page_table_levels); for (unsigned int k = 0; k < p->NumberOfActiveSurfaces; ++k) { - if (p->display_cfg->hostvm_enable == true) { + if (p->display_cfg->gpuvm_enable == true) { p->vm_group_bytes[k] = 512; p->dpte_group_bytes[k] = 512; - } else if (p->display_cfg->gpuvm_enable == true) { - p->vm_group_bytes[k] = 2048; - if (p->display_cfg->plane_descriptors[k].overrides.gpuvm_min_page_size_kbytes >= 64 && dml_is_vertical_rotation(p->myPipe[k].RotationAngle)) { - p->dpte_group_bytes[k] = 512; - } else { - p->dpte_group_bytes[k] = 2048; - } } else { p->vm_group_bytes[k] = 0; p->dpte_group_bytes[k] = 0; @@ -4556,15 +4585,6 @@ static void calculate_tdlut_setting( return; } - - if (!p->setup_for_tdlut) { - *p->tdlut_groups_per_2row_ub = 0; - *p->tdlut_opt_time = 0; - *p->tdlut_drain_time = 0; - *p->tdlut_bytes_per_group = 0; - return; - } - if (p->tdlut_mpc_width_flag) { tdlut_mpc_width = 33; tdlut_bytes_per_group_simple = 39*256; @@ -4624,7 +4644,7 @@ static void calculate_tdlut_setting( //the tdlut is fetched during the 2 row times of prefetch. if (p->setup_for_tdlut) { - *p->tdlut_groups_per_2row_ub = (unsigned int)math_ceil2(*p->tdlut_bytes_per_frame / *p->tdlut_bytes_per_group, 1); + *p->tdlut_groups_per_2row_ub = (unsigned int)math_ceil2((double) *p->tdlut_bytes_per_frame / *p->tdlut_bytes_per_group, 1); *p->tdlut_opt_time = (*p->tdlut_bytes_per_frame - p->cursor_buffer_size * 1024) / tdlut_drain_rate; *p->tdlut_drain_time = p->cursor_buffer_size * 1024 / tdlut_drain_rate; } @@ -4637,7 +4657,7 @@ static void calculate_tdlut_setting( dml2_printf("DML::%s: dispclk_mhz = %f\n", __func__, p->dispclk_mhz); dml2_printf("DML::%s: tdlut_width = %u\n", __func__, tdlut_width); - dml2_printf("DML::%s: tdlut_addressing_mode = %u\n", __func__, p->tdlut_addressing_mode); + dml2_printf("DML::%s: tdlut_addressing_mode = %s\n", __func__, (p->tdlut_addressing_mode == dml2_tdlut_sw_linear) ? "sw_linear" : "simple_linear"); dml2_printf("DML::%s: tdlut_pitch_bytes = %u\n", __func__, tdlut_pitch_bytes); dml2_printf("DML::%s: tdlut_footprint_bytes = %u\n", __func__, tdlut_footprint_bytes); dml2_printf("DML::%s: tdlut_bytes_per_frame = %u\n", __func__, *p->tdlut_bytes_per_frame); @@ -4703,11 +4723,12 @@ static void CalculateTarb( static double CalculateTWait( long reserved_vblank_time_ns, double UrgentLatency, - double Ttrip) + double Ttrip, + double g6_temp_read_blackout_us) { double TWait; double t_urg_trip = math_max2(UrgentLatency, Ttrip); - TWait = reserved_vblank_time_ns/1000.0 + t_urg_trip; + TWait = math_max2(reserved_vblank_time_ns/1000.0, g6_temp_read_blackout_us) + t_urg_trip; #ifdef __DML_VBA_DEBUG__ dml2_printf("DML::%s: reserved_vblank_time_ns = %d\n", __func__, reserved_vblank_time_ns); @@ -4855,13 +4876,23 @@ static double get_urgent_bandwidth_required( } if (!exclude_this_plane) { - surface_required_bw[k] = math_max4(NumberOfDPP[k] * prefetch_vmrow_bw[k], - l->per_plane_flip_bw[k] + ReadBandwidthLuma[k] * l->adj_factor_p0 + ReadBandwidthChroma[k] * l->adj_factor_p1 + cursor_bw[k] * l->adj_factor_cur, - l->per_plane_flip_bw[k] + NumberOfDPP[k] * (PrefetchBandwidthLuma[k] * l->adj_factor_p0_pre + PrefetchBandwidthChroma[k] * l->adj_factor_p1_pre) + prefetch_cursor_bw[k] * l->adj_factor_cur_pre, - (ReadBandwidthLuma[k] + excess_vactive_fill_bw_l[k]) * l->tmp_nom_adj_factor_p0 + (ReadBandwidthChroma[k] + excess_vactive_fill_bw_c[k]) * l->tmp_nom_adj_factor_p1 + dpte_row_bw[k] + meta_row_bw[k]); + l->vm_row_bw = NumberOfDPP[k] * prefetch_vmrow_bw[k]; + l->flip_and_active_bw = l->per_plane_flip_bw[k] + ReadBandwidthLuma[k] * l->adj_factor_p0 + ReadBandwidthChroma[k] * l->adj_factor_p1 + cursor_bw[k] * l->adj_factor_cur; + l->flip_and_prefetch_bw = l->per_plane_flip_bw[k] + NumberOfDPP[k] * (PrefetchBandwidthLuma[k] * l->adj_factor_p0_pre + PrefetchBandwidthChroma[k] * l->adj_factor_p1_pre) + prefetch_cursor_bw[k] * l->adj_factor_cur_pre; + l->active_and_excess_bw = (ReadBandwidthLuma[k] + excess_vactive_fill_bw_l[k]) * l->tmp_nom_adj_factor_p0 + (ReadBandwidthChroma[k] + excess_vactive_fill_bw_c[k]) * l->tmp_nom_adj_factor_p1 + dpte_row_bw[k] + meta_row_bw[k]; + surface_required_bw[k] = math_max4(l->vm_row_bw, l->flip_and_active_bw, l->flip_and_prefetch_bw, l->active_and_excess_bw); /* export peak required bandwidth for the surface */ surface_peak_required_bw[k] = math_max2(surface_required_bw[k], surface_peak_required_bw[k]); + +#ifdef __DML_VBA_DEBUG__ + dml2_printf("DML::%s: k=%d, max1: vm_row_bw=%f\n", __func__, k, l->vm_row_bw); + dml2_printf("DML::%s: k=%d, max2: flip_and_active_bw=%f\n", __func__, k, l->flip_and_active_bw); + dml2_printf("DML::%s: k=%d, max3: flip_and_prefetch_bw=%f\n", __func__, k, l->flip_and_prefetch_bw); + dml2_printf("DML::%s: k=%d, max4: active_and_excess_bw=%f\n", __func__, k, l->active_and_excess_bw); + dml2_printf("DML::%s: k=%d, surface_required_bw=%f\n", __func__, k, surface_required_bw[k]); + dml2_printf("DML::%s: k=%d, surface_peak_required_bw=%f\n", __func__, k, surface_peak_required_bw[k]); +#endif } else { surface_required_bw[k] = 0.0; } @@ -4870,6 +4901,8 @@ static double get_urgent_bandwidth_required( #ifdef __DML_VBA_DEBUG__ dml2_printf("DML::%s: k=%d, NumberOfDPP=%d\n", __func__, k, NumberOfDPP[k]); + dml2_printf("DML::%s: k=%d, use_qual_row_bw=%d\n", __func__, k, use_qual_row_bw); + dml2_printf("DML::%s: k=%d, immediate_flip=%d\n", __func__, k, display_cfg->plane_descriptors[k].immediate_flip); dml2_printf("DML::%s: k=%d, mall_svp_prefetch_factor=%f\n", __func__, k, l->mall_svp_prefetch_factor); dml2_printf("DML::%s: k=%d, adj_factor_p0=%f\n", __func__, k, l->adj_factor_p0); dml2_printf("DML::%s: k=%d, adj_factor_p1=%f\n", __func__, k, l->adj_factor_p1); @@ -4883,6 +4916,8 @@ static double get_urgent_bandwidth_required( dml2_printf("DML::%s: k=%d, prefetch_vmrow_bw=%f\n", __func__, k, prefetch_vmrow_bw[k]); dml2_printf("DML::%s: k=%d, ReadBandwidthLuma=%f\n", __func__, k, ReadBandwidthLuma[k]); dml2_printf("DML::%s: k=%d, ReadBandwidthChroma=%f\n", __func__, k, ReadBandwidthChroma[k]); + dml2_printf("DML::%s: k=%d, excess_vactive_fill_bw_l=%f\n", __func__, k, excess_vactive_fill_bw_l[k]); + dml2_printf("DML::%s: k=%d, excess_vactive_fill_bw_c=%f\n", __func__, k, excess_vactive_fill_bw_c[k]); dml2_printf("DML::%s: k=%d, cursor_bw=%f\n", __func__, k, cursor_bw[k]); dml2_printf("DML::%s: k=%d, meta_row_bw=%f\n", __func__, k, meta_row_bw[k]); @@ -5037,7 +5072,9 @@ static bool CalculatePrefetchSchedule(struct dml2_core_internal_scratch *scratch s->bytes_pp = 0.0; s->dep_bytes = 0.0; s->min_Lsw_oto = 0.0; + s->min_Lsw_equ = 0.0; s->Tsw_est1 = 0.0; + s->Tsw_est2 = 0.0; s->Tsw_est3 = 0.0; s->cursor_prefetch_bytes = 0; *p->prefetch_cursor_bw = 0; @@ -5059,7 +5096,6 @@ static bool CalculatePrefetchSchedule(struct dml2_core_internal_scratch *scratch dml2_printf("DML::%s: GPUVMPageTableLevels = %u\n", __func__, p->display_cfg->gpuvm_max_page_table_levels); dml2_printf("DML::%s: DCCEnable = %u\n", __func__, p->myPipe->DCCEnable); dml2_printf("DML::%s: VStartup = %u\n", __func__, p->VStartup); - dml2_printf("DML::%s: MaxVStartup = %u\n", __func__, p->MaxVStartup); dml2_printf("DML::%s: HostVMEnable = %u\n", __func__, p->display_cfg->hostvm_enable); dml2_printf("DML::%s: HostVMInefficiencyFactor = %f\n", __func__, p->HostVMInefficiencyFactor); dml2_printf("DML::%s: TWait = %f\n", __func__, p->TWait); @@ -5092,21 +5128,15 @@ static bool CalculatePrefetchSchedule(struct dml2_core_internal_scratch *scratch s->LineTime = p->myPipe->HTotal / p->myPipe->PixelClock; s->trip_to_mem = p->Ttrip; -#ifdef DML_TVM_UPDATE_EN *p->Tvm_trips = p->ExtraLatencyPrefetch + math_max2(s->trip_to_mem * (p->display_cfg->gpuvm_max_page_table_levels * (s->HostVMDynamicLevelsTrips + 1)), p->Turg); if (dcc_mrq_enable) *p->Tvm_trips_flip = *p->Tvm_trips; else *p->Tvm_trips_flip = *p->Tvm_trips - s->trip_to_mem; -#else - *p->Tvm_trips = p->ExtraLatencyPrefetch + s->trip_to_mem * (p->display_cfg->gpuvm_max_page_table_levels * (s->HostVMDynamicLevelsTrips + 1)); - *p->Tvm_trips_flip = *p->Tvm_trips - s->trip_to_mem; -#endif *p->Tr0_trips_flip = s->trip_to_mem * (s->HostVMDynamicLevelsTrips + 1); *p->Tr0_trips = math_max2(*p->Tr0_trips_flip, p->tdlut_opt_time / 2); -#ifdef DML_TVM_UPDATE_EN if (p->DynamicMetadataVMEnabled == true) { *p->Tdmdl_vm = s->TWait_p + *p->Tvm_trips; *p->Tdmdl = *p->Tdmdl_vm + p->Ttrip; @@ -5114,15 +5144,6 @@ static bool CalculatePrefetchSchedule(struct dml2_core_internal_scratch *scratch *p->Tdmdl_vm = 0; *p->Tdmdl = s->TWait_p + p->ExtraLatencyPrefetch + p->Ttrip; // Tex } -#else - if (p->DynamicMetadataVMEnabled == true) { - *p->Tdmdl_vm = s->TWait_p + *p->Tvm_trips; - *p->Tdmdl = *p->Tdmdl_vm + p->Ttrip; - } else { - *p->Tdmdl_vm = 0; - *p->Tdmdl = p->TWait + p->ExtraLatencyPrefetch; // Tex - } -#endif if (p->DynamicMetadataEnable == true) { if (p->VStartup * s->LineTime < *p->TSetup + *p->Tdmdl + s->Tdmbf + s->Tdmec + s->Tdmsks) { @@ -5186,7 +5207,6 @@ static bool CalculatePrefetchSchedule(struct dml2_core_internal_scratch *scratch dml2_printf("DML::%s: DSTYAfterScaler = %u (final)\n", __func__, *p->DSTYAfterScaler); #endif - s->NoTimeToPrefetch = false; #ifdef __DML_VBA_DEBUG__ dml2_printf("DML::%s: Tr0_trips = %f\n", __func__, *p->Tr0_trips); dml2_printf("DML::%s: Tvm_trips = %f\n", __func__, *p->Tvm_trips); @@ -5199,14 +5219,10 @@ static bool CalculatePrefetchSchedule(struct dml2_core_internal_scratch *scratch s->Tvm_trips_rounded = math_ceil2(4.0 * *p->Tvm_trips / s->LineTime, 1.0) / 4.0 * s->LineTime; *p->Tvm_trips_flip_rounded = math_ceil2(4.0 * *p->Tvm_trips_flip / s->LineTime, 1.0) / 4.0 * s->LineTime; } else { -#ifdef DML_TVM_UPDATE_EN if (p->DynamicMetadataEnable || dcc_mrq_enable || p->setup_for_tdlut) s->Tvm_trips_rounded = math_max2(s->LineTime * math_ceil2(4.0*math_max3(p->ExtraLatencyPrefetch, p->Turg, s->trip_to_mem)/s->LineTime, 1)/4, s->LineTime/4.0); else - s->Tvm_trips_rounded = s->LineTime / 4.0; -#else - s->Tvm_trips_rounded = s->LineTime / 4.0; -#endif + s->Tvm_trips_rounded = s->LineTime / 4.0; *p->Tvm_trips_flip_rounded = s->LineTime / 4.0; } @@ -5235,16 +5251,10 @@ static bool CalculatePrefetchSchedule(struct dml2_core_internal_scratch *scratch *p->Tno_bw = 0; } -#ifdef DML_TVM_UPDATE_EN if (p->mrq_present || p->display_cfg->gpuvm_max_page_table_levels >= 3) *p->Tno_bw_flip = *p->Tno_bw; else *p->Tno_bw_flip = 0; //because there is no 3DLUT for iFlip -#else - *p->Tno_bw_flip = 0; - if (p->display_cfg->gpuvm_enable == true) - *p->Tno_bw_flip = *p->Tno_bw; -#endif if (dml_is_420(p->myPipe->SourcePixelFormat)) { s->bytes_pp = p->myPipe->BytePerPixelY + p->myPipe->BytePerPixelC / 4.0; @@ -5266,6 +5276,10 @@ static bool CalculatePrefetchSchedule(struct dml2_core_internal_scratch *scratch s->min_Lsw_oto = math_max2(s->min_Lsw_oto, 2.0); s->min_Lsw_oto = math_max2(s->min_Lsw_oto, p->tdlut_drain_time / s->LineTime); + s->min_Lsw_equ = math_max2(p->PrefetchSourceLinesY, p->PrefetchSourceLinesC) / __DML2_CALCS_MAX_VRATIO_PRE_EQU__; + s->min_Lsw_equ = math_max2(s->min_Lsw_equ, 2.0); + s->min_Lsw_equ = math_max2(s->min_Lsw_equ, p->tdlut_drain_time / s->LineTime); + vm_bytes = p->vm_bytes; // vm_bytes is dpde0_bytes_per_frame_ub_l + dpde0_bytes_per_frame_ub_c + 2*extra_dpde_bytes; extra_tdpe_bytes = (unsigned int)math_max2(0, (p->display_cfg->gpuvm_max_page_table_levels - 1) * 128); @@ -5289,11 +5303,7 @@ static bool CalculatePrefetchSchedule(struct dml2_core_internal_scratch *scratch dml2_printf("DML::%s: Tvm_oto max2 = %f\n", __func__, s->LineTime / 4.0); #endif } else { -#ifdef DML_TVM_UPDATE_EN s->Tvm_oto = s->Tvm_trips_rounded; -#else - s->Tvm_oto = s->LineTime / 4.0; -#endif } if ((p->display_cfg->gpuvm_enable == true || p->setup_for_tdlut || dcc_mrq_enable)) { @@ -5317,19 +5327,16 @@ static bool CalculatePrefetchSchedule(struct dml2_core_internal_scratch *scratch Lo = (unsigned int)(*p->DSTYAfterScaler + (double)*p->DSTXAfterScaler / (double)p->myPipe->HTotal); //Tpre_equ in line time -#ifdef DML_TVM_UPDATE_EN if (p->DynamicMetadataVMEnabled && p->DynamicMetadataEnable) s->dst_y_prefetch_equ = p->VStartup - (*p->TSetup + math_max2(p->TCalc, *p->Tvm_trips) + s->TWait_p) / s->LineTime - Lo; else s->dst_y_prefetch_equ = p->VStartup - (*p->TSetup + math_max2(p->TCalc, p->ExtraLatencyPrefetch) + s->TWait_p) / s->LineTime - Lo; -#else - s->dst_y_prefetch_equ = p->VStartup - (*p->TSetup + math_max2(s->TWait_p + p->TCalc, *p->Tdmdl - p->Ttrip)) / s->LineTime - Lo; -#endif s->dst_y_prefetch_equ = math_min2(s->dst_y_prefetch_equ, 63.75); // limit to the reg limit of U6.2 for DST_Y_PREFETCH #ifdef __DML_VBA_DEBUG__ dml2_printf("DML::%s: HTotal = %u\n", __func__, p->myPipe->HTotal); dml2_printf("DML::%s: min_Lsw_oto = %f\n", __func__, s->min_Lsw_oto); + dml2_printf("DML::%s: min_Lsw_equ = %f\n", __func__, s->min_Lsw_equ); dml2_printf("DML::%s: Tno_bw = %f\n", __func__, *p->Tno_bw); dml2_printf("DML::%s: Tno_bw_flip = %f\n", __func__, *p->Tno_bw_flip); dml2_printf("DML::%s: ExtraLatencyPrefetch = %f\n", __func__, p->ExtraLatencyPrefetch); @@ -5367,6 +5374,7 @@ static bool CalculatePrefetchSchedule(struct dml2_core_internal_scratch *scratch s->dst_y_prefetch_equ = math_floor2(4.0 * (s->dst_y_prefetch_equ + 0.125), 1) / 4.0; s->Tpre_rounded = s->dst_y_prefetch_equ * s->LineTime; +#ifdef __DML_VBA_DEBUG__ dml2_printf("DML::%s: dst_y_prefetch_equ: %f (after round)\n", __func__, s->dst_y_prefetch_equ); dml2_printf("DML::%s: LineTime: %f\n", __func__, s->LineTime); dml2_printf("DML::%s: VStartup: %u\n", __func__, p->VStartup); @@ -5387,18 +5395,12 @@ static bool CalculatePrefetchSchedule(struct dml2_core_internal_scratch *scratch dml2_printf("DML::%s: Ttrip: %fus\n", __func__, p->Ttrip); dml2_printf("DML::%s: DSTXAfterScaler: %u pixels - number of pixel clocks pipeline and buffer delay after scaler \n", __func__, *p->DSTXAfterScaler); dml2_printf("DML::%s: DSTYAfterScaler: %u lines - number of lines of pipeline and buffer delay after scaler \n", __func__, *p->DSTYAfterScaler); - - s->dep_bytes = math_max2(vm_bytes * p->HostVMInefficiencyFactor, p->PixelPTEBytesPerRow * p->HostVMInefficiencyFactor + p->meta_row_bytes + tdlut_row_bytes); - - dml2_printf("DML::%s: dep_bytes: %f\n", __func__, s->dep_bytes); - dml2_printf("DML::%s: prefetch_sw_bytes: %f\n", __func__, s->prefetch_sw_bytes); dml2_printf("DML::%s: vm_bytes: %f (hvm inefficiency scaled)\n", __func__, vm_bytes*p->HostVMInefficiencyFactor); dml2_printf("DML::%s: row_bytes: %f (hvm inefficiency scaled, 1 row)\n", __func__, p->PixelPTEBytesPerRow*p->HostVMInefficiencyFactor+p->meta_row_bytes+tdlut_row_bytes); - - if (s->prefetch_sw_bytes < s->dep_bytes) { - s->prefetch_sw_bytes = 2 * s->dep_bytes; - dml2_printf("DML::%s: bump prefetch_sw_bytes to %f\n", __func__, s->prefetch_sw_bytes); - } + dml2_printf("DML::%s: Tno_bw: %f\n", __func__, *p->Tno_bw); + dml2_printf("DML::%s: Tpre=%f Tpre_rounded: %f, delta=%f\n", __func__, Tpre, s->Tpre_rounded, (s->Tpre_rounded - Tpre)); + dml2_printf("DML::%s: Tvm_trips=%f Tvm_trips_rounded: %f, delta=%f\n", __func__, *p->Tvm_trips, s->Tvm_trips_rounded, (s->Tvm_trips_rounded - *p->Tvm_trips)); +#endif *p->dst_y_per_vm_vblank = 0; *p->dst_y_per_row_vblank = 0; @@ -5411,7 +5413,9 @@ static bool CalculatePrefetchSchedule(struct dml2_core_internal_scratch *scratch // Tvm_trips_rounded is Tvm_trips ceiling to 1/4 line time // Tr0_trips_rounded is Tr0_trips ceiling to 1/4 line time // So that means prefetch bw calculated can be higher since the total time availabe for prefetch is less - if (s->dst_y_prefetch_equ > 1) { + bool min_Lsw_equ_ok = s->Tpre_rounded >= s->Tvm_trips_rounded + 2.0*s->Tr0_trips_rounded + s->min_Lsw_equ*s->LineTime; + + if (s->dst_y_prefetch_equ > 1 && min_Lsw_equ_ok) { s->prefetch_bw1 = 0.; s->prefetch_bw2 = 0.; s->prefetch_bw3 = 0.; @@ -5428,28 +5432,35 @@ static bool CalculatePrefetchSchedule(struct dml2_core_internal_scratch *scratch s->prefetch_bw1 = 0; dml2_printf("DML::%s: prefetch_bw1: %f\n", __func__, s->prefetch_bw1); - if ((p->VStartup == p->MaxVStartup) && (s->Tsw_est1 / s->LineTime < s->min_Lsw_oto) && (s->Tpre_rounded - s->min_Lsw_oto * s->LineTime - 0.75 * s->LineTime - *p->Tno_bw > 0)) { + if ((s->Tsw_est1 < s->min_Lsw_equ * s->LineTime) && (s->Tpre_rounded - s->min_Lsw_equ * s->LineTime - 0.75 * s->LineTime - *p->Tno_bw > 0)) { s->prefetch_bw1 = (vm_bytes * p->HostVMInefficiencyFactor + 2 * (p->PixelPTEBytesPerRow * p->HostVMInefficiencyFactor + p->meta_row_bytes + tdlut_row_bytes)) / - (s->Tpre_rounded - s->min_Lsw_oto * s->LineTime - 0.75 * s->LineTime - *p->Tno_bw); + (s->Tpre_rounded - s->min_Lsw_equ * s->LineTime - 0.75 * s->LineTime - *p->Tno_bw); #ifdef __DML_VBA_DEBUG__ dml2_printf("DML::%s: vm and 2 rows bytes = %f\n", __func__, (vm_bytes * p->HostVMInefficiencyFactor + 2 * (p->PixelPTEBytesPerRow * p->HostVMInefficiencyFactor + p->meta_row_bytes + tdlut_row_bytes))); dml2_printf("DML::%s: Tpre_rounded = %f\n", __func__, s->Tpre_rounded); - dml2_printf("DML::%s: minus term = %f\n", __func__, s->min_Lsw_oto * s->LineTime + 0.75 * s->LineTime + *p->Tno_bw); - dml2_printf("DML::%s: min_Lsw_oto = %f\n", __func__, s->min_Lsw_oto); + dml2_printf("DML::%s: minus term = %f\n", __func__, s->min_Lsw_equ * s->LineTime + 0.75 * s->LineTime + *p->Tno_bw); + dml2_printf("DML::%s: min_Lsw_equ = %f\n", __func__, s->min_Lsw_equ); dml2_printf("DML::%s: LineTime = %f\n", __func__, s->LineTime); dml2_printf("DML::%s: Tno_bw = %f\n", __func__, *p->Tno_bw); - dml2_printf("DML::%s: Time to fetch vm and 2 rows = %f\n", __func__, (s->Tpre_rounded - s->min_Lsw_oto * s->LineTime - 0.75 * s->LineTime - *p->Tno_bw)); + dml2_printf("DML::%s: Time to fetch vm and 2 rows = %f\n", __func__, (s->Tpre_rounded - s->min_Lsw_equ * s->LineTime - 0.75 * s->LineTime - *p->Tno_bw)); dml2_printf("DML::%s: prefetch_bw1: %f (updated)\n", __func__, s->prefetch_bw1); #endif } // prefetch_bw2: VM + SW - if (s->Tpre_rounded - *p->Tno_bw - 2 * s->Tr0_trips_rounded > 0) + if (s->Tpre_rounded - *p->Tno_bw - 2.0 * s->Tr0_trips_rounded > 0) { s->prefetch_bw2 = (vm_bytes * p->HostVMInefficiencyFactor + s->prefetch_sw_bytes) / - (s->Tpre_rounded - *p->Tno_bw - 2 * s->Tr0_trips_rounded); - else + (s->Tpre_rounded - *p->Tno_bw - 2.0 * s->Tr0_trips_rounded); + s->Tsw_est2 = s->prefetch_sw_bytes / s->prefetch_bw2; + } else s->prefetch_bw2 = 0; + dml2_printf("DML::%s: prefetch_bw2: %f\n", __func__, s->prefetch_bw2); + if ((s->Tsw_est2 < s->min_Lsw_equ * s->LineTime) && ((s->Tpre_rounded - *p->Tno_bw - 2.0 * s->Tr0_trips_rounded - s->min_Lsw_equ * s->LineTime - 0.25 * s->LineTime) > 0)) { + s->prefetch_bw2 = vm_bytes * p->HostVMInefficiencyFactor / (s->Tpre_rounded - *p->Tno_bw - 2.0 * s->Tr0_trips_rounded - s->min_Lsw_equ * s->LineTime - 0.25 * s->LineTime); + dml2_printf("DML::%s: prefetch_bw2: %f (updated)\n", __func__, s->prefetch_bw2); + } + // prefetch_bw3: 2*R0 + SW if (s->Tpre_rounded - s->Tvm_trips_rounded > 0) { s->prefetch_bw3 = (2 * (p->PixelPTEBytesPerRow * p->HostVMInefficiencyFactor + p->meta_row_bytes + tdlut_row_bytes) + s->prefetch_sw_bytes) / @@ -5459,8 +5470,8 @@ static bool CalculatePrefetchSchedule(struct dml2_core_internal_scratch *scratch s->prefetch_bw3 = 0; dml2_printf("DML::%s: prefetch_bw3: %f\n", __func__, s->prefetch_bw3); - if (p->VStartup == p->MaxVStartup && (s->Tsw_est3 / s->LineTime < s->min_Lsw_oto) && ((s->Tpre_rounded - s->min_Lsw_oto * s->LineTime - 0.5 * s->LineTime - s->Tvm_trips_rounded) > 0)) { - s->prefetch_bw3 = (2 * (p->PixelPTEBytesPerRow * p->HostVMInefficiencyFactor + p->meta_row_bytes + tdlut_row_bytes)) / (s->Tpre_rounded - s->min_Lsw_oto * s->LineTime - 0.5 * s->LineTime - s->Tvm_trips_rounded); + if ((s->Tsw_est3 < s->min_Lsw_equ * s->LineTime) && ((s->Tpre_rounded - s->min_Lsw_equ * s->LineTime - 0.5 * s->LineTime - s->Tvm_trips_rounded) > 0)) { + s->prefetch_bw3 = (2 * (p->PixelPTEBytesPerRow * p->HostVMInefficiencyFactor + p->meta_row_bytes + tdlut_row_bytes)) / (s->Tpre_rounded - s->min_Lsw_equ * s->LineTime - 0.5 * s->LineTime - s->Tvm_trips_rounded); dml2_printf("DML::%s: prefetch_bw3: %f (updated)\n", __func__, s->prefetch_bw3); } @@ -5476,6 +5487,7 @@ static bool CalculatePrefetchSchedule(struct dml2_core_internal_scratch *scratch dml2_printf("DML::%s: Tvm_trips=%f Tvm_trips_rounded: %f, delta=%f\n", __func__, *p->Tvm_trips, s->Tvm_trips_rounded, (s->Tvm_trips_rounded - *p->Tvm_trips)); dml2_printf("DML::%s: Tr0_trips=%f Tr0_trips_rounded: %f, delta=%f\n", __func__, *p->Tr0_trips, s->Tr0_trips_rounded, (s->Tr0_trips_rounded - *p->Tr0_trips)); dml2_printf("DML::%s: Tsw_est1: %f\n", __func__, s->Tsw_est1); + dml2_printf("DML::%s: Tsw_est2: %f\n", __func__, s->Tsw_est2); dml2_printf("DML::%s: Tsw_est3: %f\n", __func__, s->Tsw_est3); dml2_printf("DML::%s: prefetch_bw1: %f (final)\n", __func__, s->prefetch_bw1); dml2_printf("DML::%s: prefetch_bw2: %f (final)\n", __func__, s->prefetch_bw2); @@ -5496,9 +5508,18 @@ static bool CalculatePrefetchSchedule(struct dml2_core_internal_scratch *scratch // here is to make sure equ bw wont be more agressive than the latency-based requirement. // check vm time >= vm_trips // check r0 time >= r0_trips + + double total_row_bytes = (p->PixelPTEBytesPerRow * p->HostVMInefficiencyFactor + p->meta_row_bytes + tdlut_row_bytes); + + dml2_printf("DML::%s: Tvm_trips_rounded = %f\n", __func__, s->Tvm_trips_rounded); + dml2_printf("DML::%s: Tr0_trips_rounded = %f\n", __func__, s->Tr0_trips_rounded); + if (s->prefetch_bw1 > 0) { - if (*p->Tno_bw + vm_bytes * p->HostVMInefficiencyFactor / s->prefetch_bw1 >= s->Tvm_trips_rounded && - (p->PixelPTEBytesPerRow * p->HostVMInefficiencyFactor + p->meta_row_bytes + tdlut_row_bytes) / s->prefetch_bw1 >= s->Tr0_trips_rounded) { + double vm_transfer_time = *p->Tno_bw + vm_bytes * p->HostVMInefficiencyFactor / s->prefetch_bw1; + double row_transfer_time = total_row_bytes / s->prefetch_bw1; + dml2_printf("DML::%s: Case1: vm_transfer_time = %f\n", __func__, vm_transfer_time); + dml2_printf("DML::%s: Case1: row_transfer_time = %f\n", __func__, row_transfer_time); + if (vm_transfer_time >= s->Tvm_trips_rounded && row_transfer_time >= s->Tr0_trips_rounded) { Case1OK = true; } } @@ -5508,8 +5529,11 @@ static bool CalculatePrefetchSchedule(struct dml2_core_internal_scratch *scratch // check vm time >= vm_trips // check r0 time < r0_trips if (s->prefetch_bw2 > 0) { - if (*p->Tno_bw + vm_bytes * p->HostVMInefficiencyFactor / s->prefetch_bw2 >= s->Tvm_trips_rounded && - (p->PixelPTEBytesPerRow * p->HostVMInefficiencyFactor + p->meta_row_bytes + tdlut_row_bytes) / s->prefetch_bw2 < s->Tr0_trips_rounded) { + double vm_transfer_time = *p->Tno_bw + vm_bytes * p->HostVMInefficiencyFactor / s->prefetch_bw2; + double row_transfer_time = total_row_bytes / s->prefetch_bw2; + dml2_printf("DML::%s: Case2: vm_transfer_time = %f\n", __func__, vm_transfer_time); + dml2_printf("DML::%s: Case2: row_transfer_time = %f\n", __func__, row_transfer_time); + if (vm_transfer_time >= s->Tvm_trips_rounded && row_transfer_time < s->Tr0_trips_rounded) { Case2OK = true; } } @@ -5518,8 +5542,11 @@ static bool CalculatePrefetchSchedule(struct dml2_core_internal_scratch *scratch // check vm time < vm_trips // check r0 time >= r0_trips if (s->prefetch_bw3 > 0) { - if (*p->Tno_bw + vm_bytes * p->HostVMInefficiencyFactor / s->prefetch_bw3 < s->Tvm_trips_rounded && - (p->PixelPTEBytesPerRow * p->HostVMInefficiencyFactor + p->meta_row_bytes + tdlut_row_bytes) / s->prefetch_bw3 >= s->Tr0_trips_rounded) { + double vm_transfer_time = *p->Tno_bw + vm_bytes * p->HostVMInefficiencyFactor / s->prefetch_bw3; + double row_transfer_time = total_row_bytes / s->prefetch_bw3; + dml2_printf("DML::%s: Case3: vm_transfer_time = %f\n", __func__, vm_transfer_time); + dml2_printf("DML::%s: Case3: row_transfer_time = %f\n", __func__, row_transfer_time); + if (vm_transfer_time < s->Tvm_trips_rounded && row_transfer_time >= s->Tr0_trips_rounded) { Case3OK = true; } } @@ -5585,13 +5612,9 @@ static bool CalculatePrefetchSchedule(struct dml2_core_internal_scratch *scratch s->TimeForFetchingVM = s->Tvm_equ; s->TimeForFetchingRowInVBlank = s->Tr0_equ; - if (p->VStartup == p->MaxVStartup) { - *p->dst_y_per_vm_vblank = math_floor2(4.0 * s->TimeForFetchingVM / s->LineTime, 1.0) / 4.0; - *p->dst_y_per_row_vblank = math_floor2(4.0 * s->TimeForFetchingRowInVBlank / s->LineTime, 1.0) / 4.0; - } else { - *p->dst_y_per_vm_vblank = math_ceil2(4.0 * s->TimeForFetchingVM / s->LineTime, 1.0) / 4.0; - *p->dst_y_per_row_vblank = math_ceil2(4.0 * s->TimeForFetchingRowInVBlank / s->LineTime, 1.0) / 4.0; - } + *p->dst_y_per_vm_vblank = math_ceil2(4.0 * s->TimeForFetchingVM / s->LineTime, 1.0) / 4.0; + *p->dst_y_per_row_vblank = math_ceil2(4.0 * s->TimeForFetchingRowInVBlank / s->LineTime, 1.0) / 4.0; + #ifdef __DML_VBA_DEBUG__ dml2_printf("DML::%s: Using equ bw scheduling for prefetch\n", __func__); #endif @@ -5635,7 +5658,7 @@ static bool CalculatePrefetchSchedule(struct dml2_core_internal_scratch *scratch (double)p->MaxNumSwathY * p->SwathHeightY / (s->LinesToRequestPrefetchPixelData - (p->VInitPreFillY - 3.0) / 2.0)); } else { s->NoTimeToPrefetch = true; - dml2_printf("DML::%s: MyErr set. LinesToRequestPrefetchPixelData=%f VinitPreFillY=%u\n", __func__, s->LinesToRequestPrefetchPixelData, p->VInitPreFillY); + dml2_printf("DML::%s: No time to prefetch!. LinesToRequestPrefetchPixelData=%f VinitPreFillY=%u\n", __func__, s->LinesToRequestPrefetchPixelData, p->VInitPreFillY); *p->VRatioPrefetchY = 0; } #ifdef __DML_VBA_DEBUG__ @@ -5658,7 +5681,7 @@ static bool CalculatePrefetchSchedule(struct dml2_core_internal_scratch *scratch *p->VRatioPrefetchC = math_max2(*p->VRatioPrefetchC, (double)p->MaxNumSwathC * p->SwathHeightC / (s->LinesToRequestPrefetchPixelData - (p->VInitPreFillC - 3.0) / 2.0)); } else { s->NoTimeToPrefetch = true; - dml2_printf("DML::%s: MyErr set. LinesToRequestPrefetchPixelData=%f VInitPreFillC=%u\n", __func__, s->LinesToRequestPrefetchPixelData, p->VInitPreFillC); + dml2_printf("DML::%s: No time to prefetch!. LinesToRequestPrefetchPixelData=%f VInitPreFillC=%u\n", __func__, s->LinesToRequestPrefetchPixelData, p->VInitPreFillC); *p->VRatioPrefetchC = 0; } #ifdef __DML_VBA_DEBUG__ @@ -5680,14 +5703,13 @@ static bool CalculatePrefetchSchedule(struct dml2_core_internal_scratch *scratch #endif } else { s->NoTimeToPrefetch = true; - dml2_printf("DML::%s: MyErr set, LinesToRequestPrefetchPixelData: %f, should be >= %d\n", __func__, s->LinesToRequestPrefetchPixelData, min_lsw_required); - dml2_printf("DML::%s: MyErr set, prefetch_bw_equ: %f, should be > 0\n", __func__, s->prefetch_bw_equ); + dml2_printf("DML::%s: No time to prefetch!, LinesToRequestPrefetchPixelData: %f, should be >= %d\n", __func__, s->LinesToRequestPrefetchPixelData, min_lsw_required); + dml2_printf("DML::%s: No time to prefetch!, prefetch_bw_equ: %f, should be > 0\n", __func__, s->prefetch_bw_equ); *p->VRatioPrefetchY = 0; *p->VRatioPrefetchC = 0; *p->RequiredPrefetchPixelDataBWLuma = 0; *p->RequiredPrefetchPixelDataBWChroma = 0; } - dml2_printf("DML: Tpre: %fus - sum of time to request 2 x data pte, swaths\n", (double)s->LinesToRequestPrefetchPixelData * s->LineTime + 2.0 * s->TimeForFetchingRowInVBlank + s->TimeForFetchingVM); dml2_printf("DML: Tvm: %fus - time to fetch vm\n", s->TimeForFetchingVM); dml2_printf("DML: Tr0: %fus - time to fetch first row of data pagetables\n", s->TimeForFetchingRowInVBlank); @@ -5698,7 +5720,9 @@ static bool CalculatePrefetchSchedule(struct dml2_core_internal_scratch *scratch dml2_printf("DML: row_bytes = dpte_row_bytes (per_pipe) = PixelPTEBytesPerRow = : %u\n", p->PixelPTEBytesPerRow); } else { - dml2_printf("DML::%s: MyErr set, dst_y_prefetch_equ = %f (should be > 1)\n", __func__, s->dst_y_prefetch_equ); + dml2_printf("DML::%s: No time to prefetch! dst_y_prefetch_equ = %f (should be > 1)\n", __func__, s->dst_y_prefetch_equ); + dml2_printf("DML::%s: No time to prefetch! min_Lsw_equ_ok = %d, Tpre_rounded (%f) should be >= Tvm_trips_rounded (%f) + 2.0*Tr0_trips_rounded (%f) + min_Tsw_equ (%f)\n", + __func__, min_Lsw_equ_ok, s->Tpre_rounded, s->Tvm_trips_rounded, 2.0*s->Tr0_trips_rounded, s->min_Lsw_equ*s->LineTime); s->NoTimeToPrefetch = true; s->TimeForFetchingVM = 0; s->TimeForFetchingRowInVBlank = 0; @@ -5730,7 +5754,7 @@ static bool CalculatePrefetchSchedule(struct dml2_core_internal_scratch *scratch } else { prefetch_vm_bw = 0; s->NoTimeToPrefetch = true; - dml2_printf("DML::%s: MyErr set. dst_y_per_vm_vblank=%f (should be > 0)\n", __func__, *p->dst_y_per_vm_vblank); + dml2_printf("DML::%s: No time to prefetch!. dst_y_per_vm_vblank=%f (should be > 0)\n", __func__, *p->dst_y_per_vm_vblank); } if (p->PixelPTEBytesPerRow == 0 && tdlut_row_bytes == 0) { @@ -5746,7 +5770,7 @@ static bool CalculatePrefetchSchedule(struct dml2_core_internal_scratch *scratch } else { prefetch_row_bw = 0; s->NoTimeToPrefetch = true; - dml2_printf("DML::%s: MyErr set. dst_y_per_row_vblank=%f (should be > 0)\n", __func__, *p->dst_y_per_row_vblank); + dml2_printf("DML::%s: No time to prefetch!. dst_y_per_row_vblank=%f (should be > 0)\n", __func__, *p->dst_y_per_row_vblank); } *p->prefetch_vmrow_bw = math_max2(prefetch_vm_bw, prefetch_row_bw); @@ -5763,11 +5787,16 @@ static bool CalculatePrefetchSchedule(struct dml2_core_internal_scratch *scratch *p->VRatioPrefetchC = 0; *p->RequiredPrefetchPixelDataBWLuma = 0; *p->RequiredPrefetchPixelDataBWChroma = 0; + *p->prefetch_vmrow_bw = 0; } dml2_printf("DML::%s: dst_y_per_vm_vblank = %f (final)\n", __func__, *p->dst_y_per_vm_vblank); dml2_printf("DML::%s: dst_y_per_row_vblank = %f (final)\n", __func__, *p->dst_y_per_row_vblank); + dml2_printf("DML::%s: prefetch_vmrow_bw = %f (final)\n", __func__, *p->prefetch_vmrow_bw); + dml2_printf("DML::%s: RequiredPrefetchPixelDataBWLuma = %f (final)\n", __func__, *p->RequiredPrefetchPixelDataBWLuma); + dml2_printf("DML::%s: RequiredPrefetchPixelDataBWChroma = %f (final)\n", __func__, *p->RequiredPrefetchPixelDataBWChroma); dml2_printf("DML::%s: NoTimeToPrefetch=%d\n", __func__, s->NoTimeToPrefetch); + return s->NoTimeToPrefetch; } @@ -6174,7 +6203,7 @@ static void CalculateFlipSchedule( { struct dml2_core_shared_CalculateFlipSchedule_locals *l = &s->CalculateFlipSchedule_locals; - l->dual_plane = dml2_core_shared_is_420(SourcePixelFormat) || SourcePixelFormat == dml2_rgbe_alpha; + l->dual_plane = dml_is_420(SourcePixelFormat) || SourcePixelFormat == dml2_rgbe_alpha; l->dpte_row_bytes = DPTEBytesPerRow; #ifdef __DML_VBA_DEBUG__ @@ -6250,7 +6279,7 @@ static void CalculateFlipSchedule( #ifdef __DML_VBA_DEBUG__ dml2_printf("DML::%s: max_flip_time = %f\n", __func__, l->max_flip_time); dml2_printf("DML::%s: total vm bytes (hvm ineff scaled) = %f\n", __func__, l->hvm_scaled_vm_bytes); - dml2_printf("DML::%s: total row bytes (hvm ineff scaled) = %f\n", __func__, l->hvm_scaled_row_bytes); + dml2_printf("DML::%s: total row bytes (%d row, hvm ineff scaled) = %f\n", __func__, l->num_rows, l->hvm_scaled_row_bytes); dml2_printf("DML::%s: total vm+row bytes (hvm ineff scaled) = %f\n", __func__, l->hvm_scaled_vm_row_bytes); dml2_printf("DML::%s: lb_flip_bw for vm and row = %f\n", __func__, l->hvm_scaled_vm_row_bytes / (l->max_flip_time - Tno_bw_flip)); dml2_printf("DML::%s: lb_flip_bw for vm = %f\n", __func__, l->hvm_scaled_vm_bytes / (l->max_flip_time - Tno_bw_flip - 2 * Tr0_trips_flip_rounded)); @@ -6261,6 +6290,7 @@ static void CalculateFlipSchedule( dml2_printf("DML::%s: mode_support est Tr0_flip = %f (bw-based)\n", __func__, l->hvm_scaled_row_bytes / l->lb_flip_bw / l->num_rows); dml2_printf("DML::%s: mode_support est dst_y_per_vm_flip = %f (bw-based)\n", __func__, Tno_bw_flip + l->hvm_scaled_vm_bytes / l->lb_flip_bw / LineTime); dml2_printf("DML::%s: mode_support est dst_y_per_row_flip = %f (bw-based)\n", __func__, l->hvm_scaled_row_bytes / l->lb_flip_bw / LineTime / l->num_rows); + dml2_printf("DML::%s: Tvm_trips_flip_rounded + 2*Tr0_trips_flip_rounded = %f\n", __func__, (Tvm_trips_flip_rounded + 2 * Tr0_trips_flip_rounded)); } #endif l->lb_flip_bw = math_max3(l->lb_flip_bw, @@ -6277,7 +6307,7 @@ static void CalculateFlipSchedule( *dst_y_per_vm_flip = 1; // not used *dst_y_per_row_flip = 1; // not used - *ImmediateFlipSupportedForPipe = true; + *ImmediateFlipSupportedForPipe = l->min_row_time >= (Tvm_trips_flip_rounded + 2 * Tr0_trips_flip_rounded); } else { if (iflip_enable) { l->ImmediateFlipBW = (double)per_pipe_flip_bytes * BandwidthAvailableForImmediateFlip / (double)TotImmediateFlipBytes; // flip_bw(i) @@ -6343,6 +6373,7 @@ static void CalculateFlipSchedule( dml2_printf("DML::%s: dst_y_per_row_flip = %f (should be < 16)\n", __func__, *dst_y_per_row_flip); dml2_printf("DML::%s: Tvm_flip = %f (final)\n", __func__, l->Tvm_flip); dml2_printf("DML::%s: Tr0_flip = %f (final)\n", __func__, l->Tr0_flip); + dml2_printf("DML::%s: Tvm_flip + 2*Tr0_flip = %f (should be <= min_row_time=%f)\n", __func__, l->Tvm_flip + 2 * l->Tr0_flip, l->min_row_time); } dml2_printf("DML::%s: final_flip_bw = %f\n", __func__, *final_flip_bw); dml2_printf("DML::%s: ImmediateFlipSupportedForPipe = %u\n", __func__, *ImmediateFlipSupportedForPipe); @@ -6373,6 +6404,12 @@ static void CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport( p->Watermark->StutterEnterPlusExitWatermark = p->mmSOCParameters.SREnterPlusExitTime + p->mmSOCParameters.ExtraLatency_sr + 10 / p->DCFClkDeepSleep; p->Watermark->Z8StutterExitWatermark = p->mmSOCParameters.SRExitZ8Time + p->mmSOCParameters.ExtraLatency_sr + 10 / p->DCFClkDeepSleep; p->Watermark->Z8StutterEnterPlusExitWatermark = p->mmSOCParameters.SREnterPlusExitZ8Time + p->mmSOCParameters.ExtraLatency_sr + 10 / p->DCFClkDeepSleep; + if (p->mmSOCParameters.qos_type == dml2_qos_param_type_dcn4x) { + p->Watermark->StutterExitWatermark += p->mmSOCParameters.max_urgent_latency_us + p->mmSOCParameters.df_response_time_us; + p->Watermark->StutterEnterPlusExitWatermark += p->mmSOCParameters.max_urgent_latency_us + p->mmSOCParameters.df_response_time_us; + p->Watermark->Z8StutterExitWatermark += p->mmSOCParameters.max_urgent_latency_us + p->mmSOCParameters.df_response_time_us; + p->Watermark->Z8StutterEnterPlusExitWatermark += p->mmSOCParameters.max_urgent_latency_us + p->mmSOCParameters.df_response_time_us; + } p->Watermark->g6_temp_read_watermark_us = p->mmSOCParameters.g6_temp_read_blackout_us + p->Watermark->UrgentWatermark; #ifdef __DML_VBA_DEBUG__ @@ -6579,13 +6616,13 @@ static void CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport( s->src_y_ahead_c = (unsigned int)(math_floor2(p->DETBufferSizeC[k] / p->BytePerPixelDETC[k] / p->SwathWidthC[k], p->SwathHeightC[k]) + s->LBLatencyHidingSourceLinesC[k]); s->sub_vp_lines_c = s->src_y_pstate_c + s->src_y_ahead_c + p->meta_row_height_c[k]; - if (dml2_core_shared_is_420(p->display_cfg->plane_descriptors[k].pixel_format)) + if (dml_is_420(p->display_cfg->plane_descriptors[k].pixel_format)) p->SubViewportLinesNeededInMALL[k] = (unsigned int)(math_max2(s->sub_vp_lines_l, 2 * s->sub_vp_lines_c)); else p->SubViewportLinesNeededInMALL[k] = (unsigned int)(math_max2(s->sub_vp_lines_l, s->sub_vp_lines_c)); #ifdef __DML_VBA_DEBUG__ - dml2_printf("DML::%s: k=%u, meta_row_height_c = %u\n", __func__, p->meta_row_height_c[k]); + dml2_printf("DML::%s: k=%u, meta_row_height_c = %u\n", __func__, k, p->meta_row_height_c[k]); dml2_printf("DML::%s: k=%u, src_y_pstate_c = %u\n", __func__, k, s->src_y_pstate_c); dml2_printf("DML::%s: k=%u, src_y_ahead_c = %u\n", __func__, k, s->src_y_ahead_c); dml2_printf("DML::%s: k=%u, sub_vp_lines_c = %u\n", __func__, k, s->sub_vp_lines_c); @@ -6915,6 +6952,21 @@ static double get_g6_temp_read_blackout_us( return (double)blackout_us; } +static double get_max_urgent_latency_us( + struct dml2_dcn4x_soc_qos_params *dcn4x, + double uclk_freq_mhz, + double FabricClock, + unsigned int min_clk_index) +{ + double latency; + latency = dcn4x->per_uclk_dpm_params[min_clk_index].maximum_latency_when_urgent_uclk_cycles / uclk_freq_mhz + * (1 + dcn4x->umc_max_latency_margin / 100.0) + + dcn4x->mall_overhead_fclk_cycles / FabricClock + + dcn4x->max_round_trip_to_furthest_cs_fclk_cycles / FabricClock + * (1 + dcn4x->fabric_max_transport_latency_margin / 100.0); + return latency; +} + static void calculate_pstate_keepout_dst_lines( const struct dml2_display_cfg *display_cfg, const struct dml2_core_internal_watermarks *watermarks, @@ -6997,7 +7049,6 @@ static bool dml_core_mode_support(struct dml2_core_calcs_mode_support_ex *in_out dml2_printf("DML::%s: max_dscclk_freq_mhz = %f\n", __func__, mode_lib->ms.max_dscclk_freq_mhz); dml2_printf("DML::%s: max_dppclk_freq_mhz = %f\n", __func__, mode_lib->ms.max_dppclk_freq_mhz); dml2_printf("DML::%s: MaxFabricClock = %f\n", __func__, mode_lib->ms.MaxFabricClock); - dml2_printf("DML::%s: max_dscclk_freq_mhz = %f\n", __func__, mode_lib->ms.max_dscclk_freq_mhz); dml2_printf("DML::%s: ip.compressed_buffer_segment_size_in_kbytes = %u\n", __func__, mode_lib->ip.compressed_buffer_segment_size_in_kbytes); dml2_printf("DML::%s: ip.dcn_mrq_present = %u\n", __func__, mode_lib->ip.dcn_mrq_present); @@ -7223,12 +7274,12 @@ static bool dml_core_mode_support(struct dml2_core_calcs_mode_support_ex *in_out } #endif */ - mode_lib->ms.MaximumSwathWidthInLineBufferLuma = lb_buffer_size_bits_luma * math_max2(display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_ratio, 1.0) / 57 /*FIXME_STAGE2 was: LBBitPerPixel*/ / + mode_lib->ms.MaximumSwathWidthInLineBufferLuma = lb_buffer_size_bits_luma * math_max2(display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_ratio, 1.0) / 57 / (display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_taps + math_max2(math_ceil2(display_cfg->plane_descriptors[k].composition.scaler_info.plane0.v_ratio, 1.0) - 2, 0.0)); if (mode_lib->ms.BytePerPixelC[k] == 0.0) { mode_lib->ms.MaximumSwathWidthInLineBufferChroma = 0; } else { - mode_lib->ms.MaximumSwathWidthInLineBufferChroma = lb_buffer_size_bits_chroma * math_max2(display_cfg->plane_descriptors[k].composition.scaler_info.plane1.h_ratio, 1.0) / 57 /*FIXME_STAGE2 was: LBBitPerPixel*/ / + mode_lib->ms.MaximumSwathWidthInLineBufferChroma = lb_buffer_size_bits_chroma * math_max2(display_cfg->plane_descriptors[k].composition.scaler_info.plane1.h_ratio, 1.0) / 57 / (display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_taps + math_max2(math_ceil2(display_cfg->plane_descriptors[k].composition.scaler_info.plane1.v_ratio, 1.0) - 2, 0.0)); } @@ -7310,7 +7361,8 @@ static bool dml_core_mode_support(struct dml2_core_calcs_mode_support_ex *in_out mode_lib->ms.support.ViewportExceedsSurface = false; if (!display_cfg->overrides.hw.surface_viewport_size_check_disable) { for (k = 0; k < mode_lib->ms.num_active_planes; k++) { - if (display_cfg->plane_descriptors[k].composition.viewport.plane0.width > display_cfg->plane_descriptors[k].surface.plane0.width || display_cfg->plane_descriptors[k].composition.viewport.plane0.height > display_cfg->plane_descriptors[k].surface.plane0.height) { + if (display_cfg->plane_descriptors[k].composition.viewport.plane0.width > display_cfg->plane_descriptors[k].surface.plane0.width || + display_cfg->plane_descriptors[k].composition.viewport.plane0.height > display_cfg->plane_descriptors[k].surface.plane0.height) { mode_lib->ms.support.ViewportExceedsSurface = true; #if defined(__DML_VBA_DEBUG__) dml2_printf("DML::%s: k=%u ViewportWidth = %d\n", __func__, k, display_cfg->plane_descriptors[k].composition.viewport.plane0.width); @@ -7319,11 +7371,11 @@ static bool dml_core_mode_support(struct dml2_core_calcs_mode_support_ex *in_out dml2_printf("DML::%s: k=%u SurfaceHeightY = %d\n", __func__, k, display_cfg->plane_descriptors[k].surface.plane0.height); dml2_printf("DML::%s: k=%u ViewportExceedsSurface = %d\n", __func__, k, mode_lib->ms.support.ViewportExceedsSurface); #endif - if (dml_is_420(display_cfg->plane_descriptors[k].pixel_format) || display_cfg->plane_descriptors[k].pixel_format == dml2_rgbe_alpha) { - if (display_cfg->plane_descriptors[k].composition.viewport.plane1.width > display_cfg->plane_descriptors[k].surface.plane1.width || - display_cfg->plane_descriptors[k].composition.viewport.plane1.height > display_cfg->plane_descriptors[k].surface.plane1.height) { - mode_lib->ms.support.ViewportExceedsSurface = true; - } + } + if (dml_is_420(display_cfg->plane_descriptors[k].pixel_format) || display_cfg->plane_descriptors[k].pixel_format == dml2_rgbe_alpha) { + if (display_cfg->plane_descriptors[k].composition.viewport.plane1.width > display_cfg->plane_descriptors[k].surface.plane1.width || + display_cfg->plane_descriptors[k].composition.viewport.plane1.height > display_cfg->plane_descriptors[k].surface.plane1.height) { + mode_lib->ms.support.ViewportExceedsSurface = true; } } } @@ -7599,7 +7651,7 @@ static bool dml_core_mode_support(struct dml2_core_calcs_mode_support_ex *in_out display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.scaling_info.h_taps, display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.scaling_info.v_taps, display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.scaling_info.input_width, - display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.scaling_info.output_height, + display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.scaling_info.output_width, display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_total, mode_lib->ip.writeback_line_buffer_buffer_size)); } @@ -7684,8 +7736,6 @@ static bool dml_core_mode_support(struct dml2_core_calcs_mode_support_ex *in_out if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_format == dml2_420 && display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.interlaced == 1 && mode_lib->ip.ptoi_supported == true) mode_lib->ms.support.P2IWith420 = true; - if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_enable_if_necessary && s->OutputBpp[k] != 0) - mode_lib->ms.support.DSCOnlyIfNecessaryWithBPP = true; if ((display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_enable || display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_enable_if_necessary) && display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_format == dml2_n422 && !mode_lib->ip.dsc422_native_support) mode_lib->ms.support.DSC422NativeNotSupported = true; @@ -8483,7 +8533,6 @@ static bool dml_core_mode_support(struct dml2_core_calcs_mode_support_ex *in_out { mode_lib->ms.TimeCalc = 24 / mode_lib->ms.dcfclk_deepsleep; - calculate_hostvm_inefficiency_factor( &s->HostVMInefficiencyFactor, &s->HostVMInefficiencyFactorPrefetch, @@ -8568,7 +8617,9 @@ static bool dml_core_mode_support(struct dml2_core_calcs_mode_support_ex *in_out mode_lib->ms.TWait[k] = CalculateTWait( display_cfg->plane_descriptors[k].overrides.reserved_vblank_time_ns, mode_lib->ms.UrgLatency, - mode_lib->ms.TripToMemory); + mode_lib->ms.TripToMemory, + !dml_is_phantom_pipe(&display_cfg->plane_descriptors[k]) && display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.drr_config.enabled ? + get_g6_temp_read_blackout_us(&mode_lib->soc, (unsigned int)(mode_lib->ms.uclk_freq_mhz * 1000), in_out_params->min_clk_index) : 0.0); myPipe->Dppclk = mode_lib->ms.RequiredDPPCLK[k]; myPipe->Dispclk = mode_lib->ms.RequiredDISPCLK; @@ -8615,7 +8666,6 @@ static bool dml_core_mode_support(struct dml2_core_calcs_mode_support_ex *in_out CalculatePrefetchSchedule_params->OutputFormat = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_format; CalculatePrefetchSchedule_params->MaxInterDCNTileRepeaters = mode_lib->ip.max_inter_dcn_tile_repeaters; CalculatePrefetchSchedule_params->VStartup = s->MaximumVStartup[k]; - CalculatePrefetchSchedule_params->MaxVStartup = s->MaximumVStartup[k]; CalculatePrefetchSchedule_params->HostVMMinPageSize = mode_lib->soc.hostvm_min_page_size_kbytes; CalculatePrefetchSchedule_params->DynamicMetadataEnable = display_cfg->plane_descriptors[k].dynamic_meta_data.enable; CalculatePrefetchSchedule_params->DynamicMetadataVMEnabled = mode_lib->ip.dynamic_metadata_vm_enabled; @@ -8697,8 +8747,8 @@ static bool dml_core_mode_support(struct dml2_core_calcs_mode_support_ex *in_out dml2_printf("DML::%s: k=%d, dst_y_prefetch=%f (should not be < 2)\n", __func__, k, mode_lib->ms.dst_y_prefetch[k]); dml2_printf("DML::%s: k=%d, LinesForVM=%f (should not be >= 32)\n", __func__, k, mode_lib->ms.LinesForVM[k]); dml2_printf("DML::%s: k=%d, LinesForDPTERow=%f (should not be >= 16)\n", __func__, k, mode_lib->ms.LinesForDPTERow[k]); - dml2_printf("DML::%s: k=%d, NoTimeForPrefetch=%d\n", __func__, k, mode_lib->ms.NoTimeForPrefetch[k]); dml2_printf("DML::%s: k=%d, DSTYAfterScaler=%d (should be <= 8)\n", __func__, k, s->DSTYAfterScaler[k]); + dml2_printf("DML::%s: k=%d, NoTimeForPrefetch=%d\n", __func__, k, mode_lib->ms.NoTimeForPrefetch[k]); } } @@ -8711,20 +8761,15 @@ static bool dml_core_mode_support(struct dml2_core_calcs_mode_support_ex *in_out mode_lib->ms.support.VRatioInPrefetchSupported = true; for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) { - if (mode_lib->ms.VRatioPreY[k] > __DML2_CALCS_MAX_VRATIO_PRE_ENHANCE_PREFETCH_ACC__ || - mode_lib->ms.VRatioPreC[k] > __DML2_CALCS_MAX_VRATIO_PRE_ENHANCE_PREFETCH_ACC__) { + if (mode_lib->ms.VRatioPreY[k] > __DML2_CALCS_MAX_VRATIO_PRE__ || + mode_lib->ms.VRatioPreC[k] > __DML2_CALCS_MAX_VRATIO_PRE__) { mode_lib->ms.support.VRatioInPrefetchSupported = false; + dml2_printf("DML::%s: k=%d VRatioPreY = %f (should be <= %f)\n", __func__, k, mode_lib->ms.VRatioPreY[k], __DML2_CALCS_MAX_VRATIO_PRE__); + dml2_printf("DML::%s: k=%d VRatioPreC = %f (should be <= %f)\n", __func__, k, mode_lib->ms.VRatioPreC[k], __DML2_CALCS_MAX_VRATIO_PRE__); dml2_printf("DML::%s: VRatioInPrefetchSupported = %u\n", __func__, mode_lib->ms.support.VRatioInPrefetchSupported); } } - s->AnyLinesForVMOrRowTooLarge = false; - for (k = 0; k < mode_lib->ms.num_active_planes; ++k) { - if (mode_lib->ms.LinesForDPTERow[k] >= 16 || mode_lib->ms.LinesForVM[k] >= 32) { - s->AnyLinesForVMOrRowTooLarge = true; - } - } - // Only do urg vs prefetch bandwidth check, flip schedule check, power saving feature support check IF the Prefetch Schedule Check is ok if (mode_lib->ms.support.PrefetchSupported) { for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) { @@ -8961,6 +9006,9 @@ static bool dml_core_mode_support(struct dml2_core_calcs_mode_support_ex *in_out s->mSOCParameters.USRRetrainingLatency = 0; s->mSOCParameters.SMNLatency = 0; s->mSOCParameters.g6_temp_read_blackout_us = get_g6_temp_read_blackout_us(&mode_lib->soc, (unsigned int)(mode_lib->ms.uclk_freq_mhz * 1000), in_out_params->min_clk_index); + s->mSOCParameters.max_urgent_latency_us = get_max_urgent_latency_us(&mode_lib->soc.qos_parameters.qos_params.dcn4x, mode_lib->ms.uclk_freq_mhz, mode_lib->ms.FabricClock, in_out_params->min_clk_index); + s->mSOCParameters.df_response_time_us = mode_lib->soc.qos_parameters.qos_params.dcn4x.df_qos_response_time_fclk_cycles / mode_lib->ms.FabricClock; + s->mSOCParameters.qos_type = mode_lib->soc.qos_parameters.qos_type; CalculateWatermarks_params->display_cfg = display_cfg; CalculateWatermarks_params->USRRetrainingRequired = false; @@ -8980,7 +9028,6 @@ static bool dml_core_mode_support(struct dml2_core_calcs_mode_support_ex *in_out CalculateWatermarks_params->DETBufferSizeC = mode_lib->ms.DETBufferSizeC; CalculateWatermarks_params->SwathHeightY = mode_lib->ms.SwathHeightY; CalculateWatermarks_params->SwathHeightC = mode_lib->ms.SwathHeightC; - //CalculateWatermarks_params->LBBitPerPixel = 57; // FIXME_STAGE2, need a new ip param? CalculateWatermarks_params->SwathWidthY = mode_lib->ms.SwathWidthY; CalculateWatermarks_params->SwathWidthC = mode_lib->ms.SwathWidthC; CalculateWatermarks_params->DPPPerSurface = mode_lib->ms.NoOfDPP; @@ -9011,22 +9058,15 @@ static bool dml_core_mode_support(struct dml2_core_calcs_mode_support_ex *in_out calculate_pstate_keepout_dst_lines(display_cfg, &mode_lib->ms.support.watermarks, s->dummy_integer_array[0]); } - + dml2_printf("DML::%s: Done prefetch calculation\n", __func__); // End of Prefetch Check - dml2_printf("DML::%s: Done prefetch calculation\n", __func__); + mode_lib->ms.support.max_urgent_latency_us = s->mSOCParameters.max_urgent_latency_us; //Re-ordering Buffer Support Check - mode_lib->ms.support.max_urgent_latency_us - = mode_lib->soc.qos_parameters.qos_params.dcn4x.per_uclk_dpm_params[mode_lib->ms.qos_param_index].maximum_latency_when_urgent_uclk_cycles / mode_lib->ms.uclk_freq_mhz - * (1 + mode_lib->soc.qos_parameters.qos_params.dcn4x.umc_max_latency_margin / 100.0) - + mode_lib->soc.qos_parameters.qos_params.dcn4x.mall_overhead_fclk_cycles / mode_lib->ms.FabricClock - + mode_lib->soc.qos_parameters.qos_params.dcn4x.max_round_trip_to_furthest_cs_fclk_cycles / mode_lib->ms.FabricClock - * (1 + mode_lib->soc.qos_parameters.qos_params.dcn4x.fabric_max_transport_latency_margin / 100.0); - if (mode_lib->soc.qos_parameters.qos_type == dml2_qos_param_type_dcn4x) { if (((mode_lib->ip.rob_buffer_size_kbytes - mode_lib->ip.pixel_chunk_size_kbytes) * 1024 - / mode_lib->ms.support.non_urg_bandwidth_required_flip[dml2_core_internal_soc_state_sys_active][dml2_core_internal_bw_sdp]) >= mode_lib->ms.support.max_urgent_latency_us) { + / mode_lib->ms.support.non_urg_bandwidth_required_flip[dml2_core_internal_soc_state_sys_active][dml2_core_internal_bw_sdp]) >= s->mSOCParameters.max_urgent_latency_us) { mode_lib->ms.support.ROBSupport = true; } else { mode_lib->ms.support.ROBSupport = false; @@ -9055,15 +9095,12 @@ static bool dml_core_mode_support(struct dml2_core_calcs_mode_support_ex *in_out mode_lib->ms.dram_change_vactive_det_fill_delay_us); #ifdef __DML_VBA_DEBUG__ - dml2_printf("DML::%s: max_urgent_latency_us = %f\n", __func__, mode_lib->ms.support.max_urgent_latency_us); + dml2_printf("DML::%s: max_urgent_latency_us = %f\n", __func__, s->mSOCParameters.max_urgent_latency_us); dml2_printf("DML::%s: ROBSupport = %u\n", __func__, mode_lib->ms.support.ROBSupport); #endif /*Mode Support, Voltage State and SOC Configuration*/ { - // s->dram_clock_change_support = 1; - // s->f_clock_change_support = 1; - if (mode_lib->ms.support.ScaleRatioAndTapsSupport && mode_lib->ms.support.SourceFormatPixelAndScanSupport && mode_lib->ms.support.ViewportSizeSupport @@ -9074,9 +9111,7 @@ static bool dml_core_mode_support(struct dml2_core_calcs_mode_support_ex *in_out && !mode_lib->ms.support.ExceededMultistreamSlots && !mode_lib->ms.support.MSOOrODMSplitWithNonDPLink && !mode_lib->ms.support.NotEnoughLanesForMSO - //&& mode_lib->ms.support.LinkCapacitySupport == true // FIXME_STAGE2 && !mode_lib->ms.support.P2IWith420 - && !mode_lib->ms.support.DSCOnlyIfNecessaryWithBPP && !mode_lib->ms.support.DSC422NativeNotSupported && mode_lib->ms.support.DSCSlicesODMModeSupported && !mode_lib->ms.support.NotEnoughDSCUnits @@ -9144,7 +9179,7 @@ static bool dml_core_mode_support(struct dml2_core_calcs_mode_support_ex *in_out #if defined(__DML_VBA_DEBUG__) if (!mode_lib->ms.support.ModeSupport) - dml2_print_dml_mode_support_info(&mode_lib->ms.support, true); + dml2_print_mode_support_info(&mode_lib->ms.support, true); dml2_printf("DML::%s: --- DONE --- \n", __func__); #endif @@ -9163,6 +9198,10 @@ unsigned int dml2_core_calcs_mode_support_ex(struct dml2_core_calcs_mode_support *in_out_params->out_evaluation_info = in_out_params->mode_lib->ms.support; dml2_printf("DML::%s: is_mode_support = %u (min_clk_index=%d)\n", __func__, result, in_out_params->min_clk_index); + + for (unsigned int k = 0; k < in_out_params->in_display_cfg->num_planes; k++) + dml2_printf("DML::%s: plane_%d: reserved_vblank_time_ns = %u\n", __func__, k, in_out_params->in_display_cfg->plane_descriptors[k].overrides.reserved_vblank_time_ns); + dml2_printf("DML::%s: ------------- DONE ----------\n", __func__); return result; @@ -10697,7 +10736,9 @@ static bool dml_core_mode_programming(struct dml2_core_calcs_mode_programming_ex mode_lib->mp.TWait[k] = CalculateTWait( display_cfg->plane_descriptors[k].overrides.reserved_vblank_time_ns, mode_lib->mp.UrgentLatency, - mode_lib->mp.TripToMemory); + mode_lib->mp.TripToMemory, + !dml_is_phantom_pipe(&display_cfg->plane_descriptors[k]) && display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.drr_config.enabled ? + get_g6_temp_read_blackout_us(&mode_lib->soc, (unsigned int)(mode_lib->ms.uclk_freq_mhz * 1000), in_out_params->min_clk_index) : 0.0); myPipe->Dppclk = mode_lib->mp.Dppclk[k]; myPipe->Dispclk = mode_lib->mp.Dispclk; @@ -10743,7 +10784,6 @@ static bool dml_core_mode_programming(struct dml2_core_calcs_mode_programming_ex CalculatePrefetchSchedule_params->OutputFormat = display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_format; CalculatePrefetchSchedule_params->MaxInterDCNTileRepeaters = mode_lib->ip.max_inter_dcn_tile_repeaters; CalculatePrefetchSchedule_params->VStartup = s->MaxVStartupLines[k]; - CalculatePrefetchSchedule_params->MaxVStartup = s->MaxVStartupLines[k]; CalculatePrefetchSchedule_params->HostVMMinPageSize = mode_lib->soc.hostvm_min_page_size_kbytes; CalculatePrefetchSchedule_params->DynamicMetadataEnable = display_cfg->plane_descriptors[k].dynamic_meta_data.enable; CalculatePrefetchSchedule_params->DynamicMetadataVMEnabled = mode_lib->ip.dynamic_metadata_vm_enabled; @@ -10829,9 +10869,13 @@ static bool dml_core_mode_programming(struct dml2_core_calcs_mode_programming_ex if (mode_lib->mp.dst_y_prefetch[k] < 2) s->DestinationLineTimesForPrefetchLessThan2 = true; - if (mode_lib->mp.VRatioPrefetchY[k] > __DML2_CALCS_MAX_VRATIO_PRE_ENHANCE_PREFETCH_ACC__ || - mode_lib->mp.VRatioPrefetchC[k] > __DML2_CALCS_MAX_VRATIO_PRE_ENHANCE_PREFETCH_ACC__) + if (mode_lib->mp.VRatioPrefetchY[k] > __DML2_CALCS_MAX_VRATIO_PRE__ || + mode_lib->mp.VRatioPrefetchC[k] > __DML2_CALCS_MAX_VRATIO_PRE__) { s->VRatioPrefetchMoreThanMax = true; + dml2_printf("DML::%s: k=%d, VRatioPrefetchY=%f (should not be < %f)\n", __func__, k, mode_lib->mp.VRatioPrefetchY[k], __DML2_CALCS_MAX_VRATIO_PRE__); + dml2_printf("DML::%s: k=%d, VRatioPrefetchC=%f (should not be < %f)\n", __func__, k, mode_lib->mp.VRatioPrefetchC[k], __DML2_CALCS_MAX_VRATIO_PRE__); + dml2_printf("DML::%s: VRatioPrefetchMoreThanMax = %u\n", __func__, s->VRatioPrefetchMoreThanMax); + } if (mode_lib->mp.NotEnoughUrgentLatencyHiding[k]) { dml2_printf("DML::%s: k=%u, NotEnoughUrgentLatencyHiding = %u\n", __func__, k, mode_lib->mp.NotEnoughUrgentLatencyHiding[k]); @@ -11165,6 +11209,9 @@ static bool dml_core_mode_programming(struct dml2_core_calcs_mode_programming_ex s->mmSOCParameters.USRRetrainingLatency = 0; s->mmSOCParameters.SMNLatency = 0; s->mmSOCParameters.g6_temp_read_blackout_us = get_g6_temp_read_blackout_us(&mode_lib->soc, (unsigned int)(mode_lib->mp.uclk_freq_mhz * 1000), in_out_params->min_clk_index); + s->mmSOCParameters.max_urgent_latency_us = get_max_urgent_latency_us(&mode_lib->soc.qos_parameters.qos_params.dcn4x, mode_lib->ms.uclk_freq_mhz, mode_lib->ms.FabricClock, in_out_params->min_clk_index); + s->mmSOCParameters.df_response_time_us = mode_lib->soc.qos_parameters.qos_params.dcn4x.df_qos_response_time_fclk_cycles / mode_lib->ms.FabricClock; + s->mmSOCParameters.qos_type = mode_lib->soc.qos_parameters.qos_type; CalculateWatermarks_params->display_cfg = display_cfg; CalculateWatermarks_params->USRRetrainingRequired = false; @@ -11184,7 +11231,6 @@ static bool dml_core_mode_programming(struct dml2_core_calcs_mode_programming_ex CalculateWatermarks_params->DETBufferSizeC = mode_lib->mp.DETBufferSizeC; CalculateWatermarks_params->SwathHeightY = mode_lib->mp.SwathHeightY; CalculateWatermarks_params->SwathHeightC = mode_lib->mp.SwathHeightC; - //CalculateWatermarks_params->LBBitPerPixel = 57; //FIXME_STAGE2 CalculateWatermarks_params->SwathWidthY = mode_lib->mp.SwathWidthY; CalculateWatermarks_params->SwathWidthC = mode_lib->mp.SwathWidthC; CalculateWatermarks_params->BytePerPixelDETY = mode_lib->mp.BytePerPixelInDETY; @@ -11515,9 +11561,9 @@ static bool dml_core_mode_programming(struct dml2_core_calcs_mode_programming_ex bool dml2_core_calcs_mode_programming_ex(struct dml2_core_calcs_mode_programming_ex *in_out_params) { + dml2_printf("DML::%s: ------------- START ----------\n", __func__); bool result = dml_core_mode_programming(in_out_params); - dml2_printf("DML::%s: ------------- START ----------\n", __func__); dml2_printf("DML::%s: result = %0d\n", __func__, result); dml2_printf("DML::%s: ------------- DONE ----------\n", __func__); return result; @@ -12427,7 +12473,7 @@ void dml2_core_calcs_get_stream_support_info(const struct dml2_display_cfg *disp phantom_processing_delay_pix = (double)((mode_lib->ip.subvp_fw_processing_delay_us + mode_lib->ip.subvp_pstate_allow_width_us) * ((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[plane_index].stream_index].timing.pixel_clock_khz / 1000)); phantom_processing_delay_lines = (unsigned int)(phantom_processing_delay_pix / (double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[plane_index].stream_index].timing.h_total); - dml2_core_shared_div_rem(phantom_processing_delay_pix, + dml2_core_div_rem(phantom_processing_delay_pix, display_cfg->stream_descriptors[display_cfg->plane_descriptors[plane_index].stream_index].timing.h_total, &rem); if (rem) @@ -12470,7 +12516,7 @@ void dml2_core_calcs_get_informative(const struct dml2_core_internal_display_mod out->informative.mode_support_info.ScaleRatioAndTapsSupport = mode_lib->ms.support.ScaleRatioAndTapsSupport; out->informative.mode_support_info.SourceFormatPixelAndScanSupport = mode_lib->ms.support.SourceFormatPixelAndScanSupport; out->informative.mode_support_info.P2IWith420 = mode_lib->ms.support.P2IWith420; - out->informative.mode_support_info.DSCOnlyIfNecessaryWithBPP = mode_lib->ms.support.DSCOnlyIfNecessaryWithBPP; + out->informative.mode_support_info.DSCOnlyIfNecessaryWithBPP = false; out->informative.mode_support_info.DSC422NativeNotSupported = mode_lib->ms.support.DSC422NativeNotSupported; out->informative.mode_support_info.LinkRateDoesNotMatchDPVersion = mode_lib->ms.support.LinkRateDoesNotMatchDPVersion; out->informative.mode_support_info.LinkRateForMultistreamNotIndicated = mode_lib->ms.support.LinkRateForMultistreamNotIndicated; diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_factory.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_factory.c index 640087e862f84..28394de028855 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_factory.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_factory.c @@ -10,7 +10,7 @@ bool dml2_core_create(enum dml2_project_id project_id, struct dml2_core_instance { bool result = false; - if (!out) + if (out == 0) return false; memset(out, 0, sizeof(struct dml2_core_instance)); diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared.h b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared.h deleted file mode 100644 index f3356b072b59e..0000000000000 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared.h +++ /dev/null @@ -1,37 +0,0 @@ -// SPDX-License-Identifier: MIT -// -// Copyright 2024 Advanced Micro Devices, Inc. - -#ifndef __DML2_CORE_SHARED_H__ -#define __DML2_CORE_SHARED_H__ - -#define __DML_VBA_DEBUG__ -#define __DML2_CALCS_MAX_VRATIO_PRE_OTO__ 4.0 // 0); + return dividend / divisor; + +} + +const char *dml2_core_utils_internal_bw_type_str(enum dml2_core_internal_bw_type bw_type) +{ + switch (bw_type) { + case (dml2_core_internal_bw_sdp): + return("dml2_core_internal_bw_sdp"); + case (dml2_core_internal_bw_dram): + return("dml2_core_internal_bw_dram"); + case (dml2_core_internal_bw_max): + return("dml2_core_internal_bw_max"); + default: + return("dml2_core_internal_bw_unknown"); + } +} + +bool dml2_core_utils_is_420(enum dml2_source_format_class source_format) +{ + bool val = false; + + switch (source_format) { + case dml2_444_8: + val = 0; + break; + case dml2_444_16: + val = 0; + break; + case dml2_444_32: + val = 0; + break; + case dml2_444_64: + val = 0; + break; + case dml2_420_8: + val = 1; + break; + case dml2_420_10: + val = 1; + break; + case dml2_420_12: + val = 1; + break; + case dml2_rgbe_alpha: + val = 0; + break; + case dml2_rgbe: + val = 0; + break; + case dml2_mono_8: + val = 0; + break; + case dml2_mono_16: + val = 0; + break; + default: + DML2_ASSERT(0); + break; + } + return val; +} + +void dml2_core_utils_print_mode_support_info(const struct dml2_core_internal_mode_support_info *support, bool fail_only) +{ + dml2_printf("DML: ===================================== \n"); + dml2_printf("DML: DML_MODE_SUPPORT_INFO_ST\n"); + if (!fail_only || support->ScaleRatioAndTapsSupport == 0) + dml2_printf("DML: support: ScaleRatioAndTapsSupport = %d\n", support->ScaleRatioAndTapsSupport); + if (!fail_only || support->SourceFormatPixelAndScanSupport == 0) + dml2_printf("DML: support: SourceFormatPixelAndScanSupport = %d\n", support->SourceFormatPixelAndScanSupport); + if (!fail_only || support->ViewportSizeSupport == 0) + dml2_printf("DML: support: ViewportSizeSupport = %d\n", support->ViewportSizeSupport); + if (!fail_only || support->LinkRateDoesNotMatchDPVersion == 1) + dml2_printf("DML: support: LinkRateDoesNotMatchDPVersion = %d\n", support->LinkRateDoesNotMatchDPVersion); + if (!fail_only || support->LinkRateForMultistreamNotIndicated == 1) + dml2_printf("DML: support: LinkRateForMultistreamNotIndicated = %d\n", support->LinkRateForMultistreamNotIndicated); + if (!fail_only || support->BPPForMultistreamNotIndicated == 1) + dml2_printf("DML: support: BPPForMultistreamNotIndicated = %d\n", support->BPPForMultistreamNotIndicated); + if (!fail_only || support->MultistreamWithHDMIOreDP == 1) + dml2_printf("DML: support: MultistreamWithHDMIOreDP = %d\n", support->MultistreamWithHDMIOreDP); + if (!fail_only || support->ExceededMultistreamSlots == 1) + dml2_printf("DML: support: ExceededMultistreamSlots = %d\n", support->ExceededMultistreamSlots); + if (!fail_only || support->MSOOrODMSplitWithNonDPLink == 1) + dml2_printf("DML: support: MSOOrODMSplitWithNonDPLink = %d\n", support->MSOOrODMSplitWithNonDPLink); + if (!fail_only || support->NotEnoughLanesForMSO == 1) + dml2_printf("DML: support: NotEnoughLanesForMSO = %d\n", support->NotEnoughLanesForMSO); + if (!fail_only || support->P2IWith420 == 1) + dml2_printf("DML: support: P2IWith420 = %d\n", support->P2IWith420); + if (!fail_only || support->DSC422NativeNotSupported == 1) + dml2_printf("DML: support: DSC422NativeNotSupported = %d\n", support->DSC422NativeNotSupported); + if (!fail_only || support->DSCSlicesODMModeSupported == 0) + dml2_printf("DML: support: DSCSlicesODMModeSupported = %d\n", support->DSCSlicesODMModeSupported); + if (!fail_only || support->NotEnoughDSCUnits == 1) + dml2_printf("DML: support: NotEnoughDSCUnits = %d\n", support->NotEnoughDSCUnits); + if (!fail_only || support->NotEnoughDSCSlices == 1) + dml2_printf("DML: support: NotEnoughDSCSlices = %d\n", support->NotEnoughDSCSlices); + if (!fail_only || support->ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe == 1) + dml2_printf("DML: support: ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe = %d\n", support->ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe); + if (!fail_only || support->InvalidCombinationOfMALLUseForPStateAndStaticScreen == 1) + dml2_printf("DML: support: InvalidCombinationOfMALLUseForPStateAndStaticScreen = %d\n", support->InvalidCombinationOfMALLUseForPStateAndStaticScreen); + if (!fail_only || support->DSCCLKRequiredMoreThanSupported == 1) + dml2_printf("DML: support: DSCCLKRequiredMoreThanSupported = %d\n", support->DSCCLKRequiredMoreThanSupported); + if (!fail_only || support->PixelsPerLinePerDSCUnitSupport == 0) + dml2_printf("DML: support: PixelsPerLinePerDSCUnitSupport = %d\n", support->PixelsPerLinePerDSCUnitSupport); + if (!fail_only || support->DTBCLKRequiredMoreThanSupported == 1) + dml2_printf("DML: support: DTBCLKRequiredMoreThanSupported = %d\n", support->DTBCLKRequiredMoreThanSupported); + if (!fail_only || support->InvalidCombinationOfMALLUseForPState == 1) + dml2_printf("DML: support: InvalidCombinationOfMALLUseForPState = %d\n", support->InvalidCombinationOfMALLUseForPState); + if (!fail_only || support->ROBSupport == 0) + dml2_printf("DML: support: ROBSupport = %d\n", support->ROBSupport); + if (!fail_only || support->OutstandingRequestsSupport == 0) + dml2_printf("DML: support: OutstandingRequestsSupport = %d\n", support->OutstandingRequestsSupport); + if (!fail_only || support->OutstandingRequestsUrgencyAvoidance == 0) + dml2_printf("DML: support: OutstandingRequestsUrgencyAvoidance = %d\n", support->OutstandingRequestsUrgencyAvoidance); + if (!fail_only || support->DISPCLK_DPPCLK_Support == 0) + dml2_printf("DML: support: DISPCLK_DPPCLK_Support = %d\n", support->DISPCLK_DPPCLK_Support); + if (!fail_only || support->TotalAvailablePipesSupport == 0) + dml2_printf("DML: support: TotalAvailablePipesSupport = %d\n", support->TotalAvailablePipesSupport); + if (!fail_only || support->NumberOfOTGSupport == 0) + dml2_printf("DML: support: NumberOfOTGSupport = %d\n", support->NumberOfOTGSupport); + if (!fail_only || support->NumberOfHDMIFRLSupport == 0) + dml2_printf("DML: support: NumberOfHDMIFRLSupport = %d\n", support->NumberOfHDMIFRLSupport); + if (!fail_only || support->NumberOfDP2p0Support == 0) + dml2_printf("DML: support: NumberOfDP2p0Support = %d\n", support->NumberOfDP2p0Support); + if (!fail_only || support->EnoughWritebackUnits == 0) + dml2_printf("DML: support: EnoughWritebackUnits = %d\n", support->EnoughWritebackUnits); + if (!fail_only || support->WritebackScaleRatioAndTapsSupport == 0) + dml2_printf("DML: support: WritebackScaleRatioAndTapsSupport = %d\n", support->WritebackScaleRatioAndTapsSupport); + if (!fail_only || support->WritebackLatencySupport == 0) + dml2_printf("DML: support: WritebackLatencySupport = %d\n", support->WritebackLatencySupport); + if (!fail_only || support->CursorSupport == 0) + dml2_printf("DML: support: CursorSupport = %d\n", support->CursorSupport); + if (!fail_only || support->PitchSupport == 0) + dml2_printf("DML: support: PitchSupport = %d\n", support->PitchSupport); + if (!fail_only || support->ViewportExceedsSurface == 1) + dml2_printf("DML: support: ViewportExceedsSurface = %d\n", support->ViewportExceedsSurface); + if (!fail_only || support->PrefetchSupported == 0) + dml2_printf("DML: support: PrefetchSupported = %d\n", support->PrefetchSupported); + if (!fail_only || support->EnoughUrgentLatencyHidingSupport == 0) + dml2_printf("DML: support: EnoughUrgentLatencyHidingSupport = %d\n", support->EnoughUrgentLatencyHidingSupport); + if (!fail_only || support->AvgBandwidthSupport == 0) + dml2_printf("DML: support: AvgBandwidthSupport = %d\n", support->AvgBandwidthSupport); + if (!fail_only || support->DynamicMetadataSupported == 0) + dml2_printf("DML: support: DynamicMetadataSupported = %d\n", support->DynamicMetadataSupported); + if (!fail_only || support->VRatioInPrefetchSupported == 0) + dml2_printf("DML: support: VRatioInPrefetchSupported = %d\n", support->VRatioInPrefetchSupported); + if (!fail_only || support->PTEBufferSizeNotExceeded == 1) + dml2_printf("DML: support: PTEBufferSizeNotExceeded = %d\n", support->PTEBufferSizeNotExceeded); + if (!fail_only || support->DCCMetaBufferSizeNotExceeded == 1) + dml2_printf("DML: support: DCCMetaBufferSizeNotExceeded = %d\n", support->DCCMetaBufferSizeNotExceeded); + if (!fail_only || support->ExceededMALLSize == 1) + dml2_printf("DML: support: ExceededMALLSize = %d\n", support->ExceededMALLSize); + if (!fail_only || support->g6_temp_read_support == 0) + dml2_printf("DML: support: g6_temp_read_support = %d\n", support->g6_temp_read_support); + if (!fail_only || support->ImmediateFlipSupport == 0) + dml2_printf("DML: support: ImmediateFlipSupport = %d\n", support->ImmediateFlipSupport); + if (!fail_only || support->LinkCapacitySupport == 0) + dml2_printf("DML: support: LinkCapacitySupport = %d\n", support->LinkCapacitySupport); + + if (!fail_only || support->ModeSupport == 0) + dml2_printf("DML: support: ModeSupport = %d\n", support->ModeSupport); + dml2_printf("DML: ===================================== \n"); +} + +const char *dml2_core_utils_internal_soc_state_type_str(enum dml2_core_internal_soc_state_type dml2_core_internal_soc_state_type) +{ + switch (dml2_core_internal_soc_state_type) { + case (dml2_core_internal_soc_state_sys_idle): + return("dml2_core_internal_soc_state_sys_idle"); + case (dml2_core_internal_soc_state_sys_active): + return("dml2_core_internal_soc_state_sys_active"); + case (dml2_core_internal_soc_state_svp_prefetch): + return("dml2_core_internal_soc_state_svp_prefetch"); + case dml2_core_internal_soc_state_max: + default: + return("dml2_core_internal_soc_state_unknown"); + } +} + + +void dml2_core_utils_get_stream_output_bpp(double *out_bpp, const struct dml2_display_cfg *display_cfg) +{ + for (unsigned int k = 0; k < display_cfg->num_planes; k++) { + double bpc = (double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.bpc; + if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_disable) { + switch (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].output.output_format) { + case dml2_444: + out_bpp[k] = bpc * 3; + break; + case dml2_s422: + out_bpp[k] = bpc * 2; + break; + case dml2_n422: + out_bpp[k] = bpc * 2; + break; + case dml2_420: + default: + out_bpp[k] = bpc * 1.5; + break; + } + } else if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable == dml2_dsc_enable) { + out_bpp[k] = (double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.dsc_compressed_bpp_x16 / 16; + } else { + out_bpp[k] = 0; + } +#ifdef __DML_VBA_DEBUG__ + dml2_printf("DML::%s: k=%d bpc=%f\n", __func__, k, bpc); + dml2_printf("DML::%s: k=%d dsc.enable=%d\n", __func__, k, display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.dsc.enable); + dml2_printf("DML::%s: k=%d out_bpp=%f\n", __func__, k, out_bpp[k]); +#endif + } +} + +unsigned int dml2_core_utils_round_to_multiple(unsigned int num, unsigned int multiple, bool up) +{ + unsigned int remainder; + + if (multiple == 0) + return num; + + remainder = num % multiple; + if (remainder == 0) + return num; + + if (up) + return (num + multiple - remainder); + else + return (num - remainder); +} + +unsigned int dml2_core_util_get_num_active_pipes(int unsigned num_planes, const struct core_display_cfg_support_info *cfg_support_info) +{ + unsigned int num_active_pipes = 0; + + for (unsigned int k = 0; k < num_planes; k++) { + num_active_pipes = num_active_pipes + (unsigned int)cfg_support_info->plane_support_info[k].dpps_used; + } + +#ifdef __DML_VBA_DEBUG__ + dml2_printf("DML::%s: num_active_pipes = %d\n", __func__, num_active_pipes); +#endif + return num_active_pipes; +} + +void dml2_core_utils_pipe_plane_mapping(const struct core_display_cfg_support_info *cfg_support_info, unsigned int *pipe_plane) +{ + unsigned int pipe_idx = 0; + + for (unsigned int k = 0; k < DML2_MAX_PLANES; ++k) { + pipe_plane[k] = __DML2_CALCS_PIPE_NO_PLANE__; + } + + for (unsigned int plane_idx = 0; plane_idx < DML2_MAX_PLANES; plane_idx++) { + for (int i = 0; i < cfg_support_info->plane_support_info[plane_idx].dpps_used; i++) { + pipe_plane[pipe_idx] = plane_idx; + pipe_idx++; + } + } +} + +bool dml2_core_utils_is_phantom_pipe(const struct dml2_plane_parameters *plane_cfg) +{ + bool is_phantom = false; + + if (plane_cfg->overrides.legacy_svp_config == dml2_svp_mode_override_phantom_pipe || + plane_cfg->overrides.legacy_svp_config == dml2_svp_mode_override_phantom_pipe_no_data_return) { + is_phantom = true; + } + + return is_phantom; +} + +unsigned int dml2_core_utils_get_tile_block_size_bytes(enum dml2_swizzle_mode sw_mode) +{ + switch (sw_mode) { + case (dml2_sw_linear): + return 256; break; + case (dml2_sw_256b_2d): + return 256; break; + case (dml2_sw_4kb_2d): + return 4096; break; + case (dml2_sw_64kb_2d): + return 65536; break; + case (dml2_sw_256kb_2d): + return 262144; break; + case (dml2_gfx11_sw_linear): + return 256; break; + case (dml2_gfx11_sw_64kb_d): + return 65536; break; + case (dml2_gfx11_sw_64kb_d_t): + return 65536; break; + case (dml2_gfx11_sw_64kb_d_x): + return 65536; break; + case (dml2_gfx11_sw_64kb_r_x): + return 65536; break; + case (dml2_gfx11_sw_256kb_d_x): + return 262144; break; + case (dml2_gfx11_sw_256kb_r_x): + return 262144; break; + default: + DML2_ASSERT(0); + return 256; + }; +} + + +bool dml2_core_utils_is_vertical_rotation(enum dml2_rotation_angle Scan) +{ + bool is_vert = false; + if (Scan == dml2_rotation_90 || Scan == dml2_rotation_270) { + is_vert = true; + } else { + is_vert = false; + } + return is_vert; +} + + +int unsigned dml2_core_utils_get_gfx_version(enum dml2_swizzle_mode sw_mode) +{ + int unsigned version = 0; + + if (sw_mode == dml2_sw_linear || + sw_mode == dml2_sw_256b_2d || + sw_mode == dml2_sw_4kb_2d || + sw_mode == dml2_sw_64kb_2d || + sw_mode == dml2_sw_256kb_2d) { + version = 12; + } else if (sw_mode == dml2_gfx11_sw_linear || + sw_mode == dml2_gfx11_sw_64kb_d || + sw_mode == dml2_gfx11_sw_64kb_d_t || + sw_mode == dml2_gfx11_sw_64kb_d_x || + sw_mode == dml2_gfx11_sw_64kb_r_x || + sw_mode == dml2_gfx11_sw_256kb_d_x || + sw_mode == dml2_gfx11_sw_256kb_r_x) { + version = 11; + } else { + dml2_printf("ERROR: Invalid sw_mode setting! val=%u\n", sw_mode); + DML2_ASSERT(0); + } + + return version; +} + +unsigned int dml2_core_utils_get_qos_param_index(unsigned long uclk_freq_khz, const struct dml2_dcn4_uclk_dpm_dependent_qos_params *per_uclk_dpm_params) +{ + unsigned int i; + unsigned int index = 0; + + for (i = 0; i < DML_MAX_CLK_TABLE_SIZE; i++) { + dml2_printf("DML::%s: per_uclk_dpm_params[%d].minimum_uclk_khz = %d\n", __func__, i, per_uclk_dpm_params[i].minimum_uclk_khz); + + if (i == 0) + index = 0; + else + index = i - 1; + + if (uclk_freq_khz < per_uclk_dpm_params[i].minimum_uclk_khz || + per_uclk_dpm_params[i].minimum_uclk_khz == 0) { + break; + } + } +#if defined(__DML_VBA_DEBUG__) + dml2_printf("DML::%s: uclk_freq_khz = %d\n", __func__, uclk_freq_khz); + dml2_printf("DML::%s: index = %d\n", __func__, index); +#endif + return index; +} + +unsigned int dml2_core_utils_get_active_min_uclk_dpm_index(unsigned long uclk_freq_khz, const struct dml2_soc_state_table *clk_table) +{ + unsigned int i; + bool clk_entry_found = 0; + + for (i = 0; i < clk_table->uclk.num_clk_values; i++) { + dml2_printf("DML::%s: clk_table.uclk.clk_values_khz[%d] = %d\n", __func__, i, clk_table->uclk.clk_values_khz[i]); + + if (uclk_freq_khz == clk_table->uclk.clk_values_khz[i]) { + clk_entry_found = 1; + break; + } + } + + dml2_assert(clk_entry_found); +#if defined(__DML_VBA_DEBUG__) + dml2_printf("DML::%s: uclk_freq_khz = %ld\n", __func__, uclk_freq_khz); + dml2_printf("DML::%s: index = %d\n", __func__, i); +#endif + return i; +} + +bool dml2_core_utils_is_dual_plane(enum dml2_source_format_class source_format) +{ + bool ret_val = 0; + + if ((source_format == dml2_420_12) || (source_format == dml2_420_8) || (source_format == dml2_420_10) || (source_format == dml2_rgbe_alpha)) + ret_val = 1; + + return ret_val; +} + +unsigned int dml2_core_utils_log_and_substract_if_non_zero(unsigned int a, unsigned int subtrahend) +{ + if (a == 0) + return 0; + + return (math_log2_approx(a) - subtrahend); +} + +static void create_phantom_stream_from_main_stream(struct dml2_stream_parameters *phantom, const struct dml2_stream_parameters *main, + const struct dml2_implicit_svp_meta *meta) +{ + memcpy(phantom, main, sizeof(struct dml2_stream_parameters)); + + phantom->timing.v_total = meta->v_total; + phantom->timing.v_active = meta->v_active; + phantom->timing.v_front_porch = meta->v_front_porch; + phantom->timing.vblank_nom = phantom->timing.v_total - phantom->timing.v_active; + phantom->timing.drr_config.enabled = false; +} + +static void create_phantom_plane_from_main_plane(struct dml2_plane_parameters *phantom, const struct dml2_plane_parameters *main, + const struct dml2_stream_parameters *phantom_stream, int phantom_stream_index, const struct dml2_stream_parameters *main_stream) +{ + memcpy(phantom, main, sizeof(struct dml2_plane_parameters)); + + phantom->stream_index = phantom_stream_index; + phantom->overrides.refresh_from_mall = dml2_refresh_from_mall_mode_override_force_disable; + phantom->overrides.legacy_svp_config = dml2_svp_mode_override_phantom_pipe_no_data_return; + phantom->composition.viewport.plane0.height = (long int unsigned) math_min2(math_ceil2( + (double)main->composition.scaler_info.plane0.v_ratio * (double)phantom_stream->timing.v_active, 16.0), + (double)main->composition.viewport.plane0.height); + phantom->composition.viewport.plane1.height = (long int unsigned) math_min2(math_ceil2( + (double)main->composition.scaler_info.plane1.v_ratio * (double)phantom_stream->timing.v_active, 16.0), + (double)main->composition.viewport.plane1.height); + phantom->immediate_flip = false; + phantom->dynamic_meta_data.enable = false; + phantom->cursor.num_cursors = 0; + phantom->cursor.cursor_width = 0; + phantom->tdlut.setup_for_tdlut = false; +} + +void dml2_core_utils_expand_implict_subvp(const struct display_configuation_with_meta *display_cfg, struct dml2_display_cfg *svp_expanded_display_cfg, + struct dml2_core_scratch *scratch) +{ + unsigned int stream_index, plane_index; + const struct dml2_plane_parameters *main_plane; + const struct dml2_stream_parameters *main_stream; + const struct dml2_stream_parameters *phantom_stream; + + memcpy(svp_expanded_display_cfg, &display_cfg->display_config, sizeof(struct dml2_display_cfg)); + memset(scratch->main_stream_index_from_svp_stream_index, 0, sizeof(int) * DML2_MAX_PLANES); + memset(scratch->svp_stream_index_from_main_stream_index, 0, sizeof(int) * DML2_MAX_PLANES); + memset(scratch->main_plane_index_to_phantom_plane_index, 0, sizeof(int) * DML2_MAX_PLANES); + + if (!display_cfg->display_config.overrides.enable_subvp_implicit_pmo) + return; + + /* disable unbounded requesting for all planes until stage 3 has been performed */ + if (!display_cfg->stage3.performed) { + svp_expanded_display_cfg->overrides.hw.force_unbounded_requesting.enable = true; + svp_expanded_display_cfg->overrides.hw.force_unbounded_requesting.value = false; + } + // Create the phantom streams + for (stream_index = 0; stream_index < display_cfg->display_config.num_streams; stream_index++) { + main_stream = &display_cfg->display_config.stream_descriptors[stream_index]; + scratch->main_stream_index_from_svp_stream_index[stream_index] = stream_index; + scratch->svp_stream_index_from_main_stream_index[stream_index] = stream_index; + + if (display_cfg->stage3.stream_svp_meta[stream_index].valid) { + // Create the phantom stream + create_phantom_stream_from_main_stream(&svp_expanded_display_cfg->stream_descriptors[svp_expanded_display_cfg->num_streams], + main_stream, &display_cfg->stage3.stream_svp_meta[stream_index]); + + // Associate this phantom stream to the main stream + scratch->main_stream_index_from_svp_stream_index[svp_expanded_display_cfg->num_streams] = stream_index; + scratch->svp_stream_index_from_main_stream_index[stream_index] = svp_expanded_display_cfg->num_streams; + + // Increment num streams + svp_expanded_display_cfg->num_streams++; + } + } + + // Create the phantom planes + for (plane_index = 0; plane_index < display_cfg->display_config.num_planes; plane_index++) { + main_plane = &display_cfg->display_config.plane_descriptors[plane_index]; + + if (display_cfg->stage3.stream_svp_meta[main_plane->stream_index].valid) { + main_stream = &display_cfg->display_config.stream_descriptors[main_plane->stream_index]; + phantom_stream = &svp_expanded_display_cfg->stream_descriptors[scratch->svp_stream_index_from_main_stream_index[main_plane->stream_index]]; + create_phantom_plane_from_main_plane(&svp_expanded_display_cfg->plane_descriptors[svp_expanded_display_cfg->num_planes], + main_plane, phantom_stream, scratch->svp_stream_index_from_main_stream_index[main_plane->stream_index], main_stream); + + // Associate this phantom plane to the main plane + scratch->phantom_plane_index_to_main_plane_index[svp_expanded_display_cfg->num_planes] = plane_index; + scratch->main_plane_index_to_phantom_plane_index[plane_index] = svp_expanded_display_cfg->num_planes; + + // Increment num planes + svp_expanded_display_cfg->num_planes++; + + // Adjust the main plane settings + svp_expanded_display_cfg->plane_descriptors[plane_index].overrides.legacy_svp_config = dml2_svp_mode_override_main_pipe; + } + } +} + +bool dml2_core_utils_is_stream_encoder_required(const struct dml2_stream_parameters *stream_descriptor) +{ + switch (stream_descriptor->output.output_encoder) { + case dml2_dp: + case dml2_dp2p0: + case dml2_edp: + case dml2_hdmi: + case dml2_hdmifrl: + return true; + case dml2_none: + default: + return false; + } +} +bool dml2_core_utils_is_encoder_dsc_capable(const struct dml2_stream_parameters *stream_descriptor) +{ + switch (stream_descriptor->output.output_encoder) { + case dml2_dp: + case dml2_dp2p0: + case dml2_edp: + case dml2_hdmifrl: + return true; + case dml2_hdmi: + case dml2_none: + default: + return false; + } +} + + +bool dml2_core_utils_is_dio_dp_encoder(const struct dml2_stream_parameters *stream_descriptor) +{ + switch (stream_descriptor->output.output_encoder) { + case dml2_dp: + case dml2_edp: + return true; + case dml2_dp2p0: + case dml2_hdmi: + case dml2_hdmifrl: + case dml2_none: + default: + return false; + } +} + +bool dml2_core_utils_is_hpo_dp_encoder(const struct dml2_stream_parameters *stream_descriptor) +{ + switch (stream_descriptor->output.output_encoder) { + case dml2_dp2p0: + return true; + case dml2_dp: + case dml2_edp: + case dml2_hdmi: + case dml2_hdmifrl: + case dml2_none: + default: + return false; + } +} + +bool dml2_core_utils_is_dp_encoder(const struct dml2_stream_parameters *stream_descriptor) +{ + return dml2_core_utils_is_dio_dp_encoder(stream_descriptor) + || dml2_core_utils_is_hpo_dp_encoder(stream_descriptor); +} + + +bool dml2_core_utils_is_dp_8b_10b_link_rate(enum dml2_output_link_dp_rate rate) +{ + switch (rate) { + case dml2_dp_rate_hbr: + case dml2_dp_rate_hbr2: + case dml2_dp_rate_hbr3: + return true; + case dml2_dp_rate_na: + case dml2_dp_rate_uhbr10: + case dml2_dp_rate_uhbr13p5: + case dml2_dp_rate_uhbr20: + default: + return false; + } +} + +bool dml2_core_utils_is_dp_128b_132b_link_rate(enum dml2_output_link_dp_rate rate) +{ + switch (rate) { + case dml2_dp_rate_uhbr10: + case dml2_dp_rate_uhbr13p5: + case dml2_dp_rate_uhbr20: + return true; + case dml2_dp_rate_hbr: + case dml2_dp_rate_hbr2: + case dml2_dp_rate_hbr3: + case dml2_dp_rate_na: + default: + return false; + } +} + +bool dml2_core_utils_is_odm_split(enum dml2_odm_mode odm_mode) +{ + switch (odm_mode) { + case dml2_odm_mode_split_1to2: + case dml2_odm_mode_mso_1to2: + case dml2_odm_mode_mso_1to4: + return true; + case dml2_odm_mode_auto: + case dml2_odm_mode_bypass: + case dml2_odm_mode_combine_2to1: + case dml2_odm_mode_combine_3to1: + case dml2_odm_mode_combine_4to1: + default: + return false; + } +} diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.h b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.h new file mode 100644 index 0000000000000..a5cc6a07167ae --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.h @@ -0,0 +1,39 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2024 Advanced Micro Devices, Inc. + +#ifndef __DML2_CORE_UTILS_H__ +#define __DML2_CORE_UTILS_H__ +#include "dml2_internal_shared_types.h" +#include "dml2_debug.h" +#include "lib_float_math.h" + +double dml2_core_utils_div_rem(double dividend, unsigned int divisor, unsigned int *remainder); +const char *dml2_core_utils_internal_bw_type_str(enum dml2_core_internal_bw_type bw_type); +bool dml2_core_utils_is_420(enum dml2_source_format_class source_format); +void dml2_core_utils_print_mode_support_info(const struct dml2_core_internal_mode_support_info *support, bool fail_only); +const char *dml2_core_utils_internal_soc_state_type_str(enum dml2_core_internal_soc_state_type dml2_core_internal_soc_state_type); +void dml2_core_utils_get_stream_output_bpp(double *out_bpp, const struct dml2_display_cfg *display_cfg); +unsigned int dml2_core_utils_round_to_multiple(unsigned int num, unsigned int multiple, bool up); +unsigned int dml2_core_util_get_num_active_pipes(int unsigned num_planes, const struct core_display_cfg_support_info *cfg_support_info); +void dml2_core_utils_pipe_plane_mapping(const struct core_display_cfg_support_info *cfg_support_info, unsigned int *pipe_plane); +bool dml2_core_utils_is_phantom_pipe(const struct dml2_plane_parameters *plane_cfg); +unsigned int dml2_core_utils_get_tile_block_size_bytes(enum dml2_swizzle_mode sw_mode); +bool dml2_core_utils_is_vertical_rotation(enum dml2_rotation_angle Scan); +int unsigned dml2_core_utils_get_gfx_version(enum dml2_swizzle_mode sw_mode); +unsigned int dml2_core_utils_get_qos_param_index(unsigned long uclk_freq_khz, const struct dml2_dcn4_uclk_dpm_dependent_qos_params *per_uclk_dpm_params); +unsigned int dml2_core_utils_get_active_min_uclk_dpm_index(unsigned long uclk_freq_khz, const struct dml2_soc_state_table *clk_table); +bool dml2_core_utils_is_dual_plane(enum dml2_source_format_class source_format); +unsigned int dml2_core_utils_log_and_substract_if_non_zero(unsigned int a, unsigned int subtrahend); +void dml2_core_utils_expand_implict_subvp(const struct display_configuation_with_meta *display_cfg, struct dml2_display_cfg *svp_expanded_display_cfg, + struct dml2_core_scratch *scratch); +bool dml2_core_utils_is_stream_encoder_required(const struct dml2_stream_parameters *stream_descriptor); +bool dml2_core_utils_is_encoder_dsc_capable(const struct dml2_stream_parameters *stream_descriptor); +bool dml2_core_utils_is_dp_encoder(const struct dml2_stream_parameters *stream_descriptor); +bool dml2_core_utils_is_dio_dp_encoder(const struct dml2_stream_parameters *stream_descriptor); +bool dml2_core_utils_is_hpo_dp_encoder(const struct dml2_stream_parameters *stream_descriptor); +bool dml2_core_utils_is_dp_8b_10b_link_rate(enum dml2_output_link_dp_rate rate); +bool dml2_core_utils_is_dp_128b_132b_link_rate(enum dml2_output_link_dp_rate rate); +bool dml2_core_utils_is_odm_split(enum dml2_odm_mode odm_mode); + +#endif /* __DML2_CORE_UTILS_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c index f19f6ebaae132..8869ea0893128 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_dcn4.c @@ -203,6 +203,26 @@ static bool add_margin_and_round_to_dfs_grainularity(double clock_khz, double ma return true; } +static bool round_to_non_dfs_granularity(unsigned long dispclk_khz, unsigned long dpprefclk_khz, unsigned long dtbrefclk_khz, + unsigned long *rounded_dispclk_khz, unsigned long *rounded_dpprefclk_khz, unsigned long *rounded_dtbrefclk_khz) +{ + unsigned long pll_frequency_khz; + + pll_frequency_khz = (unsigned long) math_max2(600000, math_ceil2(math_max3(dispclk_khz, dpprefclk_khz, dtbrefclk_khz), 1000)); + + *rounded_dispclk_khz = pll_frequency_khz / (unsigned long) math_min2(pll_frequency_khz / dispclk_khz, 32); + + *rounded_dpprefclk_khz = pll_frequency_khz / (unsigned long) math_min2(pll_frequency_khz / dpprefclk_khz, 32); + + if (dtbrefclk_khz > 0) { + *rounded_dtbrefclk_khz = pll_frequency_khz / (unsigned long) math_min2(pll_frequency_khz / dtbrefclk_khz, 32); + } else { + *rounded_dtbrefclk_khz = 0; + } + + return true; +} + static bool round_up_and_copy_to_next_dpm(unsigned long min_value, unsigned long *rounded_value, const struct dml2_clk_table *clock_table) { bool result = false; @@ -555,31 +575,39 @@ static bool map_mode_to_soc_dpm(struct dml2_dpmm_map_mode_to_soc_dpm_params_in_o // but still the required dispclk can be more than the maximum dispclk speed: dispclk_khz = math_max2(dispclk_khz, mode_support_result->global.dispclk_khz * (1 + in_out->soc_bb->dcn_downspread_percent / 100.0)); - add_margin_and_round_to_dfs_grainularity(dispclk_khz, 0.0, - (unsigned long)(in_out->soc_bb->dispclk_dppclk_vco_speed_mhz * 1000), &in_out->programming->min_clocks.dcn4x.dispclk_khz, &in_out->programming->min_clocks.dcn4x.divider_ids.dispclk_did); - // DPP Ref is always set to max of all DPP clocks for (i = 0; i < DML2_MAX_DCN_PIPES; i++) { if (in_out->programming->min_clocks.dcn4x.dpprefclk_khz < mode_support_result->per_plane[i].dppclk_khz) in_out->programming->min_clocks.dcn4x.dpprefclk_khz = mode_support_result->per_plane[i].dppclk_khz; } - - add_margin_and_round_to_dfs_grainularity(in_out->programming->min_clocks.dcn4x.dpprefclk_khz, in_out->soc_bb->dcn_downspread_percent / 100.0, - (unsigned long)(in_out->soc_bb->dispclk_dppclk_vco_speed_mhz * 1000), &in_out->programming->min_clocks.dcn4x.dpprefclk_khz, &in_out->programming->min_clocks.dcn4x.divider_ids.dpprefclk_did); - - for (i = 0; i < DML2_MAX_DCN_PIPES; i++) { - in_out->programming->plane_programming[i].min_clocks.dcn4x.dppclk_khz = (unsigned long)(in_out->programming->min_clocks.dcn4x.dpprefclk_khz / 255.0 - * math_ceil2(in_out->display_cfg->mode_support_result.per_plane[i].dppclk_khz * (1.0 + in_out->soc_bb->dcn_downspread_percent / 100.0) * 255.0 / in_out->programming->min_clocks.dcn4x.dpprefclk_khz, 1.0)); - } + in_out->programming->min_clocks.dcn4x.dpprefclk_khz = (unsigned long) (in_out->programming->min_clocks.dcn4x.dpprefclk_khz * (1 + in_out->soc_bb->dcn_downspread_percent / 100.0)); // DTB Ref is always set to max of all DTB clocks for (i = 0; i < DML2_MAX_DCN_PIPES; i++) { if (in_out->programming->min_clocks.dcn4x.dtbrefclk_khz < mode_support_result->per_stream[i].dtbclk_khz) in_out->programming->min_clocks.dcn4x.dtbrefclk_khz = mode_support_result->per_stream[i].dtbclk_khz; } + in_out->programming->min_clocks.dcn4x.dtbrefclk_khz = (unsigned long)(in_out->programming->min_clocks.dcn4x.dtbrefclk_khz * (1 + in_out->soc_bb->dcn_downspread_percent / 100.0)); + + if (in_out->soc_bb->no_dfs) { + round_to_non_dfs_granularity((unsigned long)dispclk_khz, in_out->programming->min_clocks.dcn4x.dpprefclk_khz, in_out->programming->min_clocks.dcn4x.dtbrefclk_khz, + &in_out->programming->min_clocks.dcn4x.dispclk_khz, &in_out->programming->min_clocks.dcn4x.dpprefclk_khz, &in_out->programming->min_clocks.dcn4x.dtbrefclk_khz); + } else { + add_margin_and_round_to_dfs_grainularity(dispclk_khz, 0.0, + (unsigned long)(in_out->soc_bb->dispclk_dppclk_vco_speed_mhz * 1000), &in_out->programming->min_clocks.dcn4x.dispclk_khz, &in_out->programming->min_clocks.dcn4x.divider_ids.dispclk_did); + + add_margin_and_round_to_dfs_grainularity(in_out->programming->min_clocks.dcn4x.dpprefclk_khz, 0.0, + (unsigned long)(in_out->soc_bb->dispclk_dppclk_vco_speed_mhz * 1000), &in_out->programming->min_clocks.dcn4x.dpprefclk_khz, &in_out->programming->min_clocks.dcn4x.divider_ids.dpprefclk_did); + + add_margin_and_round_to_dfs_grainularity(in_out->programming->min_clocks.dcn4x.dtbrefclk_khz, 0.0, + (unsigned long)(in_out->soc_bb->dispclk_dppclk_vco_speed_mhz * 1000), &in_out->programming->min_clocks.dcn4x.dtbrefclk_khz, &in_out->programming->min_clocks.dcn4x.divider_ids.dtbrefclk_did); + } - add_margin_and_round_to_dfs_grainularity(in_out->programming->min_clocks.dcn4x.dtbrefclk_khz, in_out->soc_bb->dcn_downspread_percent / 100.0, - (unsigned long)(in_out->soc_bb->dispclk_dppclk_vco_speed_mhz * 1000), &in_out->programming->min_clocks.dcn4x.dtbrefclk_khz, &in_out->programming->min_clocks.dcn4x.divider_ids.dtbrefclk_did); + + for (i = 0; i < DML2_MAX_DCN_PIPES; i++) { + in_out->programming->plane_programming[i].min_clocks.dcn4x.dppclk_khz = (unsigned long)(in_out->programming->min_clocks.dcn4x.dpprefclk_khz / 255.0 + * math_ceil2(in_out->display_cfg->mode_support_result.per_plane[i].dppclk_khz * (1.0 + in_out->soc_bb->dcn_downspread_percent / 100.0) * 255.0 / in_out->programming->min_clocks.dcn4x.dpprefclk_khz, 1.0)); + } in_out->programming->min_clocks.dcn4x.deepsleep_dcfclk_khz = mode_support_result->global.dcfclk_deepsleep_khz; in_out->programming->min_clocks.dcn4x.socclk_khz = mode_support_result->global.socclk_khz; diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_factory.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_factory.c index dfd01440737df..3861bc6c96219 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_factory.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/dml2_dpmm_factory.c @@ -20,7 +20,7 @@ bool dml2_dpmm_create(enum dml2_project_id project_id, struct dml2_dpmm_instance { bool result = false; - if (!out) + if (out == 0) return false; memset(out, 0, sizeof(struct dml2_dpmm_instance)); diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c index 68b333b689337..30767f330fd48 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c @@ -718,7 +718,7 @@ bool pmo_dcn4_fams2_init_for_vmin(struct dml2_pmo_init_for_vmin_in_out *in_out) const struct dml2_core_mode_support_result *mode_support_result = &in_out->base_display_config->mode_support_result; struct dml2_optimization_stage4_state *state = - &in_out->base_display_config->stage4; + &in_out->base_display_config->stage4; if (in_out->instance->options->disable_dyn_odm || (in_out->instance->options->disable_dyn_odm_for_multi_stream && display_config->num_streams > 1)) @@ -1444,7 +1444,7 @@ static bool stream_matches_drr_policy(struct dml2_pmo_instance *pmo, /* DRR variable strategies are disallowed due to settings or policy */ strategy_matches_drr_requirements = false; } else if (is_bit_set_in_bitfield(PMO_DRR_CLAMPED_STRATEGY_MASK, stream_pstate_method) && - (pmo->options->disable_drr_clamped || + (pmo->options->disable_drr_clamped || (!stream_descriptor->timing.drr_config.enabled || (!stream_descriptor->timing.drr_config.drr_active_fixed && !stream_descriptor->timing.drr_config.drr_active_variable)) || (pmo->options->disable_drr_clamped_when_var_active && @@ -1910,7 +1910,8 @@ static void setup_planes_for_vblank_by_mask(struct display_configuation_with_met if (is_bit_set_in_bitfield(plane_mask, plane_index)) { plane = &display_config->display_config.plane_descriptors[plane_index]; - plane->overrides.reserved_vblank_time_ns = (long)(pmo->soc_bb->power_management_parameters.dram_clk_change_blackout_us * 1000); + plane->overrides.reserved_vblank_time_ns = (long)math_max2(pmo->soc_bb->power_management_parameters.dram_clk_change_blackout_us * 1000.0, + plane->overrides.reserved_vblank_time_ns); display_config->stage3.pstate_switch_modes[plane_index] = dml2_uclk_pstate_support_method_vblank; @@ -2196,15 +2197,15 @@ bool pmo_dcn4_fams2_test_for_stutter(struct dml2_pmo_test_for_stutter_in_out *in unsigned int i; - for (i = 0; i < in_out->base_display_config->display_config.num_streams; i++) { + for (i = 0; i < in_out->base_display_config->display_config.num_planes; i++) { if (pmo->soc_bb->power_management_parameters.z8_stutter_exit_latency_us > 0 && pmo->scratch.pmo_dcn4.z8_vblank_optimizable && - in_out->base_display_config->display_config.stream_descriptors[i].overrides.minimum_vblank_idle_requirement_us < (int)pmo->soc_bb->power_management_parameters.z8_stutter_exit_latency_us) { + in_out->base_display_config->display_config.plane_descriptors[i].overrides.reserved_vblank_time_ns < (int)pmo->soc_bb->power_management_parameters.z8_stutter_exit_latency_us * 1000) { success = false; break; } if (pmo->soc_bb->power_management_parameters.stutter_enter_plus_exit_latency_us > 0 && - in_out->base_display_config->display_config.stream_descriptors[i].overrides.minimum_vblank_idle_requirement_us < (int)pmo->soc_bb->power_management_parameters.stutter_enter_plus_exit_latency_us) { + in_out->base_display_config->display_config.plane_descriptors[i].overrides.reserved_vblank_time_ns < (int)pmo->soc_bb->power_management_parameters.stutter_enter_plus_exit_latency_us * 1000) { success = false; break; } @@ -2223,8 +2224,11 @@ bool pmo_dcn4_fams2_optimize_for_stutter(struct dml2_pmo_optimize_for_stutter_in if (!in_out->last_candidate_failed) { if (pmo->scratch.pmo_dcn4.cur_stutter_candidate < pmo->scratch.pmo_dcn4.num_stutter_candidates) { - for (i = 0; i < in_out->optimized_display_config->display_config.num_streams; i++) { - in_out->optimized_display_config->display_config.stream_descriptors[i].overrides.minimum_vblank_idle_requirement_us = pmo->scratch.pmo_dcn4.optimal_vblank_reserved_time_for_stutter_us[pmo->scratch.pmo_dcn4.cur_stutter_candidate]; + for (i = 0; i < in_out->optimized_display_config->display_config.num_planes; i++) { + /* take the max of the current and the optimal reserved time */ + in_out->optimized_display_config->display_config.plane_descriptors[i].overrides.reserved_vblank_time_ns = + (long)math_max2(pmo->scratch.pmo_dcn4.optimal_vblank_reserved_time_for_stutter_us[pmo->scratch.pmo_dcn4.cur_stutter_candidate] * 1000, + in_out->optimized_display_config->display_config.plane_descriptors[i].overrides.reserved_vblank_time_ns); } success = true; diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_factory.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_factory.c index 95f716e2641f4..add51d41a5158 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_factory.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_factory.c @@ -26,7 +26,7 @@ bool dml2_pmo_create(enum dml2_project_id project_id, struct dml2_pmo_instance * { bool result = false; - if (!out) + if (out == 0) return false; memset(out, 0, sizeof(struct dml2_pmo_instance)); From 54b6f1988a6f4ef1904ed609c3486eed0c89a6c6 Mon Sep 17 00:00:00 2001 From: Martin Leung Date: Mon, 12 Aug 2024 00:55:56 -0400 Subject: [PATCH 1369/1868] drm/amd/display: Promote DC to 3.2.297 - Various DML 2.1 fixes - Fix module unload - Fix construct_phy with MXM connector - Support UHBR10 link rate on eDP - Revert updated DCCG wrappers Reviewed-by: Roman Li Signed-off-by: Martin Leung Signed-off-by: Roman Li Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 697d615617847..8e072e60fa4cb 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -55,7 +55,7 @@ struct aux_payload; struct set_config_cmd_payload; struct dmub_notification; -#define DC_VER "3.2.296" +#define DC_VER "3.2.297" #define MAX_SURFACES 3 #define MAX_PLANES 6 From d288684ee7a803953b9c0fa310ff8cd735f0380a Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 19 Aug 2024 11:14:29 -0400 Subject: [PATCH 1370/1868] drm/amdgpu: fix eGPU hotplug regression The driver needs to wait for the on board firmware to finish its initialization before probing the card. Commit 959056982a9b ("drm/amdgpu: Fix discovery initialization failure during pci rescan") switched from using msleep() to using usleep_range() which seems to have caused init failures on some navi1x boards. Switch back to msleep(). Fixes: 959056982a9b ("drm/amdgpu: Fix discovery initialization failure during pci rescan") Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3559 Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3500 Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher Cc: Ma Jun --- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index 774f54789c215..cc7bb0bad4e75 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -280,7 +280,7 @@ static int amdgpu_discovery_read_binary_from_mem(struct amdgpu_device *adev, msg = RREG32(mmMP0_SMN_C2PMSG_33); if (msg & 0x80000000) break; - usleep_range(1000, 1100); + msleep(1); } } From 532a51351ecb009df1b6d53d1a8a719d869acda3 Mon Sep 17 00:00:00 2001 From: Victor Zhao Date: Mon, 19 Aug 2024 11:16:13 +0800 Subject: [PATCH 1371/1868] drm/amd/amdgpu: allow use kiq to do hdp flush under sriov when use cpu to do page table update under sriov runtime, since mmio access is blocked, kiq has to be used to flush hdp. change WREG32_NO_KIQ to WREG32 to allow kiq. Signed-off-by: Victor Zhao Reviewed-by: Emily Deng --- drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c index 077c6d920e27f..e019249883fb2 100644 --- a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c @@ -41,7 +41,7 @@ static void hdp_v4_0_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) { if (!ring || !ring->funcs->emit_wreg) - WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); + WREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); else amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); } diff --git a/drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c b/drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c index a9ea23fa0def7..ed7facacf2fe3 100644 --- a/drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c @@ -32,7 +32,7 @@ static void hdp_v5_0_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) { if (!ring || !ring->funcs->emit_wreg) - WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); + WREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); else amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); } diff --git a/drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c b/drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c index ab06c2b4b20b2..33736d361dd0b 100644 --- a/drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c @@ -35,7 +35,7 @@ static void hdp_v6_0_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) { if (!ring || !ring->funcs->emit_wreg) - WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); + WREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); else amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); } diff --git a/drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c b/drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c index 8d7d0813e3315..1c99bb09e2a12 100644 --- a/drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c @@ -32,7 +32,7 @@ static void hdp_v7_0_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) { if (!ring || !ring->funcs->emit_wreg) - WREG32_NO_KIQ((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); + WREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); else amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); } From f034b2e22aaef9aca16b82b828fc683cf655445c Mon Sep 17 00:00:00 2001 From: Tim Huang Date: Wed, 7 Aug 2024 17:15:12 +0800 Subject: [PATCH 1372/1868] drm/amd/pm: ensure the fw_info is not null before using it This resolves the dereference null return value warning reported by Coverity. Signed-off-by: Tim Huang Reviewed-by: Jesse Zhang --- drivers/gpu/drm/amd/pm/powerplay/hwmgr/processpptables.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/processpptables.c b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/processpptables.c index ca1c7ae8d146d..f06b29e33ba45 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/hwmgr/processpptables.c +++ b/drivers/gpu/drm/amd/pm/powerplay/hwmgr/processpptables.c @@ -1183,6 +1183,8 @@ static int init_overdrive_limits(struct pp_hwmgr *hwmgr, fw_info = smu_atom_get_data_table(hwmgr->adev, GetIndexIntoMasterTable(DATA, FirmwareInfo), &size, &frev, &crev); + PP_ASSERT_WITH_CODE(fw_info != NULL, + "Missing firmware info!", return -EINVAL); if ((fw_info->ucTableFormatRevision == 1) && (le16_to_cpu(fw_info->usStructureSize) >= sizeof(ATOM_FIRMWARE_INFO_V1_4))) From d259dd14656147c51aa7415c91ec325337e4d1ea Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 20 Aug 2024 10:35:49 -0400 Subject: [PATCH 1373/1868] drm/amd/gfx11: move the gfx mutex into the caller Otherwise we can fail to drop the software mutex when we fail to take the hardware mutex. Fixes: 76acba7b7f12 ("drm/amdgpu/gfx11: add a mutex for the gfx semaphore") Reported-by: Dan Carpenter Reviewed-by: Dan Carpenter Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index 5685aee479dfc..ee86047224672 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -4747,8 +4747,6 @@ int gfx_v11_0_request_gfx_index_mutex(struct amdgpu_device *adev, { u32 i, tmp, val; - if (req) - mutex_lock(&adev->gfx.reset_sem_mutex); for (i = 0; i < adev->usec_timeout; i++) { /* Request with MeId=2, PipeId=0 */ tmp = REG_SET_FIELD(0, CP_GFX_INDEX_MUTEX, REQUEST, req); @@ -4769,8 +4767,6 @@ int gfx_v11_0_request_gfx_index_mutex(struct amdgpu_device *adev, } udelay(1); } - if (!req) - mutex_unlock(&adev->gfx.reset_sem_mutex); if (i >= adev->usec_timeout) return -EINVAL; @@ -4818,8 +4814,10 @@ static int gfx_v11_0_soft_reset(void *handle) mutex_unlock(&adev->srbm_mutex); /* Try to acquire the gfx mutex before access to CP_VMID_RESET */ + mutex_lock(&adev->gfx.reset_sem_mutex); r = gfx_v11_0_request_gfx_index_mutex(adev, true); if (r) { + mutex_unlock(&adev->gfx.reset_sem_mutex); DRM_ERROR("Failed to acquire the gfx mutex during soft reset\n"); return r; } @@ -4834,6 +4832,7 @@ static int gfx_v11_0_soft_reset(void *handle) /* release the gfx mutex */ r = gfx_v11_0_request_gfx_index_mutex(adev, false); + mutex_unlock(&adev->gfx.reset_sem_mutex); if (r) { DRM_ERROR("Failed to release the gfx mutex during soft reset\n"); return r; From 8596c6dfcfdefbf8c77fc93ec274c0ae95203fbc Mon Sep 17 00:00:00 2001 From: Hawking Zhang Date: Tue, 20 Aug 2024 13:56:32 +0800 Subject: [PATCH 1374/1868] drm/amdkfd: Check int source id for utcl2 poison event Traditional utcl2 fault_status polling does not work in SRIOV environment. The polling of fault status register from guest side will be dropped by hardware. Driver should switch to check utcl2 interrupt source id to identify utcl2 poison event. It is set to 1 when poisoned data interrupts are signaled. v2: drop the unused local variable (Tao) Signed-off-by: Hawking Zhang Reviewed-by: Tao Zhou --- .../gpu/drm/amd/amdkfd/kfd_int_process_v9.c | 18 +----------------- drivers/gpu/drm/amd/amdkfd/soc15_int.h | 1 + 2 files changed, 2 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c index a9c3580be8c9b..fecdbbab98949 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c @@ -431,25 +431,9 @@ static void event_interrupt_wq_v9(struct kfd_node *dev, client_id == SOC15_IH_CLIENTID_UTCL2) { struct kfd_vm_fault_info info = {0}; uint16_t ring_id = SOC15_RING_ID_FROM_IH_ENTRY(ih_ring_entry); - uint32_t node_id = SOC15_NODEID_FROM_IH_ENTRY(ih_ring_entry); - uint32_t vmid_type = SOC15_VMID_TYPE_FROM_IH_ENTRY(ih_ring_entry); - int hub_inst = 0; struct kfd_hsa_memory_exception_data exception_data; - /* gfxhub */ - if (!vmid_type && dev->adev->gfx.funcs->ih_node_to_logical_xcc) { - hub_inst = dev->adev->gfx.funcs->ih_node_to_logical_xcc(dev->adev, - node_id); - if (hub_inst < 0) - hub_inst = 0; - } - - /* mmhub */ - if (vmid_type && client_id == SOC15_IH_CLIENTID_VMC) - hub_inst = node_id / 4; - - if (amdgpu_amdkfd_ras_query_utcl2_poison_status(dev->adev, - hub_inst, vmid_type)) { + if (source_id == SOC15_INTSRC_VMC_UTCL2_POISON) { event_interrupt_poison_consumption_v9(dev, pasid, client_id); return; } diff --git a/drivers/gpu/drm/amd/amdkfd/soc15_int.h b/drivers/gpu/drm/amd/amdkfd/soc15_int.h index 10138676f27fd..e5c0205f26181 100644 --- a/drivers/gpu/drm/amd/amdkfd/soc15_int.h +++ b/drivers/gpu/drm/amd/amdkfd/soc15_int.h @@ -29,6 +29,7 @@ #define SOC15_INTSRC_CP_BAD_OPCODE 183 #define SOC15_INTSRC_SQ_INTERRUPT_MSG 239 #define SOC15_INTSRC_VMC_FAULT 0 +#define SOC15_INTSRC_VMC_UTCL2_POISON 1 #define SOC15_INTSRC_SDMA_TRAP 224 #define SOC15_INTSRC_SDMA_ECC 220 #define SOC21_INTSRC_SDMA_TRAP 49 From 8f2d2960fdeb15ee4074480028429a44aa1ce940 Mon Sep 17 00:00:00 2001 From: Hawking Zhang Date: Mon, 19 Aug 2024 22:23:11 +0800 Subject: [PATCH 1375/1868] drm/amdkfd: Drop poison hanlding from gfx v10 Not supported. Signed-off-by: Hawking Zhang Reviewed-by: Tao Zhou --- .../gpu/drm/amd/amdkfd/kfd_int_process_v10.c | 71 ------------------- 1 file changed, 71 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v10.c b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v10.c index 8e0d0356e810c..bb8cbfc39b90f 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v10.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v10.c @@ -129,63 +129,6 @@ enum SQ_INTERRUPT_ERROR_TYPE { KFD_DEBUG_CP_BAD_OP_ECODE_MASK) \ >> KFD_DEBUG_CP_BAD_OP_ECODE_SHIFT) -static void event_interrupt_poison_consumption(struct kfd_node *dev, - uint16_t pasid, uint16_t client_id) -{ - enum amdgpu_ras_block block = 0; - int old_poison, ret = -EINVAL; - uint32_t reset = 0; - struct kfd_process *p = kfd_lookup_process_by_pasid(pasid); - - if (!p) - return; - - /* all queues of a process will be unmapped in one time */ - old_poison = atomic_cmpxchg(&p->poison, 0, 1); - kfd_unref_process(p); - if (old_poison) - return; - - switch (client_id) { - case SOC15_IH_CLIENTID_SE0SH: - case SOC15_IH_CLIENTID_SE1SH: - case SOC15_IH_CLIENTID_SE2SH: - case SOC15_IH_CLIENTID_SE3SH: - case SOC15_IH_CLIENTID_UTCL2: - ret = kfd_dqm_evict_pasid(dev->dqm, pasid); - block = AMDGPU_RAS_BLOCK__GFX; - if (ret) - reset = AMDGPU_RAS_GPU_RESET_MODE2_RESET; - break; - case SOC15_IH_CLIENTID_SDMA0: - case SOC15_IH_CLIENTID_SDMA1: - case SOC15_IH_CLIENTID_SDMA2: - case SOC15_IH_CLIENTID_SDMA3: - case SOC15_IH_CLIENTID_SDMA4: - block = AMDGPU_RAS_BLOCK__SDMA; - reset = AMDGPU_RAS_GPU_RESET_MODE2_RESET; - break; - default: - break; - } - - kfd_signal_poison_consumed_event(dev, pasid); - - /* resetting queue passes, do page retirement without gpu reset - * resetting queue fails, fallback to gpu reset solution - */ - if (!ret) - dev_warn(dev->adev->dev, - "RAS poison consumption, unmap queue flow succeeded: client id %d\n", - client_id); - else - dev_warn(dev->adev->dev, - "RAS poison consumption, fall back to gpu reset flow: client id %d\n", - client_id); - - amdgpu_amdkfd_ras_poison_consumption_handler(dev->adev, block, reset); -} - static bool event_interrupt_isr_v10(struct kfd_node *dev, const uint32_t *ih_ring_entry, uint32_t *patched_ihre, @@ -332,11 +275,6 @@ static void event_interrupt_wq_v10(struct kfd_node *dev, REG_GET_FIELD(context_id1, SQ_INTERRUPT_WORD_WAVE_CTXID1, WGP_ID), sq_intr_err_type); - if (sq_intr_err_type != SQ_INTERRUPT_ERROR_TYPE_ILLEGAL_INST && - sq_intr_err_type != SQ_INTERRUPT_ERROR_TYPE_MEMVIOL) { - event_interrupt_poison_consumption(dev, pasid, source_id); - return; - } break; default: break; @@ -362,9 +300,6 @@ static void event_interrupt_wq_v10(struct kfd_node *dev, client_id == SOC15_IH_CLIENTID_SDMA7) { if (source_id == SOC15_INTSRC_SDMA_TRAP) { kfd_signal_event_interrupt(pasid, context_id0 & 0xfffffff, 28); - } else if (source_id == SOC15_INTSRC_SDMA_ECC) { - event_interrupt_poison_consumption(dev, pasid, source_id); - return; } } else if (client_id == SOC15_IH_CLIENTID_VMC || client_id == SOC15_IH_CLIENTID_VMC1 || @@ -388,12 +323,6 @@ static void event_interrupt_wq_v10(struct kfd_node *dev, if (vmid_type && client_id == SOC15_IH_CLIENTID_VMC) hub_inst = node_id / 4; - if (amdgpu_amdkfd_ras_query_utcl2_poison_status(dev->adev, - hub_inst, vmid_type)) { - event_interrupt_poison_consumption(dev, pasid, client_id); - return; - } - info.vmid = vmid; info.mc_id = client_id; info.page_addr = ih_ring_entry[4] | From f6c431cc880c4408032cfa2820d22b2bd6270052 Mon Sep 17 00:00:00 2001 From: Kenneth Feng Date: Tue, 20 Aug 2024 08:57:15 +0800 Subject: [PATCH 1376/1868] drm/amd/pm: update message interface for smu v14.0.2/3 update message interface for smu v14.0.2/3 Signed-off-by: Kenneth Feng Reviewed-by: Yang Wang --- .../pm/swsmu/inc/pmfw_if/smu_v14_0_2_ppsmc.h | 18 ++++++++++++++---- .../drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c | 1 - 2 files changed, 14 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_2_ppsmc.h b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_2_ppsmc.h index de2e442281ffe..87ca5ceb1ece1 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_2_ppsmc.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v14_0_2_ppsmc.h @@ -92,7 +92,6 @@ //Resets #define PPSMC_MSG_PrepareMp1ForUnload 0x2E -#define PPSMC_MSG_Mode1Reset 0x2F //Set SystemVirtual DramAddrHigh #define PPSMC_MSG_SetSystemVirtualDramAddrHigh 0x30 @@ -119,11 +118,12 @@ //STB to dram log #define PPSMC_MSG_DumpSTBtoDram 0x3D -#define PPSMC_MSG_STBtoDramLogSetDramAddrHigh 0x3E -#define PPSMC_MSG_STBtoDramLogSetDramAddrLow 0x3F +#define PPSMC_MSG_STBtoDramLogSetDramAddress 0x3E +#define PPSMC_MSG_DummyUndefined 0x3F #define PPSMC_MSG_STBtoDramLogSetDramSize 0x40 #define PPSMC_MSG_SetOBMTraceBufferLogging 0x41 +#define PPSMC_MSG_UseProfilingMode 0x42 #define PPSMC_MSG_AllowGfxDcs 0x43 #define PPSMC_MSG_DisallowGfxDcs 0x44 #define PPSMC_MSG_EnableAudioStutterWA 0x45 @@ -135,6 +135,16 @@ #define PPSMC_MSG_SetBadMemoryPagesRetiredFlagsPerChannel 0x4B #define PPSMC_MSG_SetPriorityDeltaGain 0x4C #define PPSMC_MSG_AllowIHHostInterrupt 0x4D +#define PPSMC_MSG_EnableShadowDpm 0x4E #define PPSMC_MSG_Mode3Reset 0x4F -#define PPSMC_Message_Count 0x50 +#define PPSMC_MSG_SetDriverDramAddr 0x50 +#define PPSMC_MSG_SetToolsDramAddr 0x51 +#define PPSMC_MSG_TransferTableSmu2DramWithAddr 0x52 +#define PPSMC_MSG_TransferTableDram2SmuWithAddr 0x53 +#define PPSMC_MSG_GetAllRunningSmuFeatures 0x54 +#define PPSMC_MSG_GetSvi3Voltage 0x55 +#define PPSMC_MSG_UpdatePolicy 0x56 +#define PPSMC_MSG_ExtPwrConnSupport 0x57 +#define PPSMC_MSG_PreloadSwPstateForUclkOverDrive 0x58 +#define PPSMC_Message_Count 0x59 #endif diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c index 5913f9c60fe00..e000ac7b4c0e2 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c @@ -127,7 +127,6 @@ static struct cmn2asic_msg_mapping smu_v14_0_2_message_map[SMU_MSG_MAX_COUNT] = MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0), MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0), MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0), - MSG_MAP(Mode1Reset, PPSMC_MSG_Mode1Reset, 0), MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 0), MSG_MAP(DFCstateControl, PPSMC_MSG_SetExternalClientDfCstateAllow, 0), MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0), From e967900cbc2b41177fc0053f09efb622d2004511 Mon Sep 17 00:00:00 2001 From: Hawking Zhang Date: Mon, 19 Aug 2024 22:59:19 +0800 Subject: [PATCH 1377/1868] drm/amdgpu: Retire query_utcl2_poison_status callback Driver switches to interrupt source id to identify utcl2 poison event. polling interface is not needed. Signed-off-by: Hawking Zhang Reviewed-by: Tao Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 16 ---------------- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 2 -- drivers/gpu/drm/amd/amdgpu/amdgpu_gfxhub.h | 2 -- drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h | 2 -- drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 18 ------------------ drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c | 17 ----------------- drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c | 17 ----------------- 7 files changed, 74 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c index 99db574389e88..f43e634c8a211 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c @@ -795,22 +795,6 @@ int amdgpu_amdkfd_send_close_event_drain_irq(struct amdgpu_device *adev, return 0; } -bool amdgpu_amdkfd_ras_query_utcl2_poison_status(struct amdgpu_device *adev, - int hub_inst, int hub_type) -{ - if (!hub_type) { - if (adev->gfxhub.funcs->query_utcl2_poison_status) - return adev->gfxhub.funcs->query_utcl2_poison_status(adev, hub_inst); - else - return false; - } else { - if (adev->mmhub.funcs->query_utcl2_poison_status) - return adev->mmhub.funcs->query_utcl2_poison_status(adev, hub_inst); - else - return false; - } -} - int amdgpu_amdkfd_check_and_lock_kfd(struct amdgpu_device *adev) { return kgd2kfd_check_and_lock_kfd(); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index 6f82764c9606e..1b686697c9a88 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -415,8 +415,6 @@ bool amdgpu_amdkfd_is_fed(struct amdgpu_device *adev); bool amdgpu_amdkfd_bo_mapped_to_dev(void *drm_priv, struct kgd_mem *mem); void amdgpu_amdkfd_block_mmu_notifications(void *p); int amdgpu_amdkfd_criu_resume(void *p); -bool amdgpu_amdkfd_ras_query_utcl2_poison_status(struct amdgpu_device *adev, - int hub_inst, int hub_type); int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device *adev, uint64_t size, u32 alloc_flag, int8_t xcp_id); void amdgpu_amdkfd_unreserve_mem_limit(struct amdgpu_device *adev, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfxhub.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfxhub.h index 103a837ccc712..c7b44aeb671b0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfxhub.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfxhub.h @@ -38,8 +38,6 @@ struct amdgpu_gfxhub_funcs { void (*mode2_save_regs)(struct amdgpu_device *adev); void (*mode2_restore_regs)(struct amdgpu_device *adev); void (*halt)(struct amdgpu_device *adev); - bool (*query_utcl2_poison_status)(struct amdgpu_device *adev, - int xcc_id); }; struct amdgpu_gfxhub { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h index 95d676ee207f3..1ca9d4ed8063a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h @@ -63,8 +63,6 @@ struct amdgpu_mmhub_funcs { uint64_t page_table_base); void (*update_power_gating)(struct amdgpu_device *adev, bool enable); - bool (*query_utcl2_poison_status)(struct amdgpu_device *adev, - int hub_inst); }; struct amdgpu_mmhub { diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c index d200310d17319..0e3ddea7b8e0f 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c @@ -443,23 +443,6 @@ static void gfxhub_v1_0_init(struct amdgpu_device *adev) mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32; } -static bool gfxhub_v1_0_query_utcl2_poison_status(struct amdgpu_device *adev, - int xcc_id) -{ - u32 status = 0; - struct amdgpu_vmhub *hub; - - if (amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 2)) - return false; - - hub = &adev->vmhub[AMDGPU_GFXHUB(0)]; - status = RREG32(hub->vm_l2_pro_fault_status); - /* reset page fault status */ - WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1); - - return REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, FED); -} - const struct amdgpu_gfxhub_funcs gfxhub_v1_0_funcs = { .get_mc_fb_offset = gfxhub_v1_0_get_mc_fb_offset, .setup_vm_pt_regs = gfxhub_v1_0_setup_vm_pt_regs, @@ -468,5 +451,4 @@ const struct amdgpu_gfxhub_funcs gfxhub_v1_0_funcs = { .set_fault_enable_default = gfxhub_v1_0_set_fault_enable_default, .init = gfxhub_v1_0_init, .get_xgmi_info = gfxhub_v1_1_get_xgmi_info, - .query_utcl2_poison_status = gfxhub_v1_0_query_utcl2_poison_status, }; diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c index 72109abe7c86c..ed8e130c7d195 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.c @@ -622,22 +622,6 @@ static int gfxhub_v1_2_get_xgmi_info(struct amdgpu_device *adev) return 0; } -static bool gfxhub_v1_2_query_utcl2_poison_status(struct amdgpu_device *adev, - int xcc_id) -{ - u32 fed, status; - - status = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regVM_L2_PROTECTION_FAULT_STATUS); - fed = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, FED); - if (!amdgpu_sriov_vf(adev)) { - /* clear page fault status and address */ - WREG32_P(SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), - regVM_L2_PROTECTION_FAULT_CNTL), 1, ~1); - } - - return fed; -} - const struct amdgpu_gfxhub_funcs gfxhub_v1_2_funcs = { .get_mc_fb_offset = gfxhub_v1_2_get_mc_fb_offset, .setup_vm_pt_regs = gfxhub_v1_2_setup_vm_pt_regs, @@ -646,7 +630,6 @@ const struct amdgpu_gfxhub_funcs gfxhub_v1_2_funcs = { .set_fault_enable_default = gfxhub_v1_2_set_fault_enable_default, .init = gfxhub_v1_2_init, .get_xgmi_info = gfxhub_v1_2_get_xgmi_info, - .query_utcl2_poison_status = gfxhub_v1_2_query_utcl2_poison_status, }; static int gfxhub_v1_2_xcp_resume(void *handle, uint32_t inst_mask) diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c index 915203b91c5fb..b01bb759d0f4f 100644 --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.c @@ -559,22 +559,6 @@ static void mmhub_v1_8_get_clockgating(struct amdgpu_device *adev, u64 *flags) } -static bool mmhub_v1_8_query_utcl2_poison_status(struct amdgpu_device *adev, - int hub_inst) -{ - u32 fed, status; - - status = RREG32_SOC15(MMHUB, hub_inst, regVM_L2_PROTECTION_FAULT_STATUS); - fed = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, FED); - if (!amdgpu_sriov_vf(adev)) { - /* clear page fault status and address */ - WREG32_P(SOC15_REG_OFFSET(MMHUB, hub_inst, - regVM_L2_PROTECTION_FAULT_CNTL), 1, ~1); - } - - return fed; -} - const struct amdgpu_mmhub_funcs mmhub_v1_8_funcs = { .get_fb_location = mmhub_v1_8_get_fb_location, .init = mmhub_v1_8_init, @@ -584,7 +568,6 @@ const struct amdgpu_mmhub_funcs mmhub_v1_8_funcs = { .setup_vm_pt_regs = mmhub_v1_8_setup_vm_pt_regs, .set_clockgating = mmhub_v1_8_set_clockgating, .get_clockgating = mmhub_v1_8_get_clockgating, - .query_utcl2_poison_status = mmhub_v1_8_query_utcl2_poison_status, }; static const struct amdgpu_ras_err_status_reg_entry mmhub_v1_8_ce_reg_list[] = { From 619bd3d145aad52d6e76245e4dc9f30f8c76d01d Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 20 Aug 2024 13:11:22 -0400 Subject: [PATCH 1378/1868] drm/amdgpu/gfx12: set UNORD_DISPATCH in compute MQDs This needs to be set to 1 to avoid a potential deadlock in the GC 10.x and newer. On GC 9.x and older, this needs to be set to 0. This can lead to hangs in some mixed graphics and compute workloads. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3575 Reviewed-by: Hawking Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c index f14e27f86e0eb..54059cbcfc089 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c @@ -3054,7 +3054,7 @@ static int gfx_v12_0_compute_mqd_init(struct amdgpu_device *adev, void *m, (order_base_2(prop->queue_size / 4) - 1)); tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); - tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); + tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 1); tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c index b7a08e7a44234..d163d92a692f6 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c @@ -187,6 +187,7 @@ static void update_mqd(struct mqd_manager *mm, void *mqd, m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT; m->cp_hqd_pq_control |= ffs(q->queue_size / sizeof(unsigned int)) - 1 - 1; + m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__UNORD_DISPATCH_MASK; pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control); m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); From 2330d8f5cd12f4439368731d6745b1ca5b3ab56b Mon Sep 17 00:00:00 2001 From: Jinjie Ruan Date: Wed, 21 Aug 2024 14:40:36 +0800 Subject: [PATCH 1379/1868] drm/amd/display: Make core_dcn4_g6_temp_read_blackout_table static The sparse tool complains as follows: drivers/gpu/drm/amd/amdgpu/../display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c:6853:56: warning: symbol 'core_dcn4_g6_temp_read_blackout_table' was not declared. Should it be static? This symbol is not used outside of dml2_core_dcn4_calcs.c, so marks it static. And not want to change it, so mark it const. Signed-off-by: Jinjie Ruan Signed-off-by: Alex Deucher --- .../display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c index e2c45e498664e..805fd783131f4 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c @@ -6887,7 +6887,8 @@ struct dml2_core_internal_g6_temp_read_blackouts_table { } entries[DML_MAX_CLK_TABLE_SIZE]; }; -struct dml2_core_internal_g6_temp_read_blackouts_table core_dcn4_g6_temp_read_blackout_table = { +static const struct dml2_core_internal_g6_temp_read_blackouts_table + core_dcn4_g6_temp_read_blackout_table = { .entries = { { .uclk_khz = 96000, From 69a6495c373187e272bf97120eabdd7e1799afdc Mon Sep 17 00:00:00 2001 From: Jinjie Ruan Date: Wed, 21 Aug 2024 14:40:37 +0800 Subject: [PATCH 1380/1868] drm/amd/display: Make core_dcn4_ip_caps_base static The sparse tool complains as follows: drivers/gpu/drm/amd/amdgpu/../display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c:12:28: warning: symbol 'core_dcn4_ip_caps_base' was not declared. Should it be static? This symbol is not used outside of dcn35_hubp.c, so marks it static. And do not want to change it, so mark it const. Signed-off-by: Jinjie Ruan Signed-off-by: Alex Deucher --- .../amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c index 698307f3ca39d..0aa4e4d343b04 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c @@ -9,7 +9,7 @@ #include "dml2_debug.h" #include "lib_float_math.h" -struct dml2_core_ip_params core_dcn4_ip_caps_base = { +static const struct dml2_core_ip_params core_dcn4_ip_caps_base = { // Hardcoded values for DCN3x .vblank_nom_default_us = 668, .remote_iommu_outstanding_translations = 256, From 7000618fb5623a4831c373b2133f1cc741c11f83 Mon Sep 17 00:00:00 2001 From: Jinjie Ruan Date: Wed, 21 Aug 2024 14:40:38 +0800 Subject: [PATCH 1381/1868] drm/amd/display: Make dcn35_hubp_funcs static The sparse tool complains as follows: drivers/gpu/drm/amd/amdgpu/../display/dc/hubp/dcn35/dcn35_hubp.c:191:19: warning: symbol 'dcn35_hubp_funcs' was not declared. Should it be static? This symbol is not used outside of dcn35_hubp.c, so marks it static. Signed-off-by: Jinjie Ruan Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c index 771fcd0d3b991..d1f05b82b3dd5 100644 --- a/drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c +++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn35/dcn35_hubp.c @@ -188,7 +188,7 @@ void hubp35_program_surface_config( hubp35_program_pixel_format(hubp, format); } -struct hubp_funcs dcn35_hubp_funcs = { +static struct hubp_funcs dcn35_hubp_funcs = { .hubp_enable_tripleBuffer = hubp2_enable_triplebuffer, .hubp_is_triplebuffer_enabled = hubp2_is_triplebuffer_enabled, .hubp_program_surface_flip_and_addr = hubp3_program_surface_flip_and_addr, From b1e9bf4138cdab2fac28dd5edb131342267647fa Mon Sep 17 00:00:00 2001 From: Jinjie Ruan Date: Wed, 21 Aug 2024 14:40:39 +0800 Subject: [PATCH 1382/1868] drm/amd/display: Make dcn401_dsc_funcs static The sparse tool complains as follows: drivers/gpu/drm/amd/amdgpu/../display/dc/dsc/dcn401/dcn401_dsc.c:30:24: warning: symbol 'dcn401_dsc_funcs' was not declared. Should it be static? This symbol is not used outside of dcn401_dsc.c, so marks it static. Signed-off-by: Jinjie Ruan Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c index 6acb6699f146e..61678b0a5a1e7 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c @@ -27,7 +27,7 @@ static void dsc401_disconnect(struct display_stream_compressor *dsc); static void dsc401_wait_disconnect_pending_clear(struct display_stream_compressor *dsc); static void dsc401_get_enc_caps(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz); -const struct dsc_funcs dcn401_dsc_funcs = { +static const struct dsc_funcs dcn401_dsc_funcs = { .dsc_get_enc_caps = dsc401_get_enc_caps, .dsc_read_state = dsc401_read_state, .dsc_validate_stream = dsc401_validate_stream, From 1207685205ba597afd2057aee3643b98369a38f3 Mon Sep 17 00:00:00 2001 From: Yang Wang Date: Wed, 21 Aug 2024 14:42:41 +0800 Subject: [PATCH 1383/1868] drm/amdgpu: add list empty check to avoid null pointer issue Add list empty check to avoid null pointer issues in some corner cases. - list_for_each_entry_safe() Signed-off-by: Yang Wang Reviewed-by: Tao Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c index fa8245f326a64..c8aed31fb7f0a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c @@ -80,6 +80,9 @@ static void aca_banks_release(struct aca_banks *banks) { struct aca_bank_node *node, *tmp; + if (list_empty(&banks->list)) + return; + list_for_each_entry_safe(node, tmp, &banks->list, node) { list_del(&node->node); kvfree(node); @@ -562,9 +565,13 @@ static void aca_error_fini(struct aca_error *aerr) struct aca_bank_error *bank_error, *tmp; mutex_lock(&aerr->lock); + if (list_empty(&aerr->list)) + goto out_unlock; + list_for_each_entry_safe(bank_error, tmp, &aerr->list, node) aca_bank_error_remove(aerr, bank_error); +out_unlock: mutex_destroy(&aerr->lock); } @@ -680,6 +687,9 @@ static void aca_manager_fini(struct aca_handle_manager *mgr) { struct aca_handle *handle, *tmp; + if (list_empty(&mgr->list)) + return; + list_for_each_entry_safe(handle, tmp, &mgr->list, node) amdgpu_aca_remove_handle(handle); } From 2bfe4c4a2fce74d0f1d585955208019c67f377ea Mon Sep 17 00:00:00 2001 From: Ma Ke Date: Wed, 21 Aug 2024 12:27:24 +0800 Subject: [PATCH 1384/1868] drm/amd/display: avoid using null object of framebuffer Instead of using state->fb->obj[0] directly, get object from framebuffer by calling drm_gem_fb_get_obj() and return error code when object is null to avoid using null object of framebuffer. Cc: stable@vger.kernel.org Fixes: 5d945cbcd4b1 ("drm/amd/display: Create a file dedicated to planes") Signed-off-by: Ma Ke Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 68d546ad61b09..e68b7feb284b5 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -28,6 +28,7 @@ #include #include #include +#include #include #include "amdgpu.h" @@ -1011,9 +1012,13 @@ static int amdgpu_dm_plane_helper_prepare_fb(struct drm_plane *plane, afb = to_amdgpu_framebuffer(new_state->fb); obj = drm_gem_fb_get_obj(new_state->fb, 0); + if (!obj) { + DRM_ERROR("Failed to get obj from framebuffer\n"); + return -EINVAL; + } + rbo = gem_to_amdgpu_bo(obj); adev = amdgpu_ttm_adev(rbo->tbo.bdev); - r = amdgpu_bo_reserve(rbo, true); if (r) { dev_err(adev->dev, "fail to reserve bo (%d)\n", r); From e396d77f0c4ee9bc5443342292741279ebf7b5be Mon Sep 17 00:00:00 2001 From: Likun Gao Date: Thu, 22 Aug 2024 11:44:12 +0800 Subject: [PATCH 1385/1868] drm/amdgpu: support for gc_info table v1.3 Add gc_info table v1.3 for IP discovery. Signed-off-by: Likun Gao Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 11 +++++ drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 6 +++ drivers/gpu/drm/amd/include/discovery.h | 42 +++++++++++++++++++ 3 files changed, 59 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index cc7bb0bad4e75..3f3ff849f9bde 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -1522,6 +1522,7 @@ union gc_info { struct gc_info_v1_0 v1; struct gc_info_v1_1 v1_1; struct gc_info_v1_2 v1_2; + struct gc_info_v1_3 v1_3; struct gc_info_v2_0 v2; struct gc_info_v2_1 v2_1; }; @@ -1580,6 +1581,16 @@ static int amdgpu_discovery_get_gfx_info(struct amdgpu_device *adev) adev->gfx.config.gc_gl1c_size_per_instance = le32_to_cpu(gc_info->v1_2.gc_gl1c_size_per_instance); adev->gfx.config.gc_gl2c_per_gpu = le32_to_cpu(gc_info->v1_2.gc_gl2c_per_gpu); } + if (le16_to_cpu(gc_info->v1.header.version_minor) >= 3) { + adev->gfx.config.gc_tcp_size_per_cu = le32_to_cpu(gc_info->v1_3.gc_tcp_size_per_cu); + adev->gfx.config.gc_tcp_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_tcp_cache_line_size); + adev->gfx.config.gc_instruction_cache_size_per_sqc = le32_to_cpu(gc_info->v1_3.gc_instruction_cache_size_per_sqc); + adev->gfx.config.gc_instruction_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_instruction_cache_line_size); + adev->gfx.config.gc_scalar_data_cache_size_per_sqc = le32_to_cpu(gc_info->v1_3.gc_scalar_data_cache_size_per_sqc); + adev->gfx.config.gc_scalar_data_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_scalar_data_cache_line_size); + adev->gfx.config.gc_tcc_size = le32_to_cpu(gc_info->v1_3.gc_tcc_size); + adev->gfx.config.gc_tcc_cache_line_size = le32_to_cpu(gc_info->v1_3.gc_tcc_cache_line_size); + } break; case 2: adev->gfx.config.max_shader_engines = le32_to_cpu(gc_info->v2.gc_num_se); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h index 3f3f50c1f6360..793c9b89beee1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h @@ -254,6 +254,12 @@ struct amdgpu_gfx_config { uint32_t gc_tcp_size_per_cu; uint32_t gc_num_cu_per_sqc; uint32_t gc_tcc_size; + uint32_t gc_tcp_cache_line_size; + uint32_t gc_instruction_cache_size_per_sqc; + uint32_t gc_instruction_cache_line_size; + uint32_t gc_scalar_data_cache_size_per_sqc; + uint32_t gc_scalar_data_cache_line_size; + uint32_t gc_tcc_cache_line_size; }; struct amdgpu_cu_info { diff --git a/drivers/gpu/drm/amd/include/discovery.h b/drivers/gpu/drm/amd/include/discovery.h index 46bf19c9c5c40..710e328fad48f 100644 --- a/drivers/gpu/drm/amd/include/discovery.h +++ b/drivers/gpu/drm/amd/include/discovery.h @@ -258,6 +258,48 @@ struct gc_info_v1_2 { uint32_t gc_gl2c_per_gpu; }; +struct gc_info_v1_3 { + struct gpu_info_header header; + uint32_t gc_num_se; + uint32_t gc_num_wgp0_per_sa; + uint32_t gc_num_wgp1_per_sa; + uint32_t gc_num_rb_per_se; + uint32_t gc_num_gl2c; + uint32_t gc_num_gprs; + uint32_t gc_num_max_gs_thds; + uint32_t gc_gs_table_depth; + uint32_t gc_gsprim_buff_depth; + uint32_t gc_parameter_cache_depth; + uint32_t gc_double_offchip_lds_buffer; + uint32_t gc_wave_size; + uint32_t gc_max_waves_per_simd; + uint32_t gc_max_scratch_slots_per_cu; + uint32_t gc_lds_size; + uint32_t gc_num_sc_per_se; + uint32_t gc_num_sa_per_se; + uint32_t gc_num_packer_per_sc; + uint32_t gc_num_gl2a; + uint32_t gc_num_tcp_per_sa; + uint32_t gc_num_sdp_interface; + uint32_t gc_num_tcps; + uint32_t gc_num_tcp_per_wpg; + uint32_t gc_tcp_l1_size; + uint32_t gc_num_sqc_per_wgp; + uint32_t gc_l1_instruction_cache_size_per_sqc; + uint32_t gc_l1_data_cache_size_per_sqc; + uint32_t gc_gl1c_per_sa; + uint32_t gc_gl1c_size_per_instance; + uint32_t gc_gl2c_per_gpu; + uint32_t gc_tcp_size_per_cu; + uint32_t gc_tcp_cache_line_size; + uint32_t gc_instruction_cache_size_per_sqc; + uint32_t gc_instruction_cache_line_size; + uint32_t gc_scalar_data_cache_size_per_sqc; + uint32_t gc_scalar_data_cache_line_size; + uint32_t gc_tcc_size; + uint32_t gc_tcc_cache_line_size; +}; + struct gc_info_v2_0 { struct gpu_info_header header; From 8f17eb4e21758fddcb88ff2a9917be6c45229de5 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Fri, 16 Aug 2024 14:34:17 +0530 Subject: [PATCH 1386/1868] drm/amd/pm: Add support for new P2S table revision Add p2s table support for a new revision of SMUv13.0.6. Signed-off-by: Lijo Lazar Reviewed-by: Hawking Zhang Reviewed-by: Asad Kamal Acked-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index 63fa903b3889a..8cf36e53fc701 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -121,6 +121,7 @@ struct mca_ras_info { #define P2S_TABLE_ID_A 0x50325341 #define P2S_TABLE_ID_X 0x50325358 +#define P2S_TABLE_ID_3 0x50325303 // clang-format off static const struct cmn2asic_msg_mapping smu_v13_0_6_message_map[SMU_MSG_MAX_COUNT] = { @@ -278,14 +279,18 @@ static int smu_v13_0_6_init_microcode(struct smu_context *smu) struct amdgpu_device *adev = smu->adev; uint32_t p2s_table_id = P2S_TABLE_ID_A; int ret = 0, i, p2stable_count; + int var = (adev->pdev->device & 0xF); char ucode_prefix[15]; /* No need to load P2S tables in IOV mode */ if (amdgpu_sriov_vf(adev)) return 0; - if (!(adev->flags & AMD_IS_APU)) + if (!(adev->flags & AMD_IS_APU)) { p2s_table_id = P2S_TABLE_ID_X; + if (var == 0x5) + p2s_table_id = P2S_TABLE_ID_3; + } amdgpu_ucode_ip_version_decode(adev, MP1_HWIP, ucode_prefix, sizeof(ucode_prefix)); From d11b8b16544d35061fdf48fb5807953b3692c7f6 Mon Sep 17 00:00:00 2001 From: Xiaogang Chen Date: Fri, 23 Aug 2024 02:04:09 -0500 Subject: [PATCH 1387/1868] drm/amdkfd: Change kfd/svm page fault drain handling When app unmap vm ranges(munmap) kfd/svm starts drain pending page fault and not handle any incoming pages fault of this process until a deferred work item got executed by default system wq. The time period of "not handle page fault" can be long and is unpredicable. That is advese to kfd performance on page faults recovery. This patch uses time stamp of incoming page fault to decide to drop or recover page fault. When app unmap vm ranges kfd records each gpu device's ih ring current time stamp. These time stamps are used at kfd page fault recovery routine. Any page fault happened on unmapped ranges after unmap events is application bug that accesses vm range after unmap. It is not driver work to cover that. By using time stamp of page fault do not need drain page faults at deferred work. So, the time period that kfd does not handle page faults is reduced and can be controlled. Signed-off-by: Xiaogang.Chen Reviewed-by: Philip Yang --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 4 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 2 +- drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 3 +- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 4 +- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 2 + drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 95 +++++++++++++++++--------- drivers/gpu/drm/amd/amdkfd/kfd_svm.h | 4 +- 7 files changed, 73 insertions(+), 41 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 96aa2aaa3eca0..dad39fe611e25 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -2846,7 +2846,7 @@ int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) * shouldn't be reported any more. */ bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid, - u32 vmid, u32 node_id, uint64_t addr, + u32 vmid, u32 node_id, uint64_t addr, uint64_t ts, bool write_fault) { bool is_compute_context = false; @@ -2881,7 +2881,7 @@ bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid, addr /= AMDGPU_GPU_PAGE_SIZE; if (is_compute_context && !svm_range_restore_pages(adev, pasid, vmid, - node_id, addr, write_fault)) { + node_id, addr, ts, write_fault)) { amdgpu_bo_unref(&root); return true; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h index 96e483bddd7bf..41de3691aef9a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h @@ -567,7 +567,7 @@ amdgpu_vm_get_task_info_vm(struct amdgpu_vm *vm); void amdgpu_vm_put_task_info(struct amdgpu_task_info *task_info); bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid, - u32 vmid, u32 node_id, uint64_t addr, + u32 vmid, u32 node_id, uint64_t addr, uint64_t ts, bool write_fault); void amdgpu_vm_set_task_info(struct amdgpu_vm *vm); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c index fe30dec1b8d74..ff0ed314661fd 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c @@ -132,7 +132,8 @@ static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev, /* Try to handle the recoverable page faults by filling page * tables */ - if (amdgpu_vm_handle_fault(adev, entry->pasid, 0, 0, addr, write_fault)) + if (amdgpu_vm_handle_fault(adev, entry->pasid, 0, 0, addr, + entry->timestamp, write_fault)) return 1; } diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index 4c5a076b37a1b..0a5c8d97787a7 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -597,7 +597,7 @@ static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev, cam_index = entry->src_data[2] & 0x3ff; ret = amdgpu_vm_handle_fault(adev, entry->pasid, entry->vmid, node_id, - addr, write_fault); + addr, entry->timestamp, write_fault); WDOORBELL32(adev->irq.retry_cam_doorbell_index, cam_index); if (ret) return 1; @@ -620,7 +620,7 @@ static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev, * tables */ if (amdgpu_vm_handle_fault(adev, entry->pasid, entry->vmid, node_id, - addr, write_fault)) + addr, entry->timestamp, write_fault)) return 1; } } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index a2a547f3d3cfb..1351104b825c9 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -960,6 +960,8 @@ struct svm_range_list { struct delayed_work restore_work; DECLARE_BITMAP(bitmap_supported, MAX_GPU_INSTANCE); struct task_struct *faulting_task; + /* check point ts decides if page fault recovery need be dropped */ + uint64_t checkpoint_ts[MAX_GPU_INSTANCE]; }; /* Process data */ diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c index b55a0cce07fcf..cbc89749207b6 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c @@ -2260,16 +2260,10 @@ static void svm_range_drain_retry_fault(struct svm_range_list *svms) { struct kfd_process_device *pdd; struct kfd_process *p; - int drain; uint32_t i; p = container_of(svms, struct kfd_process, svms); -restart: - drain = atomic_read(&svms->drain_pagefaults); - if (!drain) - return; - for_each_set_bit(i, svms->bitmap_supported, p->n_pdds) { pdd = p->pdds[i]; if (!pdd) @@ -2289,8 +2283,6 @@ static void svm_range_drain_retry_fault(struct svm_range_list *svms) pr_debug("drain retry fault gpu %d svms 0x%p done\n", i, svms); } - if (atomic_cmpxchg(&svms->drain_pagefaults, drain, 0) != drain) - goto restart; } static void svm_range_deferred_list_work(struct work_struct *work) @@ -2312,17 +2304,8 @@ static void svm_range_deferred_list_work(struct work_struct *work) prange->start, prange->last, prange->work_item.op); mm = prange->work_item.mm; -retry: - mmap_write_lock(mm); - /* Checking for the need to drain retry faults must be inside - * mmap write lock to serialize with munmap notifiers. - */ - if (unlikely(atomic_read(&svms->drain_pagefaults))) { - mmap_write_unlock(mm); - svm_range_drain_retry_fault(svms); - goto retry; - } + mmap_write_lock(mm); /* Remove from deferred_list must be inside mmap write lock, for * two race cases: @@ -2443,6 +2426,7 @@ svm_range_unmap_from_cpu(struct mm_struct *mm, struct svm_range *prange, struct kfd_process *p; unsigned long s, l; bool unmap_parent; + uint32_t i; if (atomic_read(&prange->queue_refcount)) { int r; @@ -2462,11 +2446,35 @@ svm_range_unmap_from_cpu(struct mm_struct *mm, struct svm_range *prange, pr_debug("svms 0x%p prange 0x%p [0x%lx 0x%lx] [0x%lx 0x%lx]\n", svms, prange, prange->start, prange->last, start, last); - /* Make sure pending page faults are drained in the deferred worker - * before the range is freed to avoid straggler interrupts on - * unmapped memory causing "phantom faults". + /* calculate time stamps that are used to decide which page faults need be + * dropped or handled before unmap pages from gpu vm */ - atomic_inc(&svms->drain_pagefaults); + for_each_set_bit(i, svms->bitmap_supported, p->n_pdds) { + struct kfd_process_device *pdd; + struct amdgpu_device *adev; + struct amdgpu_ih_ring *ih; + uint32_t checkpoint_wptr; + + pdd = p->pdds[i]; + if (!pdd) + continue; + + adev = pdd->dev->adev; + + /* Check and drain ih1 ring if cam not available */ + ih = &adev->irq.ih1; + checkpoint_wptr = amdgpu_ih_get_wptr(adev, ih); + if (ih->rptr != checkpoint_wptr) { + svms->checkpoint_ts[i] = amdgpu_ih_decode_iv_ts(adev, ih, checkpoint_wptr, -1); + continue; + } + + /* check if dev->irq.ih_soft is not empty */ + ih = &adev->irq.ih_soft; + checkpoint_wptr = amdgpu_ih_get_wptr(adev, ih); + if (ih->rptr != checkpoint_wptr) + svms->checkpoint_ts[i] = amdgpu_ih_decode_iv_ts(adev, ih, checkpoint_wptr, -1); + } unmap_parent = start <= prange->start && last >= prange->last; @@ -2907,7 +2915,7 @@ svm_fault_allowed(struct vm_area_struct *vma, bool write_fault) int svm_range_restore_pages(struct amdgpu_device *adev, unsigned int pasid, uint32_t vmid, uint32_t node_id, - uint64_t addr, bool write_fault) + uint64_t addr, uint64_t ts, bool write_fault) { unsigned long start, last, size; struct mm_struct *mm = NULL; @@ -2917,7 +2925,7 @@ svm_range_restore_pages(struct amdgpu_device *adev, unsigned int pasid, ktime_t timestamp = ktime_get_boottime(); struct kfd_node *node; int32_t best_loc; - int32_t gpuidx = MAX_GPU_INSTANCE; + int32_t gpuid, gpuidx = MAX_GPU_INSTANCE; bool write_locked = false; struct vm_area_struct *vma; bool migration = false; @@ -2938,11 +2946,38 @@ svm_range_restore_pages(struct amdgpu_device *adev, unsigned int pasid, pr_debug("restoring svms 0x%p fault address 0x%llx\n", svms, addr); if (atomic_read(&svms->drain_pagefaults)) { - pr_debug("draining retry fault, drop fault 0x%llx\n", addr); + pr_debug("page fault handling disabled, drop fault 0x%llx\n", addr); r = 0; goto out; } + node = kfd_node_by_irq_ids(adev, node_id, vmid); + if (!node) { + pr_debug("kfd node does not exist node_id: %d, vmid: %d\n", node_id, + vmid); + r = -EFAULT; + goto out; + } + + if (kfd_process_gpuid_from_node(p, node, &gpuid, &gpuidx)) { + pr_debug("failed to get gpuid/gpuidex for node_id: %d\n", node_id); + r = -EFAULT; + goto out; + } + + /* check if this page fault time stamp is before svms->checkpoint_ts */ + if (svms->checkpoint_ts[gpuidx] != 0) { + if (amdgpu_ih_ts_after(ts, svms->checkpoint_ts[gpuidx])) { + pr_debug("draining retry fault, drop fault 0x%llx\n", addr); + r = 0; + goto out; + } else + /* ts is after svms->checkpoint_ts now, reset svms->checkpoint_ts + * to zero to avoid following ts wrap around give wrong comparing + */ + svms->checkpoint_ts[gpuidx] = 0; + } + if (!p->xnack_enabled) { pr_debug("XNACK not enabled for pasid 0x%x\n", pasid); r = -EFAULT; @@ -2959,13 +2994,6 @@ svm_range_restore_pages(struct amdgpu_device *adev, unsigned int pasid, goto out; } - node = kfd_node_by_irq_ids(adev, node_id, vmid); - if (!node) { - pr_debug("kfd node does not exist node_id: %d, vmid: %d\n", node_id, - vmid); - r = -EFAULT; - goto out; - } mmap_read_lock(mm); retry_write_locked: mutex_lock(&svms->lock); @@ -3180,8 +3208,9 @@ void svm_range_list_fini(struct kfd_process *p) /* * Ensure no retry fault comes in afterwards, as page fault handler will * not find kfd process and take mm lock to recover fault. + * stop kfd page fault handing, then wait pending page faults got drained */ - atomic_inc(&p->svms.drain_pagefaults); + atomic_set(&p->svms.drain_pagefaults, 1); svm_range_drain_retry_fault(&p->svms); list_for_each_entry_safe(prange, next, &p->svms.list, list) { diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.h b/drivers/gpu/drm/amd/amdkfd/kfd_svm.h index 747325a2ea896..bddd24f04669e 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.h @@ -174,7 +174,7 @@ int svm_range_vram_node_new(struct kfd_node *node, struct svm_range *prange, bool clear); void svm_range_vram_node_free(struct svm_range *prange); int svm_range_restore_pages(struct amdgpu_device *adev, unsigned int pasid, - uint32_t vmid, uint32_t node_id, uint64_t addr, + uint32_t vmid, uint32_t node_id, uint64_t addr, uint64_t ts, bool write_fault); int svm_range_schedule_evict_svm_bo(struct amdgpu_amdkfd_fence *fence); void svm_range_add_list_work(struct svm_range_list *svms, @@ -225,7 +225,7 @@ static inline void svm_range_list_fini(struct kfd_process *p) static inline int svm_range_restore_pages(struct amdgpu_device *adev, unsigned int pasid, uint32_t client_id, uint32_t node_id, - uint64_t addr, bool write_fault) + uint64_t addr, uint64_t ts, bool write_fault) { return -EFAULT; } From 6f76a7cfe73216bc7485e5e16d53ed7a6cbf5805 Mon Sep 17 00:00:00 2001 From: Candice Li Date: Wed, 21 Aug 2024 13:10:58 +0800 Subject: [PATCH 1388/1868] drm/amd/pm: Drop unsupported features on smu v14_0_2 Drop unsupported features on smu v14_0_2. Signed-off-by: Candice Li Reviewed-by: Yang Wang Acked-by: Alex Deucher --- .../drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c | 47 ------------------- 1 file changed, 47 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c index e000ac7b4c0e2..a31fae5feedfe 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c @@ -2114,50 +2114,6 @@ static void smu_v14_0_2_set_smu_mailbox_registers(struct smu_context *smu) smu->debug_resp_reg = SOC15_REG_OFFSET(MP1, 0, regMP1_SMN_C2PMSG_54); } -static int smu_v14_0_2_smu_send_bad_mem_page_num(struct smu_context *smu, - uint32_t size) -{ - int ret = 0; - - /* message SMU to update the bad page number on SMUBUS */ - ret = smu_cmn_send_smc_msg_with_param(smu, - SMU_MSG_SetNumBadMemoryPagesRetired, - size, NULL); - if (ret) - dev_err(smu->adev->dev, - "[%s] failed to message SMU to update bad memory pages number\n", - __func__); - - return ret; -} - -static int smu_v14_0_2_send_bad_mem_channel_flag(struct smu_context *smu, - uint32_t size) -{ - int ret = 0; - - /* message SMU to update the bad channel info on SMUBUS */ - ret = smu_cmn_send_smc_msg_with_param(smu, - SMU_MSG_SetBadMemoryPagesRetiredFlagsPerChannel, - size, NULL); - if (ret) - dev_err(smu->adev->dev, - "[%s] failed to message SMU to update bad memory pages channel info\n", - __func__); - - return ret; -} - -static ssize_t smu_v14_0_2_get_ecc_info(struct smu_context *smu, - void *table) -{ - int ret = 0; - - // TODO - - return ret; -} - static ssize_t smu_v14_0_2_get_gpu_metrics(struct smu_context *smu, void **table) { @@ -2896,12 +2852,9 @@ static const struct pptable_funcs smu_v14_0_2_ppt_funcs = { .enable_gfx_features = smu_v14_0_2_enable_gfx_features, .set_mp1_state = smu_v14_0_2_set_mp1_state, .set_df_cstate = smu_v14_0_2_set_df_cstate, - .send_hbm_bad_pages_num = smu_v14_0_2_smu_send_bad_mem_page_num, - .send_hbm_bad_channel_flag = smu_v14_0_2_send_bad_mem_channel_flag, #if 0 .gpo_control = smu_v14_0_gpo_control, #endif - .get_ecc_info = smu_v14_0_2_get_ecc_info, }; void smu_v14_0_2_set_ppt_funcs(struct smu_context *smu) From d05e196a1e7ce86f1b492654a1da582c0094407d Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 21 Aug 2024 14:32:02 -0400 Subject: [PATCH 1389/1868] drm/amdgpu: align pp_power_profile_mode with kernel docs The kernel doc says you need to select manual mode to adjust this, but the code only allows you to adjust it when manual mode is not selected. Remove the manual mode check. Reviewed-by: Kenneth Feng Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 86de840d65409..02017b0d9573e 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -2265,8 +2265,7 @@ static int smu_adjust_power_state_dynamic(struct smu_context *smu, smu_dpm_ctx->dpm_level = level; } - if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && - smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { + if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { index = fls(smu->workload_mask); index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; workload[0] = smu->workload_setting[index]; @@ -2343,8 +2342,7 @@ static int smu_switch_power_profile(void *handle, workload[0] = smu->workload_setting[index]; } - if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && - smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) + if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) smu_bump_power_profile_mode(smu, workload, 0); return 0; From cd51e78cb1495b9465b79541f94125fb55fb7f39 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 22 Aug 2024 15:16:11 -0400 Subject: [PATCH 1390/1868] drm/amdgpu/swsmu: fix ordering for setting workload_mask No change in functionality for the current code, but we need to set the index properly before changing it if we ever use a non-0 index. Reviewed-by: Kenneth Feng Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 02017b0d9573e..52083277b70da 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -1257,7 +1257,6 @@ static int smu_sw_init(void *handle) atomic_set(&smu->smu_power.power_gate.vpe_gated, 1); atomic_set(&smu->smu_power.power_gate.umsch_mm_gated, 1); - smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT]; smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0; smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1; smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2; @@ -1265,6 +1264,7 @@ static int smu_sw_init(void *handle) smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4; smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5; smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6; + smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT]; smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT; smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D; From 525cbcac1fbc23b0cd5b541f53f42c4da519eeaa Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 22 Aug 2024 16:20:10 -0400 Subject: [PATCH 1391/1868] drm/amdgpu/smu13.0.7: print index for profiles Print the index for the profiles. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3543 Reviewed-by: Kenneth Feng Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c index a7d0231727e8f..7bc95c4043778 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c @@ -2378,7 +2378,7 @@ static int smu_v13_0_7_get_power_profile_mode(struct smu_context *smu, char *buf size += sysfs_emit_at(buf, size, " "); for (i = 0; i <= PP_SMC_POWER_PROFILE_WINDOW3D; i++) - size += sysfs_emit_at(buf, size, "%-14s%s", amdgpu_pp_profile_name[i], + size += sysfs_emit_at(buf, size, "%d %-14s%s", i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "* " : " "); size += sysfs_emit_at(buf, size, "\n"); @@ -2408,7 +2408,7 @@ static int smu_v13_0_7_get_power_profile_mode(struct smu_context *smu, char *buf do { \ size += sysfs_emit_at(buf, size, "%-30s", #field); \ for (j = 0; j <= PP_SMC_POWER_PROFILE_WINDOW3D; j++) \ - size += sysfs_emit_at(buf, size, "%-16d", activity_monitor_external[j].DpmActivityMonitorCoeffInt.field); \ + size += sysfs_emit_at(buf, size, "%-18d", activity_monitor_external[j].DpmActivityMonitorCoeffInt.field); \ size += sysfs_emit_at(buf, size, "\n"); \ } while (0) From cf48d879a0cc6abdeffc4958fa9a1c34c606c22f Mon Sep 17 00:00:00 2001 From: Leo Li Date: Tue, 6 Aug 2024 13:29:13 -0400 Subject: [PATCH 1392/1868] drm/amd: Introduce additional IPS debug flags [Why] Idle power states (IPS) describe levels of power-gating within DCN. DM and DC is responsible for ensuring that we are out of IPS before any DCN programming happens. Any DCN programming while we're in IPS leads to undefined behavior (mostly hangs). Because IPS intersects with all display features, the ability to disable IPS by default while ironing out the known issues is desired. However, disabing it completely will cause important features such as s0ix entry to fail. Therefore, more granular IPS debug flags are desired. [How] Extend the dc debug mask bits to include the available list of IPS debug flags. All the flags should work as documented, with the exception of IPS_DISABLE_DYNAMIC. It requires dm changes which will be done in later changes. v2: enable docs and fix docstring format Signed-off-by: Leo Li Reviewed-by: Aurabindo Pillai --- Documentation/gpu/amdgpu/driver-core.rst | 2 +- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 ++ drivers/gpu/drm/amd/include/amd_shared.h | 75 ++++++++++++++++++- 3 files changed, 81 insertions(+), 2 deletions(-) diff --git a/Documentation/gpu/amdgpu/driver-core.rst b/Documentation/gpu/amdgpu/driver-core.rst index 467e6843aef63..32723a925377e 100644 --- a/Documentation/gpu/amdgpu/driver-core.rst +++ b/Documentation/gpu/amdgpu/driver-core.rst @@ -179,4 +179,4 @@ IP Blocks :doc: IP Blocks .. kernel-doc:: drivers/gpu/drm/amd/include/amd_shared.h - :identifiers: amd_ip_block_type amd_ip_funcs + :identifiers: amd_ip_block_type amd_ip_funcs DC_DEBUG_MASK diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index b8c22c77b3ae3..33110affea322 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1877,6 +1877,12 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) if (amdgpu_dc_debug_mask & DC_DISABLE_IPS) init_data.flags.disable_ips = DMUB_IPS_DISABLE_ALL; + else if (amdgpu_dc_debug_mask & DC_DISABLE_IPS_DYNAMIC) + init_data.flags.disable_ips = DMUB_IPS_DISABLE_DYNAMIC; + else if (amdgpu_dc_debug_mask & DC_DISABLE_IPS2_DYNAMIC) + init_data.flags.disable_ips = DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF; + else if (amdgpu_dc_debug_mask & DC_FORCE_IPS_ENABLE) + init_data.flags.disable_ips = DMUB_IPS_ENABLE; else init_data.flags.disable_ips = DMUB_IPS_ENABLE; diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h index f5b725f10a7ce..745fd052840dc 100644 --- a/drivers/gpu/drm/amd/include/amd_shared.h +++ b/drivers/gpu/drm/amd/include/amd_shared.h @@ -61,7 +61,7 @@ enum amd_apu_flags { * acquires the list of IP blocks for the GPU in use on initialization. * It can then operate on this list to perform standard driver operations * such as: init, fini, suspend, resume, etc. -* +* * * IP block implementations are named using the following convention: * _v (E.g.: gfx_v6_0). @@ -251,19 +251,92 @@ enum DC_FEATURE_MASK { DC_REPLAY_MASK = (1 << 9), //0x200, disabled by default for dcn < 3.1.4 }; +/** + * enum DC_DEBUG_MASK - Bits that are useful for debugging the Display Core IP + */ enum DC_DEBUG_MASK { + /** + * @DC_DISABLE_PIPE_SPLIT: If set, disable pipe-splitting + */ DC_DISABLE_PIPE_SPLIT = 0x1, + + /** + * @DC_DISABLE_STUTTER: If set, disable memory stutter mode + */ DC_DISABLE_STUTTER = 0x2, + + /** + * @DC_DISABLE_DSC: If set, disable display stream compression + */ DC_DISABLE_DSC = 0x4, + + /** + * @DC_DISABLE_CLOCK_GATING: If set, disable clock gating optimizations + */ DC_DISABLE_CLOCK_GATING = 0x8, + + /** + * @DC_DISABLE_PSR: If set, disable Panel self refresh v1 and PSR-SU + */ DC_DISABLE_PSR = 0x10, + + /** + * @DC_FORCE_SUBVP_MCLK_SWITCH: If set, force mclk switch in subvp, even + * if mclk switch in vblank is possible + */ DC_FORCE_SUBVP_MCLK_SWITCH = 0x20, + + /** + * @DC_DISABLE_MPO: If set, disable multi-plane offloading + */ DC_DISABLE_MPO = 0x40, + + /** + * @DC_ENABLE_DPIA_TRACE: If set, enable trace logging for DPIA + */ DC_ENABLE_DPIA_TRACE = 0x80, + + /** + * @DC_ENABLE_DML2: If set, force usage of DML2, even if the DCN version + * does not default to it. + */ DC_ENABLE_DML2 = 0x100, + + /** + * @DC_DISABLE_PSR_SU: If set, disable PSR SU + */ DC_DISABLE_PSR_SU = 0x200, + + /** + * @DC_DISABLE_REPLAY: If set, disable Panel Replay + */ DC_DISABLE_REPLAY = 0x400, + + /** + * @DC_DISABLE_IPS: If set, disable all Idle Power States, all the time. + * If more than one IPS debug bit is set, the lowest bit takes + * precedence. For example, if DC_FORCE_IPS_ENABLE and + * DC_DISABLE_IPS_DYNAMIC are set, then DC_DISABLE_IPS_DYNAMIC takes + * precedence. + */ DC_DISABLE_IPS = 0x800, + + /** + * @DC_DISABLE_IPS_DYNAMIC: If set, disable all IPS, all the time, + * *except* when driver goes into suspend. + */ + DC_DISABLE_IPS_DYNAMIC = 0x1000, + + /** + * @DC_DISABLE_IPS2_DYNAMIC: If set, disable IPS2 (IPS1 allowed) if + * there is an enabled display. Otherwise, enable all IPS. + */ + DC_DISABLE_IPS2_DYNAMIC = 0x2000, + + /** + * @DC_FORCE_IPS_ENABLE: If set, force enable all IPS, all the time. + */ + DC_FORCE_IPS_ENABLE = 0x4000, }; enum amd_dpm_forced_level; From f1f29360359186fbcbdcad58aabde7678a6804fd Mon Sep 17 00:00:00 2001 From: Alvin Lee Date: Thu, 20 Jun 2024 14:32:21 -0400 Subject: [PATCH 1393/1868] drm/amd/display: Don't skip clock updates in overclocking [Description] Skipping clock updates is not a hard requirement for overclocking and only an optimization. Remove the skip as this can cause issues for FAMS transitions during the overclock sequence. If FAMS is enabled we must disable UCLK switch on any full update (which requires update clocks to be called). Reviewed-by: Dillon Varone Signed-off-by: Alvin Lee Signed-off-by: Zaeem Mohamed Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c index 01ea3a31e54da..8cfc5f4359374 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c @@ -1366,9 +1366,6 @@ static void dcn401_update_clocks(struct clk_mgr *clk_mgr_base, unsigned int num_steps = 0; - if (dc->work_arounds.skip_clock_update) - return; - if (dc->debug.enable_legacy_clock_update) { dcn401_update_clocks_legacy(clk_mgr_base, context, safe_to_lower); return; From e41aa0f002696fba0d17d6dbdc500d2a98f764b9 Mon Sep 17 00:00:00 2001 From: "Ahmed, Muhammad" Date: Tue, 13 Aug 2024 17:11:55 -0400 Subject: [PATCH 1394/1868] drm/amd/display: guard write a 0 post_divider value to HW [why] post_divider_value should not be 0. Reviewed-by: Charlene Liu Signed-off-by: Ahmed, Muhammad Signed-off-by: Zaeem Mohamed Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c index 7f91e48902e22..60a84de4c5d13 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c @@ -1082,7 +1082,8 @@ static void dccg35_trigger_dio_fifo_resync(struct dccg *dccg) uint32_t dispclk_rdivider_value = 0; REG_GET(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_RDIVIDER, &dispclk_rdivider_value); - REG_UPDATE(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, dispclk_rdivider_value); + if (dispclk_rdivider_value != 0) + REG_UPDATE(DENTIST_DISPCLK_CNTL, DENTIST_DISPCLK_WDIVIDER, dispclk_rdivider_value); } static void dcn35_set_dppclk_enable(struct dccg *dccg, From 40f0684289c91fedf1963428e9393974e1489cbe Mon Sep 17 00:00:00 2001 From: Alvin Lee Date: Thu, 8 Aug 2024 10:19:54 -0400 Subject: [PATCH 1395/1868] drm/amd/display: Wait for all pending cleared before full update [Description] Before every full update we must wait for all pending updates to be cleared - this is particularly important for minimal transitions because if we don't wait for pending cleared, it will be as if there was no minimal transition at all. In OTG we must read 3 different status registers for pending cleared, one specifically for OTG updates, one specifically for OPTC updates, and the last for surface related updates Reviewed-by: Dillon Varone Signed-off-by: Alvin Lee Signed-off-by: Zaeem Mohamed Tested-by: Daniel Wheeler --- .../drm/amd/display/dc/core/dc_hw_sequencer.c | 9 +++- .../amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 4 +- .../amd/display/dc/hwss/dcn30/dcn30_hwseq.c | 27 +++++++++++ .../amd/display/dc/hwss/dcn30/dcn30_hwseq.h | 2 + .../amd/display/dc/hwss/dcn30/dcn30_init.c | 3 +- .../amd/display/dc/hwss/dcn301/dcn301_init.c | 1 + .../amd/display/dc/hwss/dcn32/dcn32_init.c | 1 + .../amd/display/dc/hwss/dcn401/dcn401_init.c | 1 + .../drm/amd/display/dc/hwss/hw_sequencer.h | 1 + .../amd/display/dc/inc/hw/timing_generator.h | 4 +- .../amd/display/dc/optc/dcn10/dcn10_optc.h | 9 ++++ .../amd/display/dc/optc/dcn20/dcn20_optc.h | 7 ++- .../amd/display/dc/optc/dcn30/dcn30_optc.c | 45 +++++++++++++++++++ .../amd/display/dc/optc/dcn30/dcn30_optc.h | 13 +++++- .../amd/display/dc/optc/dcn301/dcn301_optc.c | 3 ++ .../amd/display/dc/optc/dcn31/dcn31_optc.h | 9 +++- .../amd/display/dc/optc/dcn314/dcn314_optc.h | 9 +++- .../amd/display/dc/optc/dcn32/dcn32_optc.c | 16 ++----- .../amd/display/dc/optc/dcn32/dcn32_optc.h | 7 ++- .../amd/display/dc/optc/dcn35/dcn35_optc.h | 6 ++- .../amd/display/dc/optc/dcn401/dcn401_optc.c | 4 +- .../amd/display/dc/optc/dcn401/dcn401_optc.h | 6 ++- .../dc/resource/dcn32/dcn32_resource.h | 3 +- .../dc/resource/dcn401/dcn401_resource.h | 5 ++- 24 files changed, 161 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c index 7ee2be8f82c46..2cb9253c9bdec 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c @@ -1071,8 +1071,13 @@ void hwss_wait_for_outstanding_hw_updates(struct dc *dc, struct dc_state *dc_con if (!pipe_ctx->stream) continue; - if (pipe_ctx->stream_res.tg->funcs->wait_drr_doublebuffer_pending_clear) - pipe_ctx->stream_res.tg->funcs->wait_drr_doublebuffer_pending_clear(pipe_ctx->stream_res.tg); + /* For full update we must wait for all double buffer updates, not just DRR updates. This + * is particularly important for minimal transitions. Only check for OTG_MASTER pipes, + * as non-OTG Master pipes share the same OTG as + */ + if (resource_is_pipe_type(pipe_ctx, OTG_MASTER) && dc->hwss.wait_for_all_pending_updates) { + dc->hwss.wait_for_all_pending_updates(pipe_ctx); + } hubp = pipe_ctx->plane_res.hubp; if (!hubp) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c index a80c085829320..b383ed8cb4d49 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c @@ -2255,9 +2255,9 @@ void dcn20_post_unlock_program_front_end( struct timing_generator *tg = pipe->stream_res.tg; - if (tg->funcs->get_double_buffer_pending) { + if (tg->funcs->get_optc_double_buffer_pending) { for (j = 0; j < TIMEOUT_FOR_PIPE_ENABLE_US / polling_interval_us - && tg->funcs->get_double_buffer_pending(tg); j++) + && tg->funcs->get_optc_double_buffer_pending(tg); j++) udelay(polling_interval_us); } } diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c index 42c52284a8680..d5458dae6d305 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c @@ -1185,3 +1185,30 @@ void dcn30_prepare_bandwidth(struct dc *dc, if (!dc->clk_mgr->clks.fw_based_mclk_switching) dc_dmub_srv_p_state_delegate(dc, false, context); } + +void dcn30_wait_for_all_pending_updates(const struct pipe_ctx *pipe_ctx) +{ + struct timing_generator *tg = pipe_ctx->stream_res.tg; + bool pending_updates = false; + unsigned int i; + + if (tg && tg->funcs->is_tg_enabled(tg)) { + // Poll for 100ms maximum + for (i = 0; i < 100000; i++) { + pending_updates = false; + if (tg->funcs->get_optc_double_buffer_pending) + pending_updates |= tg->funcs->get_optc_double_buffer_pending(tg); + + if (tg->funcs->get_otg_double_buffer_pending) + pending_updates |= tg->funcs->get_otg_double_buffer_pending(tg); + + if (tg->funcs->get_pipe_update_pending) + pending_updates |= tg->funcs->get_pipe_update_pending(tg); + + if (!pending_updates) + break; + + udelay(1); + } + } +} diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h index 6a153e7ce910e..4b90b781c4f2d 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h @@ -96,4 +96,6 @@ void dcn30_set_hubp_blank(const struct dc *dc, void dcn30_prepare_bandwidth(struct dc *dc, struct dc_state *context); +void dcn30_wait_for_all_pending_updates(const struct pipe_ctx *pipe_ctx); + #endif /* __DC_HWSS_DCN30_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c index 2a8dc40d28477..0e8d32e3dbae1 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c @@ -108,7 +108,8 @@ static const struct hw_sequencer_funcs dcn30_funcs = { .set_disp_pattern_generator = dcn30_set_disp_pattern_generator, .get_dcc_en_bits = dcn10_get_dcc_en_bits, .update_visual_confirm_color = dcn10_update_visual_confirm_color, - .is_abm_supported = dcn21_is_abm_supported + .is_abm_supported = dcn21_is_abm_supported, + .wait_for_all_pending_updates = dcn30_wait_for_all_pending_updates, }; static const struct hwseq_private_funcs dcn30_private_funcs = { diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c index 93e49d87a67ce..780ce4c064aa5 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c @@ -107,6 +107,7 @@ static const struct hw_sequencer_funcs dcn301_funcs = { .optimize_pwr_state = dcn21_optimize_pwr_state, .exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state, .update_visual_confirm_color = dcn10_update_visual_confirm_color, + .wait_for_all_pending_updates = dcn30_wait_for_all_pending_updates, }; static const struct hwseq_private_funcs dcn301_private_funcs = { diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c index 3422b564ae984..8e0946fd5b7fe 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c @@ -121,6 +121,7 @@ static const struct hw_sequencer_funcs dcn32_funcs = { .is_pipe_topology_transition_seamless = dcn32_is_pipe_topology_transition_seamless, .calculate_pix_rate_divider = dcn32_calculate_pix_rate_divider, .program_outstanding_updates = dcn32_program_outstanding_updates, + .wait_for_all_pending_updates = dcn30_wait_for_all_pending_updates, }; static const struct hwseq_private_funcs dcn32_private_funcs = { diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c index a2ca07235c83d..73a632b5ff893 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c @@ -100,6 +100,7 @@ static const struct hw_sequencer_funcs dcn401_funcs = { .fams2_update_config = dcn401_fams2_update_config, .fams2_global_control_lock_fast = dcn401_fams2_global_control_lock_fast, .program_outstanding_updates = dcn401_program_outstanding_updates, + .wait_for_all_pending_updates = dcn30_wait_for_all_pending_updates, }; static const struct hwseq_private_funcs dcn401_private_funcs = { diff --git a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h index ac92056256233..b8c47e4c51c15 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h @@ -462,6 +462,7 @@ struct hw_sequencer_funcs { void (*program_outstanding_updates)(struct dc *dc, struct dc_state *context); void (*setup_hpo_hw_control)(const struct dce_hwseq *hws, bool enable); + void (*wait_for_all_pending_updates)(const struct pipe_ctx *pipe_ctx); }; void color_space_to_black_color( diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h index 3d4c8bd42b492..4e08e80eafe8e 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h @@ -342,7 +342,9 @@ struct timing_generator_funcs { void (*wait_drr_doublebuffer_pending_clear)(struct timing_generator *tg); void (*set_long_vtotal)(struct timing_generator *optc, const struct long_vtotal_params *params); void (*wait_odm_doublebuffer_pending_clear)(struct timing_generator *tg); - bool (*get_double_buffer_pending)(struct timing_generator *tg); + bool (*get_optc_double_buffer_pending)(struct timing_generator *tg); + bool (*get_otg_double_buffer_pending)(struct timing_generator *tg); + bool (*get_pipe_update_pending)(struct timing_generator *tg); }; #endif diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h index b7a57f98553d7..40757f20d73f4 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h @@ -202,6 +202,7 @@ struct dcn_optc_registers { uint32_t OPTC_CLOCK_CONTROL; uint32_t OPTC_WIDTH_CONTROL2; uint32_t OTG_PSTATE_REGISTER; + uint32_t OTG_PIPE_UPDATE_STATUS; }; #define TG_COMMON_MASK_SH_LIST_DCN(mask_sh)\ @@ -566,6 +567,12 @@ struct dcn_optc_registers { type OTG_H_TIMING_DIV_MODE_DB_UPDATE_PENDING;\ type OPTC_DOUBLE_BUFFER_PENDING;\ +#define TG_REG_FIELD_LIST_DCN2_0(type) \ + type OTG_FLIP_PENDING;\ + type OTG_DC_REG_UPDATE_PENDING;\ + type OTG_CURSOR_UPDATE_PENDING;\ + type OTG_VUPDATE_KEEPOUT_STATUS;\ + #define TG_REG_FIELD_LIST_DCN3_2(type) \ type OTG_H_TIMING_DIV_MODE_MANUAL; @@ -600,6 +607,7 @@ struct dcn_optc_registers { struct dcn_optc_shift { TG_REG_FIELD_LIST(uint8_t) + TG_REG_FIELD_LIST_DCN2_0(uint8_t) TG_REG_FIELD_LIST_DCN3_2(uint8_t) TG_REG_FIELD_LIST_DCN3_5(uint8_t) TG_REG_FIELD_LIST_DCN401(uint8_t) @@ -607,6 +615,7 @@ struct dcn_optc_shift { struct dcn_optc_mask { TG_REG_FIELD_LIST(uint32_t) + TG_REG_FIELD_LIST_DCN2_0(uint32_t) TG_REG_FIELD_LIST_DCN3_2(uint32_t) TG_REG_FIELD_LIST_DCN3_5(uint32_t) TG_REG_FIELD_LIST_DCN401(uint32_t) diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h index 364034b190281..928e110b95fb5 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h @@ -43,7 +43,8 @@ SRI(OPTC_MEMORY_CONFIG, ODM, inst),\ SR(DWB_SOURCE_SELECT),\ SRI(OTG_MANUAL_FLOW_CONTROL, OTG, inst), \ - SRI(OTG_DRR_CONTROL, OTG, inst) + SRI(OTG_DRR_CONTROL, OTG, inst),\ + SRI(OTG_PIPE_UPDATE_STATUS, OTG, inst) #define TG_COMMON_MASK_SH_LIST_DCN2_0(mask_sh)\ TG_COMMON_MASK_SH_LIST_DCN(mask_sh),\ @@ -53,6 +54,10 @@ SF(OTG0_OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, mask_sh),\ SF(OTG0_OTG_GLOBAL_CONTROL2, DIG_UPDATE_LOCATION, mask_sh),\ SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_RANGE_TIMING_DBUF_UPDATE_MODE, mask_sh),\ + SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_FLIP_PENDING, mask_sh),\ + SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_DC_REG_UPDATE_PENDING, mask_sh),\ + SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_CURSOR_UPDATE_PENDING, mask_sh),\ + SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_VUPDATE_KEEPOUT_STATUS, mask_sh),\ SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_START_X, mask_sh),\ SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_END_X, mask_sh), \ SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_START_Y, mask_sh),\ diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c index abcd03d786684..4c95c09586122 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c @@ -271,6 +271,48 @@ void optc3_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_c optc1->opp_count = opp_cnt; } +/* OTG status register that indicates OPTC update is pending */ +bool optc3_get_optc_double_buffer_pending(struct timing_generator *optc) +{ + struct optc *optc1 = DCN10TG_FROM_TG(optc); + uint32_t update_pending = 0; + + REG_GET(OPTC_INPUT_GLOBAL_CONTROL, + OPTC_DOUBLE_BUFFER_PENDING, + &update_pending); + + return (update_pending == 1); +} + +/* OTG status register that indicates OTG update is pending */ +bool optc3_get_otg_update_pending(struct timing_generator *optc) +{ + struct optc *optc1 = DCN10TG_FROM_TG(optc); + uint32_t update_pending = 0; + + REG_GET(OTG_DOUBLE_BUFFER_CONTROL, + OTG_UPDATE_PENDING, + &update_pending); + + return (update_pending == 1); +} + +/* OTG status register that indicates surface update is pending */ +bool optc3_get_pipe_update_pending(struct timing_generator *optc) +{ + struct optc *optc1 = DCN10TG_FROM_TG(optc); + uint32_t flip_pending = 0; + uint32_t dc_update_pending = 0; + + REG_GET_2(OTG_PIPE_UPDATE_STATUS, + OTG_FLIP_PENDING, + &flip_pending, + OTG_DC_REG_UPDATE_PENDING, + &dc_update_pending); + + return (flip_pending == 1 || dc_update_pending == 1); +} + /** * optc3_set_timing_double_buffer() - DRR double buffering control * @@ -375,6 +417,9 @@ static struct timing_generator_funcs dcn30_tg_funcs = { .get_hw_timing = optc1_get_hw_timing, .wait_drr_doublebuffer_pending_clear = optc3_wait_drr_doublebuffer_pending_clear, .is_two_pixels_per_container = optc1_is_two_pixels_per_container, + .get_optc_double_buffer_pending = optc3_get_optc_double_buffer_pending, + .get_otg_double_buffer_pending = optc3_get_otg_update_pending, + .get_pipe_update_pending = optc3_get_pipe_update_pending, }; void dcn30_timing_generator_init(struct optc *optc1) diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h index bda974d432ea6..e2303f9eaf13b 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h @@ -109,7 +109,8 @@ SRI(OPTC_BYTES_PER_PIXEL, ODM, inst),\ SRI(OPTC_WIDTH_CONTROL, ODM, inst),\ SRI(OPTC_MEMORY_CONFIG, ODM, inst),\ - SR(DWB_SOURCE_SELECT) + SR(DWB_SOURCE_SELECT),\ + SRI(OTG_PIPE_UPDATE_STATUS, OTG, inst) #define DCN30_VTOTAL_REGS_SF(mask_sh) @@ -209,6 +210,7 @@ SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_GATE_DIS, mask_sh),\ SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_OCCURRED_STATUS, mask_sh),\ SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, mask_sh),\ + SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_DOUBLE_BUFFER_PENDING, mask_sh),\ SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\ SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\ SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\ @@ -319,7 +321,11 @@ SF(OTG0_OTG_DRR_V_TOTAL_CHANGE, OTG_DRR_V_TOTAL_CHANGE_LIMIT, mask_sh),\ SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, mask_sh),\ SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_PENDING, mask_sh),\ - SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_MODE, mask_sh) + SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_MODE, mask_sh),\ + SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_FLIP_PENDING, mask_sh),\ + SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_DC_REG_UPDATE_PENDING, mask_sh),\ + SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_CURSOR_UPDATE_PENDING, mask_sh),\ + SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_VUPDATE_KEEPOUT_STATUS, mask_sh),\ void dcn30_timing_generator_init(struct optc *optc1); @@ -356,4 +362,7 @@ void optc3_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_c void optc3_wait_drr_doublebuffer_pending_clear(struct timing_generator *optc); void optc3_tg_init(struct timing_generator *optc); void optc3_set_vtotal_min_max(struct timing_generator *optc, int vtotal_min, int vtotal_max); +bool optc3_get_optc_double_buffer_pending(struct timing_generator *optc); +bool optc3_get_otg_update_pending(struct timing_generator *optc); +bool optc3_get_pipe_update_pending(struct timing_generator *optc); #endif /* __DC_OPTC_DCN30_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn301/dcn301_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn301/dcn301_optc.c index 1a22ae89fb555..d7a45ef2d01b3 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn301/dcn301_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn301/dcn301_optc.c @@ -169,6 +169,9 @@ static struct timing_generator_funcs dcn30_tg_funcs = { .get_hw_timing = optc1_get_hw_timing, .wait_drr_doublebuffer_pending_clear = optc3_wait_drr_doublebuffer_pending_clear, .is_two_pixels_per_container = optc1_is_two_pixels_per_container, + .get_optc_double_buffer_pending = optc3_get_optc_double_buffer_pending, + .get_otg_double_buffer_pending = optc3_get_otg_update_pending, + .get_pipe_update_pending = optc3_get_pipe_update_pending, }; void dcn301_timing_generator_init(struct optc *optc1) diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h index 30b81a448ce2d..fbbe86d00c2e3 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h @@ -99,7 +99,8 @@ SRI(OPTC_MEMORY_CONFIG, ODM, inst),\ SRI(OTG_CRC_CNTL2, OTG, inst),\ SR(DWB_SOURCE_SELECT),\ - SRI(OTG_DRR_CONTROL, OTG, inst) + SRI(OTG_DRR_CONTROL, OTG, inst),\ + SRI(OTG_PIPE_UPDATE_STATUS, OTG, inst) #define OPTC_COMMON_MASK_SH_LIST_DCN3_1(mask_sh)\ SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\ @@ -254,7 +255,11 @@ SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_COMBINE_MODE, mask_sh),\ SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_SPLIT_MODE, mask_sh),\ SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_FORMAT, mask_sh),\ - SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh) + SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh),\ + SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_FLIP_PENDING, mask_sh),\ + SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_DC_REG_UPDATE_PENDING, mask_sh),\ + SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_CURSOR_UPDATE_PENDING, mask_sh),\ + SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_VUPDATE_KEEPOUT_STATUS, mask_sh),\ void dcn31_timing_generator_init(struct optc *optc1); diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h index 99c098e76116f..0ff72b97b465c 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h @@ -98,7 +98,8 @@ SRI(OPTC_BYTES_PER_PIXEL, ODM, inst),\ SRI(OPTC_WIDTH_CONTROL, ODM, inst),\ SRI(OPTC_MEMORY_CONFIG, ODM, inst),\ - SRI(OTG_DRR_CONTROL, OTG, inst) + SRI(OTG_DRR_CONTROL, OTG, inst),\ + SRI(OTG_PIPE_UPDATE_STATUS, OTG, inst) #define OPTC_COMMON_MASK_SH_LIST_DCN3_14(mask_sh)\ SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\ @@ -248,7 +249,11 @@ SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, mask_sh),\ SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE_MANUAL, mask_sh),\ SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_MODE, mask_sh),\ - SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh) + SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh),\ + SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_FLIP_PENDING, mask_sh),\ + SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_DC_REG_UPDATE_PENDING, mask_sh),\ + SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_CURSOR_UPDATE_PENDING, mask_sh),\ + SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_VUPDATE_KEEPOUT_STATUS, mask_sh),\ void dcn314_timing_generator_init(struct optc *optc1); diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c index 00094f0e84706..c217f653b3c81 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c @@ -297,18 +297,6 @@ static void optc32_set_drr( optc32_setup_manual_trigger(optc); } -bool optc32_get_double_buffer_pending(struct timing_generator *optc) -{ - struct optc *optc1 = DCN10TG_FROM_TG(optc); - uint32_t update_pending = 0; - - REG_GET(OPTC_INPUT_GLOBAL_CONTROL, - OPTC_DOUBLE_BUFFER_PENDING, - &update_pending); - - return (update_pending == 1); -} - static struct timing_generator_funcs dcn32_tg_funcs = { .validate_timing = optc1_validate_timing, .program_timing = optc1_program_timing, @@ -373,7 +361,9 @@ static struct timing_generator_funcs dcn32_tg_funcs = { .setup_manual_trigger = optc2_setup_manual_trigger, .get_hw_timing = optc1_get_hw_timing, .is_two_pixels_per_container = optc1_is_two_pixels_per_container, - .get_double_buffer_pending = optc32_get_double_buffer_pending, + .get_optc_double_buffer_pending = optc3_get_optc_double_buffer_pending, + .get_otg_double_buffer_pending = optc3_get_otg_update_pending, + .get_pipe_update_pending = optc3_get_pipe_update_pending, }; void dcn32_timing_generator_init(struct optc *optc1) diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.h index 665d7c52f67cd..0b0964a9da748 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.h +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.h @@ -177,7 +177,11 @@ SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, mask_sh),\ SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE_MANUAL, mask_sh),\ SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_MODE, mask_sh),\ - SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh) + SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh),\ + SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_FLIP_PENDING, mask_sh),\ + SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_DC_REG_UPDATE_PENDING, mask_sh),\ + SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_CURSOR_UPDATE_PENDING, mask_sh),\ + SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_VUPDATE_KEEPOUT_STATUS, mask_sh) void dcn32_timing_generator_init(struct optc *optc1); void optc32_set_h_timing_div_manual_mode(struct timing_generator *optc, bool manual_mode); @@ -185,6 +189,5 @@ void optc32_get_odm_combine_segments(struct timing_generator *tg, int *odm_combi void optc32_set_odm_bypass(struct timing_generator *optc, const struct dc_crtc_timing *dc_crtc_timing); void optc32_wait_odm_doublebuffer_pending_clear(struct timing_generator *tg); -bool optc32_get_double_buffer_pending(struct timing_generator *optc); #endif /* __DC_OPTC_DCN32_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.h index d077e2392379c..be749ab41dce7 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.h +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.h @@ -67,7 +67,11 @@ SF(OTG0_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK, OTG_CRC1_WINDOWB_Y_END_READBACK, mask_sh),\ SF(OPTC_CLOCK_CONTROL, OPTC_FGCG_REP_DIS, mask_sh),\ SF(OTG0_OTG_V_COUNT_STOP_CONTROL, OTG_V_COUNT_STOP, mask_sh),\ - SF(OTG0_OTG_V_COUNT_STOP_CONTROL2, OTG_V_COUNT_STOP_TIMER, mask_sh) + SF(OTG0_OTG_V_COUNT_STOP_CONTROL2, OTG_V_COUNT_STOP_TIMER, mask_sh),\ + SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_FLIP_PENDING, mask_sh),\ + SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_DC_REG_UPDATE_PENDING, mask_sh),\ + SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_CURSOR_UPDATE_PENDING, mask_sh),\ + SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_VUPDATE_KEEPOUT_STATUS, mask_sh) void dcn35_timing_generator_init(struct optc *optc1); diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c index a5d6a7dca554c..db670fc172644 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c @@ -493,7 +493,9 @@ static struct timing_generator_funcs dcn401_tg_funcs = { .setup_manual_trigger = optc2_setup_manual_trigger, .get_hw_timing = optc1_get_hw_timing, .is_two_pixels_per_container = optc1_is_two_pixels_per_container, - .get_double_buffer_pending = optc32_get_double_buffer_pending, + .get_optc_double_buffer_pending = optc3_get_optc_double_buffer_pending, + .get_otg_double_buffer_pending = optc3_get_otg_update_pending, + .get_pipe_update_pending = optc3_get_pipe_update_pending, }; void dcn401_timing_generator_init(struct optc *optc1) diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.h index bb13a645802d0..1be89571986ff 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.h +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.h @@ -159,7 +159,11 @@ SF(OTG0_OTG_PSTATE_REGISTER, OTG_PSTATE_KEEPOUT_START, mask_sh),\ SF(OTG0_OTG_PSTATE_REGISTER, OTG_PSTATE_EXTEND, mask_sh),\ SF(OTG0_OTG_PSTATE_REGISTER, OTG_UNBLANK, mask_sh),\ - SF(OTG0_OTG_PSTATE_REGISTER, OTG_PSTATE_ALLOW_WIDTH_MIN, mask_sh) + SF(OTG0_OTG_PSTATE_REGISTER, OTG_PSTATE_ALLOW_WIDTH_MIN, mask_sh),\ + SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_FLIP_PENDING, mask_sh),\ + SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_DC_REG_UPDATE_PENDING, mask_sh),\ + SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_CURSOR_UPDATE_PENDING, mask_sh),\ + SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_VUPDATE_KEEPOUT_STATUS, mask_sh) void dcn401_timing_generator_init(struct optc *optc1); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h index 7901792afb7b3..86c6e5e8c42eb 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h @@ -1054,7 +1054,8 @@ unsigned int dcn32_calculate_mall_ways_from_bytes(const struct dc *dc, unsigned SRI_ARR(OPTC_BYTES_PER_PIXEL, ODM, inst), \ SRI_ARR(OPTC_WIDTH_CONTROL, ODM, inst), \ SRI_ARR(OPTC_MEMORY_CONFIG, ODM, inst), \ - SRI_ARR(OTG_DRR_CONTROL, OTG, inst) + SRI_ARR(OTG_DRR_CONTROL, OTG, inst), \ + SRI_ARR(OTG_PIPE_UPDATE_STATUS, OTG, inst) /* HUBP */ diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h index 514d1ce20df9e..bdafa7496ceae 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h @@ -536,8 +536,9 @@ void dcn401_prepare_mcache_programming(struct dc *dc, struct dc_state *context); SRI_ARR(OPTC_WIDTH_CONTROL, ODM, inst), \ SRI_ARR(OPTC_WIDTH_CONTROL2, ODM, inst), \ SRI_ARR(OPTC_MEMORY_CONFIG, ODM, inst), \ - SRI_ARR(OTG_DRR_CONTROL, OTG, inst), \ - SRI_ARR(OTG_PSTATE_REGISTER, OTG, inst) + SRI_ARR(OTG_DRR_CONTROL, OTG, inst), \ + SRI_ARR(OTG_PSTATE_REGISTER, OTG, inst), \ + SRI_ARR(OTG_PIPE_UPDATE_STATUS, OTG, inst) /* HUBBUB */ #define HUBBUB_REG_LIST_DCN4_01_RI(id) \ From ec3b165c152cfd6d3458dfe9c49e36705158e6a6 Mon Sep 17 00:00:00 2001 From: Dillon Varone Date: Wed, 14 Aug 2024 17:32:16 -0400 Subject: [PATCH 1396/1868] drm/amd/display: Fix MS/MP mismatches in dml21 for dcn401 [WHY] Prefetch calculations did not guarantee that bandwidth required in mode support was less than mode programming which can cause failures. [HOW] Fix bandwidth calculations to assume fixed times for OTO schedule, and choose which schedule to use based on time to fetch pixel data. Reviewed-by: Jun Lei Signed-off-by: Dillon Varone Signed-off-by: Zaeem Mohamed Tested-by: Daniel Wheeler --- .../src/dml2_core/dml2_core_dcn4_calcs.c | 47 ++++++++++++------- .../src/dml2_core/dml2_core_shared_types.h | 5 ++ 2 files changed, 36 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c index 805fd783131f4..ca4f23d105fc2 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c @@ -5056,6 +5056,8 @@ static bool CalculatePrefetchSchedule(struct dml2_core_internal_scratch *scratch s->trip_to_mem = 0.0; *p->Tvm_trips = 0.0; *p->Tr0_trips = 0.0; + s->Tvm_no_trip_oto = 0.0; + s->Tr0_no_trip_oto = 0.0; s->Tvm_trips_rounded = 0.0; s->Tr0_trips_rounded = 0.0; s->max_Tsw = 0.0; @@ -5293,31 +5295,38 @@ static bool CalculatePrefetchSchedule(struct dml2_core_internal_scratch *scratch s->Lsw_oto = math_ceil2(4.0 * math_max2(s->prefetch_sw_bytes / s->prefetch_bw_oto / s->LineTime, s->min_Lsw_oto), 1.0) / 4.0; if (p->display_cfg->gpuvm_enable == true) { - s->Tvm_oto = math_max3( - *p->Tvm_trips, + s->Tvm_no_trip_oto = math_max2( *p->Tno_bw + vm_bytes * p->HostVMInefficiencyFactor / s->prefetch_bw_oto, s->LineTime / 4.0); + s->Tvm_oto = math_max2( + *p->Tvm_trips, + s->Tvm_no_trip_oto); #ifdef __DML_VBA_DEBUG__ dml2_printf("DML::%s: Tvm_oto max0 = %f\n", __func__, *p->Tvm_trips); dml2_printf("DML::%s: Tvm_oto max1 = %f\n", __func__, *p->Tno_bw + vm_bytes * p->HostVMInefficiencyFactor / s->prefetch_bw_oto); dml2_printf("DML::%s: Tvm_oto max2 = %f\n", __func__, s->LineTime / 4.0); #endif } else { + s->Tvm_no_trip_oto = s->Tvm_trips_rounded; s->Tvm_oto = s->Tvm_trips_rounded; } if ((p->display_cfg->gpuvm_enable == true || p->setup_for_tdlut || dcc_mrq_enable)) { - s->Tr0_oto = math_max3( - *p->Tr0_trips, + s->Tr0_no_trip_oto = math_max2( (p->PixelPTEBytesPerRow * p->HostVMInefficiencyFactor + p->meta_row_bytes + tdlut_row_bytes) / s->prefetch_bw_oto, s->LineTime / 4.0); + s->Tr0_oto = math_max2( + *p->Tr0_trips, + s->Tr0_no_trip_oto); #ifdef __DML_VBA_DEBUG__ dml2_printf("DML::%s: Tr0_oto max0 = %f\n", __func__, *p->Tr0_trips); dml2_printf("DML::%s: Tr0_oto max1 = %f\n", __func__, (p->PixelPTEBytesPerRow * p->HostVMInefficiencyFactor + p->meta_row_bytes + tdlut_row_bytes) / s->prefetch_bw_oto); dml2_printf("DML::%s: Tr0_oto max2 = %f\n", __func__, s->LineTime / 4); #endif - } else - s->Tr0_oto = (s->LineTime - s->Tvm_oto) / 4.0; + } else { + s->Tr0_no_trip_oto = (s->LineTime - s->Tvm_oto) / 4.0; + s->Tr0_oto = s->Tr0_no_trip_oto; + } s->Tvm_oto_lines = math_ceil2(4.0 * s->Tvm_oto / s->LineTime, 1) / 4.0; s->Tr0_oto_lines = math_ceil2(4.0 * s->Tr0_oto / s->LineTime, 1) / 4.0; @@ -5595,6 +5604,9 @@ static bool CalculatePrefetchSchedule(struct dml2_core_internal_scratch *scratch dml2_printf("DML::%s: Tvm_equ = %f\n", __func__, s->Tvm_equ); dml2_printf("DML::%s: Tr0_equ = %f\n", __func__, s->Tr0_equ); #endif + // Lsw = dst_y_prefetch - (dst_y_per_vm_vblank + 2*dst_y_per_row_vblank) + s->Lsw_equ = s->dst_y_prefetch_equ - math_ceil2(4.0 * (s->Tvm_equ + 2 * s->Tr0_equ) / s->LineTime, 1.0) / 4.0; + // Use the more stressful prefetch schedule if (s->dst_y_prefetch_oto < s->dst_y_prefetch_equ) { *p->dst_y_prefetch = s->dst_y_prefetch_oto; @@ -5603,25 +5615,28 @@ static bool CalculatePrefetchSchedule(struct dml2_core_internal_scratch *scratch *p->dst_y_per_vm_vblank = math_ceil2(4.0 * s->TimeForFetchingVM / s->LineTime, 1.0) / 4.0; *p->dst_y_per_row_vblank = math_ceil2(4.0 * s->TimeForFetchingRowInVBlank / s->LineTime, 1.0) / 4.0; + s->dst_y_per_vm_no_trip_vblank = math_ceil2(4.0 * s->Tvm_no_trip_oto / s->LineTime, 1.0) / 4.0; + s->dst_y_per_row_no_trip_vblank = math_ceil2(4.0 * s->Tr0_no_trip_oto / s->LineTime, 1.0) / 4.0; #ifdef __DML_VBA_DEBUG__ dml2_printf("DML::%s: Using oto scheduling for prefetch\n", __func__); #endif - } else { *p->dst_y_prefetch = s->dst_y_prefetch_equ; s->TimeForFetchingVM = s->Tvm_equ; s->TimeForFetchingRowInVBlank = s->Tr0_equ; - *p->dst_y_per_vm_vblank = math_ceil2(4.0 * s->TimeForFetchingVM / s->LineTime, 1.0) / 4.0; - *p->dst_y_per_row_vblank = math_ceil2(4.0 * s->TimeForFetchingRowInVBlank / s->LineTime, 1.0) / 4.0; + *p->dst_y_per_vm_vblank = math_ceil2(4.0 * s->TimeForFetchingVM / s->LineTime, 1.0) / 4.0; + *p->dst_y_per_row_vblank = math_ceil2(4.0 * s->TimeForFetchingRowInVBlank / s->LineTime, 1.0) / 4.0; + s->dst_y_per_vm_no_trip_vblank = *p->dst_y_per_vm_vblank; + s->dst_y_per_row_no_trip_vblank = *p->dst_y_per_row_vblank; #ifdef __DML_VBA_DEBUG__ dml2_printf("DML::%s: Using equ bw scheduling for prefetch\n", __func__); #endif } - // Lsw = dst_y_prefetch - (dst_y_per_vm_vblank + 2*dst_y_per_row_vblank) - s->LinesToRequestPrefetchPixelData = *p->dst_y_prefetch - *p->dst_y_per_vm_vblank - 2 * *p->dst_y_per_row_vblank; // Lsw + /* take worst case Lsw to calculate bandwidth requirement regardless of schedule */ + s->LinesToRequestPrefetchPixelData = math_min2(s->Lsw_equ, s->Lsw_oto); // Lsw s->cursor_prefetch_bytes = (unsigned int)math_max2(p->cursor_bytes_per_chunk, 4 * p->cursor_bytes_per_line); *p->prefetch_cursor_bw = p->num_cursors * s->cursor_prefetch_bytes / (s->LinesToRequestPrefetchPixelData * s->LineTime); @@ -5741,13 +5756,13 @@ static bool CalculatePrefetchSchedule(struct dml2_core_internal_scratch *scratch if (vm_bytes == 0) { prefetch_vm_bw = 0; - } else if (*p->dst_y_per_vm_vblank > 0) { + } else if (s->dst_y_per_vm_no_trip_vblank > 0) { #ifdef __DML_VBA_DEBUG__ dml2_printf("DML::%s: HostVMInefficiencyFactor = %f\n", __func__, p->HostVMInefficiencyFactor); dml2_printf("DML::%s: dst_y_per_vm_vblank = %f\n", __func__, *p->dst_y_per_vm_vblank); dml2_printf("DML::%s: LineTime = %f\n", __func__, s->LineTime); #endif - prefetch_vm_bw = vm_bytes * p->HostVMInefficiencyFactor / (*p->dst_y_per_vm_vblank * s->LineTime); + prefetch_vm_bw = vm_bytes * p->HostVMInefficiencyFactor / (s->dst_y_per_vm_no_trip_vblank * s->LineTime); #ifdef __DML_VBA_DEBUG__ dml2_printf("DML::%s: prefetch_vm_bw = %f\n", __func__, prefetch_vm_bw); #endif @@ -5759,8 +5774,8 @@ static bool CalculatePrefetchSchedule(struct dml2_core_internal_scratch *scratch if (p->PixelPTEBytesPerRow == 0 && tdlut_row_bytes == 0) { prefetch_row_bw = 0; - } else if (*p->dst_y_per_row_vblank > 0) { - prefetch_row_bw = (p->PixelPTEBytesPerRow * p->HostVMInefficiencyFactor + tdlut_row_bytes) / (*p->dst_y_per_row_vblank * s->LineTime); + } else if (s->dst_y_per_row_no_trip_vblank > 0) { + prefetch_row_bw = (p->PixelPTEBytesPerRow * p->HostVMInefficiencyFactor + tdlut_row_bytes) / (s->dst_y_per_row_no_trip_vblank * s->LineTime); #ifdef __DML_VBA_DEBUG__ dml2_printf("DML::%s: PixelPTEBytesPerRow = %u\n", __func__, p->PixelPTEBytesPerRow); @@ -10739,7 +10754,7 @@ static bool dml_core_mode_programming(struct dml2_core_calcs_mode_programming_ex mode_lib->mp.UrgentLatency, mode_lib->mp.TripToMemory, !dml_is_phantom_pipe(&display_cfg->plane_descriptors[k]) && display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.drr_config.enabled ? - get_g6_temp_read_blackout_us(&mode_lib->soc, (unsigned int)(mode_lib->ms.uclk_freq_mhz * 1000), in_out_params->min_clk_index) : 0.0); + get_g6_temp_read_blackout_us(&mode_lib->soc, (unsigned int)(mode_lib->mp.uclk_freq_mhz * 1000), in_out_params->min_clk_index) : 0.0); myPipe->Dppclk = mode_lib->mp.Dppclk[k]; myPipe->Dispclk = mode_lib->mp.Dispclk; diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h index 13961c2eb6347..cbdfbd5a0bdea 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_shared_types.h @@ -1187,11 +1187,15 @@ struct dml2_core_calcs_CalculatePrefetchSchedule_locals { double prefetch_bw_oto; double Tvm_oto; double Tr0_oto; + double Tvm_no_trip_oto; + double Tr0_no_trip_oto; double Tvm_oto_lines; double Tr0_oto_lines; double dst_y_prefetch_oto; double TimeForFetchingVM; double TimeForFetchingRowInVBlank; + double dst_y_per_vm_no_trip_vblank; + double dst_y_per_row_no_trip_vblank; double LinesToRequestPrefetchPixelData; unsigned int HostVMDynamicLevelsTrips; double trip_to_mem; @@ -1199,6 +1203,7 @@ struct dml2_core_calcs_CalculatePrefetchSchedule_locals { double Tr0_trips_rounded; double max_Tsw; double Lsw_oto; + double Lsw_equ; double Tpre_rounded; double prefetch_bw_equ; double Tvm_equ; From 48e6650459f16fbd777451b31765529b2e83499e Mon Sep 17 00:00:00 2001 From: Daniel Sa Date: Mon, 12 Aug 2024 15:24:27 -0400 Subject: [PATCH 1397/1868] drm/amd/display: Resolve Coverity Issues [WHY] Remove coverity issues that were originally ignored. [HOW] Ran coverity locally on driver, used output report to find existing coverity issues, resolved them Reviewed-by: Nicholas Choi Signed-off-by: Daniel Sa Signed-off-by: Zaeem Mohamed Tested-by: Daniel Wheeler --- .../display/dc/dml2/dml21/inc/dml_top_types.h | 1 - .../src/dml2_core/dml2_core_dcn4_calcs.c | 21 ++++++++++++------- .../dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c | 3 +-- .../dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c | 3 --- .../src/dml2_top/dml2_top_optimization.c | 1 - 5 files changed, 15 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h b/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h index 1c773bbb99929..eeb96c4556584 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_types.h @@ -5,7 +5,6 @@ #ifndef __DML_TOP_TYPES_H__ #define __DML_TOP_TYPES_H__ -#include "dml_top_types.h" #include "dml_top_display_cfg_types.h" #include "dml_top_soc_parameter_types.h" #include "dml_top_policy_types.h" diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c index ca4f23d105fc2..3ea54fd52e468 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c @@ -2085,7 +2085,11 @@ static void CalculateDCCConfiguration( unsigned int full_swath_bytes_vert_wc_l; unsigned int full_swath_bytes_vert_wc_c; - yuv420 = dml_is_420(SourcePixelFormat); + if (dml_is_420(SourcePixelFormat)) + yuv420 = 1; + else + yuv420 = 0; + horz_div_l = 1; horz_div_c = 1; vert_div_l = 1; @@ -2553,8 +2557,11 @@ static void calculate_mcache_setting( l->luma_time_factor = (double)l->mvmpg_width_c / l->mvmpg_width_l * 2; // The algorithm starts with computing a non-integer, avg_mcache_element_size_l/c: - l->avg_mcache_element_size_l = l->meta_row_width_l / *p->num_mcaches_l; - if (l->is_dual_plane) { + if (*p->num_mcaches_l) { + l->avg_mcache_element_size_l = l->meta_row_width_l / *p->num_mcaches_l; + } + + if (l->is_dual_plane && *p->num_mcaches_c) { l->avg_mcache_element_size_c = l->meta_row_width_c / *p->num_mcaches_c; if (!p->imall_enable || (*p->mall_comb_mcache_l == *p->mall_comb_mcache_c)) { @@ -2683,9 +2690,9 @@ static double dml_get_return_bandwidth_available( double ideal_fabric_bandwidth = fclk_mhz * (double)soc->fabric_datapath_to_dcn_data_return_bytes; double ideal_dram_bandwidth = dram_bw_mbps; //dram_speed_mts * soc->clk_table.dram_config.channel_count * soc->clk_table.dram_config.channel_width_bytes; - double derate_sdp_factor = 1; - double derate_fabric_factor = 1; - double derate_dram_factor = 1; + double derate_sdp_factor; + double derate_fabric_factor; + double derate_dram_factor; double derate_sdp_bandwidth; double derate_fabric_bandwidth; @@ -7209,7 +7216,7 @@ static bool dml_core_mode_support(struct dml2_core_calcs_mode_support_ex *in_out mode_lib->ms.support.WritebackLatencySupport = true; for (k = 0; k <= mode_lib->ms.num_active_planes - 1; k++) { if (display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].writeback.enable == true && - (mode_lib->ms.WriteBandwidth[k] > mode_lib->ip.writeback_interface_buffer_size_kbytes * 1024 / mode_lib->soc.qos_parameters.writeback.base_latency_us)) { + (mode_lib->ms.WriteBandwidth[k] > mode_lib->ip.writeback_interface_buffer_size_kbytes * 1024 / ((double)mode_lib->soc.qos_parameters.writeback.base_latency_us))) { mode_lib->ms.support.WritebackLatencySupport = false; } } diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c index 8e68a8094658f..a31db5742675d 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn3.c @@ -497,7 +497,6 @@ bool pmo_dcn3_optimize_dcc_mcache(struct dml2_pmo_optimize_dcc_mcache_in_out *in in_out->cfg_support_info->plane_support_info[i].dpps_used)) { result = false; } else { - free_pipes -= planes_on_stream; break; } } else { @@ -666,7 +665,7 @@ bool pmo_dcn3_optimize_for_pstate_support(struct dml2_pmo_optimize_for_pstate_su struct dml2_pmo_instance *pmo = in_out->instance; unsigned int stream_index; bool success = false; - bool reached_end = true; + bool reached_end; memcpy(in_out->optimized_display_config, in_out->base_display_config, sizeof(struct display_configuation_with_meta)); diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c index 30767f330fd48..3bb5eb2e79aec 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c @@ -334,7 +334,6 @@ bool pmo_dcn4_fams2_optimize_dcc_mcache(struct dml2_pmo_optimize_dcc_mcache_in_o in_out->cfg_support_info->plane_support_info[i].dpps_used)) { result = false; } else { - free_pipes -= planes_on_stream; break; } } else { @@ -672,8 +671,6 @@ bool pmo_dcn4_fams2_initialize(struct dml2_pmo_initialize_in_out *in_out) /* populate list */ expand_base_strategies(pmo, base_strategy_list_4_display, base_strategy_list_4_display_size, 4); break; - default: - break; } } diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_optimization.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_optimization.c index dc8af4dd04108..d0e026d981b50 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_optimization.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/dml2_top_optimization.c @@ -219,7 +219,6 @@ bool dml2_top_optimization_perform_optimization_phase_1(struct dml2_optimization copy_display_configuration_with_meta(&l->cur_candidate_display_cfg, params->display_config); highest_state = l->cur_candidate_display_cfg.stage1.min_clk_index_for_latency; lowest_state = 0; - cur_state = 0; while (highest_state > lowest_state) { cur_state = (highest_state + lowest_state) / 2; From 2b61a48af6fbd981eccdebcf0f9f1c1302923de6 Mon Sep 17 00:00:00 2001 From: Aurabindo Pillai Date: Wed, 14 Aug 2024 17:56:17 -0400 Subject: [PATCH 1398/1868] drm/amd/display: do not set traslate_by_source for DCN401 cursor translate_by_source need not be set for DCN401 onwards since cursor cursor composition comes after scaler in the hardware pipeline. Hence offset calculation has been reworked, and this setting is not necessary to be enabled anymore. Reviewed-by: Rodrigo Siqueira Signed-off-by: Aurabindo Pillai Signed-off-by: Zaeem Mohamed Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index e68b7feb284b5..13d26f67e7539 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -1380,6 +1380,7 @@ int amdgpu_dm_plane_get_cursor_position(struct drm_plane *plane, struct drm_crtc struct dc_cursor_position *position) { struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc); + struct amdgpu_device *adev = drm_to_adev(plane->dev); int x, y; int xorigin = 0, yorigin = 0; @@ -1411,12 +1412,14 @@ int amdgpu_dm_plane_get_cursor_position(struct drm_plane *plane, struct drm_crtc y = 0; } position->enable = true; - position->translate_by_source = true; position->x = x; position->y = y; position->x_hotspot = xorigin; position->y_hotspot = yorigin; + if (amdgpu_ip_version(adev, DCE_HWIP, 0) < IP_VERSION(4, 0, 1)) + position->translate_by_source = true; + return 0; } From b7723d85627670b4b8e266b7aa0311ec0bb2eea9 Mon Sep 17 00:00:00 2001 From: Nicholas Kazlauskas Date: Thu, 15 Aug 2024 16:31:44 -0400 Subject: [PATCH 1399/1868] drm/amd/display: Allocate DCN35 clock table transfer buffers in GART [Why] Request from PMFW to use GART for clock table transfer tables as framebuffer is being deprecated on APU. [How] Switch over to GART via the allocation flag. Reviewed-by: Sung joon Kim Signed-off-by: Nicholas Kazlauskas Signed-off-by: Zaeem Mohamed Tested-by: Daniel Wheeler --- .../gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c index 0ce9b40dfc68d..f50054089da74 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c @@ -1100,7 +1100,7 @@ void dcn35_clk_mgr_construct( clk_mgr->smu_wm_set.wm_set = (struct dcn35_watermarks *)dm_helpers_allocate_gpu_mem( clk_mgr->base.base.ctx, - DC_MEM_ALLOC_TYPE_FRAME_BUFFER, + DC_MEM_ALLOC_TYPE_GART, sizeof(struct dcn35_watermarks), &clk_mgr->smu_wm_set.mc_address.quad_part); @@ -1112,7 +1112,7 @@ void dcn35_clk_mgr_construct( smu_dpm_clks.dpm_clks = (DpmClocks_t_dcn35 *)dm_helpers_allocate_gpu_mem( clk_mgr->base.base.ctx, - DC_MEM_ALLOC_TYPE_FRAME_BUFFER, + DC_MEM_ALLOC_TYPE_GART, sizeof(DpmClocks_t_dcn35), &smu_dpm_clks.mc_address.quad_part); @@ -1209,7 +1209,7 @@ void dcn35_clk_mgr_construct( } if (smu_dpm_clks.dpm_clks && smu_dpm_clks.mc_address.quad_part != 0) - dm_helpers_free_gpu_mem(clk_mgr->base.base.ctx, DC_MEM_ALLOC_TYPE_FRAME_BUFFER, + dm_helpers_free_gpu_mem(clk_mgr->base.base.ctx, DC_MEM_ALLOC_TYPE_GART, smu_dpm_clks.dpm_clks); if (ctx->dc->config.disable_ips != DMUB_IPS_DISABLE_ALL) { From 428ad7f374af7f22da8bbc9df9f17fbab34aa82d Mon Sep 17 00:00:00 2001 From: ChunTao Tso Date: Thu, 8 Aug 2024 17:25:55 +0800 Subject: [PATCH 1400/1868] drm/amd/display: Retry Replay residency [Why] Because sometime DMUB GPINT will time out, it will cause we return 0 as residency number. [How] Retry to avoid this happened. Reviewed-by: Robin Chen Signed-off-by: ChunTao Tso Signed-off-by: Zaeem Mohamed Tested-by: Daniel Wheeler --- .../gpu/drm/amd/display/dc/dce/dmub_replay.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c index 14f9359616728..c31e4f26a305b 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c @@ -12,6 +12,8 @@ #define MAX_PIPES 6 +#define GPINT_RETRY_NUM 20 + static const uint8_t DP_SINK_DEVICE_STR_ID_1[] = {7, 1, 8, 7, 3}; static const uint8_t DP_SINK_DEVICE_STR_ID_2[] = {7, 1, 8, 7, 5}; @@ -222,6 +224,7 @@ static void dmub_replay_residency(struct dmub_replay *dmub, uint8_t panel_inst, uint32_t *residency, const bool is_start, enum pr_residency_mode mode) { uint16_t param = (uint16_t)(panel_inst << 8); + uint32_t i = 0; switch (mode) { case PR_RESIDENCY_MODE_PHY: @@ -249,10 +252,17 @@ static void dmub_replay_residency(struct dmub_replay *dmub, uint8_t panel_inst, if (is_start) param |= REPLAY_RESIDENCY_ENABLE; - // Send gpint command and wait for ack - if (!dc_wake_and_execute_gpint(dmub->ctx, DMUB_GPINT__REPLAY_RESIDENCY, param, - residency, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY)) - *residency = 0; + for (i = 0; i < GPINT_RETRY_NUM; i++) { + // Send gpint command and wait for ack + if (dc_wake_and_execute_gpint(dmub->ctx, DMUB_GPINT__REPLAY_RESIDENCY, param, + residency, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY)) + return; + + udelay(100); + } + + // it means gpint retry many times + *residency = 0; } /* From ae08b889c52f9e7e9cf42b43606f96d265aecd04 Mon Sep 17 00:00:00 2001 From: Fangzhi Zuo Date: Mon, 12 Aug 2024 12:13:44 -0400 Subject: [PATCH 1401/1868] drm/amd/display: Fix Synaptics Cascaded Panamera DSC Determination Synaptics Cascaded Panamera topology needs to unconditionally acquire root aux for dsc decoding. Reviewed-by: Roman Li Signed-off-by: Fangzhi Zuo Signed-off-by: Zaeem Mohamed Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 8d803993dc627..268ef6cafc694 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -285,7 +285,7 @@ static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnecto aconnector->dsc_aux = &aconnector->mst_root->dm_dp_aux.aux; /* synaptics cascaded MST hub case */ - if (!aconnector->dsc_aux && is_synaptics_cascaded_panamera(aconnector->dc_link, port)) + if (is_synaptics_cascaded_panamera(aconnector->dc_link, port)) aconnector->dsc_aux = port->mgr->aux; if (!aconnector->dsc_aux) From 6b861a55fade09dd6c67051b8a718e4f2aafc09a Mon Sep 17 00:00:00 2001 From: Nicholas Kazlauskas Date: Fri, 21 Jun 2024 16:11:28 -0400 Subject: [PATCH 1402/1868] drm/amd/display: Notify DMCUB of D0/D3 state [Why] We want to avoid arming the HPD timer in firmware when preparing for S0i3 entry when DC is considered in D3. [How] Notify DMCUB of the power state transitions so it can decide to arm the HPD timer for idle in DCN35 only in D0. Reviewed-by: Nicholas Kazlauskas Signed-off-by: Nicholas Kazlauskas Signed-off-by: Ovidiu Bunea Signed-off-by: Zaeem Mohamed Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/core/dc.c | 4 ++ drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 30 ++++++++++++++- drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h | 24 +++++++++++- .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 38 ++++++++++++++++++- 4 files changed, 92 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 92b2a679f1663..03df38703095e 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -5162,6 +5162,8 @@ void dc_set_power_state(struct dc *dc, enum dc_acpi_cm_power_state power_state) dc_z10_restore(dc); + dc_dmub_srv_notify_fw_dc_power_state(dc->ctx->dmub_srv, power_state); + dc->hwss.init_hw(dc); if (dc->hwss.init_sys_ctx != NULL && @@ -5173,6 +5175,8 @@ void dc_set_power_state(struct dc *dc, enum dc_acpi_cm_power_state power_state) default: ASSERT(dc->current_state->stream_count == 0); + dc_dmub_srv_notify_fw_dc_power_state(dc->ctx->dmub_srv, power_state); + dc_state_destruct(dc->current_state); break; diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c index b1265124608be..1e7de0f03290a 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c +++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c @@ -1476,7 +1476,7 @@ static void dc_dmub_srv_exit_low_power_state(const struct dc *dc) ips2_exit_count); } -void dc_dmub_srv_set_power_state(struct dc_dmub_srv *dc_dmub_srv, enum dc_acpi_cm_power_state powerState) +void dc_dmub_srv_set_power_state(struct dc_dmub_srv *dc_dmub_srv, enum dc_acpi_cm_power_state power_state) { struct dmub_srv *dmub; @@ -1485,12 +1485,38 @@ void dc_dmub_srv_set_power_state(struct dc_dmub_srv *dc_dmub_srv, enum dc_acpi_c dmub = dc_dmub_srv->dmub; - if (powerState == DC_ACPI_CM_POWER_STATE_D0) + if (power_state == DC_ACPI_CM_POWER_STATE_D0) dmub_srv_set_power_state(dmub, DMUB_POWER_STATE_D0); else dmub_srv_set_power_state(dmub, DMUB_POWER_STATE_D3); } +void dc_dmub_srv_notify_fw_dc_power_state(struct dc_dmub_srv *dc_dmub_srv, + enum dc_acpi_cm_power_state power_state) +{ + union dmub_rb_cmd cmd; + + if (!dc_dmub_srv) + return; + + memset(&cmd, 0, sizeof(cmd)); + + cmd.idle_opt_set_dc_power_state.header.type = DMUB_CMD__IDLE_OPT; + cmd.idle_opt_set_dc_power_state.header.sub_type = DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE; + cmd.idle_opt_set_dc_power_state.header.payload_bytes = + sizeof(cmd.idle_opt_set_dc_power_state) - sizeof(cmd.idle_opt_set_dc_power_state.header); + + if (power_state == DC_ACPI_CM_POWER_STATE_D0) { + cmd.idle_opt_set_dc_power_state.data.power_state = DMUB_IDLE_OPT_DC_POWER_STATE_D0; + } else if (power_state == DC_ACPI_CM_POWER_STATE_D3) { + cmd.idle_opt_set_dc_power_state.data.power_state = DMUB_IDLE_OPT_DC_POWER_STATE_D3; + } else { + cmd.idle_opt_set_dc_power_state.data.power_state = DMUB_IDLE_OPT_DC_POWER_STATE_UNKNOWN; + } + + dc_wake_and_execute_dmub_cmd(dc_dmub_srv->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); +} + bool dc_dmub_srv_should_detect(struct dc_dmub_srv *dc_dmub_srv) { volatile const struct dmub_shared_state_ips_fw *ips_fw; diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h index 580940222777e..42f0cb672d8bb 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h +++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h @@ -109,7 +109,29 @@ bool dc_dmub_srv_is_hw_pwr_up(struct dc_dmub_srv *dc_dmub_srv, bool wait); void dc_dmub_srv_apply_idle_power_optimizations(const struct dc *dc, bool allow_idle); -void dc_dmub_srv_set_power_state(struct dc_dmub_srv *dc_dmub_srv, enum dc_acpi_cm_power_state powerState); +/** + * dc_dmub_srv_set_power_state() - Sets the power state for DMUB service. + * + * Controls whether messaging the DMCUB or interfacing with it via HW register + * interaction is permittable. + * + * @dc_dmub_srv - The DC DMUB service pointer + * @power_state - the DC power state + */ +void dc_dmub_srv_set_power_state(struct dc_dmub_srv *dc_dmub_srv, enum dc_acpi_cm_power_state power_state); + +/** + * dc_dmub_srv_notify_fw_dc_power_state() - Notifies firmware of the DC power state. + * + * Differs from dc_dmub_srv_set_power_state in that it needs to access HW in order + * to message DMCUB of the state transition. Should come after the D0 exit and + * before D3 set power state. + * + * @dc_dmub_srv - The DC DMUB service pointer + * @power_state - the DC power state + */ +void dc_dmub_srv_notify_fw_dc_power_state(struct dc_dmub_srv *dc_dmub_srv, + enum dc_acpi_cm_power_state power_state); /** * @dc_dmub_srv_should_detect() - Checks if link detection is required. diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index c5f99cbff0b64..f5dda1d69ae04 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -1879,7 +1879,12 @@ enum dmub_cmd_idle_opt_type { /** * DCN hardware notify idle. */ - DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE = 2 + DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE = 2, + + /** + * DCN hardware notify power state. + */ + DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE = 3, }; /** @@ -1906,6 +1911,33 @@ struct dmub_rb_cmd_idle_opt_dcn_notify_idle { struct dmub_dcn_notify_idle_cntl_data cntl_data; }; +/** + * enum dmub_idle_opt_dc_power_state - DC power states. + */ +enum dmub_idle_opt_dc_power_state { + DMUB_IDLE_OPT_DC_POWER_STATE_UNKNOWN = 0, + DMUB_IDLE_OPT_DC_POWER_STATE_D0 = 1, + DMUB_IDLE_OPT_DC_POWER_STATE_D1 = 2, + DMUB_IDLE_OPT_DC_POWER_STATE_D2 = 4, + DMUB_IDLE_OPT_DC_POWER_STATE_D3 = 8, +}; + +/** + * struct dmub_idle_opt_set_dc_power_state_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. + */ +struct dmub_idle_opt_set_dc_power_state_data { + uint8_t power_state; /**< power state */ + uint8_t pad[3]; /**< padding */ +}; + +/** + * struct dmub_rb_cmd_idle_opt_set_dc_power_state - Data passed to FW in a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. + */ +struct dmub_rb_cmd_idle_opt_set_dc_power_state { + struct dmub_cmd_header header; /**< header */ + struct dmub_idle_opt_set_dc_power_state_data data; +}; + /** * struct dmub_clocks - Clock update notification. */ @@ -5298,6 +5330,10 @@ union dmub_rb_cmd { * Definition of a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command. */ struct dmub_rb_cmd_idle_opt_dcn_notify_idle idle_opt_notify_idle; + /** + * Definition of a DMUB_CMD__IDLE_OPT_SET_DC_POWER_STATE command. + */ + struct dmub_rb_cmd_idle_opt_set_dc_power_state idle_opt_set_dc_power_state; /* * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command. */ From aa11b7e6bd09b024fe32d2817e0d879058504c60 Mon Sep 17 00:00:00 2001 From: Samson Tam Date: Fri, 16 Aug 2024 11:42:35 -0400 Subject: [PATCH 1403/1868] drm/amd/display: add back quality EASF and ISHARP and dc dependency changes [Why] Addressed previous issues with quality changes and new issues due to rolling back quality changes. [How] This reverts commit f4c206eb937e5acb12c295cb3895c112766202bc, fixes merge conflicts, and fixed some formatting errors. Store current sharpness level for each pregen table to minimize calculating sharpness table every time. Disable dynamic ODM when sharpness is enabled. Reviewed-by: Jun Lei Signed-off-by: Samson Tam Signed-off-by: Zaeem Mohamed Tested-by: Daniel Wheeler --- .../gpu/drm/amd/display/dc/core/dc_resource.c | 2 - .../gpu/drm/amd/display/dc/dc_spl_translate.c | 48 +- .../gpu/drm/amd/display/dc/dc_spl_translate.h | 1 + .../dc/dml2/dml21/dml21_translation_helper.c | 11 +- .../display/dc/dpp/dcn401/dcn401_dpp_dscl.c | 568 +++--- .../dc/resource/dcn401/dcn401_resource.c | 7 + drivers/gpu/drm/amd/display/dc/spl/Makefile | 2 +- drivers/gpu/drm/amd/display/dc/spl/dc_spl.c | 1313 ++++++++----- .../drm/amd/display/dc/spl/dc_spl_filters.c | 15 + .../drm/amd/display/dc/spl/dc_spl_filters.h | 15 + .../display/dc/spl/dc_spl_isharp_filters.c | 460 ++++- .../display/dc/spl/dc_spl_isharp_filters.h | 35 +- .../display/dc/spl/dc_spl_scl_easf_filters.c | 1726 +++++++++++++++++ .../display/dc/spl/dc_spl_scl_easf_filters.h | 38 + .../amd/display/dc/spl/dc_spl_scl_filters.c | 91 +- .../amd/display/dc/spl/dc_spl_scl_filters.h | 55 +- .../display/dc/spl/dc_spl_scl_filters_old.c | 25 - .../gpu/drm/amd/display/dc/spl/dc_spl_types.h | 43 +- .../gpu/drm/amd/display/dc/spl/spl_debug.h | 25 + .../drm/amd/display/dc/spl/spl_fixpt31_32.c | 497 +++++ .../drm/amd/display/dc/spl/spl_fixpt31_32.h | 525 +++++ 21 files changed, 4507 insertions(+), 995 deletions(-) create mode 100644 drivers/gpu/drm/amd/display/dc/spl/dc_spl_filters.c create mode 100644 drivers/gpu/drm/amd/display/dc/spl/dc_spl_filters.h create mode 100644 drivers/gpu/drm/amd/display/dc/spl/dc_spl_scl_easf_filters.c create mode 100644 drivers/gpu/drm/amd/display/dc/spl/dc_spl_scl_easf_filters.h delete mode 100644 drivers/gpu/drm/amd/display/dc/spl/dc_spl_scl_filters_old.c create mode 100644 drivers/gpu/drm/amd/display/dc/spl/spl_debug.h create mode 100644 drivers/gpu/drm/amd/display/dc/spl/spl_fixpt31_32.c create mode 100644 drivers/gpu/drm/amd/display/dc/spl/spl_fixpt31_32.h diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index ef585a89847bf..c7599c40d4be3 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -1506,8 +1506,6 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP; pipe_ctx->plane_res.scl_data.lb_params.alpha_en = plane_state->per_pixel_alpha; - spl_out->scl_data.h_active = pipe_ctx->plane_res.scl_data.h_active; - spl_out->scl_data.v_active = pipe_ctx->plane_res.scl_data.v_active; // Convert pipe_ctx to respective input params for SPL translate_SPL_in_params_from_pipe_ctx(pipe_ctx, spl_in); diff --git a/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c b/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c index 8f85a1db5eba4..92ad0bac182ca 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c +++ b/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c @@ -42,26 +42,26 @@ static void populate_spltaps_from_taps(struct spl_taps *spl_scaling_quality, static void populate_taps_from_spltaps(struct scaling_taps *scaling_quality, const struct spl_taps *spl_scaling_quality) { - scaling_quality->h_taps_c = spl_scaling_quality->h_taps_c; - scaling_quality->h_taps = spl_scaling_quality->h_taps; - scaling_quality->v_taps_c = spl_scaling_quality->v_taps_c; - scaling_quality->v_taps = spl_scaling_quality->v_taps; + scaling_quality->h_taps_c = spl_scaling_quality->h_taps_c + 1; + scaling_quality->h_taps = spl_scaling_quality->h_taps + 1; + scaling_quality->v_taps_c = spl_scaling_quality->v_taps_c + 1; + scaling_quality->v_taps = spl_scaling_quality->v_taps + 1; } static void populate_ratios_from_splratios(struct scaling_ratios *ratios, - const struct spl_ratios *spl_ratios) + const struct ratio *spl_ratios) { - ratios->horz = spl_ratios->horz; - ratios->vert = spl_ratios->vert; - ratios->horz_c = spl_ratios->horz_c; - ratios->vert_c = spl_ratios->vert_c; + ratios->horz = dc_fixpt_from_ux_dy(spl_ratios->h_scale_ratio >> 5, 3, 19); + ratios->vert = dc_fixpt_from_ux_dy(spl_ratios->v_scale_ratio >> 5, 3, 19); + ratios->horz_c = dc_fixpt_from_ux_dy(spl_ratios->h_scale_ratio_c >> 5, 3, 19); + ratios->vert_c = dc_fixpt_from_ux_dy(spl_ratios->v_scale_ratio_c >> 5, 3, 19); } static void populate_inits_from_splinits(struct scl_inits *inits, - const struct spl_inits *spl_inits) + const struct init *spl_inits) { - inits->h = spl_inits->h; - inits->v = spl_inits->v; - inits->h_c = spl_inits->h_c; - inits->v_c = spl_inits->v_c; + inits->h = dc_fixpt_from_int_dy(spl_inits->h_filter_init_int, spl_inits->h_filter_init_frac >> 5, 0, 19); + inits->v = dc_fixpt_from_int_dy(spl_inits->v_filter_init_int, spl_inits->v_filter_init_frac >> 5, 0, 19); + inits->h_c = dc_fixpt_from_int_dy(spl_inits->h_filter_init_int_c, spl_inits->h_filter_init_frac_c >> 5, 0, 19); + inits->v_c = dc_fixpt_from_int_dy(spl_inits->v_filter_init_int_c, spl_inits->v_filter_init_frac_c >> 5, 0, 19); } /// @brief Translate SPL input parameters from pipe context /// @param pipe_ctx @@ -171,6 +171,14 @@ void translate_SPL_in_params_from_pipe_ctx(struct pipe_ctx *pipe_ctx, struct spl /* Translate transfer function */ spl_in->basic_in.tf_type = (enum spl_transfer_func_type) plane_state->in_transfer_func.type; spl_in->basic_in.tf_predefined_type = (enum spl_transfer_func_predefined) plane_state->in_transfer_func.tf; + + spl_in->h_active = pipe_ctx->plane_res.scl_data.h_active; + spl_in->v_active = pipe_ctx->plane_res.scl_data.v_active; + /* Check if it is stream is in fullscreen and if its HDR. + * Use this to determine sharpness levels + */ + spl_in->is_fullscreen = dm_helpers_is_fullscreen(pipe_ctx->stream->ctx, pipe_ctx->stream); + spl_in->is_hdr_on = dm_helpers_is_hdr_on(pipe_ctx->stream->ctx, pipe_ctx->stream); } /// @brief Translate SPL output parameters to pipe context @@ -179,15 +187,15 @@ void translate_SPL_in_params_from_pipe_ctx(struct pipe_ctx *pipe_ctx, struct spl void translate_SPL_out_params_to_pipe_ctx(struct pipe_ctx *pipe_ctx, struct spl_out *spl_out) { // Make scaler data recout point to spl output field recout - populate_rect_from_splrect(&pipe_ctx->plane_res.scl_data.recout, &spl_out->scl_data.recout); + populate_rect_from_splrect(&pipe_ctx->plane_res.scl_data.recout, &spl_out->dscl_prog_data->recout); // Make scaler data ratios point to spl output field ratios - populate_ratios_from_splratios(&pipe_ctx->plane_res.scl_data.ratios, &spl_out->scl_data.ratios); + populate_ratios_from_splratios(&pipe_ctx->plane_res.scl_data.ratios, &spl_out->dscl_prog_data->ratios); // Make scaler data viewport point to spl output field viewport - populate_rect_from_splrect(&pipe_ctx->plane_res.scl_data.viewport, &spl_out->scl_data.viewport); + populate_rect_from_splrect(&pipe_ctx->plane_res.scl_data.viewport, &spl_out->dscl_prog_data->viewport); // Make scaler data viewport_c point to spl output field viewport_c - populate_rect_from_splrect(&pipe_ctx->plane_res.scl_data.viewport_c, &spl_out->scl_data.viewport_c); + populate_rect_from_splrect(&pipe_ctx->plane_res.scl_data.viewport_c, &spl_out->dscl_prog_data->viewport_c); // Make scaler data taps point to spl output field scaling taps - populate_taps_from_spltaps(&pipe_ctx->plane_res.scl_data.taps, &spl_out->scl_data.taps); + populate_taps_from_spltaps(&pipe_ctx->plane_res.scl_data.taps, &spl_out->dscl_prog_data->taps); // Make scaler data init point to spl output field init - populate_inits_from_splinits(&pipe_ctx->plane_res.scl_data.inits, &spl_out->scl_data.inits); + populate_inits_from_splinits(&pipe_ctx->plane_res.scl_data.inits, &spl_out->dscl_prog_data->init); } diff --git a/drivers/gpu/drm/amd/display/dc/dc_spl_translate.h b/drivers/gpu/drm/amd/display/dc/dc_spl_translate.h index c73d640c3632f..eaa5c5373b284 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_spl_translate.h +++ b/drivers/gpu/drm/amd/display/dc/dc_spl_translate.h @@ -6,6 +6,7 @@ #define __DC_SPL_TRANSLATE_H__ #include "dc.h" #include "resource.h" +#include "dm_helpers.h" /* Map SPL input parameters to pipe context * @pipe_ctx: pipe context diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c index 710a25dcfef0f..86a877f9a2ec1 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c @@ -514,7 +514,8 @@ static void populate_dml21_stream_overrides_from_stream_state( break; } if (!stream->ctx->dc->debug.enable_single_display_2to1_odm_policy || - stream->debug.force_odm_combine_segments > 0) + stream->debug.force_odm_combine_segments > 0 || + stream->ctx->dc->debug.force_sharpness > 1) stream_desc->overrides.disable_dynamic_odm = true; stream_desc->overrides.disable_subvp = stream->ctx->dc->debug.force_disable_subvp || stream->hw_cursor_req; } @@ -777,6 +778,14 @@ static void populate_dml21_plane_config_from_plane_state(struct dml2_context *dm * certain cases. Hence do corrective active and disable scaling. */ plane->composition.scaler_info.enabled = false; + } else if ((plane_state->ctx->dc->config.use_spl == true) && + (plane->composition.scaler_info.enabled == false)) { + /* To enable sharpener for 1:1, scaler must be enabled. If use_spl is set, then + * allow case where ratio is 1 but taps > 1 + */ + if ((scaler_data->taps.h_taps > 1) || (scaler_data->taps.v_taps > 1) || + (scaler_data->taps.h_taps_c > 1) || (scaler_data->taps.v_taps_c > 1)) + plane->composition.scaler_info.enabled = true; } /* always_scale is only used for debug purposes not used in production but has to be diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c index 505929800426d..703d7b51c6c27 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c @@ -280,7 +280,8 @@ static void dpp401_dscl_set_scaler_filter( static void dpp401_dscl_set_scl_filter( struct dcn401_dpp *dpp, const struct scaler_data *scl_data, - bool chroma_coef_mode) + bool chroma_coef_mode, + bool force_coeffs_update) { bool h_2tap_hardcode_coef_en = false; bool v_2tap_hardcode_coef_en = false; @@ -343,7 +344,7 @@ static void dpp401_dscl_set_scl_filter( || (filter_v_c && (filter_v_c != dpp->filter_v_c)); } - if (filter_updated) { + if ((filter_updated) || (force_coeffs_update)) { uint32_t scl_mode = REG_READ(SCL_MODE); if (!h_2tap_hardcode_coef_en && filter_h) { @@ -656,274 +657,252 @@ static void dpp401_dscl_set_recout(struct dcn401_dpp *dpp, RECOUT_HEIGHT, recout->height); } /** - * dpp401_dscl_program_easf - Program EASF + * dpp401_dscl_program_easf_v - Program EASF_V * * @dpp_base: High level DPP struct * @scl_data: scalaer_data info * - * This is the primary function to program EASF + * This is the primary function to program vertical EASF registers * */ -static void dpp401_dscl_program_easf(struct dpp *dpp_base, const struct scaler_data *scl_data) +static void dpp401_dscl_program_easf_v(struct dpp *dpp_base, const struct scaler_data *scl_data) { struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base); PERF_TRACE(); - REG_UPDATE(DSCL_SC_MODE, - SCL_SC_MATRIX_MODE, scl_data->dscl_prog_data.easf_matrix_mode); - REG_UPDATE(DSCL_SC_MODE, - SCL_SC_LTONL_EN, scl_data->dscl_prog_data.easf_ltonl_en); /* DSCL_EASF_V_MODE */ - REG_UPDATE(DSCL_EASF_V_MODE, - SCL_EASF_V_EN, scl_data->dscl_prog_data.easf_v_en); - REG_UPDATE(DSCL_EASF_V_MODE, - SCL_EASF_V_2TAP_SHARP_FACTOR, scl_data->dscl_prog_data.easf_v_sharp_factor); - REG_UPDATE(DSCL_EASF_V_MODE, + REG_SET_3(DSCL_EASF_V_MODE, 0, + SCL_EASF_V_EN, scl_data->dscl_prog_data.easf_v_en, + SCL_EASF_V_2TAP_SHARP_FACTOR, scl_data->dscl_prog_data.easf_v_sharp_factor, SCL_EASF_V_RINGEST_FORCE_EN, scl_data->dscl_prog_data.easf_v_ring); - REG_UPDATE(DSCL_EASF_V_BF_CNTL, - SCL_EASF_V_BF1_EN, scl_data->dscl_prog_data.easf_v_bf1_en); - REG_UPDATE(DSCL_EASF_V_BF_CNTL, - SCL_EASF_V_BF2_MODE, scl_data->dscl_prog_data.easf_v_bf2_mode); - REG_UPDATE(DSCL_EASF_V_BF_CNTL, - SCL_EASF_V_BF3_MODE, scl_data->dscl_prog_data.easf_v_bf3_mode); - REG_UPDATE(DSCL_EASF_V_BF_CNTL, - SCL_EASF_V_BF2_FLAT1_GAIN, scl_data->dscl_prog_data.easf_v_bf2_flat1_gain); - REG_UPDATE(DSCL_EASF_V_BF_CNTL, - SCL_EASF_V_BF2_FLAT2_GAIN, scl_data->dscl_prog_data.easf_v_bf2_flat2_gain); - REG_UPDATE(DSCL_EASF_V_BF_CNTL, + + if (!scl_data->dscl_prog_data.easf_v_en) { + PERF_TRACE(); + return; + } + + /* DSCL_EASF_V_BF_CNTL */ + REG_SET_6(DSCL_EASF_V_BF_CNTL, 0, + SCL_EASF_V_BF1_EN, scl_data->dscl_prog_data.easf_v_bf1_en, + SCL_EASF_V_BF2_MODE, scl_data->dscl_prog_data.easf_v_bf2_mode, + SCL_EASF_V_BF3_MODE, scl_data->dscl_prog_data.easf_v_bf3_mode, + SCL_EASF_V_BF2_FLAT1_GAIN, scl_data->dscl_prog_data.easf_v_bf2_flat1_gain, + SCL_EASF_V_BF2_FLAT2_GAIN, scl_data->dscl_prog_data.easf_v_bf2_flat2_gain, SCL_EASF_V_BF2_ROC_GAIN, scl_data->dscl_prog_data.easf_v_bf2_roc_gain); - REG_UPDATE(DSCL_EASF_V_RINGEST_3TAP_CNTL1, - SCL_EASF_V_RINGEST_3TAP_DNTILT_UPTILT, scl_data->dscl_prog_data.easf_v_ringest_3tap_dntilt_uptilt); - REG_UPDATE(DSCL_EASF_V_RINGEST_3TAP_CNTL1, + /* DSCL_EASF_V_RINGEST_3TAP_CNTLn */ + REG_SET_2(DSCL_EASF_V_RINGEST_3TAP_CNTL1, 0, + SCL_EASF_V_RINGEST_3TAP_DNTILT_UPTILT, scl_data->dscl_prog_data.easf_v_ringest_3tap_dntilt_uptilt, SCL_EASF_V_RINGEST_3TAP_UPTILT_MAXVAL, scl_data->dscl_prog_data.easf_v_ringest_3tap_uptilt_max); - REG_UPDATE(DSCL_EASF_V_RINGEST_3TAP_CNTL2, - SCL_EASF_V_RINGEST_3TAP_DNTILT_SLOPE, scl_data->dscl_prog_data.easf_v_ringest_3tap_dntilt_slope); - REG_UPDATE(DSCL_EASF_V_RINGEST_3TAP_CNTL2, + REG_SET_2(DSCL_EASF_V_RINGEST_3TAP_CNTL2, 0, + SCL_EASF_V_RINGEST_3TAP_DNTILT_SLOPE, scl_data->dscl_prog_data.easf_v_ringest_3tap_dntilt_slope, SCL_EASF_V_RINGEST_3TAP_UPTILT1_SLOPE, scl_data->dscl_prog_data.easf_v_ringest_3tap_uptilt1_slope); - REG_UPDATE(DSCL_EASF_V_RINGEST_3TAP_CNTL3, - SCL_EASF_V_RINGEST_3TAP_UPTILT2_SLOPE, scl_data->dscl_prog_data.easf_v_ringest_3tap_uptilt2_slope); - REG_UPDATE(DSCL_EASF_V_RINGEST_3TAP_CNTL3, + REG_SET_2(DSCL_EASF_V_RINGEST_3TAP_CNTL3, 0, + SCL_EASF_V_RINGEST_3TAP_UPTILT2_SLOPE, scl_data->dscl_prog_data.easf_v_ringest_3tap_uptilt2_slope, SCL_EASF_V_RINGEST_3TAP_UPTILT2_OFFSET, scl_data->dscl_prog_data.easf_v_ringest_3tap_uptilt2_offset); - REG_UPDATE(DSCL_EASF_V_RINGEST_EVENTAP_REDUCE, - SCL_EASF_V_RINGEST_EVENTAP_REDUCEG1, scl_data->dscl_prog_data.easf_v_ringest_eventap_reduceg1); - REG_UPDATE(DSCL_EASF_V_RINGEST_EVENTAP_REDUCE, + /* DSCL_EASF_V_RINGEST_EVENTAP_REDUCE */ + REG_SET_2(DSCL_EASF_V_RINGEST_EVENTAP_REDUCE, 0, + SCL_EASF_V_RINGEST_EVENTAP_REDUCEG1, scl_data->dscl_prog_data.easf_v_ringest_eventap_reduceg1, SCL_EASF_V_RINGEST_EVENTAP_REDUCEG2, scl_data->dscl_prog_data.easf_v_ringest_eventap_reduceg2); - REG_UPDATE(DSCL_EASF_V_RINGEST_EVENTAP_GAIN, - SCL_EASF_V_RINGEST_EVENTAP_GAIN1, scl_data->dscl_prog_data.easf_v_ringest_eventap_gain1); - REG_UPDATE(DSCL_EASF_V_RINGEST_EVENTAP_GAIN, + /* DSCL_EASF_V_RINGEST_EVENTAP_GAIN */ + REG_SET_2(DSCL_EASF_V_RINGEST_EVENTAP_GAIN, 0, + SCL_EASF_V_RINGEST_EVENTAP_GAIN1, scl_data->dscl_prog_data.easf_v_ringest_eventap_gain1, SCL_EASF_V_RINGEST_EVENTAP_GAIN2, scl_data->dscl_prog_data.easf_v_ringest_eventap_gain2); - REG_UPDATE(DSCL_EASF_V_BF_FINAL_MAX_MIN, - SCL_EASF_V_BF_MAXA, scl_data->dscl_prog_data.easf_v_bf_maxa); - REG_UPDATE(DSCL_EASF_V_BF_FINAL_MAX_MIN, - SCL_EASF_V_BF_MAXB, scl_data->dscl_prog_data.easf_v_bf_maxb); - REG_UPDATE(DSCL_EASF_V_BF_FINAL_MAX_MIN, - SCL_EASF_V_BF_MINA, scl_data->dscl_prog_data.easf_v_bf_mina); - REG_UPDATE(DSCL_EASF_V_BF_FINAL_MAX_MIN, + /* DSCL_EASF_V_BF_FINAL_MAX_MIN */ + REG_SET_4(DSCL_EASF_V_BF_FINAL_MAX_MIN, 0, + SCL_EASF_V_BF_MAXA, scl_data->dscl_prog_data.easf_v_bf_maxa, + SCL_EASF_V_BF_MAXB, scl_data->dscl_prog_data.easf_v_bf_maxb, + SCL_EASF_V_BF_MINA, scl_data->dscl_prog_data.easf_v_bf_mina, SCL_EASF_V_BF_MINB, scl_data->dscl_prog_data.easf_v_bf_minb); - REG_UPDATE(DSCL_EASF_V_BF1_PWL_SEG0, - SCL_EASF_V_BF1_PWL_IN_SEG0, scl_data->dscl_prog_data.easf_v_bf1_pwl_in_seg0); - REG_UPDATE(DSCL_EASF_V_BF1_PWL_SEG0, - SCL_EASF_V_BF1_PWL_BASE_SEG0, scl_data->dscl_prog_data.easf_v_bf1_pwl_base_seg0); - REG_UPDATE(DSCL_EASF_V_BF1_PWL_SEG0, + /* DSCL_EASF_V_BF1_PWL_SEGn */ + REG_SET_3(DSCL_EASF_V_BF1_PWL_SEG0, 0, + SCL_EASF_V_BF1_PWL_IN_SEG0, scl_data->dscl_prog_data.easf_v_bf1_pwl_in_seg0, + SCL_EASF_V_BF1_PWL_BASE_SEG0, scl_data->dscl_prog_data.easf_v_bf1_pwl_base_seg0, SCL_EASF_V_BF1_PWL_SLOPE_SEG0, scl_data->dscl_prog_data.easf_v_bf1_pwl_slope_seg0); - REG_UPDATE(DSCL_EASF_V_BF1_PWL_SEG1, - SCL_EASF_V_BF1_PWL_IN_SEG1, scl_data->dscl_prog_data.easf_v_bf1_pwl_in_seg1); - REG_UPDATE(DSCL_EASF_V_BF1_PWL_SEG1, - SCL_EASF_V_BF1_PWL_BASE_SEG1, scl_data->dscl_prog_data.easf_v_bf1_pwl_base_seg1); - REG_UPDATE(DSCL_EASF_V_BF1_PWL_SEG1, + REG_SET_3(DSCL_EASF_V_BF1_PWL_SEG1, 0, + SCL_EASF_V_BF1_PWL_IN_SEG1, scl_data->dscl_prog_data.easf_v_bf1_pwl_in_seg1, + SCL_EASF_V_BF1_PWL_BASE_SEG1, scl_data->dscl_prog_data.easf_v_bf1_pwl_base_seg1, SCL_EASF_V_BF1_PWL_SLOPE_SEG1, scl_data->dscl_prog_data.easf_v_bf1_pwl_slope_seg1); - REG_UPDATE(DSCL_EASF_V_BF1_PWL_SEG2, - SCL_EASF_V_BF1_PWL_IN_SEG2, scl_data->dscl_prog_data.easf_v_bf1_pwl_in_seg2); - REG_UPDATE(DSCL_EASF_V_BF1_PWL_SEG2, - SCL_EASF_V_BF1_PWL_BASE_SEG2, scl_data->dscl_prog_data.easf_v_bf1_pwl_base_seg2); - REG_UPDATE(DSCL_EASF_V_BF1_PWL_SEG2, + REG_SET_3(DSCL_EASF_V_BF1_PWL_SEG2, 0, + SCL_EASF_V_BF1_PWL_IN_SEG2, scl_data->dscl_prog_data.easf_v_bf1_pwl_in_seg2, + SCL_EASF_V_BF1_PWL_BASE_SEG2, scl_data->dscl_prog_data.easf_v_bf1_pwl_base_seg2, SCL_EASF_V_BF1_PWL_SLOPE_SEG2, scl_data->dscl_prog_data.easf_v_bf1_pwl_slope_seg2); - REG_UPDATE(DSCL_EASF_V_BF1_PWL_SEG3, - SCL_EASF_V_BF1_PWL_IN_SEG3, scl_data->dscl_prog_data.easf_v_bf1_pwl_in_seg3); - REG_UPDATE(DSCL_EASF_V_BF1_PWL_SEG3, - SCL_EASF_V_BF1_PWL_BASE_SEG3, scl_data->dscl_prog_data.easf_v_bf1_pwl_base_seg3); - REG_UPDATE(DSCL_EASF_V_BF1_PWL_SEG3, + REG_SET_3(DSCL_EASF_V_BF1_PWL_SEG3, 0, + SCL_EASF_V_BF1_PWL_IN_SEG3, scl_data->dscl_prog_data.easf_v_bf1_pwl_in_seg3, + SCL_EASF_V_BF1_PWL_BASE_SEG3, scl_data->dscl_prog_data.easf_v_bf1_pwl_base_seg3, SCL_EASF_V_BF1_PWL_SLOPE_SEG3, scl_data->dscl_prog_data.easf_v_bf1_pwl_slope_seg3); - REG_UPDATE(DSCL_EASF_V_BF1_PWL_SEG4, - SCL_EASF_V_BF1_PWL_IN_SEG4, scl_data->dscl_prog_data.easf_v_bf1_pwl_in_seg4); - REG_UPDATE(DSCL_EASF_V_BF1_PWL_SEG4, - SCL_EASF_V_BF1_PWL_BASE_SEG4, scl_data->dscl_prog_data.easf_v_bf1_pwl_base_seg4); - REG_UPDATE(DSCL_EASF_V_BF1_PWL_SEG4, + REG_SET_3(DSCL_EASF_V_BF1_PWL_SEG4, 0, + SCL_EASF_V_BF1_PWL_IN_SEG4, scl_data->dscl_prog_data.easf_v_bf1_pwl_in_seg4, + SCL_EASF_V_BF1_PWL_BASE_SEG4, scl_data->dscl_prog_data.easf_v_bf1_pwl_base_seg4, SCL_EASF_V_BF1_PWL_SLOPE_SEG4, scl_data->dscl_prog_data.easf_v_bf1_pwl_slope_seg4); - REG_UPDATE(DSCL_EASF_V_BF1_PWL_SEG5, - SCL_EASF_V_BF1_PWL_IN_SEG5, scl_data->dscl_prog_data.easf_v_bf1_pwl_in_seg5); - REG_UPDATE(DSCL_EASF_V_BF1_PWL_SEG5, - SCL_EASF_V_BF1_PWL_BASE_SEG5, scl_data->dscl_prog_data.easf_v_bf1_pwl_base_seg5); - REG_UPDATE(DSCL_EASF_V_BF1_PWL_SEG5, + REG_SET_3(DSCL_EASF_V_BF1_PWL_SEG5, 0, + SCL_EASF_V_BF1_PWL_IN_SEG5, scl_data->dscl_prog_data.easf_v_bf1_pwl_in_seg5, + SCL_EASF_V_BF1_PWL_BASE_SEG5, scl_data->dscl_prog_data.easf_v_bf1_pwl_base_seg5, SCL_EASF_V_BF1_PWL_SLOPE_SEG5, scl_data->dscl_prog_data.easf_v_bf1_pwl_slope_seg5); - REG_UPDATE(DSCL_EASF_V_BF1_PWL_SEG6, - SCL_EASF_V_BF1_PWL_IN_SEG6, scl_data->dscl_prog_data.easf_v_bf1_pwl_in_seg6); - REG_UPDATE(DSCL_EASF_V_BF1_PWL_SEG6, - SCL_EASF_V_BF1_PWL_BASE_SEG6, scl_data->dscl_prog_data.easf_v_bf1_pwl_base_seg6); - REG_UPDATE(DSCL_EASF_V_BF1_PWL_SEG6, + REG_SET_3(DSCL_EASF_V_BF1_PWL_SEG6, 0, + SCL_EASF_V_BF1_PWL_IN_SEG6, scl_data->dscl_prog_data.easf_v_bf1_pwl_in_seg6, + SCL_EASF_V_BF1_PWL_BASE_SEG6, scl_data->dscl_prog_data.easf_v_bf1_pwl_base_seg6, SCL_EASF_V_BF1_PWL_SLOPE_SEG6, scl_data->dscl_prog_data.easf_v_bf1_pwl_slope_seg6); - REG_UPDATE(DSCL_EASF_V_BF1_PWL_SEG7, - SCL_EASF_V_BF1_PWL_IN_SEG7, scl_data->dscl_prog_data.easf_v_bf1_pwl_in_seg7); - REG_UPDATE(DSCL_EASF_V_BF1_PWL_SEG7, + REG_SET_2(DSCL_EASF_V_BF1_PWL_SEG7, 0, + SCL_EASF_V_BF1_PWL_IN_SEG7, scl_data->dscl_prog_data.easf_v_bf1_pwl_in_seg7, SCL_EASF_V_BF1_PWL_BASE_SEG7, scl_data->dscl_prog_data.easf_v_bf1_pwl_base_seg7); - REG_UPDATE(DSCL_EASF_V_BF3_PWL_SEG0, - SCL_EASF_V_BF3_PWL_IN_SEG0, scl_data->dscl_prog_data.easf_v_bf3_pwl_in_set0); - REG_UPDATE(DSCL_EASF_V_BF3_PWL_SEG0, - SCL_EASF_V_BF3_PWL_BASE_SEG0, scl_data->dscl_prog_data.easf_v_bf3_pwl_base_set0); - REG_UPDATE(DSCL_EASF_V_BF3_PWL_SEG0, + /* DSCL_EASF_V_BF3_PWL_SEGn */ + REG_SET_3(DSCL_EASF_V_BF3_PWL_SEG0, 0, + SCL_EASF_V_BF3_PWL_IN_SEG0, scl_data->dscl_prog_data.easf_v_bf3_pwl_in_set0, + SCL_EASF_V_BF3_PWL_BASE_SEG0, scl_data->dscl_prog_data.easf_v_bf3_pwl_base_set0, SCL_EASF_V_BF3_PWL_SLOPE_SEG0, scl_data->dscl_prog_data.easf_v_bf3_pwl_slope_set0); - REG_UPDATE(DSCL_EASF_V_BF3_PWL_SEG1, - SCL_EASF_V_BF3_PWL_IN_SEG1, scl_data->dscl_prog_data.easf_v_bf3_pwl_in_set1); - REG_UPDATE(DSCL_EASF_V_BF3_PWL_SEG1, - SCL_EASF_V_BF3_PWL_BASE_SEG1, scl_data->dscl_prog_data.easf_v_bf3_pwl_base_set1); - REG_UPDATE(DSCL_EASF_V_BF3_PWL_SEG1, + REG_SET_3(DSCL_EASF_V_BF3_PWL_SEG1, 0, + SCL_EASF_V_BF3_PWL_IN_SEG1, scl_data->dscl_prog_data.easf_v_bf3_pwl_in_set1, + SCL_EASF_V_BF3_PWL_BASE_SEG1, scl_data->dscl_prog_data.easf_v_bf3_pwl_base_set1, SCL_EASF_V_BF3_PWL_SLOPE_SEG1, scl_data->dscl_prog_data.easf_v_bf3_pwl_slope_set1); - REG_UPDATE(DSCL_EASF_V_BF3_PWL_SEG2, - SCL_EASF_V_BF3_PWL_IN_SEG2, scl_data->dscl_prog_data.easf_v_bf3_pwl_in_set2); - REG_UPDATE(DSCL_EASF_V_BF3_PWL_SEG2, - SCL_EASF_V_BF3_PWL_BASE_SEG2, scl_data->dscl_prog_data.easf_v_bf3_pwl_base_set2); - REG_UPDATE(DSCL_EASF_V_BF3_PWL_SEG2, + REG_SET_3(DSCL_EASF_V_BF3_PWL_SEG2, 0, + SCL_EASF_V_BF3_PWL_IN_SEG2, scl_data->dscl_prog_data.easf_v_bf3_pwl_in_set2, + SCL_EASF_V_BF3_PWL_BASE_SEG2, scl_data->dscl_prog_data.easf_v_bf3_pwl_base_set2, SCL_EASF_V_BF3_PWL_SLOPE_SEG2, scl_data->dscl_prog_data.easf_v_bf3_pwl_slope_set2); - REG_UPDATE(DSCL_EASF_V_BF3_PWL_SEG3, - SCL_EASF_V_BF3_PWL_IN_SEG3, scl_data->dscl_prog_data.easf_v_bf3_pwl_in_set3); - REG_UPDATE(DSCL_EASF_V_BF3_PWL_SEG3, - SCL_EASF_V_BF3_PWL_BASE_SEG3, scl_data->dscl_prog_data.easf_v_bf3_pwl_base_set3); - REG_UPDATE(DSCL_EASF_V_BF3_PWL_SEG3, + REG_SET_3(DSCL_EASF_V_BF3_PWL_SEG3, 0, + SCL_EASF_V_BF3_PWL_IN_SEG3, scl_data->dscl_prog_data.easf_v_bf3_pwl_in_set3, + SCL_EASF_V_BF3_PWL_BASE_SEG3, scl_data->dscl_prog_data.easf_v_bf3_pwl_base_set3, SCL_EASF_V_BF3_PWL_SLOPE_SEG3, scl_data->dscl_prog_data.easf_v_bf3_pwl_slope_set3); - REG_UPDATE(DSCL_EASF_V_BF3_PWL_SEG4, - SCL_EASF_V_BF3_PWL_IN_SEG4, scl_data->dscl_prog_data.easf_v_bf3_pwl_in_set4); - REG_UPDATE(DSCL_EASF_V_BF3_PWL_SEG4, - SCL_EASF_V_BF3_PWL_BASE_SEG4, scl_data->dscl_prog_data.easf_v_bf3_pwl_base_set4); - REG_UPDATE(DSCL_EASF_V_BF3_PWL_SEG4, + REG_SET_3(DSCL_EASF_V_BF3_PWL_SEG4, 0, + SCL_EASF_V_BF3_PWL_IN_SEG4, scl_data->dscl_prog_data.easf_v_bf3_pwl_in_set4, + SCL_EASF_V_BF3_PWL_BASE_SEG4, scl_data->dscl_prog_data.easf_v_bf3_pwl_base_set4, SCL_EASF_V_BF3_PWL_SLOPE_SEG4, scl_data->dscl_prog_data.easf_v_bf3_pwl_slope_set4); - REG_UPDATE(DSCL_EASF_V_BF3_PWL_SEG5, - SCL_EASF_V_BF3_PWL_IN_SEG5, scl_data->dscl_prog_data.easf_v_bf3_pwl_in_set5); - REG_UPDATE(DSCL_EASF_V_BF3_PWL_SEG5, + REG_SET_2(DSCL_EASF_V_BF3_PWL_SEG5, 0, + SCL_EASF_V_BF3_PWL_IN_SEG5, scl_data->dscl_prog_data.easf_v_bf3_pwl_in_set5, SCL_EASF_V_BF3_PWL_BASE_SEG5, scl_data->dscl_prog_data.easf_v_bf3_pwl_base_set5); + PERF_TRACE(); +} +/** + * dpp401_dscl_program_easf_h - Program EASF_H + * + * @dpp_base: High level DPP struct + * @scl_data: scalaer_data info + * + * This is the primary function to program horizontal EASF registers + * + */ +static void dpp401_dscl_program_easf_h(struct dpp *dpp_base, const struct scaler_data *scl_data) +{ + struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base); + + PERF_TRACE(); /* DSCL_EASF_H_MODE */ - REG_UPDATE(DSCL_EASF_H_MODE, - SCL_EASF_H_EN, scl_data->dscl_prog_data.easf_h_en); - REG_UPDATE(DSCL_EASF_H_MODE, - SCL_EASF_H_2TAP_SHARP_FACTOR, scl_data->dscl_prog_data.easf_h_sharp_factor); - REG_UPDATE(DSCL_EASF_H_MODE, + REG_SET_3(DSCL_EASF_H_MODE, 0, + SCL_EASF_H_EN, scl_data->dscl_prog_data.easf_h_en, + SCL_EASF_H_2TAP_SHARP_FACTOR, scl_data->dscl_prog_data.easf_h_sharp_factor, SCL_EASF_H_RINGEST_FORCE_EN, scl_data->dscl_prog_data.easf_h_ring); - REG_UPDATE(DSCL_EASF_H_BF_CNTL, - SCL_EASF_H_BF1_EN, scl_data->dscl_prog_data.easf_h_bf1_en); - REG_UPDATE(DSCL_EASF_H_BF_CNTL, - SCL_EASF_H_BF2_MODE, scl_data->dscl_prog_data.easf_h_bf2_mode); - REG_UPDATE(DSCL_EASF_H_BF_CNTL, - SCL_EASF_H_BF3_MODE, scl_data->dscl_prog_data.easf_h_bf3_mode); - REG_UPDATE(DSCL_EASF_H_BF_CNTL, - SCL_EASF_H_BF2_FLAT1_GAIN, scl_data->dscl_prog_data.easf_h_bf2_flat1_gain); - REG_UPDATE(DSCL_EASF_H_BF_CNTL, - SCL_EASF_H_BF2_FLAT2_GAIN, scl_data->dscl_prog_data.easf_h_bf2_flat2_gain); - REG_UPDATE(DSCL_EASF_H_BF_CNTL, + + if (!scl_data->dscl_prog_data.easf_h_en) { + PERF_TRACE(); + return; + } + + /* DSCL_EASF_H_BF_CNTL */ + REG_SET_6(DSCL_EASF_H_BF_CNTL, 0, + SCL_EASF_H_BF1_EN, scl_data->dscl_prog_data.easf_h_bf1_en, + SCL_EASF_H_BF2_MODE, scl_data->dscl_prog_data.easf_h_bf2_mode, + SCL_EASF_H_BF3_MODE, scl_data->dscl_prog_data.easf_h_bf3_mode, + SCL_EASF_H_BF2_FLAT1_GAIN, scl_data->dscl_prog_data.easf_h_bf2_flat1_gain, + SCL_EASF_H_BF2_FLAT2_GAIN, scl_data->dscl_prog_data.easf_h_bf2_flat2_gain, SCL_EASF_H_BF2_ROC_GAIN, scl_data->dscl_prog_data.easf_h_bf2_roc_gain); - REG_UPDATE(DSCL_EASF_H_RINGEST_EVENTAP_REDUCE, - SCL_EASF_H_RINGEST_EVENTAP_REDUCEG1, scl_data->dscl_prog_data.easf_h_ringest_eventap_reduceg1); - REG_UPDATE(DSCL_EASF_H_RINGEST_EVENTAP_REDUCE, + /* DSCL_EASF_H_RINGEST_EVENTAP_REDUCE */ + REG_SET_2(DSCL_EASF_H_RINGEST_EVENTAP_REDUCE, 0, + SCL_EASF_H_RINGEST_EVENTAP_REDUCEG1, scl_data->dscl_prog_data.easf_h_ringest_eventap_reduceg1, SCL_EASF_H_RINGEST_EVENTAP_REDUCEG2, scl_data->dscl_prog_data.easf_h_ringest_eventap_reduceg2); - REG_UPDATE(DSCL_EASF_H_RINGEST_EVENTAP_GAIN, - SCL_EASF_H_RINGEST_EVENTAP_GAIN1, scl_data->dscl_prog_data.easf_h_ringest_eventap_gain1); - REG_UPDATE(DSCL_EASF_H_RINGEST_EVENTAP_GAIN, + /* DSCL_EASF_H_RINGEST_EVENTAP_GAIN */ + REG_SET_2(DSCL_EASF_H_RINGEST_EVENTAP_GAIN, 0, + SCL_EASF_H_RINGEST_EVENTAP_GAIN1, scl_data->dscl_prog_data.easf_h_ringest_eventap_gain1, SCL_EASF_H_RINGEST_EVENTAP_GAIN2, scl_data->dscl_prog_data.easf_h_ringest_eventap_gain2); - REG_UPDATE(DSCL_EASF_H_BF_FINAL_MAX_MIN, - SCL_EASF_H_BF_MAXA, scl_data->dscl_prog_data.easf_h_bf_maxa); - REG_UPDATE(DSCL_EASF_H_BF_FINAL_MAX_MIN, - SCL_EASF_H_BF_MAXB, scl_data->dscl_prog_data.easf_h_bf_maxb); - REG_UPDATE(DSCL_EASF_H_BF_FINAL_MAX_MIN, - SCL_EASF_H_BF_MINA, scl_data->dscl_prog_data.easf_h_bf_mina); - REG_UPDATE(DSCL_EASF_H_BF_FINAL_MAX_MIN, + /* DSCL_EASF_H_BF_FINAL_MAX_MIN */ + REG_SET_4(DSCL_EASF_H_BF_FINAL_MAX_MIN, 0, + SCL_EASF_H_BF_MAXA, scl_data->dscl_prog_data.easf_h_bf_maxa, + SCL_EASF_H_BF_MAXB, scl_data->dscl_prog_data.easf_h_bf_maxb, + SCL_EASF_H_BF_MINA, scl_data->dscl_prog_data.easf_h_bf_mina, SCL_EASF_H_BF_MINB, scl_data->dscl_prog_data.easf_h_bf_minb); - REG_UPDATE(DSCL_EASF_H_BF1_PWL_SEG0, - SCL_EASF_H_BF1_PWL_IN_SEG0, scl_data->dscl_prog_data.easf_h_bf1_pwl_in_seg0); - REG_UPDATE(DSCL_EASF_H_BF1_PWL_SEG0, - SCL_EASF_H_BF1_PWL_BASE_SEG0, scl_data->dscl_prog_data.easf_h_bf1_pwl_base_seg0); - REG_UPDATE(DSCL_EASF_H_BF1_PWL_SEG0, + /* DSCL_EASF_H_BF1_PWL_SEGn */ + REG_SET_3(DSCL_EASF_H_BF1_PWL_SEG0, 0, + SCL_EASF_H_BF1_PWL_IN_SEG0, scl_data->dscl_prog_data.easf_h_bf1_pwl_in_seg0, + SCL_EASF_H_BF1_PWL_BASE_SEG0, scl_data->dscl_prog_data.easf_h_bf1_pwl_base_seg0, SCL_EASF_H_BF1_PWL_SLOPE_SEG0, scl_data->dscl_prog_data.easf_h_bf1_pwl_slope_seg0); - REG_UPDATE(DSCL_EASF_H_BF1_PWL_SEG1, - SCL_EASF_H_BF1_PWL_IN_SEG1, scl_data->dscl_prog_data.easf_h_bf1_pwl_in_seg1); - REG_UPDATE(DSCL_EASF_H_BF1_PWL_SEG1, - SCL_EASF_H_BF1_PWL_BASE_SEG1, scl_data->dscl_prog_data.easf_h_bf1_pwl_base_seg1); - REG_UPDATE(DSCL_EASF_H_BF1_PWL_SEG1, + REG_SET_3(DSCL_EASF_H_BF1_PWL_SEG1, 0, + SCL_EASF_H_BF1_PWL_IN_SEG1, scl_data->dscl_prog_data.easf_h_bf1_pwl_in_seg1, + SCL_EASF_H_BF1_PWL_BASE_SEG1, scl_data->dscl_prog_data.easf_h_bf1_pwl_base_seg1, SCL_EASF_H_BF1_PWL_SLOPE_SEG1, scl_data->dscl_prog_data.easf_h_bf1_pwl_slope_seg1); - REG_UPDATE(DSCL_EASF_H_BF1_PWL_SEG2, - SCL_EASF_H_BF1_PWL_IN_SEG2, scl_data->dscl_prog_data.easf_h_bf1_pwl_in_seg2); - REG_UPDATE(DSCL_EASF_H_BF1_PWL_SEG2, - SCL_EASF_H_BF1_PWL_BASE_SEG2, scl_data->dscl_prog_data.easf_h_bf1_pwl_base_seg2); - REG_UPDATE(DSCL_EASF_H_BF1_PWL_SEG2, + REG_SET_3(DSCL_EASF_H_BF1_PWL_SEG2, 0, + SCL_EASF_H_BF1_PWL_IN_SEG2, scl_data->dscl_prog_data.easf_h_bf1_pwl_in_seg2, + SCL_EASF_H_BF1_PWL_BASE_SEG2, scl_data->dscl_prog_data.easf_h_bf1_pwl_base_seg2, SCL_EASF_H_BF1_PWL_SLOPE_SEG2, scl_data->dscl_prog_data.easf_h_bf1_pwl_slope_seg2); - REG_UPDATE(DSCL_EASF_H_BF1_PWL_SEG3, - SCL_EASF_H_BF1_PWL_IN_SEG3, scl_data->dscl_prog_data.easf_h_bf1_pwl_in_seg3); - REG_UPDATE(DSCL_EASF_H_BF1_PWL_SEG3, - SCL_EASF_H_BF1_PWL_BASE_SEG3, scl_data->dscl_prog_data.easf_h_bf1_pwl_base_seg3); - REG_UPDATE(DSCL_EASF_H_BF1_PWL_SEG3, + REG_SET_3(DSCL_EASF_H_BF1_PWL_SEG3, 0, + SCL_EASF_H_BF1_PWL_IN_SEG3, scl_data->dscl_prog_data.easf_h_bf1_pwl_in_seg3, + SCL_EASF_H_BF1_PWL_BASE_SEG3, scl_data->dscl_prog_data.easf_h_bf1_pwl_base_seg3, SCL_EASF_H_BF1_PWL_SLOPE_SEG3, scl_data->dscl_prog_data.easf_h_bf1_pwl_slope_seg3); - REG_UPDATE(DSCL_EASF_H_BF1_PWL_SEG4, - SCL_EASF_H_BF1_PWL_IN_SEG4, scl_data->dscl_prog_data.easf_h_bf1_pwl_in_seg4); - REG_UPDATE(DSCL_EASF_H_BF1_PWL_SEG4, - SCL_EASF_H_BF1_PWL_BASE_SEG4, scl_data->dscl_prog_data.easf_h_bf1_pwl_base_seg4); - REG_UPDATE(DSCL_EASF_H_BF1_PWL_SEG4, + REG_SET_3(DSCL_EASF_H_BF1_PWL_SEG4, 0, + SCL_EASF_H_BF1_PWL_IN_SEG4, scl_data->dscl_prog_data.easf_h_bf1_pwl_in_seg4, + SCL_EASF_H_BF1_PWL_BASE_SEG4, scl_data->dscl_prog_data.easf_h_bf1_pwl_base_seg4, SCL_EASF_H_BF1_PWL_SLOPE_SEG4, scl_data->dscl_prog_data.easf_h_bf1_pwl_slope_seg4); - REG_UPDATE(DSCL_EASF_H_BF1_PWL_SEG5, - SCL_EASF_H_BF1_PWL_IN_SEG5, scl_data->dscl_prog_data.easf_h_bf1_pwl_in_seg5); - REG_UPDATE(DSCL_EASF_H_BF1_PWL_SEG5, - SCL_EASF_H_BF1_PWL_BASE_SEG5, scl_data->dscl_prog_data.easf_h_bf1_pwl_base_seg5); - REG_UPDATE(DSCL_EASF_H_BF1_PWL_SEG5, + REG_SET_3(DSCL_EASF_H_BF1_PWL_SEG5, 0, + SCL_EASF_H_BF1_PWL_IN_SEG5, scl_data->dscl_prog_data.easf_h_bf1_pwl_in_seg5, + SCL_EASF_H_BF1_PWL_BASE_SEG5, scl_data->dscl_prog_data.easf_h_bf1_pwl_base_seg5, SCL_EASF_H_BF1_PWL_SLOPE_SEG5, scl_data->dscl_prog_data.easf_h_bf1_pwl_slope_seg5); - REG_UPDATE(DSCL_EASF_H_BF1_PWL_SEG6, - SCL_EASF_H_BF1_PWL_IN_SEG6, scl_data->dscl_prog_data.easf_h_bf1_pwl_in_seg6); - REG_UPDATE(DSCL_EASF_H_BF1_PWL_SEG6, - SCL_EASF_H_BF1_PWL_BASE_SEG6, scl_data->dscl_prog_data.easf_h_bf1_pwl_base_seg6); - REG_UPDATE(DSCL_EASF_H_BF1_PWL_SEG6, + REG_SET_3(DSCL_EASF_H_BF1_PWL_SEG6, 0, + SCL_EASF_H_BF1_PWL_IN_SEG6, scl_data->dscl_prog_data.easf_h_bf1_pwl_in_seg6, + SCL_EASF_H_BF1_PWL_BASE_SEG6, scl_data->dscl_prog_data.easf_h_bf1_pwl_base_seg6, SCL_EASF_H_BF1_PWL_SLOPE_SEG6, scl_data->dscl_prog_data.easf_h_bf1_pwl_slope_seg6); - REG_UPDATE(DSCL_EASF_H_BF1_PWL_SEG7, - SCL_EASF_H_BF1_PWL_IN_SEG7, scl_data->dscl_prog_data.easf_h_bf1_pwl_in_seg7); - REG_UPDATE(DSCL_EASF_H_BF1_PWL_SEG7, + REG_SET_2(DSCL_EASF_H_BF1_PWL_SEG7, 0, + SCL_EASF_H_BF1_PWL_IN_SEG7, scl_data->dscl_prog_data.easf_h_bf1_pwl_in_seg7, SCL_EASF_H_BF1_PWL_BASE_SEG7, scl_data->dscl_prog_data.easf_h_bf1_pwl_base_seg7); - REG_UPDATE(DSCL_EASF_H_BF3_PWL_SEG0, - SCL_EASF_H_BF3_PWL_IN_SEG0, scl_data->dscl_prog_data.easf_h_bf3_pwl_in_set0); - REG_UPDATE(DSCL_EASF_H_BF3_PWL_SEG0, - SCL_EASF_H_BF3_PWL_BASE_SEG0, scl_data->dscl_prog_data.easf_h_bf3_pwl_base_set0); - REG_UPDATE(DSCL_EASF_H_BF3_PWL_SEG0, + /* DSCL_EASF_H_BF3_PWL_SEGn */ + REG_SET_3(DSCL_EASF_H_BF3_PWL_SEG0, 0, + SCL_EASF_H_BF3_PWL_IN_SEG0, scl_data->dscl_prog_data.easf_h_bf3_pwl_in_set0, + SCL_EASF_H_BF3_PWL_BASE_SEG0, scl_data->dscl_prog_data.easf_h_bf3_pwl_base_set0, SCL_EASF_H_BF3_PWL_SLOPE_SEG0, scl_data->dscl_prog_data.easf_h_bf3_pwl_slope_set0); - REG_UPDATE(DSCL_EASF_H_BF3_PWL_SEG1, - SCL_EASF_H_BF3_PWL_IN_SEG1, scl_data->dscl_prog_data.easf_h_bf3_pwl_in_set1); - REG_UPDATE(DSCL_EASF_H_BF3_PWL_SEG1, - SCL_EASF_H_BF3_PWL_BASE_SEG1, scl_data->dscl_prog_data.easf_h_bf3_pwl_base_set1); - REG_UPDATE(DSCL_EASF_H_BF3_PWL_SEG1, + REG_SET_3(DSCL_EASF_H_BF3_PWL_SEG1, 0, + SCL_EASF_H_BF3_PWL_IN_SEG1, scl_data->dscl_prog_data.easf_h_bf3_pwl_in_set1, + SCL_EASF_H_BF3_PWL_BASE_SEG1, scl_data->dscl_prog_data.easf_h_bf3_pwl_base_set1, SCL_EASF_H_BF3_PWL_SLOPE_SEG1, scl_data->dscl_prog_data.easf_h_bf3_pwl_slope_set1); - REG_UPDATE(DSCL_EASF_H_BF3_PWL_SEG2, - SCL_EASF_H_BF3_PWL_IN_SEG2, scl_data->dscl_prog_data.easf_h_bf3_pwl_in_set2); - REG_UPDATE(DSCL_EASF_H_BF3_PWL_SEG2, - SCL_EASF_H_BF3_PWL_BASE_SEG2, scl_data->dscl_prog_data.easf_h_bf3_pwl_base_set2); - REG_UPDATE(DSCL_EASF_H_BF3_PWL_SEG2, + REG_SET_3(DSCL_EASF_H_BF3_PWL_SEG2, 0, + SCL_EASF_H_BF3_PWL_IN_SEG2, scl_data->dscl_prog_data.easf_h_bf3_pwl_in_set2, + SCL_EASF_H_BF3_PWL_BASE_SEG2, scl_data->dscl_prog_data.easf_h_bf3_pwl_base_set2, SCL_EASF_H_BF3_PWL_SLOPE_SEG2, scl_data->dscl_prog_data.easf_h_bf3_pwl_slope_set2); - REG_UPDATE(DSCL_EASF_H_BF3_PWL_SEG3, - SCL_EASF_H_BF3_PWL_IN_SEG3, scl_data->dscl_prog_data.easf_h_bf3_pwl_in_set3); - REG_UPDATE(DSCL_EASF_H_BF3_PWL_SEG3, - SCL_EASF_H_BF3_PWL_BASE_SEG3, scl_data->dscl_prog_data.easf_h_bf3_pwl_base_set3); - REG_UPDATE(DSCL_EASF_H_BF3_PWL_SEG3, + REG_SET_3(DSCL_EASF_H_BF3_PWL_SEG3, 0, + SCL_EASF_H_BF3_PWL_IN_SEG3, scl_data->dscl_prog_data.easf_h_bf3_pwl_in_set3, + SCL_EASF_H_BF3_PWL_BASE_SEG3, scl_data->dscl_prog_data.easf_h_bf3_pwl_base_set3, SCL_EASF_H_BF3_PWL_SLOPE_SEG3, scl_data->dscl_prog_data.easf_h_bf3_pwl_slope_set3); - REG_UPDATE(DSCL_EASF_H_BF3_PWL_SEG4, - SCL_EASF_H_BF3_PWL_IN_SEG4, scl_data->dscl_prog_data.easf_h_bf3_pwl_in_set4); - REG_UPDATE(DSCL_EASF_H_BF3_PWL_SEG4, - SCL_EASF_H_BF3_PWL_BASE_SEG4, scl_data->dscl_prog_data.easf_h_bf3_pwl_base_set4); - REG_UPDATE(DSCL_EASF_H_BF3_PWL_SEG4, + REG_SET_3(DSCL_EASF_H_BF3_PWL_SEG4, 0, + SCL_EASF_H_BF3_PWL_IN_SEG4, scl_data->dscl_prog_data.easf_h_bf3_pwl_in_set4, + SCL_EASF_H_BF3_PWL_BASE_SEG4, scl_data->dscl_prog_data.easf_h_bf3_pwl_base_set4, SCL_EASF_H_BF3_PWL_SLOPE_SEG4, scl_data->dscl_prog_data.easf_h_bf3_pwl_slope_set4); - REG_UPDATE(DSCL_EASF_H_BF3_PWL_SEG5, - SCL_EASF_H_BF3_PWL_IN_SEG5, scl_data->dscl_prog_data.easf_h_bf3_pwl_in_set5); - REG_UPDATE(DSCL_EASF_H_BF3_PWL_SEG5, + REG_SET_2(DSCL_EASF_H_BF3_PWL_SEG5, 0, + SCL_EASF_H_BF3_PWL_IN_SEG5, scl_data->dscl_prog_data.easf_h_bf3_pwl_in_set5, SCL_EASF_H_BF3_PWL_BASE_SEG5, scl_data->dscl_prog_data.easf_h_bf3_pwl_base_set5); + PERF_TRACE(); +} +/** + * dpp401_dscl_program_easf - Program EASF + * + * @dpp_base: High level DPP struct + * @scl_data: scalaer_data info + * + * This is the primary function to program EASF + * + */ +static void dpp401_dscl_program_easf(struct dpp *dpp_base, const struct scaler_data *scl_data) +{ + struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base); + + PERF_TRACE(); + /* DSCL_SC_MODE */ + REG_SET_2(DSCL_SC_MODE, 0, + SCL_SC_MATRIX_MODE, scl_data->dscl_prog_data.easf_matrix_mode, + SCL_SC_LTONL_EN, scl_data->dscl_prog_data.easf_ltonl_en); /* DSCL_EASF_SC_MATRIX_C0C1, DSCL_EASF_SC_MATRIX_C2C3 */ - REG_UPDATE(DSCL_SC_MATRIX_C0C1, - SCL_SC_MATRIX_C0, scl_data->dscl_prog_data.easf_matrix_c0); - REG_UPDATE(DSCL_SC_MATRIX_C0C1, + REG_SET_2(DSCL_SC_MATRIX_C0C1, 0, + SCL_SC_MATRIX_C0, scl_data->dscl_prog_data.easf_matrix_c0, SCL_SC_MATRIX_C1, scl_data->dscl_prog_data.easf_matrix_c1); - REG_UPDATE(DSCL_SC_MATRIX_C2C3, - SCL_SC_MATRIX_C2, scl_data->dscl_prog_data.easf_matrix_c2); - REG_UPDATE(DSCL_SC_MATRIX_C2C3, + REG_SET_2(DSCL_SC_MATRIX_C2C3, 0, + SCL_SC_MATRIX_C2, scl_data->dscl_prog_data.easf_matrix_c2, SCL_SC_MATRIX_C3, scl_data->dscl_prog_data.easf_matrix_c3); + dpp401_dscl_program_easf_v(dpp_base, scl_data); + dpp401_dscl_program_easf_h(dpp_base, scl_data); PERF_TRACE(); } /** @@ -958,10 +937,11 @@ static void dpp401_dscl_set_isharp_filter( REG_UPDATE(ISHARP_DELTA_CTRL, ISHARP_DELTA_LUT_HOST_SELECT, 0); + /* LUT data write is auto-indexed. Write index once */ + REG_SET(ISHARP_DELTA_INDEX, 0, + ISHARP_DELTA_INDEX, 0); for (level = 0; level < NUM_LEVELS; level++) { filter_data = filter[level]; - REG_SET(ISHARP_DELTA_INDEX, 0, - ISHARP_DELTA_INDEX, level); REG_SET(ISHARP_DELTA_DATA, 0, ISHARP_DELTA_DATA, filter_data); } @@ -976,107 +956,74 @@ static void dpp401_dscl_set_isharp_filter( * */ static void dpp401_dscl_program_isharp(struct dpp *dpp_base, - const struct scaler_data *scl_data) + const struct scaler_data *scl_data, + bool *bs_coeffs_updated) { struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base); + *bs_coeffs_updated = false; PERF_TRACE(); - /* ISHARP_EN */ - REG_UPDATE(ISHARP_MODE, - ISHARP_EN, scl_data->dscl_prog_data.isharp_en); - /* ISHARP_NOISEDET_EN */ - REG_UPDATE(ISHARP_MODE, - ISHARP_NOISEDET_EN, scl_data->dscl_prog_data.isharp_noise_det.enable); - /* ISHARP_NOISEDET_MODE */ - REG_UPDATE(ISHARP_MODE, - ISHARP_NOISEDET_MODE, scl_data->dscl_prog_data.isharp_noise_det.mode); - /* ISHARP_NOISEDET_UTHRE */ - REG_UPDATE(ISHARP_NOISEDET_THRESHOLD, - ISHARP_NOISEDET_UTHRE, scl_data->dscl_prog_data.isharp_noise_det.uthreshold); - /* ISHARP_NOISEDET_DTHRE */ - REG_UPDATE(ISHARP_NOISEDET_THRESHOLD, - ISHARP_NOISEDET_DTHRE, scl_data->dscl_prog_data.isharp_noise_det.dthreshold); - REG_UPDATE(ISHARP_MODE, - ISHARP_NOISEDET_MODE, scl_data->dscl_prog_data.isharp_noise_det.mode); - /* ISHARP_NOISEDET_UTHRE */ - REG_UPDATE(ISHARP_NOISEDET_THRESHOLD, - ISHARP_NOISEDET_UTHRE, scl_data->dscl_prog_data.isharp_noise_det.uthreshold); - /* ISHARP_NOISEDET_DTHRE */ - REG_UPDATE(ISHARP_NOISEDET_THRESHOLD, + /* ISHARP_MODE */ + REG_SET_6(ISHARP_MODE, 0, + ISHARP_EN, scl_data->dscl_prog_data.isharp_en, + ISHARP_NOISEDET_EN, scl_data->dscl_prog_data.isharp_noise_det.enable, + ISHARP_NOISEDET_MODE, scl_data->dscl_prog_data.isharp_noise_det.mode, + ISHARP_LBA_MODE, scl_data->dscl_prog_data.isharp_lba.mode, + ISHARP_FMT_MODE, scl_data->dscl_prog_data.isharp_fmt.mode, + ISHARP_FMT_NORM, scl_data->dscl_prog_data.isharp_fmt.norm); + + /* Skip remaining register programming if ISHARP is disabled */ + if (!scl_data->dscl_prog_data.isharp_en) { + PERF_TRACE(); + return; + } + + /* ISHARP_NOISEDET_THRESHOLD */ + REG_SET_2(ISHARP_NOISEDET_THRESHOLD, 0, + ISHARP_NOISEDET_UTHRE, scl_data->dscl_prog_data.isharp_noise_det.uthreshold, ISHARP_NOISEDET_DTHRE, scl_data->dscl_prog_data.isharp_noise_det.dthreshold); - /* ISHARP_NOISEDET_PWL_START_IN */ - REG_UPDATE(ISHARP_NOISE_GAIN_PWL, - ISHARP_NOISEDET_PWL_START_IN, scl_data->dscl_prog_data.isharp_noise_det.pwl_start_in); - /* ISHARP_NOISEDET_PWL_END_IN */ - REG_UPDATE(ISHARP_NOISE_GAIN_PWL, - ISHARP_NOISEDET_PWL_END_IN, scl_data->dscl_prog_data.isharp_noise_det.pwl_end_in); - /* ISHARP_NOISEDET_PWL_SLOPE */ - REG_UPDATE(ISHARP_NOISE_GAIN_PWL, + + /* ISHARP_NOISE_GAIN_PWL */ + REG_SET_3(ISHARP_NOISE_GAIN_PWL, 0, + ISHARP_NOISEDET_PWL_START_IN, scl_data->dscl_prog_data.isharp_noise_det.pwl_start_in, + ISHARP_NOISEDET_PWL_END_IN, scl_data->dscl_prog_data.isharp_noise_det.pwl_end_in, ISHARP_NOISEDET_PWL_SLOPE, scl_data->dscl_prog_data.isharp_noise_det.pwl_slope); - /* ISHARP_LBA_MODE */ - REG_UPDATE(ISHARP_MODE, - ISHARP_LBA_MODE, scl_data->dscl_prog_data.isharp_lba.mode); + /* ISHARP_LBA: IN_SEG, BASE_SEG, SLOPE_SEG */ - REG_UPDATE(ISHARP_LBA_PWL_SEG0, - ISHARP_LBA_PWL_IN_SEG0, scl_data->dscl_prog_data.isharp_lba.in_seg[0]); - REG_UPDATE(ISHARP_LBA_PWL_SEG0, - ISHARP_LBA_PWL_BASE_SEG0, scl_data->dscl_prog_data.isharp_lba.base_seg[0]); - REG_UPDATE(ISHARP_LBA_PWL_SEG0, + REG_SET_3(ISHARP_LBA_PWL_SEG0, 0, + ISHARP_LBA_PWL_IN_SEG0, scl_data->dscl_prog_data.isharp_lba.in_seg[0], + ISHARP_LBA_PWL_BASE_SEG0, scl_data->dscl_prog_data.isharp_lba.base_seg[0], ISHARP_LBA_PWL_SLOPE_SEG0, scl_data->dscl_prog_data.isharp_lba.slope_seg[0]); - REG_UPDATE(ISHARP_LBA_PWL_SEG1, - ISHARP_LBA_PWL_IN_SEG1, scl_data->dscl_prog_data.isharp_lba.in_seg[1]); - REG_UPDATE(ISHARP_LBA_PWL_SEG1, - ISHARP_LBA_PWL_BASE_SEG1, scl_data->dscl_prog_data.isharp_lba.base_seg[1]); - REG_UPDATE(ISHARP_LBA_PWL_SEG1, + REG_SET_3(ISHARP_LBA_PWL_SEG1, 0, + ISHARP_LBA_PWL_IN_SEG1, scl_data->dscl_prog_data.isharp_lba.in_seg[1], + ISHARP_LBA_PWL_BASE_SEG1, scl_data->dscl_prog_data.isharp_lba.base_seg[1], ISHARP_LBA_PWL_SLOPE_SEG1, scl_data->dscl_prog_data.isharp_lba.slope_seg[1]); - REG_UPDATE(ISHARP_LBA_PWL_SEG2, - ISHARP_LBA_PWL_IN_SEG2, scl_data->dscl_prog_data.isharp_lba.in_seg[2]); - REG_UPDATE(ISHARP_LBA_PWL_SEG2, - ISHARP_LBA_PWL_BASE_SEG2, scl_data->dscl_prog_data.isharp_lba.base_seg[2]); - REG_UPDATE(ISHARP_LBA_PWL_SEG2, + REG_SET_3(ISHARP_LBA_PWL_SEG2, 0, + ISHARP_LBA_PWL_IN_SEG2, scl_data->dscl_prog_data.isharp_lba.in_seg[2], + ISHARP_LBA_PWL_BASE_SEG2, scl_data->dscl_prog_data.isharp_lba.base_seg[2], ISHARP_LBA_PWL_SLOPE_SEG2, scl_data->dscl_prog_data.isharp_lba.slope_seg[2]); - REG_UPDATE(ISHARP_LBA_PWL_SEG3, - ISHARP_LBA_PWL_IN_SEG3, scl_data->dscl_prog_data.isharp_lba.in_seg[3]); - REG_UPDATE(ISHARP_LBA_PWL_SEG3, - ISHARP_LBA_PWL_BASE_SEG3, scl_data->dscl_prog_data.isharp_lba.base_seg[3]); - REG_UPDATE(ISHARP_LBA_PWL_SEG3, + REG_SET_3(ISHARP_LBA_PWL_SEG3, 0, + ISHARP_LBA_PWL_IN_SEG3, scl_data->dscl_prog_data.isharp_lba.in_seg[3], + ISHARP_LBA_PWL_BASE_SEG3, scl_data->dscl_prog_data.isharp_lba.base_seg[3], ISHARP_LBA_PWL_SLOPE_SEG3, scl_data->dscl_prog_data.isharp_lba.slope_seg[3]); - REG_UPDATE(ISHARP_LBA_PWL_SEG4, - ISHARP_LBA_PWL_IN_SEG4, scl_data->dscl_prog_data.isharp_lba.in_seg[4]); - REG_UPDATE(ISHARP_LBA_PWL_SEG4, - ISHARP_LBA_PWL_BASE_SEG4, scl_data->dscl_prog_data.isharp_lba.base_seg[4]); - REG_UPDATE(ISHARP_LBA_PWL_SEG4, + REG_SET_3(ISHARP_LBA_PWL_SEG4, 0, + ISHARP_LBA_PWL_IN_SEG4, scl_data->dscl_prog_data.isharp_lba.in_seg[4], + ISHARP_LBA_PWL_BASE_SEG4, scl_data->dscl_prog_data.isharp_lba.base_seg[4], ISHARP_LBA_PWL_SLOPE_SEG4, scl_data->dscl_prog_data.isharp_lba.slope_seg[4]); - REG_UPDATE(ISHARP_LBA_PWL_SEG5, - ISHARP_LBA_PWL_IN_SEG5, scl_data->dscl_prog_data.isharp_lba.in_seg[5]); - REG_UPDATE(ISHARP_LBA_PWL_SEG5, + REG_SET_2(ISHARP_LBA_PWL_SEG5, 0, + ISHARP_LBA_PWL_IN_SEG5, scl_data->dscl_prog_data.isharp_lba.in_seg[5], ISHARP_LBA_PWL_BASE_SEG5, scl_data->dscl_prog_data.isharp_lba.base_seg[5]); - /* ISHARP_FMT_MODE */ - REG_UPDATE(ISHARP_MODE, - ISHARP_FMT_MODE, scl_data->dscl_prog_data.isharp_fmt.mode); - /* ISHARP_FMT_NORM */ - REG_UPDATE(ISHARP_MODE, - ISHARP_FMT_NORM, scl_data->dscl_prog_data.isharp_fmt.norm); /* ISHARP_DELTA_LUT */ dpp401_dscl_set_isharp_filter(dpp, scl_data->dscl_prog_data.isharp_delta); - /* ISHARP_NLDELTA_SCLIP_EN_P */ - REG_UPDATE(ISHARP_NLDELTA_SOFT_CLIP, - ISHARP_NLDELTA_SCLIP_EN_P, scl_data->dscl_prog_data.isharp_nldelta_sclip.enable_p); - /* ISHARP_NLDELTA_SCLIP_PIVOT_P */ - REG_UPDATE(ISHARP_NLDELTA_SOFT_CLIP, - ISHARP_NLDELTA_SCLIP_PIVOT_P, scl_data->dscl_prog_data.isharp_nldelta_sclip.pivot_p); - /* ISHARP_NLDELTA_SCLIP_SLOPE_P */ - REG_UPDATE(ISHARP_NLDELTA_SOFT_CLIP, - ISHARP_NLDELTA_SCLIP_SLOPE_P, scl_data->dscl_prog_data.isharp_nldelta_sclip.slope_p); - /* ISHARP_NLDELTA_SCLIP_EN_N */ - REG_UPDATE(ISHARP_NLDELTA_SOFT_CLIP, - ISHARP_NLDELTA_SCLIP_EN_N, scl_data->dscl_prog_data.isharp_nldelta_sclip.enable_n); - /* ISHARP_NLDELTA_SCLIP_PIVOT_N */ - REG_UPDATE(ISHARP_NLDELTA_SOFT_CLIP, - ISHARP_NLDELTA_SCLIP_PIVOT_N, scl_data->dscl_prog_data.isharp_nldelta_sclip.pivot_n); - /* ISHARP_NLDELTA_SCLIP_SLOPE_N */ - REG_UPDATE(ISHARP_NLDELTA_SOFT_CLIP, + + /* ISHARP_NLDELTA_SOFT_CLIP */ + REG_SET_6(ISHARP_NLDELTA_SOFT_CLIP, 0, + ISHARP_NLDELTA_SCLIP_EN_P, scl_data->dscl_prog_data.isharp_nldelta_sclip.enable_p, + ISHARP_NLDELTA_SCLIP_PIVOT_P, scl_data->dscl_prog_data.isharp_nldelta_sclip.pivot_p, + ISHARP_NLDELTA_SCLIP_SLOPE_P, scl_data->dscl_prog_data.isharp_nldelta_sclip.slope_p, + ISHARP_NLDELTA_SCLIP_EN_N, scl_data->dscl_prog_data.isharp_nldelta_sclip.enable_n, + ISHARP_NLDELTA_SCLIP_PIVOT_N, scl_data->dscl_prog_data.isharp_nldelta_sclip.pivot_n, ISHARP_NLDELTA_SCLIP_SLOPE_N, scl_data->dscl_prog_data.isharp_nldelta_sclip.slope_n); /* Blur and Scale Coefficients - SCL_COEF_RAM_TAP_SELECT */ @@ -1086,12 +1033,14 @@ static void dpp401_dscl_program_isharp(struct dpp *dpp_base, dpp, scl_data->taps.v_taps, SCL_COEF_VERTICAL_BLUR_SCALE, scl_data->dscl_prog_data.filter_blur_scale_v); + *bs_coeffs_updated = true; } if (scl_data->dscl_prog_data.filter_blur_scale_h) { dpp401_dscl_set_scaler_filter( dpp, scl_data->taps.h_taps, SCL_COEF_HORIZONTAL_BLUR_SCALE, scl_data->dscl_prog_data.filter_blur_scale_h); + *bs_coeffs_updated = true; } } PERF_TRACE(); @@ -1122,6 +1071,7 @@ void dpp401_dscl_set_scaler_manual_scale(struct dpp *dpp_base, dpp_base, scl_data, dpp_base->ctx->dc->debug.always_scale); bool ycbcr = scl_data->format >= PIXEL_FORMAT_VIDEO_BEGIN && scl_data->format <= PIXEL_FORMAT_VIDEO_END; + bool bs_coeffs_updated = false; if (memcmp(&dpp->scl_data, scl_data, sizeof(*scl_data)) == 0) return; @@ -1181,7 +1131,7 @@ void dpp401_dscl_set_scaler_manual_scale(struct dpp *dpp_base, if (dscl_mode == DSCL_MODE_SCALING_444_BYPASS) { if (dpp->base.ctx->dc->config.prefer_easf) dpp401_dscl_disable_easf(dpp_base, scl_data); - dpp401_dscl_program_isharp(dpp_base, scl_data); + dpp401_dscl_program_isharp(dpp_base, scl_data, &bs_coeffs_updated); return; } @@ -1208,12 +1158,18 @@ void dpp401_dscl_set_scaler_manual_scale(struct dpp *dpp_base, SCL_V_NUM_TAPS_C, v_num_taps_c, SCL_H_NUM_TAPS_C, h_num_taps_c); - dpp401_dscl_set_scl_filter(dpp, scl_data, ycbcr); + /* ISharp configuration + * - B&S coeffs are written to same coeff RAM as WB scaler coeffs + * - coeff RAM toggle is in EASF programming + * - if we are only programming B&S coeffs, then need to reprogram + * WB scaler coeffs and toggle coeff RAM together + */ + //if (dpp->base.ctx->dc->config.prefer_easf) + dpp401_dscl_program_isharp(dpp_base, scl_data, &bs_coeffs_updated); + + dpp401_dscl_set_scl_filter(dpp, scl_data, ycbcr, bs_coeffs_updated); /* Edge adaptive scaler function configuration */ if (dpp->base.ctx->dc->config.prefer_easf) dpp401_dscl_program_easf(dpp_base, scl_data); - /* isharp configuration */ - //if (dpp->base.ctx->dc->config.prefer_easf) - dpp401_dscl_program_isharp(dpp_base, scl_data); PERF_TRACE(); } diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c index 02e63b95c36d3..9d56fbdcd06af 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c @@ -76,6 +76,9 @@ #include "dml2/dml2_wrapper.h" +#include "spl/dc_spl_scl_easf_filters.h" +#include "spl/dc_spl_isharp_filters.h" + #define DC_LOGGER_INIT(logger) enum dcn401_clk_src_array_id { @@ -2126,6 +2129,10 @@ static bool dcn401_resource_construct( dc->dml2_options.max_segments_per_hubp = 20; dc->dml2_options.det_segment_size = DCN4_01_CRB_SEGMENT_SIZE_KB; + /* SPL */ + spl_init_easf_filter_coeffs(); + spl_init_blur_scale_coeffs(); + return true; create_fail: diff --git a/drivers/gpu/drm/amd/display/dc/spl/Makefile b/drivers/gpu/drm/amd/display/dc/spl/Makefile index f8df85ea4d327..05764d4d4604b 100644 --- a/drivers/gpu/drm/amd/display/dc/spl/Makefile +++ b/drivers/gpu/drm/amd/display/dc/spl/Makefile @@ -23,7 +23,7 @@ # Makefile for the 'spl' sub-component of DAL. # It provides the scaling library interface. -SPL = dc_spl.o dc_spl_scl_filters.o dc_spl_scl_filters_old.o dc_spl_isharp_filters.o +SPL = dc_spl.o dc_spl_scl_filters.o dc_spl_scl_easf_filters.o dc_spl_isharp_filters.o dc_spl_filters.o spl_fixpt31_32.o AMD_DAL_SPL = $(addprefix $(AMDDALPATH)/dc/spl/,$(SPL)) diff --git a/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c b/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c index 9eccdb38bed48..f00bb2004d537 100644 --- a/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c +++ b/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c @@ -4,9 +4,11 @@ #include "dc_spl.h" #include "dc_spl_scl_filters.h" +#include "dc_spl_scl_easf_filters.h" #include "dc_spl_isharp_filters.h" +#include "spl_debug.h" -#define IDENTITY_RATIO(ratio) (dc_fixpt_u2d19(ratio) == (1 << 19)) +#define IDENTITY_RATIO(ratio) (spl_fixpt_u2d19(ratio) == (1 << 19)) #define MIN_VIEWPORT_SIZE 12 static struct spl_rect intersect_rec(const struct spl_rect *r0, const struct spl_rect *r1) @@ -107,26 +109,26 @@ static struct spl_rect calculate_plane_rec_in_timing_active( const struct spl_rect *stream_src = &spl_in->basic_out.src_rect; const struct spl_rect *stream_dst = &spl_in->basic_out.dst_rect; struct spl_rect rec_out = {0}; - struct fixed31_32 temp; + struct spl_fixed31_32 temp; - temp = dc_fixpt_from_fraction(rec_in->x * (long long)stream_dst->width, + temp = spl_fixpt_from_fraction(rec_in->x * (long long)stream_dst->width, stream_src->width); - rec_out.x = stream_dst->x + dc_fixpt_round(temp); + rec_out.x = stream_dst->x + spl_fixpt_round(temp); - temp = dc_fixpt_from_fraction( + temp = spl_fixpt_from_fraction( (rec_in->x + rec_in->width) * (long long)stream_dst->width, stream_src->width); - rec_out.width = stream_dst->x + dc_fixpt_round(temp) - rec_out.x; + rec_out.width = stream_dst->x + spl_fixpt_round(temp) - rec_out.x; - temp = dc_fixpt_from_fraction(rec_in->y * (long long)stream_dst->height, + temp = spl_fixpt_from_fraction(rec_in->y * (long long)stream_dst->height, stream_src->height); - rec_out.y = stream_dst->y + dc_fixpt_round(temp); + rec_out.y = stream_dst->y + spl_fixpt_round(temp); - temp = dc_fixpt_from_fraction( + temp = spl_fixpt_from_fraction( (rec_in->y + rec_in->height) * (long long)stream_dst->height, stream_src->height); - rec_out.height = stream_dst->y + dc_fixpt_round(temp) - rec_out.y; + rec_out.height = stream_dst->y + spl_fixpt_round(temp) - rec_out.y; return rec_out; } @@ -144,7 +146,7 @@ static struct spl_rect calculate_mpc_slice_in_timing_active( mpc_rec.x = plane_clip_rec->x + mpc_rec.width * mpc_slice_idx; mpc_rec.height = plane_clip_rec->height; mpc_rec.y = plane_clip_rec->y; - ASSERT(mpc_slice_count == 1 || + SPL_ASSERT(mpc_slice_count == 1 || spl_in->basic_out.view_format != SPL_VIEW_3D_SIDE_BY_SIDE || mpc_rec.width % 2 == 0); @@ -157,7 +159,7 @@ static struct spl_rect calculate_mpc_slice_in_timing_active( } if (spl_in->basic_out.view_format == SPL_VIEW_3D_TOP_AND_BOTTOM) { - ASSERT(mpc_rec.height % 2 == 0); + SPL_ASSERT(mpc_rec.height % 2 == 0); mpc_rec.height /= 2; } return mpc_rec; @@ -197,7 +199,7 @@ static struct spl_rect calculate_odm_slice_in_timing_active(struct spl_in *spl_i return spl_in->basic_out.odm_slice_rect; } -static void spl_calculate_recout(struct spl_in *spl_in, struct spl_out *spl_out) +static void spl_calculate_recout(struct spl_in *spl_in, struct spl_scratch *spl_scratch, struct spl_out *spl_out) { /* * A plane clip represents the desired plane size and position in Stream @@ -340,20 +342,23 @@ static void spl_calculate_recout(struct spl_in *spl_in, struct spl_out *spl_out) /* shift the overlapping area so it is with respect to current * ODM slice's position */ - spl_out->scl_data.recout = shift_rec( + spl_scratch->scl_data.recout = shift_rec( &overlapping_area, -odm_slice.x, -odm_slice.y); - spl_out->scl_data.recout.height -= + spl_scratch->scl_data.recout.height -= spl_in->debug.visual_confirm_base_offset; - spl_out->scl_data.recout.height -= + spl_scratch->scl_data.recout.height -= spl_in->debug.visual_confirm_dpp_offset; } else /* if there is no overlap, zero recout */ - memset(&spl_out->scl_data.recout, 0, + memset(&spl_scratch->scl_data.recout, 0, sizeof(struct spl_rect)); } + /* Calculate scaling ratios */ -static void spl_calculate_scaling_ratios(struct spl_in *spl_in, struct spl_out *spl_out) +static void spl_calculate_scaling_ratios(struct spl_in *spl_in, + struct spl_scratch *spl_scratch, + struct spl_out *spl_out) { const int in_w = spl_in->basic_out.src_rect.width; const int in_h = spl_in->basic_out.src_rect.height; @@ -364,59 +369,75 @@ static void spl_calculate_scaling_ratios(struct spl_in *spl_in, struct spl_out * /*Swap surf_src height and width since scaling ratios are in recout rotation*/ if (spl_in->basic_in.rotation == SPL_ROTATION_ANGLE_90 || spl_in->basic_in.rotation == SPL_ROTATION_ANGLE_270) - swap(surf_src.height, surf_src.width); + spl_swap(surf_src.height, surf_src.width); - spl_out->scl_data.ratios.horz = dc_fixpt_from_fraction( + spl_scratch->scl_data.ratios.horz = spl_fixpt_from_fraction( surf_src.width, spl_in->basic_in.dst_rect.width); - spl_out->scl_data.ratios.vert = dc_fixpt_from_fraction( + spl_scratch->scl_data.ratios.vert = spl_fixpt_from_fraction( surf_src.height, spl_in->basic_in.dst_rect.height); if (spl_in->basic_out.view_format == SPL_VIEW_3D_SIDE_BY_SIDE) - spl_out->scl_data.ratios.horz.value *= 2; + spl_scratch->scl_data.ratios.horz.value *= 2; else if (spl_in->basic_out.view_format == SPL_VIEW_3D_TOP_AND_BOTTOM) - spl_out->scl_data.ratios.vert.value *= 2; + spl_scratch->scl_data.ratios.vert.value *= 2; - spl_out->scl_data.ratios.vert.value = div64_s64( - spl_out->scl_data.ratios.vert.value * in_h, out_h); - spl_out->scl_data.ratios.horz.value = div64_s64( - spl_out->scl_data.ratios.horz.value * in_w, out_w); + spl_scratch->scl_data.ratios.vert.value = spl_div64_s64( + spl_scratch->scl_data.ratios.vert.value * in_h, out_h); + spl_scratch->scl_data.ratios.horz.value = spl_div64_s64( + spl_scratch->scl_data.ratios.horz.value * in_w, out_w); - spl_out->scl_data.ratios.horz_c = spl_out->scl_data.ratios.horz; - spl_out->scl_data.ratios.vert_c = spl_out->scl_data.ratios.vert; + spl_scratch->scl_data.ratios.horz_c = spl_scratch->scl_data.ratios.horz; + spl_scratch->scl_data.ratios.vert_c = spl_scratch->scl_data.ratios.vert; if (spl_in->basic_in.format == SPL_PIXEL_FORMAT_420BPP8 || spl_in->basic_in.format == SPL_PIXEL_FORMAT_420BPP10) { - spl_out->scl_data.ratios.horz_c.value /= 2; - spl_out->scl_data.ratios.vert_c.value /= 2; + spl_scratch->scl_data.ratios.horz_c.value /= 2; + spl_scratch->scl_data.ratios.vert_c.value /= 2; } - spl_out->scl_data.ratios.horz = dc_fixpt_truncate( - spl_out->scl_data.ratios.horz, 19); - spl_out->scl_data.ratios.vert = dc_fixpt_truncate( - spl_out->scl_data.ratios.vert, 19); - spl_out->scl_data.ratios.horz_c = dc_fixpt_truncate( - spl_out->scl_data.ratios.horz_c, 19); - spl_out->scl_data.ratios.vert_c = dc_fixpt_truncate( - spl_out->scl_data.ratios.vert_c, 19); + spl_scratch->scl_data.ratios.horz = spl_fixpt_truncate( + spl_scratch->scl_data.ratios.horz, 19); + spl_scratch->scl_data.ratios.vert = spl_fixpt_truncate( + spl_scratch->scl_data.ratios.vert, 19); + spl_scratch->scl_data.ratios.horz_c = spl_fixpt_truncate( + spl_scratch->scl_data.ratios.horz_c, 19); + spl_scratch->scl_data.ratios.vert_c = spl_fixpt_truncate( + spl_scratch->scl_data.ratios.vert_c, 19); + + /* + * Coefficient table and some registers are different based on ratio + * that is output/input. Currently we calculate input/output + * Store 1/ratio in recip_ratio for those lookups + */ + spl_scratch->scl_data.recip_ratios.horz = spl_fixpt_recip( + spl_scratch->scl_data.ratios.horz); + spl_scratch->scl_data.recip_ratios.vert = spl_fixpt_recip( + spl_scratch->scl_data.ratios.vert); + spl_scratch->scl_data.recip_ratios.horz_c = spl_fixpt_recip( + spl_scratch->scl_data.ratios.horz_c); + spl_scratch->scl_data.recip_ratios.vert_c = spl_fixpt_recip( + spl_scratch->scl_data.ratios.vert_c); } + /* Calculate Viewport size */ -static void spl_calculate_viewport_size(struct spl_in *spl_in, struct spl_out *spl_out) +static void spl_calculate_viewport_size(struct spl_in *spl_in, struct spl_scratch *spl_scratch) { - spl_out->scl_data.viewport.width = dc_fixpt_ceil(dc_fixpt_mul_int(spl_out->scl_data.ratios.horz, - spl_out->scl_data.recout.width)); - spl_out->scl_data.viewport.height = dc_fixpt_ceil(dc_fixpt_mul_int(spl_out->scl_data.ratios.vert, - spl_out->scl_data.recout.height)); - spl_out->scl_data.viewport_c.width = dc_fixpt_ceil(dc_fixpt_mul_int(spl_out->scl_data.ratios.horz_c, - spl_out->scl_data.recout.width)); - spl_out->scl_data.viewport_c.height = dc_fixpt_ceil(dc_fixpt_mul_int(spl_out->scl_data.ratios.vert_c, - spl_out->scl_data.recout.height)); + spl_scratch->scl_data.viewport.width = spl_fixpt_ceil(spl_fixpt_mul_int(spl_scratch->scl_data.ratios.horz, + spl_scratch->scl_data.recout.width)); + spl_scratch->scl_data.viewport.height = spl_fixpt_ceil(spl_fixpt_mul_int(spl_scratch->scl_data.ratios.vert, + spl_scratch->scl_data.recout.height)); + spl_scratch->scl_data.viewport_c.width = spl_fixpt_ceil(spl_fixpt_mul_int(spl_scratch->scl_data.ratios.horz_c, + spl_scratch->scl_data.recout.width)); + spl_scratch->scl_data.viewport_c.height = spl_fixpt_ceil(spl_fixpt_mul_int(spl_scratch->scl_data.ratios.vert_c, + spl_scratch->scl_data.recout.height)); if (spl_in->basic_in.rotation == SPL_ROTATION_ANGLE_90 || spl_in->basic_in.rotation == SPL_ROTATION_ANGLE_270) { - swap(spl_out->scl_data.viewport.width, spl_out->scl_data.viewport.height); - swap(spl_out->scl_data.viewport_c.width, spl_out->scl_data.viewport_c.height); + spl_swap(spl_scratch->scl_data.viewport.width, spl_scratch->scl_data.viewport.height); + spl_swap(spl_scratch->scl_data.viewport_c.width, spl_scratch->scl_data.viewport_c.height); } } + static void spl_get_vp_scan_direction(enum spl_rotation_angle rotation, bool horizontal_mirror, bool *orthogonal_rotation, @@ -440,6 +461,7 @@ static void spl_get_vp_scan_direction(enum spl_rotation_angle rotation, if (horizontal_mirror) *flip_horz_scan_dir = !*flip_horz_scan_dir; } + /* * We completely calculate vp offset, size and inits here based entirely on scaling * ratios and recout for pixel perfect pipe combine. @@ -449,13 +471,13 @@ static void spl_calculate_init_and_vp(bool flip_scan_dir, int recout_size, int src_size, int taps, - struct fixed31_32 ratio, - struct fixed31_32 init_adj, - struct fixed31_32 *init, + struct spl_fixed31_32 ratio, + struct spl_fixed31_32 init_adj, + struct spl_fixed31_32 *init, int *vp_offset, int *vp_size) { - struct fixed31_32 temp; + struct spl_fixed31_32 temp; int int_part; /* @@ -468,33 +490,33 @@ static void spl_calculate_init_and_vp(bool flip_scan_dir, * init_bot = init + scaling_ratio * to get pixel perfect combine add the fraction from calculating vp offset */ - temp = dc_fixpt_mul_int(ratio, recout_offset_within_recout_full); - *vp_offset = dc_fixpt_floor(temp); + temp = spl_fixpt_mul_int(ratio, recout_offset_within_recout_full); + *vp_offset = spl_fixpt_floor(temp); temp.value &= 0xffffffff; - *init = dc_fixpt_add(dc_fixpt_div_int(dc_fixpt_add_int(ratio, taps + 1), 2), temp); - *init = dc_fixpt_add(*init, init_adj); - *init = dc_fixpt_truncate(*init, 19); + *init = spl_fixpt_add(spl_fixpt_div_int(spl_fixpt_add_int(ratio, taps + 1), 2), temp); + *init = spl_fixpt_add(*init, init_adj); + *init = spl_fixpt_truncate(*init, 19); /* * If viewport has non 0 offset and there are more taps than covered by init then * we should decrease the offset and increase init so we are never sampling * outside of viewport. */ - int_part = dc_fixpt_floor(*init); + int_part = spl_fixpt_floor(*init); if (int_part < taps) { int_part = taps - int_part; if (int_part > *vp_offset) int_part = *vp_offset; *vp_offset -= int_part; - *init = dc_fixpt_add_int(*init, int_part); + *init = spl_fixpt_add_int(*init, int_part); } /* * If taps are sampling outside of viewport at end of recout and there are more pixels * available in the surface we should increase the viewport size, regardless set vp to * only what is used. */ - temp = dc_fixpt_add(*init, dc_fixpt_mul_int(ratio, recout_size - 1)); - *vp_size = dc_fixpt_floor(temp); + temp = spl_fixpt_add(*init, spl_fixpt_mul_int(ratio, recout_size - 1)); + *vp_size = spl_fixpt_floor(temp); if (*vp_size + *vp_offset > src_size) *vp_size = src_size - *vp_offset; @@ -509,15 +531,16 @@ static void spl_calculate_init_and_vp(bool flip_scan_dir, static bool spl_is_yuv420(enum spl_pixel_format format) { - if ((format >= SPL_PIXEL_FORMAT_VIDEO_BEGIN) && - (format <= SPL_PIXEL_FORMAT_VIDEO_END)) + if ((format >= SPL_PIXEL_FORMAT_420BPP8) && + (format <= SPL_PIXEL_FORMAT_420BPP10)) return true; return false; } /*Calculate inits and viewport */ -static void spl_calculate_inits_and_viewports(struct spl_in *spl_in, struct spl_out *spl_out) +static void spl_calculate_inits_and_viewports(struct spl_in *spl_in, + struct spl_scratch *spl_scratch) { struct spl_rect src = spl_in->basic_in.src_rect; struct spl_rect recout_dst_in_active_timing; @@ -528,11 +551,11 @@ static void spl_calculate_inits_and_viewports(struct spl_in *spl_in, struct spl_ int vpc_div = (spl_in->basic_in.format == SPL_PIXEL_FORMAT_420BPP8 || spl_in->basic_in.format == SPL_PIXEL_FORMAT_420BPP10) ? 2 : 1; bool orthogonal_rotation, flip_vert_scan_dir, flip_horz_scan_dir; - struct fixed31_32 init_adj_h = dc_fixpt_zero; - struct fixed31_32 init_adj_v = dc_fixpt_zero; + struct spl_fixed31_32 init_adj_h = spl_fixpt_zero; + struct spl_fixed31_32 init_adj_v = spl_fixpt_zero; recout_clip_in_active_timing = shift_rec( - &spl_out->scl_data.recout, odm_slice.x, odm_slice.y); + &spl_scratch->scl_data.recout, odm_slice.x, odm_slice.y); recout_dst_in_active_timing = calculate_plane_rec_in_timing_active( spl_in, &spl_in->basic_in.dst_rect); overlap_in_active_timing = intersect_rec(&recout_clip_in_active_timing, @@ -555,8 +578,8 @@ static void spl_calculate_inits_and_viewports(struct spl_in *spl_in, struct spl_ &flip_horz_scan_dir); if (orthogonal_rotation) { - swap(src.width, src.height); - swap(flip_vert_scan_dir, flip_horz_scan_dir); + spl_swap(src.width, src.height); + spl_swap(flip_vert_scan_dir, flip_horz_scan_dir); } if (spl_is_yuv420(spl_in->basic_in.format)) { @@ -568,17 +591,17 @@ static void spl_calculate_inits_and_viewports(struct spl_in *spl_in, struct spl_ switch (spl_in->basic_in.cositing) { case CHROMA_COSITING_LEFT: - init_adj_h = dc_fixpt_zero; - init_adj_v = dc_fixpt_from_fraction(sign, 2); + init_adj_h = spl_fixpt_zero; + init_adj_v = spl_fixpt_from_fraction(sign, 4); break; case CHROMA_COSITING_NONE: - init_adj_h = dc_fixpt_from_fraction(sign, 2); - init_adj_v = dc_fixpt_from_fraction(sign, 2); + init_adj_h = spl_fixpt_from_fraction(sign, 4); + init_adj_v = spl_fixpt_from_fraction(sign, 4); break; case CHROMA_COSITING_TOPLEFT: default: - init_adj_h = dc_fixpt_zero; - init_adj_v = dc_fixpt_zero; + init_adj_h = spl_fixpt_zero; + init_adj_v = spl_fixpt_zero; break; } } @@ -586,59 +609,60 @@ static void spl_calculate_inits_and_viewports(struct spl_in *spl_in, struct spl_ spl_calculate_init_and_vp( flip_horz_scan_dir, recout_clip_in_recout_dst.x, - spl_out->scl_data.recout.width, + spl_scratch->scl_data.recout.width, src.width, - spl_out->scl_data.taps.h_taps, - spl_out->scl_data.ratios.horz, - dc_fixpt_zero, - &spl_out->scl_data.inits.h, - &spl_out->scl_data.viewport.x, - &spl_out->scl_data.viewport.width); + spl_scratch->scl_data.taps.h_taps, + spl_scratch->scl_data.ratios.horz, + spl_fixpt_zero, + &spl_scratch->scl_data.inits.h, + &spl_scratch->scl_data.viewport.x, + &spl_scratch->scl_data.viewport.width); spl_calculate_init_and_vp( flip_horz_scan_dir, recout_clip_in_recout_dst.x, - spl_out->scl_data.recout.width, + spl_scratch->scl_data.recout.width, src.width / vpc_div, - spl_out->scl_data.taps.h_taps_c, - spl_out->scl_data.ratios.horz_c, + spl_scratch->scl_data.taps.h_taps_c, + spl_scratch->scl_data.ratios.horz_c, init_adj_h, - &spl_out->scl_data.inits.h_c, - &spl_out->scl_data.viewport_c.x, - &spl_out->scl_data.viewport_c.width); + &spl_scratch->scl_data.inits.h_c, + &spl_scratch->scl_data.viewport_c.x, + &spl_scratch->scl_data.viewport_c.width); spl_calculate_init_and_vp( flip_vert_scan_dir, recout_clip_in_recout_dst.y, - spl_out->scl_data.recout.height, + spl_scratch->scl_data.recout.height, src.height, - spl_out->scl_data.taps.v_taps, - spl_out->scl_data.ratios.vert, - dc_fixpt_zero, - &spl_out->scl_data.inits.v, - &spl_out->scl_data.viewport.y, - &spl_out->scl_data.viewport.height); + spl_scratch->scl_data.taps.v_taps, + spl_scratch->scl_data.ratios.vert, + spl_fixpt_zero, + &spl_scratch->scl_data.inits.v, + &spl_scratch->scl_data.viewport.y, + &spl_scratch->scl_data.viewport.height); spl_calculate_init_and_vp( flip_vert_scan_dir, recout_clip_in_recout_dst.y, - spl_out->scl_data.recout.height, + spl_scratch->scl_data.recout.height, src.height / vpc_div, - spl_out->scl_data.taps.v_taps_c, - spl_out->scl_data.ratios.vert_c, + spl_scratch->scl_data.taps.v_taps_c, + spl_scratch->scl_data.ratios.vert_c, init_adj_v, - &spl_out->scl_data.inits.v_c, - &spl_out->scl_data.viewport_c.y, - &spl_out->scl_data.viewport_c.height); + &spl_scratch->scl_data.inits.v_c, + &spl_scratch->scl_data.viewport_c.y, + &spl_scratch->scl_data.viewport_c.height); if (orthogonal_rotation) { - swap(spl_out->scl_data.viewport.x, spl_out->scl_data.viewport.y); - swap(spl_out->scl_data.viewport.width, spl_out->scl_data.viewport.height); - swap(spl_out->scl_data.viewport_c.x, spl_out->scl_data.viewport_c.y); - swap(spl_out->scl_data.viewport_c.width, spl_out->scl_data.viewport_c.height); + spl_swap(spl_scratch->scl_data.viewport.x, spl_scratch->scl_data.viewport.y); + spl_swap(spl_scratch->scl_data.viewport.width, spl_scratch->scl_data.viewport.height); + spl_swap(spl_scratch->scl_data.viewport_c.x, spl_scratch->scl_data.viewport_c.y); + spl_swap(spl_scratch->scl_data.viewport_c.width, spl_scratch->scl_data.viewport_c.height); } - spl_out->scl_data.viewport.x += src.x; - spl_out->scl_data.viewport.y += src.y; - ASSERT(src.x % vpc_div == 0 && src.y % vpc_div == 0); - spl_out->scl_data.viewport_c.x += src.x / vpc_div; - spl_out->scl_data.viewport_c.y += src.y / vpc_div; + spl_scratch->scl_data.viewport.x += src.x; + spl_scratch->scl_data.viewport.y += src.y; + SPL_ASSERT(src.x % vpc_div == 0 && src.y % vpc_div == 0); + spl_scratch->scl_data.viewport_c.x += src.x / vpc_div; + spl_scratch->scl_data.viewport_c.y += src.y / vpc_div; } + static void spl_handle_3d_recout(struct spl_in *spl_in, struct spl_rect *recout) { /* @@ -647,7 +671,7 @@ static void spl_handle_3d_recout(struct spl_in *spl_in, struct spl_rect *recout) * This may break with rotation, good thing we aren't mixing hw rotation and 3d */ if (spl_in->basic_in.mpc_combine_v) { - ASSERT(spl_in->basic_in.rotation == SPL_ROTATION_ANGLE_0 || + SPL_ASSERT(spl_in->basic_in.rotation == SPL_ROTATION_ANGLE_0 || (spl_in->basic_out.view_format != SPL_VIEW_3D_TOP_AND_BOTTOM && spl_in->basic_out.view_format != SPL_VIEW_3D_SIDE_BY_SIDE)); if (spl_in->basic_out.view_format == SPL_VIEW_3D_TOP_AND_BOTTOM) @@ -665,6 +689,7 @@ static void spl_clamp_viewport(struct spl_rect *viewport) if (viewport->width < MIN_VIEWPORT_SIZE) viewport->width = MIN_VIEWPORT_SIZE; } + static bool spl_dscl_is_420_format(enum spl_pixel_format format) { if (format == SPL_PIXEL_FORMAT_420BPP8 || @@ -673,6 +698,7 @@ static bool spl_dscl_is_420_format(enum spl_pixel_format format) else return false; } + static bool spl_dscl_is_video_format(enum spl_pixel_format format) { if (format >= SPL_PIXEL_FORMAT_VIDEO_BEGIN @@ -681,17 +707,21 @@ static bool spl_dscl_is_video_format(enum spl_pixel_format format) else return false; } + static enum scl_mode spl_get_dscl_mode(const struct spl_in *spl_in, - const struct spl_scaler_data *data) + const struct spl_scaler_data *data, + bool enable_isharp, bool enable_easf) { - const long long one = dc_fixpt_one.value; + const long long one = spl_fixpt_one.value; enum spl_pixel_format pixel_format = spl_in->basic_in.format; + /* Bypass if ratio is 1:1 with no ISHARP or force scale on */ if (data->ratios.horz.value == one && data->ratios.vert.value == one && data->ratios.horz_c.value == one && data->ratios.vert_c.value == one - && !spl_in->basic_out.always_scale) + && !spl_in->basic_out.always_scale + && !enable_isharp) return SCL_MODE_SCALING_444_BYPASS; if (!spl_dscl_is_420_format(pixel_format)) { @@ -700,69 +730,204 @@ static enum scl_mode spl_get_dscl_mode(const struct spl_in *spl_in, else return SCL_MODE_SCALING_444_RGB_ENABLE; } - if (data->ratios.horz.value == one && data->ratios.vert.value == one) - return SCL_MODE_SCALING_420_LUMA_BYPASS; - if (data->ratios.horz_c.value == one && data->ratios.vert_c.value == one) - return SCL_MODE_SCALING_420_CHROMA_BYPASS; + + /* Bypass YUV if at 1:1 with no ISHARP or if doing 2:1 YUV + * downscale without EASF + */ + if ((!enable_isharp) && (!enable_easf)) { + if (data->ratios.horz.value == one && data->ratios.vert.value == one) + return SCL_MODE_SCALING_420_LUMA_BYPASS; + if (data->ratios.horz_c.value == one && data->ratios.vert_c.value == one) + return SCL_MODE_SCALING_420_CHROMA_BYPASS; + } return SCL_MODE_SCALING_420_YCBCR_ENABLE; } + +static bool spl_choose_lls_policy(enum spl_pixel_format format, + enum spl_transfer_func_type tf_type, + enum spl_transfer_func_predefined tf_predefined_type, + enum linear_light_scaling *lls_pref) +{ + if (spl_is_yuv420(format)) { + *lls_pref = LLS_PREF_NO; + if ((tf_type == SPL_TF_TYPE_PREDEFINED) || + (tf_type == SPL_TF_TYPE_DISTRIBUTED_POINTS)) + return true; + } else { /* RGB or YUV444 */ + if ((tf_type == SPL_TF_TYPE_PREDEFINED) || + (tf_type == SPL_TF_TYPE_BYPASS)) { + *lls_pref = LLS_PREF_YES; + return true; + } + } + *lls_pref = LLS_PREF_NO; + return false; +} + +/* Enable EASF ?*/ +static bool enable_easf(struct spl_in *spl_in, struct spl_scratch *spl_scratch) +{ + int vratio = 0; + int hratio = 0; + bool skip_easf = false; + bool lls_enable_easf = true; + + /* + * If lls_pref is LLS_PREF_DONT_CARE, then use pixel format and transfer + * function to determine whether to use LINEAR or NONLINEAR scaling + */ + if (spl_in->lls_pref == LLS_PREF_DONT_CARE) + lls_enable_easf = spl_choose_lls_policy(spl_in->basic_in.format, + spl_in->basic_in.tf_type, spl_in->basic_in.tf_predefined_type, + &spl_in->lls_pref); + + vratio = spl_fixpt_ceil(spl_scratch->scl_data.ratios.vert); + hratio = spl_fixpt_ceil(spl_scratch->scl_data.ratios.horz); + + if (!lls_enable_easf || spl_in->disable_easf) + skip_easf = true; + + /* + * No EASF support for downscaling > 2:1 + * EASF support for upscaling or downscaling up to 2:1 + */ + if ((vratio > 2) || (hratio > 2)) + skip_easf = true; + + /* Check for linear scaling or EASF preferred */ + if (spl_in->lls_pref != LLS_PREF_YES && !spl_in->prefer_easf) + skip_easf = true; + + return skip_easf; +} + +/* Check if video is in fullscreen mode */ +static bool spl_is_video_fullscreen(struct spl_in *spl_in) +{ + if (spl_is_yuv420(spl_in->basic_in.format) && spl_in->is_fullscreen) + return true; + return false; +} + +static bool spl_get_isharp_en(struct spl_in *spl_in, + struct spl_scratch *spl_scratch) +{ + bool enable_isharp = false; + int vratio = 0; + int hratio = 0; + struct spl_taps taps = spl_scratch->scl_data.taps; + bool fullscreen = spl_is_video_fullscreen(spl_in); + + vratio = spl_fixpt_ceil(spl_scratch->scl_data.ratios.vert); + hratio = spl_fixpt_ceil(spl_scratch->scl_data.ratios.horz); + + /* Return if adaptive sharpness is disabled */ + if (spl_in->adaptive_sharpness.enable == false) + return enable_isharp; + + /* No iSHARP support for downscaling */ + if (vratio > 1 || hratio > 1) + return enable_isharp; + + // Scaling is up to 1:1 (no scaling) or upscaling + + /* + * Apply sharpness to all RGB surfaces and to + * NV12/P010 surfaces if in fullscreen + */ + if (spl_is_yuv420(spl_in->basic_in.format) && !fullscreen) + return enable_isharp; + + /* + * Apply sharpness if supports horizontal taps 4,6 AND + * vertical taps 3, 4, 6 + */ + if ((taps.h_taps == 4 || taps.h_taps == 6) && + (taps.v_taps == 3 || taps.v_taps == 4 || taps.v_taps == 6)) + enable_isharp = true; + + return enable_isharp; +} + /* Calculate optimal number of taps */ static bool spl_get_optimal_number_of_taps( - int max_downscale_src_width, struct spl_in *spl_in, struct spl_out *spl_out, - const struct spl_taps *in_taps) + int max_downscale_src_width, struct spl_in *spl_in, struct spl_scratch *spl_scratch, + const struct spl_taps *in_taps, bool *enable_easf_v, bool *enable_easf_h, + bool *enable_isharp) { int num_part_y, num_part_c; int max_taps_y, max_taps_c; int min_taps_y, min_taps_c; enum lb_memory_config lb_config; + bool skip_easf = false; - if (spl_out->scl_data.viewport.width > spl_out->scl_data.h_active && + if (spl_scratch->scl_data.viewport.width > spl_scratch->scl_data.h_active && max_downscale_src_width != 0 && - spl_out->scl_data.viewport.width > max_downscale_src_width) + spl_scratch->scl_data.viewport.width > max_downscale_src_width) return false; + + /* Check if we are using EASF or not */ + skip_easf = enable_easf(spl_in, spl_scratch); + /* * Set default taps if none are provided * From programming guide: taps = min{ ceil(2*H_RATIO,1), 8} for downscaling * taps = 4 for upscaling */ - if (in_taps->h_taps == 0) { - if (dc_fixpt_ceil(spl_out->scl_data.ratios.horz) > 1) - spl_out->scl_data.taps.h_taps = min(2 * dc_fixpt_ceil(spl_out->scl_data.ratios.horz), 8); - else - spl_out->scl_data.taps.h_taps = 4; - } else - spl_out->scl_data.taps.h_taps = in_taps->h_taps; - if (in_taps->v_taps == 0) { - if (dc_fixpt_ceil(spl_out->scl_data.ratios.vert) > 1) - spl_out->scl_data.taps.v_taps = min(dc_fixpt_ceil(dc_fixpt_mul_int( - spl_out->scl_data.ratios.vert, 2)), 8); - else - spl_out->scl_data.taps.v_taps = 4; - } else - spl_out->scl_data.taps.v_taps = in_taps->v_taps; - if (in_taps->v_taps_c == 0) { - if (dc_fixpt_ceil(spl_out->scl_data.ratios.vert_c) > 1) - spl_out->scl_data.taps.v_taps_c = min(dc_fixpt_ceil(dc_fixpt_mul_int( - spl_out->scl_data.ratios.vert_c, 2)), 8); - else - spl_out->scl_data.taps.v_taps_c = 4; - } else - spl_out->scl_data.taps.v_taps_c = in_taps->v_taps_c; - if (in_taps->h_taps_c == 0) { - if (dc_fixpt_ceil(spl_out->scl_data.ratios.horz_c) > 1) - spl_out->scl_data.taps.h_taps_c = min(2 * dc_fixpt_ceil(spl_out->scl_data.ratios.horz_c), 8); + if (skip_easf) { + if (in_taps->h_taps == 0) { + if (spl_fixpt_ceil(spl_scratch->scl_data.ratios.horz) > 1) + spl_scratch->scl_data.taps.h_taps = spl_min(2 * spl_fixpt_ceil( + spl_scratch->scl_data.ratios.horz), 8); + else + spl_scratch->scl_data.taps.h_taps = 4; + } else + spl_scratch->scl_data.taps.h_taps = in_taps->h_taps; + if (in_taps->v_taps == 0) { + if (spl_fixpt_ceil(spl_scratch->scl_data.ratios.vert) > 1) + spl_scratch->scl_data.taps.v_taps = spl_min(spl_fixpt_ceil(spl_fixpt_mul_int( + spl_scratch->scl_data.ratios.vert, 2)), 8); + else + spl_scratch->scl_data.taps.v_taps = 4; + } else + spl_scratch->scl_data.taps.v_taps = in_taps->v_taps; + if (in_taps->v_taps_c == 0) { + if (spl_fixpt_ceil(spl_scratch->scl_data.ratios.vert_c) > 1) + spl_scratch->scl_data.taps.v_taps_c = spl_min(spl_fixpt_ceil(spl_fixpt_mul_int( + spl_scratch->scl_data.ratios.vert_c, 2)), 8); + else + spl_scratch->scl_data.taps.v_taps_c = 4; + } else + spl_scratch->scl_data.taps.v_taps_c = in_taps->v_taps_c; + if (in_taps->h_taps_c == 0) { + if (spl_fixpt_ceil(spl_scratch->scl_data.ratios.horz_c) > 1) + spl_scratch->scl_data.taps.h_taps_c = spl_min(2 * spl_fixpt_ceil( + spl_scratch->scl_data.ratios.horz_c), 8); + else + spl_scratch->scl_data.taps.h_taps_c = 4; + } else if ((in_taps->h_taps_c % 2) != 0 && in_taps->h_taps_c != 1) + /* Only 1 and even h_taps_c are supported by hw */ + spl_scratch->scl_data.taps.h_taps_c = in_taps->h_taps_c - 1; else - spl_out->scl_data.taps.h_taps_c = 4; - } else if ((in_taps->h_taps_c % 2) != 0 && in_taps->h_taps_c != 1) - /* Only 1 and even h_taps_c are supported by hw */ - spl_out->scl_data.taps.h_taps_c = in_taps->h_taps_c - 1; - else - spl_out->scl_data.taps.h_taps_c = in_taps->h_taps_c; + spl_scratch->scl_data.taps.h_taps_c = in_taps->h_taps_c; + } else { + if (spl_is_yuv420(spl_in->basic_in.format)) { + spl_scratch->scl_data.taps.h_taps = 6; + spl_scratch->scl_data.taps.v_taps = 6; + spl_scratch->scl_data.taps.h_taps_c = 4; + spl_scratch->scl_data.taps.v_taps_c = 4; + } else { /* RGB */ + spl_scratch->scl_data.taps.h_taps = 6; + spl_scratch->scl_data.taps.v_taps = 6; + spl_scratch->scl_data.taps.h_taps_c = 6; + spl_scratch->scl_data.taps.v_taps_c = 6; + } + } /*Ensure we can support the requested number of vtaps*/ - min_taps_y = dc_fixpt_ceil(spl_out->scl_data.ratios.vert); - min_taps_c = dc_fixpt_ceil(spl_out->scl_data.ratios.vert_c); + min_taps_y = spl_fixpt_ceil(spl_scratch->scl_data.ratios.vert); + min_taps_c = spl_fixpt_ceil(spl_scratch->scl_data.ratios.vert_c); /* Use LB_MEMORY_CONFIG_3 for 4:2:0 */ if ((spl_in->basic_in.format == SPL_PIXEL_FORMAT_420BPP8) @@ -771,16 +936,16 @@ static bool spl_get_optimal_number_of_taps( else lb_config = LB_MEMORY_CONFIG_0; // Determine max vtap support by calculating how much line buffer can fit - spl_in->funcs->spl_calc_lb_num_partitions(spl_in->basic_out.alpha_en, &spl_out->scl_data, + spl_in->funcs->spl_calc_lb_num_partitions(spl_in->basic_out.alpha_en, &spl_scratch->scl_data, lb_config, &num_part_y, &num_part_c); /* MAX_V_TAPS = MIN (NUM_LINES - MAX(CEILING(V_RATIO,1)-2, 0), 8) */ - if (dc_fixpt_ceil(spl_out->scl_data.ratios.vert) > 2) - max_taps_y = num_part_y - (dc_fixpt_ceil(spl_out->scl_data.ratios.vert) - 2); + if (spl_fixpt_ceil(spl_scratch->scl_data.ratios.vert) > 2) + max_taps_y = num_part_y - (spl_fixpt_ceil(spl_scratch->scl_data.ratios.vert) - 2); else max_taps_y = num_part_y; - if (dc_fixpt_ceil(spl_out->scl_data.ratios.vert_c) > 2) - max_taps_c = num_part_c - (dc_fixpt_ceil(spl_out->scl_data.ratios.vert_c) - 2); + if (spl_fixpt_ceil(spl_scratch->scl_data.ratios.vert_c) > 2) + max_taps_c = num_part_c - (spl_fixpt_ceil(spl_scratch->scl_data.ratios.vert_c) - 2); else max_taps_c = num_part_c; @@ -789,48 +954,108 @@ static bool spl_get_optimal_number_of_taps( else if (max_taps_c < min_taps_c) return false; - if (spl_out->scl_data.taps.v_taps > max_taps_y) - spl_out->scl_data.taps.v_taps = max_taps_y; - - if (spl_out->scl_data.taps.v_taps_c > max_taps_c) - spl_out->scl_data.taps.v_taps_c = max_taps_c; - if (spl_in->prefer_easf) { - // EASF can be enabled only for taps 3,4,6 - // If optimal no of taps is 5, then set it to 4 - // If optimal no of taps is 7 or 8, then set it to 6 - if (spl_out->scl_data.taps.v_taps == 5) - spl_out->scl_data.taps.v_taps = 4; - if (spl_out->scl_data.taps.v_taps == 7 || spl_out->scl_data.taps.v_taps == 8) - spl_out->scl_data.taps.v_taps = 6; - - if (spl_out->scl_data.taps.v_taps_c == 5) - spl_out->scl_data.taps.v_taps_c = 4; - if (spl_out->scl_data.taps.v_taps_c == 7 || spl_out->scl_data.taps.v_taps_c == 8) - spl_out->scl_data.taps.v_taps_c = 6; - - if (spl_out->scl_data.taps.h_taps == 5) - spl_out->scl_data.taps.h_taps = 4; - if (spl_out->scl_data.taps.h_taps == 7 || spl_out->scl_data.taps.h_taps == 8) - spl_out->scl_data.taps.h_taps = 6; - - if (spl_out->scl_data.taps.h_taps_c == 5) - spl_out->scl_data.taps.h_taps_c = 4; - if (spl_out->scl_data.taps.h_taps_c == 7 || spl_out->scl_data.taps.h_taps_c == 8) - spl_out->scl_data.taps.h_taps_c = 6; + if (spl_scratch->scl_data.taps.v_taps > max_taps_y) + spl_scratch->scl_data.taps.v_taps = max_taps_y; + if (spl_scratch->scl_data.taps.v_taps_c > max_taps_c) + spl_scratch->scl_data.taps.v_taps_c = max_taps_c; + + if (!skip_easf) { + /* + * RGB ( L + NL ) and Linear HDR support 6x6, 6x4, 6x3, 4x4, 4x3 + * NL YUV420 only supports 6x6, 6x4 for Y and 4x4 for UV + * + * If LB does not support 3, 4, or 6 taps, then disable EASF_V + * and only enable EASF_H. So for RGB, support 6x2, 4x2 + * and for NL YUV420, support 6x2 for Y and 4x2 for UV + * + * All other cases, have to disable EASF_V and EASF_H + * + * If optimal no of taps is 5, then set it to 4 + * If optimal no of taps is 7 or 8, then fine since max tap is 6 + * + */ + if (spl_scratch->scl_data.taps.v_taps == 5) + spl_scratch->scl_data.taps.v_taps = 4; + + if (spl_scratch->scl_data.taps.v_taps_c == 5) + spl_scratch->scl_data.taps.v_taps_c = 4; + + if (spl_scratch->scl_data.taps.h_taps == 5) + spl_scratch->scl_data.taps.h_taps = 4; + + if (spl_scratch->scl_data.taps.h_taps_c == 5) + spl_scratch->scl_data.taps.h_taps_c = 4; + + if (spl_is_yuv420(spl_in->basic_in.format)) { + if ((spl_scratch->scl_data.taps.h_taps <= 4) || + (spl_scratch->scl_data.taps.h_taps_c <= 3)) { + *enable_easf_v = false; + *enable_easf_h = false; + } else if ((spl_scratch->scl_data.taps.v_taps <= 3) || + (spl_scratch->scl_data.taps.v_taps_c <= 3)) { + *enable_easf_v = false; + *enable_easf_h = true; + } else { + *enable_easf_v = true; + *enable_easf_h = true; + } + SPL_ASSERT((spl_scratch->scl_data.taps.v_taps > 1) && + (spl_scratch->scl_data.taps.v_taps_c > 1)); + } else { /* RGB */ + if (spl_scratch->scl_data.taps.h_taps <= 3) { + *enable_easf_v = false; + *enable_easf_h = false; + } else if (spl_scratch->scl_data.taps.v_taps < 3) { + *enable_easf_v = false; + *enable_easf_h = true; + } else { + *enable_easf_v = true; + *enable_easf_h = true; + } + SPL_ASSERT(spl_scratch->scl_data.taps.v_taps > 1); + } + } else { + *enable_easf_v = false; + *enable_easf_h = false; } // end of if prefer_easf - if (!spl_in->basic_out.always_scale) { - if (IDENTITY_RATIO(spl_out->scl_data.ratios.horz)) - spl_out->scl_data.taps.h_taps = 1; - if (IDENTITY_RATIO(spl_out->scl_data.ratios.vert)) - spl_out->scl_data.taps.v_taps = 1; - if (IDENTITY_RATIO(spl_out->scl_data.ratios.horz_c)) - spl_out->scl_data.taps.h_taps_c = 1; - if (IDENTITY_RATIO(spl_out->scl_data.ratios.vert_c)) - spl_out->scl_data.taps.v_taps_c = 1; + + /* Sharpener requires scaler to be enabled, including for 1:1 + * Check if ISHARP can be enabled + * If ISHARP is not enabled, for 1:1, set taps to 1 and disable + * EASF + * For case of 2:1 YUV where chroma is 1:1, set taps to 1 if + * EASF is not enabled + */ + + *enable_isharp = spl_get_isharp_en(spl_in, spl_scratch); + if (!*enable_isharp && !spl_in->basic_out.always_scale) { + if ((IDENTITY_RATIO(spl_scratch->scl_data.ratios.horz)) && + (IDENTITY_RATIO(spl_scratch->scl_data.ratios.vert))) { + spl_scratch->scl_data.taps.h_taps = 1; + spl_scratch->scl_data.taps.v_taps = 1; + + if (IDENTITY_RATIO(spl_scratch->scl_data.ratios.horz_c)) + spl_scratch->scl_data.taps.h_taps_c = 1; + + if (IDENTITY_RATIO(spl_scratch->scl_data.ratios.vert_c)) + spl_scratch->scl_data.taps.v_taps_c = 1; + + *enable_easf_v = false; + *enable_easf_h = false; + } else { + if ((!*enable_easf_h) && + (IDENTITY_RATIO(spl_scratch->scl_data.ratios.horz_c))) + spl_scratch->scl_data.taps.h_taps_c = 1; + + if ((!*enable_easf_v) && + (IDENTITY_RATIO(spl_scratch->scl_data.ratios.vert_c))) + spl_scratch->scl_data.taps.v_taps_c = 1; + } } return true; } + static void spl_set_black_color_data(enum spl_pixel_format format, struct scl_black_color *scl_black_color) { @@ -848,38 +1073,38 @@ static void spl_set_black_color_data(enum spl_pixel_format format, static void spl_set_manual_ratio_init_data(struct dscl_prog_data *dscl_prog_data, const struct spl_scaler_data *scl_data) { - struct fixed31_32 bot; + struct spl_fixed31_32 bot; - dscl_prog_data->ratios.h_scale_ratio = dc_fixpt_u3d19(scl_data->ratios.horz) << 5; - dscl_prog_data->ratios.v_scale_ratio = dc_fixpt_u3d19(scl_data->ratios.vert) << 5; - dscl_prog_data->ratios.h_scale_ratio_c = dc_fixpt_u3d19(scl_data->ratios.horz_c) << 5; - dscl_prog_data->ratios.v_scale_ratio_c = dc_fixpt_u3d19(scl_data->ratios.vert_c) << 5; + dscl_prog_data->ratios.h_scale_ratio = spl_fixpt_u3d19(scl_data->ratios.horz) << 5; + dscl_prog_data->ratios.v_scale_ratio = spl_fixpt_u3d19(scl_data->ratios.vert) << 5; + dscl_prog_data->ratios.h_scale_ratio_c = spl_fixpt_u3d19(scl_data->ratios.horz_c) << 5; + dscl_prog_data->ratios.v_scale_ratio_c = spl_fixpt_u3d19(scl_data->ratios.vert_c) << 5; /* * 0.24 format for fraction, first five bits zeroed */ dscl_prog_data->init.h_filter_init_frac = - dc_fixpt_u0d19(scl_data->inits.h) << 5; + spl_fixpt_u0d19(scl_data->inits.h) << 5; dscl_prog_data->init.h_filter_init_int = - dc_fixpt_floor(scl_data->inits.h); + spl_fixpt_floor(scl_data->inits.h); dscl_prog_data->init.h_filter_init_frac_c = - dc_fixpt_u0d19(scl_data->inits.h_c) << 5; + spl_fixpt_u0d19(scl_data->inits.h_c) << 5; dscl_prog_data->init.h_filter_init_int_c = - dc_fixpt_floor(scl_data->inits.h_c); + spl_fixpt_floor(scl_data->inits.h_c); dscl_prog_data->init.v_filter_init_frac = - dc_fixpt_u0d19(scl_data->inits.v) << 5; + spl_fixpt_u0d19(scl_data->inits.v) << 5; dscl_prog_data->init.v_filter_init_int = - dc_fixpt_floor(scl_data->inits.v); + spl_fixpt_floor(scl_data->inits.v); dscl_prog_data->init.v_filter_init_frac_c = - dc_fixpt_u0d19(scl_data->inits.v_c) << 5; + spl_fixpt_u0d19(scl_data->inits.v_c) << 5; dscl_prog_data->init.v_filter_init_int_c = - dc_fixpt_floor(scl_data->inits.v_c); - - bot = dc_fixpt_add(scl_data->inits.v, scl_data->ratios.vert); - dscl_prog_data->init.v_filter_init_bot_frac = dc_fixpt_u0d19(bot) << 5; - dscl_prog_data->init.v_filter_init_bot_int = dc_fixpt_floor(bot); - bot = dc_fixpt_add(scl_data->inits.v_c, scl_data->ratios.vert_c); - dscl_prog_data->init.v_filter_init_bot_frac_c = dc_fixpt_u0d19(bot) << 5; - dscl_prog_data->init.v_filter_init_bot_int_c = dc_fixpt_floor(bot); + spl_fixpt_floor(scl_data->inits.v_c); + + bot = spl_fixpt_add(scl_data->inits.v, scl_data->ratios.vert); + dscl_prog_data->init.v_filter_init_bot_frac = spl_fixpt_u0d19(bot) << 5; + dscl_prog_data->init.v_filter_init_bot_int = spl_fixpt_floor(bot); + bot = spl_fixpt_add(scl_data->inits.v_c, scl_data->ratios.vert_c); + dscl_prog_data->init.v_filter_init_bot_frac_c = spl_fixpt_u0d19(bot) << 5; + dscl_prog_data->init.v_filter_init_bot_int_c = spl_fixpt_floor(bot); } static void spl_set_taps_data(struct dscl_prog_data *dscl_prog_data, @@ -890,79 +1115,28 @@ static void spl_set_taps_data(struct dscl_prog_data *dscl_prog_data, dscl_prog_data->taps.v_taps_c = scl_data->taps.v_taps_c - 1; dscl_prog_data->taps.h_taps_c = scl_data->taps.h_taps_c - 1; } -static const uint16_t *spl_dscl_get_filter_coeffs_64p(int taps, struct fixed31_32 ratio) -{ - if (taps == 8) - return spl_get_filter_8tap_64p(ratio); - else if (taps == 7) - return spl_get_filter_7tap_64p(ratio); - else if (taps == 6) - return spl_get_filter_6tap_64p(ratio); - else if (taps == 5) - return spl_get_filter_5tap_64p(ratio); - else if (taps == 4) - return spl_get_filter_4tap_64p(ratio); - else if (taps == 3) - return spl_get_filter_3tap_64p(ratio); - else if (taps == 2) - return spl_get_filter_2tap_64p(); - else if (taps == 1) - return NULL; - else { - /* should never happen, bug */ - BREAK_TO_DEBUGGER(); - return NULL; - } -} -static void spl_set_filters_data(struct dscl_prog_data *dscl_prog_data, - const struct spl_scaler_data *data) -{ - dscl_prog_data->filter_h = spl_dscl_get_filter_coeffs_64p( - data->taps.h_taps, data->ratios.horz); - dscl_prog_data->filter_v = spl_dscl_get_filter_coeffs_64p( - data->taps.v_taps, data->ratios.vert); - dscl_prog_data->filter_h_c = spl_dscl_get_filter_coeffs_64p( - data->taps.h_taps_c, data->ratios.horz_c); - dscl_prog_data->filter_v_c = spl_dscl_get_filter_coeffs_64p( - data->taps.v_taps_c, data->ratios.vert_c); -} -#ifdef CONFIG_DRM_AMD_DC_FP -static const uint16_t *spl_dscl_get_blur_scale_coeffs_64p(int taps) -{ - if ((taps == 3) || (taps == 4) || (taps == 6)) - return spl_get_filter_isharp_bs_4tap_64p(); - else { - /* should never happen, bug */ - BREAK_TO_DEBUGGER(); - return NULL; - } -} -static void spl_set_blur_scale_data(struct dscl_prog_data *dscl_prog_data, - const struct spl_scaler_data *data) -{ - dscl_prog_data->filter_blur_scale_h = spl_dscl_get_blur_scale_coeffs_64p( - data->taps.h_taps); - dscl_prog_data->filter_blur_scale_v = spl_dscl_get_blur_scale_coeffs_64p( - data->taps.v_taps); -} -#endif + /* Populate dscl prog data structure from scaler data calculated by SPL */ -static void spl_set_dscl_prog_data(struct spl_in *spl_in, struct spl_out *spl_out) +static void spl_set_dscl_prog_data(struct spl_in *spl_in, struct spl_scratch *spl_scratch, + struct spl_out *spl_out, bool enable_easf_v, bool enable_easf_h, bool enable_isharp) { struct dscl_prog_data *dscl_prog_data = spl_out->dscl_prog_data; - const struct spl_scaler_data *data = &spl_out->scl_data; + const struct spl_scaler_data *data = &spl_scratch->scl_data; struct scl_black_color *scl_black_color = &dscl_prog_data->scl_black_color; + bool enable_easf = enable_easf_v || enable_easf_h; + // Set values for recout - dscl_prog_data->recout = spl_out->scl_data.recout; + dscl_prog_data->recout = spl_scratch->scl_data.recout; // Set values for MPC Size - dscl_prog_data->mpc_size.width = spl_out->scl_data.h_active; - dscl_prog_data->mpc_size.height = spl_out->scl_data.v_active; + dscl_prog_data->mpc_size.width = spl_scratch->scl_data.h_active; + dscl_prog_data->mpc_size.height = spl_scratch->scl_data.v_active; // SCL_MODE - Set SCL_MODE data - dscl_prog_data->dscl_mode = spl_get_dscl_mode(spl_in, data); + dscl_prog_data->dscl_mode = spl_get_dscl_mode(spl_in, data, enable_isharp, + enable_easf); // SCL_BLACK_COLOR spl_set_black_color_data(spl_in->basic_in.format, scl_black_color); @@ -973,103 +1147,101 @@ static void spl_set_dscl_prog_data(struct spl_in *spl_in, struct spl_out *spl_ou // Set HTaps/VTaps spl_set_taps_data(dscl_prog_data, data); // Set viewport - dscl_prog_data->viewport = spl_out->scl_data.viewport; + dscl_prog_data->viewport = spl_scratch->scl_data.viewport; // Set viewport_c - dscl_prog_data->viewport_c = spl_out->scl_data.viewport_c; + dscl_prog_data->viewport_c = spl_scratch->scl_data.viewport_c; // Set filters data - spl_set_filters_data(dscl_prog_data, data); -} -/* Enable EASF ?*/ -static bool enable_easf(int scale_ratio, int taps, - enum linear_light_scaling lls_pref, bool prefer_easf) -{ - // Is downscaling > 6:1 ? - if (scale_ratio > 6) { - // END - No EASF support for downscaling > 6:1 - return false; - } - // Is upscaling or downscaling up to 2:1? - if (scale_ratio <= 2) { - // Is linear scaling or EASF preferred? - if (lls_pref == LLS_PREF_YES || prefer_easf) { - // LB support taps 3, 4, 6 - if (taps == 3 || taps == 4 || taps == 6) { - // END - EASF supported - return true; - } - } - } - // END - EASF not supported - return false; + spl_set_filters_data(dscl_prog_data, data, enable_easf_v, enable_easf_h); } + /* Set EASF data */ -static void spl_set_easf_data(struct dscl_prog_data *dscl_prog_data, - bool enable_easf_v, bool enable_easf_h, enum linear_light_scaling lls_pref, - enum spl_pixel_format format) +static void spl_set_easf_data(struct spl_scratch *spl_scratch, struct spl_out *spl_out, bool enable_easf_v, + bool enable_easf_h, enum linear_light_scaling lls_pref, + enum spl_pixel_format format, enum system_setup setup) { - if (spl_is_yuv420(format)) /* TODO: 0 = RGB, 1 = YUV */ - dscl_prog_data->easf_matrix_mode = 1; - else - dscl_prog_data->easf_matrix_mode = 0; - + struct dscl_prog_data *dscl_prog_data = spl_out->dscl_prog_data; if (enable_easf_v) { dscl_prog_data->easf_v_en = true; dscl_prog_data->easf_v_ring = 0; - dscl_prog_data->easf_v_sharp_factor = 1; + dscl_prog_data->easf_v_sharp_factor = 0; dscl_prog_data->easf_v_bf1_en = 1; // 1-bit, BF1 calculation enable, 0=disable, 1=enable dscl_prog_data->easf_v_bf2_mode = 0xF; // 4-bit, BF2 calculation mode - dscl_prog_data->easf_v_bf3_mode = 2; // 2-bit, BF3 chroma mode correction calculation mode - dscl_prog_data->easf_v_bf2_flat1_gain = 4; // U1.3, BF2 Flat1 Gain control - dscl_prog_data->easf_v_bf2_flat2_gain = 8; // U4.0, BF2 Flat2 Gain control - dscl_prog_data->easf_v_bf2_roc_gain = 4; // U2.2, Rate Of Change control + /* 2-bit, BF3 chroma mode correction calculation mode */ + dscl_prog_data->easf_v_bf3_mode = spl_get_v_bf3_mode( + spl_scratch->scl_data.recip_ratios.vert); + /* FP1.5.10 [ minCoef ]*/ dscl_prog_data->easf_v_ringest_3tap_dntilt_uptilt = - 0x9F00;// FP1.5.10 [minCoef] (-0.036109167214271) + spl_get_3tap_dntilt_uptilt_offset(spl_scratch->scl_data.taps.v_taps, + spl_scratch->scl_data.recip_ratios.vert); + /* FP1.5.10 [ upTiltMaxVal ]*/ dscl_prog_data->easf_v_ringest_3tap_uptilt_max = - 0x24FE; // FP1.5.10 [upTiltMaxVal] ( 0.904556445553545) + spl_get_3tap_uptilt_maxval(spl_scratch->scl_data.taps.v_taps, + spl_scratch->scl_data.recip_ratios.vert); + /* FP1.5.10 [ dnTiltSlope ]*/ dscl_prog_data->easf_v_ringest_3tap_dntilt_slope = - 0x3940; // FP1.5.10 [dnTiltSlope] ( 0.910488988173371) + spl_get_3tap_dntilt_slope(spl_scratch->scl_data.taps.v_taps, + spl_scratch->scl_data.recip_ratios.vert); + /* FP1.5.10 [ upTilt1Slope ]*/ dscl_prog_data->easf_v_ringest_3tap_uptilt1_slope = - 0x359C; // FP1.5.10 [upTilt1Slope] ( 0.125620179040899) + spl_get_3tap_uptilt1_slope(spl_scratch->scl_data.taps.v_taps, + spl_scratch->scl_data.recip_ratios.vert); + /* FP1.5.10 [ upTilt2Slope ]*/ dscl_prog_data->easf_v_ringest_3tap_uptilt2_slope = - 0x359C; // FP1.5.10 [upTilt2Slope] ( 0.006786817723568) + spl_get_3tap_uptilt2_slope(spl_scratch->scl_data.taps.v_taps, + spl_scratch->scl_data.recip_ratios.vert); + /* FP1.5.10 [ upTilt2Offset ]*/ dscl_prog_data->easf_v_ringest_3tap_uptilt2_offset = - 0x9F00; // FP1.5.10 [upTilt2Offset] (-0.006139059716651) + spl_get_3tap_uptilt2_offset(spl_scratch->scl_data.taps.v_taps, + spl_scratch->scl_data.recip_ratios.vert); + /* FP1.5.10; (2.0) Ring reducer gain for 4 or 6-tap mode [H_REDUCER_GAIN4] */ dscl_prog_data->easf_v_ringest_eventap_reduceg1 = - 0x4000; // FP1.5.10; (2.0) Ring reducer gain for 4 or 6-tap mode [H_REDUCER_GAIN4] + spl_get_reducer_gain4(spl_scratch->scl_data.taps.v_taps, + spl_scratch->scl_data.recip_ratios.vert); + /* FP1.5.10; (2.5) Ring reducer gain for 6-tap mode [V_REDUCER_GAIN6] */ dscl_prog_data->easf_v_ringest_eventap_reduceg2 = - 0x4100; // FP1.5.10; (2.5) Ring reducer gain for 6-tap mode [V_REDUCER_GAIN6] + spl_get_reducer_gain6(spl_scratch->scl_data.taps.v_taps, + spl_scratch->scl_data.recip_ratios.vert); + /* FP1.5.10; (-0.135742) Ring gain for 6-tap set to -139/1024 */ dscl_prog_data->easf_v_ringest_eventap_gain1 = - 0xB058; // FP1.5.10; (-0.135742) Ring gain for 6-tap set to -139/1024 + spl_get_gainRing4(spl_scratch->scl_data.taps.v_taps, + spl_scratch->scl_data.recip_ratios.vert); + /* FP1.5.10; (-0.024414) Ring gain for 6-tap set to -25/1024 */ dscl_prog_data->easf_v_ringest_eventap_gain2 = - 0xA640; // FP1.5.10; (-0.024414) Ring gain for 6-tap set to -25/1024 + spl_get_gainRing6(spl_scratch->scl_data.taps.v_taps, + spl_scratch->scl_data.recip_ratios.vert); dscl_prog_data->easf_v_bf_maxa = 63; //Vertical Max BF value A in U0.6 format.Selected if V_FCNTL == 0 dscl_prog_data->easf_v_bf_maxb = 63; //Vertical Max BF value A in U0.6 format.Selected if V_FCNTL == 1 dscl_prog_data->easf_v_bf_mina = 0; //Vertical Min BF value A in U0.6 format.Selected if V_FCNTL == 0 dscl_prog_data->easf_v_bf_minb = 0; //Vertical Min BF value A in U0.6 format.Selected if V_FCNTL == 1 - dscl_prog_data->easf_v_bf1_pwl_in_seg0 = -512; // S0.10, BF1 PWL Segment 0 - dscl_prog_data->easf_v_bf1_pwl_base_seg0 = 0; // U0.6, BF1 Base PWL Segment 0 - dscl_prog_data->easf_v_bf1_pwl_slope_seg0 = 3; // S7.3, BF1 Slope PWL Segment 0 - dscl_prog_data->easf_v_bf1_pwl_in_seg1 = -20; // S0.10, BF1 PWL Segment 1 - dscl_prog_data->easf_v_bf1_pwl_base_seg1 = 12; // U0.6, BF1 Base PWL Segment 1 - dscl_prog_data->easf_v_bf1_pwl_slope_seg1 = 326; // S7.3, BF1 Slope PWL Segment 1 - dscl_prog_data->easf_v_bf1_pwl_in_seg2 = 0; // S0.10, BF1 PWL Segment 2 - dscl_prog_data->easf_v_bf1_pwl_base_seg2 = 63; // U0.6, BF1 Base PWL Segment 2 - dscl_prog_data->easf_v_bf1_pwl_slope_seg2 = 0; // S7.3, BF1 Slope PWL Segment 2 - dscl_prog_data->easf_v_bf1_pwl_in_seg3 = 16; // S0.10, BF1 PWL Segment 3 - dscl_prog_data->easf_v_bf1_pwl_base_seg3 = 63; // U0.6, BF1 Base PWL Segment 3 - dscl_prog_data->easf_v_bf1_pwl_slope_seg3 = -56; // S7.3, BF1 Slope PWL Segment 3 - dscl_prog_data->easf_v_bf1_pwl_in_seg4 = 32; // S0.10, BF1 PWL Segment 4 - dscl_prog_data->easf_v_bf1_pwl_base_seg4 = 56; // U0.6, BF1 Base PWL Segment 4 - dscl_prog_data->easf_v_bf1_pwl_slope_seg4 = -48; // S7.3, BF1 Slope PWL Segment 4 - dscl_prog_data->easf_v_bf1_pwl_in_seg5 = 48; // S0.10, BF1 PWL Segment 5 - dscl_prog_data->easf_v_bf1_pwl_base_seg5 = 50; // U0.6, BF1 Base PWL Segment 5 - dscl_prog_data->easf_v_bf1_pwl_slope_seg5 = -240; // S7.3, BF1 Slope PWL Segment 5 - dscl_prog_data->easf_v_bf1_pwl_in_seg6 = 64; // S0.10, BF1 PWL Segment 6 - dscl_prog_data->easf_v_bf1_pwl_base_seg6 = 20; // U0.6, BF1 Base PWL Segment 6 - dscl_prog_data->easf_v_bf1_pwl_slope_seg6 = -160; // S7.3, BF1 Slope PWL Segment 6 - dscl_prog_data->easf_v_bf1_pwl_in_seg7 = 80; // S0.10, BF1 PWL Segment 7 - dscl_prog_data->easf_v_bf1_pwl_base_seg7 = 0; // U0.6, BF1 Base PWL Segment 7 if (lls_pref == LLS_PREF_YES) { + dscl_prog_data->easf_v_bf2_flat1_gain = 4; // U1.3, BF2 Flat1 Gain control + dscl_prog_data->easf_v_bf2_flat2_gain = 8; // U4.0, BF2 Flat2 Gain control + dscl_prog_data->easf_v_bf2_roc_gain = 4; // U2.2, Rate Of Change control + + dscl_prog_data->easf_v_bf1_pwl_in_seg0 = 0x600; // S0.10, BF1 PWL Segment 0 = -512 + dscl_prog_data->easf_v_bf1_pwl_base_seg0 = 0; // U0.6, BF1 Base PWL Segment 0 + dscl_prog_data->easf_v_bf1_pwl_slope_seg0 = 3; // S7.3, BF1 Slope PWL Segment 0 + dscl_prog_data->easf_v_bf1_pwl_in_seg1 = 0x7EC; // S0.10, BF1 PWL Segment 1 = -20 + dscl_prog_data->easf_v_bf1_pwl_base_seg1 = 12; // U0.6, BF1 Base PWL Segment 1 + dscl_prog_data->easf_v_bf1_pwl_slope_seg1 = 326; // S7.3, BF1 Slope PWL Segment 1 + dscl_prog_data->easf_v_bf1_pwl_in_seg2 = 0; // S0.10, BF1 PWL Segment 2 + dscl_prog_data->easf_v_bf1_pwl_base_seg2 = 63; // U0.6, BF1 Base PWL Segment 2 + dscl_prog_data->easf_v_bf1_pwl_slope_seg2 = 0; // S7.3, BF1 Slope PWL Segment 2 + dscl_prog_data->easf_v_bf1_pwl_in_seg3 = 16; // S0.10, BF1 PWL Segment 3 + dscl_prog_data->easf_v_bf1_pwl_base_seg3 = 63; // U0.6, BF1 Base PWL Segment 3 + dscl_prog_data->easf_v_bf1_pwl_slope_seg3 = 0x7C8; // S7.3, BF1 Slope PWL Segment 3 = -56 + dscl_prog_data->easf_v_bf1_pwl_in_seg4 = 32; // S0.10, BF1 PWL Segment 4 + dscl_prog_data->easf_v_bf1_pwl_base_seg4 = 56; // U0.6, BF1 Base PWL Segment 4 + dscl_prog_data->easf_v_bf1_pwl_slope_seg4 = 0x7D0; // S7.3, BF1 Slope PWL Segment 4 = -48 + dscl_prog_data->easf_v_bf1_pwl_in_seg5 = 48; // S0.10, BF1 PWL Segment 5 + dscl_prog_data->easf_v_bf1_pwl_base_seg5 = 50; // U0.6, BF1 Base PWL Segment 5 + dscl_prog_data->easf_v_bf1_pwl_slope_seg5 = 0x710; // S7.3, BF1 Slope PWL Segment 5 = -240 + dscl_prog_data->easf_v_bf1_pwl_in_seg6 = 64; // S0.10, BF1 PWL Segment 6 + dscl_prog_data->easf_v_bf1_pwl_base_seg6 = 20; // U0.6, BF1 Base PWL Segment 6 + dscl_prog_data->easf_v_bf1_pwl_slope_seg6 = 0x760; // S7.3, BF1 Slope PWL Segment 6 = -160 + dscl_prog_data->easf_v_bf1_pwl_in_seg7 = 80; // S0.10, BF1 PWL Segment 7 + dscl_prog_data->easf_v_bf1_pwl_base_seg7 = 0; // U0.6, BF1 Base PWL Segment 7 + dscl_prog_data->easf_v_bf3_pwl_in_set0 = 0x000; // FP0.6.6, BF3 Input value PWL Segment 0 dscl_prog_data->easf_v_bf3_pwl_base_set0 = 63; // S0.6, BF3 Base PWL Segment 0 dscl_prog_data->easf_v_bf3_pwl_slope_set0 = 0x12C5; // FP1.6.6, BF3 Slope PWL Segment 0 @@ -1090,13 +1262,41 @@ static void spl_set_easf_data(struct dscl_prog_data *dscl_prog_data, 0x136B; // FP1.6.6, BF3 Slope PWL Segment 3 dscl_prog_data->easf_v_bf3_pwl_in_set4 = 0x0C37; // FP0.6.6, BF3 Input value PWL Segment 4 (0.125 * 125^3) - dscl_prog_data->easf_v_bf3_pwl_base_set4 = -50; // S0.6, BF3 Base PWL Segment 4 + dscl_prog_data->easf_v_bf3_pwl_base_set4 = 0x4E; // S0.6, BF3 Base PWL Segment 4 = -50 dscl_prog_data->easf_v_bf3_pwl_slope_set4 = 0x1200; // FP1.6.6, BF3 Slope PWL Segment 4 dscl_prog_data->easf_v_bf3_pwl_in_set5 = 0x0CF7; // FP0.6.6, BF3 Input value PWL Segment 5 (1.0 * 125^3) - dscl_prog_data->easf_v_bf3_pwl_base_set5 = -63; // S0.6, BF3 Base PWL Segment 5 + dscl_prog_data->easf_v_bf3_pwl_base_set5 = 0x41; // S0.6, BF3 Base PWL Segment 5 = -63 } else { + dscl_prog_data->easf_v_bf2_flat1_gain = 13; // U1.3, BF2 Flat1 Gain control + dscl_prog_data->easf_v_bf2_flat2_gain = 15; // U4.0, BF2 Flat2 Gain control + dscl_prog_data->easf_v_bf2_roc_gain = 14; // U2.2, Rate Of Change control + + dscl_prog_data->easf_v_bf1_pwl_in_seg0 = 0x440; // S0.10, BF1 PWL Segment 0 = -960 + dscl_prog_data->easf_v_bf1_pwl_base_seg0 = 0; // U0.6, BF1 Base PWL Segment 0 + dscl_prog_data->easf_v_bf1_pwl_slope_seg0 = 2; // S7.3, BF1 Slope PWL Segment 0 + dscl_prog_data->easf_v_bf1_pwl_in_seg1 = 0x7C4; // S0.10, BF1 PWL Segment 1 = -60 + dscl_prog_data->easf_v_bf1_pwl_base_seg1 = 12; // U0.6, BF1 Base PWL Segment 1 + dscl_prog_data->easf_v_bf1_pwl_slope_seg1 = 109; // S7.3, BF1 Slope PWL Segment 1 + dscl_prog_data->easf_v_bf1_pwl_in_seg2 = 0; // S0.10, BF1 PWL Segment 2 + dscl_prog_data->easf_v_bf1_pwl_base_seg2 = 63; // U0.6, BF1 Base PWL Segment 2 + dscl_prog_data->easf_v_bf1_pwl_slope_seg2 = 0; // S7.3, BF1 Slope PWL Segment 2 + dscl_prog_data->easf_v_bf1_pwl_in_seg3 = 48; // S0.10, BF1 PWL Segment 3 + dscl_prog_data->easf_v_bf1_pwl_base_seg3 = 63; // U0.6, BF1 Base PWL Segment 3 + dscl_prog_data->easf_v_bf1_pwl_slope_seg3 = 0x7ED; // S7.3, BF1 Slope PWL Segment 3 = -19 + dscl_prog_data->easf_v_bf1_pwl_in_seg4 = 96; // S0.10, BF1 PWL Segment 4 + dscl_prog_data->easf_v_bf1_pwl_base_seg4 = 56; // U0.6, BF1 Base PWL Segment 4 + dscl_prog_data->easf_v_bf1_pwl_slope_seg4 = 0x7F0; // S7.3, BF1 Slope PWL Segment 4 = -16 + dscl_prog_data->easf_v_bf1_pwl_in_seg5 = 144; // S0.10, BF1 PWL Segment 5 + dscl_prog_data->easf_v_bf1_pwl_base_seg5 = 50; // U0.6, BF1 Base PWL Segment 5 + dscl_prog_data->easf_v_bf1_pwl_slope_seg5 = 0x7B0; // S7.3, BF1 Slope PWL Segment 5 = -80 + dscl_prog_data->easf_v_bf1_pwl_in_seg6 = 192; // S0.10, BF1 PWL Segment 6 + dscl_prog_data->easf_v_bf1_pwl_base_seg6 = 20; // U0.6, BF1 Base PWL Segment 6 + dscl_prog_data->easf_v_bf1_pwl_slope_seg6 = 0x7CB; // S7.3, BF1 Slope PWL Segment 6 = -53 + dscl_prog_data->easf_v_bf1_pwl_in_seg7 = 240; // S0.10, BF1 PWL Segment 7 + dscl_prog_data->easf_v_bf1_pwl_base_seg7 = 0; // U0.6, BF1 Base PWL Segment 7 + dscl_prog_data->easf_v_bf3_pwl_in_set0 = 0x000; // FP0.6.6, BF3 Input value PWL Segment 0 dscl_prog_data->easf_v_bf3_pwl_base_set0 = 63; // S0.6, BF3 Base PWL Segment 0 dscl_prog_data->easf_v_bf3_pwl_slope_set0 = 0x0000; // FP1.6.6, BF3 Slope PWL Segment 0 @@ -1115,11 +1315,11 @@ static void spl_set_easf_data(struct dscl_prog_data *dscl_prog_data, 0x1878; // FP1.6.6, BF3 Slope PWL Segment 3 dscl_prog_data->easf_v_bf3_pwl_in_set4 = 0x0761; // FP0.6.6, BF3 Input value PWL Segment 4 (0.375) - dscl_prog_data->easf_v_bf3_pwl_base_set4 = -60; // S0.6, BF3 Base PWL Segment 4 + dscl_prog_data->easf_v_bf3_pwl_base_set4 = 0x44; // S0.6, BF3 Base PWL Segment 4 = -60 dscl_prog_data->easf_v_bf3_pwl_slope_set4 = 0x1760; // FP1.6.6, BF3 Slope PWL Segment 4 dscl_prog_data->easf_v_bf3_pwl_in_set5 = 0x0780; // FP0.6.6, BF3 Input value PWL Segment 5 (0.5) - dscl_prog_data->easf_v_bf3_pwl_base_set5 = -63; // S0.6, BF3 Base PWL Segment 5 + dscl_prog_data->easf_v_bf3_pwl_base_set5 = 0x41; // S0.6, BF3 Base PWL Segment 5 = -63 } } else dscl_prog_data->easf_v_en = false; @@ -1127,52 +1327,63 @@ static void spl_set_easf_data(struct dscl_prog_data *dscl_prog_data, if (enable_easf_h) { dscl_prog_data->easf_h_en = true; dscl_prog_data->easf_h_ring = 0; - dscl_prog_data->easf_h_sharp_factor = 1; + dscl_prog_data->easf_h_sharp_factor = 0; dscl_prog_data->easf_h_bf1_en = 1; // 1-bit, BF1 calculation enable, 0=disable, 1=enable dscl_prog_data->easf_h_bf2_mode = 0xF; // 4-bit, BF2 calculation mode - dscl_prog_data->easf_h_bf3_mode = - 2; // 2-bit, BF3 chroma mode correction calculation mode - dscl_prog_data->easf_h_bf2_flat1_gain = 4; // U1.3, BF2 Flat1 Gain control - dscl_prog_data->easf_h_bf2_flat2_gain = 8; // U4.0, BF2 Flat2 Gain control - dscl_prog_data->easf_h_bf2_roc_gain = 4; // U2.2, Rate Of Change control + /* 2-bit, BF3 chroma mode correction calculation mode */ + dscl_prog_data->easf_h_bf3_mode = spl_get_h_bf3_mode( + spl_scratch->scl_data.recip_ratios.horz); + /* FP1.5.10; (2.0) Ring reducer gain for 4 or 6-tap mode [H_REDUCER_GAIN4] */ dscl_prog_data->easf_h_ringest_eventap_reduceg1 = - 0x4000; // FP1.5.10; (2.0) Ring reducer gain for 4 or 6-tap mode [H_REDUCER_GAIN4] + spl_get_reducer_gain4(spl_scratch->scl_data.taps.h_taps, + spl_scratch->scl_data.recip_ratios.horz); + /* FP1.5.10; (2.5) Ring reducer gain for 6-tap mode [V_REDUCER_GAIN6] */ dscl_prog_data->easf_h_ringest_eventap_reduceg2 = - 0x4100; // FP1.5.10; (2.5) Ring reducer gain for 6-tap mode [V_REDUCER_GAIN6] + spl_get_reducer_gain6(spl_scratch->scl_data.taps.h_taps, + spl_scratch->scl_data.recip_ratios.horz); + /* FP1.5.10; (-0.135742) Ring gain for 6-tap set to -139/1024 */ dscl_prog_data->easf_h_ringest_eventap_gain1 = - 0xB058; // FP1.5.10; (-0.135742) Ring gain for 6-tap set to -139/1024 + spl_get_gainRing4(spl_scratch->scl_data.taps.h_taps, + spl_scratch->scl_data.recip_ratios.horz); + /* FP1.5.10; (-0.024414) Ring gain for 6-tap set to -25/1024 */ dscl_prog_data->easf_h_ringest_eventap_gain2 = - 0xA640; // FP1.5.10; (-0.024414) Ring gain for 6-tap set to -25/1024 + spl_get_gainRing6(spl_scratch->scl_data.taps.h_taps, + spl_scratch->scl_data.recip_ratios.horz); dscl_prog_data->easf_h_bf_maxa = 63; //Horz Max BF value A in U0.6 format.Selected if H_FCNTL==0 dscl_prog_data->easf_h_bf_maxb = 63; //Horz Max BF value B in U0.6 format.Selected if H_FCNTL==1 dscl_prog_data->easf_h_bf_mina = 0; //Horz Min BF value B in U0.6 format.Selected if H_FCNTL==0 dscl_prog_data->easf_h_bf_minb = 0; //Horz Min BF value B in U0.6 format.Selected if H_FCNTL==1 - dscl_prog_data->easf_h_bf1_pwl_in_seg0 = -512; // S0.10, BF1 PWL Segment 0 - dscl_prog_data->easf_h_bf1_pwl_base_seg0 = 0; // U0.6, BF1 Base PWL Segment 0 - dscl_prog_data->easf_h_bf1_pwl_slope_seg0 = 3; // S7.3, BF1 Slope PWL Segment 0 - dscl_prog_data->easf_h_bf1_pwl_in_seg1 = -20; // S0.10, BF1 PWL Segment 1 - dscl_prog_data->easf_h_bf1_pwl_base_seg1 = 12; // U0.6, BF1 Base PWL Segment 1 - dscl_prog_data->easf_h_bf1_pwl_slope_seg1 = 326; // S7.3, BF1 Slope PWL Segment 1 - dscl_prog_data->easf_h_bf1_pwl_in_seg2 = 0; // S0.10, BF1 PWL Segment 2 - dscl_prog_data->easf_h_bf1_pwl_base_seg2 = 63; // U0.6, BF1 Base PWL Segment 2 - dscl_prog_data->easf_h_bf1_pwl_slope_seg2 = 0; // S7.3, BF1 Slope PWL Segment 2 - dscl_prog_data->easf_h_bf1_pwl_in_seg3 = 16; // S0.10, BF1 PWL Segment 3 - dscl_prog_data->easf_h_bf1_pwl_base_seg3 = 63; // U0.6, BF1 Base PWL Segment 3 - dscl_prog_data->easf_h_bf1_pwl_slope_seg3 = -56; // S7.3, BF1 Slope PWL Segment 3 - dscl_prog_data->easf_h_bf1_pwl_in_seg4 = 32; // S0.10, BF1 PWL Segment 4 - dscl_prog_data->easf_h_bf1_pwl_base_seg4 = 56; // U0.6, BF1 Base PWL Segment 4 - dscl_prog_data->easf_h_bf1_pwl_slope_seg4 = -48; // S7.3, BF1 Slope PWL Segment 4 - dscl_prog_data->easf_h_bf1_pwl_in_seg5 = 48; // S0.10, BF1 PWL Segment 5 - dscl_prog_data->easf_h_bf1_pwl_base_seg5 = 50; // U0.6, BF1 Base PWL Segment 5 - dscl_prog_data->easf_h_bf1_pwl_slope_seg5 = -240; // S7.3, BF1 Slope PWL Segment 5 - dscl_prog_data->easf_h_bf1_pwl_in_seg6 = 64; // S0.10, BF1 PWL Segment 6 - dscl_prog_data->easf_h_bf1_pwl_base_seg6 = 20; // U0.6, BF1 Base PWL Segment 6 - dscl_prog_data->easf_h_bf1_pwl_slope_seg6 = -160; // S7.3, BF1 Slope PWL Segment 6 - dscl_prog_data->easf_h_bf1_pwl_in_seg7 = 80; // S0.10, BF1 PWL Segment 7 - dscl_prog_data->easf_h_bf1_pwl_base_seg7 = 0; // U0.6, BF1 Base PWL Segment 7 if (lls_pref == LLS_PREF_YES) { + dscl_prog_data->easf_h_bf2_flat1_gain = 4; // U1.3, BF2 Flat1 Gain control + dscl_prog_data->easf_h_bf2_flat2_gain = 8; // U4.0, BF2 Flat2 Gain control + dscl_prog_data->easf_h_bf2_roc_gain = 4; // U2.2, Rate Of Change control + + dscl_prog_data->easf_h_bf1_pwl_in_seg0 = 0x600; // S0.10, BF1 PWL Segment 0 = -512 + dscl_prog_data->easf_h_bf1_pwl_base_seg0 = 0; // U0.6, BF1 Base PWL Segment 0 + dscl_prog_data->easf_h_bf1_pwl_slope_seg0 = 3; // S7.3, BF1 Slope PWL Segment 0 + dscl_prog_data->easf_h_bf1_pwl_in_seg1 = 0x7EC; // S0.10, BF1 PWL Segment 1 = -20 + dscl_prog_data->easf_h_bf1_pwl_base_seg1 = 12; // U0.6, BF1 Base PWL Segment 1 + dscl_prog_data->easf_h_bf1_pwl_slope_seg1 = 326; // S7.3, BF1 Slope PWL Segment 1 + dscl_prog_data->easf_h_bf1_pwl_in_seg2 = 0; // S0.10, BF1 PWL Segment 2 + dscl_prog_data->easf_h_bf1_pwl_base_seg2 = 63; // U0.6, BF1 Base PWL Segment 2 + dscl_prog_data->easf_h_bf1_pwl_slope_seg2 = 0; // S7.3, BF1 Slope PWL Segment 2 + dscl_prog_data->easf_h_bf1_pwl_in_seg3 = 16; // S0.10, BF1 PWL Segment 3 + dscl_prog_data->easf_h_bf1_pwl_base_seg3 = 63; // U0.6, BF1 Base PWL Segment 3 + dscl_prog_data->easf_h_bf1_pwl_slope_seg3 = 0x7C8; // S7.3, BF1 Slope PWL Segment 3 = -56 + dscl_prog_data->easf_h_bf1_pwl_in_seg4 = 32; // S0.10, BF1 PWL Segment 4 + dscl_prog_data->easf_h_bf1_pwl_base_seg4 = 56; // U0.6, BF1 Base PWL Segment 4 + dscl_prog_data->easf_h_bf1_pwl_slope_seg4 = 0x7D0; // S7.3, BF1 Slope PWL Segment 4 = -48 + dscl_prog_data->easf_h_bf1_pwl_in_seg5 = 48; // S0.10, BF1 PWL Segment 5 + dscl_prog_data->easf_h_bf1_pwl_base_seg5 = 50; // U0.6, BF1 Base PWL Segment 5 + dscl_prog_data->easf_h_bf1_pwl_slope_seg5 = 0x710; // S7.3, BF1 Slope PWL Segment 5 = -240 + dscl_prog_data->easf_h_bf1_pwl_in_seg6 = 64; // S0.10, BF1 PWL Segment 6 + dscl_prog_data->easf_h_bf1_pwl_base_seg6 = 20; // U0.6, BF1 Base PWL Segment 6 + dscl_prog_data->easf_h_bf1_pwl_slope_seg6 = 0x760; // S7.3, BF1 Slope PWL Segment 6 = -160 + dscl_prog_data->easf_h_bf1_pwl_in_seg7 = 80; // S0.10, BF1 PWL Segment 7 + dscl_prog_data->easf_h_bf1_pwl_base_seg7 = 0; // U0.6, BF1 Base PWL Segment 7 + dscl_prog_data->easf_h_bf3_pwl_in_set0 = 0x000; // FP0.6.6, BF3 Input value PWL Segment 0 dscl_prog_data->easf_h_bf3_pwl_base_set0 = 63; // S0.6, BF3 Base PWL Segment 0 dscl_prog_data->easf_h_bf3_pwl_slope_set0 = 0x12C5; // FP1.6.6, BF3 Slope PWL Segment 0 @@ -1190,12 +1401,40 @@ static void spl_set_easf_data(struct dscl_prog_data *dscl_prog_data, dscl_prog_data->easf_h_bf3_pwl_slope_set3 = 0x136B; // FP1.6.6, BF3 Slope PWL Segment 3 dscl_prog_data->easf_h_bf3_pwl_in_set4 = 0x0C37; // FP0.6.6, BF3 Input value PWL Segment 4 (0.125 * 125^3) - dscl_prog_data->easf_h_bf3_pwl_base_set4 = -50; // S0.6, BF3 Base PWL Segment 4 + dscl_prog_data->easf_h_bf3_pwl_base_set4 = 0x4E; // S0.6, BF3 Base PWL Segment 4 = -50 dscl_prog_data->easf_h_bf3_pwl_slope_set4 = 0x1200; // FP1.6.6, BF3 Slope PWL Segment 4 dscl_prog_data->easf_h_bf3_pwl_in_set5 = 0x0CF7; // FP0.6.6, BF3 Input value PWL Segment 5 (1.0 * 125^3) - dscl_prog_data->easf_h_bf3_pwl_base_set5 = -63; // S0.6, BF3 Base PWL Segment 5 + dscl_prog_data->easf_h_bf3_pwl_base_set5 = 0x41; // S0.6, BF3 Base PWL Segment 5 = -63 } else { + dscl_prog_data->easf_h_bf2_flat1_gain = 13; // U1.3, BF2 Flat1 Gain control + dscl_prog_data->easf_h_bf2_flat2_gain = 15; // U4.0, BF2 Flat2 Gain control + dscl_prog_data->easf_h_bf2_roc_gain = 14; // U2.2, Rate Of Change control + + dscl_prog_data->easf_h_bf1_pwl_in_seg0 = 0x440; // S0.10, BF1 PWL Segment 0 = -960 + dscl_prog_data->easf_h_bf1_pwl_base_seg0 = 0; // U0.6, BF1 Base PWL Segment 0 + dscl_prog_data->easf_h_bf1_pwl_slope_seg0 = 2; // S7.3, BF1 Slope PWL Segment 0 + dscl_prog_data->easf_h_bf1_pwl_in_seg1 = 0x7C4; // S0.10, BF1 PWL Segment 1 = -60 + dscl_prog_data->easf_h_bf1_pwl_base_seg1 = 12; // U0.6, BF1 Base PWL Segment 1 + dscl_prog_data->easf_h_bf1_pwl_slope_seg1 = 109; // S7.3, BF1 Slope PWL Segment 1 + dscl_prog_data->easf_h_bf1_pwl_in_seg2 = 0; // S0.10, BF1 PWL Segment 2 + dscl_prog_data->easf_h_bf1_pwl_base_seg2 = 63; // U0.6, BF1 Base PWL Segment 2 + dscl_prog_data->easf_h_bf1_pwl_slope_seg2 = 0; // S7.3, BF1 Slope PWL Segment 2 + dscl_prog_data->easf_h_bf1_pwl_in_seg3 = 48; // S0.10, BF1 PWL Segment 3 + dscl_prog_data->easf_h_bf1_pwl_base_seg3 = 63; // U0.6, BF1 Base PWL Segment 3 + dscl_prog_data->easf_h_bf1_pwl_slope_seg3 = 0x7ED; // S7.3, BF1 Slope PWL Segment 3 = -19 + dscl_prog_data->easf_h_bf1_pwl_in_seg4 = 96; // S0.10, BF1 PWL Segment 4 + dscl_prog_data->easf_h_bf1_pwl_base_seg4 = 56; // U0.6, BF1 Base PWL Segment 4 + dscl_prog_data->easf_h_bf1_pwl_slope_seg4 = 0x7F0; // S7.3, BF1 Slope PWL Segment 4 = -16 + dscl_prog_data->easf_h_bf1_pwl_in_seg5 = 144; // S0.10, BF1 PWL Segment 5 + dscl_prog_data->easf_h_bf1_pwl_base_seg5 = 50; // U0.6, BF1 Base PWL Segment 5 + dscl_prog_data->easf_h_bf1_pwl_slope_seg5 = 0x7B0; // S7.3, BF1 Slope PWL Segment 5 = -80 + dscl_prog_data->easf_h_bf1_pwl_in_seg6 = 192; // S0.10, BF1 PWL Segment 6 + dscl_prog_data->easf_h_bf1_pwl_base_seg6 = 20; // U0.6, BF1 Base PWL Segment 6 + dscl_prog_data->easf_h_bf1_pwl_slope_seg6 = 0x7CB; // S7.3, BF1 Slope PWL Segment 6 = -53 + dscl_prog_data->easf_h_bf1_pwl_in_seg7 = 240; // S0.10, BF1 PWL Segment 7 + dscl_prog_data->easf_h_bf1_pwl_base_seg7 = 0; // U0.6, BF1 Base PWL Segment 7 + dscl_prog_data->easf_h_bf3_pwl_in_set0 = 0x000; // FP0.6.6, BF3 Input value PWL Segment 0 dscl_prog_data->easf_h_bf3_pwl_base_set0 = 63; // S0.6, BF3 Base PWL Segment 0 dscl_prog_data->easf_h_bf3_pwl_slope_set0 = 0x0000; // FP1.6.6, BF3 Slope PWL Segment 0 @@ -1213,25 +1452,36 @@ static void spl_set_easf_data(struct dscl_prog_data *dscl_prog_data, dscl_prog_data->easf_h_bf3_pwl_slope_set3 = 0x1878; // FP1.6.6, BF3 Slope PWL Segment 3 dscl_prog_data->easf_h_bf3_pwl_in_set4 = 0x0761; // FP0.6.6, BF3 Input value PWL Segment 4 (0.375) - dscl_prog_data->easf_h_bf3_pwl_base_set4 = -60; // S0.6, BF3 Base PWL Segment 4 + dscl_prog_data->easf_h_bf3_pwl_base_set4 = 0x44; // S0.6, BF3 Base PWL Segment 4 = -60 dscl_prog_data->easf_h_bf3_pwl_slope_set4 = 0x1760; // FP1.6.6, BF3 Slope PWL Segment 4 dscl_prog_data->easf_h_bf3_pwl_in_set5 = 0x0780; // FP0.6.6, BF3 Input value PWL Segment 5 (0.5) - dscl_prog_data->easf_h_bf3_pwl_base_set5 = -63; // S0.6, BF3 Base PWL Segment 5 + dscl_prog_data->easf_h_bf3_pwl_base_set5 = 0x41; // S0.6, BF3 Base PWL Segment 5 = -63 } // if (lls_pref == LLS_PREF_YES) } else dscl_prog_data->easf_h_en = false; if (lls_pref == LLS_PREF_YES) { dscl_prog_data->easf_ltonl_en = 1; // Linear input - dscl_prog_data->easf_matrix_c0 = - 0x504E; // fp1.5.10, C0 coefficient (LN_BT2020: 0.2627 * (2^14)/125 = 34.43750000) - dscl_prog_data->easf_matrix_c1 = - 0x558E; // fp1.5.10, C1 coefficient (LN_BT2020: 0.6780 * (2^14)/125 = 88.87500000) - dscl_prog_data->easf_matrix_c2 = - 0x47C6; // fp1.5.10, C2 coefficient (LN_BT2020: 0.0593 * (2^14)/125 = 7.77343750) - dscl_prog_data->easf_matrix_c3 = - 0x0; // fp1.5.10, C3 coefficient + if (setup == HDR_L) { + dscl_prog_data->easf_matrix_c0 = + 0x504E; // fp1.5.10, C0 coefficient (LN_BT2020: 0.2627 * (2^14)/125 = 34.43750000) + dscl_prog_data->easf_matrix_c1 = + 0x558E; // fp1.5.10, C1 coefficient (LN_BT2020: 0.6780 * (2^14)/125 = 88.87500000) + dscl_prog_data->easf_matrix_c2 = + 0x47C6; // fp1.5.10, C2 coefficient (LN_BT2020: 0.0593 * (2^14)/125 = 7.77343750) + dscl_prog_data->easf_matrix_c3 = + 0x0; // fp1.5.10, C3 coefficient + } else { // SDR_L + dscl_prog_data->easf_matrix_c0 = + 0x4EF7; // fp1.5.10, C0 coefficient (LN_rec709: 0.2126 * (2^14)/125 = 27.86590720) + dscl_prog_data->easf_matrix_c1 = + 0x55DC; // fp1.5.10, C1 coefficient (LN_rec709: 0.7152 * (2^14)/125 = 93.74269440) + dscl_prog_data->easf_matrix_c2 = + 0x48BB; // fp1.5.10, C2 coefficient (LN_rec709: 0.0722 * (2^14)/125 = 9.46339840) + dscl_prog_data->easf_matrix_c3 = + 0x0; // fp1.5.10, C3 coefficient + } } else { dscl_prog_data->easf_ltonl_en = 0; // Non-Linear input dscl_prog_data->easf_matrix_c0 = @@ -1243,27 +1493,43 @@ static void spl_set_easf_data(struct dscl_prog_data *dscl_prog_data, dscl_prog_data->easf_matrix_c3 = 0x0; // fp1.5.10, C3 coefficient } + + if (spl_is_yuv420(format)) { /* TODO: 0 = RGB, 1 = YUV */ + dscl_prog_data->easf_matrix_mode = 1; + /* + * 2-bit, BF3 chroma mode correction calculation mode + * Needs to be disabled for YUV420 mode + * Override lookup value + */ + dscl_prog_data->easf_v_bf3_mode = 0; + dscl_prog_data->easf_h_bf3_mode = 0; + } else + dscl_prog_data->easf_matrix_mode = 0; + } + /*Set isharp noise detection */ -static void spl_set_isharp_noise_det_mode(struct dscl_prog_data *dscl_prog_data) +static void spl_set_isharp_noise_det_mode(struct dscl_prog_data *dscl_prog_data, + const struct spl_scaler_data *data) { // ISHARP_NOISEDET_MODE // 0: 3x5 as VxH // 1: 4x5 as VxH // 2: // 3: 5x5 as VxH - if (dscl_prog_data->taps.v_taps == 6) - dscl_prog_data->isharp_noise_det.mode = 3; // ISHARP_NOISEDET_MODE - else if (dscl_prog_data->taps.h_taps == 4) - dscl_prog_data->isharp_noise_det.mode = 1; // ISHARP_NOISEDET_MODE - else if (dscl_prog_data->taps.h_taps == 3) - dscl_prog_data->isharp_noise_det.mode = 0; // ISHARP_NOISEDET_MODE + if (data->taps.v_taps == 6) + dscl_prog_data->isharp_noise_det.mode = 3; + else if (data->taps.v_taps == 4) + dscl_prog_data->isharp_noise_det.mode = 1; + else if (data->taps.v_taps == 3) + dscl_prog_data->isharp_noise_det.mode = 0; }; /* Set Sharpener data */ static void spl_set_isharp_data(struct dscl_prog_data *dscl_prog_data, struct adaptive_sharpness adp_sharpness, bool enable_isharp, enum linear_light_scaling lls_pref, enum spl_pixel_format format, - const struct spl_scaler_data *data) + const struct spl_scaler_data *data, struct spl_fixed31_32 ratio, + enum system_setup setup) { /* Turn off sharpener if not required */ if (!enable_isharp) { @@ -1272,10 +1538,12 @@ static void spl_set_isharp_data(struct dscl_prog_data *dscl_prog_data, } dscl_prog_data->isharp_en = 1; // ISHARP_EN - dscl_prog_data->isharp_noise_det.enable = 1; // ISHARP_NOISEDET_EN // Set ISHARP_NOISEDET_MODE if htaps = 6-tap - if (dscl_prog_data->taps.h_taps == 6) - spl_set_isharp_noise_det_mode(dscl_prog_data); // ISHARP_NOISEDET_MODE + if (data->taps.h_taps == 6) { + dscl_prog_data->isharp_noise_det.enable = 1; /* ISHARP_NOISEDET_EN */ + spl_set_isharp_noise_det_mode(dscl_prog_data, data); /* ISHARP_NOISEDET_MODE */ + } else + dscl_prog_data->isharp_noise_det.enable = 0; // ISHARP_NOISEDET_EN // Program noise detection threshold dscl_prog_data->isharp_noise_det.uthreshold = 24; // ISHARP_NOISEDET_UTHRE dscl_prog_data->isharp_noise_det.dthreshold = 4; // ISHARP_NOISEDET_DTHRE @@ -1284,50 +1552,67 @@ static void spl_set_isharp_data(struct dscl_prog_data *dscl_prog_data, dscl_prog_data->isharp_noise_det.pwl_end_in = 13; // ISHARP_NOISEDET_PWL_END_IN dscl_prog_data->isharp_noise_det.pwl_slope = 1623; // ISHARP_NOISEDET_PWL_SLOPE - if ((lls_pref == LLS_PREF_NO) && !spl_is_yuv420(format)) /* ISHARP_FMT_MODE */ + if (lls_pref == LLS_PREF_NO) /* ISHARP_FMT_MODE */ dscl_prog_data->isharp_fmt.mode = 1; else dscl_prog_data->isharp_fmt.mode = 0; dscl_prog_data->isharp_fmt.norm = 0x3C00; // ISHARP_FMT_NORM dscl_prog_data->isharp_lba.mode = 0; // ISHARP_LBA_MODE - // ISHARP_LBA_PWL_SEG0: ISHARP Local Brightness Adjustment PWL Segment 0 - dscl_prog_data->isharp_lba.in_seg[0] = 0; // ISHARP LBA PWL for Seg 0. INPUT value in U0.10 format - dscl_prog_data->isharp_lba.base_seg[0] = 0; // ISHARP LBA PWL for Seg 0. BASE value in U0.6 format - dscl_prog_data->isharp_lba.slope_seg[0] = 32; // ISHARP LBA for Seg 0. SLOPE value in S5.3 format - // ISHARP_LBA_PWL_SEG1: ISHARP LBA PWL Segment 1 - dscl_prog_data->isharp_lba.in_seg[1] = 256; // ISHARP LBA PWL for Seg 1. INPUT value in U0.10 format - dscl_prog_data->isharp_lba.base_seg[1] = 63; // ISHARP LBA PWL for Seg 1. BASE value in U0.6 format - dscl_prog_data->isharp_lba.slope_seg[1] = 0; // ISHARP LBA for Seg 1. SLOPE value in S5.3 format - // ISHARP_LBA_PWL_SEG2: ISHARP LBA PWL Segment 2 - dscl_prog_data->isharp_lba.in_seg[2] = 614; // ISHARP LBA PWL for Seg 2. INPUT value in U0.10 format - dscl_prog_data->isharp_lba.base_seg[2] = 63; // ISHARP LBA PWL for Seg 2. BASE value in U0.6 format - dscl_prog_data->isharp_lba.slope_seg[2] = -20; // ISHARP LBA for Seg 2. SLOPE value in S5.3 format - // ISHARP_LBA_PWL_SEG3: ISHARP LBA PWL Segment 3 - dscl_prog_data->isharp_lba.in_seg[3] = 1023; // ISHARP LBA PWL for Seg 3.INPUT value in U0.10 format - dscl_prog_data->isharp_lba.base_seg[3] = 0; // ISHARP LBA PWL for Seg 3. BASE value in U0.6 format - dscl_prog_data->isharp_lba.slope_seg[3] = 0; // ISHARP LBA for Seg 3. SLOPE value in S5.3 format - // ISHARP_LBA_PWL_SEG4: ISHARP LBA PWL Segment 4 - dscl_prog_data->isharp_lba.in_seg[4] = 1023; // ISHARP LBA PWL for Seg 4.INPUT value in U0.10 format - dscl_prog_data->isharp_lba.base_seg[4] = 0; // ISHARP LBA PWL for Seg 4. BASE value in U0.6 format - dscl_prog_data->isharp_lba.slope_seg[4] = 0; // ISHARP LBA for Seg 4. SLOPE value in S5.3 format - // ISHARP_LBA_PWL_SEG5: ISHARP LBA PWL Segment 5 - dscl_prog_data->isharp_lba.in_seg[5] = 1023; // ISHARP LBA PWL for Seg 5.INPUT value in U0.10 format - dscl_prog_data->isharp_lba.base_seg[5] = 0; // ISHARP LBA PWL for Seg 5. BASE value in U0.6 format - switch (adp_sharpness.sharpness) { - case SHARPNESS_LOW: - dscl_prog_data->isharp_delta = spl_get_filter_isharp_1D_lut_0p5x(); - break; - case SHARPNESS_MID: - dscl_prog_data->isharp_delta = spl_get_filter_isharp_1D_lut_1p0x(); - break; - case SHARPNESS_HIGH: - dscl_prog_data->isharp_delta = spl_get_filter_isharp_1D_lut_2p0x(); - break; - default: - BREAK_TO_DEBUGGER(); + + if (setup == SDR_L) { + // ISHARP_LBA_PWL_SEG0: ISHARP Local Brightness Adjustment PWL Segment 0 + dscl_prog_data->isharp_lba.in_seg[0] = 0; // ISHARP LBA PWL for Seg 0. INPUT value in U0.10 format + dscl_prog_data->isharp_lba.base_seg[0] = 0; // ISHARP LBA PWL for Seg 0. BASE value in U0.6 format + dscl_prog_data->isharp_lba.slope_seg[0] = 62; // ISHARP LBA for Seg 0. SLOPE value in S5.3 format + // ISHARP_LBA_PWL_SEG1: ISHARP LBA PWL Segment 1 + dscl_prog_data->isharp_lba.in_seg[1] = 130; // ISHARP LBA PWL for Seg 1. INPUT value in U0.10 format + dscl_prog_data->isharp_lba.base_seg[1] = 63; // ISHARP LBA PWL for Seg 1. BASE value in U0.6 format + dscl_prog_data->isharp_lba.slope_seg[1] = 0; // ISHARP LBA for Seg 1. SLOPE value in S5.3 format + // ISHARP_LBA_PWL_SEG2: ISHARP LBA PWL Segment 2 + dscl_prog_data->isharp_lba.in_seg[2] = 312; // ISHARP LBA PWL for Seg 2. INPUT value in U0.10 format + dscl_prog_data->isharp_lba.base_seg[2] = 63; // ISHARP LBA PWL for Seg 2. BASE value in U0.6 format + dscl_prog_data->isharp_lba.slope_seg[2] = 0x1D9; // ISHARP LBA for Seg 2. SLOPE value in S5.3 format = -39 + // ISHARP_LBA_PWL_SEG3: ISHARP LBA PWL Segment 3 + dscl_prog_data->isharp_lba.in_seg[3] = 520; // ISHARP LBA PWL for Seg 3.INPUT value in U0.10 format + dscl_prog_data->isharp_lba.base_seg[3] = 0; // ISHARP LBA PWL for Seg 3. BASE value in U0.6 format + dscl_prog_data->isharp_lba.slope_seg[3] = 0; // ISHARP LBA for Seg 3. SLOPE value in S5.3 format + // ISHARP_LBA_PWL_SEG4: ISHARP LBA PWL Segment 4 + dscl_prog_data->isharp_lba.in_seg[4] = 520; // ISHARP LBA PWL for Seg 4.INPUT value in U0.10 format + dscl_prog_data->isharp_lba.base_seg[4] = 0; // ISHARP LBA PWL for Seg 4. BASE value in U0.6 format + dscl_prog_data->isharp_lba.slope_seg[4] = 0; // ISHARP LBA for Seg 4. SLOPE value in S5.3 format + // ISHARP_LBA_PWL_SEG5: ISHARP LBA PWL Segment 5 + dscl_prog_data->isharp_lba.in_seg[5] = 520; // ISHARP LBA PWL for Seg 5.INPUT value in U0.10 format + dscl_prog_data->isharp_lba.base_seg[5] = 0; // ISHARP LBA PWL for Seg 5. BASE value in U0.6 format + } else { + // ISHARP_LBA_PWL_SEG0: ISHARP Local Brightness Adjustment PWL Segment 0 + dscl_prog_data->isharp_lba.in_seg[0] = 0; // ISHARP LBA PWL for Seg 0. INPUT value in U0.10 format + dscl_prog_data->isharp_lba.base_seg[0] = 0; // ISHARP LBA PWL for Seg 0. BASE value in U0.6 format + dscl_prog_data->isharp_lba.slope_seg[0] = 32; // ISHARP LBA for Seg 0. SLOPE value in S5.3 format + // ISHARP_LBA_PWL_SEG1: ISHARP LBA PWL Segment 1 + dscl_prog_data->isharp_lba.in_seg[1] = 256; // ISHARP LBA PWL for Seg 1. INPUT value in U0.10 format + dscl_prog_data->isharp_lba.base_seg[1] = 63; // ISHARP LBA PWL for Seg 1. BASE value in U0.6 format + dscl_prog_data->isharp_lba.slope_seg[1] = 0; // ISHARP LBA for Seg 1. SLOPE value in S5.3 format + // ISHARP_LBA_PWL_SEG2: ISHARP LBA PWL Segment 2 + dscl_prog_data->isharp_lba.in_seg[2] = 614; // ISHARP LBA PWL for Seg 2. INPUT value in U0.10 format + dscl_prog_data->isharp_lba.base_seg[2] = 63; // ISHARP LBA PWL for Seg 2. BASE value in U0.6 format + dscl_prog_data->isharp_lba.slope_seg[2] = 0x1EC; // ISHARP LBA for Seg 2. SLOPE value in S5.3 format = -20 + // ISHARP_LBA_PWL_SEG3: ISHARP LBA PWL Segment 3 + dscl_prog_data->isharp_lba.in_seg[3] = 1023; // ISHARP LBA PWL for Seg 3.INPUT value in U0.10 format + dscl_prog_data->isharp_lba.base_seg[3] = 0; // ISHARP LBA PWL for Seg 3. BASE value in U0.6 format + dscl_prog_data->isharp_lba.slope_seg[3] = 0; // ISHARP LBA for Seg 3. SLOPE value in S5.3 format + // ISHARP_LBA_PWL_SEG4: ISHARP LBA PWL Segment 4 + dscl_prog_data->isharp_lba.in_seg[4] = 1023; // ISHARP LBA PWL for Seg 4.INPUT value in U0.10 format + dscl_prog_data->isharp_lba.base_seg[4] = 0; // ISHARP LBA PWL for Seg 4. BASE value in U0.6 format + dscl_prog_data->isharp_lba.slope_seg[4] = 0; // ISHARP LBA for Seg 4. SLOPE value in S5.3 format + // ISHARP_LBA_PWL_SEG5: ISHARP LBA PWL Segment 5 + dscl_prog_data->isharp_lba.in_seg[5] = 1023; // ISHARP LBA PWL for Seg 5.INPUT value in U0.10 format + dscl_prog_data->isharp_lba.base_seg[5] = 0; // ISHARP LBA PWL for Seg 5. BASE value in U0.6 format } + spl_build_isharp_1dlut_from_reference_curve(ratio, setup, adp_sharpness.sharpness); + dscl_prog_data->isharp_delta = spl_get_pregen_filter_isharp_1D_lut(setup); + // Program the nldelta soft clip values if (lls_pref == LLS_PREF_YES) { dscl_prog_data->isharp_nldelta_sclip.enable_p = 0; /* ISHARP_NLDELTA_SCLIP_EN_P */ @@ -1346,62 +1631,7 @@ static void spl_set_isharp_data(struct dscl_prog_data *dscl_prog_data, } // Set the values as per lookup table -#ifdef CONFIG_DRM_AMD_DC_FP spl_set_blur_scale_data(dscl_prog_data, data); -#endif -} -static bool spl_get_isharp_en(struct adaptive_sharpness adp_sharpness, - int vscale_ratio, int hscale_ratio, struct spl_taps taps, - enum spl_pixel_format format) -{ - bool enable_isharp = false; - - if (adp_sharpness.enable == false) - return enable_isharp; // Return if adaptive sharpness is disabled - // Is downscaling ? - if (vscale_ratio > 1 || hscale_ratio > 1) { - // END - No iSHARP support for downscaling - return enable_isharp; - } - // Scaling is up to 1:1 (no scaling) or upscaling - - /* Only apply sharpness to NV12 and not P010 */ - if (format != SPL_PIXEL_FORMAT_420BPP8) - return enable_isharp; - - // LB support horizontal taps 4,6 or vertical taps 3, 4, 6 - if (taps.h_taps == 4 || taps.h_taps == 6 || - taps.v_taps == 3 || taps.v_taps == 4 || taps.v_taps == 6) { - // END - iSHARP supported - enable_isharp = true; - } - return enable_isharp; -} - -static bool spl_choose_lls_policy(enum spl_pixel_format format, - enum spl_transfer_func_type tf_type, - enum spl_transfer_func_predefined tf_predefined_type, - enum linear_light_scaling *lls_pref) -{ - if (spl_is_yuv420(format)) { - *lls_pref = LLS_PREF_NO; - if ((tf_type == SPL_TF_TYPE_PREDEFINED) || (tf_type == SPL_TF_TYPE_DISTRIBUTED_POINTS)) - return true; - } else { /* RGB or YUV444 */ - if (tf_type == SPL_TF_TYPE_PREDEFINED) { - if ((tf_predefined_type == SPL_TRANSFER_FUNCTION_HLG) || - (tf_predefined_type == SPL_TRANSFER_FUNCTION_HLG12)) - *lls_pref = LLS_PREF_NO; - else - *lls_pref = LLS_PREF_YES; - return true; - } else if (tf_type == SPL_TF_TYPE_BYPASS) { - *lls_pref = LLS_PREF_YES; - return true; - } - } - *lls_pref = LLS_PREF_NO; - return false; } /* Calculate scaler parameters */ @@ -1410,67 +1640,74 @@ bool spl_calculate_scaler_params(struct spl_in *spl_in, struct spl_out *spl_out) bool res = false; bool enable_easf_v = false; bool enable_easf_h = false; - bool lls_enable_easf = true; int vratio = 0; int hratio = 0; - const struct spl_scaler_data *data = &spl_out->scl_data; + struct spl_scratch spl_scratch; + struct spl_fixed31_32 isharp_scale_ratio; + enum system_setup setup; + bool enable_isharp = false; + const struct spl_scaler_data *data = &spl_scratch.scl_data; + + memset(&spl_scratch, 0, sizeof(struct spl_scratch)); + spl_scratch.scl_data.h_active = spl_in->h_active; + spl_scratch.scl_data.v_active = spl_in->v_active; + // All SPL calls /* recout calculation */ /* depends on h_active */ - spl_calculate_recout(spl_in, spl_out); + spl_calculate_recout(spl_in, &spl_scratch, spl_out); /* depends on pixel format */ - spl_calculate_scaling_ratios(spl_in, spl_out); + spl_calculate_scaling_ratios(spl_in, &spl_scratch, spl_out); /* depends on scaling ratios and recout, does not calculate offset yet */ - spl_calculate_viewport_size(spl_in, spl_out); + spl_calculate_viewport_size(spl_in, &spl_scratch); res = spl_get_optimal_number_of_taps( spl_in->basic_out.max_downscale_src_width, spl_in, - spl_out, &spl_in->scaling_quality); + &spl_scratch, &spl_in->scaling_quality, &enable_easf_v, + &enable_easf_h, &enable_isharp); /* * Depends on recout, scaling ratios, h_active and taps * May need to re-check lb size after this in some obscure scenario */ if (res) - spl_calculate_inits_and_viewports(spl_in, spl_out); + spl_calculate_inits_and_viewports(spl_in, &spl_scratch); // Handle 3d recout - spl_handle_3d_recout(spl_in, &spl_out->scl_data.recout); + spl_handle_3d_recout(spl_in, &spl_scratch.scl_data.recout); // Clamp - spl_clamp_viewport(&spl_out->scl_data.viewport); + spl_clamp_viewport(&spl_scratch.scl_data.viewport); if (!res) return res; - /* - * If lls_pref is LLS_PREF_DONT_CARE, then use pixel format and transfer - * function to determine whether to use LINEAR or NONLINEAR scaling - */ - if (spl_in->lls_pref == LLS_PREF_DONT_CARE) - lls_enable_easf = spl_choose_lls_policy(spl_in->basic_in.format, - spl_in->basic_in.tf_type, spl_in->basic_in.tf_predefined_type, - &spl_in->lls_pref); - // Save all calculated parameters in dscl_prog_data structure to program hw registers - spl_set_dscl_prog_data(spl_in, spl_out); + spl_set_dscl_prog_data(spl_in, &spl_scratch, spl_out, enable_easf_v, enable_easf_h, enable_isharp); - vratio = dc_fixpt_ceil(spl_out->scl_data.ratios.vert); - hratio = dc_fixpt_ceil(spl_out->scl_data.ratios.horz); - if (!lls_enable_easf || spl_in->disable_easf) { - enable_easf_v = false; - enable_easf_h = false; + if (spl_in->lls_pref == LLS_PREF_YES) { + if (spl_in->is_hdr_on) + setup = HDR_L; + else + setup = SDR_L; } else { - /* Enable EASF on vertical? */ - enable_easf_v = enable_easf(vratio, spl_out->scl_data.taps.v_taps, spl_in->lls_pref, spl_in->prefer_easf); - /* Enable EASF on horizontal? */ - enable_easf_h = enable_easf(hratio, spl_out->scl_data.taps.h_taps, spl_in->lls_pref, spl_in->prefer_easf); + if (spl_in->is_hdr_on) + setup = HDR_NL; + else + setup = SDR_NL; } + // Set EASF - spl_set_easf_data(spl_out->dscl_prog_data, enable_easf_v, enable_easf_h, spl_in->lls_pref, - spl_in->basic_in.format); + spl_set_easf_data(&spl_scratch, spl_out, enable_easf_v, enable_easf_h, spl_in->lls_pref, + spl_in->basic_in.format, setup); + // Set iSHARP - bool enable_isharp = spl_get_isharp_en(spl_in->adaptive_sharpness, vratio, hratio, - spl_out->scl_data.taps, spl_in->basic_in.format); + vratio = spl_fixpt_ceil(spl_scratch.scl_data.ratios.vert); + hratio = spl_fixpt_ceil(spl_scratch.scl_data.ratios.horz); + if (vratio <= hratio) + isharp_scale_ratio = spl_scratch.scl_data.recip_ratios.vert; + else + isharp_scale_ratio = spl_scratch.scl_data.recip_ratios.horz; + spl_set_isharp_data(spl_out->dscl_prog_data, spl_in->adaptive_sharpness, enable_isharp, - spl_in->lls_pref, spl_in->basic_in.format, data); + spl_in->lls_pref, spl_in->basic_in.format, data, isharp_scale_ratio, setup); return res; } diff --git a/drivers/gpu/drm/amd/display/dc/spl/dc_spl_filters.c b/drivers/gpu/drm/amd/display/dc/spl/dc_spl_filters.c new file mode 100644 index 0000000000000..99238644e0a11 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/spl/dc_spl_filters.c @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2024 Advanced Micro Devices, Inc. + +#include "dc_spl_filters.h" + +void convert_filter_s1_10_to_s1_12(const uint16_t *s1_10_filter, + uint16_t *s1_12_filter, int num_taps) +{ + int num_entries = NUM_PHASES_COEFF * num_taps; + int i; + + for (i = 0; i < num_entries; i++) + *(s1_12_filter + i) = *(s1_10_filter + i) * 4; +} diff --git a/drivers/gpu/drm/amd/display/dc/spl/dc_spl_filters.h b/drivers/gpu/drm/amd/display/dc/spl/dc_spl_filters.h new file mode 100644 index 0000000000000..20439cdbdb105 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/spl/dc_spl_filters.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: MIT */ + +/* Copyright 2024 Advanced Micro Devices, Inc. */ + +#ifndef __DC_SPL_FILTERS_H__ +#define __DC_SPL_FILTERS_H__ + +#include "dc_spl_types.h" + +#define NUM_PHASES_COEFF 33 + +void convert_filter_s1_10_to_s1_12(const uint16_t *s1_10_filter, + uint16_t *s1_12_filter, int num_taps); + +#endif /* __DC_SPL_FILTERS_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/spl/dc_spl_isharp_filters.c b/drivers/gpu/drm/amd/display/dc/spl/dc_spl_isharp_filters.c index a5d9a6223d061..8e4bcba2932a6 100644 --- a/drivers/gpu/drm/amd/display/dc/spl/dc_spl_isharp_filters.c +++ b/drivers/gpu/drm/amd/display/dc/spl/dc_spl_isharp_filters.c @@ -2,6 +2,8 @@ // // Copyright 2024 Advanced Micro Devices, Inc. +#include "spl_debug.h" +#include "dc_spl_filters.h" #include "dc_spl_isharp_filters.h" //======================================== @@ -15,7 +17,7 @@ // C_start = 40.000000 // C_end = 64.000000 //======================================== -static const uint32_t filter_isharp_1D_lut_0[32] = { +static const uint32_t filter_isharp_1D_lut_0[ISHARP_LUT_TABLE_SIZE] = { 0x02010000, 0x0A070503, 0x1614100D, @@ -61,7 +63,7 @@ static const uint32_t filter_isharp_1D_lut_0[32] = { // C_end = 127.000000 //======================================== -static const uint32_t filter_isharp_1D_lut_0p5x[32] = { +static const uint32_t filter_isharp_1D_lut_0p5x[ISHARP_LUT_TABLE_SIZE] = { 0x00000000, 0x02020101, 0x06050403, @@ -106,7 +108,7 @@ static const uint32_t filter_isharp_1D_lut_0p5x[32] = { // C_start = 96.000000 // C_end = 127.000000 //======================================== -static const uint32_t filter_isharp_1D_lut_1p0x[32] = { +static const uint32_t filter_isharp_1D_lut_1p0x[ISHARP_LUT_TABLE_SIZE] = { 0x01000000, 0x05040302, 0x0B0A0806, @@ -151,7 +153,7 @@ static const uint32_t filter_isharp_1D_lut_1p0x[32] = { // C_start = 96.000000 // C_end = 127.000000 //======================================== -static const uint32_t filter_isharp_1D_lut_1p5x[32] = { +static const uint32_t filter_isharp_1D_lut_1p5x[ISHARP_LUT_TABLE_SIZE] = { 0x01010000, 0x07050402, 0x110F0C0A, @@ -196,7 +198,7 @@ static const uint32_t filter_isharp_1D_lut_1p5x[32] = { // C_start = 40.000000 // C_end = 127.000000 //======================================== -static const uint32_t filter_isharp_1D_lut_2p0x[32] = { +static const uint32_t filter_isharp_1D_lut_2p0x[ISHARP_LUT_TABLE_SIZE] = { 0x02010000, 0x0A070503, 0x1614100D, @@ -230,6 +232,53 @@ static const uint32_t filter_isharp_1D_lut_2p0x[32] = { 0x080B0D0E, 0x00020406, }; +//======================================== +// Delta Gain 1DLUT +// LUT content is packed as 4-bytes into one DWORD/entry +// A_start = 0.000000 +// A_end = 10.000000 +// A_gain = 3.000000 +// B_start = 11.000000 +// B_end = 127.000000 +// C_start = 40.000000 +// C_end = 127.000000 +//======================================== +static const uint32_t filter_isharp_1D_lut_3p0x[ISHARP_LUT_TABLE_SIZE] = { +0x03010000, +0x0F0B0805, +0x211E1813, +0x2B292624, +0x3533302E, +0x3E3C3A37, +0x46444240, +0x4D4B4A48, +0x5352504F, +0x59575655, +0x5D5C5B5A, +0x61605F5E, +0x64646362, +0x66666565, +0x68686767, +0x68686868, +0x68686868, +0x67676868, +0x65656666, +0x62636464, +0x5E5F6061, +0x5A5B5C5D, +0x55565759, +0x4F505253, +0x484A4B4D, +0x40424446, +0x373A3C3E, +0x2E303335, +0x2426292B, +0x191B1E21, +0x0D101316, +0x0003060A, +}; + +//======================================== // Wide scaler coefficients //======================================================== // gen_scaler_coeffs.m @@ -284,7 +333,7 @@ static const uint16_t filter_isharp_wide_6tap_64p[198] = { // Blur & Scale LPF // S1.10 //======================================================== -static const uint16_t filter_isharp_bs_4tap_64p[198] = { +static const uint16_t filter_isharp_bs_4tap_in_6_64p[198] = { 0x0000, 0x00E5, 0x0237, 0x00E4, 0x0000, 0x0000, 0x0000, 0x00DE, 0x0237, 0x00EB, 0x0000, 0x0000, 0x0000, 0x00D7, 0x0236, 0x00F2, 0x0001, 0x0000, @@ -319,6 +368,246 @@ static const uint16_t filter_isharp_bs_4tap_64p[198] = { 0x0000, 0x003B, 0x01CF, 0x01C2, 0x0034, 0x0000, 0x0000, 0x0037, 0x01C9, 0x01C9, 0x0037, 0x0000 }; +//======================================================== +// gen_BlurScale_coeffs.m +// 25-Apr-2022 +// 4 +// 64 +// Blur & Scale LPF +// S1.10 +//======================================================== +static const uint16_t filter_isharp_bs_4tap_64p[132] = { +0x00E5, 0x0237, 0x00E4, 0x0000, +0x00DE, 0x0237, 0x00EB, 0x0000, +0x00D7, 0x0236, 0x00F2, 0x0001, +0x00D0, 0x0235, 0x00FA, 0x0001, +0x00C9, 0x0234, 0x0101, 0x0002, +0x00C2, 0x0233, 0x0108, 0x0003, +0x00BB, 0x0232, 0x0110, 0x0003, +0x00B5, 0x0230, 0x0117, 0x0004, +0x00AE, 0x022E, 0x011F, 0x0005, +0x00A8, 0x022C, 0x0126, 0x0006, +0x00A2, 0x022A, 0x012D, 0x0007, +0x009C, 0x0228, 0x0134, 0x0008, +0x0096, 0x0225, 0x013C, 0x0009, +0x0090, 0x0222, 0x0143, 0x000B, +0x008A, 0x021F, 0x014B, 0x000C, +0x0085, 0x021C, 0x0151, 0x000E, +0x007F, 0x0218, 0x015A, 0x000F, +0x007A, 0x0215, 0x0160, 0x0011, +0x0074, 0x0211, 0x0168, 0x0013, +0x006F, 0x020D, 0x016F, 0x0015, +0x006A, 0x0209, 0x0176, 0x0017, +0x0065, 0x0204, 0x017E, 0x0019, +0x0060, 0x0200, 0x0185, 0x001B, +0x005C, 0x01FB, 0x018C, 0x001D, +0x0057, 0x01F6, 0x0193, 0x0020, +0x0053, 0x01F1, 0x019A, 0x0022, +0x004E, 0x01EC, 0x01A1, 0x0025, +0x004A, 0x01E6, 0x01A8, 0x0028, +0x0046, 0x01E1, 0x01AF, 0x002A, +0x0042, 0x01DB, 0x01B6, 0x002D, +0x003F, 0x01D5, 0x01BB, 0x0031, +0x003B, 0x01CF, 0x01C2, 0x0034, +0x0037, 0x01C9, 0x01C9, 0x0037, +}; +//======================================================== +// gen_BlurScale_coeffs.m +// 09-Jun-2022 +// 3 +// 64 +// Blur & Scale LPF +// S1.10 +//======================================================== +static const uint16_t filter_isharp_bs_3tap_64p[99] = { +0x0200, 0x0200, 0x0000, +0x01F6, 0x0206, 0x0004, +0x01EC, 0x020B, 0x0009, +0x01E2, 0x0211, 0x000D, +0x01D8, 0x0216, 0x0012, +0x01CE, 0x021C, 0x0016, +0x01C4, 0x0221, 0x001B, +0x01BA, 0x0226, 0x0020, +0x01B0, 0x022A, 0x0026, +0x01A6, 0x022F, 0x002B, +0x019C, 0x0233, 0x0031, +0x0192, 0x0238, 0x0036, +0x0188, 0x023C, 0x003C, +0x017E, 0x0240, 0x0042, +0x0174, 0x0244, 0x0048, +0x016A, 0x0248, 0x004E, +0x0161, 0x024A, 0x0055, +0x0157, 0x024E, 0x005B, +0x014D, 0x0251, 0x0062, +0x0144, 0x0253, 0x0069, +0x013A, 0x0256, 0x0070, +0x0131, 0x0258, 0x0077, +0x0127, 0x025B, 0x007E, +0x011E, 0x025C, 0x0086, +0x0115, 0x025E, 0x008D, +0x010B, 0x0260, 0x0095, +0x0102, 0x0262, 0x009C, +0x00F9, 0x0263, 0x00A4, +0x00F0, 0x0264, 0x00AC, +0x00E7, 0x0265, 0x00B4, +0x00DF, 0x0264, 0x00BD, +0x00D6, 0x0265, 0x00C5, +0x00CD, 0x0266, 0x00CD, +}; + +/* Converted Blur & Scale coeff tables from S1.10 to S1.12 */ +static uint16_t filter_isharp_bs_4tap_in_6_64p_s1_12[198]; +static uint16_t filter_isharp_bs_4tap_64p_s1_12[132]; +static uint16_t filter_isharp_bs_3tap_64p_s1_12[99]; + +struct scale_ratio_to_sharpness_level_lookup scale_to_sharp_sdr_nl[3][6] = { + { /* LOW */ + {1125, 1000, 75, 100}, + {11, 10, 6, 10}, + {1075, 1000, 45, 100}, + {105, 100, 3, 10}, + {1025, 1000, 15, 100}, + {1, 1, 0, 1}, + }, + { /* MID */ + {1125, 1000, 2, 1}, + {11, 10, 175, 100}, + {1075, 1000, 15, 10}, + {105, 100, 125, 100}, + {1025, 1000, 1, 1}, + {1, 1, 75, 100}, + }, + { /* HIGH */ + {1125, 1000, 35, 10}, + {11, 10, 32, 10}, + {1075, 1000, 29, 10}, + {105, 100, 26, 10}, + {1025, 1000, 23, 10}, + {1, 1, 2, 1}, + }, +}; + +struct scale_ratio_to_sharpness_level_lookup scale_to_sharp_sdr_l[3][6] = { + { /* LOW */ + {1125, 1000, 75, 100}, + {11, 10, 6, 10}, + {1075, 1000, 45, 100}, + {105, 100, 3, 10}, + {1025, 1000, 15, 100}, + {1, 1, 0, 1}, + }, + { /* MID */ + {1125, 1000, 15, 10}, + {11, 10, 135, 100}, + {1075, 1000, 12, 10}, + {105, 100, 105, 100}, + {1025, 1000, 9, 10}, + {1, 1, 75, 100}, + }, + { /* HIGH */ + {1125, 1000, 25, 10}, + {11, 10, 23, 10}, + {1075, 1000, 21, 10}, + {105, 100, 19, 10}, + {1025, 1000, 17, 10}, + {1, 1, 15, 10}, + }, +}; + +struct scale_ratio_to_sharpness_level_lookup scale_to_sharp_hdr_nl[3][6] = { + { /* LOW */ + {1125, 1000, 5, 10}, + {11, 10, 4, 10}, + {1075, 1000, 3, 10}, + {105, 100, 2, 10}, + {1025, 1000, 1, 10}, + {1, 1, 0, 1}, + }, + { /* MID */ + {1125, 1000, 1, 1}, + {11, 10, 9, 10}, + {1075, 1000, 8, 10}, + {105, 100, 7, 10}, + {1025, 1000, 6, 10}, + {1, 1, 5, 10}, + }, + { /* HIGH */ + {1125, 1000, 15, 10}, + {11, 10, 14, 10}, + {1075, 1000, 13, 10}, + {105, 100, 12, 10}, + {1025, 1000, 11, 10}, + {1, 1, 1, 1}, + }, +}; + +struct scale_ratio_to_sharpness_level_lookup scale_to_sharp_hdr_l[3][6] = { + { /* LOW */ + {1125, 1000, 75, 100}, + {11, 10, 6, 10}, + {1075, 1000, 45, 100}, + {105, 100, 3, 10}, + {1025, 1000, 15, 100}, + {1, 1, 0, 1}, + }, + { /* MID */ + {1125, 1000, 15, 10}, + {11, 10, 135, 100}, + {1075, 1000, 12, 10}, + {105, 100, 105, 100}, + {1025, 1000, 9, 10}, + {1, 1, 75, 100}, + }, + { /* HIGH */ + {1125, 1000, 25, 10}, + {11, 10, 23, 10}, + {1075, 1000, 21, 10}, + {105, 100, 19, 10}, + {1025, 1000, 17, 10}, + {1, 1, 15, 10}, + }, +}; + +/* Pre-generated 1DLUT for given setup and sharpness level */ +struct isharp_1D_lut_pregen filter_isharp_1D_lut_pregen[NUM_SHARPNESS_SETUPS] = { + { + 0, 0, + { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + } + }, + { + 0, 0, + { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + } + }, + { + 0, 0, + { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + } + }, + { + 0, 0, + { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + } + }, +}; + const uint32_t *spl_get_filter_isharp_1D_lut_0(void) { return filter_isharp_1D_lut_0; @@ -339,11 +628,166 @@ const uint32_t *spl_get_filter_isharp_1D_lut_2p0x(void) { return filter_isharp_1D_lut_2p0x; } +const uint32_t *spl_get_filter_isharp_1D_lut_3p0x(void) +{ + return filter_isharp_1D_lut_3p0x; +} const uint16_t *spl_get_filter_isharp_wide_6tap_64p(void) { return filter_isharp_wide_6tap_64p; } -const uint16_t *spl_get_filter_isharp_bs_4tap_64p(void) +uint16_t *spl_get_filter_isharp_bs_4tap_in_6_64p(void) +{ + return filter_isharp_bs_4tap_in_6_64p_s1_12; +} +uint16_t *spl_get_filter_isharp_bs_4tap_64p(void) +{ + return filter_isharp_bs_4tap_64p_s1_12; +} +uint16_t *spl_get_filter_isharp_bs_3tap_64p(void) { - return filter_isharp_bs_4tap_64p; + return filter_isharp_bs_3tap_64p_s1_12; } + +void spl_build_isharp_1dlut_from_reference_curve(struct spl_fixed31_32 ratio, enum system_setup setup, enum explicit_sharpness sharpness) +{ + uint8_t *byte_ptr_1dlut_src, *byte_ptr_1dlut_dst; + struct spl_fixed31_32 sharp_base, sharp_calc, sharp_level, ratio_level; + int j; + struct scale_ratio_to_sharpness_level_lookup *setup_lookup_ptr; + int num_sharp_ramp_levels; + int size_1dlut; + int sharp_calc_int; + uint32_t filter_pregen_store[ISHARP_LUT_TABLE_SIZE]; + + /* + * Given scaling ratio, setup and sharpness, build pregenerated + * 1DLUT tables + * + * Based on setup ( HDR/SDR, L/NL ), get base scale ratio to + * sharpness curve + */ + switch (setup) { + case HDR_L: + setup_lookup_ptr = scale_to_sharp_hdr_l[sharpness]; + num_sharp_ramp_levels = sizeof(scale_to_sharp_hdr_l[sharpness])/ + sizeof(struct scale_ratio_to_sharpness_level_lookup); + break; + case HDR_NL: + setup_lookup_ptr = scale_to_sharp_hdr_nl[sharpness]; + num_sharp_ramp_levels = sizeof(scale_to_sharp_hdr_nl[sharpness])/ + sizeof(struct scale_ratio_to_sharpness_level_lookup); + break; + case SDR_L: + setup_lookup_ptr = scale_to_sharp_sdr_l[sharpness]; + num_sharp_ramp_levels = sizeof(scale_to_sharp_sdr_l[sharpness])/ + sizeof(struct scale_ratio_to_sharpness_level_lookup); + break; + case SDR_NL: + default: + setup_lookup_ptr = scale_to_sharp_sdr_nl[sharpness]; + num_sharp_ramp_levels = sizeof(scale_to_sharp_sdr_nl[sharpness])/ + sizeof(struct scale_ratio_to_sharpness_level_lookup); + break; + } + + /* + * Compare desired scaling ratio and find adjusted sharpness from + * base scale ratio to sharpness curve + */ + j = 0; + sharp_level = spl_fixpt_zero; + while (j < num_sharp_ramp_levels) { + ratio_level = spl_fixpt_from_fraction(setup_lookup_ptr->ratio_numer, + setup_lookup_ptr->ratio_denom); + if (ratio.value >= ratio_level.value) { + sharp_level = spl_fixpt_from_fraction(setup_lookup_ptr->sharpness_numer, + setup_lookup_ptr->sharpness_denom); + break; + } + setup_lookup_ptr++; + j++; + } + + /* + * Check if pregen 1dlut table is already precalculated + * If numer/denom is different, then recalculate + */ + if ((filter_isharp_1D_lut_pregen[setup].sharpness_numer == setup_lookup_ptr->sharpness_numer) && + (filter_isharp_1D_lut_pregen[setup].sharpness_denom == setup_lookup_ptr->sharpness_denom)) + return; + + /* + * Calculate LUT_128_gained with this equation: + * + * LUT_128_gained[i] = (uint8)(0.5 + min(255,(double)(LUT_128[i])*sharpLevel/iGain)) + * where LUT_128[i] is contents of 3p0x isharp 1dlut + * where sharpLevel is desired sharpness level + * where iGain is base sharpness level 3.0 + * where LUT_128_gained[i] is adjusted 1dlut value based on desired sharpness level + */ + byte_ptr_1dlut_src = (uint8_t *)filter_isharp_1D_lut_3p0x; + byte_ptr_1dlut_dst = (uint8_t *)filter_pregen_store; + size_1dlut = sizeof(filter_isharp_1D_lut_3p0x); + memset(byte_ptr_1dlut_dst, 0, size_1dlut); + for (j = 0; j < size_1dlut; j++) { + sharp_base = spl_fixpt_from_int((int)*byte_ptr_1dlut_src); + sharp_calc = spl_fixpt_mul(sharp_base, sharp_level); + sharp_calc = spl_fixpt_div(sharp_calc, spl_fixpt_from_int(3)); + sharp_calc = spl_fixpt_min(spl_fixpt_from_int(255), sharp_calc); + sharp_calc = spl_fixpt_add(sharp_calc, spl_fixpt_from_fraction(1, 2)); + sharp_calc_int = spl_fixpt_floor(sharp_calc); + if (sharp_calc_int > 255) + sharp_calc_int = 255; + *byte_ptr_1dlut_dst = (uint8_t)sharp_calc_int; + + byte_ptr_1dlut_src++; + byte_ptr_1dlut_dst++; + } + + /* Update 1dlut table and sharpness level */ + memcpy((void *)filter_isharp_1D_lut_pregen[setup].value, (void *)filter_pregen_store, size_1dlut); + filter_isharp_1D_lut_pregen[setup].sharpness_numer = setup_lookup_ptr->sharpness_numer; + filter_isharp_1D_lut_pregen[setup].sharpness_denom = setup_lookup_ptr->sharpness_denom; +} + +uint32_t *spl_get_pregen_filter_isharp_1D_lut(enum system_setup setup) +{ + return filter_isharp_1D_lut_pregen[setup].value; +} + +void spl_init_blur_scale_coeffs(void) +{ + convert_filter_s1_10_to_s1_12(filter_isharp_bs_3tap_64p, + filter_isharp_bs_3tap_64p_s1_12, 3); + convert_filter_s1_10_to_s1_12(filter_isharp_bs_4tap_64p, + filter_isharp_bs_4tap_64p_s1_12, 4); + convert_filter_s1_10_to_s1_12(filter_isharp_bs_4tap_in_6_64p, + filter_isharp_bs_4tap_in_6_64p_s1_12, 6); +} + +uint16_t *spl_dscl_get_blur_scale_coeffs_64p(int taps) +{ + if (taps == 3) + return spl_get_filter_isharp_bs_3tap_64p(); + else if (taps == 4) + return spl_get_filter_isharp_bs_4tap_64p(); + else if (taps == 6) + return spl_get_filter_isharp_bs_4tap_in_6_64p(); + else { + /* should never happen, bug */ + SPL_BREAK_TO_DEBUGGER(); + return NULL; + } +} + +void spl_set_blur_scale_data(struct dscl_prog_data *dscl_prog_data, + const struct spl_scaler_data *data) +{ + dscl_prog_data->filter_blur_scale_h = + spl_dscl_get_blur_scale_coeffs_64p(data->taps.h_taps); + + dscl_prog_data->filter_blur_scale_v = + spl_dscl_get_blur_scale_coeffs_64p(data->taps.v_taps); +} + diff --git a/drivers/gpu/drm/amd/display/dc/spl/dc_spl_isharp_filters.h b/drivers/gpu/drm/amd/display/dc/spl/dc_spl_isharp_filters.h index 1aaf4c50c1bc2..3d023a154a92e 100644 --- a/drivers/gpu/drm/amd/display/dc/spl/dc_spl_isharp_filters.h +++ b/drivers/gpu/drm/amd/display/dc/spl/dc_spl_isharp_filters.h @@ -7,11 +7,44 @@ #include "dc_spl_types.h" +#define ISHARP_LUT_TABLE_SIZE 32 const uint32_t *spl_get_filter_isharp_1D_lut_0(void); const uint32_t *spl_get_filter_isharp_1D_lut_0p5x(void); const uint32_t *spl_get_filter_isharp_1D_lut_1p0x(void); const uint32_t *spl_get_filter_isharp_1D_lut_1p5x(void); const uint32_t *spl_get_filter_isharp_1D_lut_2p0x(void); -const uint16_t *spl_get_filter_isharp_bs_4tap_64p(void); +const uint32_t *spl_get_filter_isharp_1D_lut_3p0x(void); +uint16_t *spl_get_filter_isharp_bs_4tap_in_6_64p(void); +uint16_t *spl_get_filter_isharp_bs_4tap_64p(void); +uint16_t *spl_get_filter_isharp_bs_3tap_64p(void); const uint16_t *spl_get_filter_isharp_wide_6tap_64p(void); +uint16_t *spl_dscl_get_blur_scale_coeffs_64p(int taps); + +struct scale_ratio_to_sharpness_level_lookup { + unsigned int ratio_numer; + unsigned int ratio_denom; + unsigned int sharpness_numer; + unsigned int sharpness_denom; +}; + +struct isharp_1D_lut_pregen { + unsigned int sharpness_numer; + unsigned int sharpness_denom; + uint32_t value[ISHARP_LUT_TABLE_SIZE]; +}; + +enum system_setup { + SDR_NL = 0, + SDR_L, + HDR_NL, + HDR_L, + NUM_SHARPNESS_SETUPS +}; + +void spl_init_blur_scale_coeffs(void); +void spl_set_blur_scale_data(struct dscl_prog_data *dscl_prog_data, + const struct spl_scaler_data *data); + +void spl_build_isharp_1dlut_from_reference_curve(struct spl_fixed31_32 ratio, enum system_setup setup, enum explicit_sharpness sharpness); +uint32_t *spl_get_pregen_filter_isharp_1D_lut(enum system_setup setup); #endif /* __DC_SPL_ISHARP_FILTERS_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/spl/dc_spl_scl_easf_filters.c b/drivers/gpu/drm/amd/display/dc/spl/dc_spl_scl_easf_filters.c new file mode 100644 index 0000000000000..09bf82f7d4688 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/spl/dc_spl_scl_easf_filters.c @@ -0,0 +1,1726 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2024 Advanced Micro Devices, Inc. + +#include "spl_debug.h" +#include "dc_spl_filters.h" +#include "dc_spl_scl_filters.h" +#include "dc_spl_scl_easf_filters.h" + +//======================================================== +// gen_scaler_coeffs_cnf_file.m +// make_test_script.m +// 03-Apr-2024 +// 3t_64p_LanczosEd_p_0.3_p_10qb_ +// 3 +// 64 +// input/output = 0.300000000000 +// LanczosEd +// S1.10 +//======================================================== +static const uint16_t easf_filter_3tap_64p_ratio_0_30[99] = { + 0x0200, 0x0200, 0x0000, + 0x01F6, 0x0206, 0x0004, + 0x01EC, 0x020B, 0x0009, + 0x01E2, 0x0211, 0x000D, + 0x01D8, 0x0216, 0x0012, + 0x01CE, 0x021C, 0x0016, + 0x01C4, 0x0221, 0x001B, + 0x01BA, 0x0226, 0x0020, + 0x01B0, 0x022A, 0x0026, + 0x01A6, 0x022F, 0x002B, + 0x019C, 0x0233, 0x0031, + 0x0192, 0x0238, 0x0036, + 0x0188, 0x023C, 0x003C, + 0x017E, 0x0240, 0x0042, + 0x0174, 0x0244, 0x0048, + 0x016A, 0x0248, 0x004E, + 0x0161, 0x024A, 0x0055, + 0x0157, 0x024E, 0x005B, + 0x014D, 0x0251, 0x0062, + 0x0144, 0x0253, 0x0069, + 0x013A, 0x0256, 0x0070, + 0x0131, 0x0258, 0x0077, + 0x0127, 0x025B, 0x007E, + 0x011E, 0x025C, 0x0086, + 0x0115, 0x025E, 0x008D, + 0x010B, 0x0260, 0x0095, + 0x0102, 0x0262, 0x009C, + 0x00F9, 0x0263, 0x00A4, + 0x00F0, 0x0264, 0x00AC, + 0x00E7, 0x0265, 0x00B4, + 0x00DF, 0x0264, 0x00BD, + 0x00D6, 0x0265, 0x00C5, + 0x00CD, 0x0266, 0x00CD, +}; + +//======================================================== +// gen_scaler_coeffs_cnf_file.m +// make_test_script.m +// 03-Apr-2024 +// 3t_64p_LanczosEd_p_0.4_p_10qb_ +// 3 +// 64 +// input/output = 0.400000000000 +// LanczosEd +// S1.10 +//======================================================== +static const uint16_t easf_filter_3tap_64p_ratio_0_40[99] = { + 0x0200, 0x0200, 0x0000, + 0x01F6, 0x0206, 0x0004, + 0x01EB, 0x020E, 0x0007, + 0x01E1, 0x0214, 0x000B, + 0x01D7, 0x021A, 0x000F, + 0x01CD, 0x0220, 0x0013, + 0x01C2, 0x0226, 0x0018, + 0x01B8, 0x022C, 0x001C, + 0x01AE, 0x0231, 0x0021, + 0x01A3, 0x0237, 0x0026, + 0x0199, 0x023C, 0x002B, + 0x018F, 0x0240, 0x0031, + 0x0185, 0x0245, 0x0036, + 0x017A, 0x024A, 0x003C, + 0x0170, 0x024F, 0x0041, + 0x0166, 0x0253, 0x0047, + 0x015C, 0x0257, 0x004D, + 0x0152, 0x025A, 0x0054, + 0x0148, 0x025E, 0x005A, + 0x013E, 0x0261, 0x0061, + 0x0134, 0x0264, 0x0068, + 0x012B, 0x0266, 0x006F, + 0x0121, 0x0269, 0x0076, + 0x0117, 0x026C, 0x007D, + 0x010E, 0x026E, 0x0084, + 0x0104, 0x0270, 0x008C, + 0x00FB, 0x0271, 0x0094, + 0x00F2, 0x0272, 0x009C, + 0x00E9, 0x0273, 0x00A4, + 0x00E0, 0x0274, 0x00AC, + 0x00D7, 0x0275, 0x00B4, + 0x00CE, 0x0275, 0x00BD, + 0x00C5, 0x0276, 0x00C5, +}; + +//======================================================== +// gen_scaler_coeffs_cnf_file.m +// make_test_script.m +// 03-Apr-2024 +// 3t_64p_LanczosEd_p_0.5_p_10qb_ +// 3 +// 64 +// input/output = 0.500000000000 +// LanczosEd +// S1.10 +//======================================================== +static const uint16_t easf_filter_3tap_64p_ratio_0_50[99] = { + 0x0200, 0x0200, 0x0000, + 0x01F5, 0x0209, 0x0002, + 0x01EA, 0x0211, 0x0005, + 0x01DF, 0x021A, 0x0007, + 0x01D4, 0x0222, 0x000A, + 0x01C9, 0x022A, 0x000D, + 0x01BE, 0x0232, 0x0010, + 0x01B3, 0x0239, 0x0014, + 0x01A8, 0x0241, 0x0017, + 0x019D, 0x0248, 0x001B, + 0x0192, 0x024F, 0x001F, + 0x0187, 0x0255, 0x0024, + 0x017C, 0x025C, 0x0028, + 0x0171, 0x0262, 0x002D, + 0x0166, 0x0268, 0x0032, + 0x015B, 0x026E, 0x0037, + 0x0150, 0x0273, 0x003D, + 0x0146, 0x0278, 0x0042, + 0x013B, 0x027D, 0x0048, + 0x0130, 0x0282, 0x004E, + 0x0126, 0x0286, 0x0054, + 0x011B, 0x028A, 0x005B, + 0x0111, 0x028D, 0x0062, + 0x0107, 0x0290, 0x0069, + 0x00FD, 0x0293, 0x0070, + 0x00F3, 0x0296, 0x0077, + 0x00E9, 0x0298, 0x007F, + 0x00DF, 0x029A, 0x0087, + 0x00D5, 0x029C, 0x008F, + 0x00CC, 0x029D, 0x0097, + 0x00C3, 0x029E, 0x009F, + 0x00BA, 0x029E, 0x00A8, + 0x00B1, 0x029E, 0x00B1, +}; + +//======================================================== +// gen_scaler_coeffs_cnf_file.m +// make_test_script.m +// 03-Apr-2024 +// 3t_64p_LanczosEd_p_0.6_p_10qb_ +// 3 +// 64 +// input/output = 0.600000000000 +// LanczosEd +// S1.10 +//======================================================== +static const uint16_t easf_filter_3tap_64p_ratio_0_60[99] = { + 0x0200, 0x0200, 0x0000, + 0x01F4, 0x020B, 0x0001, + 0x01E8, 0x0216, 0x0002, + 0x01DC, 0x0221, 0x0003, + 0x01D0, 0x022B, 0x0005, + 0x01C4, 0x0235, 0x0007, + 0x01B8, 0x0240, 0x0008, + 0x01AC, 0x0249, 0x000B, + 0x01A0, 0x0253, 0x000D, + 0x0194, 0x025C, 0x0010, + 0x0188, 0x0265, 0x0013, + 0x017C, 0x026E, 0x0016, + 0x0170, 0x0277, 0x0019, + 0x0164, 0x027F, 0x001D, + 0x0158, 0x0287, 0x0021, + 0x014C, 0x028F, 0x0025, + 0x0140, 0x0297, 0x0029, + 0x0135, 0x029D, 0x002E, + 0x0129, 0x02A4, 0x0033, + 0x011D, 0x02AB, 0x0038, + 0x0112, 0x02B0, 0x003E, + 0x0107, 0x02B5, 0x0044, + 0x00FC, 0x02BA, 0x004A, + 0x00F1, 0x02BF, 0x0050, + 0x00E6, 0x02C3, 0x0057, + 0x00DB, 0x02C7, 0x005E, + 0x00D1, 0x02CA, 0x0065, + 0x00C7, 0x02CC, 0x006D, + 0x00BD, 0x02CE, 0x0075, + 0x00B3, 0x02D0, 0x007D, + 0x00A9, 0x02D2, 0x0085, + 0x00A0, 0x02D2, 0x008E, + 0x0097, 0x02D2, 0x0097, +}; + +//======================================================== +// gen_scaler_coeffs_cnf_file.m +// make_test_script.m +// 03-Apr-2024 +// 3t_64p_LanczosEd_p_0.7_p_10qb_ +// 3 +// 64 +// input/output = 0.700000000000 +// LanczosEd +// S1.10 +//======================================================== +static const uint16_t easf_filter_3tap_64p_ratio_0_70[99] = { + 0x0200, 0x0200, 0x0000, + 0x01F3, 0x020D, 0x0000, + 0x01E5, 0x021B, 0x0000, + 0x01D8, 0x0228, 0x0000, + 0x01CB, 0x0235, 0x0000, + 0x01BD, 0x0243, 0x0000, + 0x01B0, 0x024F, 0x0001, + 0x01A2, 0x025C, 0x0002, + 0x0195, 0x0268, 0x0003, + 0x0187, 0x0275, 0x0004, + 0x017A, 0x0280, 0x0006, + 0x016D, 0x028C, 0x0007, + 0x015F, 0x0298, 0x0009, + 0x0152, 0x02A2, 0x000C, + 0x0145, 0x02AD, 0x000E, + 0x0138, 0x02B7, 0x0011, + 0x012B, 0x02C0, 0x0015, + 0x011E, 0x02CA, 0x0018, + 0x0111, 0x02D3, 0x001C, + 0x0105, 0x02DB, 0x0020, + 0x00F8, 0x02E3, 0x0025, + 0x00EC, 0x02EA, 0x002A, + 0x00E0, 0x02F1, 0x002F, + 0x00D5, 0x02F6, 0x0035, + 0x00C9, 0x02FC, 0x003B, + 0x00BE, 0x0301, 0x0041, + 0x00B3, 0x0305, 0x0048, + 0x00A8, 0x0309, 0x004F, + 0x009E, 0x030C, 0x0056, + 0x0094, 0x030E, 0x005E, + 0x008A, 0x0310, 0x0066, + 0x0081, 0x0310, 0x006F, + 0x0077, 0x0312, 0x0077, +}; + +//======================================================== +// gen_scaler_coeffs_cnf_file.m +// make_test_script.m +// 03-Apr-2024 +// 3t_64p_LanczosEd_p_0.8_p_10qb_ +// 3 +// 64 +// input/output = 0.800000000000 +// LanczosEd +// S1.10 +//======================================================== +static const uint16_t easf_filter_3tap_64p_ratio_0_80[99] = { + 0x0200, 0x0200, 0x0000, + 0x01F1, 0x0210, 0x0FFF, + 0x01E2, 0x0220, 0x0FFE, + 0x01D2, 0x0232, 0x0FFC, + 0x01C3, 0x0241, 0x0FFC, + 0x01B4, 0x0251, 0x0FFB, + 0x01A4, 0x0262, 0x0FFA, + 0x0195, 0x0271, 0x0FFA, + 0x0186, 0x0281, 0x0FF9, + 0x0176, 0x0291, 0x0FF9, + 0x0167, 0x02A0, 0x0FF9, + 0x0158, 0x02AE, 0x0FFA, + 0x0149, 0x02BD, 0x0FFA, + 0x013A, 0x02CB, 0x0FFB, + 0x012C, 0x02D7, 0x0FFD, + 0x011D, 0x02E5, 0x0FFE, + 0x010F, 0x02F1, 0x0000, + 0x0101, 0x02FD, 0x0002, + 0x00F3, 0x0308, 0x0005, + 0x00E5, 0x0313, 0x0008, + 0x00D8, 0x031D, 0x000B, + 0x00CB, 0x0326, 0x000F, + 0x00BE, 0x032F, 0x0013, + 0x00B2, 0x0337, 0x0017, + 0x00A6, 0x033E, 0x001C, + 0x009A, 0x0345, 0x0021, + 0x008F, 0x034A, 0x0027, + 0x0084, 0x034F, 0x002D, + 0x0079, 0x0353, 0x0034, + 0x006F, 0x0356, 0x003B, + 0x0065, 0x0358, 0x0043, + 0x005C, 0x0359, 0x004B, + 0x0053, 0x035A, 0x0053, +}; + +//======================================================== +// gen_scaler_coeffs_cnf_file.m +// make_test_script.m +// 03-Apr-2024 +// 3t_64p_LanczosEd_p_0.9_p_10qb_ +// 3 +// 64 +// input/output = 0.900000000000 +// LanczosEd +// S1.10 +//======================================================== +static const uint16_t easf_filter_3tap_64p_ratio_0_90[99] = { + 0x0200, 0x0200, 0x0000, + 0x01EE, 0x0214, 0x0FFE, + 0x01DC, 0x0228, 0x0FFC, + 0x01CA, 0x023C, 0x0FFA, + 0x01B9, 0x024F, 0x0FF8, + 0x01A7, 0x0262, 0x0FF7, + 0x0195, 0x0276, 0x0FF5, + 0x0183, 0x028A, 0x0FF3, + 0x0172, 0x029C, 0x0FF2, + 0x0160, 0x02AF, 0x0FF1, + 0x014F, 0x02C2, 0x0FEF, + 0x013E, 0x02D4, 0x0FEE, + 0x012D, 0x02E5, 0x0FEE, + 0x011C, 0x02F7, 0x0FED, + 0x010C, 0x0307, 0x0FED, + 0x00FB, 0x0318, 0x0FED, + 0x00EC, 0x0327, 0x0FED, + 0x00DC, 0x0336, 0x0FEE, + 0x00CD, 0x0344, 0x0FEF, + 0x00BE, 0x0352, 0x0FF0, + 0x00B0, 0x035E, 0x0FF2, + 0x00A2, 0x036A, 0x0FF4, + 0x0095, 0x0375, 0x0FF6, + 0x0088, 0x037F, 0x0FF9, + 0x007B, 0x0388, 0x0FFD, + 0x006F, 0x0391, 0x0000, + 0x0064, 0x0397, 0x0005, + 0x0059, 0x039D, 0x000A, + 0x004E, 0x03A3, 0x000F, + 0x0045, 0x03A6, 0x0015, + 0x003B, 0x03A9, 0x001C, + 0x0033, 0x03AA, 0x0023, + 0x002A, 0x03AC, 0x002A, +}; + +//======================================================== +// gen_scaler_coeffs_cnf_file.m +// make_test_script.m +// 03-Apr-2024 +// 3t_64p_LanczosEd_p_1_p_10qb_ +// 3 +// 64 +// input/output = 1.000000000000 +// LanczosEd +// S1.10 +//======================================================== +static const uint16_t easf_filter_3tap_64p_ratio_1_00[99] = { + 0x0200, 0x0200, 0x0000, + 0x01EB, 0x0217, 0x0FFE, + 0x01D5, 0x022F, 0x0FFC, + 0x01C0, 0x0247, 0x0FF9, + 0x01AB, 0x025E, 0x0FF7, + 0x0196, 0x0276, 0x0FF4, + 0x0181, 0x028D, 0x0FF2, + 0x016C, 0x02A5, 0x0FEF, + 0x0158, 0x02BB, 0x0FED, + 0x0144, 0x02D1, 0x0FEB, + 0x0130, 0x02E8, 0x0FE8, + 0x011C, 0x02FE, 0x0FE6, + 0x0109, 0x0313, 0x0FE4, + 0x00F6, 0x0328, 0x0FE2, + 0x00E4, 0x033C, 0x0FE0, + 0x00D2, 0x034F, 0x0FDF, + 0x00C0, 0x0363, 0x0FDD, + 0x00B0, 0x0374, 0x0FDC, + 0x009F, 0x0385, 0x0FDC, + 0x0090, 0x0395, 0x0FDB, + 0x0081, 0x03A4, 0x0FDB, + 0x0072, 0x03B3, 0x0FDB, + 0x0064, 0x03C0, 0x0FDC, + 0x0057, 0x03CC, 0x0FDD, + 0x004B, 0x03D6, 0x0FDF, + 0x003F, 0x03E0, 0x0FE1, + 0x0034, 0x03E8, 0x0FE4, + 0x002A, 0x03EF, 0x0FE7, + 0x0020, 0x03F5, 0x0FEB, + 0x0017, 0x03FA, 0x0FEF, + 0x000F, 0x03FD, 0x0FF4, + 0x0007, 0x03FF, 0x0FFA, + 0x0000, 0x0400, 0x0000, +}; + +//======================================================== +// gen_scaler_coeffs_cnf_file.m +// make_test_script.m +// 03-Apr-2024 +// 4t_64p_LanczosEd_p_0.3_p_10qb_ +// 4 +// 64 +// input/output = 0.300000000000 +// LanczosEd +// S1.10 +//======================================================== +static const uint16_t easf_filter_4tap_64p_ratio_0_30[132] = { + 0x0104, 0x01F8, 0x0104, 0x0000, + 0x00FE, 0x01F7, 0x010A, 0x0001, + 0x00F8, 0x01F6, 0x010F, 0x0003, + 0x00F2, 0x01F5, 0x0114, 0x0005, + 0x00EB, 0x01F4, 0x011B, 0x0006, + 0x00E5, 0x01F3, 0x0120, 0x0008, + 0x00DF, 0x01F2, 0x0125, 0x000A, + 0x00DA, 0x01F0, 0x012A, 0x000C, + 0x00D4, 0x01EE, 0x0130, 0x000E, + 0x00CE, 0x01ED, 0x0135, 0x0010, + 0x00C8, 0x01EB, 0x013A, 0x0013, + 0x00C2, 0x01E9, 0x0140, 0x0015, + 0x00BD, 0x01E7, 0x0145, 0x0017, + 0x00B7, 0x01E5, 0x014A, 0x001A, + 0x00B1, 0x01E2, 0x0151, 0x001C, + 0x00AC, 0x01E0, 0x0155, 0x001F, + 0x00A7, 0x01DD, 0x015A, 0x0022, + 0x00A1, 0x01DB, 0x015F, 0x0025, + 0x009C, 0x01D8, 0x0165, 0x0027, + 0x0097, 0x01D5, 0x016A, 0x002A, + 0x0092, 0x01D2, 0x016E, 0x002E, + 0x008C, 0x01CF, 0x0174, 0x0031, + 0x0087, 0x01CC, 0x0179, 0x0034, + 0x0083, 0x01C9, 0x017D, 0x0037, + 0x007E, 0x01C5, 0x0182, 0x003B, + 0x0079, 0x01C2, 0x0187, 0x003E, + 0x0074, 0x01BE, 0x018C, 0x0042, + 0x0070, 0x01BA, 0x0190, 0x0046, + 0x006B, 0x01B7, 0x0195, 0x0049, + 0x0066, 0x01B3, 0x019A, 0x004D, + 0x0062, 0x01AF, 0x019E, 0x0051, + 0x005E, 0x01AB, 0x01A2, 0x0055, + 0x005A, 0x01A6, 0x01A6, 0x005A, +}; + +//======================================================== +// gen_scaler_coeffs_cnf_file.m +// make_test_script.m +// 03-Apr-2024 +// 4t_64p_LanczosEd_p_0.4_p_10qb_ +// 4 +// 64 +// input/output = 0.400000000000 +// LanczosEd +// S1.10 +//======================================================== +static const uint16_t easf_filter_4tap_64p_ratio_0_40[132] = { + 0x00FB, 0x0209, 0x00FC, 0x0000, + 0x00F5, 0x0209, 0x0101, 0x0001, + 0x00EE, 0x0208, 0x0108, 0x0002, + 0x00E8, 0x0207, 0x010E, 0x0003, + 0x00E2, 0x0206, 0x0114, 0x0004, + 0x00DB, 0x0205, 0x011A, 0x0006, + 0x00D5, 0x0204, 0x0120, 0x0007, + 0x00CF, 0x0203, 0x0125, 0x0009, + 0x00C9, 0x0201, 0x012C, 0x000A, + 0x00C3, 0x01FF, 0x0132, 0x000C, + 0x00BD, 0x01FD, 0x0138, 0x000E, + 0x00B7, 0x01FB, 0x013E, 0x0010, + 0x00B1, 0x01F9, 0x0144, 0x0012, + 0x00AC, 0x01F7, 0x0149, 0x0014, + 0x00A6, 0x01F4, 0x0150, 0x0016, + 0x00A0, 0x01F2, 0x0156, 0x0018, + 0x009B, 0x01EF, 0x015C, 0x001A, + 0x0095, 0x01EC, 0x0162, 0x001D, + 0x0090, 0x01E9, 0x0168, 0x001F, + 0x008B, 0x01E6, 0x016D, 0x0022, + 0x0085, 0x01E3, 0x0173, 0x0025, + 0x0080, 0x01DF, 0x0179, 0x0028, + 0x007B, 0x01DC, 0x017E, 0x002B, + 0x0076, 0x01D8, 0x0184, 0x002E, + 0x0071, 0x01D4, 0x018A, 0x0031, + 0x006D, 0x01D1, 0x018E, 0x0034, + 0x0068, 0x01CD, 0x0193, 0x0038, + 0x0063, 0x01C8, 0x019A, 0x003B, + 0x005F, 0x01C4, 0x019E, 0x003F, + 0x005B, 0x01C0, 0x01A3, 0x0042, + 0x0056, 0x01BB, 0x01A9, 0x0046, + 0x0052, 0x01B7, 0x01AD, 0x004A, + 0x004E, 0x01B2, 0x01B2, 0x004E, +}; + +//======================================================== +// gen_scaler_coeffs_cnf_file.m +// make_test_script.m +// 03-Apr-2024 +// 4t_64p_LanczosEd_p_0.5_p_10qb_ +// 4 +// 64 +// input/output = 0.500000000000 +// LanczosEd +// S1.10 +//======================================================== +static const uint16_t easf_filter_4tap_64p_ratio_0_50[132] = { + 0x00E5, 0x0236, 0x00E5, 0x0000, + 0x00DE, 0x0235, 0x00ED, 0x0000, + 0x00D7, 0x0235, 0x00F4, 0x0000, + 0x00D0, 0x0235, 0x00FB, 0x0000, + 0x00C9, 0x0234, 0x0102, 0x0001, + 0x00C2, 0x0233, 0x010A, 0x0001, + 0x00BC, 0x0232, 0x0111, 0x0001, + 0x00B5, 0x0230, 0x0119, 0x0002, + 0x00AE, 0x022F, 0x0121, 0x0002, + 0x00A8, 0x022D, 0x0128, 0x0003, + 0x00A2, 0x022B, 0x012F, 0x0004, + 0x009B, 0x0229, 0x0137, 0x0005, + 0x0095, 0x0226, 0x013F, 0x0006, + 0x008F, 0x0224, 0x0146, 0x0007, + 0x0089, 0x0221, 0x014E, 0x0008, + 0x0083, 0x021E, 0x0155, 0x000A, + 0x007E, 0x021B, 0x015C, 0x000B, + 0x0078, 0x0217, 0x0164, 0x000D, + 0x0072, 0x0213, 0x016D, 0x000E, + 0x006D, 0x0210, 0x0173, 0x0010, + 0x0068, 0x020C, 0x017A, 0x0012, + 0x0063, 0x0207, 0x0182, 0x0014, + 0x005E, 0x0203, 0x0189, 0x0016, + 0x0059, 0x01FE, 0x0191, 0x0018, + 0x0054, 0x01F9, 0x0198, 0x001B, + 0x0050, 0x01F4, 0x019F, 0x001D, + 0x004B, 0x01EF, 0x01A6, 0x0020, + 0x0047, 0x01EA, 0x01AC, 0x0023, + 0x0043, 0x01E4, 0x01B3, 0x0026, + 0x003F, 0x01DF, 0x01B9, 0x0029, + 0x003B, 0x01D9, 0x01C0, 0x002C, + 0x0037, 0x01D3, 0x01C6, 0x0030, + 0x0033, 0x01CD, 0x01CD, 0x0033, +}; + +//======================================================== +// gen_scaler_coeffs_cnf_file.m +// make_test_script.m +// 03-Apr-2024 +// 4t_64p_LanczosEd_p_0.6_p_10qb_ +// 4 +// 64 +// input/output = 0.600000000000 +// LanczosEd +// S1.10 +//======================================================== +static const uint16_t easf_filter_4tap_64p_ratio_0_60[132] = { + 0x00C8, 0x026F, 0x00C9, 0x0000, + 0x00C0, 0x0270, 0x00D1, 0x0FFF, + 0x00B8, 0x0270, 0x00D9, 0x0FFF, + 0x00B1, 0x0270, 0x00E1, 0x0FFE, + 0x00A9, 0x026F, 0x00EB, 0x0FFD, + 0x00A2, 0x026E, 0x00F3, 0x0FFD, + 0x009A, 0x026D, 0x00FD, 0x0FFC, + 0x0093, 0x026C, 0x0105, 0x0FFC, + 0x008C, 0x026A, 0x010F, 0x0FFB, + 0x0085, 0x0268, 0x0118, 0x0FFB, + 0x007E, 0x0265, 0x0122, 0x0FFB, + 0x0078, 0x0263, 0x012A, 0x0FFB, + 0x0071, 0x0260, 0x0134, 0x0FFB, + 0x006B, 0x025C, 0x013E, 0x0FFB, + 0x0065, 0x0259, 0x0147, 0x0FFB, + 0x005F, 0x0255, 0x0151, 0x0FFB, + 0x0059, 0x0251, 0x015A, 0x0FFC, + 0x0054, 0x024D, 0x0163, 0x0FFC, + 0x004E, 0x0248, 0x016D, 0x0FFD, + 0x0049, 0x0243, 0x0176, 0x0FFE, + 0x0044, 0x023E, 0x017F, 0x0FFF, + 0x003F, 0x0238, 0x0189, 0x0000, + 0x003A, 0x0232, 0x0193, 0x0001, + 0x0036, 0x022C, 0x019C, 0x0002, + 0x0031, 0x0226, 0x01A5, 0x0004, + 0x002D, 0x021F, 0x01AF, 0x0005, + 0x0029, 0x0218, 0x01B8, 0x0007, + 0x0025, 0x0211, 0x01C1, 0x0009, + 0x0022, 0x020A, 0x01C9, 0x000B, + 0x001E, 0x0203, 0x01D2, 0x000D, + 0x001B, 0x01FB, 0x01DA, 0x0010, + 0x0018, 0x01F3, 0x01E3, 0x0012, + 0x0015, 0x01EB, 0x01EB, 0x0015, +}; + +//======================================================== +// gen_scaler_coeffs_cnf_file.m +// make_test_script.m +// 03-Apr-2024 +// 4t_64p_LanczosEd_p_0.7_p_10qb_ +// 4 +// 64 +// input/output = 0.700000000000 +// LanczosEd +// S1.10 +//======================================================== +static const uint16_t easf_filter_4tap_64p_ratio_0_70[132] = { + 0x00A3, 0x02B9, 0x00A4, 0x0000, + 0x009A, 0x02BA, 0x00AD, 0x0FFF, + 0x0092, 0x02BA, 0x00B6, 0x0FFE, + 0x0089, 0x02BA, 0x00C1, 0x0FFC, + 0x0081, 0x02B9, 0x00CB, 0x0FFB, + 0x0079, 0x02B8, 0x00D5, 0x0FFA, + 0x0071, 0x02B7, 0x00DF, 0x0FF9, + 0x0069, 0x02B5, 0x00EA, 0x0FF8, + 0x0062, 0x02B3, 0x00F4, 0x0FF7, + 0x005B, 0x02B0, 0x00FF, 0x0FF6, + 0x0054, 0x02AD, 0x010B, 0x0FF4, + 0x004D, 0x02A9, 0x0117, 0x0FF3, + 0x0046, 0x02A5, 0x0123, 0x0FF2, + 0x0040, 0x02A1, 0x012D, 0x0FF2, + 0x003A, 0x029C, 0x0139, 0x0FF1, + 0x0034, 0x0297, 0x0145, 0x0FF0, + 0x002F, 0x0292, 0x0150, 0x0FEF, + 0x0029, 0x028C, 0x015C, 0x0FEF, + 0x0024, 0x0285, 0x0169, 0x0FEE, + 0x001F, 0x027F, 0x0174, 0x0FEE, + 0x001B, 0x0278, 0x017F, 0x0FEE, + 0x0016, 0x0270, 0x018D, 0x0FED, + 0x0012, 0x0268, 0x0199, 0x0FED, + 0x000E, 0x0260, 0x01A4, 0x0FEE, + 0x000B, 0x0258, 0x01AF, 0x0FEE, + 0x0007, 0x024F, 0x01BC, 0x0FEE, + 0x0004, 0x0246, 0x01C7, 0x0FEF, + 0x0001, 0x023D, 0x01D3, 0x0FEF, + 0x0FFE, 0x0233, 0x01DF, 0x0FF0, + 0x0FFC, 0x0229, 0x01EA, 0x0FF1, + 0x0FFA, 0x021F, 0x01F4, 0x0FF3, + 0x0FF8, 0x0215, 0x01FF, 0x0FF4, + 0x0FF6, 0x020A, 0x020A, 0x0FF6, +}; + +//======================================================== +// gen_scaler_coeffs_cnf_file.m +// make_test_script.m +// 03-Apr-2024 +// 4t_64p_LanczosEd_p_0.8_p_10qb_ +// 4 +// 64 +// input/output = 0.800000000000 +// LanczosEd +// S1.10 +//======================================================== +static const uint16_t easf_filter_4tap_64p_ratio_0_80[132] = { + 0x0075, 0x0315, 0x0076, 0x0000, + 0x006C, 0x0316, 0x007F, 0x0FFF, + 0x0062, 0x0316, 0x008A, 0x0FFE, + 0x0059, 0x0315, 0x0096, 0x0FFC, + 0x0050, 0x0314, 0x00A1, 0x0FFB, + 0x0048, 0x0312, 0x00AD, 0x0FF9, + 0x0040, 0x0310, 0x00B8, 0x0FF8, + 0x0038, 0x030D, 0x00C5, 0x0FF6, + 0x0030, 0x030A, 0x00D1, 0x0FF5, + 0x0029, 0x0306, 0x00DE, 0x0FF3, + 0x0022, 0x0301, 0x00EB, 0x0FF2, + 0x001C, 0x02FC, 0x00F8, 0x0FF0, + 0x0015, 0x02F7, 0x0106, 0x0FEE, + 0x0010, 0x02F1, 0x0112, 0x0FED, + 0x000A, 0x02EA, 0x0121, 0x0FEB, + 0x0005, 0x02E3, 0x012F, 0x0FE9, + 0x0000, 0x02DB, 0x013D, 0x0FE8, + 0x0FFB, 0x02D3, 0x014C, 0x0FE6, + 0x0FF7, 0x02CA, 0x015A, 0x0FE5, + 0x0FF3, 0x02C1, 0x0169, 0x0FE3, + 0x0FF0, 0x02B7, 0x0177, 0x0FE2, + 0x0FEC, 0x02AD, 0x0186, 0x0FE1, + 0x0FE9, 0x02A2, 0x0196, 0x0FDF, + 0x0FE7, 0x0297, 0x01A4, 0x0FDE, + 0x0FE4, 0x028C, 0x01B3, 0x0FDD, + 0x0FE2, 0x0280, 0x01C2, 0x0FDC, + 0x0FE0, 0x0274, 0x01D0, 0x0FDC, + 0x0FDF, 0x0268, 0x01DE, 0x0FDB, + 0x0FDD, 0x025B, 0x01EE, 0x0FDA, + 0x0FDC, 0x024E, 0x01FC, 0x0FDA, + 0x0FDB, 0x0241, 0x020A, 0x0FDA, + 0x0FDB, 0x0233, 0x0218, 0x0FDA, + 0x0FDA, 0x0226, 0x0226, 0x0FDA, +}; + +//======================================================== +// gen_scaler_coeffs_cnf_file.m +// make_test_script.m +// 03-Apr-2024 +// 4t_64p_LanczosEd_p_0.9_p_10qb_ +// 4 +// 64 +// input/output = 0.900000000000 +// LanczosEd +// S1.10 +//======================================================== +static const uint16_t easf_filter_4tap_64p_ratio_0_90[132] = { + 0x003F, 0x0383, 0x003E, 0x0000, + 0x0034, 0x0383, 0x004A, 0x0FFF, + 0x002B, 0x0383, 0x0054, 0x0FFE, + 0x0021, 0x0381, 0x0061, 0x0FFD, + 0x0019, 0x037F, 0x006C, 0x0FFC, + 0x0010, 0x037C, 0x0079, 0x0FFB, + 0x0008, 0x0378, 0x0086, 0x0FFA, + 0x0001, 0x0374, 0x0093, 0x0FF8, + 0x0FFA, 0x036E, 0x00A1, 0x0FF7, + 0x0FF3, 0x0368, 0x00B0, 0x0FF5, + 0x0FED, 0x0361, 0x00BF, 0x0FF3, + 0x0FE8, 0x035A, 0x00CD, 0x0FF1, + 0x0FE2, 0x0352, 0x00DC, 0x0FF0, + 0x0FDE, 0x0349, 0x00EB, 0x0FEE, + 0x0FD9, 0x033F, 0x00FC, 0x0FEC, + 0x0FD5, 0x0335, 0x010D, 0x0FE9, + 0x0FD2, 0x032A, 0x011D, 0x0FE7, + 0x0FCF, 0x031E, 0x012E, 0x0FE5, + 0x0FCC, 0x0312, 0x013F, 0x0FE3, + 0x0FCA, 0x0305, 0x0150, 0x0FE1, + 0x0FC8, 0x02F8, 0x0162, 0x0FDE, + 0x0FC6, 0x02EA, 0x0174, 0x0FDC, + 0x0FC5, 0x02DC, 0x0185, 0x0FDA, + 0x0FC4, 0x02CD, 0x0197, 0x0FD8, + 0x0FC3, 0x02BE, 0x01AA, 0x0FD5, + 0x0FC3, 0x02AF, 0x01BB, 0x0FD3, + 0x0FC3, 0x029F, 0x01CD, 0x0FD1, + 0x0FC3, 0x028E, 0x01E0, 0x0FCF, + 0x0FC3, 0x027E, 0x01F2, 0x0FCD, + 0x0FC4, 0x026D, 0x0203, 0x0FCC, + 0x0FC5, 0x025C, 0x0215, 0x0FCA, + 0x0FC6, 0x024B, 0x0227, 0x0FC8, + 0x0FC7, 0x0239, 0x0239, 0x0FC7, +}; + +//======================================================== +// gen_scaler_coeffs_cnf_file.m +// make_test_script.m +// 03-Apr-2024 +// 4t_64p_LanczosEd_p_1_p_10qb_ +// 4 +// 64 +// input/output = 1.000000000000 +// LanczosEd +// S1.10 +//======================================================== +static const uint16_t easf_filter_4tap_64p_ratio_1_00[132] = { + 0x0000, 0x0400, 0x0000, 0x0000, + 0x0FF6, 0x03FF, 0x000B, 0x0000, + 0x0FED, 0x03FE, 0x0015, 0x0000, + 0x0FE4, 0x03FB, 0x0022, 0x0FFF, + 0x0FDC, 0x03F7, 0x002E, 0x0FFF, + 0x0FD5, 0x03F2, 0x003B, 0x0FFE, + 0x0FCE, 0x03EC, 0x0048, 0x0FFE, + 0x0FC8, 0x03E5, 0x0056, 0x0FFD, + 0x0FC3, 0x03DC, 0x0065, 0x0FFC, + 0x0FBE, 0x03D3, 0x0075, 0x0FFA, + 0x0FB9, 0x03C9, 0x0085, 0x0FF9, + 0x0FB6, 0x03BE, 0x0094, 0x0FF8, + 0x0FB2, 0x03B2, 0x00A6, 0x0FF6, + 0x0FB0, 0x03A5, 0x00B7, 0x0FF4, + 0x0FAD, 0x0397, 0x00CA, 0x0FF2, + 0x0FAB, 0x0389, 0x00DC, 0x0FF0, + 0x0FAA, 0x0379, 0x00EF, 0x0FEE, + 0x0FA9, 0x0369, 0x0102, 0x0FEC, + 0x0FA9, 0x0359, 0x0115, 0x0FE9, + 0x0FA9, 0x0348, 0x0129, 0x0FE6, + 0x0FA9, 0x0336, 0x013D, 0x0FE4, + 0x0FA9, 0x0323, 0x0153, 0x0FE1, + 0x0FAA, 0x0310, 0x0168, 0x0FDE, + 0x0FAC, 0x02FD, 0x017C, 0x0FDB, + 0x0FAD, 0x02E9, 0x0192, 0x0FD8, + 0x0FAF, 0x02D5, 0x01A7, 0x0FD5, + 0x0FB1, 0x02C0, 0x01BD, 0x0FD2, + 0x0FB3, 0x02AC, 0x01D2, 0x0FCF, + 0x0FB5, 0x0296, 0x01E9, 0x0FCC, + 0x0FB8, 0x0281, 0x01FE, 0x0FC9, + 0x0FBA, 0x026C, 0x0214, 0x0FC6, + 0x0FBD, 0x0256, 0x022A, 0x0FC3, + 0x0FC0, 0x0240, 0x0240, 0x0FC0, +}; + +//======================================================== +// gen_scaler_coeffs_cnf_file.m +// make_test_script.m +// 02-Apr-2024 +// 6t_64p_LanczosEd_p_0.3_p_10qb_ +// 6 +// 64 +// input/output = 0.300000000000 +// LanczosEd +// S1.10 +//======================================================== +static const uint16_t easf_filter_6tap_64p_ratio_0_30[198] = { + 0x004B, 0x0100, 0x0169, 0x0101, 0x004B, 0x0000, + 0x0049, 0x00FD, 0x0169, 0x0103, 0x004E, 0x0000, + 0x0047, 0x00FA, 0x0169, 0x0106, 0x0050, 0x0000, + 0x0045, 0x00F7, 0x0168, 0x0109, 0x0052, 0x0001, + 0x0043, 0x00F5, 0x0168, 0x010B, 0x0054, 0x0001, + 0x0040, 0x00F2, 0x0168, 0x010E, 0x0057, 0x0001, + 0x003E, 0x00EF, 0x0168, 0x0110, 0x0059, 0x0002, + 0x003C, 0x00EC, 0x0167, 0x0113, 0x005C, 0x0002, + 0x003A, 0x00E9, 0x0167, 0x0116, 0x005E, 0x0002, + 0x0038, 0x00E6, 0x0166, 0x0118, 0x0061, 0x0003, + 0x0036, 0x00E3, 0x0165, 0x011C, 0x0063, 0x0003, + 0x0034, 0x00E0, 0x0165, 0x011D, 0x0066, 0x0004, + 0x0033, 0x00DD, 0x0164, 0x0120, 0x0068, 0x0004, + 0x0031, 0x00DA, 0x0163, 0x0122, 0x006B, 0x0005, + 0x002F, 0x00D7, 0x0163, 0x0125, 0x006D, 0x0005, + 0x002D, 0x00D3, 0x0162, 0x0128, 0x0070, 0x0006, + 0x002B, 0x00D0, 0x0161, 0x012A, 0x0073, 0x0007, + 0x002A, 0x00CD, 0x0160, 0x012D, 0x0075, 0x0007, + 0x0028, 0x00CA, 0x015F, 0x012F, 0x0078, 0x0008, + 0x0026, 0x00C7, 0x015E, 0x0131, 0x007B, 0x0009, + 0x0025, 0x00C4, 0x015D, 0x0133, 0x007E, 0x0009, + 0x0023, 0x00C1, 0x015C, 0x0136, 0x0080, 0x000A, + 0x0022, 0x00BE, 0x015A, 0x0138, 0x0083, 0x000B, + 0x0020, 0x00BB, 0x0159, 0x013A, 0x0086, 0x000C, + 0x001F, 0x00B8, 0x0158, 0x013B, 0x0089, 0x000D, + 0x001E, 0x00B5, 0x0156, 0x013E, 0x008C, 0x000D, + 0x001C, 0x00B2, 0x0155, 0x0140, 0x008F, 0x000E, + 0x001B, 0x00AF, 0x0153, 0x0143, 0x0091, 0x000F, + 0x0019, 0x00AC, 0x0152, 0x0145, 0x0094, 0x0010, + 0x0018, 0x00A9, 0x0150, 0x0147, 0x0097, 0x0011, + 0x0017, 0x00A6, 0x014F, 0x0148, 0x009A, 0x0012, + 0x0016, 0x00A3, 0x014D, 0x0149, 0x009D, 0x0014, + 0x0015, 0x00A0, 0x014B, 0x014B, 0x00A0, 0x0015, +}; + +//======================================================== +// gen_scaler_coeffs_cnf_file.m +// make_test_script.m +// 02-Apr-2024 +// 6t_64p_LanczosEd_p_0.4_p_10qb_ +// 6 +// 64 +// input/output = 0.400000000000 +// LanczosEd +// S1.10 +//======================================================== +static const uint16_t easf_filter_6tap_64p_ratio_0_40[198] = { + 0x0028, 0x0106, 0x01A3, 0x0107, 0x0028, 0x0000, + 0x0026, 0x0102, 0x01A3, 0x010A, 0x002B, 0x0000, + 0x0024, 0x00FE, 0x01A3, 0x010F, 0x002D, 0x0FFF, + 0x0022, 0x00FA, 0x01A3, 0x0113, 0x002F, 0x0FFF, + 0x0021, 0x00F6, 0x01A3, 0x0116, 0x0031, 0x0FFF, + 0x001F, 0x00F2, 0x01A2, 0x011B, 0x0034, 0x0FFE, + 0x001D, 0x00EE, 0x01A2, 0x011F, 0x0036, 0x0FFE, + 0x001B, 0x00EA, 0x01A1, 0x0123, 0x0039, 0x0FFE, + 0x0019, 0x00E6, 0x01A1, 0x0127, 0x003B, 0x0FFE, + 0x0018, 0x00E2, 0x01A0, 0x012A, 0x003E, 0x0FFE, + 0x0016, 0x00DE, 0x01A0, 0x012E, 0x0041, 0x0FFD, + 0x0015, 0x00DA, 0x019F, 0x0132, 0x0043, 0x0FFD, + 0x0013, 0x00D6, 0x019E, 0x0136, 0x0046, 0x0FFD, + 0x0012, 0x00D2, 0x019D, 0x0139, 0x0049, 0x0FFD, + 0x0010, 0x00CE, 0x019C, 0x013D, 0x004C, 0x0FFD, + 0x000F, 0x00CA, 0x019A, 0x0141, 0x004F, 0x0FFD, + 0x000E, 0x00C6, 0x0199, 0x0144, 0x0052, 0x0FFD, + 0x000D, 0x00C2, 0x0197, 0x0148, 0x0055, 0x0FFD, + 0x000B, 0x00BE, 0x0196, 0x014C, 0x0058, 0x0FFD, + 0x000A, 0x00BA, 0x0195, 0x014F, 0x005B, 0x0FFD, + 0x0009, 0x00B6, 0x0193, 0x0153, 0x005E, 0x0FFD, + 0x0008, 0x00B2, 0x0191, 0x0157, 0x0061, 0x0FFD, + 0x0007, 0x00AE, 0x0190, 0x015A, 0x0064, 0x0FFD, + 0x0006, 0x00AA, 0x018E, 0x015D, 0x0068, 0x0FFD, + 0x0005, 0x00A6, 0x018C, 0x0161, 0x006B, 0x0FFD, + 0x0005, 0x00A2, 0x0189, 0x0164, 0x006F, 0x0FFD, + 0x0004, 0x009E, 0x0187, 0x0167, 0x0072, 0x0FFE, + 0x0003, 0x009A, 0x0185, 0x016B, 0x0075, 0x0FFE, + 0x0002, 0x0096, 0x0183, 0x016E, 0x0079, 0x0FFE, + 0x0002, 0x0093, 0x0180, 0x016F, 0x007D, 0x0FFF, + 0x0001, 0x008F, 0x017E, 0x0173, 0x0080, 0x0FFF, + 0x0001, 0x008B, 0x017B, 0x0175, 0x0084, 0x0000, + 0x0000, 0x0087, 0x0179, 0x0179, 0x0087, 0x0000, +}; + +//======================================================== +// gen_scaler_coeffs_cnf_file.m +// make_test_script.m +// 02-Apr-2024 +// 6t_64p_LanczosEd_p_0.5_p_10qb_ +// 6 +// 64 +// input/output = 0.500000000000 +// LanczosEd +// S1.10 +//======================================================== +static const uint16_t easf_filter_6tap_64p_ratio_0_50[198] = { + 0x0000, 0x0107, 0x01F3, 0x0106, 0x0000, 0x0000, + 0x0FFE, 0x0101, 0x01F3, 0x010D, 0x0002, 0x0FFF, + 0x0FFD, 0x00FB, 0x01F3, 0x0113, 0x0003, 0x0FFF, + 0x0FFC, 0x00F6, 0x01F3, 0x0118, 0x0005, 0x0FFE, + 0x0FFA, 0x00F0, 0x01F3, 0x011E, 0x0007, 0x0FFE, + 0x0FF9, 0x00EB, 0x01F2, 0x0124, 0x0009, 0x0FFD, + 0x0FF8, 0x00E5, 0x01F2, 0x0129, 0x000B, 0x0FFD, + 0x0FF7, 0x00E0, 0x01F1, 0x012F, 0x000D, 0x0FFC, + 0x0FF6, 0x00DA, 0x01F0, 0x0135, 0x0010, 0x0FFB, + 0x0FF5, 0x00D4, 0x01EF, 0x013B, 0x0012, 0x0FFB, + 0x0FF4, 0x00CF, 0x01EE, 0x0141, 0x0014, 0x0FFA, + 0x0FF3, 0x00C9, 0x01ED, 0x0147, 0x0017, 0x0FF9, + 0x0FF2, 0x00C4, 0x01EB, 0x014C, 0x001A, 0x0FF9, + 0x0FF1, 0x00BF, 0x01EA, 0x0152, 0x001C, 0x0FF8, + 0x0FF1, 0x00B9, 0x01E8, 0x0157, 0x001F, 0x0FF8, + 0x0FF0, 0x00B4, 0x01E6, 0x015D, 0x0022, 0x0FF7, + 0x0FF0, 0x00AE, 0x01E4, 0x0163, 0x0025, 0x0FF6, + 0x0FEF, 0x00A9, 0x01E2, 0x0168, 0x0028, 0x0FF6, + 0x0FEF, 0x00A4, 0x01DF, 0x016E, 0x002B, 0x0FF5, + 0x0FEF, 0x009F, 0x01DD, 0x0172, 0x002E, 0x0FF5, + 0x0FEE, 0x009A, 0x01DA, 0x0178, 0x0032, 0x0FF4, + 0x0FEE, 0x0094, 0x01D8, 0x017E, 0x0035, 0x0FF3, + 0x0FEE, 0x008F, 0x01D5, 0x0182, 0x0039, 0x0FF3, + 0x0FEE, 0x008A, 0x01D2, 0x0188, 0x003C, 0x0FF2, + 0x0FEE, 0x0085, 0x01CF, 0x018C, 0x0040, 0x0FF2, + 0x0FEE, 0x0081, 0x01CB, 0x0191, 0x0044, 0x0FF1, + 0x0FEE, 0x007C, 0x01C8, 0x0196, 0x0047, 0x0FF1, + 0x0FEE, 0x0077, 0x01C4, 0x019C, 0x004B, 0x0FF0, + 0x0FEE, 0x0072, 0x01C1, 0x01A0, 0x004F, 0x0FF0, + 0x0FEE, 0x006E, 0x01BD, 0x01A4, 0x0053, 0x0FF0, + 0x0FEE, 0x0069, 0x01B9, 0x01A9, 0x0058, 0x0FEF, + 0x0FEE, 0x0065, 0x01B5, 0x01AD, 0x005C, 0x0FEF, + 0x0FEF, 0x0060, 0x01B1, 0x01B1, 0x0060, 0x0FEF, +}; + +//======================================================== +// gen_scaler_coeffs_cnf_file.m +// make_test_script.m +// 02-Apr-2024 +// 6t_64p_LanczosEd_p_0.6_p_10qb_ +// 6 +// 64 +// input/output = 0.600000000000 +// LanczosEd +// S1.10 +//======================================================== +static const uint16_t easf_filter_6tap_64p_ratio_0_60[198] = { + 0x0FD9, 0x00FB, 0x0258, 0x00FB, 0x0FD9, 0x0000, + 0x0FD9, 0x00F3, 0x0258, 0x0102, 0x0FDA, 0x0000, + 0x0FD8, 0x00EB, 0x0258, 0x010B, 0x0FDB, 0x0FFF, + 0x0FD8, 0x00E3, 0x0258, 0x0112, 0x0FDC, 0x0FFF, + 0x0FD8, 0x00DC, 0x0257, 0x011B, 0x0FDC, 0x0FFE, + 0x0FD7, 0x00D4, 0x0256, 0x0123, 0x0FDE, 0x0FFE, + 0x0FD7, 0x00CD, 0x0255, 0x012B, 0x0FDF, 0x0FFD, + 0x0FD7, 0x00C5, 0x0254, 0x0133, 0x0FE0, 0x0FFD, + 0x0FD7, 0x00BE, 0x0252, 0x013C, 0x0FE1, 0x0FFC, + 0x0FD7, 0x00B6, 0x0251, 0x0143, 0x0FE3, 0x0FFC, + 0x0FD8, 0x00AF, 0x024F, 0x014B, 0x0FE4, 0x0FFB, + 0x0FD8, 0x00A8, 0x024C, 0x0154, 0x0FE6, 0x0FFA, + 0x0FD8, 0x00A1, 0x024A, 0x015B, 0x0FE8, 0x0FFA, + 0x0FD9, 0x009A, 0x0247, 0x0163, 0x0FEA, 0x0FF9, + 0x0FD9, 0x0093, 0x0244, 0x016C, 0x0FEC, 0x0FF8, + 0x0FD9, 0x008C, 0x0241, 0x0174, 0x0FEF, 0x0FF7, + 0x0FDA, 0x0085, 0x023E, 0x017B, 0x0FF1, 0x0FF7, + 0x0FDB, 0x007F, 0x023A, 0x0183, 0x0FF3, 0x0FF6, + 0x0FDB, 0x0078, 0x0237, 0x018B, 0x0FF6, 0x0FF5, + 0x0FDC, 0x0072, 0x0233, 0x0192, 0x0FF9, 0x0FF4, + 0x0FDD, 0x006C, 0x022F, 0x0199, 0x0FFC, 0x0FF3, + 0x0FDD, 0x0065, 0x022A, 0x01A3, 0x0FFF, 0x0FF2, + 0x0FDE, 0x005F, 0x0226, 0x01AA, 0x0002, 0x0FF1, + 0x0FDF, 0x005A, 0x0221, 0x01B0, 0x0006, 0x0FF0, + 0x0FE0, 0x0054, 0x021C, 0x01B7, 0x0009, 0x0FF0, + 0x0FE1, 0x004E, 0x0217, 0x01BE, 0x000D, 0x0FEF, + 0x0FE2, 0x0048, 0x0212, 0x01C6, 0x0010, 0x0FEE, + 0x0FE3, 0x0043, 0x020C, 0x01CD, 0x0014, 0x0FED, + 0x0FE4, 0x003E, 0x0207, 0x01D3, 0x0018, 0x0FEC, + 0x0FE5, 0x0039, 0x0200, 0x01DA, 0x001D, 0x0FEB, + 0x0FE6, 0x0034, 0x01FA, 0x01E1, 0x0021, 0x0FEA, + 0x0FE7, 0x002F, 0x01F5, 0x01E7, 0x0025, 0x0FE9, + 0x0FE8, 0x002A, 0x01EE, 0x01EE, 0x002A, 0x0FE8, +}; + +//======================================================== +// gen_scaler_coeffs_cnf_file.m +// make_test_script.m +// 02-Apr-2024 +// 6t_64p_LanczosEd_p_0.7_p_10qb_ +// 6 +// 64 +// input/output = 0.700000000000 +// LanczosEd +// S1.10 +//======================================================== +static const uint16_t easf_filter_6tap_64p_ratio_0_70[198] = { + 0x0FC0, 0x00DA, 0x02CC, 0x00DA, 0x0FC0, 0x0000, + 0x0FC1, 0x00D0, 0x02CC, 0x00E4, 0x0FBF, 0x0000, + 0x0FC2, 0x00C6, 0x02CB, 0x00EF, 0x0FBE, 0x0000, + 0x0FC3, 0x00BC, 0x02CA, 0x00F9, 0x0FBE, 0x0000, + 0x0FC4, 0x00B2, 0x02C9, 0x0104, 0x0FBD, 0x0000, + 0x0FC5, 0x00A8, 0x02C7, 0x010F, 0x0FBD, 0x0000, + 0x0FC7, 0x009F, 0x02C5, 0x0119, 0x0FBC, 0x0000, + 0x0FC8, 0x0095, 0x02C3, 0x0124, 0x0FBC, 0x0000, + 0x0FC9, 0x008C, 0x02C0, 0x012F, 0x0FBC, 0x0000, + 0x0FCB, 0x0083, 0x02BD, 0x0139, 0x0FBC, 0x0000, + 0x0FCC, 0x007A, 0x02BA, 0x0144, 0x0FBC, 0x0000, + 0x0FCE, 0x0072, 0x02B6, 0x014D, 0x0FBD, 0x0000, + 0x0FD0, 0x0069, 0x02B2, 0x0159, 0x0FBD, 0x0FFF, + 0x0FD1, 0x0061, 0x02AD, 0x0164, 0x0FBE, 0x0FFF, + 0x0FD3, 0x0059, 0x02A9, 0x016E, 0x0FBF, 0x0FFE, + 0x0FD4, 0x0051, 0x02A4, 0x017A, 0x0FBF, 0x0FFE, + 0x0FD6, 0x0049, 0x029E, 0x0184, 0x0FC1, 0x0FFE, + 0x0FD8, 0x0042, 0x0299, 0x018E, 0x0FC2, 0x0FFD, + 0x0FD9, 0x003A, 0x0293, 0x019B, 0x0FC3, 0x0FFC, + 0x0FDB, 0x0033, 0x028D, 0x01A4, 0x0FC5, 0x0FFC, + 0x0FDC, 0x002D, 0x0286, 0x01AF, 0x0FC7, 0x0FFB, + 0x0FDE, 0x0026, 0x0280, 0x01BA, 0x0FC8, 0x0FFA, + 0x0FE0, 0x001F, 0x0279, 0x01C4, 0x0FCB, 0x0FF9, + 0x0FE1, 0x0019, 0x0272, 0x01CE, 0x0FCD, 0x0FF9, + 0x0FE3, 0x0013, 0x026A, 0x01D9, 0x0FCF, 0x0FF8, + 0x0FE4, 0x000D, 0x0263, 0x01E3, 0x0FD2, 0x0FF7, + 0x0FE6, 0x0008, 0x025B, 0x01EC, 0x0FD5, 0x0FF6, + 0x0FE7, 0x0002, 0x0253, 0x01F7, 0x0FD8, 0x0FF5, + 0x0FE9, 0x0FFD, 0x024A, 0x0202, 0x0FDB, 0x0FF3, + 0x0FEA, 0x0FF8, 0x0242, 0x020B, 0x0FDF, 0x0FF2, + 0x0FEC, 0x0FF3, 0x0239, 0x0215, 0x0FE2, 0x0FF1, + 0x0FED, 0x0FEF, 0x0230, 0x021E, 0x0FE6, 0x0FF0, + 0x0FEF, 0x0FEB, 0x0226, 0x0226, 0x0FEB, 0x0FEF, +}; + +//======================================================== +// gen_scaler_coeffs_cnf_file.m +// make_test_script.m +// 02-Apr-2024 +// 6t_64p_LanczosEd_p_0.8_p_10qb_ +// 6 +// 64 +// input/output = 0.800000000000 +// LanczosEd +// S1.10 +//======================================================== +static const uint16_t easf_filter_6tap_64p_ratio_0_80[198] = { + 0x0FBF, 0x00A1, 0x0340, 0x00A1, 0x0FBF, 0x0000, + 0x0FC1, 0x0095, 0x0340, 0x00AD, 0x0FBC, 0x0001, + 0x0FC4, 0x0089, 0x033E, 0x00BA, 0x0FBA, 0x0001, + 0x0FC6, 0x007D, 0x033D, 0x00C6, 0x0FB8, 0x0002, + 0x0FC9, 0x0072, 0x033A, 0x00D3, 0x0FB6, 0x0002, + 0x0FCC, 0x0067, 0x0338, 0x00DF, 0x0FB3, 0x0003, + 0x0FCE, 0x005C, 0x0334, 0x00EE, 0x0FB1, 0x0003, + 0x0FD1, 0x0051, 0x0331, 0x00FA, 0x0FAF, 0x0004, + 0x0FD3, 0x0047, 0x032D, 0x0108, 0x0FAD, 0x0004, + 0x0FD6, 0x003D, 0x0328, 0x0116, 0x0FAB, 0x0004, + 0x0FD8, 0x0033, 0x0323, 0x0123, 0x0FAA, 0x0005, + 0x0FDB, 0x002A, 0x031D, 0x0131, 0x0FA8, 0x0005, + 0x0FDD, 0x0021, 0x0317, 0x013F, 0x0FA7, 0x0005, + 0x0FDF, 0x0018, 0x0311, 0x014D, 0x0FA5, 0x0006, + 0x0FE2, 0x0010, 0x030A, 0x015A, 0x0FA4, 0x0006, + 0x0FE4, 0x0008, 0x0302, 0x0169, 0x0FA3, 0x0006, + 0x0FE6, 0x0000, 0x02FB, 0x0177, 0x0FA2, 0x0006, + 0x0FE8, 0x0FF9, 0x02F3, 0x0185, 0x0FA1, 0x0006, + 0x0FEB, 0x0FF1, 0x02EA, 0x0193, 0x0FA1, 0x0006, + 0x0FED, 0x0FEB, 0x02E1, 0x01A1, 0x0FA0, 0x0006, + 0x0FEE, 0x0FE4, 0x02D8, 0x01B0, 0x0FA0, 0x0006, + 0x0FF0, 0x0FDE, 0x02CE, 0x01BE, 0x0FA0, 0x0006, + 0x0FF2, 0x0FD8, 0x02C5, 0x01CB, 0x0FA0, 0x0006, + 0x0FF4, 0x0FD3, 0x02BA, 0x01D8, 0x0FA1, 0x0006, + 0x0FF6, 0x0FCD, 0x02B0, 0x01E7, 0x0FA1, 0x0005, + 0x0FF7, 0x0FC8, 0x02A5, 0x01F5, 0x0FA2, 0x0005, + 0x0FF9, 0x0FC4, 0x029A, 0x0202, 0x0FA3, 0x0004, + 0x0FFA, 0x0FC0, 0x028E, 0x0210, 0x0FA4, 0x0004, + 0x0FFB, 0x0FBC, 0x0283, 0x021D, 0x0FA6, 0x0003, + 0x0FFD, 0x0FB8, 0x0276, 0x022A, 0x0FA8, 0x0003, + 0x0FFE, 0x0FB4, 0x026B, 0x0237, 0x0FAA, 0x0002, + 0x0FFF, 0x0FB1, 0x025E, 0x0245, 0x0FAC, 0x0001, + 0x0000, 0x0FAE, 0x0252, 0x0252, 0x0FAE, 0x0000, +}; + +//======================================================== +// gen_scaler_coeffs_cnf_file.m +// make_test_script.m +// 02-Apr-2024 +// 6t_64p_LanczosEd_p_0.9_p_10qb_ +// 6 +// 64 +// input/output = 0.900000000000 +// LanczosEd +// S1.10 +//======================================================== +static const uint16_t easf_filter_6tap_64p_ratio_0_90[198] = { + 0x0FD8, 0x0055, 0x03A7, 0x0054, 0x0FD8, 0x0000, + 0x0FDB, 0x0047, 0x03A7, 0x0063, 0x0FD4, 0x0000, + 0x0FDF, 0x003B, 0x03A5, 0x006F, 0x0FD1, 0x0001, + 0x0FE2, 0x002E, 0x03A3, 0x007E, 0x0FCD, 0x0002, + 0x0FE5, 0x0022, 0x03A0, 0x008D, 0x0FCA, 0x0002, + 0x0FE8, 0x0017, 0x039D, 0x009B, 0x0FC6, 0x0003, + 0x0FEB, 0x000C, 0x0398, 0x00AC, 0x0FC2, 0x0003, + 0x0FEE, 0x0001, 0x0394, 0x00BA, 0x0FBF, 0x0004, + 0x0FF1, 0x0FF7, 0x038E, 0x00CA, 0x0FBB, 0x0005, + 0x0FF4, 0x0FED, 0x0388, 0x00DA, 0x0FB8, 0x0005, + 0x0FF6, 0x0FE4, 0x0381, 0x00EB, 0x0FB4, 0x0006, + 0x0FF9, 0x0FDB, 0x037A, 0x00FA, 0x0FB1, 0x0007, + 0x0FFB, 0x0FD3, 0x0372, 0x010B, 0x0FAD, 0x0008, + 0x0FFD, 0x0FCB, 0x0369, 0x011D, 0x0FAA, 0x0008, + 0x0000, 0x0FC3, 0x0360, 0x012E, 0x0FA6, 0x0009, + 0x0002, 0x0FBC, 0x0356, 0x013F, 0x0FA3, 0x000A, + 0x0003, 0x0FB6, 0x034C, 0x0150, 0x0FA0, 0x000B, + 0x0005, 0x0FB0, 0x0341, 0x0162, 0x0F9D, 0x000B, + 0x0007, 0x0FAA, 0x0336, 0x0173, 0x0F9A, 0x000C, + 0x0008, 0x0FA5, 0x032A, 0x0185, 0x0F97, 0x000D, + 0x000A, 0x0FA0, 0x031E, 0x0197, 0x0F94, 0x000D, + 0x000B, 0x0F9B, 0x0311, 0x01A9, 0x0F92, 0x000E, + 0x000C, 0x0F97, 0x0303, 0x01BC, 0x0F8F, 0x000F, + 0x000D, 0x0F94, 0x02F6, 0x01CD, 0x0F8D, 0x000F, + 0x000E, 0x0F91, 0x02E8, 0x01DE, 0x0F8B, 0x0010, + 0x000F, 0x0F8E, 0x02D9, 0x01F1, 0x0F89, 0x0010, + 0x0010, 0x0F8B, 0x02CA, 0x0202, 0x0F88, 0x0011, + 0x0010, 0x0F89, 0x02BB, 0x0214, 0x0F87, 0x0011, + 0x0011, 0x0F87, 0x02AB, 0x0226, 0x0F86, 0x0011, + 0x0011, 0x0F86, 0x029C, 0x0236, 0x0F85, 0x0012, + 0x0011, 0x0F85, 0x028B, 0x0249, 0x0F84, 0x0012, + 0x0012, 0x0F84, 0x027B, 0x0259, 0x0F84, 0x0012, + 0x0012, 0x0F84, 0x026A, 0x026A, 0x0F84, 0x0012, +}; + +//======================================================== +// gen_scaler_coeffs_cnf_file.m +// make_test_script.m +// 02-Apr-2024 +// 6t_64p_LanczosEd_p_1_p_10qb_ +// 6 +// 64 +// input/output = 1.000000000000 +// LanczosEd +// S1.10 +//======================================================== +static const uint16_t easf_filter_6tap_64p_ratio_1_00[198] = { + 0x0000, 0x0000, 0x0400, 0x0000, 0x0000, 0x0000, + 0x0003, 0x0FF3, 0x0400, 0x000D, 0x0FFD, 0x0000, + 0x0006, 0x0FE7, 0x03FE, 0x001C, 0x0FF9, 0x0000, + 0x0009, 0x0FDB, 0x03FC, 0x002B, 0x0FF5, 0x0000, + 0x000C, 0x0FD0, 0x03F9, 0x003A, 0x0FF1, 0x0000, + 0x000E, 0x0FC5, 0x03F5, 0x004A, 0x0FED, 0x0001, + 0x0011, 0x0FBB, 0x03F0, 0x005A, 0x0FE9, 0x0001, + 0x0013, 0x0FB2, 0x03EB, 0x006A, 0x0FE5, 0x0001, + 0x0015, 0x0FA9, 0x03E4, 0x007B, 0x0FE1, 0x0002, + 0x0017, 0x0FA1, 0x03DD, 0x008D, 0x0FDC, 0x0002, + 0x0018, 0x0F99, 0x03D4, 0x00A0, 0x0FD8, 0x0003, + 0x001A, 0x0F92, 0x03CB, 0x00B2, 0x0FD3, 0x0004, + 0x001B, 0x0F8C, 0x03C1, 0x00C6, 0x0FCE, 0x0004, + 0x001C, 0x0F86, 0x03B7, 0x00D9, 0x0FC9, 0x0005, + 0x001D, 0x0F80, 0x03AB, 0x00EE, 0x0FC4, 0x0006, + 0x001E, 0x0F7C, 0x039F, 0x0101, 0x0FBF, 0x0007, + 0x001F, 0x0F78, 0x0392, 0x0115, 0x0FBA, 0x0008, + 0x001F, 0x0F74, 0x0385, 0x012B, 0x0FB5, 0x0008, + 0x0020, 0x0F71, 0x0376, 0x0140, 0x0FB0, 0x0009, + 0x0020, 0x0F6E, 0x0367, 0x0155, 0x0FAB, 0x000B, + 0x0020, 0x0F6C, 0x0357, 0x016B, 0x0FA6, 0x000C, + 0x0020, 0x0F6A, 0x0347, 0x0180, 0x0FA2, 0x000D, + 0x0020, 0x0F69, 0x0336, 0x0196, 0x0F9D, 0x000E, + 0x0020, 0x0F69, 0x0325, 0x01AB, 0x0F98, 0x000F, + 0x001F, 0x0F68, 0x0313, 0x01C3, 0x0F93, 0x0010, + 0x001F, 0x0F69, 0x0300, 0x01D8, 0x0F8F, 0x0011, + 0x001E, 0x0F69, 0x02ED, 0x01EF, 0x0F8B, 0x0012, + 0x001D, 0x0F6A, 0x02D9, 0x0205, 0x0F87, 0x0014, + 0x001D, 0x0F6C, 0x02C5, 0x021A, 0x0F83, 0x0015, + 0x001C, 0x0F6E, 0x02B1, 0x0230, 0x0F7F, 0x0016, + 0x001B, 0x0F70, 0x029C, 0x0247, 0x0F7B, 0x0017, + 0x001A, 0x0F72, 0x0287, 0x025D, 0x0F78, 0x0018, + 0x0019, 0x0F75, 0x0272, 0x0272, 0x0F75, 0x0019, +}; + +/* Converted scaler coeff tables from S1.10 to S1.12 */ +static uint16_t easf_filter_3tap_64p_ratio_0_30_s1_12[99]; +static uint16_t easf_filter_3tap_64p_ratio_0_40_s1_12[99]; +static uint16_t easf_filter_3tap_64p_ratio_0_50_s1_12[99]; +static uint16_t easf_filter_3tap_64p_ratio_0_60_s1_12[99]; +static uint16_t easf_filter_3tap_64p_ratio_0_70_s1_12[99]; +static uint16_t easf_filter_3tap_64p_ratio_0_80_s1_12[99]; +static uint16_t easf_filter_3tap_64p_ratio_0_90_s1_12[99]; +static uint16_t easf_filter_3tap_64p_ratio_1_00_s1_12[99]; +static uint16_t easf_filter_4tap_64p_ratio_0_30_s1_12[132]; +static uint16_t easf_filter_4tap_64p_ratio_0_40_s1_12[132]; +static uint16_t easf_filter_4tap_64p_ratio_0_50_s1_12[132]; +static uint16_t easf_filter_4tap_64p_ratio_0_60_s1_12[132]; +static uint16_t easf_filter_4tap_64p_ratio_0_70_s1_12[132]; +static uint16_t easf_filter_4tap_64p_ratio_0_80_s1_12[132]; +static uint16_t easf_filter_4tap_64p_ratio_0_90_s1_12[132]; +static uint16_t easf_filter_4tap_64p_ratio_1_00_s1_12[132]; +static uint16_t easf_filter_6tap_64p_ratio_0_30_s1_12[198]; +static uint16_t easf_filter_6tap_64p_ratio_0_40_s1_12[198]; +static uint16_t easf_filter_6tap_64p_ratio_0_50_s1_12[198]; +static uint16_t easf_filter_6tap_64p_ratio_0_60_s1_12[198]; +static uint16_t easf_filter_6tap_64p_ratio_0_70_s1_12[198]; +static uint16_t easf_filter_6tap_64p_ratio_0_80_s1_12[198]; +static uint16_t easf_filter_6tap_64p_ratio_0_90_s1_12[198]; +static uint16_t easf_filter_6tap_64p_ratio_1_00_s1_12[198]; + +struct scale_ratio_to_reg_value_lookup easf_v_bf3_mode_lookup[] = { + {3, 10, 0x0000}, + {4, 10, 0x0000}, + {5, 10, 0x0000}, + {6, 10, 0x0000}, + {7, 10, 0x0000}, + {8, 10, 0x0000}, + {9, 10, 0x0000}, + {1, 1, 0x0000}, + {-1, -1, 0x0002}, +}; + +struct scale_ratio_to_reg_value_lookup easf_h_bf3_mode_lookup[] = { + {3, 10, 0x0000}, + {4, 10, 0x0000}, + {5, 10, 0x0000}, + {6, 10, 0x0000}, + {7, 10, 0x0000}, + {8, 10, 0x0000}, + {9, 10, 0x0000}, + {1, 1, 0x0000}, + {-1, -1, 0x0002}, +}; + +struct scale_ratio_to_reg_value_lookup easf_reducer_gain6_6tap_lookup[] = { + {3, 10, 0x4100}, + {4, 10, 0x4100}, + {5, 10, 0x4100}, + {6, 10, 0x4100}, + {7, 10, 0x4100}, + {8, 10, 0x4100}, + {9, 10, 0x4100}, + {1, 1, 0x4100}, + {-1, -1, 0x4100}, +}; + +struct scale_ratio_to_reg_value_lookup easf_reducer_gain4_6tap_lookup[] = { + {3, 10, 0x4000}, + {4, 10, 0x4000}, + {5, 10, 0x4000}, + {6, 10, 0x4000}, + {7, 10, 0x4000}, + {8, 10, 0x4000}, + {9, 10, 0x4000}, + {1, 1, 0x4000}, + {-1, -1, 0x4000}, +}; + +struct scale_ratio_to_reg_value_lookup easf_gain_ring6_6tap_lookup[] = { + {3, 10, 0x0000}, + {4, 10, 0x251F}, + {5, 10, 0x291F}, + {6, 10, 0xA51F}, + {7, 10, 0xA51F}, + {8, 10, 0xAA66}, + {9, 10, 0xA51F}, + {1, 1, 0xA640}, + {-1, -1, 0xA640}, +}; + +struct scale_ratio_to_reg_value_lookup easf_gain_ring4_6tap_lookup[] = { + {3, 10, 0x0000}, + {4, 10, 0x9600}, + {5, 10, 0xA460}, + {6, 10, 0xA8E0}, + {7, 10, 0xAC00}, + {8, 10, 0xAD20}, + {9, 10, 0xAFC0}, + {1, 1, 0xB058}, + {-1, -1, 0xB058}, +}; + +struct scale_ratio_to_reg_value_lookup easf_reducer_gain6_4tap_lookup[] = { + {3, 10, 0x4100}, + {4, 10, 0x4100}, + {5, 10, 0x4100}, + {6, 10, 0x4100}, + {7, 10, 0x4100}, + {8, 10, 0x4100}, + {9, 10, 0x4100}, + {1, 1, 0x4100}, + {-1, -1, 0x4100}, +}; + +struct scale_ratio_to_reg_value_lookup easf_reducer_gain4_4tap_lookup[] = { + {3, 10, 0x4000}, + {4, 10, 0x4000}, + {5, 10, 0x4000}, + {6, 10, 0x4000}, + {7, 10, 0x4000}, + {8, 10, 0x4000}, + {9, 10, 0x4000}, + {1, 1, 0x4000}, + {-1, -1, 0x4000}, +}; + +struct scale_ratio_to_reg_value_lookup easf_gain_ring6_4tap_lookup[] = { + {3, 10, 0x0000}, + {4, 10, 0x0000}, + {5, 10, 0x0000}, + {6, 10, 0x0000}, + {7, 10, 0x0000}, + {8, 10, 0x0000}, + {9, 10, 0x0000}, + {1, 1, 0x0000}, + {-1, -1, 0x0000}, +}; + +struct scale_ratio_to_reg_value_lookup easf_gain_ring4_4tap_lookup[] = { + {3, 10, 0x0000}, + {4, 10, 0x0000}, + {5, 10, 0x0000}, + {6, 10, 0x9900}, + {7, 10, 0xA100}, + {8, 10, 0xA8C0}, + {9, 10, 0xAB20}, + {1, 1, 0xAC00}, + {-1, -1, 0xAC00}, +}; + +struct scale_ratio_to_reg_value_lookup easf_3tap_dntilt_uptilt_offset_lookup[] = { + {3, 10, 0x0000}, + {4, 10, 0x0000}, + {5, 10, 0x0000}, + {6, 10, 0x0000}, + {7, 10, 0x0000}, + {8, 10, 0x4100}, + {9, 10, 0x9F00}, + {1, 1, 0xA4C0}, + {-1, -1, 0xA8D8}, +}; + +struct scale_ratio_to_reg_value_lookup easf_3tap_uptilt_maxval_lookup[] = { + {3, 10, 0x0000}, + {4, 10, 0x0000}, + {5, 10, 0x0000}, + {6, 10, 0x0000}, + {7, 10, 0x0000}, + {8, 10, 0x4000}, + {9, 10, 0x24FE}, + {1, 1, 0x2D64}, + {-1, -1, 0x3ADB}, +}; + +struct scale_ratio_to_reg_value_lookup easf_3tap_dntilt_slope_lookup[] = { + {3, 10, 0x3800}, + {4, 10, 0x3800}, + {5, 10, 0x3800}, + {6, 10, 0x3800}, + {7, 10, 0x3800}, + {8, 10, 0x3886}, + {9, 10, 0x3940}, + {1, 1, 0x3A4E}, + {-1, -1, 0x3B66}, +}; + +struct scale_ratio_to_reg_value_lookup easf_3tap_uptilt1_slope_lookup[] = { + {3, 10, 0x3800}, + {4, 10, 0x3800}, + {5, 10, 0x3800}, + {6, 10, 0x3800}, + {7, 10, 0x3800}, + {8, 10, 0x36F4}, + {9, 10, 0x359C}, + {1, 1, 0x3360}, + {-1, -1, 0x2F20}, +}; + +struct scale_ratio_to_reg_value_lookup easf_3tap_uptilt2_slope_lookup[] = { + {3, 10, 0x0000}, + {4, 10, 0x0000}, + {5, 10, 0x0000}, + {6, 10, 0x0000}, + {7, 10, 0x0000}, + {8, 10, 0x0000}, + {9, 10, 0x359C}, + {1, 1, 0x31F0}, + {-1, -1, 0x1F00}, +}; + +struct scale_ratio_to_reg_value_lookup easf_3tap_uptilt2_offset_lookup[] = { + {3, 10, 0x0000}, + {4, 10, 0x0000}, + {5, 10, 0x0000}, + {6, 10, 0x0000}, + {7, 10, 0x0000}, + {8, 10, 0x0000}, + {9, 10, 0x9F00}, + {1, 1, 0xA400}, + {-1, -1, 0x9E00}, +}; + +void spl_init_easf_filter_coeffs(void) +{ + convert_filter_s1_10_to_s1_12(easf_filter_3tap_64p_ratio_0_30, + easf_filter_3tap_64p_ratio_0_30_s1_12, 3); + convert_filter_s1_10_to_s1_12(easf_filter_3tap_64p_ratio_0_40, + easf_filter_3tap_64p_ratio_0_40_s1_12, 3); + convert_filter_s1_10_to_s1_12(easf_filter_3tap_64p_ratio_0_50, + easf_filter_3tap_64p_ratio_0_50_s1_12, 3); + convert_filter_s1_10_to_s1_12(easf_filter_3tap_64p_ratio_0_60, + easf_filter_3tap_64p_ratio_0_60_s1_12, 3); + convert_filter_s1_10_to_s1_12(easf_filter_3tap_64p_ratio_0_70, + easf_filter_3tap_64p_ratio_0_70_s1_12, 3); + convert_filter_s1_10_to_s1_12(easf_filter_3tap_64p_ratio_0_80, + easf_filter_3tap_64p_ratio_0_80_s1_12, 3); + convert_filter_s1_10_to_s1_12(easf_filter_3tap_64p_ratio_0_90, + easf_filter_3tap_64p_ratio_0_90_s1_12, 3); + convert_filter_s1_10_to_s1_12(easf_filter_3tap_64p_ratio_1_00, + easf_filter_3tap_64p_ratio_1_00_s1_12, 3); + + convert_filter_s1_10_to_s1_12(easf_filter_4tap_64p_ratio_0_30, + easf_filter_4tap_64p_ratio_0_30_s1_12, 4); + convert_filter_s1_10_to_s1_12(easf_filter_4tap_64p_ratio_0_40, + easf_filter_4tap_64p_ratio_0_40_s1_12, 4); + convert_filter_s1_10_to_s1_12(easf_filter_4tap_64p_ratio_0_50, + easf_filter_4tap_64p_ratio_0_50_s1_12, 4); + convert_filter_s1_10_to_s1_12(easf_filter_4tap_64p_ratio_0_60, + easf_filter_4tap_64p_ratio_0_60_s1_12, 4); + convert_filter_s1_10_to_s1_12(easf_filter_4tap_64p_ratio_0_70, + easf_filter_4tap_64p_ratio_0_70_s1_12, 4); + convert_filter_s1_10_to_s1_12(easf_filter_4tap_64p_ratio_0_80, + easf_filter_4tap_64p_ratio_0_80_s1_12, 4); + convert_filter_s1_10_to_s1_12(easf_filter_4tap_64p_ratio_0_90, + easf_filter_4tap_64p_ratio_0_90_s1_12, 4); + convert_filter_s1_10_to_s1_12(easf_filter_4tap_64p_ratio_1_00, + easf_filter_4tap_64p_ratio_1_00_s1_12, 4); + + convert_filter_s1_10_to_s1_12(easf_filter_6tap_64p_ratio_0_30, + easf_filter_6tap_64p_ratio_0_30_s1_12, 6); + convert_filter_s1_10_to_s1_12(easf_filter_6tap_64p_ratio_0_40, + easf_filter_6tap_64p_ratio_0_40_s1_12, 6); + convert_filter_s1_10_to_s1_12(easf_filter_6tap_64p_ratio_0_50, + easf_filter_6tap_64p_ratio_0_50_s1_12, 6); + convert_filter_s1_10_to_s1_12(easf_filter_6tap_64p_ratio_0_60, + easf_filter_6tap_64p_ratio_0_60_s1_12, 6); + convert_filter_s1_10_to_s1_12(easf_filter_6tap_64p_ratio_0_70, + easf_filter_6tap_64p_ratio_0_70_s1_12, 6); + convert_filter_s1_10_to_s1_12(easf_filter_6tap_64p_ratio_0_80, + easf_filter_6tap_64p_ratio_0_80_s1_12, 6); + convert_filter_s1_10_to_s1_12(easf_filter_6tap_64p_ratio_0_90, + easf_filter_6tap_64p_ratio_0_90_s1_12, 6); + convert_filter_s1_10_to_s1_12(easf_filter_6tap_64p_ratio_1_00, + easf_filter_6tap_64p_ratio_1_00_s1_12, 6); +} + +uint16_t *spl_get_easf_filter_3tap_64p(struct spl_fixed31_32 ratio) +{ + if (ratio.value < spl_fixpt_from_fraction(3, 10).value) + return easf_filter_3tap_64p_ratio_0_30_s1_12; + else if (ratio.value < spl_fixpt_from_fraction(4, 10).value) + return easf_filter_3tap_64p_ratio_0_40_s1_12; + else if (ratio.value < spl_fixpt_from_fraction(5, 10).value) + return easf_filter_3tap_64p_ratio_0_50_s1_12; + else if (ratio.value < spl_fixpt_from_fraction(6, 10).value) + return easf_filter_3tap_64p_ratio_0_60_s1_12; + else if (ratio.value < spl_fixpt_from_fraction(7, 10).value) + return easf_filter_3tap_64p_ratio_0_70_s1_12; + else if (ratio.value < spl_fixpt_from_fraction(8, 10).value) + return easf_filter_3tap_64p_ratio_0_80_s1_12; + else if (ratio.value < spl_fixpt_from_fraction(9, 10).value) + return easf_filter_3tap_64p_ratio_0_90_s1_12; + else + return easf_filter_3tap_64p_ratio_1_00_s1_12; +} + +uint16_t *spl_get_easf_filter_4tap_64p(struct spl_fixed31_32 ratio) +{ + if (ratio.value < spl_fixpt_from_fraction(3, 10).value) + return easf_filter_4tap_64p_ratio_0_30_s1_12; + else if (ratio.value < spl_fixpt_from_fraction(4, 10).value) + return easf_filter_4tap_64p_ratio_0_40_s1_12; + else if (ratio.value < spl_fixpt_from_fraction(5, 10).value) + return easf_filter_4tap_64p_ratio_0_50_s1_12; + else if (ratio.value < spl_fixpt_from_fraction(6, 10).value) + return easf_filter_4tap_64p_ratio_0_60_s1_12; + else if (ratio.value < spl_fixpt_from_fraction(7, 10).value) + return easf_filter_4tap_64p_ratio_0_70_s1_12; + else if (ratio.value < spl_fixpt_from_fraction(8, 10).value) + return easf_filter_4tap_64p_ratio_0_80_s1_12; + else if (ratio.value < spl_fixpt_from_fraction(9, 10).value) + return easf_filter_4tap_64p_ratio_0_90_s1_12; + else + return easf_filter_4tap_64p_ratio_1_00_s1_12; +} + +uint16_t *spl_get_easf_filter_6tap_64p(struct spl_fixed31_32 ratio) +{ + if (ratio.value < spl_fixpt_from_fraction(3, 10).value) + return easf_filter_6tap_64p_ratio_0_30_s1_12; + else if (ratio.value < spl_fixpt_from_fraction(4, 10).value) + return easf_filter_6tap_64p_ratio_0_40_s1_12; + else if (ratio.value < spl_fixpt_from_fraction(5, 10).value) + return easf_filter_6tap_64p_ratio_0_50_s1_12; + else if (ratio.value < spl_fixpt_from_fraction(6, 10).value) + return easf_filter_6tap_64p_ratio_0_60_s1_12; + else if (ratio.value < spl_fixpt_from_fraction(7, 10).value) + return easf_filter_6tap_64p_ratio_0_70_s1_12; + else if (ratio.value < spl_fixpt_from_fraction(8, 10).value) + return easf_filter_6tap_64p_ratio_0_80_s1_12; + else if (ratio.value < spl_fixpt_from_fraction(9, 10).value) + return easf_filter_6tap_64p_ratio_0_90_s1_12; + else + return easf_filter_6tap_64p_ratio_1_00_s1_12; +} + +uint16_t *spl_dscl_get_easf_filter_coeffs_64p(int taps, struct spl_fixed31_32 ratio) +{ + if (taps == 6) + return spl_get_easf_filter_6tap_64p(ratio); + else if (taps == 4) + return spl_get_easf_filter_4tap_64p(ratio); + else if (taps == 3) + return spl_get_easf_filter_3tap_64p(ratio); + else { + /* should never happen, bug */ + SPL_BREAK_TO_DEBUGGER(); + return NULL; + } +} + +void spl_set_filters_data(struct dscl_prog_data *dscl_prog_data, + const struct spl_scaler_data *data, bool enable_easf_v, + bool enable_easf_h) +{ + /* + * Old coefficients calculated scaling ratio = input / output + * New coefficients are calculated based on = output / input + */ + if (enable_easf_h) { + dscl_prog_data->filter_h = spl_dscl_get_easf_filter_coeffs_64p( + data->taps.h_taps, data->recip_ratios.horz); + + dscl_prog_data->filter_h_c = spl_dscl_get_easf_filter_coeffs_64p( + data->taps.h_taps_c, data->recip_ratios.horz_c); + } else { + dscl_prog_data->filter_h = spl_dscl_get_filter_coeffs_64p( + data->taps.h_taps, data->ratios.horz); + + dscl_prog_data->filter_h_c = spl_dscl_get_filter_coeffs_64p( + data->taps.h_taps_c, data->ratios.horz_c); + } + if (enable_easf_v) { + dscl_prog_data->filter_v = spl_dscl_get_easf_filter_coeffs_64p( + data->taps.v_taps, data->recip_ratios.vert); + + dscl_prog_data->filter_v_c = spl_dscl_get_easf_filter_coeffs_64p( + data->taps.v_taps_c, data->recip_ratios.vert_c); + } else { + dscl_prog_data->filter_v = spl_dscl_get_filter_coeffs_64p( + data->taps.v_taps, data->ratios.vert); + + dscl_prog_data->filter_v_c = spl_dscl_get_filter_coeffs_64p( + data->taps.v_taps_c, data->ratios.vert_c); + } +} + +static uint32_t spl_easf_get_scale_ratio_to_reg_value(struct spl_fixed31_32 ratio, + struct scale_ratio_to_reg_value_lookup *lookup_table_base_ptr, + unsigned int num_entries) +{ + unsigned int count = 0; + uint32_t value = 0; + struct scale_ratio_to_reg_value_lookup *lookup_table_index_ptr; + + lookup_table_index_ptr = (lookup_table_base_ptr + num_entries - 1); + value = lookup_table_index_ptr->reg_value; + + while (count < num_entries) { + + lookup_table_index_ptr = (lookup_table_base_ptr + count); + if (lookup_table_index_ptr->numer < 0) + break; + + if (ratio.value < spl_fixpt_from_fraction( + lookup_table_index_ptr->numer, + lookup_table_index_ptr->denom).value) { + value = lookup_table_index_ptr->reg_value; + break; + } + + count++; + } + return value; +} +uint32_t spl_get_v_bf3_mode(struct spl_fixed31_32 ratio) +{ + uint32_t value; + unsigned int num_entries = sizeof(easf_v_bf3_mode_lookup) / + sizeof(struct scale_ratio_to_reg_value_lookup); + value = spl_easf_get_scale_ratio_to_reg_value(ratio, + easf_v_bf3_mode_lookup, num_entries); + return value; +} +uint32_t spl_get_h_bf3_mode(struct spl_fixed31_32 ratio) +{ + uint32_t value; + unsigned int num_entries = sizeof(easf_h_bf3_mode_lookup) / + sizeof(struct scale_ratio_to_reg_value_lookup); + value = spl_easf_get_scale_ratio_to_reg_value(ratio, + easf_h_bf3_mode_lookup, num_entries); + return value; +} +uint32_t spl_get_reducer_gain6(int taps, struct spl_fixed31_32 ratio) +{ + uint32_t value; + unsigned int num_entries; + + if (taps == 4) { + num_entries = sizeof(easf_reducer_gain6_4tap_lookup) / + sizeof(struct scale_ratio_to_reg_value_lookup); + value = spl_easf_get_scale_ratio_to_reg_value(ratio, + easf_reducer_gain6_4tap_lookup, num_entries); + } else if (taps == 6) { + num_entries = sizeof(easf_reducer_gain6_6tap_lookup) / + sizeof(struct scale_ratio_to_reg_value_lookup); + value = spl_easf_get_scale_ratio_to_reg_value(ratio, + easf_reducer_gain6_6tap_lookup, num_entries); + } else + value = 0; + return value; +} +uint32_t spl_get_reducer_gain4(int taps, struct spl_fixed31_32 ratio) +{ + uint32_t value; + unsigned int num_entries; + + if (taps == 4) { + num_entries = sizeof(easf_reducer_gain4_4tap_lookup) / + sizeof(struct scale_ratio_to_reg_value_lookup); + value = spl_easf_get_scale_ratio_to_reg_value(ratio, + easf_reducer_gain4_4tap_lookup, num_entries); + } else if (taps == 6) { + num_entries = sizeof(easf_reducer_gain4_6tap_lookup) / + sizeof(struct scale_ratio_to_reg_value_lookup); + value = spl_easf_get_scale_ratio_to_reg_value(ratio, + easf_reducer_gain4_6tap_lookup, num_entries); + } else + value = 0; + return value; +} +uint32_t spl_get_gainRing6(int taps, struct spl_fixed31_32 ratio) +{ + uint32_t value; + unsigned int num_entries; + + if (taps == 4) { + num_entries = sizeof(easf_gain_ring6_4tap_lookup) / + sizeof(struct scale_ratio_to_reg_value_lookup); + value = spl_easf_get_scale_ratio_to_reg_value(ratio, + easf_gain_ring6_4tap_lookup, num_entries); + } else if (taps == 6) { + num_entries = sizeof(easf_gain_ring6_6tap_lookup) / + sizeof(struct scale_ratio_to_reg_value_lookup); + value = spl_easf_get_scale_ratio_to_reg_value(ratio, + easf_gain_ring6_6tap_lookup, num_entries); + } else + value = 0; + return value; +} +uint32_t spl_get_gainRing4(int taps, struct spl_fixed31_32 ratio) +{ + uint32_t value; + unsigned int num_entries; + + if (taps == 4) { + num_entries = sizeof(easf_gain_ring4_4tap_lookup) / + sizeof(struct scale_ratio_to_reg_value_lookup); + value = spl_easf_get_scale_ratio_to_reg_value(ratio, + easf_gain_ring4_4tap_lookup, num_entries); + } else if (taps == 6) { + num_entries = sizeof(easf_gain_ring4_6tap_lookup) / + sizeof(struct scale_ratio_to_reg_value_lookup); + value = spl_easf_get_scale_ratio_to_reg_value(ratio, + easf_gain_ring4_6tap_lookup, num_entries); + } else + value = 0; + return value; +} +uint32_t spl_get_3tap_dntilt_uptilt_offset(int taps, struct spl_fixed31_32 ratio) +{ + uint32_t value; + unsigned int num_entries; + + if (taps == 3) { + num_entries = sizeof(easf_3tap_dntilt_uptilt_offset_lookup) / + sizeof(struct scale_ratio_to_reg_value_lookup); + value = spl_easf_get_scale_ratio_to_reg_value(ratio, + easf_3tap_dntilt_uptilt_offset_lookup, num_entries); + } else + value = 0; + return value; +} +uint32_t spl_get_3tap_uptilt_maxval(int taps, struct spl_fixed31_32 ratio) +{ + uint32_t value; + unsigned int num_entries; + + if (taps == 3) { + num_entries = sizeof(easf_3tap_uptilt_maxval_lookup) / + sizeof(struct scale_ratio_to_reg_value_lookup); + value = spl_easf_get_scale_ratio_to_reg_value(ratio, + easf_3tap_uptilt_maxval_lookup, num_entries); + } else + value = 0; + return value; +} +uint32_t spl_get_3tap_dntilt_slope(int taps, struct spl_fixed31_32 ratio) +{ + uint32_t value; + unsigned int num_entries; + + if (taps == 3) { + num_entries = sizeof(easf_3tap_dntilt_slope_lookup) / + sizeof(struct scale_ratio_to_reg_value_lookup); + value = spl_easf_get_scale_ratio_to_reg_value(ratio, + easf_3tap_dntilt_slope_lookup, num_entries); + } else + value = 0; + return value; +} +uint32_t spl_get_3tap_uptilt1_slope(int taps, struct spl_fixed31_32 ratio) +{ + uint32_t value; + unsigned int num_entries; + + if (taps == 3) { + num_entries = sizeof(easf_3tap_uptilt1_slope_lookup) / + sizeof(struct scale_ratio_to_reg_value_lookup); + value = spl_easf_get_scale_ratio_to_reg_value(ratio, + easf_3tap_uptilt1_slope_lookup, num_entries); + } else + value = 0; + return value; +} +uint32_t spl_get_3tap_uptilt2_slope(int taps, struct spl_fixed31_32 ratio) +{ + uint32_t value; + unsigned int num_entries; + + if (taps == 3) { + num_entries = sizeof(easf_3tap_uptilt2_slope_lookup) / + sizeof(struct scale_ratio_to_reg_value_lookup); + value = spl_easf_get_scale_ratio_to_reg_value(ratio, + easf_3tap_uptilt2_slope_lookup, num_entries); + } else + value = 0; + return value; +} +uint32_t spl_get_3tap_uptilt2_offset(int taps, struct spl_fixed31_32 ratio) +{ + uint32_t value; + unsigned int num_entries; + + if (taps == 3) { + num_entries = sizeof(easf_3tap_uptilt2_offset_lookup) / + sizeof(struct scale_ratio_to_reg_value_lookup); + value = spl_easf_get_scale_ratio_to_reg_value(ratio, + easf_3tap_uptilt2_offset_lookup, num_entries); + } else + value = 0; + return value; +} diff --git a/drivers/gpu/drm/amd/display/dc/spl/dc_spl_scl_easf_filters.h b/drivers/gpu/drm/amd/display/dc/spl/dc_spl_scl_easf_filters.h new file mode 100644 index 0000000000000..8bb2b8108e38a --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/spl/dc_spl_scl_easf_filters.h @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: MIT */ + +/* Copyright 2024 Advanced Micro Devices, Inc. */ + +#ifndef __DC_SPL_SCL_EASF_FILTERS_H__ +#define __DC_SPL_SCL_EASF_FILTERS_H__ + +#include "dc_spl_types.h" + +struct scale_ratio_to_reg_value_lookup { + int numer; + int denom; + const uint32_t reg_value; +}; + +void spl_init_easf_filter_coeffs(void); +uint16_t *spl_get_easf_filter_3tap_64p(struct spl_fixed31_32 ratio); +uint16_t *spl_get_easf_filter_4tap_64p(struct spl_fixed31_32 ratio); +uint16_t *spl_get_easf_filter_6tap_64p(struct spl_fixed31_32 ratio); +uint16_t *spl_dscl_get_easf_filter_coeffs_64p(int taps, struct spl_fixed31_32 ratio); +void spl_set_filters_data(struct dscl_prog_data *dscl_prog_data, + const struct spl_scaler_data *data, bool enable_easf_v, + bool enable_easf_h); + +uint32_t spl_get_v_bf3_mode(struct spl_fixed31_32 ratio); +uint32_t spl_get_h_bf3_mode(struct spl_fixed31_32 ratio); +uint32_t spl_get_reducer_gain6(int taps, struct spl_fixed31_32 ratio); +uint32_t spl_get_reducer_gain4(int taps, struct spl_fixed31_32 ratio); +uint32_t spl_get_gainRing6(int taps, struct spl_fixed31_32 ratio); +uint32_t spl_get_gainRing4(int taps, struct spl_fixed31_32 ratio); +uint32_t spl_get_3tap_dntilt_uptilt_offset(int taps, struct spl_fixed31_32 ratio); +uint32_t spl_get_3tap_uptilt_maxval(int taps, struct spl_fixed31_32 ratio); +uint32_t spl_get_3tap_dntilt_slope(int taps, struct spl_fixed31_32 ratio); +uint32_t spl_get_3tap_uptilt1_slope(int taps, struct spl_fixed31_32 ratio); +uint32_t spl_get_3tap_uptilt2_slope(int taps, struct spl_fixed31_32 ratio); +uint32_t spl_get_3tap_uptilt2_offset(int taps, struct spl_fixed31_32 ratio); + +#endif /* __DC_SPL_SCL_EASF_FILTERS_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/spl/dc_spl_scl_filters.c b/drivers/gpu/drm/amd/display/dc/spl/dc_spl_scl_filters.c index e2baaf5841396..b02c7b0b262b8 100644 --- a/drivers/gpu/drm/amd/display/dc/spl/dc_spl_scl_filters.c +++ b/drivers/gpu/drm/amd/display/dc/spl/dc_spl_scl_filters.c @@ -2,6 +2,7 @@ // // Copyright 2024 Advanced Micro Devices, Inc. +#include "spl_debug.h" #include "dc_spl_scl_filters.h" //========================================= // = 2 @@ -1317,97 +1318,97 @@ static const uint16_t filter_8tap_64p_183[264] = { 0x3FD4, 0x3F84, 0x0214, 0x0694, 0x0694, 0x0214, 0x3F84, 0x3FD4 }; -const uint16_t *spl_get_filter_3tap_16p(struct fixed31_32 ratio) +const uint16_t *spl_get_filter_3tap_16p(struct spl_fixed31_32 ratio) { - if (ratio.value < dc_fixpt_one.value) + if (ratio.value < spl_fixpt_one.value) return filter_3tap_16p_upscale; - else if (ratio.value < dc_fixpt_from_fraction(4, 3).value) + else if (ratio.value < spl_fixpt_from_fraction(4, 3).value) return filter_3tap_16p_116; - else if (ratio.value < dc_fixpt_from_fraction(5, 3).value) + else if (ratio.value < spl_fixpt_from_fraction(5, 3).value) return filter_3tap_16p_149; else return filter_3tap_16p_183; } -const uint16_t *spl_get_filter_3tap_64p(struct fixed31_32 ratio) +const uint16_t *spl_get_filter_3tap_64p(struct spl_fixed31_32 ratio) { - if (ratio.value < dc_fixpt_one.value) + if (ratio.value < spl_fixpt_one.value) return filter_3tap_64p_upscale; - else if (ratio.value < dc_fixpt_from_fraction(4, 3).value) + else if (ratio.value < spl_fixpt_from_fraction(4, 3).value) return filter_3tap_64p_116; - else if (ratio.value < dc_fixpt_from_fraction(5, 3).value) + else if (ratio.value < spl_fixpt_from_fraction(5, 3).value) return filter_3tap_64p_149; else return filter_3tap_64p_183; } -const uint16_t *spl_get_filter_4tap_16p(struct fixed31_32 ratio) +const uint16_t *spl_get_filter_4tap_16p(struct spl_fixed31_32 ratio) { - if (ratio.value < dc_fixpt_one.value) + if (ratio.value < spl_fixpt_one.value) return filter_4tap_16p_upscale; - else if (ratio.value < dc_fixpt_from_fraction(4, 3).value) + else if (ratio.value < spl_fixpt_from_fraction(4, 3).value) return filter_4tap_16p_116; - else if (ratio.value < dc_fixpt_from_fraction(5, 3).value) + else if (ratio.value < spl_fixpt_from_fraction(5, 3).value) return filter_4tap_16p_149; else return filter_4tap_16p_183; } -const uint16_t *spl_get_filter_4tap_64p(struct fixed31_32 ratio) +const uint16_t *spl_get_filter_4tap_64p(struct spl_fixed31_32 ratio) { - if (ratio.value < dc_fixpt_one.value) + if (ratio.value < spl_fixpt_one.value) return filter_4tap_64p_upscale; - else if (ratio.value < dc_fixpt_from_fraction(4, 3).value) + else if (ratio.value < spl_fixpt_from_fraction(4, 3).value) return filter_4tap_64p_116; - else if (ratio.value < dc_fixpt_from_fraction(5, 3).value) + else if (ratio.value < spl_fixpt_from_fraction(5, 3).value) return filter_4tap_64p_149; else return filter_4tap_64p_183; } -const uint16_t *spl_get_filter_5tap_64p(struct fixed31_32 ratio) +const uint16_t *spl_get_filter_5tap_64p(struct spl_fixed31_32 ratio) { - if (ratio.value < dc_fixpt_one.value) + if (ratio.value < spl_fixpt_one.value) return filter_5tap_64p_upscale; - else if (ratio.value < dc_fixpt_from_fraction(4, 3).value) + else if (ratio.value < spl_fixpt_from_fraction(4, 3).value) return filter_5tap_64p_116; - else if (ratio.value < dc_fixpt_from_fraction(5, 3).value) + else if (ratio.value < spl_fixpt_from_fraction(5, 3).value) return filter_5tap_64p_149; else return filter_5tap_64p_183; } -const uint16_t *spl_get_filter_6tap_64p(struct fixed31_32 ratio) +const uint16_t *spl_get_filter_6tap_64p(struct spl_fixed31_32 ratio) { - if (ratio.value < dc_fixpt_one.value) + if (ratio.value < spl_fixpt_one.value) return filter_6tap_64p_upscale; - else if (ratio.value < dc_fixpt_from_fraction(4, 3).value) + else if (ratio.value < spl_fixpt_from_fraction(4, 3).value) return filter_6tap_64p_116; - else if (ratio.value < dc_fixpt_from_fraction(5, 3).value) + else if (ratio.value < spl_fixpt_from_fraction(5, 3).value) return filter_6tap_64p_149; else return filter_6tap_64p_183; } -const uint16_t *spl_get_filter_7tap_64p(struct fixed31_32 ratio) +const uint16_t *spl_get_filter_7tap_64p(struct spl_fixed31_32 ratio) { - if (ratio.value < dc_fixpt_one.value) + if (ratio.value < spl_fixpt_one.value) return filter_7tap_64p_upscale; - else if (ratio.value < dc_fixpt_from_fraction(4, 3).value) + else if (ratio.value < spl_fixpt_from_fraction(4, 3).value) return filter_7tap_64p_116; - else if (ratio.value < dc_fixpt_from_fraction(5, 3).value) + else if (ratio.value < spl_fixpt_from_fraction(5, 3).value) return filter_7tap_64p_149; else return filter_7tap_64p_183; } -const uint16_t *spl_get_filter_8tap_64p(struct fixed31_32 ratio) +const uint16_t *spl_get_filter_8tap_64p(struct spl_fixed31_32 ratio) { - if (ratio.value < dc_fixpt_one.value) + if (ratio.value < spl_fixpt_one.value) return filter_8tap_64p_upscale; - else if (ratio.value < dc_fixpt_from_fraction(4, 3).value) + else if (ratio.value < spl_fixpt_from_fraction(4, 3).value) return filter_8tap_64p_116; - else if (ratio.value < dc_fixpt_from_fraction(5, 3).value) + else if (ratio.value < spl_fixpt_from_fraction(5, 3).value) return filter_8tap_64p_149; else return filter_8tap_64p_183; @@ -1422,3 +1423,29 @@ const uint16_t *spl_get_filter_2tap_64p(void) { return filter_2tap_64p; } + +const uint16_t *spl_dscl_get_filter_coeffs_64p(int taps, struct spl_fixed31_32 ratio) +{ + if (taps == 8) + return spl_get_filter_8tap_64p(ratio); + else if (taps == 7) + return spl_get_filter_7tap_64p(ratio); + else if (taps == 6) + return spl_get_filter_6tap_64p(ratio); + else if (taps == 5) + return spl_get_filter_5tap_64p(ratio); + else if (taps == 4) + return spl_get_filter_4tap_64p(ratio); + else if (taps == 3) + return spl_get_filter_3tap_64p(ratio); + else if (taps == 2) + return spl_get_filter_2tap_64p(); + else if (taps == 1) + return NULL; + else { + /* should never happen, bug */ + SPL_BREAK_TO_DEBUGGER(); + return NULL; + } +} + diff --git a/drivers/gpu/drm/amd/display/dc/spl/dc_spl_scl_filters.h b/drivers/gpu/drm/amd/display/dc/spl/dc_spl_scl_filters.h index 6d96aca53b24d..48202bc4f81e8 100644 --- a/drivers/gpu/drm/amd/display/dc/spl/dc_spl_scl_filters.h +++ b/drivers/gpu/drm/amd/display/dc/spl/dc_spl_scl_filters.h @@ -7,53 +7,16 @@ #include "dc_spl_types.h" -const uint16_t *spl_get_filter_3tap_16p(struct fixed31_32 ratio); -const uint16_t *spl_get_filter_3tap_64p(struct fixed31_32 ratio); -const uint16_t *spl_get_filter_4tap_16p(struct fixed31_32 ratio); -const uint16_t *spl_get_filter_4tap_64p(struct fixed31_32 ratio); -const uint16_t *spl_get_filter_5tap_64p(struct fixed31_32 ratio); -const uint16_t *spl_get_filter_6tap_64p(struct fixed31_32 ratio); -const uint16_t *spl_get_filter_7tap_64p(struct fixed31_32 ratio); -const uint16_t *spl_get_filter_8tap_64p(struct fixed31_32 ratio); +const uint16_t *spl_get_filter_3tap_16p(struct spl_fixed31_32 ratio); +const uint16_t *spl_get_filter_3tap_64p(struct spl_fixed31_32 ratio); +const uint16_t *spl_get_filter_4tap_16p(struct spl_fixed31_32 ratio); +const uint16_t *spl_get_filter_4tap_64p(struct spl_fixed31_32 ratio); +const uint16_t *spl_get_filter_5tap_64p(struct spl_fixed31_32 ratio); +const uint16_t *spl_get_filter_6tap_64p(struct spl_fixed31_32 ratio); +const uint16_t *spl_get_filter_7tap_64p(struct spl_fixed31_32 ratio); +const uint16_t *spl_get_filter_8tap_64p(struct spl_fixed31_32 ratio); const uint16_t *spl_get_filter_2tap_16p(void); const uint16_t *spl_get_filter_2tap_64p(void); -const uint16_t *spl_get_filter_3tap_16p_upscale(void); -const uint16_t *spl_get_filter_3tap_16p_116(void); -const uint16_t *spl_get_filter_3tap_16p_149(void); -const uint16_t *spl_get_filter_3tap_16p_183(void); +const uint16_t *spl_dscl_get_filter_coeffs_64p(int taps, struct spl_fixed31_32 ratio); -const uint16_t *spl_get_filter_4tap_16p_upscale(void); -const uint16_t *spl_get_filter_4tap_16p_116(void); -const uint16_t *spl_get_filter_4tap_16p_149(void); -const uint16_t *spl_get_filter_4tap_16p_183(void); - -const uint16_t *spl_get_filter_3tap_64p_upscale(void); -const uint16_t *spl_get_filter_3tap_64p_116(void); -const uint16_t *spl_get_filter_3tap_64p_149(void); -const uint16_t *spl_get_filter_3tap_64p_183(void); - -const uint16_t *spl_get_filter_4tap_64p_upscale(void); -const uint16_t *spl_get_filter_4tap_64p_116(void); -const uint16_t *spl_get_filter_4tap_64p_149(void); -const uint16_t *spl_get_filter_4tap_64p_183(void); - -const uint16_t *spl_get_filter_5tap_64p_upscale(void); -const uint16_t *spl_get_filter_5tap_64p_116(void); -const uint16_t *spl_get_filter_5tap_64p_149(void); -const uint16_t *spl_get_filter_5tap_64p_183(void); - -const uint16_t *spl_get_filter_6tap_64p_upscale(void); -const uint16_t *spl_get_filter_6tap_64p_116(void); -const uint16_t *spl_get_filter_6tap_64p_149(void); -const uint16_t *spl_get_filter_6tap_64p_183(void); - -const uint16_t *spl_get_filter_7tap_64p_upscale(void); -const uint16_t *spl_get_filter_7tap_64p_116(void); -const uint16_t *spl_get_filter_7tap_64p_149(void); -const uint16_t *spl_get_filter_7tap_64p_183(void); - -const uint16_t *spl_get_filter_8tap_64p_upscale(void); -const uint16_t *spl_get_filter_8tap_64p_116(void); -const uint16_t *spl_get_filter_8tap_64p_149(void); -const uint16_t *spl_get_filter_8tap_64p_183(void); #endif /* __DC_SPL_SCL_FILTERS_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/spl/dc_spl_scl_filters_old.c b/drivers/gpu/drm/amd/display/dc/spl/dc_spl_scl_filters_old.c deleted file mode 100644 index bb0e1b80ec3ca..0000000000000 --- a/drivers/gpu/drm/amd/display/dc/spl/dc_spl_scl_filters_old.c +++ /dev/null @@ -1,25 +0,0 @@ -/* - * Copyright 2012-16 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - diff --git a/drivers/gpu/drm/amd/display/dc/spl/dc_spl_types.h b/drivers/gpu/drm/amd/display/dc/spl/dc_spl_types.h index 36d10b0f2eed1..3d61c98258076 100644 --- a/drivers/gpu/drm/amd/display/dc/spl/dc_spl_types.h +++ b/drivers/gpu/drm/amd/display/dc/spl/dc_spl_types.h @@ -2,14 +2,15 @@ // // Copyright 2024 Advanced Micro Devices, Inc. -#include "os_types.h" // swap -#ifndef ASSERT -#define ASSERT(_bool) ((void *)0) -#endif -#include "include/fixed31_32.h" // fixed31_32 and related functions #ifndef __DC_SPL_TYPES_H__ #define __DC_SPL_TYPES_H__ +#include "spl_os_types.h" // swap +#ifndef SPL_ASSERT +#define SPL_ASSERT(_bool) ((void *)0) +#endif +#include "spl_fixpt31_32.h" // fixed31_32 and related functions + struct spl_size { uint32_t width; uint32_t height; @@ -22,16 +23,16 @@ struct spl_rect { }; struct spl_ratios { - struct fixed31_32 horz; - struct fixed31_32 vert; - struct fixed31_32 horz_c; - struct fixed31_32 vert_c; + struct spl_fixed31_32 horz; + struct spl_fixed31_32 vert; + struct spl_fixed31_32 horz_c; + struct spl_fixed31_32 vert_c; }; struct spl_inits { - struct fixed31_32 h; - struct fixed31_32 h_c; - struct fixed31_32 v; - struct fixed31_32 v_c; + struct spl_fixed31_32 h; + struct spl_fixed31_32 h_c; + struct spl_fixed31_32 v; + struct spl_fixed31_32 v_c; }; struct spl_taps { @@ -64,6 +65,8 @@ enum spl_pixel_format { SPL_PIXEL_FORMAT_420BPP10, /*end of pixel format definition*/ SPL_PIXEL_FORMAT_INVALID, + SPL_PIXEL_FORMAT_422BPP8, + SPL_PIXEL_FORMAT_422BPP10, SPL_PIXEL_FORMAT_GRPH_BEGIN = SPL_PIXEL_FORMAT_INDEX8, SPL_PIXEL_FORMAT_GRPH_END = SPL_PIXEL_FORMAT_FP16, SPL_PIXEL_FORMAT_VIDEO_BEGIN = SPL_PIXEL_FORMAT_420BPP8, @@ -135,6 +138,7 @@ struct spl_scaler_data { struct spl_rect viewport_c; struct spl_rect recout; struct spl_ratios ratios; + struct spl_ratios recip_ratios; struct spl_inits inits; }; @@ -405,10 +409,15 @@ struct dscl_prog_data { }; /* SPL input and output definitions */ -// SPL outputs struct -struct spl_out { +// SPL scratch struct +struct spl_scratch { // Pack all SPL outputs in scl_data struct spl_scaler_data scl_data; +}; + +/* SPL input and output definitions */ +// SPL outputs struct +struct spl_out { // Pack all output need to program hw registers struct dscl_prog_data *dscl_prog_data; }; @@ -491,6 +500,10 @@ struct spl_in { bool prefer_easf; bool disable_easf; struct spl_debug debug; + bool is_fullscreen; + bool is_hdr_on; + int h_active; + int v_active; }; // end of SPL inputs diff --git a/drivers/gpu/drm/amd/display/dc/spl/spl_debug.h b/drivers/gpu/drm/amd/display/dc/spl/spl_debug.h new file mode 100644 index 0000000000000..5696dafd0894d --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/spl/spl_debug.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: MIT */ + +/* Copyright 2024 Advanced Micro Devices, Inc. */ + +#ifndef SPL_DEBUG_H +#define SPL_DEBUG_H + +#ifdef SPL_ASSERT +#undef SPL_ASSERT +#endif +#define SPL_ASSERT(b) + +#define SPL_ASSERT_CRITICAL(expr) do {if (expr)/* Do nothing */; } while (0) + +#ifdef SPL_DALMSG +#undef SPL_DALMSG +#endif +#define SPL_DALMSG(b) + +#ifdef SPL_DAL_ASSERT_MSG +#undef SPL_DAL_ASSERT_MSG +#endif +#define SPL_DAL_ASSERT_MSG(b, m) + +#endif // SPL_DEBUG_H diff --git a/drivers/gpu/drm/amd/display/dc/spl/spl_fixpt31_32.c b/drivers/gpu/drm/amd/display/dc/spl/spl_fixpt31_32.c new file mode 100644 index 0000000000000..a95565df5487c --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/spl/spl_fixpt31_32.c @@ -0,0 +1,497 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2024 Advanced Micro Devices, Inc. + +#include "spl_fixpt31_32.h" + +static const struct spl_fixed31_32 spl_fixpt_two_pi = { 26986075409LL }; +static const struct spl_fixed31_32 spl_fixpt_ln2 = { 2977044471LL }; +static const struct spl_fixed31_32 spl_fixpt_ln2_div_2 = { 1488522236LL }; + +static inline unsigned long long abs_i64( + long long arg) +{ + if (arg > 0) + return (unsigned long long)arg; + else + return (unsigned long long)(-arg); +} + +/* + * @brief + * result = dividend / divisor + * *remainder = dividend % divisor + */ +static inline unsigned long long complete_integer_division_u64( + unsigned long long dividend, + unsigned long long divisor, + unsigned long long *remainder) +{ + unsigned long long result; + + ASSERT(divisor); + + result = spl_div64_u64_rem(dividend, divisor, remainder); + + return result; +} + + +#define FRACTIONAL_PART_MASK \ + ((1ULL << FIXED31_32_BITS_PER_FRACTIONAL_PART) - 1) + +#define GET_INTEGER_PART(x) \ + ((x) >> FIXED31_32_BITS_PER_FRACTIONAL_PART) + +#define GET_FRACTIONAL_PART(x) \ + (FRACTIONAL_PART_MASK & (x)) + +struct spl_fixed31_32 spl_fixpt_from_fraction(long long numerator, long long denominator) +{ + struct spl_fixed31_32 res; + + bool arg1_negative = numerator < 0; + bool arg2_negative = denominator < 0; + + unsigned long long arg1_value = arg1_negative ? -numerator : numerator; + unsigned long long arg2_value = arg2_negative ? -denominator : denominator; + + unsigned long long remainder; + + /* determine integer part */ + + unsigned long long res_value = complete_integer_division_u64( + arg1_value, arg2_value, &remainder); + + ASSERT(res_value <= LONG_MAX); + + /* determine fractional part */ + { + unsigned int i = FIXED31_32_BITS_PER_FRACTIONAL_PART; + + do { + remainder <<= 1; + + res_value <<= 1; + + if (remainder >= arg2_value) { + res_value |= 1; + remainder -= arg2_value; + } + } while (--i != 0); + } + + /* round up LSB */ + { + unsigned long long summand = (remainder << 1) >= arg2_value; + + ASSERT(res_value <= LLONG_MAX - summand); + + res_value += summand; + } + + res.value = (long long)res_value; + + if (arg1_negative ^ arg2_negative) + res.value = -res.value; + + return res; +} + +struct spl_fixed31_32 spl_fixpt_mul(struct spl_fixed31_32 arg1, struct spl_fixed31_32 arg2) +{ + struct spl_fixed31_32 res; + + bool arg1_negative = arg1.value < 0; + bool arg2_negative = arg2.value < 0; + + unsigned long long arg1_value = arg1_negative ? -arg1.value : arg1.value; + unsigned long long arg2_value = arg2_negative ? -arg2.value : arg2.value; + + unsigned long long arg1_int = GET_INTEGER_PART(arg1_value); + unsigned long long arg2_int = GET_INTEGER_PART(arg2_value); + + unsigned long long arg1_fra = GET_FRACTIONAL_PART(arg1_value); + unsigned long long arg2_fra = GET_FRACTIONAL_PART(arg2_value); + + unsigned long long tmp; + + res.value = arg1_int * arg2_int; + + ASSERT(res.value <= (long long)LONG_MAX); + + res.value <<= FIXED31_32_BITS_PER_FRACTIONAL_PART; + + tmp = arg1_int * arg2_fra; + + ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value)); + + res.value += tmp; + + tmp = arg2_int * arg1_fra; + + ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value)); + + res.value += tmp; + + tmp = arg1_fra * arg2_fra; + + tmp = (tmp >> FIXED31_32_BITS_PER_FRACTIONAL_PART) + + (tmp >= (unsigned long long)spl_fixpt_half.value); + + ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value)); + + res.value += tmp; + + if (arg1_negative ^ arg2_negative) + res.value = -res.value; + + return res; +} + +struct spl_fixed31_32 spl_fixpt_sqr(struct spl_fixed31_32 arg) +{ + struct spl_fixed31_32 res; + + unsigned long long arg_value = abs_i64(arg.value); + + unsigned long long arg_int = GET_INTEGER_PART(arg_value); + + unsigned long long arg_fra = GET_FRACTIONAL_PART(arg_value); + + unsigned long long tmp; + + res.value = arg_int * arg_int; + + ASSERT(res.value <= (long long)LONG_MAX); + + res.value <<= FIXED31_32_BITS_PER_FRACTIONAL_PART; + + tmp = arg_int * arg_fra; + + ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value)); + + res.value += tmp; + + ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value)); + + res.value += tmp; + + tmp = arg_fra * arg_fra; + + tmp = (tmp >> FIXED31_32_BITS_PER_FRACTIONAL_PART) + + (tmp >= (unsigned long long)spl_fixpt_half.value); + + ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value)); + + res.value += tmp; + + return res; +} + +struct spl_fixed31_32 spl_fixpt_recip(struct spl_fixed31_32 arg) +{ + /* + * @note + * Good idea to use Newton's method + */ + + ASSERT(arg.value); + + return spl_fixpt_from_fraction( + spl_fixpt_one.value, + arg.value); +} + +struct spl_fixed31_32 spl_fixpt_sinc(struct spl_fixed31_32 arg) +{ + struct spl_fixed31_32 square; + + struct spl_fixed31_32 res = spl_fixpt_one; + + int n = 27; + + struct spl_fixed31_32 arg_norm = arg; + + if (spl_fixpt_le( + spl_fixpt_two_pi, + spl_fixpt_abs(arg))) { + arg_norm = spl_fixpt_sub( + arg_norm, + spl_fixpt_mul_int( + spl_fixpt_two_pi, + (int)spl_div64_s64( + arg_norm.value, + spl_fixpt_two_pi.value))); + } + + square = spl_fixpt_sqr(arg_norm); + + do { + res = spl_fixpt_sub( + spl_fixpt_one, + spl_fixpt_div_int( + spl_fixpt_mul( + square, + res), + n * (n - 1))); + + n -= 2; + } while (n > 2); + + if (arg.value != arg_norm.value) + res = spl_fixpt_div( + spl_fixpt_mul(res, arg_norm), + arg); + + return res; +} + +struct spl_fixed31_32 spl_fixpt_sin(struct spl_fixed31_32 arg) +{ + return spl_fixpt_mul( + arg, + spl_fixpt_sinc(arg)); +} + +struct spl_fixed31_32 spl_fixpt_cos(struct spl_fixed31_32 arg) +{ + /* TODO implement argument normalization */ + + const struct spl_fixed31_32 square = spl_fixpt_sqr(arg); + + struct spl_fixed31_32 res = spl_fixpt_one; + + int n = 26; + + do { + res = spl_fixpt_sub( + spl_fixpt_one, + spl_fixpt_div_int( + spl_fixpt_mul( + square, + res), + n * (n - 1))); + + n -= 2; + } while (n != 0); + + return res; +} + +/* + * @brief + * result = exp(arg), + * where abs(arg) < 1 + * + * Calculated as Taylor series. + */ +static struct spl_fixed31_32 fixed31_32_exp_from_taylor_series(struct spl_fixed31_32 arg) +{ + unsigned int n = 9; + + struct spl_fixed31_32 res = spl_fixpt_from_fraction( + n + 2, + n + 1); + /* TODO find correct res */ + + ASSERT(spl_fixpt_lt(arg, spl_fixpt_one)); + + do + res = spl_fixpt_add( + spl_fixpt_one, + spl_fixpt_div_int( + spl_fixpt_mul( + arg, + res), + n)); + while (--n != 1); + + return spl_fixpt_add( + spl_fixpt_one, + spl_fixpt_mul( + arg, + res)); +} + +struct spl_fixed31_32 spl_fixpt_exp(struct spl_fixed31_32 arg) +{ + /* + * @brief + * Main equation is: + * exp(x) = exp(r + m * ln(2)) = (1 << m) * exp(r), + * where m = round(x / ln(2)), r = x - m * ln(2) + */ + + if (spl_fixpt_le( + spl_fixpt_ln2_div_2, + spl_fixpt_abs(arg))) { + int m = spl_fixpt_round( + spl_fixpt_div( + arg, + spl_fixpt_ln2)); + + struct spl_fixed31_32 r = spl_fixpt_sub( + arg, + spl_fixpt_mul_int( + spl_fixpt_ln2, + m)); + + ASSERT(m != 0); + + ASSERT(spl_fixpt_lt( + spl_fixpt_abs(r), + spl_fixpt_one)); + + if (m > 0) + return spl_fixpt_shl( + fixed31_32_exp_from_taylor_series(r), + (unsigned char)m); + else + return spl_fixpt_div_int( + fixed31_32_exp_from_taylor_series(r), + 1LL << -m); + } else if (arg.value != 0) + return fixed31_32_exp_from_taylor_series(arg); + else + return spl_fixpt_one; +} + +struct spl_fixed31_32 spl_fixpt_log(struct spl_fixed31_32 arg) +{ + struct spl_fixed31_32 res = spl_fixpt_neg(spl_fixpt_one); + /* TODO improve 1st estimation */ + + struct spl_fixed31_32 error; + + ASSERT(arg.value > 0); + /* TODO if arg is negative, return NaN */ + /* TODO if arg is zero, return -INF */ + + do { + struct spl_fixed31_32 res1 = spl_fixpt_add( + spl_fixpt_sub( + res, + spl_fixpt_one), + spl_fixpt_div( + arg, + spl_fixpt_exp(res))); + + error = spl_fixpt_sub( + res, + res1); + + res = res1; + /* TODO determine max_allowed_error based on quality of exp() */ + } while (abs_i64(error.value) > 100ULL); + + return res; +} + + +/* this function is a generic helper to translate fixed point value to + * specified integer format that will consist of integer_bits integer part and + * fractional_bits fractional part. For example it is used in + * spl_fixpt_u2d19 to receive 2 bits integer part and 19 bits fractional + * part in 32 bits. It is used in hw programming (scaler) + */ + +static inline unsigned int ux_dy( + long long value, + unsigned int integer_bits, + unsigned int fractional_bits) +{ + /* 1. create mask of integer part */ + unsigned int result = (1 << integer_bits) - 1; + /* 2. mask out fractional part */ + unsigned int fractional_part = FRACTIONAL_PART_MASK & value; + /* 3. shrink fixed point integer part to be of integer_bits width*/ + result &= GET_INTEGER_PART(value); + /* 4. make space for fractional part to be filled in after integer */ + result <<= fractional_bits; + /* 5. shrink fixed point fractional part to of fractional_bits width*/ + fractional_part >>= FIXED31_32_BITS_PER_FRACTIONAL_PART - fractional_bits; + /* 6. merge the result */ + return result | fractional_part; +} + +static inline unsigned int clamp_ux_dy( + long long value, + unsigned int integer_bits, + unsigned int fractional_bits, + unsigned int min_clamp) +{ + unsigned int truncated_val = ux_dy(value, integer_bits, fractional_bits); + + if (value >= (1LL << (integer_bits + FIXED31_32_BITS_PER_FRACTIONAL_PART))) + return (1 << (integer_bits + fractional_bits)) - 1; + else if (truncated_val > min_clamp) + return truncated_val; + else + return min_clamp; +} + +unsigned int spl_fixpt_u4d19(struct spl_fixed31_32 arg) +{ + return ux_dy(arg.value, 4, 19); +} + +unsigned int spl_fixpt_u3d19(struct spl_fixed31_32 arg) +{ + return ux_dy(arg.value, 3, 19); +} + +unsigned int spl_fixpt_u2d19(struct spl_fixed31_32 arg) +{ + return ux_dy(arg.value, 2, 19); +} + +unsigned int spl_fixpt_u0d19(struct spl_fixed31_32 arg) +{ + return ux_dy(arg.value, 0, 19); +} + +unsigned int spl_fixpt_clamp_u0d14(struct spl_fixed31_32 arg) +{ + return clamp_ux_dy(arg.value, 0, 14, 1); +} + +unsigned int spl_fixpt_clamp_u0d10(struct spl_fixed31_32 arg) +{ + return clamp_ux_dy(arg.value, 0, 10, 1); +} + +int spl_fixpt_s4d19(struct spl_fixed31_32 arg) +{ + if (arg.value < 0) + return -(int)ux_dy(spl_fixpt_abs(arg).value, 4, 19); + else + return ux_dy(arg.value, 4, 19); +} + +struct spl_fixed31_32 spl_fixpt_from_ux_dy(unsigned int value, + unsigned int integer_bits, + unsigned int fractional_bits) +{ + struct spl_fixed31_32 fixpt_value = spl_fixpt_zero; + struct spl_fixed31_32 fixpt_int_value = spl_fixpt_zero; + long long frac_mask = ((long long)1 << (long long)integer_bits) - 1; + + fixpt_value.value = (long long)value << (FIXED31_32_BITS_PER_FRACTIONAL_PART - fractional_bits); + frac_mask = frac_mask << fractional_bits; + fixpt_int_value.value = value & frac_mask; + fixpt_int_value.value <<= (FIXED31_32_BITS_PER_FRACTIONAL_PART - fractional_bits); + fixpt_value.value |= fixpt_int_value.value; + return fixpt_value; +} + +struct spl_fixed31_32 spl_fixpt_from_int_dy(unsigned int int_value, + unsigned int frac_value, + unsigned int integer_bits, + unsigned int fractional_bits) +{ + struct spl_fixed31_32 fixpt_value = spl_fixpt_from_int(int_value); + + fixpt_value.value |= (long long)frac_value << (FIXED31_32_BITS_PER_FRACTIONAL_PART - fractional_bits); + return fixpt_value; +} diff --git a/drivers/gpu/drm/amd/display/dc/spl/spl_fixpt31_32.h b/drivers/gpu/drm/amd/display/dc/spl/spl_fixpt31_32.h new file mode 100644 index 0000000000000..8a045e2f8699a --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/spl/spl_fixpt31_32.h @@ -0,0 +1,525 @@ +/* SPDX-License-Identifier: MIT */ + +/* Copyright 2024 Advanced Micro Devices, Inc. */ + +#ifndef __SPL_FIXED31_32_H__ +#define __SPL_FIXED31_32_H__ + +#include "os_types.h" +#include "spl_os_types.h" // swap +#ifndef ASSERT +#define ASSERT(_bool) ((void *)0) +#endif + +#ifndef LLONG_MAX +#define LLONG_MAX 9223372036854775807ll +#endif +#ifndef LLONG_MIN +#define LLONG_MIN (-LLONG_MAX - 1ll) +#endif + +#define FIXED31_32_BITS_PER_FRACTIONAL_PART 32 +#ifndef LLONG_MIN +#define LLONG_MIN (1LL<<63) +#endif +#ifndef LLONG_MAX +#define LLONG_MAX (-1LL>>1) +#endif + +/* + * @brief + * Arithmetic operations on real numbers + * represented as fixed-point numbers. + * There are: 1 bit for sign, + * 31 bit for integer part, + * 32 bits for fractional part. + * + * @note + * Currently, overflows and underflows are asserted; + * no special result returned. + */ + +struct spl_fixed31_32 { + long long value; +}; + + +/* + * @brief + * Useful constants + */ + +static const struct spl_fixed31_32 spl_fixpt_zero = { 0 }; +static const struct spl_fixed31_32 spl_fixpt_epsilon = { 1LL }; +static const struct spl_fixed31_32 spl_fixpt_half = { 0x80000000LL }; +static const struct spl_fixed31_32 spl_fixpt_one = { 0x100000000LL }; + +/* + * @brief + * Initialization routines + */ + +/* + * @brief + * result = numerator / denominator + */ +struct spl_fixed31_32 spl_fixpt_from_fraction(long long numerator, long long denominator); + +/* + * @brief + * result = arg + */ +static inline struct spl_fixed31_32 spl_fixpt_from_int(int arg) +{ + struct spl_fixed31_32 res; + + res.value = (long long) arg << FIXED31_32_BITS_PER_FRACTIONAL_PART; + + return res; +} + +/* + * @brief + * Unary operators + */ + +/* + * @brief + * result = -arg + */ +static inline struct spl_fixed31_32 spl_fixpt_neg(struct spl_fixed31_32 arg) +{ + struct spl_fixed31_32 res; + + res.value = -arg.value; + + return res; +} + +/* + * @brief + * result = abs(arg) := (arg >= 0) ? arg : -arg + */ +static inline struct spl_fixed31_32 spl_fixpt_abs(struct spl_fixed31_32 arg) +{ + if (arg.value < 0) + return spl_fixpt_neg(arg); + else + return arg; +} + +/* + * @brief + * Binary relational operators + */ + +/* + * @brief + * result = arg1 < arg2 + */ +static inline bool spl_fixpt_lt(struct spl_fixed31_32 arg1, struct spl_fixed31_32 arg2) +{ + return arg1.value < arg2.value; +} + +/* + * @brief + * result = arg1 <= arg2 + */ +static inline bool spl_fixpt_le(struct spl_fixed31_32 arg1, struct spl_fixed31_32 arg2) +{ + return arg1.value <= arg2.value; +} + +/* + * @brief + * result = arg1 == arg2 + */ +static inline bool spl_fixpt_eq(struct spl_fixed31_32 arg1, struct spl_fixed31_32 arg2) +{ + return arg1.value == arg2.value; +} + +/* + * @brief + * result = min(arg1, arg2) := (arg1 <= arg2) ? arg1 : arg2 + */ +static inline struct spl_fixed31_32 spl_fixpt_min(struct spl_fixed31_32 arg1, struct spl_fixed31_32 arg2) +{ + if (arg1.value <= arg2.value) + return arg1; + else + return arg2; +} + +/* + * @brief + * result = max(arg1, arg2) := (arg1 <= arg2) ? arg2 : arg1 + */ +static inline struct spl_fixed31_32 spl_fixpt_max(struct spl_fixed31_32 arg1, struct spl_fixed31_32 arg2) +{ + if (arg1.value <= arg2.value) + return arg2; + else + return arg1; +} + +/* + * @brief + * | min_value, when arg <= min_value + * result = | arg, when min_value < arg < max_value + * | max_value, when arg >= max_value + */ +static inline struct spl_fixed31_32 spl_fixpt_clamp( + struct spl_fixed31_32 arg, + struct spl_fixed31_32 min_value, + struct spl_fixed31_32 max_value) +{ + if (spl_fixpt_le(arg, min_value)) + return min_value; + else if (spl_fixpt_le(max_value, arg)) + return max_value; + else + return arg; +} + +/* + * @brief + * Binary shift operators + */ + +/* + * @brief + * result = arg << shift + */ +static inline struct spl_fixed31_32 spl_fixpt_shl(struct spl_fixed31_32 arg, unsigned char shift) +{ + ASSERT(((arg.value >= 0) && (arg.value <= LLONG_MAX >> shift)) || + ((arg.value < 0) && (arg.value >= ~(LLONG_MAX >> shift)))); + + arg.value = arg.value << shift; + + return arg; +} + +/* + * @brief + * result = arg >> shift + */ +static inline struct spl_fixed31_32 spl_fixpt_shr(struct spl_fixed31_32 arg, unsigned char shift) +{ + bool negative = arg.value < 0; + + if (negative) + arg.value = -arg.value; + arg.value = arg.value >> shift; + if (negative) + arg.value = -arg.value; + return arg; +} + +/* + * @brief + * Binary additive operators + */ + +/* + * @brief + * result = arg1 + arg2 + */ +static inline struct spl_fixed31_32 spl_fixpt_add(struct spl_fixed31_32 arg1, struct spl_fixed31_32 arg2) +{ + struct spl_fixed31_32 res; + + ASSERT(((arg1.value >= 0) && (LLONG_MAX - arg1.value >= arg2.value)) || + ((arg1.value < 0) && (LLONG_MIN - arg1.value <= arg2.value))); + + res.value = arg1.value + arg2.value; + + return res; +} + +/* + * @brief + * result = arg1 + arg2 + */ +static inline struct spl_fixed31_32 spl_fixpt_add_int(struct spl_fixed31_32 arg1, int arg2) +{ + return spl_fixpt_add(arg1, spl_fixpt_from_int(arg2)); +} + +/* + * @brief + * result = arg1 - arg2 + */ +static inline struct spl_fixed31_32 spl_fixpt_sub(struct spl_fixed31_32 arg1, struct spl_fixed31_32 arg2) +{ + struct spl_fixed31_32 res; + + ASSERT(((arg2.value >= 0) && (LLONG_MIN + arg2.value <= arg1.value)) || + ((arg2.value < 0) && (LLONG_MAX + arg2.value >= arg1.value))); + + res.value = arg1.value - arg2.value; + + return res; +} + +/* + * @brief + * result = arg1 - arg2 + */ +static inline struct spl_fixed31_32 spl_fixpt_sub_int(struct spl_fixed31_32 arg1, int arg2) +{ + return spl_fixpt_sub(arg1, spl_fixpt_from_int(arg2)); +} + + +/* + * @brief + * Binary multiplicative operators + */ + +/* + * @brief + * result = arg1 * arg2 + */ +struct spl_fixed31_32 spl_fixpt_mul(struct spl_fixed31_32 arg1, struct spl_fixed31_32 arg2); + + +/* + * @brief + * result = arg1 * arg2 + */ +static inline struct spl_fixed31_32 spl_fixpt_mul_int(struct spl_fixed31_32 arg1, int arg2) +{ + return spl_fixpt_mul(arg1, spl_fixpt_from_int(arg2)); +} + +/* + * @brief + * result = square(arg) := arg * arg + */ +struct spl_fixed31_32 spl_fixpt_sqr(struct spl_fixed31_32 arg); + +/* + * @brief + * result = arg1 / arg2 + */ +static inline struct spl_fixed31_32 spl_fixpt_div_int(struct spl_fixed31_32 arg1, long long arg2) +{ + return spl_fixpt_from_fraction(arg1.value, spl_fixpt_from_int((int)arg2).value); +} + +/* + * @brief + * result = arg1 / arg2 + */ +static inline struct spl_fixed31_32 spl_fixpt_div(struct spl_fixed31_32 arg1, struct spl_fixed31_32 arg2) +{ + return spl_fixpt_from_fraction(arg1.value, arg2.value); +} + +/* + * @brief + * Reciprocal function + */ + +/* + * @brief + * result = reciprocal(arg) := 1 / arg + * + * @note + * No special actions taken in case argument is zero. + */ +struct spl_fixed31_32 spl_fixpt_recip(struct spl_fixed31_32 arg); + +/* + * @brief + * Trigonometric functions + */ + +/* + * @brief + * result = sinc(arg) := sin(arg) / arg + * + * @note + * Argument specified in radians, + * internally it's normalized to [-2pi...2pi] range. + */ +struct spl_fixed31_32 spl_fixpt_sinc(struct spl_fixed31_32 arg); + +/* + * @brief + * result = sin(arg) + * + * @note + * Argument specified in radians, + * internally it's normalized to [-2pi...2pi] range. + */ +struct spl_fixed31_32 spl_fixpt_sin(struct spl_fixed31_32 arg); + +/* + * @brief + * result = cos(arg) + * + * @note + * Argument specified in radians + * and should be in [-2pi...2pi] range - + * passing arguments outside that range + * will cause incorrect result! + */ +struct spl_fixed31_32 spl_fixpt_cos(struct spl_fixed31_32 arg); + +/* + * @brief + * Transcendent functions + */ + +/* + * @brief + * result = exp(arg) + * + * @note + * Currently, function is verified for abs(arg) <= 1. + */ +struct spl_fixed31_32 spl_fixpt_exp(struct spl_fixed31_32 arg); + +/* + * @brief + * result = log(arg) + * + * @note + * Currently, abs(arg) should be less than 1. + * No normalization is done. + * Currently, no special actions taken + * in case of invalid argument(s). Take care! + */ +struct spl_fixed31_32 spl_fixpt_log(struct spl_fixed31_32 arg); + +/* + * @brief + * Power function + */ + +/* + * @brief + * result = pow(arg1, arg2) + * + * @note + * Currently, abs(arg1) should be less than 1. Take care! + */ +static inline struct spl_fixed31_32 spl_fixpt_pow(struct spl_fixed31_32 arg1, struct spl_fixed31_32 arg2) +{ + if (arg1.value == 0) + return arg2.value == 0 ? spl_fixpt_one : spl_fixpt_zero; + + return spl_fixpt_exp( + spl_fixpt_mul( + spl_fixpt_log(arg1), + arg2)); +} + +/* + * @brief + * Rounding functions + */ + +/* + * @brief + * result = floor(arg) := greatest integer lower than or equal to arg + */ +static inline int spl_fixpt_floor(struct spl_fixed31_32 arg) +{ + unsigned long long arg_value = arg.value > 0 ? arg.value : -arg.value; + + if (arg.value >= 0) + return (int)(arg_value >> FIXED31_32_BITS_PER_FRACTIONAL_PART); + else + return -(int)(arg_value >> FIXED31_32_BITS_PER_FRACTIONAL_PART); +} + +/* + * @brief + * result = round(arg) := integer nearest to arg + */ +static inline int spl_fixpt_round(struct spl_fixed31_32 arg) +{ + unsigned long long arg_value = arg.value > 0 ? arg.value : -arg.value; + + const long long summand = spl_fixpt_half.value; + + ASSERT(LLONG_MAX - (long long)arg_value >= summand); + + arg_value += summand; + + if (arg.value >= 0) + return (int)(arg_value >> FIXED31_32_BITS_PER_FRACTIONAL_PART); + else + return -(int)(arg_value >> FIXED31_32_BITS_PER_FRACTIONAL_PART); +} + +/* + * @brief + * result = ceil(arg) := lowest integer greater than or equal to arg + */ +static inline int spl_fixpt_ceil(struct spl_fixed31_32 arg) +{ + unsigned long long arg_value = arg.value > 0 ? arg.value : -arg.value; + + const long long summand = spl_fixpt_one.value - + spl_fixpt_epsilon.value; + + ASSERT(LLONG_MAX - (long long)arg_value >= summand); + + arg_value += summand; + + if (arg.value >= 0) + return (int)(arg_value >> FIXED31_32_BITS_PER_FRACTIONAL_PART); + else + return -(int)(arg_value >> FIXED31_32_BITS_PER_FRACTIONAL_PART); +} + +/* the following two function are used in scaler hw programming to convert fixed + * point value to format 2 bits from integer part and 19 bits from fractional + * part. The same applies for u0d19, 0 bits from integer part and 19 bits from + * fractional + */ + +unsigned int spl_fixpt_u4d19(struct spl_fixed31_32 arg); + +unsigned int spl_fixpt_u3d19(struct spl_fixed31_32 arg); + +unsigned int spl_fixpt_u2d19(struct spl_fixed31_32 arg); + +unsigned int spl_fixpt_u0d19(struct spl_fixed31_32 arg); + +unsigned int spl_fixpt_clamp_u0d14(struct spl_fixed31_32 arg); + +unsigned int spl_fixpt_clamp_u0d10(struct spl_fixed31_32 arg); + +int spl_fixpt_s4d19(struct spl_fixed31_32 arg); + +static inline struct spl_fixed31_32 spl_fixpt_truncate(struct spl_fixed31_32 arg, unsigned int frac_bits) +{ + bool negative = arg.value < 0; + + if (frac_bits >= FIXED31_32_BITS_PER_FRACTIONAL_PART) { + ASSERT(frac_bits == FIXED31_32_BITS_PER_FRACTIONAL_PART); + return arg; + } + + if (negative) + arg.value = -arg.value; + arg.value &= (~0ULL) << (FIXED31_32_BITS_PER_FRACTIONAL_PART - frac_bits); + if (negative) + arg.value = -arg.value; + return arg; +} + +struct spl_fixed31_32 spl_fixpt_from_ux_dy(unsigned int value, unsigned int integer_bits, unsigned int fractional_bits); +struct spl_fixed31_32 spl_fixpt_from_int_dy(unsigned int int_value, + unsigned int frac_value, + unsigned int integer_bits, + unsigned int fractional_bits); + +#endif From e560b858620f4a193835cbfbabcee5734c836769 Mon Sep 17 00:00:00 2001 From: Dennis Chan Date: Fri, 19 Jul 2024 15:08:35 +0800 Subject: [PATCH 1404/1868] drm/amd/display: Add Replay Low Refresh Rate parameters in dc type. Why: To supported Low Refresh Rate panel for Replay Feature, Adding some parameters to record Low Refresh Rate information. Reviewed-by: Robin Chen Signed-off-by: Dennis Chan Signed-off-by: Zaeem Mohamed Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/dc_types.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h index 97279b080f3e0..fd6dca7357143 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_types.h @@ -1050,6 +1050,23 @@ union replay_error_status { unsigned char raw; }; +union replay_low_refresh_rate_enable_options { + struct { + //BIT[0-3]: Replay Low Hz Support control + unsigned int ENABLE_LOW_RR_SUPPORT :1; + unsigned int RESERVED_1_3 :3; + //BIT[4-15]: Replay Low Hz Enable Scenarios + unsigned int ENABLE_STATIC_SCREEN :1; + unsigned int ENABLE_FULL_SCREEN_VIDEO :1; + unsigned int ENABLE_GENERAL_UI :1; + unsigned int RESERVED_7_15 :9; + //BIT[16-31]: Replay Low Hz Enable Check + unsigned int ENABLE_STATIC_FLICKER_CHECK :1; + unsigned int RESERVED_17_31 :15; + } bits; + unsigned int raw; +}; + struct replay_config { /* Replay feature is supported */ bool replay_supported; @@ -1073,6 +1090,8 @@ struct replay_config { bool replay_support_fast_resync_in_ultra_sleep_mode; /* Replay error status */ union replay_error_status replay_error_status; + /* Replay Low Hz enable Options */ + union replay_low_refresh_rate_enable_options low_rr_enable_options; }; /* Replay feature flags*/ From 736b941dbd2576c1ca479208553a8bec4015a17c Mon Sep 17 00:00:00 2001 From: Samson Tam Date: Sat, 17 Aug 2024 19:16:53 -0400 Subject: [PATCH 1405/1868] drm/amd/display: add improvements for text display and HDR DWM and MPO [Why] Tune settings for improved text display. Handle differences between DWM and MPO in HDR path. [How] Update sharpener LBA table. Use HDR multiplier to calculate scalar matrix coefficients for HDR RGB MPO path. Update unit tests. Reviewed-by: Jun Lei Signed-off-by: Samson Tam Signed-off-by: Zaeem Mohamed Tested-by: Daniel Wheeler --- .../gpu/drm/amd/display/dc/dc_spl_translate.c | 4 + drivers/gpu/drm/amd/display/dc/spl/Makefile | 2 +- drivers/gpu/drm/amd/display/dc/spl/dc_spl.c | 127 +++++++++++---- .../gpu/drm/amd/display/dc/spl/dc_spl_types.h | 2 + .../drm/amd/display/dc/spl/spl_custom_float.c | 151 ++++++++++++++++++ .../drm/amd/display/dc/spl/spl_custom_float.h | 29 ++++ 6 files changed, 282 insertions(+), 33 deletions(-) create mode 100644 drivers/gpu/drm/amd/display/dc/spl/spl_custom_float.c create mode 100644 drivers/gpu/drm/amd/display/dc/spl/spl_custom_float.h diff --git a/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c b/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c index 92ad0bac182ca..75d00c6a38f4d 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c +++ b/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c @@ -179,6 +179,10 @@ void translate_SPL_in_params_from_pipe_ctx(struct pipe_ctx *pipe_ctx, struct spl */ spl_in->is_fullscreen = dm_helpers_is_fullscreen(pipe_ctx->stream->ctx, pipe_ctx->stream); spl_in->is_hdr_on = dm_helpers_is_hdr_on(pipe_ctx->stream->ctx, pipe_ctx->stream); + spl_in->hdr_multx100 = 0; + if (spl_in->is_hdr_on) + spl_in->hdr_multx100 = (uint32_t)dc_fixpt_floor(dc_fixpt_mul(plane_state->hdr_mult, + dc_fixpt_from_int(100))); } /// @brief Translate SPL output parameters to pipe context diff --git a/drivers/gpu/drm/amd/display/dc/spl/Makefile b/drivers/gpu/drm/amd/display/dc/spl/Makefile index 05764d4d4604b..5edf3c6cf3e2d 100644 --- a/drivers/gpu/drm/amd/display/dc/spl/Makefile +++ b/drivers/gpu/drm/amd/display/dc/spl/Makefile @@ -23,7 +23,7 @@ # Makefile for the 'spl' sub-component of DAL. # It provides the scaling library interface. -SPL = dc_spl.o dc_spl_scl_filters.o dc_spl_scl_easf_filters.o dc_spl_isharp_filters.o dc_spl_filters.o spl_fixpt31_32.o +SPL = dc_spl.o dc_spl_scl_filters.o dc_spl_scl_easf_filters.o dc_spl_isharp_filters.o dc_spl_filters.o spl_fixpt31_32.o spl_custom_float.o AMD_DAL_SPL = $(addprefix $(AMDDALPATH)/dc/spl/,$(SPL)) diff --git a/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c b/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c index f00bb2004d537..059d144bab859 100644 --- a/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c +++ b/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c @@ -538,6 +538,14 @@ static bool spl_is_yuv420(enum spl_pixel_format format) return false; } +static bool spl_is_rgb8(enum spl_pixel_format format) +{ + if (format == SPL_PIXEL_FORMAT_ARGB8888) + return true; + + return false; +} + /*Calculate inits and viewport */ static void spl_calculate_inits_and_viewports(struct spl_in *spl_in, struct spl_scratch *spl_scratch) @@ -773,21 +781,12 @@ static bool enable_easf(struct spl_in *spl_in, struct spl_scratch *spl_scratch) bool skip_easf = false; bool lls_enable_easf = true; - /* - * If lls_pref is LLS_PREF_DONT_CARE, then use pixel format and transfer - * function to determine whether to use LINEAR or NONLINEAR scaling - */ - if (spl_in->lls_pref == LLS_PREF_DONT_CARE) - lls_enable_easf = spl_choose_lls_policy(spl_in->basic_in.format, - spl_in->basic_in.tf_type, spl_in->basic_in.tf_predefined_type, - &spl_in->lls_pref); + if (spl_in->disable_easf) + skip_easf = true; vratio = spl_fixpt_ceil(spl_scratch->scl_data.ratios.vert); hratio = spl_fixpt_ceil(spl_scratch->scl_data.ratios.horz); - if (!lls_enable_easf || spl_in->disable_easf) - skip_easf = true; - /* * No EASF support for downscaling > 2:1 * EASF support for upscaling or downscaling up to 2:1 @@ -795,6 +794,18 @@ static bool enable_easf(struct spl_in *spl_in, struct spl_scratch *spl_scratch) if ((vratio > 2) || (hratio > 2)) skip_easf = true; + /* + * If lls_pref is LLS_PREF_DONT_CARE, then use pixel format and transfer + * function to determine whether to use LINEAR or NONLINEAR scaling + */ + if (spl_in->lls_pref == LLS_PREF_DONT_CARE) + lls_enable_easf = spl_choose_lls_policy(spl_in->basic_in.format, + spl_in->basic_in.tf_type, spl_in->basic_in.tf_predefined_type, + &spl_in->lls_pref); + + if (!lls_enable_easf) + skip_easf = true; + /* Check for linear scaling or EASF preferred */ if (spl_in->lls_pref != LLS_PREF_YES && !spl_in->prefer_easf) skip_easf = true; @@ -819,13 +830,13 @@ static bool spl_get_isharp_en(struct spl_in *spl_in, struct spl_taps taps = spl_scratch->scl_data.taps; bool fullscreen = spl_is_video_fullscreen(spl_in); - vratio = spl_fixpt_ceil(spl_scratch->scl_data.ratios.vert); - hratio = spl_fixpt_ceil(spl_scratch->scl_data.ratios.horz); - /* Return if adaptive sharpness is disabled */ if (spl_in->adaptive_sharpness.enable == false) return enable_isharp; + vratio = spl_fixpt_ceil(spl_scratch->scl_data.ratios.vert); + hratio = spl_fixpt_ceil(spl_scratch->scl_data.ratios.horz); + /* No iSHARP support for downscaling */ if (vratio > 1 || hratio > 1) return enable_isharp; @@ -1154,10 +1165,44 @@ static void spl_set_dscl_prog_data(struct spl_in *spl_in, struct spl_scratch *sp spl_set_filters_data(dscl_prog_data, data, enable_easf_v, enable_easf_h); } +/* Calculate C0-C3 coefficients based on HDR_mult */ +static void spl_calculate_c0_c3_hdr(struct dscl_prog_data *dscl_prog_data, uint32_t hdr_multx100) +{ + struct spl_fixed31_32 hdr_mult, c0_mult, c1_mult, c2_mult; + struct spl_fixed31_32 c0_calc, c1_calc, c2_calc; + struct spl_custom_float_format fmt; + + SPL_ASSERT(hdr_multx100); + hdr_mult = spl_fixpt_from_fraction((long long)hdr_multx100, 100LL); + c0_mult = spl_fixpt_from_fraction(2126LL, 10000LL); + c1_mult = spl_fixpt_from_fraction(7152LL, 10000LL); + c2_mult = spl_fixpt_from_fraction(722LL, 10000LL); + + c0_calc = spl_fixpt_mul(hdr_mult, spl_fixpt_mul(c0_mult, spl_fixpt_from_fraction( + 16384LL, 125LL))); + c1_calc = spl_fixpt_mul(hdr_mult, spl_fixpt_mul(c1_mult, spl_fixpt_from_fraction( + 16384LL, 125LL))); + c2_calc = spl_fixpt_mul(hdr_mult, spl_fixpt_mul(c2_mult, spl_fixpt_from_fraction( + 16384LL, 125LL))); + + fmt.exponenta_bits = 5; + fmt.mantissa_bits = 10; + fmt.sign = true; + + // fp1.5.10, C0 coefficient (LN_rec709: HDR_MULT * 0.212600 * 2^14/125) + spl_convert_to_custom_float_format(c0_calc, &fmt, &dscl_prog_data->easf_matrix_c0); + // fp1.5.10, C1 coefficient (LN_rec709: HDR_MULT * 0.715200 * 2^14/125) + spl_convert_to_custom_float_format(c1_calc, &fmt, &dscl_prog_data->easf_matrix_c1); + // fp1.5.10, C2 coefficient (LN_rec709: HDR_MULT * 0.072200 * 2^14/125) + spl_convert_to_custom_float_format(c2_calc, &fmt, &dscl_prog_data->easf_matrix_c2); + dscl_prog_data->easf_matrix_c3 = 0x0; // fp1.5.10, C3 coefficient +} + /* Set EASF data */ static void spl_set_easf_data(struct spl_scratch *spl_scratch, struct spl_out *spl_out, bool enable_easf_v, bool enable_easf_h, enum linear_light_scaling lls_pref, - enum spl_pixel_format format, enum system_setup setup) + enum spl_pixel_format format, enum system_setup setup, + uint32_t hdr_multx100) { struct dscl_prog_data *dscl_prog_data = spl_out->dscl_prog_data; if (enable_easf_v) { @@ -1463,16 +1508,10 @@ static void spl_set_easf_data(struct spl_scratch *spl_scratch, struct spl_out *s if (lls_pref == LLS_PREF_YES) { dscl_prog_data->easf_ltonl_en = 1; // Linear input - if (setup == HDR_L) { - dscl_prog_data->easf_matrix_c0 = - 0x504E; // fp1.5.10, C0 coefficient (LN_BT2020: 0.2627 * (2^14)/125 = 34.43750000) - dscl_prog_data->easf_matrix_c1 = - 0x558E; // fp1.5.10, C1 coefficient (LN_BT2020: 0.6780 * (2^14)/125 = 88.87500000) - dscl_prog_data->easf_matrix_c2 = - 0x47C6; // fp1.5.10, C2 coefficient (LN_BT2020: 0.0593 * (2^14)/125 = 7.77343750) - dscl_prog_data->easf_matrix_c3 = - 0x0; // fp1.5.10, C3 coefficient - } else { // SDR_L + if ((setup == HDR_L) && (spl_is_rgb8(format))) { + /* Calculate C0-C3 coefficients based on HDR multiplier */ + spl_calculate_c0_c3_hdr(dscl_prog_data, hdr_multx100); + } else { // HDR_L ( DWM ) and SDR_L dscl_prog_data->easf_matrix_c0 = 0x4EF7; // fp1.5.10, C0 coefficient (LN_rec709: 0.2126 * (2^14)/125 = 27.86590720) dscl_prog_data->easf_matrix_c1 = @@ -1570,9 +1609,9 @@ static void spl_set_isharp_data(struct dscl_prog_data *dscl_prog_data, dscl_prog_data->isharp_lba.base_seg[1] = 63; // ISHARP LBA PWL for Seg 1. BASE value in U0.6 format dscl_prog_data->isharp_lba.slope_seg[1] = 0; // ISHARP LBA for Seg 1. SLOPE value in S5.3 format // ISHARP_LBA_PWL_SEG2: ISHARP LBA PWL Segment 2 - dscl_prog_data->isharp_lba.in_seg[2] = 312; // ISHARP LBA PWL for Seg 2. INPUT value in U0.10 format + dscl_prog_data->isharp_lba.in_seg[2] = 450; // ISHARP LBA PWL for Seg 2. INPUT value in U0.10 format dscl_prog_data->isharp_lba.base_seg[2] = 63; // ISHARP LBA PWL for Seg 2. BASE value in U0.6 format - dscl_prog_data->isharp_lba.slope_seg[2] = 0x1D9; // ISHARP LBA for Seg 2. SLOPE value in S5.3 format = -39 + dscl_prog_data->isharp_lba.slope_seg[2] = 0x18D; // ISHARP LBA for Seg 2. SLOPE value in S5.3 format = -115 // ISHARP_LBA_PWL_SEG3: ISHARP LBA PWL Segment 3 dscl_prog_data->isharp_lba.in_seg[3] = 520; // ISHARP LBA PWL for Seg 3.INPUT value in U0.10 format dscl_prog_data->isharp_lba.base_seg[3] = 0; // ISHARP LBA PWL for Seg 3. BASE value in U0.6 format @@ -1584,19 +1623,43 @@ static void spl_set_isharp_data(struct dscl_prog_data *dscl_prog_data, // ISHARP_LBA_PWL_SEG5: ISHARP LBA PWL Segment 5 dscl_prog_data->isharp_lba.in_seg[5] = 520; // ISHARP LBA PWL for Seg 5.INPUT value in U0.10 format dscl_prog_data->isharp_lba.base_seg[5] = 0; // ISHARP LBA PWL for Seg 5. BASE value in U0.6 format - } else { + } else if (setup == HDR_L) { // ISHARP_LBA_PWL_SEG0: ISHARP Local Brightness Adjustment PWL Segment 0 dscl_prog_data->isharp_lba.in_seg[0] = 0; // ISHARP LBA PWL for Seg 0. INPUT value in U0.10 format dscl_prog_data->isharp_lba.base_seg[0] = 0; // ISHARP LBA PWL for Seg 0. BASE value in U0.6 format dscl_prog_data->isharp_lba.slope_seg[0] = 32; // ISHARP LBA for Seg 0. SLOPE value in S5.3 format // ISHARP_LBA_PWL_SEG1: ISHARP LBA PWL Segment 1 - dscl_prog_data->isharp_lba.in_seg[1] = 256; // ISHARP LBA PWL for Seg 1. INPUT value in U0.10 format + dscl_prog_data->isharp_lba.in_seg[1] = 254; // ISHARP LBA PWL for Seg 1. INPUT value in U0.10 format + dscl_prog_data->isharp_lba.base_seg[1] = 63; // ISHARP LBA PWL for Seg 1. BASE value in U0.6 format + dscl_prog_data->isharp_lba.slope_seg[1] = 0; // ISHARP LBA for Seg 1. SLOPE value in S5.3 format + // ISHARP_LBA_PWL_SEG2: ISHARP LBA PWL Segment 2 + dscl_prog_data->isharp_lba.in_seg[2] = 559; // ISHARP LBA PWL for Seg 2. INPUT value in U0.10 format + dscl_prog_data->isharp_lba.base_seg[2] = 63; // ISHARP LBA PWL for Seg 2. BASE value in U0.6 format + dscl_prog_data->isharp_lba.slope_seg[2] = 0x10C; // ISHARP LBA for Seg 2. SLOPE value in S5.3 format = -244 + // ISHARP_LBA_PWL_SEG3: ISHARP LBA PWL Segment 3 + dscl_prog_data->isharp_lba.in_seg[3] = 592; // ISHARP LBA PWL for Seg 3.INPUT value in U0.10 format + dscl_prog_data->isharp_lba.base_seg[3] = 0; // ISHARP LBA PWL for Seg 3. BASE value in U0.6 format + dscl_prog_data->isharp_lba.slope_seg[3] = 0; // ISHARP LBA for Seg 3. SLOPE value in S5.3 format + // ISHARP_LBA_PWL_SEG4: ISHARP LBA PWL Segment 4 + dscl_prog_data->isharp_lba.in_seg[4] = 1023; // ISHARP LBA PWL for Seg 4.INPUT value in U0.10 format + dscl_prog_data->isharp_lba.base_seg[4] = 0; // ISHARP LBA PWL for Seg 4. BASE value in U0.6 format + dscl_prog_data->isharp_lba.slope_seg[4] = 0; // ISHARP LBA for Seg 4. SLOPE value in S5.3 format + // ISHARP_LBA_PWL_SEG5: ISHARP LBA PWL Segment 5 + dscl_prog_data->isharp_lba.in_seg[5] = 1023; // ISHARP LBA PWL for Seg 5.INPUT value in U0.10 format + dscl_prog_data->isharp_lba.base_seg[5] = 0; // ISHARP LBA PWL for Seg 5. BASE value in U0.6 format + } else { + // ISHARP_LBA_PWL_SEG0: ISHARP Local Brightness Adjustment PWL Segment 0 + dscl_prog_data->isharp_lba.in_seg[0] = 0; // ISHARP LBA PWL for Seg 0. INPUT value in U0.10 format + dscl_prog_data->isharp_lba.base_seg[0] = 0; // ISHARP LBA PWL for Seg 0. BASE value in U0.6 format + dscl_prog_data->isharp_lba.slope_seg[0] = 40; // ISHARP LBA for Seg 0. SLOPE value in S5.3 format + // ISHARP_LBA_PWL_SEG1: ISHARP LBA PWL Segment 1 + dscl_prog_data->isharp_lba.in_seg[1] = 204; // ISHARP LBA PWL for Seg 1. INPUT value in U0.10 format dscl_prog_data->isharp_lba.base_seg[1] = 63; // ISHARP LBA PWL for Seg 1. BASE value in U0.6 format dscl_prog_data->isharp_lba.slope_seg[1] = 0; // ISHARP LBA for Seg 1. SLOPE value in S5.3 format // ISHARP_LBA_PWL_SEG2: ISHARP LBA PWL Segment 2 - dscl_prog_data->isharp_lba.in_seg[2] = 614; // ISHARP LBA PWL for Seg 2. INPUT value in U0.10 format + dscl_prog_data->isharp_lba.in_seg[2] = 818; // ISHARP LBA PWL for Seg 2. INPUT value in U0.10 format dscl_prog_data->isharp_lba.base_seg[2] = 63; // ISHARP LBA PWL for Seg 2. BASE value in U0.6 format - dscl_prog_data->isharp_lba.slope_seg[2] = 0x1EC; // ISHARP LBA for Seg 2. SLOPE value in S5.3 format = -20 + dscl_prog_data->isharp_lba.slope_seg[2] = 0x1D9; // ISHARP LBA for Seg 2. SLOPE value in S5.3 format = -39 // ISHARP_LBA_PWL_SEG3: ISHARP LBA PWL Segment 3 dscl_prog_data->isharp_lba.in_seg[3] = 1023; // ISHARP LBA PWL for Seg 3.INPUT value in U0.10 format dscl_prog_data->isharp_lba.base_seg[3] = 0; // ISHARP LBA PWL for Seg 3. BASE value in U0.6 format @@ -1696,7 +1759,7 @@ bool spl_calculate_scaler_params(struct spl_in *spl_in, struct spl_out *spl_out) // Set EASF spl_set_easf_data(&spl_scratch, spl_out, enable_easf_v, enable_easf_h, spl_in->lls_pref, - spl_in->basic_in.format, setup); + spl_in->basic_in.format, setup, spl_in->hdr_multx100); // Set iSHARP vratio = spl_fixpt_ceil(spl_scratch.scl_data.ratios.vert); diff --git a/drivers/gpu/drm/amd/display/dc/spl/dc_spl_types.h b/drivers/gpu/drm/amd/display/dc/spl/dc_spl_types.h index 3d61c98258076..7c1a21c2305d1 100644 --- a/drivers/gpu/drm/amd/display/dc/spl/dc_spl_types.h +++ b/drivers/gpu/drm/amd/display/dc/spl/dc_spl_types.h @@ -10,6 +10,7 @@ #define SPL_ASSERT(_bool) ((void *)0) #endif #include "spl_fixpt31_32.h" // fixed31_32 and related functions +#include "spl_custom_float.h" // custom float and related functions struct spl_size { uint32_t width; @@ -504,6 +505,7 @@ struct spl_in { bool is_hdr_on; int h_active; int v_active; + int hdr_multx100; }; // end of SPL inputs diff --git a/drivers/gpu/drm/amd/display/dc/spl/spl_custom_float.c b/drivers/gpu/drm/amd/display/dc/spl/spl_custom_float.c new file mode 100644 index 0000000000000..be2f34d034c5c --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/spl/spl_custom_float.c @@ -0,0 +1,151 @@ +// SPDX-License-Identifier: MIT +// +// Copyright 2024 Advanced Micro Devices, Inc. + +#include "spl_debug.h" +#include "spl_custom_float.h" + +static bool spl_build_custom_float(struct spl_fixed31_32 value, + const struct spl_custom_float_format *format, + bool *negative, + uint32_t *mantissa, + uint32_t *exponenta) +{ + uint32_t exp_offset = (1 << (format->exponenta_bits - 1)) - 1; + + const struct spl_fixed31_32 mantissa_constant_plus_max_fraction = + spl_fixpt_from_fraction((1LL << (format->mantissa_bits + 1)) - 1, + 1LL << format->mantissa_bits); + + struct spl_fixed31_32 mantiss; + + if (spl_fixpt_eq(value, spl_fixpt_zero)) { + *negative = false; + *mantissa = 0; + *exponenta = 0; + return true; + } + + if (spl_fixpt_lt(value, spl_fixpt_zero)) { + *negative = format->sign; + value = spl_fixpt_neg(value); + } else { + *negative = false; + } + + if (spl_fixpt_lt(value, spl_fixpt_one)) { + uint32_t i = 1; + + do { + value = spl_fixpt_shl(value, 1); + ++i; + } while (spl_fixpt_lt(value, spl_fixpt_one)); + + --i; + + if (exp_offset <= i) { + *mantissa = 0; + *exponenta = 0; + return true; + } + + *exponenta = exp_offset - i; + } else if (spl_fixpt_le(mantissa_constant_plus_max_fraction, value)) { + uint32_t i = 1; + + do { + value = spl_fixpt_shr(value, 1); + ++i; + } while (spl_fixpt_lt(mantissa_constant_plus_max_fraction, value)); + + *exponenta = exp_offset + i - 1; + } else { + *exponenta = exp_offset; + } + + mantiss = spl_fixpt_sub(value, spl_fixpt_one); + + if (spl_fixpt_lt(mantiss, spl_fixpt_zero) || + spl_fixpt_lt(spl_fixpt_one, mantiss)) + mantiss = spl_fixpt_zero; + else + mantiss = spl_fixpt_shl(mantiss, format->mantissa_bits); + + *mantissa = spl_fixpt_floor(mantiss); + + return true; +} + +static bool spl_setup_custom_float(const struct spl_custom_float_format *format, + bool negative, + uint32_t mantissa, + uint32_t exponenta, + uint32_t *result) +{ + uint32_t i = 0; + uint32_t j = 0; + uint32_t value = 0; + + /* verification code: + * once calculation is ok we can remove it + */ + + const uint32_t mantissa_mask = + (1 << (format->mantissa_bits + 1)) - 1; + + const uint32_t exponenta_mask = + (1 << (format->exponenta_bits + 1)) - 1; + + if (mantissa & ~mantissa_mask) { + SPL_BREAK_TO_DEBUGGER(); + mantissa = mantissa_mask; + } + + if (exponenta & ~exponenta_mask) { + SPL_BREAK_TO_DEBUGGER(); + exponenta = exponenta_mask; + } + + /* end of verification code */ + + while (i < format->mantissa_bits) { + uint32_t mask = 1 << i; + + if (mantissa & mask) + value |= mask; + + ++i; + } + + while (j < format->exponenta_bits) { + uint32_t mask = 1 << j; + + if (exponenta & mask) + value |= mask << i; + + ++j; + } + + if (negative && format->sign) + value |= 1 << (i + j); + + *result = value; + + return true; +} + +bool spl_convert_to_custom_float_format(struct spl_fixed31_32 value, + const struct spl_custom_float_format *format, + uint32_t *result) +{ + uint32_t mantissa; + uint32_t exponenta; + bool negative; + + return spl_build_custom_float(value, format, &negative, &mantissa, &exponenta) && + spl_setup_custom_float(format, + negative, + mantissa, + exponenta, + result); +} diff --git a/drivers/gpu/drm/amd/display/dc/spl/spl_custom_float.h b/drivers/gpu/drm/amd/display/dc/spl/spl_custom_float.h new file mode 100644 index 0000000000000..cdc4e107b9de4 --- /dev/null +++ b/drivers/gpu/drm/amd/display/dc/spl/spl_custom_float.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: MIT */ + +/* Copyright 2024 Advanced Micro Devices, Inc. */ + +#ifndef SPL_CUSTOM_FLOAT_H_ +#define SPL_CUSTOM_FLOAT_H_ + +#include "spl_os_types.h" +#include "spl_fixpt31_32.h" + +struct spl_custom_float_format { + uint32_t mantissa_bits; + uint32_t exponenta_bits; + bool sign; +}; + +struct spl_custom_float_value { + uint32_t mantissa; + uint32_t exponenta; + uint32_t value; + bool negative; +}; + +bool spl_convert_to_custom_float_format( + struct spl_fixed31_32 value, + const struct spl_custom_float_format *format, + uint32_t *result); + +#endif //SPL_CUSTOM_FLOAT_H_ From f81bb8342aa778fc57f0f7ea48e7637d680a20b1 Mon Sep 17 00:00:00 2001 From: Samson Tam Date: Sat, 17 Aug 2024 19:24:27 -0400 Subject: [PATCH 1406/1868] drm/amd/display: add sharpness support for windowed YUV420 video [Why] Previous only applied sharpness for fullscreen YUV420 video. [How] Remove fullscrene restriction and apply sharpness for windowed YUV420 video as well. Reviewed-by: Jun Lei Signed-off-by: Samson Tam Signed-off-by: Zaeem Mohamed Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/spl/dc_spl.c | 13 +------------ 1 file changed, 1 insertion(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c b/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c index 059d144bab859..b6d1cfc494fca 100644 --- a/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c +++ b/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c @@ -813,14 +813,6 @@ static bool enable_easf(struct spl_in *spl_in, struct spl_scratch *spl_scratch) return skip_easf; } -/* Check if video is in fullscreen mode */ -static bool spl_is_video_fullscreen(struct spl_in *spl_in) -{ - if (spl_is_yuv420(spl_in->basic_in.format) && spl_in->is_fullscreen) - return true; - return false; -} - static bool spl_get_isharp_en(struct spl_in *spl_in, struct spl_scratch *spl_scratch) { @@ -828,7 +820,6 @@ static bool spl_get_isharp_en(struct spl_in *spl_in, int vratio = 0; int hratio = 0; struct spl_taps taps = spl_scratch->scl_data.taps; - bool fullscreen = spl_is_video_fullscreen(spl_in); /* Return if adaptive sharpness is disabled */ if (spl_in->adaptive_sharpness.enable == false) @@ -845,10 +836,8 @@ static bool spl_get_isharp_en(struct spl_in *spl_in, /* * Apply sharpness to all RGB surfaces and to - * NV12/P010 surfaces if in fullscreen + * NV12/P010 surfaces */ - if (spl_is_yuv420(spl_in->basic_in.format) && !fullscreen) - return enable_isharp; /* * Apply sharpness if supports horizontal taps 4,6 AND From 70a1c41afff3cb6e3040f50c4f8bcf44a8bd1203 Mon Sep 17 00:00:00 2001 From: Aric Cyr Date: Sun, 18 Aug 2024 21:39:06 -0400 Subject: [PATCH 1407/1868] drm/amd/display: 3.2.298 This version brings along the following fixes: - Fix MS/MP mismatches in dml21 for dcn401 - Resolved Coverity issues - Add back quality EASF and ISHARP and dc dependency changes - Add sharpness support for windowed YUV420 video - Add improvements for text display and HDR DWM and MPO - Fix Synaptics Cascaded Panamera DSC Determination - Allocate DCN35 clock table transfer buffers in GART - Add Replay Low Refresh Rate parameters in dc type Acked-by: Leo Li Signed-off-by: Aric Cyr Signed-off-by: Zaeem Mohamed Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 8e072e60fa4cb..20b97b5e76846 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -55,7 +55,7 @@ struct aux_payload; struct set_config_cmd_payload; struct dmub_notification; -#define DC_VER "3.2.297" +#define DC_VER "3.2.298" #define MAX_SURFACES 3 #define MAX_PLANES 6 From 34f71f1af5427b193c3004a7bd7b07ca7d240360 Mon Sep 17 00:00:00 2001 From: Fangzhi Zuo Date: Fri, 2 Aug 2024 15:03:39 -0400 Subject: [PATCH 1408/1868] drm/amd/display: Add DSC Debug Log Add DSC log in each critical routines to facilitate debugging. Reviewed-by: Rodrigo Siqueira Signed-off-by: Fangzhi Zuo Signed-off-by: Zaeem Mohamed Tested-by: Daniel Wheeler --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 9 +- .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 22 +-- .../display/amdgpu_dm/amdgpu_dm_mst_types.c | 131 ++++++++++++++---- 3 files changed, 121 insertions(+), 41 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 33110affea322..1e5c4397be86d 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -6639,7 +6639,8 @@ static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector, dc_link_get_highest_encoding_format(aconnector->dc_link), &stream->timing.dsc_cfg)) { stream->timing.flags.DSC = 1; - DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from SST RX\n", __func__, drm_connector->name); + DRM_DEBUG_DRIVER("%s: SST_DSC [%s] DSC is selected from SST RX\n", + __func__, drm_connector->name); } } else if (sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) { timing_bw_in_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing, @@ -6658,7 +6659,7 @@ static void apply_dsc_policy_for_stream(struct amdgpu_dm_connector *aconnector, dc_link_get_highest_encoding_format(aconnector->dc_link), &stream->timing.dsc_cfg)) { stream->timing.flags.DSC = 1; - DRM_DEBUG_DRIVER("%s: [%s] DSC is selected from DP-HDMI PCON\n", + DRM_DEBUG_DRIVER("%s: SST_DSC [%s] DSC is selected from DP-HDMI PCON\n", __func__, drm_connector->name); } } @@ -11893,7 +11894,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, if (dc_resource_is_dsc_encoding_supported(dc)) { ret = compute_mst_dsc_configs_for_state(state, dm_state->context, vars); if (ret) { - drm_dbg_atomic(dev, "compute_mst_dsc_configs_for_state() failed\n"); + drm_dbg_atomic(dev, "MST_DSC compute_mst_dsc_configs_for_state() failed\n"); ret = -EINVAL; goto fail; } @@ -11919,7 +11920,7 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, #if defined(HAVE_DRM_DP_MST_ATOMIC_ENABLE_DSC) ret = drm_dp_mst_atomic_check(state); if (ret) { - drm_dbg_atomic(dev, "drm_dp_mst_atomic_check() failed\n"); + drm_dbg_atomic(dev, "MST drm_dp_mst_atomic_check() failed\n"); goto fail; } #endif diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index fc314a96b302a..40688990981a5 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -980,9 +980,9 @@ static uint8_t write_dsc_enable_synaptics_non_virtual_dpcd_mst( uint8_t ret = 0; #ifdef HAVE_DRM_DP_AUX_DRM_DEV drm_dbg_dp(aux->drm_dev, - "Configure DSC to non-virtual dpcd synaptics\n"); + "MST_DSC Configure DSC to non-virtual dpcd synaptics\n"); #else - DRM_DEBUG_KMS("Configure DSC to non-virtual dpcd synaptics\n"); + DRM_DEBUG_KMS("MST_DSC Configure DSC to non-virtual dpcd synaptics\n"); #endif if (enable) { @@ -996,7 +996,7 @@ static uint8_t write_dsc_enable_synaptics_non_virtual_dpcd_mst( apply_synaptics_fifo_reset_wa(aux); ret = drm_dp_dpcd_write(aux, DP_DSC_ENABLE, &enable, 1); - DRM_INFO("Send DSC enable to synaptics\n"); + DRM_INFO("MST_DSC Send DSC enable to synaptics\n"); } else { /* Synaptics hub not support virtual dpcd, @@ -1005,7 +1005,7 @@ static uint8_t write_dsc_enable_synaptics_non_virtual_dpcd_mst( */ if (!stream->link->link_status.link_active) { ret = drm_dp_dpcd_write(aux, DP_DSC_ENABLE, &enable, 1); - DRM_INFO("Send DSC disable to synaptics\n"); + DRM_INFO("MST_DSC Send DSC disable to synaptics\n"); } } @@ -1052,14 +1052,14 @@ bool dm_helpers_dp_write_dsc_enable( DP_DSC_ENABLE, &enable_passthrough, 1); drm_dbg_dp(dev, - "Sent DSC pass-through enable to virtual dpcd port, ret = %u\n", + "MST_DSC Sent DSC pass-through enable to virtual dpcd port, ret = %u\n", ret); } ret = drm_dp_dpcd_write(aconnector->dsc_aux, DP_DSC_ENABLE, &enable_dsc, 1); drm_dbg_dp(dev, - "Sent DSC decoding enable to %s port, ret = %u\n", + "MST_DSC Sent DSC decoding enable to %s port, ret = %u\n", (port->passthrough_aux) ? "remote RX" : "virtual dpcd", ret); @@ -1067,7 +1067,7 @@ bool dm_helpers_dp_write_dsc_enable( ret = drm_dp_dpcd_write(aconnector->dsc_aux, DP_DSC_ENABLE, &enable_dsc, 1); drm_dbg_dp(dev, - "Sent DSC decoding disable to %s port, ret = %u\n", + "MST_DSC Sent DSC decoding disable to %s port, ret = %u\n", (port->passthrough_aux) ? "remote RX" : "virtual dpcd", ret); @@ -1077,7 +1077,7 @@ bool dm_helpers_dp_write_dsc_enable( DP_DSC_ENABLE, &enable_passthrough, 1); drm_dbg_dp(dev, - "Sent DSC pass-through disable to virtual dpcd port, ret = %u\n", + "MST_DSC Sent DSC pass-through disable to virtual dpcd port, ret = %u\n", ret); } } @@ -1092,12 +1092,12 @@ bool dm_helpers_dp_write_dsc_enable( if (stream->sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_NONE) { ret = dm_helpers_dp_write_dpcd(ctx, stream->link, DP_DSC_ENABLE, &enable_dsc, 1); drm_dbg_dp(dev, - "Send DSC %s to SST RX\n", + "SST_DSC Send DSC %s to SST RX\n", enable_dsc ? "enable" : "disable"); } else if (stream->sink->link->dpcd_caps.dongle_type == DISPLAY_DONGLE_DP_HDMI_CONVERTER) { ret = dm_helpers_dp_write_dpcd(ctx, stream->link, DP_DSC_ENABLE, &enable_dsc, 1); drm_dbg_dp(dev, - "Send DSC %s to DP-HDMI PCON\n", + "SST_DSC Send DSC %s to DP-HDMI PCON\n", enable_dsc ? "enable" : "disable"); } } @@ -1534,4 +1534,4 @@ bool dm_helpers_is_hdr_on(struct dc_context *ctx, struct dc_stream_state *stream { // TODO return false; -} \ No newline at end of file +} diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 268ef6cafc694..dad93a72696ef 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -647,6 +647,8 @@ dm_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr, if (!aconnector) return NULL; + DRM_DEBUG_DRIVER("%s: Create aconnector 0x%p for port 0x%p\n", __func__, aconnector, port); + connector = &aconnector->base; aconnector->mst_output_port = port; aconnector->mst_root = master; @@ -1044,11 +1046,11 @@ static void set_dsc_configs_from_fairness_vars(struct dsc_mst_fairness_params *p if (params[i].sink) { if (params[i].sink->sink_signal != SIGNAL_TYPE_VIRTUAL && params[i].sink->sink_signal != SIGNAL_TYPE_NONE) - DRM_DEBUG_DRIVER("%s i=%d dispname=%s\n", __func__, i, + DRM_DEBUG_DRIVER("MST_DSC %s i=%d dispname=%s\n", __func__, i, params[i].sink->edid_caps.display_name); } - DRM_DEBUG_DRIVER("dsc=%d bits_per_pixel=%d pbn=%d\n", + DRM_DEBUG_DRIVER("MST_DSC dsc=%d bits_per_pixel=%d pbn=%d\n", params[i].timing->flags.DSC, params[i].timing->dsc_cfg.bits_per_pixel, vars[i + k].pbn); @@ -1268,6 +1270,7 @@ static int try_disable_dsc(struct drm_atomic_state *state, if (next_index == -1) break; + DRM_DEBUG_DRIVER("MST_DSC index #%d, try no compression\n", next_index); vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.stream_kbps, fec_overhead_multiplier_x1000); ret = drm_dp_atomic_find_time_slots(state, params[next_index].port->mgr, @@ -1282,9 +1285,11 @@ static int try_disable_dsc(struct drm_atomic_state *state, ret = drm_dp_mst_atomic_check(state); if (ret == 0) { + DRM_DEBUG_DRIVER("MST_DSC index #%d, greedily disable dsc\n", next_index); vars[next_index].dsc_enabled = false; vars[next_index].bpp_x16 = 0; } else { + DRM_DEBUG_DRIVER("MST_DSC index #%d, restore minimum compression\n", next_index); vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.stream_kbps, fec_overhead_multiplier_x1000); ret = drm_dp_atomic_find_time_slots(state, params[next_index].port->mgr, @@ -1304,6 +1309,15 @@ static int try_disable_dsc(struct drm_atomic_state *state, return 0; } +static void log_dsc_params(int count, struct dsc_mst_fairness_vars *vars, int k) +{ + int i; + + for (i = 0; i < count; i++) + DRM_DEBUG_DRIVER("MST_DSC DSC params: stream #%d --- dsc_enabled = %d, bpp_x16 = %d, pbn = %d\n", + i, vars[i + k].dsc_enabled, vars[i + k].bpp_x16, vars[i + k].pbn); +} + static int compute_mst_dsc_configs_for_link(struct drm_atomic_state *state, struct dc_state *dc_state, struct dc_link *dc_link, @@ -1326,6 +1340,7 @@ static int compute_mst_dsc_configs_for_link(struct drm_atomic_state *state, return PTR_ERR(mst_state); /* Set up params */ + DRM_DEBUG_DRIVER("%s: MST_DSC Set up params for %d streams\n", __func__, dc_state->stream_count); for (i = 0; i < dc_state->stream_count; i++) { struct dc_dsc_policy dsc_policy = {0}; @@ -1367,6 +1382,9 @@ static int compute_mst_dsc_configs_for_link(struct drm_atomic_state *state, params[count].bw_range.stream_kbps = dc_bandwidth_in_kbps_from_timing(&stream->timing, dc_link_get_highest_encoding_format(dc_link)); + DRM_DEBUG_DRIVER("MST_DSC #%d stream 0x%p - max_kbps = %u, min_kbps = %u, uncompressed_kbps = %u\n", + count, stream, params[count].bw_range.max_kbps, params[count].bw_range.min_kbps, + params[count].bw_range.stream_kbps); count++; } @@ -1381,6 +1399,7 @@ static int compute_mst_dsc_configs_for_link(struct drm_atomic_state *state, *link_vars_start_index += count; /* Try no compression */ + DRM_DEBUG_DRIVER("MST_DSC Try no compression\n"); for (i = 0; i < count; i++) { vars[i + k].aconnector = params[i].aconnector; vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.stream_kbps, fec_overhead_multiplier_x1000); @@ -1403,7 +1422,10 @@ static int compute_mst_dsc_configs_for_link(struct drm_atomic_state *state, return ret; } + log_dsc_params(count, vars, k); + /* Try max compression */ + DRM_DEBUG_DRIVER("MST_DSC Try max compression\n"); for (i = 0; i < count; i++) { if (params[i].compression_possible && params[i].clock_force_enable != DSC_CLK_FORCE_DISABLE) { vars[i + k].pbn = kbps_to_peak_pbn(params[i].bw_range.min_kbps, fec_overhead_multiplier_x1000); @@ -1435,14 +1457,26 @@ static int compute_mst_dsc_configs_for_link(struct drm_atomic_state *state, if (ret != 0) return ret; + log_dsc_params(count, vars, k); + /* Optimize degree of compression */ + DRM_DEBUG_DRIVER("MST_DSC Try optimize compression\n"); ret = increase_dsc_bpp(state, mst_state, dc_link, params, vars, count, k); - if (ret < 0) + if (ret < 0) { + DRM_DEBUG_DRIVER("MST_DSC Failed to optimize compression\n"); return ret; + } + log_dsc_params(count, vars, k); + + DRM_DEBUG_DRIVER("MST_DSC Try disable compression\n"); ret = try_disable_dsc(state, dc_link, params, vars, count, k); - if (ret < 0) + if (ret < 0) { + DRM_DEBUG_DRIVER("MST_DSC Failed to disable compression\n"); return ret; + } + + log_dsc_params(count, vars, k); set_dsc_configs_from_fairness_vars(params, vars, count, k); @@ -1464,17 +1498,19 @@ static bool is_dsc_need_re_compute( /* only check phy used by dsc mst branch */ if (dc_link->type != dc_connection_mst_branch) - return false; + goto out; /* add a check for older MST DSC with no virtual DPCDs */ if (needs_dsc_aux_workaround(dc_link) && (!(dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT || dc_link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_PASSTHROUGH_SUPPORT))) - return false; + goto out; for (i = 0; i < MAX_PIPES; i++) stream_on_link[i] = NULL; + DRM_DEBUG_DRIVER("%s: MST_DSC check on %d streams in new dc_state\n", __func__, dc_state->stream_count); + /* check if there is mode change in new request */ for (i = 0; i < dc_state->stream_count; i++) { struct drm_crtc_state *new_crtc_state; @@ -1484,6 +1520,8 @@ static bool is_dsc_need_re_compute( if (!stream) continue; + DRM_DEBUG_DRIVER("%s:%d MST_DSC checking #%d stream 0x%p\n", __func__, __LINE__, i, stream); + /* check if stream using the same link for mst */ if (stream->link != dc_link) continue; @@ -1496,8 +1534,11 @@ static bool is_dsc_need_re_compute( new_stream_on_link_num++; new_conn_state = drm_atomic_get_new_connector_state(state, &aconnector->base); - if (!new_conn_state) + if (!new_conn_state) { + DRM_DEBUG_DRIVER("%s:%d MST_DSC no new_conn_state for stream 0x%p, aconnector 0x%p\n", + __func__, __LINE__, stream, aconnector); continue; + } if (IS_ERR(new_conn_state)) continue; @@ -1506,21 +1547,36 @@ static bool is_dsc_need_re_compute( continue; new_crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc); - if (!new_crtc_state) + if (!new_crtc_state) { + DRM_DEBUG_DRIVER("%s:%d MST_DSC no new_crtc_state for crtc of stream 0x%p, aconnector 0x%p\n", + __func__, __LINE__, stream, aconnector); continue; + } if (IS_ERR(new_crtc_state)) continue; if (new_crtc_state->enable && new_crtc_state->active) { if (new_crtc_state->mode_changed || new_crtc_state->active_changed || - new_crtc_state->connectors_changed) - return true; + new_crtc_state->connectors_changed) { + DRM_DEBUG_DRIVER("%s:%d MST_DSC dsc recompte required." + "stream 0x%p in new dc_state\n", + __func__, __LINE__, stream); + is_dsc_need_re_compute = true; + goto out; + } } } - if (new_stream_on_link_num == 0) - return false; + if (new_stream_on_link_num == 0) { + DRM_DEBUG_DRIVER("%s:%d MST_DSC no mode change request for streams in new dc_state\n", + __func__, __LINE__); + is_dsc_need_re_compute = false; + goto out; + } + + DRM_DEBUG_DRIVER("%s: MST_DSC check on %d streams in current dc_state\n", + __func__, dc->current_state->stream_count); /* check current_state if there stream on link but it is not in * new request state @@ -1544,11 +1600,18 @@ static bool is_dsc_need_re_compute( if (j == new_stream_on_link_num) { /* not in new state */ + DRM_DEBUG_DRIVER("%s:%d MST_DSC dsc recompute required." + "stream 0x%p in current dc_state but not in new dc_state\n", + __func__, __LINE__, stream); is_dsc_need_re_compute = true; break; } } +out: + DRM_DEBUG_DRIVER("%s: MST_DSC dsc recompute %s\n", + __func__, is_dsc_need_re_compute ? "required" : "not required"); + return is_dsc_need_re_compute; } @@ -1577,6 +1640,9 @@ int compute_mst_dsc_configs_for_state(struct drm_atomic_state *state, aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; + DRM_DEBUG_DRIVER("%s: MST_DSC compute mst dsc configs for stream 0x%p, aconnector 0x%p\n", + __func__, stream, aconnector); + if (!aconnector || !aconnector->dc_sink || !aconnector->mst_output_port) continue; @@ -1609,8 +1675,11 @@ int compute_mst_dsc_configs_for_state(struct drm_atomic_state *state, stream = dc_state->streams[i]; if (stream->timing.flags.DSC == 1) - if (dc_stream_add_dsc_to_resource(stream->ctx->dc, dc_state, stream) != DC_OK) + if (dc_stream_add_dsc_to_resource(stream->ctx->dc, dc_state, stream) != DC_OK) { + DRM_DEBUG_DRIVER("%s:%d MST_DSC Failed to request dsc hw resource for stream 0x%p\n", + __func__, __LINE__, stream); return -EINVAL; + } } return ret; @@ -1639,6 +1708,9 @@ static int pre_compute_mst_dsc_configs_for_state(struct drm_atomic_state *state, aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context; + DRM_DEBUG_DRIVER("MST_DSC pre compute mst dsc configs for #%d stream 0x%p, aconnector 0x%p\n", + i, stream, aconnector); + if (!aconnector || !aconnector->dc_sink || !aconnector->mst_output_port) continue; @@ -1728,12 +1800,12 @@ int pre_validate_dsc(struct drm_atomic_state *state, int ret = 0; if (!is_dsc_precompute_needed(state)) { - DRM_INFO_ONCE("DSC precompute is not needed.\n"); + DRM_INFO_ONCE("%s:%d MST_DSC dsc precompute is not needed\n", __func__, __LINE__); return 0; } ret = dm_atomic_get_state(state, dm_state_ptr); if (ret != 0) { - DRM_INFO_ONCE("dm_atomic_get_state() failed\n"); + DRM_INFO_ONCE("%s:%d MST_DSC dm_atomic_get_state() failed\n", __func__, __LINE__); return ret; } dm_state = *dm_state_ptr; @@ -1787,7 +1859,8 @@ int pre_validate_dsc(struct drm_atomic_state *state, ret = pre_compute_mst_dsc_configs_for_state(state, local_dc_state, vars); if (ret != 0) { - DRM_INFO_ONCE("pre_compute_mst_dsc_configs_for_state() failed\n"); + DRM_INFO_ONCE("%s:%d MST_DSC dsc pre_compute_mst_dsc_configs_for_state() failed\n", + __func__, __LINE__); ret = -EINVAL; goto clean_exit; } @@ -1801,12 +1874,15 @@ int pre_validate_dsc(struct drm_atomic_state *state, if (local_dc_state->streams[i] && dc_is_timing_changed(stream, local_dc_state->streams[i])) { - DRM_INFO_ONCE("crtc[%d] needs mode_changed\n", i); + DRM_INFO_ONCE("%s:%d MST_DSC crtc[%d] needs mode_change\n", __func__, __LINE__, i); } else { int ind = find_crtc_index_in_state_by_stream(state, stream); - if (ind >= 0) + if (ind >= 0) { + DRM_INFO_ONCE("%s:%d MST_DSC no mode changed for stream 0x%p\n", + __func__, __LINE__, stream); state->crtcs[ind].new_state->mode_changed = 0; + } } } clean_exit: @@ -1935,7 +2011,7 @@ enum dc_status dm_dp_mst_is_port_support_mode( end_to_end_bw_in_kbps = min(root_link_bw_in_kbps, virtual_channel_bw_in_kbps); if (stream_kbps <= end_to_end_bw_in_kbps) { - DRM_DEBUG_DRIVER("No DSC needed. End-to-end bw sufficient."); + DRM_DEBUG_DRIVER("MST_DSC no dsc required. End-to-end bw sufficient\n"); return DC_OK; } @@ -1948,7 +2024,8 @@ enum dc_status dm_dp_mst_is_port_support_mode( /*capable of dsc passthough. dsc bitstream along the entire path*/ if (aconnector->mst_output_port->passthrough_aux) { if (bw_range.min_kbps > end_to_end_bw_in_kbps) { - DRM_DEBUG_DRIVER("DSC passthrough. Max dsc compression can't fit into end-to-end bw\n"); + DRM_DEBUG_DRIVER("MST_DSC dsc passthrough and decode at endpoint" + "Max dsc compression bw can't fit into end-to-end bw\n"); return DC_FAIL_BANDWIDTH_VALIDATE; } } else { @@ -1959,7 +2036,8 @@ enum dc_status dm_dp_mst_is_port_support_mode( /*Get last DP link BW capability*/ if (dp_get_link_current_set_bw(&aconnector->mst_output_port->aux, &end_link_bw)) { if (stream_kbps > end_link_bw) { - DRM_DEBUG_DRIVER("DSC decode at last link. Mode required bw can't fit into available bw\n"); + DRM_DEBUG_DRIVER("MST_DSC dsc decode at last link." + "Mode required bw can't fit into last link\n"); return DC_FAIL_BANDWIDTH_VALIDATE; } } @@ -1972,7 +2050,8 @@ enum dc_status dm_dp_mst_is_port_support_mode( virtual_channel_bw_in_kbps = kbps_from_pbn(immediate_upstream_port->full_pbn); virtual_channel_bw_in_kbps = min(root_link_bw_in_kbps, virtual_channel_bw_in_kbps); if (bw_range.min_kbps > virtual_channel_bw_in_kbps) { - DRM_DEBUG_DRIVER("DSC decode at last link. Max dsc compression can't fit into MST available bw\n"); + DRM_DEBUG_DRIVER("MST_DSC dsc decode at last link." + "Max dsc compression can't fit into MST available bw\n"); return DC_FAIL_BANDWIDTH_VALIDATE; } } @@ -1989,9 +2068,9 @@ enum dc_status dm_dp_mst_is_port_support_mode( dc_link_get_highest_encoding_format(stream->link), &stream->timing.dsc_cfg)) { stream->timing.flags.DSC = 1; - DRM_DEBUG_DRIVER("Require dsc and dsc config found\n"); + DRM_DEBUG_DRIVER("MST_DSC require dsc and dsc config found\n"); } else { - DRM_DEBUG_DRIVER("Require dsc but can't find appropriate dsc config\n"); + DRM_DEBUG_DRIVER("MST_DSC require dsc but can't find appropriate dsc config\n"); return DC_FAIL_BANDWIDTH_VALIDATE; } @@ -2013,11 +2092,11 @@ enum dc_status dm_dp_mst_is_port_support_mode( if (branch_max_throughput_mps != 0 && ((stream->timing.pix_clk_100hz / 10) > branch_max_throughput_mps * 1000)) { - DRM_DEBUG_DRIVER("DSC is required but max throughput mps fails"); + DRM_DEBUG_DRIVER("MST_DSC require dsc but max throughput mps fails\n"); return DC_FAIL_BANDWIDTH_VALIDATE; } } else { - DRM_DEBUG_DRIVER("DSC is required but can't find common dsc config."); + DRM_DEBUG_DRIVER("MST_DSC require dsc but can't find common dsc config\n"); return DC_FAIL_BANDWIDTH_VALIDATE; } #else From 4e0eb57de9007ca9fcb92ae08ec97686b0d39593 Mon Sep 17 00:00:00 2001 From: Zaeem Mohamed Date: Thu, 22 Aug 2024 17:36:10 -0400 Subject: [PATCH 1409/1868] drm/amdgpu/display: SPDX copyright for spl_os_types.h Use appropriate SPDX copyright for spl_os_types.h Reviewed-by: Hamza Mahfooz Signed-off-by: Zaeem Mohamed Tested-by: Daniel Wheeler --- .../gpu/drm/amd/display/dc/spl/spl_os_types.h | 29 +++---------------- 1 file changed, 4 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/spl/spl_os_types.h b/drivers/gpu/drm/amd/display/dc/spl/spl_os_types.h index 7ebea91c84f6a..058306bb41aa2 100644 --- a/drivers/gpu/drm/amd/display/dc/spl/spl_os_types.h +++ b/drivers/gpu/drm/amd/display/dc/spl/spl_os_types.h @@ -1,28 +1,7 @@ -/* - * Copyright 2012-16 Advanced Micro Devices, Inc. - * Copyright 2019 Raptor Engineering, LLC - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ +/* SPDX-License-Identifier: MIT */ + +/* Copyright 2024 Advanced Micro Devices, Inc. */ +/* Copyright 2019 Raptor Engineering, LLC */ #ifndef _SPL_OS_TYPES_H_ #define _SPL_OS_TYPES_H_ From 59249d761733af528057668957bf88d5019469b2 Mon Sep 17 00:00:00 2001 From: Zaeem Mohamed Date: Fri, 23 Aug 2024 00:30:15 -0400 Subject: [PATCH 1410/1868] drm/amdgpu/display: remove unnecessary TODO spl_os_types.h Remove unnecessary TODO from spl_os_types.h Reviewed-by: Hamza Mahfooz Signed-off-by: Zaeem Mohamed Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/spl/spl_os_types.h | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/spl/spl_os_types.h b/drivers/gpu/drm/amd/display/dc/spl/spl_os_types.h index 058306bb41aa2..709706ed4f2c9 100644 --- a/drivers/gpu/drm/amd/display/dc/spl/spl_os_types.h +++ b/drivers/gpu/drm/amd/display/dc/spl/spl_os_types.h @@ -18,7 +18,6 @@ * general debug capabilities * */ -// TODO: need backport #define SPL_BREAK_TO_DEBUGGER() ASSERT(0) static inline uint64_t spl_div_u64_rem(uint64_t dividend, uint32_t divisor, uint32_t *remainder) From aee958c4fbafa906b231ef015f42f7e139f2b03b Mon Sep 17 00:00:00 2001 From: Asher Song Date: Fri, 30 Aug 2024 08:58:00 +0800 Subject: [PATCH 1411/1868] drm/amdgpu: fix a call trace when unload amdgpu driver MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Before release ttm_resource_manager, ttm_bo_delay_delete in workqueue is required to execute. Acked-by: Christian König Signed-off-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index 5c938ff0bf488..cbac21df5c47a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -2461,6 +2461,7 @@ void amdgpu_ttm_fini(struct amdgpu_device *adev) drm_dev_exit(idx); } + drain_workqueue(adev->mman.bdev.wq); amdgpu_direct_gma_fini(adev); amdgpu_vram_mgr_fini(adev); amdgpu_gtt_mgr_fini(adev); From 63009805b6c5ce27d86f4f5cff8d9bbc779b4146 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 22 Aug 2024 21:54:24 -0400 Subject: [PATCH 1412/1868] drm/amdgpu/swsmu: always force a state reprogram on init Always reprogram the hardware state on init. This ensures the PMFW state is explicitly programmed and we are not relying on the default PMFW state. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3131 Reviewed-by: Kenneth Feng Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 52083277b70da..2b02da35cb428 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -2224,8 +2224,9 @@ static int smu_bump_power_profile_mode(struct smu_context *smu, } static int smu_adjust_power_state_dynamic(struct smu_context *smu, - enum amd_dpm_forced_level level, - bool skip_display_settings) + enum amd_dpm_forced_level level, + bool skip_display_settings, + bool force_update) { int ret = 0; int index = 0; @@ -2254,7 +2255,7 @@ static int smu_adjust_power_state_dynamic(struct smu_context *smu, } } - if (smu_dpm_ctx->dpm_level != level) { + if (force_update || smu_dpm_ctx->dpm_level != level) { ret = smu_asic_set_performance_level(smu, level); if (ret) { dev_err(smu->adev->dev, "Failed to set performance level!"); @@ -2270,7 +2271,7 @@ static int smu_adjust_power_state_dynamic(struct smu_context *smu, index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; workload[0] = smu->workload_setting[index]; - if (smu->power_profile_mode != workload[0]) + if (force_update || smu->power_profile_mode != workload[0]) smu_bump_power_profile_mode(smu, workload, 0); } @@ -2291,11 +2292,13 @@ static int smu_handle_task(struct smu_context *smu, ret = smu_pre_display_config_changed(smu); if (ret) return ret; - ret = smu_adjust_power_state_dynamic(smu, level, false); + ret = smu_adjust_power_state_dynamic(smu, level, false, false); break; case AMD_PP_TASK_COMPLETE_INIT: + ret = smu_adjust_power_state_dynamic(smu, level, true, true); + break; case AMD_PP_TASK_READJUST_POWER_STATE: - ret = smu_adjust_power_state_dynamic(smu, level, true); + ret = smu_adjust_power_state_dynamic(smu, level, true, false); break; default: break; From 31bd2496cc1541f33eead9992ad24d544e854c47 Mon Sep 17 00:00:00 2001 From: Fangzhi Zuo Date: Tue, 27 Aug 2024 16:08:13 -0400 Subject: [PATCH 1413/1868] drm/amdgpu/display: Fix a mistake in revert commit [why] It is to fix in try_disable_dsc() due to misrevert patch of "drm/amd/display: Fix MST BW calculation Regression" [How] Fix restoring minimum compression bw by 'max_kbps', instead of native bw 'stream_kbps' Signed-off-by: Fangzhi Zuo Reviewed-by: Aurabindo Pillai --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index dad93a72696ef..e5e5a196aafc4 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -1290,7 +1290,7 @@ static int try_disable_dsc(struct drm_atomic_state *state, vars[next_index].bpp_x16 = 0; } else { DRM_DEBUG_DRIVER("MST_DSC index #%d, restore minimum compression\n", next_index); - vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.stream_kbps, fec_overhead_multiplier_x1000); + vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.max_kbps, fec_overhead_multiplier_x1000); ret = drm_dp_atomic_find_time_slots(state, params[next_index].port->mgr, params[next_index].port, From c4ea1cb6afce343906498fea5ae7b8df57977ed2 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 20 Aug 2024 15:19:04 -0400 Subject: [PATCH 1414/1868] drm/amdgpu: add experimental resets debug flag Add this flag to enable experimental resets for testing before they are fully validated. Reviewed-and-tested-by: Jiadong Zhu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 6 ++++++ 2 files changed, 7 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 911d24bc5cdf3..e017add16864b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1188,6 +1188,7 @@ struct amdgpu_device { bool debug_disable_soft_recovery; bool debug_use_vram_fw_buf; bool debug_enable_ras_aca; + bool debug_exp_resets; bool enforce_isolation[MAX_XCP]; /* Added this mutex for cleaner shader isolation between GFX and compute processes */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index cd95055f5b7c0..90c74155a26aa 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -132,6 +132,7 @@ enum AMDGPU_DEBUG_MASK { AMDGPU_DEBUG_DISABLE_GPU_SOFT_RECOVERY = BIT(2), AMDGPU_DEBUG_USE_VRAM_FW_BUF = BIT(3), AMDGPU_DEBUG_ENABLE_RAS_ACA = BIT(4), + AMDGPU_DEBUG_ENABLE_EXP_RESETS = BIT(5), }; unsigned int amdgpu_vram_limit = UINT_MAX; @@ -2224,6 +2225,11 @@ static void amdgpu_init_debug_options(struct amdgpu_device *adev) pr_info("debug: enable RAS ACA\n"); adev->debug_enable_ras_aca = true; } + + if (amdgpu_debug_mask & AMDGPU_DEBUG_ENABLE_EXP_RESETS) { + pr_info("debug: enable experimental reset features\n"); + adev->debug_exp_resets = true; + } } static unsigned long amdgpu_fix_asic_type(struct pci_dev *pdev, unsigned long flags) From 82cf15cbae5b989ccb3badcfc1a15bb2dcbcc7a5 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 20 Aug 2024 16:21:15 -0400 Subject: [PATCH 1415/1868] drm/amdgpu/gfx9: put queue resets behind a debug option Pending extended validation. Reviewed-and-tested-by: Jiadong Zhu Acked-by: Felix Kuehling Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 4 ++++ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++++ drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 6 ++++++ 3 files changed, 14 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c index 3679afa017baf..0173c606c0491 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c @@ -1151,6 +1151,10 @@ uint64_t kgd_gfx_v9_hqd_get_pq_addr(struct amdgpu_device *adev, uint32_t low, high; uint64_t queue_addr = 0; + if (!adev->debug_exp_resets && + !adev->gfx.num_gfx_rings) + return 0; + kgd_gfx_v9_acquire_queue(adev, pipe_id, queue_id, inst); amdgpu_gfx_rlc_enter_safe_mode(adev, inst); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 7b78e448adf9b..9d2333b2a610f 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -7353,6 +7353,10 @@ static int gfx_v9_0_reset_kcq(struct amdgpu_ring *ring, unsigned long flags; int i, r; + if (!adev->debug_exp_resets && + !adev->gfx.num_gfx_rings) + return -EINVAL; + if (amdgpu_sriov_vf(adev)) return -EINVAL; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index 2067f26d3a9d8..f8649546b9c4c 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -3052,6 +3052,9 @@ static void gfx_v9_4_3_ring_soft_recovery(struct amdgpu_ring *ring, struct amdgpu_device *adev = ring->adev; uint32_t value = 0; + if (!adev->debug_exp_resets) + return; + value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); @@ -3475,6 +3478,9 @@ static int gfx_v9_4_3_reset_kcq(struct amdgpu_ring *ring, unsigned long flags; int r, i; + if (!adev->debug_exp_resets) + return -EINVAL; + if (amdgpu_sriov_vf(adev)) return -EINVAL; From 32ddc92c8bae1991751680d27f8069bc08e97a6e Mon Sep 17 00:00:00 2001 From: Trigger Huang Date: Mon, 19 Aug 2024 15:53:22 +0800 Subject: [PATCH 1416/1868] drm/amdgpu: skip printing vram_lost if needed The vm lost status can only be obtained after a GPU reset occurs, but sometimes a dev core dump can be happened before GPU reset. So a new argument is added to tell the dev core dump implementation whether to skip printing the vram_lost status in the dump. And this patch is also trying to decouple the core dump function from the GPU reset function, by replacing the argument amdgpu_reset_context with amdgpu_job to specify the context for core dump. V2: Inform user if VRAM lost check is skipped so users don't assume VRAM wasn't lost (Alex) Signed-off-by: Trigger Huang Suggested-by: Alex Deucher Reviewed-by: Alex Deucher --- .../gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c | 20 ++++++++++--------- .../gpu/drm/amd/amdgpu/amdgpu_dev_coredump.h | 7 +++---- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +- 3 files changed, 15 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c index cf2b4dd4d865a..5ac59b62020cf 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c @@ -28,8 +28,8 @@ #include "atom.h" #ifndef CONFIG_DEV_COREDUMP -void amdgpu_coredump(struct amdgpu_device *adev, bool vram_lost, - struct amdgpu_reset_context *reset_context) +void amdgpu_coredump(struct amdgpu_device *adev, bool skip_vram_check, + bool vram_lost, struct amdgpu_job *job) { } #else @@ -315,7 +315,9 @@ amdgpu_devcoredump_read(char *buffer, loff_t offset, size_t count, } } - if (coredump->reset_vram_lost) + if (coredump->skip_vram_check) + drm_printf(&p, "VRAM lost check is skipped!\n"); + else if (coredump->reset_vram_lost) drm_printf(&p, "VRAM is lost due to GPU reset!\n"); return count - iter.remain; @@ -326,12 +328,11 @@ static void amdgpu_devcoredump_free(void *data) kfree(data); } -void amdgpu_coredump(struct amdgpu_device *adev, bool vram_lost, - struct amdgpu_reset_context *reset_context) +void amdgpu_coredump(struct amdgpu_device *adev, bool skip_vram_check, + bool vram_lost, struct amdgpu_job *job) { - struct amdgpu_coredump_info *coredump; struct drm_device *dev = adev_to_drm(adev); - struct amdgpu_job *job = reset_context->job; + struct amdgpu_coredump_info *coredump; struct drm_sched_job *s_job; coredump = kzalloc(sizeof(*coredump), GFP_NOWAIT); @@ -341,11 +342,12 @@ void amdgpu_coredump(struct amdgpu_device *adev, bool vram_lost, return; } + coredump->skip_vram_check = skip_vram_check; coredump->reset_vram_lost = vram_lost; - if (reset_context->job && reset_context->job->vm) { + if (job && job->vm) { + struct amdgpu_vm *vm = job->vm; struct amdgpu_task_info *ti; - struct amdgpu_vm *vm = reset_context->job->vm; ti = amdgpu_vm_get_task_info_vm(vm); if (ti) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.h index 52459512cb2b1..ef9772c6bcc9e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.h @@ -26,7 +26,6 @@ #define __AMDGPU_DEV_COREDUMP_H__ #include "amdgpu.h" -#include "amdgpu_reset.h" #ifdef CONFIG_DEV_COREDUMP @@ -36,12 +35,12 @@ struct amdgpu_coredump_info { struct amdgpu_device *adev; struct amdgpu_task_info reset_task_info; struct timespec64 reset_time; + bool skip_vram_check; bool reset_vram_lost; struct amdgpu_ring *ring; }; #endif -void amdgpu_coredump(struct amdgpu_device *adev, bool vram_lost, - struct amdgpu_reset_context *reset_context); - +void amdgpu_coredump(struct amdgpu_device *adev, bool skip_vram_check, + bool vram_lost, struct amdgpu_job *job); #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 65dff728b7a08..ae0fad28ab4c9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -5508,7 +5508,7 @@ int amdgpu_do_asic_reset(struct list_head *device_list_handle, vram_lost = amdgpu_device_check_vram_lost(tmp_adev); if (!test_bit(AMDGPU_SKIP_COREDUMP, &reset_context->flags)) - amdgpu_coredump(tmp_adev, vram_lost, reset_context); + amdgpu_coredump(tmp_adev, false, vram_lost, reset_context->job); if (vram_lost) { DRM_INFO("VRAM is lost due to GPU reset!\n"); From 2ab3304135cda1f71b0d7cec2e41b9ec413a0ae9 Mon Sep 17 00:00:00 2001 From: Trigger Huang Date: Mon, 19 Aug 2024 16:04:52 +0800 Subject: [PATCH 1417/1868] drm/amdgpu: Do core dump immediately when job tmo Do the coredump immediately after a job timeout to get a closer representation of GPU's error status. V2: This will skip printing vram_lost as the GPU reset is not happened yet (Alex) V3: Unconditionally call the core dump as we care about all the reset functions(soft-recovery and queue reset and full adapter reset, Alex) V4: Do the dump after adev->job_hang = true (Sunil) Signed-off-by: Trigger Huang Acked-by: Sunil Khatri Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 68 ++++++++++++++++++++++++- 1 file changed, 67 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c index c6a1783fc9ef4..3000a49b3e5ca 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c @@ -30,6 +30,61 @@ #include "amdgpu.h" #include "amdgpu_trace.h" #include "amdgpu_reset.h" +#include "amdgpu_dev_coredump.h" +#include "amdgpu_xgmi.h" + +static void amdgpu_job_do_core_dump(struct amdgpu_device *adev, + struct amdgpu_job *job) +{ + int i; + + dev_info(adev->dev, "Dumping IP State\n"); + for (i = 0; i < adev->num_ip_blocks; i++) { + if (adev->ip_blocks[i].version->funcs->dump_ip_state) + adev->ip_blocks[i].version->funcs + ->dump_ip_state((void *)adev); + dev_info(adev->dev, "Dumping IP State Completed\n"); + } + + amdgpu_coredump(adev, true, false, job); +} + +static void amdgpu_job_core_dump(struct amdgpu_device *adev, + struct amdgpu_job *job) +{ + struct list_head device_list, *device_list_handle = NULL; + struct amdgpu_device *tmp_adev = NULL; + struct amdgpu_hive_info *hive = NULL; + + if (!amdgpu_sriov_vf(adev)) + hive = amdgpu_get_xgmi_hive(adev); + if (hive) + mutex_lock(&hive->hive_lock); + /* + * Reuse the logic in amdgpu_device_gpu_recover() to build list of + * devices for code dump + */ + INIT_LIST_HEAD(&device_list); + if (!amdgpu_sriov_vf(adev) && (adev->gmc.xgmi.num_physical_nodes > 1) && hive) { + list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) + list_add_tail(&tmp_adev->reset_list, &device_list); + if (!list_is_first(&adev->reset_list, &device_list)) + list_rotate_to_front(&adev->reset_list, &device_list); + device_list_handle = &device_list; + } else { + list_add_tail(&adev->reset_list, &device_list); + device_list_handle = &device_list; + } + + /* Do the coredump for each device */ + list_for_each_entry(tmp_adev, device_list_handle, reset_list) + amdgpu_job_do_core_dump(tmp_adev, job); + + if (hive) { + mutex_unlock(&hive->hive_lock); + amdgpu_put_xgmi_hive(hive); + } +} static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job) { @@ -48,9 +103,14 @@ static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job) return DRM_GPU_SCHED_STAT_ENODEV; } - adev->job_hang = true; + /* + * Do the coredump immediately after a job timeout to get a very + * close dump/snapshot/representation of GPU's current error status + */ + amdgpu_job_core_dump(adev, job); + if (amdgpu_gpu_recovery && amdgpu_ring_soft_recovery(ring, job->vmid, s_job->s_fence->parent)) { dev_err(adev->dev, "ring %s timeout, but soft recovered\n", @@ -101,6 +161,12 @@ static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job) reset_context.src = AMDGPU_RESET_SRC_JOB; clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); + /* + * To avoid an unnecessary extra coredump, as we have already + * got the very close representation of GPU's error status + */ + set_bit(AMDGPU_SKIP_COREDUMP, &reset_context.flags); + r = amdgpu_device_gpu_recover(ring->adev, job, &reset_context); if (r) dev_err(adev->dev, "GPU Recovery Failed: %d\n", r); From c957006f3faad7013a83df8b7bd369827cd97648 Mon Sep 17 00:00:00 2001 From: Victor Zhao Date: Mon, 26 Aug 2024 00:14:26 +0800 Subject: [PATCH 1418/1868] drm/amd/amdgpu: move drain_workqueue before shutdown is set [background] when unloading amdgpu driver right after running a workload, drain_workqueue is causing "Fence fallback timer expired on ring sdma0.0". Under sriov, this issue will cause sriov full access timeout and a reset happening. move drain_workqueue before shutdown is set to allow ih process and before enter full access under sriov to avoid full access time cost. Signed-off-by: Victor Zhao Reviewed-by: Feifei Xu --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index ae0fad28ab4c9..500b3ff9f344a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -4546,6 +4546,9 @@ void amdgpu_device_fini_hw(struct amdgpu_device *adev) { dev_info(adev->dev, "amdgpu: finishing device.\n"); flush_delayed_work(&adev->delayed_init_work); + + if (adev->mman.initialized) + drain_workqueue(adev->mman.bdev.wq); adev->shutdown = true; /* make sure IB test finished before entering exclusive mode @@ -4566,9 +4569,6 @@ void amdgpu_device_fini_hw(struct amdgpu_device *adev) } amdgpu_fence_driver_hw_fini(adev); - if (adev->mman.initialized) - drain_workqueue(adev->mman.bdev.wq); - if (adev->pm.sysfs_initialized) amdgpu_pm_sysfs_fini(adev); if (adev->ucode_sysfs_en) From 025debd3e950846410961ce4ebbd51cac79c8fcb Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Wed, 28 Aug 2024 13:36:23 +0530 Subject: [PATCH 1419/1868] drm/amdgpu: Move the dumping log out of for loop log message "Dumping IP State Completed" needs to be logged only once when state dumping is complete. Hence moving it out of the for loop. Signed-off-by: Sunil Khatri Acked-by: Trigger Huang --- drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c index 3000a49b3e5ca..381c886298bf8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c @@ -39,12 +39,11 @@ static void amdgpu_job_do_core_dump(struct amdgpu_device *adev, int i; dev_info(adev->dev, "Dumping IP State\n"); - for (i = 0; i < adev->num_ip_blocks; i++) { + for (i = 0; i < adev->num_ip_blocks; i++) if (adev->ip_blocks[i].version->funcs->dump_ip_state) adev->ip_blocks[i].version->funcs ->dump_ip_state((void *)adev); - dev_info(adev->dev, "Dumping IP State Completed\n"); - } + dev_info(adev->dev, "Dumping IP State Completed\n"); amdgpu_coredump(adev, true, false, job); } From df5c2f294714d505e08f55210d21973d90d34470 Mon Sep 17 00:00:00 2001 From: Leo Li Date: Tue, 27 Aug 2024 11:29:53 -0400 Subject: [PATCH 1420/1868] drm/amd/display: Determine IPS mode by ASIC and PMFW versions [Why] DCN IPS interoperates with other system idle power features, such as Zstates. On DCN35, there is a known issue where system Z8 + DCN IPS2 causes a hard hang. We observe this on systems where the SBIOS allows Z8. Though there is a SBIOS fix, there's no guarantee that users will get it any time soon, or even install it. A workaround is needed to prevent this from rearing its head in the wild. [How] For DCN35, check the pmfw version to determine whether the SBIOS has the fix. If not, set IPS1+RCG as the deepest possible state in all cases except for s0ix and display off (DPMS). Otherwise, enable all IPS Signed-off-by: Leo Li Reviewed-by: Harry Wentland --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 26 ++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 1e5c4397be86d..cbed8b938042f 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1766,6 +1766,30 @@ static struct dml2_soc_bb *dm_dmub_get_vbios_bounding_box(struct amdgpu_device * return bb; } +static enum dmub_ips_disable_type dm_get_default_ips_mode( + struct amdgpu_device *adev) +{ + /* + * On DCN35 systems with Z8 enabled, it's possible for IPS2 + Z8 to + * cause a hard hang. A fix exists for newer PMFW. + * + * As a workaround, for non-fixed PMFW, force IPS1+RCG as the deepest + * IPS state in all cases, except for s0ix and all displays off (DPMS), + * where IPS2 is allowed. + * + * When checking pmfw version, use the major and minor only. + */ + if (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(3, 5, 0) && + (adev->pm.fw_version & 0x00FFFF00) < 0x005D6300) + return DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF; + + if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 5, 0)) + return DMUB_IPS_ENABLE; + + /* ASICs older than DCN35 do not have IPSs */ + return DMUB_IPS_DISABLE_ALL; +} + static int amdgpu_dm_init(struct amdgpu_device *adev) { struct dc_init_data init_data; @@ -1884,7 +1908,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) else if (amdgpu_dc_debug_mask & DC_FORCE_IPS_ENABLE) init_data.flags.disable_ips = DMUB_IPS_ENABLE; else - init_data.flags.disable_ips = DMUB_IPS_ENABLE; + init_data.flags.disable_ips = dm_get_default_ips_mode(adev); init_data.flags.disable_ips_in_vpb = 0; From 354f4561fcdf9dbc586191d24a1376f274d9b54e Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 14 Aug 2024 09:15:24 -0400 Subject: [PATCH 1421/1868] drm/amdgpu/gfx11: return early in preempt_ib() When MES is enabled KIQ is not available. Return an error when someone uses the debugfs preempt test interface in that case. Acked-by: Srinivasan Shanmugam Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index ee86047224672..aa7fdece8ad42 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -5923,6 +5923,9 @@ static int gfx_v11_0_ring_preempt_ib(struct amdgpu_ring *ring) struct amdgpu_ring *kiq_ring = &kiq->ring; unsigned long flags; + if (adev->enable_mes) + return -EINVAL; + if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) return -EINVAL; From 6d411d1167834e507b49d2f9e0c078aee44c87bc Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 15 Aug 2024 12:58:14 -0400 Subject: [PATCH 1422/1868] drm/amdgpu/gfx12: return early in preempt_ib() When MES is enabled KIQ is not available. Return an error when someone uses the debugfs preempt test interface in that case. Acked-by: Srinivasan Shanmugam Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c index 54059cbcfc089..6f700800f346b 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c @@ -4501,6 +4501,9 @@ static int gfx_v12_0_ring_preempt_ib(struct amdgpu_ring *ring) struct amdgpu_ring *kiq_ring = &kiq->ring; unsigned long flags; + if (adev->enable_mes) + return -EINVAL; + if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) return -EINVAL; From 77610cda1f3dc41080e6f2aa486f6682f063ac4c Mon Sep 17 00:00:00 2001 From: Yifan Zhang Date: Tue, 27 Aug 2024 15:14:31 +0800 Subject: [PATCH 1423/1868] drm/amdkfd: Don't drain ih1 for APU ih1 is not initialized for APUs. Don't drain it or NULL pointer error will be triggered. Fixes: 490fc21fe97c ("drm/amdkfd: Change kfd/svm page fault drain handling") Signed-off-by: Yifan Zhang Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c index cbc89749207b6..4b01fd3f63d90 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c @@ -2462,11 +2462,14 @@ svm_range_unmap_from_cpu(struct mm_struct *mm, struct svm_range *prange, adev = pdd->dev->adev; /* Check and drain ih1 ring if cam not available */ - ih = &adev->irq.ih1; - checkpoint_wptr = amdgpu_ih_get_wptr(adev, ih); - if (ih->rptr != checkpoint_wptr) { - svms->checkpoint_ts[i] = amdgpu_ih_decode_iv_ts(adev, ih, checkpoint_wptr, -1); - continue; + if (adev->irq.ih1.ring_size) { + ih = &adev->irq.ih1; + checkpoint_wptr = amdgpu_ih_get_wptr(adev, ih); + if (ih->rptr != checkpoint_wptr) { + svms->checkpoint_ts[i] = + amdgpu_ih_decode_iv_ts(adev, ih, checkpoint_wptr, -1); + continue; + } } /* check if dev->irq.ih_soft is not empty */ From 686a06d7fc2726d31e99ca7bed35f894d9a8c4eb Mon Sep 17 00:00:00 2001 From: Jack Xiao Date: Thu, 22 Aug 2024 18:18:51 +0800 Subject: [PATCH 1424/1868] drm/amdgpu/mes: add mes mapping legacy queue switch For mes11 old firmware has issue to map legacy queue, add a flag to switch mes to map legacy queue. Reported-by: Andrew Worsley Link: https://lists.freedesktop.org/archives/amd-gfx/2024-August/112773.html Signed-off-by: Jack Xiao Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 4 +- drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 1 + drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 49 +++++++++++++++++-------- drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 9 +++-- 4 files changed, 43 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c index b4efeef848de7..b779d47a546a3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c @@ -660,7 +660,7 @@ int amdgpu_gfx_enable_kcq(struct amdgpu_device *adev, int xcc_id) uint64_t queue_mask = 0; int r, i, j; - if (adev->enable_mes) + if (adev->mes.enable_legacy_queue_map) return amdgpu_gfx_mes_enable_kcq(adev, xcc_id); if (!kiq->pmf || !kiq->pmf->kiq_map_queues || !kiq->pmf->kiq_set_resources) @@ -722,7 +722,7 @@ int amdgpu_gfx_enable_kgq(struct amdgpu_device *adev, int xcc_id) amdgpu_device_flush_hdp(adev, NULL); - if (adev->enable_mes) { + if (adev->mes.enable_legacy_queue_map) { for (i = 0; i < adev->gfx.num_gfx_rings; i++) { j = i + xcc_id * adev->gfx.num_gfx_rings; r = amdgpu_mes_map_legacy_queue(adev, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h index a5b1ea60cac8d..5475e84b23e66 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h @@ -75,6 +75,7 @@ struct amdgpu_mes { uint32_t sched_version; uint32_t kiq_version; + bool enable_legacy_queue_map; uint32_t total_max_queue; uint32_t max_doorbell_slices; diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c index 8edcd85a1261f..ebc3cdc602b8b 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c @@ -775,6 +775,28 @@ static void mes_v11_0_free_ucode_buffers(struct amdgpu_device *adev, (void **)&adev->mes.ucode_fw_ptr[pipe]); } +static void mes_v11_0_get_fw_version(struct amdgpu_device *adev) +{ + int pipe; + + /* get MES scheduler/KIQ versions */ + mutex_lock(&adev->srbm_mutex); + + for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { + soc21_grbm_select(adev, 3, pipe, 0, 0); + + if (pipe == AMDGPU_MES_SCHED_PIPE) + adev->mes.sched_version = + RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); + else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq) + adev->mes.kiq_version = + RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); + } + + soc21_grbm_select(adev, 0, 0, 0, 0); + mutex_unlock(&adev->srbm_mutex); +} + static void mes_v11_0_enable(struct amdgpu_device *adev, bool enable) { uint64_t ucode_addr; @@ -1144,18 +1166,6 @@ static int mes_v11_0_queue_init(struct amdgpu_device *adev, mes_v11_0_queue_init_register(ring); } - /* get MES scheduler/KIQ versions */ - mutex_lock(&adev->srbm_mutex); - soc21_grbm_select(adev, 3, pipe, 0, 0); - - if (pipe == AMDGPU_MES_SCHED_PIPE) - adev->mes.sched_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); - else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq) - adev->mes.kiq_version = RREG32_SOC15(GC, 0, regCP_MES_GP3_LO); - - soc21_grbm_select(adev, 0, 0, 0, 0); - mutex_unlock(&adev->srbm_mutex); - return 0; } @@ -1402,15 +1412,24 @@ static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev) mes_v11_0_enable(adev, true); + mes_v11_0_get_fw_version(adev); + mes_v11_0_kiq_setting(&adev->gfx.kiq[0].ring); r = mes_v11_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE); if (r) goto failure; - r = mes_v11_0_hw_init(adev); - if (r) - goto failure; + if ((adev->mes.sched_version & AMDGPU_MES_VERSION_MASK) >= 0x47) + adev->mes.enable_legacy_queue_map = true; + else + adev->mes.enable_legacy_queue_map = false; + + if (adev->mes.enable_legacy_queue_map) { + r = mes_v11_0_hw_init(adev); + if (r) + goto failure; + } return r; diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c index 47a73f6ae4dae..e499b2857a01e 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c @@ -1332,6 +1332,7 @@ static int mes_v12_0_sw_init(void *handle) adev->mes.funcs = &mes_v12_0_funcs; adev->mes.kiq_hw_init = &mes_v12_0_kiq_hw_init; adev->mes.kiq_hw_fini = &mes_v12_0_kiq_hw_fini; + adev->mes.enable_legacy_queue_map = true; adev->mes.event_log_size = AMDGPU_MES_LOG_BUFFER_SIZE; @@ -1488,9 +1489,11 @@ static int mes_v12_0_kiq_hw_init(struct amdgpu_device *adev) mes_v12_0_set_hw_resources_1(&adev->mes, AMDGPU_MES_KIQ_PIPE); } - r = mes_v12_0_hw_init(adev); - if (r) - goto failure; + if (adev->mes.enable_legacy_queue_map) { + r = mes_v12_0_hw_init(adev); + if (r) + goto failure; + } return r; From 8790eca34d85406f9fa384bf09ed73991a2c45d0 Mon Sep 17 00:00:00 2001 From: Prike Liang Date: Thu, 29 Aug 2024 11:47:12 +0800 Subject: [PATCH 1425/1868] drm/amdgpu/gfx9.4.3: Implement compute pipe reset Implement the compute pipe reset, and the driver will fallback to pipe reset when queue reset fails. The pipe reset only deactivates the queue which is scheduled in the pipe, and meanwhile the MEC pipe will be reset to the firmware _start pointer. So, it seems pipe reset will cost more cycles than the queue reset; therefore, the driver tries to recover by doing queue reset first. Reviewed-by: Lijo Lazar Signed-off-by: Prike Liang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 127 ++++++++++++++++++++---- 1 file changed, 108 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index f8649546b9c4c..408e5600bb617 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -3469,6 +3469,98 @@ static void gfx_v9_4_3_emit_wave_limit(struct amdgpu_ring *ring, bool enable) } } +static int gfx_v9_4_3_unmap_done(struct amdgpu_device *adev, uint32_t me, + uint32_t pipe, uint32_t queue, + uint32_t xcc_id) +{ + int i, r; + /* make sure dequeue is complete*/ + gfx_v9_4_3_xcc_set_safe_mode(adev, xcc_id); + mutex_lock(&adev->srbm_mutex); + soc15_grbm_select(adev, me, pipe, queue, 0, GET_INST(GC, xcc_id)); + for (i = 0; i < adev->usec_timeout; i++) { + if (!(RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_ACTIVE) & 1)) + break; + udelay(1); + } + if (i >= adev->usec_timeout) + r = -ETIMEDOUT; + else + r = 0; + soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); + mutex_unlock(&adev->srbm_mutex); + gfx_v9_4_3_xcc_unset_safe_mode(adev, xcc_id); + + return r; + +} + +static bool gfx_v9_4_3_pipe_reset_support(struct amdgpu_device *adev) +{ + /*TODO: Need check gfx9.4.4 mec fw whether supports pipe reset as well.*/ + if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) && + adev->gfx.mec_fw_version >= 0x0000009b) + return true; + else + dev_warn_once(adev->dev, "Please use the latest MEC version to see whether support pipe reset\n"); + + return false; +} + +static int gfx_v9_4_3_reset_hw_pipe(struct amdgpu_ring *ring) +{ + struct amdgpu_device *adev = ring->adev; + uint32_t reset_pipe, clean_pipe; + int r; + + if (!gfx_v9_4_3_pipe_reset_support(adev)) + return -EINVAL; + + gfx_v9_4_3_xcc_set_safe_mode(adev, ring->xcc_id); + mutex_lock(&adev->srbm_mutex); + + reset_pipe = RREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regCP_MEC_CNTL); + clean_pipe = reset_pipe; + + if (ring->me == 1) { + switch (ring->pipe) { + case 0: + reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, + MEC_ME1_PIPE0_RESET, 1); + break; + case 1: + reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, + MEC_ME1_PIPE1_RESET, 1); + break; + case 2: + reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, + MEC_ME1_PIPE2_RESET, 1); + break; + case 3: + reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, + MEC_ME1_PIPE3_RESET, 1); + break; + default: + break; + } + } else { + if (ring->pipe) + reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, + MEC_ME2_PIPE1_RESET, 1); + else + reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, + MEC_ME2_PIPE0_RESET, 1); + } + + WREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regCP_MEC_CNTL, reset_pipe); + WREG32_SOC15(GC, GET_INST(GC, ring->xcc_id), regCP_MEC_CNTL, clean_pipe); + mutex_unlock(&adev->srbm_mutex); + gfx_v9_4_3_xcc_unset_safe_mode(adev, ring->xcc_id); + + r = gfx_v9_4_3_unmap_done(adev, ring->me, ring->pipe, ring->queue, ring->xcc_id); + return r; +} + static int gfx_v9_4_3_reset_kcq(struct amdgpu_ring *ring, unsigned int vmid) { @@ -3476,7 +3568,7 @@ static int gfx_v9_4_3_reset_kcq(struct amdgpu_ring *ring, struct amdgpu_kiq *kiq = &adev->gfx.kiq[ring->xcc_id]; struct amdgpu_ring *kiq_ring = &kiq->ring; unsigned long flags; - int r, i; + int r; if (!adev->debug_exp_resets) return -EINVAL; @@ -3501,26 +3593,23 @@ static int gfx_v9_4_3_reset_kcq(struct amdgpu_ring *ring, spin_unlock_irqrestore(&kiq->ring_lock, flags); r = amdgpu_ring_test_ring(kiq_ring); + if (r) { + dev_err(adev->dev, "kiq ring test failed after ring: %s queue reset\n", + ring->name); + goto pipe_reset; + } + + r = gfx_v9_4_3_unmap_done(adev, ring->me, ring->pipe, ring->queue, ring->xcc_id); if (r) - return r; + dev_err(adev->dev, "fail to wait on hqd deactive and will try pipe reset\n"); - /* make sure dequeue is complete*/ - amdgpu_gfx_rlc_enter_safe_mode(adev, ring->xcc_id); - mutex_lock(&adev->srbm_mutex); - soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, ring->xcc_id)); - for (i = 0; i < adev->usec_timeout; i++) { - if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) - break; - udelay(1); - } - if (i >= adev->usec_timeout) - r = -ETIMEDOUT; - soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, ring->xcc_id)); - mutex_unlock(&adev->srbm_mutex); - amdgpu_gfx_rlc_exit_safe_mode(adev, ring->xcc_id); - if (r) { - dev_err(adev->dev, "fail to wait on hqd deactive\n"); - return r; +pipe_reset: + if(r) { + r = gfx_v9_4_3_reset_hw_pipe(ring); + dev_info(adev->dev, "ring: %s pipe reset :%s\n", ring->name, + r ? "failed" : "successfully"); + if (r) + return r; } r = amdgpu_bo_reserve(ring->mqd_obj, false); From 9a87a9c93e5a6bbca102360731b4e9272aea298d Mon Sep 17 00:00:00 2001 From: Nicholas Susanto Date: Tue, 20 Aug 2024 11:05:54 -0400 Subject: [PATCH 1426/1868] drm/amd/display: Fix DCN35 set min dispclk logic [Why] Setting min dispclk to 50Mhz outside clock lowering function causes unnecessary calls to SMU to lower dispclk and causes dentist hangs when there is no stream on the pipes. [How] Move the set minimum dispclk logic inside the lowering dispclk if statement. Fixes: 2dd29403b206 ("DCN35 set min dispclk to 50Mhz") Reviewed-by: Nicholas Kazlauskas Signed-off-by: Nicholas Susanto Signed-off-by: Hamza Mahfooz --- .../gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c index f50054089da74..97164b5585a84 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c @@ -305,9 +305,6 @@ void dcn35_update_clocks(struct clk_mgr *clk_mgr_base, if (new_clocks->dtbclk_en && !new_clocks->ref_dtbclk_khz) new_clocks->ref_dtbclk_khz = 600000; - if (dc->debug.min_disp_clk_khz > 0 && new_clocks->dispclk_khz < dc->debug.min_disp_clk_khz) - new_clocks->dispclk_khz = dc->debug.min_disp_clk_khz; - /* * if it is safe to lower, but we are already in the lower state, we don't have to do anything * also if safe to lower is false, we just go in the higher state @@ -385,6 +382,9 @@ void dcn35_update_clocks(struct clk_mgr *clk_mgr_base, if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) { dcn35_disable_otg_wa(clk_mgr_base, context, safe_to_lower, true); + if (dc->debug.min_disp_clk_khz > 0 && new_clocks->dispclk_khz < dc->debug.min_disp_clk_khz) + new_clocks->dispclk_khz = dc->debug.min_disp_clk_khz; + clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz; dcn35_smu_set_dispclk(clk_mgr, clk_mgr_base->clks.dispclk_khz); dcn35_disable_otg_wa(clk_mgr_base, context, safe_to_lower, false); From 1be0c683f34935862b130a0e798b0fb82e8e8559 Mon Sep 17 00:00:00 2001 From: Daniel Sa Date: Tue, 20 Aug 2024 14:19:26 -0400 Subject: [PATCH 1427/1868] drm/amd/display: only trigger BIOS related assert for older ASICs [Why] Some asserts are always hit on startup/Pnp when they should only be used to indicate when something has gone wrong. [How] Ignore result of getting function from bios cmd table for newer asics. Reviewed-by: Jun Lei Signed-off-by: Daniel Sa Signed-off-by: Hamza Mahfooz --- drivers/gpu/drm/amd/display/dc/bios/command_table2.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table2.c index 4254bdfefe38c..7d18f372ce7ab 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/command_table2.c +++ b/drivers/gpu/drm/amd/display/dc/bios/command_table2.c @@ -227,7 +227,7 @@ static void init_transmitter_control(struct bios_parser *bp) uint8_t frev; uint8_t crev = 0; - if (!BIOS_CMD_TABLE_REVISION(dig1transmittercontrol, frev, crev)) + if (!BIOS_CMD_TABLE_REVISION(dig1transmittercontrol, frev, crev) && (bp->base.ctx->dc->ctx->dce_version <= DCN_VERSION_2_0)) BREAK_TO_DEBUGGER(); switch (crev) { From 3ae7694bc779af8dc3d2e99f297c468f65738aee Mon Sep 17 00:00:00 2001 From: Leo Li Date: Tue, 20 Aug 2024 14:34:15 -0400 Subject: [PATCH 1428/1868] drm/amd/display: Lock DC and exit IPS when changing backlight Backlight updates require aux and/or register access. Therefore, driver needs to disallow IPS beforehand. So, acquire the dc lock before calling into dc to update backlight - we should be doing this regardless of IPS. Then, while the lock is held, disallow IPS before calling into dc, then allow IPS afterwards (if it was previously allowed). Cc: stable@vger.kernel.org # 6.10+ Reviewed-by: Aurabindo Pillai Reviewed-by: Roman Li Signed-off-by: Leo Li Signed-off-by: Hamza Mahfooz --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index cbed8b938042f..e8ab82814ec6b 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4592,7 +4592,7 @@ static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm, #else uint32_t brightness = user_brightness; #endif - bool rc; + bool rc, reallow_idle = false; amdgpu_dm_update_backlight_caps(dm, bl_idx); caps = dm->backlight_caps[bl_idx]; @@ -4606,6 +4606,12 @@ static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm, link = (struct dc_link *)dm->backlight_link[bl_idx]; /* Change brightness based on AUX property */ + mutex_lock(&dm->dc_lock); + if (dm->dc->caps.ips_support && dm->dc->ctx->dmub_srv->idle_allowed) { + dc_allow_idle_optimizations(dm->dc, false); + reallow_idle = true; + } + if (caps.aux_support) { rc = dc_link_set_backlight_level_nits(link, true, brightness, AUX_BL_DEFAULT_TRANSITION_TIME_MS); @@ -4617,6 +4623,11 @@ static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm, DRM_DEBUG("DM: Failed to update backlight on eDP[%d]\n", bl_idx); } + if (dm->dc->caps.ips_support && reallow_idle) + dc_allow_idle_optimizations(dm->dc, true); + + mutex_unlock(&dm->dc_lock); + if (rc) dm->actual_brightness[bl_idx] = user_brightness; #else From a36a8d4db2b548ecdcd09a11279086db433afd7c Mon Sep 17 00:00:00 2001 From: Samson Tam Date: Wed, 21 Aug 2024 11:03:11 -0400 Subject: [PATCH 1429/1868] drm/amd/display: re-enable Dynamic ODM policy [Why] Previous disable ODM policy due to underflow issue with sharpener. Issue is resolved after updating sharpening policy to apply to both windowed and fullscreen video [How] Remove sharpness check disabling Dynamic ODM policy Reviewed-by: Martin Leung Signed-off-by: Samson Tam Signed-off-by: Hamza Mahfooz --- .../drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c index 86a877f9a2ec1..b0d9aed0f2657 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c @@ -514,8 +514,7 @@ static void populate_dml21_stream_overrides_from_stream_state( break; } if (!stream->ctx->dc->debug.enable_single_display_2to1_odm_policy || - stream->debug.force_odm_combine_segments > 0 || - stream->ctx->dc->debug.force_sharpness > 1) + stream->debug.force_odm_combine_segments > 0) stream_desc->overrides.disable_dynamic_odm = true; stream_desc->overrides.disable_subvp = stream->ctx->dc->debug.force_disable_subvp || stream->hw_cursor_req; } From 7dd70a3978b3df5c110a286ab30e1a5d2449268e Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 24 May 2024 12:20:10 -0400 Subject: [PATCH 1430/1868] drm/amdgpu/gfx11: add ring reset callbacks Add ring reset callbacks for gfx and compute. Acked-by: Vitaly Prosyak Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index aa7fdece8ad42..986cd5a3d5606 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -6544,6 +6544,22 @@ static void gfx_v11_0_emit_mem_sync(struct amdgpu_ring *ring) amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ } +static int gfx_v11_0_reset_ring(struct amdgpu_ring *ring, unsigned int vmid) +{ + int r; + + r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid); + if (r) + return r; + + /* reset the ring */ + ring->wptr = 0; + *ring->wptr_cpu_addr = 0; + amdgpu_ring_clear_ring(ring); + + return amdgpu_ring_test_ring(ring); +} + static void gfx_v11_ip_print(void *handle, struct drm_printer *p) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; @@ -6745,6 +6761,7 @@ static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_gfx = { .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait, .soft_recovery = gfx_v11_0_ring_soft_recovery, .emit_mem_sync = gfx_v11_0_emit_mem_sync, + .reset = gfx_v11_0_reset_ring, }; static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_compute = { @@ -6782,6 +6799,7 @@ static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_compute = { .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait, .soft_recovery = gfx_v11_0_ring_soft_recovery, .emit_mem_sync = gfx_v11_0_emit_mem_sync, + .reset = gfx_v11_0_reset_ring, }; static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_kiq = { From 62a4bbcc44140b52d6bd8f648d81efa570c221dd Mon Sep 17 00:00:00 2001 From: Meenakshikumar Somasundaram Date: Tue, 20 Aug 2024 13:15:38 -0400 Subject: [PATCH 1431/1868] drm/amd/display: Add dpia debug option to control power management [Why] To provide option to dpia control power management [How] By adding disable_usb4_pm_support bit field in dpia_debug option to control dpia power management Reviewed-by: Jun Lei Signed-off-by: Meenakshikumar Somasundaram Signed-off-by: Hamza Mahfooz --- drivers/gpu/drm/amd/display/dc/dc.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 20b97b5e76846..dbb2e68e8adf0 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -761,7 +761,8 @@ union dpia_debug_options { uint32_t extend_aux_rd_interval:1; /* bit 2 */ uint32_t disable_mst_dsc_work_around:1; /* bit 3 */ uint32_t enable_force_tbt3_work_around:1; /* bit 4 */ - uint32_t reserved:27; + uint32_t disable_usb4_pm_support:1; /* bit 5 */ + uint32_t reserved:26; } bits; uint32_t raw; }; From 65b40820909167a76636ed42fe52fafede59ed63 Mon Sep 17 00:00:00 2001 From: Samson Tam Date: Wed, 21 Aug 2024 20:17:23 -0400 Subject: [PATCH 1432/1868] drm/amd/display: disable sharpness if HDR Multiplier is too large [Why] Certain profiles have higher HDR multiplier than SDR boost max which is not currently supported [How] Disable sharpness for these profiles Fixes: 63697e1d69c7 ("drm/amd/display: add improvements for text display and HDR DWM and MPO") Reviewed-by: Martin Leung Signed-off-by: Samson Tam Signed-off-by: Hamza Mahfooz --- drivers/gpu/drm/amd/display/dc/dc_spl_translate.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c b/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c index 75d00c6a38f4d..328499a778849 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c +++ b/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c @@ -180,9 +180,13 @@ void translate_SPL_in_params_from_pipe_ctx(struct pipe_ctx *pipe_ctx, struct spl spl_in->is_fullscreen = dm_helpers_is_fullscreen(pipe_ctx->stream->ctx, pipe_ctx->stream); spl_in->is_hdr_on = dm_helpers_is_hdr_on(pipe_ctx->stream->ctx, pipe_ctx->stream); spl_in->hdr_multx100 = 0; - if (spl_in->is_hdr_on) + if (spl_in->is_hdr_on) { spl_in->hdr_multx100 = (uint32_t)dc_fixpt_floor(dc_fixpt_mul(plane_state->hdr_mult, dc_fixpt_from_int(100))); + /* Disable sharpness for HDR Mult > 6.0 */ + if (spl_in->hdr_multx100 > 600) + spl_in->adaptive_sharpness.enable = false; + } } /// @brief Translate SPL output parameters to pipe context From 23dd222ff3cc4b29e9ce737a8d8444fe970d659d Mon Sep 17 00:00:00 2001 From: Dillon Varone Date: Tue, 20 Aug 2024 15:13:14 -0400 Subject: [PATCH 1433/1868] Revert "drm/amd/display: Wait for all pending cleared before full update" This reverts commit 3b837c45668c3026fd09145904692ba1130c5d12. It is causing graphics hangs. Reviewed-by: Martin Leung Signed-off-by: Dillon Varone Signed-off-by: Hamza Mahfooz --- .../drm/amd/display/dc/core/dc_hw_sequencer.c | 9 +--- .../amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 4 +- .../amd/display/dc/hwss/dcn30/dcn30_hwseq.c | 27 ----------- .../amd/display/dc/hwss/dcn30/dcn30_hwseq.h | 2 - .../amd/display/dc/hwss/dcn30/dcn30_init.c | 3 +- .../amd/display/dc/hwss/dcn301/dcn301_init.c | 1 - .../amd/display/dc/hwss/dcn32/dcn32_init.c | 1 - .../amd/display/dc/hwss/dcn401/dcn401_init.c | 1 - .../drm/amd/display/dc/hwss/hw_sequencer.h | 1 - .../amd/display/dc/inc/hw/timing_generator.h | 4 +- .../amd/display/dc/optc/dcn10/dcn10_optc.h | 9 ---- .../amd/display/dc/optc/dcn20/dcn20_optc.h | 7 +-- .../amd/display/dc/optc/dcn30/dcn30_optc.c | 45 ------------------- .../amd/display/dc/optc/dcn30/dcn30_optc.h | 13 +----- .../amd/display/dc/optc/dcn301/dcn301_optc.c | 3 -- .../amd/display/dc/optc/dcn31/dcn31_optc.h | 9 +--- .../amd/display/dc/optc/dcn314/dcn314_optc.h | 9 +--- .../amd/display/dc/optc/dcn32/dcn32_optc.c | 16 +++++-- .../amd/display/dc/optc/dcn32/dcn32_optc.h | 7 +-- .../amd/display/dc/optc/dcn35/dcn35_optc.h | 6 +-- .../amd/display/dc/optc/dcn401/dcn401_optc.c | 4 +- .../amd/display/dc/optc/dcn401/dcn401_optc.h | 6 +-- .../dc/resource/dcn32/dcn32_resource.h | 3 +- .../dc/resource/dcn401/dcn401_resource.h | 5 +-- 24 files changed, 34 insertions(+), 161 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c index 2cb9253c9bdec..7ee2be8f82c46 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c @@ -1071,13 +1071,8 @@ void hwss_wait_for_outstanding_hw_updates(struct dc *dc, struct dc_state *dc_con if (!pipe_ctx->stream) continue; - /* For full update we must wait for all double buffer updates, not just DRR updates. This - * is particularly important for minimal transitions. Only check for OTG_MASTER pipes, - * as non-OTG Master pipes share the same OTG as - */ - if (resource_is_pipe_type(pipe_ctx, OTG_MASTER) && dc->hwss.wait_for_all_pending_updates) { - dc->hwss.wait_for_all_pending_updates(pipe_ctx); - } + if (pipe_ctx->stream_res.tg->funcs->wait_drr_doublebuffer_pending_clear) + pipe_ctx->stream_res.tg->funcs->wait_drr_doublebuffer_pending_clear(pipe_ctx->stream_res.tg); hubp = pipe_ctx->plane_res.hubp; if (!hubp) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c index b383ed8cb4d49..a80c085829320 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c @@ -2255,9 +2255,9 @@ void dcn20_post_unlock_program_front_end( struct timing_generator *tg = pipe->stream_res.tg; - if (tg->funcs->get_optc_double_buffer_pending) { + if (tg->funcs->get_double_buffer_pending) { for (j = 0; j < TIMEOUT_FOR_PIPE_ENABLE_US / polling_interval_us - && tg->funcs->get_optc_double_buffer_pending(tg); j++) + && tg->funcs->get_double_buffer_pending(tg); j++) udelay(polling_interval_us); } } diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c index d5458dae6d305..42c52284a8680 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c @@ -1185,30 +1185,3 @@ void dcn30_prepare_bandwidth(struct dc *dc, if (!dc->clk_mgr->clks.fw_based_mclk_switching) dc_dmub_srv_p_state_delegate(dc, false, context); } - -void dcn30_wait_for_all_pending_updates(const struct pipe_ctx *pipe_ctx) -{ - struct timing_generator *tg = pipe_ctx->stream_res.tg; - bool pending_updates = false; - unsigned int i; - - if (tg && tg->funcs->is_tg_enabled(tg)) { - // Poll for 100ms maximum - for (i = 0; i < 100000; i++) { - pending_updates = false; - if (tg->funcs->get_optc_double_buffer_pending) - pending_updates |= tg->funcs->get_optc_double_buffer_pending(tg); - - if (tg->funcs->get_otg_double_buffer_pending) - pending_updates |= tg->funcs->get_otg_double_buffer_pending(tg); - - if (tg->funcs->get_pipe_update_pending) - pending_updates |= tg->funcs->get_pipe_update_pending(tg); - - if (!pending_updates) - break; - - udelay(1); - } - } -} diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h index 4b90b781c4f2d..6a153e7ce910e 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h @@ -96,6 +96,4 @@ void dcn30_set_hubp_blank(const struct dc *dc, void dcn30_prepare_bandwidth(struct dc *dc, struct dc_state *context); -void dcn30_wait_for_all_pending_updates(const struct pipe_ctx *pipe_ctx); - #endif /* __DC_HWSS_DCN30_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c index 0e8d32e3dbae1..2a8dc40d28477 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c @@ -108,8 +108,7 @@ static const struct hw_sequencer_funcs dcn30_funcs = { .set_disp_pattern_generator = dcn30_set_disp_pattern_generator, .get_dcc_en_bits = dcn10_get_dcc_en_bits, .update_visual_confirm_color = dcn10_update_visual_confirm_color, - .is_abm_supported = dcn21_is_abm_supported, - .wait_for_all_pending_updates = dcn30_wait_for_all_pending_updates, + .is_abm_supported = dcn21_is_abm_supported }; static const struct hwseq_private_funcs dcn30_private_funcs = { diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c index 780ce4c064aa5..93e49d87a67ce 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c @@ -107,7 +107,6 @@ static const struct hw_sequencer_funcs dcn301_funcs = { .optimize_pwr_state = dcn21_optimize_pwr_state, .exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state, .update_visual_confirm_color = dcn10_update_visual_confirm_color, - .wait_for_all_pending_updates = dcn30_wait_for_all_pending_updates, }; static const struct hwseq_private_funcs dcn301_private_funcs = { diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c index 8e0946fd5b7fe..3422b564ae984 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c @@ -121,7 +121,6 @@ static const struct hw_sequencer_funcs dcn32_funcs = { .is_pipe_topology_transition_seamless = dcn32_is_pipe_topology_transition_seamless, .calculate_pix_rate_divider = dcn32_calculate_pix_rate_divider, .program_outstanding_updates = dcn32_program_outstanding_updates, - .wait_for_all_pending_updates = dcn30_wait_for_all_pending_updates, }; static const struct hwseq_private_funcs dcn32_private_funcs = { diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c index 73a632b5ff893..a2ca07235c83d 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c @@ -100,7 +100,6 @@ static const struct hw_sequencer_funcs dcn401_funcs = { .fams2_update_config = dcn401_fams2_update_config, .fams2_global_control_lock_fast = dcn401_fams2_global_control_lock_fast, .program_outstanding_updates = dcn401_program_outstanding_updates, - .wait_for_all_pending_updates = dcn30_wait_for_all_pending_updates, }; static const struct hwseq_private_funcs dcn401_private_funcs = { diff --git a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h index b8c47e4c51c15..ac92056256233 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h @@ -462,7 +462,6 @@ struct hw_sequencer_funcs { void (*program_outstanding_updates)(struct dc *dc, struct dc_state *context); void (*setup_hpo_hw_control)(const struct dce_hwseq *hws, bool enable); - void (*wait_for_all_pending_updates)(const struct pipe_ctx *pipe_ctx); }; void color_space_to_black_color( diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h index 4e08e80eafe8e..3d4c8bd42b492 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h @@ -342,9 +342,7 @@ struct timing_generator_funcs { void (*wait_drr_doublebuffer_pending_clear)(struct timing_generator *tg); void (*set_long_vtotal)(struct timing_generator *optc, const struct long_vtotal_params *params); void (*wait_odm_doublebuffer_pending_clear)(struct timing_generator *tg); - bool (*get_optc_double_buffer_pending)(struct timing_generator *tg); - bool (*get_otg_double_buffer_pending)(struct timing_generator *tg); - bool (*get_pipe_update_pending)(struct timing_generator *tg); + bool (*get_double_buffer_pending)(struct timing_generator *tg); }; #endif diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h index 40757f20d73f4..b7a57f98553d7 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h @@ -202,7 +202,6 @@ struct dcn_optc_registers { uint32_t OPTC_CLOCK_CONTROL; uint32_t OPTC_WIDTH_CONTROL2; uint32_t OTG_PSTATE_REGISTER; - uint32_t OTG_PIPE_UPDATE_STATUS; }; #define TG_COMMON_MASK_SH_LIST_DCN(mask_sh)\ @@ -567,12 +566,6 @@ struct dcn_optc_registers { type OTG_H_TIMING_DIV_MODE_DB_UPDATE_PENDING;\ type OPTC_DOUBLE_BUFFER_PENDING;\ -#define TG_REG_FIELD_LIST_DCN2_0(type) \ - type OTG_FLIP_PENDING;\ - type OTG_DC_REG_UPDATE_PENDING;\ - type OTG_CURSOR_UPDATE_PENDING;\ - type OTG_VUPDATE_KEEPOUT_STATUS;\ - #define TG_REG_FIELD_LIST_DCN3_2(type) \ type OTG_H_TIMING_DIV_MODE_MANUAL; @@ -607,7 +600,6 @@ struct dcn_optc_registers { struct dcn_optc_shift { TG_REG_FIELD_LIST(uint8_t) - TG_REG_FIELD_LIST_DCN2_0(uint8_t) TG_REG_FIELD_LIST_DCN3_2(uint8_t) TG_REG_FIELD_LIST_DCN3_5(uint8_t) TG_REG_FIELD_LIST_DCN401(uint8_t) @@ -615,7 +607,6 @@ struct dcn_optc_shift { struct dcn_optc_mask { TG_REG_FIELD_LIST(uint32_t) - TG_REG_FIELD_LIST_DCN2_0(uint32_t) TG_REG_FIELD_LIST_DCN3_2(uint32_t) TG_REG_FIELD_LIST_DCN3_5(uint32_t) TG_REG_FIELD_LIST_DCN401(uint32_t) diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h index 928e110b95fb5..364034b190281 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h @@ -43,8 +43,7 @@ SRI(OPTC_MEMORY_CONFIG, ODM, inst),\ SR(DWB_SOURCE_SELECT),\ SRI(OTG_MANUAL_FLOW_CONTROL, OTG, inst), \ - SRI(OTG_DRR_CONTROL, OTG, inst),\ - SRI(OTG_PIPE_UPDATE_STATUS, OTG, inst) + SRI(OTG_DRR_CONTROL, OTG, inst) #define TG_COMMON_MASK_SH_LIST_DCN2_0(mask_sh)\ TG_COMMON_MASK_SH_LIST_DCN(mask_sh),\ @@ -54,10 +53,6 @@ SF(OTG0_OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, mask_sh),\ SF(OTG0_OTG_GLOBAL_CONTROL2, DIG_UPDATE_LOCATION, mask_sh),\ SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_RANGE_TIMING_DBUF_UPDATE_MODE, mask_sh),\ - SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_FLIP_PENDING, mask_sh),\ - SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_DC_REG_UPDATE_PENDING, mask_sh),\ - SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_CURSOR_UPDATE_PENDING, mask_sh),\ - SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_VUPDATE_KEEPOUT_STATUS, mask_sh),\ SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_START_X, mask_sh),\ SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_END_X, mask_sh), \ SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_START_Y, mask_sh),\ diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c index 4c95c09586122..abcd03d786684 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c @@ -271,48 +271,6 @@ void optc3_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_c optc1->opp_count = opp_cnt; } -/* OTG status register that indicates OPTC update is pending */ -bool optc3_get_optc_double_buffer_pending(struct timing_generator *optc) -{ - struct optc *optc1 = DCN10TG_FROM_TG(optc); - uint32_t update_pending = 0; - - REG_GET(OPTC_INPUT_GLOBAL_CONTROL, - OPTC_DOUBLE_BUFFER_PENDING, - &update_pending); - - return (update_pending == 1); -} - -/* OTG status register that indicates OTG update is pending */ -bool optc3_get_otg_update_pending(struct timing_generator *optc) -{ - struct optc *optc1 = DCN10TG_FROM_TG(optc); - uint32_t update_pending = 0; - - REG_GET(OTG_DOUBLE_BUFFER_CONTROL, - OTG_UPDATE_PENDING, - &update_pending); - - return (update_pending == 1); -} - -/* OTG status register that indicates surface update is pending */ -bool optc3_get_pipe_update_pending(struct timing_generator *optc) -{ - struct optc *optc1 = DCN10TG_FROM_TG(optc); - uint32_t flip_pending = 0; - uint32_t dc_update_pending = 0; - - REG_GET_2(OTG_PIPE_UPDATE_STATUS, - OTG_FLIP_PENDING, - &flip_pending, - OTG_DC_REG_UPDATE_PENDING, - &dc_update_pending); - - return (flip_pending == 1 || dc_update_pending == 1); -} - /** * optc3_set_timing_double_buffer() - DRR double buffering control * @@ -417,9 +375,6 @@ static struct timing_generator_funcs dcn30_tg_funcs = { .get_hw_timing = optc1_get_hw_timing, .wait_drr_doublebuffer_pending_clear = optc3_wait_drr_doublebuffer_pending_clear, .is_two_pixels_per_container = optc1_is_two_pixels_per_container, - .get_optc_double_buffer_pending = optc3_get_optc_double_buffer_pending, - .get_otg_double_buffer_pending = optc3_get_otg_update_pending, - .get_pipe_update_pending = optc3_get_pipe_update_pending, }; void dcn30_timing_generator_init(struct optc *optc1) diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h index e2303f9eaf13b..bda974d432ea6 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h @@ -109,8 +109,7 @@ SRI(OPTC_BYTES_PER_PIXEL, ODM, inst),\ SRI(OPTC_WIDTH_CONTROL, ODM, inst),\ SRI(OPTC_MEMORY_CONFIG, ODM, inst),\ - SR(DWB_SOURCE_SELECT),\ - SRI(OTG_PIPE_UPDATE_STATUS, OTG, inst) + SR(DWB_SOURCE_SELECT) #define DCN30_VTOTAL_REGS_SF(mask_sh) @@ -210,7 +209,6 @@ SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_GATE_DIS, mask_sh),\ SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_OCCURRED_STATUS, mask_sh),\ SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, mask_sh),\ - SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_DOUBLE_BUFFER_PENDING, mask_sh),\ SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\ SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\ SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\ @@ -321,11 +319,7 @@ SF(OTG0_OTG_DRR_V_TOTAL_CHANGE, OTG_DRR_V_TOTAL_CHANGE_LIMIT, mask_sh),\ SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, mask_sh),\ SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_PENDING, mask_sh),\ - SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_MODE, mask_sh),\ - SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_FLIP_PENDING, mask_sh),\ - SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_DC_REG_UPDATE_PENDING, mask_sh),\ - SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_CURSOR_UPDATE_PENDING, mask_sh),\ - SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_VUPDATE_KEEPOUT_STATUS, mask_sh),\ + SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_MODE, mask_sh) void dcn30_timing_generator_init(struct optc *optc1); @@ -362,7 +356,4 @@ void optc3_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_c void optc3_wait_drr_doublebuffer_pending_clear(struct timing_generator *optc); void optc3_tg_init(struct timing_generator *optc); void optc3_set_vtotal_min_max(struct timing_generator *optc, int vtotal_min, int vtotal_max); -bool optc3_get_optc_double_buffer_pending(struct timing_generator *optc); -bool optc3_get_otg_update_pending(struct timing_generator *optc); -bool optc3_get_pipe_update_pending(struct timing_generator *optc); #endif /* __DC_OPTC_DCN30_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn301/dcn301_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn301/dcn301_optc.c index d7a45ef2d01b3..1a22ae89fb555 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn301/dcn301_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn301/dcn301_optc.c @@ -169,9 +169,6 @@ static struct timing_generator_funcs dcn30_tg_funcs = { .get_hw_timing = optc1_get_hw_timing, .wait_drr_doublebuffer_pending_clear = optc3_wait_drr_doublebuffer_pending_clear, .is_two_pixels_per_container = optc1_is_two_pixels_per_container, - .get_optc_double_buffer_pending = optc3_get_optc_double_buffer_pending, - .get_otg_double_buffer_pending = optc3_get_otg_update_pending, - .get_pipe_update_pending = optc3_get_pipe_update_pending, }; void dcn301_timing_generator_init(struct optc *optc1) diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h index fbbe86d00c2e3..30b81a448ce2d 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h @@ -99,8 +99,7 @@ SRI(OPTC_MEMORY_CONFIG, ODM, inst),\ SRI(OTG_CRC_CNTL2, OTG, inst),\ SR(DWB_SOURCE_SELECT),\ - SRI(OTG_DRR_CONTROL, OTG, inst),\ - SRI(OTG_PIPE_UPDATE_STATUS, OTG, inst) + SRI(OTG_DRR_CONTROL, OTG, inst) #define OPTC_COMMON_MASK_SH_LIST_DCN3_1(mask_sh)\ SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\ @@ -255,11 +254,7 @@ SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_COMBINE_MODE, mask_sh),\ SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_SPLIT_MODE, mask_sh),\ SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_FORMAT, mask_sh),\ - SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh),\ - SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_FLIP_PENDING, mask_sh),\ - SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_DC_REG_UPDATE_PENDING, mask_sh),\ - SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_CURSOR_UPDATE_PENDING, mask_sh),\ - SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_VUPDATE_KEEPOUT_STATUS, mask_sh),\ + SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh) void dcn31_timing_generator_init(struct optc *optc1); diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h index 0ff72b97b465c..99c098e76116f 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h @@ -98,8 +98,7 @@ SRI(OPTC_BYTES_PER_PIXEL, ODM, inst),\ SRI(OPTC_WIDTH_CONTROL, ODM, inst),\ SRI(OPTC_MEMORY_CONFIG, ODM, inst),\ - SRI(OTG_DRR_CONTROL, OTG, inst),\ - SRI(OTG_PIPE_UPDATE_STATUS, OTG, inst) + SRI(OTG_DRR_CONTROL, OTG, inst) #define OPTC_COMMON_MASK_SH_LIST_DCN3_14(mask_sh)\ SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\ @@ -249,11 +248,7 @@ SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, mask_sh),\ SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE_MANUAL, mask_sh),\ SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_MODE, mask_sh),\ - SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh),\ - SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_FLIP_PENDING, mask_sh),\ - SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_DC_REG_UPDATE_PENDING, mask_sh),\ - SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_CURSOR_UPDATE_PENDING, mask_sh),\ - SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_VUPDATE_KEEPOUT_STATUS, mask_sh),\ + SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh) void dcn314_timing_generator_init(struct optc *optc1); diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c index c217f653b3c81..00094f0e84706 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c @@ -297,6 +297,18 @@ static void optc32_set_drr( optc32_setup_manual_trigger(optc); } +bool optc32_get_double_buffer_pending(struct timing_generator *optc) +{ + struct optc *optc1 = DCN10TG_FROM_TG(optc); + uint32_t update_pending = 0; + + REG_GET(OPTC_INPUT_GLOBAL_CONTROL, + OPTC_DOUBLE_BUFFER_PENDING, + &update_pending); + + return (update_pending == 1); +} + static struct timing_generator_funcs dcn32_tg_funcs = { .validate_timing = optc1_validate_timing, .program_timing = optc1_program_timing, @@ -361,9 +373,7 @@ static struct timing_generator_funcs dcn32_tg_funcs = { .setup_manual_trigger = optc2_setup_manual_trigger, .get_hw_timing = optc1_get_hw_timing, .is_two_pixels_per_container = optc1_is_two_pixels_per_container, - .get_optc_double_buffer_pending = optc3_get_optc_double_buffer_pending, - .get_otg_double_buffer_pending = optc3_get_otg_update_pending, - .get_pipe_update_pending = optc3_get_pipe_update_pending, + .get_double_buffer_pending = optc32_get_double_buffer_pending, }; void dcn32_timing_generator_init(struct optc *optc1) diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.h index 0b0964a9da748..665d7c52f67cd 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.h +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.h @@ -177,11 +177,7 @@ SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, mask_sh),\ SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE_MANUAL, mask_sh),\ SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_MODE, mask_sh),\ - SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh),\ - SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_FLIP_PENDING, mask_sh),\ - SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_DC_REG_UPDATE_PENDING, mask_sh),\ - SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_CURSOR_UPDATE_PENDING, mask_sh),\ - SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_VUPDATE_KEEPOUT_STATUS, mask_sh) + SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh) void dcn32_timing_generator_init(struct optc *optc1); void optc32_set_h_timing_div_manual_mode(struct timing_generator *optc, bool manual_mode); @@ -189,5 +185,6 @@ void optc32_get_odm_combine_segments(struct timing_generator *tg, int *odm_combi void optc32_set_odm_bypass(struct timing_generator *optc, const struct dc_crtc_timing *dc_crtc_timing); void optc32_wait_odm_doublebuffer_pending_clear(struct timing_generator *tg); +bool optc32_get_double_buffer_pending(struct timing_generator *optc); #endif /* __DC_OPTC_DCN32_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.h index be749ab41dce7..d077e2392379c 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.h +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.h @@ -67,11 +67,7 @@ SF(OTG0_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK, OTG_CRC1_WINDOWB_Y_END_READBACK, mask_sh),\ SF(OPTC_CLOCK_CONTROL, OPTC_FGCG_REP_DIS, mask_sh),\ SF(OTG0_OTG_V_COUNT_STOP_CONTROL, OTG_V_COUNT_STOP, mask_sh),\ - SF(OTG0_OTG_V_COUNT_STOP_CONTROL2, OTG_V_COUNT_STOP_TIMER, mask_sh),\ - SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_FLIP_PENDING, mask_sh),\ - SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_DC_REG_UPDATE_PENDING, mask_sh),\ - SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_CURSOR_UPDATE_PENDING, mask_sh),\ - SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_VUPDATE_KEEPOUT_STATUS, mask_sh) + SF(OTG0_OTG_V_COUNT_STOP_CONTROL2, OTG_V_COUNT_STOP_TIMER, mask_sh) void dcn35_timing_generator_init(struct optc *optc1); diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c index db670fc172644..a5d6a7dca554c 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c @@ -493,9 +493,7 @@ static struct timing_generator_funcs dcn401_tg_funcs = { .setup_manual_trigger = optc2_setup_manual_trigger, .get_hw_timing = optc1_get_hw_timing, .is_two_pixels_per_container = optc1_is_two_pixels_per_container, - .get_optc_double_buffer_pending = optc3_get_optc_double_buffer_pending, - .get_otg_double_buffer_pending = optc3_get_otg_update_pending, - .get_pipe_update_pending = optc3_get_pipe_update_pending, + .get_double_buffer_pending = optc32_get_double_buffer_pending, }; void dcn401_timing_generator_init(struct optc *optc1) diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.h index 1be89571986ff..bb13a645802d0 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.h +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.h @@ -159,11 +159,7 @@ SF(OTG0_OTG_PSTATE_REGISTER, OTG_PSTATE_KEEPOUT_START, mask_sh),\ SF(OTG0_OTG_PSTATE_REGISTER, OTG_PSTATE_EXTEND, mask_sh),\ SF(OTG0_OTG_PSTATE_REGISTER, OTG_UNBLANK, mask_sh),\ - SF(OTG0_OTG_PSTATE_REGISTER, OTG_PSTATE_ALLOW_WIDTH_MIN, mask_sh),\ - SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_FLIP_PENDING, mask_sh),\ - SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_DC_REG_UPDATE_PENDING, mask_sh),\ - SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_CURSOR_UPDATE_PENDING, mask_sh),\ - SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_VUPDATE_KEEPOUT_STATUS, mask_sh) + SF(OTG0_OTG_PSTATE_REGISTER, OTG_PSTATE_ALLOW_WIDTH_MIN, mask_sh) void dcn401_timing_generator_init(struct optc *optc1); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h index 86c6e5e8c42eb..7901792afb7b3 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h @@ -1054,8 +1054,7 @@ unsigned int dcn32_calculate_mall_ways_from_bytes(const struct dc *dc, unsigned SRI_ARR(OPTC_BYTES_PER_PIXEL, ODM, inst), \ SRI_ARR(OPTC_WIDTH_CONTROL, ODM, inst), \ SRI_ARR(OPTC_MEMORY_CONFIG, ODM, inst), \ - SRI_ARR(OTG_DRR_CONTROL, OTG, inst), \ - SRI_ARR(OTG_PIPE_UPDATE_STATUS, OTG, inst) + SRI_ARR(OTG_DRR_CONTROL, OTG, inst) /* HUBP */ diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h index bdafa7496ceae..514d1ce20df9e 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h @@ -536,9 +536,8 @@ void dcn401_prepare_mcache_programming(struct dc *dc, struct dc_state *context); SRI_ARR(OPTC_WIDTH_CONTROL, ODM, inst), \ SRI_ARR(OPTC_WIDTH_CONTROL2, ODM, inst), \ SRI_ARR(OPTC_MEMORY_CONFIG, ODM, inst), \ - SRI_ARR(OTG_DRR_CONTROL, OTG, inst), \ - SRI_ARR(OTG_PSTATE_REGISTER, OTG, inst), \ - SRI_ARR(OTG_PIPE_UPDATE_STATUS, OTG, inst) + SRI_ARR(OTG_DRR_CONTROL, OTG, inst), \ + SRI_ARR(OTG_PSTATE_REGISTER, OTG, inst) /* HUBBUB */ #define HUBBUB_REG_LIST_DCN4_01_RI(id) \ From b6530bfaaefc10d167f08a50da1c008c9e2a9119 Mon Sep 17 00:00:00 2001 From: Relja Vojvodic Date: Wed, 21 Aug 2024 09:34:21 -0400 Subject: [PATCH 1434/1868] drm/amd/display: Add sharpness control interface - Add interface for controlling shapness level input into DCN. - Update SPL to support custom sharpness values. - Add support for different sharpness values depending on YUV/RGB content. Reviewed-by: Samson Tam Signed-off-by: Relja Vojvodic Signed-off-by: Hamza Mahfooz --- drivers/gpu/drm/amd/display/dc/core/dc.c | 8 +- drivers/gpu/drm/amd/display/dc/dc.h | 3 +- .../gpu/drm/amd/display/dc/dc_spl_translate.c | 46 ++-- drivers/gpu/drm/amd/display/dc/dc_stream.h | 3 + .../display/dc/dpp/dcn401/dcn401_dpp_dscl.c | 24 +- drivers/gpu/drm/amd/display/dc/spl/dc_spl.c | 4 +- .../display/dc/spl/dc_spl_isharp_filters.c | 213 +++++------------- .../display/dc/spl/dc_spl_isharp_filters.h | 2 +- .../gpu/drm/amd/display/dc/spl/dc_spl_types.h | 27 ++- 9 files changed, 138 insertions(+), 192 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 03df38703095e..a5a988fe1e742 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -2690,6 +2690,9 @@ static enum surface_update_type check_update_surfaces_for_stream( stream_update->vrr_active_variable || stream_update->vrr_active_fixed)) su_flags->bits.fams_changed = 1; + if (stream_update->scaler_sharpener_update) + su_flags->bits.scaler_sharpener = 1; + if (su_flags->raw != 0) overall_type = UPDATE_TYPE_FULL; @@ -3023,6 +3026,8 @@ static void copy_stream_update_to_stream(struct dc *dc, update->dsc_config = NULL; } } + if (update->scaler_sharpener_update) + stream->scaler_sharpener_update = *update->scaler_sharpener_update; } static void backup_planes_and_stream_state( @@ -4714,7 +4719,8 @@ static bool full_update_required(struct dc *dc, stream_update->func_shaper || stream_update->lut3d_func || stream_update->pending_test_pattern || - stream_update->crtc_timing_adjust)) + stream_update->crtc_timing_adjust || + stream_update->scaler_sharpener_update)) return true; if (stream) { diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index dbb2e68e8adf0..22f0d64148751 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -1055,6 +1055,7 @@ struct dc_debug_options { unsigned int disable_spl; unsigned int force_easf; unsigned int force_sharpness; + unsigned int force_sharpness_level; unsigned int force_lls; bool notify_dpia_hr_bw; bool enable_ips_visual_confirm; @@ -1351,7 +1352,7 @@ struct dc_plane_state { enum mpcc_movable_cm_location mcm_location; struct dc_csc_transform cursor_csc_color_matrix; bool adaptive_sharpness_en; - unsigned int sharpnessX1000; + int sharpness_level; enum linear_light_scaling linear_light_scaling; }; diff --git a/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c b/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c index 328499a778849..cd6de93eb91c3 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c +++ b/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c @@ -139,24 +139,36 @@ void translate_SPL_in_params_from_pipe_ctx(struct pipe_ctx *pipe_ctx, struct spl else if (pipe_ctx->stream->ctx->dc->debug.force_easf == 2) spl_in->disable_easf = true; /* Translate adaptive sharpening preference */ - if (pipe_ctx->stream->ctx->dc->debug.force_sharpness > 0) { - spl_in->adaptive_sharpness.enable = (pipe_ctx->stream->ctx->dc->debug.force_sharpness > 1) ? true : false; - if (pipe_ctx->stream->ctx->dc->debug.force_sharpness == 2) - spl_in->adaptive_sharpness.sharpness = SHARPNESS_LOW; - else if (pipe_ctx->stream->ctx->dc->debug.force_sharpness == 3) - spl_in->adaptive_sharpness.sharpness = SHARPNESS_MID; - else if (pipe_ctx->stream->ctx->dc->debug.force_sharpness >= 4) - spl_in->adaptive_sharpness.sharpness = SHARPNESS_HIGH; - } else { - spl_in->adaptive_sharpness.enable = plane_state->adaptive_sharpness_en; - if (plane_state->sharpnessX1000 == 0) + unsigned int sharpness_setting = pipe_ctx->stream->ctx->dc->debug.force_sharpness; + unsigned int force_sharpness_level = pipe_ctx->stream->ctx->dc->debug.force_sharpness_level; + if (sharpness_setting == SHARPNESS_HW_OFF) + spl_in->adaptive_sharpness.enable = false; + else if (sharpness_setting == SHARPNESS_ZERO) { + spl_in->adaptive_sharpness.enable = true; + spl_in->adaptive_sharpness.sharpness_level = 0; + } else if (sharpness_setting == SHARPNESS_CUSTOM) { + spl_in->adaptive_sharpness.sharpness_range.sdr_rgb_min = 0; + spl_in->adaptive_sharpness.sharpness_range.sdr_rgb_max = 1750; + spl_in->adaptive_sharpness.sharpness_range.sdr_rgb_mid = 750; + spl_in->adaptive_sharpness.sharpness_range.sdr_yuv_min = 0; + spl_in->adaptive_sharpness.sharpness_range.sdr_yuv_max = 3500; + spl_in->adaptive_sharpness.sharpness_range.sdr_yuv_mid = 1500; + spl_in->adaptive_sharpness.sharpness_range.hdr_rgb_min = 0; + spl_in->adaptive_sharpness.sharpness_range.hdr_rgb_max = 2750; + spl_in->adaptive_sharpness.sharpness_range.hdr_rgb_mid = 1500; + + if (force_sharpness_level > 0) { + if (force_sharpness_level > 10) + force_sharpness_level = 10; + spl_in->adaptive_sharpness.enable = true; + spl_in->adaptive_sharpness.sharpness_level = force_sharpness_level; + } else if (!plane_state->adaptive_sharpness_en) { spl_in->adaptive_sharpness.enable = false; - else if (plane_state->sharpnessX1000 < 999) - spl_in->adaptive_sharpness.sharpness = SHARPNESS_LOW; - else if (plane_state->sharpnessX1000 < 1999) - spl_in->adaptive_sharpness.sharpness = SHARPNESS_MID; - else // Any other value is high sharpness - spl_in->adaptive_sharpness.sharpness = SHARPNESS_HIGH; + spl_in->adaptive_sharpness.sharpness_level = 0; + } else { + spl_in->adaptive_sharpness.enable = true; + spl_in->adaptive_sharpness.sharpness_level = plane_state->sharpness_level; + } } // Translate linear light scaling preference if (pipe_ctx->stream->ctx->dc->debug.force_lls > 0) diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h index de9bd72ca514d..14ea47eda0c87 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_stream.h +++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h @@ -142,6 +142,7 @@ union stream_update_flags { uint32_t mst_bw : 1; uint32_t crtc_timing_adjust : 1; uint32_t fams_changed : 1; + uint32_t scaler_sharpener : 1; } bits; uint32_t raw; @@ -308,6 +309,7 @@ struct dc_stream_state { bool is_phantom; struct luminance_data lumin_data; + bool scaler_sharpener_update; }; #define ABM_LEVEL_IMMEDIATE_DISABLE 255 @@ -353,6 +355,7 @@ struct dc_stream_update { struct dc_cursor_attributes *cursor_attributes; struct dc_cursor_position *cursor_position; bool *hw_cursor_req; + bool *scaler_sharpener_update; }; bool dc_is_stream_unchanged( diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c index 703d7b51c6c27..01f98139292e7 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c @@ -957,6 +957,7 @@ static void dpp401_dscl_set_isharp_filter( */ static void dpp401_dscl_program_isharp(struct dpp *dpp_base, const struct scaler_data *scl_data, + bool program_isharp_1dlut, bool *bs_coeffs_updated) { struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base); @@ -1015,7 +1016,8 @@ static void dpp401_dscl_program_isharp(struct dpp *dpp_base, ISHARP_LBA_PWL_BASE_SEG5, scl_data->dscl_prog_data.isharp_lba.base_seg[5]); /* ISHARP_DELTA_LUT */ - dpp401_dscl_set_isharp_filter(dpp, scl_data->dscl_prog_data.isharp_delta); + if (!program_isharp_1dlut) + dpp401_dscl_set_isharp_filter(dpp, scl_data->dscl_prog_data.isharp_delta); /* ISHARP_NLDELTA_SOFT_CLIP */ REG_SET_6(ISHARP_NLDELTA_SOFT_CLIP, 0, @@ -1071,13 +1073,29 @@ void dpp401_dscl_set_scaler_manual_scale(struct dpp *dpp_base, dpp_base, scl_data, dpp_base->ctx->dc->debug.always_scale); bool ycbcr = scl_data->format >= PIXEL_FORMAT_VIDEO_BEGIN && scl_data->format <= PIXEL_FORMAT_VIDEO_END; + bool program_isharp_1dlut = false; bool bs_coeffs_updated = false; + if (memcmp(&dpp->scl_data, scl_data, sizeof(*scl_data)) == 0) return; PERF_TRACE(); + /* If only sharpness has changed, then only update 1dlut, then return */ + if (scl_data->dscl_prog_data.isharp_en && + (dpp->scl_data.dscl_prog_data.sharpness_level + != scl_data->dscl_prog_data.sharpness_level)) { + /* ISHARP_DELTA_LUT */ + dpp401_dscl_set_isharp_filter(dpp, scl_data->dscl_prog_data.isharp_delta); + dpp->scl_data.dscl_prog_data.sharpness_level = scl_data->dscl_prog_data.sharpness_level; + dpp->scl_data.dscl_prog_data.isharp_delta = scl_data->dscl_prog_data.isharp_delta; + + if (memcmp(&dpp->scl_data, scl_data, sizeof(*scl_data)) == 0) + return; + program_isharp_1dlut = true; + } + dpp->scl_data = *scl_data; if ((dpp->base.ctx->dc->config.use_spl) && (!dpp->base.ctx->dc->debug.disable_spl)) { @@ -1131,7 +1149,7 @@ void dpp401_dscl_set_scaler_manual_scale(struct dpp *dpp_base, if (dscl_mode == DSCL_MODE_SCALING_444_BYPASS) { if (dpp->base.ctx->dc->config.prefer_easf) dpp401_dscl_disable_easf(dpp_base, scl_data); - dpp401_dscl_program_isharp(dpp_base, scl_data, &bs_coeffs_updated); + dpp401_dscl_program_isharp(dpp_base, scl_data, program_isharp_1dlut, &bs_coeffs_updated); return; } @@ -1165,7 +1183,7 @@ void dpp401_dscl_set_scaler_manual_scale(struct dpp *dpp_base, * WB scaler coeffs and toggle coeff RAM together */ //if (dpp->base.ctx->dc->config.prefer_easf) - dpp401_dscl_program_isharp(dpp_base, scl_data, &bs_coeffs_updated); + dpp401_dscl_program_isharp(dpp_base, scl_data, program_isharp_1dlut, &bs_coeffs_updated); dpp401_dscl_set_scl_filter(dpp, scl_data, ycbcr, bs_coeffs_updated); /* Edge adaptive scaler function configuration */ diff --git a/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c b/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c index b6d1cfc494fca..15f7eda903e64 100644 --- a/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c +++ b/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c @@ -1662,8 +1662,10 @@ static void spl_set_isharp_data(struct dscl_prog_data *dscl_prog_data, dscl_prog_data->isharp_lba.base_seg[5] = 0; // ISHARP LBA PWL for Seg 5. BASE value in U0.6 format } - spl_build_isharp_1dlut_from_reference_curve(ratio, setup, adp_sharpness.sharpness); + + spl_build_isharp_1dlut_from_reference_curve(ratio, setup, adp_sharpness); dscl_prog_data->isharp_delta = spl_get_pregen_filter_isharp_1D_lut(setup); + dscl_prog_data->sharpness_level = adp_sharpness.sharpness_level; // Program the nldelta soft clip values if (lls_pref == LLS_PREF_YES) { diff --git a/drivers/gpu/drm/amd/display/dc/spl/dc_spl_isharp_filters.c b/drivers/gpu/drm/amd/display/dc/spl/dc_spl_isharp_filters.c index 8e4bcba2932a6..33712f50d303b 100644 --- a/drivers/gpu/drm/amd/display/dc/spl/dc_spl_isharp_filters.c +++ b/drivers/gpu/drm/amd/display/dc/spl/dc_spl_isharp_filters.c @@ -460,114 +460,6 @@ static uint16_t filter_isharp_bs_4tap_in_6_64p_s1_12[198]; static uint16_t filter_isharp_bs_4tap_64p_s1_12[132]; static uint16_t filter_isharp_bs_3tap_64p_s1_12[99]; -struct scale_ratio_to_sharpness_level_lookup scale_to_sharp_sdr_nl[3][6] = { - { /* LOW */ - {1125, 1000, 75, 100}, - {11, 10, 6, 10}, - {1075, 1000, 45, 100}, - {105, 100, 3, 10}, - {1025, 1000, 15, 100}, - {1, 1, 0, 1}, - }, - { /* MID */ - {1125, 1000, 2, 1}, - {11, 10, 175, 100}, - {1075, 1000, 15, 10}, - {105, 100, 125, 100}, - {1025, 1000, 1, 1}, - {1, 1, 75, 100}, - }, - { /* HIGH */ - {1125, 1000, 35, 10}, - {11, 10, 32, 10}, - {1075, 1000, 29, 10}, - {105, 100, 26, 10}, - {1025, 1000, 23, 10}, - {1, 1, 2, 1}, - }, -}; - -struct scale_ratio_to_sharpness_level_lookup scale_to_sharp_sdr_l[3][6] = { - { /* LOW */ - {1125, 1000, 75, 100}, - {11, 10, 6, 10}, - {1075, 1000, 45, 100}, - {105, 100, 3, 10}, - {1025, 1000, 15, 100}, - {1, 1, 0, 1}, - }, - { /* MID */ - {1125, 1000, 15, 10}, - {11, 10, 135, 100}, - {1075, 1000, 12, 10}, - {105, 100, 105, 100}, - {1025, 1000, 9, 10}, - {1, 1, 75, 100}, - }, - { /* HIGH */ - {1125, 1000, 25, 10}, - {11, 10, 23, 10}, - {1075, 1000, 21, 10}, - {105, 100, 19, 10}, - {1025, 1000, 17, 10}, - {1, 1, 15, 10}, - }, -}; - -struct scale_ratio_to_sharpness_level_lookup scale_to_sharp_hdr_nl[3][6] = { - { /* LOW */ - {1125, 1000, 5, 10}, - {11, 10, 4, 10}, - {1075, 1000, 3, 10}, - {105, 100, 2, 10}, - {1025, 1000, 1, 10}, - {1, 1, 0, 1}, - }, - { /* MID */ - {1125, 1000, 1, 1}, - {11, 10, 9, 10}, - {1075, 1000, 8, 10}, - {105, 100, 7, 10}, - {1025, 1000, 6, 10}, - {1, 1, 5, 10}, - }, - { /* HIGH */ - {1125, 1000, 15, 10}, - {11, 10, 14, 10}, - {1075, 1000, 13, 10}, - {105, 100, 12, 10}, - {1025, 1000, 11, 10}, - {1, 1, 1, 1}, - }, -}; - -struct scale_ratio_to_sharpness_level_lookup scale_to_sharp_hdr_l[3][6] = { - { /* LOW */ - {1125, 1000, 75, 100}, - {11, 10, 6, 10}, - {1075, 1000, 45, 100}, - {105, 100, 3, 10}, - {1025, 1000, 15, 100}, - {1, 1, 0, 1}, - }, - { /* MID */ - {1125, 1000, 15, 10}, - {11, 10, 135, 100}, - {1075, 1000, 12, 10}, - {105, 100, 105, 100}, - {1025, 1000, 9, 10}, - {1, 1, 75, 100}, - }, - { /* HIGH */ - {1125, 1000, 25, 10}, - {11, 10, 23, 10}, - {1075, 1000, 21, 10}, - {105, 100, 19, 10}, - {1025, 1000, 17, 10}, - {1, 1, 15, 10}, - }, -}; - /* Pre-generated 1DLUT for given setup and sharpness level */ struct isharp_1D_lut_pregen filter_isharp_1D_lut_pregen[NUM_SHARPNESS_SETUPS] = { { @@ -649,74 +541,72 @@ uint16_t *spl_get_filter_isharp_bs_3tap_64p(void) return filter_isharp_bs_3tap_64p_s1_12; } -void spl_build_isharp_1dlut_from_reference_curve(struct spl_fixed31_32 ratio, enum system_setup setup, enum explicit_sharpness sharpness) +static unsigned int spl_calculate_sharpness_level(int discrete_sharpness_level, enum system_setup setup, + struct spl_sharpness_range sharpness_range) { - uint8_t *byte_ptr_1dlut_src, *byte_ptr_1dlut_dst; - struct spl_fixed31_32 sharp_base, sharp_calc, sharp_level, ratio_level; - int j; - struct scale_ratio_to_sharpness_level_lookup *setup_lookup_ptr; - int num_sharp_ramp_levels; - int size_1dlut; - int sharp_calc_int; - uint32_t filter_pregen_store[ISHARP_LUT_TABLE_SIZE]; + unsigned int sharpness_level = 0; + + int min_sharpness, max_sharpness, mid_sharpness; - /* - * Given scaling ratio, setup and sharpness, build pregenerated - * 1DLUT tables - * - * Based on setup ( HDR/SDR, L/NL ), get base scale ratio to - * sharpness curve - */ switch (setup) { + case HDR_L: - setup_lookup_ptr = scale_to_sharp_hdr_l[sharpness]; - num_sharp_ramp_levels = sizeof(scale_to_sharp_hdr_l[sharpness])/ - sizeof(struct scale_ratio_to_sharpness_level_lookup); + min_sharpness = sharpness_range.hdr_rgb_min; + max_sharpness = sharpness_range.hdr_rgb_max; + mid_sharpness = sharpness_range.hdr_rgb_mid; break; case HDR_NL: - setup_lookup_ptr = scale_to_sharp_hdr_nl[sharpness]; - num_sharp_ramp_levels = sizeof(scale_to_sharp_hdr_nl[sharpness])/ - sizeof(struct scale_ratio_to_sharpness_level_lookup); + /* currently no use case, use Non-linear SDR values for now */ + case SDR_NL: + min_sharpness = sharpness_range.sdr_yuv_min; + max_sharpness = sharpness_range.sdr_yuv_max; + mid_sharpness = sharpness_range.sdr_yuv_mid; break; case SDR_L: - setup_lookup_ptr = scale_to_sharp_sdr_l[sharpness]; - num_sharp_ramp_levels = sizeof(scale_to_sharp_sdr_l[sharpness])/ - sizeof(struct scale_ratio_to_sharpness_level_lookup); - break; - case SDR_NL: default: - setup_lookup_ptr = scale_to_sharp_sdr_nl[sharpness]; - num_sharp_ramp_levels = sizeof(scale_to_sharp_sdr_nl[sharpness])/ - sizeof(struct scale_ratio_to_sharpness_level_lookup); + min_sharpness = sharpness_range.sdr_rgb_min; + max_sharpness = sharpness_range.sdr_rgb_max; + mid_sharpness = sharpness_range.sdr_rgb_mid; break; } - /* - * Compare desired scaling ratio and find adjusted sharpness from - * base scale ratio to sharpness curve - */ - j = 0; - sharp_level = spl_fixpt_zero; - while (j < num_sharp_ramp_levels) { - ratio_level = spl_fixpt_from_fraction(setup_lookup_ptr->ratio_numer, - setup_lookup_ptr->ratio_denom); - if (ratio.value >= ratio_level.value) { - sharp_level = spl_fixpt_from_fraction(setup_lookup_ptr->sharpness_numer, - setup_lookup_ptr->sharpness_denom); - break; - } - setup_lookup_ptr++; - j++; - } + int lower_half_step_size = (mid_sharpness - min_sharpness) / 5; + int upper_half_step_size = (max_sharpness - mid_sharpness) / 5; + + // lower half linear approximation + if (discrete_sharpness_level < 5) + sharpness_level = min_sharpness + (lower_half_step_size * discrete_sharpness_level); + // upper half linear approximation + else + sharpness_level = mid_sharpness + (upper_half_step_size * (discrete_sharpness_level - 5)); + + return sharpness_level; +} + +void spl_build_isharp_1dlut_from_reference_curve(struct spl_fixed31_32 ratio, enum system_setup setup, + struct adaptive_sharpness sharpness) +{ + uint8_t *byte_ptr_1dlut_src, *byte_ptr_1dlut_dst; + struct spl_fixed31_32 sharp_base, sharp_calc, sharp_level; + int j; + int size_1dlut; + int sharp_calc_int; + uint32_t filter_pregen_store[ISHARP_LUT_TABLE_SIZE]; + + /* Custom sharpnessX1000 value */ + unsigned int sharpnessX1000 = spl_calculate_sharpness_level(sharpness.sharpness_level, + setup, sharpness.sharpness_range); + sharp_level = spl_fixpt_from_fraction(sharpnessX1000, 1000); /* * Check if pregen 1dlut table is already precalculated * If numer/denom is different, then recalculate */ - if ((filter_isharp_1D_lut_pregen[setup].sharpness_numer == setup_lookup_ptr->sharpness_numer) && - (filter_isharp_1D_lut_pregen[setup].sharpness_denom == setup_lookup_ptr->sharpness_denom)) + if ((filter_isharp_1D_lut_pregen[setup].sharpness_numer == sharpnessX1000) && + (filter_isharp_1D_lut_pregen[setup].sharpness_denom == 1000)) return; + /* * Calculate LUT_128_gained with this equation: * @@ -737,8 +627,9 @@ void spl_build_isharp_1dlut_from_reference_curve(struct spl_fixed31_32 ratio, en sharp_calc = spl_fixpt_min(spl_fixpt_from_int(255), sharp_calc); sharp_calc = spl_fixpt_add(sharp_calc, spl_fixpt_from_fraction(1, 2)); sharp_calc_int = spl_fixpt_floor(sharp_calc); - if (sharp_calc_int > 255) - sharp_calc_int = 255; + /* Clamp it at 0x7F so it doesn't wrap */ + if (sharp_calc_int > 127) + sharp_calc_int = 127; *byte_ptr_1dlut_dst = (uint8_t)sharp_calc_int; byte_ptr_1dlut_src++; @@ -747,8 +638,8 @@ void spl_build_isharp_1dlut_from_reference_curve(struct spl_fixed31_32 ratio, en /* Update 1dlut table and sharpness level */ memcpy((void *)filter_isharp_1D_lut_pregen[setup].value, (void *)filter_pregen_store, size_1dlut); - filter_isharp_1D_lut_pregen[setup].sharpness_numer = setup_lookup_ptr->sharpness_numer; - filter_isharp_1D_lut_pregen[setup].sharpness_denom = setup_lookup_ptr->sharpness_denom; + filter_isharp_1D_lut_pregen[setup].sharpness_numer = sharpnessX1000; + filter_isharp_1D_lut_pregen[setup].sharpness_denom = 1000; } uint32_t *spl_get_pregen_filter_isharp_1D_lut(enum system_setup setup) diff --git a/drivers/gpu/drm/amd/display/dc/spl/dc_spl_isharp_filters.h b/drivers/gpu/drm/amd/display/dc/spl/dc_spl_isharp_filters.h index 3d023a154a92e..fe0b12571f2c5 100644 --- a/drivers/gpu/drm/amd/display/dc/spl/dc_spl_isharp_filters.h +++ b/drivers/gpu/drm/amd/display/dc/spl/dc_spl_isharp_filters.h @@ -45,6 +45,6 @@ void spl_init_blur_scale_coeffs(void); void spl_set_blur_scale_data(struct dscl_prog_data *dscl_prog_data, const struct spl_scaler_data *data); -void spl_build_isharp_1dlut_from_reference_curve(struct spl_fixed31_32 ratio, enum system_setup setup, enum explicit_sharpness sharpness); +void spl_build_isharp_1dlut_from_reference_curve(struct spl_fixed31_32 ratio, enum system_setup setup, struct adaptive_sharpness sharpness); uint32_t *spl_get_pregen_filter_isharp_1D_lut(enum system_setup setup); #endif /* __DC_SPL_ISHARP_FILTERS_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/spl/dc_spl_types.h b/drivers/gpu/drm/amd/display/dc/spl/dc_spl_types.h index 7c1a21c2305d1..85b19ebe2c576 100644 --- a/drivers/gpu/drm/amd/display/dc/spl/dc_spl_types.h +++ b/drivers/gpu/drm/amd/display/dc/spl/dc_spl_types.h @@ -407,6 +407,7 @@ struct dscl_prog_data { /* blur and scale filter */ const uint16_t *filter_blur_scale_v; const uint16_t *filter_blur_scale_h; + int sharpness_level; /* Track sharpness level */ }; /* SPL input and output definitions */ @@ -460,14 +461,26 @@ struct basic_out { bool alpha_en; bool use_two_pixels_per_container; }; -enum explicit_sharpness { - SHARPNESS_LOW = 0, - SHARPNESS_MID, - SHARPNESS_HIGH -}; -struct adaptive_sharpness { +enum sharpness_setting { + SHARPNESS_HW_OFF = 0, + SHARPNESS_ZERO, + SHARPNESS_CUSTOM +}; +struct spl_sharpness_range { + int sdr_rgb_min; + int sdr_rgb_max; + int sdr_rgb_mid; + int sdr_yuv_min; + int sdr_yuv_max; + int sdr_yuv_mid; + int hdr_rgb_min; + int hdr_rgb_max; + int hdr_rgb_mid; +}; +struct adaptive_sharpness { bool enable; - enum explicit_sharpness sharpness; + int sharpness_level; + struct spl_sharpness_range sharpness_range; }; enum linear_light_scaling { // convert it in translation logic LLS_PREF_DONT_CARE = 0, From 8d2bd99e7c69ead75b589f49ae5a3f9267eaacec Mon Sep 17 00:00:00 2001 From: Gabe Teeger Date: Fri, 23 Aug 2024 09:50:22 -0400 Subject: [PATCH 1435/1868] drm/amd/display: fix graphics hang in multi-display mst case [what] Graphics hang observed with 3 displays connected to DP2.0 mst dock. [why] There's a mismatch in dml and dc between the assignments of hpo link encoders. [how] Add a new array in dml that tracks the current mapping of HPO stream encoders to HPO link encoders in dc. Cc: stable@vger.kernel.org Reviewed-by: Sung joon Kim Reviewed-by: Nicholas Kazlauskas Signed-off-by: Gabe Teeger Signed-off-by: Hamza Mahfooz --- .../amd/display/dc/dml2/dml2_internal_types.h | 2 +- .../display/dc/dml2/dml2_translation_helper.c | 67 +++++++++---------- .../display/dc/dml2/dml2_translation_helper.h | 2 +- .../gpu/drm/amd/display/dc/dml2/dml2_utils.c | 12 +--- 4 files changed, 34 insertions(+), 49 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_internal_types.h b/drivers/gpu/drm/amd/display/dc/dml2/dml2_internal_types.h index 3ba184be25d38..140ec01545db8 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_internal_types.h +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_internal_types.h @@ -101,7 +101,7 @@ struct dml2_wrapper_scratch { struct dml2_dml_to_dc_pipe_mapping dml_to_dc_pipe_mapping; bool enable_flexible_pipe_mapping; bool plane_duplicate_exists; - unsigned int dp2_mst_stream_count; + int hpo_stream_to_link_encoder_mapping[MAX_HPO_DP2_ENCODERS]; }; struct dml2_helper_det_policy_scratch { diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c b/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c index 7e39873832bfc..bde4250853b10 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.c @@ -733,8 +733,7 @@ static void populate_dml_timing_cfg_from_stream_state(struct dml_timing_cfg_st * } static void populate_dml_output_cfg_from_stream_state(struct dml_output_cfg_st *out, unsigned int location, - const struct dc_stream_state *in, const struct pipe_ctx *pipe, - unsigned int dp2_mst_stream_count) + const struct dc_stream_state *in, const struct pipe_ctx *pipe, struct dml2_context *dml2) { unsigned int output_bpc; @@ -747,8 +746,8 @@ static void populate_dml_output_cfg_from_stream_state(struct dml_output_cfg_st * case SIGNAL_TYPE_DISPLAY_PORT_MST: case SIGNAL_TYPE_DISPLAY_PORT: out->OutputEncoder[location] = dml_dp; - if (is_dp2p0_output_encoder(pipe, dp2_mst_stream_count)) - out->OutputEncoder[location] = dml_dp2p0; + if (dml2->v20.scratch.hpo_stream_to_link_encoder_mapping[location] != -1) + out->OutputEncoder[dml2->v20.scratch.hpo_stream_to_link_encoder_mapping[location]] = dml_dp2p0; break; case SIGNAL_TYPE_EDP: out->OutputEncoder[location] = dml_edp; @@ -1199,36 +1198,6 @@ static void dml2_populate_pipe_to_plane_index_mapping(struct dml2_context *dml2, } } -static unsigned int calculate_dp2_mst_stream_count(struct dc_state *context) -{ - int i, j; - unsigned int dp2_mst_stream_count = 0; - - for (i = 0; i < context->stream_count; i++) { - struct dc_stream_state *stream = context->streams[i]; - - if (!stream || stream->signal != SIGNAL_TYPE_DISPLAY_PORT_MST) - continue; - - for (j = 0; j < MAX_PIPES; j++) { - struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; - - if (!pipe_ctx || !pipe_ctx->stream) - continue; - - if (stream != pipe_ctx->stream) - continue; - - if (pipe_ctx->stream_res.hpo_dp_stream_enc && pipe_ctx->link_res.hpo_dp_link_enc) { - dp2_mst_stream_count++; - break; - } - } - } - - return dp2_mst_stream_count; -} - static void populate_dml_writeback_cfg_from_stream_state(struct dml_writeback_cfg_st *out, unsigned int location, const struct dc_stream_state *in) { @@ -1269,6 +1238,30 @@ static void populate_dml_writeback_cfg_from_stream_state(struct dml_writeback_cf } } } + +static void dml2_map_hpo_stream_encoder_to_hpo_link_encoder_index(struct dml2_context *dml2, struct dc_state *context) +{ + int i; + struct pipe_ctx *current_pipe_context; + + /* Scratch gets reset to zero in dml, but link encoder instance can be zero, so reset to -1 */ + for (i = 0; i < MAX_HPO_DP2_ENCODERS; i++) { + dml2->v20.scratch.hpo_stream_to_link_encoder_mapping[i] = -1; + } + + /* If an HPO stream encoder is allocated to a pipe, get the instance of it's allocated HPO Link encoder */ + for (i = 0; i < MAX_PIPES; i++) { + current_pipe_context = &context->res_ctx.pipe_ctx[i]; + if (current_pipe_context->stream && + current_pipe_context->stream_res.hpo_dp_stream_enc && + current_pipe_context->link_res.hpo_dp_link_enc && + dc_is_dp_signal(current_pipe_context->stream->signal)) { + dml2->v20.scratch.hpo_stream_to_link_encoder_mapping[current_pipe_context->stream_res.hpo_dp_stream_enc->inst] = + current_pipe_context->link_res.hpo_dp_link_enc->inst; + } + } +} + void map_dc_state_into_dml_display_cfg(struct dml2_context *dml2, struct dc_state *context, struct dml_display_cfg_st *dml_dispcfg) { int i = 0, j = 0, k = 0; @@ -1291,8 +1284,8 @@ void map_dc_state_into_dml_display_cfg(struct dml2_context *dml2, struct dc_stat if (dml2->v20.dml_core_ctx.ip.hostvm_enable) dml2->v20.dml_core_ctx.policy.AllowForPStateChangeOrStutterInVBlankFinal = dml_prefetch_support_uclk_fclk_and_stutter; - dml2->v20.scratch.dp2_mst_stream_count = calculate_dp2_mst_stream_count(context); dml2_populate_pipe_to_plane_index_mapping(dml2, context); + dml2_map_hpo_stream_encoder_to_hpo_link_encoder_index(dml2, context); for (i = 0; i < context->stream_count; i++) { current_pipe_context = NULL; @@ -1313,7 +1306,7 @@ void map_dc_state_into_dml_display_cfg(struct dml2_context *dml2, struct dc_stat ASSERT(disp_cfg_stream_location >= 0 && disp_cfg_stream_location <= __DML2_WRAPPER_MAX_STREAMS_PLANES__); populate_dml_timing_cfg_from_stream_state(&dml_dispcfg->timing, disp_cfg_stream_location, context->streams[i]); - populate_dml_output_cfg_from_stream_state(&dml_dispcfg->output, disp_cfg_stream_location, context->streams[i], current_pipe_context, dml2->v20.scratch.dp2_mst_stream_count); + populate_dml_output_cfg_from_stream_state(&dml_dispcfg->output, disp_cfg_stream_location, context->streams[i], current_pipe_context, dml2); /*Call site for populate_dml_writeback_cfg_from_stream_state*/ populate_dml_writeback_cfg_from_stream_state(&dml_dispcfg->writeback, disp_cfg_stream_location, context->streams[i]); @@ -1378,7 +1371,7 @@ void map_dc_state_into_dml_display_cfg(struct dml2_context *dml2, struct dc_stat if (j >= 1) { populate_dml_timing_cfg_from_stream_state(&dml_dispcfg->timing, disp_cfg_plane_location, context->streams[i]); - populate_dml_output_cfg_from_stream_state(&dml_dispcfg->output, disp_cfg_plane_location, context->streams[i], current_pipe_context, dml2->v20.scratch.dp2_mst_stream_count); + populate_dml_output_cfg_from_stream_state(&dml_dispcfg->output, disp_cfg_plane_location, context->streams[i], current_pipe_context, dml2); switch (context->streams[i]->debug.force_odm_combine_segments) { case 2: dml2->v20.dml_core_ctx.policy.ODMUse[disp_cfg_plane_location] = dml_odm_use_policy_combine_2to1; diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.h b/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.h index 55659b22d87f7..d764773938f4e 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.h +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_translation_helper.h @@ -36,6 +36,6 @@ void dml2_translate_socbb_params(const struct dc *in_dc, struct soc_bounding_box void dml2_translate_soc_states(const struct dc *in_dc, struct soc_states_st *out, int num_states); void map_dc_state_into_dml_display_cfg(struct dml2_context *dml2, struct dc_state *context, struct dml_display_cfg_st *dml_dispcfg); void dml2_update_pipe_ctx_dchub_regs(struct _vcs_dpi_dml_display_rq_regs_st *rq_regs, struct _vcs_dpi_dml_display_dlg_regs_st *disp_dlg_regs, struct _vcs_dpi_dml_display_ttu_regs_st *disp_ttu_regs, struct pipe_ctx *out); -bool is_dp2p0_output_encoder(const struct pipe_ctx *pipe, unsigned int dp2_mst_stream_count); +bool is_dp2p0_output_encoder(const struct pipe_ctx *pipe); #endif //__DML2_TRANSLATION_HELPER_H__ diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_utils.c b/drivers/gpu/drm/amd/display/dc/dml2/dml2_utils.c index 9e8ff3a9718e7..9a33158b63bf8 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_utils.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_utils.c @@ -153,7 +153,7 @@ unsigned int dml2_util_get_maximum_odm_combine_for_output(bool force_odm_4to1, e } } -bool is_dp2p0_output_encoder(const struct pipe_ctx *pipe_ctx, unsigned int dp2_mst_stream_count) +bool is_dp2p0_output_encoder(const struct pipe_ctx *pipe_ctx) { if (pipe_ctx == NULL || pipe_ctx->stream == NULL) return false; @@ -161,14 +161,6 @@ bool is_dp2p0_output_encoder(const struct pipe_ctx *pipe_ctx, unsigned int dp2_m /* If this assert is hit then we have a link encoder dynamic management issue */ ASSERT(pipe_ctx->stream_res.hpo_dp_stream_enc ? pipe_ctx->link_res.hpo_dp_link_enc != NULL : true); - /* Count MST hubs once by treating only 1st remote sink in topology as an encoder */ - if (pipe_ctx->stream->link && pipe_ctx->stream->link->remote_sinks[0] && dp2_mst_stream_count > 1) { - return (pipe_ctx->stream_res.hpo_dp_stream_enc && - pipe_ctx->link_res.hpo_dp_link_enc && - dc_is_dp_signal(pipe_ctx->stream->signal) && - (pipe_ctx->stream->link->remote_sinks[0]->sink_id == pipe_ctx->stream->sink->sink_id)); - } - return (pipe_ctx->stream_res.hpo_dp_stream_enc && pipe_ctx->link_res.hpo_dp_link_enc && dc_is_dp_signal(pipe_ctx->stream->signal)); @@ -181,7 +173,7 @@ bool is_dtbclk_required(const struct dc *dc, struct dc_state *context) for (i = 0; i < dc->res_pool->pipe_count; i++) { if (!context->res_ctx.pipe_ctx[i].stream) continue; - if (is_dp2p0_output_encoder(&context->res_ctx.pipe_ctx[i], context->bw_ctx.dml2->v20.scratch.dp2_mst_stream_count)) + if (is_dp2p0_output_encoder(&context->res_ctx.pipe_ctx[i])) return true; } return false; From 7750f9b3a2ff1fa3895eac97f15627cc5e059c3b Mon Sep 17 00:00:00 2001 From: Dillon Varone Date: Thu, 22 Aug 2024 17:52:57 -0400 Subject: [PATCH 1436/1868] drm/amd/display: Block timing sync for different signals in PMO PMO assumes that like timings can be synchronized, but DC only allows this if the signal types match. Cc: stable@vger.kernel.org Reviewed-by: Austin Zheng Signed-off-by: Dillon Varone Signed-off-by: Hamza Mahfooz --- .../display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c index 3bb5eb2e79aec..d63558ee31351 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c @@ -941,7 +941,8 @@ static void build_synchronized_timing_groups( for (j = i + 1; j < display_config->display_config.num_streams; j++) { if (memcmp(master_timing, &display_config->display_config.stream_descriptors[j].timing, - sizeof(struct dml2_timing_cfg)) == 0) { + sizeof(struct dml2_timing_cfg)) == 0 && + display_config->display_config.stream_descriptors[i].output.output_encoder == display_config->display_config.stream_descriptors[j].output.output_encoder) { set_bit_in_bitfield(&pmo->scratch.pmo_dcn4.synchronized_timing_group_masks[timing_group_idx], j); set_bit_in_bitfield(&stream_mapped_mask, j); } From cc42b5b15d9d2f600d8b1821cd2dccde905e250e Mon Sep 17 00:00:00 2001 From: Hansen Dsouza Date: Wed, 14 Aug 2024 11:20:08 -0400 Subject: [PATCH 1437/1868] drm/amd/display: Fix flickering caused by dccg Always allow un-gating. Follow legacy workaround for repeated dppclk dto updates Reviewed-by: Muhammad Ahmed Signed-off-by: Hansen Dsouza Signed-off-by: Hamza Mahfooz --- .../amd/display/dc/dccg/dcn20/dcn20_dccg.h | 11 +++ .../amd/display/dc/dccg/dcn35/dcn35_dccg.c | 89 +++++++++++++------ .../amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 45 ---------- 3 files changed, 72 insertions(+), 73 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h b/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h index 6ac2bd86c4dbb..160c299419b72 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h @@ -328,6 +328,17 @@ type DPSTREAMCLK1_GATE_DISABLE;\ type DPSTREAMCLK2_GATE_DISABLE;\ type DPSTREAMCLK3_GATE_DISABLE;\ + type SYMCLKA_FE_GATE_DISABLE;\ + type SYMCLKB_FE_GATE_DISABLE;\ + type SYMCLKC_FE_GATE_DISABLE;\ + type SYMCLKD_FE_GATE_DISABLE;\ + type SYMCLKE_FE_GATE_DISABLE;\ + type SYMCLKA_GATE_DISABLE;\ + type SYMCLKB_GATE_DISABLE;\ + type SYMCLKC_GATE_DISABLE;\ + type SYMCLKD_GATE_DISABLE;\ + type SYMCLKE_GATE_DISABLE;\ + #define DCCG401_REG_FIELD_LIST(type) \ type OTG0_TMDS_PIXEL_RATE_DIV;\ diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c index 60a84de4c5d13..ee02b78e290f4 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c @@ -24,6 +24,7 @@ #include "reg_helper.h" #include "core_types.h" +#include "resource.h" #include "dcn35_dccg.h" #define TO_DCN_DCCG(dccg)\ @@ -136,7 +137,7 @@ static void dccg35_set_dsc_clk_rcg(struct dccg *dccg, int inst, bool enable) { struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); - if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dsc) + if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dsc && enable) return; switch (inst) { @@ -165,7 +166,7 @@ static void dccg35_set_symclk32_se_rcg( { struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); - if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) + if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se && enable) return; /* SYMCLK32_ROOT_SE#_GATE_DISABLE will clock gate in DCCG */ @@ -204,7 +205,7 @@ static void dccg35_set_symclk32_le_rcg( { struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); - if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le) + if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_le && enable) return; switch (inst) { @@ -231,7 +232,7 @@ static void dccg35_set_physymclk_rcg( { struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); - if (!dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) + if (!dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk && enable) return; switch (inst) { @@ -262,35 +263,45 @@ static void dccg35_set_physymclk_rcg( } static void dccg35_set_symclk_fe_rcg( - struct dccg *dccg, - int inst, - bool enable) + struct dccg *dccg, + int inst, + bool enable) { struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); - if (!dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) + if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk_fe && enable) return; switch (inst) { case 0: + REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, + SYMCLKA_FE_GATE_DISABLE, enable ? 0 : 1); REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, - SYMCLKA_FE_ROOT_GATE_DISABLE, enable ? 0 : 1); + SYMCLKA_FE_ROOT_GATE_DISABLE, enable ? 0 : 1); break; case 1: + REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, + SYMCLKB_FE_GATE_DISABLE, enable ? 0 : 1); REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, - SYMCLKB_FE_ROOT_GATE_DISABLE, enable ? 0 : 1); + SYMCLKB_FE_ROOT_GATE_DISABLE, enable ? 0 : 1); break; case 2: + REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, + SYMCLKC_FE_GATE_DISABLE, enable ? 0 : 1); REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, - SYMCLKC_FE_ROOT_GATE_DISABLE, enable ? 0 : 1); + SYMCLKC_FE_ROOT_GATE_DISABLE, enable ? 0 : 1); break; case 3: + REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, + SYMCLKD_FE_GATE_DISABLE, enable ? 0 : 1); REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, - SYMCLKD_FE_ROOT_GATE_DISABLE, enable ? 0 : 1); + SYMCLKD_FE_ROOT_GATE_DISABLE, enable ? 0 : 1); break; case 4: + REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, + SYMCLKE_FE_GATE_DISABLE, enable ? 0 : 1); REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, - SYMCLKE_FE_ROOT_GATE_DISABLE, enable ? 0 : 1); + SYMCLKE_FE_ROOT_GATE_DISABLE, enable ? 0 : 1); break; default: BREAK_TO_DEBUGGER(); @@ -307,27 +318,37 @@ static void dccg35_set_symclk_be_rcg( struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); /* TBD add symclk_be in rcg control bits */ - if (!dccg->ctx->dc->debug.root_clock_optimization.bits.physymclk) + if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk_fe && enable) return; switch (inst) { case 0: + REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, + SYMCLKA_GATE_DISABLE, enable ? 0 : 1); REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKA_ROOT_GATE_DISABLE, enable ? 0 : 1); break; case 1: + REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, + SYMCLKB_GATE_DISABLE, enable ? 0 : 1); REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKB_ROOT_GATE_DISABLE, enable ? 0 : 1); break; case 2: + REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, + SYMCLKC_GATE_DISABLE, enable ? 0 : 1); REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKC_ROOT_GATE_DISABLE, enable ? 0 : 1); break; case 3: + REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, + SYMCLKD_GATE_DISABLE, enable ? 0 : 1); REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKD_ROOT_GATE_DISABLE, enable ? 0 : 1); break; case 4: + REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, + SYMCLKE_GATE_DISABLE, enable ? 0 : 1); REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKE_ROOT_GATE_DISABLE, enable ? 0 : 1); break; @@ -342,7 +363,7 @@ static void dccg35_set_dtbclk_p_rcg(struct dccg *dccg, int inst, bool enable) struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); - if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dpp) + if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dpp && enable) return; switch (inst) { @@ -370,7 +391,7 @@ static void dccg35_set_dppclk_rcg(struct dccg *dccg, struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); - if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dpp) + if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dpp && enable) return; switch (inst) { @@ -399,7 +420,7 @@ static void dccg35_set_dpstreamclk_rcg( { struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); - if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream) + if (!dccg->ctx->dc->debug.root_clock_optimization.bits.dpstream && enable) return; switch (inst) { @@ -436,7 +457,7 @@ static void dccg35_set_smclk32_se_rcg( { struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); - if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) + if (!dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se && enable) return; switch (inst) { @@ -1693,6 +1714,12 @@ static void dccg35_disable_symclk32_se( } } +static void dccg35_init_cb(struct dccg *dccg) +{ + (void)dccg; + /* Any RCG should be done when driver enter low power mode*/ +} + void dccg35_init(struct dccg *dccg) { int otg_inst; @@ -2043,8 +2070,6 @@ static void dccg35_set_dpstreamclk_cb( enum dtbclk_source dtb_clk_src; enum dp_stream_clk_source dp_stream_clk_src; - ASSERT(otg_inst >= DP_STREAM_DTBCLK_P5); - switch (src) { case REFCLK: dtb_clk_src = DTBCLK_REFCLK; @@ -2099,6 +2124,13 @@ static void dccg35_update_dpp_dto_cb(struct dccg *dccg, int dpp_inst, { struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); + if (dccg->dpp_clock_gated[dpp_inst]) { + /* + * Do not update the DPPCLK DTO if the clock is stopped. + */ + return; + } + if (dccg->ref_dppclk && req_dppclk) { int ref_dppclk = dccg->ref_dppclk; int modulo, phase; @@ -2126,19 +2158,20 @@ static void dccg35_update_dpp_dto_cb(struct dccg *dccg, int dpp_inst, } static void dccg35_dpp_root_clock_control_cb( - struct dccg *dccg, - unsigned int dpp_inst, - bool power_on) + struct dccg *dccg, + unsigned int dpp_inst, + bool power_on) { + if (dccg->dpp_clock_gated[dpp_inst] == power_on) + return; /* power_on set indicates we need to ungate * Currently called from optimize_bandwidth and prepare_bandwidth calls * Since clock source is not passed restore to refclock on ungate * Redundant as gating when enabled is acheived through update_dpp_dto */ - if (power_on) - dccg35_enable_dpp_clk_new(dccg, dpp_inst, DPP_REFCLK); - else - dccg35_disable_dpp_clk_new(dccg, dpp_inst); + dccg35_set_dppclk_rcg(dccg, dpp_inst, !power_on); + + dccg->dpp_clock_gated[dpp_inst] = !power_on; } static void dccg35_enable_symclk32_se_cb( @@ -2322,7 +2355,7 @@ static const struct dccg_funcs dccg35_funcs_new = { .update_dpp_dto = dccg35_update_dpp_dto_cb, .dpp_root_clock_control = dccg35_dpp_root_clock_control_cb, .get_dccg_ref_freq = dccg31_get_dccg_ref_freq, - .dccg_init = dccg35_init, + .dccg_init = dccg35_init_cb, .set_dpstreamclk = dccg35_set_dpstreamclk_cb, .set_dpstreamclk_root_clock_gating = dccg35_set_dpstreamclk_root_clock_gating_cb, .enable_symclk32_se = dccg35_enable_symclk32_se_cb, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c index fbbb20b9dbee7..a4c6decee0f8a 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c @@ -147,37 +147,6 @@ void dcn35_init_hw(struct dc *dc) hws->funcs.bios_golden_init(dc); } - if (!dc->debug.disable_clock_gate) { - REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); - REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0); - - /* Disable gating for PHYASYMCLK. This will be enabled in dccg if needed */ - REG_UPDATE_5(DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_ROOT_GATE_DISABLE, 1, - PHYBSYMCLK_ROOT_GATE_DISABLE, 1, - PHYCSYMCLK_ROOT_GATE_DISABLE, 1, - PHYDSYMCLK_ROOT_GATE_DISABLE, 1, - PHYESYMCLK_ROOT_GATE_DISABLE, 1); - - REG_UPDATE_4(DCCG_GATE_DISABLE_CNTL4, - DPIASYMCLK0_GATE_DISABLE, 0, - DPIASYMCLK1_GATE_DISABLE, 0, - DPIASYMCLK2_GATE_DISABLE, 0, - DPIASYMCLK3_GATE_DISABLE, 0); - - REG_WRITE(DCCG_GATE_DISABLE_CNTL5, 0xFFFFFFFF); - REG_UPDATE_4(DCCG_GATE_DISABLE_CNTL5, - DTBCLK_P0_GATE_DISABLE, 0, - DTBCLK_P1_GATE_DISABLE, 0, - DTBCLK_P2_GATE_DISABLE, 0, - DTBCLK_P3_GATE_DISABLE, 0); - REG_UPDATE_4(DCCG_GATE_DISABLE_CNTL5, - DPSTREAMCLK0_GATE_DISABLE, 0, - DPSTREAMCLK1_GATE_DISABLE, 0, - DPSTREAMCLK2_GATE_DISABLE, 0, - DPSTREAMCLK3_GATE_DISABLE, 0); - - } - // Initialize the dccg if (res_pool->dccg->funcs->dccg_init) res_pool->dccg->funcs->dccg_init(res_pool->dccg); @@ -305,20 +274,6 @@ void dcn35_init_hw(struct dc *dc) if (!dc->debug.disable_clock_gate) { /* enable all DCN clock gating */ - REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0); - - REG_UPDATE_5(DCCG_GATE_DISABLE_CNTL2, SYMCLKA_FE_GATE_DISABLE, 0, - SYMCLKB_FE_GATE_DISABLE, 0, - SYMCLKC_FE_GATE_DISABLE, 0, - SYMCLKD_FE_GATE_DISABLE, 0, - SYMCLKE_FE_GATE_DISABLE, 0); - REG_UPDATE(DCCG_GATE_DISABLE_CNTL2, HDMICHARCLK0_GATE_DISABLE, 0); - REG_UPDATE_5(DCCG_GATE_DISABLE_CNTL2, SYMCLKA_GATE_DISABLE, 0, - SYMCLKB_GATE_DISABLE, 0, - SYMCLKC_GATE_DISABLE, 0, - SYMCLKD_GATE_DISABLE, 0, - SYMCLKE_GATE_DISABLE, 0); - REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0); } From 23154d1b77ddf50dc245fde6523e83f745953fd6 Mon Sep 17 00:00:00 2001 From: Aric Cyr Date: Sun, 25 Aug 2024 19:40:51 -0400 Subject: [PATCH 1438/1868] drm/amd/display: 3.2.299 This version brings along the following: - DCN35 fixes - DML2 fixes - IPS fixes - ODM fixes - Miscellaneous cleanups - MST fixes - SPL fixes Acked-by: Aurabindo Pillai Signed-off-by: Aric Cyr Signed-off-by: Hamza Mahfooz --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 22f0d64148751..7542b0b1c3217 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -55,7 +55,7 @@ struct aux_payload; struct set_config_cmd_payload; struct dmub_notification; -#define DC_VER "3.2.298" +#define DC_VER "3.2.299" #define MAX_SURFACES 3 #define MAX_PLANES 6 diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index f5dda1d69ae04..e20c220aa8b4c 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -111,7 +111,7 @@ #define DMUB_MAX_PHANTOM_PLANES ((DMUB_MAX_PLANES) / 2) /* Trace buffer offset for entry */ -#define TRACE_BUFFER_ENTRY_OFFSET 16 +#define TRACE_BUFFER_ENTRY_OFFSET 16 /** * Maximum number of dirty rects supported by FW. From 54395d61f075d92e0c44d0ea85949c980e9bcb5c Mon Sep 17 00:00:00 2001 From: Prike Liang Date: Fri, 14 Jun 2024 21:25:44 +0800 Subject: [PATCH 1439/1868] drm/amdgpu/gfx11: fallback to driver reset compute queue directly (v2) Since the MES FW resets kernel compute queue always failed, this may caused by the KIQ failed to process unmap KCQ. So, before MES FW work properly that will fallback to driver executes dequeue and resets SPI directly. Besides, rework the ring reset function and make the busy ring type reset in each function respectively. Acked-by: Vitaly Prosyak Signed-off-by: Prike Liang Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 84 ++++++++++++++++++++++---- 1 file changed, 71 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index 986cd5a3d5606..b923b70b2abd5 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -3984,13 +3984,13 @@ static int gfx_v11_0_gfx_mqd_init(struct amdgpu_device *adev, void *m, return 0; } -static int gfx_v11_0_gfx_init_queue(struct amdgpu_ring *ring) +static int gfx_v11_0_gfx_init_queue(struct amdgpu_ring *ring, bool reset) { struct amdgpu_device *adev = ring->adev; struct v11_gfx_mqd *mqd = ring->mqd_ptr; int mqd_idx = ring - &adev->gfx.gfx_ring[0]; - if (!amdgpu_in_reset(adev) && !adev->in_suspend) { + if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) { memset((void *)mqd, 0, sizeof(*mqd)); mutex_lock(&adev->srbm_mutex); soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); @@ -4026,7 +4026,7 @@ static int gfx_v11_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); if (!r) { - r = gfx_v11_0_gfx_init_queue(ring); + r = gfx_v11_0_gfx_init_queue(ring, false); amdgpu_bo_kunmap(ring->mqd_obj); ring->mqd_ptr = NULL; } @@ -4321,13 +4321,13 @@ static int gfx_v11_0_kiq_init_queue(struct amdgpu_ring *ring) return 0; } -static int gfx_v11_0_kcq_init_queue(struct amdgpu_ring *ring) +static int gfx_v11_0_kcq_init_queue(struct amdgpu_ring *ring, bool reset) { struct amdgpu_device *adev = ring->adev; struct v11_compute_mqd *mqd = ring->mqd_ptr; int mqd_idx = ring - &adev->gfx.compute_ring[0]; - if (!amdgpu_in_reset(adev) && !adev->in_suspend) { + if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) { memset((void *)mqd, 0, sizeof(*mqd)); mutex_lock(&adev->srbm_mutex); soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); @@ -4391,7 +4391,7 @@ static int gfx_v11_0_kcq_resume(struct amdgpu_device *adev) goto done; r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); if (!r) { - r = gfx_v11_0_kcq_init_queue(ring); + r = gfx_v11_0_kcq_init_queue(ring, false); amdgpu_bo_kunmap(ring->mqd_obj); ring->mqd_ptr = NULL; } @@ -6544,18 +6544,76 @@ static void gfx_v11_0_emit_mem_sync(struct amdgpu_ring *ring) amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ } -static int gfx_v11_0_reset_ring(struct amdgpu_ring *ring, unsigned int vmid) +static int gfx_v11_0_reset_kgq(struct amdgpu_ring *ring, unsigned int vmid) { + struct amdgpu_device *adev = ring->adev; int r; r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid); if (r) return r; - /* reset the ring */ - ring->wptr = 0; - *ring->wptr_cpu_addr = 0; - amdgpu_ring_clear_ring(ring); + r = amdgpu_bo_reserve(ring->mqd_obj, false); + if (unlikely(r != 0)) { + dev_err(adev->dev, "fail to resv mqd_obj\n"); + return r; + } + r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); + if (!r) { + r = gfx_v11_0_gfx_init_queue(ring, true); + amdgpu_bo_kunmap(ring->mqd_obj); + ring->mqd_ptr = NULL; + } + amdgpu_bo_unreserve(ring->mqd_obj); + if (r) { + dev_err(adev->dev, "fail to unresv mqd_obj\n"); + return r; + } + + r = amdgpu_mes_map_legacy_queue(adev, ring); + if (r) { + dev_err(adev->dev, "failed to remap kgq\n"); + return r; + } + + return amdgpu_ring_test_ring(ring); +} + +static int gfx_v11_0_reset_kcq(struct amdgpu_ring *ring, unsigned int vmid) +{ + struct amdgpu_device *adev = ring->adev; + int r; + + gfx_v11_0_set_safe_mode(adev, 0); + mutex_lock(&adev->srbm_mutex); + soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); + WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2); + WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1); + soc21_grbm_select(adev, 0, 0, 0, 0); + mutex_unlock(&adev->srbm_mutex); + gfx_v11_0_unset_safe_mode(adev, 0); + + r = amdgpu_bo_reserve(ring->mqd_obj, false); + if (unlikely(r != 0)) { + dev_err(adev->dev, "fail to resv mqd_obj\n"); + return r; + } + r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); + if (!r) { + r = gfx_v11_0_kcq_init_queue(ring, true); + amdgpu_bo_kunmap(ring->mqd_obj); + ring->mqd_ptr = NULL; + } + amdgpu_bo_unreserve(ring->mqd_obj); + if (r) { + dev_err(adev->dev, "fail to unresv mqd_obj\n"); + return r; + } + r = amdgpu_mes_map_legacy_queue(adev, ring); + if (r) { + dev_err(adev->dev, "failed to remap kcq\n"); + return r; + } return amdgpu_ring_test_ring(ring); } @@ -6761,7 +6819,7 @@ static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_gfx = { .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait, .soft_recovery = gfx_v11_0_ring_soft_recovery, .emit_mem_sync = gfx_v11_0_emit_mem_sync, - .reset = gfx_v11_0_reset_ring, + .reset = gfx_v11_0_reset_kgq, }; static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_compute = { @@ -6799,7 +6857,7 @@ static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_compute = { .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait, .soft_recovery = gfx_v11_0_ring_soft_recovery, .emit_mem_sync = gfx_v11_0_emit_mem_sync, - .reset = gfx_v11_0_reset_ring, + .reset = gfx_v11_0_reset_kcq, }; static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_kiq = { From 5642954462d95f1f838dd053a8c2af93cb5240d3 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 1 Jul 2024 18:04:40 -0400 Subject: [PATCH 1440/1868] drm/amdgpu/gfx11: rename gfx_v11_0_gfx_init_queue() Rename to gfx_v11_0_kgq_init_queue() to better align with the other naming in the file. Acked-by: Vitaly Prosyak Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index b923b70b2abd5..561edfcc84047 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -3984,7 +3984,7 @@ static int gfx_v11_0_gfx_mqd_init(struct amdgpu_device *adev, void *m, return 0; } -static int gfx_v11_0_gfx_init_queue(struct amdgpu_ring *ring, bool reset) +static int gfx_v11_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset) { struct amdgpu_device *adev = ring->adev; struct v11_gfx_mqd *mqd = ring->mqd_ptr; @@ -4026,7 +4026,7 @@ static int gfx_v11_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); if (!r) { - r = gfx_v11_0_gfx_init_queue(ring, false); + r = gfx_v11_0_kgq_init_queue(ring, false); amdgpu_bo_kunmap(ring->mqd_obj); ring->mqd_ptr = NULL; } @@ -6560,7 +6560,7 @@ static int gfx_v11_0_reset_kgq(struct amdgpu_ring *ring, unsigned int vmid) } r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); if (!r) { - r = gfx_v11_0_gfx_init_queue(ring, true); + r = gfx_v11_0_kgq_init_queue(ring, true); amdgpu_bo_kunmap(ring->mqd_obj); ring->mqd_ptr = NULL; } From ec4de4f9ad44c256a7b7e5b23c3d39c5c7c0ce46 Mon Sep 17 00:00:00 2001 From: Jiadong Zhu Date: Tue, 2 Jul 2024 10:01:21 +0800 Subject: [PATCH 1441/1868] drm/amdgpu/gfx11: wait for reset done before remap There is a racing condition that cp firmware modifies MQD in reset sequence after driver updates it for remapping. We have to wait till CP_HQD_ACTIVE becoming false then remap the queue. Acked-by: Vitaly Prosyak Signed-off-by: Jiadong Zhu Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index 561edfcc84047..2f5eed56892d1 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -6582,16 +6582,29 @@ static int gfx_v11_0_reset_kgq(struct amdgpu_ring *ring, unsigned int vmid) static int gfx_v11_0_reset_kcq(struct amdgpu_ring *ring, unsigned int vmid) { struct amdgpu_device *adev = ring->adev; - int r; + int i, r = 0; gfx_v11_0_set_safe_mode(adev, 0); mutex_lock(&adev->srbm_mutex); soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2); WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1); + + /* make sure dequeue is complete*/ + for (i = 0; i < adev->usec_timeout; i++) { + if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) + break; + udelay(1); + } + if (i >= adev->usec_timeout) + r = -ETIMEDOUT; soc21_grbm_select(adev, 0, 0, 0, 0); mutex_unlock(&adev->srbm_mutex); gfx_v11_0_unset_safe_mode(adev, 0); + if (r) { + dev_err(adev->dev, "fail to wait on hqd deactivate\n"); + return r; + } r = amdgpu_bo_reserve(ring->mqd_obj, false); if (unlikely(r != 0)) { From b5987cd4d3bf3e970a0da964fa04d8926eccd7e6 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 24 May 2024 12:37:50 -0400 Subject: [PATCH 1442/1868] drm/amdgpu/gfx10: add ring reset callbacks Add ring reset callbacks for gfx and compute. v2: fix gfx handling v3: wait for KIQ to complete Acked-by: Vitaly Prosyak Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 91 ++++++++++++++++++++++++++ 1 file changed, 91 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 56ad3f9bce0ad..556fb72b303fb 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -9522,6 +9522,95 @@ static void gfx_v10_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop) amdgpu_ring_write(ring, ring->funcs->nop); } +static int gfx_v10_0_reset_kgq(struct amdgpu_ring *ring, unsigned int vmid) +{ + struct amdgpu_device *adev = ring->adev; + struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; + struct amdgpu_ring *kiq_ring = &kiq->ring; + unsigned long flags; + u32 tmp; + u64 addr; + int r; + + if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) + return -EINVAL; + + spin_lock_irqsave(&kiq->ring_lock, flags); + + if (amdgpu_ring_alloc(kiq_ring, 5 + 7 + 7 + kiq->pmf->map_queues_size)) { + spin_unlock_irqrestore(&kiq->ring_lock, flags); + return -ENOMEM; + } + + addr = amdgpu_bo_gpu_offset(ring->mqd_obj) + + offsetof(struct v10_gfx_mqd, cp_gfx_hqd_active); + tmp = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid); + if (ring->pipe == 0) + tmp = REG_SET_FIELD(tmp, CP_VMID_RESET, PIPE0_QUEUES, 1 << ring->queue); + else + tmp = REG_SET_FIELD(tmp, CP_VMID_RESET, PIPE1_QUEUES, 1 << ring->queue); + + gfx_v10_0_ring_emit_wreg(kiq_ring, + SOC15_REG_OFFSET(GC, 0, mmCP_VMID_RESET), tmp); + gfx_v10_0_wait_reg_mem(kiq_ring, 0, 1, 0, + lower_32_bits(addr), upper_32_bits(addr), + 0, 1, 0x20); + gfx_v10_0_ring_emit_reg_wait(kiq_ring, + SOC15_REG_OFFSET(GC, 0, mmCP_VMID_RESET), 0, 0xffffffff); + kiq->pmf->kiq_map_queues(kiq_ring, ring); + amdgpu_ring_commit(kiq_ring); + + spin_unlock_irqrestore(&kiq->ring_lock, flags); + + r = amdgpu_ring_test_ring(kiq_ring); + if (r) + return r; + + /* reset the ring */ + ring->wptr = 0; + *ring->wptr_cpu_addr = 0; + amdgpu_ring_clear_ring(ring); + + return amdgpu_ring_test_ring(ring); +} + +static int gfx_v10_0_reset_kcq(struct amdgpu_ring *ring, + unsigned int vmid) +{ + struct amdgpu_device *adev = ring->adev; + struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; + struct amdgpu_ring *kiq_ring = &kiq->ring; + unsigned long flags; + int r; + + if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) + return -EINVAL; + + spin_lock_irqsave(&kiq->ring_lock, flags); + + if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { + spin_unlock_irqrestore(&kiq->ring_lock, flags); + return -ENOMEM; + } + + kiq->pmf->kiq_unmap_queues(kiq_ring, ring, RESET_QUEUES, + 0, 0); + amdgpu_ring_commit(kiq_ring); + + spin_unlock_irqrestore(&kiq->ring_lock, flags); + + r = amdgpu_ring_test_ring(kiq_ring); + if (r) + return r; + + /* reset the ring */ + ring->wptr = 0; + *ring->wptr_cpu_addr = 0; + amdgpu_ring_clear_ring(ring); + + return amdgpu_ring_test_ring(ring); +} + static void gfx_v10_ip_print(void *handle, struct drm_printer *p) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; @@ -9751,6 +9840,7 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = { .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, .soft_recovery = gfx_v10_0_ring_soft_recovery, .emit_mem_sync = gfx_v10_0_emit_mem_sync, + .reset = gfx_v10_0_reset_kgq, }; static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = { @@ -9787,6 +9877,7 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = { .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, .soft_recovery = gfx_v10_0_ring_soft_recovery, .emit_mem_sync = gfx_v10_0_emit_mem_sync, + .reset = gfx_v10_0_reset_kcq, }; static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = { From 3a533a9c274fcd29d484e096bc8f0e84a226682c Mon Sep 17 00:00:00 2001 From: Jiadong Zhu Date: Fri, 14 Jun 2024 13:46:36 +0800 Subject: [PATCH 1443/1868] drm/amdgpu/gfx10: remap queue after reset successfully Kiq command unmap_queues only does the dequeueing action. We have to map the queue back with clean mqd. v2: fix up error handling (Alex) Acked-by: Vitaly Prosyak Signed-off-by: Jiadong Zhu Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 46 ++++++++++++++++++++------ 1 file changed, 35 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 556fb72b303fb..30003bf6721ca 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -7037,13 +7037,13 @@ static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring) return 0; } -static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring) +static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring, bool restore) { struct amdgpu_device *adev = ring->adev; struct v10_compute_mqd *mqd = ring->mqd_ptr; int mqd_idx = ring - &adev->gfx.compute_ring[0]; - if (!amdgpu_in_reset(adev) && !adev->in_suspend) { + if (!restore && !amdgpu_in_reset(adev) && !adev->in_suspend) { memset((void *)mqd, 0, sizeof(*mqd)); mutex_lock(&adev->srbm_mutex); nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); @@ -7105,7 +7105,7 @@ static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev) goto done; r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); if (!r) { - r = gfx_v10_0_kcq_init_queue(ring); + r = gfx_v10_0_kcq_init_queue(ring, false); amdgpu_bo_kunmap(ring->mqd_obj); ring->mqd_ptr = NULL; } @@ -9589,25 +9589,49 @@ static int gfx_v10_0_reset_kcq(struct amdgpu_ring *ring, spin_lock_irqsave(&kiq->ring_lock, flags); if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { - spin_unlock_irqrestore(&kiq->ring_lock, flags); - return -ENOMEM; + r = -ENOMEM; + goto out; } kiq->pmf->kiq_unmap_queues(kiq_ring, ring, RESET_QUEUES, 0, 0); amdgpu_ring_commit(kiq_ring); - spin_unlock_irqrestore(&kiq->ring_lock, flags); + r = amdgpu_ring_test_ring(kiq_ring); + if (r) + goto out; + + r = amdgpu_bo_reserve(ring->mqd_obj, false); + if (unlikely(r != 0)) { + dev_err(adev->dev, "fail to resv mqd_obj\n"); + goto out; + } + r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); + if (!r) { + r = gfx_v10_0_kcq_init_queue(ring, true); + amdgpu_bo_kunmap(ring->mqd_obj); + ring->mqd_ptr = NULL; + } + amdgpu_bo_unreserve(ring->mqd_obj); + if (r) { + dev_err(adev->dev, "fail to unresv mqd_obj\n"); + goto out; + } + + if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size)) { + r = -ENOMEM; + goto out; + } + kiq->pmf->kiq_map_queues(kiq_ring, ring); + amdgpu_ring_commit(kiq_ring); r = amdgpu_ring_test_ring(kiq_ring); + +out: + spin_unlock_irqrestore(&kiq->ring_lock, flags); if (r) return r; - /* reset the ring */ - ring->wptr = 0; - *ring->wptr_cpu_addr = 0; - amdgpu_ring_clear_ring(ring); - return amdgpu_ring_test_ring(ring); } From c177a7e339b04e878668e70550b905775fdf95a7 Mon Sep 17 00:00:00 2001 From: Jiadong Zhu Date: Tue, 2 Jul 2024 09:17:14 +0800 Subject: [PATCH 1444/1868] drm/amdgpu/gfx10: wait for reset done before remap There is a racing condition that cp firmware modifies MQD in reset sequence after driver updates it for remapping. We have to wait till CP_HQD_ACTIVE becoming false then remap the queue. v2: fix KIQ locking (Alex) v3: fix KIQ locking harder (Jessie) Acked-by: Vitaly Prosyak Signed-off-by: Jiadong Zhu Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 41 +++++++++++++++++++------- 1 file changed, 30 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 30003bf6721ca..7433ffaa05fa6 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -9581,7 +9581,7 @@ static int gfx_v10_0_reset_kcq(struct amdgpu_ring *ring, struct amdgpu_kiq *kiq = &adev->gfx.kiq[0]; struct amdgpu_ring *kiq_ring = &kiq->ring; unsigned long flags; - int r; + int i, r; if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) return -EINVAL; @@ -9589,22 +9589,42 @@ static int gfx_v10_0_reset_kcq(struct amdgpu_ring *ring, spin_lock_irqsave(&kiq->ring_lock, flags); if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) { - r = -ENOMEM; - goto out; + spin_unlock_irqrestore(&kiq->ring_lock, flags); + return -ENOMEM; } kiq->pmf->kiq_unmap_queues(kiq_ring, ring, RESET_QUEUES, 0, 0); amdgpu_ring_commit(kiq_ring); + spin_unlock_irqrestore(&kiq->ring_lock, flags); r = amdgpu_ring_test_ring(kiq_ring); if (r) - goto out; + return r; + + /* make sure dequeue is complete*/ + gfx_v10_0_set_safe_mode(adev, 0); + mutex_lock(&adev->srbm_mutex); + nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); + for (i = 0; i < adev->usec_timeout; i++) { + if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) + break; + udelay(1); + } + if (i >= adev->usec_timeout) + r = -ETIMEDOUT; + nv_grbm_select(adev, 0, 0, 0, 0); + mutex_unlock(&adev->srbm_mutex); + gfx_v10_0_unset_safe_mode(adev, 0); + if (r) { + dev_err(adev->dev, "fail to wait on hqd deactivate\n"); + return r; + } r = amdgpu_bo_reserve(ring->mqd_obj, false); if (unlikely(r != 0)) { dev_err(adev->dev, "fail to resv mqd_obj\n"); - goto out; + return r; } r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); if (!r) { @@ -9615,20 +9635,19 @@ static int gfx_v10_0_reset_kcq(struct amdgpu_ring *ring, amdgpu_bo_unreserve(ring->mqd_obj); if (r) { dev_err(adev->dev, "fail to unresv mqd_obj\n"); - goto out; + return r; } + spin_lock_irqsave(&kiq->ring_lock, flags); if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size)) { - r = -ENOMEM; - goto out; + spin_unlock_irqrestore(&kiq->ring_lock, flags); + return -ENOMEM; } kiq->pmf->kiq_map_queues(kiq_ring, ring); amdgpu_ring_commit(kiq_ring); + spin_unlock_irqrestore(&kiq->ring_lock, flags); r = amdgpu_ring_test_ring(kiq_ring); - -out: - spin_unlock_irqrestore(&kiq->ring_lock, flags); if (r) return r; From 9df9f0421a22c68123f87a450841ea5ef3e86d00 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 1 Jul 2024 18:14:14 -0400 Subject: [PATCH 1445/1868] drm/amdgpu/gfx10: rework reset sequence To match other GFX IPs. Acked-by: Vitaly Prosyak Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 26 +++++++++++++++++++------- 1 file changed, 19 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 7433ffaa05fa6..d76535e2a938a 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -6699,13 +6699,13 @@ static int gfx_v10_0_gfx_mqd_init(struct amdgpu_device *adev, void *m, return 0; } -static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring) +static int gfx_v10_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset) { struct amdgpu_device *adev = ring->adev; struct v10_gfx_mqd *mqd = ring->mqd_ptr; int mqd_idx = ring - &adev->gfx.gfx_ring[0]; - if (!amdgpu_in_reset(adev) && !adev->in_suspend) { + if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) { memset((void *)mqd, 0, sizeof(*mqd)); mutex_lock(&adev->srbm_mutex); nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); @@ -6757,7 +6757,7 @@ static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); if (!r) { - r = gfx_v10_0_gfx_init_queue(ring); + r = gfx_v10_0_kgq_init_queue(ring, false); amdgpu_bo_kunmap(ring->mqd_obj); ring->mqd_ptr = NULL; } @@ -9566,10 +9566,22 @@ static int gfx_v10_0_reset_kgq(struct amdgpu_ring *ring, unsigned int vmid) if (r) return r; - /* reset the ring */ - ring->wptr = 0; - *ring->wptr_cpu_addr = 0; - amdgpu_ring_clear_ring(ring); + r = amdgpu_bo_reserve(ring->mqd_obj, false); + if (unlikely(r != 0)) { + DRM_ERROR("fail to resv mqd_obj\n"); + return r; + } + r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); + if (!r) { + r = gfx_v10_0_kgq_init_queue(ring, true); + amdgpu_bo_kunmap(ring->mqd_obj); + ring->mqd_ptr = NULL; + } + amdgpu_bo_unreserve(ring->mqd_obj); + if (r) { + DRM_ERROR("fail to unresv mqd_obj\n"); + return r; + } return amdgpu_ring_test_ring(ring); } From 6870505e2a6d22a3450382a5c81f1c02b921511f Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 3 Jun 2024 17:07:56 -0400 Subject: [PATCH 1446/1868] drm/amdgpu/gfx12: add ring reset callbacks Add ring reset callbacks for gfx and compute. Acked-by: Vitaly Prosyak Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c index 6f700800f346b..335b5f01c6e80 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c @@ -5158,6 +5158,22 @@ static void gfx_v12_ip_dump(void *handle) amdgpu_gfx_off_ctrl(adev, true); } +static int gfx_v12_0_reset_ring(struct amdgpu_ring *ring, unsigned int vmid) +{ + int r; + + r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid); + if (r) + return r; + + /* reset the ring */ + ring->wptr = 0; + *ring->wptr_cpu_addr = 0; + amdgpu_ring_clear_ring(ring); + + return amdgpu_ring_test_ring(ring); +} + static const struct amd_ip_funcs gfx_v12_0_ip_funcs = { .name = "gfx_v12_0", .early_init = gfx_v12_0_early_init, @@ -5220,6 +5236,7 @@ static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_gfx = { .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait, .soft_recovery = gfx_v12_0_ring_soft_recovery, .emit_mem_sync = gfx_v12_0_emit_mem_sync, + .reset = gfx_v12_0_reset_ring, }; static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_compute = { @@ -5254,6 +5271,7 @@ static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_compute = { .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait, .soft_recovery = gfx_v12_0_ring_soft_recovery, .emit_mem_sync = gfx_v12_0_emit_mem_sync, + .reset = gfx_v12_0_reset_ring, }; static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_kiq = { From bb036d05233feff7ec62424bfbd64c539781ff92 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 1 Jul 2024 18:22:24 -0400 Subject: [PATCH 1447/1868] drm/amdgpu/gfx12: fallback to driver reset compute queue directly Since the MES FW resets kernel compute queue always failed, this may caused by the KIQ failed to process unmap KCQ. So, before MES FW work properly that will fallback to driver executes dequeue and resets SPI directly. Besides, rework the ring reset function and make the busy ring type reset in each function respectively. Acked-by: Vitaly Prosyak Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 93 ++++++++++++++++++++++---- 1 file changed, 79 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c index 335b5f01c6e80..b207de46a29b5 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c @@ -2916,13 +2916,13 @@ static int gfx_v12_0_gfx_mqd_init(struct amdgpu_device *adev, void *m, return 0; } -static int gfx_v12_0_gfx_init_queue(struct amdgpu_ring *ring) +static int gfx_v12_0_kgq_init_queue(struct amdgpu_ring *ring, bool reset) { struct amdgpu_device *adev = ring->adev; struct v12_gfx_mqd *mqd = ring->mqd_ptr; int mqd_idx = ring - &adev->gfx.gfx_ring[0]; - if (!amdgpu_in_reset(adev) && !adev->in_suspend) { + if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) { memset((void *)mqd, 0, sizeof(*mqd)); mutex_lock(&adev->srbm_mutex); soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); @@ -2958,7 +2958,7 @@ static int gfx_v12_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev) r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); if (!r) { - r = gfx_v12_0_gfx_init_queue(ring); + r = gfx_v12_0_kgq_init_queue(ring, false); amdgpu_bo_kunmap(ring->mqd_obj); ring->mqd_ptr = NULL; } @@ -3262,13 +3262,13 @@ static int gfx_v12_0_kiq_init_queue(struct amdgpu_ring *ring) return 0; } -static int gfx_v12_0_kcq_init_queue(struct amdgpu_ring *ring) +static int gfx_v12_0_kcq_init_queue(struct amdgpu_ring *ring, bool reset) { struct amdgpu_device *adev = ring->adev; struct v12_compute_mqd *mqd = ring->mqd_ptr; int mqd_idx = ring - &adev->gfx.compute_ring[0]; - if (!amdgpu_in_reset(adev) && !adev->in_suspend) { + if (!reset && !amdgpu_in_reset(adev) && !adev->in_suspend) { memset((void *)mqd, 0, sizeof(*mqd)); mutex_lock(&adev->srbm_mutex); soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); @@ -3332,7 +3332,7 @@ static int gfx_v12_0_kcq_resume(struct amdgpu_device *adev) goto done; r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); if (!r) { - r = gfx_v12_0_kcq_init_queue(ring); + r = gfx_v12_0_kcq_init_queue(ring, false); amdgpu_bo_kunmap(ring->mqd_obj); ring->mqd_ptr = NULL; } @@ -5158,18 +5158,83 @@ static void gfx_v12_ip_dump(void *handle) amdgpu_gfx_off_ctrl(adev, true); } -static int gfx_v12_0_reset_ring(struct amdgpu_ring *ring, unsigned int vmid) +static int gfx_v12_0_reset_kgq(struct amdgpu_ring *ring, unsigned int vmid) { + struct amdgpu_device *adev = ring->adev; int r; r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid); - if (r) + if (r) { + dev_err(adev->dev, "reset via MES failed %d\n", r); return r; + } - /* reset the ring */ - ring->wptr = 0; - *ring->wptr_cpu_addr = 0; - amdgpu_ring_clear_ring(ring); + r = amdgpu_bo_reserve(ring->mqd_obj, false); + if (unlikely(r != 0)) { + dev_err(adev->dev, "fail to resv mqd_obj\n"); + return r; + } + r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); + if (!r) { + r = gfx_v12_0_kgq_init_queue(ring, true); + amdgpu_bo_kunmap(ring->mqd_obj); + ring->mqd_ptr = NULL; + } + amdgpu_bo_unreserve(ring->mqd_obj); + if (r) { + DRM_ERROR("fail to unresv mqd_obj\n"); + return r; + } + + r = amdgpu_mes_map_legacy_queue(adev, ring); + if (r) { + dev_err(adev->dev, "failed to remap kgq\n"); + return r; + } + + return amdgpu_ring_test_ring(ring); +} + +static int gfx_v12_0_reset_kcq(struct amdgpu_ring *ring, unsigned int vmid) +{ + struct amdgpu_device *adev = ring->adev; + int r, i; + + gfx_v12_0_set_safe_mode(adev, 0); + mutex_lock(&adev->srbm_mutex); + soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); + WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2); + WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1); + for (i = 0; i < adev->usec_timeout; i++) { + if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) + break; + udelay(1); + } + soc24_grbm_select(adev, 0, 0, 0, 0); + mutex_unlock(&adev->srbm_mutex); + gfx_v12_0_unset_safe_mode(adev, 0); + + r = amdgpu_bo_reserve(ring->mqd_obj, false); + if (unlikely(r != 0)) { + DRM_ERROR("fail to resv mqd_obj\n"); + return r; + } + r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); + if (!r) { + r = gfx_v12_0_kcq_init_queue(ring, true); + amdgpu_bo_kunmap(ring->mqd_obj); + ring->mqd_ptr = NULL; + } + amdgpu_bo_unreserve(ring->mqd_obj); + if (r) { + DRM_ERROR("fail to unresv mqd_obj\n"); + return r; + } + r = amdgpu_mes_map_legacy_queue(adev, ring); + if (r) { + dev_err(adev->dev, "failed to remap kcq\n"); + return r; + } return amdgpu_ring_test_ring(ring); } @@ -5236,7 +5301,7 @@ static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_gfx = { .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait, .soft_recovery = gfx_v12_0_ring_soft_recovery, .emit_mem_sync = gfx_v12_0_emit_mem_sync, - .reset = gfx_v12_0_reset_ring, + .reset = gfx_v12_0_reset_kgq, }; static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_compute = { @@ -5271,7 +5336,7 @@ static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_compute = { .emit_reg_write_reg_wait = gfx_v12_0_ring_emit_reg_write_reg_wait, .soft_recovery = gfx_v12_0_ring_soft_recovery, .emit_mem_sync = gfx_v12_0_emit_mem_sync, - .reset = gfx_v12_0_reset_ring, + .reset = gfx_v12_0_reset_kcq, }; static const struct amdgpu_ring_funcs gfx_v12_0_ring_funcs_kiq = { From 66acb26b1bc0922b55533db7c812f8358eaf991a Mon Sep 17 00:00:00 2001 From: Jiadong Zhu Date: Thu, 4 Jul 2024 12:10:59 +0800 Subject: [PATCH 1448/1868] drm/amdgpu/mes: modify mes api for mmio queue reset Add me/pipe/queue parameters for queue reset input. v2: fix build (Alex) Acked-by: Vitaly Prosyak Signed-off-by: Jiadong Zhu Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 3 ++- drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 14 +++++++++++++- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 2 +- 4 files changed, 17 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c index 6d0cb6b5bf719..199bd762113c3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c @@ -873,7 +873,8 @@ int amdgpu_mes_unmap_legacy_queue(struct amdgpu_device *adev, int amdgpu_mes_reset_legacy_queue(struct amdgpu_device *adev, struct amdgpu_ring *ring, - unsigned int vmid) + unsigned int vmid, + bool use_mmio) { struct mes_reset_legacy_queue_input queue_input; int r; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h index 5475e84b23e66..96788c0f42f1b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h @@ -252,6 +252,13 @@ struct mes_remove_queue_input { struct mes_reset_queue_input { uint32_t doorbell_offset; uint64_t gang_context_addr; + bool use_mmio; + uint32_t queue_type; + uint32_t me_id; + uint32_t pipe_id; + uint32_t queue_id; + uint32_t xcc_id; + uint32_t vmid; }; struct mes_map_legacy_queue_input { @@ -288,6 +295,8 @@ struct mes_resume_gang_input { struct mes_reset_legacy_queue_input { uint32_t queue_type; uint32_t doorbell_offset; + bool use_mmio; + uint32_t me_id; uint32_t pipe_id; uint32_t queue_id; uint64_t mqd_addr; @@ -397,6 +406,8 @@ int amdgpu_mes_add_hw_queue(struct amdgpu_device *adev, int gang_id, int *queue_id); int amdgpu_mes_remove_hw_queue(struct amdgpu_device *adev, int queue_id); int amdgpu_mes_reset_hw_queue(struct amdgpu_device *adev, int queue_id); +int amdgpu_mes_reset_hw_queue_mmio(struct amdgpu_device *adev, int queue_type, + int me_id, int pipe_id, int queue_id, int vmid); int amdgpu_mes_map_legacy_queue(struct amdgpu_device *adev, struct amdgpu_ring *ring); @@ -406,7 +417,8 @@ int amdgpu_mes_unmap_legacy_queue(struct amdgpu_device *adev, u64 gpu_addr, u64 seq); int amdgpu_mes_reset_legacy_queue(struct amdgpu_device *adev, struct amdgpu_ring *ring, - unsigned int vmid); + unsigned int vmid, + bool use_mmio); uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg); int amdgpu_mes_wreg(struct amdgpu_device *adev, diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index 2f5eed56892d1..fd0d51e93dd42 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -6549,7 +6549,7 @@ static int gfx_v11_0_reset_kgq(struct amdgpu_ring *ring, unsigned int vmid) struct amdgpu_device *adev = ring->adev; int r; - r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid); + r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, false); if (r) return r; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c index b207de46a29b5..6e2883e2dbe5a 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c @@ -5163,7 +5163,7 @@ static int gfx_v12_0_reset_kgq(struct amdgpu_ring *ring, unsigned int vmid) struct amdgpu_device *adev = ring->adev; int r; - r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid); + r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, false); if (r) { dev_err(adev->dev, "reset via MES failed %d\n", r); return r; From f16150a594a6b8c19a514b6fb532db199324a0c3 Mon Sep 17 00:00:00 2001 From: Jiadong Zhu Date: Thu, 4 Jul 2024 12:26:16 +0800 Subject: [PATCH 1449/1868] drm/amdgpu/mes: implement amdgpu_mes_reset_hw_queue_mmio The reset_queue api could be used from kfd or kgd. v2: add use_mmio parameter for mes_reset_legacy_queue. Acked-by: Vitaly Prosyak Signed-off-by: Jiadong Zhu Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c index 199bd762113c3..e395373f7c563 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c @@ -826,6 +826,24 @@ int amdgpu_mes_reset_hw_queue(struct amdgpu_device *adev, int queue_id) return 0; } +int amdgpu_mes_reset_hw_queue_mmio(struct amdgpu_device *adev, int queue_type, + int me_id, int pipe_id, int queue_id, int vmid) +{ + struct mes_reset_queue_input queue_input; + int r; + + queue_input.use_mmio = true; + queue_input.me_id = me_id; + queue_input.pipe_id = pipe_id; + queue_input.queue_id = queue_id; + queue_input.vmid = vmid; + r = adev->mes.funcs->reset_hw_queue(&adev->mes, &queue_input); + if (r) + DRM_ERROR("failed to reset hardware queue by mmio, queue id = %d\n", + queue_id); + return r; +} + int amdgpu_mes_map_legacy_queue(struct amdgpu_device *adev, struct amdgpu_ring *ring) { @@ -883,11 +901,13 @@ int amdgpu_mes_reset_legacy_queue(struct amdgpu_device *adev, queue_input.queue_type = ring->funcs->type; queue_input.doorbell_offset = ring->doorbell_index; + queue_input.me_id = ring->me; queue_input.pipe_id = ring->pipe; queue_input.queue_id = ring->queue; queue_input.mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); queue_input.wptr_addr = ring->wptr_gpu_addr; queue_input.vmid = vmid; + queue_input.use_mmio = use_mmio; r = adev->mes.funcs->reset_legacy_queue(&adev->mes, &queue_input); if (r) From a97624c79c1f5f4c1e9a15a04d9a9d8fff9d91eb Mon Sep 17 00:00:00 2001 From: Jiadong Zhu Date: Thu, 4 Jul 2024 12:32:01 +0800 Subject: [PATCH 1450/1868] drm/amdgpu/mes11: implement mmio queue reset for gfx11 Implement queue reset for graphic and compute queue. v2: use amdgpu_gfx_rlc funcs to enter/exit safe mode. v3: use gfx_v11_0_request_gfx_index_mutex() v4: fix mutex handling Acked-by: Vitaly Prosyak Signed-off-by: Jiadong Zhu Reviewed-by: Alex Deucher Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 80 ++++++++++++++++++++++++++ 1 file changed, 80 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c index ebc3cdc602b8b..0f055d1b1da6b 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c @@ -26,6 +26,7 @@ #include "amdgpu.h" #include "soc15_common.h" #include "soc21.h" +#include "gfx_v11_0.h" #include "gc/gc_11_0_0_offset.h" #include "gc/gc_11_0_0_sh_mask.h" #include "gc/gc_11_0_0_default.h" @@ -360,9 +361,83 @@ static int mes_v11_0_remove_hw_queue(struct amdgpu_mes *mes, offsetof(union MESAPI__REMOVE_QUEUE, api_status)); } +static int mes_v11_0_reset_queue_mmio(struct amdgpu_mes *mes, uint32_t queue_type, + uint32_t me_id, uint32_t pipe_id, + uint32_t queue_id, uint32_t vmid) +{ + struct amdgpu_device *adev = mes->adev; + uint32_t value; + int i, r = 0; + + amdgpu_gfx_rlc_enter_safe_mode(adev, 0); + + if (queue_type == AMDGPU_RING_TYPE_GFX) { + dev_info(adev->dev, "reset gfx queue (%d:%d:%d: vmid:%d)\n", + me_id, pipe_id, queue_id, vmid); + + mutex_lock(&adev->gfx.reset_sem_mutex); + gfx_v11_0_request_gfx_index_mutex(adev, true); + /* all se allow writes */ + WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, + (uint32_t)(0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT)); + value = REG_SET_FIELD(0, CP_VMID_RESET, RESET_REQUEST, 1 << vmid); + if (pipe_id == 0) + value = REG_SET_FIELD(value, CP_VMID_RESET, PIPE0_QUEUES, 1 << queue_id); + else + value = REG_SET_FIELD(value, CP_VMID_RESET, PIPE1_QUEUES, 1 << queue_id); + WREG32_SOC15(GC, 0, regCP_VMID_RESET, value); + gfx_v11_0_request_gfx_index_mutex(adev, false); + mutex_unlock(&adev->gfx.reset_sem_mutex); + + mutex_lock(&adev->srbm_mutex); + soc21_grbm_select(adev, me_id, pipe_id, queue_id, 0); + /* wait till dequeue take effects */ + for (i = 0; i < adev->usec_timeout; i++) { + if (!(RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE) & 1)) + break; + udelay(1); + } + if (i >= adev->usec_timeout) { + dev_err(adev->dev, "failed to wait on gfx hqd deactivate\n"); + r = -ETIMEDOUT; + } + + soc21_grbm_select(adev, 0, 0, 0, 0); + mutex_unlock(&adev->srbm_mutex); + } else if (queue_type == AMDGPU_RING_TYPE_COMPUTE) { + dev_info(adev->dev, "reset compute queue (%d:%d:%d)\n", + me_id, pipe_id, queue_id); + mutex_lock(&adev->srbm_mutex); + soc21_grbm_select(adev, me_id, pipe_id, queue_id, 0); + WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2); + WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1); + + /* wait till dequeue take effects */ + for (i = 0; i < adev->usec_timeout; i++) { + if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) + break; + udelay(1); + } + if (i >= adev->usec_timeout) { + dev_err(adev->dev, "failed to wait on hqd deactivate\n"); + r = -ETIMEDOUT; + } + soc21_grbm_select(adev, 0, 0, 0, 0); + mutex_unlock(&adev->srbm_mutex); + } + + amdgpu_gfx_rlc_exit_safe_mode(adev, 0); + return r; +} + static int mes_v11_0_reset_hw_queue(struct amdgpu_mes *mes, struct mes_reset_queue_input *input) { + if (input->use_mmio) + return mes_v11_0_reset_queue_mmio(mes, input->queue_type, + input->me_id, input->pipe_id, + input->queue_id, input->vmid); + union MESAPI__RESET mes_reset_queue_pkt; memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt)); @@ -648,6 +723,11 @@ static int mes_v11_0_reset_legacy_queue(struct amdgpu_mes *mes, { union MESAPI__RESET mes_reset_queue_pkt; + if (input->use_mmio) + return mes_v11_0_reset_queue_mmio(mes, input->queue_type, + input->me_id, input->pipe_id, + input->queue_id, input->vmid); + memset(&mes_reset_queue_pkt, 0, sizeof(mes_reset_queue_pkt)); mes_reset_queue_pkt.header.type = MES_API_TYPE_SCHEDULER; From 143ad1de18e6458d4327bf7f3513626d5a1b98d8 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 18 Jul 2024 10:21:21 -0400 Subject: [PATCH 1451/1868] drm/amdgpu/gfx10: per queue reset only on bare metal It's not supported under SR-IOV at the moment. Acked-by: Vitaly Prosyak Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index d76535e2a938a..fe561bbd994ba 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -9532,6 +9532,9 @@ static int gfx_v10_0_reset_kgq(struct amdgpu_ring *ring, unsigned int vmid) u64 addr; int r; + if (amdgpu_sriov_vf(adev)) + return -EINVAL; + if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) return -EINVAL; @@ -9595,6 +9598,9 @@ static int gfx_v10_0_reset_kcq(struct amdgpu_ring *ring, unsigned long flags; int i, r; + if (amdgpu_sriov_vf(adev)) + return -EINVAL; + if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues) return -EINVAL; From fcef58793cfb05928acce36124e99df47e3a580f Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 18 Jul 2024 10:21:45 -0400 Subject: [PATCH 1452/1868] drm/amdgpu/gfx11: per queue reset only on bare metal It's not supported under SR-IOV at the moment. Acked-by: Vitaly Prosyak Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index fd0d51e93dd42..5ef4ff90ed86a 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -6549,6 +6549,9 @@ static int gfx_v11_0_reset_kgq(struct amdgpu_ring *ring, unsigned int vmid) struct amdgpu_device *adev = ring->adev; int r; + if (amdgpu_sriov_vf(adev)) + return -EINVAL; + r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, false); if (r) return r; @@ -6584,6 +6587,9 @@ static int gfx_v11_0_reset_kcq(struct amdgpu_ring *ring, unsigned int vmid) struct amdgpu_device *adev = ring->adev; int i, r = 0; + if (amdgpu_sriov_vf(adev)) + return -EINVAL; + gfx_v11_0_set_safe_mode(adev, 0); mutex_lock(&adev->srbm_mutex); soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); From 8b31df7d0353670617a032dcf73b9288f84afc19 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 18 Jul 2024 10:22:00 -0400 Subject: [PATCH 1453/1868] drm/amdgpu/gfx12: per queue reset only on bare metal It's not supported under SR-IOV at the moment. Acked-by: Vitaly Prosyak Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c index 6e2883e2dbe5a..5935cc55a098f 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c @@ -5163,6 +5163,9 @@ static int gfx_v12_0_reset_kgq(struct amdgpu_ring *ring, unsigned int vmid) struct amdgpu_device *adev = ring->adev; int r; + if (amdgpu_sriov_vf(adev)) + return -EINVAL; + r = amdgpu_mes_reset_legacy_queue(ring->adev, ring, vmid, false); if (r) { dev_err(adev->dev, "reset via MES failed %d\n", r); @@ -5200,6 +5203,9 @@ static int gfx_v12_0_reset_kcq(struct amdgpu_ring *ring, unsigned int vmid) struct amdgpu_device *adev = ring->adev; int r, i; + if (amdgpu_sriov_vf(adev)) + return -EINVAL; + gfx_v12_0_set_safe_mode(adev, 0); mutex_lock(&adev->srbm_mutex); soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); From 42decc3ace6ea27f2e17e6b4a9c844713618c186 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 24 Jul 2024 18:07:28 -0400 Subject: [PATCH 1454/1868] drm/amdgpu/gfx10: use proper rlc safe mode helpers Rather than open coding it for the queue reset. Acked-by: Vitaly Prosyak Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index fe561bbd994ba..2ddd7fc48c6ca 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -9621,7 +9621,7 @@ static int gfx_v10_0_reset_kcq(struct amdgpu_ring *ring, return r; /* make sure dequeue is complete*/ - gfx_v10_0_set_safe_mode(adev, 0); + amdgpu_gfx_rlc_enter_safe_mode(adev, 0); mutex_lock(&adev->srbm_mutex); nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); for (i = 0; i < adev->usec_timeout; i++) { @@ -9633,7 +9633,7 @@ static int gfx_v10_0_reset_kcq(struct amdgpu_ring *ring, r = -ETIMEDOUT; nv_grbm_select(adev, 0, 0, 0, 0); mutex_unlock(&adev->srbm_mutex); - gfx_v10_0_unset_safe_mode(adev, 0); + amdgpu_gfx_rlc_exit_safe_mode(adev, 0); if (r) { dev_err(adev->dev, "fail to wait on hqd deactivate\n"); return r; From 8144047ccea572333f518d1b0be915a449eaacff Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 24 Jul 2024 18:10:04 -0400 Subject: [PATCH 1455/1868] drm/amdgpu/gfx11: use proper rlc safe mode helpers Rather than open coding it for the queue reset. Acked-by: Vitaly Prosyak Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index 5ef4ff90ed86a..a470a71bc74d5 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -4781,7 +4781,7 @@ static int gfx_v11_0_soft_reset(void *handle) int r, i, j, k; struct amdgpu_device *adev = (struct amdgpu_device *)handle; - gfx_v11_0_set_safe_mode(adev, 0); + amdgpu_gfx_rlc_enter_safe_mode(adev, 0); tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL); tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 0); @@ -4900,7 +4900,7 @@ static int gfx_v11_0_soft_reset(void *handle) tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1); WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp); - gfx_v11_0_unset_safe_mode(adev, 0); + amdgpu_gfx_rlc_exit_safe_mode(adev, 0); return gfx_v11_0_cp_resume(adev); } @@ -6590,7 +6590,7 @@ static int gfx_v11_0_reset_kcq(struct amdgpu_ring *ring, unsigned int vmid) if (amdgpu_sriov_vf(adev)) return -EINVAL; - gfx_v11_0_set_safe_mode(adev, 0); + amdgpu_gfx_rlc_enter_safe_mode(adev, 0); mutex_lock(&adev->srbm_mutex); soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2); @@ -6606,7 +6606,7 @@ static int gfx_v11_0_reset_kcq(struct amdgpu_ring *ring, unsigned int vmid) r = -ETIMEDOUT; soc21_grbm_select(adev, 0, 0, 0, 0); mutex_unlock(&adev->srbm_mutex); - gfx_v11_0_unset_safe_mode(adev, 0); + amdgpu_gfx_rlc_exit_safe_mode(adev, 0); if (r) { dev_err(adev->dev, "fail to wait on hqd deactivate\n"); return r; From 1d26a31471804c1c166aefca751879d1760f12e9 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 24 Jul 2024 18:11:52 -0400 Subject: [PATCH 1456/1868] drm/amdgpu/gfx12: use proper rlc safe mode helpers Rather than open coding it for the queue reset. Acked-by: Vitaly Prosyak Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c index 5935cc55a098f..94ef02d551e65 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c @@ -5206,7 +5206,7 @@ static int gfx_v12_0_reset_kcq(struct amdgpu_ring *ring, unsigned int vmid) if (amdgpu_sriov_vf(adev)) return -EINVAL; - gfx_v12_0_set_safe_mode(adev, 0); + amdgpu_gfx_rlc_enter_safe_mode(adev, 0); mutex_lock(&adev->srbm_mutex); soc24_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0); WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2); @@ -5218,7 +5218,7 @@ static int gfx_v12_0_reset_kcq(struct amdgpu_ring *ring, unsigned int vmid) } soc24_grbm_select(adev, 0, 0, 0, 0); mutex_unlock(&adev->srbm_mutex); - gfx_v12_0_unset_safe_mode(adev, 0); + amdgpu_gfx_rlc_exit_safe_mode(adev, 0); r = amdgpu_bo_reserve(ring->mqd_obj, false); if (unlikely(r != 0)) { From b1bccb86d2607c13d58f78bd01847bb52ce52661 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 24 Jul 2024 18:20:13 -0400 Subject: [PATCH 1457/1868] drm/amdgpu/gfx12: use rlc safe mode for soft recovery Protect the MMIO access with safe mode. Acked-by: Vitaly Prosyak Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c index 94ef02d551e65..d1357c01eb391 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c @@ -4620,7 +4620,9 @@ static void gfx_v12_0_ring_soft_recovery(struct amdgpu_ring *ring, value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); + amdgpu_gfx_rlc_enter_safe_mode(adev, 0); WREG32_SOC15(GC, 0, regSQ_CMD, value); + amdgpu_gfx_rlc_exit_safe_mode(adev, 0); } static void From 5445ee94611166c2948cd2605601244152f25485 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 24 Jul 2024 18:20:23 -0400 Subject: [PATCH 1458/1868] drm/amdgpu/gfx11: use rlc safe mode for soft recovery Protect the MMIO access with safe mode. Acked-by: Vitaly Prosyak Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index a470a71bc74d5..d3e8be82a1727 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -6091,7 +6091,9 @@ static void gfx_v11_0_ring_soft_recovery(struct amdgpu_ring *ring, value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); + amdgpu_gfx_rlc_enter_safe_mode(adev, 0); WREG32_SOC15(GC, 0, regSQ_CMD, value); + amdgpu_gfx_rlc_exit_safe_mode(adev, 0); } static void From 44ac14a44c9c2c367265e2f374f69467919916e6 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 24 Jul 2024 18:20:34 -0400 Subject: [PATCH 1459/1868] drm/amdgpu/gfx10: use rlc safe mode for soft recovery Protect the MMIO access with safe mode. Acked-by: Vitaly Prosyak Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 2ddd7fc48c6ca..90ccf4baa7f5a 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -9055,7 +9055,9 @@ static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring, value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); + amdgpu_gfx_rlc_enter_safe_mode(adev, 0); WREG32_SOC15(GC, 0, mmSQ_CMD, value); + amdgpu_gfx_rlc_exit_safe_mode(adev, 0); } static void From cd54e558969cf628adde715e7eebbb2c4648d272 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Tue, 20 Aug 2024 12:01:22 +0200 Subject: [PATCH 1460/1868] drm/amdgpu: re-work VM syncing MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Rework how VM operations synchronize to submissions. Provide an amdgpu_sync container to the backends instead of an reservation object and fill in the amdgpu_sync object in the higher layers of the code. No intended functional change, just prepares for upcomming changes. Signed-off-by: Christian König Reviewed-by: Friedrich Vock Acked-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 84 +++++++++++++-------- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 11 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c | 7 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 16 +--- 5 files changed, 65 insertions(+), 55 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index dad39fe611e25..97996ac22b75b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -859,7 +859,7 @@ int amdgpu_vm_update_pdes(struct amdgpu_device *adev, params.vm = vm; params.immediate = immediate; - r = vm->update_funcs->prepare(¶ms, NULL, AMDGPU_SYNC_EXPLICIT); + r = vm->update_funcs->prepare(¶ms, NULL); if (r) goto error; @@ -954,7 +954,7 @@ amdgpu_vm_tlb_flush(struct amdgpu_vm_update_params *params, * @unlocked: unlocked invalidation during MM callback * @flush_tlb: trigger tlb invalidation after update completed * @allow_override: change MTYPE for local NUMA nodes - * @resv: fences we need to sync to + * @sync: fences we need to sync to * @start: start of mapped range * @last: last mapped entry * @flags: flags for the entries @@ -970,16 +970,16 @@ amdgpu_vm_tlb_flush(struct amdgpu_vm_update_params *params, * 0 for success, negative erro code for failure. */ int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm, - bool immediate, bool unlocked, bool flush_tlb, bool allow_override, - struct dma_resv *resv, uint64_t start, uint64_t last, - uint64_t flags, uint64_t offset, uint64_t vram_base, + bool immediate, bool unlocked, bool flush_tlb, + bool allow_override, struct amdgpu_sync *sync, + uint64_t start, uint64_t last, uint64_t flags, + uint64_t offset, uint64_t vram_base, struct ttm_resource *res, dma_addr_t *pages_addr, struct dma_fence **fence) { struct amdgpu_vm_tlb_seq_struct *tlb_cb; struct amdgpu_vm_update_params params; struct amdgpu_res_cursor cursor; - enum amdgpu_sync_mode sync_mode; int r, idx; if (!drm_dev_enter(adev_to_drm(adev), &idx)) @@ -1012,14 +1012,6 @@ int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm, params.allow_override = allow_override; INIT_LIST_HEAD(¶ms.tlb_flush_waitlist); - /* Implicitly sync to command submissions in the same VM before - * unmapping. Sync to moving fences before mapping. - */ - if (!(flags & AMDGPU_PTE_VALID)) - sync_mode = AMDGPU_SYNC_EQ_OWNER; - else - sync_mode = AMDGPU_SYNC_EXPLICIT; - amdgpu_vm_eviction_lock(vm); if (vm->evicting) { r = -EBUSY; @@ -1034,7 +1026,7 @@ int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm, dma_fence_put(tmp); } - r = vm->update_funcs->prepare(¶ms, resv, sync_mode); + r = vm->update_funcs->prepare(¶ms, sync); if (r) goto error_free; @@ -1190,24 +1182,31 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va, struct amdgpu_bo *bo = bo_va->base.bo; struct amdgpu_vm *vm = bo_va->base.vm; struct amdgpu_bo_va_mapping *mapping; + struct dma_fence **last_update; dma_addr_t *pages_addr = NULL; struct ttm_resource *mem; - struct dma_fence **last_update; + struct amdgpu_sync sync; bool flush_tlb = clear; - bool uncached; - struct dma_resv *resv; uint64_t vram_base; uint64_t flags; + bool uncached; int r; struct amdgpu_device *bo_adev = adev; + amdgpu_sync_create(&sync); if (clear || !bo) { mem = NULL; - resv = amdkcl_ttm_resvp(&vm->root.bo->tbo); + + /* Implicitly sync to command submissions in the same VM before + * unmapping. + */ + r = amdgpu_sync_resv(adev, &sync, vm->root.bo->tbo.base.resv, + AMDGPU_SYNC_EQ_OWNER, vm); + if (r) + goto error_free; } else { struct drm_gem_object *obj = &bo->tbo.base; - resv = amdkcl_ttm_resvp(&bo->tbo); if (obj->import_attach && bo_va->is_xgmi) { struct dma_buf *dma_buf = obj->import_attach->dmabuf; struct drm_gem_object *gobj = dma_buf->priv; @@ -1223,6 +1222,12 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va, pages_addr = bo->tbo.ttm->dma_address; else if (mem && mem->mem_type == AMDGPU_PL_DGMA_IMPORT) pages_addr = (dma_addr_t *)bo->dgma_addr; + + /* Implicitly sync to moving fences before mapping anything */ + r = amdgpu_sync_resv(adev, &sync, bo->tbo.base.resv, + AMDGPU_SYNC_EXPLICIT, vm); + if (r) + goto error_free; } if (bo) { @@ -1282,12 +1287,12 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va, trace_amdgpu_vm_bo_update(mapping); r = amdgpu_vm_update_range(adev, vm, false, false, flush_tlb, - !uncached, resv, mapping->start, mapping->last, - update_flags, mapping->offset, - vram_base, mem, pages_addr, - last_update); + !uncached, &sync, mapping->start, + mapping->last, update_flags, + mapping->offset, vram_base, mem, + pages_addr, last_update); if (r) - return r; + goto error_free; } /* If the BO is not in its preferred location add it back to @@ -1315,7 +1320,9 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va, trace_amdgpu_vm_bo_mapping(mapping); } - return 0; +error_free: + amdgpu_sync_free(&sync); + return r; } /** @@ -1462,25 +1469,34 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev, struct amdgpu_vm *vm, struct dma_fence **fence) { - struct dma_resv *resv = amdkcl_ttm_resvp(&vm->root.bo->tbo); struct amdgpu_bo_va_mapping *mapping; - uint64_t init_pte_value = 0; struct dma_fence *f = NULL; + struct amdgpu_sync sync; int r; + + /* + * Implicitly sync to command submissions in the same VM before + * unmapping. + */ + amdgpu_sync_create(&sync); + r = amdgpu_sync_resv(adev, &sync, vm->root.bo->tbo.base.resv, + AMDGPU_SYNC_EQ_OWNER, vm); + if (r) + goto error_free; + while (!list_empty(&vm->freed)) { mapping = list_first_entry(&vm->freed, struct amdgpu_bo_va_mapping, list); list_del(&mapping->list); r = amdgpu_vm_update_range(adev, vm, false, false, true, false, - resv, mapping->start, mapping->last, - init_pte_value, 0, 0, NULL, NULL, - &f); + &sync, mapping->start, mapping->last, + 0, 0, 0, NULL, NULL, &f); amdgpu_vm_free_mapping(adev, vm, mapping, f); if (r) { dma_fence_put(f); - return r; + goto error_free; } } @@ -1491,7 +1507,9 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev, dma_fence_put(f); } - return 0; +error_free: + amdgpu_sync_free(&sync); + return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h index 41de3691aef9a..e62471b04e955 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h @@ -304,8 +304,8 @@ struct amdgpu_vm_update_params { struct amdgpu_vm_update_funcs { int (*map_table)(struct amdgpu_bo_vm *bo); - int (*prepare)(struct amdgpu_vm_update_params *p, struct dma_resv *resv, - enum amdgpu_sync_mode sync_mode); + int (*prepare)(struct amdgpu_vm_update_params *p, + struct amdgpu_sync *sync); int (*update)(struct amdgpu_vm_update_params *p, struct amdgpu_bo_vm *bo, uint64_t pe, uint64_t addr, unsigned count, uint32_t incr, uint64_t flags); @@ -514,9 +514,10 @@ int amdgpu_vm_flush_compute_tlb(struct amdgpu_device *adev, void amdgpu_vm_bo_base_init(struct amdgpu_vm_bo_base *base, struct amdgpu_vm *vm, struct amdgpu_bo *bo); int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm, - bool immediate, bool unlocked, bool flush_tlb, bool allow_override, - struct dma_resv *resv, uint64_t start, uint64_t last, - uint64_t flags, uint64_t offset, uint64_t vram_base, + bool immediate, bool unlocked, bool flush_tlb, + bool allow_override, struct amdgpu_sync *sync, + uint64_t start, uint64_t last, uint64_t flags, + uint64_t offset, uint64_t vram_base, struct ttm_resource *res, dma_addr_t *pages_addr, struct dma_fence **fence); int amdgpu_vm_bo_update(struct amdgpu_device *adev, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c index 01092929f61d6..cd842351121a4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c @@ -46,13 +46,12 @@ static int amdgpu_vm_cpu_map_table(struct amdgpu_bo_vm *table) * Negativ errno, 0 for success. */ static int amdgpu_vm_cpu_prepare(struct amdgpu_vm_update_params *p, - struct dma_resv *resv, - enum amdgpu_sync_mode sync_mode) + struct amdgpu_sync *sync) { - if (!resv) + if (!sync) return 0; - return amdgpu_bo_sync_wait_resv(p->adev, resv, sync_mode, p->vm, true); + return amdgpu_sync_wait(sync, true); } /** diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c index 5cf2d5d87c879..761b7ac12f1ff 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c @@ -403,7 +403,7 @@ int amdgpu_vm_pt_clear(struct amdgpu_device *adev, struct amdgpu_vm *vm, params.vm = vm; params.immediate = immediate; - r = vm->update_funcs->prepare(¶ms, NULL, AMDGPU_SYNC_EXPLICIT); + r = vm->update_funcs->prepare(¶ms, NULL); if (r) goto exit; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c index 07ce990fc9573..7769884f555dd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c @@ -77,32 +77,24 @@ static int amdgpu_vm_sdma_alloc_job(struct amdgpu_vm_update_params *p, * amdgpu_vm_sdma_prepare - prepare SDMA command submission * * @p: see amdgpu_vm_update_params definition - * @resv: reservation object with embedded fence - * @sync_mode: synchronization mode + * @sync: amdgpu_sync object with fences to wait for * * Returns: * Negativ errno, 0 for success. */ static int amdgpu_vm_sdma_prepare(struct amdgpu_vm_update_params *p, - struct dma_resv *resv, - enum amdgpu_sync_mode sync_mode) + struct amdgpu_sync *sync) { - struct amdgpu_sync sync; int r; r = amdgpu_vm_sdma_alloc_job(p, 0); if (r) return r; - if (!resv) + if (!sync) return 0; - amdgpu_sync_create(&sync); - r = amdgpu_sync_resv(p->adev, &sync, resv, sync_mode, p->vm); - if (!r) - r = amdgpu_sync_push_to_job(&sync, p->job); - amdgpu_sync_free(&sync); - + r = amdgpu_sync_push_to_job(sync, p->job); if (r) { p->num_dw_left = 0; amdgpu_job_free(p->job); From b10e9e23327026e4661a209266c60ee032a620d2 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 2 Sep 2024 14:25:24 +0800 Subject: [PATCH 1461/1868] drm/amdkcl: wrap code under amdkcl_ttm_resvp() It's caused by 5efa478729c8f2c8eb3c05034a37ad72654307af "drm/amdgpu: re-work VM syncing" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 97996ac22b75b..5aa1cb7f84974 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -1200,7 +1200,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va, /* Implicitly sync to command submissions in the same VM before * unmapping. */ - r = amdgpu_sync_resv(adev, &sync, vm->root.bo->tbo.base.resv, + r = amdgpu_sync_resv(adev, &sync, amdkcl_ttm_resvp(&vm->root.bo->tbo), AMDGPU_SYNC_EQ_OWNER, vm); if (r) goto error_free; @@ -1224,7 +1224,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va, pages_addr = (dma_addr_t *)bo->dgma_addr; /* Implicitly sync to moving fences before mapping anything */ - r = amdgpu_sync_resv(adev, &sync, bo->tbo.base.resv, + r = amdgpu_sync_resv(adev, &sync, amdkcl_ttm_resvp(&bo->tbo), AMDGPU_SYNC_EXPLICIT, vm); if (r) goto error_free; @@ -1480,7 +1480,7 @@ int amdgpu_vm_clear_freed(struct amdgpu_device *adev, * unmapping. */ amdgpu_sync_create(&sync); - r = amdgpu_sync_resv(adev, &sync, vm->root.bo->tbo.base.resv, + r = amdgpu_sync_resv(adev, &sync, amdkcl_ttm_resvp(&vm->root.bo->tbo), AMDGPU_SYNC_EQ_OWNER, vm); if (r) goto error_free; From e6ff40d5653eee6bf173e2b8d66dc9b453ede56e Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 5 Sep 2024 17:22:51 +0800 Subject: [PATCH 1462/1868] drm/amdkcl: update config.h Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/dkms/config/config.h | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index e1ac8fe9c7a1e..9ad1a8121c634 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -58,6 +58,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_ASM_SET_MEMORY_H 1 +/* __assign_str() wants 1 arguments */ +#define HAVE_ASSIGN_STR_ONE_ARGUMENT 1 + /* amdgpu_attr_group->is_bin_visible is available */ #define HAVE_ATTRIBUTE_GROUP_IS_BIN_VISIBLE 1 @@ -82,6 +85,9 @@ /* cpuinfo_x86.topo is available */ #define HAVE_CPUINFO_TOPOLOGY_IN_CPUINFO_X86_STRUCT 1 +/* drm_edid_raw() is available */ +#define HAVE_CRTC_DRM_VBLANK_CRTC 1 + /* debugfs_create_file_size() is available */ #define HAVE_DEBUGFS_CREATE_FILE_SIZE 1 @@ -596,12 +602,6 @@ /* drm_show_fdinfo() is available */ #define HAVE_DRM_SHOW_FDINFO 1 -/* __assign_str() wants 1 arguments */ -#define HAVE_ASSIGN_STR_ONE_ARGUMENT 1 - -/* follow_pfn() is available */ -/* #undef HAVE_FOLLOW_PFN */ - /* drm_simple_encoder is available */ #define HAVE_DRM_SIMPLE_ENCODER_INIT 1 @@ -620,6 +620,9 @@ /* fault_flag_allow_retry_first() is available */ #define HAVE_FAULT_FLAG_ALLOW_RETRY_FIRST 1 +/* follow_pfn() is available */ +/* #undef HAVE_FOLLOW_PFN */ + /* fsleep() is available */ #define HAVE_FSLEEP 1 @@ -1078,7 +1081,7 @@ #define PACKAGE_NAME "amdgpu-dkms" /* Define to the full name and version of this package. */ -#define PACKAGE_STRING "amdgpu-dkms 6.9.0" +#define PACKAGE_STRING "amdgpu-dkms 6.10.0" /* Define to the one symbol short name of this package. */ #define PACKAGE_TARNAME "amdgpu-dkms" @@ -1087,7 +1090,7 @@ #define PACKAGE_URL "" /* Define to the version of this package. */ -#define PACKAGE_VERSION "6.9.0" +#define PACKAGE_VERSION "6.10.0" #include "config-amd-chips.h" From cedb7225751e729972b3bf80321ed95a0fe97a6c Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Mon, 12 Aug 2024 15:23:10 +0300 Subject: [PATCH 1463/1868] drm/mst: switch to guid_t type for GUID The kernel has a guid_t type for GUIDs. Switch to using it, but avoid any functional changes here. Reviewed-by: Daniel Vetter Acked-by: Harry Wentland Acked-by: Alex Deucher Acked-by: Hamza Mahfooz Link: https://patchwork.freedesktop.org/patch/msgid/20240812122312.1567046-1-jani.nikula@intel.com Signed-off-by: Jani Nikula (cherry picked from commit 33929707b808ba7839c40c15d3e68cbc51070b31) --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- drivers/gpu/drm/display/drm_dp_mst_topology.c | 67 +++++++++++-------- include/drm/display/drm_dp_mst_helper.h | 12 ++-- 3 files changed, 45 insertions(+), 36 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index e8ab82814ec6b..ffa40912477ce 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2682,7 +2682,7 @@ static void resume_mst_branch_status(struct drm_dp_mst_topology_mgr *mgr) } } - memcpy(mgr->mst_primary->guid, guid, 16); + import_guid(&mgr->mst_primary->guid, guid); out_fail: mutex_unlock(&mgr->lock); diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c index fc2ceae61db2d..d8fdc88427564 100644 --- a/drivers/gpu/drm/display/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c @@ -89,7 +89,7 @@ static int drm_dp_send_enum_path_resources(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_branch *mstb, struct drm_dp_mst_port *port); static bool drm_dp_validate_guid(struct drm_dp_mst_topology_mgr *mgr, - u8 *guid); + guid_t *guid); static int drm_dp_mst_register_i2c_bus(struct drm_dp_mst_port *port); static void drm_dp_mst_unregister_i2c_bus(struct drm_dp_mst_port *port); @@ -801,7 +801,7 @@ static bool drm_dp_sideband_parse_link_address(const struct drm_dp_mst_topology_ int idx = 1; int i; - memcpy(repmsg->u.link_addr.guid, &raw->msg[idx], 16); + import_guid(&repmsg->u.link_addr.guid, &raw->msg[idx]); idx += 16; repmsg->u.link_addr.nports = raw->msg[idx] & 0xf; idx++; @@ -829,7 +829,7 @@ static bool drm_dp_sideband_parse_link_address(const struct drm_dp_mst_topology_ idx++; if (idx > raw->curlen) goto fail_len; - memcpy(repmsg->u.link_addr.ports[i].peer_guid, &raw->msg[idx], 16); + import_guid(&repmsg->u.link_addr.ports[i].peer_guid, &raw->msg[idx]); idx += 16; if (idx > raw->curlen) goto fail_len; @@ -1029,7 +1029,7 @@ static bool drm_dp_sideband_parse_reply(const struct drm_dp_mst_topology_mgr *mg msg->req_type = (raw->msg[0] & 0x7f); if (msg->reply_type == DP_SIDEBAND_REPLY_NAK) { - memcpy(msg->u.nak.guid, &raw->msg[1], 16); + import_guid(&msg->u.nak.guid, &raw->msg[1]); msg->u.nak.reason = raw->msg[17]; msg->u.nak.nak_data = raw->msg[18]; return false; @@ -1078,7 +1078,7 @@ drm_dp_sideband_parse_connection_status_notify(const struct drm_dp_mst_topology_ if (idx > raw->curlen) goto fail_len; - memcpy(msg->u.conn_stat.guid, &raw->msg[idx], 16); + import_guid(&msg->u.conn_stat.guid, &raw->msg[idx]); idx += 16; if (idx > raw->curlen) goto fail_len; @@ -1107,7 +1107,7 @@ static bool drm_dp_sideband_parse_resource_status_notify(const struct drm_dp_mst if (idx > raw->curlen) goto fail_len; - memcpy(msg->u.resource_stat.guid, &raw->msg[idx], 16); + import_guid(&msg->u.resource_stat.guid, &raw->msg[idx]); idx += 16; if (idx > raw->curlen) goto fail_len; @@ -2174,20 +2174,24 @@ ssize_t drm_dp_mst_dpcd_write(struct drm_dp_aux *aux, offset, size, buffer); } -static int drm_dp_check_mstb_guid(struct drm_dp_mst_branch *mstb, u8 *guid) +static int drm_dp_check_mstb_guid(struct drm_dp_mst_branch *mstb, guid_t *guid) { int ret = 0; - memcpy(mstb->guid, guid, 16); + guid_copy(&mstb->guid, guid); + + if (!drm_dp_validate_guid(mstb->mgr, &mstb->guid)) { + u8 buf[UUID_SIZE]; + + export_guid(buf, &mstb->guid); - if (!drm_dp_validate_guid(mstb->mgr, mstb->guid)) { if (mstb->port_parent) { ret = drm_dp_send_dpcd_write(mstb->mgr, mstb->port_parent, - DP_GUID, 16, mstb->guid); + DP_GUID, sizeof(buf), buf); } else { ret = drm_dp_dpcd_write(mstb->mgr->aux, - DP_GUID, mstb->guid, 16); + DP_GUID, buf, sizeof(buf)); } } @@ -2570,9 +2574,9 @@ static struct drm_dp_mst_branch *drm_dp_get_mst_branch_device(struct drm_dp_mst_ return mstb; } -static struct drm_dp_mst_branch *get_mst_branch_device_by_guid_helper( - struct drm_dp_mst_branch *mstb, - const uint8_t *guid) +static struct drm_dp_mst_branch * +get_mst_branch_device_by_guid_helper(struct drm_dp_mst_branch *mstb, + const guid_t *guid) { struct drm_dp_mst_branch *found_mstb; struct drm_dp_mst_port *port; @@ -2580,10 +2584,9 @@ static struct drm_dp_mst_branch *get_mst_branch_device_by_guid_helper( if (!mstb) return NULL; - if (memcmp(mstb->guid, guid, 16) == 0) + if (guid_equal(&mstb->guid, guid)) return mstb; - list_for_each_entry(port, &mstb->ports, next) { found_mstb = get_mst_branch_device_by_guid_helper(port->mstb, guid); @@ -2596,7 +2599,7 @@ static struct drm_dp_mst_branch *get_mst_branch_device_by_guid_helper( static struct drm_dp_mst_branch * drm_dp_get_mst_branch_device_by_guid(struct drm_dp_mst_topology_mgr *mgr, - const uint8_t *guid) + const guid_t *guid) { struct drm_dp_mst_branch *mstb; int ret; @@ -2693,17 +2696,20 @@ static void drm_dp_mst_link_probe_work(struct work_struct *work) } static bool drm_dp_validate_guid(struct drm_dp_mst_topology_mgr *mgr, - u8 *guid) + guid_t *guid) { u64 salt; + u8 buf[UUID_SIZE]; - if (memchr_inv(guid, 0, 16)) + if (!guid_is_null(guid)) return true; salt = get_jiffies_64(); - memcpy(&guid[0], &salt, sizeof(u64)); - memcpy(&guid[8], &salt, sizeof(u64)); + memcpy(&buf[0], &salt, sizeof(u64)); + memcpy(&buf[8], &salt, sizeof(u64)); + + import_guid(guid, buf); return false; } @@ -2943,7 +2949,7 @@ static int drm_dp_send_link_address(struct drm_dp_mst_topology_mgr *mgr, drm_dbg_kms(mgr->dev, "link address reply: %d\n", reply->nports); drm_dp_dump_link_address(mgr, reply); - ret = drm_dp_check_mstb_guid(mstb, reply->guid); + ret = drm_dp_check_mstb_guid(mstb, &reply->guid); if (ret) { char buf[64]; @@ -3770,8 +3776,9 @@ EXPORT_SYMBOL(drm_dp_mst_topology_mgr_suspend); int drm_dp_mst_topology_mgr_resume(struct drm_dp_mst_topology_mgr *mgr, bool sync) { + u8 buf[UUID_SIZE]; + guid_t guid; int ret; - u8 guid[16]; mutex_lock(&mgr->lock); if (!mgr->mst_primary) @@ -3792,13 +3799,15 @@ int drm_dp_mst_topology_mgr_resume(struct drm_dp_mst_topology_mgr *mgr, } /* Some hubs forget their guids after they resume */ - ret = drm_dp_dpcd_read(mgr->aux, DP_GUID, guid, 16); - if (ret != 16) { + ret = drm_dp_dpcd_read(mgr->aux, DP_GUID, buf, sizeof(buf)); + if (ret != sizeof(buf)) { drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n"); goto out_fail; } - ret = drm_dp_check_mstb_guid(mgr->mst_primary, guid); + import_guid(&guid, buf); + + ret = drm_dp_check_mstb_guid(mgr->mst_primary, &guid); if (ret) { drm_dbg_kms(mgr->dev, "check mstb failed - undocked during suspend?\n"); goto out_fail; @@ -3976,12 +3985,12 @@ drm_dp_mst_process_up_req(struct drm_dp_mst_topology_mgr *mgr, bool hotplug = false, dowork = false; if (hdr->broadcast) { - const u8 *guid = NULL; + const guid_t *guid = NULL; if (msg->req_type == DP_CONNECTION_STATUS_NOTIFY) - guid = msg->u.conn_stat.guid; + guid = &msg->u.conn_stat.guid; else if (msg->req_type == DP_RESOURCE_STATUS_NOTIFY) - guid = msg->u.resource_stat.guid; + guid = &msg->u.resource_stat.guid; if (guid) mstb = drm_dp_get_mst_branch_device_by_guid(mgr, guid); diff --git a/include/drm/display/drm_dp_mst_helper.h b/include/drm/display/drm_dp_mst_helper.h index cfe096389d94f..dd466631f174f 100644 --- a/include/drm/display/drm_dp_mst_helper.h +++ b/include/drm/display/drm_dp_mst_helper.h @@ -244,18 +244,18 @@ struct drm_dp_mst_branch { bool link_address_sent; /* global unique identifier to identify branch devices */ - u8 guid[16]; + guid_t guid; }; struct drm_dp_nak_reply { - u8 guid[16]; + guid_t guid; u8 reason; u8 nak_data; }; struct drm_dp_link_address_ack_reply { - u8 guid[16]; + guid_t guid; u8 nports; struct drm_dp_link_addr_reply_port { bool input_port; @@ -265,7 +265,7 @@ struct drm_dp_link_address_ack_reply { bool ddps; bool legacy_device_plug_status; u8 dpcd_revision; - u8 peer_guid[16]; + guid_t peer_guid; u8 num_sdp_streams; u8 num_sdp_stream_sinks; } ports[16]; @@ -348,7 +348,7 @@ struct drm_dp_allocate_payload_ack_reply { }; struct drm_dp_connection_status_notify { - u8 guid[16]; + guid_t guid; u8 port_number; bool legacy_device_plug_status; bool displayport_device_plug_status; @@ -425,7 +425,7 @@ struct drm_dp_query_payload { struct drm_dp_resource_status_notify { u8 port_number; - u8 guid[16]; + guid_t guid; u16 available_pbn; }; From 6974f8fe84743c18f8efb1ccf0315ac17ffa8a4b Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Mon, 12 Aug 2024 15:23:11 +0300 Subject: [PATCH 1464/1868] drm/mst: switch to guid_gen() to generate valid GUIDs Instead of just smashing jiffies into a GUID, use guid_gen() to generate RFC 4122 compliant GUIDs. Reviewed-by: Daniel Vetter Acked-by: Harry Wentland Acked-by: Alex Deucher Acked-by: Hamza Mahfooz Link: https://patchwork.freedesktop.org/patch/msgid/20240812122312.1567046-2-jani.nikula@intel.com Signed-off-by: Jani Nikula (cherry picked from commit 4548f10bf4c67b569b7c9fbc6746340a558faab9) --- drivers/gpu/drm/display/drm_dp_mst_topology.c | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c index d8fdc88427564..c4a662ae7e884 100644 --- a/drivers/gpu/drm/display/drm_dp_mst_topology.c +++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c @@ -2698,18 +2698,10 @@ static void drm_dp_mst_link_probe_work(struct work_struct *work) static bool drm_dp_validate_guid(struct drm_dp_mst_topology_mgr *mgr, guid_t *guid) { - u64 salt; - u8 buf[UUID_SIZE]; - if (!guid_is_null(guid)) return true; - salt = get_jiffies_64(); - - memcpy(&buf[0], &salt, sizeof(u64)); - memcpy(&buf[8], &salt, sizeof(u64)); - - import_guid(guid, buf); + guid_gen(guid); return false; } From 7839382565c9304305ed03074cd572acdda2d366 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Mon, 12 Aug 2024 15:23:12 +0300 Subject: [PATCH 1465/1868] drm/amd/display: switch to guid_gen() to generate valid GUIDs Instead of just smashing jiffies into a GUID, use guid_gen() to generate RFC 4122 compliant GUIDs. Reviewed-by: Daniel Vetter Acked-by: Harry Wentland Acked-by: Alex Deucher Acked-by: Hamza Mahfooz Link: https://patchwork.freedesktop.org/patch/msgid/20240812122312.1567046-3-jani.nikula@intel.com Signed-off-by: Jani Nikula (cherry picked from commit b71ccff68ef1a5bd1c02d0fca01ddb3d9088329a) --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 23 ++++++++++--------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index ffa40912477ce..c5962617fa433 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2640,9 +2640,9 @@ static int dm_late_init(void *handle) static void resume_mst_branch_status(struct drm_dp_mst_topology_mgr *mgr) { + u8 buf[UUID_SIZE]; + guid_t guid; int ret; - u8 guid[16]; - u64 tmp64; mutex_lock(&mgr->lock); if (!mgr->mst_primary) @@ -2663,26 +2663,27 @@ static void resume_mst_branch_status(struct drm_dp_mst_topology_mgr *mgr) } /* Some hubs forget their guids after they resume */ - ret = drm_dp_dpcd_read(mgr->aux, DP_GUID, guid, 16); - if (ret != 16) { + ret = drm_dp_dpcd_read(mgr->aux, DP_GUID, buf, sizeof(buf)); + if (ret != sizeof(buf)) { drm_dbg_kms(mgr->dev, "dpcd read failed - undocked during suspend?\n"); goto out_fail; } - if (memchr_inv(guid, 0, 16) == NULL) { - tmp64 = get_jiffies_64(); - memcpy(&guid[0], &tmp64, sizeof(u64)); - memcpy(&guid[8], &tmp64, sizeof(u64)); + import_guid(&guid, buf); - ret = drm_dp_dpcd_write(mgr->aux, DP_GUID, guid, 16); + if (guid_is_null(&guid)) { + guid_gen(&guid); + export_guid(buf, &guid); - if (ret != 16) { + ret = drm_dp_dpcd_write(mgr->aux, DP_GUID, buf, sizeof(buf)); + + if (ret != sizeof(buf)) { drm_dbg_kms(mgr->dev, "check mstb guid failed - undocked during suspend?\n"); goto out_fail; } } - import_guid(&mgr->mst_primary->guid, guid); + guid_copy(&mgr->mst_primary->guid, &guid); out_fail: mutex_unlock(&mgr->lock); From bdceca4ea2e9f178c6d2b33d2eb33a5c331a8c97 Mon Sep 17 00:00:00 2001 From: Victor Zhao Date: Mon, 26 Aug 2024 00:14:26 +0800 Subject: [PATCH 1466/1868] drm/amd/amdgpu: move drain_workqueue before shutdown is set [background] when unloading amdgpu driver right after running a workload, drain_workqueue is causing "Fence fallback timer expired on ring sdma0.0". Under sriov, this issue will cause sriov full access timeout and a reset happening. move drain_workqueue before shutdown is set to allow ih process and before enter full access under sriov to avoid full access time cost. Signed-off-by: Victor Zhao Reviewed-by: Feifei Xu (cherry picked from commit 999738317278a7e6a5ba7768541e232fd248700d) Change-Id: I0c80ed0817f351385be56a95d4dcefcbbd3840c9 --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 65dff728b7a08..63c44e4829a3b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -4546,6 +4546,9 @@ void amdgpu_device_fini_hw(struct amdgpu_device *adev) { dev_info(adev->dev, "amdgpu: finishing device.\n"); flush_delayed_work(&adev->delayed_init_work); + + if (adev->mman.initialized) + drain_workqueue(adev->mman.bdev.wq); adev->shutdown = true; /* make sure IB test finished before entering exclusive mode @@ -4566,9 +4569,6 @@ void amdgpu_device_fini_hw(struct amdgpu_device *adev) } amdgpu_fence_driver_hw_fini(adev); - if (adev->mman.initialized) - drain_workqueue(adev->mman.bdev.wq); - if (adev->pm.sysfs_initialized) amdgpu_pm_sysfs_fini(adev); if (adev->ucode_sysfs_en) From eb47ebe773f8441128e5753bd6ee7ff4408c2c9c Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Fri, 16 Aug 2024 12:40:43 +0530 Subject: [PATCH 1467/1868] drm/amdgpu: Normalize reg offsets on JPEG v4.0.3 On VFs and SOCs with GC 9.4.4, VCN RRMT is disabled. Only local register offsets should be used on JPEG v4.0.3 as they cannot handle remote access to other AIDs. Since only local offsets are used, the special write to MCM_ADDR register is no longer needed. Signed-off-by: Lijo Lazar Reviewed-by: Sathishkumar S --- drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 36 ++++++++++-------------- 1 file changed, 15 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c index c30c4cc3bb991..8219248a9a870 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c @@ -59,6 +59,12 @@ static int amdgpu_ih_srcid_jpeg[] = { VCN_4_0__SRCID__JPEG7_DECODE }; +static inline bool jpeg_v4_0_3_normalizn_reqd(struct amdgpu_device *adev) +{ + return amdgpu_sriov_vf(adev) || + (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)); +} + /** * jpeg_v4_0_3_early_init - set function pointers * @@ -732,32 +738,20 @@ void jpeg_v4_0_3_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4)); amdgpu_ring_write(ring, 0); - if (ring->adev->jpeg.inst[ring->me].aid_id) { - amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_MCM_ADDR_INTERNAL_OFFSET, - 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE0)); - amdgpu_ring_write(ring, 0x4); - } else { - amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6)); - amdgpu_ring_write(ring, 0); - } + amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6)); + amdgpu_ring_write(ring, 0); amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 0, 0, PACKETJ_TYPE0)); amdgpu_ring_write(ring, 0x3fbc); - if (ring->adev->jpeg.inst[ring->me].aid_id) { - amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_MCM_ADDR_INTERNAL_OFFSET, - 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE0)); - amdgpu_ring_write(ring, 0x0); - } else { - amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6)); - amdgpu_ring_write(ring, 0); - } - amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 0, 0, PACKETJ_TYPE0)); amdgpu_ring_write(ring, 0x1); + amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6)); + amdgpu_ring_write(ring, 0); + amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7)); amdgpu_ring_write(ring, 0); } @@ -832,8 +826,8 @@ void jpeg_v4_0_3_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, { uint32_t reg_offset; - /* For VF, only local offsets should be used */ - if (amdgpu_sriov_vf(ring->adev)) + /* Use normalized offsets if required */ + if (jpeg_v4_0_3_normalizn_reqd(ring->adev)) reg = NORMALIZE_JPEG_REG_OFFSET(reg); reg_offset = (reg << 2); @@ -879,8 +873,8 @@ void jpeg_v4_0_3_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint { uint32_t reg_offset; - /* For VF, only local offsets should be used */ - if (amdgpu_sriov_vf(ring->adev)) + /* Use normalized offsets if required */ + if (jpeg_v4_0_3_normalizn_reqd(ring->adev)) reg = NORMALIZE_JPEG_REG_OFFSET(reg); reg_offset = (reg << 2); From add998637542cd729d3b2c46594f963d001d6849 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 2 Sep 2024 14:27:41 +0800 Subject: [PATCH 1468/1868] drm/amdkcl: test import_guid() is available It's caused by ea612cbee8cea66d71922f446cdd3223636e1df2 "drm/amd/display: switch to guid_gen() to generate valid GUIDs" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/backport/backport.h | 1 + drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/import_guid.m4 | 19 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + include/kcl/kcl_uuid.h | 19 +++++++++++++++++++ 5 files changed, 43 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/import_guid.m4 create mode 100644 include/kcl/kcl_uuid.h diff --git a/drivers/gpu/drm/amd/backport/backport.h b/drivers/gpu/drm/amd/backport/backport.h index 6ec330de9f4dd..013a98f215a07 100644 --- a/drivers/gpu/drm/amd/backport/backport.h +++ b/drivers/gpu/drm/amd/backport/backport.h @@ -129,4 +129,5 @@ #include #include #include +#include #endif /* AMDGPU_BACKPORT_H */ diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 9ad1a8121c634..91b03ecf5768a 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -680,6 +680,9 @@ /* idr_remove return void pointer */ #define HAVE_IDR_REMOVE_RETURN_VOID_POINTER 1 +/* import_guid() is available */ +#define HAVE_IMPORT_GUID 1 + /* in_compat_syscall is defined */ #define HAVE_IN_COMPAT_SYSCALL 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/import_guid.m4 b/drivers/gpu/drm/amd/dkms/m4/import_guid.m4 new file mode 100644 index 0000000000000..c96b4703e6cf9 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/import_guid.m4 @@ -0,0 +1,19 @@ +dnl # +dnl # v5.6-rc7-127-gd01cd62400b3 +dnl # uuid: Add inline helpers to import / export UUIDs +dnl # +AC_DEFUN([AC_AMDGPU_IMPORT_GUID], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + import_guid(NULL, NULL); + ],[ + AC_DEFINE(HAVE_IMPORT_GUID, 1, + [import_guid() is available]) + ]) + ]) +]) + + + diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 1ac442785ee3f..90776194c415f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -214,6 +214,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_MMAP_ASSERT_WRITE_LOCKED AC_AMDGPU_PID_TYPE AC_AMDGPU_FOLLOW_PFN + AC_AMDGPU_IMPORT_GUID AC_AMDGPU_LIST_CMP_FUNC_IS_CONST_PARAM AC_AMDGPU_DMA_FENCE_OPS_SET_DEADLINE AC_AMDGPU_DRM_SHOW_FDINFO diff --git a/include/kcl/kcl_uuid.h b/include/kcl/kcl_uuid.h new file mode 100644 index 0000000000000..be6580926dabc --- /dev/null +++ b/include/kcl/kcl_uuid.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: MIT */ +#ifndef KCL_KCL_UUID_H +#define KCL_KCL_UUID_H + +#include + +#ifndef HAVE_IMPORT_GUID +static inline void import_guid(guid_t *dst, const __u8 *src) +{ + memcpy(dst, src, sizeof(guid_t)); +} + +static inline void export_guid(__u8 *dst, const guid_t *src) +{ + memcpy(dst, src, sizeof(guid_t)); +} +#endif + +#endif \ No newline at end of file From ef0325f8f1b93fd2d0dfe048c012beee7b751e1f Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 5 Sep 2024 17:17:04 +0800 Subject: [PATCH 1469/1868] drm/amdkcl: test struct drm_dp_mst_branch has guid_t It's caused by ea612cbee8cea66d71922f446cdd3223636e1df2 "drm/amd/display: switch to guid_gen() to generate valid GUIDs" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + .../amd/dkms/m4/struct_drm_dp_mst_branch.m4 | 21 +++++++++++++++++++ 4 files changed, 29 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/struct_drm_dp_mst_branch.m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index c5962617fa433..554e59f2b9807 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2683,7 +2683,11 @@ static void resume_mst_branch_status(struct drm_dp_mst_topology_mgr *mgr) } } +#ifdef HAVE_DRM_DP_MST_BRANCH_GUID_T guid_copy(&mgr->mst_primary->guid, &guid); +#else + memcpy(mgr->mst_primary->guid, &guid, 16); +#endif out_fail: mutex_unlock(&mgr->lock); diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 91b03ecf5768a..2a67a341b8dbc 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -353,6 +353,9 @@ /* drm_dp_mst_atomic_enable_dsc() wants 5args */ /* #undef HAVE_DRM_DP_MST_ATOMIC_ENABLE_DSC_WITH_5_ARGS */ +/* the guid of struct drm_dp_mst_branch is guid_t */ +#define HAVE_DRM_DP_MST_BRANCH_GUID_T 1 + /* drm_dp_mst_connector_early_unregister() is available */ #define HAVE_DRM_DP_MST_CONNECTOR_EARLY_UNREGISTER 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 90776194c415f..aea55240b6724 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -215,6 +215,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_PID_TYPE AC_AMDGPU_FOLLOW_PFN AC_AMDGPU_IMPORT_GUID + AC_AMDGPU_DRM_DP_MST_BRANCH_GUID_T AC_AMDGPU_LIST_CMP_FUNC_IS_CONST_PARAM AC_AMDGPU_DMA_FENCE_OPS_SET_DEADLINE AC_AMDGPU_DRM_SHOW_FDINFO diff --git a/drivers/gpu/drm/amd/dkms/m4/struct_drm_dp_mst_branch.m4 b/drivers/gpu/drm/amd/dkms/m4/struct_drm_dp_mst_branch.m4 new file mode 100644 index 0000000000000..753914f3cc392 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/struct_drm_dp_mst_branch.m4 @@ -0,0 +1,21 @@ +dnl # +dnl # v5.6-rc7-127-gd01cd62400b3 +dnl # uuid: Add inline helpers to import / export UUIDs +dnl # +AC_DEFUN([AC_AMDGPU_DRM_DP_MST_BRANCH_GUID_T], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_dp_mst_branch mst_primary; + const guid_t guid; + guid_copy(&mst_primary.guid, &guid); + ],[ + AC_DEFINE(HAVE_DRM_DP_MST_BRANCH_GUID_T, 1, + [the guid of struct drm_dp_mst_branch is guid_t]) + ]) + ]) +]) + + + From 2febc5ccc0dda32aa13f6e43fe19430475943a59 Mon Sep 17 00:00:00 2001 From: Hamza Mahfooz Date: Thu, 25 Jul 2024 16:51:08 -0400 Subject: [PATCH 1470/1868] drm/vblank: add dynamic per-crtc vblank configuration support We would like to be able to enable vblank_disable_immediate unconditionally, however there are a handful of cases where a small off delay is necessary (e.g. with PSR enabled). So, we would like to be able to adjust the vblank off delay and disable imminent values dynamically for a given CRTC. Since, it will allow drivers to apply static screen optimizations more quickly and consequently allow users to benefit more so from the power savings afforded by the aforementioned optimizations, while avoiding issues in cases where an off delay is still warranted. In particular, the PSR case requires a small off delay of 2 frames, otherwise display firmware isn't able to keep up with all of the requests made to amdgpu. So, introduce drm_crtc_vblank_on_config() which is like drm_crtc_vblank_on(), but it allows drivers to specify the vblank CRTC configuration before enabling vblanking support for a given CRTC. Signed-off-by: Hamza Mahfooz Acked-by: Daniel Vetter Link: https://patchwork.freedesktop.org/patch/msgid/20240725205109.209743-1-hamza.mahfooz@amd.com (cherry picked from commit 0d5040e406d2c4404d26b841c4aa34cec0bf1088) --- drivers/gpu/drm/drm_vblank.c | 81 ++++++++++++++++++++++++++---------- include/drm/drm_device.h | 5 ++- include/drm/drm_vblank.h | 37 +++++++++++++++- 3 files changed, 97 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/drm_vblank.c b/drivers/gpu/drm/drm_vblank.c index cc3571e25a9ac..c6b4cd77df729 100644 --- a/drivers/gpu/drm/drm_vblank.c +++ b/drivers/gpu/drm/drm_vblank.c @@ -131,7 +131,7 @@ * guaranteed to be enabled. * * On many hardware disabling the vblank interrupt cannot be done in a race-free - * manner, see &drm_driver.vblank_disable_immediate and + * manner, see &drm_vblank_crtc_config.disable_immediate and * &drm_driver.max_vblank_count. In that case the vblank core only disables the * vblanks after a timer has expired, which can be configured through the * ``vblankoffdelay`` module parameter. @@ -1241,6 +1241,7 @@ EXPORT_SYMBOL(drm_crtc_vblank_get); void drm_vblank_put(struct drm_device *dev, unsigned int pipe) { struct drm_vblank_crtc *vblank = drm_vblank_crtc(dev, pipe); + int vblank_offdelay = vblank->config.offdelay_ms; if (drm_WARN_ON(dev, pipe >= dev->num_crtcs)) return; @@ -1250,13 +1251,13 @@ void drm_vblank_put(struct drm_device *dev, unsigned int pipe) /* Last user schedules interrupt disable */ if (atomic_dec_and_test(&vblank->refcount)) { - if (drm_vblank_offdelay == 0) + if (!vblank_offdelay) return; - else if (drm_vblank_offdelay < 0) + else if (vblank_offdelay < 0) vblank_disable_fn(&vblank->disable_timer); - else if (!dev->vblank_disable_immediate) + else if (!vblank->config.disable_immediate) mod_timer(&vblank->disable_timer, - jiffies + ((drm_vblank_offdelay * HZ)/1000)); + jiffies + ((vblank_offdelay * HZ) / 1000)); } } @@ -1265,7 +1266,8 @@ void drm_vblank_put(struct drm_device *dev, unsigned int pipe) * @crtc: which counter to give up * * Release ownership of a given vblank counter, turning off interrupts - * if possible. Disable interrupts after drm_vblank_offdelay milliseconds. + * if possible. Disable interrupts after &drm_vblank_crtc_config.offdelay_ms + * milliseconds. */ void drm_crtc_vblank_put(struct drm_crtc *crtc) { @@ -1466,16 +1468,20 @@ void drm_crtc_set_max_vblank_count(struct drm_crtc *crtc, EXPORT_SYMBOL(drm_crtc_set_max_vblank_count); /** - * drm_crtc_vblank_on - enable vblank events on a CRTC + * drm_crtc_vblank_on_config - enable vblank events on a CRTC with custom + * configuration options * @crtc: CRTC in question + * @config: Vblank configuration value * - * This functions restores the vblank interrupt state captured with - * drm_crtc_vblank_off() again and is generally called when enabling @crtc. Note - * that calls to drm_crtc_vblank_on() and drm_crtc_vblank_off() can be - * unbalanced and so can also be unconditionally called in driver load code to - * reflect the current hardware state of the crtc. + * See drm_crtc_vblank_on(). In addition, this function allows you to provide a + * custom vblank configuration for a given CRTC. + * + * Note that @config is copied, the pointer does not need to stay valid beyond + * this function call. For details of the parameters see + * struct drm_vblank_crtc_config. */ -void drm_crtc_vblank_on(struct drm_crtc *crtc) +void drm_crtc_vblank_on_config(struct drm_crtc *crtc, + const struct drm_vblank_crtc_config *config) { struct drm_device *dev = crtc->dev; unsigned int pipe = drm_crtc_index(crtc); @@ -1488,6 +1494,8 @@ void drm_crtc_vblank_on(struct drm_crtc *crtc) drm_dbg_vbl(dev, "crtc %d, vblank enabled %d, inmodeset %d\n", pipe, vblank->enabled, vblank->inmodeset); + vblank->config = *config; + /* Drop our private "prevent drm_vblank_get" refcount */ if (vblank->inmodeset) { atomic_dec(&vblank->refcount); @@ -1500,10 +1508,33 @@ void drm_crtc_vblank_on(struct drm_crtc *crtc) * re-enable interrupts if there are users left, or the * user wishes vblank interrupts to be enabled all the time. */ - if (atomic_read(&vblank->refcount) != 0 || drm_vblank_offdelay == 0) + if (atomic_read(&vblank->refcount) != 0 || !vblank->config.offdelay_ms) drm_WARN_ON(dev, drm_vblank_enable(dev, pipe)); spin_unlock_irq(&dev->vbl_lock); } +EXPORT_SYMBOL(drm_crtc_vblank_on_config); + +/** + * drm_crtc_vblank_on - enable vblank events on a CRTC + * @crtc: CRTC in question + * + * This functions restores the vblank interrupt state captured with + * drm_crtc_vblank_off() again and is generally called when enabling @crtc. Note + * that calls to drm_crtc_vblank_on() and drm_crtc_vblank_off() can be + * unbalanced and so can also be unconditionally called in driver load code to + * reflect the current hardware state of the crtc. + * + * Note that unlike in drm_crtc_vblank_on_config(), default values are used. + */ +void drm_crtc_vblank_on(struct drm_crtc *crtc) +{ + const struct drm_vblank_crtc_config config = { + .offdelay_ms = drm_vblank_offdelay, + .disable_immediate = crtc->dev->vblank_disable_immediate + }; + + drm_crtc_vblank_on_config(crtc, &config); +} EXPORT_SYMBOL(drm_crtc_vblank_on); static void drm_vblank_restore(struct drm_device *dev, unsigned int pipe) @@ -1556,16 +1587,21 @@ static void drm_vblank_restore(struct drm_device *dev, unsigned int pipe) * * Note that drivers must have race-free high-precision timestamping support, * i.e. &drm_crtc_funcs.get_vblank_timestamp must be hooked up and - * &drm_driver.vblank_disable_immediate must be set to indicate the + * &drm_vblank_crtc_config.disable_immediate must be set to indicate the * time-stamping functions are race-free against vblank hardware counter * increments. */ void drm_crtc_vblank_restore(struct drm_crtc *crtc) { - WARN_ON_ONCE(!crtc->funcs->get_vblank_timestamp); - WARN_ON_ONCE(!crtc->dev->vblank_disable_immediate); + struct drm_device *dev = crtc->dev; + unsigned int pipe = drm_crtc_index(crtc); + struct drm_vblank_crtc *vblank = drm_vblank_crtc(dev, pipe); + + drm_WARN_ON_ONCE(dev, !crtc->funcs->get_vblank_timestamp); + drm_WARN_ON_ONCE(dev, vblank->inmodeset); + drm_WARN_ON_ONCE(dev, !vblank->config.disable_immediate); - drm_vblank_restore(crtc->dev, drm_crtc_index(crtc)); + drm_vblank_restore(dev, pipe); } EXPORT_SYMBOL(drm_crtc_vblank_restore); @@ -1754,7 +1790,7 @@ int drm_wait_vblank_ioctl(struct drm_device *dev, void *data, /* If the counter is currently enabled and accurate, short-circuit * queries to return the cached timestamp of the last vblank. */ - if (dev->vblank_disable_immediate && + if (vblank->config.disable_immediate && drm_wait_vblank_is_query(vblwait) && READ_ONCE(vblank->enabled)) { drm_wait_vblank_reply(dev, pipe, &vblwait->reply); @@ -1918,8 +1954,8 @@ bool drm_handle_vblank(struct drm_device *dev, unsigned int pipe) * been signaled. The disable has to be last (after * drm_handle_vblank_events) so that the timestamp is always accurate. */ - disable_irq = (dev->vblank_disable_immediate && - drm_vblank_offdelay > 0 && + disable_irq = (vblank->config.disable_immediate && + vblank->config.offdelay_ms > 0 && !atomic_read(&vblank->refcount)); drm_handle_vblank_events(dev, pipe); @@ -1992,7 +2028,8 @@ int drm_crtc_get_sequence_ioctl(struct drm_device *dev, void *data, pipe = drm_crtc_index(crtc); vblank = drm_crtc_vblank_crtc(crtc); - vblank_enabled = dev->vblank_disable_immediate && READ_ONCE(vblank->enabled); + vblank_enabled = READ_ONCE(vblank->config.disable_immediate) && + READ_ONCE(vblank->enabled); if (!vblank_enabled) { ret = drm_crtc_vblank_get(crtc); diff --git a/include/drm/drm_device.h b/include/drm/drm_device.h index 63767cf24371b..c91f87b5242d7 100644 --- a/include/drm/drm_device.h +++ b/include/drm/drm_device.h @@ -213,8 +213,9 @@ struct drm_device { * This can be set to true it the hardware has a working vblank counter * with high-precision timestamping (otherwise there are races) and the * driver uses drm_crtc_vblank_on() and drm_crtc_vblank_off() - * appropriately. See also @max_vblank_count and - * &drm_crtc_funcs.get_vblank_counter. + * appropriately. Also, see @max_vblank_count, + * &drm_crtc_funcs.get_vblank_counter and + * &drm_vblank_crtc_config.disable_immediate. */ bool vblank_disable_immediate; diff --git a/include/drm/drm_vblank.h b/include/drm/drm_vblank.h index c8f829b4307cb..151ab1e85b1b7 100644 --- a/include/drm/drm_vblank.h +++ b/include/drm/drm_vblank.h @@ -78,6 +78,31 @@ struct drm_pending_vblank_event { } event; }; +/** + * struct drm_vblank_crtc_config - vblank configuration for a CRTC + */ +struct drm_vblank_crtc_config { + /** + * @offdelay_ms: Vblank off delay in ms, used to determine how long + * &drm_vblank_crtc.disable_timer waits before disabling. + * + * Defaults to the value of drm_vblank_offdelay in drm_crtc_vblank_on(). + */ + int offdelay_ms; + + /** + * @disable_immediate: See &drm_device.vblank_disable_immediate + * for the exact semantics of immediate vblank disabling. + * + * Additionally, this tracks the disable immediate value per crtc, just + * in case it needs to differ from the default value for a given device. + * + * Defaults to the value of &drm_device.vblank_disable_immediate in + * drm_crtc_vblank_on(). + */ + bool disable_immediate; +}; + /** * struct drm_vblank_crtc - vblank tracking for a CRTC * @@ -99,8 +124,8 @@ struct drm_vblank_crtc { wait_queue_head_t queue; /** * @disable_timer: Disable timer for the delayed vblank disabling - * hysteresis logic. Vblank disabling is controlled through the - * drm_vblank_offdelay module option and the setting of the + * hysteresis logic. Vblank disabling is controlled through + * &drm_vblank_crtc_config.offdelay_ms and the setting of the * &drm_device.max_vblank_count value. */ struct timer_list disable_timer; @@ -198,6 +223,12 @@ struct drm_vblank_crtc { */ struct drm_display_mode hwmode; + /** + * @config: Stores vblank configuration values for a given CRTC. + * Also, see drm_crtc_vblank_on_config(). + */ + struct drm_vblank_crtc_config config; + /** * @enabled: Tracks the enabling state of the corresponding &drm_crtc to * avoid double-disabling and hence corrupting saved state. Needed by @@ -247,6 +278,8 @@ void drm_wait_one_vblank(struct drm_device *dev, unsigned int pipe); void drm_crtc_wait_one_vblank(struct drm_crtc *crtc); void drm_crtc_vblank_off(struct drm_crtc *crtc); void drm_crtc_vblank_reset(struct drm_crtc *crtc); +void drm_crtc_vblank_on_config(struct drm_crtc *crtc, + const struct drm_vblank_crtc_config *config); void drm_crtc_vblank_on(struct drm_crtc *crtc); u64 drm_crtc_accurate_vblank_count(struct drm_crtc *crtc); void drm_crtc_vblank_restore(struct drm_crtc *crtc); From 1d33875abd1f6a172643c91284718d6821b40baf Mon Sep 17 00:00:00 2001 From: Hamza Mahfooz Date: Thu, 15 Aug 2024 14:37:27 -0400 Subject: [PATCH 1471/1868] drm/amd/display: use new vblank enable policy for DCN35+ Hook up drm_crtc_vblank_on_config() in amdgpu_dm. So, that we can enable PSR and other static screen optimizations more quickly, while avoiding stuttering issues that are accompanied by the following dmesg error: [drm:dc_dmub_srv_wait_idle [amdgpu]] *ERROR* Error waiting for DMUB idle: status=3 This also allows us to mimic how vblanking is handled by the Windows amdgpu driver. Specifically, we wait two idle frames before disabling the vblank timer there. Reviewed-by: Harry Wentland Signed-off-by: Hamza Mahfooz Link: https://patchwork.freedesktop.org/patch/msgid/20240822161856.174600-2-hamza.mahfooz@amd.com (cherry picked from commit 537ef0f8889761ffe3a6cb4a7bda4de47fe2d69b) --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 38 +++++++++++++------ 1 file changed, 26 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 554e59f2b9807..ab26db540c219 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -5083,12 +5083,6 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev) if (psr_feature_enabled) amdgpu_dm_set_psr_caps(link); - - /* TODO: Fix vblank control helpers to delay PSR entry to allow this when - * PSR is also supported. - */ - if (link->psr_settings.psr_feature_enabled) - adev_to_drm(adev)->vblank_disable_immediate = false; } } amdgpu_set_panel_orientation(&aconnector->base); @@ -8540,12 +8534,32 @@ static int amdgpu_dm_encoder_init(struct drm_device *dev, static void manage_dm_interrupts(struct amdgpu_device *adev, struct amdgpu_crtc *acrtc, - bool enable) + struct dm_crtc_state *acrtc_state) { - if (enable) - drm_crtc_vblank_on(&acrtc->base); - else + struct drm_vblank_crtc_config config = {0}; + struct dc_crtc_timing *timing; + int offdelay; + + if (acrtc_state) { + if (amdgpu_ip_version(adev, DCE_HWIP, 0) < + IP_VERSION(3, 5, 0)) { + drm_crtc_vblank_on(&acrtc->base); + } else { + timing = &acrtc_state->stream->timing; + + /* at least 2 frames */ + offdelay = DIV64_U64_ROUND_UP((u64)20 * + timing->v_total * + timing->h_total, + timing->pix_clk_100hz); + + config.offdelay_ms = offdelay ?: 30; + drm_crtc_vblank_on_config(&acrtc->base, + &config); + } + } else { drm_crtc_vblank_off(&acrtc->base); + } } static void dm_update_pflip_irq_state(struct amdgpu_device *adev, @@ -9609,7 +9623,7 @@ static void amdgpu_dm_commit_streams(struct drm_atomic_state *state, if (old_crtc_state->active && (!new_crtc_state->active || drm_atomic_crtc_needs_modeset(new_crtc_state))) { - manage_dm_interrupts(adev, acrtc, false); + manage_dm_interrupts(adev, acrtc, NULL); dc_stream_release(dm_old_crtc_state->stream); } } @@ -10145,7 +10159,7 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state) drm_atomic_crtc_needs_modeset(new_crtc_state))) { dc_stream_retain(dm_new_crtc_state->stream); acrtc->dm_irq_params.stream = dm_new_crtc_state->stream; - manage_dm_interrupts(adev, acrtc, true); + manage_dm_interrupts(adev, acrtc, dm_new_crtc_state); } /* Handle vrr on->off / off->on transitions */ amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, dm_new_crtc_state); From 21f3b2655d9169983a2a6cf3d23d02d8e8ede17c Mon Sep 17 00:00:00 2001 From: Hamza Mahfooz Date: Tue, 20 Aug 2024 13:53:23 -0400 Subject: [PATCH 1472/1868] drm/amd/display: use a more lax vblank enable policy for DCN35+ Ideally, we want to enable immediate vblank disable, when possible and we should be able to do so on DCN35+, if PSR isn't supported by a given CRTC. Suggested-by: Leo Li Reviewed-by: Harry Wentland Signed-off-by: Hamza Mahfooz Link: https://patchwork.freedesktop.org/patch/msgid/20240822161856.174600-3-hamza.mahfooz@amd.com (cherry picked from commit e45b6716de4bf06b628a9f3559f7fc8dd5e94d58) --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index ab26db540c219..e95fcfd75e66a 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8544,7 +8544,8 @@ static void manage_dm_interrupts(struct amdgpu_device *adev, if (amdgpu_ip_version(adev, DCE_HWIP, 0) < IP_VERSION(3, 5, 0)) { drm_crtc_vblank_on(&acrtc->base); - } else { + } else if (acrtc_state->stream->link->psr_settings.psr_version < + DC_PSR_VERSION_UNSUPPORTED) { timing = &acrtc_state->stream->timing; /* at least 2 frames */ @@ -8556,6 +8557,10 @@ static void manage_dm_interrupts(struct amdgpu_device *adev, config.offdelay_ms = offdelay ?: 30; drm_crtc_vblank_on_config(&acrtc->base, &config); + } else { + config.disable_immediate = true; + drm_crtc_vblank_on_config(&acrtc->base, + &config); } } else { drm_crtc_vblank_off(&acrtc->base); From ace18dc50fdbe9f8a66621cbb87a46097af39bc0 Mon Sep 17 00:00:00 2001 From: Hamza Mahfooz Date: Thu, 22 Aug 2024 11:58:22 -0400 Subject: [PATCH 1473/1868] drm/amd/display: use a more lax vblank enable policy for older ASICs Ideally, we want to drop the legacy vblank enable for older ASICs. This should be possible now, since we can now specify how many frames we need to wait before disabling vblanking instead of being forced to either choose between no delay (which can still be buggy) and drm_vblank_offdelay (which is much longer by default than is required on AMD hardware). Suggested-by: Leo Li Reviewed-by: Harry Wentland Signed-off-by: Hamza Mahfooz Link: https://patchwork.freedesktop.org/patch/msgid/20240822161856.174600-4-hamza.mahfooz@amd.com (cherry picked from commit 58a261bfc96763a851cb48b203ed57da37e157b8) --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index e95fcfd75e66a..8614b47d06523 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8542,10 +8542,9 @@ static void manage_dm_interrupts(struct amdgpu_device *adev, if (acrtc_state) { if (amdgpu_ip_version(adev, DCE_HWIP, 0) < - IP_VERSION(3, 5, 0)) { - drm_crtc_vblank_on(&acrtc->base); - } else if (acrtc_state->stream->link->psr_settings.psr_version < - DC_PSR_VERSION_UNSUPPORTED) { + IP_VERSION(3, 5, 0) || + acrtc_state->stream->link->psr_settings.psr_version < + DC_PSR_VERSION_UNSUPPORTED) { timing = &acrtc_state->stream->timing; /* at least 2 frames */ @@ -8555,13 +8554,12 @@ static void manage_dm_interrupts(struct amdgpu_device *adev, timing->pix_clk_100hz); config.offdelay_ms = offdelay ?: 30; - drm_crtc_vblank_on_config(&acrtc->base, - &config); } else { config.disable_immediate = true; - drm_crtc_vblank_on_config(&acrtc->base, - &config); } + + drm_crtc_vblank_on_config(&acrtc->base, + &config); } else { drm_crtc_vblank_off(&acrtc->base); } From 66f11395d8b2f33af83b3cbe7f00b3cdbf02f437 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 6 Sep 2024 16:17:17 +0800 Subject: [PATCH 1474/1868] drm/amdkcl: test drm_vblank_crtc_config is available It's caused by 786628e0bf493cabcaa1c7a5ef5c27e2fa530c18 "drm/amd/display: use new vblank enable policy for DCN35+" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 7 +++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../amd/dkms/m4/drm_vblank_crtc_config .m4 | 19 +++++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 30 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_vblank_crtc_config .m4 diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 8614b47d06523..76b6172d8e16c 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -8536,6 +8536,7 @@ static void manage_dm_interrupts(struct amdgpu_device *adev, struct amdgpu_crtc *acrtc, struct dm_crtc_state *acrtc_state) { +#ifdef HAVE_DRM_VBLANK_CRTC_CONFIG struct drm_vblank_crtc_config config = {0}; struct dc_crtc_timing *timing; int offdelay; @@ -8563,6 +8564,12 @@ static void manage_dm_interrupts(struct amdgpu_device *adev, } else { drm_crtc_vblank_off(&acrtc->base); } +#else + if (acrtc_state) + drm_crtc_vblank_on(&acrtc->base); + else + drm_crtc_vblank_off(&acrtc->base); +#endif } static void dm_update_pflip_irq_state(struct amdgpu_device *adev, diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 2a67a341b8dbc..af1670609d2f2 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -614,6 +614,9 @@ /* Define to 1 if you have the header file. */ #define HAVE_DRM_TASK_BARRIER_H 1 +/* drm_vblank_crtc_config is available */ +/* #undef HAVE_DRM_VBLANK_CRTC_CONFIG */ + /* struct drm_vma_offset_node has readonly field */ /* #undef HAVE_DRM_VMA_OFFSET_NODE_READONLY_FIELD */ diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_vblank_crtc_config .m4 b/drivers/gpu/drm/amd/dkms/m4/drm_vblank_crtc_config .m4 new file mode 100644 index 0000000000000..90ef0ba2c3cc5 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_vblank_crtc_config .m4 @@ -0,0 +1,19 @@ +dnl # +dnl # v5.11-20-g2d24dd5798d0 +dnl # rbtree: Add generic add and find helpers +dnl # +AC_DEFUN([AC_AMDGPU_DRM_VBLANK_CRTC_CONFIG], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE([ + #include + ],[ + struct drm_vblank_crtc_config config; + ],[ + AC_DEFINE(HAVE_DRM_VBLANK_CRTC_CONFIG, 1, + [drm_vblank_crtc_config is available]) + ]) + ]) +]) + + + diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index aea55240b6724..7c525cf5e5f0f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -105,6 +105,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_CONNECTOR_HAVE_HDR_SINK_METADATA AC_AMDGPU_DRM_DP_MST_TOPOLOGY_MGR_INIT AC_AMDGPU_DRM_MODE_CONFIG + AC_AMDGPU_DRM_VBLANK_CRTC_CONFIG AC_AMDGPU_DRM_CONNECTOR_STATE_HDCP_CONTENT_TYPE AC_AMDGPU_DRM_HDCP_UPDATE_CONTENT_PROTECTION AC_AMDGPU_DRM_MODE_CREATE_COLORSPACE_PROPERTY_FUNCS From cf782e1b6e71d5eb3ff9ecfdd9481fa02e842028 Mon Sep 17 00:00:00 2001 From: David Belanger Date: Fri, 23 Aug 2024 13:50:03 -0400 Subject: [PATCH 1475/1868] drm/amdkfd: Add cache line size info Populate cache line size info in topology based on information from IP discovery table. Signed-off-by: David Belanger Reviewed-by: Sreekant Somasekharan --- drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c index dd37a8c173812..d1fa06ad42781 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c @@ -1345,7 +1345,8 @@ static int kfd_fill_gpu_cache_info_from_gfx_config(struct kfd_dev *kdev, pcache_info[i].flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE); - pcache_info[0].num_cu_shared = adev->gfx.config.gc_num_tcp_per_wpg / 2; + pcache_info[i].num_cu_shared = adev->gfx.config.gc_num_tcp_per_wpg / 2; + pcache_info[i].cache_line_size = adev->gfx.config.gc_tcp_cache_line_size; i++; } /* Scalar L1 Instruction Cache per SQC */ @@ -1357,6 +1358,7 @@ static int kfd_fill_gpu_cache_info_from_gfx_config(struct kfd_dev *kdev, CRAT_CACHE_FLAGS_INST_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE); pcache_info[i].num_cu_shared = adev->gfx.config.gc_num_sqc_per_wgp * 2; + pcache_info[i].cache_line_size = adev->gfx.config.gc_instruction_cache_line_size; i++; } /* Scalar L1 Data Cache per SQC */ @@ -1367,6 +1369,7 @@ static int kfd_fill_gpu_cache_info_from_gfx_config(struct kfd_dev *kdev, CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE); pcache_info[i].num_cu_shared = adev->gfx.config.gc_num_sqc_per_wgp * 2; + pcache_info[i].cache_line_size = adev->gfx.config.gc_scalar_data_cache_line_size; i++; } /* GL1 Data Cache per SA */ @@ -1379,6 +1382,7 @@ static int kfd_fill_gpu_cache_info_from_gfx_config(struct kfd_dev *kdev, CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE); pcache_info[i].num_cu_shared = adev->gfx.config.max_cu_per_sh; + pcache_info[i].cache_line_size = 0; i++; } /* L2 Data Cache per GPU (Total Tex Cache) */ @@ -1389,6 +1393,7 @@ static int kfd_fill_gpu_cache_info_from_gfx_config(struct kfd_dev *kdev, CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE); pcache_info[i].num_cu_shared = adev->gfx.config.max_cu_per_sh; + pcache_info[i].cache_line_size = adev->gfx.config.gc_tcc_cache_line_size; i++; } /* L3 Data Cache per GPU */ @@ -1399,6 +1404,7 @@ static int kfd_fill_gpu_cache_info_from_gfx_config(struct kfd_dev *kdev, CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE); pcache_info[i].num_cu_shared = adev->gfx.config.max_cu_per_sh; + pcache_info[i].cache_line_size = 0; i++; } return i; From 33cb02153bb07f8365103f299fdb19fbcba69163 Mon Sep 17 00:00:00 2001 From: Lang Yu Date: Sun, 1 Sep 2024 08:56:07 -0400 Subject: [PATCH 1476/1868] drm/amdgpu: fix invalid fence handling in amdgpu_vm_tlb_flush MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit CPU based update doesn't produce a fence, handle such cases properly. Fixes: 5a1c27951966 ("drm/amdgpu: implement TLB flush fence") Signed-off-by: Lang Yu Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 5aa1cb7f84974..f544d1afa4e38 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -923,10 +923,12 @@ amdgpu_vm_tlb_flush(struct amdgpu_vm_update_params *params, { struct amdgpu_vm *vm = params->vm; - if (!fence || !*fence) + tlb_cb->vm = vm; + if (!fence || !*fence) { + amdgpu_vm_tlb_seq_cb(NULL, &tlb_cb->cb); return; + } - tlb_cb->vm = vm; if (!dma_fence_add_callback(*fence, &tlb_cb->cb, amdgpu_vm_tlb_seq_cb)) { dma_fence_put(vm->last_tlb_flush); From a09e5d1ea71f92296e76d21eebbecb02c850e358 Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Wed, 28 Aug 2024 16:55:23 +0530 Subject: [PATCH 1477/1868] drm/amd/display: Add missing kdoc entry for 'bs_coeffs_updated' in dpp401_dscl_program_isharp This commit addresses a missing kdoc for the 'bs_coeffs_updated' parameter in the 'dpp401_dscl_program_isharp' function. The 'bs_coeffs_updated' is a flag indicating whether the Blur and Scale Coefficients have been updated. The 'dpp401_dscl_program_isharp' function is responsible for programming the isharp, which includes setting the isharp filter, noise gain, and blur and scale coefficients. If the 'bs_coeffs_updated' flag is set to true, the function updates the blur and scale coefficients. Fixes the below with gcc W=1: drivers/gpu/drm/amd/amdgpu/../display/dc/dpp/dcn401/dcn401_dpp_dscl.c:961: warning: Function parameter or struct member 'bs_coeffs_updated' not described in 'dpp401_dscl_program_isharp' Cc: Tom Chung Cc: Rodrigo Siqueira Cc: Roman Li Cc: Alex Hung Cc: Aurabindo Pillai Cc: Harry Wentland Cc: Hamza Mahfooz Signed-off-by: Srinivasan Shanmugam Suggested-by: Tom Chung Reviewed-by: Tom Chung --- drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c index 01f98139292e7..8564369f09b48 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c @@ -951,6 +951,7 @@ static void dpp401_dscl_set_isharp_filter( * * @dpp_base: High level DPP struct * @scl_data: scalaer_data info + * @bs_coeffs_updated: Blur and Scale Coefficients update flag * * This is the primary function to program isharp * From 8a10b9c0fe8010769a3b4799f1b927259fdecb72 Mon Sep 17 00:00:00 2001 From: Colin Ian King Date: Wed, 28 Aug 2024 10:32:50 +0100 Subject: [PATCH 1478/1868] drm/amd/display: Fix spelling mistake "recompte" -> "recompute" There is a spelling mistake in a DRM_DEBUG_DRIVER message. Fix it. Signed-off-by: Colin Ian King Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index e5e5a196aafc4..43eb0b66bb41f 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -1559,7 +1559,7 @@ static bool is_dsc_need_re_compute( if (new_crtc_state->enable && new_crtc_state->active) { if (new_crtc_state->mode_changed || new_crtc_state->active_changed || new_crtc_state->connectors_changed) { - DRM_DEBUG_DRIVER("%s:%d MST_DSC dsc recompte required." + DRM_DEBUG_DRIVER("%s:%d MST_DSC dsc recompute required." "stream 0x%p in new dc_state\n", __func__, __LINE__, stream); is_dsc_need_re_compute = true; From ea1f7ea8e9c261f88bb10b531682838f53fa39b8 Mon Sep 17 00:00:00 2001 From: Peng Liu Date: Fri, 30 Aug 2024 15:25:54 +0800 Subject: [PATCH 1479/1868] drm/amdgpu: add raven1 gfxoff quirk Fix screen corruption with openkylin. Link: https://bbs.openkylin.top/t/topic/171497 Signed-off-by: Peng Liu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 9d2333b2a610f..ec4bc9ba1169a 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -1345,6 +1345,8 @@ static const struct amdgpu_gfxoff_quirk amdgpu_gfxoff_quirk_list[] = { { 0x1002, 0x15dd, 0x1002, 0x15dd, 0xc6 }, /* Apple MacBook Pro (15-inch, 2019) Radeon Pro Vega 20 4 GB */ { 0x1002, 0x69af, 0x106b, 0x019a, 0xc0 }, + /* https://bbs.openkylin.top/t/topic/171497 */ + { 0x1002, 0x15d8, 0x19e5, 0x3e14, 0xc2 }, { 0, 0, 0, 0, 0 }, }; From 297e6e12fd20a2c8b6e2c000a2998acb90f9dc4a Mon Sep 17 00:00:00 2001 From: Peng Liu Date: Fri, 30 Aug 2024 15:27:08 +0800 Subject: [PATCH 1480/1868] drm/amdgpu: enable gfxoff quirk on HP 705G4 Enabling gfxoff quirk results in perfectly usable graphical user interface on HP 705G4 DM with R5 2400G. Without the quirk, X server is completely unusable as every few seconds there is gpu reset due to ring gfx timeout. Signed-off-by: Peng Liu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index ec4bc9ba1169a..33fc97a88ce7b 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -1347,6 +1347,8 @@ static const struct amdgpu_gfxoff_quirk amdgpu_gfxoff_quirk_list[] = { { 0x1002, 0x69af, 0x106b, 0x019a, 0xc0 }, /* https://bbs.openkylin.top/t/topic/171497 */ { 0x1002, 0x15d8, 0x19e5, 0x3e14, 0xc2 }, + /* HP 705G4 DM with R5 2400G */ + { 0x1002, 0x15dd, 0x103c, 0x8464, 0xd6 }, { 0, 0, 0, 0, 0 }, }; From eb397abbed43db2fe1cb954b6dd7c348082dda3e Mon Sep 17 00:00:00 2001 From: Li Zetao Date: Fri, 30 Aug 2024 09:22:14 +0800 Subject: [PATCH 1481/1868] drm/amd: use clamp() in amdgpu_pll_get_fb_ref_div() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When it needs to get a value within a certain interval, using clamp() makes the code easier to understand than min(max()). Reviewed-by: Christian König Signed-off-by: Li Zetao Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c index 0bb2466d539a9..675aa138ea112 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c @@ -94,7 +94,7 @@ static void amdgpu_pll_get_fb_ref_div(struct amdgpu_device *adev, unsigned int n ref_div_max = min(128 / post_div, ref_div_max); /* get matching reference and feedback divider */ - *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max); + *ref_div = clamp(DIV_ROUND_CLOSEST(den, post_div), 1u, ref_div_max); *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den); /* limit fb divider to its maximum */ From 3ef3fbc78281537251a26cad1c53ed6e87fee7fb Mon Sep 17 00:00:00 2001 From: Joseph Greathouse Date: Fri, 19 Jan 2024 20:01:50 -0600 Subject: [PATCH 1482/1868] drm/amdkfd: Add cache line sizes to KFD topology The KFD topology includes cache line size, but we have not been filling that information out unless we are parsing a CRAT table. Fill in this information for the devices where we have cache information structs, and pipe this information to the topology sysfs files. v2: squash in fix from Joe (Alex) Signed-off-by: Joseph Greathouse Acked-by: Alex Deucher Reviewed-by: Felix Kuehling Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 93 ++++++++++++++++++++++- drivers/gpu/drm/amd/amdkfd/kfd_crat.h | 1 + drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 2 + 3 files changed, 94 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c index d1fa06ad42781..7b2c408db75cf 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c @@ -55,6 +55,7 @@ static struct kfd_gpu_cache_info kaveri_cache_info[] = { /* TCP L1 Cache per CU */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -64,6 +65,7 @@ static struct kfd_gpu_cache_info kaveri_cache_info[] = { /* Scalar L1 Instruction Cache (in SQC module) per bank */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_INST_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -73,6 +75,7 @@ static struct kfd_gpu_cache_info kaveri_cache_info[] = { /* Scalar L1 Data Cache (in SQC module) per bank */ .cache_size = 8, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -88,6 +91,7 @@ static struct kfd_gpu_cache_info carrizo_cache_info[] = { /* TCP L1 Cache per CU */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -95,8 +99,9 @@ static struct kfd_gpu_cache_info carrizo_cache_info[] = { }, { /* Scalar L1 Instruction Cache (in SQC module) per bank */ - .cache_size = 8, + .cache_size = 32, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_INST_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -104,8 +109,9 @@ static struct kfd_gpu_cache_info carrizo_cache_info[] = { }, { /* Scalar L1 Data Cache (in SQC module) per bank. */ - .cache_size = 4, + .cache_size = 16, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -135,6 +141,7 @@ static struct kfd_gpu_cache_info vega10_cache_info[] = { /* TCP L1 Cache per CU */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -144,6 +151,7 @@ static struct kfd_gpu_cache_info vega10_cache_info[] = { /* Scalar L1 Instruction Cache per SQC */ .cache_size = 32, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_INST_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -153,6 +161,7 @@ static struct kfd_gpu_cache_info vega10_cache_info[] = { /* Scalar L1 Data Cache per SQC */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -162,6 +171,7 @@ static struct kfd_gpu_cache_info vega10_cache_info[] = { /* L2 Data Cache per GPU (Total Tex Cache) */ .cache_size = 4096, .cache_level = 2, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -174,6 +184,7 @@ static struct kfd_gpu_cache_info raven_cache_info[] = { /* TCP L1 Cache per CU */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -183,6 +194,7 @@ static struct kfd_gpu_cache_info raven_cache_info[] = { /* Scalar L1 Instruction Cache per SQC */ .cache_size = 32, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_INST_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -192,6 +204,7 @@ static struct kfd_gpu_cache_info raven_cache_info[] = { /* Scalar L1 Data Cache per SQC */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -201,6 +214,7 @@ static struct kfd_gpu_cache_info raven_cache_info[] = { /* L2 Data Cache per GPU (Total Tex Cache) */ .cache_size = 1024, .cache_level = 2, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -213,6 +227,7 @@ static struct kfd_gpu_cache_info renoir_cache_info[] = { /* TCP L1 Cache per CU */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -222,6 +237,7 @@ static struct kfd_gpu_cache_info renoir_cache_info[] = { /* Scalar L1 Instruction Cache per SQC */ .cache_size = 32, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_INST_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -231,6 +247,7 @@ static struct kfd_gpu_cache_info renoir_cache_info[] = { /* Scalar L1 Data Cache per SQC */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -240,6 +257,7 @@ static struct kfd_gpu_cache_info renoir_cache_info[] = { /* L2 Data Cache per GPU (Total Tex Cache) */ .cache_size = 1024, .cache_level = 2, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -252,6 +270,7 @@ static struct kfd_gpu_cache_info vega12_cache_info[] = { /* TCP L1 Cache per CU */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -261,6 +280,7 @@ static struct kfd_gpu_cache_info vega12_cache_info[] = { /* Scalar L1 Instruction Cache per SQC */ .cache_size = 32, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_INST_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -270,6 +290,7 @@ static struct kfd_gpu_cache_info vega12_cache_info[] = { /* Scalar L1 Data Cache per SQC */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -279,6 +300,7 @@ static struct kfd_gpu_cache_info vega12_cache_info[] = { /* L2 Data Cache per GPU (Total Tex Cache) */ .cache_size = 2048, .cache_level = 2, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -291,6 +313,7 @@ static struct kfd_gpu_cache_info vega20_cache_info[] = { /* TCP L1 Cache per CU */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -300,6 +323,7 @@ static struct kfd_gpu_cache_info vega20_cache_info[] = { /* Scalar L1 Instruction Cache per SQC */ .cache_size = 32, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_INST_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -309,6 +333,7 @@ static struct kfd_gpu_cache_info vega20_cache_info[] = { /* Scalar L1 Data Cache per SQC */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -318,6 +343,7 @@ static struct kfd_gpu_cache_info vega20_cache_info[] = { /* L2 Data Cache per GPU (Total Tex Cache) */ .cache_size = 8192, .cache_level = 2, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -330,6 +356,7 @@ static struct kfd_gpu_cache_info aldebaran_cache_info[] = { /* TCP L1 Cache per CU */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -339,6 +366,7 @@ static struct kfd_gpu_cache_info aldebaran_cache_info[] = { /* Scalar L1 Instruction Cache per SQC */ .cache_size = 32, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_INST_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -348,6 +376,7 @@ static struct kfd_gpu_cache_info aldebaran_cache_info[] = { /* Scalar L1 Data Cache per SQC */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -357,6 +386,7 @@ static struct kfd_gpu_cache_info aldebaran_cache_info[] = { /* L2 Data Cache per GPU (Total Tex Cache) */ .cache_size = 8192, .cache_level = 2, + .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -369,6 +399,7 @@ static struct kfd_gpu_cache_info navi10_cache_info[] = { /* TCP L1 Cache per CU */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -378,6 +409,7 @@ static struct kfd_gpu_cache_info navi10_cache_info[] = { /* Scalar L1 Instruction Cache per SQC */ .cache_size = 32, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_INST_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -387,6 +419,7 @@ static struct kfd_gpu_cache_info navi10_cache_info[] = { /* Scalar L1 Data Cache per SQC */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -396,6 +429,7 @@ static struct kfd_gpu_cache_info navi10_cache_info[] = { /* GL1 Data Cache per SA */ .cache_size = 128, .cache_level = 1, + .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -405,6 +439,7 @@ static struct kfd_gpu_cache_info navi10_cache_info[] = { /* L2 Data Cache per GPU (Total Tex Cache) */ .cache_size = 4096, .cache_level = 2, + .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -417,6 +452,7 @@ static struct kfd_gpu_cache_info vangogh_cache_info[] = { /* TCP L1 Cache per CU */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -426,6 +462,7 @@ static struct kfd_gpu_cache_info vangogh_cache_info[] = { /* Scalar L1 Instruction Cache per SQC */ .cache_size = 32, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_INST_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -435,6 +472,7 @@ static struct kfd_gpu_cache_info vangogh_cache_info[] = { /* Scalar L1 Data Cache per SQC */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -444,6 +482,7 @@ static struct kfd_gpu_cache_info vangogh_cache_info[] = { /* GL1 Data Cache per SA */ .cache_size = 128, .cache_level = 1, + .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -453,6 +492,7 @@ static struct kfd_gpu_cache_info vangogh_cache_info[] = { /* L2 Data Cache per GPU (Total Tex Cache) */ .cache_size = 1024, .cache_level = 2, + .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -465,6 +505,7 @@ static struct kfd_gpu_cache_info navi14_cache_info[] = { /* TCP L1 Cache per CU */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -474,6 +515,7 @@ static struct kfd_gpu_cache_info navi14_cache_info[] = { /* Scalar L1 Instruction Cache per SQC */ .cache_size = 32, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_INST_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -483,6 +525,7 @@ static struct kfd_gpu_cache_info navi14_cache_info[] = { /* Scalar L1 Data Cache per SQC */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -492,6 +535,7 @@ static struct kfd_gpu_cache_info navi14_cache_info[] = { /* GL1 Data Cache per SA */ .cache_size = 128, .cache_level = 1, + .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -501,6 +545,7 @@ static struct kfd_gpu_cache_info navi14_cache_info[] = { /* L2 Data Cache per GPU (Total Tex Cache) */ .cache_size = 2048, .cache_level = 2, + .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -513,6 +558,7 @@ static struct kfd_gpu_cache_info sienna_cichlid_cache_info[] = { /* TCP L1 Cache per CU */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -522,6 +568,7 @@ static struct kfd_gpu_cache_info sienna_cichlid_cache_info[] = { /* Scalar L1 Instruction Cache per SQC */ .cache_size = 32, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_INST_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -531,6 +578,7 @@ static struct kfd_gpu_cache_info sienna_cichlid_cache_info[] = { /* Scalar L1 Data Cache per SQC */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -540,6 +588,7 @@ static struct kfd_gpu_cache_info sienna_cichlid_cache_info[] = { /* GL1 Data Cache per SA */ .cache_size = 128, .cache_level = 1, + .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -549,6 +598,7 @@ static struct kfd_gpu_cache_info sienna_cichlid_cache_info[] = { /* L2 Data Cache per GPU (Total Tex Cache) */ .cache_size = 4096, .cache_level = 2, + .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -558,6 +608,7 @@ static struct kfd_gpu_cache_info sienna_cichlid_cache_info[] = { /* L3 Data Cache per GPU */ .cache_size = 128*1024, .cache_level = 3, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -570,6 +621,7 @@ static struct kfd_gpu_cache_info navy_flounder_cache_info[] = { /* TCP L1 Cache per CU */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -579,6 +631,7 @@ static struct kfd_gpu_cache_info navy_flounder_cache_info[] = { /* Scalar L1 Instruction Cache per SQC */ .cache_size = 32, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_INST_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -588,6 +641,7 @@ static struct kfd_gpu_cache_info navy_flounder_cache_info[] = { /* Scalar L1 Data Cache per SQC */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -597,6 +651,7 @@ static struct kfd_gpu_cache_info navy_flounder_cache_info[] = { /* GL1 Data Cache per SA */ .cache_size = 128, .cache_level = 1, + .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -606,6 +661,7 @@ static struct kfd_gpu_cache_info navy_flounder_cache_info[] = { /* L2 Data Cache per GPU (Total Tex Cache) */ .cache_size = 3072, .cache_level = 2, + .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -615,6 +671,7 @@ static struct kfd_gpu_cache_info navy_flounder_cache_info[] = { /* L3 Data Cache per GPU */ .cache_size = 96*1024, .cache_level = 3, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -627,6 +684,7 @@ static struct kfd_gpu_cache_info dimgrey_cavefish_cache_info[] = { /* TCP L1 Cache per CU */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -636,6 +694,7 @@ static struct kfd_gpu_cache_info dimgrey_cavefish_cache_info[] = { /* Scalar L1 Instruction Cache per SQC */ .cache_size = 32, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_INST_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -645,6 +704,7 @@ static struct kfd_gpu_cache_info dimgrey_cavefish_cache_info[] = { /* Scalar L1 Data Cache per SQC */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -654,6 +714,7 @@ static struct kfd_gpu_cache_info dimgrey_cavefish_cache_info[] = { /* GL1 Data Cache per SA */ .cache_size = 128, .cache_level = 1, + .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -663,6 +724,7 @@ static struct kfd_gpu_cache_info dimgrey_cavefish_cache_info[] = { /* L2 Data Cache per GPU (Total Tex Cache) */ .cache_size = 2048, .cache_level = 2, + .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -672,6 +734,7 @@ static struct kfd_gpu_cache_info dimgrey_cavefish_cache_info[] = { /* L3 Data Cache per GPU */ .cache_size = 32*1024, .cache_level = 3, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -684,6 +747,7 @@ static struct kfd_gpu_cache_info beige_goby_cache_info[] = { /* TCP L1 Cache per CU */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -693,6 +757,7 @@ static struct kfd_gpu_cache_info beige_goby_cache_info[] = { /* Scalar L1 Instruction Cache per SQC */ .cache_size = 32, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_INST_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -702,6 +767,7 @@ static struct kfd_gpu_cache_info beige_goby_cache_info[] = { /* Scalar L1 Data Cache per SQC */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -711,6 +777,7 @@ static struct kfd_gpu_cache_info beige_goby_cache_info[] = { /* GL1 Data Cache per SA */ .cache_size = 128, .cache_level = 1, + .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -720,6 +787,7 @@ static struct kfd_gpu_cache_info beige_goby_cache_info[] = { /* L2 Data Cache per GPU (Total Tex Cache) */ .cache_size = 1024, .cache_level = 2, + .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -729,6 +797,7 @@ static struct kfd_gpu_cache_info beige_goby_cache_info[] = { /* L3 Data Cache per GPU */ .cache_size = 16*1024, .cache_level = 3, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -741,6 +810,7 @@ static struct kfd_gpu_cache_info yellow_carp_cache_info[] = { /* TCP L1 Cache per CU */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -750,6 +820,7 @@ static struct kfd_gpu_cache_info yellow_carp_cache_info[] = { /* Scalar L1 Instruction Cache per SQC */ .cache_size = 32, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_INST_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -759,6 +830,7 @@ static struct kfd_gpu_cache_info yellow_carp_cache_info[] = { /* Scalar L1 Data Cache per SQC */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -768,6 +840,7 @@ static struct kfd_gpu_cache_info yellow_carp_cache_info[] = { /* GL1 Data Cache per SA */ .cache_size = 128, .cache_level = 1, + .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -777,6 +850,7 @@ static struct kfd_gpu_cache_info yellow_carp_cache_info[] = { /* L2 Data Cache per GPU (Total Tex Cache) */ .cache_size = 2048, .cache_level = 2, + .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -789,6 +863,7 @@ static struct kfd_gpu_cache_info gfx1037_cache_info[] = { /* TCP L1 Cache per CU */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -798,6 +873,7 @@ static struct kfd_gpu_cache_info gfx1037_cache_info[] = { /* Scalar L1 Instruction Cache per SQC */ .cache_size = 32, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_INST_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -807,6 +883,7 @@ static struct kfd_gpu_cache_info gfx1037_cache_info[] = { /* Scalar L1 Data Cache per SQC */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -816,6 +893,7 @@ static struct kfd_gpu_cache_info gfx1037_cache_info[] = { /* GL1 Data Cache per SA */ .cache_size = 128, .cache_level = 1, + .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -825,6 +903,7 @@ static struct kfd_gpu_cache_info gfx1037_cache_info[] = { /* L2 Data Cache per GPU (Total Tex Cache) */ .cache_size = 256, .cache_level = 2, + .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -837,6 +916,7 @@ static struct kfd_gpu_cache_info gc_10_3_6_cache_info[] = { /* TCP L1 Cache per CU */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -846,6 +926,7 @@ static struct kfd_gpu_cache_info gc_10_3_6_cache_info[] = { /* Scalar L1 Instruction Cache per SQC */ .cache_size = 32, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_INST_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -855,6 +936,7 @@ static struct kfd_gpu_cache_info gc_10_3_6_cache_info[] = { /* Scalar L1 Data Cache per SQC */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -864,6 +946,7 @@ static struct kfd_gpu_cache_info gc_10_3_6_cache_info[] = { /* GL1 Data Cache per SA */ .cache_size = 128, .cache_level = 1, + .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -873,6 +956,7 @@ static struct kfd_gpu_cache_info gc_10_3_6_cache_info[] = { /* L2 Data Cache per GPU (Total Tex Cache) */ .cache_size = 256, .cache_level = 2, + .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -885,6 +969,7 @@ static struct kfd_gpu_cache_info dummy_cache_info[] = { /* TCP L1 Cache per CU */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -894,6 +979,7 @@ static struct kfd_gpu_cache_info dummy_cache_info[] = { /* Scalar L1 Instruction Cache per SQC */ .cache_size = 32, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_INST_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -903,6 +989,7 @@ static struct kfd_gpu_cache_info dummy_cache_info[] = { /* Scalar L1 Data Cache per SQC */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -912,6 +999,7 @@ static struct kfd_gpu_cache_info dummy_cache_info[] = { /* GL1 Data Cache per SA */ .cache_size = 128, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -921,6 +1009,7 @@ static struct kfd_gpu_cache_info dummy_cache_info[] = { /* L2 Data Cache per GPU (Total Tex Cache) */ .cache_size = 2048, .cache_level = 2, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.h b/drivers/gpu/drm/amd/amdkfd/kfd_crat.h index 2f54ee08f2696..a8ca7ecb6d271 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.h @@ -301,6 +301,7 @@ struct kfd_node; struct kfd_gpu_cache_info { uint32_t cache_size; uint32_t cache_level; + uint32_t cache_line_size; uint32_t flags; /* Indicates how many Compute Units share this cache * within a SA. Value = 1 indicates the cache is not shared diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index bd692eefec616..7ccd9983e1368 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -1711,6 +1711,7 @@ static int fill_in_l1_pcache(struct kfd_cache_properties **props_ext, pcache->processor_id_low = cu_processor_id + (first_active_cu - 1); pcache->cache_level = pcache_info[cache_type].cache_level; pcache->cache_size = pcache_info[cache_type].cache_size; + pcache->cacheline_size = pcache_info[cache_type].cache_line_size; if (pcache_info[cache_type].flags & CRAT_CACHE_FLAGS_DATA_CACHE) pcache->cache_type |= HSA_CACHE_TYPE_DATA; @@ -1779,6 +1780,7 @@ static int fill_in_l2_l3_pcache(struct kfd_cache_properties **props_ext, pcache->processor_id_low = cu_processor_id + (first_active_cu - 1); pcache->cache_level = pcache_info[cache_type].cache_level; + pcache->cacheline_size = pcache_info[cache_type].cache_line_size; if (KFD_GC_VERSION(knode) == IP_VERSION(9, 4, 3) || KFD_GC_VERSION(knode) == IP_VERSION(9, 4, 4)) From ceb15818e04100f59c68d9f3c083a8b69de41089 Mon Sep 17 00:00:00 2001 From: Li Zetao Date: Fri, 30 Aug 2024 09:22:15 +0800 Subject: [PATCH 1483/1868] drm/amdgpu: use clamp() in amdgpu_vm_adjust_size() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When it needs to get a value within a certain interval, using clamp() makes the code easier to understand than min(max()). Reviewed-by: Christian König Signed-off-by: Li Zetao Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index f544d1afa4e38..d35b474e6c41b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -2286,7 +2286,7 @@ void amdgpu_vm_adjust_size(struct amdgpu_device *adev, uint32_t min_vm_size, phys_ram_gb = ((uint64_t)si.totalram * si.mem_unit + (1 << 30) - 1) >> 30; vm_size = roundup_pow_of_two( - min(max(phys_ram_gb * 3, min_vm_size), max_size)); + clamp(phys_ram_gb * 3, min_vm_size, max_size)); } adev->vm_manager.max_pfn = (uint64_t)vm_size << 18; From b0f62b61878600206f5021de2d569a36126d553d Mon Sep 17 00:00:00 2001 From: Tobias Jakobi Date: Mon, 2 Sep 2024 11:40:26 +0200 Subject: [PATCH 1484/1868] drm/amd/display: Avoid race between dcn10_set_drr() and dc_state_destruct() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit dc_state_destruct() nulls the resource context of the DC state. The pipe context passed to dcn10_set_drr() is a member of this resource context. If dc_state_destruct() is called parallel to the IRQ processing (which calls dcn10_set_drr() at some point), we can end up using already nulled function callback fields of struct stream_resource. The logic in dcn10_set_drr() already tries to avoid this, by checking tg against NULL. But if the nulling happens exactly after the NULL check and before the next access, then we get a race. Avoid this by copying tg first to a local variable, and then use this variable for all the operations. This should work, as long as nobody frees the resource pool where the timing generators live. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3142 Fixes: 06ad7e164256 ("drm/amd/display: Destroy DC context while keeping DML and DML2") Signed-off-by: Tobias Jakobi Tested-by: Raoul van Rüschen Tested-by: Christopher Snowhill Reviewed-by: Harry Wentland Tested-by: Sefa Eyeoglu Signed-off-by: Mario Limonciello --- .../amd/display/dc/hwss/dcn10/dcn10_hwseq.c | 20 +++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c index 01dffed4d30ba..a6a1db5ba8bad 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c @@ -3212,15 +3212,19 @@ void dcn10_set_drr(struct pipe_ctx **pipe_ctx, * as well. */ for (i = 0; i < num_pipes; i++) { - if ((pipe_ctx[i]->stream_res.tg != NULL) && pipe_ctx[i]->stream_res.tg->funcs) { - if (pipe_ctx[i]->stream_res.tg->funcs->set_drr) - pipe_ctx[i]->stream_res.tg->funcs->set_drr( - pipe_ctx[i]->stream_res.tg, ¶ms); + /* dc_state_destruct() might null the stream resources, so fetch tg + * here first to avoid a race condition. The lifetime of the pointee + * itself (the timing_generator object) is not a problem here. + */ + struct timing_generator *tg = pipe_ctx[i]->stream_res.tg; + + if ((tg != NULL) && tg->funcs) { + if (tg->funcs->set_drr) + tg->funcs->set_drr(tg, ¶ms); if (adjust.v_total_max != 0 && adjust.v_total_min != 0) - if (pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control) - pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control( - pipe_ctx[i]->stream_res.tg, - event_triggers, num_frames); + if (tg->funcs->set_static_screen_control) + tg->funcs->set_static_screen_control( + tg, event_triggers, num_frames); } } } From 9c1abcb82fde8bf859e0d693ec2c382f60b2bf66 Mon Sep 17 00:00:00 2001 From: Tobias Jakobi Date: Mon, 2 Sep 2024 11:40:27 +0200 Subject: [PATCH 1485/1868] drm/amd/display: Avoid race between dcn35_set_drr() and dc_state_destruct() dc_state_destruct() nulls the resource context of the DC state. The pipe context passed to dcn35_set_drr() is a member of this resource context. If dc_state_destruct() is called parallel to the IRQ processing (which calls dcn35_set_drr() at some point), we can end up using already nulled function callback fields of struct stream_resource. The logic in dcn35_set_drr() already tries to avoid this, by checking tg against NULL. But if the nulling happens exactly after the NULL check and before the next access, then we get a race. Avoid this by copying tg first to a local variable, and then use this variable for all the operations. This should work, as long as nobody frees the resource pool where the timing generators live. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3142 Fixes: 06ad7e164256 ("drm/amd/display: Destroy DC context while keeping DML and DML2") Signed-off-by: Tobias Jakobi Reviewed-by: Harry Wentland (Adjust for contextual changes) Signed-off-by: Mario Limonciello --- .../amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 20 +++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c index a4c6decee0f8a..5c5b2dd86f586 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c @@ -1414,7 +1414,13 @@ void dcn35_set_drr(struct pipe_ctx **pipe_ctx, params.vertical_total_mid_frame_num = adjust.v_total_mid_frame_num; for (i = 0; i < num_pipes; i++) { - if ((pipe_ctx[i]->stream_res.tg != NULL) && pipe_ctx[i]->stream_res.tg->funcs) { + /* dc_state_destruct() might null the stream resources, so fetch tg + * here first to avoid a race condition. The lifetime of the pointee + * itself (the timing_generator object) is not a problem here. + */ + struct timing_generator *tg = pipe_ctx[i]->stream_res.tg; + + if ((tg != NULL) && tg->funcs) { if (pipe_ctx[i]->stream && pipe_ctx[i]->stream->ctx->dc->debug.static_screen_wait_frames) { struct dc_crtc_timing *timing = &pipe_ctx[i]->stream->timing; struct dc *dc = pipe_ctx[i]->stream->ctx->dc; @@ -1426,14 +1432,12 @@ void dcn35_set_drr(struct pipe_ctx **pipe_ctx, num_frames = 2 * (frame_rate % 60); } } - if (pipe_ctx[i]->stream_res.tg->funcs->set_drr) - pipe_ctx[i]->stream_res.tg->funcs->set_drr( - pipe_ctx[i]->stream_res.tg, ¶ms); + if (tg->funcs->set_drr) + tg->funcs->set_drr(tg, ¶ms); if (adjust.v_total_max != 0 && adjust.v_total_min != 0) - if (pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control) - pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control( - pipe_ctx[i]->stream_res.tg, - event_triggers, num_frames); + if (tg->funcs->set_static_screen_control) + tg->funcs->set_static_screen_control( + tg, event_triggers, num_frames); } } } From dcebfdb0e9ee91b13f8636bb1690c9fd9a89c6b5 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Fri, 16 Aug 2024 12:40:43 +0530 Subject: [PATCH 1486/1868] drm/amdgpu: Normalize reg offsets on JPEG v4.0.3 On VFs and SOCs with GC 9.4.4, VCN RRMT is disabled. Only local register offsets should be used on JPEG v4.0.3 as they cannot handle remote access to other AIDs. Since only local offsets are used, the special write to MCM_ADDR register is no longer needed. Signed-off-by: Lijo Lazar Reviewed-by: Sathishkumar S --- drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 36 ++++++++++-------------- 1 file changed, 15 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c index c30c4cc3bb991..8219248a9a870 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c @@ -59,6 +59,12 @@ static int amdgpu_ih_srcid_jpeg[] = { VCN_4_0__SRCID__JPEG7_DECODE }; +static inline bool jpeg_v4_0_3_normalizn_reqd(struct amdgpu_device *adev) +{ + return amdgpu_sriov_vf(adev) || + (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)); +} + /** * jpeg_v4_0_3_early_init - set function pointers * @@ -732,32 +738,20 @@ void jpeg_v4_0_3_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE4)); amdgpu_ring_write(ring, 0); - if (ring->adev->jpeg.inst[ring->me].aid_id) { - amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_MCM_ADDR_INTERNAL_OFFSET, - 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE0)); - amdgpu_ring_write(ring, 0x4); - } else { - amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6)); - amdgpu_ring_write(ring, 0); - } + amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6)); + amdgpu_ring_write(ring, 0); amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 0, 0, PACKETJ_TYPE0)); amdgpu_ring_write(ring, 0x3fbc); - if (ring->adev->jpeg.inst[ring->me].aid_id) { - amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_MCM_ADDR_INTERNAL_OFFSET, - 0, PACKETJ_CONDITION_CHECK0, PACKETJ_TYPE0)); - amdgpu_ring_write(ring, 0x0); - } else { - amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6)); - amdgpu_ring_write(ring, 0); - } - amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 0, 0, PACKETJ_TYPE0)); amdgpu_ring_write(ring, 0x1); + amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6)); + amdgpu_ring_write(ring, 0); + amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE7)); amdgpu_ring_write(ring, 0); } @@ -832,8 +826,8 @@ void jpeg_v4_0_3_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, { uint32_t reg_offset; - /* For VF, only local offsets should be used */ - if (amdgpu_sriov_vf(ring->adev)) + /* Use normalized offsets if required */ + if (jpeg_v4_0_3_normalizn_reqd(ring->adev)) reg = NORMALIZE_JPEG_REG_OFFSET(reg); reg_offset = (reg << 2); @@ -879,8 +873,8 @@ void jpeg_v4_0_3_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint { uint32_t reg_offset; - /* For VF, only local offsets should be used */ - if (amdgpu_sriov_vf(ring->adev)) + /* Use normalized offsets if required */ + if (jpeg_v4_0_3_normalizn_reqd(ring->adev)) reg = NORMALIZE_JPEG_REG_OFFSET(reg); reg_offset = (reg << 2); From d591dffb5d5be7ae5fe3d84c81ea74ae8aff32f4 Mon Sep 17 00:00:00 2001 From: Jani Nikula Date: Thu, 23 May 2024 16:37:07 +0300 Subject: [PATCH 1487/1868] drm/amdgpu: drop redundant W=1 warnings from Makefile Since commit a61ddb4393ad ("drm: enable (most) W=1 warnings by default across the subsystem"), most of the extra warnings in the driver Makefile are redundant. Remove them. Note that -Wmissing-declarations and -Wmissing-prototypes are always enabled by default in scripts/Makefile.extrawarn. Reviewed-by: Hamza Mahfooz Signed-off-by: Jani Nikula Signed-off-by: Hamza Mahfooz --- drivers/gpu/drm/amd/amdgpu/Makefile | 18 +----------------- 1 file changed, 1 insertion(+), 17 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile index 37347b2d30374..45f3661afa023 100644 --- a/drivers/gpu/drm/amd/amdgpu/Makefile +++ b/drivers/gpu/drm/amd/amdgpu/Makefile @@ -39,23 +39,7 @@ ccflags-y := -I$(FULL_AMD_PATH)/include/asic_reg \ -I$(FULL_AMD_DISPLAY_PATH)/amdgpu_dm \ -I$(FULL_AMD_PATH)/amdkfd -subdir-ccflags-y := -Wextra -subdir-ccflags-y += -Wunused -subdir-ccflags-y += -Wmissing-prototypes -subdir-ccflags-y += -Wmissing-declarations -subdir-ccflags-y += -Wmissing-include-dirs -subdir-ccflags-y += -Wold-style-definition -subdir-ccflags-y += -Wmissing-format-attribute -# Need this to avoid recursive variable evaluation issues -cond-flags := $(call cc-option, -Wunused-but-set-variable) \ - $(call cc-option, -Wunused-const-variable) \ - $(call cc-option, -Wstringop-truncation) \ - $(call cc-option, -Wpacked-not-aligned) -subdir-ccflags-y += $(cond-flags) -subdir-ccflags-y += -Wno-unused-parameter -subdir-ccflags-y += -Wno-type-limits -subdir-ccflags-y += -Wno-sign-compare -subdir-ccflags-y += -Wno-missing-field-initializers +# Locally disable W=1 warnings enabled in drm subsystem Makefile subdir-ccflags-y += -Wno-override-init subdir-ccflags-$(CONFIG_DRM_AMDGPU_WERROR) += -Werror From 0d7186ec078780261bac6def06a12831540ad249 Mon Sep 17 00:00:00 2001 From: Nicholas Susanto Date: Tue, 20 Aug 2024 15:10:45 -0400 Subject: [PATCH 1488/1868] drm/amd/display: Refactor dccg35_get_other_enabled_symclk_fe [Why] Function used to check the number of FEs connected to the current BE. This was then used to determine if the symclk could be disabled, if all FEs were disconnected. However, the function would skip over the primary FE and return 0 when the primary FE was still connected. This caused black screens on driver disable with an MST daisy chain hooked up. [How] Refactor the function to correctly return the number of FEs connected to the input BE. Also, rename it for clarity. Reviewed-by: Nicholas Kazlauskas Signed-off-by: Nicholas Susanto Signed-off-by: Hamza Mahfooz --- .../amd/display/dc/dccg/dcn35/dcn35_dccg.c | 65 +++++++------------ 1 file changed, 25 insertions(+), 40 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c index ee02b78e290f4..18267ccd89a72 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c @@ -1932,47 +1932,32 @@ static void dccg35_enable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, } /*get other front end connected to this backend*/ -static uint8_t dccg35_get_other_enabled_symclk_fe(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst) +static uint8_t dccg35_get_number_enabled_symclk_fe_connected_to_be(struct dccg *dccg, uint32_t link_enc_inst) { uint8_t num_enabled_symclk_fe = 0; - uint32_t be_clk_en = 0, fe_clk_en[5] = {0}, be_clk_sel[5] = {0}; + uint32_t fe_clk_en[5] = {0}, be_clk_sel[5] = {0}; struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); - switch (link_enc_inst) { - case 0: - REG_GET_3(SYMCLKA_CLOCK_ENABLE, SYMCLKA_CLOCK_ENABLE, &be_clk_en, - SYMCLKA_FE_EN, &fe_clk_en[0], - SYMCLKA_FE_SRC_SEL, &be_clk_sel[0]); - break; - case 1: - REG_GET_3(SYMCLKB_CLOCK_ENABLE, SYMCLKB_CLOCK_ENABLE, &be_clk_en, - SYMCLKB_FE_EN, &fe_clk_en[1], - SYMCLKB_FE_SRC_SEL, &be_clk_sel[1]); - break; - case 2: - REG_GET_3(SYMCLKC_CLOCK_ENABLE, SYMCLKC_CLOCK_ENABLE, &be_clk_en, - SYMCLKC_FE_EN, &fe_clk_en[2], - SYMCLKC_FE_SRC_SEL, &be_clk_sel[2]); - break; - case 3: - REG_GET_3(SYMCLKD_CLOCK_ENABLE, SYMCLKD_CLOCK_ENABLE, &be_clk_en, - SYMCLKD_FE_EN, &fe_clk_en[3], - SYMCLKD_FE_SRC_SEL, &be_clk_sel[3]); - break; - case 4: - REG_GET_3(SYMCLKE_CLOCK_ENABLE, SYMCLKE_CLOCK_ENABLE, &be_clk_en, - SYMCLKE_FE_EN, &fe_clk_en[4], - SYMCLKE_FE_SRC_SEL, &be_clk_sel[4]); - break; - } - if (be_clk_en) { - /* for DPMST, this backend could be used by multiple front end. - only disable the backend if this stream_enc_ins is the last active stream enc connected to this back_end*/ - uint8_t i; - for (i = 0; i != link_enc_inst && i < ARRAY_SIZE(fe_clk_en); i++) { - if (fe_clk_en[i] && be_clk_sel[i] == link_enc_inst) - num_enabled_symclk_fe++; - } + REG_GET_2(SYMCLKA_CLOCK_ENABLE, SYMCLKA_FE_EN, &fe_clk_en[0], + SYMCLKA_FE_SRC_SEL, &be_clk_sel[0]); + + REG_GET_2(SYMCLKB_CLOCK_ENABLE, SYMCLKB_FE_EN, &fe_clk_en[1], + SYMCLKB_FE_SRC_SEL, &be_clk_sel[1]); + + REG_GET_2(SYMCLKC_CLOCK_ENABLE, SYMCLKC_FE_EN, &fe_clk_en[2], + SYMCLKC_FE_SRC_SEL, &be_clk_sel[2]); + + REG_GET_2(SYMCLKD_CLOCK_ENABLE, SYMCLKD_FE_EN, &fe_clk_en[3], + SYMCLKD_FE_SRC_SEL, &be_clk_sel[3]); + + REG_GET_2(SYMCLKE_CLOCK_ENABLE, SYMCLKE_FE_EN, &fe_clk_en[4], + SYMCLKE_FE_SRC_SEL, &be_clk_sel[4]); + + uint8_t i; + + for (i = 0; i < ARRAY_SIZE(fe_clk_en); i++) { + if (fe_clk_en[i] && be_clk_sel[i] == link_enc_inst) + num_enabled_symclk_fe++; } return num_enabled_symclk_fe; } @@ -2020,9 +2005,9 @@ static void dccg35_disable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst break; } - /*check other enabled symclk fe */ - num_enabled_symclk_fe = dccg35_get_other_enabled_symclk_fe(dccg, stream_enc_inst, link_enc_inst); - /*only turn off backend clk if other front end attachecd to this backend are all off, + /*check other enabled symclk fe connected to this be */ + num_enabled_symclk_fe = dccg35_get_number_enabled_symclk_fe_connected_to_be(dccg, link_enc_inst); + /*only turn off backend clk if other front end attached to this backend are all off, for mst, only turn off the backend if this is the last front end*/ if (num_enabled_symclk_fe == 0) { switch (link_enc_inst) { From 9810c5d5088e54984bb8427eeab1cf838c904650 Mon Sep 17 00:00:00 2001 From: Qili Lu Date: Wed, 21 Aug 2024 16:26:13 -0400 Subject: [PATCH 1489/1868] drm/amd/display: fix dccg root clock optimization related hang [Why] enable dpp rcg before we disable dppclk in hw_init cause system hang/reboot [How] we remove dccg rcg related code from init into a separate function and call it after we init pipe Cc: stable@vger.kernel.org # 6.10+ Reviewed-by: Nicholas Kazlauskas Signed-off-by: Qili Lu Signed-off-by: Hamza Mahfooz --- .../gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c | 14 +++++++++----- .../gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h | 1 + .../drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 4 ++++ drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h | 1 + 4 files changed, 15 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c index 18267ccd89a72..838d72eaa87fb 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c @@ -1748,10 +1748,6 @@ void dccg35_init(struct dccg *dccg) dccg35_set_dpstreamclk_root_clock_gating(dccg, otg_inst, false); } - if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpp) - for (otg_inst = 0; otg_inst < 4; otg_inst++) - dccg35_set_dppclk_root_clock_gating(dccg, otg_inst, 0); - /* dccg35_enable_global_fgcg_rep( dccg, dccg->ctx->dc->debug.enable_fine_grain_clock_gating.bits @@ -2336,6 +2332,14 @@ static void dccg35_disable_symclk_se_cb( /* DMU PHY sequence switches SYMCLK_BE (link_enc_inst) to ref clock once PHY is turned off */ } +void dccg35_root_gate_disable_control(struct dccg *dccg, uint32_t pipe_idx, uint32_t disable_clock_gating) +{ + + if (dccg->ctx->dc->debug.root_clock_optimization.bits.dpp) { + dccg35_set_dppclk_root_clock_gating(dccg, pipe_idx, disable_clock_gating); + } +} + static const struct dccg_funcs dccg35_funcs_new = { .update_dpp_dto = dccg35_update_dpp_dto_cb, .dpp_root_clock_control = dccg35_dpp_root_clock_control_cb, @@ -2396,7 +2400,7 @@ static const struct dccg_funcs dccg35_funcs = { .enable_symclk_se = dccg35_enable_symclk_se, .disable_symclk_se = dccg35_disable_symclk_se, .set_dtbclk_p_src = dccg35_set_dtbclk_p_src, - + .dccg_root_gate_disable_control = dccg35_root_gate_disable_control, }; struct dccg *dccg35_create( diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h index 1586a45ca3bd4..51f98c5c51c41 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h @@ -241,6 +241,7 @@ struct dccg *dccg35_create( void dccg35_init(struct dccg *dccg); void dccg35_enable_global_fgcg_rep(struct dccg *dccg, bool value); +void dccg35_root_gate_disable_control(struct dccg *dccg, uint32_t pipe_idx, uint32_t disable_clock_gating); #endif //__DCN35_DCCG_H__ diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c index 5c5b2dd86f586..479fd3e89e5ab 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c @@ -240,6 +240,10 @@ void dcn35_init_hw(struct dc *dc) dc->res_pool->hubbub->funcs->allow_self_refresh_control(dc->res_pool->hubbub, !dc->res_pool->hubbub->ctx->dc->debug.disable_stutter); } + if (res_pool->dccg->funcs->dccg_root_gate_disable_control) { + for (i = 0; i < res_pool->pipe_count; i++) + res_pool->dccg->funcs->dccg_root_gate_disable_control(res_pool->dccg, i, 0); + } for (i = 0; i < res_pool->audio_count; i++) { struct audio *audio = res_pool->audios[i]; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h index d619eb229a62a..e94e9ba60f55a 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h @@ -213,6 +213,7 @@ struct dccg_funcs { uint32_t otg_inst); void (*set_dto_dscclk)(struct dccg *dccg, uint32_t dsc_inst); void (*set_ref_dscclk)(struct dccg *dccg, uint32_t dsc_inst); + void (*dccg_root_gate_disable_control)(struct dccg *dccg, uint32_t pipe_idx, uint32_t disable_clock_gating); }; #endif //__DAL_DCCG_H__ From d7b98dda7534cf667691675dcb846398d5e09326 Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Mon, 26 Aug 2024 18:53:50 +0530 Subject: [PATCH 1490/1868] drm/amdgpu/: Add missing kdoc entry in amdgpu_vm_handle_fault function MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This commit adds a description for the 'ts' parameter in the amdgpu_vm_handle_fault function's comment block. Fixes the below with gcc W=1: drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:2781: warning: Function parameter or struct member 'ts' not described in 'amdgpu_vm_handle_fault' Cc: Xiaogang.Chen Cc: Christian König Cc: Alex Deucher Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202408251419.vgZHg3GV-lkp@intel.com/ Signed-off-by: Srinivasan Shanmugam Reviewed-by: Xiaogang Chen --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index d35b474e6c41b..f494d541d24cb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -2856,6 +2856,7 @@ int amdgpu_vm_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) * amdgpu_vm_handle_fault - graceful handling of VM faults. * @adev: amdgpu device pointer * @pasid: PASID of the VM + * @ts: Timestamp of the fault * @vmid: VMID, only used for GFX 9.4.3. * @node_id: Node_id received in IH cookie. Only applicable for * GFX 9.4.3. From f09ee34ff9db1bc5df9308119538c8cf1e770d4f Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Wed, 4 Sep 2024 12:30:16 +0530 Subject: [PATCH 1491/1868] drm/amdgpu: Replace 'amdgpu_job_submit_direct' with 'drm_sched_entity' in cleaner shader MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This commit replaces the use of amdgpu_job_submit_direct which submits the job to the ring directly, with drm_sched_entity in the cleaner shader job submission process. The change allows the GPU scheduler to manage the cleaner shader job. - The job is then submitted to the GPU using the drm_sched_entity_push_job function, which allows the GPU scheduler to manage the job. This change improves the reliability of the cleaner shader job submission process by leveraging the capabilities of the GPU scheduler. Fixes: f70111466165 ("drm/amdgpu: Add sysfs interface for running cleaner shader") Cc: Christian König Cc: Alex Deucher Signed-off-by: Srinivasan Shanmugam Suggested-by: Christian König Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 35 ++++++++++++++----------- 1 file changed, 19 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c index b779d47a546a3..83e54697f0ee8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c @@ -1397,14 +1397,23 @@ static ssize_t amdgpu_gfx_get_available_compute_partition(struct device *dev, static int amdgpu_gfx_run_cleaner_shader_job(struct amdgpu_ring *ring) { struct amdgpu_device *adev = ring->adev; - long timeout = msecs_to_jiffies(1000); - struct dma_fence *f = NULL; + struct drm_gpu_scheduler *sched = &ring->sched; + struct drm_sched_entity entity; + struct dma_fence *f; struct amdgpu_job *job; struct amdgpu_ib *ib; int i, r; - r = amdgpu_job_alloc_with_ib(adev, NULL, NULL, - 64, AMDGPU_IB_POOL_DIRECT, + /* Initialize the scheduler entity */ + r = drm_sched_entity_init(&entity, DRM_SCHED_PRIORITY_NORMAL, + &sched, 1, NULL); + if (r) { + dev_err(adev->dev, "Failed setting up GFX kernel entity.\n"); + goto err; + } + + r = amdgpu_job_alloc_with_ib(ring->adev, &entity, NULL, + 64, 0, &job); if (r) goto err; @@ -1416,24 +1425,18 @@ static int amdgpu_gfx_run_cleaner_shader_job(struct amdgpu_ring *ring) ib->ptr[i] = ring->funcs->nop; ib->length_dw = ring->funcs->align_mask + 1; - r = amdgpu_job_submit_direct(job, ring, &f); - if (r) - goto err_free; + f = amdgpu_job_submit(job); - r = dma_fence_wait_timeout(f, false, timeout); - if (r == 0) - r = -ETIMEDOUT; - else if (r > 0) - r = 0; + r = dma_fence_wait(f, false); + if (r) + goto err; - amdgpu_ib_free(adev, ib, f); dma_fence_put(f); + /* Clean up the scheduler entity */ + drm_sched_entity_destroy(&entity); return 0; -err_free: - amdgpu_job_free(job); - amdgpu_ib_free(adev, ib, f); err: return r; } From afc657c594f068f7e35ba2fdbec6679338aa3183 Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Wed, 4 Sep 2024 13:10:59 +0530 Subject: [PATCH 1492/1868] drm/amd/display: Add kdoc entry for 'program_isharp_1dlut' in 'dpp401_dscl_program_isharp' Added a descriptor for the 'program_isharp_1dlut' parameter, which is a flag used to determine whether to program the isharp 1D LUT. Fixes the below with gcc W=1: drivers/gpu/drm/amd/amdgpu/../display/dc/dpp/dcn401/dcn401_dpp_dscl.c:963: warning: Function parameter or struct member 'program_isharp_1dlut' not described in 'dpp401_dscl_program_isharp' Cc: Tom Chung Cc: Rodrigo Siqueira Cc: Roman Li Cc: Alex Hung Cc: Aurabindo Pillai Cc: Harry Wentland Cc: Hamza Mahfooz Signed-off-by: Srinivasan Shanmugam Reviewed-by: Tom Chung --- drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c index 8564369f09b48..5105fd580017c 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c @@ -951,6 +951,7 @@ static void dpp401_dscl_set_isharp_filter( * * @dpp_base: High level DPP struct * @scl_data: scalaer_data info + * @program_isharp_1dlut: flag to program isharp 1D LUT * @bs_coeffs_updated: Blur and Scale Coefficients update flag * * This is the primary function to program isharp From e275640961a61e2cebe3fa0f774ffb49b8c304ad Mon Sep 17 00:00:00 2001 From: "Jesse.zhang@amd.com" Date: Wed, 4 Sep 2024 17:47:06 +0800 Subject: [PATCH 1493/1868] drm/amdgpu: fix queue reset issue by mmio Initialize the queue type before resetting the queue using mmio. Signed-off-by: Jesse Zhang Acked-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c index e395373f7c563..ff43540abcfcd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c @@ -832,6 +832,7 @@ int amdgpu_mes_reset_hw_queue_mmio(struct amdgpu_device *adev, int queue_type, struct mes_reset_queue_input queue_input; int r; + queue_input.queue_type = queue_type; queue_input.use_mmio = true; queue_input.me_id = me_id; queue_input.pipe_id = pipe_id; From a44d98046a239b54cb09fa718d3b94c9eba87eaa Mon Sep 17 00:00:00 2001 From: Ramesh Errabolu Date: Tue, 20 Aug 2024 16:05:30 -0500 Subject: [PATCH 1494/1868] drm/amdgpu: Surface svm_default_granularity, a RW module parameter Enables users to update SVM's default granularity, used in buffer migration and handling of recoverable page faults. Param value is set in terms of log(numPages(buffer)), e.g. 9 for a 2 MIB buffer Signed-off-by: Ramesh Errabolu Reviewed-by: Philip Yang --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 17 +++++++++++++++++ drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 6 ++++++ drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 22 +++++++++++++++------- 4 files changed, 39 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index e017add16864b..27769f10914b2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -241,6 +241,7 @@ extern int sched_policy; extern bool debug_evictions; extern bool no_system_mem_limit; extern int halt_if_hws_hang; +extern uint amdgpu_svm_default_granularity; #else static const int __maybe_unused sched_policy = KFD_SCHED_POLICY_HWS; static const bool __maybe_unused debug_evictions; /* = false */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 90c74155a26aa..94b1d1f169a3b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -172,6 +172,16 @@ uint amdgpu_sdma_phase_quantum = 32; char *amdgpu_disable_cu; char *amdgpu_virtual_display; bool enforce_isolation; + +/* Specifies the default granularity for SVM, used in buffer + * migration and restoration of backing memory when handling + * recoverable page faults. + * + * The value is given as log(numPages(buffer)); for a 2 MiB + * buffer it computes to be 9 + */ +uint amdgpu_svm_default_granularity = 9; + /* * OverDrive(bit 14) disabled by default * GFX DCS(bit 19) disabled by default @@ -323,6 +333,13 @@ module_param_named(pcie_gen2, amdgpu_pcie_gen2, int, 0444); MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)"); module_param_named(msi, amdgpu_msi, int, 0444); +/** + * DOC: svm_default_granularity (uint) + * Used in buffer migration and handling of recoverable page faults + */ +MODULE_PARM_DESC(svm_default_granularity, "SVM's default granularity in log(2^Pages), default 9 = 2^9 = 2 MiB"); +module_param_named(svm_default_granularity, amdgpu_svm_default_granularity, uint, 0644); + /** * DOC: lockup_timeout (string) * Set GPU scheduler timeout value in ms. diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 1351104b825c9..f2a2a87925fbe 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -962,6 +962,12 @@ struct svm_range_list { struct task_struct *faulting_task; /* check point ts decides if page fault recovery need be dropped */ uint64_t checkpoint_ts[MAX_GPU_INSTANCE]; + + /* Default granularity to use in buffer migration + * and restoration of backing memory while handling + * recoverable page faults + */ + uint8_t default_granularity; }; /* Process data */ diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c index 4b01fd3f63d90..53bf2c9f7a0d6 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c @@ -313,12 +313,13 @@ static void svm_range_free(struct svm_range *prange, bool do_unmap) } static void -svm_range_set_default_attributes(int32_t *location, int32_t *prefetch_loc, - uint8_t *granularity, uint32_t *flags) +svm_range_set_default_attributes(struct svm_range_list *svms, int32_t *location, + int32_t *prefetch_loc, uint8_t *granularity, + uint32_t *flags) { *location = KFD_IOCTL_SVM_LOCATION_UNDEFINED; *prefetch_loc = KFD_IOCTL_SVM_LOCATION_UNDEFINED; - *granularity = 9; + *granularity = svms->default_granularity; *flags = KFD_IOCTL_SVM_FLAG_HOST_ACCESS | KFD_IOCTL_SVM_FLAG_COHERENT; } @@ -362,7 +363,7 @@ svm_range *svm_range_new(struct svm_range_list *svms, uint64_t start, bitmap_copy(prange->bitmap_access, svms->bitmap_supported, MAX_GPU_INSTANCE); - svm_range_set_default_attributes(&prange->preferred_loc, + svm_range_set_default_attributes(svms, &prange->preferred_loc, &prange->prefetch_loc, &prange->granularity, &prange->flags); @@ -2701,9 +2702,10 @@ svm_range_get_range_boundaries(struct kfd_process *p, int64_t addr, *is_heap_stack = vma_is_initial_heap(vma) || vma_is_initial_stack(vma); start_limit = max(vma->vm_start >> PAGE_SHIFT, - (unsigned long)ALIGN_DOWN(addr, 2UL << 8)); + (unsigned long)ALIGN_DOWN(addr, 1UL << p->svms.default_granularity)); end_limit = min(vma->vm_end >> PAGE_SHIFT, - (unsigned long)ALIGN(addr + 1, 2UL << 8)); + (unsigned long)ALIGN(addr + 1, 1UL << p->svms.default_granularity)); + /* First range that starts after the fault address */ node = interval_tree_iter_first(&p->svms.objects, addr + 1, ULONG_MAX); if (node) { @@ -3247,6 +3249,12 @@ int svm_range_list_init(struct kfd_process *p) if (KFD_IS_SVM_API_SUPPORTED(p->pdds[i]->dev->adev)) bitmap_set(svms->bitmap_supported, i, 1); + /* Value of default granularity cannot exceed 0x1B, the + * number of pages supported by a 4-level paging table + */ + svms->default_granularity = min_t(u8, amdgpu_svm_default_granularity, 0x1B); + pr_debug("Default SVM Granularity to use: %d\n", svms->default_granularity); + return 0; } @@ -3774,7 +3782,7 @@ svm_range_get_attr(struct kfd_process *p, struct mm_struct *mm, node = interval_tree_iter_first(&svms->objects, start, last); if (!node) { pr_debug("range attrs not found return default values\n"); - svm_range_set_default_attributes(&location, &prefetch_loc, + svm_range_set_default_attributes(svms, &location, &prefetch_loc, &granularity, &flags_and); flags_or = flags_and; if (p->xnack_enabled) From 66e3aaac41f10249e8565fdbb116a639120bb547 Mon Sep 17 00:00:00 2001 From: Jonathan Kim Date: Thu, 22 Aug 2024 10:44:39 -0400 Subject: [PATCH 1495/1868] drm/amdkfd: fix missed queue reset on queue destroy If a queue is being destroyed but causes a HWS hang on removal, the KFD may issue an unnecessary gpu reset if the destroyed queue can be fixed by a queue reset. This is because the queue has been removed from the KFD's queue list prior to the preemption action on destroy so the reset call will fail to match the HQD PQ reset information against the KFD's queue record to do the actual reset. To fix this, deactivate the queue prior to preemption since it's being destroyed anyways and remove the queue from the KFD's queue list after preemption. Signed-off-by: Jonathan Kim Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index e96de444db64a..56b0ba718319b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -2433,10 +2433,9 @@ static int destroy_queue_cpsch(struct device_queue_manager *dqm, pdd->sdma_past_activity_counter += sdma_val; } - list_del(&q->list); - qpd->queue_count--; if (q->properties.is_active) { decrement_queue_count(dqm, qpd, q); + q->properties.is_active = false; if (!dqm->dev->kfd->shared_resources.enable_mes) { retval = execute_queues_cpsch(dqm, KFD_UNMAP_QUEUES_FILTER_DYNAMIC_QUEUES, 0, @@ -2447,6 +2446,8 @@ static int destroy_queue_cpsch(struct device_queue_manager *dqm, retval = remove_queue_mes(dqm, q, qpd); } } + list_del(&q->list); + qpd->queue_count--; /* * Unconditionally decrement this counter, regardless of the queue's From 6c532a0765a5ac37de026be275f4a83aa0939ec8 Mon Sep 17 00:00:00 2001 From: Hawking Zhang Date: Fri, 6 Sep 2024 16:06:13 +0800 Subject: [PATCH 1496/1868] drm/amdkfd: Select reset method for poison handling Driver mode-2 is only supported by relative new smc firmware. Signed-off-by: Hawking Zhang Reviewed-by: Tao Zhou --- .../gpu/drm/amd/amdkfd/kfd_int_process_v9.c | 40 +++++++++++++++---- 1 file changed, 32 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c index fecdbbab98949..d46a13156ee9d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c @@ -167,11 +167,23 @@ static void event_interrupt_poison_consumption_v9(struct kfd_node *dev, case SOC15_IH_CLIENTID_SE3SH: case SOC15_IH_CLIENTID_UTCL2: block = AMDGPU_RAS_BLOCK__GFX; - if (amdgpu_ip_version(dev->adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || - amdgpu_ip_version(dev->adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) - reset = AMDGPU_RAS_GPU_RESET_MODE1_RESET; - else + if (amdgpu_ip_version(dev->adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) { + /* driver mode-2 for gfx poison is only supported by + * pmfw 0x00557300 and onwards */ + if (dev->adev->pm.fw_version < 0x00557300) + reset = AMDGPU_RAS_GPU_RESET_MODE1_RESET; + else + reset = AMDGPU_RAS_GPU_RESET_MODE2_RESET; + } else if (amdgpu_ip_version(dev->adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) { + /* driver mode-2 for gfx poison is only supported by + * pmfw 0x05550C00 and onwards */ + if (dev->adev->pm.fw_version < 0x05550C00) + reset = AMDGPU_RAS_GPU_RESET_MODE1_RESET; + else + reset = AMDGPU_RAS_GPU_RESET_MODE2_RESET; + } else { reset = AMDGPU_RAS_GPU_RESET_MODE2_RESET; + } break; case SOC15_IH_CLIENTID_VMC: case SOC15_IH_CLIENTID_VMC1: @@ -184,11 +196,23 @@ static void event_interrupt_poison_consumption_v9(struct kfd_node *dev, case SOC15_IH_CLIENTID_SDMA3: case SOC15_IH_CLIENTID_SDMA4: block = AMDGPU_RAS_BLOCK__SDMA; - if (amdgpu_ip_version(dev->adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || - amdgpu_ip_version(dev->adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) - reset = AMDGPU_RAS_GPU_RESET_MODE1_RESET; - else + if (amdgpu_ip_version(dev->adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 2)) { + /* driver mode-2 for gfx poison is only supported by + * pmfw 0x00557300 and onwards */ + if (dev->adev->pm.fw_version < 0x00557300) + reset = AMDGPU_RAS_GPU_RESET_MODE1_RESET; + else + reset = AMDGPU_RAS_GPU_RESET_MODE2_RESET; + } else if (amdgpu_ip_version(dev->adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 5)) { + /* driver mode-2 for gfx poison is only supported by + * pmfw 0x05550C00 and onwards */ + if (dev->adev->pm.fw_version < 0x05550C00) + reset = AMDGPU_RAS_GPU_RESET_MODE1_RESET; + else + reset = AMDGPU_RAS_GPU_RESET_MODE2_RESET; + } else { reset = AMDGPU_RAS_GPU_RESET_MODE2_RESET; + } break; default: dev_warn(dev->adev->dev, From 2f097771535c7948c7bfe3090a97d9c205110880 Mon Sep 17 00:00:00 2001 From: Philip Yang Date: Fri, 16 Feb 2024 11:00:10 -0500 Subject: [PATCH 1497/1868] drm/amdkfd: Document and define SVM events message macro Document how to use SMI system management interface to enable and receive SVM events. Document SVM event triggers. Define SVM events message string format macro that could be used by user mode for sscanf to parse the event. Add it to uAPI header file to make it obvious that is changing uAPI in future. No functional changes. Signed-off-by: Philip Yang Reviewed-by: James Zhu --- drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c | 45 +++++---- include/uapi/linux/kfd_ioctl.h | 100 +++++++++++++++++--- 2 files changed, 109 insertions(+), 36 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c b/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c index 2976a6c873dd2..4a590dfc479b6 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_smi_events.c @@ -235,17 +235,16 @@ void kfd_smi_event_update_gpu_reset(struct kfd_node *dev, bool post_reset, amdgpu_reset_get_desc(reset_context, reset_cause, sizeof(reset_cause)); - kfd_smi_event_add(0, dev, event, "%x %s\n", - dev->reset_seq_num, - reset_cause); + kfd_smi_event_add(0, dev, event, KFD_EVENT_FMT_UPDATE_GPU_RESET( + dev->reset_seq_num, reset_cause)); } void kfd_smi_event_update_thermal_throttling(struct kfd_node *dev, uint64_t throttle_bitmask) { - kfd_smi_event_add(0, dev, KFD_SMI_EVENT_THERMAL_THROTTLE, "%llx:%llx\n", + kfd_smi_event_add(0, dev, KFD_SMI_EVENT_THERMAL_THROTTLE, KFD_EVENT_FMT_THERMAL_THROTTLING( throttle_bitmask, - amdgpu_dpm_get_thermal_throttling_counter(dev->adev)); + amdgpu_dpm_get_thermal_throttling_counter(dev->adev))); } void kfd_smi_event_update_vmfault(struct kfd_node *dev, uint16_t pasid) @@ -256,8 +255,8 @@ void kfd_smi_event_update_vmfault(struct kfd_node *dev, uint16_t pasid) if (task_info) { /* Report VM faults from user applications, not retry from kernel */ if (task_info->pid) - kfd_smi_event_add(0, dev, KFD_SMI_EVENT_VMFAULT, "%x:%s\n", - task_info->pid, task_info->task_name); + kfd_smi_event_add(0, dev, KFD_SMI_EVENT_VMFAULT, KFD_EVENT_FMT_VMFAULT( + task_info->pid, task_info->task_name)); amdgpu_vm_put_task_info(task_info); } } @@ -267,16 +266,16 @@ void kfd_smi_event_page_fault_start(struct kfd_node *node, pid_t pid, ktime_t ts) { kfd_smi_event_add(pid, node, KFD_SMI_EVENT_PAGE_FAULT_START, - "%lld -%d @%lx(%x) %c\n", ktime_to_ns(ts), pid, - address, node->id, write_fault ? 'W' : 'R'); + KFD_EVENT_FMT_PAGEFAULT_START(ktime_to_ns(ts), pid, + address, node->id, write_fault ? 'W' : 'R')); } void kfd_smi_event_page_fault_end(struct kfd_node *node, pid_t pid, unsigned long address, bool migration) { kfd_smi_event_add(pid, node, KFD_SMI_EVENT_PAGE_FAULT_END, - "%lld -%d @%lx(%x) %c\n", ktime_get_boottime_ns(), - pid, address, node->id, migration ? 'M' : 'U'); + KFD_EVENT_FMT_PAGEFAULT_END(ktime_get_boottime_ns(), + pid, address, node->id, migration ? 'M' : 'U')); } void kfd_smi_event_migration_start(struct kfd_node *node, pid_t pid, @@ -286,9 +285,9 @@ void kfd_smi_event_migration_start(struct kfd_node *node, pid_t pid, uint32_t trigger) { kfd_smi_event_add(pid, node, KFD_SMI_EVENT_MIGRATE_START, - "%lld -%d @%lx(%lx) %x->%x %x:%x %d\n", + KFD_EVENT_FMT_MIGRATE_START( ktime_get_boottime_ns(), pid, start, end - start, - from, to, prefetch_loc, preferred_loc, trigger); + from, to, prefetch_loc, preferred_loc, trigger)); } void kfd_smi_event_migration_end(struct kfd_node *node, pid_t pid, @@ -296,24 +295,24 @@ void kfd_smi_event_migration_end(struct kfd_node *node, pid_t pid, uint32_t from, uint32_t to, uint32_t trigger) { kfd_smi_event_add(pid, node, KFD_SMI_EVENT_MIGRATE_END, - "%lld -%d @%lx(%lx) %x->%x %d\n", + KFD_EVENT_FMT_MIGRATE_END( ktime_get_boottime_ns(), pid, start, end - start, - from, to, trigger); + from, to, trigger)); } void kfd_smi_event_queue_eviction(struct kfd_node *node, pid_t pid, uint32_t trigger) { kfd_smi_event_add(pid, node, KFD_SMI_EVENT_QUEUE_EVICTION, - "%lld -%d %x %d\n", ktime_get_boottime_ns(), pid, - node->id, trigger); + KFD_EVENT_FMT_QUEUE_EVICTION(ktime_get_boottime_ns(), pid, + node->id, trigger)); } void kfd_smi_event_queue_restore(struct kfd_node *node, pid_t pid) { kfd_smi_event_add(pid, node, KFD_SMI_EVENT_QUEUE_RESTORE, - "%lld -%d %x\n", ktime_get_boottime_ns(), pid, - node->id); + KFD_EVENT_FMT_QUEUE_RESTORE(ktime_get_boottime_ns(), pid, + node->id, 0)); } void kfd_smi_event_queue_restore_rescheduled(struct mm_struct *mm) @@ -330,8 +329,8 @@ void kfd_smi_event_queue_restore_rescheduled(struct mm_struct *mm) kfd_smi_event_add(p->lead_thread->pid, pdd->dev, KFD_SMI_EVENT_QUEUE_RESTORE, - "%lld -%d %x %c\n", ktime_get_boottime_ns(), - p->lead_thread->pid, pdd->dev->id, 'R'); + KFD_EVENT_FMT_QUEUE_RESTORE(ktime_get_boottime_ns(), + p->lead_thread->pid, pdd->dev->id, 'R')); } kfd_unref_process(p); } @@ -341,8 +340,8 @@ void kfd_smi_event_unmap_from_gpu(struct kfd_node *node, pid_t pid, uint32_t trigger) { kfd_smi_event_add(pid, node, KFD_SMI_EVENT_UNMAP_FROM_GPU, - "%lld -%d @%lx(%lx) %x %d\n", ktime_get_boottime_ns(), - pid, address, last - address + 1, node->id, trigger); + KFD_EVENT_FMT_UNMAP_FROM_GPU(ktime_get_boottime_ns(), + pid, address, last - address + 1, node->id, trigger)); } int kfd_smi_event_open(struct kfd_node *dev, uint32_t *fd) diff --git a/include/uapi/linux/kfd_ioctl.h b/include/uapi/linux/kfd_ioctl.h index 2b68c0c17313b..d3b678708d381 100644 --- a/include/uapi/linux/kfd_ioctl.h +++ b/include/uapi/linux/kfd_ioctl.h @@ -551,26 +551,29 @@ enum kfd_smi_event { KFD_SMI_EVENT_ALL_PROCESS = 64 }; +/* The reason of the page migration event */ enum KFD_MIGRATE_TRIGGERS { - KFD_MIGRATE_TRIGGER_PREFETCH, - KFD_MIGRATE_TRIGGER_PAGEFAULT_GPU, - KFD_MIGRATE_TRIGGER_PAGEFAULT_CPU, - KFD_MIGRATE_TRIGGER_TTM_EVICTION + KFD_MIGRATE_TRIGGER_PREFETCH, /* Prefetch to GPU VRAM or system memory */ + KFD_MIGRATE_TRIGGER_PAGEFAULT_GPU, /* GPU page fault recover */ + KFD_MIGRATE_TRIGGER_PAGEFAULT_CPU, /* CPU page fault recover */ + KFD_MIGRATE_TRIGGER_TTM_EVICTION /* TTM eviction */ }; +/* The reason of user queue evition event */ enum KFD_QUEUE_EVICTION_TRIGGERS { - KFD_QUEUE_EVICTION_TRIGGER_SVM, - KFD_QUEUE_EVICTION_TRIGGER_USERPTR, - KFD_QUEUE_EVICTION_TRIGGER_TTM, - KFD_QUEUE_EVICTION_TRIGGER_SUSPEND, - KFD_QUEUE_EVICTION_CRIU_CHECKPOINT, - KFD_QUEUE_EVICTION_CRIU_RESTORE + KFD_QUEUE_EVICTION_TRIGGER_SVM, /* SVM buffer migration */ + KFD_QUEUE_EVICTION_TRIGGER_USERPTR, /* userptr movement */ + KFD_QUEUE_EVICTION_TRIGGER_TTM, /* TTM move buffer */ + KFD_QUEUE_EVICTION_TRIGGER_SUSPEND, /* GPU suspend */ + KFD_QUEUE_EVICTION_CRIU_CHECKPOINT, /* CRIU checkpoint */ + KFD_QUEUE_EVICTION_CRIU_RESTORE /* CRIU restore */ }; +/* The reason of unmap buffer from GPU event */ enum KFD_SVM_UNMAP_TRIGGERS { - KFD_SVM_UNMAP_TRIGGER_MMU_NOTIFY, - KFD_SVM_UNMAP_TRIGGER_MMU_NOTIFY_MIGRATE, - KFD_SVM_UNMAP_TRIGGER_UNMAP_FROM_CPU + KFD_SVM_UNMAP_TRIGGER_MMU_NOTIFY, /* MMU notifier CPU buffer movement */ + KFD_SVM_UNMAP_TRIGGER_MMU_NOTIFY_MIGRATE,/* MMU notifier page migration */ + KFD_SVM_UNMAP_TRIGGER_UNMAP_FROM_CPU /* Unmap to free the buffer */ }; #define KFD_SMI_EVENT_MASK_FROM_INDEX(i) (1ULL << ((i) - 1)) @@ -656,6 +659,77 @@ struct kfd_ioctl_spm_args { __u32 has_data_loss; }; +/* + * SVM event tracing via SMI system management interface + * + * Open event file descriptor + * use ioctl AMDKFD_IOC_SMI_EVENTS, pass in gpuid and return a anonymous file + * descriptor to receive SMI events. + * If calling with sudo permission, then file descriptor can be used to receive + * SVM events from all processes, otherwise, to only receive SVM events of same + * process. + * + * To enable the SVM event + * Write event file descriptor with KFD_SMI_EVENT_MASK_FROM_INDEX(event) bitmap + * mask to start record the event to the kfifo, use bitmap mask combination + * for multiple events. New event mask will overwrite the previous event mask. + * KFD_SMI_EVENT_MASK_FROM_INDEX(KFD_SMI_EVENT_ALL_PROCESS) bit requires sudo + * permisson to receive SVM events from all process. + * + * To receive the event + * Application can poll file descriptor to wait for the events, then read event + * from the file into a buffer. Each event is one line string message, starting + * with the event id, then the event specific information. + * + * To decode event information + * The following event format string macro can be used with sscanf to decode + * the specific event information. + * event triggers: the reason to generate the event, defined as enum for unmap, + * eviction and migrate events. + * node, from, to, prefetch_loc, preferred_loc: GPU ID, or 0 for system memory. + * addr: user mode address, in pages + * size: in pages + * pid: the process ID to generate the event + * ns: timestamp in nanosecond-resolution, starts at system boot time but + * stops during suspend + * migrate_update: GPU page fault is recovered by 'M' for migrate, 'U' for update + * rw: 'W' for write page fault, 'R' for read page fault + * rescheduled: 'R' if the queue restore failed and rescheduled to try again + */ +#define KFD_EVENT_FMT_UPDATE_GPU_RESET(reset_seq_num, reset_cause)\ + "%x %s\n", (reset_seq_num), (reset_cause) + +#define KFD_EVENT_FMT_THERMAL_THROTTLING(bitmask, counter)\ + "%llx:%llx\n", (bitmask), (counter) + +#define KFD_EVENT_FMT_VMFAULT(pid, task_name)\ + "%x:%s\n", (pid), (task_name) + +#define KFD_EVENT_FMT_PAGEFAULT_START(ns, pid, addr, node, rw)\ + "%lld -%d @%lx(%x) %c\n", (ns), (pid), (addr), (node), (rw) + +#define KFD_EVENT_FMT_PAGEFAULT_END(ns, pid, addr, node, migrate_update)\ + "%lld -%d @%lx(%x) %c\n", (ns), (pid), (addr), (node), (migrate_update) + +#define KFD_EVENT_FMT_MIGRATE_START(ns, pid, start, size, from, to, prefetch_loc,\ + preferred_loc, migrate_trigger)\ + "%lld -%d @%lx(%lx) %x->%x %x:%x %d\n", (ns), (pid), (start), (size),\ + (from), (to), (prefetch_loc), (preferred_loc), (migrate_trigger) + +#define KFD_EVENT_FMT_MIGRATE_END(ns, pid, start, size, from, to, migrate_trigger)\ + "%lld -%d @%lx(%lx) %x->%x %d\n", (ns), (pid), (start), (size),\ + (from), (to), (migrate_trigger) + +#define KFD_EVENT_FMT_QUEUE_EVICTION(ns, pid, node, evict_trigger)\ + "%lld -%d %x %d\n", (ns), (pid), (node), (evict_trigger) + +#define KFD_EVENT_FMT_QUEUE_RESTORE(ns, pid, node, rescheduled)\ + "%lld -%d %x %c\n", (ns), (pid), (node), (rescheduled) + +#define KFD_EVENT_FMT_UNMAP_FROM_GPU(ns, pid, addr, size, node, unmap_trigger)\ + "%lld -%d @%lx(%lx) %x %d\n", (ns), (pid), (addr), (size),\ + (node), (unmap_trigger) + /************************************************************************************************** * CRIU IOCTLs (Checkpoint Restore In Userspace) * From 54514a1958f08e8dcae0f257b6750ba9582c4fe6 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 5 Sep 2024 14:24:38 -0400 Subject: [PATCH 1498/1868] Revert "drm/amdgpu: align pp_power_profile_mode with kernel docs" This reverts commit bbb05f8a9cd87f5046d05a0c596fddfb714ee457. This breaks some manual setting of the profile mode in certain cases. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3600 Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 2b02da35cb428..87d6a23d28058 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -2266,7 +2266,8 @@ static int smu_adjust_power_state_dynamic(struct smu_context *smu, smu_dpm_ctx->dpm_level = level; } - if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { + if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && + smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) { index = fls(smu->workload_mask); index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; workload[0] = smu->workload_setting[index]; @@ -2345,7 +2346,8 @@ static int smu_switch_power_profile(void *handle, workload[0] = smu->workload_setting[index]; } - if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) + if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL && + smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) smu_bump_power_profile_mode(smu, workload, 0); return 0; From 080d30d41a64d23ed679bad2a138fe4e680679ef Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Wed, 4 Sep 2024 11:01:43 +0300 Subject: [PATCH 1499/1868] drm/amdgpu/mes11: Indent an if statment Indent the "break" statement one more tab. Signed-off-by: Dan Carpenter Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c index 0f055d1b1da6b..ee91ff9e52a20 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c @@ -415,7 +415,7 @@ static int mes_v11_0_reset_queue_mmio(struct amdgpu_mes *mes, uint32_t queue_typ /* wait till dequeue take effects */ for (i = 0; i < adev->usec_timeout; i++) { if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1)) - break; + break; udelay(1); } if (i >= adev->usec_timeout) { From dec07cfdaffbeda6471cd4edad88091dc3456718 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Tue, 27 Aug 2024 16:15:06 +0200 Subject: [PATCH 1500/1868] drm/amdgpu: revert "use CPU for page table update if SDMA is unavailable" MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit That is clearly not something we should do upstream. The SDMA is mandatory for the driver to work correctly. We could do this for emulation and bringup, but in those cases the engineer should probably enabled CPU based updates manually. This reverts commit 23335f9577e0b509c20ad8d65d9fdedd14545b55. Signed-off-by: Christian König Reviewed-by: Yifan Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index f494d541d24cb..0e959bac094e9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -2471,7 +2471,6 @@ void amdgpu_vm_set_task_info(struct amdgpu_vm *vm) int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, int32_t xcp_id) { - struct amdgpu_ip_block *ip_block; struct amdgpu_bo *root_bo; struct amdgpu_bo_vm *root; int r, i; @@ -2505,11 +2504,6 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode & AMDGPU_VM_USE_CPU_FOR_GFX); - /* use CPU for page table update if SDMA is unavailable */ - ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_SDMA); - if (!ip_block || ip_block->status.valid == false) - vm->use_cpu_for_update = true; - DRM_DEBUG_DRIVER("VM update mode is %s\n", vm->use_cpu_for_update ? "CPU" : "SDMA"); WARN_ONCE((vm->use_cpu_for_update && From 37a3aca3228dc811685f180e9b8e2ed922090851 Mon Sep 17 00:00:00 2001 From: Leo Li Date: Thu, 5 Sep 2024 18:45:04 -0400 Subject: [PATCH 1501/1868] drm/amd/display: Do not reset planes based on crtc zpos_changed [Why] drm_normalize_zpos will set the crtc_state->zpos_changed to 1 if any of it's assigned planes changes zpos, or is removed/added from it. To have amdgpu_dm request a plane reset on this is too broad. For example, if only the cursor plane was moved from one crtc to another, the crtc's zpos_changed will be set to true. But that does not mean that the underlying primary plane requires a reset. [How] Narrow it down so that only the plane that has a change in zpos will require a reset. As a future TODO, we can further optimize this by only requiring a reset on z-order change. Z-order is different from z-pos, since a zpos change doesn't necessarily mean the z-ordering changed, and DC should only require a reset if the z-ordering changed. For example, the following zpos update does not change z-ordering: Plane A: zpos 2 -> 3 Plane B: zpos 1 -> 2 => Plane A is still on top of plane B: no reset needed Whereas this one does change z-ordering: Plane A: zpos 2 -> 1 Plane B: zpos 1 -> 2 => Plane A changed from on top, to below plane B: reset needed Fixes: 38e0c3df6dbd ("drm/amd/display: Move PRIMARY plane zpos higher") Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3569 Signed-off-by: Leo Li Reviewed-by: Harry Wentland --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 76b6172d8e16c..ad067e0c68887 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -10873,7 +10873,7 @@ static bool should_reset_plane(struct drm_atomic_state *state, * TODO: We can likely skip bandwidth validation if the only thing that * changed about the plane was it'z z-ordering. */ - if (new_crtc_state->zpos_changed) + if (old_plane_state->normalized_zpos != new_plane_state->normalized_zpos) return true; if (drm_atomic_crtc_needs_modeset(new_crtc_state)) From 250489498c6bec38b72a965887899567921867d1 Mon Sep 17 00:00:00 2001 From: "Jesse.zhang@amd.com" Date: Fri, 6 Sep 2024 11:29:55 +0800 Subject: [PATCH 1502/1868] drm/amdkfd: Fix resource leak in riu rsetore queue To avoid memory leaks, release q_extra_data when exiting the restore queue. v2: Correct the proto (Alex) Signed-off-by: Jesse Zhang Reviewed-by: Tim Huang --- drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c index a9dba9a0b6029..120f36804618a 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c @@ -1050,6 +1050,7 @@ int kfd_criu_restore_queue(struct kfd_process *p, pr_debug("Queue id %d was restored successfully\n", queue_id); kfree(q_data); + kfree(q_extra_data); return ret; } From c685b552414e6c7d644f2424e8d6d23950d5b988 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 11 Sep 2024 10:51:46 +0800 Subject: [PATCH 1503/1868] Bump AMDGPU version to 6.10.1 Signed-off-by: Asher Song --- drivers/gpu/drm/amd/dkms/configure.ac | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/configure.ac b/drivers/gpu/drm/amd/dkms/configure.ac index e4dddf1c64de5..cd022ad0caf95 100644 --- a/drivers/gpu/drm/amd/dkms/configure.ac +++ b/drivers/gpu/drm/amd/dkms/configure.ac @@ -1,4 +1,4 @@ -AC_INIT(amdgpu-dkms, 6.10.0) +AC_INIT(amdgpu-dkms, 6.10.1) AC_LANG(C) AC_CONFIG_AUX_DIR([config]) From b5eb38b24def80353eabead19db09c6e40a0b907 Mon Sep 17 00:00:00 2001 From: Kenneth Feng Date: Thu, 5 Sep 2024 15:38:18 +0800 Subject: [PATCH 1504/1868] drm/amd/pm: update the features set on smu v14.0.2/3 update the features set on smu v14.0.2/3 Signed-off-by: Kenneth Feng Reviewed-by: Yang Wang --- drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h | 11 ++++++++++- drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c | 9 +++++++++ 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h index 2b8233d2bdf32..fa7449b289cac 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_types.h @@ -446,7 +446,16 @@ enum smu_clk_type { __SMU_DUMMY_MAP(BACO_CG), \ __SMU_DUMMY_MAP(SOC_CG), \ __SMU_DUMMY_MAP(LOW_POWER_DCNCLKS), \ - __SMU_DUMMY_MAP(WHISPER_MODE), + __SMU_DUMMY_MAP(WHISPER_MODE), \ + __SMU_DUMMY_MAP(EDC_PWRBRK), \ + __SMU_DUMMY_MAP(SOC_EDC_XVMIN), \ + __SMU_DUMMY_MAP(GFX_PSM_DIDT), \ + __SMU_DUMMY_MAP(APT_ALL_ENABLE), \ + __SMU_DUMMY_MAP(APT_SQ_THROTTLE), \ + __SMU_DUMMY_MAP(APT_PF_DCS), \ + __SMU_DUMMY_MAP(GFX_EDC_XVMIN), \ + __SMU_DUMMY_MAP(GFX_DIDT_XVMIN), \ + __SMU_DUMMY_MAP(FAN_ABNORMAL), #undef __SMU_DUMMY_MAP #define __SMU_DUMMY_MAP(feature) SMU_FEATURE_##feature##_BIT diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c index a31fae5feedfe..7125f72d01f25 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c @@ -199,6 +199,15 @@ static struct cmn2asic_mapping smu_v14_0_2_feature_mask_map[SMU_FEATURE_COUNT] = FEA_MAP(MEM_TEMP_READ), FEA_MAP(ATHUB_MMHUB_PG), FEA_MAP(SOC_PCC), + FEA_MAP(EDC_PWRBRK), + FEA_MAP(SOC_EDC_XVMIN), + FEA_MAP(GFX_PSM_DIDT), + FEA_MAP(APT_ALL_ENABLE), + FEA_MAP(APT_SQ_THROTTLE), + FEA_MAP(APT_PF_DCS), + FEA_MAP(GFX_EDC_XVMIN), + FEA_MAP(GFX_DIDT_XVMIN), + FEA_MAP(FAN_ABNORMAL), [SMU_FEATURE_DPM_VCLK_BIT] = {1, FEATURE_MM_DPM_BIT}, [SMU_FEATURE_DPM_DCLK_BIT] = {1, FEATURE_MM_DPM_BIT}, [SMU_FEATURE_PPT_BIT] = {1, FEATURE_THROTTLERS_BIT}, From 842d918e65e1ee74ace71c788917a3b41a99822e Mon Sep 17 00:00:00 2001 From: Kenneth Feng Date: Fri, 6 Sep 2024 20:46:54 +0800 Subject: [PATCH 1505/1868] drm/amd/pm: fix the pp_dpm_pcie issue on smu v14.0.2/3 fix the pp_dpm_pcie issue on smu v14.0.2/3 as below: 0: 2.5GT/s, x4 250Mhz 1: 8.0GT/s, x4 616Mhz * 2: 8.0GT/s, x4 1143Mhz * the middle level can be removed since it is always skipped on smu v14.0.2/3 Signed-off-by: Kenneth Feng Acked-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c index 7125f72d01f25..43820d7d2c54a 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c @@ -696,6 +696,9 @@ static int smu_v14_0_2_set_default_dpm_table(struct smu_context *smu) pcie_table->clk_freq[pcie_table->num_of_link_levels] = skutable->LclkFreq[link_level]; pcie_table->num_of_link_levels++; + + if (link_level == 0) + link_level++; } /* dcefclk dpm table setup */ From 26a696dfcfc66a96fcb2f22f1473319f0cbbb609 Mon Sep 17 00:00:00 2001 From: Hamza Mahfooz Date: Fri, 9 Aug 2024 16:42:53 -0400 Subject: [PATCH 1506/1868] drm/amd/display: change the panel power savings level without a modeset We don't actually need to request that the compositor does a full modeset to modify the panel power savings level, we can instead just make a request to DMUB, to set the new level dynamically. Cc: Harry Wentland Cc: Leo Li Cc: Mario Limonciello Cc: Sebastian Wick Signed-off-by: Hamza Mahfooz Tested-by: Mario Limonciello Reviewed-by: Mario Limonciello Closes: https://gitlab.gnome.org/GNOME/mutter/-/issues/3578 Signed-off-by: Mario Limonciello --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 17 +++++++- drivers/gpu/drm/amd/display/dc/core/dc.c | 39 +++++++++++-------- drivers/gpu/drm/amd/display/dc/dc.h | 2 + 3 files changed, 41 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index ad067e0c68887..2aafeeaa41eb8 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -7045,9 +7045,14 @@ static ssize_t panel_power_savings_store(struct device *device, const char *buf, size_t count) { struct drm_connector *connector = dev_get_drvdata(device); + struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector); struct drm_device *dev = connector->dev; + struct amdgpu_device *adev = drm_to_adev(dev); + struct dc *dc = adev->dm.dc; + struct pipe_ctx *pipe_ctx; long val; int ret; + int i; ret = kstrtol(buf, 0, &val); @@ -7062,7 +7067,17 @@ static ssize_t panel_power_savings_store(struct device *device, ABM_LEVEL_IMMEDIATE_DISABLE; drm_modeset_unlock(&dev->mode_config.connection_mutex); - drm_kms_helper_hotplug_event(dev); + mutex_lock(&adev->dm.dc_lock); + for (i = 0; i < dc->res_pool->pipe_count; i++) { + pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; + + if (pipe_ctx->stream && + pipe_ctx->stream->link == aconn->dc_link) { + dc_set_abm_level(dc, pipe_ctx, val); + break; + } + } + mutex_unlock(&adev->dm.dc_lock); return count; } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index a5a988fe1e742..95120a0e126e5 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -3251,6 +3251,23 @@ static bool update_planes_and_stream_state(struct dc *dc, } +void dc_set_abm_level(struct dc *dc, struct pipe_ctx *pipe_ctx, int level) +{ + struct timing_generator *tg = pipe_ctx->stream_res.tg; + struct abm *abm = pipe_ctx->stream_res.abm; + + if (!abm) + return; + + if (tg->funcs->is_blanked && !tg->funcs->is_blanked(tg)) + tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK); + + if (level == ABM_LEVEL_IMMEDIATE_DISABLE) + dc->hwss.set_abm_immediate_disable(pipe_ctx); + else + abm->funcs->set_abm_level(abm, level); +} + static void commit_planes_do_stream_update(struct dc *dc, struct dc_stream_state *stream, struct dc_stream_update *stream_update, @@ -3379,22 +3396,12 @@ static void commit_planes_do_stream_update(struct dc *dc, dc->link_srv->set_dpms_on(dc->current_state, pipe_ctx); } - if (stream_update->abm_level && pipe_ctx->stream_res.abm) { - bool should_program_abm = true; - - // if otg funcs defined check if blanked before programming - if (pipe_ctx->stream_res.tg->funcs->is_blanked) - if (pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg)) - should_program_abm = false; - - if (should_program_abm) { - if (*stream_update->abm_level == ABM_LEVEL_IMMEDIATE_DISABLE) { - dc->hwss.set_abm_immediate_disable(pipe_ctx); - } else { - pipe_ctx->stream_res.abm->funcs->set_abm_level( - pipe_ctx->stream_res.abm, stream->abm_level); - } - } + if (stream_update->abm_level) { + dc_set_abm_level(dc, pipe_ctx, + *stream_update->abm_level == + ABM_LEVEL_IMMEDIATE_DISABLE ? + ABM_LEVEL_IMMEDIATE_DISABLE : + stream->abm_level); } } } diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 7542b0b1c3217..2e254c16e6425 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -2498,6 +2498,8 @@ void dc_z10_save_init(struct dc *dc); bool dc_is_dmub_outbox_supported(struct dc *dc); bool dc_enable_dmub_notifications(struct dc *dc); +void dc_set_abm_level(struct dc *dc, struct pipe_ctx *pipe_ctx, int level); + bool dc_abm_save_restore( struct dc *dc, struct dc_stream_state *stream, From 697543aa9b1db419bd38058735ae82c6344dc2f5 Mon Sep 17 00:00:00 2001 From: "David (Ming Qiang) Wu" Date: Fri, 16 Aug 2024 11:43:05 -0400 Subject: [PATCH 1507/1868] drm/amd/amdgpu: apply command submission parser for JPEG v2+ This patch extends the same cs parser from JPEG v4.0.3 to other JPEG versions (v2 and above). Rename to more common name as jpeg_v2_dec_ring_parse_cs() from jpeg_v4_0_3_dec_ring_parse_cs(). Acked-by: Alex Deucher Signed-off-by: David (Ming Qiang) Wu --- drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c | 63 +++++++++++++++++++++++- drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.h | 6 +++ drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c | 2 + drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c | 1 + drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c | 1 + drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.h | 1 - drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 57 +-------------------- drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.h | 7 +-- drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c | 1 + drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c | 3 +- 10 files changed, 78 insertions(+), 64 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c index 98aa3ccd0d202..41c0f8750dc1d 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c @@ -23,6 +23,7 @@ #include "amdgpu.h" #include "amdgpu_jpeg.h" +#include "amdgpu_cs.h" #include "amdgpu_pm.h" #include "soc15.h" #include "soc15d.h" @@ -538,7 +539,11 @@ void jpeg_v2_0_dec_ring_emit_ib(struct amdgpu_ring *ring, amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JRBC_IB_VMID_INTERNAL_OFFSET, 0, 0, PACKETJ_TYPE0)); - amdgpu_ring_write(ring, (vmid | (vmid << 4) | (vmid << 8))); + + if (ring->funcs->parse_cs) + amdgpu_ring_write(ring, 0); + else + amdgpu_ring_write(ring, (vmid | (vmid << 4) | (vmid << 8))); amdgpu_ring_write(ring, PACKETJ(mmUVD_LMI_JPEG_VMID_INTERNAL_OFFSET, 0, 0, PACKETJ_TYPE0)); @@ -764,6 +769,7 @@ static const struct amdgpu_ring_funcs jpeg_v2_0_dec_ring_vm_funcs = { .get_rptr = jpeg_v2_0_dec_ring_get_rptr, .get_wptr = jpeg_v2_0_dec_ring_get_wptr, .set_wptr = jpeg_v2_0_dec_ring_set_wptr, + .parse_cs = jpeg_v2_dec_ring_parse_cs, .emit_frame_size = SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + @@ -810,3 +816,58 @@ const struct amdgpu_ip_block_version jpeg_v2_0_ip_block = { .rev = 0, .funcs = &jpeg_v2_0_ip_funcs, }; + +/** + * jpeg_v2_dec_ring_parse_cs - command submission parser + * + * @parser: Command submission parser context + * @job: the job to parse + * @ib: the IB to parse + * + * Parse the command stream, return -EINVAL for invalid packet, + * 0 otherwise + */ +int jpeg_v2_dec_ring_parse_cs(struct amdgpu_cs_parser *parser, + struct amdgpu_job *job, + struct amdgpu_ib *ib) +{ + u32 i, reg, res, cond, type; + struct amdgpu_device *adev = parser->adev; + + for (i = 0; i < ib->length_dw ; i += 2) { + reg = CP_PACKETJ_GET_REG(ib->ptr[i]); + res = CP_PACKETJ_GET_RES(ib->ptr[i]); + cond = CP_PACKETJ_GET_COND(ib->ptr[i]); + type = CP_PACKETJ_GET_TYPE(ib->ptr[i]); + + if (res) /* only support 0 at the moment */ + return -EINVAL; + + switch (type) { + case PACKETJ_TYPE0: + if (cond != PACKETJ_CONDITION_CHECK0 || reg < JPEG_REG_RANGE_START || + reg > JPEG_REG_RANGE_END) { + dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]); + return -EINVAL; + } + break; + case PACKETJ_TYPE3: + if (cond != PACKETJ_CONDITION_CHECK3 || reg < JPEG_REG_RANGE_START || + reg > JPEG_REG_RANGE_END) { + dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]); + return -EINVAL; + } + break; + case PACKETJ_TYPE6: + if (ib->ptr[i] == CP_PACKETJ_NOP) + continue; + dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]); + return -EINVAL; + default: + dev_err(adev->dev, "Unknown packet type %d !\n", type); + return -EINVAL; + } + } + + return 0; +} diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.h b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.h index 654e43e83e2c4..63fadda7a6733 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.h +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.h @@ -45,6 +45,9 @@ #define JRBC_DEC_EXTERNAL_REG_WRITE_ADDR 0x18000 +#define JPEG_REG_RANGE_START 0x4000 +#define JPEG_REG_RANGE_END 0x41c2 + void jpeg_v2_0_dec_ring_insert_start(struct amdgpu_ring *ring); void jpeg_v2_0_dec_ring_insert_end(struct amdgpu_ring *ring); void jpeg_v2_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, @@ -57,6 +60,9 @@ void jpeg_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring, unsigned vmid, uint64_t pd_addr); void jpeg_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val); void jpeg_v2_0_dec_ring_nop(struct amdgpu_ring *ring, uint32_t count); +int jpeg_v2_dec_ring_parse_cs(struct amdgpu_cs_parser *parser, + struct amdgpu_job *job, + struct amdgpu_ib *ib); extern const struct amdgpu_ip_block_version jpeg_v2_0_ip_block; diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c index d8ef95c847c2a..eedb9a829d950 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c @@ -662,6 +662,7 @@ static const struct amdgpu_ring_funcs jpeg_v2_5_dec_ring_vm_funcs = { .get_rptr = jpeg_v2_5_dec_ring_get_rptr, .get_wptr = jpeg_v2_5_dec_ring_get_wptr, .set_wptr = jpeg_v2_5_dec_ring_set_wptr, + .parse_cs = jpeg_v2_dec_ring_parse_cs, .emit_frame_size = SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + @@ -691,6 +692,7 @@ static const struct amdgpu_ring_funcs jpeg_v2_6_dec_ring_vm_funcs = { .get_rptr = jpeg_v2_5_dec_ring_get_rptr, .get_wptr = jpeg_v2_5_dec_ring_get_wptr, .set_wptr = jpeg_v2_5_dec_ring_set_wptr, + .parse_cs = jpeg_v2_dec_ring_parse_cs, .emit_frame_size = SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c index 31cfa3ce6528d..b1e7fd25afbcb 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c @@ -560,6 +560,7 @@ static const struct amdgpu_ring_funcs jpeg_v3_0_dec_ring_vm_funcs = { .get_rptr = jpeg_v3_0_dec_ring_get_rptr, .get_wptr = jpeg_v3_0_dec_ring_get_wptr, .set_wptr = jpeg_v3_0_dec_ring_set_wptr, + .parse_cs = jpeg_v2_dec_ring_parse_cs, .emit_frame_size = SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c index 3dac8f259d7fb..6c5c1a68a9b7b 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c @@ -727,6 +727,7 @@ static const struct amdgpu_ring_funcs jpeg_v4_0_dec_ring_vm_funcs = { .get_rptr = jpeg_v4_0_dec_ring_get_rptr, .get_wptr = jpeg_v4_0_dec_ring_get_wptr, .set_wptr = jpeg_v4_0_dec_ring_set_wptr, + .parse_cs = jpeg_v2_dec_ring_parse_cs, .emit_frame_size = SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.h b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.h index 07d36c2abd6bb..47638fd4d4e21 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.h +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.h @@ -32,5 +32,4 @@ enum amdgpu_jpeg_v4_0_sub_block { }; extern const struct amdgpu_ip_block_version jpeg_v4_0_ip_block; - #endif /* __JPEG_V4_0_H__ */ diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c index 8219248a9a870..de67fb48d3b8a 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c @@ -23,9 +23,9 @@ #include "amdgpu.h" #include "amdgpu_jpeg.h" -#include "amdgpu_cs.h" #include "soc15.h" #include "soc15d.h" +#include "jpeg_v2_0.h" #include "jpeg_v4_0_3.h" #include "mmsch_v4_0_3.h" @@ -1081,7 +1081,7 @@ static const struct amdgpu_ring_funcs jpeg_v4_0_3_dec_ring_vm_funcs = { .get_rptr = jpeg_v4_0_3_dec_ring_get_rptr, .get_wptr = jpeg_v4_0_3_dec_ring_get_wptr, .set_wptr = jpeg_v4_0_3_dec_ring_set_wptr, - .parse_cs = jpeg_v4_0_3_dec_ring_parse_cs, + .parse_cs = jpeg_v2_dec_ring_parse_cs, .emit_frame_size = SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + @@ -1246,56 +1246,3 @@ static void jpeg_v4_0_3_set_ras_funcs(struct amdgpu_device *adev) { adev->jpeg.ras = &jpeg_v4_0_3_ras; } - -/** - * jpeg_v4_0_3_dec_ring_parse_cs - command submission parser - * - * @parser: Command submission parser context - * @job: the job to parse - * @ib: the IB to parse - * - * Parse the command stream, return -EINVAL for invalid packet, - * 0 otherwise - */ -int jpeg_v4_0_3_dec_ring_parse_cs(struct amdgpu_cs_parser *parser, - struct amdgpu_job *job, - struct amdgpu_ib *ib) -{ - uint32_t i, reg, res, cond, type; - struct amdgpu_device *adev = parser->adev; - - for (i = 0; i < ib->length_dw ; i += 2) { - reg = CP_PACKETJ_GET_REG(ib->ptr[i]); - res = CP_PACKETJ_GET_RES(ib->ptr[i]); - cond = CP_PACKETJ_GET_COND(ib->ptr[i]); - type = CP_PACKETJ_GET_TYPE(ib->ptr[i]); - - if (res) /* only support 0 at the moment */ - return -EINVAL; - - switch (type) { - case PACKETJ_TYPE0: - if (cond != PACKETJ_CONDITION_CHECK0 || reg < JPEG_REG_RANGE_START || reg > JPEG_REG_RANGE_END) { - dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]); - return -EINVAL; - } - break; - case PACKETJ_TYPE3: - if (cond != PACKETJ_CONDITION_CHECK3 || reg < JPEG_REG_RANGE_START || reg > JPEG_REG_RANGE_END) { - dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]); - return -EINVAL; - } - break; - case PACKETJ_TYPE6: - if (ib->ptr[i] == CP_PACKETJ_NOP) - continue; - dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]); - return -EINVAL; - default: - dev_err(adev->dev, "Unknown packet type %d !\n", type); - return -EINVAL; - } - } - - return 0; -} diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.h b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.h index 71c54b294e157..747a3e5f68564 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.h +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.h @@ -46,9 +46,6 @@ #define JRBC_DEC_EXTERNAL_REG_WRITE_ADDR 0x18000 -#define JPEG_REG_RANGE_START 0x4000 -#define JPEG_REG_RANGE_END 0x41c2 - extern const struct amdgpu_ip_block_version jpeg_v4_0_3_ip_block; void jpeg_v4_0_3_dec_ring_emit_ib(struct amdgpu_ring *ring, @@ -65,7 +62,5 @@ void jpeg_v4_0_3_dec_ring_insert_end(struct amdgpu_ring *ring); void jpeg_v4_0_3_dec_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val); void jpeg_v4_0_3_dec_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, uint32_t val, uint32_t mask); -int jpeg_v4_0_3_dec_ring_parse_cs(struct amdgpu_cs_parser *parser, - struct amdgpu_job *job, - struct amdgpu_ib *ib); + #endif /* __JPEG_V4_0_3_H__ */ diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c index f96ac6bce526d..44eeed445ea91 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c @@ -768,6 +768,7 @@ static const struct amdgpu_ring_funcs jpeg_v4_0_5_dec_ring_vm_funcs = { .get_rptr = jpeg_v4_0_5_dec_ring_get_rptr, .get_wptr = jpeg_v4_0_5_dec_ring_get_wptr, .set_wptr = jpeg_v4_0_5_dec_ring_set_wptr, + .parse_cs = jpeg_v2_dec_ring_parse_cs, .emit_frame_size = SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c index f4daff90c7709..d662aa841f971 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c @@ -26,6 +26,7 @@ #include "amdgpu_pm.h" #include "soc15.h" #include "soc15d.h" +#include "jpeg_v2_0.h" #include "jpeg_v4_0_3.h" #include "vcn/vcn_5_0_0_offset.h" @@ -646,7 +647,7 @@ static const struct amdgpu_ring_funcs jpeg_v5_0_0_dec_ring_vm_funcs = { .get_rptr = jpeg_v5_0_0_dec_ring_get_rptr, .get_wptr = jpeg_v5_0_0_dec_ring_get_wptr, .set_wptr = jpeg_v5_0_0_dec_ring_set_wptr, - .parse_cs = jpeg_v4_0_3_dec_ring_parse_cs, + .parse_cs = jpeg_v2_dec_ring_parse_cs, .emit_frame_size = SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + From a7c07d0c2641fee94b40d7a20bdffa3d7a1cace7 Mon Sep 17 00:00:00 2001 From: "David (Ming Qiang) Wu" Date: Thu, 5 Sep 2024 16:57:28 -0400 Subject: [PATCH 1508/1868] drm/amd/amdgpu: apply command submission parser for JPEG v1 Similar to jpeg_v2_dec_ring_parse_cs() but it has different register ranges and a few other registers access. Acked-by: Alex Deucher Signed-off-by: David (Ming Qiang) Wu --- drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c | 76 +++++++++++++++++++++++++- drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.h | 11 ++++ 2 files changed, 86 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c index 71f43a5c7f721..6e0e88076224b 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c @@ -23,6 +23,7 @@ #include "amdgpu.h" #include "amdgpu_jpeg.h" +#include "amdgpu_cs.h" #include "soc15.h" #include "soc15d.h" #include "vcn_v1_0.h" @@ -34,6 +35,9 @@ static void jpeg_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev); static void jpeg_v1_0_set_irq_funcs(struct amdgpu_device *adev); static void jpeg_v1_0_ring_begin_use(struct amdgpu_ring *ring); +static int jpeg_v1_dec_ring_parse_cs(struct amdgpu_cs_parser *parser, + struct amdgpu_job *job, + struct amdgpu_ib *ib); static void jpeg_v1_0_decode_ring_patch_wreg(struct amdgpu_ring *ring, uint32_t *ptr, uint32_t reg_offset, uint32_t val) { @@ -300,7 +304,10 @@ static void jpeg_v1_0_decode_ring_emit_ib(struct amdgpu_ring *ring, amdgpu_ring_write(ring, PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JRBC_IB_VMID), 0, 0, PACKETJ_TYPE0)); - amdgpu_ring_write(ring, (vmid | (vmid << 4))); + if (ring->funcs->parse_cs) + amdgpu_ring_write(ring, 0); + else + amdgpu_ring_write(ring, (vmid | (vmid << 4))); amdgpu_ring_write(ring, PACKETJ(SOC15_REG_OFFSET(JPEG, 0, mmUVD_LMI_JPEG_VMID), 0, 0, PACKETJ_TYPE0)); @@ -554,6 +561,7 @@ static const struct amdgpu_ring_funcs jpeg_v1_0_decode_ring_vm_funcs = { .get_rptr = jpeg_v1_0_decode_ring_get_rptr, .get_wptr = jpeg_v1_0_decode_ring_get_wptr, .set_wptr = jpeg_v1_0_decode_ring_set_wptr, + .parse_cs = jpeg_v1_dec_ring_parse_cs, .emit_frame_size = 6 + 6 + /* hdp invalidate / flush */ SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + @@ -611,3 +619,69 @@ static void jpeg_v1_0_ring_begin_use(struct amdgpu_ring *ring) vcn_v1_0_set_pg_for_begin_use(ring, set_clocks); } + +/** + * jpeg_v1_dec_ring_parse_cs - command submission parser + * + * @parser: Command submission parser context + * @job: the job to parse + * @ib: the IB to parse + * + * Parse the command stream, return -EINVAL for invalid packet, + * 0 otherwise + */ +static int jpeg_v1_dec_ring_parse_cs(struct amdgpu_cs_parser *parser, + struct amdgpu_job *job, + struct amdgpu_ib *ib) +{ + u32 i, reg, res, cond, type; + int ret = 0; + struct amdgpu_device *adev = parser->adev; + + for (i = 0; i < ib->length_dw ; i += 2) { + reg = CP_PACKETJ_GET_REG(ib->ptr[i]); + res = CP_PACKETJ_GET_RES(ib->ptr[i]); + cond = CP_PACKETJ_GET_COND(ib->ptr[i]); + type = CP_PACKETJ_GET_TYPE(ib->ptr[i]); + + if (res || cond != PACKETJ_CONDITION_CHECK0) /* only allow 0 for now */ + return -EINVAL; + + if (reg >= JPEG_V1_REG_RANGE_START && reg <= JPEG_V1_REG_RANGE_END) + continue; + + switch (type) { + case PACKETJ_TYPE0: + if (reg != JPEG_V1_LMI_JPEG_WRITE_64BIT_BAR_HIGH && + reg != JPEG_V1_LMI_JPEG_WRITE_64BIT_BAR_LOW && + reg != JPEG_V1_LMI_JPEG_READ_64BIT_BAR_HIGH && + reg != JPEG_V1_LMI_JPEG_READ_64BIT_BAR_LOW && + reg != JPEG_V1_REG_CTX_INDEX && + reg != JPEG_V1_REG_CTX_DATA) { + ret = -EINVAL; + } + break; + case PACKETJ_TYPE1: + if (reg != JPEG_V1_REG_CTX_DATA) + ret = -EINVAL; + break; + case PACKETJ_TYPE3: + if (reg != JPEG_V1_REG_SOFT_RESET) + ret = -EINVAL; + break; + case PACKETJ_TYPE6: + if (ib->ptr[i] != CP_PACKETJ_NOP) + ret = -EINVAL; + break; + default: + ret = -EINVAL; + } + + if (ret) { + dev_err(adev->dev, "Invalid packet [0x%08x]!\n", ib->ptr[i]); + break; + } + } + + return ret; +} diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.h b/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.h index bbf33a6a39729..9654d22e03763 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.h +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.h @@ -29,4 +29,15 @@ int jpeg_v1_0_sw_init(void *handle); void jpeg_v1_0_sw_fini(void *handle); void jpeg_v1_0_start(struct amdgpu_device *adev, int mode); +#define JPEG_V1_REG_RANGE_START 0x8000 +#define JPEG_V1_REG_RANGE_END 0x803f + +#define JPEG_V1_LMI_JPEG_WRITE_64BIT_BAR_HIGH 0x8238 +#define JPEG_V1_LMI_JPEG_WRITE_64BIT_BAR_LOW 0x8239 +#define JPEG_V1_LMI_JPEG_READ_64BIT_BAR_HIGH 0x825a +#define JPEG_V1_LMI_JPEG_READ_64BIT_BAR_LOW 0x825b +#define JPEG_V1_REG_CTX_INDEX 0x8328 +#define JPEG_V1_REG_CTX_DATA 0x8329 +#define JPEG_V1_REG_SOFT_RESET 0x83a0 + #endif /*__JPEG_V1_0_H__*/ From 52bacc75bdbdca2f2ab4c525dd4c6c4d86ed9ff0 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 6 Sep 2024 13:45:23 -0400 Subject: [PATCH 1509/1868] Revert "drm/amdgpu: Add flags to distinguish vf/pf/pt mode" This reverts commit f03b874313cc9b5859596fe9c5b368387b6da771. This is unused so far and has not gone upstream yet, so remove it until the userspace side is ready. Having this in the tree just makes it more difficult to deal with version bumps. Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 9 --------- include/uapi/drm/amdgpu_drm.h | 10 ---------- 3 files changed, 1 insertion(+), 21 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 94b1d1f169a3b..9b85f832a59e4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -117,10 +117,9 @@ * - 3.56.0 - Update IB start address and size alignment for decode and encode * - 3.57.0 - Compute tunneling on GFX10+ * - 3.58.0 - Add GFX12 DCC support - * - 3.59.0 - Add AMDGPU_IDS_FLAGS_MODE_PF, AMDGPU_IDS_FLAGS_MODE_VF & AMDGPU_IDS_FLAGS_MODE_PT */ #define KMS_DRIVER_MAJOR 3 -#define KMS_DRIVER_MINOR 59 +#define KMS_DRIVER_MINOR 58 #define KMS_DRIVER_PATCHLEVEL 0 /* diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c index cb12c0ca46450..5ffe1dad96227 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c @@ -906,15 +906,6 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) if (adev->gfx.config.ta_cntl2_truncate_coord_mode) dev_info->ids_flags |= AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD; - if (amdgpu_passthrough(adev)) - dev_info->ids_flags |= (AMDGPU_IDS_FLAGS_MODE_PT << - AMDGPU_IDS_FLAGS_MODE_SHIFT) & - AMDGPU_IDS_FLAGS_MODE_MASK; - else if (amdgpu_sriov_vf(adev)) - dev_info->ids_flags |= (AMDGPU_IDS_FLAGS_MODE_VF << - AMDGPU_IDS_FLAGS_MODE_SHIFT) & - AMDGPU_IDS_FLAGS_MODE_MASK; - vm_size = adev->vm_manager.max_pfn * AMDGPU_GPU_PAGE_SIZE; vm_size -= AMDGPU_VA_RESERVED_TOP; diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index 03284eab9127a..6daa4a9434325 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -816,16 +816,6 @@ struct drm_amdgpu_cs_chunk_cp_gfx_shadow { #define AMDGPU_IDS_FLAGS_TMZ 0x4 #define AMDGPU_IDS_FLAGS_CONFORMANT_TRUNC_COORD 0x8 -/* - * Query h/w info: Flag identifying VF/PF/PT mode - * - */ -#define AMDGPU_IDS_FLAGS_MODE_MASK 0x300 -#define AMDGPU_IDS_FLAGS_MODE_SHIFT 0x8 -#define AMDGPU_IDS_FLAGS_MODE_PF 0x0 -#define AMDGPU_IDS_FLAGS_MODE_VF 0x1 -#define AMDGPU_IDS_FLAGS_MODE_PT 0x2 - /* indicate if acceleration can be working */ #define AMDGPU_INFO_ACCEL_WORKING 0x00 /* get the crtc_id from the mode object id? */ From 9d1f0e7b194edee76d556f06c8653cae77f9c484 Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Wed, 4 Sep 2024 13:01:13 +0530 Subject: [PATCH 1510/1868] drm/amdgpu: Fix kdoc entry in 'amdgpu_vm_cpu_prepare' MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This commit updates described non-existent parameters 'resv' and 'sync_mode', and failed to describe the existing 'sync' parameter. Fixes the below with gcc W=1: drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c:50: warning: Function parameter or struct member 'sync' not described in 'amdgpu_vm_cpu_prepare' drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c:50: warning: Excess function parameter 'resv' description in 'amdgpu_vm_cpu_prepare' drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c:50: warning: Excess function parameter 'sync_mode' description in 'amdgpu_vm_cpu_prepare' Cc: Christian König Cc: Alex Deucher Signed-off-by: Srinivasan Shanmugam Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c index cd842351121a4..1e79d31544a98 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c @@ -39,8 +39,7 @@ static int amdgpu_vm_cpu_map_table(struct amdgpu_bo_vm *table) * amdgpu_vm_cpu_prepare - prepare page table update with the CPU * * @p: see amdgpu_vm_update_params definition - * @resv: reservation object with embedded fence - * @sync_mode: synchronization mode + * @sync: sync obj with fences to wait on * * Returns: * Negativ errno, 0 for success. From ade2e5cdafb4fb0be497b012345042636a469902 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 6 Sep 2024 10:42:45 -0400 Subject: [PATCH 1511/1868] drm/amdgpu/atomfirmware: Silence UBSAN warning Per the comments, these are variable sized arrays. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3613 Reviewed-by: Harry Wentland Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/include/atomfirmware.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/include/atomfirmware.h b/drivers/gpu/drm/amd/include/atomfirmware.h index 09cbc3afd6d89..b0fc22383e287 100644 --- a/drivers/gpu/drm/amd/include/atomfirmware.h +++ b/drivers/gpu/drm/amd/include/atomfirmware.h @@ -1038,7 +1038,7 @@ struct display_object_info_table_v1_4 uint16_t supporteddevices; uint8_t number_of_path; uint8_t reserved; - struct atom_display_object_path_v2 display_path[8]; //the real number of this included in the structure is calculated by using the (whole structure size - the header size- number_of_path)/size of atom_display_object_path + struct atom_display_object_path_v2 display_path[]; //the real number of this included in the structure is calculated by using the (whole structure size - the header size- number_of_path)/size of atom_display_object_path }; struct display_object_info_table_v1_5 { @@ -1048,7 +1048,7 @@ struct display_object_info_table_v1_5 { uint8_t reserved; // the real number of this included in the structure is calculated by using the // (whole structure size - the header size- number_of_path)/size of atom_display_object_path - struct atom_display_object_path_v3 display_path[8]; + struct atom_display_object_path_v3 display_path[]; }; /* From 769ed7695c139154f15c97c4660f2c144455994d Mon Sep 17 00:00:00 2001 From: Leo Li Date: Mon, 9 Sep 2024 16:15:23 -0400 Subject: [PATCH 1512/1868] Revert "drm/amd/display: change the panel power savings level without a modeset" This reverts commit 09d4eb07a643d11ac344857da57620483990c340. It's causing a failure in the abm_gradual igt test. Signed-off-by: Leo Li --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 17 +------- drivers/gpu/drm/amd/display/dc/core/dc.c | 39 ++++++++----------- drivers/gpu/drm/amd/display/dc/dc.h | 2 - 3 files changed, 17 insertions(+), 41 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 2aafeeaa41eb8..ad067e0c68887 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -7045,14 +7045,9 @@ static ssize_t panel_power_savings_store(struct device *device, const char *buf, size_t count) { struct drm_connector *connector = dev_get_drvdata(device); - struct amdgpu_dm_connector *aconn = to_amdgpu_dm_connector(connector); struct drm_device *dev = connector->dev; - struct amdgpu_device *adev = drm_to_adev(dev); - struct dc *dc = adev->dm.dc; - struct pipe_ctx *pipe_ctx; long val; int ret; - int i; ret = kstrtol(buf, 0, &val); @@ -7067,17 +7062,7 @@ static ssize_t panel_power_savings_store(struct device *device, ABM_LEVEL_IMMEDIATE_DISABLE; drm_modeset_unlock(&dev->mode_config.connection_mutex); - mutex_lock(&adev->dm.dc_lock); - for (i = 0; i < dc->res_pool->pipe_count; i++) { - pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; - - if (pipe_ctx->stream && - pipe_ctx->stream->link == aconn->dc_link) { - dc_set_abm_level(dc, pipe_ctx, val); - break; - } - } - mutex_unlock(&adev->dm.dc_lock); + drm_kms_helper_hotplug_event(dev); return count; } diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 95120a0e126e5..a5a988fe1e742 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -3251,23 +3251,6 @@ static bool update_planes_and_stream_state(struct dc *dc, } -void dc_set_abm_level(struct dc *dc, struct pipe_ctx *pipe_ctx, int level) -{ - struct timing_generator *tg = pipe_ctx->stream_res.tg; - struct abm *abm = pipe_ctx->stream_res.abm; - - if (!abm) - return; - - if (tg->funcs->is_blanked && !tg->funcs->is_blanked(tg)) - tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK); - - if (level == ABM_LEVEL_IMMEDIATE_DISABLE) - dc->hwss.set_abm_immediate_disable(pipe_ctx); - else - abm->funcs->set_abm_level(abm, level); -} - static void commit_planes_do_stream_update(struct dc *dc, struct dc_stream_state *stream, struct dc_stream_update *stream_update, @@ -3396,12 +3379,22 @@ static void commit_planes_do_stream_update(struct dc *dc, dc->link_srv->set_dpms_on(dc->current_state, pipe_ctx); } - if (stream_update->abm_level) { - dc_set_abm_level(dc, pipe_ctx, - *stream_update->abm_level == - ABM_LEVEL_IMMEDIATE_DISABLE ? - ABM_LEVEL_IMMEDIATE_DISABLE : - stream->abm_level); + if (stream_update->abm_level && pipe_ctx->stream_res.abm) { + bool should_program_abm = true; + + // if otg funcs defined check if blanked before programming + if (pipe_ctx->stream_res.tg->funcs->is_blanked) + if (pipe_ctx->stream_res.tg->funcs->is_blanked(pipe_ctx->stream_res.tg)) + should_program_abm = false; + + if (should_program_abm) { + if (*stream_update->abm_level == ABM_LEVEL_IMMEDIATE_DISABLE) { + dc->hwss.set_abm_immediate_disable(pipe_ctx); + } else { + pipe_ctx->stream_res.abm->funcs->set_abm_level( + pipe_ctx->stream_res.abm, stream->abm_level); + } + } } } } diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 2e254c16e6425..7542b0b1c3217 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -2498,8 +2498,6 @@ void dc_z10_save_init(struct dc *dc); bool dc_is_dmub_outbox_supported(struct dc *dc); bool dc_enable_dmub_notifications(struct dc *dc); -void dc_set_abm_level(struct dc *dc, struct pipe_ctx *pipe_ctx, int level); - bool dc_abm_save_restore( struct dc *dc, struct dc_stream_state *stream, From 39229f32bf61f769fb64863351add13a32b9f879 Mon Sep 17 00:00:00 2001 From: Hawking Zhang Date: Fri, 6 Sep 2024 16:06:13 +0800 Subject: [PATCH 1513/1868] drm/amdkfd: Select reset method for poison handling Driver mode-2 is only supported by relative new smc firmware. Signed-off-by: Hawking Zhang Reviewed-by: Tao Zhou --- .../gpu/drm/amd/amdkfd/kfd_int_process_v9.c | 40 +++++++++++++++---- 1 file changed, 32 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c index fecdbbab98949..d46a13156ee9d 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c @@ -167,11 +167,23 @@ static void event_interrupt_poison_consumption_v9(struct kfd_node *dev, case SOC15_IH_CLIENTID_SE3SH: case SOC15_IH_CLIENTID_UTCL2: block = AMDGPU_RAS_BLOCK__GFX; - if (amdgpu_ip_version(dev->adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || - amdgpu_ip_version(dev->adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) - reset = AMDGPU_RAS_GPU_RESET_MODE1_RESET; - else + if (amdgpu_ip_version(dev->adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) { + /* driver mode-2 for gfx poison is only supported by + * pmfw 0x00557300 and onwards */ + if (dev->adev->pm.fw_version < 0x00557300) + reset = AMDGPU_RAS_GPU_RESET_MODE1_RESET; + else + reset = AMDGPU_RAS_GPU_RESET_MODE2_RESET; + } else if (amdgpu_ip_version(dev->adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) { + /* driver mode-2 for gfx poison is only supported by + * pmfw 0x05550C00 and onwards */ + if (dev->adev->pm.fw_version < 0x05550C00) + reset = AMDGPU_RAS_GPU_RESET_MODE1_RESET; + else + reset = AMDGPU_RAS_GPU_RESET_MODE2_RESET; + } else { reset = AMDGPU_RAS_GPU_RESET_MODE2_RESET; + } break; case SOC15_IH_CLIENTID_VMC: case SOC15_IH_CLIENTID_VMC1: @@ -184,11 +196,23 @@ static void event_interrupt_poison_consumption_v9(struct kfd_node *dev, case SOC15_IH_CLIENTID_SDMA3: case SOC15_IH_CLIENTID_SDMA4: block = AMDGPU_RAS_BLOCK__SDMA; - if (amdgpu_ip_version(dev->adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || - amdgpu_ip_version(dev->adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) - reset = AMDGPU_RAS_GPU_RESET_MODE1_RESET; - else + if (amdgpu_ip_version(dev->adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 2)) { + /* driver mode-2 for gfx poison is only supported by + * pmfw 0x00557300 and onwards */ + if (dev->adev->pm.fw_version < 0x00557300) + reset = AMDGPU_RAS_GPU_RESET_MODE1_RESET; + else + reset = AMDGPU_RAS_GPU_RESET_MODE2_RESET; + } else if (amdgpu_ip_version(dev->adev, SDMA0_HWIP, 0) == IP_VERSION(4, 4, 5)) { + /* driver mode-2 for gfx poison is only supported by + * pmfw 0x05550C00 and onwards */ + if (dev->adev->pm.fw_version < 0x05550C00) + reset = AMDGPU_RAS_GPU_RESET_MODE1_RESET; + else + reset = AMDGPU_RAS_GPU_RESET_MODE2_RESET; + } else { reset = AMDGPU_RAS_GPU_RESET_MODE2_RESET; + } break; default: dev_warn(dev->adev->dev, From 6d77c36d48508f2955788eac234303b85f7647a3 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 12 Sep 2024 13:08:12 -0400 Subject: [PATCH 1514/1868] drm/amdgpu/gfx9.4.3: set additional bits on MEC halt Need to set the pipe reset and cache invalidation bits on halt otherwise we can get stale state if the CP firmware changes (e.g., on module unload and reload). Tested-by: Amber Lin Reviewed-by: Amber Lin Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index 408e5600bb617..9221b4e9a7f7e 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -1701,7 +1701,15 @@ static void gfx_v9_4_3_xcc_cp_compute_enable(struct amdgpu_device *adev, WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 0); } else { WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, - (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); + (CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK | + CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK | + CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK | + CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK | + CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK | + CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK | + CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK | + CP_MEC_CNTL__MEC_ME1_HALT_MASK | + CP_MEC_CNTL__MEC_ME2_HALT_MASK)); adev->gfx.kiq[xcc_id].ring.sched.ready = false; } udelay(50); From 1f0998eb9ab40a483a025e6ffd379b7be26b0399 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 12 Sep 2024 16:15:55 -0400 Subject: [PATCH 1515/1868] drm/amdgpu/gfx9.4.3: Explicitly halt MEC before init Need to make sure it's halted as we don't know what state the GPU may have been left in previously. Tested-by: Amber Lin Acked-by: Amber Lin Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index 9221b4e9a7f7e..1df55b83ec736 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -2248,6 +2248,8 @@ static int gfx_v9_4_3_xcc_cp_resume(struct amdgpu_device *adev, int xcc_id) r = gfx_v9_4_3_xcc_cp_compute_load_microcode(adev, xcc_id); if (r) return r; + } else { + gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id); } r = gfx_v9_4_3_xcc_kiq_resume(adev, xcc_id); From 53136cafb2d2f961cddf6e113a226628d8fb91d9 Mon Sep 17 00:00:00 2001 From: Jack Xiao Date: Wed, 11 Sep 2024 16:24:35 +0800 Subject: [PATCH 1516/1868] drm/amdgpu/mes12: switch SET_SHADER_DEBUGGER pkt to mes schq pipe The SET_SHADER_DEBUGGER packet must work with the added hardware queue, switch the packet submitting to mes schq pipe. Signed-off-by: Jack Xiao Acked-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c index e499b2857a01e..ef05a41162306 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c @@ -479,6 +479,11 @@ static int mes_v12_0_misc_op(struct amdgpu_mes *mes, union MESAPI__MISC misc_pkt; int pipe; + if (mes->adev->enable_uni_mes) + pipe = AMDGPU_MES_KIQ_PIPE; + else + pipe = AMDGPU_MES_SCHED_PIPE; + memset(&misc_pkt, 0, sizeof(misc_pkt)); misc_pkt.header.type = MES_API_TYPE_SCHEDULER; @@ -513,6 +518,7 @@ static int mes_v12_0_misc_op(struct amdgpu_mes *mes, misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1; break; case MES_MISC_OP_SET_SHADER_DEBUGGER: + pipe = AMDGPU_MES_SCHED_PIPE; misc_pkt.opcode = MESAPI_MISC__SET_SHADER_DEBUGGER; misc_pkt.set_shader_debugger.process_context_addr = input->set_shader_debugger.process_context_addr; @@ -530,11 +536,6 @@ static int mes_v12_0_misc_op(struct amdgpu_mes *mes, return -EINVAL; } - if (mes->adev->enable_uni_mes) - pipe = AMDGPU_MES_KIQ_PIPE; - else - pipe = AMDGPU_MES_SCHED_PIPE; - return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe, &misc_pkt, sizeof(misc_pkt), offsetof(union MESAPI__MISC, api_status)); From c23e3c1033d48ba00834cedec6856409e6ce3446 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 12 Sep 2024 16:15:55 -0400 Subject: [PATCH 1517/1868] drm/amdgpu/gfx9.4.3: Explicitly halt MEC before init Need to make sure it's halted as we don't know what state the GPU may have been left in previously. Tested-by: Amber Lin Acked-by: Amber Lin Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index 408e5600bb617..6c9c7ed2d56a2 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -2240,6 +2240,8 @@ static int gfx_v9_4_3_xcc_cp_resume(struct amdgpu_device *adev, int xcc_id) r = gfx_v9_4_3_xcc_cp_compute_load_microcode(adev, xcc_id); if (r) return r; + } else { + gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id); } r = gfx_v9_4_3_xcc_kiq_resume(adev, xcc_id); From 85cc6a77add1054685c1e6829d2628195cdd6a2b Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 13 Sep 2024 01:21:35 -0400 Subject: [PATCH 1518/1868] Revert "drm/amdgpu/gfx9.4.3: Explicitly halt MEC before init" This reverts commit c23e3c1033d48ba00834cedec6856409e6ce3446. Mistake merge this patch and it need more test Signed-off-by: Bob Zhou Change-Id: Ibfa10638daa90b5a1de46db30dbfc7b331719f88 --- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index 6c9c7ed2d56a2..408e5600bb617 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -2240,8 +2240,6 @@ static int gfx_v9_4_3_xcc_cp_resume(struct amdgpu_device *adev, int xcc_id) r = gfx_v9_4_3_xcc_cp_compute_load_microcode(adev, xcc_id); if (r) return r; - } else { - gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id); } r = gfx_v9_4_3_xcc_kiq_resume(adev, xcc_id); From df25188f7b7c9f04d64a335ffdb9e2aa33a1654e Mon Sep 17 00:00:00 2001 From: Jack Xiao Date: Wed, 11 Sep 2024 16:24:35 +0800 Subject: [PATCH 1519/1868] drm/amdgpu/mes12: switch SET_SHADER_DEBUGGER pkt to mes schq pipe The SET_SHADER_DEBUGGER packet must work with the added hardware queue, switch the packet submitting to mes schq pipe. Signed-off-by: Jack Xiao Acked-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c index e499b2857a01e..ef05a41162306 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c @@ -479,6 +479,11 @@ static int mes_v12_0_misc_op(struct amdgpu_mes *mes, union MESAPI__MISC misc_pkt; int pipe; + if (mes->adev->enable_uni_mes) + pipe = AMDGPU_MES_KIQ_PIPE; + else + pipe = AMDGPU_MES_SCHED_PIPE; + memset(&misc_pkt, 0, sizeof(misc_pkt)); misc_pkt.header.type = MES_API_TYPE_SCHEDULER; @@ -513,6 +518,7 @@ static int mes_v12_0_misc_op(struct amdgpu_mes *mes, misc_pkt.wait_reg_mem.reg_offset2 = input->wrm_reg.reg1; break; case MES_MISC_OP_SET_SHADER_DEBUGGER: + pipe = AMDGPU_MES_SCHED_PIPE; misc_pkt.opcode = MESAPI_MISC__SET_SHADER_DEBUGGER; misc_pkt.set_shader_debugger.process_context_addr = input->set_shader_debugger.process_context_addr; @@ -530,11 +536,6 @@ static int mes_v12_0_misc_op(struct amdgpu_mes *mes, return -EINVAL; } - if (mes->adev->enable_uni_mes) - pipe = AMDGPU_MES_KIQ_PIPE; - else - pipe = AMDGPU_MES_SCHED_PIPE; - return mes_v12_0_submit_pkt_and_poll_completion(mes, pipe, &misc_pkt, sizeof(misc_pkt), offsetof(union MESAPI__MISC, api_status)); From 06670c43433f931f16138e0e9bfe458e280f5610 Mon Sep 17 00:00:00 2001 From: Le Ma Date: Tue, 10 Sep 2024 17:53:42 +0800 Subject: [PATCH 1520/1868] drm/amdgpu: add psp funcs callback to check if aux fw is needed Query pmfw version to determine if aux sos fw needs to be loaded in psp v13.0. v2: refine callback to check if aux_fw loading is needed instead of getting pmfw version barely v3: return the comparison directly Signed-off-by: Le Ma Reviewed-by: Lijo Lazar Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 4 ++++ drivers/gpu/drm/amd/amdgpu/psp_v13_0.c | 17 +++++++++++++++++ 2 files changed, 21 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h index 74a96516c9138..e8abbbcb43266 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h @@ -138,6 +138,7 @@ struct psp_funcs { int (*vbflash_stat)(struct psp_context *psp); int (*fatal_error_recovery_quirk)(struct psp_context *psp); bool (*get_ras_capability)(struct psp_context *psp); + bool (*is_aux_sos_load_required)(struct psp_context *psp); }; struct ta_funcs { @@ -464,6 +465,9 @@ struct amdgpu_psp_funcs { ((psp)->funcs->fatal_error_recovery_quirk ? \ (psp)->funcs->fatal_error_recovery_quirk((psp)) : 0) +#define psp_is_aux_sos_load_required(psp) \ + ((psp)->funcs->is_aux_sos_load_required ? (psp)->funcs->is_aux_sos_load_required((psp)) : 0) + extern const struct amd_ip_funcs psp_ip_funcs; extern const struct amdgpu_ip_block_version psp_v3_1_ip_block; diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c index 1251ee38a6764..51e470e8d67d9 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c @@ -81,6 +81,8 @@ MODULE_FIRMWARE("amdgpu/psp_14_0_4_ta.bin"); /* memory training timeout define */ #define MEM_TRAIN_SEND_MSG_TIMEOUT_US 3000000 +#define regMP1_PUB_SCRATCH0 0x3b10090 + static int psp_v13_0_init_microcode(struct psp_context *psp) { struct amdgpu_device *adev = psp->adev; @@ -807,6 +809,20 @@ static bool psp_v13_0_get_ras_capability(struct psp_context *psp) } } +static bool psp_v13_0_is_aux_sos_load_required(struct psp_context *psp) +{ + struct amdgpu_device *adev = psp->adev; + u32 pmfw_ver; + + if (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6)) + return false; + + /* load 4e version of sos if pmfw version less than 85.115.0 */ + pmfw_ver = RREG32(regMP1_PUB_SCRATCH0 / 4); + + return (pmfw_ver < 0x557300); +} + static const struct psp_funcs psp_v13_0_funcs = { .init_microcode = psp_v13_0_init_microcode, .wait_for_bootloader = psp_v13_0_wait_for_bootloader_steady_state, @@ -830,6 +846,7 @@ static const struct psp_funcs psp_v13_0_funcs = { .vbflash_stat = psp_v13_0_vbflash_status, .fatal_error_recovery_quirk = psp_v13_0_fatal_error_recovery_quirk, .get_ras_capability = psp_v13_0_get_ras_capability, + .is_aux_sos_load_required = psp_v13_0_is_aux_sos_load_required, }; void psp_v13_0_set_psp_funcs(struct psp_context *psp) From 14a47654281d74a96e33a98db80fd13e10f9b775 Mon Sep 17 00:00:00 2001 From: Le Ma Date: Tue, 10 Sep 2024 20:10:45 +0800 Subject: [PATCH 1521/1868] drm/amdgpu: load sos binary properly on the basis of pmfw version To be compatible with legacy IFWI, driver needs to carry legacy tOS and query pmfw version to load them accordingly. Add psp_firmware_header_v2_1 to handle the combined sos binary. Double the sos count limit for the case of aux sos fw packed. v2: pass the correct fw_bin_desc to parse_sos_bin_descriptor Signed-off-by: Le Ma Reviewed-by: Lijo Lazar Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 29 ++++++++++++++++++----- drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 11 ++++++++- 2 files changed, 33 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index d6aeb53563ed0..09dad501d0402 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -3425,9 +3425,11 @@ int psp_init_sos_microcode(struct psp_context *psp, const char *chip_name) const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; const struct psp_firmware_header_v2_0 *sos_hdr_v2_0; - int err = 0; + const struct psp_firmware_header_v2_1 *sos_hdr_v2_1; + int fw_index, fw_bin_count, start_index = 0; + const struct psp_fw_bin_desc *fw_bin; uint8_t *ucode_array_start_addr; - int fw_index = 0; + int err = 0; err = amdgpu_ucode_request(adev, &adev->psp.sos_fw, "amdgpu/%s_sos.bin", chip_name); if (err) @@ -3478,15 +3480,30 @@ int psp_init_sos_microcode(struct psp_context *psp, const char *chip_name) case 2: sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data; - if (le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { + fw_bin_count = le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); + + if (fw_bin_count >= UCODE_MAX_PSP_PACKAGING) { dev_err(adev->dev, "packed SOS count exceeds maximum limit\n"); err = -EINVAL; goto out; } - for (fw_index = 0; fw_index < le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); fw_index++) { - err = parse_sos_bin_descriptor(psp, - &sos_hdr_v2_0->psp_fw_bin[fw_index], + if (sos_hdr_v2_0->header.header_version_minor == 1) { + sos_hdr_v2_1 = (const struct psp_firmware_header_v2_1 *)adev->psp.sos_fw->data; + + fw_bin = sos_hdr_v2_1->psp_fw_bin; + + if (psp_is_aux_sos_load_required(psp)) + start_index = le32_to_cpu(sos_hdr_v2_1->psp_aux_fw_bin_index); + else + fw_bin_count -= le32_to_cpu(sos_hdr_v2_1->psp_aux_fw_bin_index); + + } else { + fw_bin = sos_hdr_v2_0->psp_fw_bin; + } + + for (fw_index = start_index; fw_index < fw_bin_count; fw_index++) { + err = parse_sos_bin_descriptor(psp, fw_bin + fw_index, sos_hdr_v2_0); if (err) goto out; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h index 5bc37acd39819..4e23419b92d4e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h @@ -136,6 +136,14 @@ struct psp_firmware_header_v2_0 { struct psp_fw_bin_desc psp_fw_bin[]; }; +/* version_major=2, version_minor=1 */ +struct psp_firmware_header_v2_1 { + struct common_firmware_header header; + uint32_t psp_fw_bin_count; + uint32_t psp_aux_fw_bin_index; + struct psp_fw_bin_desc psp_fw_bin[]; +}; + /* version_major=1, version_minor=0 */ struct ta_firmware_header_v1_0 { struct common_firmware_header header; @@ -426,6 +434,7 @@ union amdgpu_firmware_header { struct psp_firmware_header_v1_1 psp_v1_1; struct psp_firmware_header_v1_3 psp_v1_3; struct psp_firmware_header_v2_0 psp_v2_0; + struct psp_firmware_header_v2_0 psp_v2_1; struct ta_firmware_header_v1_0 ta; struct ta_firmware_header_v2_0 ta_v2_0; struct gfx_firmware_header_v1_0 gfx; @@ -447,7 +456,7 @@ union amdgpu_firmware_header { uint8_t raw[0x100]; }; -#define UCODE_MAX_PSP_PACKAGING ((sizeof(union amdgpu_firmware_header) - sizeof(struct common_firmware_header) - 4) / sizeof(struct psp_fw_bin_desc)) +#define UCODE_MAX_PSP_PACKAGING (((sizeof(union amdgpu_firmware_header) - sizeof(struct common_firmware_header) - 4) / sizeof(struct psp_fw_bin_desc)) * 2) /* * fw loading support From d7238bc25f17e3aa24ff845f03e4ff705d1cbfcb Mon Sep 17 00:00:00 2001 From: Le Ma Date: Tue, 10 Sep 2024 17:53:42 +0800 Subject: [PATCH 1522/1868] drm/amdgpu: add psp funcs callback to check if aux fw is needed Query pmfw version to determine if aux sos fw needs to be loaded in psp v13.0. v2: refine callback to check if aux_fw loading is needed instead of getting pmfw version barely v3: return the comparison directly Signed-off-by: Le Ma Reviewed-by: Lijo Lazar Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 4 ++++ drivers/gpu/drm/amd/amdgpu/psp_v13_0.c | 17 +++++++++++++++++ 2 files changed, 21 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h index 74a96516c9138..e8abbbcb43266 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h @@ -138,6 +138,7 @@ struct psp_funcs { int (*vbflash_stat)(struct psp_context *psp); int (*fatal_error_recovery_quirk)(struct psp_context *psp); bool (*get_ras_capability)(struct psp_context *psp); + bool (*is_aux_sos_load_required)(struct psp_context *psp); }; struct ta_funcs { @@ -464,6 +465,9 @@ struct amdgpu_psp_funcs { ((psp)->funcs->fatal_error_recovery_quirk ? \ (psp)->funcs->fatal_error_recovery_quirk((psp)) : 0) +#define psp_is_aux_sos_load_required(psp) \ + ((psp)->funcs->is_aux_sos_load_required ? (psp)->funcs->is_aux_sos_load_required((psp)) : 0) + extern const struct amd_ip_funcs psp_ip_funcs; extern const struct amdgpu_ip_block_version psp_v3_1_ip_block; diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c index 1251ee38a6764..51e470e8d67d9 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c @@ -81,6 +81,8 @@ MODULE_FIRMWARE("amdgpu/psp_14_0_4_ta.bin"); /* memory training timeout define */ #define MEM_TRAIN_SEND_MSG_TIMEOUT_US 3000000 +#define regMP1_PUB_SCRATCH0 0x3b10090 + static int psp_v13_0_init_microcode(struct psp_context *psp) { struct amdgpu_device *adev = psp->adev; @@ -807,6 +809,20 @@ static bool psp_v13_0_get_ras_capability(struct psp_context *psp) } } +static bool psp_v13_0_is_aux_sos_load_required(struct psp_context *psp) +{ + struct amdgpu_device *adev = psp->adev; + u32 pmfw_ver; + + if (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6)) + return false; + + /* load 4e version of sos if pmfw version less than 85.115.0 */ + pmfw_ver = RREG32(regMP1_PUB_SCRATCH0 / 4); + + return (pmfw_ver < 0x557300); +} + static const struct psp_funcs psp_v13_0_funcs = { .init_microcode = psp_v13_0_init_microcode, .wait_for_bootloader = psp_v13_0_wait_for_bootloader_steady_state, @@ -830,6 +846,7 @@ static const struct psp_funcs psp_v13_0_funcs = { .vbflash_stat = psp_v13_0_vbflash_status, .fatal_error_recovery_quirk = psp_v13_0_fatal_error_recovery_quirk, .get_ras_capability = psp_v13_0_get_ras_capability, + .is_aux_sos_load_required = psp_v13_0_is_aux_sos_load_required, }; void psp_v13_0_set_psp_funcs(struct psp_context *psp) From 512a901b567bb6f57b6ef2e89766ac17df9d765f Mon Sep 17 00:00:00 2001 From: Le Ma Date: Tue, 10 Sep 2024 20:10:45 +0800 Subject: [PATCH 1523/1868] drm/amdgpu: load sos binary properly on the basis of pmfw version To be compatible with legacy IFWI, driver needs to carry legacy tOS and query pmfw version to load them accordingly. Add psp_firmware_header_v2_1 to handle the combined sos binary. Double the sos count limit for the case of aux sos fw packed. v2: pass the correct fw_bin_desc to parse_sos_bin_descriptor Signed-off-by: Le Ma Reviewed-by: Lijo Lazar Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 29 ++++++++++++++++++----- drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h | 11 ++++++++- 2 files changed, 33 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index d6aeb53563ed0..09dad501d0402 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -3425,9 +3425,11 @@ int psp_init_sos_microcode(struct psp_context *psp, const char *chip_name) const struct psp_firmware_header_v1_2 *sos_hdr_v1_2; const struct psp_firmware_header_v1_3 *sos_hdr_v1_3; const struct psp_firmware_header_v2_0 *sos_hdr_v2_0; - int err = 0; + const struct psp_firmware_header_v2_1 *sos_hdr_v2_1; + int fw_index, fw_bin_count, start_index = 0; + const struct psp_fw_bin_desc *fw_bin; uint8_t *ucode_array_start_addr; - int fw_index = 0; + int err = 0; err = amdgpu_ucode_request(adev, &adev->psp.sos_fw, "amdgpu/%s_sos.bin", chip_name); if (err) @@ -3478,15 +3480,30 @@ int psp_init_sos_microcode(struct psp_context *psp, const char *chip_name) case 2: sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data; - if (le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) { + fw_bin_count = le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); + + if (fw_bin_count >= UCODE_MAX_PSP_PACKAGING) { dev_err(adev->dev, "packed SOS count exceeds maximum limit\n"); err = -EINVAL; goto out; } - for (fw_index = 0; fw_index < le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); fw_index++) { - err = parse_sos_bin_descriptor(psp, - &sos_hdr_v2_0->psp_fw_bin[fw_index], + if (sos_hdr_v2_0->header.header_version_minor == 1) { + sos_hdr_v2_1 = (const struct psp_firmware_header_v2_1 *)adev->psp.sos_fw->data; + + fw_bin = sos_hdr_v2_1->psp_fw_bin; + + if (psp_is_aux_sos_load_required(psp)) + start_index = le32_to_cpu(sos_hdr_v2_1->psp_aux_fw_bin_index); + else + fw_bin_count -= le32_to_cpu(sos_hdr_v2_1->psp_aux_fw_bin_index); + + } else { + fw_bin = sos_hdr_v2_0->psp_fw_bin; + } + + for (fw_index = start_index; fw_index < fw_bin_count; fw_index++) { + err = parse_sos_bin_descriptor(psp, fw_bin + fw_index, sos_hdr_v2_0); if (err) goto out; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h index 5bc37acd39819..4e23419b92d4e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h @@ -136,6 +136,14 @@ struct psp_firmware_header_v2_0 { struct psp_fw_bin_desc psp_fw_bin[]; }; +/* version_major=2, version_minor=1 */ +struct psp_firmware_header_v2_1 { + struct common_firmware_header header; + uint32_t psp_fw_bin_count; + uint32_t psp_aux_fw_bin_index; + struct psp_fw_bin_desc psp_fw_bin[]; +}; + /* version_major=1, version_minor=0 */ struct ta_firmware_header_v1_0 { struct common_firmware_header header; @@ -426,6 +434,7 @@ union amdgpu_firmware_header { struct psp_firmware_header_v1_1 psp_v1_1; struct psp_firmware_header_v1_3 psp_v1_3; struct psp_firmware_header_v2_0 psp_v2_0; + struct psp_firmware_header_v2_0 psp_v2_1; struct ta_firmware_header_v1_0 ta; struct ta_firmware_header_v2_0 ta_v2_0; struct gfx_firmware_header_v1_0 gfx; @@ -447,7 +456,7 @@ union amdgpu_firmware_header { uint8_t raw[0x100]; }; -#define UCODE_MAX_PSP_PACKAGING ((sizeof(union amdgpu_firmware_header) - sizeof(struct common_firmware_header) - 4) / sizeof(struct psp_fw_bin_desc)) +#define UCODE_MAX_PSP_PACKAGING (((sizeof(union amdgpu_firmware_header) - sizeof(struct common_firmware_header) - 4) / sizeof(struct psp_fw_bin_desc)) * 2) /* * fw loading support From eda4b27eb9a668f746d0cbf21653b87e9853c988 Mon Sep 17 00:00:00 2001 From: Leo Li Date: Tue, 10 Sep 2024 16:31:20 -0400 Subject: [PATCH 1524/1868] drm/amd/display: Add all planes on CRTC to state for overlay cursor [Why] DC has a special commit path for native cursor, which use the built-in cursor pipe within DCN planes. This update path does not require all enabled planes to be added to the list of surface updates sent to DC. This is not the case for overlay cursor; it uses the same path as MPO commits. This update path requires all enabled planes to be added to the list of surface updates sent to DC. Otherwise, DC will disable planes not inside the list. [How] If overlay cursor is needed, add all planes on the same CRTC as this cursor to the atomic state. This is already done for non-cursor planes (MPO), just before the added lines. Fixes: 1b04dcca4fb1 ("drm/amd/display: Introduce overlay cursor mode") Closes: https://lore.kernel.org/lkml/f68020a3-c413-482d-beb2-5432d98a1d3e@amd.com Signed-off-by: Leo Li Tested-by: Mikhail Gavrilov Reviewed-by: Harry Wentland --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index ad067e0c68887..db606df14368a 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -11722,6 +11722,17 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, drm_dbg(dev, "Failed to determine cursor mode\n"); goto fail; } + + /* + * If overlay cursor is needed, DC cannot go through the + * native cursor update path. All enabled planes on the CRTC + * need to be added for DC to not disable a plane by mistake + */ + if (dm_new_crtc_state->cursor_mode == DM_CURSOR_OVERLAY_MODE) { + ret = drm_atomic_add_affected_planes(state, crtc); + if (ret) + goto fail; + } } /* Remove exiting planes if they are modified */ From f328d1e8c655282c94a2f704df01da9f08d2c442 Mon Sep 17 00:00:00 2001 From: Kent Russell Date: Tue, 10 Sep 2024 09:21:25 -0400 Subject: [PATCH 1525/1868] drm/amdkfd: Move queue fs deletion after destroy check We were removing the kernfs entry for queue info before checking if the queue could be destroyed. If it failed to get destroyed (e.g. during some GPU resets), then we would try to delete it later during pqm teardown, but the file was already removed. This led to a kernel WARN trying to remove size, gpuid and type. Move the remove to after the destroy check. Signed-off-by: Kent Russell Reviewed-by: Jonathan Kim --- drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c index 120f36804618a..c23d25e4af9d2 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c @@ -531,6 +531,7 @@ int pqm_destroy_queue(struct process_queue_manager *pqm, unsigned int qid) if (retval != -ETIME) goto err_destroy_queue; } + kfd_procfs_del_queue(pqn->q); kfd_queue_release_buffers(pdd, &pqn->q->properties); pqm_clean_queue_resource(pqm, pqn); uninit_queue(pqn->q); From b1dda390f7447fe2182ace4ba846bf584eb7736a Mon Sep 17 00:00:00 2001 From: "Jesse.zhang@amd.com" Date: Tue, 10 Sep 2024 13:17:30 +0800 Subject: [PATCH 1526/1868] drm/amdkfd: clean up code for interrupt v10 Variable hub_inst is unused. Related the commit "bde7ae79ca40": "drm/amdkfd: Drop poison hanlding from gfx v10" Signed-off-by: Jesse Zhang Reviewed-by: Tim Huang --- drivers/gpu/drm/amd/amdkfd/kfd_int_process_v10.c | 15 --------------- 1 file changed, 15 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v10.c b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v10.c index bb8cbfc39b90f..37b69fe0ede38 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v10.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v10.c @@ -306,23 +306,8 @@ static void event_interrupt_wq_v10(struct kfd_node *dev, client_id == SOC15_IH_CLIENTID_UTCL2) { struct kfd_vm_fault_info info = {0}; uint16_t ring_id = SOC15_RING_ID_FROM_IH_ENTRY(ih_ring_entry); - uint32_t node_id = SOC15_NODEID_FROM_IH_ENTRY(ih_ring_entry); - uint32_t vmid_type = SOC15_VMID_TYPE_FROM_IH_ENTRY(ih_ring_entry); - int hub_inst = 0; struct kfd_hsa_memory_exception_data exception_data; - /* gfxhub */ - if (!vmid_type && dev->adev->gfx.funcs->ih_node_to_logical_xcc) { - hub_inst = dev->adev->gfx.funcs->ih_node_to_logical_xcc(dev->adev, - node_id); - if (hub_inst < 0) - hub_inst = 0; - } - - /* mmhub */ - if (vmid_type && client_id == SOC15_IH_CLIENTID_VMC) - hub_inst = node_id / 4; - info.vmid = vmid; info.mc_id = client_id; info.page_addr = ih_ring_entry[4] | From 10968f8684a364c55929cfadf6e1410e6e782ce3 Mon Sep 17 00:00:00 2001 From: Tim Huang Date: Wed, 7 Aug 2024 17:33:42 +0800 Subject: [PATCH 1527/1868] drm/amdgpu: ensure the connector is not null before using it This resolves the dereference null return value warning reported by Coverity. Signed-off-by: Tim Huang Reviewed-by: Jesse Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index c63056043b0db..d2dcc1aa49571 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -1532,7 +1532,7 @@ bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc, ((amdgpu_encoder->underscan_type == UNDERSCAN_ON) || ((amdgpu_encoder->underscan_type == UNDERSCAN_AUTO) && #if defined(HAVE_DRM_DISPLAY_INFO_IS_HDMI) - connector->display_info.is_hdmi && + connector && connector->display_info.is_hdmi && #else drm_detect_hdmi_monitor(to_amdgpu_connector(connector)->edid) && #endif From a0ae8e3c43c4c79c78a98fc67ecea55cb481f175 Mon Sep 17 00:00:00 2001 From: Tao Zhou Date: Mon, 9 Sep 2024 18:51:42 +0800 Subject: [PATCH 1528/1868] drm/amdgpu: disable GPU RAS bad page feature for specific ASIC The feature is not applicable to specific app platform. v2: update the disablement condition and commit description v3: move the setting to amdgpu_ras_check_supported Signed-off-by: Tao Zhou Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index dbfc41ddc3c71..ebe3e8f01fe28 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -3483,6 +3483,11 @@ static void amdgpu_ras_check_supported(struct amdgpu_device *adev) /* aca is disabled by default */ adev->aca.is_enabled = false; + + /* bad page feature is not applicable to specific app platform */ + if (adev->gmc.is_app_apu && + amdgpu_ip_version(adev, UMC_HWIP, 0) == IP_VERSION(12, 0, 0)) + amdgpu_bad_page_threshold = 0; } static void amdgpu_ras_counte_dw(struct work_struct *work) From 7467845669c0c8eb96bd73db8a5fd6c8d9d5b880 Mon Sep 17 00:00:00 2001 From: Jiadong Zhu Date: Mon, 9 Sep 2024 14:19:53 +0800 Subject: [PATCH 1529/1868] drm/amdgpu/mes11: update mes_reset_queue function to support sdma queue Reset sdma queue through mmio based on me_id and queue_id. v2: simplify callflows and register calculation. Signed-off-by: Jiadong Zhu Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 2 +- drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 27 ++++++++++++++++++++++++- 2 files changed, 27 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c index ff43540abcfcd..331d7cb0beb5c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c @@ -905,7 +905,7 @@ int amdgpu_mes_reset_legacy_queue(struct amdgpu_device *adev, queue_input.me_id = ring->me; queue_input.pipe_id = ring->pipe; queue_input.queue_id = ring->queue; - queue_input.mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj); + queue_input.mqd_addr = ring->mqd_obj ? amdgpu_bo_gpu_offset(ring->mqd_obj) : 0; queue_input.wptr_addr = ring->wptr_gpu_addr; queue_input.vmid = vmid; queue_input.use_mmio = use_mmio; diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c index ee91ff9e52a20..3c923719e32d3 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c @@ -366,7 +366,7 @@ static int mes_v11_0_reset_queue_mmio(struct amdgpu_mes *mes, uint32_t queue_typ uint32_t queue_id, uint32_t vmid) { struct amdgpu_device *adev = mes->adev; - uint32_t value; + uint32_t value, reg; int i, r = 0; amdgpu_gfx_rlc_enter_safe_mode(adev, 0); @@ -424,6 +424,31 @@ static int mes_v11_0_reset_queue_mmio(struct amdgpu_mes *mes, uint32_t queue_typ } soc21_grbm_select(adev, 0, 0, 0, 0); mutex_unlock(&adev->srbm_mutex); + } else if (queue_type == AMDGPU_RING_TYPE_SDMA) { + dev_info(adev->dev, "reset sdma queue (%d:%d:%d)\n", + me_id, pipe_id, queue_id); + switch (me_id) { + case 1: + reg = SOC15_REG_OFFSET(GC, 0, regSDMA1_QUEUE_RESET_REQ); + break; + case 0: + default: + reg = SOC15_REG_OFFSET(GC, 0, regSDMA0_QUEUE_RESET_REQ); + break; + } + + value = 1 << queue_id; + WREG32(reg, value); + /* wait for queue reset done */ + for (i = 0; i < adev->usec_timeout; i++) { + if (!(RREG32(reg) & value)) + break; + udelay(1); + } + if (i >= adev->usec_timeout) { + dev_err(adev->dev, "failed to wait on sdma queue reset done\n"); + r = -ETIMEDOUT; + } } amdgpu_gfx_rlc_exit_safe_mode(adev, 0); From 1c9d58969978ffc9fb4ef5af85cb806ce291f038 Mon Sep 17 00:00:00 2001 From: Jiadong Zhu Date: Mon, 9 Sep 2024 15:36:26 +0800 Subject: [PATCH 1530/1868] drm/amdgpu/sdma6: split out per instance resume function Extract the resume sequence for individual sdma instance from sdma_v6_0_gfx_resume. The function could be used for start/restart scenario on a certain instance. Signed-off-by: Jiadong Zhu Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 240 ++++++++++++++----------- 1 file changed, 131 insertions(+), 109 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c index 208a1fa9d4e7f..b2efc678b7e91 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c @@ -469,14 +469,16 @@ static void sdma_v6_0_enable(struct amdgpu_device *adev, bool enable) } /** - * sdma_v6_0_gfx_resume - setup and start the async dma engines + * sdma_v6_0_gfx_resume_instance - start/restart a certain sdma engine * * @adev: amdgpu_device pointer + * @i: instance + * @restore: used to restore wptr when restart * - * Set up the gfx DMA ring buffers and enable them. - * Returns 0 for success, error for failure. + * Set up the gfx DMA ring buffers and enable them. On restart, we will restore wptr and rptr. + * Return 0 for success. */ -static int sdma_v6_0_gfx_resume(struct amdgpu_device *adev) +static int sdma_v6_0_gfx_resume_instance(struct amdgpu_device *adev, int i, bool restore) { struct amdgpu_ring *ring; u32 rb_cntl, ib_cntl; @@ -485,132 +487,152 @@ static int sdma_v6_0_gfx_resume(struct amdgpu_device *adev) u32 doorbell_offset; u32 temp; u64 wptr_gpu_addr; - int i, r; - - for (i = 0; i < adev->sdma.num_instances; i++) { - ring = &adev->sdma.instance[i].ring; - if (!amdgpu_sriov_vf(adev)) - WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); + ring = &adev->sdma.instance[i].ring; + if (!amdgpu_sriov_vf(adev)) + WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); - /* Set ring buffer size in dwords */ - rb_bufsz = order_base_2(ring->ring_size / 4); - rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL)); - rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SIZE, rb_bufsz); + /* Set ring buffer size in dwords */ + rb_bufsz = order_base_2(ring->ring_size / 4); + rb_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL)); + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SIZE, rb_bufsz); #ifdef __BIG_ENDIAN - rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SWAP_ENABLE, 1); - rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, - RPTR_WRITEBACK_SWAP_ENABLE, 1); + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_SWAP_ENABLE, 1); + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, + RPTR_WRITEBACK_SWAP_ENABLE, 1); #endif - rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_PRIV, 1); - WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl); - - /* Initialize the ring buffer's read and write pointers */ + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_PRIV, 1); + WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl); + + /* Initialize the ring buffer's read and write pointers */ + if (restore) { + WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), lower_32_bits(ring->wptr << 2)); + WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), upper_32_bits(ring->wptr << 2)); + WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr << 2)); + WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr << 2)); + } else { WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR), 0); WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_HI), 0); WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), 0); WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), 0); + } + /* setup the wptr shadow polling */ + wptr_gpu_addr = ring->wptr_gpu_addr; + WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO), + lower_32_bits(wptr_gpu_addr)); + WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI), + upper_32_bits(wptr_gpu_addr)); + + /* set the wb address whether it's enabled or not */ + WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_HI), + upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF); + WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_LO), + lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); + + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 0); + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, F32_WPTR_POLL_ENABLE, 1); + + WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE), ring->gpu_addr >> 8); + WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE_HI), ring->gpu_addr >> 40); + + if (!restore) + ring->wptr = 0; - /* setup the wptr shadow polling */ - wptr_gpu_addr = ring->wptr_gpu_addr; - WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_LO), - lower_32_bits(wptr_gpu_addr)); - WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_POLL_ADDR_HI), - upper_32_bits(wptr_gpu_addr)); - - /* set the wb address whether it's enabled or not */ - WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_HI), - upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF); - WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_RPTR_ADDR_LO), - lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); - - rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); - rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, WPTR_POLL_ENABLE, 0); - rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, F32_WPTR_POLL_ENABLE, 1); + /* before programing wptr to a less value, need set minor_ptr_update first */ + WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 1); - WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE), ring->gpu_addr >> 8); - WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_BASE_HI), ring->gpu_addr >> 40); + if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ + WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr) << 2); + WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2); + } - ring->wptr = 0; + doorbell = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL)); + doorbell_offset = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET)); - /* before programing wptr to a less value, need set minor_ptr_update first */ - WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 1); + if (ring->use_doorbell) { + doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 1); + doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_QUEUE0_DOORBELL_OFFSET, + OFFSET, ring->doorbell_index); + } else { + doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 0); + } + WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL), doorbell); + WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET), doorbell_offset); - if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ - WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR), lower_32_bits(ring->wptr) << 2); - WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_WPTR_HI), upper_32_bits(ring->wptr) << 2); - } + if (i == 0) + adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, + ring->doorbell_index, + adev->doorbell_index.sdma_doorbell_range * adev->sdma.num_instances); - doorbell = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL)); - doorbell_offset = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET)); + if (amdgpu_sriov_vf(adev)) + sdma_v6_0_ring_set_wptr(ring); + + /* set minor_ptr_update to 0 after wptr programed */ + WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 0); + + /* Set up sdma hang watchdog */ + temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_WATCHDOG_CNTL)); + /* 100ms per unit */ + temp = REG_SET_FIELD(temp, SDMA0_WATCHDOG_CNTL, QUEUE_HANG_COUNT, + max(adev->usec_timeout/100000, 1)); + WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_WATCHDOG_CNTL), temp); + + /* Set up RESP_MODE to non-copy addresses */ + temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL)); + temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3); + temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9); + WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL), temp); + + /* program default cache read and write policy */ + temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE)); + /* clean read policy and write policy bits */ + temp &= 0xFF0FFF; + temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | + (CACHE_WRITE_POLICY_L2__DEFAULT << 14) | + SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK); + WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE), temp); - if (ring->use_doorbell) { - doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 1); - doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_QUEUE0_DOORBELL_OFFSET, - OFFSET, ring->doorbell_index); - } else { - doorbell = REG_SET_FIELD(doorbell, SDMA0_QUEUE0_DOORBELL, ENABLE, 0); - } - WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL), doorbell); - WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_DOORBELL_OFFSET), doorbell_offset); - - if (i == 0) - adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, - ring->doorbell_index, - adev->doorbell_index.sdma_doorbell_range * adev->sdma.num_instances); - - if (amdgpu_sriov_vf(adev)) - sdma_v6_0_ring_set_wptr(ring); - - /* set minor_ptr_update to 0 after wptr programed */ - WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_MINOR_PTR_UPDATE), 0); - - /* Set up sdma hang watchdog */ - temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_WATCHDOG_CNTL)); - /* 100ms per unit */ - temp = REG_SET_FIELD(temp, SDMA0_WATCHDOG_CNTL, QUEUE_HANG_COUNT, - max(adev->usec_timeout/100000, 1)); - WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_WATCHDOG_CNTL), temp); - - /* Set up RESP_MODE to non-copy addresses */ - temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL)); - temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3); - temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9); - WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_CNTL), temp); - - /* program default cache read and write policy */ - temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE)); - /* clean read policy and write policy bits */ - temp &= 0xFF0FFF; - temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | - (CACHE_WRITE_POLICY_L2__DEFAULT << 14) | - SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK); - WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_UTCL1_PAGE), temp); - - if (!amdgpu_sriov_vf(adev)) { - /* unhalt engine */ - temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL)); - temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); - temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, TH1_RESET, 0); - WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), temp); - } + if (!amdgpu_sriov_vf(adev)) { + /* unhalt engine */ + temp = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL)); + temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); + temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, TH1_RESET, 0); + WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_F32_CNTL), temp); + } - /* enable DMA RB */ - rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 1); - WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl); + /* enable DMA RB */ + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_QUEUE0_RB_CNTL, RB_ENABLE, 1); + WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_RB_CNTL), rb_cntl); - ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL)); - ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 1); + ib_cntl = RREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL)); + ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_ENABLE, 1); #ifdef __BIG_ENDIAN - ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_SWAP_ENABLE, 1); + ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_QUEUE0_IB_CNTL, IB_SWAP_ENABLE, 1); #endif - /* enable DMA IBs */ - WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl); + /* enable DMA IBs */ + WREG32_SOC15_IP(GC, sdma_v6_0_get_reg_offset(adev, i, regSDMA0_QUEUE0_IB_CNTL), ib_cntl); + + if (amdgpu_sriov_vf(adev)) + sdma_v6_0_enable(adev, true); - if (amdgpu_sriov_vf(adev)) - sdma_v6_0_enable(adev, true); + return amdgpu_ring_test_helper(ring); +} - r = amdgpu_ring_test_helper(ring); +/** + * sdma_v6_0_gfx_resume - setup and start the async dma engines + * + * @adev: amdgpu_device pointer + * + * Set up the gfx DMA ring buffers and enable them. + * Returns 0 for success, error for failure. + */ +static int sdma_v6_0_gfx_resume(struct amdgpu_device *adev) +{ + int i, r; + + for (i = 0; i < adev->sdma.num_instances; i++) { + r = sdma_v6_0_gfx_resume_instance(adev, i, false); if (r) return r; } From ef73f6c0555eefd73292a69a85698f18cd4114b2 Mon Sep 17 00:00:00 2001 From: Jiadong Zhu Date: Tue, 10 Sep 2024 11:27:02 +0800 Subject: [PATCH 1531/1868] drm/amdgpu/sdma6: implement ring reset callback for sdma6 Implement sdma queue reset callback using mes_reset_queue_mmio. v2: check instance id before reset queue. Signed-off-by: Jiadong Zhu Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c index b2efc678b7e91..581fa550ef29f 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c @@ -1491,6 +1491,31 @@ static int sdma_v6_0_ring_preempt_ib(struct amdgpu_ring *ring) return r; } +static int sdma_v6_0_reset_queue(struct amdgpu_ring *ring, unsigned int vmid) +{ + struct amdgpu_device *adev = ring->adev; + int i, r; + + if (amdgpu_sriov_vf(adev)) + return -EINVAL; + + for (i = 0; i < adev->sdma.num_instances; i++) { + if (ring == &adev->sdma.instance[i].ring) + break; + } + + if (i == adev->sdma.num_instances) { + DRM_ERROR("sdma instance not found\n"); + return -EINVAL; + } + + r = amdgpu_mes_reset_legacy_queue(adev, ring, vmid, true); + if (r) + return r; + + return sdma_v6_0_gfx_resume_instance(adev, i, true); +} + static int sdma_v6_0_set_trap_irq_state(struct amdgpu_device *adev, struct amdgpu_irq_src *source, unsigned type, @@ -1674,6 +1699,7 @@ static const struct amdgpu_ring_funcs sdma_v6_0_ring_funcs = { .emit_reg_write_reg_wait = sdma_v6_0_ring_emit_reg_write_reg_wait, .init_cond_exec = sdma_v6_0_ring_init_cond_exec, .preempt_ib = sdma_v6_0_ring_preempt_ib, + .reset = sdma_v6_0_reset_queue, }; static void sdma_v6_0_set_ring_funcs(struct amdgpu_device *adev) From 8c512ec2285428b2be07455ea63614543597deb4 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 10 Sep 2024 09:33:30 -0400 Subject: [PATCH 1532/1868] drm/amdgpu/gfx9.4.3: drop extra wrapper Drop wrapper used in one place. gfx_v9_4_3_xcc_cp_enable() is used in one place. gfx_v9_4_3_xcc_cp_compute_enable() is used everywhere else. Reviewed-by: Lijo Lazar Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index 1df55b83ec736..c100845409f79 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -2309,12 +2309,6 @@ static int gfx_v9_4_3_cp_resume(struct amdgpu_device *adev) return 0; } -static void gfx_v9_4_3_xcc_cp_enable(struct amdgpu_device *adev, bool enable, - int xcc_id) -{ - gfx_v9_4_3_xcc_cp_compute_enable(adev, enable, xcc_id); -} - static void gfx_v9_4_3_xcc_fini(struct amdgpu_device *adev, int xcc_id) { if (amdgpu_gfx_disable_kcq(adev, xcc_id)) @@ -2346,7 +2340,7 @@ static void gfx_v9_4_3_xcc_fini(struct amdgpu_device *adev, int xcc_id) } gfx_v9_4_3_xcc_kcq_fini_register(adev, xcc_id); - gfx_v9_4_3_xcc_cp_enable(adev, false, xcc_id); + gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id); } static int gfx_v9_4_3_hw_init(void *handle) From cc3c5767b34de07506ed3a130eaaa7af60640a25 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 10 Sep 2024 10:19:43 -0400 Subject: [PATCH 1533/1868] drm/amdgpu: fix spelling in amd_shared.h Fix spelling in documentation. Reviewed-by: Kent Russell Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/include/amd_shared.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h index 745fd052840dc..3f91926a50e99 100644 --- a/drivers/gpu/drm/amd/include/amd_shared.h +++ b/drivers/gpu/drm/amd/include/amd_shared.h @@ -85,7 +85,7 @@ enum amd_apu_flags { * @AMD_IP_BLOCK_TYPE_MES: Micro-Engine Scheduler * @AMD_IP_BLOCK_TYPE_JPEG: JPEG Engine * @AMD_IP_BLOCK_TYPE_VPE: Video Processing Engine -* @AMD_IP_BLOCK_TYPE_UMSCH_MM: User Mode Schduler for Multimedia +* @AMD_IP_BLOCK_TYPE_UMSCH_MM: User Mode Scheduler for Multimedia * @AMD_IP_BLOCK_TYPE_ISP: Image Signal Processor * @AMD_IP_BLOCK_TYPE_NUM: Total number of IP block types */ From da1877eacdf799a064ba8aa6cbd592e285069039 Mon Sep 17 00:00:00 2001 From: Yan Zhen Date: Wed, 11 Sep 2024 12:27:38 +0800 Subject: [PATCH 1534/1868] drm/amdgpu: fix typo in the comment MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Correctly spelled comments make it easier for the reader to understand the code. Replace 'udpate' with 'update' in the comment & replace 'recieved' with 'received' in the comment & replace 'dsiable' with 'disable' in the comment & replace 'Initiailize' with 'Initialize' in the comment & replace 'disble' with 'disable' in the comment & replace 'Disbale' with 'Disable' in the comment & replace 'enogh' with 'enough' in the comment & replace 'availabe' with 'available' in the comment. Acked-by: Christian König Signed-off-by: Yan Zhen Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 2 +- drivers/gpu/drm/amd/amdgpu/imu_v11_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c | 2 +- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/smuio_v9_0.c | 2 +- 8 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c index c8aed31fb7f0a..7b64c5b67e10b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_aca.c @@ -511,7 +511,7 @@ static int __aca_get_error_data(struct amdgpu_device *adev, struct aca_handle *h return -EINVAL; } - /* udpate aca bank to aca source error_cache first */ + /* update aca bank to aca source error_cache first */ ret = aca_banks_update(adev, smu_type, handler_aca_log_bank_error, qctx, NULL); if (ret) return ret; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 09dad501d0402..e5c8b7dac8cbc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -2853,7 +2853,7 @@ static int psp_load_non_psp_fw(struct psp_context *psp) if (ret) return ret; - /* Start rlc autoload after psp recieved all the gfx firmware */ + /* Start rlc autoload after psp received all the gfx firmware */ if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ? adev->virt.autoload_ucode_id : AMDGPU_UCODE_ID_RLC_G)) { ret = psp_rlc_autoload_start(psp); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index ebe3e8f01fe28..b017be040b49f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -882,7 +882,7 @@ int amdgpu_ras_feature_enable_on_boot(struct amdgpu_device *adev, if (ret) return ret; - /* gfx block ras dsiable cmd must send to ras-ta */ + /* gfx block ras disable cmd must send to ras-ta */ if (head->block == AMDGPU_RAS_BLOCK__GFX) con->features |= BIT(head->block); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c index cbac21df5c47a..7afad16b5a3a8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c @@ -2375,7 +2375,7 @@ int amdgpu_ttm_init(struct amdgpu_device *adev) (unsigned int)(gtt_size / (1024 * 1024))); amdgpu_direct_gma_init(adev); - /* Initiailize doorbell pool on PCI BAR */ + /* Initialize doorbell pool on PCI BAR */ r = amdgpu_ttm_init_on_chip(adev, AMDGPU_PL_DOORBELL, adev->doorbell.size / PAGE_SIZE); if (r) { DRM_ERROR("Failed initializing doorbell heap.\n"); diff --git a/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c b/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c index 6c1891889c4da..d4f72e47ae9e2 100644 --- a/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/imu_v11_0.c @@ -153,7 +153,7 @@ static void imu_v11_0_setup(struct amdgpu_device *adev) WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_16, imu_reg_val); } - //disble imu Rtavfs, SmsRepair, DfllBTC, and ClkB + //disable imu Rtavfs, SmsRepair, DfllBTC, and ClkB imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_10); imu_reg_val |= 0x10007; WREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_10, imu_reg_val); diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c index 80cd6a08a0388..b66141b5afeef 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c @@ -365,7 +365,7 @@ static void nbio_v2_3_enable_aspm(struct amdgpu_device *adev, data &= ~PCIE_LC_CNTL__LC_PMI_TO_L1_DIS_MASK; } else { - /* Disbale ASPM L1 */ + /* Disable ASPM L1 */ data &= ~PCIE_LC_CNTL__LC_L1_INACTIVITY_MASK; /* Disable ASPM TxL0s */ data &= ~PCIE_LC_CNTL__LC_L0S_INACTIVITY_MASK; diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c index aa637541da584..e65194fe94af6 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c @@ -710,7 +710,7 @@ static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev) upper_32_bits(wptr_gpu_addr)); wptr_poll_cntl = RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i]); if (ring->use_pollmem) { - /*wptr polling is not enogh fast, directly clean the wptr register */ + /*wptr polling is not enough fast, directly clean the wptr register */ WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0); wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, SDMA0_GFX_RB_WPTR_POLL_CNTL, diff --git a/drivers/gpu/drm/amd/amdgpu/smuio_v9_0.c b/drivers/gpu/drm/amd/amdgpu/smuio_v9_0.c index e4e30b9d481b4..c04fdd2d5b389 100644 --- a/drivers/gpu/drm/amd/amdgpu/smuio_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/smuio_v9_0.c @@ -60,7 +60,7 @@ static void smuio_v9_0_get_clock_gating_state(struct amdgpu_device *adev, u64 *f { u32 data; - /* CGTT_ROM_CLK_CTRL0 is not availabe for APUs */ + /* CGTT_ROM_CLK_CTRL0 is not available for APUs */ if (adev->flags & AMD_IS_APU) return; From 3b508b82f93e4849c14e5ba61c9becbdcb42cb2b Mon Sep 17 00:00:00 2001 From: Andrew Kreimer Date: Tue, 10 Sep 2024 01:41:05 +0300 Subject: [PATCH 1535/1868] drm/amdgpu: Fix a typo Fix a typo in comments. Reported-by: Matthew Wilcox Signed-off-by: Andrew Kreimer Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c index aab8077e50988..f28f6b4ba765d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c @@ -58,7 +58,7 @@ #define EEPROM_I2C_MADDR_4 0x40000 /* - * The 2 macros bellow represent the actual size in bytes that + * The 2 macros below represent the actual size in bytes that * those entities occupy in the EEPROM memory. * RAS_TABLE_RECORD_SIZE is different than sizeof(eeprom_table_record) which * uses uint64 to store 6b fields such as retired_page. From bc7746dbc2a1334256d73f3e8d4404ea86f0d33c Mon Sep 17 00:00:00 2001 From: Yan Zhen Date: Thu, 12 Sep 2024 15:12:09 +0800 Subject: [PATCH 1536/1868] drm/amd/display: fix typo in the comment Correctly spelled comments make it easier for the reader to understand the code. Replace 'maxium' with 'maximum' in the comment & replace 'diffculty' with 'difficulty' in the comment & replace 'suppluy' with 'supply' in the comment & replace 'Congiuration' with 'Configuration' in the comment & replace 'eanbled' with 'enabled' in the comment. Signed-off-by: Yan Zhen Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c | 2 +- drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c | 6 +++--- drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c | 2 +- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c b/drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c index e47e9db062f44..681799468487c 100644 --- a/drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c @@ -569,7 +569,7 @@ static void calculate_bandwidth( break; } data->lb_partitions[i] = bw_floor2(bw_div(data->lb_size_per_component[i], data->lb_line_pitch), bw_int_to_fixed(1)); - /*clamp the partitions to the maxium number supported by the lb*/ + /* clamp the partitions to the maximum number supported by the lb */ if ((surface_type[i] != bw_def_graphics || dceip->graphics_lb_nodownscaling_multi_line_prefetching == 1)) { data->lb_partitions_max[i] = bw_int_to_fixed(10); } diff --git a/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c b/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c index 547dfcc80fde4..d851c081e3768 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c @@ -8926,7 +8926,7 @@ void dml_core_mode_programming(struct display_mode_lib_st *mode_lib, const struc // The prefetch scheduling should only be calculated once as per AllowForPStateChangeOrStutterInVBlank requirement // If the AllowForPStateChangeOrStutterInVBlank requirement is not strict (i.e. only try those power saving feature - // if possible, then will try to program for the best power saving features in order of diffculty (dram, fclk, stutter) + // if possible, then will try to program for the best power saving features in order of difficulty (dram, fclk, stutter) s->iteration = 0; s->MaxTotalRDBandwidth = 0; s->AllPrefetchModeTested = false; @@ -9977,7 +9977,7 @@ void dml_core_get_row_heights( dml_print("DML_DLG: %s: GPUVMMinPageSizeKBytes = %u\n", __func__, GPUVMMinPageSizeKBytes); #endif - // just suppluy with enough parameters to calculate meta and dte + // just supply with enough parameters to calculate meta and dte CalculateVMAndRowBytes( 0, // dml_bool_t ViewportStationary, 1, // dml_bool_t DCCEnable, @@ -10110,7 +10110,7 @@ dml_bool_t dml_mode_support( /// Note: In this function, it is assumed that DCFCLK, SOCCLK freq are the state values, and mode_program will just use the DML calculated DPPCLK and DISPCLK /// @param mode_lib mode_lib data struct that house all the input/output/bbox and calculation values. /// @param state_idx Power state idx chosen -/// @param display_cfg Display Congiuration +/// @param display_cfg Display Configuration /// @param call_standalone Calling mode_programming without calling mode support. Some of the "support" struct member will be pre-calculated before doing mode programming /// TODO: Add clk_cfg input, could be useful for standalone mode dml_bool_t dml_mode_programming( diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c index 42c52284a8680..bded33575493b 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c @@ -455,7 +455,7 @@ bool dcn30_mmhubbub_warmup( struct mcif_wb *mcif_wb; struct mcif_warmup_params warmup_params = {0}; unsigned int i, i_buf; - /*make sure there is no active DWB eanbled */ + /* make sure there is no active DWB enabled */ for (i = 0; i < num_dwb; i++) { dwb = dc->res_pool->dwbc[wb_info[i].dwb_pipe_inst]; if (dwb->dwb_is_efc_transition || dwb->dwb_is_drc) { From 33455abb27b7937fc4ff0ac701a72113f196b397 Mon Sep 17 00:00:00 2001 From: Kent Russell Date: Tue, 10 Sep 2024 09:32:13 -0400 Subject: [PATCH 1537/1868] drm/amdgpu: Retry i2c transfer once if it fails on SMU13.0.6 During init, there can be some collisions on the i2c bus that result in the EEPROM read failing. This has been mitigated in the PMFW to a degree, but there is still a small chance that the bus will be busy. When the read fails during RAS init, that disables page retirement altogether, which is obviously not ideal. To try to avoid that situation, set the eeprom_read function to retry once if the first read fails, specifically for smu_v13_0_6. Signed-off-by: Kent Russell Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index 8cf36e53fc701..c70b6ef5e5f3a 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -2265,8 +2265,12 @@ static int smu_v13_0_6_i2c_xfer(struct i2c_adapter *i2c_adap, } mutex_lock(&adev->pm.mutex); r = smu_v13_0_6_request_i2c_xfer(smu, req); - if (r) - goto fail; + if (r) { + /* Retry once, in case of an i2c collision */ + r = smu_v13_0_6_request_i2c_xfer(smu, req); + if (r) + goto fail; + } for (c = i = 0; i < num_msgs; i++) { if (!(msg[i].flags & I2C_M_RD)) { From 3668a18e24afe8646389dbff8cfbb84928ae539a Mon Sep 17 00:00:00 2001 From: David Belanger Date: Wed, 11 Sep 2024 11:16:50 -0400 Subject: [PATCH 1538/1868] drm/amdgpu: Fix selfring initialization sequence on soc24 Move enable_doorbell_selfring_aperture from common_hw_init to common_late_init in soc24, otherwise selfring aperture is initialized with an incorrect doorbell aperture base. Port changes from this commit from soc21 to soc24: commit 1c312e816c40 ("drm/amdgpu: Enable doorbell selfring after resize FB BAR") Signed-off-by: David Belanger Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/soc24.c | 23 +++++++++++++---------- 1 file changed, 13 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/soc24.c b/drivers/gpu/drm/amd/amdgpu/soc24.c index b0c3678cfb31d..fd4c3d4f83879 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc24.c +++ b/drivers/gpu/drm/amd/amdgpu/soc24.c @@ -250,13 +250,6 @@ static void soc24_program_aspm(struct amdgpu_device *adev) adev->nbio.funcs->program_aspm(adev); } -static void soc24_enable_doorbell_aperture(struct amdgpu_device *adev, - bool enable) -{ - adev->nbio.funcs->enable_doorbell_aperture(adev, enable); - adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, enable); -} - const struct amdgpu_ip_block_version soc24_common_ip_block = { .type = AMD_IP_BLOCK_TYPE_COMMON, .major = 1, @@ -454,6 +447,11 @@ static int soc24_common_late_init(void *handle) if (amdgpu_sriov_vf(adev)) xgpu_nv_mailbox_get_irq(adev); + /* Enable selfring doorbell aperture late because doorbell BAR + * aperture will change if resize BAR successfully in gmc sw_init. + */ + adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, true); + return 0; } @@ -491,7 +489,7 @@ static int soc24_common_hw_init(void *handle) adev->df.funcs->hw_init(adev); /* enable the doorbell aperture */ - soc24_enable_doorbell_aperture(adev, true); + adev->nbio.funcs->enable_doorbell_aperture(adev, true); return 0; } @@ -500,8 +498,13 @@ static int soc24_common_hw_fini(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; - /* disable the doorbell aperture */ - soc24_enable_doorbell_aperture(adev, false); + /* Disable the doorbell aperture and selfring doorbell aperture + * separately in hw_fini because soc21_enable_doorbell_aperture + * has been removed and there is no need to delay disabling + * selfring doorbell. + */ + adev->nbio.funcs->enable_doorbell_aperture(adev, false); + adev->nbio.funcs->enable_doorbell_selfring_aperture(adev, false); if (amdgpu_sriov_vf(adev)) xgpu_nv_mailbox_put_irq(adev); From c667a01dc35d4cf6c344f8a475a03aa329627582 Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Thu, 4 Jul 2024 12:08:33 +0800 Subject: [PATCH 1539/1868] drm/amd/amdgpu: Add helper to get ip block valid Add helper function to check if ip block is enabled Signed-off-by: Asad Kamal Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 22 ++++++++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 27769f10914b2..3515a39fda660 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -368,6 +368,8 @@ int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, enum amd_ip_block_type block_type); bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, enum amd_ip_block_type block_type); +bool amdgpu_device_ip_is_valid(struct amdgpu_device *adev, + enum amd_ip_block_type block_type); #define AMDGPU_MAX_IP_NUM 16 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 500b3ff9f344a..68a3c958f3e2f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -2208,6 +2208,28 @@ bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, } +/** + * amdgpu_device_ip_is_valid - is the hardware IP enabled + * + * @adev: amdgpu_device pointer + * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) + * + * Check if the hardware IP is enable or not. + * Returns true if it the IP is enable, false if not. + */ +bool amdgpu_device_ip_is_valid(struct amdgpu_device *adev, + enum amd_ip_block_type block_type) +{ + int i; + + for (i = 0; i < adev->num_ip_blocks; i++) { + if (adev->ip_blocks[i].version->type == block_type) + return adev->ip_blocks[i].status.valid; + } + return false; + +} + /** * amdgpu_device_ip_get_ip_block - get a hw IP pointer * From 67553cd5e5c674b148e904451992d9147aec01de Mon Sep 17 00:00:00 2001 From: Le Ma Date: Sat, 14 Sep 2024 19:35:32 +0800 Subject: [PATCH 1540/1868] Revert "drm/amdgpu/swsmu: always force a state reprogram on init" This reverts commit 63009805b6c5ce27d86f4f5cff8d9bbc779b4146. This patch inserts extra SMU messages to set dpm level during intialization and will cause SMU msg timeout on some platforms. Remove this patch until issue gets fixed. --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 2b02da35cb428..52083277b70da 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -2224,9 +2224,8 @@ static int smu_bump_power_profile_mode(struct smu_context *smu, } static int smu_adjust_power_state_dynamic(struct smu_context *smu, - enum amd_dpm_forced_level level, - bool skip_display_settings, - bool force_update) + enum amd_dpm_forced_level level, + bool skip_display_settings) { int ret = 0; int index = 0; @@ -2255,7 +2254,7 @@ static int smu_adjust_power_state_dynamic(struct smu_context *smu, } } - if (force_update || smu_dpm_ctx->dpm_level != level) { + if (smu_dpm_ctx->dpm_level != level) { ret = smu_asic_set_performance_level(smu, level); if (ret) { dev_err(smu->adev->dev, "Failed to set performance level!"); @@ -2271,7 +2270,7 @@ static int smu_adjust_power_state_dynamic(struct smu_context *smu, index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; workload[0] = smu->workload_setting[index]; - if (force_update || smu->power_profile_mode != workload[0]) + if (smu->power_profile_mode != workload[0]) smu_bump_power_profile_mode(smu, workload, 0); } @@ -2292,13 +2291,11 @@ static int smu_handle_task(struct smu_context *smu, ret = smu_pre_display_config_changed(smu); if (ret) return ret; - ret = smu_adjust_power_state_dynamic(smu, level, false, false); + ret = smu_adjust_power_state_dynamic(smu, level, false); break; case AMD_PP_TASK_COMPLETE_INIT: - ret = smu_adjust_power_state_dynamic(smu, level, true, true); - break; case AMD_PP_TASK_READJUST_POWER_STATE: - ret = smu_adjust_power_state_dynamic(smu, level, true, false); + ret = smu_adjust_power_state_dynamic(smu, level, true); break; default: break; From 91da6d81ce7f93caed26365eae432986bb7db1f7 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 12 Sep 2024 13:08:12 -0400 Subject: [PATCH 1541/1868] drm/amdgpu/gfx9.4.3: set additional bits on MEC halt Need to set the pipe reset and cache invalidation bits on halt otherwise we can get stale state if the CP firmware changes (e.g., on module unload and reload). Tested-by: Amber Lin Reviewed-by: Amber Lin Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index 408e5600bb617..9221b4e9a7f7e 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -1701,7 +1701,15 @@ static void gfx_v9_4_3_xcc_cp_compute_enable(struct amdgpu_device *adev, WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, 0); } else { WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_MEC_CNTL, - (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); + (CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK | + CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK | + CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK | + CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK | + CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK | + CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK | + CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK | + CP_MEC_CNTL__MEC_ME1_HALT_MASK | + CP_MEC_CNTL__MEC_ME2_HALT_MASK)); adev->gfx.kiq[xcc_id].ring.sched.ready = false; } udelay(50); From b8f68b5ae8efc541695dadae6029e96a9550947e Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Thu, 12 Sep 2024 16:15:55 -0400 Subject: [PATCH 1542/1868] drm/amdgpu/gfx9.4.3: Explicitly halt MEC before init Need to make sure it's halted as we don't know what state the GPU may have been left in previously. Tested-by: Amber Lin Acked-by: Amber Lin Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index 9221b4e9a7f7e..1df55b83ec736 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -2248,6 +2248,8 @@ static int gfx_v9_4_3_xcc_cp_resume(struct amdgpu_device *adev, int xcc_id) r = gfx_v9_4_3_xcc_cp_compute_load_microcode(adev, xcc_id); if (r) return r; + } else { + gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id); } r = gfx_v9_4_3_xcc_kiq_resume(adev, xcc_id); From 5b75b2274e517b6586e270ecb7fc6c8f6a336976 Mon Sep 17 00:00:00 2001 From: David Belanger Date: Fri, 23 Aug 2024 13:50:03 -0400 Subject: [PATCH 1543/1868] drm/amdkfd: Add cache line size info Populate cache line size info in topology based on information from IP discovery table. Signed-off-by: David Belanger Reviewed-by: Sreekant Somasekharan --- drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c index dd37a8c173812..d1fa06ad42781 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c @@ -1345,7 +1345,8 @@ static int kfd_fill_gpu_cache_info_from_gfx_config(struct kfd_dev *kdev, pcache_info[i].flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE); - pcache_info[0].num_cu_shared = adev->gfx.config.gc_num_tcp_per_wpg / 2; + pcache_info[i].num_cu_shared = adev->gfx.config.gc_num_tcp_per_wpg / 2; + pcache_info[i].cache_line_size = adev->gfx.config.gc_tcp_cache_line_size; i++; } /* Scalar L1 Instruction Cache per SQC */ @@ -1357,6 +1358,7 @@ static int kfd_fill_gpu_cache_info_from_gfx_config(struct kfd_dev *kdev, CRAT_CACHE_FLAGS_INST_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE); pcache_info[i].num_cu_shared = adev->gfx.config.gc_num_sqc_per_wgp * 2; + pcache_info[i].cache_line_size = adev->gfx.config.gc_instruction_cache_line_size; i++; } /* Scalar L1 Data Cache per SQC */ @@ -1367,6 +1369,7 @@ static int kfd_fill_gpu_cache_info_from_gfx_config(struct kfd_dev *kdev, CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE); pcache_info[i].num_cu_shared = adev->gfx.config.gc_num_sqc_per_wgp * 2; + pcache_info[i].cache_line_size = adev->gfx.config.gc_scalar_data_cache_line_size; i++; } /* GL1 Data Cache per SA */ @@ -1379,6 +1382,7 @@ static int kfd_fill_gpu_cache_info_from_gfx_config(struct kfd_dev *kdev, CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE); pcache_info[i].num_cu_shared = adev->gfx.config.max_cu_per_sh; + pcache_info[i].cache_line_size = 0; i++; } /* L2 Data Cache per GPU (Total Tex Cache) */ @@ -1389,6 +1393,7 @@ static int kfd_fill_gpu_cache_info_from_gfx_config(struct kfd_dev *kdev, CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE); pcache_info[i].num_cu_shared = adev->gfx.config.max_cu_per_sh; + pcache_info[i].cache_line_size = adev->gfx.config.gc_tcc_cache_line_size; i++; } /* L3 Data Cache per GPU */ @@ -1399,6 +1404,7 @@ static int kfd_fill_gpu_cache_info_from_gfx_config(struct kfd_dev *kdev, CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE); pcache_info[i].num_cu_shared = adev->gfx.config.max_cu_per_sh; + pcache_info[i].cache_line_size = 0; i++; } return i; From 6f24577f4f20733e7c015d8c90f4658176e94ea2 Mon Sep 17 00:00:00 2001 From: Joseph Greathouse Date: Fri, 19 Jan 2024 20:01:50 -0600 Subject: [PATCH 1544/1868] drm/amdkfd: Add cache line sizes to KFD topology The KFD topology includes cache line size, but we have not been filling that information out unless we are parsing a CRAT table. Fill in this information for the devices where we have cache information structs, and pipe this information to the topology sysfs files. v2: squash in fix from Joe (Alex) Signed-off-by: Joseph Greathouse Acked-by: Alex Deucher Reviewed-by: Felix Kuehling Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdkfd/kfd_crat.c | 93 ++++++++++++++++++++++- drivers/gpu/drm/amd/amdkfd/kfd_crat.h | 1 + drivers/gpu/drm/amd/amdkfd/kfd_topology.c | 2 + 3 files changed, 94 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c index d1fa06ad42781..7b2c408db75cf 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.c @@ -55,6 +55,7 @@ static struct kfd_gpu_cache_info kaveri_cache_info[] = { /* TCP L1 Cache per CU */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -64,6 +65,7 @@ static struct kfd_gpu_cache_info kaveri_cache_info[] = { /* Scalar L1 Instruction Cache (in SQC module) per bank */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_INST_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -73,6 +75,7 @@ static struct kfd_gpu_cache_info kaveri_cache_info[] = { /* Scalar L1 Data Cache (in SQC module) per bank */ .cache_size = 8, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -88,6 +91,7 @@ static struct kfd_gpu_cache_info carrizo_cache_info[] = { /* TCP L1 Cache per CU */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -95,8 +99,9 @@ static struct kfd_gpu_cache_info carrizo_cache_info[] = { }, { /* Scalar L1 Instruction Cache (in SQC module) per bank */ - .cache_size = 8, + .cache_size = 32, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_INST_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -104,8 +109,9 @@ static struct kfd_gpu_cache_info carrizo_cache_info[] = { }, { /* Scalar L1 Data Cache (in SQC module) per bank. */ - .cache_size = 4, + .cache_size = 16, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -135,6 +141,7 @@ static struct kfd_gpu_cache_info vega10_cache_info[] = { /* TCP L1 Cache per CU */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -144,6 +151,7 @@ static struct kfd_gpu_cache_info vega10_cache_info[] = { /* Scalar L1 Instruction Cache per SQC */ .cache_size = 32, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_INST_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -153,6 +161,7 @@ static struct kfd_gpu_cache_info vega10_cache_info[] = { /* Scalar L1 Data Cache per SQC */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -162,6 +171,7 @@ static struct kfd_gpu_cache_info vega10_cache_info[] = { /* L2 Data Cache per GPU (Total Tex Cache) */ .cache_size = 4096, .cache_level = 2, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -174,6 +184,7 @@ static struct kfd_gpu_cache_info raven_cache_info[] = { /* TCP L1 Cache per CU */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -183,6 +194,7 @@ static struct kfd_gpu_cache_info raven_cache_info[] = { /* Scalar L1 Instruction Cache per SQC */ .cache_size = 32, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_INST_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -192,6 +204,7 @@ static struct kfd_gpu_cache_info raven_cache_info[] = { /* Scalar L1 Data Cache per SQC */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -201,6 +214,7 @@ static struct kfd_gpu_cache_info raven_cache_info[] = { /* L2 Data Cache per GPU (Total Tex Cache) */ .cache_size = 1024, .cache_level = 2, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -213,6 +227,7 @@ static struct kfd_gpu_cache_info renoir_cache_info[] = { /* TCP L1 Cache per CU */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -222,6 +237,7 @@ static struct kfd_gpu_cache_info renoir_cache_info[] = { /* Scalar L1 Instruction Cache per SQC */ .cache_size = 32, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_INST_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -231,6 +247,7 @@ static struct kfd_gpu_cache_info renoir_cache_info[] = { /* Scalar L1 Data Cache per SQC */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -240,6 +257,7 @@ static struct kfd_gpu_cache_info renoir_cache_info[] = { /* L2 Data Cache per GPU (Total Tex Cache) */ .cache_size = 1024, .cache_level = 2, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -252,6 +270,7 @@ static struct kfd_gpu_cache_info vega12_cache_info[] = { /* TCP L1 Cache per CU */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -261,6 +280,7 @@ static struct kfd_gpu_cache_info vega12_cache_info[] = { /* Scalar L1 Instruction Cache per SQC */ .cache_size = 32, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_INST_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -270,6 +290,7 @@ static struct kfd_gpu_cache_info vega12_cache_info[] = { /* Scalar L1 Data Cache per SQC */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -279,6 +300,7 @@ static struct kfd_gpu_cache_info vega12_cache_info[] = { /* L2 Data Cache per GPU (Total Tex Cache) */ .cache_size = 2048, .cache_level = 2, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -291,6 +313,7 @@ static struct kfd_gpu_cache_info vega20_cache_info[] = { /* TCP L1 Cache per CU */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -300,6 +323,7 @@ static struct kfd_gpu_cache_info vega20_cache_info[] = { /* Scalar L1 Instruction Cache per SQC */ .cache_size = 32, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_INST_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -309,6 +333,7 @@ static struct kfd_gpu_cache_info vega20_cache_info[] = { /* Scalar L1 Data Cache per SQC */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -318,6 +343,7 @@ static struct kfd_gpu_cache_info vega20_cache_info[] = { /* L2 Data Cache per GPU (Total Tex Cache) */ .cache_size = 8192, .cache_level = 2, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -330,6 +356,7 @@ static struct kfd_gpu_cache_info aldebaran_cache_info[] = { /* TCP L1 Cache per CU */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -339,6 +366,7 @@ static struct kfd_gpu_cache_info aldebaran_cache_info[] = { /* Scalar L1 Instruction Cache per SQC */ .cache_size = 32, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_INST_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -348,6 +376,7 @@ static struct kfd_gpu_cache_info aldebaran_cache_info[] = { /* Scalar L1 Data Cache per SQC */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -357,6 +386,7 @@ static struct kfd_gpu_cache_info aldebaran_cache_info[] = { /* L2 Data Cache per GPU (Total Tex Cache) */ .cache_size = 8192, .cache_level = 2, + .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -369,6 +399,7 @@ static struct kfd_gpu_cache_info navi10_cache_info[] = { /* TCP L1 Cache per CU */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -378,6 +409,7 @@ static struct kfd_gpu_cache_info navi10_cache_info[] = { /* Scalar L1 Instruction Cache per SQC */ .cache_size = 32, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_INST_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -387,6 +419,7 @@ static struct kfd_gpu_cache_info navi10_cache_info[] = { /* Scalar L1 Data Cache per SQC */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -396,6 +429,7 @@ static struct kfd_gpu_cache_info navi10_cache_info[] = { /* GL1 Data Cache per SA */ .cache_size = 128, .cache_level = 1, + .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -405,6 +439,7 @@ static struct kfd_gpu_cache_info navi10_cache_info[] = { /* L2 Data Cache per GPU (Total Tex Cache) */ .cache_size = 4096, .cache_level = 2, + .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -417,6 +452,7 @@ static struct kfd_gpu_cache_info vangogh_cache_info[] = { /* TCP L1 Cache per CU */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -426,6 +462,7 @@ static struct kfd_gpu_cache_info vangogh_cache_info[] = { /* Scalar L1 Instruction Cache per SQC */ .cache_size = 32, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_INST_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -435,6 +472,7 @@ static struct kfd_gpu_cache_info vangogh_cache_info[] = { /* Scalar L1 Data Cache per SQC */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -444,6 +482,7 @@ static struct kfd_gpu_cache_info vangogh_cache_info[] = { /* GL1 Data Cache per SA */ .cache_size = 128, .cache_level = 1, + .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -453,6 +492,7 @@ static struct kfd_gpu_cache_info vangogh_cache_info[] = { /* L2 Data Cache per GPU (Total Tex Cache) */ .cache_size = 1024, .cache_level = 2, + .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -465,6 +505,7 @@ static struct kfd_gpu_cache_info navi14_cache_info[] = { /* TCP L1 Cache per CU */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -474,6 +515,7 @@ static struct kfd_gpu_cache_info navi14_cache_info[] = { /* Scalar L1 Instruction Cache per SQC */ .cache_size = 32, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_INST_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -483,6 +525,7 @@ static struct kfd_gpu_cache_info navi14_cache_info[] = { /* Scalar L1 Data Cache per SQC */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -492,6 +535,7 @@ static struct kfd_gpu_cache_info navi14_cache_info[] = { /* GL1 Data Cache per SA */ .cache_size = 128, .cache_level = 1, + .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -501,6 +545,7 @@ static struct kfd_gpu_cache_info navi14_cache_info[] = { /* L2 Data Cache per GPU (Total Tex Cache) */ .cache_size = 2048, .cache_level = 2, + .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -513,6 +558,7 @@ static struct kfd_gpu_cache_info sienna_cichlid_cache_info[] = { /* TCP L1 Cache per CU */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -522,6 +568,7 @@ static struct kfd_gpu_cache_info sienna_cichlid_cache_info[] = { /* Scalar L1 Instruction Cache per SQC */ .cache_size = 32, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_INST_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -531,6 +578,7 @@ static struct kfd_gpu_cache_info sienna_cichlid_cache_info[] = { /* Scalar L1 Data Cache per SQC */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -540,6 +588,7 @@ static struct kfd_gpu_cache_info sienna_cichlid_cache_info[] = { /* GL1 Data Cache per SA */ .cache_size = 128, .cache_level = 1, + .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -549,6 +598,7 @@ static struct kfd_gpu_cache_info sienna_cichlid_cache_info[] = { /* L2 Data Cache per GPU (Total Tex Cache) */ .cache_size = 4096, .cache_level = 2, + .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -558,6 +608,7 @@ static struct kfd_gpu_cache_info sienna_cichlid_cache_info[] = { /* L3 Data Cache per GPU */ .cache_size = 128*1024, .cache_level = 3, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -570,6 +621,7 @@ static struct kfd_gpu_cache_info navy_flounder_cache_info[] = { /* TCP L1 Cache per CU */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -579,6 +631,7 @@ static struct kfd_gpu_cache_info navy_flounder_cache_info[] = { /* Scalar L1 Instruction Cache per SQC */ .cache_size = 32, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_INST_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -588,6 +641,7 @@ static struct kfd_gpu_cache_info navy_flounder_cache_info[] = { /* Scalar L1 Data Cache per SQC */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -597,6 +651,7 @@ static struct kfd_gpu_cache_info navy_flounder_cache_info[] = { /* GL1 Data Cache per SA */ .cache_size = 128, .cache_level = 1, + .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -606,6 +661,7 @@ static struct kfd_gpu_cache_info navy_flounder_cache_info[] = { /* L2 Data Cache per GPU (Total Tex Cache) */ .cache_size = 3072, .cache_level = 2, + .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -615,6 +671,7 @@ static struct kfd_gpu_cache_info navy_flounder_cache_info[] = { /* L3 Data Cache per GPU */ .cache_size = 96*1024, .cache_level = 3, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -627,6 +684,7 @@ static struct kfd_gpu_cache_info dimgrey_cavefish_cache_info[] = { /* TCP L1 Cache per CU */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -636,6 +694,7 @@ static struct kfd_gpu_cache_info dimgrey_cavefish_cache_info[] = { /* Scalar L1 Instruction Cache per SQC */ .cache_size = 32, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_INST_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -645,6 +704,7 @@ static struct kfd_gpu_cache_info dimgrey_cavefish_cache_info[] = { /* Scalar L1 Data Cache per SQC */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -654,6 +714,7 @@ static struct kfd_gpu_cache_info dimgrey_cavefish_cache_info[] = { /* GL1 Data Cache per SA */ .cache_size = 128, .cache_level = 1, + .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -663,6 +724,7 @@ static struct kfd_gpu_cache_info dimgrey_cavefish_cache_info[] = { /* L2 Data Cache per GPU (Total Tex Cache) */ .cache_size = 2048, .cache_level = 2, + .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -672,6 +734,7 @@ static struct kfd_gpu_cache_info dimgrey_cavefish_cache_info[] = { /* L3 Data Cache per GPU */ .cache_size = 32*1024, .cache_level = 3, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -684,6 +747,7 @@ static struct kfd_gpu_cache_info beige_goby_cache_info[] = { /* TCP L1 Cache per CU */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -693,6 +757,7 @@ static struct kfd_gpu_cache_info beige_goby_cache_info[] = { /* Scalar L1 Instruction Cache per SQC */ .cache_size = 32, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_INST_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -702,6 +767,7 @@ static struct kfd_gpu_cache_info beige_goby_cache_info[] = { /* Scalar L1 Data Cache per SQC */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -711,6 +777,7 @@ static struct kfd_gpu_cache_info beige_goby_cache_info[] = { /* GL1 Data Cache per SA */ .cache_size = 128, .cache_level = 1, + .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -720,6 +787,7 @@ static struct kfd_gpu_cache_info beige_goby_cache_info[] = { /* L2 Data Cache per GPU (Total Tex Cache) */ .cache_size = 1024, .cache_level = 2, + .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -729,6 +797,7 @@ static struct kfd_gpu_cache_info beige_goby_cache_info[] = { /* L3 Data Cache per GPU */ .cache_size = 16*1024, .cache_level = 3, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -741,6 +810,7 @@ static struct kfd_gpu_cache_info yellow_carp_cache_info[] = { /* TCP L1 Cache per CU */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -750,6 +820,7 @@ static struct kfd_gpu_cache_info yellow_carp_cache_info[] = { /* Scalar L1 Instruction Cache per SQC */ .cache_size = 32, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_INST_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -759,6 +830,7 @@ static struct kfd_gpu_cache_info yellow_carp_cache_info[] = { /* Scalar L1 Data Cache per SQC */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -768,6 +840,7 @@ static struct kfd_gpu_cache_info yellow_carp_cache_info[] = { /* GL1 Data Cache per SA */ .cache_size = 128, .cache_level = 1, + .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -777,6 +850,7 @@ static struct kfd_gpu_cache_info yellow_carp_cache_info[] = { /* L2 Data Cache per GPU (Total Tex Cache) */ .cache_size = 2048, .cache_level = 2, + .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -789,6 +863,7 @@ static struct kfd_gpu_cache_info gfx1037_cache_info[] = { /* TCP L1 Cache per CU */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -798,6 +873,7 @@ static struct kfd_gpu_cache_info gfx1037_cache_info[] = { /* Scalar L1 Instruction Cache per SQC */ .cache_size = 32, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_INST_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -807,6 +883,7 @@ static struct kfd_gpu_cache_info gfx1037_cache_info[] = { /* Scalar L1 Data Cache per SQC */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -816,6 +893,7 @@ static struct kfd_gpu_cache_info gfx1037_cache_info[] = { /* GL1 Data Cache per SA */ .cache_size = 128, .cache_level = 1, + .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -825,6 +903,7 @@ static struct kfd_gpu_cache_info gfx1037_cache_info[] = { /* L2 Data Cache per GPU (Total Tex Cache) */ .cache_size = 256, .cache_level = 2, + .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -837,6 +916,7 @@ static struct kfd_gpu_cache_info gc_10_3_6_cache_info[] = { /* TCP L1 Cache per CU */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -846,6 +926,7 @@ static struct kfd_gpu_cache_info gc_10_3_6_cache_info[] = { /* Scalar L1 Instruction Cache per SQC */ .cache_size = 32, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_INST_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -855,6 +936,7 @@ static struct kfd_gpu_cache_info gc_10_3_6_cache_info[] = { /* Scalar L1 Data Cache per SQC */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -864,6 +946,7 @@ static struct kfd_gpu_cache_info gc_10_3_6_cache_info[] = { /* GL1 Data Cache per SA */ .cache_size = 128, .cache_level = 1, + .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -873,6 +956,7 @@ static struct kfd_gpu_cache_info gc_10_3_6_cache_info[] = { /* L2 Data Cache per GPU (Total Tex Cache) */ .cache_size = 256, .cache_level = 2, + .cache_line_size = 128, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -885,6 +969,7 @@ static struct kfd_gpu_cache_info dummy_cache_info[] = { /* TCP L1 Cache per CU */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -894,6 +979,7 @@ static struct kfd_gpu_cache_info dummy_cache_info[] = { /* Scalar L1 Instruction Cache per SQC */ .cache_size = 32, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_INST_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -903,6 +989,7 @@ static struct kfd_gpu_cache_info dummy_cache_info[] = { /* Scalar L1 Data Cache per SQC */ .cache_size = 16, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -912,6 +999,7 @@ static struct kfd_gpu_cache_info dummy_cache_info[] = { /* GL1 Data Cache per SA */ .cache_size = 128, .cache_level = 1, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), @@ -921,6 +1009,7 @@ static struct kfd_gpu_cache_info dummy_cache_info[] = { /* L2 Data Cache per GPU (Total Tex Cache) */ .cache_size = 2048, .cache_level = 2, + .cache_line_size = 64, .flags = (CRAT_CACHE_FLAGS_ENABLED | CRAT_CACHE_FLAGS_DATA_CACHE | CRAT_CACHE_FLAGS_SIMD_CACHE), diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_crat.h b/drivers/gpu/drm/amd/amdkfd/kfd_crat.h index 2f54ee08f2696..a8ca7ecb6d271 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_crat.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_crat.h @@ -301,6 +301,7 @@ struct kfd_node; struct kfd_gpu_cache_info { uint32_t cache_size; uint32_t cache_level; + uint32_t cache_line_size; uint32_t flags; /* Indicates how many Compute Units share this cache * within a SA. Value = 1 indicates the cache is not shared diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c index bd692eefec616..7ccd9983e1368 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_topology.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_topology.c @@ -1711,6 +1711,7 @@ static int fill_in_l1_pcache(struct kfd_cache_properties **props_ext, pcache->processor_id_low = cu_processor_id + (first_active_cu - 1); pcache->cache_level = pcache_info[cache_type].cache_level; pcache->cache_size = pcache_info[cache_type].cache_size; + pcache->cacheline_size = pcache_info[cache_type].cache_line_size; if (pcache_info[cache_type].flags & CRAT_CACHE_FLAGS_DATA_CACHE) pcache->cache_type |= HSA_CACHE_TYPE_DATA; @@ -1779,6 +1780,7 @@ static int fill_in_l2_l3_pcache(struct kfd_cache_properties **props_ext, pcache->processor_id_low = cu_processor_id + (first_active_cu - 1); pcache->cache_level = pcache_info[cache_type].cache_level; + pcache->cacheline_size = pcache_info[cache_type].cache_line_size; if (KFD_GC_VERSION(knode) == IP_VERSION(9, 4, 3) || KFD_GC_VERSION(knode) == IP_VERSION(9, 4, 4)) From 9cef84b0a3bcc35fed8fb750b5d7b1ae1fe11a9c Mon Sep 17 00:00:00 2001 From: Prike Liang Date: Fri, 23 Aug 2024 09:48:13 +0800 Subject: [PATCH 1545/1868] drm/amdgpu: update suspend status for aborting from deeper suspend There're some other suspend abort cases which can call the noirq suspend except for executing _S3 method. In those cases need to process as incomplete suspendsion. Signed-off-by: Prike Liang Acked-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/soc15.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index 8d16dacdc1720..cf701bb8fc797 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -587,11 +587,13 @@ static bool soc15_need_reset_on_resume(struct amdgpu_device *adev) * 2) S3 suspend abort and TOS already launched. */ if (adev->flags & AMD_IS_APU && adev->in_s3 && - !adev->suspend_complete && - sol_reg) + sol_reg) { + adev->suspend_complete = false; return true; - - return false; + } else { + adev->suspend_complete = true; + return false; + } } static int soc15_asic_reset(struct amdgpu_device *adev) From fd6c8eadf8716788928c3efa1ed84f57fcc733e7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Tue, 27 Aug 2024 16:12:11 +0200 Subject: [PATCH 1546/1868] drm/amdgpu: nuke the VM PD/PT shadow handling MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This was only used as workaround for recovering the page tables after VRAM was lost and is no longer necessary after the function amdgpu_vm_bo_reset_state_machine() started to do the same. Compute never used shadows either, so the only proplematic case left is SVM and that is most likely not recoverable in any way when VRAM is lost. Signed-off-by: Christian König Acked-by: Lijo Lazar --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4 - drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 87 +-------------------- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 67 +--------------- drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 21 ----- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 17 ---- drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c | 56 +------------ drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 19 +---- 7 files changed, 6 insertions(+), 265 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 3515a39fda660..9298d274bb3d2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1107,10 +1107,6 @@ struct amdgpu_device { struct amdgpu_virt virt; - /* link all shadow bo */ - struct list_head shadow_list; - struct mutex shadow_list_lock; - /* record hw reset is performed */ bool has_hw_reset; u8 reset_magic[AMDGPU_RESET_MAGIC_NUM]; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 68a3c958f3e2f..5f0cd9cc20785 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -4125,9 +4125,6 @@ int amdgpu_device_init(struct amdgpu_device *adev, spin_lock_init(&adev->mm_stats.lock); spin_lock_init(&adev->wb.lock); - INIT_LIST_HEAD(&adev->shadow_list); - mutex_init(&adev->shadow_list_lock); - INIT_LIST_HEAD(&adev->reset_list); INIT_LIST_HEAD(&adev->ras_list); @@ -5070,80 +5067,6 @@ static int amdgpu_device_ip_post_soft_reset(struct amdgpu_device *adev) return 0; } -/** - * amdgpu_device_recover_vram - Recover some VRAM contents - * - * @adev: amdgpu_device pointer - * - * Restores the contents of VRAM buffers from the shadows in GTT. Used to - * restore things like GPUVM page tables after a GPU reset where - * the contents of VRAM might be lost. - * - * Returns: - * 0 on success, negative error code on failure. - */ -static int amdgpu_device_recover_vram(struct amdgpu_device *adev) -{ - struct dma_fence *fence = NULL, *next = NULL; - struct amdgpu_bo *shadow; - struct amdgpu_bo_vm *vmbo; - long r = 1, tmo; - - if (amdgpu_sriov_runtime(adev)) - tmo = msecs_to_jiffies(8000); - else - tmo = msecs_to_jiffies(100); - - dev_info(adev->dev, "recover vram bo from shadow start\n"); - mutex_lock(&adev->shadow_list_lock); - list_for_each_entry(vmbo, &adev->shadow_list, shadow_list) { - /* If vm is compute context or adev is APU, shadow will be NULL */ - if (!vmbo->shadow) - continue; - shadow = vmbo->shadow; - - /* No need to recover an evicted BO */ - if (!shadow->tbo.resource || - shadow->tbo.resource->mem_type != TTM_PL_TT || - shadow->tbo.resource->start == AMDGPU_BO_INVALID_OFFSET || - shadow->parent->tbo.resource->mem_type != TTM_PL_VRAM) - continue; - - r = amdgpu_bo_restore_shadow(shadow, &next); - if (r) - break; - - if (fence) { - tmo = dma_fence_wait_timeout(fence, false, tmo); - dma_fence_put(fence); - fence = next; - if (tmo == 0) { - r = -ETIMEDOUT; - break; - } else if (tmo < 0) { - r = tmo; - break; - } - } else { - fence = next; - } - } - mutex_unlock(&adev->shadow_list_lock); - - if (fence) - tmo = dma_fence_wait_timeout(fence, false, tmo); - dma_fence_put(fence); - - if (r < 0 || tmo <= 0) { - dev_err(adev->dev, "recover vram bo from shadow failed, r is %ld, tmo is %ld\n", r, tmo); - return -EIO; - } - - dev_info(adev->dev, "recover vram bo from shadow done\n"); - return 0; -} - - /** * amdgpu_device_reset_sriov - reset ASIC for SR-IOV vf * @@ -5206,12 +5129,8 @@ static int amdgpu_device_reset_sriov(struct amdgpu_device *adev, if (r) return r; - if (adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) { + if (adev->virt.gim_feature & AMDGIM_FEATURE_GIM_FLR_VRAMLOST) amdgpu_inc_vram_lost(adev); - r = amdgpu_device_recover_vram(adev); - } - if (r) - return r; /* need to be called during full access so we can't do it later like * bare-metal does. @@ -5610,9 +5529,7 @@ int amdgpu_do_asic_reset(struct list_head *device_list_handle, } } - if (!r) - r = amdgpu_device_recover_vram(tmp_adev); - else + if (r) tmp_adev->asic_reset_res = r; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index 6a84cd130d677..14a10e73f0575 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -79,24 +79,6 @@ static void amdgpu_bo_user_destroy(struct ttm_buffer_object *tbo) amdgpu_bo_destroy(tbo); } -static void amdgpu_bo_vm_destroy(struct ttm_buffer_object *tbo) -{ - struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev); - struct amdgpu_bo *shadow_bo = ttm_to_amdgpu_bo(tbo), *bo; - struct amdgpu_bo_vm *vmbo; - - bo = shadow_bo->parent; - vmbo = to_amdgpu_bo_vm(bo); - /* in case amdgpu_device_recover_vram got NULL of bo->parent */ - if (!list_empty(&vmbo->shadow_list)) { - mutex_lock(&adev->shadow_list_lock); - list_del_init(&vmbo->shadow_list); - mutex_unlock(&adev->shadow_list_lock); - } - - amdgpu_bo_destroy(tbo); -} - /** * amdgpu_bo_is_amdgpu_bo - check if the buffer object is an &amdgpu_bo * @bo: buffer object to be checked @@ -110,8 +92,7 @@ static void amdgpu_bo_vm_destroy(struct ttm_buffer_object *tbo) bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo) { if (bo->destroy == &amdgpu_bo_destroy || - bo->destroy == &amdgpu_bo_user_destroy || - bo->destroy == &amdgpu_bo_vm_destroy) + bo->destroy == &amdgpu_bo_user_destroy) return true; return false; @@ -752,52 +733,6 @@ int amdgpu_bo_create_vm(struct amdgpu_device *adev, return r; } -/** - * amdgpu_bo_add_to_shadow_list - add a BO to the shadow list - * - * @vmbo: BO that will be inserted into the shadow list - * - * Insert a BO to the shadow list. - */ -void amdgpu_bo_add_to_shadow_list(struct amdgpu_bo_vm *vmbo) -{ - struct amdgpu_device *adev = amdgpu_ttm_adev(vmbo->bo.tbo.bdev); - - mutex_lock(&adev->shadow_list_lock); - list_add_tail(&vmbo->shadow_list, &adev->shadow_list); - vmbo->shadow->parent = amdgpu_bo_ref(&vmbo->bo); - vmbo->shadow->tbo.destroy = &amdgpu_bo_vm_destroy; - mutex_unlock(&adev->shadow_list_lock); -} - -/** - * amdgpu_bo_restore_shadow - restore an &amdgpu_bo shadow - * - * @shadow: &amdgpu_bo shadow to be restored - * @fence: dma_fence associated with the operation - * - * Copies a buffer object's shadow content back to the object. - * This is used for recovering a buffer from its shadow in case of a gpu - * reset where vram context may be lost. - * - * Returns: - * 0 for success or a negative error code on failure. - */ -int amdgpu_bo_restore_shadow(struct amdgpu_bo *shadow, struct dma_fence **fence) - -{ - struct amdgpu_device *adev = amdgpu_ttm_adev(shadow->tbo.bdev); - struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring; - uint64_t shadow_addr, parent_addr; - - shadow_addr = amdgpu_bo_gpu_offset(shadow); - parent_addr = amdgpu_bo_gpu_offset(shadow->parent); - - return amdgpu_copy_buffer(ring, shadow_addr, parent_addr, - amdgpu_bo_size(shadow), NULL, fence, - true, false, 0); -} - /** * amdgpu_bo_kmap - map an &amdgpu_bo buffer object * @bo: &amdgpu_bo buffer object to be mapped diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h index 74cfaf0fb8fe1..6e28b44d25c73 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h @@ -148,8 +148,6 @@ struct amdgpu_bo_user { struct amdgpu_bo_vm { struct amdgpu_bo bo; - struct amdgpu_bo *shadow; - struct list_head shadow_list; struct amdgpu_vm_bo_base entries[]; }; @@ -291,22 +289,6 @@ static inline bool amdgpu_bo_encrypted(struct amdgpu_bo *bo) return bo->flags & AMDGPU_GEM_CREATE_ENCRYPTED; } -/** - * amdgpu_bo_shadowed - check if the BO is shadowed - * - * @bo: BO to be tested. - * - * Returns: - * NULL if not shadowed or else return a BO pointer. - */ -static inline struct amdgpu_bo *amdgpu_bo_shadowed(struct amdgpu_bo *bo) -{ - if (bo->tbo.type == ttm_bo_type_kernel) - return to_amdgpu_bo_vm(bo)->shadow; - - return NULL; -} - bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo); void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain); @@ -365,9 +347,6 @@ u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo); u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo); void amdgpu_bo_get_memory(struct amdgpu_bo *bo, struct amdgpu_mem_stats *stats); -void amdgpu_bo_add_to_shadow_list(struct amdgpu_bo_vm *vmbo); -int amdgpu_bo_restore_shadow(struct amdgpu_bo *shadow, - struct dma_fence **fence); uint32_t amdgpu_bo_get_preferred_domain(struct amdgpu_device *adev, uint32_t domain); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index 0e959bac094e9..a16b2050184e6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -480,7 +480,6 @@ int amdgpu_vm_validate(struct amdgpu_device *adev, struct amdgpu_vm *vm, { uint64_t new_vm_generation = amdgpu_vm_generation(adev, vm); struct amdgpu_vm_bo_base *bo_base; - struct amdgpu_bo *shadow; struct amdgpu_bo *bo; int r; @@ -501,16 +500,10 @@ int amdgpu_vm_validate(struct amdgpu_device *adev, struct amdgpu_vm *vm, spin_unlock(&vm->status_lock); bo = bo_base->bo; - shadow = amdgpu_bo_shadowed(bo); r = validate(param, bo); if (r) return r; - if (shadow) { - r = validate(param, shadow); - if (r) - return r; - } if (bo->tbo.type != ttm_bo_type_kernel) { amdgpu_vm_bo_moved(bo_base); @@ -2191,10 +2184,6 @@ void amdgpu_vm_bo_invalidate(struct amdgpu_device *adev, { struct amdgpu_vm_bo_base *bo_base; - /* shadow bo doesn't have bo base, its validation needs its parent */ - if (bo->parent && (amdgpu_bo_shadowed(bo->parent) == bo)) - bo = bo->parent; - for (bo_base = bo->vm_bo; bo_base; bo_base = bo_base->next) { struct amdgpu_vm *vm = bo_base->vm; @@ -2532,7 +2521,6 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, root_bo = amdgpu_bo_ref(&root->bo); r = amdgpu_bo_reserve(root_bo, true); if (r) { - amdgpu_bo_unref(&root->shadow); amdgpu_bo_unref(&root_bo); goto error_free_delayed; } @@ -2624,11 +2612,6 @@ int amdgpu_vm_make_compute(struct amdgpu_device *adev, struct amdgpu_vm *vm) vm->last_update = dma_fence_get_stub(); vm->is_compute_context = true; - /* Free the shadow bo for compute VM */ - amdgpu_bo_unref(&to_amdgpu_bo_vm(vm->root.bo)->shadow); - - goto unreserve_bo; - unreserve_bo: amdgpu_bo_unreserve(vm->root.bo); return r; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c index 761b7ac12f1ff..43ecd84a61011 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c @@ -383,14 +383,6 @@ int amdgpu_vm_pt_clear(struct amdgpu_device *adev, struct amdgpu_vm *vm, if (r) return r; - if (vmbo->shadow) { - struct amdgpu_bo *shadow = vmbo->shadow; - - r = ttm_bo_validate(&shadow->tbo, &shadow->placement, &ctx); - if (r) - return r; - } - if (!drm_dev_enter(adev_to_drm(adev), &idx)) return -ENODEV; @@ -448,10 +440,7 @@ int amdgpu_vm_pt_create(struct amdgpu_device *adev, struct amdgpu_vm *vm, int32_t xcp_id) { struct amdgpu_bo_param bp; - struct amdgpu_bo *bo; - struct dma_resv *resv; unsigned int num_entries; - int r; memset(&bp, 0, sizeof(bp)); @@ -484,42 +473,7 @@ int amdgpu_vm_pt_create(struct amdgpu_device *adev, struct amdgpu_vm *vm, if (vm->root.bo) bp.resv = amdkcl_ttm_resvp(&vm->root.bo->tbo); - r = amdgpu_bo_create_vm(adev, &bp, vmbo); - if (r) - return r; - - bo = &(*vmbo)->bo; - if (vm->is_compute_context || (adev->flags & AMD_IS_APU)) { - (*vmbo)->shadow = NULL; - return 0; - } - - if (!bp.resv) - WARN_ON(dma_resv_lock(amdkcl_ttm_resvp(&bo->tbo), - NULL)); - resv = bp.resv; - memset(&bp, 0, sizeof(bp)); - bp.size = amdgpu_vm_pt_size(adev, level); - bp.domain = AMDGPU_GEM_DOMAIN_GTT; - bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC; - bp.type = ttm_bo_type_kernel; - bp.resv = amdkcl_ttm_resvp(&bo->tbo); - bp.bo_ptr_size = sizeof(struct amdgpu_bo); - bp.xcp_id_plus1 = xcp_id + 1; - - r = amdgpu_bo_create(adev, &bp, &(*vmbo)->shadow); - - if (!resv) - dma_resv_unlock(amdkcl_ttm_resvp(&bo->tbo)); - - if (r) { - amdgpu_bo_unref(&bo); - return r; - } - - amdgpu_bo_add_to_shadow_list(*vmbo); - - return 0; + return amdgpu_bo_create_vm(adev, &bp, vmbo); } /** @@ -569,7 +523,6 @@ static int amdgpu_vm_pt_alloc(struct amdgpu_device *adev, return 0; error_free_pt: - amdgpu_bo_unref(&pt->shadow); amdgpu_bo_unref(&pt_bo); return r; } @@ -581,17 +534,10 @@ static int amdgpu_vm_pt_alloc(struct amdgpu_device *adev, */ static void amdgpu_vm_pt_free(struct amdgpu_vm_bo_base *entry) { - struct amdgpu_bo *shadow; - if (!entry->bo) return; entry->bo->vm_bo = NULL; - shadow = amdgpu_bo_shadowed(entry->bo); - if (shadow) { - ttm_bo_set_bulk_move(&shadow->tbo, NULL); - amdgpu_bo_unref(&shadow); - } ttm_bo_set_bulk_move(&entry->bo->tbo, NULL); spin_lock(&entry->vm->status_lock); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c index 7769884f555dd..b1c44648da82b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c @@ -35,16 +35,7 @@ */ static int amdgpu_vm_sdma_map_table(struct amdgpu_bo_vm *table) { - int r; - - r = amdgpu_ttm_alloc_gart(&table->bo.tbo); - if (r) - return r; - - if (table->shadow) - r = amdgpu_ttm_alloc_gart(&table->shadow->tbo); - - return r; + return amdgpu_ttm_alloc_gart(&table->bo.tbo); } /* Allocate a new job for @count PTE updates */ @@ -267,17 +258,13 @@ static int amdgpu_vm_sdma_update(struct amdgpu_vm_update_params *p, if (!p->pages_addr) { /* set page commands needed */ - if (vmbo->shadow) - amdgpu_vm_sdma_set_ptes(p, vmbo->shadow, pe, addr, - count, incr, flags); amdgpu_vm_sdma_set_ptes(p, bo, pe, addr, count, incr, flags); return 0; } /* copy commands needed */ - ndw -= p->adev->vm_manager.vm_pte_funcs->copy_pte_num_dw * - (vmbo->shadow ? 2 : 1); + ndw -= p->adev->vm_manager.vm_pte_funcs->copy_pte_num_dw; /* for padding */ ndw -= 7; @@ -292,8 +279,6 @@ static int amdgpu_vm_sdma_update(struct amdgpu_vm_update_params *p, pte[i] |= flags; } - if (vmbo->shadow) - amdgpu_vm_sdma_copy_ptes(p, vmbo->shadow, pe, nptes); amdgpu_vm_sdma_copy_ptes(p, bo, pe, nptes); pe += nptes * 8; From 3bcc02c71b8a0b8018b94027f53b0662beccac88 Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Thu, 18 Jul 2024 18:09:17 +0800 Subject: [PATCH 1547/1868] drm/amd/pm: Update SMUv13.0.6 PMFW headers Update PMFW interface headers for updated metrics table with gfx activity per xcd Signed-off-by: Asad Kamal Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h index 0b3c2f54a3433..822c6425d90e0 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h @@ -123,7 +123,7 @@ typedef enum { VOLTAGE_GUARDBAND_COUNT } GFX_GUARDBAND_e; -#define SMU_METRICS_TABLE_VERSION 0xC +#define SMU_METRICS_TABLE_VERSION 0xD typedef struct __attribute__((packed, aligned(4))) { uint32_t AccumulationCounter; @@ -227,6 +227,10 @@ typedef struct __attribute__((packed, aligned(4))) { // PCIE LINK Speed and width uint32_t PCIeLinkSpeed; uint32_t PCIeLinkWidth; + + // PER XCD ACTIVITY + uint32_t GfxBusy[8]; + uint64_t GfxBusyAcc[8]; } MetricsTableX_t; typedef struct __attribute__((packed, aligned(4))) { From 247d6cb1b74ad2898a1ff4905b02a7453663aca1 Mon Sep 17 00:00:00 2001 From: Robin Chen Date: Fri, 23 Aug 2024 15:00:28 +0800 Subject: [PATCH 1548/1868] drm/amd/display: Round calculated vtotal [WHY] The calculated vtotal may has 1 line deviation. To get precisely vtotal number, round the vtotal result. Cc: Mario Limonciello Cc: Alex Deucher Cc: stable@vger.kernel.org Reviewed-by: Anthony Koo Signed-off-by: Robin Chen Signed-off-by: Alex Hung Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/modules/freesync/freesync.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c index a40e6590215a6..bbd259cea4f4f 100644 --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c @@ -134,7 +134,7 @@ unsigned int mod_freesync_calc_v_total_from_refresh( v_total = div64_u64(div64_u64(((unsigned long long)( frame_duration_in_ns) * (stream->timing.pix_clk_100hz / 10)), - stream->timing.h_total), 1000000); + stream->timing.h_total) + 500000, 1000000); /* v_total cannot be less than nominal */ if (v_total < stream->timing.v_total) { From 94de2b863aceeffed24083bb5bc0db56b1c0302b Mon Sep 17 00:00:00 2001 From: Samson Tam Date: Fri, 23 Aug 2024 16:57:33 -0400 Subject: [PATCH 1549/1868] drm/amd/display: Use SDR white level to calculate matrix coefficients [WHY] Certain profiles have higher HDR multiplier than SDR white level max which is not currently supported. [HOW] Use SDR white level when calculating matrix coefficients for HDR RGB MPO path instead of HDR multiplier. Cc: Mario Limonciello Cc: Alex Deucher Cc: stable@vger.kernel.org Reviewed-by: Jun Lei Signed-off-by: Samson Tam Signed-off-by: Alex Hung Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/core/dc.c | 12 ++++++++++++ drivers/gpu/drm/amd/display/dc/dc.h | 3 +++ .../gpu/drm/amd/display/dc/dc_spl_translate.c | 9 +-------- drivers/gpu/drm/amd/display/dc/spl/dc_spl.c | 17 +++++++++++------ .../gpu/drm/amd/display/dc/spl/dc_spl_types.h | 2 +- 5 files changed, 28 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index a5a988fe1e742..cbb1521ba115c 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -2596,6 +2596,12 @@ static enum surface_update_type det_surface_update(const struct dc *dc, elevate_update_type(&overall_type, UPDATE_TYPE_MED); } + if (u->sdr_white_level_nits) + if (u->sdr_white_level_nits != u->surface->sdr_white_level_nits) { + update_flags->bits.sdr_white_level_nits = 1; + elevate_update_type(&overall_type, UPDATE_TYPE_FULL); + } + if (u->cm2_params) { if ((u->cm2_params->component_settings.shaper_3dlut_setting != u->surface->mcm_shaper_3dlut_setting) @@ -2876,6 +2882,10 @@ static void copy_surface_update_to_plane( surface->hdr_mult = srf_update->hdr_mult; + if (srf_update->sdr_white_level_nits) + surface->sdr_white_level_nits = + srf_update->sdr_white_level_nits; + if (srf_update->blend_tf) memcpy(&surface->blend_tf, srf_update->blend_tf, sizeof(surface->blend_tf)); @@ -4680,6 +4690,8 @@ static bool full_update_required(struct dc *dc, srf_updates[i].scaling_info || (srf_updates[i].hdr_mult.value && srf_updates[i].hdr_mult.value != srf_updates->surface->hdr_mult.value) || + (srf_updates[i].sdr_white_level_nits && + srf_updates[i].sdr_white_level_nits != srf_updates->surface->sdr_white_level_nits) || srf_updates[i].in_transfer_func || srf_updates[i].func_shaper || srf_updates[i].lut3d_func || diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 7542b0b1c3217..d41f1c2f743bd 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -1272,6 +1272,7 @@ union surface_update_flags { uint32_t tmz_changed:1; uint32_t mcm_transfer_function_enable_change:1; /* disable or enable MCM transfer func */ uint32_t full_update:1; + uint32_t sdr_white_level_nits:1; } bits; uint32_t raw; @@ -1354,6 +1355,7 @@ struct dc_plane_state { bool adaptive_sharpness_en; int sharpness_level; enum linear_light_scaling linear_light_scaling; + unsigned int sdr_white_level_nits; }; struct dc_plane_info { @@ -1511,6 +1513,7 @@ struct dc_surface_update { */ struct dc_cm2_parameters *cm2_params; const struct dc_csc_transform *cursor_csc_color_matrix; + unsigned int sdr_white_level_nits; }; /* diff --git a/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c b/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c index cd6de93eb91c3..f711fc2e3e651 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c +++ b/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c @@ -191,14 +191,7 @@ void translate_SPL_in_params_from_pipe_ctx(struct pipe_ctx *pipe_ctx, struct spl */ spl_in->is_fullscreen = dm_helpers_is_fullscreen(pipe_ctx->stream->ctx, pipe_ctx->stream); spl_in->is_hdr_on = dm_helpers_is_hdr_on(pipe_ctx->stream->ctx, pipe_ctx->stream); - spl_in->hdr_multx100 = 0; - if (spl_in->is_hdr_on) { - spl_in->hdr_multx100 = (uint32_t)dc_fixpt_floor(dc_fixpt_mul(plane_state->hdr_mult, - dc_fixpt_from_int(100))); - /* Disable sharpness for HDR Mult > 6.0 */ - if (spl_in->hdr_multx100 > 600) - spl_in->adaptive_sharpness.enable = false; - } + spl_in->sdr_white_level_nits = plane_state->sdr_white_level_nits; } /// @brief Translate SPL output parameters to pipe context diff --git a/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c b/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c index 15f7eda903e64..a59aa6b596875 100644 --- a/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c +++ b/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c @@ -1155,14 +1155,19 @@ static void spl_set_dscl_prog_data(struct spl_in *spl_in, struct spl_scratch *sp } /* Calculate C0-C3 coefficients based on HDR_mult */ -static void spl_calculate_c0_c3_hdr(struct dscl_prog_data *dscl_prog_data, uint32_t hdr_multx100) +static void spl_calculate_c0_c3_hdr(struct dscl_prog_data *dscl_prog_data, uint32_t sdr_white_level_nits) { struct spl_fixed31_32 hdr_mult, c0_mult, c1_mult, c2_mult; struct spl_fixed31_32 c0_calc, c1_calc, c2_calc; struct spl_custom_float_format fmt; + uint32_t hdr_multx100_int; - SPL_ASSERT(hdr_multx100); - hdr_mult = spl_fixpt_from_fraction((long long)hdr_multx100, 100LL); + if ((sdr_white_level_nits >= 80) && (sdr_white_level_nits <= 480)) + hdr_multx100_int = sdr_white_level_nits * 100 / 80; + else + hdr_multx100_int = 100; /* default for 80 nits otherwise */ + + hdr_mult = spl_fixpt_from_fraction((long long)hdr_multx100_int, 100LL); c0_mult = spl_fixpt_from_fraction(2126LL, 10000LL); c1_mult = spl_fixpt_from_fraction(7152LL, 10000LL); c2_mult = spl_fixpt_from_fraction(722LL, 10000LL); @@ -1191,7 +1196,7 @@ static void spl_calculate_c0_c3_hdr(struct dscl_prog_data *dscl_prog_data, uint3 static void spl_set_easf_data(struct spl_scratch *spl_scratch, struct spl_out *spl_out, bool enable_easf_v, bool enable_easf_h, enum linear_light_scaling lls_pref, enum spl_pixel_format format, enum system_setup setup, - uint32_t hdr_multx100) + uint32_t sdr_white_level_nits) { struct dscl_prog_data *dscl_prog_data = spl_out->dscl_prog_data; if (enable_easf_v) { @@ -1499,7 +1504,7 @@ static void spl_set_easf_data(struct spl_scratch *spl_scratch, struct spl_out *s dscl_prog_data->easf_ltonl_en = 1; // Linear input if ((setup == HDR_L) && (spl_is_rgb8(format))) { /* Calculate C0-C3 coefficients based on HDR multiplier */ - spl_calculate_c0_c3_hdr(dscl_prog_data, hdr_multx100); + spl_calculate_c0_c3_hdr(dscl_prog_data, sdr_white_level_nits); } else { // HDR_L ( DWM ) and SDR_L dscl_prog_data->easf_matrix_c0 = 0x4EF7; // fp1.5.10, C0 coefficient (LN_rec709: 0.2126 * (2^14)/125 = 27.86590720) @@ -1750,7 +1755,7 @@ bool spl_calculate_scaler_params(struct spl_in *spl_in, struct spl_out *spl_out) // Set EASF spl_set_easf_data(&spl_scratch, spl_out, enable_easf_v, enable_easf_h, spl_in->lls_pref, - spl_in->basic_in.format, setup, spl_in->hdr_multx100); + spl_in->basic_in.format, setup, spl_in->sdr_white_level_nits); // Set iSHARP vratio = spl_fixpt_ceil(spl_scratch.scl_data.ratios.vert); diff --git a/drivers/gpu/drm/amd/display/dc/spl/dc_spl_types.h b/drivers/gpu/drm/amd/display/dc/spl/dc_spl_types.h index 85b19ebe2c576..74f2a8c42f4f8 100644 --- a/drivers/gpu/drm/amd/display/dc/spl/dc_spl_types.h +++ b/drivers/gpu/drm/amd/display/dc/spl/dc_spl_types.h @@ -518,7 +518,7 @@ struct spl_in { bool is_hdr_on; int h_active; int v_active; - int hdr_multx100; + int sdr_white_level_nits; }; // end of SPL inputs From 4f08d3bd3ba6bd9260658e8217e85f9f57ed693f Mon Sep 17 00:00:00 2001 From: Ryan Seto Date: Mon, 19 Aug 2024 17:06:56 -0400 Subject: [PATCH 1550/1868] drm/amd/display: Implement new DPCD register handling [WHY] There are some monitor timings that seem to be supported without DSC but actually require DSC to be displayed. A VESA SCR introduced a new max uncompressed pixel rate cap register that we can use to handle these edge cases. [HOW] SST: Read caps from link and invalidate timings that exceed the max limit but do not support DSC. Then check for options override when determining BPP. MST: Read caps from virtual DPCD peer device or daisy chained SST monitor and set validation set BPPs to max if pixel rate exceeds uncompressed limit. Validation set optimization continues as normal. Reviewed-by: Wenjing Liu Signed-off-by: Ryan Seto Signed-off-by: Alex Hung Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/dc_dp_types.h | 12 ++++++++++++ drivers/gpu/drm/amd/display/dc/dc_dsc.h | 1 + drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 10 +++++----- .../gpu/drm/amd/display/dc/link/link_validation.c | 7 +++++++ .../display/dc/link/protocols/link_dp_capability.c | 5 +++++ 5 files changed, 30 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h index 519c3df78ee5b..41bd95e9177a4 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h @@ -969,6 +969,14 @@ union dp_sink_video_fallback_formats { uint8_t raw; }; +union dpcd_max_uncompressed_pixel_rate_cap { + struct { + uint16_t max_uncompressed_pixel_rate_cap :15; + uint16_t valid :1; + } bits; + uint8_t raw[2]; +}; + union dp_fec_capability1 { struct { uint8_t AGGREGATED_ERROR_COUNTERS_CAPABLE :1; @@ -1170,6 +1178,7 @@ struct dpcd_caps { struct dc_lttpr_caps lttpr_caps; struct adaptive_sync_caps adaptive_sync_caps; struct dpcd_usb4_dp_tunneling_info usb4_dp_tun_info; + union dpcd_max_uncompressed_pixel_rate_cap max_uncompressed_pixel_rate_cap; union dp_128b_132b_supported_link_rates dp_128b_132b_supported_link_rates; union dp_main_line_channel_coding_cap channel_coding_cap; @@ -1340,6 +1349,9 @@ struct dp_trace { #ifndef DP_CABLE_ATTRIBUTES_UPDATED_BY_DPTX #define DP_CABLE_ATTRIBUTES_UPDATED_BY_DPTX 0x110 #endif +#ifndef DPCD_MAX_UNCOMPRESSED_PIXEL_RATE_CAP +#define DPCD_MAX_UNCOMPRESSED_PIXEL_RATE_CAP 0x221c +#endif #ifndef DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE #define DP_REPEATER_CONFIGURATION_AND_STATUS_SIZE 0x50 #endif diff --git a/drivers/gpu/drm/amd/display/dc/dc_dsc.h b/drivers/gpu/drm/amd/display/dc/dc_dsc.h index fe3078b8789ef..2a5120ecf48be 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dsc.h +++ b/drivers/gpu/drm/amd/display/dc/dc_dsc.h @@ -59,6 +59,7 @@ struct dc_dsc_config_options { uint32_t max_target_bpp_limit_override_x16; uint32_t slice_height_granularity; uint32_t dsc_force_odm_hslice_override; + bool force_dsc_when_not_needed; }; bool dc_dsc_parse_dsc_dpcd(const struct dc *dc, diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c index a1727e5bf0247..79c426425911f 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c @@ -668,6 +668,7 @@ static bool decide_dsc_bandwidth_range( */ static bool decide_dsc_target_bpp_x16( const struct dc_dsc_policy *policy, + const struct dc_dsc_config_options *options, const struct dsc_enc_caps *dsc_common_caps, const int target_bandwidth_kbps, const struct dc_crtc_timing *timing, @@ -682,7 +683,7 @@ static bool decide_dsc_target_bpp_x16( if (decide_dsc_bandwidth_range(policy->min_target_bpp * 16, policy->max_target_bpp * 16, num_slices_h, dsc_common_caps, timing, link_encoding, &range)) { if (target_bandwidth_kbps >= range.stream_kbps) { - if (policy->enable_dsc_when_not_needed) + if (policy->enable_dsc_when_not_needed || options->force_dsc_when_not_needed) /* enable max bpp even dsc is not needed */ *target_bpp_x16 = range.max_target_bpp_x16; } else if (target_bandwidth_kbps >= range.max_kbps) { @@ -1080,6 +1081,7 @@ static bool setup_dsc_config( if (target_bandwidth_kbps > 0) { is_dsc_possible = decide_dsc_target_bpp_x16( &policy, + options, &dsc_common_caps, target_bandwidth_kbps, timing, @@ -1235,10 +1237,7 @@ void dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing, policy->max_target_bpp = max_target_bpp_limit_override_x16 / 16; /* enable DSC when not needed, default false */ - if (dsc_policy_enable_dsc_when_not_needed) - policy->enable_dsc_when_not_needed = dsc_policy_enable_dsc_when_not_needed; - else - policy->enable_dsc_when_not_needed = false; + policy->enable_dsc_when_not_needed = dsc_policy_enable_dsc_when_not_needed; } void dc_dsc_policy_set_max_target_bpp_limit(uint32_t limit) @@ -1267,4 +1266,5 @@ void dc_dsc_get_default_config_option(const struct dc *dc, struct dc_dsc_config_ options->dsc_force_odm_hslice_override = dc->debug.force_odm_combine; options->max_target_bpp_limit_override_x16 = 0; options->slice_height_granularity = 1; + options->force_dsc_when_not_needed = false; } diff --git a/drivers/gpu/drm/amd/display/dc/link/link_validation.c b/drivers/gpu/drm/amd/display/dc/link/link_validation.c index 0b3e4f596cc2a..cd654db1ab3ed 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_validation.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_validation.c @@ -285,6 +285,13 @@ static bool dp_validate_mode_timing( req_bw = dc_bandwidth_in_kbps_from_timing(timing, dc_link_get_highest_encoding_format(link)); max_bw = dp_link_bandwidth_kbps(link, link_setting); + bool is_max_uncompressed_pixel_rate_exceeded = link->dpcd_caps.max_uncompressed_pixel_rate_cap.bits.valid && + timing->pix_clk_100hz > link->dpcd_caps.max_uncompressed_pixel_rate_cap.bits.max_uncompressed_pixel_rate_cap * 10000; + + if (is_max_uncompressed_pixel_rate_exceeded && !timing->flags.DSC) { + return false; + } + if (req_bw <= max_bw) { /* remember the biggest mode here, during * initial link training (to get diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c index 1b43d9a9d1b06..5041a2124c397 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c @@ -1943,6 +1943,11 @@ static bool retrieve_link_cap(struct dc_link *link) DC_LOG_DP2("\tFEC aggregated error counters are supported"); } + core_link_read_dpcd(link, + DPCD_MAX_UNCOMPRESSED_PIXEL_RATE_CAP, + link->dpcd_caps.max_uncompressed_pixel_rate_cap.raw, + sizeof(link->dpcd_caps.max_uncompressed_pixel_rate_cap.raw)); + retrieve_cable_id(link); dpcd_write_cable_id_to_dprx(link); From ebd174186b04575219e359c62a7b206e04513eb4 Mon Sep 17 00:00:00 2001 From: Daniel Sa Date: Fri, 23 Aug 2024 11:29:23 -0400 Subject: [PATCH 1551/1868] drm/amd/display: Emulate Display Hotplug Hang [WHY] Driver reports 0 display when the virtual display is still present, and causes P-state hang in FW. [HOW] When enumerating through streams, check for active planes and use that to indicate number of displays. Reviewed-by: Dillon Varone Signed-off-by: Daniel Sa Signed-off-by: Alex Hung Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c index f770828df1493..0e243f4344d05 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/clk_mgr.c @@ -59,6 +59,7 @@ int clk_mgr_helper_get_active_display_cnt( display_count = 0; for (i = 0; i < context->stream_count; i++) { const struct dc_stream_state *stream = context->streams[i]; + const struct dc_stream_status *stream_status = &context->stream_status[i]; /* Don't count SubVP phantom pipes as part of active * display count @@ -66,13 +67,7 @@ int clk_mgr_helper_get_active_display_cnt( if (dc_state_get_stream_subvp_type(context, stream) == SUBVP_PHANTOM) continue; - /* - * Only notify active stream or virtual stream. - * Need to notify virtual stream to work around - * headless case. HPD does not fire when system is in - * S0i2. - */ - if (!stream->dpms_off || stream->signal == SIGNAL_TYPE_VIRTUAL) + if (!stream->dpms_off || (stream_status && stream_status->plane_count)) display_count++; } From 7c990b0bd52aaeb08735fe83ebbf1898624140dc Mon Sep 17 00:00:00 2001 From: Roman Li Date: Wed, 21 Aug 2024 10:53:15 -0400 Subject: [PATCH 1552/1868] drm/amd/display: Add dmub hpd sense callback [WHY] HPD sense notification has been implemented in DMUB, which can occur during low power states and need to be notified from firmware to driver. [HOW] Define callback and register new HPD sense notification. Reviewed-by: Nicholas Kazlauskas Signed-off-by: Roman Li Signed-off-by: Alex Hung Tested-by: Daniel Wheeler --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 20 +++++++++++++++++++ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 2 +- 2 files changed, 21 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index db606df14368a..3a78a2f1b5448 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -820,6 +820,20 @@ static void dmub_hpd_callback(struct amdgpu_device *adev, } } +/** + * dmub_hpd_sense_callback - DMUB HPD sense processing callback. + * @adev: amdgpu_device pointer + * @notify: dmub notification structure + * + * HPD sense changes can occur during low power states and need to be + * notified from firmware to driver. + */ +static void dmub_hpd_sense_callback(struct amdgpu_device *adev, + struct dmub_notification *notify) +{ + DRM_DEBUG_DRIVER("DMUB HPD SENSE callback.\n"); +} + /** * register_dmub_notify_callback - Sets callback for DMUB notify * @adev: amdgpu_device pointer @@ -3853,6 +3867,12 @@ static int register_hpd_handlers(struct amdgpu_device *adev) DRM_ERROR("amdgpu: fail to register dmub hpd callback"); return -EINVAL; } + + if (!register_dmub_notify_callback(adev, DMUB_NOTIFICATION_HPD_SENSE_NOTIFY, + dmub_hpd_sense_callback, true)) { + DRM_ERROR("amdgpu: fail to register dmub hpd sense callback"); + return -EINVAL; + } } list_for_each_entry(connector, diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index 861f9c03af65e..9fe06a6290a9f 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -50,7 +50,7 @@ #define AMDGPU_DM_MAX_NUM_EDP 2 -#define AMDGPU_DMUB_NOTIFICATION_MAX 6 +#define AMDGPU_DMUB_NOTIFICATION_MAX 7 #define HDMI_AMD_VENDOR_SPECIFIC_DATA_BLOCK_IEEE_REGISTRATION_ID 0x00001A #define AMD_VSDB_VERSION_3_FEATURECAP_REPLAYMODE 0x40 From 27f2286b803dab244ca0d0009d77f02a1415c61d Mon Sep 17 00:00:00 2001 From: Yihan Zhu Date: Mon, 26 Aug 2024 14:44:04 -0400 Subject: [PATCH 1553/1868] drm/amd/display: Enable DML2 override_det_buffer_size_kbytes [WHY] Corrupted screen will be observed when 4k144 DP/HDMI display and 4k144 eDP are connected, changing eDP refresh rate from 60Hz to 144Hz. [HOW] override_det_buffer_size_kbytes should be true for DCN35/DCN351. Cc: Mario Limonciello Cc: Alex Deucher Cc: stable@vger.kernel.org Reviewed-by: Roman Li Reviewed-by: Nicholas Kazlauskas Signed-off-by: Yihan Zhu Signed-off-by: Alex Hung Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c | 1 + drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c index 46ad684fe1920..893a9d9ee870d 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c @@ -2155,6 +2155,7 @@ static bool dcn35_resource_construct( dc->dml2_options.max_segments_per_hubp = 24; dc->dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;/*todo*/ + dc->dml2_options.override_det_buffer_size_kbytes = true; if (dc->config.sdpif_request_limit_words_per_umc == 0) dc->config.sdpif_request_limit_words_per_umc = 16;/*todo*/ diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c index 4c5e722baa3a6..514c6d56925d5 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c @@ -2133,6 +2133,7 @@ static bool dcn351_resource_construct( dc->dml2_options.max_segments_per_hubp = 24; dc->dml2_options.det_segment_size = DCN3_2_DET_SEG_SIZE;/*todo*/ + dc->dml2_options.override_det_buffer_size_kbytes = true; if (dc->config.sdpif_request_limit_words_per_umc == 0) dc->config.sdpif_request_limit_words_per_umc = 16;/*todo*/ From ccb9e9d0fb0ca35443d006b887f7364212a0b05d Mon Sep 17 00:00:00 2001 From: Dillon Varone Date: Mon, 26 Aug 2024 17:08:33 -0400 Subject: [PATCH 1554/1868] drm/amd/display: Block timing sync for different output formats in pmo [WHY & HOW] If the output format is different for HDMI TMDS signals, they are not synchronizable. Cc: Mario Limonciello Cc: Alex Deucher Cc: stable@vger.kernel.org Reviewed-by: Alvin Lee Signed-off-by: Dillon Varone Signed-off-by: Alex Hung Tested-by: Daniel Wheeler --- .../dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c index d63558ee31351..1cf9015e854a9 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c @@ -940,9 +940,11 @@ static void build_synchronized_timing_groups( /* find synchronizable timing groups */ for (j = i + 1; j < display_config->display_config.num_streams; j++) { if (memcmp(master_timing, - &display_config->display_config.stream_descriptors[j].timing, - sizeof(struct dml2_timing_cfg)) == 0 && - display_config->display_config.stream_descriptors[i].output.output_encoder == display_config->display_config.stream_descriptors[j].output.output_encoder) { + &display_config->display_config.stream_descriptors[j].timing, + sizeof(struct dml2_timing_cfg)) == 0 && + display_config->display_config.stream_descriptors[i].output.output_encoder == display_config->display_config.stream_descriptors[j].output.output_encoder && + (display_config->display_config.stream_descriptors[i].output.output_encoder != dml2_hdmi || //hdmi requires formats match + display_config->display_config.stream_descriptors[i].output.output_format == display_config->display_config.stream_descriptors[j].output.output_format)) { set_bit_in_bitfield(&pmo->scratch.pmo_dcn4.synchronized_timing_group_masks[timing_group_idx], j); set_bit_in_bitfield(&stream_mapped_mask, j); } From 22e88a306942abd817ffec98dd6129cb619c3d72 Mon Sep 17 00:00:00 2001 From: Samson Tam Date: Tue, 27 Aug 2024 11:53:10 -0400 Subject: [PATCH 1555/1868] drm/amd/display: Add debug options to change sharpen policies [WHY] Add options to change sharpen policy based on surface format and scaling ratios. [HOW] Add sharpen_policy to change policy based on surface format and scale_to_sharpness_policy based on scaling ratios. Reviewed-by: Jun Lei Signed-off-by: Samson Tam Signed-off-by: Alex Hung Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/dc.h | 2 + .../gpu/drm/amd/display/dc/dc_spl_translate.c | 5 ++ drivers/gpu/drm/amd/display/dc/spl/dc_spl.c | 34 ++++++-- .../display/dc/spl/dc_spl_isharp_filters.c | 85 +++++++++++++++++-- .../display/dc/spl/dc_spl_isharp_filters.h | 9 +- .../gpu/drm/amd/display/dc/spl/dc_spl_types.h | 12 +++ 6 files changed, 128 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index d41f1c2f743bd..7de04903775ba 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -1059,6 +1059,8 @@ struct dc_debug_options { unsigned int force_lls; bool notify_dpia_hr_bw; bool enable_ips_visual_confirm; + unsigned int sharpen_policy; + unsigned int scale_to_sharpness_policy; }; diff --git a/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c b/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c index f711fc2e3e651..603552dbd7716 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c +++ b/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c @@ -186,6 +186,11 @@ void translate_SPL_in_params_from_pipe_ctx(struct pipe_ctx *pipe_ctx, struct spl spl_in->h_active = pipe_ctx->plane_res.scl_data.h_active; spl_in->v_active = pipe_ctx->plane_res.scl_data.v_active; + + spl_in->debug.sharpen_policy = (enum sharpen_policy)pipe_ctx->stream->ctx->dc->debug.sharpen_policy; + spl_in->debug.scale_to_sharpness_policy = + (enum scale_to_sharpness_policy)pipe_ctx->stream->ctx->dc->debug.scale_to_sharpness_policy; + /* Check if it is stream is in fullscreen and if its HDR. * Use this to determine sharpness levels */ diff --git a/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c b/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c index a59aa6b596875..f7a654b3a092f 100644 --- a/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c +++ b/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c @@ -813,6 +813,14 @@ static bool enable_easf(struct spl_in *spl_in, struct spl_scratch *spl_scratch) return skip_easf; } +/* Check if video is in fullscreen mode */ +static bool spl_is_video_fullscreen(struct spl_in *spl_in) +{ + if (spl_is_yuv420(spl_in->basic_in.format) && spl_in->is_fullscreen) + return true; + return false; +} + static bool spl_get_isharp_en(struct spl_in *spl_in, struct spl_scratch *spl_scratch) { @@ -820,6 +828,7 @@ static bool spl_get_isharp_en(struct spl_in *spl_in, int vratio = 0; int hratio = 0; struct spl_taps taps = spl_scratch->scl_data.taps; + bool fullscreen = spl_is_video_fullscreen(spl_in); /* Return if adaptive sharpness is disabled */ if (spl_in->adaptive_sharpness.enable == false) @@ -835,9 +844,15 @@ static bool spl_get_isharp_en(struct spl_in *spl_in, // Scaling is up to 1:1 (no scaling) or upscaling /* - * Apply sharpness to all RGB surfaces and to - * NV12/P010 surfaces + * Apply sharpness to RGB and YUV (NV12/P010) + * surfaces based on policy setting */ + if (!spl_is_yuv420(spl_in->basic_in.format) && + (spl_in->debug.sharpen_policy == SHARPEN_YUV)) + return enable_isharp; + else if ((spl_is_yuv420(spl_in->basic_in.format) && !fullscreen) && + (spl_in->debug.sharpen_policy == SHARPEN_RGB_FULLSCREEN_YUV)) + return enable_isharp; /* * Apply sharpness if supports horizontal taps 4,6 AND @@ -1562,7 +1577,7 @@ static void spl_set_isharp_data(struct dscl_prog_data *dscl_prog_data, struct adaptive_sharpness adp_sharpness, bool enable_isharp, enum linear_light_scaling lls_pref, enum spl_pixel_format format, const struct spl_scaler_data *data, struct spl_fixed31_32 ratio, - enum system_setup setup) + enum system_setup setup, enum scale_to_sharpness_policy scale_to_sharpness_policy) { /* Turn off sharpener if not required */ if (!enable_isharp) { @@ -1570,6 +1585,11 @@ static void spl_set_isharp_data(struct dscl_prog_data *dscl_prog_data, return; } + spl_build_isharp_1dlut_from_reference_curve(ratio, setup, adp_sharpness, + scale_to_sharpness_policy); + dscl_prog_data->isharp_delta = spl_get_pregen_filter_isharp_1D_lut(setup); + dscl_prog_data->sharpness_level = adp_sharpness.sharpness_level; + dscl_prog_data->isharp_en = 1; // ISHARP_EN // Set ISHARP_NOISEDET_MODE if htaps = 6-tap if (data->taps.h_taps == 6) { @@ -1667,11 +1687,6 @@ static void spl_set_isharp_data(struct dscl_prog_data *dscl_prog_data, dscl_prog_data->isharp_lba.base_seg[5] = 0; // ISHARP LBA PWL for Seg 5. BASE value in U0.6 format } - - spl_build_isharp_1dlut_from_reference_curve(ratio, setup, adp_sharpness); - dscl_prog_data->isharp_delta = spl_get_pregen_filter_isharp_1D_lut(setup); - dscl_prog_data->sharpness_level = adp_sharpness.sharpness_level; - // Program the nldelta soft clip values if (lls_pref == LLS_PREF_YES) { dscl_prog_data->isharp_nldelta_sclip.enable_p = 0; /* ISHARP_NLDELTA_SCLIP_EN_P */ @@ -1766,7 +1781,8 @@ bool spl_calculate_scaler_params(struct spl_in *spl_in, struct spl_out *spl_out) isharp_scale_ratio = spl_scratch.scl_data.recip_ratios.horz; spl_set_isharp_data(spl_out->dscl_prog_data, spl_in->adaptive_sharpness, enable_isharp, - spl_in->lls_pref, spl_in->basic_in.format, data, isharp_scale_ratio, setup); + spl_in->lls_pref, spl_in->basic_in.format, data, isharp_scale_ratio, setup, + spl_in->debug.scale_to_sharpness_policy); return res; } diff --git a/drivers/gpu/drm/amd/display/dc/spl/dc_spl_isharp_filters.c b/drivers/gpu/drm/amd/display/dc/spl/dc_spl_isharp_filters.c index 33712f50d303b..e0572252c6404 100644 --- a/drivers/gpu/drm/amd/display/dc/spl/dc_spl_isharp_filters.c +++ b/drivers/gpu/drm/amd/display/dc/spl/dc_spl_isharp_filters.c @@ -500,6 +500,15 @@ struct isharp_1D_lut_pregen filter_isharp_1D_lut_pregen[NUM_SHARPNESS_SETUPS] = }, }; +struct scale_ratio_to_sharpness_level_adj sharpness_level_adj[NUM_SHARPNESS_ADJ_LEVELS] = { + {1125, 1000, 0}, + {11, 10, 1}, + {1075, 1000, 2}, + {105, 100, 3}, + {1025, 1000, 4}, + {1, 1, 5}, +}; + const uint32_t *spl_get_filter_isharp_1D_lut_0(void) { return filter_isharp_1D_lut_0; @@ -541,19 +550,72 @@ uint16_t *spl_get_filter_isharp_bs_3tap_64p(void) return filter_isharp_bs_3tap_64p_s1_12; } -static unsigned int spl_calculate_sharpness_level(int discrete_sharpness_level, enum system_setup setup, - struct spl_sharpness_range sharpness_range) +static unsigned int spl_calculate_sharpness_level_adj(struct spl_fixed31_32 ratio) +{ + int j; + struct spl_fixed31_32 ratio_level; + struct scale_ratio_to_sharpness_level_adj *lookup_ptr; + unsigned int sharpness_level_down_adj; + + /* + * Adjust sharpness level based on current scaling ratio + * + * We have 5 discrete scaling ratios which we will use to adjust the + * sharpness level down by 1 as we pass each ratio. The ratios + * are + * + * 1.125 upscale and higher - no adj + * 1.100 - under 1.125 - adj level down 1 + * 1.075 - under 1.100 - adj level down 2 + * 1.050 - under 1.075 - adj level down 3 + * 1.025 - under 1.050 - adj level down 4 + * 1.000 - under 1.025 - adj level down 5 + * + */ + j = 0; + sharpness_level_down_adj = 0; + lookup_ptr = sharpness_level_adj; + while (j < NUM_SHARPNESS_ADJ_LEVELS) { + ratio_level = spl_fixpt_from_fraction(lookup_ptr->ratio_numer, + lookup_ptr->ratio_denom); + if (ratio.value >= ratio_level.value) { + sharpness_level_down_adj = lookup_ptr->level_down_adj; + break; + } + lookup_ptr++; + j++; + } + return sharpness_level_down_adj; +} + +static unsigned int spl_calculate_sharpness_level(struct spl_fixed31_32 ratio, + int discrete_sharpness_level, enum system_setup setup, + struct spl_sharpness_range sharpness_range, + enum scale_to_sharpness_policy scale_to_sharpness_policy) { unsigned int sharpness_level = 0; + unsigned int sharpness_level_down_adj = 0; int min_sharpness, max_sharpness, mid_sharpness; + /* + * Adjust sharpness level if policy requires we adjust it based on + * scale ratio. Based on scale ratio, we may adjust the sharpness + * level down by a certain number of steps. We will not select + * a sharpness value of 0 so the lowest sharpness level will be + * 0 or 1 depending on what the min_sharpness is + * + * If the policy is no required, this code maybe removed at a later + * date + */ switch (setup) { case HDR_L: min_sharpness = sharpness_range.hdr_rgb_min; max_sharpness = sharpness_range.hdr_rgb_max; mid_sharpness = sharpness_range.hdr_rgb_mid; + if (scale_to_sharpness_policy == SCALE_TO_SHARPNESS_ADJ_ALL) + sharpness_level_down_adj = spl_calculate_sharpness_level_adj(ratio); break; case HDR_NL: /* currently no use case, use Non-linear SDR values for now */ @@ -561,15 +623,26 @@ static unsigned int spl_calculate_sharpness_level(int discrete_sharpness_level, min_sharpness = sharpness_range.sdr_yuv_min; max_sharpness = sharpness_range.sdr_yuv_max; mid_sharpness = sharpness_range.sdr_yuv_mid; + if (scale_to_sharpness_policy >= SCALE_TO_SHARPNESS_ADJ_YUV) + sharpness_level_down_adj = spl_calculate_sharpness_level_adj(ratio); break; case SDR_L: default: min_sharpness = sharpness_range.sdr_rgb_min; max_sharpness = sharpness_range.sdr_rgb_max; mid_sharpness = sharpness_range.sdr_rgb_mid; + if (scale_to_sharpness_policy == SCALE_TO_SHARPNESS_ADJ_ALL) + sharpness_level_down_adj = spl_calculate_sharpness_level_adj(ratio); break; } + if ((min_sharpness == 0) && (sharpness_level_down_adj >= discrete_sharpness_level)) + discrete_sharpness_level = 1; + else if (sharpness_level_down_adj >= discrete_sharpness_level) + discrete_sharpness_level = 0; + else + discrete_sharpness_level -= sharpness_level_down_adj; + int lower_half_step_size = (mid_sharpness - min_sharpness) / 5; int upper_half_step_size = (max_sharpness - mid_sharpness) / 5; @@ -584,7 +657,7 @@ static unsigned int spl_calculate_sharpness_level(int discrete_sharpness_level, } void spl_build_isharp_1dlut_from_reference_curve(struct spl_fixed31_32 ratio, enum system_setup setup, - struct adaptive_sharpness sharpness) + struct adaptive_sharpness sharpness, enum scale_to_sharpness_policy scale_to_sharpness_policy) { uint8_t *byte_ptr_1dlut_src, *byte_ptr_1dlut_dst; struct spl_fixed31_32 sharp_base, sharp_calc, sharp_level; @@ -594,8 +667,9 @@ void spl_build_isharp_1dlut_from_reference_curve(struct spl_fixed31_32 ratio, en uint32_t filter_pregen_store[ISHARP_LUT_TABLE_SIZE]; /* Custom sharpnessX1000 value */ - unsigned int sharpnessX1000 = spl_calculate_sharpness_level(sharpness.sharpness_level, - setup, sharpness.sharpness_range); + unsigned int sharpnessX1000 = spl_calculate_sharpness_level(ratio, + sharpness.sharpness_level, setup, + sharpness.sharpness_range, scale_to_sharpness_policy); sharp_level = spl_fixpt_from_fraction(sharpnessX1000, 1000); /* @@ -606,7 +680,6 @@ void spl_build_isharp_1dlut_from_reference_curve(struct spl_fixed31_32 ratio, en (filter_isharp_1D_lut_pregen[setup].sharpness_denom == 1000)) return; - /* * Calculate LUT_128_gained with this equation: * diff --git a/drivers/gpu/drm/amd/display/dc/spl/dc_spl_isharp_filters.h b/drivers/gpu/drm/amd/display/dc/spl/dc_spl_isharp_filters.h index fe0b12571f2c5..afcc66206ca2a 100644 --- a/drivers/gpu/drm/amd/display/dc/spl/dc_spl_isharp_filters.h +++ b/drivers/gpu/drm/amd/display/dc/spl/dc_spl_isharp_filters.h @@ -20,11 +20,11 @@ uint16_t *spl_get_filter_isharp_bs_3tap_64p(void); const uint16_t *spl_get_filter_isharp_wide_6tap_64p(void); uint16_t *spl_dscl_get_blur_scale_coeffs_64p(int taps); -struct scale_ratio_to_sharpness_level_lookup { +#define NUM_SHARPNESS_ADJ_LEVELS 6 +struct scale_ratio_to_sharpness_level_adj { unsigned int ratio_numer; unsigned int ratio_denom; - unsigned int sharpness_numer; - unsigned int sharpness_denom; + unsigned int level_down_adj; /* adjust sharpness level down */ }; struct isharp_1D_lut_pregen { @@ -45,6 +45,7 @@ void spl_init_blur_scale_coeffs(void); void spl_set_blur_scale_data(struct dscl_prog_data *dscl_prog_data, const struct spl_scaler_data *data); -void spl_build_isharp_1dlut_from_reference_curve(struct spl_fixed31_32 ratio, enum system_setup setup, struct adaptive_sharpness sharpness); +void spl_build_isharp_1dlut_from_reference_curve(struct spl_fixed31_32 ratio, enum system_setup setup, + struct adaptive_sharpness sharpness, enum scale_to_sharpness_policy scale_to_sharpness_policy); uint32_t *spl_get_pregen_filter_isharp_1D_lut(enum system_setup setup); #endif /* __DC_SPL_ISHARP_FILTERS_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/spl/dc_spl_types.h b/drivers/gpu/drm/amd/display/dc/spl/dc_spl_types.h index 74f2a8c42f4f8..425d4a282c7a7 100644 --- a/drivers/gpu/drm/amd/display/dc/spl/dc_spl_types.h +++ b/drivers/gpu/drm/amd/display/dc/spl/dc_spl_types.h @@ -487,6 +487,16 @@ enum linear_light_scaling { // convert it in translation logic LLS_PREF_YES, LLS_PREF_NO }; +enum sharpen_policy { + SHARPEN_ALWAYS = 0, + SHARPEN_YUV = 1, + SHARPEN_RGB_FULLSCREEN_YUV = 2 +}; +enum scale_to_sharpness_policy { + NO_SCALE_TO_SHARPNESS_ADJ = 0, + SCALE_TO_SHARPNESS_ADJ_YUV = 1, + SCALE_TO_SHARPNESS_ADJ_ALL = 2 +}; struct spl_funcs { void (*spl_calc_lb_num_partitions) (bool alpha_en, @@ -499,6 +509,8 @@ struct spl_funcs { struct spl_debug { int visual_confirm_base_offset; int visual_confirm_dpp_offset; + enum sharpen_policy sharpen_policy; + enum scale_to_sharpness_policy scale_to_sharpness_policy; }; struct spl_in { From 2a4a5e3c7d9115b0487b84411438ec7daabf977e Mon Sep 17 00:00:00 2001 From: Nicholas Kazlauskas Date: Tue, 27 Aug 2024 14:13:10 -0400 Subject: [PATCH 1556/1868] drm/amd/display: Block dynamic IPS2 on DCN35 for incompatible FW versions [WHY] Hangs with Z8 can occur if running an older unfixed PMFW version. [HOW] Fallback to RCG only for dynamic IPS2 states if it's not newer than 93.12. Limit to DCN35. Cc: Mario Limonciello Cc: Alex Deucher Cc: stable@vger.kernel.org Reviewed-by: Charlene Liu Signed-off-by: Nicholas Kazlauskas Signed-off-by: Alex Hung Tested-by: Daniel Wheeler --- .../gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c index 97164b5585a84..b46a3afe48ca7 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c @@ -1222,6 +1222,12 @@ void dcn35_clk_mgr_construct( ctx->dc->debug.disable_dpp_power_gate = false; ctx->dc->debug.disable_hubp_power_gate = false; ctx->dc->debug.disable_dsc_power_gate = false; + + /* Disable dynamic IPS2 in older PMFW (93.12) for Z8 interop. */ + if (ctx->dc->config.disable_ips == DMUB_IPS_ENABLE && + ctx->dce_version == DCN_VERSION_3_5 && + ((clk_mgr->base.smu_ver & 0x00FFFFFF) <= 0x005d0c00)) + ctx->dc->config.disable_ips = DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF; } else { /*let's reset the config control flag*/ ctx->dc->config.disable_ips = DMUB_IPS_DISABLE_ALL; /*pmfw not support it, disable it all*/ From 1c658f2a24b78745d5465554686ab4ec3fd3599a Mon Sep 17 00:00:00 2001 From: Martin Tsai Date: Mon, 22 Jul 2024 14:12:25 +0800 Subject: [PATCH 1557/1868] drm/amd/display: Clean up dsc blocks in accelerated mode [WHY] DSC on eDP could be enabled during VBIOS post. The enabled DSC may not be disabled when enter to OS, once the system was in second screen only mode before entering to S4. In this case, OS will not send setTimings to reset eDP path again. The enabled DSC HW will make a new stream without DSC cannot output normally if it reused this pipe with enabled DSC. [HOW] In accelerated mode, to clean up DSC blocks if eDP is on link but not active when we are not in fast boot and seamless boot. Cc: Mario Limonciello Cc: Alex Deucher Cc: stable@vger.kernel.org Reviewed-by: Charlene Liu Signed-off-by: Martin Tsai Signed-off-by: Alex Hung Tested-by: Daniel Wheeler --- .../amd/display/dc/hwss/dce110/dce110_hwseq.c | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c index d52ce58c6a987..aa7479b318982 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c @@ -57,6 +57,7 @@ #include "panel_cntl.h" #include "dc_state_priv.h" #include "dpcd_defs.h" +#include "dsc.h" /* include DCE11 register header files */ #include "dce/dce_11_0_d.h" #include "dce/dce_11_0_sh_mask.h" @@ -1823,6 +1824,48 @@ static void get_edp_links_with_sink( } } +static void clean_up_dsc_blocks(struct dc *dc) +{ + struct display_stream_compressor *dsc = NULL; + struct timing_generator *tg = NULL; + struct stream_encoder *se = NULL; + struct dccg *dccg = dc->res_pool->dccg; + struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl; + int i; + + if (dc->ctx->dce_version != DCN_VERSION_3_5 && + dc->ctx->dce_version != DCN_VERSION_3_51) + return; + + for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) { + struct dcn_dsc_state s = {0}; + + dsc = dc->res_pool->dscs[i]; + dsc->funcs->dsc_read_state(dsc, &s); + if (s.dsc_fw_en) { + /* disable DSC in OPTC */ + if (i < dc->res_pool->timing_generator_count) { + tg = dc->res_pool->timing_generators[i]; + tg->funcs->set_dsc_config(tg, OPTC_DSC_DISABLED, 0, 0); + } + /* disable DSC in stream encoder */ + if (i < dc->res_pool->stream_enc_count) { + se = dc->res_pool->stream_enc[i]; + se->funcs->dp_set_dsc_config(se, OPTC_DSC_DISABLED, 0, 0); + se->funcs->dp_set_dsc_pps_info_packet(se, false, NULL, true); + } + /* disable DSC block */ + if (dccg->funcs->set_ref_dscclk) + dccg->funcs->set_ref_dscclk(dccg, dsc->inst); + dsc->funcs->dsc_disable(dsc); + + /* power down DSC */ + if (pg_cntl != NULL) + pg_cntl->funcs->dsc_pg_control(pg_cntl, dsc->inst, false); + } + } +} + /* * When ASIC goes from VBIOS/VGA mode to driver/accelerated mode we need: * 1. Power down all DC HW blocks @@ -1927,6 +1970,13 @@ void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context) clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr); power_down_all_hw_blocks(dc); + + /* DSC could be enabled on eDP during VBIOS post. + * To clean up dsc blocks if eDP is in link but not active. + */ + if (edp_link_with_sink && (edp_stream_num == 0)) + clean_up_dsc_blocks(dc); + disable_vga_and_power_gate_all_controllers(dc); if (edp_link_with_sink && !keep_edp_vdd_on) dc->hwss.edp_power_control(edp_link_with_sink, false); From 881d5fcef734f95b3b02b42dcbaca30b226305a4 Mon Sep 17 00:00:00 2001 From: Sung Joon Kim Date: Tue, 27 Aug 2024 14:49:44 -0400 Subject: [PATCH 1558/1868] drm/amd/display: Disable SYMCLK32_LE root clock gating [WHY & HOW] On display on sequence, enabling SYMCLK32_LE root clock gating causes issue in link training so disabling it is needed. Cc: Mario Limonciello Cc: Alex Deucher Cc: stable@vger.kernel.org Reviewed-by: Nicholas Kazlauskas Signed-off-by: Sung Joon Kim Signed-off-by: Alex Hung Tested-by: Daniel Wheeler --- .../gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c index 514c6d56925d5..da9101b83e8c1 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c @@ -736,7 +736,7 @@ static const struct dc_debug_options debug_defaults_drv = { .hdmichar = true, .dpstream = true, .symclk32_se = true, - .symclk32_le = true, + .symclk32_le = false, .symclk_fe = true, .physymclk = false, .dpiasymclk = true, From ebf493cdfeacaffa0d2b11f349cd8e620e2a6ada Mon Sep 17 00:00:00 2001 From: Peichen Huang Date: Thu, 22 Aug 2024 14:50:07 +0800 Subject: [PATCH 1559/1868] drm/amd/display: Restructure dpia link training [WHY] We intend to consolidate dp tunneling and conventional dp link training. [HOW] 1. Use the same link training entry for both dp and dpia 2. Move SET_CONFIG of non-transparent mode to dmub side 3. Add set_tps_notification dmub_cmd to notify tps request for non-transparent dpia link training 4. Check dpcd request result and abort link training early if dpia aux tunneling fails 5. Add option to avoid affect old product 6. Separately handle wait_time_microsec for dpia Reviewed-by: Cruise Hung Reviewed-by: George Shen Reviewed-by: Meenakshikumar Somasundaram Signed-off-by: Peichen Huang Signed-off-by: Alex Hung Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/core/dc.c | 21 +++++ drivers/gpu/drm/amd/display/dc/dc.h | 6 +- .../amd/display/dc/link/hwss/link_hwss_dpia.c | 31 ++++++- .../dc/link/protocols/link_dp_training.c | 80 ++++++++++++++++--- .../dc/link/protocols/link_dp_training.h | 16 +++- .../link/protocols/link_dp_training_8b_10b.c | 21 ++--- .../dc/link/protocols/link_dp_training_dpia.c | 64 ++++++++------- .../dc/link/protocols/link_dp_training_dpia.h | 19 +++++ drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 1 + .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 25 +++++- .../gpu/drm/amd/display/dmub/src/dmub_dcn35.c | 1 + 11 files changed, 233 insertions(+), 52 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index cbb1521ba115c..beb46561a2aac 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -5756,6 +5756,27 @@ enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc, return DC_OK; } +/** + * dc_process_dmub_dpia_set_tps_notification - Submits tps notification + * + * @dc: [in] dc structure + * @link_index: [in] link index + * @ts: [in] request tps + * + * Submits set_tps_notification command to dmub via inbox message + */ +void dc_process_dmub_dpia_set_tps_notification(const struct dc *dc, uint32_t link_index, uint8_t tps) +{ + union dmub_rb_cmd cmd = {0}; + + cmd.set_tps_notification.header.type = DMUB_CMD__DPIA; + cmd.set_tps_notification.header.sub_type = DMUB_CMD__DPIA_SET_TPS_NOTIFICATION; + cmd.set_tps_notification.tps_notification.instance = dc->links[link_index]->ddc_hw_inst; + cmd.set_tps_notification.tps_notification.tps = tps; + + dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT); +} + /** * dc_process_dmub_dpia_hpd_int_enable - Submits DPIA DPD interruption * diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 7de04903775ba..f98242ec52420 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -462,6 +462,7 @@ struct dc_config { bool support_edp0_on_dp1; unsigned int enable_fpo_flicker_detection; bool disable_hbr_audio_dp2; + bool consolidated_dpia_dp_lt; }; enum visual_confirm { @@ -762,7 +763,8 @@ union dpia_debug_options { uint32_t disable_mst_dsc_work_around:1; /* bit 3 */ uint32_t enable_force_tbt3_work_around:1; /* bit 4 */ uint32_t disable_usb4_pm_support:1; /* bit 5 */ - uint32_t reserved:26; + uint32_t enable_consolidated_dpia_dp_lt:1; /* bit 6 */ + uint32_t reserved:25; } bits; uint32_t raw; }; @@ -2528,6 +2530,8 @@ enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc, uint8_t mst_alloc_slots, uint8_t *mst_slots_in_use); +void dc_process_dmub_dpia_set_tps_notification(const struct dc *dc, uint32_t link_index, uint8_t tps); + void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc, uint32_t hpd_int_enable); diff --git a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dpia.c b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dpia.c index 46fb3649bc86a..6499807af72a1 100644 --- a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dpia.c +++ b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_dpia.c @@ -50,8 +50,31 @@ static void update_dpia_stream_allocation_table(struct dc_link *link, DC_LOG_MST("dpia : status[%d]: alloc_slots[%d]: used_slots[%d]\n", status, mst_alloc_slots, prev_mst_slots_in_use); - ASSERT(link_enc); - link_enc->funcs->update_mst_stream_allocation_table(link_enc, table); + if (link_enc) + link_enc->funcs->update_mst_stream_allocation_table(link_enc, table); +} + +static void set_dio_dpia_link_test_pattern(struct dc_link *link, + const struct link_resource *link_res, + struct encoder_set_dp_phy_pattern_param *tp_params) +{ + if (tp_params->dp_phy_pattern != DP_TEST_PATTERN_VIDEO_MODE) + return; + + struct link_encoder *link_enc = link_enc_cfg_get_link_enc(link); + + if (!link_enc) + return; + + link_enc->funcs->dp_set_phy_pattern(link_enc, tp_params); + link->dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_SET_SOURCE_PATTERN); +} + +static void set_dio_dpia_lane_settings(struct dc_link *link, + const struct link_resource *link_res, + const struct dc_link_settings *link_settings, + const struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX]) +{ } static const struct link_hwss dpia_link_hwss = { @@ -65,8 +88,8 @@ static const struct link_hwss dpia_link_hwss = { .ext = { .set_throttled_vcp_size = set_dio_throttled_vcp_size, .enable_dp_link_output = enable_dio_dp_link_output, - .set_dp_link_test_pattern = set_dio_dp_link_test_pattern, - .set_dp_lane_settings = set_dio_dp_lane_settings, + .set_dp_link_test_pattern = set_dio_dpia_link_test_pattern, + .set_dp_lane_settings = set_dio_dpia_lane_settings, .update_stream_allocation_table = update_dpia_stream_allocation_table, }, }; diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c index c9de5d5f2c3ca..27a606f73213c 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.c @@ -515,6 +515,41 @@ bool dp_is_interlane_aligned(union lane_align_status_updated align_status) return align_status.bits.INTERLANE_ALIGN_DONE == 1; } +bool dp_check_interlane_aligned(union lane_align_status_updated align_status, + struct dc_link *link, + uint8_t retries) +{ + /* Take into consideration corner case for DP 1.4a LL Compliance CTS as USB4 + * has to share encoders unlike DP and USBC + */ + return (dp_is_interlane_aligned(align_status) || + (link->skip_fallback_on_link_loss && retries)); +} + +uint32_t dp_get_eq_aux_rd_interval( + const struct dc_link *link, + const struct link_training_settings *lt_settings, + uint32_t offset, + uint8_t retries) +{ + if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) { + if (offset == 0 && retries == 1 && lt_settings->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) + return max(lt_settings->eq_pattern_time, (uint32_t) DPIA_CLK_SYNC_DELAY); + else + return dpia_get_eq_aux_rd_interval(link, lt_settings, offset); + } else if (is_repeater(lt_settings, offset)) + return dp_translate_training_aux_read_interval( + link->dpcd_caps.lttpr_caps.aux_rd_interval[offset - 1]); + else + return lt_settings->eq_pattern_time; +} + +bool dp_check_dpcd_reqeust_status(const struct dc_link *link, + enum dc_status status) +{ + return (status != DC_OK && link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA); +} + enum link_training_result dp_check_link_loss_status( struct dc_link *link, const struct link_training_settings *link_training_setting) @@ -974,13 +1009,17 @@ void repeater_training_done(struct dc_link *link, uint32_t offset) dpcd_pattern.v1_4.TRAINING_PATTERN_SET); } -static void dpcd_exit_training_mode(struct dc_link *link, enum dp_link_encoding encoding) +static enum link_training_result dpcd_exit_training_mode(struct dc_link *link, enum dp_link_encoding encoding) { + enum dc_status status; uint8_t sink_status = 0; uint8_t i; /* clear training pattern set */ - dpcd_set_training_pattern(link, DP_TRAINING_PATTERN_VIDEOIDLE); + status = dpcd_set_training_pattern(link, DP_TRAINING_PATTERN_VIDEOIDLE); + + if (dp_check_dpcd_reqeust_status(link, status)) + return LINK_TRAINING_ABORT; if (encoding == DP_128b_132b_ENCODING) { /* poll for intra-hop disable */ @@ -991,6 +1030,8 @@ static void dpcd_exit_training_mode(struct dc_link *link, enum dp_link_encoding fsleep(1000); } } + + return LINK_TRAINING_SUCCESS; } enum dc_status dpcd_configure_channel_coding(struct dc_link *link, @@ -1014,17 +1055,18 @@ enum dc_status dpcd_configure_channel_coding(struct dc_link *link, return status; } -void dpcd_set_training_pattern( +enum dc_status dpcd_set_training_pattern( struct dc_link *link, enum dc_dp_training_pattern training_pattern) { + enum dc_status status; union dpcd_training_pattern dpcd_pattern = {0}; dpcd_pattern.v1_4.TRAINING_PATTERN_SET = dp_training_pattern_to_dpcd_training_pattern( link, training_pattern); - core_link_write_dpcd( + status = core_link_write_dpcd( link, DP_TRAINING_PATTERN_SET, &dpcd_pattern.raw, @@ -1034,6 +1076,8 @@ void dpcd_set_training_pattern( __func__, DP_TRAINING_PATTERN_SET, dpcd_pattern.v1_4.TRAINING_PATTERN_SET); + + return status; } enum dc_status dpcd_set_link_settings( @@ -1186,6 +1230,13 @@ void dpcd_set_lt_pattern_and_lane_settings( dpcd_lt_buffer[DP_TRAINING_PATTERN_SET - DP_TRAINING_PATTERN_SET] = dpcd_pattern.raw; + if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) + dpia_set_tps_notification( + link, + lt_settings, + dpcd_pattern.v1_4.TRAINING_PATTERN_SET, + offset); + if (is_repeater(lt_settings, offset)) { DC_LOG_HW_LINK_TRAINING("%s\n LTTPR Repeater ID: %d\n 0x%X pattern = %x\n", __func__, @@ -1456,7 +1507,8 @@ static enum link_training_result dp_transition_to_video_idle( */ if (link->connector_signal != SIGNAL_TYPE_EDP && status == LINK_TRAINING_SUCCESS) { msleep(5); - status = dp_check_link_loss_status(link, lt_settings); + if (!link->skip_fallback_on_link_loss) + status = dp_check_link_loss_status(link, lt_settings); } return status; } @@ -1522,7 +1574,9 @@ enum link_training_result dp_perform_link_training( ASSERT(0); /* exit training mode */ - dpcd_exit_training_mode(link, encoding); + if ((dpcd_exit_training_mode(link, encoding) != LINK_TRAINING_SUCCESS || status == LINK_TRAINING_ABORT) && + link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) + dpia_training_abort(link, <_settings, 0); /* switch to video idle */ if ((status == LINK_TRAINING_SUCCESS) || !skip_video_pattern) @@ -1600,8 +1654,7 @@ bool perform_link_training_with_retries( dp_perform_link_training_skip_aux(link, &pipe_ctx->link_res, &cur_link_settings); return true; } else { - /** @todo Consolidate USB4 DP and DPx.x training. */ - if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) { + if (!link->dc->config.consolidated_dpia_dp_lt && link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA) { status = dpia_perform_link_training( link, &pipe_ctx->link_res, @@ -1630,8 +1683,17 @@ bool perform_link_training_with_retries( dp_trace_lt_total_count_increment(link, false); dp_trace_lt_result_update(link, status, false); dp_trace_set_lt_end_timestamp(link, false); - if (status == LINK_TRAINING_SUCCESS && !is_link_bw_low) + if (status == LINK_TRAINING_SUCCESS && !is_link_bw_low) { + // Update verified link settings to current one + // Because DPIA LT might fallback to lower link setting. + if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && + stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) { + link->verified_link_cap.link_rate = link->cur_link_settings.link_rate; + link->verified_link_cap.lane_count = link->cur_link_settings.lane_count; + dm_helpers_dp_mst_update_branch_bandwidth(link->ctx, link); + } return true; + } } fail_count++; diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.h b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.h index 851bd17317a0c..0b18aa35c33cb 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.h +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training.h @@ -55,7 +55,7 @@ void dp_set_hw_test_pattern( uint8_t *custom_pattern, uint32_t custom_pattern_size); -void dpcd_set_training_pattern( +enum dc_status dpcd_set_training_pattern( struct dc_link *link, enum dc_dp_training_pattern training_pattern); @@ -182,4 +182,18 @@ uint32_t dp_translate_training_aux_read_interval( uint8_t dp_get_nibble_at_index(const uint8_t *buf, uint32_t index); + +bool dp_check_interlane_aligned(union lane_align_status_updated align_status, + struct dc_link *link, + uint8_t retries); + +uint32_t dp_get_eq_aux_rd_interval( + const struct dc_link *link, + const struct link_training_settings *lt_settings, + uint32_t offset, + uint8_t retries); + +bool dp_check_dpcd_reqeust_status(const struct dc_link *link, + enum dc_status status); + #endif /* __DC_LINK_DP_TRAINING_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c index 2b4c15b0b4070..3bdce32a85e3c 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c @@ -157,6 +157,7 @@ enum link_training_result perform_8b_10b_clock_recovery_sequence( struct link_training_settings *lt_settings, uint32_t offset) { + enum dc_status status; uint32_t retries_cr; uint32_t retry_count; uint32_t wait_time_microsec; @@ -216,7 +217,7 @@ enum link_training_result perform_8b_10b_clock_recovery_sequence( /* 4. Read lane status and requested drive * settings as set by the sink */ - dp_get_lane_status_and_lane_adjust( + status = dp_get_lane_status_and_lane_adjust( link, lt_settings, dpcd_lane_status, @@ -224,6 +225,9 @@ enum link_training_result perform_8b_10b_clock_recovery_sequence( dpcd_lane_adjust, offset); + if (dp_check_dpcd_reqeust_status(link, status)) + return LINK_TRAINING_ABORT; + /* 5. check CR done*/ if (dp_is_cr_done(lane_count, dpcd_lane_status)) { DC_LOG_HW_LINK_TRAINING("%s: Clock recovery OK\n", __func__); @@ -273,6 +277,7 @@ enum link_training_result perform_8b_10b_channel_equalization_sequence( struct link_training_settings *lt_settings, uint32_t offset) { + enum dc_status status; enum dc_dp_training_pattern tr_pattern; uint32_t retries_ch_eq; uint32_t wait_time_microsec; @@ -308,12 +313,7 @@ enum link_training_result perform_8b_10b_channel_equalization_sequence( dpcd_set_lane_settings(link, lt_settings, offset); /* 3. wait for receiver to lock-on*/ - wait_time_microsec = lt_settings->eq_pattern_time; - - if (is_repeater(lt_settings, offset)) - wait_time_microsec = - dp_translate_training_aux_read_interval( - link->dpcd_caps.lttpr_caps.aux_rd_interval[offset - 1]); + wait_time_microsec = dp_get_eq_aux_rd_interval(link, lt_settings, offset, retries_ch_eq); dp_wait_for_training_aux_rd_interval( link, @@ -322,7 +322,7 @@ enum link_training_result perform_8b_10b_channel_equalization_sequence( /* 4. Read lane status and requested * drive settings as set by the sink*/ - dp_get_lane_status_and_lane_adjust( + status = dp_get_lane_status_and_lane_adjust( link, lt_settings, dpcd_lane_status, @@ -330,6 +330,9 @@ enum link_training_result perform_8b_10b_channel_equalization_sequence( dpcd_lane_adjust, offset); + if (dp_check_dpcd_reqeust_status(link, status)) + return LINK_TRAINING_ABORT; + /* 5. check CR done*/ if (!dp_is_cr_done(lane_count, dpcd_lane_status)) return dpcd_lane_status[0].bits.CR_DONE_0 ? @@ -339,7 +342,7 @@ enum link_training_result perform_8b_10b_channel_equalization_sequence( /* 6. check CHEQ done*/ if (dp_is_ch_eq_done(lane_count, dpcd_lane_status) && dp_is_symbol_locked(lane_count, dpcd_lane_status) && - dp_is_interlane_aligned(dpcd_lane_status_updated)) + dp_check_interlane_aligned(dpcd_lane_status_updated, link, retries_ch_eq)) return LINK_TRAINING_SUCCESS; /* 7. update VS/PE/PC2 in lt_settings*/ diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c index cd1975c03f38d..39e4b7dc9588f 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.c @@ -43,9 +43,6 @@ #define DC_LOGGER \ link->ctx->logger -/* The approximate time (us) it takes to transmit 9 USB4 DP clock sync packets. */ -#define DPIA_CLK_SYNC_DELAY 16000 - /* Extend interval between training status checks for manual testing. */ #define DPIA_DEBUG_EXTENDED_AUX_RD_INTERVAL_US 60000000 @@ -566,28 +563,6 @@ static enum link_training_result dpia_training_cr_phase( return result; } -/* Return status read interval during equalization phase. */ -static uint32_t dpia_get_eq_aux_rd_interval( - const struct dc_link *link, - const struct link_training_settings *lt_settings, - uint32_t hop) -{ - uint32_t wait_time_microsec; - - if (hop == DPRX) - wait_time_microsec = lt_settings->eq_pattern_time; - else - wait_time_microsec = - dp_translate_training_aux_read_interval( - link->dpcd_caps.lttpr_caps.aux_rd_interval[hop - 1]); - - /* Check debug option for extending aux read interval. */ - if (link->dc->debug.dpia_debug.bits.extend_aux_rd_interval) - wait_time_microsec = DPIA_DEBUG_EXTENDED_AUX_RD_INTERVAL_US; - - return wait_time_microsec; -} - /* Execute equalization phase of link training for specified hop in display * path in non-transparent mode: * - driver issues both DPCD and SET_CONFIG transactions. @@ -936,6 +911,22 @@ static enum link_training_result dpia_training_end( return result; } +/* Return status read interval during equalization phase. */ +uint32_t dpia_get_eq_aux_rd_interval( + const struct dc_link *link, + const struct link_training_settings *lt_settings, + uint32_t hop) +{ + /* Check debug option for extending aux read interval. */ + if (link->dc->debug.dpia_debug.bits.extend_aux_rd_interval) + return DPIA_DEBUG_EXTENDED_AUX_RD_INTERVAL_US; + else if (hop == DPRX) + return lt_settings->eq_pattern_time; + else + return dp_translate_training_aux_read_interval( + link->dpcd_caps.lttpr_caps.aux_rd_interval[hop - 1]); +} + /* When aborting training of specified hop in display path, clean up by: * - Attempting to clear DPCD TRAINING_PATTERN_SET, LINK_BW_SET and LANE_COUNT_SET. * - Sending SET_CONFIG(SET_LINK) with lane count and link rate set to 0. @@ -943,7 +934,7 @@ static enum link_training_result dpia_training_end( * @param link DPIA link being trained. * @param hop Hop in display path. DPRX = 0. */ -static void dpia_training_abort( +void dpia_training_abort( struct dc_link *link, struct link_training_settings *lt_settings, uint32_t hop) @@ -968,7 +959,26 @@ static void dpia_training_abort( core_link_write_dpcd(link, dpcd_tps_offset, &data, 1); core_link_write_dpcd(link, DP_LINK_BW_SET, &data, 1); core_link_write_dpcd(link, DP_LANE_COUNT_SET, &data, 1); - core_link_send_set_config(link, DPIA_SET_CFG_SET_LINK, data); + + if (!link->dc->config.consolidated_dpia_dp_lt) + core_link_send_set_config(link, DPIA_SET_CFG_SET_LINK, data); +} + +void dpia_set_tps_notification( + struct dc_link *link, + const struct link_training_settings *lt_settings, + uint8_t pattern, + uint32_t hop) +{ + uint8_t repeater_cnt = 0; /* Number of hops/repeaters in display path. */ + + if (lt_settings->lttpr_mode != LTTPR_MODE_NON_TRANSPARENT || pattern == DPCD_TRAINING_PATTERN_VIDEOIDLE) + return; + + repeater_cnt = dp_parse_lttpr_repeater_count(link->dpcd_caps.lttpr_caps.phy_repeater_cnt); + + if (hop != repeater_cnt) + dc_process_dmub_dpia_set_tps_notification(link->ctx->dc, link->link_index, pattern); } enum link_training_result dpia_perform_link_training( diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.h b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.h index b39fb9faf1c2c..9f4eceb494c2d 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.h +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_dpia.h @@ -28,6 +28,9 @@ #define __DC_LINK_DP_TRAINING_DPIA_H__ #include "link_dp_training.h" +/* The approximate time (us) it takes to transmit 9 USB4 DP clock sync packets. */ +#define DPIA_CLK_SYNC_DELAY 16000 + /* Train DP tunneling link for USB4 DPIA display endpoint. * DPIA equivalent of dc_link_dp_perfrorm_link_training. * Aborts link training upon detection of sink unplug. @@ -38,4 +41,20 @@ enum link_training_result dpia_perform_link_training( const struct dc_link_settings *link_setting, bool skip_video_pattern); +void dpia_training_abort( + struct dc_link *link, + struct link_training_settings *lt_settings, + uint32_t hop); + +uint32_t dpia_get_eq_aux_rd_interval( + const struct dc_link *link, + const struct link_training_settings *lt_settings, + uint32_t hop); + +void dpia_set_tps_notification( + struct dc_link *link, + const struct link_training_settings *lt_settings, + uint8_t pattern, + uint32_t offset); + #endif /* __DC_LINK_DP_TRAINING_DPIA_H__ */ diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h index cd70453aeae05..fe5b6f7a3eb1e 100644 --- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h +++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h @@ -300,6 +300,7 @@ struct dmub_srv_hw_params { enum dmub_ips_disable_type disable_ips; bool disallow_phy_access; bool disable_sldo_opt; + bool enable_non_transparent_setconfig; }; /** diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index e20c220aa8b4c..ebcf68bfae2b3 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -682,7 +682,7 @@ union dmub_fw_boot_options { uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/ uint32_t usb4_cm_version: 1; /**< 1 CM support */ uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */ - uint32_t reserved0: 1; + uint32_t enable_non_transparent_setconfig: 1; /* 1 if dpia use conventional dp lt flow*/ uint32_t disable_clk_ds: 1; /* 1 if disallow dispclk_ds and dppclk_ds*/ uint32_t disable_timeout_recovery : 1; /* 1 if timeout recovery should be disabled */ uint32_t ips_pg_disable: 1; /* 1 to disable ONO domains power gating*/ @@ -1308,6 +1308,7 @@ enum dmub_cmd_dpia_type { DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0, DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2, + DMUB_CMD__DPIA_SET_TPS_NOTIFICATION = 3, }; /* DMUB_OUT_CMD__DPIA_NOTIFICATION command types. */ @@ -2138,6 +2139,24 @@ struct dmub_rb_cmd_set_mst_alloc_slots { struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */ }; +/** + * Data passed from driver to FW in a DMUB_CMD__SET_TPS_NOTIFICATION command. + */ +struct dmub_cmd_tps_notification_data { + uint8_t instance; /* DPIA instance */ + uint8_t tps; /* requested training pattern */ + uint8_t reserved1; + uint8_t reserved2; +}; + +/** + * DMUB command structure for SET_TPS_NOTIFICATION command. + */ +struct dmub_rb_cmd_set_tps_notification { + struct dmub_cmd_header header; /* header */ + struct dmub_cmd_tps_notification_data tps_notification; /* set tps_notification data */ +}; + /** * DMUB command structure for DPIA HPD int enable control. */ @@ -5304,6 +5323,10 @@ union dmub_rb_cmd { * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. */ struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots; + /** + * Definition of a DMUB_CMD__DPIA_SET_TPS_NOTIFICATION command. + */ + struct dmub_rb_cmd_set_tps_notification set_tps_notification; /** * Definition of a DMUB_CMD__EDID_CEA command. */ diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c index 746696b6f09a8..2ccad79053c58 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c @@ -425,6 +425,7 @@ void dmub_dcn35_enable_dmub_boot_options(struct dmub_srv *dmub, const struct dmu boot_options.bits.ips_disable = params->disable_ips; boot_options.bits.ips_sequential_ono = params->ips_sequential_ono; boot_options.bits.disable_sldo_opt = params->disable_sldo_opt; + boot_options.bits.enable_non_transparent_setconfig = params->enable_non_transparent_setconfig; REG_WRITE(DMCUB_SCRATCH14, boot_options.all); } From 1a05a8259c4fc76beea29416c10afc1f0bc16ad9 Mon Sep 17 00:00:00 2001 From: Relja Vojvodic Date: Wed, 28 Aug 2024 11:42:26 -0400 Subject: [PATCH 1560/1868] drm/amd/display: Add fullscreen only sharpening policy [WHAT & HOW] Disable sharpening if not in fullscreen if this policy is selected Reviewed-by: Samson Tam Signed-off-by: Relja Vojvodic Signed-off-by: Alex Hung Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/spl/dc_spl.c | 3 +++ drivers/gpu/drm/amd/display/dc/spl/dc_spl_types.h | 3 ++- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c b/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c index f7a654b3a092f..014e8a296f0c7 100644 --- a/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c +++ b/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c @@ -853,6 +853,9 @@ static bool spl_get_isharp_en(struct spl_in *spl_in, else if ((spl_is_yuv420(spl_in->basic_in.format) && !fullscreen) && (spl_in->debug.sharpen_policy == SHARPEN_RGB_FULLSCREEN_YUV)) return enable_isharp; + else if (!spl_in->is_fullscreen && + spl_in->debug.sharpen_policy == SHARPEN_FULLSCREEN_ALL) + return enable_isharp; /* * Apply sharpness if supports horizontal taps 4,6 AND diff --git a/drivers/gpu/drm/amd/display/dc/spl/dc_spl_types.h b/drivers/gpu/drm/amd/display/dc/spl/dc_spl_types.h index 425d4a282c7a7..2a74ff5fdfdbc 100644 --- a/drivers/gpu/drm/amd/display/dc/spl/dc_spl_types.h +++ b/drivers/gpu/drm/amd/display/dc/spl/dc_spl_types.h @@ -490,7 +490,8 @@ enum linear_light_scaling { // convert it in translation logic enum sharpen_policy { SHARPEN_ALWAYS = 0, SHARPEN_YUV = 1, - SHARPEN_RGB_FULLSCREEN_YUV = 2 + SHARPEN_RGB_FULLSCREEN_YUV = 2, + SHARPEN_FULLSCREEN_ALL = 3 }; enum scale_to_sharpness_policy { NO_SCALE_TO_SHARPNESS_ADJ = 0, From 48aaf9ea8b19bad7f1fadee9e87152758e1a5909 Mon Sep 17 00:00:00 2001 From: Leo Ma Date: Mon, 19 Aug 2024 13:25:27 -0400 Subject: [PATCH 1561/1868] drm/amd/display: Add HDMI DSC native YCbCr422 support [WHY && HOW] For some HDMI OVT timing, YCbCr422 encoding fails at the DSC bandwidth check. The root cause is our DSC policy for timing doesn't account for HDMI YCbCr422 native support. Cc: Mario Limonciello Cc: Alex Deucher Cc: stable@vger.kernel.org Reviewed-by: Chris Park Signed-off-by: Leo Ma Signed-off-by: Alex Hung Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 4 ++-- drivers/gpu/drm/amd/display/dc/dc_dsc.h | 3 ++- drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c | 5 +++-- 3 files changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 43eb0b66bb41f..89abb820f32ff 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -1369,7 +1369,7 @@ static int compute_mst_dsc_configs_for_link(struct drm_atomic_state *state, params[count].num_slices_v = aconnector->dsc_settings.dsc_num_slices_v; params[count].bpp_overwrite = aconnector->dsc_settings.dsc_bits_per_pixel; params[count].compression_possible = stream->sink->dsc_caps.dsc_dec_caps.is_dsc_supported; - dc_dsc_get_policy_for_timing(params[count].timing, 0, &dsc_policy); + dc_dsc_get_policy_for_timing(params[count].timing, 0, &dsc_policy, dc_link_get_highest_encoding_format(stream->link)); if (!dc_dsc_compute_bandwidth_range( stream->sink->ctx->dc->res_pool->dscs[0], stream->sink->ctx->dc->debug.dsc_min_slice_height_override, @@ -1916,7 +1916,7 @@ static bool is_dsc_common_config_possible(struct dc_stream_state *stream, { struct dc_dsc_policy dsc_policy = {0}; - dc_dsc_get_policy_for_timing(&stream->timing, 0, &dsc_policy); + dc_dsc_get_policy_for_timing(&stream->timing, 0, &dsc_policy, dc_link_get_highest_encoding_format(stream->link)); dc_dsc_compute_bandwidth_range(stream->sink->ctx->dc->res_pool->dscs[0], stream->sink->ctx->dc->debug.dsc_min_slice_height_override, dsc_policy.min_target_bpp * 16, diff --git a/drivers/gpu/drm/amd/display/dc/dc_dsc.h b/drivers/gpu/drm/amd/display/dc/dc_dsc.h index 2a5120ecf48be..9014c24098178 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dsc.h +++ b/drivers/gpu/drm/amd/display/dc/dc_dsc.h @@ -101,7 +101,8 @@ uint32_t dc_dsc_stream_bandwidth_overhead_in_kbps( */ void dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing, uint32_t max_target_bpp_limit_override_x16, - struct dc_dsc_policy *policy); + struct dc_dsc_policy *policy, + const enum dc_link_encoding_format link_encoding); void dc_dsc_policy_set_max_target_bpp_limit(uint32_t limit); diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c index 79c426425911f..ebd5df1a36e8b 100644 --- a/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c +++ b/drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c @@ -883,7 +883,7 @@ static bool setup_dsc_config( memset(dsc_cfg, 0, sizeof(struct dc_dsc_config)); - dc_dsc_get_policy_for_timing(timing, options->max_target_bpp_limit_override_x16, &policy); + dc_dsc_get_policy_for_timing(timing, options->max_target_bpp_limit_override_x16, &policy, link_encoding); pic_width = timing->h_addressable + timing->h_border_left + timing->h_border_right; pic_height = timing->v_addressable + timing->v_border_top + timing->v_border_bottom; @@ -1173,7 +1173,8 @@ uint32_t dc_dsc_stream_bandwidth_overhead_in_kbps( void dc_dsc_get_policy_for_timing(const struct dc_crtc_timing *timing, uint32_t max_target_bpp_limit_override_x16, - struct dc_dsc_policy *policy) + struct dc_dsc_policy *policy, + const enum dc_link_encoding_format link_encoding) { uint32_t bpc = 0; From faf63e20a46e00eef431c40d7ff503b66ac77eb6 Mon Sep 17 00:00:00 2001 From: Aric Cyr Date: Tue, 3 Sep 2024 08:45:48 -0400 Subject: [PATCH 1562/1868] drm/amd/display: 3.2.300 - Add HDMI DSC native YCbCr422 support - Add fullscreen only sharpening policy - Restructure dpia link training - Disable SYMCLK32_LE root clock gating - Clean up dsc blocks in accelerated mode - Block dynamic IPS2 on DCN35 for incompatible FW versions - Add debug options to change sharpen policies - Block timing sync for different output formats in pmo - Enable DML2 override_det_buffer_size_kbytes - Add dmub hpd sense callback - Emulate Display Hotplug Hang - Implement new DPCD register handling - Use SDR white level to calculate matrix coefficients - Round calculated vtotal Reviewed-by: Alex Hung Signed-off-by: Aric Cyr Signed-off-by: Alex Hung Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index f98242ec52420..05cd15ccb7828 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -55,7 +55,7 @@ struct aux_payload; struct set_config_cmd_payload; struct dmub_notification; -#define DC_VER "3.2.299" +#define DC_VER "3.2.300" #define MAX_SURFACES 3 #define MAX_PLANES 6 From 05b78c7a3a173ede25c433dd16477cfe7382315a Mon Sep 17 00:00:00 2001 From: Alex Hung Date: Thu, 29 Aug 2024 17:30:26 -0600 Subject: [PATCH 1563/1868] drm/amd/display: Check null pointer before dereferencing se [WHAT & HOW] se is null checked previously in the same function, indicating it might be null; therefore, it must be checked when used again. This fixes 1 FORWARD_NULL issue reported by Coverity. Acked-by: Alex Hung Reviewed-by: Rodrigo Siqueira Signed-off-by: Alex Hung Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index beb46561a2aac..774a0685b11a9 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1767,7 +1767,7 @@ bool dc_validate_boot_timing(const struct dc *dc, if (crtc_timing->pix_clk_100hz != pix_clk_100hz) return false; - if (!se->funcs->dp_get_pixel_format) + if (!se || !se->funcs->dp_get_pixel_format) return false; if (!se->funcs->dp_get_pixel_format( From 552d02ed662e1185e1d95fa5eb7d24f4441b38bf Mon Sep 17 00:00:00 2001 From: Alex Hung Date: Thu, 29 Aug 2024 16:35:51 -0600 Subject: [PATCH 1564/1868] drm/amd/display: Remove always-false branches [WHAT & HOW] req128_c is always set to false and its branch is never taken. Similarly, MacroTileSizeBytes is set to either 256 or 65535 and it is never 4096 and it's branch is not taken. Therefore, their branches are removed. This fixes 3 DEADCODE issues reported by Coverity. Acked-by: Alex Hung Reviewed-by: Alvin Lee Reviewed-by: Rodrigo Siqueira Signed-off-by: Alex Hung Tested-by: Daniel Wheeler --- .../amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c | 3 --- .../amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c | 3 --- .../drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c | 9 --------- 3 files changed, 15 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c index e7019c95ba79e..4fce64a030b60 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c @@ -313,9 +313,6 @@ static void handle_det_buf_split(struct display_mode_lib *mode_lib, if (swath_height_c > 0) log2_swath_height_c = dml_log2(swath_height_c); - - if (req128_c && log2_swath_height_c > 0) - log2_swath_height_c -= 1; } rq_param->dlg.rq_l.swath_height = 1 << log2_swath_height_l; diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c index ae52510417280..3fa9a5da02f6a 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c @@ -313,9 +313,6 @@ static void handle_det_buf_split(struct display_mode_lib *mode_lib, if (swath_height_c > 0) log2_swath_height_c = dml_log2(swath_height_c); - - if (req128_c && log2_swath_height_c > 0) - log2_swath_height_c -= 1; } rq_param->dlg.rq_l.swath_height = 1 << log2_swath_height_l; diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c index 0b132ce1d2cdc..2b275e6803797 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c @@ -1924,15 +1924,6 @@ static unsigned int CalculateVMAndRowBytes( *PixelPTEReqWidth = 32768.0 / BytePerPixel; *PTERequestSize = 64; FractionOfPTEReturnDrop = 0; - } else if (MacroTileSizeBytes == 4096) { - PixelPTEReqHeightPTEs = 1; - *PixelPTEReqHeight = MacroTileHeight; - *PixelPTEReqWidth = 8 * *MacroTileWidth; - *PTERequestSize = 64; - if (ScanDirection != dm_vert) - FractionOfPTEReturnDrop = 0; - else - FractionOfPTEReturnDrop = 7.0 / 8; } else if (GPUVMMinPageSize == 4 && MacroTileSizeBytes > 4096) { PixelPTEReqHeightPTEs = 16; *PixelPTEReqHeight = 16 * BlockHeight256Bytes; From fdf26e0a2ff8f64def4d450b93d2362675ee115c Mon Sep 17 00:00:00 2001 From: Aurabindo Pillai Date: Tue, 3 Sep 2024 10:10:44 -0400 Subject: [PATCH 1565/1868] drm/amd/display: Fix underflow when setting underscan on DCN401 [WHY & HOW] When underscan is set through xrandr, it causes the stream destination rect to change in a way it becomes complicated to handle the calculations for subvp. Since this is a corner case, disable subvp when underscan is set. Fix the existing check that is supposed to catch this corner case by adding a check based on the parameters in the stream Cc: Mario Limonciello Cc: Alex Deucher Cc: stable@vger.kernel.org Reviewed-by: Dillon Varone Reviewed-by: Rodrigo Siqueira Signed-off-by: Aurabindo Pillai Signed-off-by: Alex Hung Tested-by: Daniel Wheeler --- .../drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c index b0d9aed0f2657..8697eac1e1f7e 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c @@ -858,7 +858,9 @@ static void populate_dml21_plane_config_from_plane_state(struct dml2_context *dm plane->immediate_flip = plane_state->flip_immediate; - plane->composition.rect_out_height_spans_vactive = plane_state->dst_rect.height >= stream->timing.v_addressable; + plane->composition.rect_out_height_spans_vactive = + plane_state->dst_rect.height >= stream->timing.v_addressable && + stream->dst.height >= stream->timing.v_addressable; } //TODO : Could be possibly moved to a common helper layer. From bad091aa16fa9d116c2c56108ab94bbe5f45c196 Mon Sep 17 00:00:00 2001 From: Zhikai Zhai Date: Tue, 27 Aug 2024 14:06:01 +0800 Subject: [PATCH 1566/1868] drm/amd/display: Skip to enable dsc if it has been off [WHY] It makes DSC enable when we commit the stream which need keep power off, and then it will skip to disable DSC if pipe reset at this situation as power has been off. It may cause the DSC unexpected enable on the pipe with the next new stream which doesn't support DSC. [HOW] Check the DSC used on current pipe status when update stream. Skip to enable if it has been off. The operation enable DSC should happen when set power on. Cc: Mario Limonciello Cc: Alex Deucher Cc: stable@vger.kernel.org Reviewed-by: Wenjing Liu Signed-off-by: Zhikai Zhai Signed-off-by: Alex Hung Tested-by: Daniel Wheeler --- .../drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c | 14 ++++++++++++++ .../drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c | 13 +++++++++++++ 2 files changed, 27 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c index 4a23eca625f5d..7ee6e53a98afa 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c @@ -1031,6 +1031,20 @@ void dcn32_update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) struct dsc_config dsc_cfg; struct dsc_optc_config dsc_optc_cfg = {0}; enum optc_dsc_mode optc_dsc_mode; + struct dcn_dsc_state dsc_state = {0}; + + if (!dsc) { + DC_LOG_DSC("DSC is NULL for tg instance %d:", pipe_ctx->stream_res.tg->inst); + return; + } + + if (dsc->funcs->dsc_read_state) { + dsc->funcs->dsc_read_state(dsc, &dsc_state); + if (!dsc_state.dsc_fw_en) { + DC_LOG_DSC("DSC has been disabled for tg instance %d:", pipe_ctx->stream_res.tg->inst); + return; + } + } /* Enable DSC hw block */ dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt; diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c index 479fd3e89e5ab..bd309dbdf7b2a 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c @@ -334,7 +334,20 @@ static void update_dsc_on_stream(struct pipe_ctx *pipe_ctx, bool enable) struct dsc_config dsc_cfg; struct dsc_optc_config dsc_optc_cfg = {0}; enum optc_dsc_mode optc_dsc_mode; + struct dcn_dsc_state dsc_state = {0}; + if (!dsc) { + DC_LOG_DSC("DSC is NULL for tg instance %d:", pipe_ctx->stream_res.tg->inst); + return; + } + + if (dsc->funcs->dsc_read_state) { + dsc->funcs->dsc_read_state(dsc, &dsc_state); + if (!dsc_state.dsc_fw_en) { + DC_LOG_DSC("DSC has been disabled for tg instance %d:", pipe_ctx->stream_res.tg->inst); + return; + } + } /* Enable DSC hw block */ dsc_cfg.pic_width = (stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right) / opp_cnt; dsc_cfg.pic_height = stream->timing.v_addressable + stream->timing.v_border_top + stream->timing.v_border_bottom; From 50d795d4313b52507bf21e6ac6f99d57cd7efc0a Mon Sep 17 00:00:00 2001 From: Charlene Liu Date: Wed, 4 Sep 2024 15:58:25 -0400 Subject: [PATCH 1567/1868] drm/amd/display: Use full update for swizzle mode change [WHY & HOW] 1) We did linear/non linear transition properly long ago 2) We used that path to handle SystemDisplayEnable 3) We fixed a SystemDisplayEnable inability to fallback to passive by impacting the transition flow generically 4) AFMF later relied on the generic transition behavior Separating the two flows to make (3) non-generic is the best immediate coarse of action. DC can discern SSAMPO3 very easily from SDE. Cc: Mario Limonciello Cc: Alex Deucher Cc: stable@vger.kernel.org Reviewed-by: Chris Park Signed-off-by: Charlene Liu Signed-off-by: Alex Hung Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/core/dc.c | 6 +++--- drivers/gpu/drm/amd/display/dc/dc.h | 1 + 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 774a0685b11a9..77abeb8628cc2 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -2376,7 +2376,7 @@ static bool is_surface_in_context( return false; } -static enum surface_update_type get_plane_info_update_type(const struct dc_surface_update *u) +static enum surface_update_type get_plane_info_update_type(const struct dc *dc, const struct dc_surface_update *u) { union surface_update_flags *update_flags = &u->surface->update_flags; enum surface_update_type update_type = UPDATE_TYPE_FAST; @@ -2455,7 +2455,7 @@ static enum surface_update_type get_plane_info_update_type(const struct dc_surfa /* todo: below are HW dependent, we should add a hook to * DCE/N resource and validated there. */ - if (u->plane_info->tiling_info.gfx9.swizzle != DC_SW_LINEAR) { + if (!dc->debug.skip_full_updated_if_possible) { /* swizzled mode requires RQ to be setup properly, * thus need to run DML to calculate RQ settings */ @@ -2547,7 +2547,7 @@ static enum surface_update_type det_surface_update(const struct dc *dc, update_flags->raw = 0; // Reset all flags - type = get_plane_info_update_type(u); + type = get_plane_info_update_type(dc, u); elevate_update_type(&overall_type, type); type = get_scaling_info_update_type(dc, u); diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 05cd15ccb7828..65425a7b33242 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -1063,6 +1063,7 @@ struct dc_debug_options { bool enable_ips_visual_confirm; unsigned int sharpen_policy; unsigned int scale_to_sharpness_policy; + bool skip_full_updated_if_possible; }; From f0e8d7f2fb8e97ecc4aa5a1e49a00c15dfd473e2 Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Fri, 13 Sep 2024 13:00:39 -0500 Subject: [PATCH 1568/1868] drm/amd/display: Validate backlight caps are sane Currently amdgpu takes backlight caps provided by the ACPI tables on systems as is. If the firmware sets maximums that are too low this means that users don't get a good experience. To avoid having to maintain a quirk list of such systems, do a sanity check on the values. Check that the spread is at least half of the values that amdgpu would use if no ACPI table was found and if not use the amdgpu defaults. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3020 Reviewed-by: Harry Wentland Signed-off-by: Mario Limonciello --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 3a78a2f1b5448..78172e62d9c18 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4517,6 +4517,7 @@ static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev) #define AMDGPU_DM_DEFAULT_MIN_BACKLIGHT 12 #define AMDGPU_DM_DEFAULT_MAX_BACKLIGHT 255 +#define AMDGPU_DM_MIN_SPREAD ((AMDGPU_DM_DEFAULT_MAX_BACKLIGHT - AMDGPU_DM_DEFAULT_MIN_BACKLIGHT) / 2) #ifdef HAVE_HDR_SINK_METADATA #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50 #endif @@ -4533,6 +4534,21 @@ static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm, return; amdgpu_acpi_get_backlight_caps(&caps); + + /* validate the firmware value is sane */ + if (caps.caps_valid) { + int spread = caps.max_input_signal - caps.min_input_signal; + + if (caps.max_input_signal > AMDGPU_DM_DEFAULT_MAX_BACKLIGHT || + caps.min_input_signal < AMDGPU_DM_DEFAULT_MIN_BACKLIGHT || + spread > AMDGPU_DM_DEFAULT_MAX_BACKLIGHT || + spread < AMDGPU_DM_MIN_SPREAD) { + DRM_DEBUG_KMS("DM: Invalid backlight caps: min=%d, max=%d\n", + caps.min_input_signal, caps.max_input_signal); + caps.caps_valid = false; + } + } + if (caps.caps_valid) { dm->backlight_caps[bl_idx].caps_valid = true; #ifdef HAVE_HDR_SINK_METADATA From 96e1a0a34e4c05f55ee26a5209764629c649b65c Mon Sep 17 00:00:00 2001 From: Roman Li Date: Thu, 5 Sep 2024 14:22:30 -0400 Subject: [PATCH 1569/1868] drm/amd/display: Update IPS default mode for DCN35/DCN351 [WHY] RCG state of IPX in idle is more stable for DCN351 and some variants of DCN35 than IPS2. [HOW] Rework dm_get_default_ips_mode() to specify default per ASIC and update DCN35/DCN351 defaults accordingly. Cc: Mario Limonciello Cc: Alex Deucher Cc: stable@vger.kernel.org Reviewed-by: Sun peng Li Signed-off-by: Roman Li Signed-off-by: Alex Hung Tested-by: Daniel Wheeler --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 50 ++++++++++++------- 1 file changed, 33 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 78172e62d9c18..9e0e42c5e507b 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1783,25 +1783,41 @@ static struct dml2_soc_bb *dm_dmub_get_vbios_bounding_box(struct amdgpu_device * static enum dmub_ips_disable_type dm_get_default_ips_mode( struct amdgpu_device *adev) { - /* - * On DCN35 systems with Z8 enabled, it's possible for IPS2 + Z8 to - * cause a hard hang. A fix exists for newer PMFW. - * - * As a workaround, for non-fixed PMFW, force IPS1+RCG as the deepest - * IPS state in all cases, except for s0ix and all displays off (DPMS), - * where IPS2 is allowed. - * - * When checking pmfw version, use the major and minor only. - */ - if (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(3, 5, 0) && - (adev->pm.fw_version & 0x00FFFF00) < 0x005D6300) - return DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF; + enum dmub_ips_disable_type ret = DMUB_IPS_ENABLE; - if (amdgpu_ip_version(adev, DCE_HWIP, 0) >= IP_VERSION(3, 5, 0)) - return DMUB_IPS_ENABLE; + switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) { + case IP_VERSION(3, 5, 0): + /* + * On DCN35 systems with Z8 enabled, it's possible for IPS2 + Z8 to + * cause a hard hang. A fix exists for newer PMFW. + * + * As a workaround, for non-fixed PMFW, force IPS1+RCG as the deepest + * IPS state in all cases, except for s0ix and all displays off (DPMS), + * where IPS2 is allowed. + * + * When checking pmfw version, use the major and minor only. + */ + if ((adev->pm.fw_version & 0x00FFFF00) < 0x005D6300) + ret = DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF; + else if (amdgpu_ip_version(adev, GC_HWIP, 0) > IP_VERSION(11, 5, 0)) + /* + * Other ASICs with DCN35 that have residency issues with + * IPS2 in idle. + * We want them to use IPS2 only in display off cases. + */ + ret = DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF; + break; + case IP_VERSION(3, 5, 1): + ret = DMUB_IPS_RCG_IN_ACTIVE_IPS2_IN_OFF; + break; + default: + /* ASICs older than DCN35 do not have IPSs */ + if (amdgpu_ip_version(adev, DCE_HWIP, 0) < IP_VERSION(3, 5, 0)) + ret = DMUB_IPS_DISABLE_ALL; + break; + } - /* ASICs older than DCN35 do not have IPSs */ - return DMUB_IPS_DISABLE_ALL; + return ret; } static int amdgpu_dm_init(struct amdgpu_device *adev) From 6aa1aa6237ba6042615acee7268f7611c2e03a5d Mon Sep 17 00:00:00 2001 From: Charlene Liu Date: Thu, 5 Sep 2024 17:28:12 -0400 Subject: [PATCH 1570/1868] drm/amd/display: Clear cached watermark after resume [WHY] Driver could skip program watermarks when resume from S0i3/S4. [HOW] Clear the cached one first to make sure new value gets applied. Reviewed-by: Alvin Lee Reviewed-by: Roman Li Signed-off-by: Charlene Liu Signed-off-by: Alex Hung Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c index 6293173ba2b9d..5eb3da8d5206e 100644 --- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c +++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn35/dcn35_hubbub.c @@ -545,6 +545,7 @@ static void hubbub35_init(struct hubbub *hubbub) DCHUBBUB_ARB_MAX_REQ_OUTSTAND, 256, DCHUBBUB_ARB_MIN_REQ_OUTSTAND, 256); + memset(&hubbub2->watermarks.a.cstate_pstate, 0, sizeof(hubbub2->watermarks.a.cstate_pstate)); } /*static void hubbub35_set_request_limit(struct hubbub *hubbub, From 9b80fcc2e4a8108fdadeda42ec3e3fbe53871753 Mon Sep 17 00:00:00 2001 From: Aric Cyr Date: Sun, 8 Sep 2024 21:40:21 -0400 Subject: [PATCH 1571/1868] drm/amd/display: 3.2.301 - Clear cached watermark after resume - Update IPS default mode for DCN35/DCN351 - Use full update for swizzle mode change - Skip to enable dsc if it has been off - Fix underflow when setting underscan on DCN401 - Remove always-false branches - Check null pointer before dereferencing se Acked-by: Alex Hung Signed-off-by: Aric Cyr Signed-off-by: Alex Hung Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 65425a7b33242..e39b56bf028d1 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -55,7 +55,7 @@ struct aux_payload; struct set_config_cmd_payload; struct dmub_notification; -#define DC_VER "3.2.300" +#define DC_VER "3.2.301" #define MAX_SURFACES 3 #define MAX_PLANES 6 From f606d83b59b3370993ab6e5e7cc16fe5cb803c14 Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Thu, 18 Jul 2024 18:55:06 +0800 Subject: [PATCH 1572/1868] drm/amd/pm: Use same metric table for APU Use same metric table for APU and Non APU systems for smu_v_13_0_6 to get metric data based on newer pmfw versions v2: Use inline func to check for unified metrics support Signed-off-by: Asad Kamal Reviewed-by: Lijo Lazar --- .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 102 ++++++++++-------- 1 file changed, 55 insertions(+), 47 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index c70b6ef5e5f3a..52eff3dab8a80 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -102,6 +102,12 @@ MODULE_FIRMWARE("amdgpu/smu_13_0_14.bin"); #define MCA_BANK_IPID(_ip, _hwid, _type) \ [AMDGPU_MCA_IP_##_ip] = { .hwid = _hwid, .mcatype = _type, } +static inline bool smu_v13_0_6_is_unified_metrics(struct smu_context *smu) +{ + return (smu->adev->flags & AMD_IS_APU) && + smu->smc_fw_version <= 0x4556900; +} + struct mca_bank_ipid { enum amdgpu_mca_ip ip; uint16_t hwid; @@ -260,7 +266,7 @@ struct PPTable_t { #define SMUQ10_TO_UINT(x) ((x) >> 10) #define SMUQ10_FRAC(x) ((x) & 0x3ff) #define SMUQ10_ROUND(x) ((SMUQ10_TO_UINT(x)) + ((SMUQ10_FRAC(x)) >= 0x200)) -#define GET_METRIC_FIELD(field) ((adev->flags & AMD_IS_APU) ?\ +#define GET_METRIC_FIELD(field, flag) ((flag) ?\ (metrics_a->field) : (metrics_x->field)) struct smu_v13_0_6_dpm_map { @@ -732,7 +738,7 @@ static int smu_v13_0_6_setup_driver_pptable(struct smu_context *smu) MetricsTableA_t *metrics_a = (MetricsTableA_t *)smu_table->metrics_table; struct PPTable_t *pptable = (struct PPTable_t *)smu_table->driver_pptable; - struct amdgpu_device *adev = smu->adev; + bool flag = smu_v13_0_6_is_unified_metrics(smu); int ret, i, retry = 100; uint32_t table_version; @@ -744,7 +750,7 @@ static int smu_v13_0_6_setup_driver_pptable(struct smu_context *smu) return ret; /* Ensure that metrics have been updated */ - if (GET_METRIC_FIELD(AccumulationCounter)) + if (GET_METRIC_FIELD(AccumulationCounter, flag)) break; usleep_range(1000, 1100); @@ -761,29 +767,29 @@ static int smu_v13_0_6_setup_driver_pptable(struct smu_context *smu) table_version; pptable->MaxSocketPowerLimit = - SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketPowerLimit)); + SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketPowerLimit, flag)); pptable->MaxGfxclkFrequency = - SMUQ10_ROUND(GET_METRIC_FIELD(MaxGfxclkFrequency)); + SMUQ10_ROUND(GET_METRIC_FIELD(MaxGfxclkFrequency, flag)); pptable->MinGfxclkFrequency = - SMUQ10_ROUND(GET_METRIC_FIELD(MinGfxclkFrequency)); + SMUQ10_ROUND(GET_METRIC_FIELD(MinGfxclkFrequency, flag)); for (i = 0; i < 4; ++i) { pptable->FclkFrequencyTable[i] = - SMUQ10_ROUND(GET_METRIC_FIELD(FclkFrequencyTable)[i]); + SMUQ10_ROUND(GET_METRIC_FIELD(FclkFrequencyTable, flag)[i]); pptable->UclkFrequencyTable[i] = - SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequencyTable)[i]); + SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequencyTable, flag)[i]); pptable->SocclkFrequencyTable[i] = SMUQ10_ROUND( - GET_METRIC_FIELD(SocclkFrequencyTable)[i]); + GET_METRIC_FIELD(SocclkFrequencyTable, flag)[i]); pptable->VclkFrequencyTable[i] = - SMUQ10_ROUND(GET_METRIC_FIELD(VclkFrequencyTable)[i]); + SMUQ10_ROUND(GET_METRIC_FIELD(VclkFrequencyTable, flag)[i]); pptable->DclkFrequencyTable[i] = - SMUQ10_ROUND(GET_METRIC_FIELD(DclkFrequencyTable)[i]); + SMUQ10_ROUND(GET_METRIC_FIELD(DclkFrequencyTable, flag)[i]); pptable->LclkFrequencyTable[i] = - SMUQ10_ROUND(GET_METRIC_FIELD(LclkFrequencyTable)[i]); + SMUQ10_ROUND(GET_METRIC_FIELD(LclkFrequencyTable, flag)[i]); } /* use AID0 serial number by default */ - pptable->PublicSerialNumber_AID = GET_METRIC_FIELD(PublicSerialNumber_AID)[0]; + pptable->PublicSerialNumber_AID = GET_METRIC_FIELD(PublicSerialNumber_AID, flag)[0]; pptable->Init = true; } @@ -1115,6 +1121,7 @@ static int smu_v13_0_6_get_smu_metrics_data(struct smu_context *smu, struct smu_table_context *smu_table = &smu->smu_table; MetricsTableX_t *metrics_x = (MetricsTableX_t *)smu_table->metrics_table; MetricsTableA_t *metrics_a = (MetricsTableA_t *)smu_table->metrics_table; + bool flag = smu_v13_0_6_is_unified_metrics(smu); struct amdgpu_device *adev = smu->adev; int ret = 0; int xcc_id; @@ -1129,50 +1136,50 @@ static int smu_v13_0_6_get_smu_metrics_data(struct smu_context *smu, case METRICS_AVERAGE_GFXCLK: if (smu->smc_fw_version >= 0x552F00) { xcc_id = GET_INST(GC, 0); - *value = SMUQ10_ROUND(GET_METRIC_FIELD(GfxclkFrequency)[xcc_id]); + *value = SMUQ10_ROUND(GET_METRIC_FIELD(GfxclkFrequency, flag)[xcc_id]); } else { *value = 0; } break; case METRICS_CURR_SOCCLK: case METRICS_AVERAGE_SOCCLK: - *value = SMUQ10_ROUND(GET_METRIC_FIELD(SocclkFrequency)[0]); + *value = SMUQ10_ROUND(GET_METRIC_FIELD(SocclkFrequency, flag)[0]); break; case METRICS_CURR_UCLK: case METRICS_AVERAGE_UCLK: - *value = SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequency)); + *value = SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequency, flag)); break; case METRICS_CURR_VCLK: - *value = SMUQ10_ROUND(GET_METRIC_FIELD(VclkFrequency)[0]); + *value = SMUQ10_ROUND(GET_METRIC_FIELD(VclkFrequency, flag)[0]); break; case METRICS_CURR_DCLK: - *value = SMUQ10_ROUND(GET_METRIC_FIELD(DclkFrequency)[0]); + *value = SMUQ10_ROUND(GET_METRIC_FIELD(DclkFrequency, flag)[0]); break; case METRICS_CURR_FCLK: - *value = SMUQ10_ROUND(GET_METRIC_FIELD(FclkFrequency)); + *value = SMUQ10_ROUND(GET_METRIC_FIELD(FclkFrequency, flag)); break; case METRICS_AVERAGE_GFXACTIVITY: - *value = SMUQ10_ROUND(GET_METRIC_FIELD(SocketGfxBusy)); + *value = SMUQ10_ROUND(GET_METRIC_FIELD(SocketGfxBusy, flag)); break; case METRICS_AVERAGE_MEMACTIVITY: - *value = SMUQ10_ROUND(GET_METRIC_FIELD(DramBandwidthUtilization)); + *value = SMUQ10_ROUND(GET_METRIC_FIELD(DramBandwidthUtilization, flag)); break; case METRICS_CURR_SOCKETPOWER: - *value = SMUQ10_ROUND(GET_METRIC_FIELD(SocketPower)) << 8; + *value = SMUQ10_ROUND(GET_METRIC_FIELD(SocketPower, flag)) << 8; break; case METRICS_TEMPERATURE_HOTSPOT: - *value = SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketTemperature)) * + *value = SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketTemperature, flag)) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; break; case METRICS_TEMPERATURE_MEM: - *value = SMUQ10_ROUND(GET_METRIC_FIELD(MaxHbmTemperature)) * + *value = SMUQ10_ROUND(GET_METRIC_FIELD(MaxHbmTemperature, flag)) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; break; /* This is the max of all VRs and not just SOC VR. * No need to define another data type for the same. */ case METRICS_TEMPERATURE_VRSOC: - *value = SMUQ10_ROUND(GET_METRIC_FIELD(MaxVrTemperature)) * + *value = SMUQ10_ROUND(GET_METRIC_FIELD(MaxVrTemperature, flag)) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; break; default: @@ -2460,6 +2467,7 @@ static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table struct smu_table_context *smu_table = &smu->smu_table; struct gpu_metrics_v1_5 *gpu_metrics = (struct gpu_metrics_v1_5 *)smu_table->gpu_metrics_table; + bool flag = smu_v13_0_6_is_unified_metrics(smu); struct amdgpu_device *adev = smu->adev; int ret = 0, xcc_id, inst, i, j; MetricsTableX_t *metrics_x; @@ -2478,50 +2486,50 @@ static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 5); gpu_metrics->temperature_hotspot = - SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketTemperature)); + SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketTemperature, flag)); /* Individual HBM stack temperature is not reported */ gpu_metrics->temperature_mem = - SMUQ10_ROUND(GET_METRIC_FIELD(MaxHbmTemperature)); + SMUQ10_ROUND(GET_METRIC_FIELD(MaxHbmTemperature, flag)); /* Reports max temperature of all voltage rails */ gpu_metrics->temperature_vrsoc = - SMUQ10_ROUND(GET_METRIC_FIELD(MaxVrTemperature)); + SMUQ10_ROUND(GET_METRIC_FIELD(MaxVrTemperature, flag)); gpu_metrics->average_gfx_activity = - SMUQ10_ROUND(GET_METRIC_FIELD(SocketGfxBusy)); + SMUQ10_ROUND(GET_METRIC_FIELD(SocketGfxBusy, flag)); gpu_metrics->average_umc_activity = - SMUQ10_ROUND(GET_METRIC_FIELD(DramBandwidthUtilization)); + SMUQ10_ROUND(GET_METRIC_FIELD(DramBandwidthUtilization, flag)); gpu_metrics->curr_socket_power = - SMUQ10_ROUND(GET_METRIC_FIELD(SocketPower)); + SMUQ10_ROUND(GET_METRIC_FIELD(SocketPower, flag)); /* Energy counter reported in 15.259uJ (2^-16) units */ - gpu_metrics->energy_accumulator = GET_METRIC_FIELD(SocketEnergyAcc); + gpu_metrics->energy_accumulator = GET_METRIC_FIELD(SocketEnergyAcc, flag); for (i = 0; i < MAX_GFX_CLKS; i++) { xcc_id = GET_INST(GC, i); if (xcc_id >= 0) gpu_metrics->current_gfxclk[i] = - SMUQ10_ROUND(GET_METRIC_FIELD(GfxclkFrequency)[xcc_id]); + SMUQ10_ROUND(GET_METRIC_FIELD(GfxclkFrequency, flag)[xcc_id]); if (i < MAX_CLKS) { gpu_metrics->current_socclk[i] = - SMUQ10_ROUND(GET_METRIC_FIELD(SocclkFrequency)[i]); + SMUQ10_ROUND(GET_METRIC_FIELD(SocclkFrequency, flag)[i]); inst = GET_INST(VCN, i); if (inst >= 0) { gpu_metrics->current_vclk0[i] = - SMUQ10_ROUND(GET_METRIC_FIELD(VclkFrequency)[inst]); + SMUQ10_ROUND(GET_METRIC_FIELD(VclkFrequency, flag)[inst]); gpu_metrics->current_dclk0[i] = - SMUQ10_ROUND(GET_METRIC_FIELD(DclkFrequency)[inst]); + SMUQ10_ROUND(GET_METRIC_FIELD(DclkFrequency, flag)[inst]); } } } - gpu_metrics->current_uclk = SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequency)); + gpu_metrics->current_uclk = SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequency, flag)); /* Throttle status is not reported through metrics now */ gpu_metrics->throttle_status = 0; /* Clock Lock Status. Each bit corresponds to each GFXCLK instance */ - gpu_metrics->gfxclk_lock_status = GET_METRIC_FIELD(GfxLockXCDMak) >> GET_INST(GC, 0); + gpu_metrics->gfxclk_lock_status = GET_METRIC_FIELD(GfxLockXCDMak, flag) >> GET_INST(GC, 0); if (!(adev->flags & AMD_IS_APU)) { /*Check smu version, PCIE link speed and width will be reported from pmfw metric @@ -2562,22 +2570,22 @@ static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); gpu_metrics->gfx_activity_acc = - SMUQ10_ROUND(GET_METRIC_FIELD(SocketGfxBusyAcc)); + SMUQ10_ROUND(GET_METRIC_FIELD(SocketGfxBusyAcc, flag)); gpu_metrics->mem_activity_acc = - SMUQ10_ROUND(GET_METRIC_FIELD(DramBandwidthUtilizationAcc)); + SMUQ10_ROUND(GET_METRIC_FIELD(DramBandwidthUtilizationAcc, flag)); for (i = 0; i < NUM_XGMI_LINKS; i++) { gpu_metrics->xgmi_read_data_acc[i] = - SMUQ10_ROUND(GET_METRIC_FIELD(XgmiReadDataSizeAcc)[i]); + SMUQ10_ROUND(GET_METRIC_FIELD(XgmiReadDataSizeAcc, flag)[i]); gpu_metrics->xgmi_write_data_acc[i] = - SMUQ10_ROUND(GET_METRIC_FIELD(XgmiWriteDataSizeAcc)[i]); + SMUQ10_ROUND(GET_METRIC_FIELD(XgmiWriteDataSizeAcc, flag)[i]); } for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { inst = GET_INST(JPEG, i); for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { gpu_metrics->jpeg_activity[(i * adev->jpeg.num_jpeg_rings) + j] = - SMUQ10_ROUND(GET_METRIC_FIELD(JpegBusy) + SMUQ10_ROUND(GET_METRIC_FIELD(JpegBusy, flag) [(inst * adev->jpeg.num_jpeg_rings) + j]); } } @@ -2585,13 +2593,13 @@ static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { inst = GET_INST(VCN, i); gpu_metrics->vcn_activity[i] = - SMUQ10_ROUND(GET_METRIC_FIELD(VcnBusy)[inst]); + SMUQ10_ROUND(GET_METRIC_FIELD(VcnBusy, flag)[inst]); } - gpu_metrics->xgmi_link_width = SMUQ10_ROUND(GET_METRIC_FIELD(XgmiWidth)); - gpu_metrics->xgmi_link_speed = SMUQ10_ROUND(GET_METRIC_FIELD(XgmiBitrate)); + gpu_metrics->xgmi_link_width = SMUQ10_ROUND(GET_METRIC_FIELD(XgmiWidth, flag)); + gpu_metrics->xgmi_link_speed = SMUQ10_ROUND(GET_METRIC_FIELD(XgmiBitrate, flag)); - gpu_metrics->firmware_timestamp = GET_METRIC_FIELD(Timestamp); + gpu_metrics->firmware_timestamp = GET_METRIC_FIELD(Timestamp, flag); *table = (void *)gpu_metrics; kfree(metrics_x); From 89c9b56c30cc57b9472aa5b7e804630637ec6b31 Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Sun, 14 Jul 2024 04:04:51 +0800 Subject: [PATCH 1573/1868] drm/amd/pm: Add gpu_metrics_v1_6 Add new gpu_metrics_v1_6 with activities per partition Signed-off-by: Asad Kamal Reviewed-by: Lijo Lazar --- .../gpu/drm/amd/include/kgd_pp_interface.h | 103 +++++++++++++++++- drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 3 + 2 files changed, 105 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h index 79020d17ac784..0cec1c4d4e266 100644 --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h @@ -345,7 +345,8 @@ enum pp_pm_phase_det_param_id { #define MAX_CLKS 4 #define NUM_VCN 4 #define NUM_JPEG_ENG 32 - +#define MAX_XCC 8 +#define NUM_XCP 8 struct seq_file; enum amd_pp_clock_type; struct amd_pp_simple_clock_info; @@ -359,6 +360,15 @@ struct pp_smu_wm_range_sets; struct pp_smu_nv_clock_table; struct dpm_clocks; +struct amdgpu_xcp_metrics { + /* Utilization Instantaneous (%) */ + u32 gfx_busy_inst[MAX_XCC]; + u16 jpeg_busy[NUM_JPEG_ENG]; + u16 vcn_busy[NUM_VCN]; + /* Utilization Accumulated (%) */ + u64 gfx_busy_acc[MAX_XCC]; +}; + struct amd_pm_funcs { /* export for dpm on ci and si */ int (*pre_set_power_state)(void *handle); @@ -881,6 +891,97 @@ struct gpu_metrics_v1_5 { uint16_t padding; }; +struct gpu_metrics_v1_6 { + struct metrics_table_header common_header; + + /* Temperature (Celsius) */ + uint16_t temperature_hotspot; + uint16_t temperature_mem; + uint16_t temperature_vrsoc; + + /* Power (Watts) */ + uint16_t curr_socket_power; + + /* Utilization (%) */ + uint16_t average_gfx_activity; + uint16_t average_umc_activity; // memory controller + + /* Energy (15.259uJ (2^-16) units) */ + uint64_t energy_accumulator; + + /* Driver attached timestamp (in ns) */ + uint64_t system_clock_counter; + + /* Accumulation cycle counter */ + uint32_t accumulation_counter; + + /* Accumulated throttler residencies */ + uint32_t prochot_residency_acc; + uint32_t ppt_residency_acc; + uint32_t socket_thm_residency_acc; + uint32_t vr_thm_residency_acc; + uint32_t hbm_thm_residency_acc; + + /* Clock Lock Status. Each bit corresponds to clock instance */ + uint32_t gfxclk_lock_status; + + /* Link width (number of lanes) and speed (in 0.1 GT/s) */ + uint16_t pcie_link_width; + uint16_t pcie_link_speed; + + /* XGMI bus width and bitrate (in Gbps) */ + uint16_t xgmi_link_width; + uint16_t xgmi_link_speed; + + /* Utilization Accumulated (%) */ + uint32_t gfx_activity_acc; + uint32_t mem_activity_acc; + + /*PCIE accumulated bandwidth (GB/sec) */ + uint64_t pcie_bandwidth_acc; + + /*PCIE instantaneous bandwidth (GB/sec) */ + uint64_t pcie_bandwidth_inst; + + /* PCIE L0 to recovery state transition accumulated count */ + uint64_t pcie_l0_to_recov_count_acc; + + /* PCIE replay accumulated count */ + uint64_t pcie_replay_count_acc; + + /* PCIE replay rollover accumulated count */ + uint64_t pcie_replay_rover_count_acc; + + /* PCIE NAK sent accumulated count */ + uint32_t pcie_nak_sent_count_acc; + + /* PCIE NAK received accumulated count */ + uint32_t pcie_nak_rcvd_count_acc; + + /* XGMI accumulated data transfer size(KiloBytes) */ + uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS]; + uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS]; + + /* PMFW attached timestamp (10ns resolution) */ + uint64_t firmware_timestamp; + + /* Current clocks (Mhz) */ + uint16_t current_gfxclk[MAX_GFX_CLKS]; + uint16_t current_socclk[MAX_CLKS]; + uint16_t current_vclk0[MAX_CLKS]; + uint16_t current_dclk0[MAX_CLKS]; + uint16_t current_uclk; + + /* Number of current partition */ + uint16_t num_partition; + + /* XCP metrics stats */ + struct amdgpu_xcp_metrics xcp_stats[NUM_XCP]; + + /* PCIE other end recovery counter */ + uint32_t pcie_lc_perf_other_end_recovery; +}; + /* * gpu_metrics_v2_0 is not recommended as it's not naturally aligned. * Use gpu_metrics_v2_1 or later instead. diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c index 88eefef05faed..63c4f75fa1183 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c @@ -1078,6 +1078,9 @@ void smu_cmn_init_soft_gpu_metrics(void *table, uint8_t frev, uint8_t crev) case METRICS_VERSION(1, 5): structure_size = sizeof(struct gpu_metrics_v1_5); break; + case METRICS_VERSION(1, 6): + structure_size = sizeof(struct gpu_metrics_v1_6); + break; case METRICS_VERSION(2, 0): structure_size = sizeof(struct gpu_metrics_v2_0); break; From cd6c1c24c8a1e53447c66ace63788725f07e8709 Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Mon, 22 Jul 2024 19:45:11 +0800 Subject: [PATCH 1574/1868] drm/amdgpu: Fix get each xcp macro Fix get each xcp macro to loop over each partition correctly Fixes: 4bdca2057933 ("drm/amdgpu: Add utility functions for xcp") Signed-off-by: Asad Kamal Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h index 90138bc5f03d1..32775260556f4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h @@ -180,6 +180,6 @@ amdgpu_get_next_xcp(struct amdgpu_xcp_mgr *xcp_mgr, int *from) #define for_each_xcp(xcp_mgr, xcp, i) \ for (i = 0, xcp = amdgpu_get_next_xcp(xcp_mgr, &i); xcp; \ - xcp = amdgpu_get_next_xcp(xcp_mgr, &i)) + ++i, xcp = amdgpu_get_next_xcp(xcp_mgr, &i)) #endif From e457c4e6a7a1d5be7457883938b1bc7b8ded2eb5 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Wed, 11 Sep 2024 13:49:51 +0530 Subject: [PATCH 1575/1868] drm/amdgpu: Fix XCP instance mask calculation Fix instance mask calculation for VCN IP. There are cases where VCN instance could be shared across partitions. Fix here so that other blocks don't need to check for any shared instances based on partition mode. Signed-off-by: Lijo Lazar Reviewed-by: Asad Kamal --- drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c | 32 +++++++++------------- 1 file changed, 13 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c b/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c index 79cd14223c89c..9f6a28ea0e694 100644 --- a/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c +++ b/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c @@ -94,8 +94,6 @@ static void aqua_vanjaram_set_xcp_id(struct amdgpu_device *adev, case AMDGPU_RING_TYPE_VCN_ENC: case AMDGPU_RING_TYPE_VCN_JPEG: ip_blk = AMDGPU_XCP_VCN; - if (aqua_vanjaram_xcp_vcn_shared(adev)) - inst_mask = 1 << (inst_idx * 2); break; default: DRM_ERROR("Not support ring type %d!", ring->funcs->type); @@ -105,6 +103,8 @@ static void aqua_vanjaram_set_xcp_id(struct amdgpu_device *adev, for (xcp_id = 0; xcp_id < adev->xcp_mgr->num_xcps; xcp_id++) { if (adev->xcp_mgr->xcp[xcp_id].ip[ip_blk].inst_mask & inst_mask) { ring->xcp_id = xcp_id; + dev_dbg(adev->dev, "ring:%s xcp_id :%u", ring->name, + ring->xcp_id); if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) adev->gfx.enforce_isolation[xcp_id].xcp_id = xcp_id; break; @@ -394,38 +394,31 @@ static int __aqua_vanjaram_get_xcp_ip_info(struct amdgpu_xcp_mgr *xcp_mgr, int x struct amdgpu_xcp_ip *ip) { struct amdgpu_device *adev = xcp_mgr->adev; + int num_sdma, num_vcn, num_shared_vcn, num_xcp; int num_xcc_xcp, num_sdma_xcp, num_vcn_xcp; - int num_sdma, num_vcn; num_sdma = adev->sdma.num_instances; num_vcn = adev->vcn.num_vcn_inst; + num_shared_vcn = 1; + + num_xcc_xcp = adev->gfx.num_xcc_per_xcp; + num_xcp = NUM_XCC(adev->gfx.xcc_mask) / num_xcc_xcp; switch (xcp_mgr->mode) { case AMDGPU_SPX_PARTITION_MODE: - num_sdma_xcp = num_sdma; - num_vcn_xcp = num_vcn; - break; case AMDGPU_DPX_PARTITION_MODE: - num_sdma_xcp = num_sdma / 2; - num_vcn_xcp = num_vcn / 2; - break; case AMDGPU_TPX_PARTITION_MODE: - num_sdma_xcp = num_sdma / 3; - num_vcn_xcp = num_vcn / 3; - break; case AMDGPU_QPX_PARTITION_MODE: - num_sdma_xcp = num_sdma / 4; - num_vcn_xcp = num_vcn / 4; - break; case AMDGPU_CPX_PARTITION_MODE: - num_sdma_xcp = 2; - num_vcn_xcp = num_vcn ? 1 : 0; + num_sdma_xcp = DIV_ROUND_UP(num_sdma, num_xcp); + num_vcn_xcp = DIV_ROUND_UP(num_vcn, num_xcp); break; default: return -EINVAL; } - num_xcc_xcp = adev->gfx.num_xcc_per_xcp; + if (num_vcn && num_xcp > num_vcn) + num_shared_vcn = num_xcp / num_vcn; switch (ip_id) { case AMDGPU_XCP_GFXHUB: @@ -441,7 +434,8 @@ static int __aqua_vanjaram_get_xcp_ip_info(struct amdgpu_xcp_mgr *xcp_mgr, int x ip->ip_funcs = &sdma_v4_4_2_xcp_funcs; break; case AMDGPU_XCP_VCN: - ip->inst_mask = XCP_INST_MASK(num_vcn_xcp, xcp_id); + ip->inst_mask = + XCP_INST_MASK(num_vcn_xcp, xcp_id / num_shared_vcn); /* TODO : Assign IP funcs */ break; default: From 64a3b965dd68f02000cea54e6694f20ad1d7d38d Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Mon, 22 Jul 2024 20:00:52 +0800 Subject: [PATCH 1576/1868] drm/amd/pm: Use metrics 1_6 Use metrics 1_6 to report activities per partition v2: Use separate per instance for different platforms, shared vcn handled by other fix Signed-off-by: Asad Kamal Reviewed-by: Lijo Lazar --- .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 78 ++++++++++++++----- 1 file changed, 60 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index 52eff3dab8a80..a91a39bc44c3b 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -365,7 +365,7 @@ static int smu_v13_0_6_tables_init(struct smu_context *smu) return -ENOMEM; smu_table->metrics_time = 0; - smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_5); + smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_6); smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); if (!smu_table->gpu_metrics_table) { @@ -2464,15 +2464,18 @@ static int smu_v13_0_6_get_current_pcie_link_speed(struct smu_context *smu) static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table) { + bool per_inst, smu_13_0_6_per_inst, smu_13_0_14_per_inst, apu_per_inst; struct smu_table_context *smu_table = &smu->smu_table; - struct gpu_metrics_v1_5 *gpu_metrics = - (struct gpu_metrics_v1_5 *)smu_table->gpu_metrics_table; + struct gpu_metrics_v1_6 *gpu_metrics = + (struct gpu_metrics_v1_6 *)smu_table->gpu_metrics_table; bool flag = smu_v13_0_6_is_unified_metrics(smu); + int ret = 0, xcc_id, inst, i, j, k, idx; struct amdgpu_device *adev = smu->adev; - int ret = 0, xcc_id, inst, i, j; MetricsTableX_t *metrics_x; MetricsTableA_t *metrics_a; + struct amdgpu_xcp *xcp; u16 link_width_level; + u32 inst_mask; metrics_x = kzalloc(max(sizeof(MetricsTableX_t), sizeof(MetricsTableA_t)), GFP_KERNEL); ret = smu_v13_0_6_get_metrics_table(smu, metrics_x, true); @@ -2483,7 +2486,7 @@ static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table metrics_a = (MetricsTableA_t *)metrics_x; - smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 5); + smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 6); gpu_metrics->temperature_hotspot = SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketTemperature, flag)); @@ -2525,8 +2528,15 @@ static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table gpu_metrics->current_uclk = SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequency, flag)); - /* Throttle status is not reported through metrics now */ - gpu_metrics->throttle_status = 0; + /* Total accumulated cycle counter */ + gpu_metrics->accumulation_counter = GET_METRIC_FIELD(AccumulationCounter, flag); + + /* Accumulated throttler residencies */ + gpu_metrics->prochot_residency_acc = GET_METRIC_FIELD(ProchotResidencyAcc, flag); + gpu_metrics->ppt_residency_acc = GET_METRIC_FIELD(PptResidencyAcc, flag); + gpu_metrics->socket_thm_residency_acc = GET_METRIC_FIELD(SocketThmResidencyAcc, flag); + gpu_metrics->vr_thm_residency_acc = GET_METRIC_FIELD(VrThmResidencyAcc, flag); + gpu_metrics->hbm_thm_residency_acc = GET_METRIC_FIELD(HbmThmResidencyAcc, flag); /* Clock Lock Status. Each bit corresponds to each GFXCLK instance */ gpu_metrics->gfxclk_lock_status = GET_METRIC_FIELD(GfxLockXCDMak, flag) >> GET_INST(GC, 0); @@ -2581,19 +2591,51 @@ static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table SMUQ10_ROUND(GET_METRIC_FIELD(XgmiWriteDataSizeAcc, flag)[i]); } - for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { - inst = GET_INST(JPEG, i); - for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { - gpu_metrics->jpeg_activity[(i * adev->jpeg.num_jpeg_rings) + j] = - SMUQ10_ROUND(GET_METRIC_FIELD(JpegBusy, flag) - [(inst * adev->jpeg.num_jpeg_rings) + j]); + gpu_metrics->num_partition = adev->xcp_mgr->num_xcps; + + apu_per_inst = (adev->flags & AMD_IS_APU) && (smu->smc_fw_version >= 0x04556A00); + smu_13_0_6_per_inst = !(adev->flags & AMD_IS_APU) && + (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) + == IP_VERSION(13, 0, 6)) && + (smu->smc_fw_version >= 0x556F00); + smu_13_0_14_per_inst = !(adev->flags & AMD_IS_APU) && + (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) + == IP_VERSION(13, 0, 14)) && + (smu->smc_fw_version >= 0x05550B00); + + per_inst = apu_per_inst || smu_13_0_6_per_inst || smu_13_0_14_per_inst; + + for_each_xcp(adev->xcp_mgr, xcp, i) { + amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_VCN, &inst_mask); + idx = 0; + for_each_inst(k, inst_mask) { + /* Both JPEG and VCN has same instances */ + inst = GET_INST(VCN, k); + + for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { + gpu_metrics->xcp_stats[i].jpeg_busy + [(idx * adev->jpeg.num_jpeg_rings) + j] = + SMUQ10_ROUND(GET_METRIC_FIELD(JpegBusy, flag) + [(inst * adev->jpeg.num_jpeg_rings) + j]); + } + gpu_metrics->xcp_stats[i].vcn_busy[idx] = + SMUQ10_ROUND(GET_METRIC_FIELD(VcnBusy, flag)[inst]); + idx++; + } - } - for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { - inst = GET_INST(VCN, i); - gpu_metrics->vcn_activity[i] = - SMUQ10_ROUND(GET_METRIC_FIELD(VcnBusy, flag)[inst]); + if (per_inst) { + amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_GFX, &inst_mask); + idx = 0; + for_each_inst(k, inst_mask) { + inst = GET_INST(GC, k); + gpu_metrics->xcp_stats[i].gfx_busy_inst[idx] = + SMUQ10_ROUND(metrics_x->GfxBusy[inst]); + gpu_metrics->xcp_stats[i].gfx_busy_acc[idx] = + SMUQ10_ROUND(metrics_x->GfxBusyAcc[inst]); + idx++; + } + } } gpu_metrics->xgmi_link_width = SMUQ10_ROUND(GET_METRIC_FIELD(XgmiWidth, flag)); From f90252b401408bbd4392976ed519a1f121c070c5 Mon Sep 17 00:00:00 2001 From: Yang Su Date: Thu, 19 Sep 2024 16:10:15 +0800 Subject: [PATCH 1577/1868] Bump AMDGPU version to 6.10.2 Signed-off-by: Yang Su --- drivers/gpu/drm/amd/dkms/configure.ac | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/configure.ac b/drivers/gpu/drm/amd/dkms/configure.ac index cd022ad0caf95..68225c89eabea 100644 --- a/drivers/gpu/drm/amd/dkms/configure.ac +++ b/drivers/gpu/drm/amd/dkms/configure.ac @@ -1,4 +1,4 @@ -AC_INIT(amdgpu-dkms, 6.10.1) +AC_INIT(amdgpu-dkms, 6.10.2) AC_LANG(C) AC_CONFIG_AUX_DIR([config]) From 78548293df95d211c21a9e4513e8d1d31442293e Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 19 Sep 2024 19:21:03 +0800 Subject: [PATCH 1578/1868] Revert "drm/amdkfd: Move queue fs deletion after destroy check" This reverts commit f328d1e8c655282c94a2f704df01da9f08d2c442. The patch has conflict with the non-upstream patch e2681918678d794b80a1232de7bbbd5fe0c2efae "drm/amdkfd: block queue destroy on suspended queues" So keep the non-upstream solution. Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c index c23d25e4af9d2..120f36804618a 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c @@ -531,7 +531,6 @@ int pqm_destroy_queue(struct process_queue_manager *pqm, unsigned int qid) if (retval != -ETIME) goto err_destroy_queue; } - kfd_procfs_del_queue(pqn->q); kfd_queue_release_buffers(pdd, &pqn->q->properties); pqm_clean_queue_resource(pqm, pqn); uninit_queue(pqn->q); From e33dac932e22353a24afcb87992f628ef5075c55 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 20 Sep 2024 11:22:18 +0800 Subject: [PATCH 1579/1868] Revert "drm/amd/pm: Update SMUv13.0.6 PMFW headers" This reverts commit 3bcc02c71b8a0b8018b94027f53b0662beccac88. The reverted patche causes a Jira issue SWDEV-486083 and SWDEV-486084. So temporarily revert it. Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h index 822c6425d90e0..0b3c2f54a3433 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h @@ -123,7 +123,7 @@ typedef enum { VOLTAGE_GUARDBAND_COUNT } GFX_GUARDBAND_e; -#define SMU_METRICS_TABLE_VERSION 0xD +#define SMU_METRICS_TABLE_VERSION 0xC typedef struct __attribute__((packed, aligned(4))) { uint32_t AccumulationCounter; @@ -227,10 +227,6 @@ typedef struct __attribute__((packed, aligned(4))) { // PCIE LINK Speed and width uint32_t PCIeLinkSpeed; uint32_t PCIeLinkWidth; - - // PER XCD ACTIVITY - uint32_t GfxBusy[8]; - uint64_t GfxBusyAcc[8]; } MetricsTableX_t; typedef struct __attribute__((packed, aligned(4))) { From 05532af9584ff4e2ee5a1929af95678e84e0eedc Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 20 Sep 2024 11:27:07 +0800 Subject: [PATCH 1580/1868] Revert "drm/amd/pm: Use metrics 1_6" This reverts commit 64a3b965dd68f02000cea54e6694f20ad1d7d38d. The reverted patche causes a Jira issue SWDEV-486083 and SWDEV-486084. So temporarily revert it. Signed-off-by: Bob Zhou --- .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 78 +++++-------------- 1 file changed, 18 insertions(+), 60 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index a91a39bc44c3b..52eff3dab8a80 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -365,7 +365,7 @@ static int smu_v13_0_6_tables_init(struct smu_context *smu) return -ENOMEM; smu_table->metrics_time = 0; - smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_6); + smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_5); smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); if (!smu_table->gpu_metrics_table) { @@ -2464,18 +2464,15 @@ static int smu_v13_0_6_get_current_pcie_link_speed(struct smu_context *smu) static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table) { - bool per_inst, smu_13_0_6_per_inst, smu_13_0_14_per_inst, apu_per_inst; struct smu_table_context *smu_table = &smu->smu_table; - struct gpu_metrics_v1_6 *gpu_metrics = - (struct gpu_metrics_v1_6 *)smu_table->gpu_metrics_table; + struct gpu_metrics_v1_5 *gpu_metrics = + (struct gpu_metrics_v1_5 *)smu_table->gpu_metrics_table; bool flag = smu_v13_0_6_is_unified_metrics(smu); - int ret = 0, xcc_id, inst, i, j, k, idx; struct amdgpu_device *adev = smu->adev; + int ret = 0, xcc_id, inst, i, j; MetricsTableX_t *metrics_x; MetricsTableA_t *metrics_a; - struct amdgpu_xcp *xcp; u16 link_width_level; - u32 inst_mask; metrics_x = kzalloc(max(sizeof(MetricsTableX_t), sizeof(MetricsTableA_t)), GFP_KERNEL); ret = smu_v13_0_6_get_metrics_table(smu, metrics_x, true); @@ -2486,7 +2483,7 @@ static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table metrics_a = (MetricsTableA_t *)metrics_x; - smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 6); + smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 5); gpu_metrics->temperature_hotspot = SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketTemperature, flag)); @@ -2528,15 +2525,8 @@ static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table gpu_metrics->current_uclk = SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequency, flag)); - /* Total accumulated cycle counter */ - gpu_metrics->accumulation_counter = GET_METRIC_FIELD(AccumulationCounter, flag); - - /* Accumulated throttler residencies */ - gpu_metrics->prochot_residency_acc = GET_METRIC_FIELD(ProchotResidencyAcc, flag); - gpu_metrics->ppt_residency_acc = GET_METRIC_FIELD(PptResidencyAcc, flag); - gpu_metrics->socket_thm_residency_acc = GET_METRIC_FIELD(SocketThmResidencyAcc, flag); - gpu_metrics->vr_thm_residency_acc = GET_METRIC_FIELD(VrThmResidencyAcc, flag); - gpu_metrics->hbm_thm_residency_acc = GET_METRIC_FIELD(HbmThmResidencyAcc, flag); + /* Throttle status is not reported through metrics now */ + gpu_metrics->throttle_status = 0; /* Clock Lock Status. Each bit corresponds to each GFXCLK instance */ gpu_metrics->gfxclk_lock_status = GET_METRIC_FIELD(GfxLockXCDMak, flag) >> GET_INST(GC, 0); @@ -2591,51 +2581,19 @@ static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table SMUQ10_ROUND(GET_METRIC_FIELD(XgmiWriteDataSizeAcc, flag)[i]); } - gpu_metrics->num_partition = adev->xcp_mgr->num_xcps; - - apu_per_inst = (adev->flags & AMD_IS_APU) && (smu->smc_fw_version >= 0x04556A00); - smu_13_0_6_per_inst = !(adev->flags & AMD_IS_APU) && - (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) - == IP_VERSION(13, 0, 6)) && - (smu->smc_fw_version >= 0x556F00); - smu_13_0_14_per_inst = !(adev->flags & AMD_IS_APU) && - (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) - == IP_VERSION(13, 0, 14)) && - (smu->smc_fw_version >= 0x05550B00); - - per_inst = apu_per_inst || smu_13_0_6_per_inst || smu_13_0_14_per_inst; - - for_each_xcp(adev->xcp_mgr, xcp, i) { - amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_VCN, &inst_mask); - idx = 0; - for_each_inst(k, inst_mask) { - /* Both JPEG and VCN has same instances */ - inst = GET_INST(VCN, k); - - for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { - gpu_metrics->xcp_stats[i].jpeg_busy - [(idx * adev->jpeg.num_jpeg_rings) + j] = - SMUQ10_ROUND(GET_METRIC_FIELD(JpegBusy, flag) - [(inst * adev->jpeg.num_jpeg_rings) + j]); - } - gpu_metrics->xcp_stats[i].vcn_busy[idx] = - SMUQ10_ROUND(GET_METRIC_FIELD(VcnBusy, flag)[inst]); - idx++; - + for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { + inst = GET_INST(JPEG, i); + for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { + gpu_metrics->jpeg_activity[(i * adev->jpeg.num_jpeg_rings) + j] = + SMUQ10_ROUND(GET_METRIC_FIELD(JpegBusy, flag) + [(inst * adev->jpeg.num_jpeg_rings) + j]); } + } - if (per_inst) { - amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_GFX, &inst_mask); - idx = 0; - for_each_inst(k, inst_mask) { - inst = GET_INST(GC, k); - gpu_metrics->xcp_stats[i].gfx_busy_inst[idx] = - SMUQ10_ROUND(metrics_x->GfxBusy[inst]); - gpu_metrics->xcp_stats[i].gfx_busy_acc[idx] = - SMUQ10_ROUND(metrics_x->GfxBusyAcc[inst]); - idx++; - } - } + for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { + inst = GET_INST(VCN, i); + gpu_metrics->vcn_activity[i] = + SMUQ10_ROUND(GET_METRIC_FIELD(VcnBusy, flag)[inst]); } gpu_metrics->xgmi_link_width = SMUQ10_ROUND(GET_METRIC_FIELD(XgmiWidth, flag)); From a9e57a77ba5cff6ba6ac84cb6725e226607ef4dc Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 20 Sep 2024 11:27:33 +0800 Subject: [PATCH 1581/1868] Revert "drm/amdgpu: Fix XCP instance mask calculation" This reverts commit e457c4e6a7a1d5be7457883938b1bc7b8ded2eb5. The reverted patche causes a Jira issue SWDEV-486083 and SWDEV-486084. So temporarily revert it. Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c | 32 +++++++++++++--------- 1 file changed, 19 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c b/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c index 9f6a28ea0e694..79cd14223c89c 100644 --- a/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c +++ b/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c @@ -94,6 +94,8 @@ static void aqua_vanjaram_set_xcp_id(struct amdgpu_device *adev, case AMDGPU_RING_TYPE_VCN_ENC: case AMDGPU_RING_TYPE_VCN_JPEG: ip_blk = AMDGPU_XCP_VCN; + if (aqua_vanjaram_xcp_vcn_shared(adev)) + inst_mask = 1 << (inst_idx * 2); break; default: DRM_ERROR("Not support ring type %d!", ring->funcs->type); @@ -103,8 +105,6 @@ static void aqua_vanjaram_set_xcp_id(struct amdgpu_device *adev, for (xcp_id = 0; xcp_id < adev->xcp_mgr->num_xcps; xcp_id++) { if (adev->xcp_mgr->xcp[xcp_id].ip[ip_blk].inst_mask & inst_mask) { ring->xcp_id = xcp_id; - dev_dbg(adev->dev, "ring:%s xcp_id :%u", ring->name, - ring->xcp_id); if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) adev->gfx.enforce_isolation[xcp_id].xcp_id = xcp_id; break; @@ -394,31 +394,38 @@ static int __aqua_vanjaram_get_xcp_ip_info(struct amdgpu_xcp_mgr *xcp_mgr, int x struct amdgpu_xcp_ip *ip) { struct amdgpu_device *adev = xcp_mgr->adev; - int num_sdma, num_vcn, num_shared_vcn, num_xcp; int num_xcc_xcp, num_sdma_xcp, num_vcn_xcp; + int num_sdma, num_vcn; num_sdma = adev->sdma.num_instances; num_vcn = adev->vcn.num_vcn_inst; - num_shared_vcn = 1; - - num_xcc_xcp = adev->gfx.num_xcc_per_xcp; - num_xcp = NUM_XCC(adev->gfx.xcc_mask) / num_xcc_xcp; switch (xcp_mgr->mode) { case AMDGPU_SPX_PARTITION_MODE: + num_sdma_xcp = num_sdma; + num_vcn_xcp = num_vcn; + break; case AMDGPU_DPX_PARTITION_MODE: + num_sdma_xcp = num_sdma / 2; + num_vcn_xcp = num_vcn / 2; + break; case AMDGPU_TPX_PARTITION_MODE: + num_sdma_xcp = num_sdma / 3; + num_vcn_xcp = num_vcn / 3; + break; case AMDGPU_QPX_PARTITION_MODE: + num_sdma_xcp = num_sdma / 4; + num_vcn_xcp = num_vcn / 4; + break; case AMDGPU_CPX_PARTITION_MODE: - num_sdma_xcp = DIV_ROUND_UP(num_sdma, num_xcp); - num_vcn_xcp = DIV_ROUND_UP(num_vcn, num_xcp); + num_sdma_xcp = 2; + num_vcn_xcp = num_vcn ? 1 : 0; break; default: return -EINVAL; } - if (num_vcn && num_xcp > num_vcn) - num_shared_vcn = num_xcp / num_vcn; + num_xcc_xcp = adev->gfx.num_xcc_per_xcp; switch (ip_id) { case AMDGPU_XCP_GFXHUB: @@ -434,8 +441,7 @@ static int __aqua_vanjaram_get_xcp_ip_info(struct amdgpu_xcp_mgr *xcp_mgr, int x ip->ip_funcs = &sdma_v4_4_2_xcp_funcs; break; case AMDGPU_XCP_VCN: - ip->inst_mask = - XCP_INST_MASK(num_vcn_xcp, xcp_id / num_shared_vcn); + ip->inst_mask = XCP_INST_MASK(num_vcn_xcp, xcp_id); /* TODO : Assign IP funcs */ break; default: From baefeb3dc80508fe3353cca019d73cf383ed12ea Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 20 Sep 2024 11:28:09 +0800 Subject: [PATCH 1582/1868] Revert "drm/amdgpu: Fix get each xcp macro" This reverts commit cd6c1c24c8a1e53447c66ace63788725f07e8709. The reverted patche causes a Jira issue SWDEV-486083 and SWDEV-486084. So temporarily revert it. Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h index 32775260556f4..90138bc5f03d1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h @@ -180,6 +180,6 @@ amdgpu_get_next_xcp(struct amdgpu_xcp_mgr *xcp_mgr, int *from) #define for_each_xcp(xcp_mgr, xcp, i) \ for (i = 0, xcp = amdgpu_get_next_xcp(xcp_mgr, &i); xcp; \ - ++i, xcp = amdgpu_get_next_xcp(xcp_mgr, &i)) + xcp = amdgpu_get_next_xcp(xcp_mgr, &i)) #endif From 7695c46a3a8b5fe0aa0aa79e9684fc2580473580 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 20 Sep 2024 11:28:49 +0800 Subject: [PATCH 1583/1868] Revert "drm/amd/pm: Add gpu_metrics_v1_6" This reverts commit 89c9b56c30cc57b9472aa5b7e804630637ec6b31. The reverted patche causes a Jira issue SWDEV-486083 and SWDEV-486084. So temporarily revert it. Signed-off-by: Bob Zhou --- .../gpu/drm/amd/include/kgd_pp_interface.h | 103 +----------------- drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 3 - 2 files changed, 1 insertion(+), 105 deletions(-) diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h index 0cec1c4d4e266..79020d17ac784 100644 --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h @@ -345,8 +345,7 @@ enum pp_pm_phase_det_param_id { #define MAX_CLKS 4 #define NUM_VCN 4 #define NUM_JPEG_ENG 32 -#define MAX_XCC 8 -#define NUM_XCP 8 + struct seq_file; enum amd_pp_clock_type; struct amd_pp_simple_clock_info; @@ -360,15 +359,6 @@ struct pp_smu_wm_range_sets; struct pp_smu_nv_clock_table; struct dpm_clocks; -struct amdgpu_xcp_metrics { - /* Utilization Instantaneous (%) */ - u32 gfx_busy_inst[MAX_XCC]; - u16 jpeg_busy[NUM_JPEG_ENG]; - u16 vcn_busy[NUM_VCN]; - /* Utilization Accumulated (%) */ - u64 gfx_busy_acc[MAX_XCC]; -}; - struct amd_pm_funcs { /* export for dpm on ci and si */ int (*pre_set_power_state)(void *handle); @@ -891,97 +881,6 @@ struct gpu_metrics_v1_5 { uint16_t padding; }; -struct gpu_metrics_v1_6 { - struct metrics_table_header common_header; - - /* Temperature (Celsius) */ - uint16_t temperature_hotspot; - uint16_t temperature_mem; - uint16_t temperature_vrsoc; - - /* Power (Watts) */ - uint16_t curr_socket_power; - - /* Utilization (%) */ - uint16_t average_gfx_activity; - uint16_t average_umc_activity; // memory controller - - /* Energy (15.259uJ (2^-16) units) */ - uint64_t energy_accumulator; - - /* Driver attached timestamp (in ns) */ - uint64_t system_clock_counter; - - /* Accumulation cycle counter */ - uint32_t accumulation_counter; - - /* Accumulated throttler residencies */ - uint32_t prochot_residency_acc; - uint32_t ppt_residency_acc; - uint32_t socket_thm_residency_acc; - uint32_t vr_thm_residency_acc; - uint32_t hbm_thm_residency_acc; - - /* Clock Lock Status. Each bit corresponds to clock instance */ - uint32_t gfxclk_lock_status; - - /* Link width (number of lanes) and speed (in 0.1 GT/s) */ - uint16_t pcie_link_width; - uint16_t pcie_link_speed; - - /* XGMI bus width and bitrate (in Gbps) */ - uint16_t xgmi_link_width; - uint16_t xgmi_link_speed; - - /* Utilization Accumulated (%) */ - uint32_t gfx_activity_acc; - uint32_t mem_activity_acc; - - /*PCIE accumulated bandwidth (GB/sec) */ - uint64_t pcie_bandwidth_acc; - - /*PCIE instantaneous bandwidth (GB/sec) */ - uint64_t pcie_bandwidth_inst; - - /* PCIE L0 to recovery state transition accumulated count */ - uint64_t pcie_l0_to_recov_count_acc; - - /* PCIE replay accumulated count */ - uint64_t pcie_replay_count_acc; - - /* PCIE replay rollover accumulated count */ - uint64_t pcie_replay_rover_count_acc; - - /* PCIE NAK sent accumulated count */ - uint32_t pcie_nak_sent_count_acc; - - /* PCIE NAK received accumulated count */ - uint32_t pcie_nak_rcvd_count_acc; - - /* XGMI accumulated data transfer size(KiloBytes) */ - uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS]; - uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS]; - - /* PMFW attached timestamp (10ns resolution) */ - uint64_t firmware_timestamp; - - /* Current clocks (Mhz) */ - uint16_t current_gfxclk[MAX_GFX_CLKS]; - uint16_t current_socclk[MAX_CLKS]; - uint16_t current_vclk0[MAX_CLKS]; - uint16_t current_dclk0[MAX_CLKS]; - uint16_t current_uclk; - - /* Number of current partition */ - uint16_t num_partition; - - /* XCP metrics stats */ - struct amdgpu_xcp_metrics xcp_stats[NUM_XCP]; - - /* PCIE other end recovery counter */ - uint32_t pcie_lc_perf_other_end_recovery; -}; - /* * gpu_metrics_v2_0 is not recommended as it's not naturally aligned. * Use gpu_metrics_v2_1 or later instead. diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c index 63c4f75fa1183..88eefef05faed 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c @@ -1078,9 +1078,6 @@ void smu_cmn_init_soft_gpu_metrics(void *table, uint8_t frev, uint8_t crev) case METRICS_VERSION(1, 5): structure_size = sizeof(struct gpu_metrics_v1_5); break; - case METRICS_VERSION(1, 6): - structure_size = sizeof(struct gpu_metrics_v1_6); - break; case METRICS_VERSION(2, 0): structure_size = sizeof(struct gpu_metrics_v2_0); break; From 83d073fd39bdce72c0b76ad3616456bbfec65f94 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 20 Sep 2024 11:29:10 +0800 Subject: [PATCH 1584/1868] Revert "drm/amd/pm: Use same metric table for APU" This reverts commit f606d83b59b3370993ab6e5e7cc16fe5cb803c14. The reverted patche causes a Jira issue SWDEV-486083 and SWDEV-486084. So temporarily revert it. Signed-off-by: Bob Zhou --- .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 102 ++++++++---------- 1 file changed, 47 insertions(+), 55 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index 52eff3dab8a80..c70b6ef5e5f3a 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -102,12 +102,6 @@ MODULE_FIRMWARE("amdgpu/smu_13_0_14.bin"); #define MCA_BANK_IPID(_ip, _hwid, _type) \ [AMDGPU_MCA_IP_##_ip] = { .hwid = _hwid, .mcatype = _type, } -static inline bool smu_v13_0_6_is_unified_metrics(struct smu_context *smu) -{ - return (smu->adev->flags & AMD_IS_APU) && - smu->smc_fw_version <= 0x4556900; -} - struct mca_bank_ipid { enum amdgpu_mca_ip ip; uint16_t hwid; @@ -266,7 +260,7 @@ struct PPTable_t { #define SMUQ10_TO_UINT(x) ((x) >> 10) #define SMUQ10_FRAC(x) ((x) & 0x3ff) #define SMUQ10_ROUND(x) ((SMUQ10_TO_UINT(x)) + ((SMUQ10_FRAC(x)) >= 0x200)) -#define GET_METRIC_FIELD(field, flag) ((flag) ?\ +#define GET_METRIC_FIELD(field) ((adev->flags & AMD_IS_APU) ?\ (metrics_a->field) : (metrics_x->field)) struct smu_v13_0_6_dpm_map { @@ -738,7 +732,7 @@ static int smu_v13_0_6_setup_driver_pptable(struct smu_context *smu) MetricsTableA_t *metrics_a = (MetricsTableA_t *)smu_table->metrics_table; struct PPTable_t *pptable = (struct PPTable_t *)smu_table->driver_pptable; - bool flag = smu_v13_0_6_is_unified_metrics(smu); + struct amdgpu_device *adev = smu->adev; int ret, i, retry = 100; uint32_t table_version; @@ -750,7 +744,7 @@ static int smu_v13_0_6_setup_driver_pptable(struct smu_context *smu) return ret; /* Ensure that metrics have been updated */ - if (GET_METRIC_FIELD(AccumulationCounter, flag)) + if (GET_METRIC_FIELD(AccumulationCounter)) break; usleep_range(1000, 1100); @@ -767,29 +761,29 @@ static int smu_v13_0_6_setup_driver_pptable(struct smu_context *smu) table_version; pptable->MaxSocketPowerLimit = - SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketPowerLimit, flag)); + SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketPowerLimit)); pptable->MaxGfxclkFrequency = - SMUQ10_ROUND(GET_METRIC_FIELD(MaxGfxclkFrequency, flag)); + SMUQ10_ROUND(GET_METRIC_FIELD(MaxGfxclkFrequency)); pptable->MinGfxclkFrequency = - SMUQ10_ROUND(GET_METRIC_FIELD(MinGfxclkFrequency, flag)); + SMUQ10_ROUND(GET_METRIC_FIELD(MinGfxclkFrequency)); for (i = 0; i < 4; ++i) { pptable->FclkFrequencyTable[i] = - SMUQ10_ROUND(GET_METRIC_FIELD(FclkFrequencyTable, flag)[i]); + SMUQ10_ROUND(GET_METRIC_FIELD(FclkFrequencyTable)[i]); pptable->UclkFrequencyTable[i] = - SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequencyTable, flag)[i]); + SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequencyTable)[i]); pptable->SocclkFrequencyTable[i] = SMUQ10_ROUND( - GET_METRIC_FIELD(SocclkFrequencyTable, flag)[i]); + GET_METRIC_FIELD(SocclkFrequencyTable)[i]); pptable->VclkFrequencyTable[i] = - SMUQ10_ROUND(GET_METRIC_FIELD(VclkFrequencyTable, flag)[i]); + SMUQ10_ROUND(GET_METRIC_FIELD(VclkFrequencyTable)[i]); pptable->DclkFrequencyTable[i] = - SMUQ10_ROUND(GET_METRIC_FIELD(DclkFrequencyTable, flag)[i]); + SMUQ10_ROUND(GET_METRIC_FIELD(DclkFrequencyTable)[i]); pptable->LclkFrequencyTable[i] = - SMUQ10_ROUND(GET_METRIC_FIELD(LclkFrequencyTable, flag)[i]); + SMUQ10_ROUND(GET_METRIC_FIELD(LclkFrequencyTable)[i]); } /* use AID0 serial number by default */ - pptable->PublicSerialNumber_AID = GET_METRIC_FIELD(PublicSerialNumber_AID, flag)[0]; + pptable->PublicSerialNumber_AID = GET_METRIC_FIELD(PublicSerialNumber_AID)[0]; pptable->Init = true; } @@ -1121,7 +1115,6 @@ static int smu_v13_0_6_get_smu_metrics_data(struct smu_context *smu, struct smu_table_context *smu_table = &smu->smu_table; MetricsTableX_t *metrics_x = (MetricsTableX_t *)smu_table->metrics_table; MetricsTableA_t *metrics_a = (MetricsTableA_t *)smu_table->metrics_table; - bool flag = smu_v13_0_6_is_unified_metrics(smu); struct amdgpu_device *adev = smu->adev; int ret = 0; int xcc_id; @@ -1136,50 +1129,50 @@ static int smu_v13_0_6_get_smu_metrics_data(struct smu_context *smu, case METRICS_AVERAGE_GFXCLK: if (smu->smc_fw_version >= 0x552F00) { xcc_id = GET_INST(GC, 0); - *value = SMUQ10_ROUND(GET_METRIC_FIELD(GfxclkFrequency, flag)[xcc_id]); + *value = SMUQ10_ROUND(GET_METRIC_FIELD(GfxclkFrequency)[xcc_id]); } else { *value = 0; } break; case METRICS_CURR_SOCCLK: case METRICS_AVERAGE_SOCCLK: - *value = SMUQ10_ROUND(GET_METRIC_FIELD(SocclkFrequency, flag)[0]); + *value = SMUQ10_ROUND(GET_METRIC_FIELD(SocclkFrequency)[0]); break; case METRICS_CURR_UCLK: case METRICS_AVERAGE_UCLK: - *value = SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequency, flag)); + *value = SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequency)); break; case METRICS_CURR_VCLK: - *value = SMUQ10_ROUND(GET_METRIC_FIELD(VclkFrequency, flag)[0]); + *value = SMUQ10_ROUND(GET_METRIC_FIELD(VclkFrequency)[0]); break; case METRICS_CURR_DCLK: - *value = SMUQ10_ROUND(GET_METRIC_FIELD(DclkFrequency, flag)[0]); + *value = SMUQ10_ROUND(GET_METRIC_FIELD(DclkFrequency)[0]); break; case METRICS_CURR_FCLK: - *value = SMUQ10_ROUND(GET_METRIC_FIELD(FclkFrequency, flag)); + *value = SMUQ10_ROUND(GET_METRIC_FIELD(FclkFrequency)); break; case METRICS_AVERAGE_GFXACTIVITY: - *value = SMUQ10_ROUND(GET_METRIC_FIELD(SocketGfxBusy, flag)); + *value = SMUQ10_ROUND(GET_METRIC_FIELD(SocketGfxBusy)); break; case METRICS_AVERAGE_MEMACTIVITY: - *value = SMUQ10_ROUND(GET_METRIC_FIELD(DramBandwidthUtilization, flag)); + *value = SMUQ10_ROUND(GET_METRIC_FIELD(DramBandwidthUtilization)); break; case METRICS_CURR_SOCKETPOWER: - *value = SMUQ10_ROUND(GET_METRIC_FIELD(SocketPower, flag)) << 8; + *value = SMUQ10_ROUND(GET_METRIC_FIELD(SocketPower)) << 8; break; case METRICS_TEMPERATURE_HOTSPOT: - *value = SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketTemperature, flag)) * + *value = SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketTemperature)) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; break; case METRICS_TEMPERATURE_MEM: - *value = SMUQ10_ROUND(GET_METRIC_FIELD(MaxHbmTemperature, flag)) * + *value = SMUQ10_ROUND(GET_METRIC_FIELD(MaxHbmTemperature)) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; break; /* This is the max of all VRs and not just SOC VR. * No need to define another data type for the same. */ case METRICS_TEMPERATURE_VRSOC: - *value = SMUQ10_ROUND(GET_METRIC_FIELD(MaxVrTemperature, flag)) * + *value = SMUQ10_ROUND(GET_METRIC_FIELD(MaxVrTemperature)) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; break; default: @@ -2467,7 +2460,6 @@ static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table struct smu_table_context *smu_table = &smu->smu_table; struct gpu_metrics_v1_5 *gpu_metrics = (struct gpu_metrics_v1_5 *)smu_table->gpu_metrics_table; - bool flag = smu_v13_0_6_is_unified_metrics(smu); struct amdgpu_device *adev = smu->adev; int ret = 0, xcc_id, inst, i, j; MetricsTableX_t *metrics_x; @@ -2486,50 +2478,50 @@ static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 5); gpu_metrics->temperature_hotspot = - SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketTemperature, flag)); + SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketTemperature)); /* Individual HBM stack temperature is not reported */ gpu_metrics->temperature_mem = - SMUQ10_ROUND(GET_METRIC_FIELD(MaxHbmTemperature, flag)); + SMUQ10_ROUND(GET_METRIC_FIELD(MaxHbmTemperature)); /* Reports max temperature of all voltage rails */ gpu_metrics->temperature_vrsoc = - SMUQ10_ROUND(GET_METRIC_FIELD(MaxVrTemperature, flag)); + SMUQ10_ROUND(GET_METRIC_FIELD(MaxVrTemperature)); gpu_metrics->average_gfx_activity = - SMUQ10_ROUND(GET_METRIC_FIELD(SocketGfxBusy, flag)); + SMUQ10_ROUND(GET_METRIC_FIELD(SocketGfxBusy)); gpu_metrics->average_umc_activity = - SMUQ10_ROUND(GET_METRIC_FIELD(DramBandwidthUtilization, flag)); + SMUQ10_ROUND(GET_METRIC_FIELD(DramBandwidthUtilization)); gpu_metrics->curr_socket_power = - SMUQ10_ROUND(GET_METRIC_FIELD(SocketPower, flag)); + SMUQ10_ROUND(GET_METRIC_FIELD(SocketPower)); /* Energy counter reported in 15.259uJ (2^-16) units */ - gpu_metrics->energy_accumulator = GET_METRIC_FIELD(SocketEnergyAcc, flag); + gpu_metrics->energy_accumulator = GET_METRIC_FIELD(SocketEnergyAcc); for (i = 0; i < MAX_GFX_CLKS; i++) { xcc_id = GET_INST(GC, i); if (xcc_id >= 0) gpu_metrics->current_gfxclk[i] = - SMUQ10_ROUND(GET_METRIC_FIELD(GfxclkFrequency, flag)[xcc_id]); + SMUQ10_ROUND(GET_METRIC_FIELD(GfxclkFrequency)[xcc_id]); if (i < MAX_CLKS) { gpu_metrics->current_socclk[i] = - SMUQ10_ROUND(GET_METRIC_FIELD(SocclkFrequency, flag)[i]); + SMUQ10_ROUND(GET_METRIC_FIELD(SocclkFrequency)[i]); inst = GET_INST(VCN, i); if (inst >= 0) { gpu_metrics->current_vclk0[i] = - SMUQ10_ROUND(GET_METRIC_FIELD(VclkFrequency, flag)[inst]); + SMUQ10_ROUND(GET_METRIC_FIELD(VclkFrequency)[inst]); gpu_metrics->current_dclk0[i] = - SMUQ10_ROUND(GET_METRIC_FIELD(DclkFrequency, flag)[inst]); + SMUQ10_ROUND(GET_METRIC_FIELD(DclkFrequency)[inst]); } } } - gpu_metrics->current_uclk = SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequency, flag)); + gpu_metrics->current_uclk = SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequency)); /* Throttle status is not reported through metrics now */ gpu_metrics->throttle_status = 0; /* Clock Lock Status. Each bit corresponds to each GFXCLK instance */ - gpu_metrics->gfxclk_lock_status = GET_METRIC_FIELD(GfxLockXCDMak, flag) >> GET_INST(GC, 0); + gpu_metrics->gfxclk_lock_status = GET_METRIC_FIELD(GfxLockXCDMak) >> GET_INST(GC, 0); if (!(adev->flags & AMD_IS_APU)) { /*Check smu version, PCIE link speed and width will be reported from pmfw metric @@ -2570,22 +2562,22 @@ static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); gpu_metrics->gfx_activity_acc = - SMUQ10_ROUND(GET_METRIC_FIELD(SocketGfxBusyAcc, flag)); + SMUQ10_ROUND(GET_METRIC_FIELD(SocketGfxBusyAcc)); gpu_metrics->mem_activity_acc = - SMUQ10_ROUND(GET_METRIC_FIELD(DramBandwidthUtilizationAcc, flag)); + SMUQ10_ROUND(GET_METRIC_FIELD(DramBandwidthUtilizationAcc)); for (i = 0; i < NUM_XGMI_LINKS; i++) { gpu_metrics->xgmi_read_data_acc[i] = - SMUQ10_ROUND(GET_METRIC_FIELD(XgmiReadDataSizeAcc, flag)[i]); + SMUQ10_ROUND(GET_METRIC_FIELD(XgmiReadDataSizeAcc)[i]); gpu_metrics->xgmi_write_data_acc[i] = - SMUQ10_ROUND(GET_METRIC_FIELD(XgmiWriteDataSizeAcc, flag)[i]); + SMUQ10_ROUND(GET_METRIC_FIELD(XgmiWriteDataSizeAcc)[i]); } for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { inst = GET_INST(JPEG, i); for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { gpu_metrics->jpeg_activity[(i * adev->jpeg.num_jpeg_rings) + j] = - SMUQ10_ROUND(GET_METRIC_FIELD(JpegBusy, flag) + SMUQ10_ROUND(GET_METRIC_FIELD(JpegBusy) [(inst * adev->jpeg.num_jpeg_rings) + j]); } } @@ -2593,13 +2585,13 @@ static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { inst = GET_INST(VCN, i); gpu_metrics->vcn_activity[i] = - SMUQ10_ROUND(GET_METRIC_FIELD(VcnBusy, flag)[inst]); + SMUQ10_ROUND(GET_METRIC_FIELD(VcnBusy)[inst]); } - gpu_metrics->xgmi_link_width = SMUQ10_ROUND(GET_METRIC_FIELD(XgmiWidth, flag)); - gpu_metrics->xgmi_link_speed = SMUQ10_ROUND(GET_METRIC_FIELD(XgmiBitrate, flag)); + gpu_metrics->xgmi_link_width = SMUQ10_ROUND(GET_METRIC_FIELD(XgmiWidth)); + gpu_metrics->xgmi_link_speed = SMUQ10_ROUND(GET_METRIC_FIELD(XgmiBitrate)); - gpu_metrics->firmware_timestamp = GET_METRIC_FIELD(Timestamp, flag); + gpu_metrics->firmware_timestamp = GET_METRIC_FIELD(Timestamp); *table = (void *)gpu_metrics; kfree(metrics_x); From fc127011fcd360bf271309a414ee65d37fc5a43f Mon Sep 17 00:00:00 2001 From: Kent Russell Date: Tue, 10 Sep 2024 09:21:25 -0400 Subject: [PATCH 1585/1868] drm/amdkfd: Move queue fs deletion after destroy check We were removing the kernfs entry for queue info before checking if the queue could be destroyed. If it failed to get destroyed (e.g. during some GPU resets), then we would try to delete it later during pqm teardown, but the file was already removed. This led to a kernel WARN trying to remove size, gpuid and type. Move the remove to after the destroy check. Signed-off-by: Kent Russell Reviewed-by: Jonathan Kim --- drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c index 120f36804618a..74427fa6662d3 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c @@ -523,7 +523,6 @@ int pqm_destroy_queue(struct process_queue_manager *pqm, unsigned int qid) if (retval == -ERESTARTSYS) return retval; - kfd_procfs_del_queue(pqn->q); if (retval) { pr_err("Pasid 0x%x destroy queue %d failed, ret %d\n", pqm->process->pasid, @@ -531,6 +530,7 @@ int pqm_destroy_queue(struct process_queue_manager *pqm, unsigned int qid) if (retval != -ETIME) goto err_destroy_queue; } + kfd_procfs_del_queue(pqn->q); kfd_queue_release_buffers(pdd, &pqn->q->properties); pqm_clean_queue_resource(pqm, pqn); uninit_queue(pqn->q); From ee17ed9b0dceb1417fcd5f9eee650ed4a584cbbe Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 20 Sep 2024 18:37:18 +0800 Subject: [PATCH 1586/1868] drm/amdkcl: wrap code out of HAVE_DRM_DP_MST_DSC_AUX_FOR_PORT HAVE_DRM_DP_MST_DSC_AUX_FOR_PORT is for validate_dsc_caps_on_connector. It should not be guarding retrieve_downstream_port_device. Signed-off-by: Kent Russell --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 89abb820f32ff..f0f6055ef5745 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -306,6 +306,7 @@ static bool validate_dsc_caps_on_connector(struct amdgpu_dm_connector *aconnecto return true; } #endif +#endif static bool retrieve_downstream_port_device(struct amdgpu_dm_connector *aconnector) { @@ -325,7 +326,6 @@ static bool retrieve_downstream_port_device(struct amdgpu_dm_connector *aconnect return true; } -#endif static int dm_dp_mst_get_modes(struct drm_connector *connector) { @@ -448,11 +448,10 @@ static int dm_dp_mst_get_modes(struct drm_connector *connector) memset(&aconnector->dc_sink->dsc_caps, 0, sizeof(aconnector->dc_sink->dsc_caps)); #endif - +#endif if (!retrieve_downstream_port_device(aconnector)) memset(&aconnector->mst_downstream_port_present, 0, sizeof(aconnector->mst_downstream_port_present)); -#endif } } From 6f4baf41cf41b8052352e19764b246b47dd03c25 Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Fri, 20 Sep 2024 15:22:24 +0800 Subject: [PATCH 1587/1868] amd/amdgpu: Reduce unnecessary repetitive GPU resets In multiple GPUs case, after a GPU has started resetting all GPUs on hive, other GPUs do not need to trigger GPU reset again. Signed-off-by: YiPeng Chai Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index b017be040b49f..0d214fc3a39b1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -4311,8 +4311,27 @@ int amdgpu_ras_reset_gpu(struct amdgpu_device *adev) ras->gpu_reset_flags |= AMDGPU_RAS_GPU_RESET_MODE1_RESET; } - if (atomic_cmpxchg(&ras->in_recovery, 0, 1) == 0) + if (atomic_cmpxchg(&ras->in_recovery, 0, 1) == 0) { + struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev); + int hive_ras_recovery = 0; + + if (hive) { + hive_ras_recovery = atomic_read(&hive->ras_recovery); + amdgpu_put_xgmi_hive(hive); + } + /* In the case of multiple GPUs, after a GPU has started + * resetting all GPUs on hive, other GPUs do not need to + * trigger GPU reset again. + */ + if (!hive_ras_recovery) + amdgpu_reset_domain_schedule(ras->adev->reset_domain, &ras->recovery_work); + else + atomic_set(&ras->in_recovery, 0); + } else { + flush_work(&ras->recovery_work); amdgpu_reset_domain_schedule(ras->adev->reset_domain, &ras->recovery_work); + } + return 0; } From e6585817ebdb8f0fbfa0549948507b27bc7ecdd9 Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Fri, 20 Sep 2024 15:22:24 +0800 Subject: [PATCH 1588/1868] amd/amdgpu: Reduce unnecessary repetitive GPU resets In multiple GPUs case, after a GPU has started resetting all GPUs on hive, other GPUs do not need to trigger GPU reset again. Signed-off-by: YiPeng Chai Reviewed-by: Hawking Zhang (cherry picked from commit 6f4baf41cf41b8052352e19764b246b47dd03c25) Change-Id: I80a74bb50619468e7698c3429442c0fceb72e0da --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index dbfc41ddc3c71..7d48541b03d87 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -4306,8 +4306,27 @@ int amdgpu_ras_reset_gpu(struct amdgpu_device *adev) ras->gpu_reset_flags |= AMDGPU_RAS_GPU_RESET_MODE1_RESET; } - if (atomic_cmpxchg(&ras->in_recovery, 0, 1) == 0) + if (atomic_cmpxchg(&ras->in_recovery, 0, 1) == 0) { + struct amdgpu_hive_info *hive = amdgpu_get_xgmi_hive(adev); + int hive_ras_recovery = 0; + + if (hive) { + hive_ras_recovery = atomic_read(&hive->ras_recovery); + amdgpu_put_xgmi_hive(hive); + } + /* In the case of multiple GPUs, after a GPU has started + * resetting all GPUs on hive, other GPUs do not need to + * trigger GPU reset again. + */ + if (!hive_ras_recovery) + amdgpu_reset_domain_schedule(ras->adev->reset_domain, &ras->recovery_work); + else + atomic_set(&ras->in_recovery, 0); + } else { + flush_work(&ras->recovery_work); amdgpu_reset_domain_schedule(ras->adev->reset_domain, &ras->recovery_work); + } + return 0; } From 79aabc5e18c656633d383e4baea361c04f7026a1 Mon Sep 17 00:00:00 2001 From: Feifei Xu Date: Thu, 12 Sep 2024 18:08:07 +0800 Subject: [PATCH 1589/1868] drm/amdgpu: Add psp command CONFIG_SQ_PERFMON Add support for enable/disable perfmon profiling. Signed-off-by: Feifei Xu Reviewed-by: Hawking Zhang Reviewed-by: Lijo Lazar Reviewed-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 40 ++++++++++++++++++++++++- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 4 +++ drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h | 12 ++++++++ 3 files changed, 55 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index e5c8b7dac8cbc..0e2377c0ad86a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -639,6 +639,8 @@ static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id) return "AUTOLOAD_RLC"; case GFX_CMD_ID_BOOT_CFG: return "BOOT_CFG"; + case GFX_CMD_ID_CONFIG_SQ_PERFMON: + return "CONFIG_SQ_PERFMON"; default: return "UNKNOWN CMD"; } @@ -3736,8 +3738,44 @@ int psp_init_cap_microcode(struct psp_context *psp, const char *chip_name) return err; } +int psp_config_sq_perfmon(struct psp_context *psp, + uint32_t xcp_id, bool core_override_enable, + bool reg_override_enable, bool perfmon_override_enable) +{ + int ret; + + if (amdgpu_sriov_vf(psp->adev)) + return 0; + + if (xcp_id > MAX_XCP) { + dev_err(psp->adev->dev, "invalid xcp_id %d\n", xcp_id); + return -EINVAL; + } + + if (amdgpu_ip_version(psp->adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6)) { + dev_err(psp->adev->dev, "Unsupported MP0 version 0x%x for CONFIG_SQ_PERFMON command\n", + amdgpu_ip_version(psp->adev, MP0_HWIP, 0)); + return -EINVAL; + } + struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp); + + cmd->cmd_id = GFX_CMD_ID_CONFIG_SQ_PERFMON; + cmd->cmd.config_sq_perfmon.gfx_xcp_mask = BIT_MASK(xcp_id); + cmd->cmd.config_sq_perfmon.core_override = core_override_enable; + cmd->cmd.config_sq_perfmon.reg_override = reg_override_enable; + cmd->cmd.config_sq_perfmon.perfmon_override = perfmon_override_enable; + + ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); + if (ret) + dev_warn(psp->adev->dev, "PSP failed to config sq: xcp%d core%d reg%d perfmon%d\n", + xcp_id, core_override_enable, reg_override_enable, perfmon_override_enable); + + release_psp_cmd_buf(psp); + return ret; +} + static int psp_set_clockgating_state(void *handle, - enum amd_clockgating_state state) + enum amd_clockgating_state state) { return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h index e8abbbcb43266..f61ba076573c3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h @@ -557,4 +557,8 @@ int is_psp_fw_valid(struct psp_bin_desc bin); int amdgpu_psp_wait_for_bootloader(struct amdgpu_device *adev); bool amdgpu_psp_get_ras_capability(struct psp_context *psp); + +int psp_config_sq_perfmon(struct psp_context *psp, uint32_t xcp_id, + bool core_override_enable, bool reg_override_enable, bool perfmon_override_enable); + #endif diff --git a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h b/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h index 37b5ddd6f13b3..604301371e4f6 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h +++ b/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h @@ -103,6 +103,8 @@ enum psp_gfx_cmd_id GFX_CMD_ID_AUTOLOAD_RLC = 0x00000021, /* Indicates all graphics fw loaded, start RLC autoload */ GFX_CMD_ID_BOOT_CFG = 0x00000022, /* Boot Config */ GFX_CMD_ID_SRIOV_SPATIAL_PART = 0x00000027, /* Configure spatial partitioning mode */ + /*IDs of performance monitoring/profiling*/ + GFX_CMD_ID_CONFIG_SQ_PERFMON = 0x00000046, /* Config CGTT_SQ_CLK_CTRL */ }; /* PSP boot config sub-commands */ @@ -351,6 +353,15 @@ struct psp_gfx_cmd_sriov_spatial_part { uint32_t override_this_aid; }; +/*Structure for sq performance monitoring/profiling enable/disable*/ +struct psp_gfx_cmd_config_sq_perfmon { + uint32_t gfx_xcp_mask; + uint8_t core_override; + uint8_t reg_override; + uint8_t perfmon_override; + uint8_t reserved[5]; +}; + /* All GFX ring buffer commands. */ union psp_gfx_commands { @@ -365,6 +376,7 @@ union psp_gfx_commands struct psp_gfx_cmd_load_toc cmd_load_toc; struct psp_gfx_cmd_boot_cfg boot_cfg; struct psp_gfx_cmd_sriov_spatial_part cmd_spatial_part; + struct psp_gfx_cmd_config_sq_perfmon config_sq_perfmon; }; struct psp_gfx_uresp_reserved From 5697d096f17f1a8bb336403f2daac4ec68762d3f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Wed, 5 Jun 2024 16:26:22 +0200 Subject: [PATCH 1590/1868] drm/amdgpu: explicitely set the AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS flag MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Instead of having that in the amdgpu_bo_pin() function applied for all pinned BOs. Signed-off-by: Christian König Acked-by: Lijo Lazar --- drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 2 ++ drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 1 - drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 1 + drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 2 ++ drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 2 ++ drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 2 ++ drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 2 ++ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 1 + drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c | 1 + 9 files changed, 13 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index d2dcc1aa49571..6604fdc6c2e8c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -234,6 +234,7 @@ int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc, } if (!adev->enable_virtual_display) { + new_abo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; r = amdgpu_bo_pin(new_abo, amdgpu_display_supported_domains(adev, new_abo->flags)); if (unlikely(r != 0)) { @@ -1823,6 +1824,7 @@ int amdgpu_display_resume_helper(struct amdgpu_device *adev) r = amdgpu_bo_reserve(aobj, true); if (r == 0) { + aobj->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; r = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM); if (r != 0) dev_err(adev->dev, "Failed to pin cursor BO (%d)\n", r); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index 14a10e73f0575..7dcf45bf9b332 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -974,7 +974,6 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, */ int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain) { - bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; return amdgpu_bo_pin_restricted(bo, domain, 0, 0); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c index 0e5bfeb1dbf05..b2b0cfadc6d22 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c @@ -383,6 +383,7 @@ static int amdgpu_vkms_prepare_fb(struct drm_plane *plane, else domain = AMDGPU_GEM_DOMAIN_VRAM; + rbo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; r = amdgpu_bo_pin(rbo, domain); if (unlikely(r != 0)) { if (r != -ERESTARTSYS) diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index 9ab3c77f72034..e6006da6264e0 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -1887,6 +1887,7 @@ static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc, return r; if (!atomic) { + abo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM); if (unlikely(r != 0)) { amdgpu_bo_unreserve(abo); @@ -2407,6 +2408,7 @@ static int dce_v10_0_crtc_cursor_set2(struct drm_crtc *crtc, return ret; } + aobj->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM); amdgpu_bo_unreserve(aobj); if (ret) { diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index 612c6c88ef845..096ee0e4302d9 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -1937,6 +1937,7 @@ static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc, return r; if (!atomic) { + abo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM); if (unlikely(r != 0)) { amdgpu_bo_unreserve(abo); @@ -2491,6 +2492,7 @@ static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc, return ret; } + aobj->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM); amdgpu_bo_unreserve(aobj); if (ret) { diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c index 850bad398d140..14ea27d3fd51c 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c @@ -1867,6 +1867,7 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc, return r; if (!atomic) { + abo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM); if (unlikely(r != 0)) { amdgpu_bo_unreserve(abo); @@ -2327,6 +2328,7 @@ static int dce_v6_0_crtc_cursor_set2(struct drm_crtc *crtc, return ret; } + aobj->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM); amdgpu_bo_unreserve(aobj); if (ret) { diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index 8d032587fac5c..ddbe5c79f6c72 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -1833,6 +1833,7 @@ static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc, return r; if (!atomic) { + abo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM); if (unlikely(r != 0)) { amdgpu_bo_unreserve(abo); @@ -2325,6 +2326,7 @@ static int dce_v8_0_crtc_cursor_set2(struct drm_crtc *crtc, return ret; } + aobj->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM); amdgpu_bo_unreserve(aobj); if (ret) { diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c index 13d26f67e7539..149672e44a93d 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c @@ -1036,6 +1036,7 @@ static int amdgpu_dm_plane_helper_prepare_fb(struct drm_plane *plane, else domain = AMDGPU_GEM_DOMAIN_VRAM; + rbo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; r = amdgpu_bo_pin(rbo, domain); if (unlikely(r != 0)) { if (r != -ERESTARTSYS) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c index 14ddb3850582d..faf19d03312fa 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c @@ -115,6 +115,7 @@ static int amdgpu_dm_wb_prepare_job(struct drm_writeback_connector *wb_connector domain = amdgpu_display_supported_domains(adev, rbo->flags); + rbo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS; r = amdgpu_bo_pin(rbo, domain); if (unlikely(r != 0)) { if (r != -ERESTARTSYS) From d5e0891d1910679f7b13c122cd2ca0b09cda61d9 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Wed, 5 Jun 2024 16:34:49 +0200 Subject: [PATCH 1591/1868] drm/amdgpu: remove amdgpu_pin_restricted() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We haven't used the functionality to pin BOs in a certain range at all while the driver existed. Just nuke it. Signed-off-by: Christian König Acked-by: Lijo Lazar --- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 56 ++----------------- drivers/gpu/drm/amd/amdgpu/amdgpu_object.h | 2 - 3 files changed, 6 insertions(+), 54 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 15829496a87fe..049723c6a3926 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -1592,7 +1592,7 @@ int amdgpu_amdkfd_gpuvm_pin_bo(struct amdgpu_bo *bo, u32 domain) } } - ret = amdgpu_bo_pin_restricted(bo, domain, 0, 0); + ret = amdgpu_bo_pin(bo, domain); if (ret) pr_err("Error in Pinning BO to domain: %d\n", domain); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c index 7dcf45bf9b332..2a4a7d2056f84 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c @@ -839,29 +839,22 @@ void amdgpu_bo_unref(struct amdgpu_bo **bo) } /** - * amdgpu_bo_pin_restricted - pin an &amdgpu_bo buffer object + * amdgpu_bo_pin - pin an &amdgpu_bo buffer object * @bo: &amdgpu_bo buffer object to be pinned * @domain: domain to be pinned to - * @min_offset: the start of requested address range - * @max_offset: the end of requested address range * - * Pins the buffer object according to requested domain and address range. If - * the memory is unbound gart memory, binds the pages into gart table. Adjusts - * pin_count and pin_size accordingly. + * Pins the buffer object according to requested domain. If the memory is + * unbound gart memory, binds the pages into gart table. Adjusts pin_count and + * pin_size accordingly. * * Pinning means to lock pages in memory along with keeping them at a fixed * offset. It is required when a buffer can not be moved, for example, when * a display buffer is being scanned out. * - * Compared with amdgpu_bo_pin(), this function gives more flexibility on - * where to pin a buffer if there are specific restrictions on where a buffer - * must be located. - * * Returns: * 0 for success or a negative error code on failure. */ -int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, - u64 min_offset, u64 max_offset) +int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain) { struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); struct ttm_operation_ctx ctx = { false, false }; @@ -870,9 +863,6 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) return -EPERM; - if (WARN_ON_ONCE(min_offset > max_offset)) - return -EINVAL; - /* Check domain to be pinned to against preferred domains */ if (bo->preferred_domains & domain) domain = bo->preferred_domains & domain; @@ -898,14 +888,6 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, return -EINVAL; ttm_bo_pin(&bo->tbo); - - if (max_offset != 0) { - u64 domain_start = amdgpu_ttm_domain_start(adev, - mem_type); - WARN_ON_ONCE(max_offset < - (amdgpu_bo_gpu_offset(bo) - domain_start)); - } - return 0; } @@ -924,17 +906,6 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; amdgpu_bo_placement_from_domain(bo, domain); for (i = 0; i < bo->placement.num_placement; i++) { - unsigned int fpfn, lpfn; - - fpfn = min_offset >> PAGE_SHIFT; - lpfn = max_offset >> PAGE_SHIFT; - - if (fpfn > bo->placements[i].fpfn) - bo->placements[i].fpfn = fpfn; - if (!bo->placements[i].lpfn || - (lpfn && lpfn < bo->placements[i].lpfn)) - bo->placements[i].lpfn = lpfn; - if (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS && bo->placements[i].mem_type == TTM_PL_VRAM) bo->placements[i].flags |= TTM_PL_FLAG_CONTIGUOUS; @@ -960,23 +931,6 @@ int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, return r; } -/** - * amdgpu_bo_pin - pin an &amdgpu_bo buffer object - * @bo: &amdgpu_bo buffer object to be pinned - * @domain: domain to be pinned to - * - * A simple wrapper to amdgpu_bo_pin_restricted(). - * Provides a simpler API for buffers that do not have any strict restrictions - * on where a buffer must be located. - * - * Returns: - * 0 for success or a negative error code on failure. - */ -int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain) -{ - return amdgpu_bo_pin_restricted(bo, domain, 0, 0); -} - /** * amdgpu_bo_unpin - unpin an &amdgpu_bo buffer object * @bo: &amdgpu_bo buffer object to be unpinned diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h index 6e28b44d25c73..525cd58090b89 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.h @@ -320,8 +320,6 @@ void amdgpu_bo_kunmap(struct amdgpu_bo *bo); struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo); void amdgpu_bo_unref(struct amdgpu_bo **bo); int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain); -int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, - u64 min_offset, u64 max_offset); void amdgpu_bo_unpin(struct amdgpu_bo *bo); int amdgpu_bo_init(struct amdgpu_device *adev); void amdgpu_bo_fini(struct amdgpu_device *adev); From a728458ea43d38ebd853af7423fd2f309e60a509 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 13 Sep 2024 16:22:01 -0400 Subject: [PATCH 1592/1868] drm/amdgpu/bios: split vbios fetching between APU and dGPU We need some different logic for dGPUs and the APU path can be simplified because there are some methods which are never used on APUs. This also fixes a regression on some older APUs causing the driver to fetch the unpatched ROM image rather than the patched image. Fixes: 9c081c11c621 ("drm/amdgpu: Reorder to read EFI exported ROM first") Reviewed-by: George Zhang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c | 47 +++++++++++++++++++++++- 1 file changed, 45 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c index 42e64bce661e4..e8f62d718167b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c @@ -414,7 +414,36 @@ static inline bool amdgpu_acpi_vfct_bios(struct amdgpu_device *adev) } #endif -bool amdgpu_get_bios(struct amdgpu_device *adev) +static bool amdgpu_get_bios_apu(struct amdgpu_device *adev) +{ + if (amdgpu_acpi_vfct_bios(adev)) { + dev_info(adev->dev, "Fetched VBIOS from VFCT\n"); + goto success; + } + + if (igp_read_bios_from_vram(adev)) { + dev_info(adev->dev, "Fetched VBIOS from VRAM BAR\n"); + goto success; + } + + if (amdgpu_read_bios(adev)) { + dev_info(adev->dev, "Fetched VBIOS from ROM BAR\n"); + goto success; + } + + if (amdgpu_read_platform_bios(adev)) { + dev_info(adev->dev, "Fetched VBIOS from platform\n"); + goto success; + } + + dev_err(adev->dev, "Unable to locate a BIOS ROM\n"); + return false; + +success: + return true; +} + +static bool amdgpu_get_bios_dgpu(struct amdgpu_device *adev) { if (amdgpu_atrm_get_bios(adev)) { dev_info(adev->dev, "Fetched VBIOS from ATRM\n"); @@ -455,10 +484,24 @@ bool amdgpu_get_bios(struct amdgpu_device *adev) return false; success: - adev->is_atom_fw = adev->asic_type >= CHIP_VEGA10; return true; } +bool amdgpu_get_bios(struct amdgpu_device *adev) +{ + bool found; + + if (adev->flags & AMD_IS_APU) + found = amdgpu_get_bios_apu(adev); + else + found = amdgpu_get_bios_dgpu(adev); + + if (found) + adev->is_atom_fw = adev->asic_type >= CHIP_VEGA10; + + return found; +} + /* helper function for soc15 and onwards to read bios from rom */ bool amdgpu_soc15_read_bios_from_rom(struct amdgpu_device *adev, u8 *bios, u32 length_bytes) From 535339b1029a0c95e72f5ee4531aa9d724a69f9a Mon Sep 17 00:00:00 2001 From: Tobias Jakobi Date: Mon, 16 Sep 2024 14:54:05 +0200 Subject: [PATCH 1593/1868] drm/amd/display: handle nulled pipe context in DCE110's set_drr() As set_drr() is called from IRQ context, it can happen that the pipe context has been nulled by dc_state_destruct(). Apply the same protection here that is already present for dcn35_set_drr() and dcn10_set_drr(). I.e. fetch the tg pointer first (to avoid a race with dc_state_destruct()), and then check the local copy before using it. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3142 Fixes: 06ad7e164256 ("drm/amd/display: Destroy DC context while keeping DML and DML2") Acked-by: Alex Deucher Signed-off-by: Tobias Jakobi Signed-off-by: Alex Deucher --- .../amd/display/dc/hwss/dce110/dce110_hwseq.c | 21 ++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c index aa7479b318982..4fbed0298adfa 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c @@ -2096,13 +2096,20 @@ static void set_drr(struct pipe_ctx **pipe_ctx, * as well. */ for (i = 0; i < num_pipes; i++) { - pipe_ctx[i]->stream_res.tg->funcs->set_drr( - pipe_ctx[i]->stream_res.tg, ¶ms); - - if (adjust.v_total_max != 0 && adjust.v_total_min != 0) - pipe_ctx[i]->stream_res.tg->funcs->set_static_screen_control( - pipe_ctx[i]->stream_res.tg, - event_triggers, num_frames); + /* dc_state_destruct() might null the stream resources, so fetch tg + * here first to avoid a race condition. The lifetime of the pointee + * itself (the timing_generator object) is not a problem here. + */ + struct timing_generator *tg = pipe_ctx[i]->stream_res.tg; + + if ((tg != NULL) && tg->funcs) { + if (tg->funcs->set_drr) + tg->funcs->set_drr(tg, ¶ms); + if (adjust.v_total_max != 0 && adjust.v_total_min != 0) + if (tg->funcs->set_static_screen_control) + tg->funcs->set_static_screen_control( + tg, event_triggers, num_frames); + } } } From 28d8a37c8c9c1457369b67c5ebe2b300c9160e4b Mon Sep 17 00:00:00 2001 From: "Dr. David Alan Gilbert" Date: Sun, 15 Sep 2024 15:01:44 +0100 Subject: [PATCH 1594/1868] drm/amd/display: Remove unused function bios_get_vga_enabled_displays bios_get_vga_enabled_displays has been unused since commit 5a8132b9f606 ("drm/amd/display: remove dead dc vbios code") Remove it. Acked-by: Alex Deucher Signed-off-by: Dr. David Alan Gilbert Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c | 7 ------- drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.h | 1 - 2 files changed, 8 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c index adc710fe4a453..8d2cf95ae7393 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c +++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.c @@ -78,10 +78,3 @@ void bios_set_scratch_critical_state( uint32_t critial_state = state ? 1 : 0; REG_UPDATE(BIOS_SCRATCH_6, S6_CRITICAL_STATE, critial_state); } - -uint32_t bios_get_vga_enabled_displays( - struct dc_bios *bios) -{ - return REG_READ(BIOS_SCRATCH_3) & 0XFFFF; -} - diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.h b/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.h index e1b4a40a353db..ab162f2fe5776 100644 --- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.h +++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser_helper.h @@ -34,7 +34,6 @@ uint8_t *bios_get_image(struct dc_bios *bp, uint32_t offset, bool bios_is_accelerated_mode(struct dc_bios *bios); void bios_set_scratch_acc_mode_change(struct dc_bios *bios, uint32_t state); void bios_set_scratch_critical_state(struct dc_bios *bios, bool state); -uint32_t bios_get_vga_enabled_displays(struct dc_bios *bios); #define GET_IMAGE(type, offset) ((type *) bios_get_image(&bp->base, offset, sizeof(type))) From a3a163adcf4409bffab7e95a5132fbff67f87f95 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 17 Sep 2024 08:53:21 -0400 Subject: [PATCH 1595/1868] drm/amdgpu: clean up vbios fetching code After splitting the logic between APU and dGPU, clean up some of the APU and dGPU specific logic that no longer applied. Reviewed-by: Lijo Lazar Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c | 16 ++-------------- 1 file changed, 2 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c index e8f62d718167b..46bf623919d7c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c @@ -284,10 +284,6 @@ static bool amdgpu_atrm_get_bios(struct amdgpu_device *adev) acpi_status status; bool found = false; - /* ATRM is for the discrete card only */ - if (adev->flags & AMD_IS_APU) - return false; - /* ATRM is for on-platform devices only */ if (dev_is_removable(&adev->pdev->dev)) return false; @@ -343,11 +339,8 @@ static inline bool amdgpu_atrm_get_bios(struct amdgpu_device *adev) static bool amdgpu_read_disabled_bios(struct amdgpu_device *adev) { - if (adev->flags & AMD_IS_APU) - return igp_read_bios_from_vram(adev); - else - return (!adev->asic_funcs || !adev->asic_funcs->read_disabled_bios) ? - false : amdgpu_asic_read_disabled_bios(adev); + return (!adev->asic_funcs || !adev->asic_funcs->read_disabled_bios) ? + false : amdgpu_asic_read_disabled_bios(adev); } #ifdef CONFIG_ACPI @@ -455,11 +448,6 @@ static bool amdgpu_get_bios_dgpu(struct amdgpu_device *adev) goto success; } - if (igp_read_bios_from_vram(adev)) { - dev_info(adev->dev, "Fetched VBIOS from VRAM BAR\n"); - goto success; - } - if (amdgpu_read_platform_bios(adev)) { dev_info(adev->dev, "Fetched VBIOS from platform\n"); goto success; From a8bd521d616deda7163cec0639422af7fd48ed50 Mon Sep 17 00:00:00 2001 From: Frank Min Date: Wed, 4 Sep 2024 10:50:33 +0800 Subject: [PATCH 1596/1868] drm/amdgpu: update golden regs for gfx12 update golden regs for gfx12 Signed-off-by: Frank Min Reviewed-by: Likun Gao Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c index d1357c01eb391..47b47d21f4644 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c @@ -202,12 +202,16 @@ static const struct amdgpu_hwip_reg_entry gc_gfx_queue_reg_list_12[] = { SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ) }; -static const struct soc15_reg_golden golden_settings_gc_12_0[] = { +static const struct soc15_reg_golden golden_settings_gc_12_0_rev0[] = { SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_MEM_CONFIG, 0x0000000f, 0x0000000f), SOC15_REG_GOLDEN_VALUE(GC, 0, regCB_HW_CONTROL_1, 0x03000000, 0x03000000), SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL5, 0x00000070, 0x00000020) }; +static const struct soc15_reg_golden golden_settings_gc_12_0[] = { + SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_MEM_CONFIG, 0x00008000, 0x00008000), +}; + #define DEFAULT_SH_MEM_CONFIG \ ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ @@ -3495,10 +3499,14 @@ static void gfx_v12_0_init_golden_registers(struct amdgpu_device *adev) switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { case IP_VERSION(12, 0, 0): case IP_VERSION(12, 0, 1): + soc15_program_register_sequence(adev, + golden_settings_gc_12_0, + (const u32)ARRAY_SIZE(golden_settings_gc_12_0)); + if (adev->rev_id == 0) soc15_program_register_sequence(adev, - golden_settings_gc_12_0, - (const u32)ARRAY_SIZE(golden_settings_gc_12_0)); + golden_settings_gc_12_0_rev0, + (const u32)ARRAY_SIZE(golden_settings_gc_12_0_rev0)); break; default: break; From 22498c462766cbe0e26ea06c672c7eaae349b518 Mon Sep 17 00:00:00 2001 From: Sathishkumar S Date: Mon, 9 Sep 2024 14:52:39 +0530 Subject: [PATCH 1597/1868] drm/amdgpu: add amdgpu_jpeg_sched_mask debugfs JPEG_4_0_3 has up to 32 jpeg cores and a single mjpeg video decode will use all available cores on the hardware. This debugfs entry helps to disable or enable job submission to a cluster of cores or one specific core in the ip for debugging. The entry is populated only if there is at least two or more cores in the jpeg ip. Signed-off-by: Sathishkumar S Reviewed-by: Leo Liu --- drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c | 73 +++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h | 1 + 3 files changed, 76 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c index d4a791c442adf..da52911293612 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c @@ -2128,6 +2128,8 @@ int amdgpu_debugfs_init(struct amdgpu_device *adev) if (amdgpu_umsch_mm & amdgpu_umsch_mm_fwlog) amdgpu_debugfs_umsch_fwlog_init(adev, &adev->umsch_mm); + amdgpu_debugfs_jpeg_sched_mask_init(adev); + amdgpu_ras_debugfs_create_all(adev); amdgpu_rap_debugfs_init(adev); amdgpu_securedisplay_debugfs_init(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c index cae26cd9da733..a8df976f158a7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c @@ -342,3 +342,76 @@ int amdgpu_jpeg_psp_update_sram(struct amdgpu_device *adev, int inst_idx, return psp_execute_ip_fw_load(&adev->psp, &ucode); } + +/* + * debugfs for to enable/disable jpeg job submission to specific core. + */ +#if defined(CONFIG_DEBUG_FS) +static int amdgpu_debugfs_jpeg_sched_mask_set(void *data, u64 val) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)data; + u32 i, j; + u64 mask = 0; + struct amdgpu_ring *ring; + + if (!adev) + return -ENODEV; + + mask = (1 << (adev->jpeg.num_jpeg_inst * adev->jpeg.num_jpeg_rings)) - 1; + if ((val & mask) == 0) + return -EINVAL; + + for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { + for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { + ring = &adev->jpeg.inst[i].ring_dec[j]; + if (val & (1 << ((i * adev->jpeg.num_jpeg_rings) + j))) + ring->sched.ready = true; + else + ring->sched.ready = false; + } + } + /* publish sched.ready flag update effective immediately across smp */ + smp_rmb(); + return 0; +} + +static int amdgpu_debugfs_jpeg_sched_mask_get(void *data, u64 *val) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)data; + u32 i, j; + u64 mask = 0; + struct amdgpu_ring *ring; + + if (!adev) + return -ENODEV; + for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { + for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { + ring = &adev->jpeg.inst[i].ring_dec[j]; + if (ring->sched.ready) + mask |= 1 << ((i * adev->jpeg.num_jpeg_rings) + j); + } + } + *val = mask; + return 0; +} + +DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_debugfs_jpeg_sched_mask_fops, + amdgpu_debugfs_jpeg_sched_mask_get, + amdgpu_debugfs_jpeg_sched_mask_set, "%llx\n"); + +#endif + +void amdgpu_debugfs_jpeg_sched_mask_init(struct amdgpu_device *adev) +{ +#if defined(CONFIG_DEBUG_FS) + struct drm_minor *minor = adev_to_drm(adev)->primary; + struct dentry *root = minor->debugfs_root; + char name[32]; + + if (!(adev->jpeg.num_jpeg_inst > 1) && !(adev->jpeg.num_jpeg_rings > 1)) + return; + sprintf(name, "amdgpu_jpeg_sched_mask"); + debugfs_create_file(name, 0600, root, adev, + &amdgpu_debugfs_jpeg_sched_mask_fops); +#endif +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h index f9cdd873ac9b0..819dc7a0af99e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.h @@ -149,5 +149,6 @@ int amdgpu_jpeg_ras_late_init(struct amdgpu_device *adev, int amdgpu_jpeg_ras_sw_init(struct amdgpu_device *adev); int amdgpu_jpeg_psp_update_sram(struct amdgpu_device *adev, int inst_idx, enum AMDGPU_UCODE_ID ucode_id); +void amdgpu_debugfs_jpeg_sched_mask_init(struct amdgpu_device *adev); #endif /*__AMDGPU_JPEG_H__*/ From afb3e442ca38136b82c9af5982d970736be6a1d9 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Thu, 19 Sep 2024 15:38:15 +0800 Subject: [PATCH 1598/1868] drm/amdkcl: wrap code under macro DEFINE_DEBUGFS_ATTRIBUTE It's caused by 71372e402994d29b6d456b714e6e8608c8112e91 "drm/amdgpu: add amdgpu_jpeg_sched_mask debugfs" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c index a8df976f158a7..0a6397e3b8a74 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c @@ -395,9 +395,15 @@ static int amdgpu_debugfs_jpeg_sched_mask_get(void *data, u64 *val) return 0; } +#ifdef DEFINE_DEBUGFS_ATTRIBUTE DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_debugfs_jpeg_sched_mask_fops, amdgpu_debugfs_jpeg_sched_mask_get, amdgpu_debugfs_jpeg_sched_mask_set, "%llx\n"); +#else +DEFINE_SIMPLE_ATTRIBUTE(amdgpu_debugfs_jpeg_sched_mask_fops, + amdgpu_debugfs_jpeg_sched_mask_get, + amdgpu_debugfs_jpeg_sched_mask_set, "%llx\n"); +#endif #endif From 50799448f51a1d2109aa950f0c6ba32f9e229caa Mon Sep 17 00:00:00 2001 From: Le Ma Date: Sat, 14 Sep 2024 19:35:32 +0800 Subject: [PATCH 1599/1868] Revert "drm/amdgpu/swsmu: always force a state reprogram on init" This reverts commit 63009805b6c5ce27d86f4f5cff8d9bbc779b4146. This patch inserts extra SMU messages to set dpm level during intialization and will cause SMU msg timeout on some platforms. The reverted patche causes a Jira issue SWDEV-485774 and involve SWDEV-485801. Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 87d6a23d28058..b30a1a49d5a2e 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -2224,9 +2224,8 @@ static int smu_bump_power_profile_mode(struct smu_context *smu, } static int smu_adjust_power_state_dynamic(struct smu_context *smu, - enum amd_dpm_forced_level level, - bool skip_display_settings, - bool force_update) + enum amd_dpm_forced_level level, + bool skip_display_settings) { int ret = 0; int index = 0; @@ -2255,7 +2254,7 @@ static int smu_adjust_power_state_dynamic(struct smu_context *smu, } } - if (force_update || smu_dpm_ctx->dpm_level != level) { + if (smu_dpm_ctx->dpm_level != level) { ret = smu_asic_set_performance_level(smu, level); if (ret) { dev_err(smu->adev->dev, "Failed to set performance level!"); @@ -2272,7 +2271,7 @@ static int smu_adjust_power_state_dynamic(struct smu_context *smu, index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0; workload[0] = smu->workload_setting[index]; - if (force_update || smu->power_profile_mode != workload[0]) + if (smu->power_profile_mode != workload[0]) smu_bump_power_profile_mode(smu, workload, 0); } @@ -2293,13 +2292,11 @@ static int smu_handle_task(struct smu_context *smu, ret = smu_pre_display_config_changed(smu); if (ret) return ret; - ret = smu_adjust_power_state_dynamic(smu, level, false, false); + ret = smu_adjust_power_state_dynamic(smu, level, false); break; case AMD_PP_TASK_COMPLETE_INIT: - ret = smu_adjust_power_state_dynamic(smu, level, true, true); - break; case AMD_PP_TASK_READJUST_POWER_STATE: - ret = smu_adjust_power_state_dynamic(smu, level, true, false); + ret = smu_adjust_power_state_dynamic(smu, level, true); break; default: break; From 0e8357c6fe048e49b54df173227c1a5e61ef5366 Mon Sep 17 00:00:00 2001 From: Jack Xiao Date: Wed, 18 Sep 2024 17:07:13 +0800 Subject: [PATCH 1600/1868] drm/amdgpu/mes12: set enable_level_process_quantum_check enable_level_process_quantum_check is requried to enable process quantum based scheduling. Signed-off-by: Jack Xiao Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c index ef05a41162306..ad87621f91b15 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c @@ -609,6 +609,7 @@ static int mes_v12_0_set_hw_resources(struct amdgpu_mes *mes, int pipe) mes_set_hw_res_pkt.disable_mes_log = 1; mes_set_hw_res_pkt.use_different_vmid_compute = 1; mes_set_hw_res_pkt.enable_reg_active_poll = 1; + mes_set_hw_res_pkt.enable_level_process_quantum_check = 1; /* * Keep oversubscribe timer for sdma . When we have unmapped doorbell From 1bb0469c86689addcdfe1970c6d47852285d101e Mon Sep 17 00:00:00 2001 From: Jack Xiao Date: Wed, 18 Sep 2024 17:07:13 +0800 Subject: [PATCH 1601/1868] drm/amdgpu/mes12: set enable_level_process_quantum_check enable_level_process_quantum_check is requried to enable process quantum based scheduling. Signed-off-by: Jack Xiao Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c index ef05a41162306..ad87621f91b15 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c @@ -609,6 +609,7 @@ static int mes_v12_0_set_hw_resources(struct amdgpu_mes *mes, int pipe) mes_set_hw_res_pkt.disable_mes_log = 1; mes_set_hw_res_pkt.use_different_vmid_compute = 1; mes_set_hw_res_pkt.enable_reg_active_poll = 1; + mes_set_hw_res_pkt.enable_level_process_quantum_check = 1; /* * Keep oversubscribe timer for sdma . When we have unmapped doorbell From 9bc42c49922c8293dff9add0f4fdae3bad34a92e Mon Sep 17 00:00:00 2001 From: ZhenGuo Yin Date: Thu, 19 Sep 2024 11:38:04 +0800 Subject: [PATCH 1602/1868] drm/amdgpu: skip coredump after job timeout in SRIOV VF FLR will be triggered by host driver before job timeout, hence the error status of GPU get cleared. Performing a coredump here is unnecessary. Signed-off-by: ZhenGuo Yin Acked-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c index 381c886298bf8..13a3604cf1079 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c @@ -107,8 +107,11 @@ static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job) /* * Do the coredump immediately after a job timeout to get a very * close dump/snapshot/representation of GPU's current error status + * Skip it for SRIOV, since VF FLR will be triggered by host driver + * before job timeout */ - amdgpu_job_core_dump(adev, job); + if (!amdgpu_sriov_vf(adev)) + amdgpu_job_core_dump(adev, job); if (amdgpu_gpu_recovery && amdgpu_ring_soft_recovery(ring, job->vmid, s_job->s_fence->parent)) { From c5bb0495979656e6257c5ea5082b28cf6c5cb0f2 Mon Sep 17 00:00:00 2001 From: ZhenGuo Yin Date: Thu, 19 Sep 2024 11:38:04 +0800 Subject: [PATCH 1603/1868] drm/amdgpu: skip coredump after job timeout in SRIOV VF FLR will be triggered by host driver before job timeout, hence the error status of GPU get cleared. Performing a coredump here is unnecessary. Signed-off-by: ZhenGuo Yin Acked-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c index 381c886298bf8..13a3604cf1079 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c @@ -107,8 +107,11 @@ static enum drm_gpu_sched_stat amdgpu_job_timedout(struct drm_sched_job *s_job) /* * Do the coredump immediately after a job timeout to get a very * close dump/snapshot/representation of GPU's current error status + * Skip it for SRIOV, since VF FLR will be triggered by host driver + * before job timeout */ - amdgpu_job_core_dump(adev, job); + if (!amdgpu_sriov_vf(adev)) + amdgpu_job_core_dump(adev, job); if (amdgpu_gpu_recovery && amdgpu_ring_soft_recovery(ring, job->vmid, s_job->s_fence->parent)) { From ae65abb4568ae9b9ebf02147051f15543e757867 Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Tue, 17 Sep 2024 18:39:07 +0530 Subject: [PATCH 1604/1868] drm/amd/display: Fix kdoc entry for 'tps' in 'dc_process_dmub_dpia_set_tps_notification' Correct the parameter descriptor for the function `dc_process_dmub_dpia_set_tps_notification` to match the actual parameters used. Fixes the below with gcc W=1: drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:5768: warning: Function parameter or struct member 'tps' not described in 'dc_process_dmub_dpia_set_tps_notification' drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:5768: warning: Excess function parameter 'ts' description in 'dc_process_dmub_dpia_set_tps_notification' Cc: Tom Chung Cc: Rodrigo Siqueira Cc: Roman Li Cc: Alex Hung Cc: Aurabindo Pillai Cc: Harry Wentland Cc: Hamza Mahfooz Signed-off-by: Srinivasan Shanmugam Reviewed-by: Tom Chung Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 77abeb8628cc2..804b3ed69f053 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -5761,7 +5761,7 @@ enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc, * * @dc: [in] dc structure * @link_index: [in] link index - * @ts: [in] request tps + * @tps: [in] request tps * * Submits set_tps_notification command to dmub via inbox message */ From e724f47c1b8456ba7bf57e9b249cd95a71ac67a6 Mon Sep 17 00:00:00 2001 From: Mario Limonciello Date: Sun, 15 Sep 2024 14:28:37 -0500 Subject: [PATCH 1605/1868] drm/amd/display: Allow backlight to go below `AMDGPU_DM_DEFAULT_MIN_BACKLIGHT` MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The issue with panel power savings compatibility below `AMDGPU_DM_DEFAULT_MIN_BACKLIGHT` happens at `AMDGPU_DM_DEFAULT_MIN_BACKLIGHT` as well. That issue will be fixed separately, so don't prevent the backlight brightness from going that low. Cc: Harry Wentland Cc: Thomas Weißschuh Link: https://lore.kernel.org/amd-gfx/be04226a-a9e3-4a45-a83b-6d263c6557d8@t-8ch.de/T/#m400dee4e2fc61fe9470334d20a7c8c89c9aef44f Reviewed-by: Harry Wentland Signed-off-by: Mario Limonciello Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 9e0e42c5e507b..4909dd1bc8207 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -4556,7 +4556,7 @@ static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm, int spread = caps.max_input_signal - caps.min_input_signal; if (caps.max_input_signal > AMDGPU_DM_DEFAULT_MAX_BACKLIGHT || - caps.min_input_signal < AMDGPU_DM_DEFAULT_MIN_BACKLIGHT || + caps.min_input_signal < 0 || spread > AMDGPU_DM_DEFAULT_MAX_BACKLIGHT || spread < AMDGPU_DM_MIN_SPREAD) { DRM_DEBUG_KMS("DM: Invalid backlight caps: min=%d, max=%d\n", From 7264a6760df88099ad69d2b25a8132b8f0edbee5 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 16 Sep 2024 10:52:24 -0400 Subject: [PATCH 1606/1868] drm/amdgpu/mes11: reduce timeout MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The firmware timeout is 2s. Reduce the driver timeout to 2.1 seconds to avoid back pressure on queue submissions. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/3627 Fixes: f7c161a4c250 ("drm/amdgpu: increase mes submission timeout") Acked-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c index 3c923719e32d3..e2b3f859a1c05 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c @@ -161,7 +161,7 @@ static int mes_v11_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, int api_status_off) { union MESAPI__QUERY_MES_STATUS mes_status_pkt; - signed long timeout = 3000000; /* 3000 ms */ + signed long timeout = 2100000; /* 2100 ms */ struct amdgpu_device *adev = mes->adev; struct amdgpu_ring *ring = &mes->ring[0]; struct MES_API_STATUS *api_status; From 31f81520c850faf23baf8f6ff9cfd3c324c59f05 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 18 Sep 2024 09:37:31 -0400 Subject: [PATCH 1607/1868] drm/amdgpu/mes12: reduce timeout MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The firmware timeout is 2s. Reduce the driver timeout to 2.1 seconds to avoid back pressure on queue submissions. Fixes: 94b51a3d01ed ("drm/amdgpu/mes12: increase mes submission timeout") Acked-by: Christian König Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c index ad87621f91b15..8d27421689c9d 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c @@ -146,7 +146,7 @@ static int mes_v12_0_submit_pkt_and_poll_completion(struct amdgpu_mes *mes, int api_status_off) { union MESAPI__QUERY_MES_STATUS mes_status_pkt; - signed long timeout = 3000000; /* 3000 ms */ + signed long timeout = 2100000; /* 2100 ms */ struct amdgpu_device *adev = mes->adev; struct amdgpu_ring *ring = &mes->ring[pipe]; spinlock_t *ring_lock = &mes->ring_lock[pipe]; From 6120bca3af43ddb2d022bf41afb3bc0aee8b9432 Mon Sep 17 00:00:00 2001 From: Feifei Xu Date: Thu, 12 Sep 2024 18:09:11 +0800 Subject: [PATCH 1608/1868] drm/amdkfd:Add kfd function to config sq perfmon Expose the interface for kfd to config sq perfmon. Signed-off-by: Feifei Xu Reviewed-by: Hawking Zhang Reviewed-by: Lijo Lazar Reviewed-by: James Zhu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 15 +++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 3 +++ 2 files changed, 18 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c index f43e634c8a211..9f39f8d8350b9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c @@ -901,3 +901,18 @@ int amdgpu_amdkfd_start_sched(struct amdgpu_device *adev, uint32_t node_id) return kgd2kfd_start_sched(adev->kfd.dev, node_id); } + +/* Config CGTT_SQ_CLK_CTRL */ +int amdgpu_amdkfd_config_sq_perfmon(struct amdgpu_device *adev, uint32_t xcp_id, + bool core_override_enable, bool reg_override_enable, bool perfmon_override_enable) +{ + int r; + + if (!adev->kfd.init_complete) + return 0; + + r = psp_config_sq_perfmon(&adev->psp, xcp_id, core_override_enable, + reg_override_enable, perfmon_override_enable); + + return r; +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index 1b686697c9a88..4f59b80af73c3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -282,6 +282,9 @@ int amdgpu_amdkfd_unmap_hiq(struct amdgpu_device *adev, u32 doorbell_off, u32 inst); int amdgpu_amdkfd_start_sched(struct amdgpu_device *adev, uint32_t node_id); int amdgpu_amdkfd_stop_sched(struct amdgpu_device *adev, uint32_t node_id); +int amdgpu_amdkfd_config_sq_perfmon(struct amdgpu_device *adev, uint32_t xcp_id, + bool core_override_enable, bool reg_override_enable, bool perfmon_override_enable); + /* Read user wptr from a specified user address space with page fault * disabled. The memory must be pinned and mapped to the hardware when From 3e519cfc97cc39211d7e6c36056624b639998cff Mon Sep 17 00:00:00 2001 From: Rohit Chavan Date: Tue, 17 Sep 2024 22:01:19 +0530 Subject: [PATCH 1609/1868] drm/amd/display: Fix unnecessary cast warnings from checkpatch This patch addresses warnings produced by the checkpatch script related to unnecessary casts that could potentially hide bugs. The specific warnings are as follows: - Warning at drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c:16 - Warning at drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c:20 - Warning at drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c:30 Acked-by: Alex Deucher Signed-off-by: Rohit Chavan Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c index d35dd507cb9f8..bbc28b9a15a36 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_wrapper.c @@ -13,11 +13,11 @@ static bool dml21_allocate_memory(struct dml2_context **dml_ctx) { - *dml_ctx = (struct dml2_context *)kzalloc(sizeof(struct dml2_context), GFP_KERNEL); + *dml_ctx = kzalloc(sizeof(struct dml2_context), GFP_KERNEL); if (!(*dml_ctx)) return false; - (*dml_ctx)->v21.dml_init.dml2_instance = (struct dml2_instance *)kzalloc(sizeof(struct dml2_instance), GFP_KERNEL); + (*dml_ctx)->v21.dml_init.dml2_instance = kzalloc(sizeof(struct dml2_instance), GFP_KERNEL); if (!((*dml_ctx)->v21.dml_init.dml2_instance)) return false; @@ -27,7 +27,7 @@ static bool dml21_allocate_memory(struct dml2_context **dml_ctx) (*dml_ctx)->v21.mode_support.display_config = &(*dml_ctx)->v21.display_config; (*dml_ctx)->v21.mode_programming.display_config = (*dml_ctx)->v21.mode_support.display_config; - (*dml_ctx)->v21.mode_programming.programming = (struct dml2_display_cfg_programming *)kzalloc(sizeof(struct dml2_display_cfg_programming), GFP_KERNEL); + (*dml_ctx)->v21.mode_programming.programming = kzalloc(sizeof(struct dml2_display_cfg_programming), GFP_KERNEL); if (!((*dml_ctx)->v21.mode_programming.programming)) return false; From b61ddf7681e1df5823f4995538f3991c5637a6be Mon Sep 17 00:00:00 2001 From: Hawking Zhang Date: Sun, 18 Aug 2024 16:04:09 +0800 Subject: [PATCH 1610/1868] drm/amd/pm: Do not support swSMU if SMU IP is disabled When SMU IP is disabled by ip_block_mask, driver should not refer to any dpm/swSMU callback. Instead, any driver call into swSMU/dpm callback needs to return error code EOPNOTSUPP. Signed-off-by: Hawking Zhang Reviewed-by: Yang Wang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index b30a1a49d5a2e..814202c073191 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -549,7 +549,8 @@ bool is_support_sw_smu(struct amdgpu_device *adev) if (adev->asic_type == CHIP_VEGA20) return false; - if (amdgpu_ip_version(adev, MP1_HWIP, 0) >= IP_VERSION(11, 0, 0)) + if ((amdgpu_ip_version(adev, MP1_HWIP, 0) >= IP_VERSION(11, 0, 0)) && + amdgpu_device_ip_is_valid(adev, AMD_IP_BLOCK_TYPE_SMC)) return true; return false; From f419f4d2409ddff140a82e336d1740f430aa8d43 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Fri, 6 Sep 2024 14:10:19 +0530 Subject: [PATCH 1611/1868] drm/amdgpu: Fix JPEG v4.0.3 register write EXTERNAL_REG_INTERNAL_OFFSET/EXTERNAL_REG_WRITE_ADDR should be used in pairs. If an external register shouldn't be written, both packets shouldn't be sent. Fixes: a78b48146972 ("drm/amdgpu: Skip PCTL0_MMHUB_DEEPSLEEP_IB write in jpegv4.0.3 under SRIOV") Signed-off-by: Lijo Lazar Acked-by: Leo Liu Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c index de67fb48d3b8a..f424170337aa6 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c @@ -672,11 +672,12 @@ void jpeg_v4_0_3_dec_ring_insert_start(struct amdgpu_ring *ring) amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 0, 0, PACKETJ_TYPE0)); amdgpu_ring_write(ring, 0x62a04); /* PCTL0_MMHUB_DEEPSLEEP_IB */ - } - amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, - 0, 0, PACKETJ_TYPE0)); - amdgpu_ring_write(ring, 0x80004000); + amdgpu_ring_write(ring, + PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 0, + 0, PACKETJ_TYPE0)); + amdgpu_ring_write(ring, 0x80004000); + } } /** @@ -692,11 +693,12 @@ void jpeg_v4_0_3_dec_ring_insert_end(struct amdgpu_ring *ring) amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, 0, 0, PACKETJ_TYPE0)); amdgpu_ring_write(ring, 0x62a04); - } - amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, - 0, 0, PACKETJ_TYPE0)); - amdgpu_ring_write(ring, 0x00004000); + amdgpu_ring_write(ring, + PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, 0, + 0, PACKETJ_TYPE0)); + amdgpu_ring_write(ring, 0x00004000); + } } /** From 0a6be403bd01158ed81019a22bad290245b03b97 Mon Sep 17 00:00:00 2001 From: Jane Jian Date: Tue, 10 Sep 2024 11:53:26 +0800 Subject: [PATCH 1612/1868] drm/amdgpu: Remove unneeded write in JPEG v4.0.3 HDP_DEBUG1(offset = 0x3fbc) is no longer functional, remove the redundant write. Signed-off-by: Jane Jian Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c index f424170337aa6..c274b05351c66 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c @@ -743,14 +743,6 @@ void jpeg_v4_0_3_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6)); amdgpu_ring_write(ring, 0); - amdgpu_ring_write(ring, PACKETJ(regUVD_JRBC_EXTERNAL_REG_INTERNAL_OFFSET, - 0, 0, PACKETJ_TYPE0)); - amdgpu_ring_write(ring, 0x3fbc); - - amdgpu_ring_write(ring, PACKETJ(JRBC_DEC_EXTERNAL_REG_WRITE_ADDR, - 0, 0, PACKETJ_TYPE0)); - amdgpu_ring_write(ring, 0x1); - amdgpu_ring_write(ring, PACKETJ(0, 0, 0, PACKETJ_TYPE6)); amdgpu_ring_write(ring, 0); @@ -1088,7 +1080,7 @@ static const struct amdgpu_ring_funcs jpeg_v4_0_3_dec_ring_vm_funcs = { SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 + SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 + 8 + /* jpeg_v4_0_3_dec_ring_emit_vm_flush */ - 22 + 22 + /* jpeg_v4_0_3_dec_ring_emit_fence x2 vm fence */ + 18 + 18 + /* jpeg_v4_0_3_dec_ring_emit_fence x2 vm fence */ 8 + 16, .emit_ib_size = 22, /* jpeg_v4_0_3_dec_ring_emit_ib */ .emit_ib = jpeg_v4_0_3_dec_ring_emit_ib, From ea10de7acdf03997f27efe0468f1e9f3ad774770 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Mon, 19 Aug 2024 12:27:48 +0530 Subject: [PATCH 1613/1868] drm/amdgpu: Add init levels Add init levels to define the level to which device needs to be initialized. Signed-off-by: Lijo Lazar Acked-by: Rajneesh Bhardwaj Tested-by: Rajneesh Bhardwaj --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 22 ++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 66 ++++++++++++++++++++++ 2 files changed, 88 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 9298d274bb3d2..3b218e62f9c28 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -841,6 +841,24 @@ struct amdgpu_mqd { struct amdgpu_mqd_prop *p); }; +/* + * Custom Init levels could be defined for different situations where a full + * initialization of all hardware blocks are not expected. Sample cases are + * custom init sequences after resume after S0i3/S3, reset on initialization, + * partial reset of blocks etc. Presently, this defines only two levels. Levels + * are described in corresponding struct definitions - amdgpu_init_default, + * amdgpu_init_minimal_xgmi. + */ +enum amdgpu_init_lvl_id { + AMDGPU_INIT_LEVEL_DEFAULT, + AMDGPU_INIT_LEVEL_MINIMAL_XGMI, +}; + +struct amdgpu_init_level { + enum amdgpu_init_lvl_id level; + uint32_t hwini_ip_block_mask; +}; + #define AMDGPU_RESET_MAGIC_NUM 64 #define AMDGPU_MAX_DF_PERFMONS 4 struct amdgpu_reset_domain; @@ -1192,6 +1210,8 @@ struct amdgpu_device { bool enforce_isolation[MAX_XCP]; /* Added this mutex for cleaner shader isolation between GFX and compute processes */ struct mutex enforce_isolation_mutex; + + struct amdgpu_init_level *init_lvl; }; static inline uint32_t amdgpu_ip_version(const struct amdgpu_device *adev, @@ -1663,4 +1683,6 @@ extern const struct attribute_group amdgpu_vram_mgr_attr_group; extern const struct attribute_group amdgpu_gtt_mgr_attr_group; extern const struct attribute_group amdgpu_flash_attr_group; +void amdgpu_set_init_level(struct amdgpu_device *adev, + enum amdgpu_init_lvl_id lvl); #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 5f0cd9cc20785..262b496b0b9ca 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -146,6 +146,50 @@ const char *amdgpu_asic_name[] = { "LAST", }; +#define AMDGPU_IP_BLK_MASK_ALL GENMASK(AMDGPU_MAX_IP_NUM - 1, 0) +/* + * Default init level where all blocks are expected to be initialized. This is + * the level of initialization expected by default and also after a full reset + * of the device. + */ +struct amdgpu_init_level amdgpu_init_default = { + .level = AMDGPU_INIT_LEVEL_DEFAULT, + .hwini_ip_block_mask = AMDGPU_IP_BLK_MASK_ALL, +}; + +/* + * Minimal blocks needed to be initialized before a XGMI hive can be reset. This + * is used for cases like reset on initialization where the entire hive needs to + * be reset before first use. + */ +struct amdgpu_init_level amdgpu_init_minimal_xgmi = { + .level = AMDGPU_INIT_LEVEL_MINIMAL_XGMI, + .hwini_ip_block_mask = + BIT(AMD_IP_BLOCK_TYPE_GMC) | BIT(AMD_IP_BLOCK_TYPE_SMC) | + BIT(AMD_IP_BLOCK_TYPE_COMMON) | BIT(AMD_IP_BLOCK_TYPE_IH) +}; + +static inline bool amdgpu_ip_member_of_hwini(struct amdgpu_device *adev, + enum amd_ip_block_type block) +{ + return (adev->init_lvl->hwini_ip_block_mask & (1U << block)) != 0; +} + +void amdgpu_set_init_level(struct amdgpu_device *adev, + enum amdgpu_init_lvl_id lvl) +{ + switch (lvl) { + case AMDGPU_INIT_LEVEL_MINIMAL_XGMI: + adev->init_lvl = &amdgpu_init_minimal_xgmi; + break; + case AMDGPU_INIT_LEVEL_DEFAULT: + fallthrough; + default: + adev->init_lvl = &amdgpu_init_default; + break; + } +} + static inline void amdgpu_device_stop_pending_resets(struct amdgpu_device *adev); /** @@ -2670,6 +2714,9 @@ static int amdgpu_device_ip_hw_init_phase1(struct amdgpu_device *adev) continue; if (adev->ip_blocks[i].status.hw) continue; + if (!amdgpu_ip_member_of_hwini( + adev, adev->ip_blocks[i].version->type)) + continue; if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || (amdgpu_sriov_vf(adev) && (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)) || adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) { @@ -2695,6 +2742,9 @@ static int amdgpu_device_ip_hw_init_phase2(struct amdgpu_device *adev) continue; if (adev->ip_blocks[i].status.hw) continue; + if (!amdgpu_ip_member_of_hwini( + adev, adev->ip_blocks[i].version->type)) + continue; r = adev->ip_blocks[i].version->funcs->hw_init(adev); if (r) { DRM_ERROR("hw_init of IP block <%s> failed %d\n", @@ -2718,6 +2768,10 @@ static int amdgpu_device_fw_loading(struct amdgpu_device *adev) if (adev->ip_blocks[i].version->type != AMD_IP_BLOCK_TYPE_PSP) continue; + if (!amdgpu_ip_member_of_hwini(adev, + AMD_IP_BLOCK_TYPE_PSP)) + break; + if (!adev->ip_blocks[i].status.sw) continue; @@ -2840,6 +2894,10 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev) } adev->ip_blocks[i].status.sw = true; + if (!amdgpu_ip_member_of_hwini( + adev, adev->ip_blocks[i].version->type)) + continue; + if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON) { /* need to do common hw init early so everything is set up for gmc */ r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev); @@ -4213,6 +4271,12 @@ int amdgpu_device_init(struct amdgpu_device *adev, amdgpu_device_set_mcbp(adev); + /* + * By default, use default mode where all blocks are expected to be + * initialized. At present a 'swinit' of blocks is required to be + * completed before the need for a different level is detected. + */ + amdgpu_set_init_level(adev, AMDGPU_INIT_LEVEL_DEFAULT); /* early init functions */ r = amdgpu_device_ip_early_init(adev); if (r) @@ -5433,6 +5497,8 @@ int amdgpu_do_asic_reset(struct list_head *device_list_handle, } list_for_each_entry(tmp_adev, device_list_handle, reset_list) { + /* After reset, it's default init level */ + amdgpu_set_init_level(tmp_adev, AMDGPU_INIT_LEVEL_DEFAULT); if (need_full_reset) { /* post card */ amdgpu_ras_set_fed(tmp_adev, false); From 3c32e50938cc339b96bcc98ba7334454557e93af Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Mon, 19 Aug 2024 13:23:42 +0530 Subject: [PATCH 1614/1868] drm/amdgpu: Use init level for pending_reset flag Drop pending_reset flag in gmc block. Instead use init level to determine which type of init is preferred - in this case MINIMAL. Signed-off-by: Lijo Lazar Acked-by: Rajneesh Bhardwaj Tested-by: Rajneesh Bhardwaj --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 34 +++++-------------- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 1 - drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 1 - drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 6 ++-- .../gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c | 3 +- 6 files changed, 14 insertions(+), 33 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 262b496b0b9ca..f11facc58e556 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -1698,7 +1698,7 @@ bool amdgpu_device_need_post(struct amdgpu_device *adev) } /* Don't post if we need to reset whole hive on init */ - if (adev->gmc.xgmi.pending_reset) + if (adev->init_lvl->level == AMDGPU_INIT_LEVEL_MINIMAL_XGMI) return false; if (adev->has_hw_reset) { @@ -3030,7 +3030,7 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev) amdgpu_ttm_set_buffer_funcs_status(adev, true); /* Don't init kfd if whole hive need to be reset during init */ - if (!adev->gmc.xgmi.pending_reset) { + if (adev->init_lvl->level != AMDGPU_INIT_LEVEL_MINIMAL_XGMI) { kgd2kfd_init_zone_device(adev); amdgpu_amdkfd_device_init(adev); } @@ -3544,14 +3544,9 @@ static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev) } /* skip unnecessary suspend if we do not initialize them yet */ - if (adev->gmc.xgmi.pending_reset && - !(adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || - adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC || - adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || - adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH)) { - adev->ip_blocks[i].status.hw = false; + if (!amdgpu_ip_member_of_hwini( + adev, adev->ip_blocks[i].version->type)) continue; - } /* skip suspend of gfx/mes and psp for S0ix * gfx is in gfxoff state, so on resume it will exit gfxoff just @@ -4353,20 +4348,8 @@ int amdgpu_device_init(struct amdgpu_device *adev, if (!amdgpu_sriov_vf(adev) && amdgpu_asic_need_reset_on_init(adev)) { if (adev->gmc.xgmi.num_physical_nodes) { dev_info(adev->dev, "Pending hive reset.\n"); - adev->gmc.xgmi.pending_reset = true; - /* Only need to init necessary block for SMU to handle the reset */ - for (i = 0; i < adev->num_ip_blocks; i++) { - if (!adev->ip_blocks[i].status.valid) - continue; - if (!(adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || - adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || - adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH || - adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC)) { - DRM_DEBUG("IP %s disabled for hw_init.\n", - adev->ip_blocks[i].version->funcs->name); - adev->ip_blocks[i].status.hw = true; - } - } + amdgpu_set_init_level(adev, + AMDGPU_INIT_LEVEL_MINIMAL_XGMI); } else if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 10) && !amdgpu_device_has_display_hardware(adev)) { r = psp_gpu_reset(adev); @@ -4480,7 +4463,7 @@ int amdgpu_device_init(struct amdgpu_device *adev, /* enable clockgating, etc. after ib tests, etc. since some blocks require * explicit gating rather than handling it automatically. */ - if (!adev->gmc.xgmi.pending_reset) { + if (adev->init_lvl->level != AMDGPU_INIT_LEVEL_MINIMAL_XGMI) { r = amdgpu_device_ip_late_init(adev); if (r) { dev_err(adev->dev, "amdgpu_device_ip_late_init failed\n"); @@ -4564,7 +4547,7 @@ int amdgpu_device_init(struct amdgpu_device *adev, if (px) vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain); - if (adev->gmc.xgmi.pending_reset) + if (adev->init_lvl->level == AMDGPU_INIT_LEVEL_MINIMAL_XGMI) queue_delayed_work(system_wq, &mgpu_info.delayed_reset_work, msecs_to_jiffies(AMDGPU_RESUME_MS)); @@ -5462,7 +5445,6 @@ int amdgpu_do_asic_reset(struct list_head *device_list_handle, list_for_each_entry(tmp_adev, device_list_handle, reset_list) { /* For XGMI run all resets in parallel to speed up the process */ if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) { - tmp_adev->gmc.xgmi.pending_reset = false; if (!queue_work(system_unbound_wq, &tmp_adev->xgmi_reset_work)) r = -EALREADY; } else diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 9b85f832a59e4..31a3c82c37f20 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2566,7 +2566,6 @@ static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work) for (i = 0; i < mgpu_info.num_dgpu; i++) { adev = mgpu_info.gpu_ins[i].adev; flush_work(&adev->xgmi_reset_work); - adev->gmc.xgmi.pending_reset = false; } /* reset function will rebuild the xgmi hive info , clear it now */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h index 4d951a1baefab..33b2adffd58b1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h @@ -182,7 +182,6 @@ struct amdgpu_xgmi { bool supported; struct ras_common_if *ras_if; bool connected_to_cpu; - bool pending_reset; struct amdgpu_xgmi_ras *ras; }; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 0d214fc3a39b1..ed437c451d540 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -3195,7 +3195,7 @@ int amdgpu_ras_recovery_init(struct amdgpu_device *adev) * when the GPU is pending on XGMI reset during probe time * (Mostly after second bus reset), skip it now */ - if (adev->gmc.xgmi.pending_reset) + if (adev->init_lvl->level == AMDGPU_INIT_LEVEL_MINIMAL_XGMI) return 0; ret = amdgpu_ras_eeprom_init(&con->eeprom_control); /* diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c index c142e79ef81b6..bcd59162d8918 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c @@ -866,7 +866,7 @@ int amdgpu_xgmi_add_device(struct amdgpu_device *adev) if (!adev->gmc.xgmi.supported) return 0; - if (!adev->gmc.xgmi.pending_reset && + if ((adev->init_lvl->level != AMDGPU_INIT_LEVEL_MINIMAL_XGMI) && amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP)) { ret = psp_xgmi_initialize(&adev->psp, false, true); if (ret) { @@ -913,7 +913,7 @@ int amdgpu_xgmi_add_device(struct amdgpu_device *adev) task_barrier_add_task(&hive->tb); - if (!adev->gmc.xgmi.pending_reset && + if ((adev->init_lvl->level != AMDGPU_INIT_LEVEL_MINIMAL_XGMI) && amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP)) { list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) { /* update node list for other device in the hive */ @@ -991,7 +991,7 @@ int amdgpu_xgmi_add_device(struct amdgpu_device *adev) } } - if (!ret && !adev->gmc.xgmi.pending_reset) + if (!ret && (adev->init_lvl->level != AMDGPU_INIT_LEVEL_MINIMAL_XGMI)) ret = amdgpu_xgmi_sysfs_add_dev_info(adev, hive); exit_unlock: diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c index 16fcd9dcd202e..8981302b19c8e 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c @@ -1616,7 +1616,8 @@ int smu_v11_0_baco_set_state(struct smu_context *smu, enum smu_baco_state state) break; default: if (!ras || !adev->ras_enabled || - adev->gmc.xgmi.pending_reset) { + (adev->init_lvl->level == + AMDGPU_INIT_LEVEL_MINIMAL_XGMI)) { if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 2)) { data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL_ARCT); From 09edf37df48fbad4ca1986de5df7d1b1df911ed3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Christian=20K=C3=B6nig?= Date: Wed, 21 Aug 2024 13:55:41 +0200 Subject: [PATCH 1615/1868] drm/amdgpu: sync to KFD fences before clearing PTEs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch tries to solve the basic problem we also need to sync to the KFD fences of the BO because otherwise it can be that we clear PTEs while the KFD queues are still running. Signed-off-by: Christian König Acked-by: Felix Kuehling --- drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c | 30 ++++++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 6 +++++ 3 files changed, 37 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c index 97ead0dbffab0..8dc23cbfb039a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.c @@ -258,6 +258,36 @@ int amdgpu_sync_resv(struct amdgpu_device *adev, struct amdgpu_sync *sync, return 0; } +/** + * amdgpu_sync_kfd - sync to KFD fences + * + * @sync: sync object to add KFD fences to + * @resv: reservation object with KFD fences + * + * Extract all KFD fences and add them to the sync object. + */ +int amdgpu_sync_kfd(struct amdgpu_sync *sync, struct dma_resv *resv) +{ + struct dma_resv_iter cursor; + struct dma_fence *f; + int r = 0; + + dma_resv_iter_begin(&cursor, resv, DMA_RESV_USAGE_BOOKKEEP); + dma_resv_for_each_fence_unlocked(&cursor, f) { + void *fence_owner = amdgpu_sync_get_owner(f); + + if (fence_owner != AMDGPU_FENCE_OWNER_KFD) + continue; + + r = amdgpu_sync_fence(sync, f); + if (r) + break; + } + dma_resv_iter_end(&cursor); + + return r; +} + /* Free the entry back to the slab */ static void amdgpu_sync_entry_free(struct amdgpu_sync_entry *e) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h index cf1e9e858efdc..e3272dce798d7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sync.h @@ -51,6 +51,7 @@ int amdgpu_sync_fence(struct amdgpu_sync *sync, struct dma_fence *f); int amdgpu_sync_resv(struct amdgpu_device *adev, struct amdgpu_sync *sync, struct dma_resv *resv, enum amdgpu_sync_mode mode, void *owner); +int amdgpu_sync_kfd(struct amdgpu_sync *sync, struct dma_resv *resv); struct dma_fence *amdgpu_sync_peek_fence(struct amdgpu_sync *sync, struct amdgpu_ring *ring); struct dma_fence *amdgpu_sync_get_fence(struct amdgpu_sync *sync); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index a16b2050184e6..a815f8d22855c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -1199,6 +1199,12 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va, AMDGPU_SYNC_EQ_OWNER, vm); if (r) goto error_free; + if (bo) { + r = amdgpu_sync_kfd(&sync, bo->tbo.base.resv); + if (r) + goto error_free; + } + } else { struct drm_gem_object *obj = &bo->tbo.base; From a7d9253849ef54f588d1324a3d161fecfa6f0cd5 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 23 Sep 2024 11:30:20 +0800 Subject: [PATCH 1616/1868] drm/amdkcl: wrap code under amdkcl_ttm_resvp() It's caused by f6ca006dfa5cc9e46cf3b4a48f12388d02f56843 "drm/amdgpu: sync to KFD fences before clearing PTEs" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c index a815f8d22855c..3d99ba92ab0b0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c @@ -1200,7 +1200,7 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev, struct amdgpu_bo_va *bo_va, if (r) goto error_free; if (bo) { - r = amdgpu_sync_kfd(&sync, bo->tbo.base.resv); + r = amdgpu_sync_kfd(&sync, amdkcl_ttm_resvp(&bo->tbo)); if (r) goto error_free; } From 6383f07d19b738f50517ed0e4bfbb1186adf3a94 Mon Sep 17 00:00:00 2001 From: Hawking Zhang Date: Thu, 26 Sep 2024 00:51:23 +0800 Subject: [PATCH 1617/1868] Revert "drm/amdgpu: remove reset lock from low level functions" This reverts commit b3a4745025be8ccefd767fc07bf721e39a48e625. Signed-off-by: Hawking Zhang Reviewed-by: Victor Skvortsov --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 500b3ff9f344a..6105cfdd0e8bd 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -616,10 +616,13 @@ uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, if ((reg * 4) < adev->rmmio_size) { if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && - amdgpu_sriov_runtime(adev)) + amdgpu_sriov_runtime(adev) && + down_read_trylock(&adev->reset_domain->sem)) { ret = amdgpu_kiq_rreg(adev, reg, 0); - else + up_read(&adev->reset_domain->sem); + } else { ret = readl(((void __iomem *)adev->rmmio) + (reg * 4)); + } } else { ret = adev->pcie_rreg(adev, reg * 4); } @@ -740,10 +743,13 @@ void amdgpu_device_wreg(struct amdgpu_device *adev, if ((reg * 4) < adev->rmmio_size) { if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && - amdgpu_sriov_runtime(adev)) + amdgpu_sriov_runtime(adev) && + down_read_trylock(&adev->reset_domain->sem)) { amdgpu_kiq_wreg(adev, reg, v, 0); - else + up_read(&adev->reset_domain->sem); + } else { writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); + } } else { adev->pcie_wreg(adev, reg * 4, v); } From 0c7aaa10bb565111ca756e53fbaae5eb3a985fa7 Mon Sep 17 00:00:00 2001 From: Hawking Zhang Date: Thu, 26 Sep 2024 01:02:42 +0800 Subject: [PATCH 1618/1868] Revert "drm/amdgpu: remove reset lock from low level functions" This reverts commit b3a4745025be8ccefd767fc07bf721e39a48e625. Signed-off-by: Hawking Zhang Reviewed-by: Victor Skvortsov --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index f11facc58e556..152da318ca3a2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -660,10 +660,13 @@ uint32_t amdgpu_device_rreg(struct amdgpu_device *adev, if ((reg * 4) < adev->rmmio_size) { if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && - amdgpu_sriov_runtime(adev)) + amdgpu_sriov_runtime(adev) && + down_read_trylock(&adev->reset_domain->sem)) { ret = amdgpu_kiq_rreg(adev, reg, 0); - else + up_read(&adev->reset_domain->sem); + } else { ret = readl(((void __iomem *)adev->rmmio) + (reg * 4)); + } } else { ret = adev->pcie_rreg(adev, reg * 4); } @@ -784,10 +787,13 @@ void amdgpu_device_wreg(struct amdgpu_device *adev, if ((reg * 4) < adev->rmmio_size) { if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && - amdgpu_sriov_runtime(adev)) + amdgpu_sriov_runtime(adev) && + down_read_trylock(&adev->reset_domain->sem)) { amdgpu_kiq_wreg(adev, reg, v, 0); - else + up_read(&adev->reset_domain->sem); + } else { writel(v, ((void __iomem *)adev->rmmio) + (reg * 4)); + } } else { adev->pcie_wreg(adev, reg * 4, v); } From b55d462f88ed3d0e0fe43941b7851e6266c9e841 Mon Sep 17 00:00:00 2001 From: Al Viro Date: Fri, 2 Aug 2024 09:56:28 -0400 Subject: [PATCH 1619/1868] drm: new helper: drm_gem_prime_handle_to_dmabuf() Once something had been put into descriptor table, the only thing you can do with it is returning descriptor to userland - you can't withdraw it on subsequent failure exit, etc. You certainly can't count upon it staying in the same slot of descriptor table - another thread could've played with close(2)/dup2(2)/whatnot. drm_gem_prime_handle_to_fd() creates a dmabuf, allocates a descriptor and attaches dmabuf's file to it (the last two steps are done in dma_buf_fd()). That's nice when all you are going to do is passing a descriptor to userland. If you just need to work with the resulting object or have something else to be done that might fail, drm_gem_prime_handle_to_fd() is racy. The problem is analogous to one with anon_inode_getfd(), and solution is similar to what anon_inode_getfile() provides. Add drm_gem_prime_handle_to_dmabuf() - the "set dmabuf up" parts of drm_gem_prime_handle_to_fd() without the descriptor-related ones. Instead of inserting into descriptor table and returning the file descriptor it just returns the struct file. drm_gem_prime_handle_to_fd() becomes a wrapper for it. Other users will be introduced in the next commit. Acked-by: Thomas Zimmermann Signed-off-by: Al Viro Signed-off-by: Alex Deucher --- drivers/gpu/drm/drm_prime.c | 84 ++++++++++++++++++++++++------------- include/drm/drm_prime.h | 3 ++ 2 files changed, 57 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/drm_prime.c b/drivers/gpu/drm/drm_prime.c index 03bd3c7bd0dc2..0e3f8adf162f6 100644 --- a/drivers/gpu/drm/drm_prime.c +++ b/drivers/gpu/drm/drm_prime.c @@ -410,22 +410,30 @@ static struct dma_buf *export_and_register_object(struct drm_device *dev, } /** - * drm_gem_prime_handle_to_fd - PRIME export function for GEM drivers + * drm_gem_prime_handle_to_dmabuf - PRIME export function for GEM drivers * @dev: dev to export the buffer from * @file_priv: drm file-private structure * @handle: buffer handle to export * @flags: flags like DRM_CLOEXEC - * @prime_fd: pointer to storage for the fd id of the create dma-buf * * This is the PRIME export function which must be used mandatorily by GEM * drivers to ensure correct lifetime management of the underlying GEM object. * The actual exporting from GEM object to a dma-buf is done through the * &drm_gem_object_funcs.export callback. + * + * Unlike drm_gem_prime_handle_to_fd(), it returns the struct dma_buf it + * has created, without attaching it to any file descriptors. The difference + * between those two is similar to that between anon_inode_getfile() and + * anon_inode_getfd(); insertion into descriptor table is something you + * can not revert if any cleanup is needed, so the descriptor-returning + * variants should only be used when you are past the last failure exit + * and the only thing left is passing the new file descriptor to userland. + * When all you need is the object itself or when you need to do something + * else that might fail, use that one instead. */ -int drm_gem_prime_handle_to_fd(struct drm_device *dev, +struct dma_buf *drm_gem_prime_handle_to_dmabuf(struct drm_device *dev, struct drm_file *file_priv, uint32_t handle, - uint32_t flags, - int *prime_fd) + uint32_t flags) { struct drm_gem_object *obj; int ret = 0; @@ -434,14 +442,14 @@ int drm_gem_prime_handle_to_fd(struct drm_device *dev, mutex_lock(&file_priv->prime.lock); obj = drm_gem_object_lookup(file_priv, handle); if (!obj) { - ret = -ENOENT; + dmabuf = ERR_PTR(-ENOENT); goto out_unlock; } dmabuf = drm_prime_lookup_buf_by_handle(&file_priv->prime, handle); if (dmabuf) { get_dma_buf(dmabuf); - goto out_have_handle; + goto out; } mutex_lock(&dev->object_name_lock); @@ -463,7 +471,6 @@ int drm_gem_prime_handle_to_fd(struct drm_device *dev, /* normally the created dma-buf takes ownership of the ref, * but if that fails then drop the ref */ - ret = PTR_ERR(dmabuf); mutex_unlock(&dev->object_name_lock); goto out; } @@ -478,34 +485,51 @@ int drm_gem_prime_handle_to_fd(struct drm_device *dev, ret = drm_prime_add_buf_handle(&file_priv->prime, dmabuf, handle); mutex_unlock(&dev->object_name_lock); - if (ret) - goto fail_put_dmabuf; - -out_have_handle: - ret = dma_buf_fd(dmabuf, flags); - /* - * We must _not_ remove the buffer from the handle cache since the newly - * created dma buf is already linked in the global obj->dma_buf pointer, - * and that is invariant as long as a userspace gem handle exists. - * Closing the handle will clean out the cache anyway, so we don't leak. - */ - if (ret < 0) { - goto fail_put_dmabuf; - } else { - *prime_fd = ret; - ret = 0; + if (ret) { + dma_buf_put(dmabuf); + dmabuf = ERR_PTR(ret); } - - goto out; - -fail_put_dmabuf: - dma_buf_put(dmabuf); out: drm_gem_object_put(obj); out_unlock: mutex_unlock(&file_priv->prime.lock); + return dmabuf; +} +EXPORT_SYMBOL(drm_gem_prime_handle_to_dmabuf); - return ret; +/** + * drm_gem_prime_handle_to_fd - PRIME export function for GEM drivers + * @dev: dev to export the buffer from + * @file_priv: drm file-private structure + * @handle: buffer handle to export + * @flags: flags like DRM_CLOEXEC + * @prime_fd: pointer to storage for the fd id of the create dma-buf + * + * This is the PRIME export function which must be used mandatorily by GEM + * drivers to ensure correct lifetime management of the underlying GEM object. + * The actual exporting from GEM object to a dma-buf is done through the + * &drm_gem_object_funcs.export callback. + */ +int drm_gem_prime_handle_to_fd(struct drm_device *dev, + struct drm_file *file_priv, uint32_t handle, + uint32_t flags, + int *prime_fd) +{ + struct dma_buf *dmabuf; + int fd = get_unused_fd_flags(flags); + + if (fd < 0) + return fd; + + dmabuf = drm_gem_prime_handle_to_dmabuf(dev, file_priv, handle, flags); + if (IS_ERR(dmabuf)) { + put_unused_fd(fd); + return PTR_ERR(dmabuf); + } + + fd_install(fd, dmabuf->file); + *prime_fd = fd; + return 0; } EXPORT_SYMBOL(drm_gem_prime_handle_to_fd); diff --git a/include/drm/drm_prime.h b/include/drm/drm_prime.h index 2a1d01e5b56b8..fa085c44d4ca4 100644 --- a/include/drm/drm_prime.h +++ b/include/drm/drm_prime.h @@ -69,6 +69,9 @@ void drm_gem_dmabuf_release(struct dma_buf *dma_buf); int drm_gem_prime_fd_to_handle(struct drm_device *dev, struct drm_file *file_priv, int prime_fd, uint32_t *handle); +struct dma_buf *drm_gem_prime_handle_to_dmabuf(struct drm_device *dev, + struct drm_file *file_priv, uint32_t handle, + uint32_t flags); int drm_gem_prime_handle_to_fd(struct drm_device *dev, struct drm_file *file_priv, uint32_t handle, uint32_t flags, int *prime_fd); From 4edab5d4016f17cb7adb65b6d6e402fd44f8ff22 Mon Sep 17 00:00:00 2001 From: Al Viro Date: Mon, 3 Jun 2024 21:37:49 -0400 Subject: [PATCH 1620/1868] drm/amdgpu: fix a race in kfd_mem_export_dmabuf() Using drm_gem_prime_handle_to_fd() to set dmabuf up and insert it into descriptor table, only to have it looked up by file descriptor and remove it from descriptor table is not just too convoluted - it's racy; another thread might have modified the descriptor table while we'd been going through that song and dance. Switch kfd_mem_export_dmabuf() to using drm_gem_prime_handle_to_dmabuf() and leave the descriptor table alone... Reviewed-by: Felix Kuehling Signed-off-by: Al Viro Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 14 ++++---------- 1 file changed, 4 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 049723c6a3926..0aa94548aa514 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -25,7 +25,6 @@ #include #include #include -#include #include #include @@ -820,18 +819,13 @@ static int kfd_mem_export_dmabuf(struct kgd_mem *mem) if (!mem->dmabuf) { struct amdgpu_device *bo_adev; struct dma_buf *dmabuf; - int r, fd; bo_adev = amdgpu_ttm_adev(mem->bo->tbo.bdev); - r = drm_gem_prime_handle_to_fd(&bo_adev->ddev, bo_adev->kfd.client.file, + dmabuf = drm_gem_prime_handle_to_dmabuf(&bo_adev->ddev, bo_adev->kfd.client.file, mem->gem_handle, - mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ? - DRM_RDWR : 0, &fd); - if (r) - return r; - dmabuf = dma_buf_get(fd); - close_fd(fd); - if (WARN_ON_ONCE(IS_ERR(dmabuf))) + mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ? + DRM_RDWR : 0); + if (IS_ERR(dmabuf)) return PTR_ERR(dmabuf); mem->dmabuf = dmabuf; } From ff854a470688856dde12b6962558141d7908e7b3 Mon Sep 17 00:00:00 2001 From: Al Viro Date: Mon, 3 Jun 2024 21:43:53 -0400 Subject: [PATCH 1621/1868] drm/amdkfd: CRIU fixes Instead of trying to use close_fd() on failure exits, just have criu_get_prime_handle() store the file reference without inserting it into descriptor table. Then, once the callers are past the last failure exit, they can go and either insert all those file references into the corresponding slots of descriptor table, or drop all those file references and free the unused descriptors. Reviewed-by: Felix Kuehling Signed-off-by: Al Viro Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 64 +++++++++++++++++------- 1 file changed, 46 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 4ae65500bc167..75135dc7dae70 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -36,7 +36,6 @@ #include #include #include -#include #include #include "kfd_priv.h" #include "kfd_device_queue_manager.h" @@ -1984,7 +1983,8 @@ static uint32_t get_process_num_bos(struct kfd_process *p) } static int criu_get_prime_handle(struct kgd_mem *mem, - int flags, u32 *shared_fd) + int flags, u32 *shared_fd, + struct file **file) { struct dma_buf *dmabuf; int ret; @@ -1995,13 +1995,14 @@ static int criu_get_prime_handle(struct kgd_mem *mem, return ret; } - ret = dma_buf_fd(dmabuf, flags); + ret = get_unused_fd_flags(flags); if (ret < 0) { pr_err("dmabuf create fd failed, ret:%d\n", ret); goto out_free_dmabuf; } *shared_fd = ret; + *file = dmabuf->file; return 0; out_free_dmabuf: @@ -2009,6 +2010,25 @@ static int criu_get_prime_handle(struct kgd_mem *mem, return ret; } +static void commit_files(struct file **files, + struct kfd_criu_bo_bucket *bo_buckets, + unsigned int count, + int err) +{ + while (count--) { + struct file *file = files[count]; + + if (!file) + continue; + if (err) { + fput(file); + put_unused_fd(bo_buckets[count].dmabuf_fd); + } else { + fd_install(bo_buckets[count].dmabuf_fd, file); + } + } +} + static int criu_checkpoint_bos(struct kfd_process *p, uint32_t num_bos, uint8_t __user *user_bos, @@ -2017,6 +2037,7 @@ static int criu_checkpoint_bos(struct kfd_process *p, { struct kfd_criu_bo_bucket *bo_buckets; struct kfd_criu_bo_priv_data *bo_privs; + struct file **files = NULL; int ret = 0, pdd_index, bo_index = 0, id; struct kfd_bo *buf_obj; @@ -2030,6 +2051,12 @@ static int criu_checkpoint_bos(struct kfd_process *p, goto exit; } + files = kvzalloc(num_bos * sizeof(struct file *), GFP_KERNEL); + if (!files) { + ret = -ENOMEM; + goto exit; + } + for (pdd_index = 0; pdd_index < p->n_pdds; pdd_index++) { struct kfd_process_device *pdd = p->pdds[pdd_index]; struct amdgpu_bo *dumper_bo; @@ -2072,7 +2099,7 @@ static int criu_checkpoint_bos(struct kfd_process *p, ret = criu_get_prime_handle(kgd_mem, bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ? DRM_RDWR : 0, - &bo_bucket->dmabuf_fd); + &bo_bucket->dmabuf_fd, &files[bo_index]); if (ret) goto exit; } else { @@ -2133,12 +2160,8 @@ static int criu_checkpoint_bos(struct kfd_process *p, *priv_offset += num_bos * sizeof(*bo_privs); exit: - while (ret && bo_index--) { - if (bo_buckets[bo_index].alloc_flags - & (KFD_IOC_ALLOC_MEM_FLAGS_VRAM | KFD_IOC_ALLOC_MEM_FLAGS_GTT)) - close_fd(bo_buckets[bo_index].dmabuf_fd); - } - + commit_files(files, bo_buckets, bo_index, ret); + kvfree(files); kvfree(bo_buckets); kvfree(bo_privs); return ret; @@ -2586,7 +2609,8 @@ static int criu_restore_memory_of_gpu(struct kfd_process_device *pdd, static int criu_restore_bo(struct kfd_process *p, struct kfd_criu_bo_bucket *bo_bucket, - struct kfd_criu_bo_priv_data *bo_priv) + struct kfd_criu_bo_priv_data *bo_priv, + struct file **file) { const uint32_t zero_handle[4] = { 0, 0, 0, 0 }; struct kfd_process_device *pdd; @@ -2645,7 +2669,7 @@ static int criu_restore_bo(struct kfd_process *p, if (bo_bucket->alloc_flags & (KFD_IOC_ALLOC_MEM_FLAGS_VRAM | KFD_IOC_ALLOC_MEM_FLAGS_GTT)) { ret = criu_get_prime_handle(kgd_mem, DRM_RDWR, - &bo_bucket->dmabuf_fd); + &bo_bucket->dmabuf_fd, file); if (ret) return ret; } else { @@ -2662,6 +2686,7 @@ static int criu_restore_bos(struct kfd_process *p, { struct kfd_criu_bo_bucket *bo_buckets = NULL; struct kfd_criu_bo_priv_data *bo_privs = NULL; + struct file **files = NULL; int ret = 0; uint32_t i = 0; @@ -2675,6 +2700,12 @@ static int criu_restore_bos(struct kfd_process *p, if (!bo_buckets) return -ENOMEM; + files = kvzalloc(args->num_bos * sizeof(struct file *), GFP_KERNEL); + if (!files) { + ret = -ENOMEM; + goto exit; + } + ret = copy_from_user(bo_buckets, (void __user *)args->bos, args->num_bos * sizeof(*bo_buckets)); if (ret) { @@ -2700,7 +2731,7 @@ static int criu_restore_bos(struct kfd_process *p, /* Create and map new BOs */ for (; i < args->num_bos; i++) { - ret = criu_restore_bo(p, &bo_buckets[i], &bo_privs[i]); + ret = criu_restore_bo(p, &bo_buckets[i], &bo_privs[i], &files[i]); if (ret) { pr_debug("Failed to restore BO[%d] ret%d\n", i, ret); goto exit; @@ -2715,11 +2746,8 @@ static int criu_restore_bos(struct kfd_process *p, ret = -EFAULT; exit: - while (ret && i--) { - if (bo_buckets[i].alloc_flags - & (KFD_IOC_ALLOC_MEM_FLAGS_VRAM | KFD_IOC_ALLOC_MEM_FLAGS_GTT)) - close_fd(bo_buckets[i].dmabuf_fd); - } + commit_files(files, bo_buckets, i, ret); + kvfree(files); kvfree(bo_buckets); kvfree(bo_privs); return ret; From 720e658268a836e0165a3fefa36968606966c834 Mon Sep 17 00:00:00 2001 From: Al Viro Date: Mon, 3 Jun 2024 21:49:16 -0400 Subject: [PATCH 1622/1868] drm/amdgpu: get rid of bogus includes of fdtable.h Signed-off-by: Al Viro Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c | 1 - drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c | 1 - 2 files changed, 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c index b9bf273289dd5..bb95ee172014b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.c @@ -20,7 +20,6 @@ * OTHER DEALINGS IN THE SOFTWARE. */ #include -#include #include #include #include "amdgpu.h" diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c index 863b2a34b2d64..f9ff493c100e6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sched.c @@ -22,7 +22,6 @@ * Authors: Andres Rodriguez */ -#include #include #include From 1755c3974e0a72d7d82fd9732948c5e28ca780b9 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Mon, 23 Sep 2024 13:22:28 +0800 Subject: [PATCH 1623/1868] drm/amdkcl: test drm_gem_prime_handle_to_dmabuf() is available It's caused by eeab2428df5a886d40c08f9847ea4d2c2fbce7e0 "drm/amdgpu: fix a race in kfd_mem_export_dmabuf()" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c | 14 ++++++++++++++ drivers/gpu/drm/amd/dkms/config/config.h | 3 +++ .../dkms/m4/drm_gem_prime_handle_to_dmabuf.m4 | 16 ++++++++++++++++ drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 + 4 files changed, 34 insertions(+) create mode 100644 drivers/gpu/drm/amd/dkms/m4/drm_gem_prime_handle_to_dmabuf.m4 diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c index 0aa94548aa514..105c3829bb98c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c @@ -25,6 +25,7 @@ #include #include #include +#include #include #include @@ -819,12 +820,25 @@ static int kfd_mem_export_dmabuf(struct kgd_mem *mem) if (!mem->dmabuf) { struct amdgpu_device *bo_adev; struct dma_buf *dmabuf; +#ifndef HAVE_DRM_GEM_PRIME_HANDLE_TO_DMABUF + int r, fd; + bo_adev = amdgpu_ttm_adev(mem->bo->tbo.bdev); + r = drm_gem_prime_handle_to_fd(&bo_adev->ddev, bo_adev->kfd.client.file, + mem->gem_handle, + mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ? + DRM_RDWR : 0, &fd); + if (r) + return r; + dmabuf = dma_buf_get(fd); + close_fd(fd); +#else bo_adev = amdgpu_ttm_adev(mem->bo->tbo.bdev); dmabuf = drm_gem_prime_handle_to_dmabuf(&bo_adev->ddev, bo_adev->kfd.client.file, mem->gem_handle, mem->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE ? DRM_RDWR : 0); +#endif if (IS_ERR(dmabuf)) return PTR_ERR(dmabuf); mem->dmabuf = dmabuf; diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index af1670609d2f2..1ce9545fdce37 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -542,6 +542,9 @@ /* drm_gem_plane_helper_prepare_fb() is available */ #define HAVE_DRM_GEM_PLANE_HELPER_PREPARE_FB 1 +/* drm_gem_prime_handle_to_dmabuf() is available */ +#define HAVE_DRM_GEM_PRIME_HANDLE_TO_DMABUF 1 + /* drm_gem_prime_handle_to_fd() is available */ #define HAVE_DRM_GEM_PRIME_HANDLE_TO_FD 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/drm_gem_prime_handle_to_dmabuf.m4 b/drivers/gpu/drm/amd/dkms/m4/drm_gem_prime_handle_to_dmabuf.m4 new file mode 100644 index 0000000000000..cfdf6da657222 --- /dev/null +++ b/drivers/gpu/drm/amd/dkms/m4/drm_gem_prime_handle_to_dmabuf.m4 @@ -0,0 +1,16 @@ +dnl # +dnl # commit v6.10-3140-ge9b641807e5e +dnl # drm: new helper: drm_gem_prime_handle_to_dmabuf() +dnl # +AC_DEFUN([AC_AMDGPU_DRM_GEM_PRIME_HANDLE_TO_DMABUF], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_TRY_COMPILE_SYMBOL([ + #include + ],[ + drm_gem_prime_handle_to_dmabuf(NULL, NULL, 0, 0); + ],[drm_gem_prime_handle_to_dmabuf],[drivers/gpu/drm/drm_prime.c],[ + AC_DEFINE(HAVE_DRM_GEM_PRIME_HANDLE_TO_DMABUF, 1, + [drm_gem_prime_handle_to_dmabuf() is available]) + ]) + ]) +]) diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index 7c525cf5e5f0f..c2a10026eb98e 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -213,6 +213,7 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_DRM_SUBALLOC_MANAGER_INIT AC_AMDGPU_VM_FLAGS_SET AC_AMDGPU_MMAP_ASSERT_WRITE_LOCKED + AC_AMDGPU_DRM_GEM_PRIME_HANDLE_TO_DMABUF AC_AMDGPU_PID_TYPE AC_AMDGPU_FOLLOW_PFN AC_AMDGPU_IMPORT_GUID From 9170b4874574f52da77094f99f5855a18ccfa417 Mon Sep 17 00:00:00 2001 From: "Lin.Cao" Date: Sun, 22 Sep 2024 20:40:48 +0800 Subject: [PATCH 1624/1868] drm/buddy: fix issue that force_merge cannot free all roots If buddy manager have more than one roots and each root have sub-block need to be free. When drm_buddy_fini called, the first loop of force_merge will merge and free all of the sub block of first root, which offset is 0x0 and size is biggest(more than have of the mm size). In subsequent force_merge rounds, if we use 0 as start and use remaining mm size as end, the block of other roots will be skipped in __force_merge function. It will cause the other roots can not be freed. Solution: use roots' offset as the start could fix this issue. Signed-off-by: Lin.Cao Reviewed-by: Arunpravin Paneer Selvam --- drivers/gpu/drm/drm_buddy.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/drm_buddy.c b/drivers/gpu/drm/drm_buddy.c index 103c185bb1c8a..ca42e6081d27c 100644 --- a/drivers/gpu/drm/drm_buddy.c +++ b/drivers/gpu/drm/drm_buddy.c @@ -324,7 +324,7 @@ EXPORT_SYMBOL(drm_buddy_init); */ void drm_buddy_fini(struct drm_buddy *mm) { - u64 root_size, size; + u64 root_size, size, start; unsigned int order; int i; @@ -332,7 +332,8 @@ void drm_buddy_fini(struct drm_buddy *mm) for (i = 0; i < mm->n_roots; ++i) { order = ilog2(size) - ilog2(mm->chunk_size); - __force_merge(mm, 0, size, order); + start = drm_buddy_block_offset(mm->roots[i]); + __force_merge(mm, start, start + size, order); WARN_ON(!drm_buddy_block_is_free(mm->roots[i])); drm_block_free(mm, mm->roots[i]); From 64989ae0f0f5d6ae38619c43759376a27cd78bdc Mon Sep 17 00:00:00 2001 From: Tim Huang Date: Thu, 1 Aug 2024 14:04:52 +0800 Subject: [PATCH 1625/1868] drm/amdgpu: check return for setting engine dram timings This resolves the unchecded return value warning reported by Coverity. Signed-off-by: Tim Huang Reviewed-by: Jesse Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c | 8 ++++---- drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h | 4 ++-- drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 8 +++++--- 3 files changed, 11 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c index 4414b55605359..7abbec85fb6ec 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c @@ -1145,8 +1145,8 @@ int amdgpu_atombios_get_memory_pll_dividers(struct amdgpu_device *adev, return 0; } -void amdgpu_atombios_set_engine_dram_timings(struct amdgpu_device *adev, - u32 eng_clock, u32 mem_clock) +int amdgpu_atombios_set_engine_dram_timings(struct amdgpu_device *adev, + u32 eng_clock, u32 mem_clock) { SET_ENGINE_CLOCK_PS_ALLOCATION args; int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings); @@ -1161,8 +1161,8 @@ void amdgpu_atombios_set_engine_dram_timings(struct amdgpu_device *adev, if (mem_clock) args.sReserved.ulClock = cpu_to_le32(mem_clock & SET_CLOCK_FREQ_MASK); - amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args, - sizeof(args)); + return amdgpu_atom_execute_table(adev->mode_info.atom_context, index, + (uint32_t *)&args, sizeof(args)); } void amdgpu_atombios_get_default_voltages(struct amdgpu_device *adev, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h index b2f13ad336af2..442cc70474775 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h @@ -163,8 +163,8 @@ int amdgpu_atombios_get_memory_pll_dividers(struct amdgpu_device *adev, bool strobe_mode, struct atom_mpll_param *mpll_param); -void amdgpu_atombios_set_engine_dram_timings(struct amdgpu_device *adev, - u32 eng_clock, u32 mem_clock); +int amdgpu_atombios_set_engine_dram_timings(struct amdgpu_device *adev, + u32 eng_clock, u32 mem_clock); bool amdgpu_atombios_is_voltage_gpio(struct amdgpu_device *adev, diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c index a1baa13ab2c26..43028e776c932 100644 --- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c @@ -4755,13 +4755,15 @@ static int si_populate_memory_timing_parameters(struct amdgpu_device *adev, u32 dram_timing; u32 dram_timing2; u32 burst_time; + int ret; arb_regs->mc_arb_rfsh_rate = (u8)si_calculate_memory_refresh_rate(adev, pl->sclk); - amdgpu_atombios_set_engine_dram_timings(adev, - pl->sclk, - pl->mclk); + ret = amdgpu_atombios_set_engine_dram_timings(adev, pl->sclk, + pl->mclk); + if (ret) + return ret; dram_timing = RREG32(MC_ARB_DRAM_TIMING); dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); From a11d86314312f217f2cb6920bd9d27708fcbe189 Mon Sep 17 00:00:00 2001 From: Mukul Joshi Date: Mon, 16 Sep 2024 14:33:58 -0400 Subject: [PATCH 1626/1868] drm/amdkfd: Update logic for CU occupancy calculations Currently, the code uses the IH_VMID_X_LUT register to map a queue's vmid to the corresponding PASID. This logic is racy since CP can update the VMID-PASID mapping anytime especially when there are more processes than number of vmids. Update the logic to calculate CU occupancy by matching doorbell offset of the queue with valid wave counts against the process's queues. Signed-off-by: Mukul Joshi Reviewed-by: Harish Kasiviswanathan --- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 102 ++++++++---------- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h | 5 +- .../drm/amd/amdkfd/kfd_device_queue_manager.c | 20 ++++ .../drm/amd/amdkfd/kfd_device_queue_manager.h | 3 + drivers/gpu/drm/amd/amdkfd/kfd_process.c | 14 ++- .../gpu/drm/amd/include/kgd_kfd_interface.h | 10 +- 6 files changed, 89 insertions(+), 65 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c index 0173c606c0491..0f536c96d5dfc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c @@ -950,28 +950,30 @@ static void unlock_spi_csq_mutexes(struct amdgpu_device *adev) * @inst: xcc's instance number on a multi-XCC setup */ static void get_wave_count(struct amdgpu_device *adev, int queue_idx, - int *wave_cnt, int *vmid, uint32_t inst) + struct kfd_cu_occupancy *queue_cnt, uint32_t inst) { int pipe_idx; int queue_slot; unsigned int reg_val; - + unsigned int wave_cnt; /* * Program GRBM with appropriate MEID, PIPEID, QUEUEID and VMID * parameters to read out waves in flight. Get VMID if there are * non-zero waves in flight. */ - *vmid = 0xFF; - *wave_cnt = 0; pipe_idx = queue_idx / adev->gfx.mec.num_queue_per_pipe; queue_slot = queue_idx % adev->gfx.mec.num_queue_per_pipe; soc15_grbm_select(adev, 1, pipe_idx, queue_slot, 0, inst); - reg_val = RREG32_SOC15_IP(GC, SOC15_REG_OFFSET(GC, inst, mmSPI_CSQ_WF_ACTIVE_COUNT_0) + - queue_slot); - *wave_cnt = reg_val & SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK; - if (*wave_cnt != 0) - *vmid = (RREG32_SOC15(GC, inst, mmCP_HQD_VMID) & - CP_HQD_VMID__VMID_MASK) >> CP_HQD_VMID__VMID__SHIFT; + reg_val = RREG32_SOC15_IP(GC, SOC15_REG_OFFSET(GC, inst, + mmSPI_CSQ_WF_ACTIVE_COUNT_0) + queue_slot); + wave_cnt = reg_val & SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK; + if (wave_cnt != 0) { + queue_cnt->wave_cnt += wave_cnt; + queue_cnt->doorbell_off = + (RREG32_SOC15(GC, inst, mmCP_HQD_PQ_DOORBELL_CONTROL) & + CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK) >> + CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT; + } } /** @@ -981,9 +983,8 @@ static void get_wave_count(struct amdgpu_device *adev, int queue_idx, * or more queues running and submitting waves to compute units. * * @adev: Handle of device from which to get number of waves in flight - * @pasid: Identifies the process for which this query call is invoked - * @pasid_wave_cnt: Output parameter updated with number of waves in flight that - * belong to process with given pasid + * @cu_occupancy: Array that gets filled with wave_cnt and doorbell offset + * for comparison later. * @max_waves_per_cu: Output parameter updated with maximum number of waves * possible per Compute Unit * @inst: xcc's instance number on a multi-XCC setup @@ -1011,30 +1012,24 @@ static void get_wave_count(struct amdgpu_device *adev, int queue_idx, * number of waves that are in flight for the queue at specified index. The * index ranges from 0 to 7. * - * If non-zero waves are in flight, read CP_HQD_VMID register to obtain VMID - * of the wave(s). + * If non-zero waves are in flight, store the corresponding doorbell offset + * of the queue, along with the wave count. * - * Determine if VMID from above step maps to pasid provided as parameter. If - * it matches agrregate the wave count. That the VMID will not match pasid is - * a normal condition i.e. a device is expected to support multiple queues - * from multiple proceses. + * Determine if the queue belongs to the process by comparing the doorbell + * offset against the process's queues. If it matches, aggregate the wave + * count for the process. * * Reading registers referenced above involves programming GRBM appropriately */ -void kgd_gfx_v9_get_cu_occupancy(struct amdgpu_device *adev, int pasid, - int *pasid_wave_cnt, int *max_waves_per_cu, uint32_t inst) +void kgd_gfx_v9_get_cu_occupancy(struct amdgpu_device *adev, + struct kfd_cu_occupancy *cu_occupancy, + int *max_waves_per_cu, uint32_t inst) { int qidx; - int vmid; int se_idx; - int sh_idx; int se_cnt; - int sh_cnt; - int wave_cnt; int queue_map; - int pasid_tmp; int max_queue_cnt; - int vmid_wave_cnt = 0; DECLARE_BITMAP(cp_queue_bitmap, AMDGPU_MAX_QUEUES); lock_spi_csq_mutexes(adev); @@ -1048,42 +1043,30 @@ void kgd_gfx_v9_get_cu_occupancy(struct amdgpu_device *adev, int pasid, AMDGPU_MAX_QUEUES); max_queue_cnt = adev->gfx.mec.num_pipe_per_mec * adev->gfx.mec.num_queue_per_pipe; - sh_cnt = adev->gfx.config.max_sh_per_se; se_cnt = adev->gfx.config.max_shader_engines; for (se_idx = 0; se_idx < se_cnt; se_idx++) { - for (sh_idx = 0; sh_idx < sh_cnt; sh_idx++) { + amdgpu_gfx_select_se_sh(adev, se_idx, 0, 0xffffffff, inst); + queue_map = RREG32_SOC15(GC, inst, mmSPI_CSQ_WF_ACTIVE_STATUS); + + /* + * Assumption: queue map encodes following schema: four + * pipes per each micro-engine, with each pipe mapping + * eight queues. This schema is true for GFX9 devices + * and must be verified for newer device families + */ + for (qidx = 0; qidx < max_queue_cnt; qidx++) { + /* Skip qeueus that are not associated with + * compute functions + */ + if (!test_bit(qidx, cp_queue_bitmap)) + continue; - amdgpu_gfx_select_se_sh(adev, se_idx, sh_idx, 0xffffffff, inst); - queue_map = RREG32_SOC15(GC, inst, mmSPI_CSQ_WF_ACTIVE_STATUS); + if (!(queue_map & (1 << qidx))) + continue; - /* - * Assumption: queue map encodes following schema: four - * pipes per each micro-engine, with each pipe mapping - * eight queues. This schema is true for GFX9 devices - * and must be verified for newer device families - */ - for (qidx = 0; qidx < max_queue_cnt; qidx++) { - - /* Skip qeueus that are not associated with - * compute functions - */ - if (!test_bit(qidx, cp_queue_bitmap)) - continue; - - if (!(queue_map & (1 << qidx))) - continue; - - /* Get number of waves in flight and aggregate them */ - get_wave_count(adev, qidx, &wave_cnt, &vmid, - inst); - if (wave_cnt != 0) { - pasid_tmp = - RREG32(SOC15_REG_OFFSET(OSSSYS, inst, - mmIH_VMID_0_LUT) + vmid); - if (pasid_tmp == pasid) - vmid_wave_cnt += wave_cnt; - } - } + /* Get number of waves in flight and aggregate them */ + get_wave_count(adev, qidx, &cu_occupancy[qidx], + inst); } } @@ -1092,7 +1075,6 @@ void kgd_gfx_v9_get_cu_occupancy(struct amdgpu_device *adev, int pasid, unlock_spi_csq_mutexes(adev); /* Update the output parameters and return */ - *pasid_wave_cnt = vmid_wave_cnt; *max_waves_per_cu = adev->gfx.cu_info.simd_per_cu * adev->gfx.cu_info.max_waves_per_simd; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h index d2eba1a137407..ad9b26be3bb4c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h @@ -52,8 +52,9 @@ bool kgd_gfx_v9_get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev, uint8_t vmid, uint16_t *p_pasid); void kgd_gfx_v9_set_vm_context_page_table_base(struct amdgpu_device *adev, uint32_t vmid, uint64_t page_table_base); -void kgd_gfx_v9_get_cu_occupancy(struct amdgpu_device *adev, int pasid, - int *pasid_wave_cnt, int *max_waves_per_cu, uint32_t inst); +void kgd_gfx_v9_get_cu_occupancy(struct amdgpu_device *adev, + struct kfd_cu_occupancy *cu_occupancy, + int *max_waves_per_cu, uint32_t inst); void kgd_gfx_v9_program_trap_handler_settings(struct amdgpu_device *adev, uint32_t vmid, uint64_t tba_addr, uint64_t tma_addr, uint32_t inst); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index 56b0ba718319b..1fc15e8d0ed9b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -3577,6 +3577,26 @@ void remap_queue(struct device_queue_manager *dqm, dqm_unlock(dqm); } +bool kfd_dqm_is_queue_in_process(struct device_queue_manager *dqm, + struct qcm_process_device *qpd, + int doorbell_off) +{ + struct queue *q; + bool r = false; + + dqm_lock(dqm); + + list_for_each_entry(q, &qpd->queues_list, list) { + if (q->properties.doorbell_off == doorbell_off) { + r = true; + goto out; + } + } + +out: + dqm_unlock(dqm); + return r; +} #if defined(CONFIG_DEBUG_FS) static void seq_reg_dump(struct seq_file *m, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h index 596e8058cd855..8a3fb68f45645 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h @@ -326,6 +326,9 @@ void set_queue_snapshot_entry(struct queue *q, int debug_lock_and_unmap(struct device_queue_manager *dqm); int debug_map_and_unlock(struct device_queue_manager *dqm); int debug_refresh_runlist(struct device_queue_manager *dqm); +bool kfd_dqm_is_queue_in_process(struct device_queue_manager *dqm, + struct qcm_process_device *qpd, + int doorbell_off); void remap_queue(struct device_queue_manager *dqm, enum kfd_unmap_queues_filter filter, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 4be8e0c99f84a..6f66deddab764 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -274,6 +274,10 @@ static int kfd_get_cu_occupancy(struct attribute *attr, char *buffer) struct kfd_node *dev = NULL; struct kfd_process *proc = NULL; struct kfd_process_device *pdd = NULL; + int i; + struct kfd_cu_occupancy cu_occupancy[AMDGPU_MAX_QUEUES]; + + memset(cu_occupancy, 0x0, sizeof(cu_occupancy)); pdd = container_of(attr, struct kfd_process_device, attr_cu_occupancy); dev = pdd->dev; @@ -291,9 +295,17 @@ static int kfd_get_cu_occupancy(struct attribute *attr, char *buffer) /* Collect wave count from device if it supports */ wave_cnt = 0; max_waves_per_cu = 0; - dev->kfd2kgd->get_cu_occupancy(dev->adev, proc->pasid, &wave_cnt, + + dev->kfd2kgd->get_cu_occupancy(dev->adev, cu_occupancy, &max_waves_per_cu, 0); + for (i = 0; i < AMDGPU_MAX_QUEUES; i++) { + if (cu_occupancy[i].wave_cnt != 0 && + kfd_dqm_is_queue_in_process(dev->dqm, &pdd->qpd, + cu_occupancy[i].doorbell_off)) + wave_cnt += cu_occupancy[i].wave_cnt; + } + /* Translate wave count to number of compute units */ cu_cnt = (wave_cnt + (max_waves_per_cu - 1)) / max_waves_per_cu; return snprintf(buffer, PAGE_SIZE, "%d\n", cu_cnt); diff --git a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h index 3393b9c80bd2f..f221e5bee50fc 100644 --- a/drivers/gpu/drm/amd/include/kgd_kfd_interface.h +++ b/drivers/gpu/drm/amd/include/kgd_kfd_interface.h @@ -73,6 +73,11 @@ enum kgd_memory_pool { KGD_POOL_FRAMEBUFFER = 3, }; +struct kfd_cu_occupancy { + u32 wave_cnt; + u32 doorbell_off; +}; + /** * enum kfd_sched_policy * @@ -320,8 +325,9 @@ struct kfd2kgd_calls { uint32_t grace_period, uint32_t *reg_offset, uint32_t *reg_data); - void (*get_cu_occupancy)(struct amdgpu_device *adev, int pasid, - int *wave_cnt, int *max_waves_per_cu, uint32_t inst); + void (*get_cu_occupancy)(struct amdgpu_device *adev, + struct kfd_cu_occupancy *cu_occupancy, + int *max_waves_per_cu, uint32_t inst); void (*program_trap_handler_settings)(struct amdgpu_device *adev, uint32_t vmid, uint64_t tba_addr, uint64_t tma_addr, uint32_t inst); From e3a24aaa3b8cd3d1af98955bbaf87c3ccad21524 Mon Sep 17 00:00:00 2001 From: Mukul Joshi Date: Fri, 20 Sep 2024 14:59:29 -0400 Subject: [PATCH 1627/1868] drm/amdkfd: Fix CU occupancy for GFX 9.4.3 Make CU occupancy calculations work on GFX 9.4.3 by updating the logic to handle multiple XCCs correctly. Signed-off-by: Mukul Joshi Reviewed-by: Harish Kasiviswanathan --- .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 12 +++++------ .../drm/amd/amdkfd/kfd_device_queue_manager.c | 6 +++++- .../drm/amd/amdkfd/kfd_device_queue_manager.h | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 20 ++++++++++++++++--- 4 files changed, 29 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c index 0f536c96d5dfc..52a8aea4d9b26 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c @@ -963,14 +963,14 @@ static void get_wave_count(struct amdgpu_device *adev, int queue_idx, */ pipe_idx = queue_idx / adev->gfx.mec.num_queue_per_pipe; queue_slot = queue_idx % adev->gfx.mec.num_queue_per_pipe; - soc15_grbm_select(adev, 1, pipe_idx, queue_slot, 0, inst); - reg_val = RREG32_SOC15_IP(GC, SOC15_REG_OFFSET(GC, inst, + soc15_grbm_select(adev, 1, pipe_idx, queue_slot, 0, GET_INST(GC, inst)); + reg_val = RREG32_SOC15_IP(GC, SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmSPI_CSQ_WF_ACTIVE_COUNT_0) + queue_slot); wave_cnt = reg_val & SPI_CSQ_WF_ACTIVE_COUNT_0__COUNT_MASK; if (wave_cnt != 0) { queue_cnt->wave_cnt += wave_cnt; queue_cnt->doorbell_off = - (RREG32_SOC15(GC, inst, mmCP_HQD_PQ_DOORBELL_CONTROL) & + (RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_PQ_DOORBELL_CONTROL) & CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET_MASK) >> CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT; } @@ -1033,7 +1033,7 @@ void kgd_gfx_v9_get_cu_occupancy(struct amdgpu_device *adev, DECLARE_BITMAP(cp_queue_bitmap, AMDGPU_MAX_QUEUES); lock_spi_csq_mutexes(adev); - soc15_grbm_select(adev, 1, 0, 0, 0, inst); + soc15_grbm_select(adev, 1, 0, 0, 0, GET_INST(GC, inst)); /* * Iterate through the shader engines and arrays of the device @@ -1046,7 +1046,7 @@ void kgd_gfx_v9_get_cu_occupancy(struct amdgpu_device *adev, se_cnt = adev->gfx.config.max_shader_engines; for (se_idx = 0; se_idx < se_cnt; se_idx++) { amdgpu_gfx_select_se_sh(adev, se_idx, 0, 0xffffffff, inst); - queue_map = RREG32_SOC15(GC, inst, mmSPI_CSQ_WF_ACTIVE_STATUS); + queue_map = RREG32_SOC15(GC, GET_INST(GC, inst), mmSPI_CSQ_WF_ACTIVE_STATUS); /* * Assumption: queue map encodes following schema: four @@ -1071,7 +1071,7 @@ void kgd_gfx_v9_get_cu_occupancy(struct amdgpu_device *adev, } amdgpu_gfx_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, inst); - soc15_grbm_select(adev, 0, 0, 0, 0, inst); + soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, inst)); unlock_spi_csq_mutexes(adev); /* Update the output parameters and return */ diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index 1fc15e8d0ed9b..6a5d50242d474 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -3579,15 +3579,19 @@ void remap_queue(struct device_queue_manager *dqm, bool kfd_dqm_is_queue_in_process(struct device_queue_manager *dqm, struct qcm_process_device *qpd, - int doorbell_off) + int doorbell_off, u32 *queue_format) { struct queue *q; bool r = false; + if (!queue_format) + return r; + dqm_lock(dqm); list_for_each_entry(q, &qpd->queues_list, list) { if (q->properties.doorbell_off == doorbell_off) { + *queue_format = q->properties.format; r = true; goto out; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h index 8a3fb68f45645..75bdc066166c2 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h @@ -328,7 +328,7 @@ int debug_map_and_unlock(struct device_queue_manager *dqm); int debug_refresh_runlist(struct device_queue_manager *dqm); bool kfd_dqm_is_queue_in_process(struct device_queue_manager *dqm, struct qcm_process_device *qpd, - int doorbell_off); + int doorbell_off, u32 *queue_format); void remap_queue(struct device_queue_manager *dqm, enum kfd_unmap_queues_filter filter, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index 6f66deddab764..cde8d34fc4394 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -276,6 +276,7 @@ static int kfd_get_cu_occupancy(struct attribute *attr, char *buffer) struct kfd_process_device *pdd = NULL; int i; struct kfd_cu_occupancy cu_occupancy[AMDGPU_MAX_QUEUES]; + u32 queue_format; memset(cu_occupancy, 0x0, sizeof(cu_occupancy)); @@ -296,14 +297,27 @@ static int kfd_get_cu_occupancy(struct attribute *attr, char *buffer) wave_cnt = 0; max_waves_per_cu = 0; + /* + * For GFX 9.4.3, fetch the CU occupancy from the first XCC in the partition. + * For AQL queues, because of cooperative dispatch we multiply the wave count + * by number of XCCs in the partition to get the total wave counts across all + * XCCs in the partition. + * For PM4 queues, there is no cooperative dispatch so wave_cnt stay as it is. + */ dev->kfd2kgd->get_cu_occupancy(dev->adev, cu_occupancy, - &max_waves_per_cu, 0); + &max_waves_per_cu, ffs(dev->xcc_mask) - 1); for (i = 0; i < AMDGPU_MAX_QUEUES; i++) { if (cu_occupancy[i].wave_cnt != 0 && kfd_dqm_is_queue_in_process(dev->dqm, &pdd->qpd, - cu_occupancy[i].doorbell_off)) - wave_cnt += cu_occupancy[i].wave_cnt; + cu_occupancy[i].doorbell_off, + &queue_format)) { + if (unlikely(queue_format == KFD_QUEUE_FORMAT_PM4)) + wave_cnt += cu_occupancy[i].wave_cnt; + else + wave_cnt += (NUM_XCC(dev->xcc_mask) * + cu_occupancy[i].wave_cnt); + } } /* Translate wave count to number of compute units */ From d85d6a1d320e0c456289774f96f3b1ea1ab02d5b Mon Sep 17 00:00:00 2001 From: Saleemkhan Jamadar Date: Fri, 20 Sep 2024 18:40:18 +0530 Subject: [PATCH 1628/1868] drm/amdgpu/vcn: enable AV1 on both instances v1 - remove cs parse code (Christian) On VCN v4_0_6 AV1 is supported on both the instances. Remove cs IB parse code since explict handling of AV1 schedule is not required. Signed-off-by: Saleemkhan Jamadar Reviewed-by: Leo Liu --- drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 165 ------------------------ 1 file changed, 165 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c index b1fd226b7efb4..9d4f5352a62c8 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c @@ -1395,170 +1395,6 @@ static void vcn_v4_0_5_unified_ring_set_wptr(struct amdgpu_ring *ring) } } -static int vcn_v4_0_5_limit_sched(struct amdgpu_cs_parser *p, - struct amdgpu_job *job) -{ - struct drm_gpu_scheduler **scheds; - - /* The create msg must be in the first IB submitted */ - if (atomic_read(&job->base.entity->fence_seq)) - return -EINVAL; - - /* if VCN0 is harvested, we can't support AV1 */ - if (p->adev->vcn.harvest_config & AMDGPU_VCN_HARVEST_VCN0) - return -EINVAL; - - scheds = p->adev->gpu_sched[AMDGPU_HW_IP_VCN_ENC] - [AMDGPU_RING_PRIO_0].sched; - drm_sched_entity_modify_sched(job->base.entity, scheds, 1); - return 0; -} - -static int vcn_v4_0_5_dec_msg(struct amdgpu_cs_parser *p, struct amdgpu_job *job, - uint64_t addr) -{ - struct ttm_operation_ctx ctx = { false, false }; - struct amdgpu_bo_va_mapping *map; - uint32_t *msg, num_buffers; - struct amdgpu_bo *bo; - uint64_t start, end; - unsigned int i; - void *ptr; - int r; - - addr &= AMDGPU_GMC_HOLE_MASK; - r = amdgpu_cs_find_mapping(p, addr, &bo, &map); - if (r) { - DRM_ERROR("Can't find BO for addr 0x%08llx\n", addr); - return r; - } - - start = map->start * AMDGPU_GPU_PAGE_SIZE; - end = (map->last + 1) * AMDGPU_GPU_PAGE_SIZE; - if (addr & 0x7) { - DRM_ERROR("VCN messages must be 8 byte aligned!\n"); - return -EINVAL; - } - - bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED; - amdgpu_bo_placement_from_domain(bo, bo->allowed_domains); - r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); - if (r) { - DRM_ERROR("Failed validating the VCN message BO (%d)!\n", r); - return r; - } - - r = amdgpu_bo_kmap(bo, &ptr); - if (r) { - DRM_ERROR("Failed mapping the VCN message (%d)!\n", r); - return r; - } - - msg = ptr + addr - start; - - /* Check length */ - if (msg[1] > end - addr) { - r = -EINVAL; - goto out; - } - - if (msg[3] != RDECODE_MSG_CREATE) - goto out; - - num_buffers = msg[2]; - for (i = 0, msg = &msg[6]; i < num_buffers; ++i, msg += 4) { - uint32_t offset, size, *create; - - if (msg[0] != RDECODE_MESSAGE_CREATE) - continue; - - offset = msg[1]; - size = msg[2]; - - if (offset + size > end) { - r = -EINVAL; - goto out; - } - - create = ptr + addr + offset - start; - - /* H264, HEVC and VP9 can run on any instance */ - if (create[0] == 0x7 || create[0] == 0x10 || create[0] == 0x11) - continue; - - r = vcn_v4_0_5_limit_sched(p, job); - if (r) - goto out; - } - -out: - amdgpu_bo_kunmap(bo); - return r; -} - -#define RADEON_VCN_ENGINE_TYPE_ENCODE (0x00000002) -#define RADEON_VCN_ENGINE_TYPE_DECODE (0x00000003) - -#define RADEON_VCN_ENGINE_INFO (0x30000001) -#define RADEON_VCN_ENGINE_INFO_MAX_OFFSET 16 - -#define RENCODE_ENCODE_STANDARD_AV1 2 -#define RENCODE_IB_PARAM_SESSION_INIT 0x00000003 -#define RENCODE_IB_PARAM_SESSION_INIT_MAX_OFFSET 64 - -/* return the offset in ib if id is found, -1 otherwise - * to speed up the searching we only search upto max_offset - */ -static int vcn_v4_0_5_enc_find_ib_param(struct amdgpu_ib *ib, uint32_t id, int max_offset) -{ - int i; - - for (i = 0; i < ib->length_dw && i < max_offset && ib->ptr[i] >= 8; i += ib->ptr[i]/4) { - if (ib->ptr[i + 1] == id) - return i; - } - return -1; -} - -static int vcn_v4_0_5_ring_patch_cs_in_place(struct amdgpu_cs_parser *p, - struct amdgpu_job *job, - struct amdgpu_ib *ib) -{ - struct amdgpu_ring *ring = amdgpu_job_ring(job); - struct amdgpu_vcn_decode_buffer *decode_buffer; - uint64_t addr; - uint32_t val; - int idx; - - /* The first instance can decode anything */ - if (!ring->me) - return 0; - - /* RADEON_VCN_ENGINE_INFO is at the top of ib block */ - idx = vcn_v4_0_5_enc_find_ib_param(ib, RADEON_VCN_ENGINE_INFO, - RADEON_VCN_ENGINE_INFO_MAX_OFFSET); - if (idx < 0) /* engine info is missing */ - return 0; - - val = amdgpu_ib_get_value(ib, idx + 2); /* RADEON_VCN_ENGINE_TYPE */ - if (val == RADEON_VCN_ENGINE_TYPE_DECODE) { - decode_buffer = (struct amdgpu_vcn_decode_buffer *)&ib->ptr[idx + 6]; - - if (!(decode_buffer->valid_buf_flag & 0x1)) - return 0; - - addr = ((u64)decode_buffer->msg_buffer_address_hi) << 32 | - decode_buffer->msg_buffer_address_lo; - return vcn_v4_0_5_dec_msg(p, job, addr); - } else if (val == RADEON_VCN_ENGINE_TYPE_ENCODE) { - idx = vcn_v4_0_5_enc_find_ib_param(ib, RENCODE_IB_PARAM_SESSION_INIT, - RENCODE_IB_PARAM_SESSION_INIT_MAX_OFFSET); - if (idx >= 0 && ib->ptr[idx + 2] == RENCODE_ENCODE_STANDARD_AV1) - return vcn_v4_0_5_limit_sched(p, job); - } - return 0; -} - static const struct amdgpu_ring_funcs vcn_v4_0_5_unified_ring_vm_funcs = { .type = AMDGPU_RING_TYPE_VCN_ENC, .align_mask = 0x3f, @@ -1566,7 +1402,6 @@ static const struct amdgpu_ring_funcs vcn_v4_0_5_unified_ring_vm_funcs = { .get_rptr = vcn_v4_0_5_unified_ring_get_rptr, .get_wptr = vcn_v4_0_5_unified_ring_get_wptr, .set_wptr = vcn_v4_0_5_unified_ring_set_wptr, - .patch_cs_in_place = vcn_v4_0_5_ring_patch_cs_in_place, .emit_frame_size = SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 + SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 + From 0a81779c006ca00f8cfdcf357ffa66d8ba8605ee Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Mon, 26 Aug 2024 11:46:26 +0530 Subject: [PATCH 1629/1868] drm/amdgpu: Separate reinitialization after reset Move the reinitialization part after a reset to another function. No functional changes. Signed-off-by: Lijo Lazar Reviewed-by: Feifei Xu Acked-by: Alex Deucher Acked-by: Rajneesh Bhardwaj Tested-by: Rajneesh Bhardwaj --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 150 ++++++++++++--------- 2 files changed, 89 insertions(+), 63 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 3b218e62f9c28..6c4c0e86fb37c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1307,6 +1307,8 @@ int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, int amdgpu_do_asic_reset(struct list_head *device_list_handle, struct amdgpu_reset_context *reset_context); +int amdgpu_device_reinit_after_reset(struct amdgpu_reset_context *reset_context); + int emu_soc_asic_init(struct amdgpu_device *adev); /* diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 152da318ca3a2..5e36e8f06035c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -5419,75 +5419,25 @@ int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, return r; } -int amdgpu_do_asic_reset(struct list_head *device_list_handle, - struct amdgpu_reset_context *reset_context) +int amdgpu_device_reinit_after_reset(struct amdgpu_reset_context *reset_context) { - struct amdgpu_device *tmp_adev = NULL; - bool need_full_reset, skip_hw_reset, vram_lost = false; - int r = 0; - - /* Try reset handler method first */ - tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device, - reset_list); - - reset_context->reset_device_list = device_list_handle; - r = amdgpu_reset_perform_reset(tmp_adev, reset_context); - /* If reset handler not implemented, continue; otherwise return */ - if (r == -EOPNOTSUPP) - r = 0; - else - return r; - - /* Reset handler not implemented, use the default method */ - need_full_reset = - test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags); - skip_hw_reset = test_bit(AMDGPU_SKIP_HW_RESET, &reset_context->flags); - - /* - * ASIC reset has to be done on all XGMI hive nodes ASAP - * to allow proper links negotiation in FW (within 1 sec) - */ - if (!skip_hw_reset && need_full_reset) { - list_for_each_entry(tmp_adev, device_list_handle, reset_list) { - /* For XGMI run all resets in parallel to speed up the process */ - if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) { - if (!queue_work(system_unbound_wq, &tmp_adev->xgmi_reset_work)) - r = -EALREADY; - } else - r = amdgpu_asic_reset(tmp_adev); - - if (r) { - dev_err(tmp_adev->dev, "ASIC reset failed with error, %d for drm dev, %s", - r, adev_to_drm(tmp_adev)->unique); - goto out; - } - } + struct list_head *device_list_handle; + bool full_reset, vram_lost = false; + struct amdgpu_device *tmp_adev; + int r; - /* For XGMI wait for all resets to complete before proceed */ - if (!r) { - list_for_each_entry(tmp_adev, device_list_handle, reset_list) { - if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) { - flush_work(&tmp_adev->xgmi_reset_work); - r = tmp_adev->asic_reset_res; - if (r) - break; - } - } - } - } + device_list_handle = reset_context->reset_device_list; - if (!r && amdgpu_ras_intr_triggered()) { - list_for_each_entry(tmp_adev, device_list_handle, reset_list) { - amdgpu_ras_reset_error_count(tmp_adev, AMDGPU_RAS_BLOCK__MMHUB); - } + if (!device_list_handle) + return -EINVAL; - amdgpu_ras_intr_cleared(); - } + full_reset = test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags); + r = 0; list_for_each_entry(tmp_adev, device_list_handle, reset_list) { /* After reset, it's default init level */ amdgpu_set_init_level(tmp_adev, AMDGPU_INIT_LEVEL_DEFAULT); - if (need_full_reset) { + if (full_reset) { /* post card */ amdgpu_ras_set_fed(tmp_adev, false); r = amdgpu_device_asic_init(tmp_adev); @@ -5577,7 +5527,6 @@ int amdgpu_do_asic_reset(struct list_head *device_list_handle, r = amdgpu_ib_ring_tests(tmp_adev); if (r) { dev_err(tmp_adev->dev, "ib ring test failed (%d).\n", r); - need_full_reset = true; r = -EAGAIN; goto end; } @@ -5588,10 +5537,85 @@ int amdgpu_do_asic_reset(struct list_head *device_list_handle, } end: - if (need_full_reset) + return r; +} + +int amdgpu_do_asic_reset(struct list_head *device_list_handle, + struct amdgpu_reset_context *reset_context) +{ + struct amdgpu_device *tmp_adev = NULL; + bool need_full_reset, skip_hw_reset; + int r = 0; + + /* Try reset handler method first */ + tmp_adev = list_first_entry(device_list_handle, struct amdgpu_device, + reset_list); + + reset_context->reset_device_list = device_list_handle; + r = amdgpu_reset_perform_reset(tmp_adev, reset_context); + /* If reset handler not implemented, continue; otherwise return */ + if (r == -EOPNOTSUPP) + r = 0; + else + return r; + + /* Reset handler not implemented, use the default method */ + need_full_reset = + test_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags); + skip_hw_reset = test_bit(AMDGPU_SKIP_HW_RESET, &reset_context->flags); + + /* + * ASIC reset has to be done on all XGMI hive nodes ASAP + * to allow proper links negotiation in FW (within 1 sec) + */ + if (!skip_hw_reset && need_full_reset) { + list_for_each_entry(tmp_adev, device_list_handle, reset_list) { + /* For XGMI run all resets in parallel to speed up the process */ + if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) { + if (!queue_work(system_unbound_wq, + &tmp_adev->xgmi_reset_work)) + r = -EALREADY; + } else + r = amdgpu_asic_reset(tmp_adev); + + if (r) { + dev_err(tmp_adev->dev, + "ASIC reset failed with error, %d for drm dev, %s", + r, adev_to_drm(tmp_adev)->unique); + goto out; + } + } + + /* For XGMI wait for all resets to complete before proceed */ + if (!r) { + list_for_each_entry(tmp_adev, device_list_handle, + reset_list) { + if (tmp_adev->gmc.xgmi.num_physical_nodes > 1) { + flush_work(&tmp_adev->xgmi_reset_work); + r = tmp_adev->asic_reset_res; + if (r) + break; + } + } + } + } + + if (!r && amdgpu_ras_intr_triggered()) { + list_for_each_entry(tmp_adev, device_list_handle, reset_list) { + amdgpu_ras_reset_error_count(tmp_adev, + AMDGPU_RAS_BLOCK__MMHUB); + } + + amdgpu_ras_intr_cleared(); + } + + r = amdgpu_device_reinit_after_reset(reset_context); + if (r == -EAGAIN) set_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags); else clear_bit(AMDGPU_NEED_FULL_RESET, &reset_context->flags); + +out: return r; } From 28cd85cf5301882ed2dcffd6357f082dc1d105ae Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Tue, 24 Sep 2024 18:16:29 +0530 Subject: [PATCH 1630/1868] drm/amdgpu: add amdgpu_device reference in ip block MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit To handle amdgpu_device reference for different GPUs we add it's reference in each ip block which can be used to differentiate between difference gpu devices. Signed-off-by: Sunil Khatri Suggested-by: Christian König Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 6c4c0e86fb37c..d6e9e4fc81af1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -392,6 +392,7 @@ struct amdgpu_ip_block_version { struct amdgpu_ip_block { struct amdgpu_ip_block_status status; const struct amdgpu_ip_block_version *version; + struct amdgpu_device *adev; }; int amdgpu_device_ip_block_version_cmp(struct amdgpu_device *adev, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 5e36e8f06035c..83ae2d47804c2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -2358,6 +2358,8 @@ int amdgpu_device_ip_block_add(struct amdgpu_device *adev, DRM_INFO("add ip block number %d <%s>\n", adev->num_ip_blocks, ip_block_version->funcs->name); + adev->ip_blocks[adev->num_ip_blocks].adev = adev; + adev->ip_blocks[adev->num_ip_blocks++].version = ip_block_version; return 0; From 15992aae96afdc229c71b005225d48efc8dac4e6 Mon Sep 17 00:00:00 2001 From: Sreekant Somasekharan Date: Fri, 20 Sep 2024 01:53:17 -0400 Subject: [PATCH 1631/1868] drm/amdkfd: Add SDMA queue quantum support for GFX12 program SDMAx_QUEUEx_SCHEDULE_CNTL for context switch due to quantum in KFD for GFX12. Signed-off-by: Sreekant Somasekharan Reviewed-by: Harish Kasiviswanathan --- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c index d163d92a692f6..2b72d5b4949b6 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c @@ -341,6 +341,10 @@ static void update_mqd_sdma(struct mqd_manager *mm, void *mqd, m->sdmax_rlcx_doorbell_offset = q->doorbell_off << SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT; + m->sdmax_rlcx_sched_cntl = (amdgpu_sdma_phase_quantum + << SDMA0_QUEUE0_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT) + & SDMA0_QUEUE0_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK; + m->sdma_engine_id = q->sdma_engine_id; m->sdma_queue_id = q->sdma_queue_id; From 4f20f4c53f0b58006ec64d8fc9872c5a4a132287 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 16 Sep 2024 13:16:53 -0400 Subject: [PATCH 1632/1868] drm/amdgpu/gfx9: set additional bits on CP halt Need to set the pipe reset and cache invalidation bits on halt otherwise we can get stale state if the CP firmware changes (e.g., on module unload and reload). Reviewed-by: Srinivasan Shanmugam Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 33fc97a88ce7b..0a9fef0026e0e 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -3191,6 +3191,15 @@ static void gfx_v9_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable) { u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL); + tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_INVALIDATE_ICACHE, enable ? 0 : 1); + tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_INVALIDATE_ICACHE, enable ? 0 : 1); + tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_INVALIDATE_ICACHE, enable ? 0 : 1); + tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_PIPE0_RESET, enable ? 0 : 1); + tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_PIPE1_RESET, enable ? 0 : 1); + tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, enable ? 0 : 1); + tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, enable ? 0 : 1); + tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, enable ? 0 : 1); + tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, enable ? 0 : 1); tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1); tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1); tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1); @@ -3400,7 +3409,15 @@ static void gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool enable) WREG32_SOC15_RLC(GC, 0, mmCP_MEC_CNTL, 0); } else { WREG32_SOC15_RLC(GC, 0, mmCP_MEC_CNTL, - (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); + (CP_MEC_CNTL__MEC_INVALIDATE_ICACHE_MASK | + CP_MEC_CNTL__MEC_ME1_PIPE0_RESET_MASK | + CP_MEC_CNTL__MEC_ME1_PIPE1_RESET_MASK | + CP_MEC_CNTL__MEC_ME1_PIPE2_RESET_MASK | + CP_MEC_CNTL__MEC_ME1_PIPE3_RESET_MASK | + CP_MEC_CNTL__MEC_ME2_PIPE0_RESET_MASK | + CP_MEC_CNTL__MEC_ME2_PIPE1_RESET_MASK | + CP_MEC_CNTL__MEC_ME1_HALT_MASK | + CP_MEC_CNTL__MEC_ME2_HALT_MASK)); adev->gfx.kiq[0].ring.sched.ready = false; } udelay(50); From 305c132a351d08f23305205101e059233410df7b Mon Sep 17 00:00:00 2001 From: WangYuli Date: Fri, 20 Sep 2024 10:27:55 +0800 Subject: [PATCH 1633/1868] drm/amdgpu: Fix typo "acccess" and improve the comment style here MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit There are some spelling mistakes of 'acccess' in comments which should be instead of 'access'. And the comment style should be like this: /* * Text * Text */ Suggested-by: Christian König Link: https://lore.kernel.org/all/f75fbe30-528e-404f-97e4-854d27d7a401@amd.com/ Acked-by: Thomas Zimmermann Link: https://lore.kernel.org/all/0c768bf6-bc19-43de-a30b-ff5e3ddfd0b3@suse.de/ Reviewed-by: Christian König Signed-off-by: WangYuli Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 6 ++++-- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 6 ++++-- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index d3e8be82a1727..33fd2da49a2a7 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -1893,8 +1893,10 @@ static void gfx_v11_0_init_compute_vmid(struct amdgpu_device *adev) soc21_grbm_select(adev, 0, 0, 0, 0); mutex_unlock(&adev->srbm_mutex); - /* Initialize all compute VMIDs to have no GDS, GWS, or OA - acccess. These should be enabled by FW for target VMIDs. */ + /* + * Initialize all compute VMIDs to have no GDS, GWS, or OA + * access. These should be enabled by FW for target VMIDs. + */ for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * i, 0); WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * i, 0); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index c100845409f79..59d0c34aeacf9 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -1247,8 +1247,10 @@ static void gfx_v9_4_3_xcc_init_compute_vmid(struct amdgpu_device *adev, soc15_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); mutex_unlock(&adev->srbm_mutex); - /* Initialize all compute VMIDs to have no GDS, GWS, or OA - acccess. These should be enabled by FW for target VMIDs. */ + /* + * Initialize all compute VMIDs to have no GDS, GWS, or OA + * access. These should be enabled by FW for target VMIDs. + */ for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_BASE, 2 * i, 0); WREG32_SOC15_OFFSET(GC, GET_INST(GC, xcc_id), regGDS_VMID0_SIZE, 2 * i, 0); From 888c122060cc81e2d40fc7ef229bced8e8b91797 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Tue, 17 Sep 2024 16:24:11 +0800 Subject: [PATCH 1634/1868] drm/amd: Add helper to get partition config modes Add helper to get supported/available partition config modes Signed-off-by: Lijo Lazar Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 40 ++++++++-------- drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h | 2 + drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c | 54 ++++++++++++++++++++++ 3 files changed, 76 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c index 83e54697f0ee8..2d3fdb6c31617 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c @@ -1363,35 +1363,35 @@ static ssize_t amdgpu_gfx_set_compute_partition(struct device *dev, return count; } +static const char *xcp_desc[] = { + [AMDGPU_SPX_PARTITION_MODE] = "SPX", + [AMDGPU_DPX_PARTITION_MODE] = "DPX", + [AMDGPU_TPX_PARTITION_MODE] = "TPX", + [AMDGPU_QPX_PARTITION_MODE] = "QPX", + [AMDGPU_CPX_PARTITION_MODE] = "CPX", +}; + static ssize_t amdgpu_gfx_get_available_compute_partition(struct device *dev, struct device_attribute *addr, char *buf) { struct drm_device *ddev = dev_get_drvdata(dev); struct amdgpu_device *adev = drm_to_adev(ddev); - char *supported_partition; + struct amdgpu_xcp_mgr *xcp_mgr = adev->xcp_mgr; + int size = 0, mode; + char *sep = ""; - /* TBD */ - switch (NUM_XCC(adev->gfx.xcc_mask)) { - case 8: - supported_partition = "SPX, DPX, QPX, CPX"; - break; - case 6: - supported_partition = "SPX, TPX, CPX"; - break; - case 4: - supported_partition = "SPX, DPX, CPX"; - break; - /* this seems only existing in emulation phase */ - case 2: - supported_partition = "SPX, CPX"; - break; - default: - supported_partition = "Not supported"; - break; + if (!xcp_mgr || !xcp_mgr->avail_xcp_modes) + return sysfs_emit(buf, "Not supported\n"); + + for_each_inst(mode, xcp_mgr->avail_xcp_modes) { + size += sysfs_emit_at(buf, size, "%s%s", sep, xcp_desc[mode]); + sep = ", "; } - return sysfs_emit(buf, "%s\n", supported_partition); + size += sysfs_emit_at(buf, size, "\n"); + + return size; } static int amdgpu_gfx_run_cleaner_shader_job(struct amdgpu_ring *ring) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h index 90138bc5f03d1..b9a72eb15a221 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h @@ -97,6 +97,8 @@ struct amdgpu_xcp_mgr { /* Used to determine KFD memory size limits per XCP */ unsigned int num_xcp_per_mem_partition; + uint32_t supp_xcp_modes; + uint32_t avail_xcp_modes; }; struct amdgpu_xcp_mgr_funcs { diff --git a/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c b/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c index 79cd14223c89c..b7405468e078a 100644 --- a/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c +++ b/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c @@ -536,6 +536,57 @@ static int __aqua_vanjaram_post_partition_switch(struct amdgpu_xcp_mgr *xcp_mgr, return ret; } +static void +__aqua_vanjaram_update_supported_modes(struct amdgpu_xcp_mgr *xcp_mgr) +{ + struct amdgpu_device *adev = xcp_mgr->adev; + + xcp_mgr->supp_xcp_modes = 0; + + switch (NUM_XCC(adev->gfx.xcc_mask)) { + case 8: + xcp_mgr->supp_xcp_modes = BIT(AMDGPU_SPX_PARTITION_MODE) | + BIT(AMDGPU_DPX_PARTITION_MODE) | + BIT(AMDGPU_QPX_PARTITION_MODE) | + BIT(AMDGPU_CPX_PARTITION_MODE); + break; + case 6: + xcp_mgr->supp_xcp_modes = BIT(AMDGPU_SPX_PARTITION_MODE) | + BIT(AMDGPU_TPX_PARTITION_MODE) | + BIT(AMDGPU_CPX_PARTITION_MODE); + break; + case 4: + xcp_mgr->supp_xcp_modes = BIT(AMDGPU_SPX_PARTITION_MODE) | + BIT(AMDGPU_DPX_PARTITION_MODE) | + BIT(AMDGPU_CPX_PARTITION_MODE); + break; + /* this seems only existing in emulation phase */ + case 2: + xcp_mgr->supp_xcp_modes = BIT(AMDGPU_SPX_PARTITION_MODE) | + BIT(AMDGPU_CPX_PARTITION_MODE); + break; + case 1: + xcp_mgr->supp_xcp_modes = BIT(AMDGPU_SPX_PARTITION_MODE) | + BIT(AMDGPU_CPX_PARTITION_MODE); + break; + + default: + break; + } +} + +static void __aqua_vanjaram_update_available_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr) +{ + int mode; + + xcp_mgr->avail_xcp_modes = 0; + + for_each_inst(mode, xcp_mgr->supp_xcp_modes) { + if (__aqua_vanjaram_is_valid_mode(xcp_mgr, mode)) + xcp_mgr->avail_xcp_modes |= BIT(mode); + } +} + static int aqua_vanjaram_switch_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr, int mode, int *num_xcps) { @@ -584,6 +635,8 @@ static int aqua_vanjaram_switch_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr, amdgpu_xcp_init(xcp_mgr, *num_xcps, mode); ret = __aqua_vanjaram_post_partition_switch(xcp_mgr, flags); + if (!ret) + __aqua_vanjaram_update_available_partition_mode(xcp_mgr); unlock: if (flags & AMDGPU_XCP_OPS_KFD) amdgpu_amdkfd_unlock_kfd(adev); @@ -683,6 +736,7 @@ static int aqua_vanjaram_xcp_mgr_init(struct amdgpu_device *adev) if (ret) return ret; + __aqua_vanjaram_update_supported_modes(adev->xcp_mgr); /* TODO: Default memory node affinity init */ return ret; From 0ed235080d414394c35a7d36228937eb7b35a641 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Mon, 9 Sep 2024 17:38:24 +0530 Subject: [PATCH 1635/1868] drm/amdgpu: Add callback get xcp resource info Add a callback interface to get the resource information of a partition mode. Presently the information has number of resources and number of entities sharing the resource. Add the implementation for aquavanjaram SOCs. Signed-off-by: Lijo Lazar Signed-off-by: Asad Kamal Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h | 26 +++++++++- drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c | 59 +++++++++++++++++++++- 2 files changed, 83 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h index b9a72eb15a221..3aa3996c0250d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h @@ -56,6 +56,27 @@ enum AMDGPU_XCP_STATE { AMDGPU_XCP_RESUME, }; +enum amdgpu_xcp_res_id { + AMDGPU_XCP_RES_XCC, + AMDGPU_XCP_RES_DMA, + AMDGPU_XCP_RES_DEC, + AMDGPU_XCP_RES_JPEG, + AMDGPU_XCP_RES_MAX, +}; + +struct amdgpu_xcp_res_details { + enum amdgpu_xcp_res_id id; + u8 num_inst; + u8 num_shared; +}; + +struct amdgpu_xcp_cfg { + u8 mode; + struct amdgpu_xcp_res_details xcp_res[AMDGPU_XCP_RES_MAX]; + u8 num_res; + struct amdgpu_xcp_mgr *xcp_mgr; +}; + struct amdgpu_xcp_ip_funcs { int (*prepare_suspend)(void *handle, uint32_t inst_mask); int (*suspend)(void *handle, uint32_t inst_mask); @@ -97,6 +118,7 @@ struct amdgpu_xcp_mgr { /* Used to determine KFD memory size limits per XCP */ unsigned int num_xcp_per_mem_partition; + struct amdgpu_xcp_cfg *xcp_cfg; uint32_t supp_xcp_modes; uint32_t avail_xcp_modes; }; @@ -110,7 +132,9 @@ struct amdgpu_xcp_mgr_funcs { struct amdgpu_xcp_ip *ip); int (*get_xcp_mem_id)(struct amdgpu_xcp_mgr *xcp_mgr, struct amdgpu_xcp *xcp, uint8_t *mem_id); - + int (*get_xcp_res_info)(struct amdgpu_xcp_mgr *xcp_mgr, + int mode, + struct amdgpu_xcp_cfg *xcp_cfg); int (*prepare_suspend)(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id); int (*suspend)(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id); int (*prepare_resume)(struct amdgpu_xcp_mgr *xcp_mgr, int xcp_id); diff --git a/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c b/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c index b7405468e078a..f2fe6dafe62dd 100644 --- a/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c +++ b/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c @@ -453,6 +453,61 @@ static int __aqua_vanjaram_get_xcp_ip_info(struct amdgpu_xcp_mgr *xcp_mgr, int x return 0; } +static int aqua_vanjaram_get_xcp_res_info(struct amdgpu_xcp_mgr *xcp_mgr, + int mode, + struct amdgpu_xcp_cfg *xcp_cfg) +{ + struct amdgpu_device *adev = xcp_mgr->adev; + int max_res[AMDGPU_XCP_RES_MAX] = {}; + bool res_lt_xcp; + int num_xcp, i; + + if (!(xcp_mgr->supp_xcp_modes & BIT(mode))) + return -EINVAL; + + max_res[AMDGPU_XCP_RES_XCC] = NUM_XCC(adev->gfx.xcc_mask); + max_res[AMDGPU_XCP_RES_DMA] = adev->sdma.num_instances; + max_res[AMDGPU_XCP_RES_DEC] = adev->vcn.num_vcn_inst; + max_res[AMDGPU_XCP_RES_JPEG] = adev->jpeg.num_jpeg_inst; + + switch (mode) { + case AMDGPU_SPX_PARTITION_MODE: + num_xcp = 1; + break; + case AMDGPU_DPX_PARTITION_MODE: + num_xcp = 2; + break; + case AMDGPU_TPX_PARTITION_MODE: + num_xcp = 3; + break; + case AMDGPU_QPX_PARTITION_MODE: + num_xcp = 4; + break; + case AMDGPU_CPX_PARTITION_MODE: + num_xcp = NUM_XCC(adev->gfx.xcc_mask); + break; + default: + return -EINVAL; + } + + xcp_cfg->num_res = ARRAY_SIZE(max_res); + + for (i = 0; i < xcp_cfg->num_res; i++) { + res_lt_xcp = max_res[i] < num_xcp; + xcp_cfg->xcp_res[i].id = i; + xcp_cfg->xcp_res[i].num_inst = + res_lt_xcp ? 1 : max_res[i] / num_xcp; + xcp_cfg->xcp_res[i].num_inst = + i == AMDGPU_XCP_RES_JPEG ? + xcp_cfg->xcp_res[i].num_inst * + adev->jpeg.num_jpeg_rings : xcp_cfg->xcp_res[i].num_inst; + xcp_cfg->xcp_res[i].num_shared = + res_lt_xcp ? num_xcp / max_res[i] : 1; + } + + return 0; +} + static enum amdgpu_gfx_partition __aqua_vanjaram_get_auto_mode(struct amdgpu_xcp_mgr *xcp_mgr) { @@ -717,11 +772,13 @@ struct amdgpu_xcp_mgr_funcs aqua_vanjaram_xcp_funcs = { .switch_partition_mode = &aqua_vanjaram_switch_partition_mode, .query_partition_mode = &aqua_vanjaram_query_partition_mode, .get_ip_details = &aqua_vanjaram_get_xcp_ip_details, + .get_xcp_res_info = &aqua_vanjaram_get_xcp_res_info, #ifdef HAVE_ACPI_DEV_GET_FIRST_MATCH_DEV .get_xcp_mem_id = &aqua_vanjaram_get_xcp_mem_id, #endif .select_scheds = &aqua_vanjaram_select_scheds, - .update_partition_sched_list = &aqua_vanjaram_update_partition_sched_list + .update_partition_sched_list = + &aqua_vanjaram_update_partition_sched_list }; static int aqua_vanjaram_xcp_mgr_init(struct amdgpu_device *adev) From 392e16d303de2ec48f4d0f4afd7f345cbe97a3b9 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 16 Sep 2024 13:21:02 -0400 Subject: [PATCH 1636/1868] drm/amdgpu/gfx9: Explicitly halt CP before init Need to make sure it's halted as we don't know what state the GPU may have been left in previously. Reviewed-by: Srinivasan Shanmugam Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 0a9fef0026e0e..b53f8416e2371 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -3938,6 +3938,10 @@ static int gfx_v9_0_cp_resume(struct amdgpu_device *adev) return r; } + if (adev->gfx.num_gfx_rings) + gfx_v9_0_cp_gfx_enable(adev, false); + gfx_v9_0_cp_compute_enable(adev, false); + r = gfx_v9_0_kiq_resume(adev); if (r) return r; From 8b87d41208abff942fdbc91dfe37142d903fbfc3 Mon Sep 17 00:00:00 2001 From: Vitaliy Shevtsov Date: Sat, 21 Sep 2024 02:43:40 +0500 Subject: [PATCH 1637/1868] drm/amd/display: fix typos in several function pointer checks Fix several copypaste mistakes in *_disable_link_output() functions where an improper function pointer is checked before dereference. Found by Linux Verification Center (linuxtesting.org) with Svace. Signed-off-by: Vitaliy Shevtsov Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c | 2 +- drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c | 2 +- drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c | 4 ++-- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c index 4fbed0298adfa..9d00d8dc5ae87 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c @@ -3315,7 +3315,7 @@ void dce110_disable_link_output(struct dc_link *link, * from enable/disable link output and only call edp panel control * in enable_link_dp and disable_link_dp once. */ - if (dmcu != NULL && dmcu->funcs->lock_phy) + if (dmcu != NULL && dmcu->funcs->unlock_phy) dmcu->funcs->unlock_phy(dmcu); dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY); } diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c index 4e93eeedfc1bb..5b6cf2a8e38da 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c @@ -478,7 +478,7 @@ void dcn314_disable_link_output(struct dc_link *link, * from enable/disable link output and only call edp panel control * in enable_link_dp and disable_link_dp once. */ - if (dmcu != NULL && dmcu->funcs->lock_phy) + if (dmcu != NULL && dmcu->funcs->unlock_phy) dmcu->funcs->unlock_phy(dmcu); dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c index 7ee6e53a98afa..dd6dac7b46194 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c @@ -1397,10 +1397,10 @@ void dcn32_disable_link_output(struct dc_link *link, link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF; if (signal == SIGNAL_TYPE_EDP && - link->dc->hwss.edp_backlight_control && + link->dc->hwss.edp_power_control && !link->skip_implict_edp_power_control) link->dc->hwss.edp_power_control(link, false); - else if (dmcu != NULL && dmcu->funcs->lock_phy) + else if (dmcu != NULL && dmcu->funcs->unlock_phy) dmcu->funcs->unlock_phy(dmcu); dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY); From 0e6440903b1d9430e0dd42a0b49b2661f868f8b2 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Wed, 21 Aug 2024 11:40:16 +0530 Subject: [PATCH 1638/1868] drm/amdgpu: Add reset on init handler for XGMI In some cases, device needs to be reset before first use. Add handlers for doing device reset during driver init sequence. Signed-off-by: Lijo Lazar Reviewed-by: Feifei Xu Acked-by: Rajneesh Bhardwaj Tested-by: Rajneesh Bhardwaj --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c | 149 ++++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h | 5 + 3 files changed, 155 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index d6e9e4fc81af1..47005f1baf10c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -573,6 +573,7 @@ enum amd_reset_method { AMD_RESET_METHOD_MODE2, AMD_RESET_METHOD_BACO, AMD_RESET_METHOD_PCI, + AMD_RESET_METHOD_ON_INIT, }; struct amdgpu_video_codec_info { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c index 91531e3563827..ea5e861accb13 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c @@ -26,6 +26,155 @@ #include "sienna_cichlid.h" #include "smu_v13_0_10.h" +static int amdgpu_reset_xgmi_reset_on_init_suspend(struct amdgpu_device *adev) +{ + int i, r; + + for (i = adev->num_ip_blocks - 1; i >= 0; i--) { + if (!adev->ip_blocks[i].status.valid) + continue; + if (!adev->ip_blocks[i].status.hw) + continue; + /* displays are handled in phase1 */ + if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) + continue; + + /* XXX handle errors */ + r = adev->ip_blocks[i].version->funcs->suspend(adev); + /* XXX handle errors */ + if (r) { + dev_err(adev->dev, "suspend of IP block <%s> failed %d", + adev->ip_blocks[i].version->funcs->name, r); + } + adev->ip_blocks[i].status.hw = false; + } + + return 0; +} + +static int amdgpu_reset_xgmi_reset_on_init_prep_hwctxt( + struct amdgpu_reset_control *reset_ctl, + struct amdgpu_reset_context *reset_context) +{ + struct list_head *reset_device_list = reset_context->reset_device_list; + struct amdgpu_device *tmp_adev; + int r; + + list_for_each_entry(tmp_adev, reset_device_list, reset_list) { + amdgpu_unregister_gpu_instance(tmp_adev); + r = amdgpu_reset_xgmi_reset_on_init_suspend(tmp_adev); + if (r) { + dev_err(tmp_adev->dev, + "xgmi reset on init: prepare for reset failed"); + return r; + } + } + + return r; +} + +static int amdgpu_reset_xgmi_reset_on_init_restore_hwctxt( + struct amdgpu_reset_control *reset_ctl, + struct amdgpu_reset_context *reset_context) +{ + struct list_head *reset_device_list = reset_context->reset_device_list; + struct amdgpu_device *tmp_adev = NULL; + int r; + + r = amdgpu_device_reinit_after_reset(reset_context); + if (r) + return r; + list_for_each_entry(tmp_adev, reset_device_list, reset_list) { + if (!tmp_adev->kfd.init_complete) { + kgd2kfd_init_zone_device(tmp_adev); + amdgpu_amdkfd_device_init(tmp_adev); + amdgpu_amdkfd_drm_client_create(tmp_adev); + } + } + + return r; +} + +static int amdgpu_reset_xgmi_reset_on_init_perform_reset( + struct amdgpu_reset_control *reset_ctl, + struct amdgpu_reset_context *reset_context) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)reset_ctl->handle; + struct list_head *reset_device_list = reset_context->reset_device_list; + struct amdgpu_device *tmp_adev = NULL; + int r; + + dev_dbg(adev->dev, "xgmi roi - hw reset\n"); + + list_for_each_entry(tmp_adev, reset_device_list, reset_list) { + mutex_lock(&tmp_adev->reset_cntl->reset_lock); + tmp_adev->reset_cntl->active_reset = + amdgpu_asic_reset_method(adev); + } + r = 0; + /* Mode1 reset needs to be triggered on all devices together */ + list_for_each_entry(tmp_adev, reset_device_list, reset_list) { + /* For XGMI run all resets in parallel to speed up the process */ + if (!queue_work(system_unbound_wq, &tmp_adev->xgmi_reset_work)) + r = -EALREADY; + if (r) { + dev_err(tmp_adev->dev, + "xgmi reset on init: reset failed with error, %d", + r); + break; + } + } + + /* For XGMI wait for all resets to complete before proceed */ + if (!r) { + list_for_each_entry(tmp_adev, reset_device_list, reset_list) { + flush_work(&tmp_adev->xgmi_reset_work); + r = tmp_adev->asic_reset_res; + if (r) + break; + } + } + + list_for_each_entry(tmp_adev, reset_device_list, reset_list) { + mutex_unlock(&tmp_adev->reset_cntl->reset_lock); + tmp_adev->reset_cntl->active_reset = AMD_RESET_METHOD_NONE; + } + + return r; +} + +int amdgpu_reset_do_xgmi_reset_on_init( + struct amdgpu_reset_context *reset_context) +{ + struct list_head *reset_device_list = reset_context->reset_device_list; + struct amdgpu_device *adev; + int r; + + if (!reset_device_list || list_empty(reset_device_list) || + list_is_singular(reset_device_list)) + return -EINVAL; + + adev = list_first_entry(reset_device_list, struct amdgpu_device, + reset_list); + r = amdgpu_reset_prepare_hwcontext(adev, reset_context); + if (r) + return r; + + r = amdgpu_reset_perform_reset(adev, reset_context); + + return r; +} + +struct amdgpu_reset_handler xgmi_reset_on_init_handler = { + .reset_method = AMD_RESET_METHOD_ON_INIT, + .prepare_env = NULL, + .prepare_hwcontext = amdgpu_reset_xgmi_reset_on_init_prep_hwctxt, + .perform_reset = amdgpu_reset_xgmi_reset_on_init_perform_reset, + .restore_hwcontext = amdgpu_reset_xgmi_reset_on_init_restore_hwctxt, + .restore_env = NULL, + .do_reset = NULL, +}; + int amdgpu_reset_init(struct amdgpu_device *adev) { int ret = 0; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h index 929d372fc3635..977b2dd2205ac 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.h @@ -169,4 +169,9 @@ void amdgpu_reset_get_desc(struct amdgpu_reset_context *rst_ctxt, char *buf, for (i = 0; (i < AMDGPU_RESET_MAX_HANDLERS) && \ (handler = (*reset_ctl->reset_handlers)[i]); \ ++i) + +extern struct amdgpu_reset_handler xgmi_reset_on_init_handler; +int amdgpu_reset_do_xgmi_reset_on_init( + struct amdgpu_reset_context *reset_context); + #endif From fa9af0fed3653acbf54137efebf8f29e52c631bc Mon Sep 17 00:00:00 2001 From: Frank Min Date: Wed, 25 Sep 2024 11:39:06 +0800 Subject: [PATCH 1639/1868] drm/amdgpu: fix PTE copy corruption for sdma 7 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Without setting dcc bit, there is ramdon PTE copy corruption on sdma 7. so add this bit and update the packet format accordingly. Signed-off-by: Frank Min Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c index cfd8e183ad503..a8763496aed31 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c @@ -1080,13 +1080,16 @@ static void sdma_v7_0_vm_copy_pte(struct amdgpu_ib *ib, unsigned bytes = count * 8; ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_COPY) | - SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR); + SDMA_PKT_COPY_LINEAR_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR) | + SDMA_PKT_COPY_LINEAR_HEADER_CPV(1); + ib->ptr[ib->length_dw++] = bytes - 1; ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ ib->ptr[ib->length_dw++] = lower_32_bits(src); ib->ptr[ib->length_dw++] = upper_32_bits(src); ib->ptr[ib->length_dw++] = lower_32_bits(pe); ib->ptr[ib->length_dw++] = upper_32_bits(pe); + ib->ptr[ib->length_dw++] = 0; } @@ -1744,7 +1747,7 @@ static void sdma_v7_0_set_buffer_funcs(struct amdgpu_device *adev) } static const struct amdgpu_vm_pte_funcs sdma_v7_0_vm_pte_funcs = { - .copy_pte_num_dw = 7, + .copy_pte_num_dw = 8, .copy_pte = sdma_v7_0_vm_copy_pte, .write_pte = sdma_v7_0_vm_write_pte, .set_pte_pde = sdma_v7_0_vm_set_pte_pde, From 9509de93b14d5183d16e5a6e1b2442c0b4c7214a Mon Sep 17 00:00:00 2001 From: Yang Su Date: Fri, 27 Sep 2024 10:32:36 +0800 Subject: [PATCH 1640/1868] Bump AMDGPU version to 6.10.3 Signed-off-by: Yang Su --- drivers/gpu/drm/amd/dkms/configure.ac | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/configure.ac b/drivers/gpu/drm/amd/dkms/configure.ac index 68225c89eabea..be3642117a8b2 100644 --- a/drivers/gpu/drm/amd/dkms/configure.ac +++ b/drivers/gpu/drm/amd/dkms/configure.ac @@ -1,4 +1,4 @@ -AC_INIT(amdgpu-dkms, 6.10.2) +AC_INIT(amdgpu-dkms, 6.10.3) AC_LANG(C) AC_CONFIG_AUX_DIR([config]) From b2f857c15573b6a3a10c0ee4444b73bef61b55f5 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 25 Sep 2024 14:17:53 -0400 Subject: [PATCH 1641/1868] drm/amdgpu: fix vbios fetching for SR-IOV SR-IOV fetches the vbios from VRAM in some cases. Re-enable the VRAM path for dGPUs and rename the function to make it clear that it is not IGP specific. Fixes: 042658d17a54 ("drm/amdgpu: clean up vbios fetching code") Reviewed-by: Yang Wang Tested-by: Yang Wang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c index 46bf623919d7c..45affc02548c1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c @@ -87,8 +87,9 @@ static bool check_atom_bios(uint8_t *bios, size_t size) * part of the system bios. On boot, the system bios puts a * copy of the igp rom at the start of vram if a discrete card is * present. + * For SR-IOV, the vbios image is also put in VRAM in the VF. */ -static bool igp_read_bios_from_vram(struct amdgpu_device *adev) +static bool amdgpu_read_bios_from_vram(struct amdgpu_device *adev) { uint8_t __iomem *bios; resource_size_t vram_base; @@ -414,7 +415,7 @@ static bool amdgpu_get_bios_apu(struct amdgpu_device *adev) goto success; } - if (igp_read_bios_from_vram(adev)) { + if (amdgpu_read_bios_from_vram(adev)) { dev_info(adev->dev, "Fetched VBIOS from VRAM BAR\n"); goto success; } @@ -448,6 +449,12 @@ static bool amdgpu_get_bios_dgpu(struct amdgpu_device *adev) goto success; } + /* this is required for SR-IOV */ + if (amdgpu_read_bios_from_vram(adev)) { + dev_info(adev->dev, "Fetched VBIOS from VRAM BAR\n"); + goto success; + } + if (amdgpu_read_platform_bios(adev)) { dev_info(adev->dev, "Fetched VBIOS from platform\n"); goto success; From bd098b4defe9f58d231c7bcc3b3e19d804a2f443 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 25 Sep 2024 14:17:53 -0400 Subject: [PATCH 1642/1868] drm/amdgpu: fix vbios fetching for SR-IOV SR-IOV fetches the vbios from VRAM in some cases. Re-enable the VRAM path for dGPUs and rename the function to make it clear that it is not IGP specific. Fixes: 042658d17a54 ("drm/amdgpu: clean up vbios fetching code") Reviewed-by: Yang Wang Tested-by: Yang Wang Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c index 46bf623919d7c..45affc02548c1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_bios.c @@ -87,8 +87,9 @@ static bool check_atom_bios(uint8_t *bios, size_t size) * part of the system bios. On boot, the system bios puts a * copy of the igp rom at the start of vram if a discrete card is * present. + * For SR-IOV, the vbios image is also put in VRAM in the VF. */ -static bool igp_read_bios_from_vram(struct amdgpu_device *adev) +static bool amdgpu_read_bios_from_vram(struct amdgpu_device *adev) { uint8_t __iomem *bios; resource_size_t vram_base; @@ -414,7 +415,7 @@ static bool amdgpu_get_bios_apu(struct amdgpu_device *adev) goto success; } - if (igp_read_bios_from_vram(adev)) { + if (amdgpu_read_bios_from_vram(adev)) { dev_info(adev->dev, "Fetched VBIOS from VRAM BAR\n"); goto success; } @@ -448,6 +449,12 @@ static bool amdgpu_get_bios_dgpu(struct amdgpu_device *adev) goto success; } + /* this is required for SR-IOV */ + if (amdgpu_read_bios_from_vram(adev)) { + dev_info(adev->dev, "Fetched VBIOS from VRAM BAR\n"); + goto success; + } + if (amdgpu_read_platform_bios(adev)) { dev_info(adev->dev, "Fetched VBIOS from platform\n"); goto success; From 0fa7150ccc9cb54f87db50ace87c0024144f9412 Mon Sep 17 00:00:00 2001 From: Sreekant Somasekharan Date: Fri, 20 Sep 2024 01:53:17 -0400 Subject: [PATCH 1643/1868] drm/amdkfd: Add SDMA queue quantum support for GFX12 program SDMAx_QUEUEx_SCHEDULE_CNTL for context switch due to quantum in KFD for GFX12. Signed-off-by: Sreekant Somasekharan Reviewed-by: Harish Kasiviswanathan --- drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c index d163d92a692f6..2b72d5b4949b6 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12.c @@ -341,6 +341,10 @@ static void update_mqd_sdma(struct mqd_manager *mm, void *mqd, m->sdmax_rlcx_doorbell_offset = q->doorbell_off << SDMA0_QUEUE0_DOORBELL_OFFSET__OFFSET__SHIFT; + m->sdmax_rlcx_sched_cntl = (amdgpu_sdma_phase_quantum + << SDMA0_QUEUE0_SCHEDULE_CNTL__CONTEXT_QUANTUM__SHIFT) + & SDMA0_QUEUE0_SCHEDULE_CNTL__CONTEXT_QUANTUM_MASK; + m->sdma_engine_id = q->sdma_engine_id; m->sdma_queue_id = q->sdma_queue_id; From 1e97a5805ed6578057f1dc4eedab6d7f5b125f1a Mon Sep 17 00:00:00 2001 From: Bing Ma Date: Fri, 20 Sep 2024 10:46:49 -0700 Subject: [PATCH 1644/1868] drm/amdkfd: [SPM] Fix a crash issue when running SPM on latest kernel driver Root cause: Parameter type for amdgpu_amdkfd_free_gtt_mem() has changed. Fix: Change SPM code to match this change. Signed-off-by: Bing Ma Reviewed-by: James Zhu --- drivers/gpu/drm/amd/amdkfd/kfd_spm.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c index 6480e9c49f608..a9354d43bba3b 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c @@ -62,7 +62,7 @@ static int kfd_spm_data_copy(struct kfd_process_device *pdd, u32 size_to_copy) return -EFAULT; user_address = (uint64_t *)((uint64_t)spm->ubuf.user_addr + spm->size_copied); - // From RLC spec, ring_rptr = 0 points to spm->cpu_addr+0x20 + /* From RLC spec, ring_rptr = 0 points to spm->cpu_addr + 0x20 */ ring_buf = (uint64_t *)((uint64_t)spm->cpu_addr + spm->ring_rptr + 0x20); if (user_address == NULL) @@ -221,7 +221,7 @@ static int kfd_acquire_spm(struct kfd_process_device *pdd, struct amdgpu_device goto out; acquire_spm_failure: - amdgpu_amdkfd_free_gtt_mem(adev, pdd->spm_cntr->spm_obj); + amdgpu_amdkfd_free_gtt_mem(adev, &pdd->spm_cntr->spm_obj); alloc_gtt_mem_failure: kfree(pdd->spm_cntr); @@ -250,7 +250,7 @@ static int kfd_release_spm(struct kfd_process_device *pdd, struct amdgpu_device wake_up_all(&pdd->spm_cntr->spm_buf_wq); amdgpu_amdkfd_rlc_spm_release(adev, drm_priv_to_vm(pdd->drm_priv)); - amdgpu_amdkfd_free_gtt_mem(adev, pdd->spm_cntr->spm_obj); + amdgpu_amdkfd_free_gtt_mem(adev, &pdd->spm_cntr->spm_obj); spin_lock_irqsave(&pdd->spm_irq_lock, flags); kfree(pdd->spm_cntr); From da4bdf2cabaa84129b6561bda127647d16dad498 Mon Sep 17 00:00:00 2001 From: Bing Ma Date: Fri, 20 Sep 2024 11:13:12 -0700 Subject: [PATCH 1645/1868] drm/amdgpu: [SPM] Remove 'SPM Start' logic from gfx_v9_0_spm_start() We should start SPM only after all SPM configurations are done, otherwise we might see garbage data or other undefined behaviors. Because user mode module (profiler) is responsible for SPM configurations, we will let user mode module to start SPM. Signed-off-by: Bing Ma Acked-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index b53f8416e2371..915cb29c9f4a6 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -4789,11 +4789,6 @@ static void gfx_v9_0_spm_start(struct amdgpu_device *adev) gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, SOC15_REG_OFFSET(GC, 0, mmCP_PERFMON_CNTL), data); - data = REG_SET_FIELD(0, CP_PERFMON_CNTL, SPM_PERFMON_STATE, - STRM_PERFMON_STATE_START_COUNTING); - gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, - SOC15_REG_OFFSET(GC, 0, mmCP_PERFMON_CNTL), data); - gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_INT_CNTL), 1); } From 35b64b159c2161b9d188273e638bdfd2c10e9c94 Mon Sep 17 00:00:00 2001 From: Bing Ma Date: Tue, 24 Sep 2024 16:58:03 -0700 Subject: [PATCH 1646/1868] drm/amd: [SPM] Reset SPM ringbuffer 'rptr' When SPM is reset When SPM is reset, RLC automatically resets wptr to 0. We need to manually reset rptr to match this. Signed-off-by: Bing Ma Reviewed-by: James Zhu --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 12 ++++++++++++ drivers/gpu/drm/amd/amdkfd/kfd_spm.c | 8 ++++++++ 2 files changed, 20 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 915cb29c9f4a6..df15cb942a727 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -4789,6 +4789,12 @@ static void gfx_v9_0_spm_start(struct amdgpu_device *adev) gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, SOC15_REG_OFFSET(GC, 0, mmCP_PERFMON_CNTL), data); + /* When SPM is reset, RLC automatically resets wptr to 0. + * Manually reset rptr to match this. + */ + gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_RING_RDPTR), 0); + gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_INT_CNTL), 1); } @@ -4807,6 +4813,12 @@ static void gfx_v9_0_spm_stop(struct amdgpu_device *adev) CP_PERFMON_STATE_DISABLE_AND_RESET); gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, SOC15_REG_OFFSET(GC, 0, mmCP_PERFMON_CNTL), data); + + /* When SPM is reset, RLC automatically resets wptr to 0. + * Manually reset rptr to match this. + */ + gfx_v9_0_write_data_to_reg(kiq_ring, 0, false, + SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_RING_RDPTR), 0); } static void gfx_v9_0_spm_set_rdptr(struct amdgpu_device *adev, u32 rptr) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c index a9354d43bba3b..0827e2d4163c0 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c @@ -371,6 +371,10 @@ static int kfd_set_dest_buffer(struct kfd_process_device *pdd, struct amdgpu_dev amdgpu_amdkfd_rlc_spm_cntl(adev, 1); spin_lock_irqsave(&pdd->spm_irq_lock, flags); spm->is_spm_started = true; + /* amdgpu_amdkfd_rlc_spm_cntl() will reset SPM and wptr will become 0. + * Adjust rptr accordingly + */ + spm->ring_rptr = 0; spin_unlock_irqrestore(&pdd->spm_irq_lock, flags); } else { /* If SPM was already started, there may already @@ -382,6 +386,10 @@ static int kfd_set_dest_buffer(struct kfd_process_device *pdd, struct amdgpu_dev amdgpu_amdkfd_rlc_spm_cntl(adev, 0); spin_lock_irqsave(&pdd->spm_irq_lock, flags); spm->is_spm_started = false; + /* amdgpu_amdkfd_rlc_spm_cntl() will reset SPM and wptr will become 0. + * Adjust rptr accordingly + */ + spm->ring_rptr = 0; spin_unlock_irqrestore(&pdd->spm_irq_lock, flags); } From a84109d96ec9e47b5ceeb3c02968583285bd5296 Mon Sep 17 00:00:00 2001 From: Bing Ma Date: Fri, 20 Sep 2024 15:29:40 -0700 Subject: [PATCH 1647/1868] drm/amdkfd: [SPM] Remove 'rptr = wptr' when 'is_user_buf_filled == true'. We cannot set rptr = wptr here, because wptr is always set at segment boundary and profiler uses this knowledge to parse SPM counters. But rptr is not always set at segment boundary, and if we force 'rptr = wptr', we might leave an incomplete segment to user mode profiler and profiler won't be able to parse the counter properly. Signed-off-by: Bing Ma Acked-by: James Zhu --- drivers/gpu/drm/amd/amdkfd/kfd_spm.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c index 0827e2d4163c0..9b829adfc8ed9 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c @@ -103,9 +103,12 @@ static int kfd_spm_read_ring_buffer(struct kfd_process_device *pdd) ring_wptr = READ_ONCE(spm->cpu_addr[0]); - /* keep SPM ring buffer running */ + /* SPM might stall if we cannot copy data out of SPM ringbuffer. + * spm->has_data_loss is only a hint here since stall is only a + * possibility and data loss might not happen. But it is a useful + * hint for user mode profiler to take extra actions. + */ if (!spm->has_user_buf || spm->is_user_buf_filled) { - spm->ring_rptr = ring_wptr; spm->has_data_loss = true; /* set flag due to there is no flag setup * when read ring buffer timeout. From e3bceba3e36bc5fc63d3ead8f8e86a7e716ee786 Mon Sep 17 00:00:00 2001 From: Bing Ma Date: Fri, 20 Sep 2024 15:33:02 -0700 Subject: [PATCH 1648/1868] drm/amdkfd: [SPM] Merge spm_copy_data_to_usr() and spm_set_dest_info() into one function spm_update_dest_info() The gap between the two functions will trigger unnecessary data loss condition in kfd_spm_read_ring_buffer(). Signed-off-by: Bing Ma Reviewed-by: James Zhu --- drivers/gpu/drm/amd/amdkfd/kfd_spm.c | 45 +++++++++++++--------------- 1 file changed, 21 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c index 9b829adfc8ed9..45a81dd764eab 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c @@ -264,26 +264,24 @@ static int kfd_release_spm(struct kfd_process_device *pdd, struct amdgpu_device return 0; } -static void spm_copy_data_to_usr(struct kfd_ioctl_spm_args *user_spm_data, - struct kfd_process_device *pdd) -{ - mutex_lock(&pdd->spm_cntr->spm_worker_mutex); - user_spm_data->bytes_copied = pdd->spm_cntr->size_copied; - user_spm_data->has_data_loss = pdd->spm_cntr->has_data_loss; - pdd->spm_cntr->has_user_buf = false; - mutex_unlock(&pdd->spm_cntr->spm_worker_mutex); -} - -static void spm_set_dest_info(struct kfd_process_device *pdd, +static void spm_update_dest_info(struct kfd_process_device *pdd, struct kfd_ioctl_spm_args *user_spm_data) { + struct kfd_spm_cntr *spm = pdd->spm_cntr; mutex_lock(&pdd->spm_cntr->spm_worker_mutex); - pdd->spm_cntr->ubuf.user_addr = (uint64_t *)user_spm_data->dest_buf; - pdd->spm_cntr->ubuf.ubufsize = user_spm_data->buf_size; - pdd->spm_cntr->has_data_loss = false; - pdd->spm_cntr->size_copied = 0; - pdd->spm_cntr->is_user_buf_filled = false; - pdd->spm_cntr->has_user_buf = true; + if (spm->has_user_buf) { + user_spm_data->bytes_copied = spm->size_copied; + user_spm_data->has_data_loss = spm->has_data_loss; + spm->has_user_buf = false; + } + if (user_spm_data->dest_buf) { + spm->ubuf.user_addr = (uint64_t *)user_spm_data->dest_buf; + spm->ubuf.ubufsize = user_spm_data->buf_size; + spm->has_data_loss = false; + spm->size_copied = 0; + spm->is_user_buf_filled = false; + spm->has_user_buf = true; + } mutex_unlock(&pdd->spm_cntr->spm_worker_mutex); } @@ -360,16 +358,15 @@ static int kfd_set_dest_buffer(struct kfd_process_device *pdd, struct amdgpu_dev flush_work(&pdd->spm_work); } - if (spm->has_user_buf) { - /* get info about filled space in previous output buffer */ - spm_copy_data_to_usr(user_spm_data, pdd); + if (spm->has_user_buf || user_spm_data->dest_buf) { + /* Get info about filled space in previous output buffer. + * Setup new dest buf if provided. + */ + spm_update_dest_info(pdd, user_spm_data); } if (user_spm_data->dest_buf) { - /* setup new dest buf, start streaming if necessary */ - spm_set_dest_info(pdd, user_spm_data); - - /* Start SPM */ + /* Start SPM if necessary*/ if (spm->is_spm_started == false) { amdgpu_amdkfd_rlc_spm_cntl(adev, 1); spin_lock_irqsave(&pdd->spm_irq_lock, flags); From ca0c51a5a46c3b847ad43124b0dc2dfb791678a0 Mon Sep 17 00:00:00 2001 From: "Dr. David Alan Gilbert" Date: Mon, 23 Sep 2024 02:24:42 +0100 Subject: [PATCH 1649/1868] drm/amdgpu: Remove unused amdgpu_device_ip_is_idle amdgpu_device_ip_is_idle is unused. It was renamed from 'amdgpu_is_idle' which was originally added in commit 5dbbb60ba61e ("drm/amdgpu: add IP helpers for wait_for_idle and is_idle") but hasn't been used. Remove it. Signed-off-by: Dr. David Alan Gilbert Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 -- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 24 ---------------------- 2 files changed, 26 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 47005f1baf10c..3b78046646d43 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -366,8 +366,6 @@ void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev, u64 *flags); int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, enum amd_ip_block_type block_type); -bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, - enum amd_ip_block_type block_type); bool amdgpu_device_ip_is_valid(struct amdgpu_device *adev, enum amd_ip_block_type block_type); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 83ae2d47804c2..c2b3514734d83 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -2234,30 +2234,6 @@ int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, } -/** - * amdgpu_device_ip_is_idle - is the hardware IP idle - * - * @adev: amdgpu_device pointer - * @block_type: Type of hardware IP (SMU, GFX, UVD, etc.) - * - * Check if the hardware IP is idle or not. - * Returns true if it the IP is idle, false if not. - */ -bool amdgpu_device_ip_is_idle(struct amdgpu_device *adev, - enum amd_ip_block_type block_type) -{ - int i; - - for (i = 0; i < adev->num_ip_blocks; i++) { - if (!adev->ip_blocks[i].status.valid) - continue; - if (adev->ip_blocks[i].version->type == block_type) - return adev->ip_blocks[i].version->funcs->is_idle((void *)adev); - } - return true; - -} - /** * amdgpu_device_ip_is_valid - is the hardware IP enabled * From 130ceb0f0b77aeef169f123adc8fb8a54d7071e5 Mon Sep 17 00:00:00 2001 From: "Dr. David Alan Gilbert" Date: Mon, 23 Sep 2024 02:24:43 +0100 Subject: [PATCH 1650/1868] drm/amdgpu: Remove unused amdgpu_atpx functions amdgpu_atpx_dgpu_req_power_for_displays has been unused since commit bdb1ccb080da ("drm/amdgpu: remove ATPX_DGPU_REQ_POWER_FOR_DISPLAYS check when hotplug-in") amdgpu_atpx_get_dhandle has been unused since commit f9b7f3703ff9 ("drm/amdgpu/acpi: make ATPX/ATCS structures global (v2)") Remove them. Signed-off-by: Dr. David Alan Gilbert Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 8 -------- drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c | 12 ------------ 2 files changed, 20 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 3b78046646d43..3cc570624d21c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -1505,23 +1505,15 @@ void amdgpu_register_atpx_handler(void); void amdgpu_unregister_atpx_handler(void); bool amdgpu_has_atpx_dgpu_power_cntl(void); bool amdgpu_is_atpx_hybrid(void); -bool amdgpu_atpx_dgpu_req_power_for_displays(void); bool amdgpu_has_atpx(void); #else static inline void amdgpu_register_atpx_handler(void) {} static inline void amdgpu_unregister_atpx_handler(void) {} static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; } static inline bool amdgpu_is_atpx_hybrid(void) { return false; } -static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; } static inline bool amdgpu_has_atpx(void) { return false; } #endif -#if defined(CONFIG_VGA_SWITCHEROO) && defined(CONFIG_ACPI) -void *amdgpu_atpx_get_dhandle(void); -#else -static inline void *amdgpu_atpx_get_dhandle(void) { return NULL; } -#endif - /* * KMS */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c index fda8bf2751513..3353c78a258aa 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c @@ -91,18 +91,6 @@ bool amdgpu_is_atpx_hybrid(void) return amdgpu_atpx_priv.atpx.is_hybrid; } -bool amdgpu_atpx_dgpu_req_power_for_displays(void) -{ - return amdgpu_atpx_priv.atpx.dgpu_req_power_for_displays; -} - -#if defined(CONFIG_ACPI) -void *amdgpu_atpx_get_dhandle(void) -{ - return amdgpu_atpx_priv.dhandle; -} -#endif - /** * amdgpu_atpx_call - call an ATPX method * From 7e54c0dd9ff1c83978b966be8f35318773030d19 Mon Sep 17 00:00:00 2001 From: "Dr. David Alan Gilbert" Date: Mon, 23 Sep 2024 02:24:44 +0100 Subject: [PATCH 1651/1868] drm/amdgpu: Remove unused amdgpu_gmc_vram_cpu_pa amdgpu_gmc_vram_cpu_pa has been unused since commit 087451f372bf ("drm/amdgpu: use generic fb helpers instead of setting up AMD own's.") Remove it. Signed-off-by: Dr. David Alan Gilbert Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 12 ------------ drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 1 - 2 files changed, 13 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c index d571b20fe11d4..ea8142bc60515 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c @@ -1086,18 +1086,6 @@ uint64_t amdgpu_gmc_vram_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo) return amdgpu_gmc_vram_mc2pa(adev, amdgpu_bo_gpu_offset(bo)); } -/** - * amdgpu_gmc_vram_cpu_pa - calculate vram buffer object's physical address - * from CPU's view - * - * @adev: amdgpu_device pointer - * @bo: amdgpu buffer object - */ -uint64_t amdgpu_gmc_vram_cpu_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo) -{ - return amdgpu_bo_gpu_offset(bo) - adev->gmc.vram_start + adev->gmc.aper_base; -} - int amdgpu_gmc_vram_checking(struct amdgpu_device *adev) { struct amdgpu_bo *vram_bo = NULL; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h index 33b2adffd58b1..1970d18a21380 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h @@ -446,7 +446,6 @@ void amdgpu_gmc_get_vbios_allocations(struct amdgpu_device *adev); void amdgpu_gmc_init_pdb0(struct amdgpu_device *adev); uint64_t amdgpu_gmc_vram_mc2pa(struct amdgpu_device *adev, uint64_t mc_addr); uint64_t amdgpu_gmc_vram_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo); -uint64_t amdgpu_gmc_vram_cpu_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo); int amdgpu_gmc_vram_checking(struct amdgpu_device *adev); int amdgpu_gmc_sysfs_init(struct amdgpu_device *adev); void amdgpu_gmc_sysfs_fini(struct amdgpu_device *adev); From 20ae8b53051428d9f4f97aa4993453030ce8bde8 Mon Sep 17 00:00:00 2001 From: "Dr. David Alan Gilbert" Date: Mon, 23 Sep 2024 02:24:45 +0100 Subject: [PATCH 1652/1868] drm/amdgpu: Remove unused amdgpu_gfx_bit_to_me_queue amdgpu_gfx_bit_to_me_queue has been unused since it was added in commit 7470bfcf2014 ("drm/amdgpu: add helper function for gfx queue/bitmap transition") Remove it. Signed-off-by: Dr. David Alan Gilbert Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 10 ---------- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 2 -- 2 files changed, 12 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c index 2d3fdb6c31617..2fe75c920a73c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c @@ -87,16 +87,6 @@ int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev, return bit; } -void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit, - int *me, int *pipe, int *queue) -{ - *queue = bit % adev->gfx.me.num_queue_per_pipe; - *pipe = (bit / adev->gfx.me.num_queue_per_pipe) - % adev->gfx.me.num_pipe_per_me; - *me = (bit / adev->gfx.me.num_queue_per_pipe) - / adev->gfx.me.num_pipe_per_me; -} - bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, int me, int pipe, int queue) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h index 793c9b89beee1..15fffc2875e70 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h @@ -551,8 +551,6 @@ bool amdgpu_gfx_is_high_priority_graphics_queue(struct amdgpu_device *adev, struct amdgpu_ring *ring); int amdgpu_gfx_me_queue_to_bit(struct amdgpu_device *adev, int me, int pipe, int queue); -void amdgpu_gfx_bit_to_me_queue(struct amdgpu_device *adev, int bit, - int *me, int *pipe, int *queue); bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, int me, int pipe, int queue); void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable); From 8ca0b4a999f24cf218156105784ebeb93e121a96 Mon Sep 17 00:00:00 2001 From: "Dr. David Alan Gilbert" Date: Mon, 23 Sep 2024 02:24:46 +0100 Subject: [PATCH 1653/1868] drm/amdgpu: Remove unused amdgpu_i2c functions amdgpu_i2c_add and amdgpu_i2c_init were added in 2015's commit d38ceaf99ed0 ("drm/amdgpu: add core driver (v4)") but never used. Remove them. Signed-off-by: Dr. David Alan Gilbert Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c | 25 ------------------------- drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.h | 4 ---- 2 files changed, 29 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c index 00d6211e0fbf9..f0765ccde6680 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.c @@ -225,15 +225,6 @@ void amdgpu_i2c_destroy(struct amdgpu_i2c_chan *i2c) kfree(i2c); } -/* Add the default buses */ -void amdgpu_i2c_init(struct amdgpu_device *adev) -{ - if (amdgpu_hw_i2c) - DRM_INFO("hw_i2c forced on, you may experience display detection problems!\n"); - - amdgpu_atombios_i2c_init(adev); -} - /* remove all the buses */ void amdgpu_i2c_fini(struct amdgpu_device *adev) { @@ -247,22 +238,6 @@ void amdgpu_i2c_fini(struct amdgpu_device *adev) } } -/* Add additional buses */ -void amdgpu_i2c_add(struct amdgpu_device *adev, - const struct amdgpu_i2c_bus_rec *rec, - const char *name) -{ - struct drm_device *dev = adev_to_drm(adev); - int i; - - for (i = 0; i < AMDGPU_MAX_I2C_BUS; i++) { - if (!adev->i2c_bus[i]) { - adev->i2c_bus[i] = amdgpu_i2c_create(dev, rec, name); - return; - } - } -} - /* looks up bus based on id */ struct amdgpu_i2c_chan * amdgpu_i2c_lookup(struct amdgpu_device *adev, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.h index 63c2ff7499e17..21e3d1dad0a12 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.h @@ -28,11 +28,7 @@ struct amdgpu_i2c_chan *amdgpu_i2c_create(struct drm_device *dev, const struct amdgpu_i2c_bus_rec *rec, const char *name); void amdgpu_i2c_destroy(struct amdgpu_i2c_chan *i2c); -void amdgpu_i2c_init(struct amdgpu_device *adev); void amdgpu_i2c_fini(struct amdgpu_device *adev); -void amdgpu_i2c_add(struct amdgpu_device *adev, - const struct amdgpu_i2c_bus_rec *rec, - const char *name); struct amdgpu_i2c_chan * amdgpu_i2c_lookup(struct amdgpu_device *adev, const struct amdgpu_i2c_bus_rec *i2c_bus); From c3e7a20e68f06d8c6a10bde992db9831ddfb13bb Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Fri, 30 Aug 2024 11:21:43 +0530 Subject: [PATCH 1654/1868] drm/amdgpu: Add helper to initialize badpage info Add a separate function to read badpage data during initialization. Reading bad pages will need hardware access and cannot be done during reset. Hence in cases where device needs a full reset during init itself, attempting to read will cause a deadlock. Signed-off-by: Lijo Lazar Reviewed-by: Feifei Xu Reviewed-by: Alex Deucher Acked-by: Rajneesh Bhardwaj Tested-by: Rajneesh Bhardwaj --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 56 +++++++++++++++------- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 4 +- 3 files changed, 41 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index c2b3514734d83..fd932adbc08c2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -2974,7 +2974,7 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev) * Note: theoretically, this should be called before all vram allocations * to protect retired page from abusing */ - r = amdgpu_ras_recovery_init(adev); + r = amdgpu_ras_recovery_init(adev, true); if (r) goto init_failed; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index ed437c451d540..086b9844d24f7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -3156,7 +3156,42 @@ static int amdgpu_ras_page_retirement_thread(void *param) return 0; } -int amdgpu_ras_recovery_init(struct amdgpu_device *adev) +int amdgpu_ras_init_badpage_info(struct amdgpu_device *adev) +{ + struct amdgpu_ras *con = amdgpu_ras_get_context(adev); + int ret; + + if (!con || amdgpu_sriov_vf(adev)) + return 0; + + ret = amdgpu_ras_eeprom_init(&con->eeprom_control); + + if (ret) + return ret; + + /* HW not usable */ + if (amdgpu_ras_is_rma(adev)) + return -EHWPOISON; + + if (con->eeprom_control.ras_num_recs) { + ret = amdgpu_ras_load_bad_pages(adev); + if (ret) + return ret; + + amdgpu_dpm_send_hbm_bad_pages_num( + adev, con->eeprom_control.ras_num_recs); + + if (con->update_channel_flag == true) { + amdgpu_dpm_send_hbm_bad_channel_flag( + adev, con->eeprom_control.bad_channel_bitmap); + con->update_channel_flag = false; + } + } + + return ret; +} + +int amdgpu_ras_recovery_init(struct amdgpu_device *adev, bool init_bp_info) { struct amdgpu_ras *con = amdgpu_ras_get_context(adev); struct ras_err_handler_data **data; @@ -3197,25 +3232,10 @@ int amdgpu_ras_recovery_init(struct amdgpu_device *adev) */ if (adev->init_lvl->level == AMDGPU_INIT_LEVEL_MINIMAL_XGMI) return 0; - ret = amdgpu_ras_eeprom_init(&con->eeprom_control); - /* - * This calling fails when is_rma is true or - * ret != 0. - */ - if (amdgpu_ras_is_rma(adev) || ret) - goto free; - - if (con->eeprom_control.ras_num_recs) { - ret = amdgpu_ras_load_bad_pages(adev); + if (init_bp_info) { + ret = amdgpu_ras_init_badpage_info(adev); if (ret) goto free; - - amdgpu_dpm_send_hbm_bad_pages_num(adev, con->eeprom_control.ras_num_recs); - - if (con->update_channel_flag == true) { - amdgpu_dpm_send_hbm_bad_channel_flag(adev, con->eeprom_control.bad_channel_bitmap); - con->update_channel_flag = false; - } } mutex_init(&con->page_rsv_lock); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h index 669720a9c60af..871b2d6278e07 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h @@ -736,8 +736,8 @@ struct amdgpu_ras_block_hw_ops { * 8: feature disable */ - -int amdgpu_ras_recovery_init(struct amdgpu_device *adev); +int amdgpu_ras_init_badpage_info(struct amdgpu_device *adev); +int amdgpu_ras_recovery_init(struct amdgpu_device *adev, bool init_bp_info); void amdgpu_ras_resume(struct amdgpu_device *adev); void amdgpu_ras_suspend(struct amdgpu_device *adev); From c57da5990f795b653bb22b0bff6655eaaf6b290f Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Mon, 26 Aug 2024 18:52:14 +0530 Subject: [PATCH 1655/1868] drm/amdgpu: Refactor XGMI reset on init handling Use XGMI hive information to rely on resetting XGMI devices on initialization rather than using mgpu structure. mgpu structure may have other devices as well. Signed-off-by: Lijo Lazar Reviewed-by: Feifei Xu Acked-by: Rajneesh Bhardwaj Tested-by: Rajneesh Bhardwaj --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 10 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 6 -- drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 73 ++++++++++++++++++++-- drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h | 2 + drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 14 +++-- drivers/gpu/drm/amd/amdgpu/soc15.c | 5 ++ 6 files changed, 91 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index fd932adbc08c2..514d55e0c31e8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -166,7 +166,8 @@ struct amdgpu_init_level amdgpu_init_minimal_xgmi = { .level = AMDGPU_INIT_LEVEL_MINIMAL_XGMI, .hwini_ip_block_mask = BIT(AMD_IP_BLOCK_TYPE_GMC) | BIT(AMD_IP_BLOCK_TYPE_SMC) | - BIT(AMD_IP_BLOCK_TYPE_COMMON) | BIT(AMD_IP_BLOCK_TYPE_IH) + BIT(AMD_IP_BLOCK_TYPE_COMMON) | BIT(AMD_IP_BLOCK_TYPE_IH) | + BIT(AMD_IP_BLOCK_TYPE_PSP) }; static inline bool amdgpu_ip_member_of_hwini(struct amdgpu_device *adev, @@ -2861,6 +2862,7 @@ static int amdgpu_device_init_schedulers(struct amdgpu_device *adev) */ static int amdgpu_device_ip_init(struct amdgpu_device *adev) { + bool init_badpage; int i, r; r = amdgpu_ras_init(adev); @@ -2974,7 +2976,8 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev) * Note: theoretically, this should be called before all vram allocations * to protect retired page from abusing */ - r = amdgpu_ras_recovery_init(adev, true); + init_badpage = (adev->init_lvl->level != AMDGPU_INIT_LEVEL_MINIMAL_XGMI); + r = amdgpu_ras_recovery_init(adev, init_badpage); if (r) goto init_failed; @@ -4532,8 +4535,7 @@ int amdgpu_device_init(struct amdgpu_device *adev, vga_switcheroo_init_domain_pm_ops(adev->dev, &adev->vga_pm_domain); if (adev->init_lvl->level == AMDGPU_INIT_LEVEL_MINIMAL_XGMI) - queue_delayed_work(system_wq, &mgpu_info.delayed_reset_work, - msecs_to_jiffies(AMDGPU_RESUME_MS)); + amdgpu_xgmi_reset_on_init(adev); amdgpu_device_check_iommu_direct_map(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 086b9844d24f7..5307012f6de7d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -3226,12 +3226,6 @@ int amdgpu_ras_recovery_init(struct amdgpu_device *adev, bool init_bp_info) max_eeprom_records_count = amdgpu_ras_eeprom_max_record_count(&con->eeprom_control); amdgpu_ras_validate_threshold(adev, max_eeprom_records_count); - /* Todo: During test the SMU might fail to read the eeprom through I2C - * when the GPU is pending on XGMI reset during probe time - * (Mostly after second bus reset), skip it now - */ - if (adev->init_lvl->level == AMDGPU_INIT_LEVEL_MINIMAL_XGMI) - return 0; if (init_bp_info) { ret = amdgpu_ras_init_badpage_info(adev); if (ret) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c index bcd59162d8918..13a699cd8f8d8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c @@ -866,8 +866,7 @@ int amdgpu_xgmi_add_device(struct amdgpu_device *adev) if (!adev->gmc.xgmi.supported) return 0; - if ((adev->init_lvl->level != AMDGPU_INIT_LEVEL_MINIMAL_XGMI) && - amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP)) { + if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP)) { ret = psp_xgmi_initialize(&adev->psp, false, true); if (ret) { dev_err(adev->dev, @@ -913,8 +912,7 @@ int amdgpu_xgmi_add_device(struct amdgpu_device *adev) task_barrier_add_task(&hive->tb); - if ((adev->init_lvl->level != AMDGPU_INIT_LEVEL_MINIMAL_XGMI) && - amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP)) { + if (amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_PSP)) { list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) { /* update node list for other device in the hive */ if (tmp_adev != adev) { @@ -991,7 +989,7 @@ int amdgpu_xgmi_add_device(struct amdgpu_device *adev) } } - if (!ret && (adev->init_lvl->level != AMDGPU_INIT_LEVEL_MINIMAL_XGMI)) + if (!ret) ret = amdgpu_xgmi_sysfs_add_dev_info(adev, hive); exit_unlock: @@ -1506,3 +1504,68 @@ int amdgpu_xgmi_ras_sw_init(struct amdgpu_device *adev) return 0; } + +static void amdgpu_xgmi_reset_on_init_work(struct work_struct *work) +{ + struct amdgpu_hive_info *hive = + container_of(work, struct amdgpu_hive_info, reset_on_init_work); + struct amdgpu_reset_context reset_context; + struct amdgpu_device *tmp_adev; + struct list_head device_list; + int r; + + mutex_lock(&hive->hive_lock); + + INIT_LIST_HEAD(&device_list); + list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) + list_add_tail(&tmp_adev->reset_list, &device_list); + + tmp_adev = list_first_entry(&device_list, struct amdgpu_device, + reset_list); + amdgpu_device_lock_reset_domain(tmp_adev->reset_domain); + + reset_context.method = AMD_RESET_METHOD_ON_INIT; + reset_context.reset_req_dev = tmp_adev; + reset_context.hive = hive; + reset_context.reset_device_list = &device_list; + set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); + set_bit(AMDGPU_SKIP_COREDUMP, &reset_context.flags); + + amdgpu_reset_do_xgmi_reset_on_init(&reset_context); + mutex_unlock(&hive->hive_lock); + amdgpu_device_unlock_reset_domain(tmp_adev->reset_domain); + + list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) { + r = amdgpu_ras_init_badpage_info(tmp_adev); + if (r && r != -EHWPOISON) + dev_err(tmp_adev->dev, + "error during bad page data initializtion"); + } +} + +static void amdgpu_xgmi_schedule_reset_on_init(struct amdgpu_hive_info *hive) +{ + INIT_WORK(&hive->reset_on_init_work, amdgpu_xgmi_reset_on_init_work); + amdgpu_reset_domain_schedule(hive->reset_domain, + &hive->reset_on_init_work); +} + +int amdgpu_xgmi_reset_on_init(struct amdgpu_device *adev) +{ + struct amdgpu_hive_info *hive; + int num_devs; + + hive = amdgpu_get_xgmi_hive(adev); + if (!hive) + return -EINVAL; + + mutex_lock(&hive->hive_lock); + num_devs = atomic_read(&hive->number_devices); + if (num_devs == adev->gmc.xgmi.num_physical_nodes) + amdgpu_xgmi_schedule_reset_on_init(hive); + + mutex_unlock(&hive->hive_lock); + amdgpu_put_xgmi_hive(hive); + + return 0; +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h index a3bfc16de6d49..d652727ca5655 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h @@ -45,6 +45,7 @@ struct amdgpu_hive_info { struct amdgpu_reset_domain *reset_domain; atomic_t ras_recovery; struct ras_event_manager event_mgr; + struct work_struct reset_on_init_work; }; struct amdgpu_pcs_ras_field { @@ -75,5 +76,6 @@ static inline bool amdgpu_xgmi_same_hive(struct amdgpu_device *adev, adev->gmc.xgmi.hive_id == bo_adev->gmc.xgmi.hive_id); } int amdgpu_xgmi_ras_sw_init(struct amdgpu_device *adev); +int amdgpu_xgmi_reset_on_init(struct amdgpu_device *adev); #endif diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index 0a5c8d97787a7..cffda0a045b9b 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -2419,11 +2419,17 @@ static int gmc_v9_0_hw_fini(void *handle) if (adev->mmhub.funcs->update_power_gating) adev->mmhub.funcs->update_power_gating(adev, false); - amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); + /* + * For minimal init, late_init is not called, hence VM fault/RAS irqs + * are not enabled. + */ + if (adev->init_lvl->level != AMDGPU_INIT_LEVEL_MINIMAL_XGMI) { + amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); - if (adev->gmc.ecc_irq.funcs && - amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) - amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); + if (adev->gmc.ecc_irq.funcs && + amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC)) + amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); + } return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index cf701bb8fc797..6a49ed4b46162 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -1297,7 +1297,12 @@ static int soc15_common_hw_fini(void *handle) if (amdgpu_sriov_vf(adev)) xgpu_ai_mailbox_put_irq(adev); + /* + * For minimal init, late_init is not called, hence RAS irqs are not + * enabled. + */ if ((!amdgpu_sriov_vf(adev)) && + (adev->init_lvl->level != AMDGPU_INIT_LEVEL_MINIMAL_XGMI) && adev->nbio.ras_if && amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) { if (adev->nbio.ras && From 1d4930069cc379c98014a30031f4d81139772c46 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Mon, 2 Sep 2024 11:52:26 +0530 Subject: [PATCH 1656/1868] drm/amdgpu: Drop delayed reset work handler Drop delayed reset work handler as it is no longer used. Signed-off-by: Lijo Lazar Reviewed-by: Feifei Xu Reviewed-by: Alex Deucher Acked-by: Rajneesh Bhardwaj Tested-by: Rajneesh Bhardwaj --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 4 -- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 80 ------------------------- 2 files changed, 84 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 3cc570624d21c..d240dd8e15248 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -132,10 +132,6 @@ struct amdgpu_mgpu_info { uint32_t num_gpu; uint32_t num_dgpu; uint32_t num_apu; - - /* delayed reset_func for XGMI configuration if necessary */ - struct delayed_work delayed_reset_work; - bool pending_reset; }; enum amdgpu_ss { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 31a3c82c37f20..4aeaf3403a25a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -232,8 +232,6 @@ int amdgpu_wbrf = -1; int amdgpu_damage_clips = -1; /* auto */ int amdgpu_umsch_mm_fwlog; -static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work); - DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0, "DRM_UT_CORE", "DRM_UT_DRIVER", @@ -248,9 +246,6 @@ DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0, struct amdgpu_mgpu_info mgpu_info = { .mutex = __MUTEX_INITIALIZER(mgpu_info.mutex), - .delayed_reset_work = __DELAYED_WORK_INITIALIZER( - mgpu_info.delayed_reset_work, - amdgpu_drv_delayed_reset_work_handler, 0), }; int amdgpu_ras_enable = -1; uint amdgpu_ras_mask = 0xffffffff; @@ -2526,81 +2521,6 @@ amdgpu_pci_shutdown(struct pci_dev *pdev) adev->mp1_state = PP_MP1_STATE_NONE; } -/** - * amdgpu_drv_delayed_reset_work_handler - work handler for reset - * - * @work: work_struct. - */ -static void amdgpu_drv_delayed_reset_work_handler(struct work_struct *work) -{ - struct list_head device_list; - struct amdgpu_device *adev; - int i, r; - struct amdgpu_reset_context reset_context; - - memset(&reset_context, 0, sizeof(reset_context)); - - mutex_lock(&mgpu_info.mutex); - if (mgpu_info.pending_reset == true) { - mutex_unlock(&mgpu_info.mutex); - return; - } - mgpu_info.pending_reset = true; - mutex_unlock(&mgpu_info.mutex); - - /* Use a common context, just need to make sure full reset is done */ - reset_context.method = AMD_RESET_METHOD_NONE; - set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags); - - for (i = 0; i < mgpu_info.num_dgpu; i++) { - adev = mgpu_info.gpu_ins[i].adev; - reset_context.reset_req_dev = adev; - r = amdgpu_device_pre_asic_reset(adev, &reset_context); - if (r) { - dev_err(adev->dev, "GPU pre asic reset failed with err, %d for drm dev, %s ", - r, adev_to_drm(adev)->unique); - } - if (!queue_work(system_unbound_wq, &adev->xgmi_reset_work)) - r = -EALREADY; - } - for (i = 0; i < mgpu_info.num_dgpu; i++) { - adev = mgpu_info.gpu_ins[i].adev; - flush_work(&adev->xgmi_reset_work); - } - - /* reset function will rebuild the xgmi hive info , clear it now */ - for (i = 0; i < mgpu_info.num_dgpu; i++) - amdgpu_xgmi_remove_device(mgpu_info.gpu_ins[i].adev); - - INIT_LIST_HEAD(&device_list); - - for (i = 0; i < mgpu_info.num_dgpu; i++) - list_add_tail(&mgpu_info.gpu_ins[i].adev->reset_list, &device_list); - - /* unregister the GPU first, reset function will add them back */ - list_for_each_entry(adev, &device_list, reset_list) - amdgpu_unregister_gpu_instance(adev); - - /* Use a common context, just need to make sure full reset is done */ - set_bit(AMDGPU_SKIP_HW_RESET, &reset_context.flags); - set_bit(AMDGPU_SKIP_COREDUMP, &reset_context.flags); - r = amdgpu_do_asic_reset(&device_list, &reset_context); - - if (r) { - DRM_ERROR("reinit gpus failure"); - return; - } - for (i = 0; i < mgpu_info.num_dgpu; i++) { - adev = mgpu_info.gpu_ins[i].adev; - if (!adev->kfd.init_complete) { - kgd2kfd_init_zone_device(adev); - amdgpu_amdkfd_device_init(adev); - amdgpu_amdkfd_drm_client_create(adev); - } - amdgpu_ttm_set_buffer_funcs_status(adev, true); - } -} - static int amdgpu_pmops_prepare(struct device *dev) { struct drm_device *drm_dev = dev_get_drvdata(dev); From 85762c0f594d80172b2a9fb8efecd5ed53a14e7a Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Mon, 2 Sep 2024 11:34:39 +0530 Subject: [PATCH 1657/1868] drm/amdgpu: Support reset-on-init on select SOCs Add XGMI reset on init support to aldebaran and SOCs with GC v9.4.3. Signed-off-by: Lijo Lazar Reviewed-by: Feifei Xu Reviewed-by: Alex Deucher Acked-by: Rajneesh Bhardwaj Tested-by: Rajneesh Bhardwaj --- drivers/gpu/drm/amd/amdgpu/aldebaran.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/aldebaran.c b/drivers/gpu/drm/amd/amdgpu/aldebaran.c index b0f95a7649bfe..98fb0ba4f9cb8 100644 --- a/drivers/gpu/drm/amd/amdgpu/aldebaran.c +++ b/drivers/gpu/drm/amd/amdgpu/aldebaran.c @@ -417,6 +417,7 @@ static struct amdgpu_reset_handler aldebaran_mode2_handler = { static struct amdgpu_reset_handler *aldebaran_rst_handlers[AMDGPU_RESET_MAX_HANDLERS] = { &aldebaran_mode2_handler, + &xgmi_reset_on_init_handler, }; int aldebaran_reset_init(struct amdgpu_device *adev) From ae06a9c3f2cbee52945b2397a193f12cba7f26b9 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Mon, 2 Sep 2024 11:20:22 +0530 Subject: [PATCH 1658/1868] drm/amdgpu: Add interface for TOS reload cases Add interface to check if a different TOS needs to be loaded than the one which is which is already active on the SOC. Presently the interface is restricted to specific variants of PSPv13.0. Signed-off-by: Lijo Lazar Reviewed-by: Feifei Xu Reviewed-by: Alex Deucher Acked-by: Rajneesh Bhardwaj Tested-by: Rajneesh Bhardwaj --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 13 +++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 2 ++ drivers/gpu/drm/amd/amdgpu/psp_v13_0.c | 25 +++++++++++++++++++++++++ 3 files changed, 40 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 0e2377c0ad86a..c9e7e49ffc828 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -2266,6 +2266,19 @@ bool amdgpu_psp_get_ras_capability(struct psp_context *psp) } } +bool amdgpu_psp_tos_reload_needed(struct amdgpu_device *adev) +{ + struct psp_context *psp = &adev->psp; + + if (amdgpu_sriov_vf(adev)) + return false; + + if (psp->funcs && psp->funcs->is_reload_needed) + return psp->funcs->is_reload_needed(psp); + + return false; +} + static int psp_hw_start(struct psp_context *psp) { struct amdgpu_device *adev = psp->adev; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h index f61ba076573c3..76fa18ffc0452 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h @@ -139,6 +139,7 @@ struct psp_funcs { int (*fatal_error_recovery_quirk)(struct psp_context *psp); bool (*get_ras_capability)(struct psp_context *psp); bool (*is_aux_sos_load_required)(struct psp_context *psp); + bool (*is_reload_needed)(struct psp_context *psp); }; struct ta_funcs { @@ -560,5 +561,6 @@ bool amdgpu_psp_get_ras_capability(struct psp_context *psp); int psp_config_sq_perfmon(struct psp_context *psp, uint32_t xcp_id, bool core_override_enable, bool reg_override_enable, bool perfmon_override_enable); +bool amdgpu_psp_tos_reload_needed(struct amdgpu_device *adev); #endif diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c index 51e470e8d67d9..c4b775aaee9fe 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c +++ b/drivers/gpu/drm/amd/amdgpu/psp_v13_0.c @@ -823,6 +823,30 @@ static bool psp_v13_0_is_aux_sos_load_required(struct psp_context *psp) return (pmfw_ver < 0x557300); } +static bool psp_v13_0_is_reload_needed(struct psp_context *psp) +{ + uint32_t ucode_ver; + + if (!psp_v13_0_is_sos_alive(psp)) + return false; + + /* Restrict reload support only to specific IP versions */ + switch (amdgpu_ip_version(psp->adev, MP0_HWIP, 0)) { + case IP_VERSION(13, 0, 2): + case IP_VERSION(13, 0, 6): + case IP_VERSION(13, 0, 14): + /* TOS version read from microcode header */ + ucode_ver = psp->sos.fw_version; + /* Read TOS version from hardware */ + psp_v13_0_init_sos_version(psp); + return (ucode_ver != psp->sos.fw_version); + default: + return false; + } + + return false; +} + static const struct psp_funcs psp_v13_0_funcs = { .init_microcode = psp_v13_0_init_microcode, .wait_for_bootloader = psp_v13_0_wait_for_bootloader_steady_state, @@ -847,6 +871,7 @@ static const struct psp_funcs psp_v13_0_funcs = { .fatal_error_recovery_quirk = psp_v13_0_fatal_error_recovery_quirk, .get_ras_capability = psp_v13_0_get_ras_capability, .is_aux_sos_load_required = psp_v13_0_is_aux_sos_load_required, + .is_reload_needed = psp_v13_0_is_reload_needed, }; void psp_v13_0_set_psp_funcs(struct psp_context *psp) From 754dda113d00a67f6c1632e258c32f5d7794432c Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Mon, 2 Sep 2024 11:28:34 +0530 Subject: [PATCH 1659/1868] drm/amdgpu: Add PSP reload case to reset-on-init A reset on initialization will be needed if a new PSP TOS needs to be loaded than the one currently active on the system. This is possible only on SOCs which support a full device reset which results in unload of active PSP TOS. Signed-off-by: Lijo Lazar Reviewed-by: Feifei Xu Reviewed-by: Alex Deucher Acked-by: Rajneesh Bhardwaj Tested-by: Rajneesh Bhardwaj --- drivers/gpu/drm/amd/amdgpu/soc15.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index 6a49ed4b46162..619933f252aa5 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -831,6 +831,8 @@ static bool soc15_need_reset_on_init(struct amdgpu_device *adev) if (adev->asic_type == CHIP_RENOIR) return true; + if (amdgpu_psp_tos_reload_needed(adev)) + return true; /* Just return false for soc15 GPUs. Reset does not seem to * be necessary. */ From a097cff1e6e627ca08f27c6fe2679905684ef0b5 Mon Sep 17 00:00:00 2001 From: Kenneth Feng Date: Fri, 20 Sep 2024 19:05:37 +0800 Subject: [PATCH 1660/1868] drm/amd/pm: update workload mask after the setting update workload mask after the setting, to fix: https://gitlab.freedesktop.org/drm/amd/-/issues/3625 Signed-off-by: Kenneth Feng Acked-by: Alex Deucher --- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 6 +++++- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 3 +++ drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c | 6 +++++- 3 files changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c index c9639141792f4..d5d74e4913223 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c @@ -2569,10 +2569,14 @@ static int smu_v13_0_0_set_power_profile_mode(struct smu_context *smu, } } - return smu_cmn_send_smc_msg_with_param(smu, + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask, workload_mask, NULL); + if (!ret) + smu->workload_mask = workload_mask; + + return ret; } static bool smu_v13_0_0_is_mode1_reset_supported(struct smu_context *smu) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c index 7bc95c4043778..b891a5e0a3969 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c @@ -2501,8 +2501,11 @@ static int smu_v13_0_7_set_power_profile_mode(struct smu_context *smu, long *inp return -EINVAL; ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask, 1 << workload_type, NULL); + if (ret) dev_err(smu->adev->dev, "[%s] Failed to set work load mask!", __func__); + else + smu->workload_mask = (1 << workload_type); return ret; } diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c index 43820d7d2c54a..5899d01fa73d3 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c @@ -1861,10 +1861,14 @@ static int smu_v14_0_2_set_power_profile_mode(struct smu_context *smu, if (workload_type < 0) return -EINVAL; - return smu_cmn_send_smc_msg_with_param(smu, + ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask, 1 << workload_type, NULL); + if (!ret) + smu->workload_mask = 1 << workload_type; + + return ret; } static int smu_v14_0_2_baco_enter(struct smu_context *smu) From 0d5b2e83ccd09d204a38bd684a437b5696c417ce Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Fri, 6 Sep 2024 13:51:06 -0400 Subject: [PATCH 1661/1868] drm/amdgpu: bump driver version for cleared VRAM MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Driver now clears VRAM on allocation. Bump the driver version so mesa knows when it will get cleared vram by default. Reviewed-by: Marek Olšák Reviewed-by: Rajneesh Bhardwaj Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 4aeaf3403a25a..8110dbf8878a5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -117,9 +117,10 @@ * - 3.56.0 - Update IB start address and size alignment for decode and encode * - 3.57.0 - Compute tunneling on GFX10+ * - 3.58.0 - Add GFX12 DCC support + * - 3.59.0 - Cleared VRAM */ #define KMS_DRIVER_MAJOR 3 -#define KMS_DRIVER_MINOR 58 +#define KMS_DRIVER_MINOR 59 #define KMS_DRIVER_PATCHLEVEL 0 /* From 5d14f4e41e395530da5530f6f9f44189c39e9ea6 Mon Sep 17 00:00:00 2001 From: Lang Yu Date: Mon, 23 Sep 2024 16:59:42 +0800 Subject: [PATCH 1662/1868] drm/amdkfd: Remove an unused parameter in queue creation struct file *f is unused in queue creation, remove it. Signed-off-by: Lang Yu Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 1 - drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c | 10 ++++------ 3 files changed, 5 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index 75135dc7dae70..a61d019485665 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -369,7 +369,7 @@ static int kfd_ioctl_create_queue(struct file *filep, struct kfd_process *p, p->pasid, dev->id); - err = pqm_create_queue(&p->pqm, dev, filep, &q_properties, &queue_id, + err = pqm_create_queue(&p->pqm, dev, &q_properties, &queue_id, NULL, NULL, NULL, &doorbell_offset_in_process); if (err != 0) goto err_create_queue; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index f2a2a87925fbe..319c1dade2c4f 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -1480,7 +1480,6 @@ int pqm_init(struct process_queue_manager *pqm, struct kfd_process *p); void pqm_uninit(struct process_queue_manager *pqm); int pqm_create_queue(struct process_queue_manager *pqm, struct kfd_node *dev, - struct file *f, struct queue_properties *properties, unsigned int *qid, const struct kfd_criu_queue_priv_data *q_data, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c index 74427fa6662d3..82ddd13453d06 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process_queue_manager.c @@ -235,7 +235,7 @@ void pqm_uninit(struct process_queue_manager *pqm) static int init_user_queue(struct process_queue_manager *pqm, struct kfd_node *dev, struct queue **q, struct queue_properties *q_properties, - struct file *f, unsigned int qid) + unsigned int qid) { int retval; @@ -300,7 +300,6 @@ static int init_user_queue(struct process_queue_manager *pqm, int pqm_create_queue(struct process_queue_manager *pqm, struct kfd_node *dev, - struct file *f, struct queue_properties *properties, unsigned int *qid, const struct kfd_criu_queue_priv_data *q_data, @@ -374,7 +373,7 @@ int pqm_create_queue(struct process_queue_manager *pqm, * allocate_sdma_queue() in create_queue() has the * corresponding check logic. */ - retval = init_user_queue(pqm, dev, &q, properties, f, *qid); + retval = init_user_queue(pqm, dev, &q, properties, *qid); if (retval != 0) goto err_create_queue; pqn->q = q; @@ -395,7 +394,7 @@ int pqm_create_queue(struct process_queue_manager *pqm, goto err_create_queue; } - retval = init_user_queue(pqm, dev, &q, properties, f, *qid); + retval = init_user_queue(pqm, dev, &q, properties, *qid); if (retval != 0) goto err_create_queue; pqn->q = q; @@ -1033,8 +1032,7 @@ int kfd_criu_restore_queue(struct kfd_process *p, print_queue_properties(&qp); - ret = pqm_create_queue(&p->pqm, pdd->dev, NULL, &qp, &queue_id, q_data, mqd, ctl_stack, - NULL); + ret = pqm_create_queue(&p->pqm, pdd->dev, &qp, &queue_id, q_data, mqd, ctl_stack, NULL); if (ret) { pr_err("Failed to create new queue err:%d\n", ret); goto exit; From e1baa1ac2b7e62ee1e09ab8492911ac75fea09dc Mon Sep 17 00:00:00 2001 From: Jiadong Zhu Date: Fri, 20 Sep 2024 09:45:42 +0800 Subject: [PATCH 1663/1868] drm/amdgpu/sdma5: split out per instance resume function Extract the resume sequence from sdma_v5_0_gfx_resume for starting/restarting an individual instance. Signed-off-by: Jiadong Zhu Acked-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 253 ++++++++++++++----------- 1 file changed, 138 insertions(+), 115 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c index 3e48ea38385de..e813da1e48aa8 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c @@ -705,14 +705,16 @@ static void sdma_v5_0_enable(struct amdgpu_device *adev, bool enable) } /** - * sdma_v5_0_gfx_resume - setup and start the async dma engines + * sdma_v5_0_gfx_resume_instance - start/restart a certain sdma engine * * @adev: amdgpu_device pointer + * @i: instance + * @restore: used to restore wptr when restart * - * Set up the gfx DMA ring buffers and enable them (NAVI10). - * Returns 0 for success, error for failure. + * Set up the gfx DMA ring buffers and enable them. On restart, we will restore wptr and rptr. + * Return 0 for success. */ -static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev) +static int sdma_v5_0_gfx_resume_instance(struct amdgpu_device *adev, int i, bool restore) { struct amdgpu_ring *ring; u32 rb_cntl, ib_cntl; @@ -722,142 +724,163 @@ static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev) u32 temp; u32 wptr_poll_cntl; u64 wptr_gpu_addr; - int i, r; - for (i = 0; i < adev->sdma.num_instances; i++) { - ring = &adev->sdma.instance[i].ring; + ring = &adev->sdma.instance[i].ring; - if (!amdgpu_sriov_vf(adev)) - WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); + if (!amdgpu_sriov_vf(adev)) + WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); - /* Set ring buffer size in dwords */ - rb_bufsz = order_base_2(ring->ring_size / 4); - rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); - rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); + /* Set ring buffer size in dwords */ + rb_bufsz = order_base_2(ring->ring_size / 4); + rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); #ifdef __BIG_ENDIAN - rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); - rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, - RPTR_WRITEBACK_SWAP_ENABLE, 1); + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, + RPTR_WRITEBACK_SWAP_ENABLE, 1); #endif - WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); - - /* Initialize the ring buffer's read and write pointers */ + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); + + /* Initialize the ring buffer's read and write pointers */ + if (restore) { + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), lower_32_bits(ring->wptr << 2)); + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), upper_32_bits(ring->wptr << 2)); + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2)); + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2)); + } else { WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0); WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0); WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0); WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0); - - /* setup the wptr shadow polling */ - wptr_gpu_addr = ring->wptr_gpu_addr; - WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO), - lower_32_bits(wptr_gpu_addr)); - WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI), - upper_32_bits(wptr_gpu_addr)); - wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, - mmSDMA0_GFX_RB_WPTR_POLL_CNTL)); - wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, - SDMA0_GFX_RB_WPTR_POLL_CNTL, - F32_POLL_ENABLE, 1); - WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), - wptr_poll_cntl); - - /* set the wb address whether it's enabled or not */ - WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI), - upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF); - WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO), - lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); - - rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); - - WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), - ring->gpu_addr >> 8); - WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), - ring->gpu_addr >> 40); - + } + /* setup the wptr shadow polling */ + wptr_gpu_addr = ring->wptr_gpu_addr; + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO), + lower_32_bits(wptr_gpu_addr)); + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI), + upper_32_bits(wptr_gpu_addr)); + wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, + mmSDMA0_GFX_RB_WPTR_POLL_CNTL)); + wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, + SDMA0_GFX_RB_WPTR_POLL_CNTL, + F32_POLL_ENABLE, 1); + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), + wptr_poll_cntl); + + /* set the wb address whether it's enabled or not */ + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI), + upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF); + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO), + lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); + + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); + + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), + ring->gpu_addr >> 8); + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), + ring->gpu_addr >> 40); + + if (!restore) ring->wptr = 0; - /* before programing wptr to a less value, need set minor_ptr_update first */ - WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1); + /* before programing wptr to a less value, need set minor_ptr_update first */ + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1); - if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ - WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), - lower_32_bits(ring->wptr << 2)); - WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), - upper_32_bits(ring->wptr << 2)); - } + if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ + WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), + lower_32_bits(ring->wptr << 2)); + WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), + upper_32_bits(ring->wptr << 2)); + } - doorbell = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL)); - doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, - mmSDMA0_GFX_DOORBELL_OFFSET)); + doorbell = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL)); + doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, + mmSDMA0_GFX_DOORBELL_OFFSET)); - if (ring->use_doorbell) { - doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); - doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET, - OFFSET, ring->doorbell_index); - } else { - doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); - } - WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell); - WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), - doorbell_offset); + if (ring->use_doorbell) { + doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); + doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET, + OFFSET, ring->doorbell_index); + } else { + doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); + } + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell); + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), + doorbell_offset); - adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, - ring->doorbell_index, 20); + adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, + ring->doorbell_index, 20); - if (amdgpu_sriov_vf(adev)) - sdma_v5_0_ring_set_wptr(ring); + if (amdgpu_sriov_vf(adev)) + sdma_v5_0_ring_set_wptr(ring); - /* set minor_ptr_update to 0 after wptr programed */ - WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0); + /* set minor_ptr_update to 0 after wptr programed */ + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0); - if (!amdgpu_sriov_vf(adev)) { - /* set utc l1 enable flag always to 1 */ - temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL)); - temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); - - /* enable MCBP */ - temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1); - WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp); - - /* Set up RESP_MODE to non-copy addresses */ - temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL)); - temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3); - temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9); - WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp); - - /* program default cache read and write policy */ - temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE)); - /* clean read policy and write policy bits */ - temp &= 0xFF0FFF; - temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | (CACHE_WRITE_POLICY_L2__DEFAULT << 14)); - WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp); - } + if (!amdgpu_sriov_vf(adev)) { + /* set utc l1 enable flag always to 1 */ + temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL)); + temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); + + /* enable MCBP */ + temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1); + WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp); + + /* Set up RESP_MODE to non-copy addresses */ + temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL)); + temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3); + temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9); + WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp); + + /* program default cache read and write policy */ + temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE)); + /* clean read policy and write policy bits */ + temp &= 0xFF0FFF; + temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | (CACHE_WRITE_POLICY_L2__DEFAULT << 14)); + WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp); + } - if (!amdgpu_sriov_vf(adev)) { - /* unhalt engine */ - temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); - temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); - WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp); - } + if (!amdgpu_sriov_vf(adev)) { + /* unhalt engine */ + temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); + temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); + WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp); + } - /* enable DMA RB */ - rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); - WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); + /* enable DMA RB */ + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); - ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); - ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); + ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); + ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); #ifdef __BIG_ENDIAN - ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); + ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); #endif - /* enable DMA IBs */ - WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); + /* enable DMA IBs */ + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); - if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */ - sdma_v5_0_ctx_switch_enable(adev, true); - sdma_v5_0_enable(adev, true); - } + if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */ + sdma_v5_0_ctx_switch_enable(adev, true); + sdma_v5_0_enable(adev, true); + } + + return amdgpu_ring_test_helper(ring); +} - r = amdgpu_ring_test_helper(ring); +/** + * sdma_v5_0_gfx_resume - setup and start the async dma engines + * + * @adev: amdgpu_device pointer + * + * Set up the gfx DMA ring buffers and enable them (NAVI10). + * Returns 0 for success, error for failure. + */ +static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev) +{ + int i, r; + + for (i = 0; i < adev->sdma.num_instances; i++) { + r = sdma_v5_0_gfx_resume_instance(adev, i, false); if (r) return r; } From 5aec32fdac1ed211ee5decedae1ba7d5c055bb9d Mon Sep 17 00:00:00 2001 From: Yihan Zhu Date: Sat, 7 Sep 2024 13:25:19 -0400 Subject: [PATCH 1664/1868] drm/amd/display: update DML2 policy EnhancedPrefetchScheduleAccelerationFinal DCN35 [WHY & HOW] Mismatch in DCN35 DML2 cause bw validation failed to acquire unexpected DPP pipe to cause grey screen and system hang. Remove EnhancedPrefetchScheduleAccelerationFinal value override to match HW spec. Cc: Mario Limonciello Cc: Alex Deucher Cc: stable@vger.kernel.org Reviewed-by: Charlene Liu Signed-off-by: Yihan Zhu Signed-off-by: Aurabindo Pillai Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/dml2/dml2_policy.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_policy.c b/drivers/gpu/drm/amd/display/dc/dml2/dml2_policy.c index c4c52173ef224..11c904ae29586 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_policy.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_policy.c @@ -303,7 +303,6 @@ void build_unoptimized_policy_settings(enum dml_project_id project, struct dml_m if (project == dml_project_dcn35 || project == dml_project_dcn351) { policy->DCCProgrammingAssumesScanDirectionUnknownFinal = false; - policy->EnhancedPrefetchScheduleAccelerationFinal = 0; policy->AllowForPStateChangeOrStutterInVBlankFinal = dml_prefetch_support_uclk_fclk_and_stutter_if_possible; /*new*/ policy->UseOnlyMaxPrefetchModes = 1; } From 1d527217762f5e1b1d7a596a1c207ace7f76e65a Mon Sep 17 00:00:00 2001 From: Samson Tam Date: Fri, 6 Sep 2024 03:28:47 -0400 Subject: [PATCH 1665/1868] drm/amd/display: disable adaptive scaler and sharpener when integer scaling is enabled [Why & How] When integer scaling is enabled, set taps to 1 and disable adaptive scaler and sharpener. Reviewed-by: Jun Lei Signed-off-by: Samson Tam Signed-off-by: Aurabindo Pillai Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/dc_spl_translate.c | 1 + drivers/gpu/drm/amd/display/dc/spl/dc_spl.c | 12 ++++++++++++ 2 files changed, 13 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c b/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c index 603552dbd7716..20fd0afca8cb0 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c +++ b/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c @@ -38,6 +38,7 @@ static void populate_spltaps_from_taps(struct spl_taps *spl_scaling_quality, spl_scaling_quality->h_taps = scaling_quality->h_taps; spl_scaling_quality->v_taps_c = scaling_quality->v_taps_c; spl_scaling_quality->v_taps = scaling_quality->v_taps; + spl_scaling_quality->integer_scaling = scaling_quality->integer_scaling; } static void populate_taps_from_spltaps(struct scaling_taps *scaling_quality, const struct spl_taps *spl_scaling_quality) diff --git a/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c b/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c index 014e8a296f0c7..c38a5c8646e86 100644 --- a/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c +++ b/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c @@ -885,6 +885,18 @@ static bool spl_get_optimal_number_of_taps( spl_scratch->scl_data.viewport.width > max_downscale_src_width) return false; + /* Disable adaptive scaler and sharpener when integer scaling is enabled */ + if (spl_in->scaling_quality.integer_scaling) { + spl_scratch->scl_data.taps.h_taps = 1; + spl_scratch->scl_data.taps.v_taps = 1; + spl_scratch->scl_data.taps.v_taps_c = 1; + spl_scratch->scl_data.taps.h_taps_c = 1; + *enable_easf_v = false; + *enable_easf_h = false; + *enable_isharp = false; + return true; + } + /* Check if we are using EASF or not */ skip_easf = enable_easf(spl_in, spl_scratch); From c6e8fab7cbb84df3ecff28a60a266db86b70ba22 Mon Sep 17 00:00:00 2001 From: Fangzhi Zuo Date: Wed, 4 Sep 2024 15:29:24 -0400 Subject: [PATCH 1666/1868] drm/amd/display: Restore Optimized pbn Value if Failed to Disable DSC Existing last step of dsc policy is to restore pbn value under minimum compression when try to greedily disable dsc for a stream failed to fit in MST bw. Optimized dsc params result from optimization step is not necessarily the minimum compression, therefore it is not correct to restore the pbn under minimum compression rate. Restore the pbn under minimum compression instead of the value from optimized pbn could result in the dsc params not correct at the modeset where atomic_check failed due to not enough bw. One or more monitors connected could not light up in such case. Restore the optimized pbn value, instead of using the pbn value under minimum compression. Cc: Mario Limonciello Cc: Alex Deucher Cc: stable@vger.kernel.org Reviewed-by: Wayne Lin Signed-off-by: Fangzhi Zuo Signed-off-by: Aurabindo Pillai Tested-by: Daniel Wheeler --- .../amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index f0f6055ef5745..1faa7612427bb 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -1240,6 +1240,7 @@ static int try_disable_dsc(struct drm_atomic_state *state, int remaining_to_try = 0; int ret; uint16_t fec_overhead_multiplier_x1000 = get_fec_overhead_multiplier(dc_link); + int var_pbn; for (i = 0; i < count; i++) { if (vars[i + k].dsc_enabled @@ -1270,6 +1271,7 @@ static int try_disable_dsc(struct drm_atomic_state *state, break; DRM_DEBUG_DRIVER("MST_DSC index #%d, try no compression\n", next_index); + var_pbn = vars[next_index].pbn; vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.stream_kbps, fec_overhead_multiplier_x1000); ret = drm_dp_atomic_find_time_slots(state, params[next_index].port->mgr, @@ -1279,8 +1281,12 @@ static int try_disable_dsc(struct drm_atomic_state *state, , dm_mst_get_pbn_divider(dc_link) #endif ); - if (ret < 0) + if (ret < 0) { + DRM_DEBUG_DRIVER("%s:%d MST_DSC index #%d, failed to set pbn to the state, %d\n", + __func__, __LINE__, next_index, ret); + vars[next_index].pbn = var_pbn; return ret; + } ret = drm_dp_mst_atomic_check(state); if (ret == 0) { @@ -1288,8 +1294,8 @@ static int try_disable_dsc(struct drm_atomic_state *state, vars[next_index].dsc_enabled = false; vars[next_index].bpp_x16 = 0; } else { - DRM_DEBUG_DRIVER("MST_DSC index #%d, restore minimum compression\n", next_index); - vars[next_index].pbn = kbps_to_peak_pbn(params[next_index].bw_range.max_kbps, fec_overhead_multiplier_x1000); + DRM_DEBUG_DRIVER("MST_DSC index #%d, restore optimized pbn value\n", next_index); + vars[next_index].pbn = var_pbn; ret = drm_dp_atomic_find_time_slots(state, params[next_index].port->mgr, params[next_index].port, @@ -1298,8 +1304,11 @@ static int try_disable_dsc(struct drm_atomic_state *state, , dm_mst_get_pbn_divider(dc_link) #endif ); - if (ret < 0) + if (ret < 0) { + DRM_DEBUG_DRIVER("%s:%d MST_DSC index #%d, failed to set pbn to the state, %d\n", + __func__, __LINE__, next_index, ret); return ret; + } } tried[next_index] = true; From be3951c05e96effecaeb58eee81ffe7ea93ce6f5 Mon Sep 17 00:00:00 2001 From: Alvin Lee Date: Mon, 9 Sep 2024 16:24:05 -0400 Subject: [PATCH 1667/1868] drm/amd/display: Wait for all pending cleared before full update [Description] Before every full update we must wait for all pending updates to be cleared - this is particularly important for minimal transitions because if we don't wait for pending cleared, it will be as if there was no minimal transition at all. In OTG we must read 3 different status registers for pending cleared, one specifically for OTG updates, one specifically for OPTC updates, and the last for surface related updates. Reviewed-by: Dillon Varone Signed-off-by: Alvin Lee Signed-off-by: Aurabindo Pillai Tested-by: Daniel Wheeler --- .../drm/amd/display/dc/core/dc_hw_sequencer.c | 9 +++- .../amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 4 +- .../amd/display/dc/hwss/dcn30/dcn30_hwseq.c | 27 +++++++++++ .../amd/display/dc/hwss/dcn30/dcn30_hwseq.h | 2 + .../amd/display/dc/hwss/dcn30/dcn30_init.c | 3 +- .../amd/display/dc/hwss/dcn301/dcn301_init.c | 1 + .../amd/display/dc/hwss/dcn32/dcn32_init.c | 1 + .../amd/display/dc/hwss/dcn401/dcn401_init.c | 1 + .../drm/amd/display/dc/hwss/hw_sequencer.h | 1 + .../amd/display/dc/inc/hw/timing_generator.h | 4 +- .../amd/display/dc/optc/dcn10/dcn10_optc.h | 9 ++++ .../amd/display/dc/optc/dcn20/dcn20_optc.h | 7 ++- .../amd/display/dc/optc/dcn30/dcn30_optc.c | 45 +++++++++++++++++++ .../amd/display/dc/optc/dcn30/dcn30_optc.h | 13 +++++- .../amd/display/dc/optc/dcn301/dcn301_optc.c | 3 ++ .../amd/display/dc/optc/dcn31/dcn31_optc.h | 9 +++- .../amd/display/dc/optc/dcn314/dcn314_optc.h | 9 +++- .../amd/display/dc/optc/dcn32/dcn32_optc.c | 16 ++----- .../amd/display/dc/optc/dcn32/dcn32_optc.h | 7 ++- .../amd/display/dc/optc/dcn35/dcn35_optc.h | 6 ++- .../amd/display/dc/optc/dcn401/dcn401_optc.c | 4 +- .../amd/display/dc/optc/dcn401/dcn401_optc.h | 6 ++- .../dc/resource/dcn32/dcn32_resource.h | 3 +- .../dc/resource/dcn401/dcn401_resource.h | 5 ++- 24 files changed, 161 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c index 7ee2be8f82c46..2cb9253c9bdec 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c @@ -1071,8 +1071,13 @@ void hwss_wait_for_outstanding_hw_updates(struct dc *dc, struct dc_state *dc_con if (!pipe_ctx->stream) continue; - if (pipe_ctx->stream_res.tg->funcs->wait_drr_doublebuffer_pending_clear) - pipe_ctx->stream_res.tg->funcs->wait_drr_doublebuffer_pending_clear(pipe_ctx->stream_res.tg); + /* For full update we must wait for all double buffer updates, not just DRR updates. This + * is particularly important for minimal transitions. Only check for OTG_MASTER pipes, + * as non-OTG Master pipes share the same OTG as + */ + if (resource_is_pipe_type(pipe_ctx, OTG_MASTER) && dc->hwss.wait_for_all_pending_updates) { + dc->hwss.wait_for_all_pending_updates(pipe_ctx); + } hubp = pipe_ctx->plane_res.hubp; if (!hubp) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c index a80c085829320..b383ed8cb4d49 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c @@ -2255,9 +2255,9 @@ void dcn20_post_unlock_program_front_end( struct timing_generator *tg = pipe->stream_res.tg; - if (tg->funcs->get_double_buffer_pending) { + if (tg->funcs->get_optc_double_buffer_pending) { for (j = 0; j < TIMEOUT_FOR_PIPE_ENABLE_US / polling_interval_us - && tg->funcs->get_double_buffer_pending(tg); j++) + && tg->funcs->get_optc_double_buffer_pending(tg); j++) udelay(polling_interval_us); } } diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c index bded33575493b..bf9b5daea2af2 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c @@ -1185,3 +1185,30 @@ void dcn30_prepare_bandwidth(struct dc *dc, if (!dc->clk_mgr->clks.fw_based_mclk_switching) dc_dmub_srv_p_state_delegate(dc, false, context); } + +void dcn30_wait_for_all_pending_updates(const struct pipe_ctx *pipe_ctx) +{ + struct timing_generator *tg = pipe_ctx->stream_res.tg; + bool pending_updates = false; + unsigned int i; + + if (tg && tg->funcs->is_tg_enabled(tg)) { + // Poll for 100ms maximum + for (i = 0; i < 100000; i++) { + pending_updates = false; + if (tg->funcs->get_optc_double_buffer_pending) + pending_updates |= tg->funcs->get_optc_double_buffer_pending(tg); + + if (tg->funcs->get_otg_double_buffer_pending) + pending_updates |= tg->funcs->get_otg_double_buffer_pending(tg); + + if (tg->funcs->get_pipe_update_pending && pipe_ctx->plane_state) + pending_updates |= tg->funcs->get_pipe_update_pending(tg); + + if (!pending_updates) + break; + + udelay(1); + } + } +} diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h index 6a153e7ce910e..4b90b781c4f2d 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.h @@ -96,4 +96,6 @@ void dcn30_set_hubp_blank(const struct dc *dc, void dcn30_prepare_bandwidth(struct dc *dc, struct dc_state *context); +void dcn30_wait_for_all_pending_updates(const struct pipe_ctx *pipe_ctx); + #endif /* __DC_HWSS_DCN30_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c index 2a8dc40d28477..0e8d32e3dbae1 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_init.c @@ -108,7 +108,8 @@ static const struct hw_sequencer_funcs dcn30_funcs = { .set_disp_pattern_generator = dcn30_set_disp_pattern_generator, .get_dcc_en_bits = dcn10_get_dcc_en_bits, .update_visual_confirm_color = dcn10_update_visual_confirm_color, - .is_abm_supported = dcn21_is_abm_supported + .is_abm_supported = dcn21_is_abm_supported, + .wait_for_all_pending_updates = dcn30_wait_for_all_pending_updates, }; static const struct hwseq_private_funcs dcn30_private_funcs = { diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c index 93e49d87a67ce..780ce4c064aa5 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn301/dcn301_init.c @@ -107,6 +107,7 @@ static const struct hw_sequencer_funcs dcn301_funcs = { .optimize_pwr_state = dcn21_optimize_pwr_state, .exit_optimized_pwr_state = dcn21_exit_optimized_pwr_state, .update_visual_confirm_color = dcn10_update_visual_confirm_color, + .wait_for_all_pending_updates = dcn30_wait_for_all_pending_updates, }; static const struct hwseq_private_funcs dcn301_private_funcs = { diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c index 3422b564ae984..8e0946fd5b7fe 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c @@ -121,6 +121,7 @@ static const struct hw_sequencer_funcs dcn32_funcs = { .is_pipe_topology_transition_seamless = dcn32_is_pipe_topology_transition_seamless, .calculate_pix_rate_divider = dcn32_calculate_pix_rate_divider, .program_outstanding_updates = dcn32_program_outstanding_updates, + .wait_for_all_pending_updates = dcn30_wait_for_all_pending_updates, }; static const struct hwseq_private_funcs dcn32_private_funcs = { diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c index a2ca07235c83d..73a632b5ff893 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c @@ -100,6 +100,7 @@ static const struct hw_sequencer_funcs dcn401_funcs = { .fams2_update_config = dcn401_fams2_update_config, .fams2_global_control_lock_fast = dcn401_fams2_global_control_lock_fast, .program_outstanding_updates = dcn401_program_outstanding_updates, + .wait_for_all_pending_updates = dcn30_wait_for_all_pending_updates, }; static const struct hwseq_private_funcs dcn401_private_funcs = { diff --git a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h index ac92056256233..b8c47e4c51c15 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h @@ -462,6 +462,7 @@ struct hw_sequencer_funcs { void (*program_outstanding_updates)(struct dc *dc, struct dc_state *context); void (*setup_hpo_hw_control)(const struct dce_hwseq *hws, bool enable); + void (*wait_for_all_pending_updates)(const struct pipe_ctx *pipe_ctx); }; void color_space_to_black_color( diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h index 3d4c8bd42b492..4e08e80eafe8e 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h @@ -342,7 +342,9 @@ struct timing_generator_funcs { void (*wait_drr_doublebuffer_pending_clear)(struct timing_generator *tg); void (*set_long_vtotal)(struct timing_generator *optc, const struct long_vtotal_params *params); void (*wait_odm_doublebuffer_pending_clear)(struct timing_generator *tg); - bool (*get_double_buffer_pending)(struct timing_generator *tg); + bool (*get_optc_double_buffer_pending)(struct timing_generator *tg); + bool (*get_otg_double_buffer_pending)(struct timing_generator *tg); + bool (*get_pipe_update_pending)(struct timing_generator *tg); }; #endif diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h index b7a57f98553d7..40757f20d73f4 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.h @@ -202,6 +202,7 @@ struct dcn_optc_registers { uint32_t OPTC_CLOCK_CONTROL; uint32_t OPTC_WIDTH_CONTROL2; uint32_t OTG_PSTATE_REGISTER; + uint32_t OTG_PIPE_UPDATE_STATUS; }; #define TG_COMMON_MASK_SH_LIST_DCN(mask_sh)\ @@ -566,6 +567,12 @@ struct dcn_optc_registers { type OTG_H_TIMING_DIV_MODE_DB_UPDATE_PENDING;\ type OPTC_DOUBLE_BUFFER_PENDING;\ +#define TG_REG_FIELD_LIST_DCN2_0(type) \ + type OTG_FLIP_PENDING;\ + type OTG_DC_REG_UPDATE_PENDING;\ + type OTG_CURSOR_UPDATE_PENDING;\ + type OTG_VUPDATE_KEEPOUT_STATUS;\ + #define TG_REG_FIELD_LIST_DCN3_2(type) \ type OTG_H_TIMING_DIV_MODE_MANUAL; @@ -600,6 +607,7 @@ struct dcn_optc_registers { struct dcn_optc_shift { TG_REG_FIELD_LIST(uint8_t) + TG_REG_FIELD_LIST_DCN2_0(uint8_t) TG_REG_FIELD_LIST_DCN3_2(uint8_t) TG_REG_FIELD_LIST_DCN3_5(uint8_t) TG_REG_FIELD_LIST_DCN401(uint8_t) @@ -607,6 +615,7 @@ struct dcn_optc_shift { struct dcn_optc_mask { TG_REG_FIELD_LIST(uint32_t) + TG_REG_FIELD_LIST_DCN2_0(uint32_t) TG_REG_FIELD_LIST_DCN3_2(uint32_t) TG_REG_FIELD_LIST_DCN3_5(uint32_t) TG_REG_FIELD_LIST_DCN401(uint32_t) diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h index 364034b190281..928e110b95fb5 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.h @@ -43,7 +43,8 @@ SRI(OPTC_MEMORY_CONFIG, ODM, inst),\ SR(DWB_SOURCE_SELECT),\ SRI(OTG_MANUAL_FLOW_CONTROL, OTG, inst), \ - SRI(OTG_DRR_CONTROL, OTG, inst) + SRI(OTG_DRR_CONTROL, OTG, inst),\ + SRI(OTG_PIPE_UPDATE_STATUS, OTG, inst) #define TG_COMMON_MASK_SH_LIST_DCN2_0(mask_sh)\ TG_COMMON_MASK_SH_LIST_DCN(mask_sh),\ @@ -53,6 +54,10 @@ SF(OTG0_OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, mask_sh),\ SF(OTG0_OTG_GLOBAL_CONTROL2, DIG_UPDATE_LOCATION, mask_sh),\ SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_RANGE_TIMING_DBUF_UPDATE_MODE, mask_sh),\ + SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_FLIP_PENDING, mask_sh),\ + SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_DC_REG_UPDATE_PENDING, mask_sh),\ + SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_CURSOR_UPDATE_PENDING, mask_sh),\ + SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_VUPDATE_KEEPOUT_STATUS, mask_sh),\ SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_START_X, mask_sh),\ SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_END_X, mask_sh), \ SF(OTG0_OTG_GSL_WINDOW_Y, OTG_GSL_WINDOW_START_Y, mask_sh),\ diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c index abcd03d786684..4c95c09586122 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.c @@ -271,6 +271,48 @@ void optc3_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_c optc1->opp_count = opp_cnt; } +/* OTG status register that indicates OPTC update is pending */ +bool optc3_get_optc_double_buffer_pending(struct timing_generator *optc) +{ + struct optc *optc1 = DCN10TG_FROM_TG(optc); + uint32_t update_pending = 0; + + REG_GET(OPTC_INPUT_GLOBAL_CONTROL, + OPTC_DOUBLE_BUFFER_PENDING, + &update_pending); + + return (update_pending == 1); +} + +/* OTG status register that indicates OTG update is pending */ +bool optc3_get_otg_update_pending(struct timing_generator *optc) +{ + struct optc *optc1 = DCN10TG_FROM_TG(optc); + uint32_t update_pending = 0; + + REG_GET(OTG_DOUBLE_BUFFER_CONTROL, + OTG_UPDATE_PENDING, + &update_pending); + + return (update_pending == 1); +} + +/* OTG status register that indicates surface update is pending */ +bool optc3_get_pipe_update_pending(struct timing_generator *optc) +{ + struct optc *optc1 = DCN10TG_FROM_TG(optc); + uint32_t flip_pending = 0; + uint32_t dc_update_pending = 0; + + REG_GET_2(OTG_PIPE_UPDATE_STATUS, + OTG_FLIP_PENDING, + &flip_pending, + OTG_DC_REG_UPDATE_PENDING, + &dc_update_pending); + + return (flip_pending == 1 || dc_update_pending == 1); +} + /** * optc3_set_timing_double_buffer() - DRR double buffering control * @@ -375,6 +417,9 @@ static struct timing_generator_funcs dcn30_tg_funcs = { .get_hw_timing = optc1_get_hw_timing, .wait_drr_doublebuffer_pending_clear = optc3_wait_drr_doublebuffer_pending_clear, .is_two_pixels_per_container = optc1_is_two_pixels_per_container, + .get_optc_double_buffer_pending = optc3_get_optc_double_buffer_pending, + .get_otg_double_buffer_pending = optc3_get_otg_update_pending, + .get_pipe_update_pending = optc3_get_pipe_update_pending, }; void dcn30_timing_generator_init(struct optc *optc1) diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h index bda974d432ea6..e2303f9eaf13b 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn30/dcn30_optc.h @@ -109,7 +109,8 @@ SRI(OPTC_BYTES_PER_PIXEL, ODM, inst),\ SRI(OPTC_WIDTH_CONTROL, ODM, inst),\ SRI(OPTC_MEMORY_CONFIG, ODM, inst),\ - SR(DWB_SOURCE_SELECT) + SR(DWB_SOURCE_SELECT),\ + SRI(OTG_PIPE_UPDATE_STATUS, OTG, inst) #define DCN30_VTOTAL_REGS_SF(mask_sh) @@ -209,6 +210,7 @@ SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_GATE_DIS, mask_sh),\ SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_OCCURRED_STATUS, mask_sh),\ SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, mask_sh),\ + SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_DOUBLE_BUFFER_PENDING, mask_sh),\ SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\ SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\ SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\ @@ -319,7 +321,11 @@ SF(OTG0_OTG_DRR_V_TOTAL_CHANGE, OTG_DRR_V_TOTAL_CHANGE_LIMIT, mask_sh),\ SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, mask_sh),\ SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_PENDING, mask_sh),\ - SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_MODE, mask_sh) + SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_MODE, mask_sh),\ + SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_FLIP_PENDING, mask_sh),\ + SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_DC_REG_UPDATE_PENDING, mask_sh),\ + SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_CURSOR_UPDATE_PENDING, mask_sh),\ + SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_VUPDATE_KEEPOUT_STATUS, mask_sh),\ void dcn30_timing_generator_init(struct optc *optc1); @@ -356,4 +362,7 @@ void optc3_set_odm_combine(struct timing_generator *optc, int *opp_id, int opp_c void optc3_wait_drr_doublebuffer_pending_clear(struct timing_generator *optc); void optc3_tg_init(struct timing_generator *optc); void optc3_set_vtotal_min_max(struct timing_generator *optc, int vtotal_min, int vtotal_max); +bool optc3_get_optc_double_buffer_pending(struct timing_generator *optc); +bool optc3_get_otg_update_pending(struct timing_generator *optc); +bool optc3_get_pipe_update_pending(struct timing_generator *optc); #endif /* __DC_OPTC_DCN30_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn301/dcn301_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn301/dcn301_optc.c index 1a22ae89fb555..d7a45ef2d01b3 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn301/dcn301_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn301/dcn301_optc.c @@ -169,6 +169,9 @@ static struct timing_generator_funcs dcn30_tg_funcs = { .get_hw_timing = optc1_get_hw_timing, .wait_drr_doublebuffer_pending_clear = optc3_wait_drr_doublebuffer_pending_clear, .is_two_pixels_per_container = optc1_is_two_pixels_per_container, + .get_optc_double_buffer_pending = optc3_get_optc_double_buffer_pending, + .get_otg_double_buffer_pending = optc3_get_otg_update_pending, + .get_pipe_update_pending = optc3_get_pipe_update_pending, }; void dcn301_timing_generator_init(struct optc *optc1) diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h index 30b81a448ce2d..fbbe86d00c2e3 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn31/dcn31_optc.h @@ -99,7 +99,8 @@ SRI(OPTC_MEMORY_CONFIG, ODM, inst),\ SRI(OTG_CRC_CNTL2, OTG, inst),\ SR(DWB_SOURCE_SELECT),\ - SRI(OTG_DRR_CONTROL, OTG, inst) + SRI(OTG_DRR_CONTROL, OTG, inst),\ + SRI(OTG_PIPE_UPDATE_STATUS, OTG, inst) #define OPTC_COMMON_MASK_SH_LIST_DCN3_1(mask_sh)\ SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\ @@ -254,7 +255,11 @@ SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_COMBINE_MODE, mask_sh),\ SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_STREAM_SPLIT_MODE, mask_sh),\ SF(OTG0_OTG_CRC_CNTL2, OTG_CRC_DATA_FORMAT, mask_sh),\ - SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh) + SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh),\ + SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_FLIP_PENDING, mask_sh),\ + SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_DC_REG_UPDATE_PENDING, mask_sh),\ + SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_CURSOR_UPDATE_PENDING, mask_sh),\ + SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_VUPDATE_KEEPOUT_STATUS, mask_sh),\ void dcn31_timing_generator_init(struct optc *optc1); diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h index 99c098e76116f..0ff72b97b465c 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn314/dcn314_optc.h @@ -98,7 +98,8 @@ SRI(OPTC_BYTES_PER_PIXEL, ODM, inst),\ SRI(OPTC_WIDTH_CONTROL, ODM, inst),\ SRI(OPTC_MEMORY_CONFIG, ODM, inst),\ - SRI(OTG_DRR_CONTROL, OTG, inst) + SRI(OTG_DRR_CONTROL, OTG, inst),\ + SRI(OTG_PIPE_UPDATE_STATUS, OTG, inst) #define OPTC_COMMON_MASK_SH_LIST_DCN3_14(mask_sh)\ SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\ @@ -248,7 +249,11 @@ SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, mask_sh),\ SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE_MANUAL, mask_sh),\ SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_MODE, mask_sh),\ - SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh) + SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh),\ + SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_FLIP_PENDING, mask_sh),\ + SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_DC_REG_UPDATE_PENDING, mask_sh),\ + SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_CURSOR_UPDATE_PENDING, mask_sh),\ + SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_VUPDATE_KEEPOUT_STATUS, mask_sh),\ void dcn314_timing_generator_init(struct optc *optc1); diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c index 00094f0e84706..c217f653b3c81 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c @@ -297,18 +297,6 @@ static void optc32_set_drr( optc32_setup_manual_trigger(optc); } -bool optc32_get_double_buffer_pending(struct timing_generator *optc) -{ - struct optc *optc1 = DCN10TG_FROM_TG(optc); - uint32_t update_pending = 0; - - REG_GET(OPTC_INPUT_GLOBAL_CONTROL, - OPTC_DOUBLE_BUFFER_PENDING, - &update_pending); - - return (update_pending == 1); -} - static struct timing_generator_funcs dcn32_tg_funcs = { .validate_timing = optc1_validate_timing, .program_timing = optc1_program_timing, @@ -373,7 +361,9 @@ static struct timing_generator_funcs dcn32_tg_funcs = { .setup_manual_trigger = optc2_setup_manual_trigger, .get_hw_timing = optc1_get_hw_timing, .is_two_pixels_per_container = optc1_is_two_pixels_per_container, - .get_double_buffer_pending = optc32_get_double_buffer_pending, + .get_optc_double_buffer_pending = optc3_get_optc_double_buffer_pending, + .get_otg_double_buffer_pending = optc3_get_otg_update_pending, + .get_pipe_update_pending = optc3_get_pipe_update_pending, }; void dcn32_timing_generator_init(struct optc *optc1) diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.h index 665d7c52f67cd..0b0964a9da748 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.h +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.h @@ -177,7 +177,11 @@ SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE, mask_sh),\ SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_MODE_MANUAL, mask_sh),\ SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_DRR_TIMING_DBUF_UPDATE_MODE, mask_sh),\ - SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh) + SF(OTG0_OTG_DRR_CONTROL, OTG_V_TOTAL_LAST_USED_BY_DRR, mask_sh),\ + SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_FLIP_PENDING, mask_sh),\ + SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_DC_REG_UPDATE_PENDING, mask_sh),\ + SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_CURSOR_UPDATE_PENDING, mask_sh),\ + SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_VUPDATE_KEEPOUT_STATUS, mask_sh) void dcn32_timing_generator_init(struct optc *optc1); void optc32_set_h_timing_div_manual_mode(struct timing_generator *optc, bool manual_mode); @@ -185,6 +189,5 @@ void optc32_get_odm_combine_segments(struct timing_generator *tg, int *odm_combi void optc32_set_odm_bypass(struct timing_generator *optc, const struct dc_crtc_timing *dc_crtc_timing); void optc32_wait_odm_doublebuffer_pending_clear(struct timing_generator *tg); -bool optc32_get_double_buffer_pending(struct timing_generator *optc); #endif /* __DC_OPTC_DCN32_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.h index d077e2392379c..be749ab41dce7 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.h +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.h @@ -67,7 +67,11 @@ SF(OTG0_OTG_CRC1_WINDOWB_Y_CONTROL_READBACK, OTG_CRC1_WINDOWB_Y_END_READBACK, mask_sh),\ SF(OPTC_CLOCK_CONTROL, OPTC_FGCG_REP_DIS, mask_sh),\ SF(OTG0_OTG_V_COUNT_STOP_CONTROL, OTG_V_COUNT_STOP, mask_sh),\ - SF(OTG0_OTG_V_COUNT_STOP_CONTROL2, OTG_V_COUNT_STOP_TIMER, mask_sh) + SF(OTG0_OTG_V_COUNT_STOP_CONTROL2, OTG_V_COUNT_STOP_TIMER, mask_sh),\ + SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_FLIP_PENDING, mask_sh),\ + SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_DC_REG_UPDATE_PENDING, mask_sh),\ + SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_CURSOR_UPDATE_PENDING, mask_sh),\ + SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_VUPDATE_KEEPOUT_STATUS, mask_sh) void dcn35_timing_generator_init(struct optc *optc1); diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c index a5d6a7dca554c..db670fc172644 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.c @@ -493,7 +493,9 @@ static struct timing_generator_funcs dcn401_tg_funcs = { .setup_manual_trigger = optc2_setup_manual_trigger, .get_hw_timing = optc1_get_hw_timing, .is_two_pixels_per_container = optc1_is_two_pixels_per_container, - .get_double_buffer_pending = optc32_get_double_buffer_pending, + .get_optc_double_buffer_pending = optc3_get_optc_double_buffer_pending, + .get_otg_double_buffer_pending = optc3_get_otg_update_pending, + .get_pipe_update_pending = optc3_get_pipe_update_pending, }; void dcn401_timing_generator_init(struct optc *optc1) diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.h index bb13a645802d0..1be89571986ff 100644 --- a/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.h +++ b/drivers/gpu/drm/amd/display/dc/optc/dcn401/dcn401_optc.h @@ -159,7 +159,11 @@ SF(OTG0_OTG_PSTATE_REGISTER, OTG_PSTATE_KEEPOUT_START, mask_sh),\ SF(OTG0_OTG_PSTATE_REGISTER, OTG_PSTATE_EXTEND, mask_sh),\ SF(OTG0_OTG_PSTATE_REGISTER, OTG_UNBLANK, mask_sh),\ - SF(OTG0_OTG_PSTATE_REGISTER, OTG_PSTATE_ALLOW_WIDTH_MIN, mask_sh) + SF(OTG0_OTG_PSTATE_REGISTER, OTG_PSTATE_ALLOW_WIDTH_MIN, mask_sh),\ + SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_FLIP_PENDING, mask_sh),\ + SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_DC_REG_UPDATE_PENDING, mask_sh),\ + SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_CURSOR_UPDATE_PENDING, mask_sh),\ + SF(OTG0_OTG_PIPE_UPDATE_STATUS, OTG_VUPDATE_KEEPOUT_STATUS, mask_sh) void dcn401_timing_generator_init(struct optc *optc1); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h index 7901792afb7b3..86c6e5e8c42eb 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.h @@ -1054,7 +1054,8 @@ unsigned int dcn32_calculate_mall_ways_from_bytes(const struct dc *dc, unsigned SRI_ARR(OPTC_BYTES_PER_PIXEL, ODM, inst), \ SRI_ARR(OPTC_WIDTH_CONTROL, ODM, inst), \ SRI_ARR(OPTC_MEMORY_CONFIG, ODM, inst), \ - SRI_ARR(OTG_DRR_CONTROL, OTG, inst) + SRI_ARR(OTG_DRR_CONTROL, OTG, inst), \ + SRI_ARR(OTG_PIPE_UPDATE_STATUS, OTG, inst) /* HUBP */ diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h index 514d1ce20df9e..bdafa7496ceae 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h @@ -536,8 +536,9 @@ void dcn401_prepare_mcache_programming(struct dc *dc, struct dc_state *context); SRI_ARR(OPTC_WIDTH_CONTROL, ODM, inst), \ SRI_ARR(OPTC_WIDTH_CONTROL2, ODM, inst), \ SRI_ARR(OPTC_MEMORY_CONFIG, ODM, inst), \ - SRI_ARR(OTG_DRR_CONTROL, OTG, inst), \ - SRI_ARR(OTG_PSTATE_REGISTER, OTG, inst) + SRI_ARR(OTG_DRR_CONTROL, OTG, inst), \ + SRI_ARR(OTG_PSTATE_REGISTER, OTG, inst), \ + SRI_ARR(OTG_PIPE_UPDATE_STATUS, OTG, inst) /* HUBBUB */ #define HUBBUB_REG_LIST_DCN4_01_RI(id) \ From 1ee7d436c9d1a590df4ec042d55e40112fd68a3d Mon Sep 17 00:00:00 2001 From: Zhongwei Date: Tue, 10 Sep 2024 13:28:34 +0800 Subject: [PATCH 1668/1868] drm/amd/display: Monitor patch to call blank_stream() before otg off [Why] Turning off OTG before DIG is on and backlight is on, might cause: DIG FIFO underflow. EDP output unexpected video data. That might violate EDP spec. EDP spec requires black light should be off before validate video data is turned off. Currently garbage issue only occurs in one type of EDP to MIPI converter. [How] Add monitor patch to call blank_stream() before disable_crtc(). That will be no impact for current sequence. If there are more types of EDP panels meeting this issue later, we might remove this monitor patch and fix the current sequence. Reviewed-by: Nicholas Kazlauskas Signed-off-by: Zhongwei Signed-off-by: Aurabindo Pillai Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/dc_types.h | 1 + drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h index fd6dca7357143..2bbafd1cdce47 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_types.h @@ -178,6 +178,7 @@ struct dc_panel_patch { unsigned int skip_avmute; unsigned int mst_start_top_delay; unsigned int remove_sink_ext_caps; + uint8_t blankstream_before_otg_off; }; struct dc_edid_caps { diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c index 3d4b31bd99469..bfc78a42bc2a7 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c @@ -517,6 +517,11 @@ static void dcn31_reset_back_end_for_pipe( dc->hwss.set_abm_immediate_disable(pipe_ctx); + if ((!pipe_ctx->stream->dpms_off || pipe_ctx->stream->link->link_status.link_active) + && pipe_ctx->stream->sink && pipe_ctx->stream->sink->edid_caps.panel_patch.blankstream_before_otg_off) { + dc->hwss.blank_stream(pipe_ctx); + } + pipe_ctx->stream_res.tg->funcs->set_dsc_config( pipe_ctx->stream_res.tg, OPTC_DSC_DISABLED, 0, 0); From baafb5989a6d8718b281ef9d16df8116036c214e Mon Sep 17 00:00:00 2001 From: Fangzhi Zuo Date: Wed, 4 Sep 2024 16:56:45 -0400 Subject: [PATCH 1669/1868] drm/amd/display: Fix incorrect DSC recompute trigger A stream without dsc_aux should not be eliminated from the dsc determination. Whether it needs a dsc recompute depends on whether its mode has changed or not. Eliminating such a no-dsc stream from the dsc determination policy will end up with inconsistencies in the new dc_state when compared to the current dc_state, triggering a dsc recompute that should not have happened. Reviewed-by: Rodrigo Siqueira Signed-off-by: Fangzhi Zuo Signed-off-by: Aurabindo Pillai Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index 1faa7612427bb..f4214dc372da3 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -1535,7 +1535,7 @@ static bool is_dsc_need_re_compute( continue; aconnector = (struct amdgpu_dm_connector *) stream->dm_stream_context; - if (!aconnector || !aconnector->dsc_aux) + if (!aconnector) continue; stream_on_link[new_stream_on_link_num] = aconnector; From 3621611bd857e117336e3e8b56d0fcb7c568c008 Mon Sep 17 00:00:00 2001 From: Sung Lee Date: Mon, 9 Sep 2024 16:12:55 -0400 Subject: [PATCH 1670/1868] drm/amd/display: Clean up triple buffer enablement code [WHY] Triple buffer enablement currently does not work properly [HOW] Allow triple buffer enablement to happen properly on fast updates Reviewed-by: Aric Cyr Signed-off-by: Sung Lee Signed-off-by: Aurabindo Pillai Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/core/dc.c | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 804b3ed69f053..3dc4a68eaa320 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -3678,13 +3678,14 @@ static void commit_planes_for_stream_fast(struct dc *dc, if (!pipe_ctx->plane_state) continue; - if (should_update_pipe_for_plane(context, pipe_ctx, plane_state)) + if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state)) continue; + pipe_ctx->plane_state->triplebuffer_flips = false; if (update_type == UPDATE_TYPE_FAST && - dc->hwss.program_triplebuffer != NULL && - !pipe_ctx->plane_state->flip_immediate && dc->debug.enable_tri_buf) { - /*triple buffer for VUpdate only*/ + dc->hwss.program_triplebuffer != NULL && + !pipe_ctx->plane_state->flip_immediate && dc->debug.enable_tri_buf) { + /*triple buffer for VUpdate only*/ pipe_ctx->plane_state->triplebuffer_flips = true; } } @@ -3921,19 +3922,20 @@ static void commit_planes_for_stream(struct dc *dc, struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; if (!pipe_ctx->plane_state) continue; - if (should_update_pipe_for_plane(context, pipe_ctx, plane_state)) + if (!should_update_pipe_for_plane(context, pipe_ctx, plane_state)) continue; pipe_ctx->plane_state->triplebuffer_flips = false; if (update_type == UPDATE_TYPE_FAST && - dc->hwss.program_triplebuffer != NULL && - !pipe_ctx->plane_state->flip_immediate && dc->debug.enable_tri_buf) { - /*triple buffer for VUpdate only*/ - pipe_ctx->plane_state->triplebuffer_flips = true; + dc->hwss.program_triplebuffer != NULL && + !pipe_ctx->plane_state->flip_immediate && dc->debug.enable_tri_buf) { + /*triple buffer for VUpdate only*/ + pipe_ctx->plane_state->triplebuffer_flips = true; } } if (update_type == UPDATE_TYPE_FULL) { /* force vsync flip when reconfiguring pipes to prevent underflow */ plane_state->flip_immediate = false; + plane_state->triplebuffer_flips = false; } } @@ -3954,7 +3956,6 @@ static void commit_planes_for_stream(struct dc *dc, continue; ASSERT(!pipe_ctx->plane_state->triplebuffer_flips); - if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) { /*turn off triple buffer for full update*/ dc->hwss.program_triplebuffer( @@ -4029,7 +4030,7 @@ static void commit_planes_for_stream(struct dc *dc, /*program triple buffer after lock based on flip type*/ if (dc->hwss.program_triplebuffer != NULL && dc->debug.enable_tri_buf) { - /*only enable triplebuffer for fast_update*/ + /*only enable triplebuffer for fast_update*/ dc->hwss.program_triplebuffer( dc, pipe_ctx, pipe_ctx->plane_state->triplebuffer_flips); } From 0f9e47291896c1db25bb31f4c5df6a8967655289 Mon Sep 17 00:00:00 2001 From: Shunlu Zhang Date: Tue, 3 Sep 2024 01:08:01 -0400 Subject: [PATCH 1671/1868] drm/amd/display: Change dc_surface_update cm2_params to const [WHY] cm2_params is used to set update_flags. It's value is not intended to be modified. [WHAT] Change the declaration of cm2_params to be a constant variable Reviewed-by: Tao Huang Reviewed-by: Ariel Bernstein Signed-off-by: Shunlu Zhang Signed-off-by: Aurabindo Pillai Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index e39b56bf028d1..a34ca77483493 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -1516,7 +1516,7 @@ struct dc_surface_update { * change cm2_params.component_settings: Full update * change cm2_params.cm2_luts: Fast update */ - struct dc_cm2_parameters *cm2_params; + const struct dc_cm2_parameters *cm2_params; const struct dc_csc_transform *cursor_csc_color_matrix; unsigned int sdr_white_level_nits; }; From 3f896d00e46b2cdceb72d3fa410b95ea457b0e7d Mon Sep 17 00:00:00 2001 From: Austin Zheng Date: Tue, 10 Sep 2024 13:46:50 -0400 Subject: [PATCH 1672/1868] drm/amd/display: Set Pipe Unlock Order Outside of HWSEQ [Why] Current pipe unlock order set within dcn401_interdependent_update_lock. Separate the logic from the functionality to allow for unit testing and make it easier to debug. [How] Add a flag to indicate if a pipe unlock order should be set. Create function to determine unlock order. Indicate which pipes should be unlocked first using array stored in dc scratch memory. Pipes indicated in array can be unlocked in any order. Reviewed-by: Alvin Lee Signed-off-by: Austin Zheng Signed-off-by: Aurabindo Pillai Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/core/dc.c | 42 +++++++++++++++++++ drivers/gpu/drm/amd/display/dc/dc.h | 2 + .../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 32 ++++++-------- .../dc/resource/dcn401/dcn401_resource.c | 1 + 4 files changed, 57 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 3dc4a68eaa320..2c5233ff90f62 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1876,6 +1876,41 @@ void dc_z10_save_init(struct dc *dc) dc->hwss.z10_save_init(dc); } +/* Set a pipe unlock order based on the change in DET allocation and stores it in dc scratch memory + * Prevents over allocation of DET during unlock process + * e.g. 2 pipe config with different streams with a max of 20 DET segments + * Before: After: + * - Pipe0: 10 DET segments - Pipe0: 12 DET segments + * - Pipe1: 10 DET segments - Pipe1: 8 DET segments + * If Pipe0 gets updated first, 22 DET segments will be allocated + */ +static void determine_pipe_unlock_order(struct dc *dc, struct dc_state *context) +{ + unsigned int i = 0; + struct pipe_ctx *pipe = NULL; + struct timing_generator *tg = NULL; + + if (!dc->config.set_pipe_unlock_order) + return; + + memset(dc->scratch.pipes_to_unlock_first, 0, sizeof(dc->scratch.pipes_to_unlock_first)); + for (i = 0; i < dc->res_pool->pipe_count; i++) { + pipe = &context->res_ctx.pipe_ctx[i]; + tg = pipe->stream_res.tg; + + if (!resource_is_pipe_type(pipe, OTG_MASTER) || + !tg->funcs->is_tg_enabled(tg) || + dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM) { + continue; + } + + if (resource_calculate_det_for_stream(context, pipe) < + resource_calculate_det_for_stream(dc->current_state, &dc->current_state->res_ctx.pipe_ctx[i])) { + dc->scratch.pipes_to_unlock_first[i] = true; + } + } +} + /** * dc_commit_state_no_check - Apply context to the hardware * @@ -1974,6 +2009,7 @@ static enum dc_status dc_commit_state_no_check(struct dc *dc, struct dc_state *c context->streams[i]->update_flags.bits.dsc_changed = prev_dsc_changed; } + determine_pipe_unlock_order(dc, context); /* Program all planes within new context*/ if (dc->res_pool->funcs->prepare_mcache_programming) dc->res_pool->funcs->prepare_mcache_programming(dc, context); @@ -3626,6 +3662,10 @@ static void commit_planes_for_stream_fast(struct dc *dc, struct pipe_ctx *top_pipe_to_program = NULL; struct dc_stream_status *stream_status = NULL; bool should_offload_fams2_flip = false; + bool should_lock_all_pipes = (update_type != UPDATE_TYPE_FAST); + + if (should_lock_all_pipes) + determine_pipe_unlock_order(dc, context); if (dc->debug.fams2_config.bits.enable && dc->debug.fams2_config.bits.enable_offload_flip && @@ -3744,6 +3784,8 @@ static void commit_planes_for_stream(struct dc *dc, bool subvp_curr_use = false; uint8_t current_stream_mask = 0; + if (should_lock_all_pipes) + determine_pipe_unlock_order(dc, context); // Once we apply the new subvp context to hardware it won't be in the // dc->current_state anymore, so we have to cache it before we apply // the new SubVP context diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index a34ca77483493..3321f44c9fd8f 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -463,6 +463,7 @@ struct dc_config { unsigned int enable_fpo_flicker_detection; bool disable_hbr_audio_dp2; bool consolidated_dpia_dp_lt; + bool set_pipe_unlock_order; }; enum visual_confirm { @@ -1464,6 +1465,7 @@ struct dc { struct dc_scratch_space current_state; struct dc_scratch_space new_state; struct dc_stream_state temp_stream; // Used so we don't need to allocate stream on the stack + bool pipes_to_unlock_first[MAX_PIPES]; /* Any of the pipes indicated here should be unlocked first */ } scratch; struct dml2_configuration_options dml2_options; diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c index 0b743669f23b4..29fcb4ed66464 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c @@ -1705,7 +1705,6 @@ void dcn401_interdependent_update_lock(struct dc *dc, unsigned int i = 0; struct pipe_ctx *pipe = NULL; struct timing_generator *tg = NULL; - bool pipe_unlocked[MAX_PIPES] = {0}; if (lock) { for (i = 0; i < dc->res_pool->pipe_count; i++) { @@ -1719,43 +1718,36 @@ void dcn401_interdependent_update_lock(struct dc *dc, dc->hwss.pipe_control_lock(dc, pipe, true); } } else { - /* Unlock pipes based on the change in DET allocation instead of pipe index - * Prevents over allocation of DET during unlock process - * e.g. 2 pipe config with different streams with a max of 20 DET segments - * Before: After: - * - Pipe0: 10 DET segments - Pipe0: 12 DET segments - * - Pipe1: 10 DET segments - Pipe1: 8 DET segments - * If Pipe0 gets updated first, 22 DET segments will be allocated - */ + /* Need to free DET being used first and have pipe update, then unlock the remaining pipes*/ for (i = 0; i < dc->res_pool->pipe_count; i++) { pipe = &context->res_ctx.pipe_ctx[i]; tg = pipe->stream_res.tg; - int current_pipe_idx = i; if (!resource_is_pipe_type(pipe, OTG_MASTER) || !tg->funcs->is_tg_enabled(tg) || dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM) { - pipe_unlocked[i] = true; continue; } - // If the same stream exists in old context, ensure the OTG_MASTER pipes for the same stream get compared - struct pipe_ctx *old_otg_master = resource_get_otg_master_for_stream(&dc->current_state->res_ctx, pipe->stream); - - if (old_otg_master) - current_pipe_idx = old_otg_master->pipe_idx; - if (resource_calculate_det_for_stream(context, pipe) < - resource_calculate_det_for_stream(dc->current_state, &dc->current_state->res_ctx.pipe_ctx[current_pipe_idx])) { + if (dc->scratch.pipes_to_unlock_first[i]) { dc->hwss.pipe_control_lock(dc, pipe, false); - pipe_unlocked[i] = true; dcn401_wait_for_det_buffer_update(dc, context, pipe); } } + /* Unlocking the rest of the pipes */ for (i = 0; i < dc->res_pool->pipe_count; i++) { - if (pipe_unlocked[i]) + if (dc->scratch.pipes_to_unlock_first[i]) continue; + pipe = &context->res_ctx.pipe_ctx[i]; + tg = pipe->stream_res.tg; + if (!resource_is_pipe_type(pipe, OTG_MASTER) || + !tg->funcs->is_tg_enabled(tg) || + dc_state_get_pipe_subvp_type(context, pipe) == SUBVP_PHANTOM) { + continue; + } + dc->hwss.pipe_control_lock(dc, pipe, false); } } diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c index 9d56fbdcd06af..f2653a86d3e7d 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c @@ -1867,6 +1867,7 @@ static bool dcn401_resource_construct( dc->config.prefer_easf = true; dc->config.dc_mode_clk_limit_support = true; dc->config.enable_windowed_mpo_odm = true; + dc->config.set_pipe_unlock_order = true; /* Need to ensure DET gets freed before allocating */ /* read VBIOS LTTPR caps */ { if (ctx->dc_bios->funcs->get_lttpr_caps) { From 1dede8e6057c2bfe13020e2689ed3ddc9cb80550 Mon Sep 17 00:00:00 2001 From: Michael Strauss Date: Tue, 3 Sep 2024 16:23:11 -0400 Subject: [PATCH 1673/1868] drm/amd/display: Block UHBR Based On USB-C PD Cable ID [WHY] Currently the absence of UHBR cable ID caps from USB-C PD does not block UHBR rates. In situations where DPCD reports valid UHBR capability but USB-C PD does not, such as using a USB-C to DP1.4 dongle connected to a native DP2.1 cable, link loss and lightup failures can be seen as a result. Additionally, in edge cases where a platform supports cable ID but DMUB doesn't correctly return cable ID caps, driver currently also allows UHBR. [HOW] Block UHBR rates over DP alt mode if cable id indicates no UHBR support. Additionally, block UHBR rates if a cable ID supported platform receives no reply from a DMUB cable id query. Reviewed-by: Wenjing Liu Reviewed-by: Ovidiu Bunea Signed-off-by: Michael Strauss Signed-off-by: Aurabindo Pillai Tested-by: Daniel Wheeler --- .../dc/link/protocols/link_dp_capability.c | 22 ++++++++++++++----- 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c index 5041a2124c397..571825e29c7b2 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c @@ -1410,7 +1410,8 @@ static bool get_usbc_cable_id(struct dc_link *link, union dp_cable_id *cable_id) if (!link->ctx->dmub_srv || link->ep_type != DISPLAY_ENDPOINT_PHY || - link->link_enc->features.flags.bits.DP_IS_USB_C == 0) + link->link_enc->features.flags.bits.DP_IS_USB_C == 0 || + link->link_enc->features.flags.bits.IS_DP2_CAPABLE == 0) return false; memset(&cmd, 0, sizeof(cmd)); @@ -1423,7 +1424,9 @@ static bool get_usbc_cable_id(struct dc_link *link, union dp_cable_id *cable_id) cable_id->raw = cmd.cable_id.data.output_raw; DC_LOG_DC("usbc_cable_id = %d.\n", cable_id->raw); } - return cmd.cable_id.header.ret_status == 1; + + ASSERT(cmd.cable_id.header.ret_status); + return true; } static void retrieve_cable_id(struct dc_link *link) @@ -2104,6 +2107,8 @@ struct dc_link_settings dp_get_max_link_cap(struct dc_link *link) /* get max link encoder capability */ if (link_enc) link_enc->funcs->get_max_link_cap(link_enc, &max_link_cap); + else + return max_link_cap; /* Lower link settings based on sink's link cap */ if (link->reported_link_cap.lane_count < max_link_cap.lane_count) @@ -2137,10 +2142,15 @@ struct dc_link_settings dp_get_max_link_cap(struct dc_link *link) */ cable_max_link_rate = get_cable_max_link_rate(link); - if (!link->dc->debug.ignore_cable_id && - cable_max_link_rate != LINK_RATE_UNKNOWN) { - if (cable_max_link_rate < max_link_cap.link_rate) - max_link_cap.link_rate = cable_max_link_rate; + if (!link->dc->debug.ignore_cable_id) { + if (cable_max_link_rate != LINK_RATE_UNKNOWN) + // cable max link rate known + max_link_cap.link_rate = MIN(max_link_cap.link_rate, cable_max_link_rate); + else if (link_enc->funcs->is_in_alt_mode && link_enc->funcs->is_in_alt_mode(link_enc)) + // cable max link rate ambiguous, DP alt mode, limit to HBR3 + max_link_cap.link_rate = MIN(max_link_cap.link_rate, LINK_RATE_HIGH3); + //else {} + // cable max link rate ambiguous, DP, do nothing if (!link->dpcd_caps.cable_id.bits.UHBR13_5_CAPABILITY && link->dpcd_caps.cable_id.bits.CABLE_TYPE >= 2) From 9015c46ff04f80efa280bedc997a472639cce989 Mon Sep 17 00:00:00 2001 From: Charlene Liu Date: Wed, 11 Sep 2024 19:45:09 -0400 Subject: [PATCH 1674/1868] drm/amd/display: avoid set dispclk to 0 [why] set dispclk to 0 cause stability issue. Cc: Mario Limonciello Cc: Alex Deucher Cc: stable@vger.kernel.org Reviewed-by: Nicholas Kazlauskas Signed-off-by: Charlene Liu Signed-off-by: Aurabindo Pillai Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c index da9101b83e8c1..70abd32ce2ad1 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c @@ -766,6 +766,7 @@ static const struct dc_debug_options debug_defaults_drv = { .disable_dmub_reallow_idle = false, .static_screen_wait_frames = 2, .notify_dpia_hr_bw = true, + .min_disp_clk_khz = 50000, }; static const struct dc_panel_config panel_config_defaults = { From 5d51116be7a66ea5420024856dbc32090e8a87a8 Mon Sep 17 00:00:00 2001 From: Charlene Liu Date: Wed, 11 Sep 2024 20:35:39 -0400 Subject: [PATCH 1675/1868] drm/amd/display: correct register Clock Gater incorrectly disabled [why] The "dpp35_dppclk_control" routine is incorrectly disabling the register clock gater when the DPP is enabled. The "DISPCLK_R_GATE_DISABLE" should never be set to 1 in the normal operating mode. This will disable the clock gater and the DPPCLK register clock branch will always be running. As a consequence, the dynamic power will be higher than expected. Reviewed-by: Alvin Lee Signed-off-by: Charlene Liu Signed-off-by: Aurabindo Pillai Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c index 8473c694bfdc2..9f885a03eec6a 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c @@ -50,13 +50,11 @@ void dpp35_dppclk_control( DPPCLK_RATE_CONTROL, dppclk_div, DPP_CLOCK_ENABLE, 1); else - REG_UPDATE_2(DPP_CONTROL, - DPP_CLOCK_ENABLE, 1, - DISPCLK_R_GATE_DISABLE, 1); + REG_UPDATE(DPP_CONTROL, + DPP_CLOCK_ENABLE, 1); } else - REG_UPDATE_2(DPP_CONTROL, - DPP_CLOCK_ENABLE, 0, - DISPCLK_R_GATE_DISABLE, 0); + REG_UPDATE(DPP_CONTROL, + DPP_CLOCK_ENABLE, 0); } void dpp35_program_bias_and_scale_fcnv( From d61e7b62846f77e6f3e4ab0084122c19f51a2a5a Mon Sep 17 00:00:00 2001 From: Samson Tam Date: Tue, 10 Sep 2024 01:02:16 -0400 Subject: [PATCH 1676/1868] drm/amd/display: fix static analysis warnings [Why & How] Fix static analysis warnings in SPL library Reviewed-by: Alvin Lee Signed-off-by: Samson Tam Signed-off-by: Aurabindo Pillai Tested-by: Daniel Wheeler --- .../gpu/drm/amd/display/dc/spl/dc_spl_types.h | 4 +-- .../gpu/drm/amd/display/dc/spl/spl_debug.h | 33 +++++++++++-------- .../drm/amd/display/dc/spl/spl_fixpt31_32.c | 32 +++++++++--------- .../drm/amd/display/dc/spl/spl_fixpt31_32.h | 17 ++++------ .../gpu/drm/amd/display/dc/spl/spl_os_types.h | 3 +- 5 files changed, 45 insertions(+), 44 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/spl/dc_spl_types.h b/drivers/gpu/drm/amd/display/dc/spl/dc_spl_types.h index 2a74ff5fdfdbc..48e4217555f84 100644 --- a/drivers/gpu/drm/amd/display/dc/spl/dc_spl_types.h +++ b/drivers/gpu/drm/amd/display/dc/spl/dc_spl_types.h @@ -5,10 +5,8 @@ #ifndef __DC_SPL_TYPES_H__ #define __DC_SPL_TYPES_H__ +#include "spl_debug.h" #include "spl_os_types.h" // swap -#ifndef SPL_ASSERT -#define SPL_ASSERT(_bool) ((void *)0) -#endif #include "spl_fixpt31_32.h" // fixed31_32 and related functions #include "spl_custom_float.h" // custom float and related functions diff --git a/drivers/gpu/drm/amd/display/dc/spl/spl_debug.h b/drivers/gpu/drm/amd/display/dc/spl/spl_debug.h index 5696dafd0894d..a6f6132df2416 100644 --- a/drivers/gpu/drm/amd/display/dc/spl/spl_debug.h +++ b/drivers/gpu/drm/amd/display/dc/spl/spl_debug.h @@ -5,21 +5,26 @@ #ifndef SPL_DEBUG_H #define SPL_DEBUG_H -#ifdef SPL_ASSERT -#undef SPL_ASSERT -#endif -#define SPL_ASSERT(b) +#if defined(CONFIG_HAVE_KGDB) || defined(CONFIG_KGDB) +#define SPL_ASSERT_CRITICAL(expr) do { \ + if (WARN_ON(!(expr))) { \ + kgdb_breakpoint(); \ + } \ +} while (0) +#else +#define SPL_ASSERT_CRITICAL(expr) do { \ + if (WARN_ON(!(expr))) { \ + ; \ + } \ +} while (0) +#endif /* CONFIG_HAVE_KGDB || CONFIG_KGDB */ -#define SPL_ASSERT_CRITICAL(expr) do {if (expr)/* Do nothing */; } while (0) +#if defined(CONFIG_DEBUG_KERNEL_DC) +#define SPL_ASSERT(expr) SPL_ASSERT_CRITICAL(expr) +#else +#define SPL_ASSERT(expr) WARN_ON(!(expr)) +#endif /* CONFIG_DEBUG_KERNEL_DC */ -#ifdef SPL_DALMSG -#undef SPL_DALMSG -#endif -#define SPL_DALMSG(b) - -#ifdef SPL_DAL_ASSERT_MSG -#undef SPL_DAL_ASSERT_MSG -#endif -#define SPL_DAL_ASSERT_MSG(b, m) +#define SPL_BREAK_TO_DEBUGGER() SPL_ASSERT(0) #endif // SPL_DEBUG_H diff --git a/drivers/gpu/drm/amd/display/dc/spl/spl_fixpt31_32.c b/drivers/gpu/drm/amd/display/dc/spl/spl_fixpt31_32.c index a95565df5487c..5fd79d9c67e20 100644 --- a/drivers/gpu/drm/amd/display/dc/spl/spl_fixpt31_32.c +++ b/drivers/gpu/drm/amd/display/dc/spl/spl_fixpt31_32.c @@ -29,7 +29,7 @@ static inline unsigned long long complete_integer_division_u64( { unsigned long long result; - ASSERT(divisor); + SPL_ASSERT(divisor); result = spl_div64_u64_rem(dividend, divisor, remainder); @@ -63,7 +63,7 @@ struct spl_fixed31_32 spl_fixpt_from_fraction(long long numerator, long long den unsigned long long res_value = complete_integer_division_u64( arg1_value, arg2_value, &remainder); - ASSERT(res_value <= LONG_MAX); + SPL_ASSERT(res_value <= (unsigned long long)LONG_MAX); /* determine fractional part */ { @@ -85,7 +85,7 @@ struct spl_fixed31_32 spl_fixpt_from_fraction(long long numerator, long long den { unsigned long long summand = (remainder << 1) >= arg2_value; - ASSERT(res_value <= LLONG_MAX - summand); + SPL_ASSERT(res_value <= (unsigned long long)LLONG_MAX - summand); res_value += summand; } @@ -118,19 +118,19 @@ struct spl_fixed31_32 spl_fixpt_mul(struct spl_fixed31_32 arg1, struct spl_fixed res.value = arg1_int * arg2_int; - ASSERT(res.value <= (long long)LONG_MAX); + SPL_ASSERT(res.value <= (long long)LONG_MAX); res.value <<= FIXED31_32_BITS_PER_FRACTIONAL_PART; tmp = arg1_int * arg2_fra; - ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value)); + SPL_ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value)); res.value += tmp; tmp = arg2_int * arg1_fra; - ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value)); + SPL_ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value)); res.value += tmp; @@ -139,7 +139,7 @@ struct spl_fixed31_32 spl_fixpt_mul(struct spl_fixed31_32 arg1, struct spl_fixed tmp = (tmp >> FIXED31_32_BITS_PER_FRACTIONAL_PART) + (tmp >= (unsigned long long)spl_fixpt_half.value); - ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value)); + SPL_ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value)); res.value += tmp; @@ -163,17 +163,17 @@ struct spl_fixed31_32 spl_fixpt_sqr(struct spl_fixed31_32 arg) res.value = arg_int * arg_int; - ASSERT(res.value <= (long long)LONG_MAX); + SPL_ASSERT(res.value <= (long long)LONG_MAX); res.value <<= FIXED31_32_BITS_PER_FRACTIONAL_PART; tmp = arg_int * arg_fra; - ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value)); + SPL_ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value)); res.value += tmp; - ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value)); + SPL_ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value)); res.value += tmp; @@ -182,7 +182,7 @@ struct spl_fixed31_32 spl_fixpt_sqr(struct spl_fixed31_32 arg) tmp = (tmp >> FIXED31_32_BITS_PER_FRACTIONAL_PART) + (tmp >= (unsigned long long)spl_fixpt_half.value); - ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value)); + SPL_ASSERT(tmp <= (unsigned long long)(LLONG_MAX - res.value)); res.value += tmp; @@ -196,7 +196,7 @@ struct spl_fixed31_32 spl_fixpt_recip(struct spl_fixed31_32 arg) * Good idea to use Newton's method */ - ASSERT(arg.value); + SPL_ASSERT(arg.value); return spl_fixpt_from_fraction( spl_fixpt_one.value, @@ -295,7 +295,7 @@ static struct spl_fixed31_32 fixed31_32_exp_from_taylor_series(struct spl_fixed3 n + 1); /* TODO find correct res */ - ASSERT(spl_fixpt_lt(arg, spl_fixpt_one)); + SPL_ASSERT(spl_fixpt_lt(arg, spl_fixpt_one)); do res = spl_fixpt_add( @@ -337,9 +337,9 @@ struct spl_fixed31_32 spl_fixpt_exp(struct spl_fixed31_32 arg) spl_fixpt_ln2, m)); - ASSERT(m != 0); + SPL_ASSERT(m != 0); - ASSERT(spl_fixpt_lt( + SPL_ASSERT(spl_fixpt_lt( spl_fixpt_abs(r), spl_fixpt_one)); @@ -364,7 +364,7 @@ struct spl_fixed31_32 spl_fixpt_log(struct spl_fixed31_32 arg) struct spl_fixed31_32 error; - ASSERT(arg.value > 0); + SPL_ASSERT(arg.value > 0); /* TODO if arg is negative, return NaN */ /* TODO if arg is zero, return -INF */ diff --git a/drivers/gpu/drm/amd/display/dc/spl/spl_fixpt31_32.h b/drivers/gpu/drm/amd/display/dc/spl/spl_fixpt31_32.h index 8a045e2f8699a..ed2647f9a0999 100644 --- a/drivers/gpu/drm/amd/display/dc/spl/spl_fixpt31_32.h +++ b/drivers/gpu/drm/amd/display/dc/spl/spl_fixpt31_32.h @@ -5,11 +5,8 @@ #ifndef __SPL_FIXED31_32_H__ #define __SPL_FIXED31_32_H__ -#include "os_types.h" +#include "spl_debug.h" #include "spl_os_types.h" // swap -#ifndef ASSERT -#define ASSERT(_bool) ((void *)0) -#endif #ifndef LLONG_MAX #define LLONG_MAX 9223372036854775807ll @@ -194,7 +191,7 @@ static inline struct spl_fixed31_32 spl_fixpt_clamp( */ static inline struct spl_fixed31_32 spl_fixpt_shl(struct spl_fixed31_32 arg, unsigned char shift) { - ASSERT(((arg.value >= 0) && (arg.value <= LLONG_MAX >> shift)) || + SPL_ASSERT(((arg.value >= 0) && (arg.value <= LLONG_MAX >> shift)) || ((arg.value < 0) && (arg.value >= ~(LLONG_MAX >> shift)))); arg.value = arg.value << shift; @@ -231,7 +228,7 @@ static inline struct spl_fixed31_32 spl_fixpt_add(struct spl_fixed31_32 arg1, st { struct spl_fixed31_32 res; - ASSERT(((arg1.value >= 0) && (LLONG_MAX - arg1.value >= arg2.value)) || + SPL_ASSERT(((arg1.value >= 0) && (LLONG_MAX - arg1.value >= arg2.value)) || ((arg1.value < 0) && (LLONG_MIN - arg1.value <= arg2.value))); res.value = arg1.value + arg2.value; @@ -256,7 +253,7 @@ static inline struct spl_fixed31_32 spl_fixpt_sub(struct spl_fixed31_32 arg1, st { struct spl_fixed31_32 res; - ASSERT(((arg2.value >= 0) && (LLONG_MIN + arg2.value <= arg1.value)) || + SPL_ASSERT(((arg2.value >= 0) && (LLONG_MIN + arg2.value <= arg1.value)) || ((arg2.value < 0) && (LLONG_MAX + arg2.value >= arg1.value))); res.value = arg1.value - arg2.value; @@ -448,7 +445,7 @@ static inline int spl_fixpt_round(struct spl_fixed31_32 arg) const long long summand = spl_fixpt_half.value; - ASSERT(LLONG_MAX - (long long)arg_value >= summand); + SPL_ASSERT(LLONG_MAX - (long long)arg_value >= summand); arg_value += summand; @@ -469,7 +466,7 @@ static inline int spl_fixpt_ceil(struct spl_fixed31_32 arg) const long long summand = spl_fixpt_one.value - spl_fixpt_epsilon.value; - ASSERT(LLONG_MAX - (long long)arg_value >= summand); + SPL_ASSERT(LLONG_MAX - (long long)arg_value >= summand); arg_value += summand; @@ -504,7 +501,7 @@ static inline struct spl_fixed31_32 spl_fixpt_truncate(struct spl_fixed31_32 arg bool negative = arg.value < 0; if (frac_bits >= FIXED31_32_BITS_PER_FRACTIONAL_PART) { - ASSERT(frac_bits == FIXED31_32_BITS_PER_FRACTIONAL_PART); + SPL_ASSERT(frac_bits == FIXED31_32_BITS_PER_FRACTIONAL_PART); return arg; } diff --git a/drivers/gpu/drm/amd/display/dc/spl/spl_os_types.h b/drivers/gpu/drm/amd/display/dc/spl/spl_os_types.h index 709706ed4f2c9..2e6ba71960acf 100644 --- a/drivers/gpu/drm/amd/display/dc/spl/spl_os_types.h +++ b/drivers/gpu/drm/amd/display/dc/spl/spl_os_types.h @@ -6,6 +6,8 @@ #ifndef _SPL_OS_TYPES_H_ #define _SPL_OS_TYPES_H_ +#include "spl_debug.h" + #include #include #include @@ -18,7 +20,6 @@ * general debug capabilities * */ -#define SPL_BREAK_TO_DEBUGGER() ASSERT(0) static inline uint64_t spl_div_u64_rem(uint64_t dividend, uint32_t divisor, uint32_t *remainder) { From f813dd65abf08147bce3ab7f422f97ec00c77deb Mon Sep 17 00:00:00 2001 From: Austin Zheng Date: Tue, 10 Sep 2024 16:41:20 -0400 Subject: [PATCH 1677/1868] drm/amd/display: Update Interface to Check UCLK DPM [Why] Videos using YUV420 format may result in high power being used. Disabling MPO may result in lower power usage. Update interface that can be used to check power profile of a dc_state. [How] Allow pstate switching in VBlank as last entry in strategy candidates. Add helper functions that can be used to determine power level: -get power profile after a dc_state has undergone full validation Reviewed-by: Aric Cyr Signed-off-by: Austin Zheng Signed-off-by: Aurabindo Pillai Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/core/dc.c | 9 ++++++++- .../dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c | 1 + drivers/gpu/drm/amd/display/dc/inc/core_types.h | 4 ++++ .../dc/resource/dcn315/dcn315_resource.c | 6 ++++++ .../dc/resource/dcn401/dcn401_resource.c | 17 +++++++++++++++++ 5 files changed, 36 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 2c5233ff90f62..c46fc93014271 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -6019,8 +6019,15 @@ void dc_set_edp_power(const struct dc *dc, struct dc_link *edp_link, struct dc_power_profile dc_get_power_profile_for_dc_state(const struct dc_state *context) { struct dc_power_profile profile = { 0 }; + struct dc *dc = NULL; - profile.power_level += !context->bw_ctx.bw.dcn.clk.p_state_change_support; + if (!context || !context->clk_mgr || !context->clk_mgr->ctx || !context->clk_mgr->ctx->dc) + return profile; + + dc = context->clk_mgr->ctx->dc; + + if (dc->res_pool->funcs->get_power_profile) + profile.power_level = dc->res_pool->funcs->get_power_profile(context); return profile; } diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c index 1cf9015e854a9..2e9c59e9e0c13 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c @@ -1798,6 +1798,7 @@ bool pmo_dcn4_fams2_init_for_pstate_support(struct dml2_pmo_init_for_pstate_supp } if (s->pmo_dcn4.num_pstate_candidates > 0) { + s->pmo_dcn4.pstate_strategy_candidates[s->pmo_dcn4.num_pstate_candidates-1].allow_state_increase = true; s->pmo_dcn4.cur_pstate_candidate = -1; return true; } else { diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index 805b25676734e..7de2dc933a098 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -214,6 +214,10 @@ struct resource_funcs { void (*get_panel_config_defaults)(struct dc_panel_config *panel_config); void (*build_pipe_pix_clk_params)(struct pipe_ctx *pipe_ctx); + /* + * Get indicator of power from a context that went through full validation + */ + int (*get_power_profile)(const struct dc_state *context); }; struct audio_support{ diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c index 3f4b9dba41124..f6b840f046a5d 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c @@ -1812,6 +1812,11 @@ static void dcn315_get_panel_config_defaults(struct dc_panel_config *panel_confi *panel_config = panel_config_defaults; } +static int dcn315_get_power_profile(const struct dc_state *context) +{ + return !context->bw_ctx.bw.dcn.clk.p_state_change_support; +} + static struct dc_cap_funcs cap_funcs = { .get_dcc_compression_cap = dcn20_get_dcc_compression_cap }; @@ -1840,6 +1845,7 @@ static struct resource_funcs dcn315_res_pool_funcs = { .update_bw_bounding_box = dcn315_update_bw_bounding_box, .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, .get_panel_config_defaults = dcn315_get_panel_config_defaults, + .get_power_profile = dcn315_get_power_profile, }; static bool dcn315_resource_construct( diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c index f2653a86d3e7d..59184abab1a70 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c @@ -1688,6 +1688,22 @@ static void dcn401_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx) } } +static int dcn401_get_power_profile(const struct dc_state *context) +{ + int uclk_mhz = context->bw_ctx.bw.dcn.clk.dramclk_khz / 1000; + int dpm_level = 0; + + for (int i = 0; i < context->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels; i++) { + if (context->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz == 0 || + uclk_mhz < context->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz) + break; + if (uclk_mhz > context->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz) + dpm_level++; + } + + return dpm_level; +} + static struct resource_funcs dcn401_res_pool_funcs = { .destroy = dcn401_destroy_resource_pool, .link_enc_create = dcn401_link_encoder_create, @@ -1714,6 +1730,7 @@ static struct resource_funcs dcn401_res_pool_funcs = { .prepare_mcache_programming = dcn401_prepare_mcache_programming, .build_pipe_pix_clk_params = dcn401_build_pipe_pix_clk_params, .calculate_mall_ways_from_bytes = dcn32_calculate_mall_ways_from_bytes, + .get_power_profile = dcn401_get_power_profile, }; static uint32_t read_pipe_fuses(struct dc_context *ctx) From 016b41e1773ab0a38de233ec1c2caeeebe45ad4f Mon Sep 17 00:00:00 2001 From: Ilya Bakoulin Date: Thu, 12 Sep 2024 14:31:13 -0400 Subject: [PATCH 1678/1868] drm/amd/display: Fix cursor visual confirm update [Why/How] Certain transitions from HW to SW cursor can be missed, which will result in black visual confirm instead of expected blue/red. Need to add handling for cursor visual confirm to dc_update_visual_confirm_color. Reviewed-by: Alvin Lee Signed-off-by: Ilya Bakoulin Signed-off-by: Aurabindo Pillai Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/core/dc.c | 2 ++ .../drm/amd/display/dc/core/dc_hw_sequencer.c | 17 +++++++++++++++++ drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 11 +---------- .../gpu/drm/amd/display/dc/hwss/hw_sequencer.h | 4 ++++ 4 files changed, 24 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index c46fc93014271..5c5cbf94304d0 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1157,6 +1157,8 @@ static void dc_update_visual_confirm_color(struct dc *dc, struct dc_state *conte get_surface_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color)); else if (dc->debug.visual_confirm == VISUAL_CONFIRM_SWIZZLE) get_surface_tile_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color)); + else if (dc->debug.visual_confirm == VISUAL_CONFIRM_HW_CURSOR) + get_cursor_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color)); else { if (dc->ctx->dce_version < DCN_VERSION_2_0) color_space_to_black_color( diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c index 2cb9253c9bdec..2fdcf8d59b9f5 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c @@ -497,6 +497,23 @@ void get_mclk_switch_visual_confirm_color( } } +void get_cursor_visual_confirm_color( + struct pipe_ctx *pipe_ctx, + struct tg_color *color) +{ + uint32_t color_value = MAX_TG_COLOR_VALUE; + + if (pipe_ctx->stream && pipe_ctx->stream->cursor_position.enable) { + color->color_r_cr = color_value; + color->color_g_y = 0; + color->color_b_cb = 0; + } else { + color->color_r_cr = 0; + color->color_g_y = 0; + color->color_b_cb = color_value; + } +} + void set_p_state_switch_method( struct dc *dc, struct dc_state *context, diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index be2638c763d78..b000bf39762f0 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -419,7 +419,6 @@ bool dc_stream_program_cursor_position( /* apply/update visual confirm */ if (dc->debug.visual_confirm == VISUAL_CONFIRM_HW_CURSOR) { /* update software state */ - uint32_t color_value = MAX_TG_COLOR_VALUE; int i; for (i = 0; i < dc->res_pool->pipe_count; i++) { @@ -427,15 +426,7 @@ bool dc_stream_program_cursor_position( /* adjust visual confirm color for all pipes with current stream */ if (stream == pipe_ctx->stream) { - if (stream->cursor_position.enable) { - pipe_ctx->visual_confirm_color.color_r_cr = color_value; - pipe_ctx->visual_confirm_color.color_g_y = 0; - pipe_ctx->visual_confirm_color.color_b_cb = 0; - } else { - pipe_ctx->visual_confirm_color.color_r_cr = 0; - pipe_ctx->visual_confirm_color.color_g_y = 0; - pipe_ctx->visual_confirm_color.color_b_cb = color_value; - } + get_cursor_visual_confirm_color(pipe_ctx, &(pipe_ctx->visual_confirm_color)); /* programming hardware */ if (pipe_ctx->plane_state) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h index b8c47e4c51c15..2f56c36e42510 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h @@ -505,6 +505,10 @@ void get_mclk_switch_visual_confirm_color( struct pipe_ctx *pipe_ctx, struct tg_color *color); +void get_cursor_visual_confirm_color( + struct pipe_ctx *pipe_ctx, + struct tg_color *color); + void set_p_state_switch_method( struct dc *dc, struct dc_state *context, From eb8e76f46774146372d2723e60aaa49cae96e4b3 Mon Sep 17 00:00:00 2001 From: Joshua Aberback Date: Thu, 12 Sep 2024 18:47:22 -0400 Subject: [PATCH 1679/1868] drm/amd/display: Clip rect size changes should be full updates [Why] In cases where an MPO plane is being dragged around partially off-screen, it is possible to get a flip where the only scaling parameters to change are the clip rect size and position. Currently, clip rect size changes are considered medium updates, which can result in the clip rect being used for HW programming being larger than the clip rect that was used for the last DML validation. This can lead to mismatches in different parts of the pipe and can result in a p-state hang. [How] - consider clip rect size changes scaling changes, therefore full updates - refactor get_scaling_info_update_type for clarity - remove clip_size_change update flag Clip rect size changes were previously demoted from full updates as an optimization when the MPO + ODM policy changed to always pre-allocate MPO pipes, but it created the issue described above. Personally testing this use case, the performance feels fine with full update spam, and we expect this is a fairly infrequent use case. If the performance needs to be optimized in the future, consider reworking the entire update type logic to run a DML pass and determine the update type based on what DML says will actually change. Reviewed-by: Dillon Varone Signed-off-by: Joshua Aberback Signed-off-by: Aurabindo Pillai Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/core/dc.c | 45 ++++++++----------- drivers/gpu/drm/amd/display/dc/dc.h | 1 - .../amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 2 - 3 files changed, 19 insertions(+), 29 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 5c5cbf94304d0..8d5a4e4e234fc 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -2515,41 +2515,35 @@ static enum surface_update_type get_scaling_info_update_type( if (!u->scaling_info) return UPDATE_TYPE_FAST; - if (u->scaling_info->dst_rect.width != u->surface->dst_rect.width + if (u->scaling_info->src_rect.width != u->surface->src_rect.width + || u->scaling_info->src_rect.height != u->surface->src_rect.height + || u->scaling_info->dst_rect.width != u->surface->dst_rect.width || u->scaling_info->dst_rect.height != u->surface->dst_rect.height + || u->scaling_info->clip_rect.width != u->surface->clip_rect.width + || u->scaling_info->clip_rect.height != u->surface->clip_rect.height || u->scaling_info->scaling_quality.integer_scaling != - u->surface->scaling_quality.integer_scaling - ) { + u->surface->scaling_quality.integer_scaling) { update_flags->bits.scaling_change = 1; + if (u->scaling_info->src_rect.width > u->surface->src_rect.width + || u->scaling_info->src_rect.height > u->surface->src_rect.height) + /* Making src rect bigger requires a bandwidth change */ + update_flags->bits.clock_change = 1; + if ((u->scaling_info->dst_rect.width < u->surface->dst_rect.width || u->scaling_info->dst_rect.height < u->surface->dst_rect.height) && (u->scaling_info->dst_rect.width < u->surface->src_rect.width || u->scaling_info->dst_rect.height < u->surface->src_rect.height)) /* Making dst rect smaller requires a bandwidth change */ update_flags->bits.bandwidth_change = 1; - } - - if (u->scaling_info->src_rect.width != u->surface->src_rect.width - || u->scaling_info->src_rect.height != u->surface->src_rect.height) { - update_flags->bits.scaling_change = 1; - if (u->scaling_info->src_rect.width > u->surface->src_rect.width - || u->scaling_info->src_rect.height > u->surface->src_rect.height) - /* Making src rect bigger requires a bandwidth change */ - update_flags->bits.clock_change = 1; + if (u->scaling_info->src_rect.width > dc->caps.max_optimizable_video_width && + (u->scaling_info->clip_rect.width > u->surface->clip_rect.width || + u->scaling_info->clip_rect.height > u->surface->clip_rect.height)) + /* Changing clip size of a large surface may result in MPC slice count change */ + update_flags->bits.bandwidth_change = 1; } - if (u->scaling_info->src_rect.width > dc->caps.max_optimizable_video_width && - (u->scaling_info->clip_rect.width > u->surface->clip_rect.width || - u->scaling_info->clip_rect.height > u->surface->clip_rect.height)) - /* Changing clip size of a large surface may result in MPC slice count change */ - update_flags->bits.bandwidth_change = 1; - - if (u->scaling_info->clip_rect.width != u->surface->clip_rect.width || - u->scaling_info->clip_rect.height != u->surface->clip_rect.height) - update_flags->bits.clip_size_change = 1; - if (u->scaling_info->src_rect.x != u->surface->src_rect.x || u->scaling_info->src_rect.y != u->surface->src_rect.y || u->scaling_info->clip_rect.x != u->surface->clip_rect.x @@ -2558,13 +2552,13 @@ static enum surface_update_type get_scaling_info_update_type( || u->scaling_info->dst_rect.y != u->surface->dst_rect.y) update_flags->bits.position_change = 1; + /* process every update flag before returning */ if (update_flags->bits.clock_change || update_flags->bits.bandwidth_change || update_flags->bits.scaling_change) return UPDATE_TYPE_FULL; - if (update_flags->bits.position_change || - update_flags->bits.clip_size_change) + if (update_flags->bits.position_change) return UPDATE_TYPE_MED; return UPDATE_TYPE_FAST; @@ -3264,8 +3258,7 @@ static bool update_planes_and_stream_state(struct dc *dc, if (update_type != UPDATE_TYPE_MED) continue; - if (surface->update_flags.bits.clip_size_change || - surface->update_flags.bits.position_change) { + if (surface->update_flags.bits.position_change) { for (j = 0; j < dc->res_pool->pipe_count; j++) { struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j]; diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 3321f44c9fd8f..5c7f9e0d3199f 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -1257,7 +1257,6 @@ union surface_update_flags { uint32_t rotation_change:1; uint32_t swizzle_change:1; uint32_t scaling_change:1; - uint32_t clip_size_change: 1; uint32_t position_change:1; uint32_t in_transfer_func_change:1; uint32_t input_csc_change:1; diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c index b383ed8cb4d49..e89499536c460 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c @@ -1732,7 +1732,6 @@ static void dcn20_update_dchubp_dpp( if (pipe_ctx->update_flags.bits.scaler || plane_state->update_flags.bits.scaling_change || plane_state->update_flags.bits.position_change || - plane_state->update_flags.bits.clip_size_change || plane_state->update_flags.bits.per_pixel_alpha_change || pipe_ctx->stream->update_flags.bits.scaling) { pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->plane_state->per_pixel_alpha; @@ -1745,7 +1744,6 @@ static void dcn20_update_dchubp_dpp( if (pipe_ctx->update_flags.bits.viewport || (context == dc->current_state && plane_state->update_flags.bits.position_change) || (context == dc->current_state && plane_state->update_flags.bits.scaling_change) || - (context == dc->current_state && plane_state->update_flags.bits.clip_size_change) || (context == dc->current_state && pipe_ctx->stream->update_flags.bits.scaling)) { hubp->funcs->mem_program_viewport( From 2bb07a3ce9445ef8162e522de095f9e1dfd4c63e Mon Sep 17 00:00:00 2001 From: Alex Hung Date: Fri, 6 Sep 2024 11:39:18 -0600 Subject: [PATCH 1680/1868] drm/amd/display: Add HDR workaround for specific eDP [WHY & HOW] Some eDP panels suffer from flicking when HDR is enabled in KDE. This quirk works around it by skipping VSC that is incompatible with eDP panels. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/3151 Cc: Mario Limonciello Cc: Alex Deucher Cc: stable@vger.kernel.org Reviewed-by: Rodrigo Siqueira Signed-off-by: Alex Hung Signed-off-by: Aurabindo Pillai Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 11 ++++++++++- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 4 ++++ drivers/gpu/drm/amd/display/dc/dc_types.h | 1 + 3 files changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 4909dd1bc8207..307e32b4f845a 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -6924,12 +6924,21 @@ create_stream_for_sink(struct drm_connector *connector, if (stream->signal == SIGNAL_TYPE_DISPLAY_PORT || stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST || stream->signal == SIGNAL_TYPE_EDP) { + const struct dc_edid_caps *edid_caps; + unsigned int disable_colorimetry = 0; + + if (aconnector->dc_sink) { + edid_caps = &aconnector->dc_sink->edid_caps; + disable_colorimetry = edid_caps->panel_patch.disable_colorimetry; + } + // // should decide stream support vsc sdp colorimetry capability // before building vsc info packet // stream->use_vsc_sdp_for_colorimetry = stream->link->dpcd_caps.dpcd_rev.raw >= 0x14 && - stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED; + stream->link->dpcd_caps.dprx_feature.bits.VSC_SDP_COLORIMETRY_SUPPORTED && + !disable_colorimetry; if (stream->out_transfer_func.tf == TRANSFER_FUNCTION_GAMMA22) tf = TRANSFER_FUNC_GAMMA_22; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index 40688990981a5..2379d40c3121f 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -108,6 +108,10 @@ static void apply_edid_quirks(struct edid *edid, struct dc_edid_caps *edid_caps) DRM_DEBUG_DRIVER("Clearing DPCD 0x317 on monitor with panel id %X\n", panel_id); edid_caps->panel_patch.remove_sink_ext_caps = true; break; + case drm_edid_encode_panel_id('S', 'D', 'C', 0x4154): + DRM_DEBUG_DRIVER("Disabling VSC on monitor with panel id %X\n", panel_id); + edid_caps->panel_patch.disable_colorimetry = true; + break; default: return; } diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h index 2bbafd1cdce47..b0b7102fdbc75 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_types.h @@ -178,6 +178,7 @@ struct dc_panel_patch { unsigned int skip_avmute; unsigned int mst_start_top_delay; unsigned int remove_sink_ext_caps; + unsigned int disable_colorimetry; uint8_t blankstream_before_otg_off; }; From ccb34e113fa4e0dcc77fb41459072fea1a2fb7e5 Mon Sep 17 00:00:00 2001 From: Austin Zheng Date: Thu, 12 Sep 2024 15:34:14 -0400 Subject: [PATCH 1681/1868] drm/amd/display: Wait For DET Update Should Use Current State [Why] Current state should be used when waiting for DET update instead of new context. For any streams decreasing in DET, pipes used in the current state should be checked since those pipes need to free their DET before DET can be reallocated. [How] Pass in current_state instead of context. Use pipe from current_state instead of context. This assumes that pipe in the current_state is an OTG_MASTER pipe if the pipe in the context is an OTG_MASTER pipe. Reviewed-by: Dillon Varone Signed-off-by: Austin Zheng Signed-off-by: Aurabindo Pillai Tested-by: Daniel Wheeler --- .../gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 9 +++++++-- .../gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h | 2 +- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c index 29fcb4ed66464..805e7b52df29d 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c @@ -1669,7 +1669,7 @@ void dcn401_hardware_release(struct dc *dc) } } -void dcn401_wait_for_det_buffer_update(struct dc *dc, struct dc_state *context, struct pipe_ctx *otg_master) +void dcn401_wait_for_det_buffer_update_under_otg_master(struct dc *dc, struct dc_state *context, struct pipe_ctx *otg_master) { struct pipe_ctx *opp_heads[MAX_PIPES]; struct pipe_ctx *dpp_pipes[MAX_PIPES]; @@ -1695,6 +1695,9 @@ void dcn401_wait_for_det_buffer_update(struct dc *dc, struct dc_state *context, hubbub->funcs->wait_for_det_update) hubbub->funcs->wait_for_det_update(hubbub, dpp_pipe->plane_res.hubp->inst); } + } else { + if (hubbub && opp_heads[slice_idx]->plane_res.hubp && hubbub->funcs->wait_for_det_update) + hubbub->funcs->wait_for_det_update(hubbub, opp_heads[slice_idx]->plane_res.hubp->inst); } } } @@ -1730,8 +1733,10 @@ void dcn401_interdependent_update_lock(struct dc *dc, } if (dc->scratch.pipes_to_unlock_first[i]) { + struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i]; dc->hwss.pipe_control_lock(dc, pipe, false); - dcn401_wait_for_det_buffer_update(dc, context, pipe); + /* Assumes pipe of the same index in current_state is also an OTG_MASTER pipe*/ + dcn401_wait_for_det_buffer_update_under_otg_master(dc, dc->current_state, old_pipe); } } diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h index a27e62081685d..1e8189bb447e4 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h @@ -81,7 +81,7 @@ void dcn401_hardware_release(struct dc *dc); void dcn401_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *otg_master); void adjust_hotspot_between_slices_for_2x_magnify(uint32_t cursor_width, struct dc_cursor_position *pos_cpy); -void dcn401_wait_for_det_buffer_update(struct dc *dc, struct dc_state *context, struct pipe_ctx *otg_master); +void dcn401_wait_for_det_buffer_update_under_otg_master(struct dc *dc, struct dc_state *context, struct pipe_ctx *otg_master); void dcn401_interdependent_update_lock(struct dc *dc, struct dc_state *context, bool lock); void dcn401_program_outstanding_updates(struct dc *dc, struct dc_state *context); #endif /* __DC_HWSS_DCN401_H__ */ From f869fefc8595faff86fc9a7b6750b38a75327894 Mon Sep 17 00:00:00 2001 From: Leo Li Date: Wed, 11 Sep 2024 17:27:08 -0400 Subject: [PATCH 1682/1868] drm/amd/display: Enable idle workqueue for more IPS modes [Why] There are more IPS modes other than DMUB_IPS_ENABLE that enables IPS. We need to enable the hotplug detect idle workqueue for those modes as well. [How] Modify the if condition to initialize the workqueue in all IPS modes except for DMUB_IPS_DISABLE_ALL. Fixes: 514fd3e75d90 ("drm/amd/display: Determine IPS mode by ASIC and PMFW versions") Signed-off-by: Leo Li Reviewed-by: Roman Li Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 307e32b4f845a..662081360d305 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2058,7 +2058,8 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) DRM_ERROR("amdgpu: failed to initialize vblank_workqueue.\n"); } - if (adev->dm.dc->caps.ips_support && adev->dm.dc->config.disable_ips == DMUB_IPS_ENABLE) + if (adev->dm.dc->caps.ips_support && + adev->dm.dc->config.disable_ips != DMUB_IPS_DISABLE_ALL) adev->dm.idle_workqueue = idle_create_workqueue(adev); if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) { From 069abf58a305a52c4a65b9c5b89427e3c5159bc6 Mon Sep 17 00:00:00 2001 From: Aric Cyr Date: Sun, 15 Sep 2024 20:34:33 -0400 Subject: [PATCH 1683/1868] drm/amd/display: 3.2.302 * Stability fixes in DML, SPL, * Improvements for MST, DSC, eDP, IPS, HDR * Fix clock gating on DCN35 * Fixes from static analysis checks * Other bug fixes and debug improvements Reviewed-by: Leo Li Signed-off-by: Aric Cyr Signed-off-by: Aurabindo Pillai Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 5c7f9e0d3199f..bf03853e200cc 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -55,7 +55,7 @@ struct aux_payload; struct set_config_cmd_payload; struct dmub_notification; -#define DC_VER "3.2.301" +#define DC_VER "3.2.302" #define MAX_SURFACES 3 #define MAX_PLANES 6 From 42934e4b8e3026090e13a3398106edda9a0b0e9e Mon Sep 17 00:00:00 2001 From: Ryan Seto Date: Fri, 13 Sep 2024 16:01:47 -0400 Subject: [PATCH 1684/1868] drm/amd/display: Adjust PHY FSM transition to TX_EN-to-PLL_ON for TMDS [Why] If two monitors with TMDS signals were timing synced and one was disconnected, the stream would go out of sync too early due to the PLL turning off and the system could hang [How] On link disable output, change PHY FSM transition from TX_EN-to-PHY_OFF to TX_EN-to-PLL_ON for TMDS Reviewed-by: Wenjing Liu Signed-off-by: Ryan Seto Signed-off-by: Fangzhi Zuo Tested-by: Daniel Wheeler --- .../amd/display/dc/dccg/dcn401/dcn401_dccg.c | 81 ------------------- .../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 52 ++++++++++++ .../amd/display/dc/hwss/dcn401/dcn401_hwseq.h | 4 + .../amd/display/dc/hwss/dcn401/dcn401_init.c | 2 +- 4 files changed, 57 insertions(+), 82 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c index 0b889004509ad..5babd53025aef 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c @@ -805,33 +805,6 @@ static void dccg401_enable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst { struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); - switch (link_enc_inst) { - case 0: - REG_UPDATE(SYMCLKA_CLOCK_ENABLE, - SYMCLKA_CLOCK_ENABLE, 1); - if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) - REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKA_ROOT_GATE_DISABLE, 1); - break; - case 1: - REG_UPDATE(SYMCLKB_CLOCK_ENABLE, - SYMCLKB_CLOCK_ENABLE, 1); - if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) - REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKB_ROOT_GATE_DISABLE, 1); - break; - case 2: - REG_UPDATE(SYMCLKC_CLOCK_ENABLE, - SYMCLKC_CLOCK_ENABLE, 1); - if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) - REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKC_ROOT_GATE_DISABLE, 1); - break; - case 3: - REG_UPDATE(SYMCLKD_CLOCK_ENABLE, - SYMCLKD_CLOCK_ENABLE, 1); - if (dccg->ctx->dc->debug.root_clock_optimization.bits.symclk32_se) - REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, SYMCLKD_ROOT_GATE_DISABLE, 1); - break; - } - switch (stream_enc_inst) { case 0: REG_UPDATE_2(SYMCLKA_CLOCK_ENABLE, @@ -864,37 +837,8 @@ static void dccg401_enable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst } } -/*get other front end connected to this backend*/ -static uint8_t dccg401_get_number_enabled_symclk_fe_connected_to_be(struct dccg *dccg, uint32_t link_enc_inst) -{ - uint8_t num_enabled_symclk_fe = 0; - uint32_t fe_clk_en[4] = {0}, be_clk_sel[4] = {0}; - struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); - uint8_t i; - - REG_GET_2(SYMCLKA_CLOCK_ENABLE, SYMCLKA_FE_EN, &fe_clk_en[0], - SYMCLKA_FE_SRC_SEL, &be_clk_sel[0]); - - REG_GET_2(SYMCLKB_CLOCK_ENABLE, SYMCLKB_FE_EN, &fe_clk_en[1], - SYMCLKB_FE_SRC_SEL, &be_clk_sel[1]); - - REG_GET_2(SYMCLKC_CLOCK_ENABLE, SYMCLKC_FE_EN, &fe_clk_en[2], - SYMCLKC_FE_SRC_SEL, &be_clk_sel[2]); - - REG_GET_2(SYMCLKD_CLOCK_ENABLE, SYMCLKD_FE_EN, &fe_clk_en[3], - SYMCLKD_FE_SRC_SEL, &be_clk_sel[3]); - - for (i = 0; i < ARRAY_SIZE(fe_clk_en); i++) { - if (fe_clk_en[i] && be_clk_sel[i] == link_enc_inst) - num_enabled_symclk_fe++; - } - - return num_enabled_symclk_fe; -} - static void dccg401_disable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst) { - uint8_t num_enabled_symclk_fe = 0; struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); switch (stream_enc_inst) { @@ -919,31 +863,6 @@ static void dccg401_disable_symclk_se(struct dccg *dccg, uint32_t stream_enc_ins SYMCLKD_FE_SRC_SEL, 0); break; } - - /*check other enabled symclk fe connected to this be */ - num_enabled_symclk_fe = dccg401_get_number_enabled_symclk_fe_connected_to_be(dccg, link_enc_inst); - /*only turn off backend clk if other front ends attached to this backend are all off, - for mst, only turn off the backend if this is the last front end*/ - if (num_enabled_symclk_fe == 0) { - switch (link_enc_inst) { - case 0: - REG_UPDATE(SYMCLKA_CLOCK_ENABLE, - SYMCLKA_CLOCK_ENABLE, 0); - break; - case 1: - REG_UPDATE(SYMCLKB_CLOCK_ENABLE, - SYMCLKB_CLOCK_ENABLE, 0); - break; - case 2: - REG_UPDATE(SYMCLKC_CLOCK_ENABLE, - SYMCLKC_CLOCK_ENABLE, 0); - break; - case 3: - REG_UPDATE(SYMCLKD_CLOCK_ENABLE, - SYMCLKD_CLOCK_ENABLE, 0); - break; - } - } } static const struct dccg_funcs dccg401_funcs = { diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c index 805e7b52df29d..b690f0565d285 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c @@ -1097,6 +1097,58 @@ void adjust_hotspot_between_slices_for_2x_magnify(uint32_t cursor_width, struct } } +static void disable_link_output_symclk_on_tx_off(struct dc_link *link, enum dp_link_encoding link_encoding) +{ + struct dc *dc = link->ctx->dc; + struct pipe_ctx *pipe_ctx = NULL; + uint8_t i; + + for (i = 0; i < MAX_PIPES; i++) { + pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i]; + if (pipe_ctx->stream && pipe_ctx->stream->link == link && pipe_ctx->top_pipe == NULL) { + pipe_ctx->clock_source->funcs->program_pix_clk( + pipe_ctx->clock_source, + &pipe_ctx->stream_res.pix_clk_params, + link_encoding, + &pipe_ctx->pll_settings); + break; + } + } +} + +void dcn401_disable_link_output(struct dc_link *link, + const struct link_resource *link_res, + enum signal_type signal) +{ + struct dc *dc = link->ctx->dc; + const struct link_hwss *link_hwss = get_link_hwss(link, link_res); + struct dmcu *dmcu = dc->res_pool->dmcu; + + if (signal == SIGNAL_TYPE_EDP && + link->dc->hwss.edp_backlight_control && + !link->skip_implict_edp_power_control) + link->dc->hwss.edp_backlight_control(link, false); + else if (dmcu != NULL && dmcu->funcs->lock_phy) + dmcu->funcs->lock_phy(dmcu); + + if (dc_is_tmds_signal(signal) && link->phy_state.symclk_ref_cnts.otg > 0) { + disable_link_output_symclk_on_tx_off(link, DP_UNKNOWN_ENCODING); + link->phy_state.symclk_state = SYMCLK_ON_TX_OFF; + } else { + link_hwss->disable_link_output(link, link_res, signal); + link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF; + } + + if (signal == SIGNAL_TYPE_EDP && + link->dc->hwss.edp_backlight_control && + !link->skip_implict_edp_power_control) + link->dc->hwss.edp_power_control(link, false); + else if (dmcu != NULL && dmcu->funcs->lock_phy) + dmcu->funcs->unlock_phy(dmcu); + + dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY); +} + void dcn401_set_cursor_position(struct pipe_ctx *pipe_ctx) { struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position; diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h index 1e8189bb447e4..e6692cd905d65 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h @@ -55,6 +55,10 @@ void dcn401_populate_mcm_luts(struct dc *dc, bool lut_bank_a); void dcn401_setup_hpo_hw_control(const struct dce_hwseq *hws, bool enable); +void dcn401_disable_link_output(struct dc_link *link, + const struct link_resource *link_res, + enum signal_type signal); + void dcn401_set_cursor_position(struct pipe_ctx *pipe_ctx); bool dcn401_apply_idle_power_optimizations(struct dc *dc, bool enable); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c index 73a632b5ff893..d1128a8082a5e 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c @@ -84,7 +84,7 @@ static const struct hw_sequencer_funcs dcn401_funcs = { .enable_lvds_link_output = dce110_enable_lvds_link_output, .enable_tmds_link_output = dce110_enable_tmds_link_output, .enable_dp_link_output = dce110_enable_dp_link_output, - .disable_link_output = dcn32_disable_link_output, + .disable_link_output = dcn401_disable_link_output, .set_disp_pattern_generator = dcn30_set_disp_pattern_generator, .get_dcc_en_bits = dcn10_get_dcc_en_bits, .enable_phantom_streams = dcn32_enable_phantom_streams, From 4e37586a589b3b3c6909cb19f5b5588da446ee41 Mon Sep 17 00:00:00 2001 From: Tom Chung Date: Fri, 13 Sep 2024 15:44:40 +0800 Subject: [PATCH 1685/1868] drm/amd/display: Fix system hang while resume with TBT monitor [Why] Connected with a Thunderbolt monitor and do the suspend and the system may hang while resume. The TBT monitor HPD will be triggered during the resume procedure and call the drm_client_modeset_probe() while struct drm_connector connector->dev->master is NULL. It will mess up the pipe topology after resume. [How] Skip the TBT monitor HPD during the resume procedure because we currently will probe the connectors after resume by default. Reviewed-by: Wayne Lin Signed-off-by: Tom Chung Signed-off-by: Fangzhi Zuo Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 662081360d305..843c729315e2b 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -783,6 +783,12 @@ static void dmub_hpd_callback(struct amdgpu_device *adev, return; } + /* Skip DMUB HPD IRQ in suspend/resume. We will probe them later. */ + if (notify->type == DMUB_NOTIFICATION_HPD && adev->in_suspend) { + DRM_INFO("Skip DMUB HPD IRQ callback in suspend/resume\n"); + return; + } + link_index = notify->link_index; link = adev->dm.dc->links[link_index]; dev = adev->dm.ddev; From 3aee17e36fa09813df55bfbbcab7e4fc19e9a598 Mon Sep 17 00:00:00 2001 From: Paul Hsieh Date: Thu, 12 Sep 2024 14:47:51 +0800 Subject: [PATCH 1686/1868] drm/amd/display: Add logs to record register read/write [Why] There are some issues which customer only can provide full dump for analyze, without register history, it's hard to debug HW status. [How] 1. Put register read/write into WPP log so we can trace the logs from full memory dump. 2. MALL doesn't add into WPP, add it. Reviewed-by: Aric Cyr Signed-off-by: Paul Hsieh Signed-off-by: Fangzhi Zuo Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/include/logger_types.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/include/logger_types.h b/drivers/gpu/drm/amd/display/include/logger_types.h index a48d564d1660c..4d68c1c6e2100 100644 --- a/drivers/gpu/drm/amd/display/include/logger_types.h +++ b/drivers/gpu/drm/amd/display/include/logger_types.h @@ -61,11 +61,13 @@ #define DC_LOG_ALL_TF_CHANNELS(...) pr_debug("[GAMMA]:"__VA_ARGS__) #define DC_LOG_DSC(...) drm_dbg_dp((DC_LOGGER)->dev, __VA_ARGS__) #define DC_LOG_SMU(...) pr_debug("[SMU_MSG]:"__VA_ARGS__) -#define DC_LOG_MALL(...) pr_debug("[MALL]:"__VA_ARGS__) #define DC_LOG_DWB(...) drm_dbg((DC_LOGGER)->dev, __VA_ARGS__) #define DC_LOG_DP2(...) drm_dbg_dp((DC_LOGGER)->dev, __VA_ARGS__) #define DC_LOG_AUTO_DPM_TEST(...) pr_debug("[AutoDPMTest]: "__VA_ARGS__) #define DC_LOG_IPS(...) pr_debug("[IPS]: "__VA_ARGS__) +#define DC_LOG_MALL(...) pr_debug("[MALL]:"__VA_ARGS__) +#define DC_LOG_REGISTER_READ(...) pr_debug("[REGISTER_READ]: "__VA_ARGS__) +#define DC_LOG_REGISTER_WRITE(...) pr_debug("[REGISTER_WRITE]: "__VA_ARGS__) struct dc_log_buffer_ctx { char *buf; From b6b5e41dd681ed359cc15fc465af307041c038dd Mon Sep 17 00:00:00 2001 From: "Liu Xi (Alex)" Date: Thu, 19 Sep 2024 15:10:15 -0400 Subject: [PATCH 1687/1868] drm/amd/display: add more support for UHBR10 eDP [Why and how] The current UHBR10 eDP panel has new security feature update. Add support for the new FW Reviewed-by: Wenjing Liu Signed-off-by: Liu Xi (Alex) Signed-off-by: Fangzhi Zuo Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/dc.h | 1 - .../drm/amd/display/dc/link/protocols/link_edp_panel_control.c | 3 --- 2 files changed, 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index bf03853e200cc..b56790ede5c64 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -1774,7 +1774,6 @@ struct dc_link { bool dongle_mode_timing_override; bool blank_stream_on_ocs_change; bool read_dpcd204h_on_irq_hpd; - bool disable_assr_for_uhbr; } wa_flags; struct link_mst_stream_allocation_table mst_stream_alloc_table; diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c index 3aa05a2be6c09..070b6c8c1aef9 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c @@ -1168,9 +1168,6 @@ static void edp_set_assr_enable(const struct dc *pDC, struct dc_link *link, link_enc_index = link->link_enc->transmitter - TRANSMITTER_UNIPHY_A; if (link_res->hpo_dp_link_enc) { - if (link->wa_flags.disable_assr_for_uhbr) - return; - link_enc_index = link_res->hpo_dp_link_enc->inst; use_hpo_dp_link_enc = true; } From 6ed0796a837a4d91e6b4159091a7b002e6040545 Mon Sep 17 00:00:00 2001 From: Muyuan Yang Date: Wed, 5 Jun 2024 10:24:59 -0400 Subject: [PATCH 1688/1868] drm/amd/display: Change Brightness Control Priority Prioritize Aux-based over PWM-based brightness control for more types of panels and introduce a new structure to store and manage the type of brightness control used. Reviewed-by: Anthony Koo Signed-off-by: Muyuan Yang Signed-off-by: Fangzhi Zuo Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/dc.h | 1 + drivers/gpu/drm/amd/display/dc/dc_types.h | 6 ++++++ 2 files changed, 7 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index b56790ede5c64..cec44579cb9f5 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -1789,6 +1789,7 @@ struct dc_link { // BW ALLOCATON USB4 ONLY struct dc_dpia_bw_alloc dpia_bw_alloc_config; bool skip_implict_edp_power_control; + enum backlight_control_type backlight_control_type; }; /* Return an enumerated dc_link. diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h index b0b7102fdbc75..3401f4c9fb10e 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_types.h @@ -923,6 +923,12 @@ struct display_endpoint_id { enum display_endpoint_type ep_type; }; +enum backlight_control_type { + BACKLIGHT_CONTROL_PWM = 0, + BACKLIGHT_CONTROL_VESA_AUX = 1, + BACKLIGHT_CONTROL_AMD_AUX = 2, +}; + #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY) struct otg_phy_mux { uint8_t phy_output_num; From 7e08be99d357f368d4388df89f74f19c0a29c6ed Mon Sep 17 00:00:00 2001 From: Muyuan Yang Date: Thu, 18 Jul 2024 14:03:18 -0400 Subject: [PATCH 1689/1868] drm/amd/display: Introduce New ABC Framework for Brightness Control Adjust the existing brightness control functions to use the new ABC Framework and prioritize Aux-based brightness control. Reviewed-by: Anthony Koo Signed-off-by: Muyuan Yang Signed-off-by: Fangzhi Zuo Tested-by: Daniel Wheeler --- .../link/protocols/link_edp_panel_control.c | 40 +++++++++---------- 1 file changed, 19 insertions(+), 21 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c index 070b6c8c1aef9..7680bc8845d42 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c @@ -157,31 +157,11 @@ bool edp_set_backlight_level_nits(struct dc_link *link, uint32_t backlight_millinits, uint32_t transition_time_in_ms) { - struct dpcd_source_backlight_set dpcd_backlight_set; - uint8_t backlight_control = isHDR ? 1 : 0; - if (!link || (link->connector_signal != SIGNAL_TYPE_EDP && link->connector_signal != SIGNAL_TYPE_DISPLAY_PORT)) return false; - // OLEDs have no PWM, they can only use AUX - if (link->dpcd_sink_ext_caps.bits.oled == 1) - backlight_control = 1; - - *(uint32_t *)&dpcd_backlight_set.backlight_level_millinits = backlight_millinits; - *(uint16_t *)&dpcd_backlight_set.backlight_transition_time_ms = (uint16_t)transition_time_in_ms; - - - if (!link->dpcd_caps.panel_luminance_control) { - if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL, - (uint8_t *)(&dpcd_backlight_set), - sizeof(dpcd_backlight_set)) != DC_OK) - return false; - - if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_CONTROL, - &backlight_control, 1) != DC_OK) - return false; - } else { + if (link->backlight_control_type == BACKLIGHT_CONTROL_VESA_AUX) { uint8_t backlight_enable = 0; struct target_luminance_value *target_luminance = NULL; @@ -205,6 +185,24 @@ bool edp_set_backlight_level_nits(struct dc_link *link, (uint8_t *)(target_luminance), sizeof(struct target_luminance_value)) != DC_OK) return false; + } else { + struct dpcd_source_backlight_set dpcd_backlight_set; + *(uint32_t *)&dpcd_backlight_set.backlight_level_millinits = backlight_millinits; + *(uint16_t *)&dpcd_backlight_set.backlight_transition_time_ms = (uint16_t)transition_time_in_ms; + + uint8_t backlight_control = isHDR ? 1 : 0; + // OLEDs have no PWM, they can only use AUX + if (link->dpcd_sink_ext_caps.bits.oled == 1) + backlight_control = 1; + + if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_LEVEL, + (uint8_t *)(&dpcd_backlight_set), + sizeof(dpcd_backlight_set)) != DC_OK) + return false; + + if (core_link_write_dpcd(link, DP_SOURCE_BACKLIGHT_CONTROL, + &backlight_control, 1) != DC_OK) + return false; } return true; From badd206293b0a9b9ba41e2b4969e166c6acb7097 Mon Sep 17 00:00:00 2001 From: Alex Hung Date: Wed, 18 Sep 2024 15:33:27 -0600 Subject: [PATCH 1690/1868] drm/amd/display: Remove always-false branches [WHAT & HOW] MacroTileSizeBytes is set to either 256 or 65535 and it is never 4096. Its branch is not taken, and should be removed. Similarly, mode_422 is always 0 and thus ppe will always be 1. The ternary operator should be removed. This fixes 2 DEADCODE issues reported by Coverity. Reviewed-by: Rodrigo Siqueira Signed-off-by: Alex Hung Signed-off-by: Fangzhi Zuo Tested-by: Daniel Wheeler --- .../drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c | 9 --------- .../drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c | 3 +-- 2 files changed, 1 insertion(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c index 1c10ba4dcddea..4822fad6ce3a1 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c @@ -1775,15 +1775,6 @@ static unsigned int CalculateVMAndRowBytes( *PixelPTEReqWidth = 32768.0 / BytePerPixel; *PTERequestSize = 64; FractionOfPTEReturnDrop = 0; - } else if (MacroTileSizeBytes == 4096) { - PixelPTEReqHeightPTEs = 1; - *PixelPTEReqHeight = MacroTileHeight; - *PixelPTEReqWidth = 8 * *MacroTileWidth; - *PTERequestSize = 64; - if (ScanDirection != dm_vert) - FractionOfPTEReturnDrop = 0; - else - FractionOfPTEReturnDrop = 7.0 / 8; } else if (GPUVMMinPageSize == 4 && MacroTileSizeBytes > 4096) { PixelPTEReqHeightPTEs = 16; *PixelPTEReqHeight = 16 * BlockHeight256Bytes; diff --git a/drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c b/drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c index d8bfc85e5dcd0..88dc2b97e7bf5 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c @@ -559,12 +559,11 @@ static void get_surf_rq_param( const struct _vcs_dpi_display_pipe_source_params_st *pipe_src_param, bool is_chroma) { - bool mode_422 = 0; unsigned int vp_width = 0; unsigned int vp_height = 0; unsigned int data_pitch = 0; unsigned int meta_pitch = 0; - unsigned int ppe = mode_422 ? 2 : 1; + unsigned int ppe = 1; bool surf_linear; bool surf_vert; unsigned int bytes_per_element; From f9b4e6a5866ccd56de5922c78d3c7f1b2193baa7 Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Wed, 25 Sep 2024 20:04:15 +0530 Subject: [PATCH 1691/1868] drm/amd/display: Fix out-of-bounds access in 'dcn21_link_encoder_create' An issue was identified in the dcn21_link_encoder_create function where an out-of-bounds access could occur when the hpd_source index was used to reference the link_enc_hpd_regs array. This array has a fixed size and the index was not being checked against the array's bounds before accessing it. This fix adds a conditional check to ensure that the hpd_source index is within the valid range of the link_enc_hpd_regs array. If the index is out of bounds, the function now returns NULL to prevent undefined behavior. References: [ 65.920507] ------------[ cut here ]------------ [ 65.920510] UBSAN: array-index-out-of-bounds in drivers/gpu/drm/amd/amdgpu/../display/dc/resource/dcn21/dcn21_resource.c:1312:29 [ 65.920519] index 7 is out of range for type 'dcn10_link_enc_hpd_registers [5]' [ 65.920523] CPU: 3 PID: 1178 Comm: modprobe Tainted: G OE 6.8.0-cleanershaderfeatureresetasdntipmi200nv2132 #13 [ 65.920525] Hardware name: AMD Majolica-RN/Majolica-RN, BIOS WMJ0429N_Weekly_20_04_2 04/29/2020 [ 65.920527] Call Trace: [ 65.920529] [ 65.920532] dump_stack_lvl+0x48/0x70 [ 65.920541] dump_stack+0x10/0x20 [ 65.920543] __ubsan_handle_out_of_bounds+0xa2/0xe0 [ 65.920549] dcn21_link_encoder_create+0xd9/0x140 [amdgpu] [ 65.921009] link_create+0x6d3/0xed0 [amdgpu] [ 65.921355] create_links+0x18a/0x4e0 [amdgpu] [ 65.921679] dc_create+0x360/0x720 [amdgpu] [ 65.921999] ? dmi_matches+0xa0/0x220 [ 65.922004] amdgpu_dm_init+0x2b6/0x2c90 [amdgpu] [ 65.922342] ? console_unlock+0x77/0x120 [ 65.922348] ? dev_printk_emit+0x86/0xb0 [ 65.922354] dm_hw_init+0x15/0x40 [amdgpu] [ 65.922686] amdgpu_device_init+0x26a8/0x33a0 [amdgpu] [ 65.922921] amdgpu_driver_load_kms+0x1b/0xa0 [amdgpu] [ 65.923087] amdgpu_pci_probe+0x1b7/0x630 [amdgpu] [ 65.923087] local_pci_probe+0x4b/0xb0 [ 65.923087] pci_device_probe+0xc8/0x280 [ 65.923087] really_probe+0x187/0x300 [ 65.923087] __driver_probe_device+0x85/0x130 [ 65.923087] driver_probe_device+0x24/0x110 [ 65.923087] __driver_attach+0xac/0x1d0 [ 65.923087] ? __pfx___driver_attach+0x10/0x10 [ 65.923087] bus_for_each_dev+0x7d/0xd0 [ 65.923087] driver_attach+0x1e/0x30 [ 65.923087] bus_add_driver+0xf2/0x200 [ 65.923087] driver_register+0x64/0x130 [ 65.923087] ? __pfx_amdgpu_init+0x10/0x10 [amdgpu] [ 65.923087] __pci_register_driver+0x61/0x70 [ 65.923087] amdgpu_init+0x7d/0xff0 [amdgpu] [ 65.923087] do_one_initcall+0x49/0x310 [ 65.923087] ? kmalloc_trace+0x136/0x360 [ 65.923087] do_init_module+0x6a/0x270 [ 65.923087] load_module+0x1fce/0x23a0 [ 65.923087] init_module_from_file+0x9c/0xe0 [ 65.923087] ? init_module_from_file+0x9c/0xe0 [ 65.923087] idempotent_init_module+0x179/0x230 [ 65.923087] __x64_sys_finit_module+0x5d/0xa0 [ 65.923087] do_syscall_64+0x76/0x120 [ 65.923087] entry_SYSCALL_64_after_hwframe+0x6e/0x76 [ 65.923087] RIP: 0033:0x7f2d80f1e88d [ 65.923087] Code: 5b 41 5c c3 66 0f 1f 84 00 00 00 00 00 f3 0f 1e fa 48 89 f8 48 89 f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08 0f 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d 73 b5 0f 00 f7 d8 64 89 01 48 [ 65.923087] RSP: 002b:00007ffc7bc1aa78 EFLAGS: 00000246 ORIG_RAX: 0000000000000139 [ 65.923087] RAX: ffffffffffffffda RBX: 0000564c9c1db130 RCX: 00007f2d80f1e88d [ 65.923087] RDX: 0000000000000000 RSI: 0000564c9c1e5480 RDI: 000000000000000f [ 65.923087] RBP: 0000000000040000 R08: 0000000000000000 R09: 0000000000000002 [ 65.923087] R10: 000000000000000f R11: 0000000000000246 R12: 0000564c9c1e5480 [ 65.923087] R13: 0000564c9c1db260 R14: 0000000000000000 R15: 0000564c9c1e54b0 [ 65.923087] [ 65.923927] ---[ end trace ]--- Cc: Tom Chung Cc: Rodrigo Siqueira Cc: Roman Li Cc: Alex Hung Cc: Aurabindo Pillai Cc: Harry Wentland Cc: Hamza Mahfooz Signed-off-by: Srinivasan Shanmugam Reviewed-by: Roman Li --- drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c index 228fe25077a7d..7d82b75ed66b9 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c @@ -1297,7 +1297,7 @@ static struct link_encoder *dcn21_link_encoder_create( kzalloc(sizeof(struct dcn21_link_encoder), GFP_KERNEL); int link_regs_id; - if (!enc21) + if (!enc21 || enc_init_data->hpd_source >= ARRAY_SIZE(link_enc_hpd_regs)) return NULL; link_regs_id = From 4f21b7e12c7528be1369c2782f0a03f08c3006fb Mon Sep 17 00:00:00 2001 From: Alex Hung Date: Wed, 18 Sep 2024 20:45:51 -0600 Subject: [PATCH 1692/1868] drm/amd/display: Eliminate recursive header inclusion [WHAT & HOW] This removes recursive inclusion like dc.h -> dc_state.h -> dc.h and dc.h -> dc_plane.h -> dc.h This fixes 4 PW.INCLUDE_RECURSION issues reported by Coverity. Reviewed-by: Rodrigo Siqueira Signed-off-by: Alex Hung Signed-off-by: Fangzhi Zuo Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/dc_plane.h | 1 - drivers/gpu/drm/amd/display/dc/dc_state.h | 1 - 2 files changed, 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc_plane.h b/drivers/gpu/drm/amd/display/dc/dc_plane.h index 44afcd9892248..bd37ec82b42d1 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_plane.h +++ b/drivers/gpu/drm/amd/display/dc/dc_plane.h @@ -26,7 +26,6 @@ #ifndef _DC_PLANE_H_ #define _DC_PLANE_H_ -#include "dc.h" #include "dc_hw_types.h" struct dc_plane_state *dc_create_plane_state(const struct dc *dc); diff --git a/drivers/gpu/drm/amd/display/dc/dc_state.h b/drivers/gpu/drm/amd/display/dc/dc_state.h index caa45db502329..db1e63a7d460e 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_state.h +++ b/drivers/gpu/drm/amd/display/dc/dc_state.h @@ -26,7 +26,6 @@ #ifndef _DC_STATE_H_ #define _DC_STATE_H_ -#include "dc.h" #include "inc/core_status.h" struct dc_state *dc_state_create(struct dc *dc, struct dc_state_create_params *params); From b11f1aa7313a43e55a91ae6af3473ca4792b4d49 Mon Sep 17 00:00:00 2001 From: Alex Hung Date: Thu, 19 Sep 2024 18:46:48 -0600 Subject: [PATCH 1693/1868] drm/amd/display: Removed unused assignments and variables [WHAT] A number of values are assigned to variables but the stored values are not used afterwards. [HOW] The assignments are removed. If the variables are not used, they are removed as well. This fixes 9 UNUSED_VALUE issues reported by Coverity. Reviewed-by: Rodrigo Siqueira Signed-off-by: Alex Hung Signed-off-by: Fangzhi Zuo Tested-by: Daniel Wheeler --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 3 -- .../amd/display/amdgpu_dm/amdgpu_dm_debugfs.c | 48 ++++--------------- 2 files changed, 8 insertions(+), 43 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 843c729315e2b..6bef25af62b92 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -12552,9 +12552,6 @@ void amdgpu_dm_update_freesync_caps(struct drm_connector *connector, } else if (edid && sink->sink_signal == SIGNAL_TYPE_HDMI_TYPE_A) { i = parse_hdmi_amd_vsdb(amdgpu_dm_connector, edid, &vsdb_info); if (i >= 0 && vsdb_info.freesync_supported) { - timing = &edid->detailed_timings[i]; - data = &timing->data.other_data; - amdgpu_dm_connector->min_vfreq = vsdb_info.min_refresh_rate_hz; amdgpu_dm_connector->max_vfreq = vsdb_info.max_refresh_rate_hz; if (amdgpu_dm_connector->max_vfreq - amdgpu_dm_connector->min_vfreq > 10) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c index d07f25f611b47..a71e0cd90cd6f 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c @@ -1532,7 +1532,6 @@ static ssize_t dp_dsc_clock_en_read(struct file *f, char __user *buf, size_t size, loff_t *pos) { char *rd_buf = NULL; - char *rd_buf_ptr = NULL; struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; struct display_stream_compressor *dsc; struct dcn_dsc_state dsc_state = {0}; @@ -1546,8 +1545,6 @@ static ssize_t dp_dsc_clock_en_read(struct file *f, char __user *buf, if (!rd_buf) return -ENOMEM; - rd_buf_ptr = rd_buf; - for (i = 0; i < MAX_PIPES; i++) { pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; if (pipe_ctx->stream && @@ -1561,10 +1558,9 @@ static ssize_t dp_dsc_clock_en_read(struct file *f, char __user *buf, if (dsc) dsc->funcs->dsc_read_state(dsc, &dsc_state); - snprintf(rd_buf_ptr, str_len, + snprintf(rd_buf, str_len, "%d\n", dsc_state.dsc_clock_en); - rd_buf_ptr += str_len; while (size) { if (*pos >= rd_buf_size) @@ -1722,7 +1718,6 @@ static ssize_t dp_dsc_slice_width_read(struct file *f, char __user *buf, size_t size, loff_t *pos) { char *rd_buf = NULL; - char *rd_buf_ptr = NULL; struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; struct display_stream_compressor *dsc; struct dcn_dsc_state dsc_state = {0}; @@ -1736,8 +1731,6 @@ static ssize_t dp_dsc_slice_width_read(struct file *f, char __user *buf, if (!rd_buf) return -ENOMEM; - rd_buf_ptr = rd_buf; - for (i = 0; i < MAX_PIPES; i++) { pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; if (pipe_ctx->stream && @@ -1751,10 +1744,9 @@ static ssize_t dp_dsc_slice_width_read(struct file *f, char __user *buf, if (dsc) dsc->funcs->dsc_read_state(dsc, &dsc_state); - snprintf(rd_buf_ptr, str_len, + snprintf(rd_buf, str_len, "%d\n", dsc_state.dsc_slice_width); - rd_buf_ptr += str_len; while (size) { if (*pos >= rd_buf_size) @@ -1910,7 +1902,6 @@ static ssize_t dp_dsc_slice_height_read(struct file *f, char __user *buf, size_t size, loff_t *pos) { char *rd_buf = NULL; - char *rd_buf_ptr = NULL; struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; struct display_stream_compressor *dsc; struct dcn_dsc_state dsc_state = {0}; @@ -1924,8 +1915,6 @@ static ssize_t dp_dsc_slice_height_read(struct file *f, char __user *buf, if (!rd_buf) return -ENOMEM; - rd_buf_ptr = rd_buf; - for (i = 0; i < MAX_PIPES; i++) { pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; if (pipe_ctx->stream && @@ -1939,10 +1928,9 @@ static ssize_t dp_dsc_slice_height_read(struct file *f, char __user *buf, if (dsc) dsc->funcs->dsc_read_state(dsc, &dsc_state); - snprintf(rd_buf_ptr, str_len, + snprintf(rd_buf, str_len, "%d\n", dsc_state.dsc_slice_height); - rd_buf_ptr += str_len; while (size) { if (*pos >= rd_buf_size) @@ -2094,7 +2082,6 @@ static ssize_t dp_dsc_bits_per_pixel_read(struct file *f, char __user *buf, size_t size, loff_t *pos) { char *rd_buf = NULL; - char *rd_buf_ptr = NULL; struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; struct display_stream_compressor *dsc; struct dcn_dsc_state dsc_state = {0}; @@ -2108,8 +2095,6 @@ static ssize_t dp_dsc_bits_per_pixel_read(struct file *f, char __user *buf, if (!rd_buf) return -ENOMEM; - rd_buf_ptr = rd_buf; - for (i = 0; i < MAX_PIPES; i++) { pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; if (pipe_ctx->stream && @@ -2123,10 +2108,9 @@ static ssize_t dp_dsc_bits_per_pixel_read(struct file *f, char __user *buf, if (dsc) dsc->funcs->dsc_read_state(dsc, &dsc_state); - snprintf(rd_buf_ptr, str_len, + snprintf(rd_buf, str_len, "%d\n", dsc_state.dsc_bits_per_pixel); - rd_buf_ptr += str_len; while (size) { if (*pos >= rd_buf_size) @@ -2273,7 +2257,6 @@ static ssize_t dp_dsc_pic_width_read(struct file *f, char __user *buf, size_t size, loff_t *pos) { char *rd_buf = NULL; - char *rd_buf_ptr = NULL; struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; struct display_stream_compressor *dsc; struct dcn_dsc_state dsc_state = {0}; @@ -2287,8 +2270,6 @@ static ssize_t dp_dsc_pic_width_read(struct file *f, char __user *buf, if (!rd_buf) return -ENOMEM; - rd_buf_ptr = rd_buf; - for (i = 0; i < MAX_PIPES; i++) { pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; if (pipe_ctx->stream && @@ -2302,10 +2283,9 @@ static ssize_t dp_dsc_pic_width_read(struct file *f, char __user *buf, if (dsc) dsc->funcs->dsc_read_state(dsc, &dsc_state); - snprintf(rd_buf_ptr, str_len, + snprintf(rd_buf, str_len, "%d\n", dsc_state.dsc_pic_width); - rd_buf_ptr += str_len; while (size) { if (*pos >= rd_buf_size) @@ -2331,7 +2311,6 @@ static ssize_t dp_dsc_pic_height_read(struct file *f, char __user *buf, size_t size, loff_t *pos) { char *rd_buf = NULL; - char *rd_buf_ptr = NULL; struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; struct display_stream_compressor *dsc; struct dcn_dsc_state dsc_state = {0}; @@ -2345,8 +2324,6 @@ static ssize_t dp_dsc_pic_height_read(struct file *f, char __user *buf, if (!rd_buf) return -ENOMEM; - rd_buf_ptr = rd_buf; - for (i = 0; i < MAX_PIPES; i++) { pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; if (pipe_ctx->stream && @@ -2360,10 +2337,9 @@ static ssize_t dp_dsc_pic_height_read(struct file *f, char __user *buf, if (dsc) dsc->funcs->dsc_read_state(dsc, &dsc_state); - snprintf(rd_buf_ptr, str_len, + snprintf(rd_buf, str_len, "%d\n", dsc_state.dsc_pic_height); - rd_buf_ptr += str_len; while (size) { if (*pos >= rd_buf_size) @@ -2404,7 +2380,6 @@ static ssize_t dp_dsc_chunk_size_read(struct file *f, char __user *buf, size_t size, loff_t *pos) { char *rd_buf = NULL; - char *rd_buf_ptr = NULL; struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; struct display_stream_compressor *dsc; struct dcn_dsc_state dsc_state = {0}; @@ -2418,8 +2393,6 @@ static ssize_t dp_dsc_chunk_size_read(struct file *f, char __user *buf, if (!rd_buf) return -ENOMEM; - rd_buf_ptr = rd_buf; - for (i = 0; i < MAX_PIPES; i++) { pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; if (pipe_ctx->stream && @@ -2433,10 +2406,9 @@ static ssize_t dp_dsc_chunk_size_read(struct file *f, char __user *buf, if (dsc) dsc->funcs->dsc_read_state(dsc, &dsc_state); - snprintf(rd_buf_ptr, str_len, + snprintf(rd_buf, str_len, "%d\n", dsc_state.dsc_chunk_size); - rd_buf_ptr += str_len; while (size) { if (*pos >= rd_buf_size) @@ -2477,7 +2449,6 @@ static ssize_t dp_dsc_slice_bpg_offset_read(struct file *f, char __user *buf, size_t size, loff_t *pos) { char *rd_buf = NULL; - char *rd_buf_ptr = NULL; struct amdgpu_dm_connector *aconnector = file_inode(f)->i_private; struct display_stream_compressor *dsc; struct dcn_dsc_state dsc_state = {0}; @@ -2491,8 +2462,6 @@ static ssize_t dp_dsc_slice_bpg_offset_read(struct file *f, char __user *buf, if (!rd_buf) return -ENOMEM; - rd_buf_ptr = rd_buf; - for (i = 0; i < MAX_PIPES; i++) { pipe_ctx = &aconnector->dc_link->dc->current_state->res_ctx.pipe_ctx[i]; if (pipe_ctx->stream && @@ -2506,10 +2475,9 @@ static ssize_t dp_dsc_slice_bpg_offset_read(struct file *f, char __user *buf, if (dsc) dsc->funcs->dsc_read_state(dsc, &dsc_state); - snprintf(rd_buf_ptr, str_len, + snprintf(rd_buf, str_len, "%d\n", dsc_state.dsc_slice_bpg_offset); - rd_buf_ptr += str_len; while (size) { if (*pos >= rd_buf_size) From 849e414f06f307dc363e8285e5c632ebf08431f4 Mon Sep 17 00:00:00 2001 From: Ovidiu Bunea Date: Wed, 31 Jul 2024 14:18:08 -0400 Subject: [PATCH 1694/1868] drm/amd/display: Add IPS residency capture helpers to dc_dmub_srv This enables starting and stopping IPS residency measurements and querying the IPS residency information consisting of residency percent, entry counter, total time active & inactive, and histograms for the specified IPS mode. Reviewed-by: Nicholas Kazlauskas Reviewed-by: Aric Cyr Signed-off-by: Ovidiu Bunea Signed-off-by: Fangzhi Zuo Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 78 +++++++++++++++ drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h | 39 ++++++++ drivers/gpu/drm/amd/display/dmub/dmub_srv.h | 8 ++ .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 95 +++++++++++++++++++ 4 files changed, 220 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c index 1e7de0f03290a..9291f078ffde7 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c +++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c @@ -1862,3 +1862,81 @@ void dc_dmub_srv_fams2_passthrough_flip( dm_execute_dmub_cmd_list(dc->ctx, num_cmds, cmds, DM_DMUB_WAIT_TYPE_WAIT); } } + +bool dc_dmub_srv_ips_residency_cntl(struct dc_dmub_srv *dc_dmub_srv, bool start_measurement) +{ + bool result; + + if (!dc_dmub_srv || !dc_dmub_srv->dmub) + return false; + + result = dc_wake_and_execute_gpint(dc_dmub_srv->ctx, DMUB_GPINT__IPS_RESIDENCY, + start_measurement, NULL, DM_DMUB_WAIT_TYPE_WAIT); + + return result; +} + +void dc_dmub_srv_ips_query_residency_info(struct dc_dmub_srv *dc_dmub_srv, struct ips_residency_info *output) +{ + uint32_t i; + enum dmub_gpint_command command_code; + + if (!dc_dmub_srv || !dc_dmub_srv->dmub) + return; + + switch (output->ips_mode) { + case DMUB_IPS_MODE_IPS1_MAX: + command_code = DMUB_GPINT__GET_IPS1_HISTOGRAM_COUNTER; + break; + case DMUB_IPS_MODE_IPS2: + command_code = DMUB_GPINT__GET_IPS2_HISTOGRAM_COUNTER; + break; + case DMUB_IPS_MODE_IPS1_RCG: + command_code = DMUB_GPINT__GET_IPS1_RCG_HISTOGRAM_COUNTER; + break; + case DMUB_IPS_MODE_IPS1_ONO2_ON: + command_code = DMUB_GPINT__GET_IPS1_ONO2_ON_HISTOGRAM_COUNTER; + break; + default: + command_code = DMUB_GPINT__INVALID_COMMAND; + break; + } + + if (command_code == DMUB_GPINT__INVALID_COMMAND) + return; + + // send gpint commands and wait for ack + if (!dc_wake_and_execute_gpint(dc_dmub_srv->ctx, DMUB_GPINT__GET_IPS_RESIDENCY_PERCENT, + (uint16_t)(output->ips_mode), + &output->residency_percent, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY)) + output->residency_percent = 0; + + if (!dc_wake_and_execute_gpint(dc_dmub_srv->ctx, DMUB_GPINT__GET_IPS_RESIDENCY_ENTRY_COUNTER, + (uint16_t)(output->ips_mode), + &output->entry_counter, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY)) + output->entry_counter = 0; + + if (!dc_wake_and_execute_gpint(dc_dmub_srv->ctx, DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_LO, + (uint16_t)(output->ips_mode), + &output->total_active_time_us[0], DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY)) + output->total_active_time_us[0] = 0; + if (!dc_wake_and_execute_gpint(dc_dmub_srv->ctx, DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_HI, + (uint16_t)(output->ips_mode), + &output->total_active_time_us[1], DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY)) + output->total_active_time_us[1] = 0; + + if (!dc_wake_and_execute_gpint(dc_dmub_srv->ctx, DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_LO, + (uint16_t)(output->ips_mode), + &output->total_inactive_time_us[0], DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY)) + output->total_inactive_time_us[0] = 0; + if (!dc_wake_and_execute_gpint(dc_dmub_srv->ctx, DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_HI, + (uint16_t)(output->ips_mode), + &output->total_inactive_time_us[1], DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY)) + output->total_inactive_time_us[1] = 0; + + // NUM_IPS_HISTOGRAM_BUCKETS = 16 + for (i = 0; i < 16; i++) + if (!dc_wake_and_execute_gpint(dc_dmub_srv->ctx, command_code, i, &output->histogram[i], + DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY)) + output->histogram[i] = 0; +} diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h index 42f0cb672d8bb..10b48198b7a62 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h +++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.h @@ -209,4 +209,43 @@ void dc_dmub_srv_fams2_passthrough_flip( struct dc_stream_state *stream, struct dc_surface_update *srf_updates, int surface_count); + +/** + * struct ips_residency_info - struct containing info from dmub_ips_residency_stats + * + * @ips_mode: The mode of IPS that the follow stats appertain to + * @residency_percent: The percentage of time spent in given IPS mode in millipercent + * @entry_counter: The number of entries made in to this IPS state + * @total_active_time_us: uint32_t array of length 2 representing time in the given IPS mode + * in microseconds. Index 0 is lower 32 bits, index 1 is upper 32 bits. + * @total_inactive_time_us: uint32_t array of length 2 representing time outside the given IPS mode + * in microseconds. Index 0 is lower 32 bits, index 1 is upper 32 bits. + * @histogram: Histogram of given IPS state durations - bucket definitions in dmub_ips.c + */ +struct ips_residency_info { + enum dmub_ips_mode ips_mode; + unsigned int residency_percent; + unsigned int entry_counter; + unsigned int total_active_time_us[2]; + unsigned int total_inactive_time_us[2]; + unsigned int histogram[16]; +}; + +/** + * bool dc_dmub_srv_ips_residency_cntl() - Controls IPS residency measurement status + * + * @dc_dmub_srv: The DC DMUB service pointer + * @start_measurement: Describes whether to start or stop measurement + * + * Return: true if GPINT was sent successfully, false otherwise + */ +bool dc_dmub_srv_ips_residency_cntl(struct dc_dmub_srv *dc_dmub_srv, bool start_measurement); + +/** + * bool dc_dmub_srv_ips_query_residency_info() - Queries DMCUB for residency info + * + * @dc_dmub_srv: The DC DMUB service pointer + * @output: Output struct to copy the the residency info to + */ +void dc_dmub_srv_ips_query_residency_info(struct dc_dmub_srv *dc_dmub_srv, struct ips_residency_info *output); #endif /* _DMUB_DC_SRV_H_ */ diff --git a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h index fe5b6f7a3eb1e..ff27229cc3a47 100644 --- a/drivers/gpu/drm/amd/display/dmub/dmub_srv.h +++ b/drivers/gpu/drm/amd/display/dmub/dmub_srv.h @@ -570,6 +570,14 @@ struct dmub_notification { }; }; +/* enum dmub_ips_mode - IPS mode identifier */ +enum dmub_ips_mode { + DMUB_IPS_MODE_IPS1_MAX = 0, + DMUB_IPS_MODE_IPS2, + DMUB_IPS_MODE_IPS1_RCG, + DMUB_IPS_MODE_IPS1_ONO2_ON +}; + /** * DMUB firmware version helper macro - useful for checking if the version * of a firmware to know if feature or functionality is supported or present. diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index ebcf68bfae2b3..3296788731ec7 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -1050,12 +1050,107 @@ enum dmub_gpint_command { */ DMUB_GPINT__GET_TRACE_BUFFER_MASK_WORD3 = 119, + /** + * DESC: Set IPS residency measurement + * ARGS: 0 - Disable ips measurement + * 1 - Enable ips measurement + */ + DMUB_GPINT__IPS_RESIDENCY = 121, + /** * DESC: Enable measurements for various task duration * ARGS: 0 - Disable measurement * 1 - Enable measurement */ DMUB_GPINT__TRACE_DMUB_WAKE_ACTIVITY = 123, + + /** + * DESC: Gets IPS residency in microseconds + * ARGS: 0 - Return IPS1 residency + * 1 - Return IPS2 residency + * 2 - Return IPS1_RCG residency + * 3 - Return IPS1_ONO2_ON residency + * RETURN: Total residency in microseconds - lower 32 bits + */ + DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_LO = 124, + + /** + * DESC: Gets IPS1 histogram counts + * ARGS: Bucket index + * RETURN: Total count for the bucket + */ + DMUB_GPINT__GET_IPS1_HISTOGRAM_COUNTER = 125, + + /** + * DESC: Gets IPS2 histogram counts + * ARGS: Bucket index + * RETURN: Total count for the bucket + */ + DMUB_GPINT__GET_IPS2_HISTOGRAM_COUNTER = 126, + + /** + * DESC: Gets IPS residency + * ARGS: 0 - Return IPS1 residency + * 1 - Return IPS2 residency + * 2 - Return IPS1_RCG residency + * 3 - Return IPS1_ONO2_ON residency + * RETURN: Total residency in milli-percent. + */ + DMUB_GPINT__GET_IPS_RESIDENCY_PERCENT = 127, + + /** + * DESC: Gets IPS1_RCG histogram counts + * ARGS: Bucket index + * RETURN: Total count for the bucket + */ + DMUB_GPINT__GET_IPS1_RCG_HISTOGRAM_COUNTER = 128, + + /** + * DESC: Gets IPS1_ONO2_ON histogram counts + * ARGS: Bucket index + * RETURN: Total count for the bucket + */ + DMUB_GPINT__GET_IPS1_ONO2_ON_HISTOGRAM_COUNTER = 129, + + /** + * DESC: Gets IPS entry counter during residency measurement + * ARGS: 0 - Return IPS1 entry counts + * 1 - Return IPS2 entry counts + * 2 - Return IPS1_RCG entry counts + * 3 - Return IPS2_ONO2_ON entry counts + * RETURN: Entry counter for selected IPS mode + */ + DMUB_GPINT__GET_IPS_RESIDENCY_ENTRY_COUNTER = 130, + + /** + * DESC: Gets IPS inactive residency in microseconds + * ARGS: 0 - Return IPS1_MAX residency + * 1 - Return IPS2 residency + * 2 - Return IPS1_RCG residency + * 3 - Return IPS1_ONO2_ON residency + * RETURN: Total inactive residency in microseconds - lower 32 bits + */ + DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_LO = 131, + + /** + * DESC: Gets IPS inactive residency in microseconds + * ARGS: 0 - Return IPS1_MAX residency + * 1 - Return IPS2 residency + * 2 - Return IPS1_RCG residency + * 3 - Return IPS1_ONO2_ON residency + * RETURN: Total inactive residency in microseconds - upper 32 bits + */ + DMUB_GPINT__GET_IPS_INACTIVE_RESIDENCY_DURATION_US_HI = 132, + + /** + * DESC: Gets IPS residency in microseconds + * ARGS: 0 - Return IPS1 residency + * 1 - Return IPS2 residency + * 2 - Return IPS1_RCG residency + * 3 - Return IPS1_ONO2_ON residency + * RETURN: Total residency in microseconds - upper 32 bits + */ + DMUB_GPINT__GET_IPS_RESIDENCY_DURATION_US_HI = 133, }; /** From 65c27969a6ae1ed8c226aea8da416ffde6d26ba9 Mon Sep 17 00:00:00 2001 From: Dillon Varone Date: Fri, 20 Sep 2024 16:56:20 -0400 Subject: [PATCH 1695/1868] drm/amd/display: Configure DTBCLK_P with OPTC only for dcn401 [WHY] DTBCLK_P is used to generate virtual pixel clock, and to drive the HPO stream encoder clock. Programming the required clock when enabling/disabling both components can cause issues. For example, if HPO is being disabled and clock source is changed to REFCLK, virtual pixel rate will then be wrong, causing issues in CRTC. [HOW] Only program the DTBCLK_P when programming CRTC, as its expected it will be enabled prior to HPO, and disabled after HPO in all valid cases. Reviewed-by: Alvin Lee Signed-off-by: Dillon Varone Signed-off-by: Fangzhi Zuo Tested-by: Daniel Wheeler --- .../amd/display/dc/dccg/dcn401/dcn401_dccg.c | 3 - .../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 135 +++++++++++++++++- .../amd/display/dc/hwss/dcn401/dcn401_hwseq.h | 7 + .../amd/display/dc/hwss/dcn401/dcn401_init.c | 4 +- 4 files changed, 142 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c index 5babd53025aef..d3e46c3cfa575 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c @@ -580,9 +580,6 @@ static void dccg401_set_dpstreamclk( int otg_inst, int dp_hpo_inst) { - /* set the dtbclk_p source */ - dccg401_set_dtbclk_p_src(dccg, src, otg_inst); - /* enabled to select one of the DTBCLKs for pipe */ if (src == REFCLK) dccg401_disable_dpstreamclk(dccg, dp_hpo_inst); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c index b690f0565d285..49a37f5ee28e7 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c @@ -844,6 +844,13 @@ enum dc_status dcn401_enable_stream_timing( odm_slice_width, last_odm_slice_width); } + /* set DTBCLK_P */ + if (dc->res_pool->dccg->funcs->set_dtbclk_p_src) { + if (dc_is_dp_signal(stream->signal) || dc_is_virtual_signal(stream->signal)) { + dc->res_pool->dccg->funcs->set_dtbclk_p_src(dc->res_pool->dccg, DPREFCLK, pipe_ctx->stream_res.tg->inst); + } + } + /* HW program guide assume display already disable * by unplug sequence. OTG assume stop. */ @@ -1004,8 +1011,6 @@ void dcn401_enable_stream(struct pipe_ctx *pipe_ctx) dccg->funcs->enable_symclk32_se(dccg, dp_hpo_inst, phyd32clk); } else { - /* need to set DTBCLK_P source to DPREFCLK for DP8B10B */ - dccg->funcs->set_dtbclk_p_src(dccg, DPREFCLK, tg->inst); dccg->funcs->enable_symclk_se(dccg, stream_enc->stream_enc_inst, link_enc->transmitter - TRANSMITTER_UNIPHY_A); } @@ -1819,3 +1824,129 @@ void dcn401_program_outstanding_updates(struct dc *dc, if (hubbub->funcs->program_compbuf_segments) hubbub->funcs->program_compbuf_segments(hubbub, context->bw_ctx.bw.dcn.arb_regs.compbuf_size, true); } + +void dcn401_reset_back_end_for_pipe( + struct dc *dc, + struct pipe_ctx *pipe_ctx, + struct dc_state *context) +{ + int i; + struct dc_link *link = pipe_ctx->stream->link; + const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); + + DC_LOGGER_INIT(dc->ctx->logger); + if (pipe_ctx->stream_res.stream_enc == NULL) { + pipe_ctx->stream = NULL; + return; + } + + /* DPMS may already disable or */ + /* dpms_off status is incorrect due to fastboot + * feature. When system resume from S4 with second + * screen only, the dpms_off would be true but + * VBIOS lit up eDP, so check link status too. + */ + if (!pipe_ctx->stream->dpms_off || link->link_status.link_active) + dc->link_srv->set_dpms_off(pipe_ctx); + else if (pipe_ctx->stream_res.audio) + dc->hwss.disable_audio_stream(pipe_ctx); + + /* free acquired resources */ + if (pipe_ctx->stream_res.audio) { + /*disable az_endpoint*/ + pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio); + + /*free audio*/ + if (dc->caps.dynamic_audio == true) { + /*we have to dynamic arbitrate the audio endpoints*/ + /*we free the resource, need reset is_audio_acquired*/ + update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, + pipe_ctx->stream_res.audio, false); + pipe_ctx->stream_res.audio = NULL; + } + } + + /* by upper caller loop, parent pipe: pipe0, will be reset last. + * back end share by all pipes and will be disable only when disable + * parent pipe. + */ + if (pipe_ctx->top_pipe == NULL) { + + dc->hwss.set_abm_immediate_disable(pipe_ctx); + + pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg); + + pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false); + if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass) + pipe_ctx->stream_res.tg->funcs->set_odm_bypass( + pipe_ctx->stream_res.tg, &pipe_ctx->stream->timing); + + if (pipe_ctx->stream_res.tg->funcs->set_drr) + pipe_ctx->stream_res.tg->funcs->set_drr( + pipe_ctx->stream_res.tg, NULL); + /* TODO - convert symclk_ref_cnts for otg to a bit map to solve + * the case where the same symclk is shared across multiple otg + * instances + */ + if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal)) + link->phy_state.symclk_ref_cnts.otg = 0; + if (link->phy_state.symclk_state == SYMCLK_ON_TX_OFF) { + link_hwss->disable_link_output(link, + &pipe_ctx->link_res, pipe_ctx->stream->signal); + link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF; + } + + /* reset DTBCLK_P */ + if (dc->res_pool->dccg->funcs->set_dtbclk_p_src) + dc->res_pool->dccg->funcs->set_dtbclk_p_src(dc->res_pool->dccg, REFCLK, pipe_ctx->stream_res.tg->inst); + } + + for (i = 0; i < dc->res_pool->pipe_count; i++) + if (&dc->current_state->res_ctx.pipe_ctx[i] == pipe_ctx) + break; + + if (i == dc->res_pool->pipe_count) + return; + +/* + * In case of a dangling plane, setting this to NULL unconditionally + * causes failures during reset hw ctx where, if stream is NULL, + * it is expected that the pipe_ctx pointers to pipes and plane are NULL. + */ + pipe_ctx->stream = NULL; + DC_LOG_DEBUG("Reset back end for pipe %d, tg:%d\n", + pipe_ctx->pipe_idx, pipe_ctx->stream_res.tg->inst); +} + +void dcn401_reset_hw_ctx_wrap( + struct dc *dc, + struct dc_state *context) +{ + int i; + struct dce_hwseq *hws = dc->hwseq; + + /* Reset Back End*/ + for (i = dc->res_pool->pipe_count - 1; i >= 0 ; i--) { + struct pipe_ctx *pipe_ctx_old = + &dc->current_state->res_ctx.pipe_ctx[i]; + struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; + + if (!pipe_ctx_old->stream) + continue; + + if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe) + continue; + + if (!pipe_ctx->stream || + pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { + struct clock_source *old_clk = pipe_ctx_old->clock_source; + + if (hws->funcs.reset_back_end_for_pipe) + hws->funcs.reset_back_end_for_pipe(dc, pipe_ctx_old, dc->current_state); + if (hws->funcs.enable_stream_gating) + hws->funcs.enable_stream_gating(dc, pipe_ctx_old); + if (old_clk) + old_clk->funcs->cs_power_down(old_clk); + } + } +} diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h index e6692cd905d65..66d679080c449 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.h @@ -88,4 +88,11 @@ void adjust_hotspot_between_slices_for_2x_magnify(uint32_t cursor_width, struct void dcn401_wait_for_det_buffer_update_under_otg_master(struct dc *dc, struct dc_state *context, struct pipe_ctx *otg_master); void dcn401_interdependent_update_lock(struct dc *dc, struct dc_state *context, bool lock); void dcn401_program_outstanding_updates(struct dc *dc, struct dc_state *context); +void dcn401_reset_back_end_for_pipe( + struct dc *dc, + struct pipe_ctx *pipe_ctx, + struct dc_state *context); +void dcn401_reset_hw_ctx_wrap( + struct dc *dc, + struct dc_state *context); #endif /* __DC_HWSS_DCN401_H__ */ diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c index d1128a8082a5e..af0d40a5cb77a 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c @@ -112,7 +112,7 @@ static const struct hwseq_private_funcs dcn401_private_funcs = { .power_down = dce110_power_down, .enable_display_power_gating = dcn10_dummy_display_power_gating, .blank_pixel_data = dcn20_blank_pixel_data, - .reset_hw_ctx_wrap = dcn20_reset_hw_ctx_wrap, + .reset_hw_ctx_wrap = dcn401_reset_hw_ctx_wrap, .enable_stream_timing = dcn401_enable_stream_timing, .edp_backlight_control = dce110_edp_backlight_control, .setup_vupdate_interrupt = dcn20_setup_vupdate_interrupt, @@ -137,7 +137,7 @@ static const struct hwseq_private_funcs dcn401_private_funcs = { .update_mall_sel = dcn32_update_mall_sel, .calculate_dccg_k1_k2_values = NULL, .apply_single_controller_ctx_to_hw = dce110_apply_single_controller_ctx_to_hw, - .reset_back_end_for_pipe = dcn20_reset_back_end_for_pipe, + .reset_back_end_for_pipe = dcn401_reset_back_end_for_pipe, .populate_mcm_luts = NULL, }; From 001072e6d1d26e46668b97fcd448bd27708bdde8 Mon Sep 17 00:00:00 2001 From: Taimur Hassan Date: Mon, 23 Sep 2024 01:37:51 -0400 Subject: [PATCH 1696/1868] drm/amd/display: [FW Promotion] Release 0.0.236.0 Reviewed-by: Zaeem Mohamed Signed-off-by: Taimur Hassan Signed-off-by: Fangzhi Zuo Tested-by: Daniel Wheeler --- .../gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 62 +++++++++++++++++-- 1 file changed, 57 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index 3296788731ec7..05d352c7b1d3c 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -1401,9 +1401,10 @@ enum dmub_out_cmd_type { /* DMUB_CMD__DPIA command sub-types. */ enum dmub_cmd_dpia_type { DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0, - DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, + DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1, // will be replaced by DPIA_SET_CONFIG_REQUEST DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2, DMUB_CMD__DPIA_SET_TPS_NOTIFICATION = 3, + DMUB_CMD__DPIA_SET_CONFIG_REQUEST = 4, }; /* DMUB_OUT_CMD__DPIA_NOTIFICATION command types. */ @@ -2192,7 +2193,7 @@ struct dmub_rb_cmd_dig1_dpia_control { }; /** - * SET_CONFIG Command Payload + * SET_CONFIG Command Payload (deprecated) */ struct set_config_cmd_payload { uint8_t msg_type; /* set config message type */ @@ -2200,7 +2201,7 @@ struct set_config_cmd_payload { }; /** - * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. + * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. (deprecated) */ struct dmub_cmd_set_config_control_data { struct set_config_cmd_payload cmd_pkt; @@ -2208,6 +2209,17 @@ struct dmub_cmd_set_config_control_data { uint8_t immed_status; /* Immediate status returned in case of error */ }; +/** + * SET_CONFIG Request Command Payload + */ +struct set_config_request_cmd_payload { + uint8_t instance; /* DPIA instance */ + uint8_t immed_status; /* Immediate status returned in case of error */ + uint8_t msg_type; /* set config message type */ + uint8_t reserved; + uint32_t msg_data; /* set config message data */ +}; + /** * DMUB command structure for SET_CONFIG command. */ @@ -2216,6 +2228,14 @@ struct dmub_rb_cmd_set_config_access { struct dmub_cmd_set_config_control_data set_config_control; /* set config data */ }; +/** + * DMUB command structure for SET_CONFIG request command. + */ +struct dmub_rb_cmd_set_config_request { + struct dmub_cmd_header header; /* header */ + struct set_config_request_cmd_payload payload; /* set config request payload */ +}; + /** * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. */ @@ -4410,10 +4430,38 @@ struct dmub_cmd_abm_set_backlight_data { */ uint8_t panel_mask; + /** + * Backlight control type. + * Value 0 is PWM backlight control. + * Value 1 is VAUX backlight control. + * Value 2 is AMD DPCD AUX backlight control. + */ + uint8_t backlight_control_type; + /** * Explicit padding to 4 byte boundary. */ - uint8_t pad[2]; + uint8_t pad[1]; + + /** + * Minimum luminance in nits. + */ + uint32_t min_luminance; + + /** + * Maximum luminance in nits. + */ + uint32_t max_luminance; + + /** + * Minimum backlight in pwm. + */ + uint32_t min_backlight_pwm; + + /** + * Maximum backlight in pwm. + */ + uint32_t max_backlight_pwm; }; /** @@ -5413,7 +5461,11 @@ union dmub_rb_cmd { /** * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. */ - struct dmub_rb_cmd_set_config_access set_config_access; + struct dmub_rb_cmd_set_config_access set_config_access; // (deprecated) + /** + * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command. + */ + struct dmub_rb_cmd_set_config_request set_config_request; /** * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command. */ From 49cb81eea162b8b77b1dd85a5443929bf84bd2ac Mon Sep 17 00:00:00 2001 From: Aric Cyr Date: Mon, 23 Sep 2024 09:14:59 -0400 Subject: [PATCH 1697/1868] drm/amd/display: 3.2.303 DC 3.2.303 contains some improvements as summarized below: * Improve brightness control * Add support for UHBR10 eDP * OPTC required only for DTBCLK_P for dcn401 * Fix TBT monitor resume issue * Code cleanup Reviewed-by: Zaeem Mohamed Signed-off-by: Aric Cyr Signed-off-by: Fangzhi Zuo Tested-by: Daniel Wheeler --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index cec44579cb9f5..36e059c55dc50 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -55,7 +55,7 @@ struct aux_payload; struct set_config_cmd_payload; struct dmub_notification; -#define DC_VER "3.2.302" +#define DC_VER "3.2.303" #define MAX_SURFACES 3 #define MAX_PLANES 6 From e5774c5fc90d34ec9b03ec0f70d88d550e21787b Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Tue, 1 Oct 2024 10:21:30 +0800 Subject: [PATCH 1698/1868] Revert "drm/amdgpu/sdma5: split out per instance resume function" This reverts commit e1baa1ac2b7e62ee1e09ab8492911ac75fea09dc. The reverted patch causes a Jira issue SWDEV-488436. Signed-off-by: Bob Zhou --- drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 253 +++++++++++-------------- 1 file changed, 115 insertions(+), 138 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c index e813da1e48aa8..3e48ea38385de 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c @@ -705,16 +705,14 @@ static void sdma_v5_0_enable(struct amdgpu_device *adev, bool enable) } /** - * sdma_v5_0_gfx_resume_instance - start/restart a certain sdma engine + * sdma_v5_0_gfx_resume - setup and start the async dma engines * * @adev: amdgpu_device pointer - * @i: instance - * @restore: used to restore wptr when restart * - * Set up the gfx DMA ring buffers and enable them. On restart, we will restore wptr and rptr. - * Return 0 for success. + * Set up the gfx DMA ring buffers and enable them (NAVI10). + * Returns 0 for success, error for failure. */ -static int sdma_v5_0_gfx_resume_instance(struct amdgpu_device *adev, int i, bool restore) +static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev) { struct amdgpu_ring *ring; u32 rb_cntl, ib_cntl; @@ -724,163 +722,142 @@ static int sdma_v5_0_gfx_resume_instance(struct amdgpu_device *adev, int i, bool u32 temp; u32 wptr_poll_cntl; u64 wptr_gpu_addr; + int i, r; - ring = &adev->sdma.instance[i].ring; + for (i = 0; i < adev->sdma.num_instances; i++) { + ring = &adev->sdma.instance[i].ring; - if (!amdgpu_sriov_vf(adev)) - WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); + if (!amdgpu_sriov_vf(adev)) + WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); - /* Set ring buffer size in dwords */ - rb_bufsz = order_base_2(ring->ring_size / 4); - rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); - rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); + /* Set ring buffer size in dwords */ + rb_bufsz = order_base_2(ring->ring_size / 4); + rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); #ifdef __BIG_ENDIAN - rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); - rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, - RPTR_WRITEBACK_SWAP_ENABLE, 1); + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, + RPTR_WRITEBACK_SWAP_ENABLE, 1); #endif - WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); - - /* Initialize the ring buffer's read and write pointers */ - if (restore) { - WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), lower_32_bits(ring->wptr << 2)); - WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), upper_32_bits(ring->wptr << 2)); - WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2)); - WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2)); - } else { + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); + + /* Initialize the ring buffer's read and write pointers */ WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0); WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0); WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0); WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0); - } - /* setup the wptr shadow polling */ - wptr_gpu_addr = ring->wptr_gpu_addr; - WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO), - lower_32_bits(wptr_gpu_addr)); - WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI), - upper_32_bits(wptr_gpu_addr)); - wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, - mmSDMA0_GFX_RB_WPTR_POLL_CNTL)); - wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, - SDMA0_GFX_RB_WPTR_POLL_CNTL, - F32_POLL_ENABLE, 1); - WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), - wptr_poll_cntl); - - /* set the wb address whether it's enabled or not */ - WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI), - upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF); - WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO), - lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); - - rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); - - WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), - ring->gpu_addr >> 8); - WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), - ring->gpu_addr >> 40); - - if (!restore) + + /* setup the wptr shadow polling */ + wptr_gpu_addr = ring->wptr_gpu_addr; + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO), + lower_32_bits(wptr_gpu_addr)); + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI), + upper_32_bits(wptr_gpu_addr)); + wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, + mmSDMA0_GFX_RB_WPTR_POLL_CNTL)); + wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, + SDMA0_GFX_RB_WPTR_POLL_CNTL, + F32_POLL_ENABLE, 1); + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), + wptr_poll_cntl); + + /* set the wb address whether it's enabled or not */ + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI), + upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF); + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO), + lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); + + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); + + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), + ring->gpu_addr >> 8); + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), + ring->gpu_addr >> 40); + ring->wptr = 0; - /* before programing wptr to a less value, need set minor_ptr_update first */ - WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1); + /* before programing wptr to a less value, need set minor_ptr_update first */ + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1); - if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ - WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), - lower_32_bits(ring->wptr << 2)); - WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), - upper_32_bits(ring->wptr << 2)); - } + if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ + WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), + lower_32_bits(ring->wptr << 2)); + WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), + upper_32_bits(ring->wptr << 2)); + } - doorbell = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL)); - doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, - mmSDMA0_GFX_DOORBELL_OFFSET)); + doorbell = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL)); + doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, + mmSDMA0_GFX_DOORBELL_OFFSET)); - if (ring->use_doorbell) { - doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); - doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET, - OFFSET, ring->doorbell_index); - } else { - doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); - } - WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell); - WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), - doorbell_offset); + if (ring->use_doorbell) { + doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); + doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET, + OFFSET, ring->doorbell_index); + } else { + doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); + } + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell); + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), + doorbell_offset); - adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, - ring->doorbell_index, 20); + adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, + ring->doorbell_index, 20); - if (amdgpu_sriov_vf(adev)) - sdma_v5_0_ring_set_wptr(ring); + if (amdgpu_sriov_vf(adev)) + sdma_v5_0_ring_set_wptr(ring); - /* set minor_ptr_update to 0 after wptr programed */ - WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0); + /* set minor_ptr_update to 0 after wptr programed */ + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0); - if (!amdgpu_sriov_vf(adev)) { - /* set utc l1 enable flag always to 1 */ - temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL)); - temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); - - /* enable MCBP */ - temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1); - WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp); - - /* Set up RESP_MODE to non-copy addresses */ - temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL)); - temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3); - temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9); - WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp); - - /* program default cache read and write policy */ - temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE)); - /* clean read policy and write policy bits */ - temp &= 0xFF0FFF; - temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | (CACHE_WRITE_POLICY_L2__DEFAULT << 14)); - WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp); - } + if (!amdgpu_sriov_vf(adev)) { + /* set utc l1 enable flag always to 1 */ + temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL)); + temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); + + /* enable MCBP */ + temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1); + WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp); + + /* Set up RESP_MODE to non-copy addresses */ + temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL)); + temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3); + temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9); + WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp); + + /* program default cache read and write policy */ + temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE)); + /* clean read policy and write policy bits */ + temp &= 0xFF0FFF; + temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | (CACHE_WRITE_POLICY_L2__DEFAULT << 14)); + WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp); + } - if (!amdgpu_sriov_vf(adev)) { - /* unhalt engine */ - temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); - temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); - WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp); - } + if (!amdgpu_sriov_vf(adev)) { + /* unhalt engine */ + temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); + temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); + WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp); + } - /* enable DMA RB */ - rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); - WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); + /* enable DMA RB */ + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); - ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); - ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); + ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); + ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); #ifdef __BIG_ENDIAN - ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); + ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); #endif - /* enable DMA IBs */ - WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); - - if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */ - sdma_v5_0_ctx_switch_enable(adev, true); - sdma_v5_0_enable(adev, true); - } - - return amdgpu_ring_test_helper(ring); -} + /* enable DMA IBs */ + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); -/** - * sdma_v5_0_gfx_resume - setup and start the async dma engines - * - * @adev: amdgpu_device pointer - * - * Set up the gfx DMA ring buffers and enable them (NAVI10). - * Returns 0 for success, error for failure. - */ -static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev) -{ - int i, r; + if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */ + sdma_v5_0_ctx_switch_enable(adev, true); + sdma_v5_0_enable(adev, true); + } - for (i = 0; i < adev->sdma.num_instances; i++) { - r = sdma_v5_0_gfx_resume_instance(adev, i, false); + r = amdgpu_ring_test_helper(ring); if (r) return r; } From bc713c28b45dfea0a62d2c866a877f98813b3775 Mon Sep 17 00:00:00 2001 From: James Zhu Date: Mon, 23 Sep 2024 10:15:39 -0400 Subject: [PATCH 1699/1868] drm/amdkfd: release spm when process destroy If process is killed, process destroy will be called. Signed-off-by: James Zhu Tested-by: Bing Ma --- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 1 + drivers/gpu/drm/amd/amdkfd/kfd_process.c | 1 + drivers/gpu/drm/amd/amdkfd/kfd_spm.c | 2 +- 3 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 319c1dade2c4f..77a778f6b5b91 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -1649,6 +1649,7 @@ int kfd_send_exception_to_runtime(struct kfd_process *p, bool kfd_is_locked(void); void kfd_spm_init_process_device(struct kfd_process_device *pdd); +int kfd_release_spm(struct kfd_process_device *pdd, struct amdgpu_device *adev); int kfd_rlc_spm(struct kfd_process *p, void __user *data); /* PeerDirect support */ diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index cde8d34fc4394..af56e600d7a15 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -1044,6 +1044,7 @@ static void kfd_process_destroy_pdds(struct kfd_process *p) pdd->dev->id, p->pasid); kfd_pc_sample_release(pdd); + kfd_release_spm(pdd, pdd->dev->adev); kfd_process_device_destroy_cwsr_dgpu(pdd); kfd_process_device_destroy_ib_mem(pdd); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c index 45a81dd764eab..9a27949e00f59 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c @@ -235,7 +235,7 @@ static int kfd_acquire_spm(struct kfd_process_device *pdd, struct amdgpu_device return ret; } -static int kfd_release_spm(struct kfd_process_device *pdd, struct amdgpu_device *adev) +int kfd_release_spm(struct kfd_process_device *pdd, struct amdgpu_device *adev) { unsigned long flags; From d24f04ae59ef058d717f6f86b662b138e29589cd Mon Sep 17 00:00:00 2001 From: James Zhu Date: Mon, 23 Sep 2024 11:05:44 -0400 Subject: [PATCH 1700/1868] drm/amdkfd: workaround for spm overflow reserve space to avoid page fault and data loss. Signed-off-by: James Zhu Reviewed-by: Bing Ma --- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 2 ++ drivers/gpu/drm/amd/amdkfd/kfd_spm.c | 40 ++++++++++++++++++++++++++- 2 files changed, 41 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 77a778f6b5b91..01781a43836a6 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -875,6 +875,8 @@ struct kfd_process_device { struct mutex spm_mutex; struct work_struct spm_work; spinlock_t spm_irq_lock; + /* reserve space to fix spm overflow */ + u32 spm_overflow_reserved; /* Eviction activity tracking */ uint64_t last_evict_timestamp; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c index 9a27949e00f59..d6a03240f36af 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_spm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_spm.c @@ -50,6 +50,21 @@ struct kfd_spm_cntr { bool is_spm_started; }; +/* used to detect SPM overflow */ +#define SPM_OVERFLOW_MAGIC 0xBEEFABCDDEADABCD + +static void kfd_spm_preset(struct kfd_process_device *pdd, u32 size) +{ + uint64_t *overflow_ptr, *overflow_end_ptr; + + overflow_ptr = (uint64_t *)((uint64_t)pdd->spm_cntr->cpu_addr + + pdd->spm_cntr->ring_size + 0x20); + overflow_end_ptr = overflow_ptr + (size >> 3); + /* SPM data filling is 0x20 alignment */ + for ( ; overflow_ptr < overflow_end_ptr; overflow_ptr += 4) + *overflow_ptr = SPM_OVERFLOW_MAGIC; +} + static int kfd_spm_data_copy(struct kfd_process_device *pdd, u32 size_to_copy) { struct kfd_spm_cntr *spm = pdd->spm_cntr; @@ -97,6 +112,7 @@ static int kfd_spm_data_copy(struct kfd_process_device *pdd, u32 size_to_copy) static int kfd_spm_read_ring_buffer(struct kfd_process_device *pdd) { struct kfd_spm_cntr *spm = pdd->spm_cntr; + u32 overflow_size = 0; u32 size_to_copy; int ret = 0; u32 ring_wptr; @@ -125,6 +141,19 @@ static int kfd_spm_read_ring_buffer(struct kfd_process_device *pdd) size_to_copy = ring_wptr - spm->ring_rptr; ret = kfd_spm_data_copy(pdd, size_to_copy); } else { + uint64_t *ring_start, *ring_end; + + ring_start = (uint64_t *)((uint64_t)pdd->spm_cntr->cpu_addr + 0x20); + ring_end = ring_start + (pdd->spm_cntr->ring_size >> 3); + for ( ; overflow_size < pdd->spm_overflow_reserved; overflow_size += 0x20) { + uint64_t *overflow_ptr = ring_end + (overflow_size >> 3); + + if (*overflow_ptr == SPM_OVERFLOW_MAGIC) + break; + } + /* move overflow counters into ring buffer to avoid data loss */ + memcpy(ring_start, ring_end, overflow_size); + size_to_copy = spm->ring_size - spm->ring_rptr; ret = kfd_spm_data_copy(pdd, size_to_copy); @@ -143,6 +172,7 @@ static int kfd_spm_read_ring_buffer(struct kfd_process_device *pdd) } exit: + kfd_spm_preset(pdd, overflow_size); amdgpu_amdkfd_rlc_spm_set_rdptr(pdd->dev->adev, spm->ring_rptr); return ret; } @@ -168,6 +198,10 @@ static void kfd_spm_work(struct work_struct *work) void kfd_spm_init_process_device(struct kfd_process_device *pdd) { + /* pre-gfx11 spm has a hardware bug to cause overflow */ + if (pdd->dev->adev->ip_versions[GC_HWIP][0] < IP_VERSION(11, 0, 1)) + pdd->spm_overflow_reserved = 0x400; + mutex_init(&pdd->spm_mutex); pdd->spm_cntr = NULL; } @@ -202,7 +236,9 @@ static int kfd_acquire_spm(struct kfd_process_device *pdd, struct amdgpu_device if (ret) goto alloc_gtt_mem_failure; - ret = amdgpu_amdkfd_rlc_spm_acquire(adev, drm_priv_to_vm(pdd->drm_priv), + /* reserve space to fix spm overflow */ + pdd->spm_cntr->ring_size -= pdd->spm_overflow_reserved; + ret = amdgpu_amdkfd_rlc_spm_acquire(adev, drm_priv_to_vm(pdd->drm_priv), pdd->spm_cntr->gpu_addr, pdd->spm_cntr->ring_size); /* @@ -221,6 +257,8 @@ static int kfd_acquire_spm(struct kfd_process_device *pdd, struct amdgpu_device spin_lock_init(&pdd->spm_irq_lock); + kfd_spm_preset(pdd, pdd->spm_overflow_reserved); + goto out; acquire_spm_failure: From 5cc743a22f5b07e294bd6e8d145d3bfd4a5776cd Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Mon, 30 Sep 2024 17:35:50 +0530 Subject: [PATCH 1701/1868] drm/amdgpu: Fix logic to determine TOS reload Avoid comparing TOS version on APUs. On APUs driver doesn't take care of TOS load. Fixes: 2edc5ecbf1a9 ("drm/amdgpu: Add interface for TOS reload cases") Signed-off-by: Lijo Lazar Acked-by: Rajneesh Bhardwaj (cherry picked from commit f6e9977f95a610eb08732325588b7be3effe2151) Change-Id: Ic1e8601a9e2999fa87e898e3ed9d37b6580ad1ce --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index c9e7e49ffc828..a8ec3ad5beae9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -2270,7 +2270,7 @@ bool amdgpu_psp_tos_reload_needed(struct amdgpu_device *adev) { struct psp_context *psp = &adev->psp; - if (amdgpu_sriov_vf(adev)) + if (amdgpu_sriov_vf(adev) || (adev->flags & AMD_IS_APU)) return false; if (psp->funcs && psp->funcs->is_reload_needed) From 04495128c9115e504631aced610eeb4ff21abedf Mon Sep 17 00:00:00 2001 From: Philip Yang Date: Thu, 3 Oct 2024 11:53:51 -0400 Subject: [PATCH 1702/1868] drm/amdkfd: Copy wave state only for compute queue get_wave_state is not defined for sdma queue, copy_context_work_handler calls it for sdma queue will crash. Signed-off-by: Philip Yang Reviewed-by: Jonathan Kim Tested-by: Jonathan Kim --- drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index 6a5d50242d474..53e0cd5c11860 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -3199,7 +3199,7 @@ struct copy_context_work_handler_workarea { struct kfd_process *p; }; -static void copy_context_work_handler (struct work_struct *work) +static void copy_context_work_handler(struct work_struct *work) { struct copy_context_work_handler_workarea *workarea; struct mqd_manager *mqd_mgr; @@ -3226,6 +3226,9 @@ static void copy_context_work_handler (struct work_struct *work) struct qcm_process_device *qpd = &pdd->qpd; list_for_each_entry(q, &qpd->queues_list, list) { + if (q->properties.type != KFD_QUEUE_TYPE_COMPUTE) + continue; + mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_CP]; /* We ignore the return value from get_wave_state From f849873778b93f0a9b7974d02ce67cb3471e54e0 Mon Sep 17 00:00:00 2001 From: Jiadong Zhu Date: Fri, 20 Sep 2024 09:45:42 +0800 Subject: [PATCH 1703/1868] drm/amdgpu/sdma5: split out per instance resume function Extract the resume sequence from sdma_v5_0_gfx_resume for starting/restarting an individual instance. Signed-off-by: Jiadong Zhu Acked-by: Alex Deucher (cherry picked from commit e1baa1ac2b7e62ee1e09ab8492911ac75fea09dc) Change-Id: Icbfa6e845f84a4b4c84cd5a8b90255cd95737a5c --- drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 253 ++++++++++++++----------- 1 file changed, 138 insertions(+), 115 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c index 3e48ea38385de..e813da1e48aa8 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c @@ -705,14 +705,16 @@ static void sdma_v5_0_enable(struct amdgpu_device *adev, bool enable) } /** - * sdma_v5_0_gfx_resume - setup and start the async dma engines + * sdma_v5_0_gfx_resume_instance - start/restart a certain sdma engine * * @adev: amdgpu_device pointer + * @i: instance + * @restore: used to restore wptr when restart * - * Set up the gfx DMA ring buffers and enable them (NAVI10). - * Returns 0 for success, error for failure. + * Set up the gfx DMA ring buffers and enable them. On restart, we will restore wptr and rptr. + * Return 0 for success. */ -static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev) +static int sdma_v5_0_gfx_resume_instance(struct amdgpu_device *adev, int i, bool restore) { struct amdgpu_ring *ring; u32 rb_cntl, ib_cntl; @@ -722,142 +724,163 @@ static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev) u32 temp; u32 wptr_poll_cntl; u64 wptr_gpu_addr; - int i, r; - for (i = 0; i < adev->sdma.num_instances; i++) { - ring = &adev->sdma.instance[i].ring; + ring = &adev->sdma.instance[i].ring; - if (!amdgpu_sriov_vf(adev)) - WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); + if (!amdgpu_sriov_vf(adev)) + WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); - /* Set ring buffer size in dwords */ - rb_bufsz = order_base_2(ring->ring_size / 4); - rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); - rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); + /* Set ring buffer size in dwords */ + rb_bufsz = order_base_2(ring->ring_size / 4); + rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); #ifdef __BIG_ENDIAN - rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); - rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, - RPTR_WRITEBACK_SWAP_ENABLE, 1); + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, + RPTR_WRITEBACK_SWAP_ENABLE, 1); #endif - WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); - - /* Initialize the ring buffer's read and write pointers */ + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); + + /* Initialize the ring buffer's read and write pointers */ + if (restore) { + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), lower_32_bits(ring->wptr << 2)); + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), upper_32_bits(ring->wptr << 2)); + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2)); + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2)); + } else { WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0); WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0); WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0); WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0); - - /* setup the wptr shadow polling */ - wptr_gpu_addr = ring->wptr_gpu_addr; - WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO), - lower_32_bits(wptr_gpu_addr)); - WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI), - upper_32_bits(wptr_gpu_addr)); - wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, - mmSDMA0_GFX_RB_WPTR_POLL_CNTL)); - wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, - SDMA0_GFX_RB_WPTR_POLL_CNTL, - F32_POLL_ENABLE, 1); - WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), - wptr_poll_cntl); - - /* set the wb address whether it's enabled or not */ - WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI), - upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF); - WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO), - lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); - - rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); - - WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), - ring->gpu_addr >> 8); - WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), - ring->gpu_addr >> 40); - + } + /* setup the wptr shadow polling */ + wptr_gpu_addr = ring->wptr_gpu_addr; + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO), + lower_32_bits(wptr_gpu_addr)); + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI), + upper_32_bits(wptr_gpu_addr)); + wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, + mmSDMA0_GFX_RB_WPTR_POLL_CNTL)); + wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, + SDMA0_GFX_RB_WPTR_POLL_CNTL, + F32_POLL_ENABLE, 1); + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), + wptr_poll_cntl); + + /* set the wb address whether it's enabled or not */ + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI), + upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF); + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO), + lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); + + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); + + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), + ring->gpu_addr >> 8); + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), + ring->gpu_addr >> 40); + + if (!restore) ring->wptr = 0; - /* before programing wptr to a less value, need set minor_ptr_update first */ - WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1); + /* before programing wptr to a less value, need set minor_ptr_update first */ + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1); - if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ - WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), - lower_32_bits(ring->wptr << 2)); - WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), - upper_32_bits(ring->wptr << 2)); - } + if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ + WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), + lower_32_bits(ring->wptr << 2)); + WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), + upper_32_bits(ring->wptr << 2)); + } - doorbell = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL)); - doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, - mmSDMA0_GFX_DOORBELL_OFFSET)); + doorbell = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL)); + doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, + mmSDMA0_GFX_DOORBELL_OFFSET)); - if (ring->use_doorbell) { - doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); - doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET, - OFFSET, ring->doorbell_index); - } else { - doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); - } - WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell); - WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), - doorbell_offset); + if (ring->use_doorbell) { + doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); + doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET, + OFFSET, ring->doorbell_index); + } else { + doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); + } + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell); + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), + doorbell_offset); - adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, - ring->doorbell_index, 20); + adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, + ring->doorbell_index, 20); - if (amdgpu_sriov_vf(adev)) - sdma_v5_0_ring_set_wptr(ring); + if (amdgpu_sriov_vf(adev)) + sdma_v5_0_ring_set_wptr(ring); - /* set minor_ptr_update to 0 after wptr programed */ - WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0); + /* set minor_ptr_update to 0 after wptr programed */ + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0); - if (!amdgpu_sriov_vf(adev)) { - /* set utc l1 enable flag always to 1 */ - temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL)); - temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); - - /* enable MCBP */ - temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1); - WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp); - - /* Set up RESP_MODE to non-copy addresses */ - temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL)); - temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3); - temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9); - WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp); - - /* program default cache read and write policy */ - temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE)); - /* clean read policy and write policy bits */ - temp &= 0xFF0FFF; - temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | (CACHE_WRITE_POLICY_L2__DEFAULT << 14)); - WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp); - } + if (!amdgpu_sriov_vf(adev)) { + /* set utc l1 enable flag always to 1 */ + temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL)); + temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); + + /* enable MCBP */ + temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1); + WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), temp); + + /* Set up RESP_MODE to non-copy addresses */ + temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL)); + temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3); + temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9); + WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp); + + /* program default cache read and write policy */ + temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE)); + /* clean read policy and write policy bits */ + temp &= 0xFF0FFF; + temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | (CACHE_WRITE_POLICY_L2__DEFAULT << 14)); + WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp); + } - if (!amdgpu_sriov_vf(adev)) { - /* unhalt engine */ - temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); - temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); - WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp); - } + if (!amdgpu_sriov_vf(adev)) { + /* unhalt engine */ + temp = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); + temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); + WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp); + } - /* enable DMA RB */ - rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); - WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); + /* enable DMA RB */ + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); - ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); - ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); + ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); + ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); #ifdef __BIG_ENDIAN - ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); + ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); #endif - /* enable DMA IBs */ - WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); + /* enable DMA IBs */ + WREG32_SOC15_IP(GC, sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); - if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */ - sdma_v5_0_ctx_switch_enable(adev, true); - sdma_v5_0_enable(adev, true); - } + if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */ + sdma_v5_0_ctx_switch_enable(adev, true); + sdma_v5_0_enable(adev, true); + } + + return amdgpu_ring_test_helper(ring); +} - r = amdgpu_ring_test_helper(ring); +/** + * sdma_v5_0_gfx_resume - setup and start the async dma engines + * + * @adev: amdgpu_device pointer + * + * Set up the gfx DMA ring buffers and enable them (NAVI10). + * Returns 0 for success, error for failure. + */ +static int sdma_v5_0_gfx_resume(struct amdgpu_device *adev) +{ + int i, r; + + for (i = 0; i < adev->sdma.num_instances; i++) { + r = sdma_v5_0_gfx_resume_instance(adev, i, false); if (r) return r; } From 708d20de125b6b8ee4a38eb20041dd1efc9a8dd6 Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Tue, 24 Sep 2024 21:30:17 +0530 Subject: [PATCH 1704/1868] drm/amdgpu: update the handle ptr in dump_ip_state MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Update the ptr handle to amdgpu_ip_block ptr in all the functions. Signed-off-by: Sunil Khatri Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 2 +- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 4 ++-- drivers/gpu/drm/amd/include/amd_shared.h | 4 +++- 22 files changed, 43 insertions(+), 41 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 514d55e0c31e8..88744766c87e7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -5383,7 +5383,7 @@ int amdgpu_device_pre_asic_reset(struct amdgpu_device *adev, for (i = 0; i < tmp_adev->num_ip_blocks; i++) if (tmp_adev->ip_blocks[i].version->funcs->dump_ip_state) tmp_adev->ip_blocks[i].version->funcs - ->dump_ip_state((void *)tmp_adev); + ->dump_ip_state((void *)&tmp_adev->ip_blocks[i]); dev_info(tmp_adev->dev, "Dumping IP State Completed\n"); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c index 13a3604cf1079..fdadbe49c913e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c @@ -42,7 +42,7 @@ static void amdgpu_job_do_core_dump(struct amdgpu_device *adev, for (i = 0; i < adev->num_ip_blocks; i++) if (adev->ip_blocks[i].version->funcs->dump_ip_state) adev->ip_blocks[i].version->funcs - ->dump_ip_state((void *)adev); + ->dump_ip_state((void *)&adev->ip_blocks[i]); dev_info(adev->dev, "Dumping IP State Completed\n"); amdgpu_coredump(adev, true, false, job); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 90ccf4baa7f5a..3f61fd0389e29 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -9738,9 +9738,9 @@ static void gfx_v10_ip_print(void *handle, struct drm_printer *p) } } -static void gfx_v10_ip_dump(void *handle) +static void gfx_v10_ip_dump(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; uint32_t i, j, k, reg, index = 0; uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index 33fd2da49a2a7..acf2e7634200c 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -6705,9 +6705,9 @@ static void gfx_v11_ip_print(void *handle, struct drm_printer *p) } } -static void gfx_v11_ip_dump(void *handle) +static void gfx_v11_ip_dump(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; uint32_t i, j, k, reg, index = 0; uint32_t reg_count = ARRAY_SIZE(gc_reg_list_11_0); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c index 47b47d21f4644..13baa6868a789 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c @@ -5102,9 +5102,9 @@ static void gfx_v12_ip_print(void *handle, struct drm_printer *p) } } -static void gfx_v12_ip_dump(void *handle) +static void gfx_v12_ip_dump(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; uint32_t i, j, k, reg, index = 0; uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index df15cb942a727..5f5ffb8695424 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -7504,9 +7504,9 @@ static void gfx_v9_ip_print(void *handle, struct drm_printer *p) } -static void gfx_v9_ip_dump(void *handle) +static void gfx_v9_ip_dump(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; uint32_t i, j, k, reg, index = 0; uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index 59d0c34aeacf9..3d48eb281e99b 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -4645,9 +4645,9 @@ static void gfx_v9_4_3_ip_print(void *handle, struct drm_printer *p) } } -static void gfx_v9_4_3_ip_dump(void *handle) +static void gfx_v9_4_3_ip_dump(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; uint32_t i, j, k; uint32_t num_xcc, reg, num_inst; uint32_t xcc_id, xcc_offset, inst_offset; diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index b2ea1ae5b737b..7b6092d50f1d9 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c @@ -2372,9 +2372,9 @@ static void sdma_v4_0_print_ip_state(void *handle, struct drm_printer *p) } } -static void sdma_v4_0_dump_ip_state(void *handle) +static void sdma_v4_0_dump_ip_state(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i, j; uint32_t instance_offset; uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_4_0); diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c index c77889040760a..487cc0992263b 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c @@ -1878,9 +1878,9 @@ static void sdma_v4_4_2_print_ip_state(void *handle, struct drm_printer *p) } } -static void sdma_v4_4_2_dump_ip_state(void *handle) +static void sdma_v4_4_2_dump_ip_state(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i, j; uint32_t instance_offset; uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_4_4_2); diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c index e813da1e48aa8..4dc8ff7618885 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c @@ -1822,9 +1822,9 @@ static void sdma_v5_0_print_ip_state(void *handle, struct drm_printer *p) } } -static void sdma_v5_0_dump_ip_state(void *handle) +static void sdma_v5_0_dump_ip_state(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i, j; uint32_t instance_offset; uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_5_0); diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c index bc9b240a3488e..d19dde1d6fc5b 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c @@ -1757,9 +1757,9 @@ static void sdma_v5_2_print_ip_state(void *handle, struct drm_printer *p) } } -static void sdma_v5_2_dump_ip_state(void *handle) +static void sdma_v5_2_dump_ip_state(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i, j; uint32_t instance_offset; uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_5_2); diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c index 581fa550ef29f..ed7413c1954c4 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c @@ -1624,9 +1624,9 @@ static void sdma_v6_0_print_ip_state(void *handle, struct drm_printer *p) } } -static void sdma_v6_0_dump_ip_state(void *handle) +static void sdma_v6_0_dump_ip_state(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i, j; uint32_t instance_offset; uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_6_0); diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c index a8763496aed31..9e8b1ec4e6cb8 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c @@ -1559,9 +1559,9 @@ static void sdma_v7_0_print_ip_state(void *handle, struct drm_printer *p) } } -static void sdma_v7_0_dump_ip_state(void *handle) +static void sdma_v7_0_dump_ip_state(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i, j; uint32_t instance_offset; uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_7_0); diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index 5d3bfc24609bf..f27ddfe7c0fb8 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c @@ -1957,9 +1957,9 @@ static void vcn_v1_0_print_ip_state(void *handle, struct drm_printer *p) } } -static void vcn_v1_0_dump_ip_state(void *handle) +static void vcn_v1_0_dump_ip_state(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i, j; bool is_powered; uint32_t inst_off; diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c index bfd067e2d2f1d..5d6accdba4804 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c @@ -2066,9 +2066,9 @@ static void vcn_v2_0_print_ip_state(void *handle, struct drm_printer *p) } } -static void vcn_v2_0_dump_ip_state(void *handle) +static void vcn_v2_0_dump_ip_state(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i, j; bool is_powered; uint32_t inst_off; diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c index 04e9e806e3187..8896c25fd1d43 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c @@ -1958,9 +1958,9 @@ static void vcn_v2_5_print_ip_state(void *handle, struct drm_printer *p) } } -static void vcn_v2_5_dump_ip_state(void *handle) +static void vcn_v2_5_dump_ip_state(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i, j; bool is_powered; uint32_t inst_off; diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c index 65dd68b322806..3009f52f62d7c 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c @@ -2284,9 +2284,9 @@ static void vcn_v3_0_print_ip_state(void *handle, struct drm_printer *p) } } -static void vcn_v3_0_dump_ip_state(void *handle) +static void vcn_v3_0_dump_ip_state(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i, j; bool is_powered; uint32_t inst_off; diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c index 26c6f10a8c8fa..17ea10c14e299 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c @@ -2190,9 +2190,9 @@ static void vcn_v4_0_print_ip_state(void *handle, struct drm_printer *p) } } -static void vcn_v4_0_dump_ip_state(void *handle) +static void vcn_v4_0_dump_ip_state(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i, j; bool is_powered; uint32_t inst_off; diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c index 0fda703363004..742bf09ae195e 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c @@ -1765,9 +1765,9 @@ static void vcn_v4_0_3_print_ip_state(void *handle, struct drm_printer *p) } } -static void vcn_v4_0_3_dump_ip_state(void *handle) +static void vcn_v4_0_3_dump_ip_state(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i, j; bool is_powered; uint32_t inst_off, inst_id; diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c index 9d4f5352a62c8..3fb8b218e2781 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c @@ -1648,9 +1648,9 @@ static void vcn_v4_0_5_print_ip_state(void *handle, struct drm_printer *p) } } -static void vcn_v4_0_5_dump_ip_state(void *handle) +static void vcn_v4_0_5_dump_ip_state(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i, j; bool is_powered; uint32_t inst_off; diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c index c305386358b4b..25ae338df3461 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c @@ -1375,9 +1375,9 @@ static void vcn_v5_0_print_ip_state(void *handle, struct drm_printer *p) } } -static void vcn_v5_0_dump_ip_state(void *handle) +static void vcn_v5_0_dump_ip_state(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i, j; bool is_powered; uint32_t inst_off; diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h index 3f91926a50e99..cbb19895ddaf5 100644 --- a/drivers/gpu/drm/amd/include/amd_shared.h +++ b/drivers/gpu/drm/amd/include/amd_shared.h @@ -375,6 +375,8 @@ enum amd_dpm_forced_level; * making calls to hooks from each IP block. This list is ordered to ensure * that the driver initializes the IP blocks in a safe sequence. */ +struct amdgpu_ip_block; + struct amd_ip_funcs { char *name; int (*early_init)(void *handle); @@ -399,7 +401,7 @@ struct amd_ip_funcs { int (*set_powergating_state)(void *handle, enum amd_powergating_state state); void (*get_clockgating_state)(void *handle, u64 *flags); - void (*dump_ip_state)(void *handle); + void (*dump_ip_state)(struct amdgpu_ip_block *ip_block); void (*print_ip_state)(void *handle, struct drm_printer *p); }; From 627f3798d53d1f1f966c74fecd05b99a411bae39 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Mon, 9 Sep 2024 14:17:17 +0530 Subject: [PATCH 1705/1868] drm/amdgpu: Add sysfs nodes to get xcp details Add partition config nodes in sysfs to get resource instance details for a particular partition mode. A resource could be anything like an xcc, vcn decoder, system dma units etc. Details of various resource instances are available under /sys/bus/pci/devices/.../compute_partition_config/ Select a partition configuration: /sys/bus/pci/devices/.../compute_partition_config/xcp_config Number of instances of a resource: /sys/bus/pci/devices/.../compute_partition_config//num_inst Total partitions sharing the resource: /sys/bus/pci/devices/.../compute_partition_config//num_shared v2: Update node name as per spec Signed-off-by: Lijo Lazar Signed-off-by: Asad Kamal Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c | 201 +++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h | 5 + 3 files changed, 208 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 88744766c87e7..71b1942518df1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -4503,6 +4503,7 @@ int amdgpu_device_init(struct amdgpu_device *adev, amdgpu_fru_sysfs_init(adev); amdgpu_reg_state_sysfs_init(adev); + amdgpu_xcp_cfg_sysfs_init(adev); if (IS_ENABLED(CONFIG_PERF_EVENTS)) r = amdgpu_pmu_init(adev); @@ -4629,6 +4630,7 @@ void amdgpu_device_fini_hw(struct amdgpu_device *adev) amdgpu_fru_sysfs_fini(adev); amdgpu_reg_state_sysfs_fini(adev); + amdgpu_xcp_cfg_sysfs_fini(adev); /* disable ras feature must before hw fini */ amdgpu_ras_pre_fini(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c index a6d456ec6aeb1..fc4ab1d8c7c96 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c @@ -433,3 +433,204 @@ void amdgpu_xcp_release_sched(struct amdgpu_device *adev, } } +#define XCP_CFG_SYSFS_RES_ATTR_SHOW(_name) \ + static ssize_t amdgpu_xcp_res_sysfs_##_name##_show( \ + struct amdgpu_xcp_res_details *xcp_res, char *buf) \ + { \ + return sysfs_emit(buf, "%d\n", xcp_res->_name); \ + } + +struct amdgpu_xcp_res_sysfs_attribute { + struct attribute attr; + ssize_t (*show)(struct amdgpu_xcp_res_details *xcp_res, char *buf); +}; + +#define XCP_CFG_SYSFS_RES_ATTR(_name) \ + struct amdgpu_xcp_res_sysfs_attribute xcp_res_sysfs_attr_##_name = { \ + .attr = { .name = __stringify(_name), .mode = 0400 }, \ + .show = amdgpu_xcp_res_sysfs_##_name##_show, \ + } + +XCP_CFG_SYSFS_RES_ATTR_SHOW(num_inst) +XCP_CFG_SYSFS_RES_ATTR(num_inst); +XCP_CFG_SYSFS_RES_ATTR_SHOW(num_shared) +XCP_CFG_SYSFS_RES_ATTR(num_shared); + +#define XCP_CFG_SYSFS_RES_ATTR_PTR(_name) xcp_res_sysfs_attr_##_name.attr + +static struct attribute *xcp_cfg_res_sysfs_attrs[] = { + &XCP_CFG_SYSFS_RES_ATTR_PTR(num_inst), + &XCP_CFG_SYSFS_RES_ATTR_PTR(num_shared), NULL +}; + +ATTRIBUTE_GROUPS(xcp_cfg_res_sysfs); + +#define to_xcp_attr(x) \ + container_of(x, struct amdgpu_xcp_res_sysfs_attribute, attr) +#define to_xcp_res(x) container_of(x, struct amdgpu_xcp_res_details, kobj) + +static ssize_t xcp_cfg_res_sysfs_attr_show(struct kobject *kobj, + struct attribute *attr, char *buf) +{ + struct amdgpu_xcp_res_sysfs_attribute *attribute; + struct amdgpu_xcp_res_details *xcp_res; + + attribute = to_xcp_attr(attr); + xcp_res = to_xcp_res(kobj); + + if (!attribute->show) + return -EIO; + + return attribute->show(xcp_res, buf); +} + +static const struct sysfs_ops xcp_cfg_res_sysfs_ops = { + .show = xcp_cfg_res_sysfs_attr_show, +}; + +static const struct kobj_type xcp_cfg_res_sysfs_ktype = { + .sysfs_ops = &xcp_cfg_res_sysfs_ops, + .default_groups = xcp_cfg_res_sysfs_groups, +}; + +const char *xcp_res_names[] = { + [AMDGPU_XCP_RES_XCC] = "xcc", + [AMDGPU_XCP_RES_DMA] = "dma", + [AMDGPU_XCP_RES_DEC] = "dec", + [AMDGPU_XCP_RES_JPEG] = "jpeg", +}; + +static int amdgpu_xcp_get_res_info(struct amdgpu_xcp_mgr *xcp_mgr, + int mode, + struct amdgpu_xcp_cfg *xcp_cfg) +{ + if (xcp_mgr->funcs && xcp_mgr->funcs->get_xcp_res_info) + return xcp_mgr->funcs->get_xcp_res_info(xcp_mgr, mode, xcp_cfg); + + return -EOPNOTSUPP; +} + +#define to_xcp_cfg(x) container_of(x, struct amdgpu_xcp_cfg, kobj) +static ssize_t xcp_config_show(struct kobject *kobj, + struct kobj_attribute *attr, char *buf) +{ + struct amdgpu_xcp_cfg *xcp_cfg = to_xcp_cfg(kobj); + + return sysfs_emit(buf, "%s\n", + amdgpu_gfx_compute_mode_desc(xcp_cfg->mode)); +} + +static ssize_t xcp_config_store(struct kobject *kobj, + struct kobj_attribute *attr, + const char *buf, size_t size) +{ + struct amdgpu_xcp_cfg *xcp_cfg = to_xcp_cfg(kobj); + int mode, r; + + if (!strncasecmp("SPX", buf, strlen("SPX"))) + mode = AMDGPU_SPX_PARTITION_MODE; + else if (!strncasecmp("DPX", buf, strlen("DPX"))) + mode = AMDGPU_DPX_PARTITION_MODE; + else if (!strncasecmp("TPX", buf, strlen("TPX"))) + mode = AMDGPU_TPX_PARTITION_MODE; + else if (!strncasecmp("QPX", buf, strlen("QPX"))) + mode = AMDGPU_QPX_PARTITION_MODE; + else if (!strncasecmp("CPX", buf, strlen("CPX"))) + mode = AMDGPU_CPX_PARTITION_MODE; + else + return -EINVAL; + + r = amdgpu_xcp_get_res_info(xcp_cfg->xcp_mgr, mode, xcp_cfg); + + if (r) + return r; + + xcp_cfg->mode = mode; + return size; +} + +static struct kobj_attribute xcp_cfg_sysfs_mode = + __ATTR_RW_MODE(xcp_config, 0644); + +static void xcp_cfg_sysfs_release(struct kobject *kobj) +{ + struct amdgpu_xcp_cfg *xcp_cfg = to_xcp_cfg(kobj); + + kfree(xcp_cfg); +} + +static const struct kobj_type xcp_cfg_sysfs_ktype = { + .release = xcp_cfg_sysfs_release, + .sysfs_ops = &kobj_sysfs_ops, +}; + +void amdgpu_xcp_cfg_sysfs_init(struct amdgpu_device *adev) +{ + struct amdgpu_xcp_res_details *xcp_res; + struct amdgpu_xcp_cfg *xcp_cfg; + int i, r, j, rid; + + if (!adev->xcp_mgr) + return; + + xcp_cfg = kzalloc(sizeof(*xcp_cfg), GFP_KERNEL); + if (!xcp_cfg) + return; + xcp_cfg->xcp_mgr = adev->xcp_mgr; + + r = kobject_init_and_add(&xcp_cfg->kobj, &xcp_cfg_sysfs_ktype, + &adev->dev->kobj, "compute_partition_config"); + if (r) + goto err1; + + r = sysfs_create_file(&xcp_cfg->kobj, &xcp_cfg_sysfs_mode.attr); + if (r) + goto err1; + + r = amdgpu_xcp_get_res_info(xcp_cfg->xcp_mgr, xcp_cfg->xcp_mgr->mode, xcp_cfg); + if (r) + goto err1; + + xcp_cfg->mode = xcp_cfg->xcp_mgr->mode; + for (i = 0; i < xcp_cfg->num_res; i++) { + xcp_res = &xcp_cfg->xcp_res[i]; + rid = xcp_res->id; + r = kobject_init_and_add(&xcp_res->kobj, + &xcp_cfg_res_sysfs_ktype, + &xcp_cfg->kobj, "%s", + xcp_res_names[rid]); + if (r) + goto err; + } + + adev->xcp_mgr->xcp_cfg = xcp_cfg; + return; +err: + for (j = 0; j < i; j++) { + xcp_res = &xcp_cfg->xcp_res[i]; + kobject_put(&xcp_res->kobj); + } + + sysfs_remove_file(&xcp_cfg->kobj, &xcp_cfg_sysfs_mode.attr); +err1: + kobject_put(&xcp_cfg->kobj); +} + +void amdgpu_xcp_cfg_sysfs_fini(struct amdgpu_device *adev) +{ + struct amdgpu_xcp_res_details *xcp_res; + struct amdgpu_xcp_cfg *xcp_cfg; + int i; + + if (!adev->xcp_mgr) + return; + + xcp_cfg = adev->xcp_mgr->xcp_cfg; + for (i = 0; i < xcp_cfg->num_res; i++) { + xcp_res = &xcp_cfg->xcp_res[i]; + kobject_put(&xcp_res->kobj); + } + + sysfs_remove_file(&xcp_cfg->kobj, &xcp_cfg_sysfs_mode.attr); + kobject_put(&xcp_cfg->kobj); +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h index 3aa3996c0250d..c0ec1ad4a606c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h @@ -68,6 +68,7 @@ struct amdgpu_xcp_res_details { enum amdgpu_xcp_res_id id; u8 num_inst; u8 num_shared; + struct kobject kobj; }; struct amdgpu_xcp_cfg { @@ -75,6 +76,7 @@ struct amdgpu_xcp_cfg { struct amdgpu_xcp_res_details xcp_res[AMDGPU_XCP_RES_MAX]; u8 num_res; struct amdgpu_xcp_mgr *xcp_mgr; + struct kobject kobj; }; struct amdgpu_xcp_ip_funcs { @@ -172,6 +174,9 @@ int amdgpu_xcp_open_device(struct amdgpu_device *adev, void amdgpu_xcp_release_sched(struct amdgpu_device *adev, struct amdgpu_ctx_entity *entity); +void amdgpu_xcp_cfg_sysfs_init(struct amdgpu_device *adev); +void amdgpu_xcp_cfg_sysfs_fini(struct amdgpu_device *adev); + #define amdgpu_xcp_select_scheds(adev, e, c, d, x, y) \ ((adev)->xcp_mgr && (adev)->xcp_mgr->funcs && \ (adev)->xcp_mgr->funcs->select_scheds ? \ From 82904bc4d35e4ae6e8fdc5008fd928ff569ffaef Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Sun, 29 Sep 2024 11:50:28 +0800 Subject: [PATCH 1706/1868] drm/amdkcl: wrap code under HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE It's caused by c7de57033d9b55b4bdc89dfeae6f57ba45401032 "drm/amdgpu: Add sysfs nodes to get xcp details" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c index fc4ab1d8c7c96..932c8fd24a8c1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c @@ -462,8 +462,9 @@ static struct attribute *xcp_cfg_res_sysfs_attrs[] = { &XCP_CFG_SYSFS_RES_ATTR_PTR(num_inst), &XCP_CFG_SYSFS_RES_ATTR_PTR(num_shared), NULL }; - +#ifdef HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE ATTRIBUTE_GROUPS(xcp_cfg_res_sysfs); +#endif #define to_xcp_attr(x) \ container_of(x, struct amdgpu_xcp_res_sysfs_attribute, attr) @@ -490,7 +491,11 @@ static const struct sysfs_ops xcp_cfg_res_sysfs_ops = { static const struct kobj_type xcp_cfg_res_sysfs_ktype = { .sysfs_ops = &xcp_cfg_res_sysfs_ops, +#ifdef HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE .default_groups = xcp_cfg_res_sysfs_groups, +#else + .default_attrs = xcp_cfg_res_sysfs_attrs, +#endif }; const char *xcp_res_names[] = { From 46c5edb88a516f59f750cb9819397d037939b733 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Sun, 29 Sep 2024 11:52:03 +0800 Subject: [PATCH 1707/1868] drm/amdkcl: test if macro __ATTR_RW_MODE is available It's caused by c7de57033d9b55b4bdc89dfeae6f57ba45401032 "drm/amdgpu: Add sysfs nodes to get xcp details" Signed-off-by: Bob Zhou Reviewed-by: Asher Song --- drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c index 932c8fd24a8c1..39b181e2d9546 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c @@ -555,7 +555,11 @@ static ssize_t xcp_config_store(struct kobject *kobj, } static struct kobj_attribute xcp_cfg_sysfs_mode = +#ifdef __ATTR_RW_MODE __ATTR_RW_MODE(xcp_config, 0644); +#else + __ATTR(xcp_config, 0644, xcp_config_show, xcp_config_store); +#endif static void xcp_cfg_sysfs_release(struct kobject *kobj) { From a4f3a0c78941cba0db6c19a6c42c1b6ab8391e5e Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Wed, 25 Sep 2024 08:56:40 +0530 Subject: [PATCH 1708/1868] drm/amdgpu: update the handle ptr in print_ip_state MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Update the ptr handle to amdgpu_ip_block ptr in all the functions affected. Signed-off-by: Sunil Khatri Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c | 12 +++++------- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 4 ++-- drivers/gpu/drm/amd/include/amd_shared.h | 2 +- 21 files changed, 44 insertions(+), 46 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c index 5ac59b62020cf..946c48829f197 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dev_coredump.c @@ -203,6 +203,7 @@ amdgpu_devcoredump_read(char *buffer, loff_t offset, size_t count, struct amdgpu_coredump_info *coredump = data; struct drm_print_iterator iter; struct amdgpu_vm_fault_info *fault_info; + struct amdgpu_ip_block *ip_block; int ver; iter.data = buffer; @@ -282,13 +283,10 @@ amdgpu_devcoredump_read(char *buffer, loff_t offset, size_t count, /* dump the ip state for each ip */ drm_printf(&p, "IP Dump\n"); for (int i = 0; i < coredump->adev->num_ip_blocks; i++) { - if (coredump->adev->ip_blocks[i].version->funcs->print_ip_state) { - drm_printf(&p, "IP: %s\n", - coredump->adev->ip_blocks[i] - .version->funcs->name); - coredump->adev->ip_blocks[i] - .version->funcs->print_ip_state( - (void *)coredump->adev, &p); + ip_block = &coredump->adev->ip_blocks[i]; + if (ip_block->version->funcs->print_ip_state) { + drm_printf(&p, "IP: %s\n", ip_block->version->funcs->name); + ip_block->version->funcs->print_ip_state(ip_block, &p); drm_printf(&p, "\n"); } } diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 3f61fd0389e29..0e4849178bda1 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -9674,9 +9674,9 @@ static int gfx_v10_0_reset_kcq(struct amdgpu_ring *ring, return amdgpu_ring_test_ring(ring); } -static void gfx_v10_ip_print(void *handle, struct drm_printer *p) +static void gfx_v10_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; uint32_t i, j, k, reg, index = 0; uint32_t reg_count = ARRAY_SIZE(gc_reg_list_10_1); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index acf2e7634200c..3f29b36323a15 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -6641,9 +6641,9 @@ static int gfx_v11_0_reset_kcq(struct amdgpu_ring *ring, unsigned int vmid) return amdgpu_ring_test_ring(ring); } -static void gfx_v11_ip_print(void *handle, struct drm_printer *p) +static void gfx_v11_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; uint32_t i, j, k, reg, index = 0; uint32_t reg_count = ARRAY_SIZE(gc_reg_list_11_0); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c index 13baa6868a789..3044436436c86 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c @@ -5038,9 +5038,9 @@ static void gfx_v12_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_nop) amdgpu_ring_write(ring, ring->funcs->nop); } -static void gfx_v12_ip_print(void *handle, struct drm_printer *p) +static void gfx_v12_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; uint32_t i, j, k, reg, index = 0; uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_0); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 5f5ffb8695424..befb049a97234 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -7464,9 +7464,9 @@ static int gfx_v9_0_reset_kcq(struct amdgpu_ring *ring, return amdgpu_ring_test_ring(ring); } -static void gfx_v9_ip_print(void *handle, struct drm_printer *p) +static void gfx_v9_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; uint32_t i, j, k, reg, index = 0; uint32_t reg_count = ARRAY_SIZE(gc_reg_list_9); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index 3d48eb281e99b..eabe0cf6191c1 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -4585,9 +4585,9 @@ static void gfx_v9_4_3_ring_insert_nop(struct amdgpu_ring *ring, uint32_t num_no amdgpu_ring_write(ring, ring->funcs->nop); } -static void gfx_v9_4_3_ip_print(void *handle, struct drm_printer *p) +static void gfx_v9_4_3_ip_print(struct amdgpu_ip_block *ip_block, struct drm_printer *p) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; uint32_t i, j, k; uint32_t xcc_id, xcc_offset, inst_offset; uint32_t num_xcc, reg, num_inst; diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index 7b6092d50f1d9..197a0cbda4bfd 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c @@ -2351,9 +2351,9 @@ static void sdma_v4_0_get_clockgating_state(void *handle, u64 *flags) *flags |= AMD_CG_SUPPORT_SDMA_LS; } -static void sdma_v4_0_print_ip_state(void *handle, struct drm_printer *p) +static void sdma_v4_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i, j; uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_4_0); uint32_t instance_offset; diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c index 487cc0992263b..d577b973d0a40 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c @@ -1857,9 +1857,9 @@ static void sdma_v4_4_2_get_clockgating_state(void *handle, u64 *flags) *flags |= AMD_CG_SUPPORT_SDMA_LS; } -static void sdma_v4_4_2_print_ip_state(void *handle, struct drm_printer *p) +static void sdma_v4_4_2_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i, j; uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_4_4_2); uint32_t instance_offset; diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c index 4dc8ff7618885..d3d2c8bf9000e 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c @@ -1801,9 +1801,9 @@ static void sdma_v5_0_get_clockgating_state(void *handle, u64 *flags) *flags |= AMD_CG_SUPPORT_SDMA_LS; } -static void sdma_v5_0_print_ip_state(void *handle, struct drm_printer *p) +static void sdma_v5_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i, j; uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_5_0); uint32_t instance_offset; diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c index d19dde1d6fc5b..8761b54050ca8 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c @@ -1736,9 +1736,9 @@ static void sdma_v5_2_ring_end_use(struct amdgpu_ring *ring) amdgpu_gfx_off_ctrl(adev, true); } -static void sdma_v5_2_print_ip_state(void *handle, struct drm_printer *p) +static void sdma_v5_2_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i, j; uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_5_2); uint32_t instance_offset; diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c index ed7413c1954c4..5eafc81e82f94 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c @@ -1603,9 +1603,9 @@ static void sdma_v6_0_get_clockgating_state(void *handle, u64 *flags) { } -static void sdma_v6_0_print_ip_state(void *handle, struct drm_printer *p) +static void sdma_v6_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i, j; uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_6_0); uint32_t instance_offset; diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c index 9e8b1ec4e6cb8..8509769db9c01 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c @@ -1538,9 +1538,9 @@ static void sdma_v7_0_get_clockgating_state(void *handle, u64 *flags) { } -static void sdma_v7_0_print_ip_state(void *handle, struct drm_printer *p) +static void sdma_v7_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i, j; uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_7_0); uint32_t instance_offset; diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index f27ddfe7c0fb8..2b273f5022be2 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c @@ -1925,9 +1925,9 @@ void vcn_v1_0_ring_end_use(struct amdgpu_ring *ring) mutex_unlock(&ring->adev->vcn.vcn1_jpeg1_workaround); } -static void vcn_v1_0_print_ip_state(void *handle, struct drm_printer *p) +static void vcn_v1_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i, j; uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_1_0); uint32_t inst_off, is_powered; diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c index 5d6accdba4804..b6d41d531ef93 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c @@ -2034,9 +2034,9 @@ static int vcn_v2_0_start_sriov(struct amdgpu_device *adev) return vcn_v2_0_start_mmsch(adev, &adev->virt.mm_table); } -static void vcn_v2_0_print_ip_state(void *handle, struct drm_printer *p) +static void vcn_v2_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i, j; uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_0); uint32_t inst_off, is_powered; diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c index 8896c25fd1d43..6be770a060eff 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c @@ -1926,9 +1926,9 @@ static void vcn_v2_5_set_irq_funcs(struct amdgpu_device *adev) } } -static void vcn_v2_5_print_ip_state(void *handle, struct drm_printer *p) +static void vcn_v2_5_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i, j; uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_5); uint32_t inst_off, is_powered; diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c index 3009f52f62d7c..0c2d698ca0464 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c @@ -2251,9 +2251,9 @@ static void vcn_v3_0_set_irq_funcs(struct amdgpu_device *adev) } } -static void vcn_v3_0_print_ip_state(void *handle, struct drm_printer *p) +static void vcn_v3_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i, j; uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_3_0); uint32_t inst_off; diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c index 17ea10c14e299..d3aa1a5b2529f 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c @@ -2158,9 +2158,9 @@ static void vcn_v4_0_set_irq_funcs(struct amdgpu_device *adev) } } -static void vcn_v4_0_print_ip_state(void *handle, struct drm_printer *p) +static void vcn_v4_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i, j; uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0); uint32_t inst_off, is_powered; diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c index 742bf09ae195e..ca5ac917f07d3 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c @@ -1733,9 +1733,9 @@ static void vcn_v4_0_3_set_irq_funcs(struct amdgpu_device *adev) adev->vcn.inst->irq.funcs = &vcn_v4_0_3_irq_funcs; } -static void vcn_v4_0_3_print_ip_state(void *handle, struct drm_printer *p) +static void vcn_v4_0_3_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i, j; uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_3); uint32_t inst_off, is_powered; diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c index 3fb8b218e2781..0d8aa5a0904b0 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c @@ -1616,9 +1616,9 @@ static void vcn_v4_0_5_set_irq_funcs(struct amdgpu_device *adev) } } -static void vcn_v4_0_5_print_ip_state(void *handle, struct drm_printer *p) +static void vcn_v4_0_5_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i, j; uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_5); uint32_t inst_off, is_powered; diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c index 25ae338df3461..8a2e217ae5c97 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c @@ -1343,9 +1343,9 @@ static void vcn_v5_0_0_set_irq_funcs(struct amdgpu_device *adev) } } -static void vcn_v5_0_print_ip_state(void *handle, struct drm_printer *p) +static void vcn_v5_0_print_ip_state(struct amdgpu_ip_block *ip_block, struct drm_printer *p) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i, j; uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_5_0); uint32_t inst_off, is_powered; diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h index cbb19895ddaf5..9b02ab1c2048a 100644 --- a/drivers/gpu/drm/amd/include/amd_shared.h +++ b/drivers/gpu/drm/amd/include/amd_shared.h @@ -402,7 +402,7 @@ struct amd_ip_funcs { enum amd_powergating_state state); void (*get_clockgating_state)(void *handle, u64 *flags); void (*dump_ip_state)(struct amdgpu_ip_block *ip_block); - void (*print_ip_state)(void *handle, struct drm_printer *p); + void (*print_ip_state)(struct amdgpu_ip_block *ip_block, struct drm_printer *p); }; From 7004ddd39a4a12e468cab4d51c8123e53c38fdd2 Mon Sep 17 00:00:00 2001 From: Jiadong Zhu Date: Fri, 20 Sep 2024 10:54:13 +0800 Subject: [PATCH 1709/1868] drm/amdgpu/sdma5: implement ring reset callback for sdma5 Implement sdma queue reset callback via MMIO. v2: enter/exit safemode when sdma queue reset. Change-Id: I66101cb19557f718663dce61f91d760f845c788b Signed-off-by: Jiadong Zhu Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 88 ++++++++++++++++++++++++++ 1 file changed, 88 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c index d3d2c8bf9000e..397797aef0ea1 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c @@ -1555,6 +1555,93 @@ static int sdma_v5_0_soft_reset(void *handle) return 0; } +static int sdma_v5_0_reset_queue(struct amdgpu_ring *ring, unsigned int vmid) +{ + struct amdgpu_device *adev = ring->adev; + int i, j, r; + u32 rb_cntl, ib_cntl, f32_cntl, freeze, cntl, preempt, soft_reset, stat1_reg; + + if (amdgpu_sriov_vf(adev)) + return -EINVAL; + + for (i = 0; i < adev->sdma.num_instances; i++) { + if (ring == &adev->sdma.instance[i].ring) + break; + } + + if (i == adev->sdma.num_instances) { + DRM_ERROR("sdma instance not found\n"); + return -EINVAL; + } + + amdgpu_gfx_rlc_enter_safe_mode(adev, 0); + + /* stop queue */ + ib_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); + ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); + WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); + + rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); + WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); + + /* engine stop SDMA1_F32_CNTL.HALT to 1 and SDMAx_FREEZE freeze bit to 1 */ + freeze = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_FREEZE)); + freeze = REG_SET_FIELD(freeze, SDMA0_FREEZE, FREEZE, 1); + WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_FREEZE), freeze); + + for (j = 0; j < adev->usec_timeout; j++) { + freeze = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_FREEZE)); + if (REG_GET_FIELD(freeze, SDMA0_FREEZE, FROZEN) & 1) + break; + udelay(1); + } + + /* check sdma copy engine all idle if frozen not received*/ + if (j == adev->usec_timeout) { + stat1_reg = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_STATUS1_REG)); + if ((stat1_reg & 0x3FF) != 0x3FF) { + DRM_ERROR("cannot soft reset as sdma not idle\n"); + r = -ETIMEDOUT; + goto err0; + } + } + + f32_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); + f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1); + WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl); + + cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL)); + cntl = REG_SET_FIELD(cntl, SDMA0_CNTL, UTC_L1_ENABLE, 0); + WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_CNTL), cntl); + + /* soft reset SDMA_GFX_PREEMPT.IB_PREEMPT = 0 mmGRBM_SOFT_RESET.SOFT_RESET_SDMA0/1 = 1 */ + preempt = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_PREEMPT)); + preempt = REG_SET_FIELD(preempt, SDMA0_GFX_PREEMPT, IB_PREEMPT, 0); + WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_PREEMPT), preempt); + + soft_reset = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); + soft_reset |= 1 << GRBM_SOFT_RESET__SOFT_RESET_SDMA0__SHIFT << i; + + WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, soft_reset); + + udelay(50); + + soft_reset &= ~(1 << GRBM_SOFT_RESET__SOFT_RESET_SDMA0__SHIFT << i); + WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, soft_reset); + + /* unfreeze*/ + freeze = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_FREEZE)); + freeze = REG_SET_FIELD(freeze, SDMA0_FREEZE, FREEZE, 0); + WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_FREEZE), freeze); + + r = sdma_v5_0_gfx_resume_instance(adev, i, true); + +err0: + amdgpu_gfx_rlc_exit_safe_mode(adev, 0); + return r; +} + static int sdma_v5_0_ring_preempt_ib(struct amdgpu_ring *ring) { int i, r = 0; @@ -1897,6 +1984,7 @@ static const struct amdgpu_ring_funcs sdma_v5_0_ring_funcs = { .emit_reg_write_reg_wait = sdma_v5_0_ring_emit_reg_write_reg_wait, .init_cond_exec = sdma_v5_0_ring_init_cond_exec, .preempt_ib = sdma_v5_0_ring_preempt_ib, + .reset = sdma_v5_0_reset_queue, }; static void sdma_v5_0_set_ring_funcs(struct amdgpu_device *adev) From dad8a5a2c0a65948825fe778d6534ec8ad37ee06 Mon Sep 17 00:00:00 2001 From: Jiadong Zhu Date: Fri, 20 Sep 2024 11:18:29 +0800 Subject: [PATCH 1710/1868] drm/amdgpu/sdma5.2: split out per instance resume function Extract the resume sequence from sdma_v5_2_gfx_resume for starting/restarting an individual instance. Change-Id: I783d6024c3694478f4ed04d547aa272448e498ce Signed-off-by: Jiadong Zhu Acked-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 247 ++++++++++++++----------- 1 file changed, 136 insertions(+), 111 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c index 8761b54050ca8..95b3b5c3462b6 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c @@ -522,14 +522,17 @@ static void sdma_v5_2_enable(struct amdgpu_device *adev, bool enable) } /** - * sdma_v5_2_gfx_resume - setup and start the async dma engines + * sdma_v5_2_gfx_resume_instance - start/restart a certain sdma engine * * @adev: amdgpu_device pointer + * @i: instance + * @restore: used to restore wptr when restart * - * Set up the gfx DMA ring buffers and enable them. - * Returns 0 for success, error for failure. + * Set up the gfx DMA ring buffers and enable them. On restart, we will restore wptr and rptr. + * Return 0 for success. */ -static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev) + +static int sdma_v5_2_gfx_resume_instance(struct amdgpu_device *adev, int i, bool restore) { struct amdgpu_ring *ring; u32 rb_cntl, ib_cntl; @@ -539,139 +542,161 @@ static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev) u32 temp; u32 wptr_poll_cntl; u64 wptr_gpu_addr; - int i, r; - for (i = 0; i < adev->sdma.num_instances; i++) { - ring = &adev->sdma.instance[i].ring; + ring = &adev->sdma.instance[i].ring; - if (!amdgpu_sriov_vf(adev)) - WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); + if (!amdgpu_sriov_vf(adev)) + WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL), 0); - /* Set ring buffer size in dwords */ - rb_bufsz = order_base_2(ring->ring_size / 4); - rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); - rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); + /* Set ring buffer size in dwords */ + rb_bufsz = order_base_2(ring->ring_size / 4); + rb_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); #ifdef __BIG_ENDIAN - rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); - rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, - RPTR_WRITEBACK_SWAP_ENABLE, 1); + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, + RPTR_WRITEBACK_SWAP_ENABLE, 1); #endif - WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); - - /* Initialize the ring buffer's read and write pointers */ + WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); + + /* Initialize the ring buffer's read and write pointers */ + if (restore) { + WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), lower_32_bits(ring->wptr << 2)); + WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), upper_32_bits(ring->wptr << 2)); + WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2)); + WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2)); + } else { WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR), 0); WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_HI), 0); WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), 0); WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), 0); + } - /* setup the wptr shadow polling */ - wptr_gpu_addr = ring->wptr_gpu_addr; - WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO), - lower_32_bits(wptr_gpu_addr)); - WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI), - upper_32_bits(wptr_gpu_addr)); - wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, - mmSDMA0_GFX_RB_WPTR_POLL_CNTL)); - wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, - SDMA0_GFX_RB_WPTR_POLL_CNTL, - F32_POLL_ENABLE, 1); - WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), - wptr_poll_cntl); - - /* set the wb address whether it's enabled or not */ - WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI), - upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF); - WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO), - lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); - - rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); - - WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8); - WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40); - + /* setup the wptr shadow polling */ + wptr_gpu_addr = ring->wptr_gpu_addr; + WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO), + lower_32_bits(wptr_gpu_addr)); + WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI), + upper_32_bits(wptr_gpu_addr)); + wptr_poll_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, + mmSDMA0_GFX_RB_WPTR_POLL_CNTL)); + wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl, + SDMA0_GFX_RB_WPTR_POLL_CNTL, + F32_POLL_ENABLE, 1); + WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_POLL_CNTL), + wptr_poll_cntl); + + /* set the wb address whether it's enabled or not */ + WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_HI), + upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF); + WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_RPTR_ADDR_LO), + lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC); + + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); + + WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE), ring->gpu_addr >> 8); + WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_BASE_HI), ring->gpu_addr >> 40); + + if (!restore) ring->wptr = 0; - /* before programing wptr to a less value, need set minor_ptr_update first */ - WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1); + /* before programing wptr to a less value, need set minor_ptr_update first */ + WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 1); - if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ - WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2)); - WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2)); - } + if (!amdgpu_sriov_vf(adev)) { /* only bare-metal use register write for wptr */ + WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR), lower_32_bits(ring->wptr << 2)); + WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_WPTR_HI), upper_32_bits(ring->wptr << 2)); + } - doorbell = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL)); - doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET)); + doorbell = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL)); + doorbell_offset = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET)); - if (ring->use_doorbell) { - doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); - doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET, - OFFSET, ring->doorbell_index); - } else { - doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); - } - WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell); - WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset); + if (ring->use_doorbell) { + doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1); + doorbell_offset = REG_SET_FIELD(doorbell_offset, SDMA0_GFX_DOORBELL_OFFSET, + OFFSET, ring->doorbell_index); + } else { + doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0); + } + WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL), doorbell); + WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_DOORBELL_OFFSET), doorbell_offset); - adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, - ring->doorbell_index, - adev->doorbell_index.sdma_doorbell_range); + adev->nbio.funcs->sdma_doorbell_range(adev, i, ring->use_doorbell, + ring->doorbell_index, + adev->doorbell_index.sdma_doorbell_range); - if (amdgpu_sriov_vf(adev)) - sdma_v5_2_ring_set_wptr(ring); + if (amdgpu_sriov_vf(adev)) + sdma_v5_2_ring_set_wptr(ring); - /* set minor_ptr_update to 0 after wptr programed */ + /* set minor_ptr_update to 0 after wptr programed */ - WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0); + WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_MINOR_PTR_UPDATE), 0); - /* SRIOV VF has no control of any of registers below */ - if (!amdgpu_sriov_vf(adev)) { - /* set utc l1 enable flag always to 1 */ - temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL)); - temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); - - /* enable MCBP */ - temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1); - WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), temp); - - /* Set up RESP_MODE to non-copy addresses */ - temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL)); - temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3); - temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9); - WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp); - - /* program default cache read and write policy */ - temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE)); - /* clean read policy and write policy bits */ - temp &= 0xFF0FFF; - temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | - (CACHE_WRITE_POLICY_L2__DEFAULT << 14) | - SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK); - WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp); - - /* unhalt engine */ - temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); - temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); - WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp); - } + /* SRIOV VF has no control of any of registers below */ + if (!amdgpu_sriov_vf(adev)) { + /* set utc l1 enable flag always to 1 */ + temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL)); + temp = REG_SET_FIELD(temp, SDMA0_CNTL, UTC_L1_ENABLE, 1); + + /* enable MCBP */ + temp = REG_SET_FIELD(temp, SDMA0_CNTL, MIDCMD_PREEMPT_ENABLE, 1); + WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), temp); + + /* Set up RESP_MODE to non-copy addresses */ + temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL)); + temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, RESP_MODE, 3); + temp = REG_SET_FIELD(temp, SDMA0_UTCL1_CNTL, REDO_DELAY, 9); + WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_CNTL), temp); + + /* program default cache read and write policy */ + temp = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE)); + /* clean read policy and write policy bits */ + temp &= 0xFF0FFF; + temp |= ((CACHE_READ_POLICY_L2__DEFAULT << 12) | + (CACHE_WRITE_POLICY_L2__DEFAULT << 14) | + SDMA0_UTCL1_PAGE__LLC_NOALLOC_MASK); + WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_UTCL1_PAGE), temp); + + /* unhalt engine */ + temp = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); + temp = REG_SET_FIELD(temp, SDMA0_F32_CNTL, HALT, 0); + WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), temp); + } - /* enable DMA RB */ - rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); - WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); + /* enable DMA RB */ + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); + WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); - ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); - ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); + ib_cntl = RREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); + ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1); #ifdef __BIG_ENDIAN - ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); + ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1); #endif - /* enable DMA IBs */ - WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); + /* enable DMA IBs */ + WREG32_SOC15_IP(GC, sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); - if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */ - sdma_v5_2_ctx_switch_enable(adev, true); - sdma_v5_2_enable(adev, true); - } + if (amdgpu_sriov_vf(adev)) { /* bare-metal sequence doesn't need below to lines */ + sdma_v5_2_ctx_switch_enable(adev, true); + sdma_v5_2_enable(adev, true); + } + + return amdgpu_ring_test_helper(ring); +} - r = amdgpu_ring_test_helper(ring); +/** + * sdma_v5_2_gfx_resume - setup and start the async dma engines + * + * @adev: amdgpu_device pointer + * + * Set up the gfx DMA ring buffers and enable them. + * Returns 0 for success, error for failure. + */ +static int sdma_v5_2_gfx_resume(struct amdgpu_device *adev) +{ + int i, r; + + for (i = 0; i < adev->sdma.num_instances; i++) { + r = sdma_v5_2_gfx_resume_instance(adev, i, false); if (r) return r; } From c644a34bbf2857fccddd2f35a40b2581746860a0 Mon Sep 17 00:00:00 2001 From: chengjya Date: Wed, 9 Oct 2024 19:19:33 +0800 Subject: [PATCH 1711/1868] drm/amdgpu: update the handle ptr in early_init MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit update the handle ptr to amdgpu_ip_block ptr for all functions pointers on early_init. Signed-off-by: Sunil Khatri Reviewed-by: Christian König (cherry picked from commit 8f215d13be0d85de33daffdd1d66efbf1dda33ae) --- drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 24 +++++++++---------- drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c | 5 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/cik.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/cik_ih.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/cz_ih.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 5 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/iceland_ih.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/ih_v6_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/ih_v6_1.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/ih_v7_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.h | 2 +- drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/nv.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/si.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/si_dma.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/si_ih.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/soc15.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/soc21.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/soc24.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 6 ++--- drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vega20_ih.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vi.c | 4 ++-- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 ++--- drivers/gpu/drm/amd/include/amd_shared.h | 2 +- drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c | 4 ++-- drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 4 ++-- .../gpu/drm/amd/pm/powerplay/amd_powerplay.c | 5 ++-- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 4 ++-- 86 files changed, 182 insertions(+), 183 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c index 8ef2018fbff6b..d3c6669f66fba 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c @@ -588,7 +588,7 @@ static int acp_resume(void *handle) return 0; } -static int acp_early_init(void *handle) +static int acp_early_init(struct amdgpu_ip_block *ip_block) { return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 71b1942518df1..8ed1d9b03bab4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -2632,25 +2632,25 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev) total = true; for (i = 0; i < adev->num_ip_blocks; i++) { + ip_block = &adev->ip_blocks[i]; + if ((amdgpu_ip_block_mask & (1 << i)) == 0) { DRM_WARN("disabled ip block: %d <%s>\n", i, adev->ip_blocks[i].version->funcs->name); adev->ip_blocks[i].status.valid = false; - } else { - if (adev->ip_blocks[i].version->funcs->early_init) { - r = adev->ip_blocks[i].version->funcs->early_init((void *)adev); - if (r == -ENOENT) { - adev->ip_blocks[i].status.valid = false; - } else if (r) { - DRM_ERROR("early_init of IP block <%s> failed %d\n", - adev->ip_blocks[i].version->funcs->name, r); - total = false; - } else { - adev->ip_blocks[i].status.valid = true; - } + } else if (ip_block->version->funcs->early_init) { + r = ip_block->version->funcs->early_init(ip_block); + if (r == -ENOENT) { + adev->ip_blocks[i].status.valid = false; + } else if (r) { + DRM_ERROR("early_init of IP block <%s> failed %d\n", + adev->ip_blocks[i].version->funcs->name, r); + total = false; } else { adev->ip_blocks[i].status.valid = true; } + } else { + adev->ip_blocks[i].status.valid = true; } /* get the vbios after the asic_funcs are set up */ if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c index 4766e99dd98fb..7c1f17dc6b4b6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c @@ -122,9 +122,10 @@ static int isp_load_fw_by_psp(struct amdgpu_device *adev) return r; } -static int isp_early_init(void *handle) +static int isp_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + + struct amdgpu_device *adev = ip_block->adev; struct amdgpu_isp *isp = &adev->isp; switch (amdgpu_ip_version(adev, ISP_HWIP, 0)) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index a8ec3ad5beae9..6a7e2d14f363d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -159,9 +159,9 @@ static int psp_init_sriov_microcode(struct psp_context *psp) return ret; } -static int psp_early_init(void *handle) +static int psp_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; struct psp_context *psp = &adev->psp; psp->autoload_supported = true; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c index 6162582d0aa27..d7e3773413676 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c @@ -765,9 +765,9 @@ static int umsch_mm_init(struct amdgpu_device *adev) } -static int umsch_mm_early_init(void *handle) +static int umsch_mm_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; switch (amdgpu_ip_version(adev, VCN_HWIP, 0)) { case IP_VERSION(4, 0, 5): diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c index 5acd20ff59797..c9c4e8c7dc9f5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c @@ -295,9 +295,9 @@ int amdgpu_vpe_ring_fini(struct amdgpu_vpe *vpe) return 0; } -static int vpe_early_init(void *handle) +static int vpe_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; struct amdgpu_vpe *vpe = &adev->vpe; switch (amdgpu_ip_version(adev, VPE_HWIP, 0)) { diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c index cf1d5d462b676..0a0114de11b49 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik.c +++ b/drivers/gpu/drm/amd/amdgpu/cik.c @@ -1985,9 +1985,9 @@ static const struct amdgpu_asic_funcs cik_asic_funcs = .query_video_codecs = &cik_query_video_codecs, }; -static int cik_common_early_init(void *handle) +static int cik_common_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; adev->smc_rreg = &cik_smc_rreg; adev->smc_wreg = &cik_smc_wreg; diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c index 576baa9dbb0e1..5ccd7e2ebf675 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c @@ -283,9 +283,9 @@ static void cik_ih_set_rptr(struct amdgpu_device *adev, WREG32(mmIH_RB_RPTR, ih->rptr); } -static int cik_ih_early_init(void *handle) +static int cik_ih_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int ret; ret = amdgpu_irq_add_domain(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c index 952737de94111..3565dbcf7e38d 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c @@ -918,9 +918,9 @@ static void cik_enable_sdma_mgls(struct amdgpu_device *adev, } } -static int cik_sdma_early_init(void *handle) +static int cik_sdma_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; adev->sdma.num_instances = SDMA_MAX_INSTANCE; diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c index 0726437873845..bbc50a8e3bc48 100644 --- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c @@ -274,9 +274,9 @@ static void cz_ih_set_rptr(struct amdgpu_device *adev, WREG32(mmIH_RB_RPTR, ih->rptr); } -static int cz_ih_early_init(void *handle) +static int cz_ih_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int ret; ret = amdgpu_irq_add_domain(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index e6006da6264e0..8e18fece431f1 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -2748,9 +2748,9 @@ static int dce_v10_0_crtc_init(struct amdgpu_device *adev, int index) return 0; } -static int dce_v10_0_early_init(void *handle) +static int dce_v10_0_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; adev->audio_endpt_rreg = &dce_v10_0_audio_endpt_rreg; adev->audio_endpt_wreg = &dce_v10_0_audio_endpt_wreg; diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index 096ee0e4302d9..870bf80bff5ac 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -2861,9 +2861,9 @@ static int dce_v11_0_crtc_init(struct amdgpu_device *adev, int index) return 0; } -static int dce_v11_0_early_init(void *handle) +static int dce_v11_0_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; adev->audio_endpt_rreg = &dce_v11_0_audio_endpt_rreg; adev->audio_endpt_wreg = &dce_v11_0_audio_endpt_wreg; diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c index 14ea27d3fd51c..a51fa254d770e 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c @@ -2643,9 +2643,9 @@ static int dce_v6_0_crtc_init(struct amdgpu_device *adev, int index) return 0; } -static int dce_v6_0_early_init(void *handle) +static int dce_v6_0_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; adev->audio_endpt_rreg = &dce_v6_0_audio_endpt_rreg; adev->audio_endpt_wreg = &dce_v6_0_audio_endpt_wreg; diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index ddbe5c79f6c72..cc916d2948ac1 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -2653,9 +2653,9 @@ static int dce_v8_0_crtc_init(struct amdgpu_device *adev, int index) return 0; } -static int dce_v8_0_early_init(void *handle) +static int dce_v8_0_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; adev->audio_endpt_rreg = &dce_v8_0_audio_endpt_rreg; adev->audio_endpt_wreg = &dce_v8_0_audio_endpt_wreg; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 0e4849178bda1..244005d356236 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -7774,10 +7774,9 @@ static void gfx_v10_0_set_spm_funcs(struct amdgpu_device *adev) adev->gfx.spmfuncs = &gfx_v10_0_spm_funcs; } - -static int gfx_v10_0_early_init(void *handle) +static int gfx_v10_0_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; adev->gfx.funcs = &gfx_v10_0_gfx_funcs; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index 3f29b36323a15..690cd7b173f72 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -4997,9 +4997,9 @@ static void gfx_v11_0_ring_emit_gds_switch(struct amdgpu_ring *ring, (1 << (oa_size + oa_base)) - (1 << oa_base)); } -static int gfx_v11_0_early_init(void *handle) +static int gfx_v11_0_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; adev->gfx.funcs = &gfx_v11_0_gfx_funcs; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c index 3044436436c86..6423b20e9156c 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c @@ -3695,9 +3695,9 @@ static uint64_t gfx_v12_0_get_gpu_clock_counter(struct amdgpu_device *adev) return clock; } -static int gfx_v12_0_early_init(void *handle) +static int gfx_v12_0_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; adev->gfx.funcs = &gfx_v12_0_gfx_funcs; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c index 564f0b9336b6a..cc9f9b10b435b 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c @@ -3023,9 +3023,9 @@ static const struct amdgpu_rlc_funcs gfx_v6_0_rlc_funcs = { .start = gfx_v6_0_rlc_start }; -static int gfx_v6_0_early_init(void *handle) +static int gfx_v6_0_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; adev->gfx.xcc_mask = 1; adev->gfx.num_gfx_rings = GFX6_NUM_GFX_RINGS; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index f146806c4633b..3babf5b5a9dd2 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -4134,9 +4134,9 @@ static const struct amdgpu_rlc_funcs gfx_v7_0_rlc_funcs = { .update_spm_vmid = gfx_v7_0_update_spm_vmid }; -static int gfx_v7_0_early_init(void *handle) +static int gfx_v7_0_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; adev->gfx.xcc_mask = 1; adev->gfx.num_gfx_rings = GFX7_NUM_GFX_RINGS; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index b3dd8a532f1b5..78c766857abb0 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -5352,9 +5352,9 @@ static void gfx_v8_0_set_spm_funcs(struct amdgpu_device *adev) adev->gfx.spmfuncs = &gfx_v8_0_spm_funcs; } -static int gfx_v8_0_early_init(void *handle) +static int gfx_v8_0_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; adev->gfx.xcc_mask = 1; adev->gfx.num_gfx_rings = GFX8_NUM_GFX_RINGS; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index befb049a97234..9ee87f1949009 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -4862,9 +4862,9 @@ static void gfx_v9_0_set_spm_funcs(struct amdgpu_device *adev) adev->gfx.spmfuncs = &gfx_v9_0_spm_funcs; } -static int gfx_v9_0_early_init(void *handle) +static int gfx_v9_0_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; adev->gfx.funcs = &gfx_v9_0_gfx_funcs; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index eabe0cf6191c1..0dee2102d7598 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -2511,9 +2511,9 @@ static void gfx_v9_4_3_ring_emit_gds_switch(struct amdgpu_ring *ring, (1 << (oa_size + oa_base)) - (1 << oa_base)); } -static int gfx_v9_4_3_early_init(void *handle) +static int gfx_v9_4_3_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), AMDGPU_MAX_COMPUTE_RINGS); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c index ff0ed314661fd..bee6af1f5289a 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c @@ -629,9 +629,9 @@ static void gmc_v10_0_set_gfxhub_funcs(struct amdgpu_device *adev) } -static int gmc_v10_0_early_init(void *handle) +static int gmc_v10_0_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; gmc_v10_0_set_mmhub_funcs(adev); gmc_v10_0_set_gfxhub_funcs(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c index 63ad403eb5fb5..604258f5927b0 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c @@ -600,9 +600,9 @@ static void gmc_v11_0_set_gfxhub_funcs(struct amdgpu_device *adev) } } -static int gmc_v11_0_early_init(void *handle) +static int gmc_v11_0_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; gmc_v11_0_set_gfxhub_funcs(adev); gmc_v11_0_set_mmhub_funcs(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c index 60acf676000b3..7cd3f180c1591 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c @@ -587,9 +587,9 @@ static void gmc_v12_0_set_gfxhub_funcs(struct amdgpu_device *adev) } } -static int gmc_v12_0_early_init(void *handle) +static int gmc_v12_0_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; gmc_v12_0_set_gfxhub_funcs(adev); gmc_v12_0_set_mmhub_funcs(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c index edd3b826c277b..8afcb19998f91 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c @@ -761,9 +761,9 @@ static int gmc_v6_0_convert_vram_type(int mc_seq_vram_type) } } -static int gmc_v6_0_early_init(void *handle) +static int gmc_v6_0_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; gmc_v6_0_set_gmc_funcs(adev); gmc_v6_0_set_irq_funcs(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c index f24ed94b2132c..ece84808dee65 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c @@ -920,9 +920,9 @@ static int gmc_v7_0_convert_vram_type(int mc_seq_vram_type) } } -static int gmc_v7_0_early_init(void *handle) +static int gmc_v7_0_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; gmc_v7_0_set_gmc_funcs(adev); gmc_v7_0_set_irq_funcs(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index 4da5125287b37..94ee112c81382 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -1031,9 +1031,9 @@ static int gmc_v8_0_convert_vram_type(int mc_seq_vram_type) } } -static int gmc_v8_0_early_init(void *handle) +static int gmc_v8_0_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; gmc_v8_0_set_gmc_funcs(adev); gmc_v8_0_set_irq_funcs(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index cffda0a045b9b..84537abe1f5a4 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -1547,9 +1547,9 @@ static void gmc_v9_0_set_xgmi_ras_funcs(struct amdgpu_device *adev) adev->gmc.xgmi.ras = &xgmi_ras; } -static int gmc_v9_0_early_init(void *handle) +static int gmc_v9_0_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; /* * 9.4.0, 9.4.1 and 9.4.3 don't have XGMI defined diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c index 07984f7c3ae77..87b29600cf1fb 100644 --- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c @@ -273,9 +273,9 @@ static void iceland_ih_set_rptr(struct amdgpu_device *adev, WREG32(mmIH_RB_RPTR, ih->rptr); } -static int iceland_ih_early_init(void *handle) +static int iceland_ih_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int ret; ret = amdgpu_irq_add_domain(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c index 18a761d6ef330..fa6c7e5fbbe3b 100644 --- a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c @@ -559,9 +559,9 @@ static void ih_v6_0_set_self_irq_funcs(struct amdgpu_device *adev) adev->irq.self_irq.funcs = &ih_v6_0_self_irq_funcs; } -static int ih_v6_0_early_init(void *handle) +static int ih_v6_0_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; ih_v6_0_set_interrupt_funcs(adev); ih_v6_0_set_self_irq_funcs(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c index 2e0469feca1e9..ebe23630e8f67 100644 --- a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c +++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c @@ -532,9 +532,9 @@ static void ih_v6_1_set_self_irq_funcs(struct amdgpu_device *adev) adev->irq.self_irq.funcs = &ih_v6_1_self_irq_funcs; } -static int ih_v6_1_early_init(void *handle) +static int ih_v6_1_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int ret; ret = amdgpu_irq_add_domain(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c index 6852081fcff21..1619f0ba4d1b9 100644 --- a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c @@ -528,9 +528,9 @@ static void ih_v7_0_set_self_irq_funcs(struct amdgpu_device *adev) adev->irq.self_irq.funcs = &ih_v7_0_self_irq_funcs; } -static int ih_v7_0_early_init(void *handle) +static int ih_v7_0_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; ih_v7_0_set_interrupt_funcs(adev); ih_v7_0_set_self_irq_funcs(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c index 6e0e88076224b..8effd6dc65d41 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c @@ -462,9 +462,9 @@ static int jpeg_v1_0_process_interrupt(struct amdgpu_device *adev, * * Set ring and irq function pointers */ -int jpeg_v1_0_early_init(void *handle) +int jpeg_v1_0_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; adev->jpeg.num_jpeg_inst = 1; adev->jpeg.num_jpeg_rings = 1; diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.h b/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.h index 9654d22e03763..791de235cd8bd 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.h +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.h @@ -24,7 +24,7 @@ #ifndef __JPEG_V1_0_H__ #define __JPEG_V1_0_H__ -int jpeg_v1_0_early_init(void *handle); +int jpeg_v1_0_early_init(struct amdgpu_ip_block *ip_block); int jpeg_v1_0_sw_init(void *handle); void jpeg_v1_0_sw_fini(void *handle); void jpeg_v1_0_start(struct amdgpu_device *adev, int mode); diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c index 41c0f8750dc1d..341c551dad8b0 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c @@ -45,9 +45,9 @@ static int jpeg_v2_0_set_powergating_state(void *handle, * * Set ring and irq function pointers */ -static int jpeg_v2_0_early_init(void *handle) +static int jpeg_v2_0_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; adev->jpeg.num_jpeg_inst = 1; adev->jpeg.num_jpeg_rings = 1; diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c index eedb9a829d950..ec0fa685e1275 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c @@ -54,9 +54,9 @@ static int amdgpu_ih_clientid_jpeg[] = { * * Set ring and irq function pointers */ -static int jpeg_v2_5_early_init(void *handle) +static int jpeg_v2_5_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; u32 harvest; int i; diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c index b1e7fd25afbcb..dd00daa1d7eda 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c @@ -46,9 +46,9 @@ static int jpeg_v3_0_set_powergating_state(void *handle, * * Set ring and irq function pointers */ -static int jpeg_v3_0_early_init(void *handle) +static int jpeg_v3_0_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; u32 harvest; diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c index 6c5c1a68a9b7b..b147e0eba31da 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c @@ -52,9 +52,9 @@ static void jpeg_v4_0_dec_ring_set_wptr(struct amdgpu_ring *ring); * * Set ring and irq function pointers */ -static int jpeg_v4_0_early_init(void *handle) +static int jpeg_v4_0_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; adev->jpeg.num_jpeg_inst = 1; diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c index c274b05351c66..270167c20cfff 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c @@ -72,9 +72,9 @@ static inline bool jpeg_v4_0_3_normalizn_reqd(struct amdgpu_device *adev) * * Set ring and irq function pointers */ -static int jpeg_v4_0_3_early_init(void *handle) +static int jpeg_v4_0_3_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; adev->jpeg.num_jpeg_rings = AMDGPU_MAX_JPEG_RINGS; diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c index 44eeed445ea91..48ab3e0a62d25 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c @@ -65,9 +65,9 @@ static int amdgpu_ih_clientid_jpeg[] = { * * Set ring and irq function pointers */ -static int jpeg_v4_0_5_early_init(void *handle) +static int jpeg_v4_0_5_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; switch (amdgpu_ip_version(adev, UVD_HWIP, 0)) { case IP_VERSION(4, 0, 5): diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c index d662aa841f971..61288104060de 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c @@ -46,9 +46,9 @@ static int jpeg_v5_0_0_set_powergating_state(void *handle, * * Set ring and irq function pointers */ -static int jpeg_v5_0_0_early_init(void *handle) +static int jpeg_v5_0_0_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; adev->jpeg.num_jpeg_inst = 1; adev->jpeg.num_jpeg_rings = 1; diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c index e2b3f859a1c05..d476cf771bbe6 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c @@ -1653,9 +1653,9 @@ static int mes_v11_0_resume(void *handle) return amdgpu_mes_resume(adev); } -static int mes_v11_0_early_init(void *handle) +static int mes_v11_0_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int pipe, r; for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c index 8d27421689c9d..a490d0e2c2cb4 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c @@ -1617,9 +1617,9 @@ static int mes_v12_0_resume(void *handle) return amdgpu_mes_resume(adev); } -static int mes_v12_0_early_init(void *handle) +static int mes_v12_0_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int pipe, r; for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c index b281462093f11..17aab897f86b9 100644 --- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c @@ -542,9 +542,9 @@ static void navi10_ih_set_self_irq_funcs(struct amdgpu_device *adev) adev->irq.self_irq.funcs = &navi10_ih_self_irq_funcs; } -static int navi10_ih_early_init(void *handle) +static int navi10_ih_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; navi10_ih_set_interrupt_funcs(adev); navi10_ih_set_self_irq_funcs(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index 4938e6b340e9e..63a3c725ceb95 100644 --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c @@ -634,9 +634,9 @@ static const struct amdgpu_asic_funcs nv_asic_funcs = { .query_video_codecs = &nv_query_video_codecs, }; -static int nv_common_early_init(void *handle) +static int nv_common_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; adev->nbio.funcs->set_reg_remap(adev); adev->smc_rreg = NULL; diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c index 725392522267f..5b81985588690 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c @@ -807,9 +807,9 @@ static void sdma_v2_4_ring_emit_wreg(struct amdgpu_ring *ring, amdgpu_ring_write(ring, val); } -static int sdma_v2_4_early_init(void *handle) +static int sdma_v2_4_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; adev->sdma.num_instances = SDMA_MAX_INSTANCE; diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c index e65194fe94af6..37275b38bca82 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c @@ -1080,9 +1080,9 @@ static void sdma_v3_0_ring_emit_wreg(struct amdgpu_ring *ring, amdgpu_ring_write(ring, val); } -static int sdma_v3_0_early_init(void *handle) +static int sdma_v3_0_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; switch (adev->asic_type) { diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index 197a0cbda4bfd..101b38a4d5ced 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c @@ -1752,9 +1752,9 @@ static bool sdma_v4_0_fw_support_paging_queue(struct amdgpu_device *adev) } } -static int sdma_v4_0_early_init(void *handle) +static int sdma_v4_0_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; r = sdma_v4_0_init_microcode(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c index d577b973d0a40..c7c4456586cc9 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c @@ -1290,9 +1290,9 @@ static bool sdma_v4_4_2_fw_support_paging_queue(struct amdgpu_device *adev) } } -static int sdma_v4_4_2_early_init(void *handle) +static int sdma_v4_4_2_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; r = sdma_v4_4_2_init_microcode(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c index 397797aef0ea1..475629702fa61 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c @@ -1389,9 +1389,9 @@ static void sdma_v5_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask); } -static int sdma_v5_0_early_init(void *handle) +static int sdma_v5_0_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; r = sdma_v5_0_init_microcode(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c index 95b3b5c3462b6..17b90b01c4f23 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c @@ -1241,9 +1241,9 @@ static void sdma_v5_2_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask); } -static int sdma_v5_2_early_init(void *handle) +static int sdma_v5_2_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; r = amdgpu_sdma_init_microcode(adev, 0, true); diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c index 5eafc81e82f94..5b549e00143ee 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c @@ -1294,9 +1294,9 @@ static void sdma_v6_0_set_ras_funcs(struct amdgpu_device *adev) } } -static int sdma_v6_0_early_init(void *handle) +static int sdma_v6_0_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; r = amdgpu_sdma_init_microcode(adev, 0, true); diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c index 8509769db9c01..90baf9a20b227 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c @@ -1253,9 +1253,9 @@ static void sdma_v7_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask); } -static int sdma_v7_0_early_init(void *handle) +static int sdma_v7_0_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; r = amdgpu_sdma_init_microcode(adev, 0, true); diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c index 85235470e872c..93c68abf447a6 100644 --- a/drivers/gpu/drm/amd/amdgpu/si.c +++ b/drivers/gpu/drm/amd/amdgpu/si.c @@ -2022,9 +2022,9 @@ static uint32_t si_get_rev_id(struct amdgpu_device *adev) >> CC_DRM_ID_STRAPS__ATI_REV_ID__SHIFT; } -static int si_common_early_init(void *handle) +static int si_common_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; adev->smc_rreg = &si_smc_rreg; adev->smc_wreg = &si_smc_wreg; diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c index 11db5b7558321..791d492e991d4 100644 --- a/drivers/gpu/drm/amd/amdgpu/si_dma.c +++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c @@ -457,9 +457,9 @@ static void si_dma_ring_emit_wreg(struct amdgpu_ring *ring, amdgpu_ring_write(ring, val); } -static int si_dma_early_init(void *handle) +static int si_dma_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; adev->sdma.num_instances = 2; diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c b/drivers/gpu/drm/amd/amdgpu/si_ih.c index 5237395e4fab5..bd2ae82554982 100644 --- a/drivers/gpu/drm/amd/amdgpu/si_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c @@ -156,9 +156,9 @@ static void si_ih_set_rptr(struct amdgpu_device *adev, WREG32(IH_RB_RPTR, ih->rptr); } -static int si_ih_early_init(void *handle) +static int si_ih_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; si_ih_set_interrupt_funcs(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index 619933f252aa5..e1161027ec3b7 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -933,9 +933,9 @@ static const struct amdgpu_asic_funcs aqua_vanjaram_asic_funcs = .get_reg_state = &aqua_vanjaram_get_reg_state, }; -static int soc15_common_early_init(void *handle) +static int soc15_common_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; adev->nbio.funcs->set_reg_remap(adev); adev->smc_rreg = NULL; diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c index d30ad7d56def9..c9e88cd4349ae 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc21.c +++ b/drivers/gpu/drm/amd/amdgpu/soc21.c @@ -556,9 +556,9 @@ static const struct amdgpu_asic_funcs soc21_asic_funcs = { .update_umd_stable_pstate = &soc21_update_umd_stable_pstate, }; -static int soc21_common_early_init(void *handle) +static int soc21_common_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; adev->nbio.funcs->set_reg_remap(adev); adev->smc_rreg = NULL; diff --git a/drivers/gpu/drm/amd/amdgpu/soc24.c b/drivers/gpu/drm/amd/amdgpu/soc24.c index fd4c3d4f83879..3dcb3d953509d 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc24.c +++ b/drivers/gpu/drm/amd/amdgpu/soc24.c @@ -363,9 +363,9 @@ static const struct amdgpu_asic_funcs soc24_asic_funcs = { .update_umd_stable_pstate = &soc24_update_umd_stable_pstate, }; -static int soc24_common_early_init(void *handle) +static int soc24_common_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; adev->nbio.funcs->set_reg_remap(adev); adev->smc_rreg = NULL; diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c index 24d49d813607f..ae27dac941177 100644 --- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c @@ -283,9 +283,9 @@ static void tonga_ih_set_rptr(struct amdgpu_device *adev, } } -static int tonga_ih_early_init(void *handle) +static int tonga_ih_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int ret; ret = amdgpu_irq_add_domain(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c index 805d6662c88b6..d5e2b9639238c 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c @@ -531,9 +531,9 @@ static void uvd_v3_1_set_irq_funcs(struct amdgpu_device *adev) } -static int uvd_v3_1_early_init(void *handle) +static int uvd_v3_1_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; adev->uvd.num_uvd_inst = 1; uvd_v3_1_set_ring_funcs(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c index 3f19c606f4de5..5c46174dabbf3 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c @@ -90,9 +90,9 @@ static void uvd_v4_2_ring_set_wptr(struct amdgpu_ring *ring) WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); } -static int uvd_v4_2_early_init(void *handle) +static int uvd_v4_2_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; adev->uvd.num_uvd_inst = 1; uvd_v4_2_set_ring_funcs(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c index efd903c21d48e..fd4acb1300f93 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c @@ -88,9 +88,9 @@ static void uvd_v5_0_ring_set_wptr(struct amdgpu_ring *ring) WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); } -static int uvd_v5_0_early_init(void *handle) +static int uvd_v5_0_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; adev->uvd.num_uvd_inst = 1; uvd_v5_0_set_ring_funcs(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c index 495de50684554..e05e81d6fbd49 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c @@ -354,9 +354,9 @@ static int uvd_v6_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout) return r; } -static int uvd_v6_0_early_init(void *handle) +static int uvd_v6_0_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; adev->uvd.num_uvd_inst = 1; if (!(adev->flags & AMD_IS_APU) && diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c index 6068b784dc693..15b8f6211bb58 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c @@ -361,9 +361,9 @@ static int uvd_v7_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout) return r; } -static int uvd_v7_0_early_init(void *handle) +static int uvd_v7_0_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (adev->asic_type == CHIP_VEGA20) { u32 harvest; diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c index 66fada199bda2..97ce06228a910 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c @@ -398,9 +398,9 @@ static void vce_v2_0_enable_mgcg(struct amdgpu_device *adev, bool enable, } } -static int vce_v2_0_early_init(void *handle) +static int vce_v2_0_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; adev->vce.num_rings = 2; diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c index 4bfba2931b088..31ca855a950af 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c @@ -396,9 +396,9 @@ static unsigned vce_v3_0_get_harvest_config(struct amdgpu_device *adev) } } -static int vce_v3_0_early_init(void *handle) +static int vce_v3_0_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; adev->vce.harvest_config = vce_v3_0_get_harvest_config(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c index 0748bf44c8808..14ead62ec57db 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c @@ -407,9 +407,9 @@ static int vce_v4_0_stop(struct amdgpu_device *adev) return 0; } -static int vce_v4_0_early_init(void *handle) +static int vce_v4_0_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (amdgpu_sriov_vf(adev)) /* currently only VCN0 support SRIOV */ adev->vce.num_rings = 1; diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index 2b273f5022be2..b079afa9fff7c 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c @@ -100,9 +100,9 @@ static void vcn_v1_0_ring_begin_use(struct amdgpu_ring *ring); * Set ring and irq function pointers * Load microcode from filesystem */ -static int vcn_v1_0_early_init(void *handle) +static int vcn_v1_0_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; adev->vcn.num_enc_rings = 2; @@ -110,7 +110,7 @@ static int vcn_v1_0_early_init(void *handle) vcn_v1_0_set_enc_ring_funcs(adev); vcn_v1_0_set_irq_funcs(adev); - jpeg_v1_0_early_init(handle); + jpeg_v1_0_early_init(ip_block); return amdgpu_vcn_early_init(adev); } diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c index b6d41d531ef93..18383e7a13ce1 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c @@ -105,9 +105,9 @@ static int vcn_v2_0_start_sriov(struct amdgpu_device *adev); * Set ring and irq function pointers * Load microcode from filesystem */ -static int vcn_v2_0_early_init(void *handle) +static int vcn_v2_0_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (amdgpu_sriov_vf(adev)) adev->vcn.num_enc_rings = 1; diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c index 6be770a060eff..0ba7bc0524479 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c @@ -115,9 +115,9 @@ static int amdgpu_ih_clientid_vcns[] = { * Set ring and irq function pointers * Load microcode from filesystem */ -static int vcn_v2_5_early_init(void *handle) +static int vcn_v2_5_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (amdgpu_sriov_vf(adev)) { adev->vcn.num_vcn_inst = 2; diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c index 0c2d698ca0464..7204e3630052b 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c @@ -121,9 +121,9 @@ static void vcn_v3_0_enc_ring_set_wptr(struct amdgpu_ring *ring); * Set ring and irq function pointers * Load microcode from filesystem */ -static int vcn_v3_0_early_init(void *handle) +static int vcn_v3_0_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (amdgpu_sriov_vf(adev)) { adev->vcn.num_vcn_inst = VCN_INSTANCES_SIENNA_CICHLID; diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c index d3aa1a5b2529f..cfebd1255b758 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c @@ -111,9 +111,9 @@ static void vcn_v4_0_set_ras_funcs(struct amdgpu_device *adev); * Set ring and irq function pointers * Load microcode from filesystem */ -static int vcn_v4_0_early_init(void *handle) +static int vcn_v4_0_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i; if (amdgpu_sriov_vf(adev)) { diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c index ca5ac917f07d3..d64f4735ebf37 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c @@ -102,9 +102,9 @@ static void vcn_v4_0_3_enable_ras(struct amdgpu_device *adev, * * Set ring and irq function pointers */ -static int vcn_v4_0_3_early_init(void *handle) +static int vcn_v4_0_3_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; /* re-use enc ring as unified ring */ adev->vcn.num_enc_rings = 1; diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c index 0d8aa5a0904b0..d13f07faae8a0 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c @@ -109,9 +109,9 @@ static void vcn_v4_0_5_unified_ring_set_wptr(struct amdgpu_ring *ring); * Set ring and irq function pointers * Load microcode from filesystem */ -static int vcn_v4_0_5_early_init(void *handle) +static int vcn_v4_0_5_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; /* re-use enc ring as unified ring */ adev->vcn.num_enc_rings = 1; diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c index 8a2e217ae5c97..d9c92df3843f0 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c @@ -92,9 +92,9 @@ static void vcn_v5_0_0_unified_ring_set_wptr(struct amdgpu_ring *ring); * Set ring and irq function pointers * Load microcode from filesystem */ -static int vcn_v5_0_0_early_init(void *handle) +static int vcn_v5_0_0_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; /* re-use enc ring as unified ring */ adev->vcn.num_enc_rings = 1; diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c index bf68e18e3824b..5b0c81d510e7b 100644 --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c @@ -472,9 +472,9 @@ static void vega10_ih_set_self_irq_funcs(struct amdgpu_device *adev) adev->irq.self_irq.funcs = &vega10_ih_self_irq_funcs; } -static int vega10_ih_early_init(void *handle) +static int vega10_ih_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; vega10_ih_set_interrupt_funcs(adev); vega10_ih_set_self_irq_funcs(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c index ac439f0565e35..dec7279c81062 100644 --- a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c @@ -526,9 +526,9 @@ static void vega20_ih_set_self_irq_funcs(struct amdgpu_device *adev) adev->irq.self_irq.funcs = &vega20_ih_self_irq_funcs; } -static int vega20_ih_early_init(void *handle) +static int vega20_ih_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; vega20_ih_set_interrupt_funcs(adev); vega20_ih_set_self_irq_funcs(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index d39c670f62204..c9ee4491ba64c 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/drivers/gpu/drm/amd/amdgpu/vi.c @@ -1455,9 +1455,9 @@ static const struct amdgpu_asic_funcs vi_asic_funcs = #define CZ_REV_BRISTOL(rev) \ ((rev >= 0xC8 && rev <= 0xCE) || (rev >= 0xE1 && rev <= 0xE6)) -static int vi_common_early_init(void *handle) +static int vi_common_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (adev->flags & AMD_IS_APU) { adev->smc_rreg = &cz_smc_rreg; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 6bef25af62b92..ed4e2defbb444 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -981,7 +981,7 @@ static int dm_set_powergating_state(void *handle, } /* Prototypes of private functions */ -static int dm_early_init(void *handle); +static int dm_early_init(struct amdgpu_ip_block *ip_block); /* Allocate memory for FBC compressed data */ static void amdgpu_dm_fbc_init(struct drm_connector *connector) @@ -5354,9 +5354,9 @@ static int dm_init_microcode(struct amdgpu_device *adev) return r; } -static int dm_early_init(void *handle) +static int dm_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; struct amdgpu_mode_info *mode_info = &adev->mode_info; struct atom_context *ctx = mode_info->atom_context; int index = GetIndexIntoMasterTable(DATA, Object_Header); diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h index 9b02ab1c2048a..67d75ac339bf1 100644 --- a/drivers/gpu/drm/amd/include/amd_shared.h +++ b/drivers/gpu/drm/amd/include/amd_shared.h @@ -379,7 +379,7 @@ struct amdgpu_ip_block; struct amd_ip_funcs { char *name; - int (*early_init)(void *handle); + int (*early_init)(struct amdgpu_ip_block *ip_block); int (*late_init)(void *handle); int (*sw_init)(void *handle); int (*sw_fini)(void *handle); diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c index e8b6989a40f35..ff71af96eb1a9 100644 --- a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c @@ -2954,9 +2954,9 @@ static int kv_dpm_get_temp(void *handle) return actual_temp; } -static int kv_dpm_early_init(void *handle) +static int kv_dpm_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; adev->powerplay.pp_funcs = &kv_dpm_funcs; adev->powerplay.pp_handle = adev; diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c index 43028e776c932..5aa4eca21708c 100644 --- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c @@ -7930,10 +7930,10 @@ static void si_dpm_print_power_state(void *handle, amdgpu_dpm_print_ps_status(adev, rps); } -static int si_dpm_early_init(void *handle) +static int si_dpm_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; adev->powerplay.pp_funcs = &si_dpm_funcs; adev->powerplay.pp_handle = adev; diff --git a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c index a71c6117d7e54..2af325b9fc197 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c +++ b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c @@ -75,11 +75,10 @@ static void amd_powerplay_destroy(struct amdgpu_device *adev) hwmgr = NULL; } -static int pp_early_init(void *handle) +static int pp_early_init(struct amdgpu_ip_block *ip_block) { int ret; - struct amdgpu_device *adev = handle; - + struct amdgpu_device *adev = ip_block->adev; ret = amd_powerplay_create(adev); if (ret != 0) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 814202c073191..8b0182d589b7b 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -742,9 +742,9 @@ static int smu_set_funcs(struct amdgpu_device *adev) return 0; } -static int smu_early_init(void *handle) +static int smu_early_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; struct smu_context *smu; int r; From b7d8b507a3d63bd62330b1b23e07eeab9e07fe2c Mon Sep 17 00:00:00 2001 From: Jiadong Zhu Date: Fri, 20 Sep 2024 11:29:41 +0800 Subject: [PATCH 1712/1868] drm/amdgpu/sdma5.2: implement ring reset callback for sdma5.2 Implement sdma queue reset callback via MMIO. v2: enter/exit safemode for mmio queue reset. Signed-off-by: Jiadong Zhu Reviewed-by: Alex Deucher (cherry picked from commit 9f4b2ea3e07e707537b4779c01f053191fad9e59) --- drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 91 ++++++++++++++++++++++++++ 1 file changed, 91 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c index 17b90b01c4f23..65a93de9c904f 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c @@ -1424,6 +1424,96 @@ static int sdma_v5_2_wait_for_idle(void *handle) return -ETIMEDOUT; } +static int sdma_v5_2_reset_queue(struct amdgpu_ring *ring, unsigned int vmid) +{ + struct amdgpu_device *adev = ring->adev; + int i, j, r; + u32 rb_cntl, ib_cntl, f32_cntl, freeze, cntl, preempt, soft_reset, stat1_reg; + + if (amdgpu_sriov_vf(adev)) + return -EINVAL; + + for (i = 0; i < adev->sdma.num_instances; i++) { + if (ring == &adev->sdma.instance[i].ring) + break; + } + + if (i == adev->sdma.num_instances) { + DRM_ERROR("sdma instance not found\n"); + return -EINVAL; + } + + amdgpu_gfx_rlc_enter_safe_mode(adev, 0); + + /* stop queue */ + ib_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL)); + ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0); + WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_IB_CNTL), ib_cntl); + + rb_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); + rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); + WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); + + /*engine stop SDMA1_F32_CNTL.HALT to 1 and SDMAx_FREEZE freeze bit to 1 */ + freeze = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_FREEZE)); + freeze = REG_SET_FIELD(freeze, SDMA0_FREEZE, FREEZE, 1); + WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_FREEZE), freeze); + + for (j = 0; j < adev->usec_timeout; j++) { + freeze = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_FREEZE)); + + if (REG_GET_FIELD(freeze, SDMA0_FREEZE, FROZEN) & 1) + break; + udelay(1); + } + + + if (j == adev->usec_timeout) { + stat1_reg = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_STATUS1_REG)); + if ((stat1_reg & 0x3FF) != 0x3FF) { + DRM_ERROR("cannot soft reset as sdma not idle\n"); + r = -ETIMEDOUT; + goto err0; + } + } + + f32_cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL)); + f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1); + WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_F32_CNTL), f32_cntl); + + cntl = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL)); + cntl = REG_SET_FIELD(cntl, SDMA0_CNTL, UTC_L1_ENABLE, 0); + WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_CNTL), cntl); + + /* soft reset SDMA_GFX_PREEMPT.IB_PREEMPT = 0 mmGRBM_SOFT_RESET.SOFT_RESET_SDMA0/1 = 1 */ + preempt = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_PREEMPT)); + preempt = REG_SET_FIELD(preempt, SDMA0_GFX_PREEMPT, IB_PREEMPT, 0); + WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_GFX_PREEMPT), preempt); + + soft_reset = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET); + soft_reset |= 1 << GRBM_SOFT_RESET__SOFT_RESET_SDMA0__SHIFT << i; + + + WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, soft_reset); + + udelay(50); + + soft_reset &= ~(1 << GRBM_SOFT_RESET__SOFT_RESET_SDMA0__SHIFT << i); + + WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, soft_reset); + + /* unfreeze and unhalt */ + freeze = RREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_FREEZE)); + freeze = REG_SET_FIELD(freeze, SDMA0_FREEZE, FREEZE, 0); + WREG32(sdma_v5_2_get_reg_offset(adev, i, mmSDMA0_FREEZE), freeze); + + r = sdma_v5_2_gfx_resume_instance(adev, i, true); + +err0: + amdgpu_gfx_rlc_exit_safe_mode(adev, 0); + return r; +} + static int sdma_v5_2_ring_preempt_ib(struct amdgpu_ring *ring) { int i, r = 0; @@ -1859,6 +1949,7 @@ static const struct amdgpu_ring_funcs sdma_v5_2_ring_funcs = { .emit_reg_write_reg_wait = sdma_v5_2_ring_emit_reg_write_reg_wait, .init_cond_exec = sdma_v5_2_ring_init_cond_exec, .preempt_ib = sdma_v5_2_ring_preempt_ib, + .reset = sdma_v5_2_reset_queue, }; static void sdma_v5_2_set_ring_funcs(struct amdgpu_device *adev) From 67a4809b721d7f538a36b14f1e7689c4885614a0 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Wed, 18 Sep 2024 15:57:08 +0530 Subject: [PATCH 1713/1868] drm/amdgpu: Add option to refresh NPS data In certain use cases, NPS data needs to be refreshed again from discovery table. Add API parameter to refresh NPS data from discovery table. Signed-off-by: Lijo Lazar Reviewed-by: Rajneesh Bhardwaj (cherry picked from commit b3fa8f8c4225d4ae4c01aa673413c0c0efe20ddb) --- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 68 +++++++++++++++---- drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 2 +- 3 files changed, 55 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c index 3f3ff849f9bde..0692eb154fb9b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c @@ -1745,37 +1745,75 @@ union nps_info { struct nps_info_v1_0 v1; }; +static int amdgpu_discovery_refresh_nps_info(struct amdgpu_device *adev, + union nps_info *nps_data) +{ + uint64_t vram_size, pos, offset; + struct nps_info_header *nhdr; + struct binary_header bhdr; + uint16_t checksum; + + vram_size = (uint64_t)RREG32(mmRCC_CONFIG_MEMSIZE) << 20; + pos = vram_size - DISCOVERY_TMR_OFFSET; + amdgpu_device_vram_access(adev, pos, &bhdr, sizeof(bhdr), false); + + offset = le16_to_cpu(bhdr.table_list[NPS_INFO].offset); + checksum = le16_to_cpu(bhdr.table_list[NPS_INFO].checksum); + + amdgpu_device_vram_access(adev, (pos + offset), nps_data, + sizeof(*nps_data), false); + + nhdr = (struct nps_info_header *)(nps_data); + if (!amdgpu_discovery_verify_checksum((uint8_t *)nps_data, + le32_to_cpu(nhdr->size_bytes), + checksum)) { + dev_err(adev->dev, "nps data refresh, checksum mismatch\n"); + return -EINVAL; + } + + return 0; +} + int amdgpu_discovery_get_nps_info(struct amdgpu_device *adev, uint32_t *nps_type, struct amdgpu_gmc_memrange **ranges, - int *range_cnt) + int *range_cnt, bool refresh) { struct amdgpu_gmc_memrange *mem_ranges; struct binary_header *bhdr; union nps_info *nps_info; + union nps_info nps_data; u16 offset; - int i; + int i, r; if (!nps_type || !range_cnt || !ranges) return -EINVAL; - if (!adev->mman.discovery_bin) { - dev_err(adev->dev, - "fetch mem range failed, ip discovery uninitialized\n"); - return -EINVAL; - } + if (refresh) { + r = amdgpu_discovery_refresh_nps_info(adev, &nps_data); + if (r) + return r; + nps_info = &nps_data; + } else { + if (!adev->mman.discovery_bin) { + dev_err(adev->dev, + "fetch mem range failed, ip discovery uninitialized\n"); + return -EINVAL; + } - bhdr = (struct binary_header *)adev->mman.discovery_bin; - offset = le16_to_cpu(bhdr->table_list[NPS_INFO].offset); + bhdr = (struct binary_header *)adev->mman.discovery_bin; + offset = le16_to_cpu(bhdr->table_list[NPS_INFO].offset); - if (!offset) - return -ENOENT; + if (!offset) + return -ENOENT; - /* If verification fails, return as if NPS table doesn't exist */ - if (amdgpu_discovery_verify_npsinfo(adev, bhdr)) - return -ENOENT; + /* If verification fails, return as if NPS table doesn't exist */ + if (amdgpu_discovery_verify_npsinfo(adev, bhdr)) + return -ENOENT; - nps_info = (union nps_info *)(adev->mman.discovery_bin + offset); + nps_info = + (union nps_info *)(adev->mman.discovery_bin + offset); + } switch (le16_to_cpu(nps_info->v1.header.version_major)) { case 1: diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h index f5d36525ec3ef..b44d56465c5b9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h @@ -33,6 +33,6 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev); int amdgpu_discovery_get_nps_info(struct amdgpu_device *adev, uint32_t *nps_type, struct amdgpu_gmc_memrange **ranges, - int *range_cnt); + int *range_cnt, bool refresh); #endif /* __AMDGPU_DISCOVERY__ */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c index ea8142bc60515..041103073ea7f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c @@ -1193,7 +1193,7 @@ int amdgpu_gmc_get_nps_memranges(struct amdgpu_device *adev, return -EINVAL; ret = amdgpu_discovery_get_nps_info(adev, &nps_type, &ranges, - &range_cnt); + &range_cnt, false); if (ret) return ret; From 1f70f4627cee281f5cb5297a2c27a44cd23dec47 Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Tue, 24 Sep 2024 19:22:05 +0800 Subject: [PATCH 1714/1868] drm/amdgpu: Add supported partition mode node Add sysfs node to show supported partition modes across all NPS modes Signed-off-by: Asad Kamal Reviewed-by: Lijo Lazar Reviewed-by: Hawking Zhang (cherry picked from commit f05f751625e7fe1dae3b1bec41be9aa118eabecd) --- drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c | 45 +++++++++++++++++++++++-- 1 file changed, 42 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c index 39b181e2d9546..6e0d6da1df500 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c @@ -462,6 +462,15 @@ static struct attribute *xcp_cfg_res_sysfs_attrs[] = { &XCP_CFG_SYSFS_RES_ATTR_PTR(num_inst), &XCP_CFG_SYSFS_RES_ATTR_PTR(num_shared), NULL }; + +static const char *xcp_desc[] = { + [AMDGPU_SPX_PARTITION_MODE] = "SPX", + [AMDGPU_DPX_PARTITION_MODE] = "DPX", + [AMDGPU_TPX_PARTITION_MODE] = "TPX", + [AMDGPU_QPX_PARTITION_MODE] = "QPX", + [AMDGPU_CPX_PARTITION_MODE] = "CPX", +}; + #ifdef HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE ATTRIBUTE_GROUPS(xcp_cfg_res_sysfs); #endif @@ -516,6 +525,27 @@ static int amdgpu_xcp_get_res_info(struct amdgpu_xcp_mgr *xcp_mgr, } #define to_xcp_cfg(x) container_of(x, struct amdgpu_xcp_cfg, kobj) +static ssize_t supported_xcp_configs_show(struct kobject *kobj, + struct kobj_attribute *attr, char *buf) +{ + struct amdgpu_xcp_cfg *xcp_cfg = to_xcp_cfg(kobj); + struct amdgpu_xcp_mgr *xcp_mgr = xcp_cfg->xcp_mgr; + int size = 0, mode; + char *sep = ""; + + if (!xcp_mgr || !xcp_mgr->supp_xcp_modes) + return sysfs_emit(buf, "Not supported\n"); + + for_each_inst(mode, xcp_mgr->supp_xcp_modes) { + size += sysfs_emit_at(buf, size, "%s%s", sep, xcp_desc[mode]); + sep = ", "; + } + + size += sysfs_emit_at(buf, size, "\n"); + + return size; +} + static ssize_t xcp_config_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf) { @@ -573,6 +603,15 @@ static const struct kobj_type xcp_cfg_sysfs_ktype = { .sysfs_ops = &kobj_sysfs_ops, }; +static struct kobj_attribute supp_part_sysfs_mode = + __ATTR_RO(supported_xcp_configs); + +static const struct attribute *xcp_attrs[] = { + &supp_part_sysfs_mode.attr, + &xcp_cfg_sysfs_mode.attr, + NULL, +}; + void amdgpu_xcp_cfg_sysfs_init(struct amdgpu_device *adev) { struct amdgpu_xcp_res_details *xcp_res; @@ -592,7 +631,7 @@ void amdgpu_xcp_cfg_sysfs_init(struct amdgpu_device *adev) if (r) goto err1; - r = sysfs_create_file(&xcp_cfg->kobj, &xcp_cfg_sysfs_mode.attr); + r = sysfs_create_files(&xcp_cfg->kobj, xcp_attrs); if (r) goto err1; @@ -620,7 +659,7 @@ void amdgpu_xcp_cfg_sysfs_init(struct amdgpu_device *adev) kobject_put(&xcp_res->kobj); } - sysfs_remove_file(&xcp_cfg->kobj, &xcp_cfg_sysfs_mode.attr); + sysfs_remove_files(&xcp_cfg->kobj, xcp_attrs); err1: kobject_put(&xcp_cfg->kobj); } @@ -640,6 +679,6 @@ void amdgpu_xcp_cfg_sysfs_fini(struct amdgpu_device *adev) kobject_put(&xcp_res->kobj); } - sysfs_remove_file(&xcp_cfg->kobj, &xcp_cfg_sysfs_mode.attr); + sysfs_remove_files(&xcp_cfg->kobj, xcp_attrs); kobject_put(&xcp_cfg->kobj); } From e323bd3418d366dee0d33060b7c924ed7a93746f Mon Sep 17 00:00:00 2001 From: Shyam Sundar S K Date: Thu, 22 Aug 2024 15:23:57 +0530 Subject: [PATCH 1715/1868] platform/x86/amd/pmc: Extend support for PMC features on new AMD platform MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit PMC driver has capability to get the idle mask values and STB data from the PMFW. Extend this support to the platforms that belong to family 1Ah model 60h series. Co-developed-by: Sanket Goswami Signed-off-by: Sanket Goswami Signed-off-by: Shyam Sundar S K Reviewed-by: Mario Limonciello Link: https://lore.kernel.org/r/20240822095357.395808-2-Shyam-sundar.S-k@amd.com Reviewed-by: Ilpo Järvinen Signed-off-by: Ilpo Järvinen (cherry picked from commit 81af080c90e46a51d626096684e6084195283838) --- drivers/platform/x86/amd/pmc/pmc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/platform/x86/amd/pmc/pmc.c b/drivers/platform/x86/amd/pmc/pmc.c index a3d881f6e5d90..3bfa312839b3c 100644 --- a/drivers/platform/x86/amd/pmc/pmc.c +++ b/drivers/platform/x86/amd/pmc/pmc.c @@ -597,6 +597,7 @@ static int amd_pmc_idlemask_read(struct amd_pmc_dev *pdev, struct device *dev, val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_YC); break; case PCI_DEVICE_ID_AMD_1AH_M20H_ROOT: + case PCI_DEVICE_ID_AMD_1AH_M60H_ROOT: val = amd_pmc_reg_read(pdev, AMD_PMC_SCRATCH_REG_1AH); break; default: @@ -630,6 +631,7 @@ static bool amd_pmc_is_stb_supported(struct amd_pmc_dev *dev) case AMD_CPU_ID_CB: case AMD_CPU_ID_PS: case PCI_DEVICE_ID_AMD_1AH_M20H_ROOT: + case PCI_DEVICE_ID_AMD_1AH_M60H_ROOT: return true; default: return false; From 1e43a756afc8f2bfb5e635a04dc748a2af61fb56 Mon Sep 17 00:00:00 2001 From: YuanShang Date: Mon, 9 Sep 2024 16:29:22 +0800 Subject: [PATCH 1716/1868] drm/amdgpu: Flush tlb by VM_INVALIDATION packet in sdma_v5_2 In order for SDMA not to be switched between VM_INVALIDATION request and ack, use an single VM_INVALIDATION packet in function sdma_v5_2_ring_emit_vm_flush. Signed-off-by: YuanShang Reviewed-By: Horace Chen (cherry picked from commit 970d97bcf98597c37f9bd63eb093c7ec72ee344b) --- .../gpu/drm/amd/amdgpu/navi10_sdma_pkt_open.h | 64 +++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 23 ++++++- 2 files changed, 86 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_sdma_pkt_open.h b/drivers/gpu/drm/amd/amdgpu/navi10_sdma_pkt_open.h index a5b60c9a24189..c88284ff92d85 100644 --- a/drivers/gpu/drm/amd/amdgpu/navi10_sdma_pkt_open.h +++ b/drivers/gpu/drm/amd/amdgpu/navi10_sdma_pkt_open.h @@ -68,6 +68,7 @@ #define SDMA_SUBOP_POLL_REG_WRITE_MEM 1 #define SDMA_SUBOP_POLL_DBIT_WRITE_MEM 2 #define SDMA_SUBOP_POLL_MEM_VERIFY 3 +#define SDMA_SUBOP_VM_INVALIDATION 4 #define HEADER_AGENT_DISPATCH 4 #define HEADER_BARRIER 5 #define SDMA_OP_AQL_COPY 0 @@ -4040,6 +4041,69 @@ #define SDMA_PKT_POLL_MEM_VERIFY_RESERVED_RESERVED(x) (((x) & SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_mask) << SDMA_PKT_POLL_MEM_VERIFY_RESERVED_reserved_shift) +/* +** Definitions for SDMA_PKT_VM_INVALIDATION packet +*/ + +/*define for HEADER word*/ +/*define for op field*/ +#define SDMA_PKT_VM_INVALIDATION_HEADER_op_offset 0 +#define SDMA_PKT_VM_INVALIDATION_HEADER_op_mask 0x000000FF +#define SDMA_PKT_VM_INVALIDATION_HEADER_op_shift 0 +#define SDMA_PKT_VM_INVALIDATION_HEADER_OP(x) (((x) & SDMA_PKT_VM_INVALIDATION_HEADER_op_mask) << SDMA_PKT_VM_INVALIDATION_HEADER_op_shift) + +/*define for sub_op field*/ +#define SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_offset 0 +#define SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_mask 0x000000FF +#define SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_shift 8 +#define SDMA_PKT_VM_INVALIDATION_HEADER_SUB_OP(x) (((x) & SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_mask) << SDMA_PKT_VM_INVALIDATION_HEADER_sub_op_shift) + +/*define for gfx_eng_id field*/ +#define SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_offset 0 +#define SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_mask 0x0000001F +#define SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_shift 16 +#define SDMA_PKT_VM_INVALIDATION_HEADER_GFX_ENG_ID(x) (((x) & SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_mask) << SDMA_PKT_VM_INVALIDATION_HEADER_gfx_eng_id_shift) + +/*define for mm_eng_id field*/ +#define SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_offset 0 +#define SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_mask 0x0000001F +#define SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_shift 24 +#define SDMA_PKT_VM_INVALIDATION_HEADER_MM_ENG_ID(x) (((x) & SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_mask) << SDMA_PKT_VM_INVALIDATION_HEADER_mm_eng_id_shift) + +/*define for INVALIDATEREQ word*/ +/*define for invalidatereq field*/ +#define SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_offset 1 +#define SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_mask 0xFFFFFFFF +#define SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_shift 0 +#define SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_INVALIDATEREQ(x) (((x) & SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_mask) << SDMA_PKT_VM_INVALIDATION_INVALIDATEREQ_invalidatereq_shift) + +/*define for ADDRESSRANGELO word*/ +/*define for addressrangelo field*/ +#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_offset 2 +#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_mask 0xFFFFFFFF +#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_shift 0 +#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_ADDRESSRANGELO(x) (((x) & SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_mask) << SDMA_PKT_VM_INVALIDATION_ADDRESSRANGELO_addressrangelo_shift) + +/*define for ADDRESSRANGEHI word*/ +/*define for invalidateack field*/ +#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_offset 3 +#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_mask 0x0000FFFF +#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_shift 0 +#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_INVALIDATEACK(x) (((x) & SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_mask) << SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_invalidateack_shift) + +/*define for addressrangehi field*/ +#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_offset 3 +#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_mask 0x0000001F +#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_shift 16 +#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_ADDRESSRANGEHI(x) (((x) & SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_mask) << SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_addressrangehi_shift) + +/*define for reserved field*/ +#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_offset 3 +#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_mask 0x000001FF +#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_shift 23 +#define SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_RESERVED(x) (((x) & SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_mask) << SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_reserved_shift) + + /* ** Definitions for SDMA_PKT_ATOMIC packet */ diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c index 65a93de9c904f..64583cbeeb361 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c @@ -1205,7 +1205,28 @@ static void sdma_v5_2_ring_emit_pipeline_sync(struct amdgpu_ring *ring) static void sdma_v5_2_ring_emit_vm_flush(struct amdgpu_ring *ring, unsigned vmid, uint64_t pd_addr) { - amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); + struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->vm_hub]; + uint32_t req = hub->vmhub_funcs->get_invalidate_req(vmid, 0); + + /* Update the PD address for this VMID. */ + amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + + (hub->ctx_addr_distance * vmid), + lower_32_bits(pd_addr)); + amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 + + (hub->ctx_addr_distance * vmid), + upper_32_bits(pd_addr)); + + /* Trigger invalidation. */ + amdgpu_ring_write(ring, + SDMA_PKT_VM_INVALIDATION_HEADER_OP(SDMA_OP_POLL_REGMEM) | + SDMA_PKT_VM_INVALIDATION_HEADER_SUB_OP(SDMA_SUBOP_VM_INVALIDATION) | + SDMA_PKT_VM_INVALIDATION_HEADER_GFX_ENG_ID(ring->vm_inv_eng) | + SDMA_PKT_VM_INVALIDATION_HEADER_MM_ENG_ID(0x1f)); + amdgpu_ring_write(ring, req); + amdgpu_ring_write(ring, 0xFFFFFFFF); + amdgpu_ring_write(ring, + SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_INVALIDATEACK(1 << vmid) | + SDMA_PKT_VM_INVALIDATION_ADDRESSRANGEHI_ADDRESSRANGEHI(0x1F)); } static void sdma_v5_2_ring_emit_wreg(struct amdgpu_ring *ring, From c7c1b1323a40e665347b892d7aa13f5c9d3e3103 Mon Sep 17 00:00:00 2001 From: Philip Yang Date: Thu, 3 Oct 2024 11:53:51 -0400 Subject: [PATCH 1717/1868] drm/amdkfd: Copy wave state only for compute queue get_wave_state is not defined for sdma queue, copy_context_work_handler calls it for sdma queue will crash. Signed-off-by: Philip Yang Reviewed-by: Jonathan Kim Tested-by: Jonathan Kim --- drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index 56b0ba718319b..471144e71c29a 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -3199,7 +3199,7 @@ struct copy_context_work_handler_workarea { struct kfd_process *p; }; -static void copy_context_work_handler (struct work_struct *work) +static void copy_context_work_handler(struct work_struct *work) { struct copy_context_work_handler_workarea *workarea; struct mqd_manager *mqd_mgr; @@ -3226,6 +3226,9 @@ static void copy_context_work_handler (struct work_struct *work) struct qcm_process_device *qpd = &pdd->qpd; list_for_each_entry(q, &qpd->queues_list, list) { + if (q->properties.type != KFD_QUEUE_TYPE_COMPUTE) + continue; + mqd_mgr = dqm->mqd_mgrs[KFD_MQD_TYPE_CP]; /* We ignore the return value from get_wave_state From efafe8e0bc1bf25628d11b2b3b73b7749b80b887 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 8 Oct 2024 16:02:48 -0400 Subject: [PATCH 1718/1868] drm/amdgpu: enable enforce_isolation sysfs node on VFs It should be enabled on both bare metal and VFs. Fixes: e189be9b2e38 ("drm/amdgpu: Add enforce_isolation sysfs attribute") Signed-off-by: Alex Deucher Cc: Srinivasan Shanmugam Cc: Amber Lin Reviewed-by: Srinivasan Shanmugam --- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c index 2fe75c920a73c..ae692d0591bab 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c @@ -1625,11 +1625,9 @@ int amdgpu_gfx_sysfs_isolation_shader_init(struct amdgpu_device *adev) { int r; - if (!amdgpu_sriov_vf(adev)) { - r = device_create_file(adev->dev, &dev_attr_enforce_isolation); - if (r) - return r; - } + r = device_create_file(adev->dev, &dev_attr_enforce_isolation); + if (r) + return r; r = device_create_file(adev->dev, &dev_attr_run_cleaner_shader); if (r) @@ -1640,8 +1638,7 @@ int amdgpu_gfx_sysfs_isolation_shader_init(struct amdgpu_device *adev) void amdgpu_gfx_sysfs_isolation_shader_fini(struct amdgpu_device *adev) { - if (!amdgpu_sriov_vf(adev)) - device_remove_file(adev->dev, &dev_attr_enforce_isolation); + device_remove_file(adev->dev, &dev_attr_enforce_isolation); device_remove_file(adev->dev, &dev_attr_run_cleaner_shader); } From d1a9ddf15ac4bee8f910fd42097bdb0df2176d2c Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Thu, 19 Sep 2024 18:51:07 +0530 Subject: [PATCH 1719/1868] drm/amdgpu: Add gmc interface to request NPS mode Add a common interface in GMC to request NPS mode through PSP. Also add a variable in hive and gmc control to track the last requested mode. Signed-off-by: Rajneesh Bhardwaj Signed-off-by: Lijo Lazar Reviewed-by: Feifei Xu (cherry picked from commit cb9c2a5efb2753327a605ca35e87a2bbf3198bdd) --- drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 16 ++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 6 ++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h | 1 + 4 files changed, 24 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c index 041103073ea7f..23ebda1342207 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c @@ -1256,3 +1256,19 @@ int amdgpu_gmc_get_nps_memranges(struct amdgpu_device *adev, return ret; } + +int amdgpu_gmc_request_memory_partition(struct amdgpu_device *adev, + int nps_mode) +{ + /* Not supported on VF devices and APUs */ + if (amdgpu_sriov_vf(adev) || (adev->flags & AMD_IS_APU)) + return -EOPNOTSUPP; + + if (!adev->psp.funcs) { + dev_err(adev->dev, + "PSP interface not available for nps mode change request"); + return -EINVAL; + } + + return psp_memory_partition(&adev->psp, nps_mode); +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h index 1970d18a21380..910cd227d8c25 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h @@ -161,6 +161,9 @@ struct amdgpu_gmc_funcs { enum amdgpu_memory_partition (*query_mem_partition_mode)( struct amdgpu_device *adev); + /* Request NPS mode */ + int (*request_mem_partition_mode)(struct amdgpu_device *adev, + int nps_mode); }; struct amdgpu_xgmi_ras { @@ -304,6 +307,7 @@ struct amdgpu_gmc { struct amdgpu_mem_partition_info *mem_partitions; uint8_t num_mem_partitions; const struct amdgpu_gmc_funcs *gmc_funcs; + enum amdgpu_memory_partition requested_nps_mode; struct amdgpu_xgmi xgmi; struct amdgpu_irq_src ecc_irq; @@ -454,4 +458,6 @@ int amdgpu_gmc_get_nps_memranges(struct amdgpu_device *adev, struct amdgpu_mem_partition_info *mem_ranges, int exp_ranges); +int amdgpu_gmc_request_memory_partition(struct amdgpu_device *adev, + int nps_mode); #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c index 13a699cd8f8d8..9e9a9ba8c342f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c @@ -673,6 +673,7 @@ struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev) task_barrier_init(&hive->tb); hive->pstate = AMDGPU_XGMI_PSTATE_UNKNOWN; hive->hi_req_gpu = NULL; + atomic_set(&hive->requested_nps_mode, UNKNOWN_MEMORY_PARTITION_MODE); /* * hive pstate on boot is high in vega20 so we have to go to low diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h index d652727ca5655..67abadb4f298e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h @@ -46,6 +46,7 @@ struct amdgpu_hive_info { atomic_t ras_recovery; struct ras_event_manager event_mgr; struct work_struct reset_on_init_work; + atomic_t requested_nps_mode; }; struct amdgpu_pcs_ras_field { From e6a5e7787a3829ca30516c4dd7b3f2ba5a94ceaa Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 8 Oct 2024 16:02:48 -0400 Subject: [PATCH 1720/1868] drm/amdgpu: enable enforce_isolation sysfs node on VFs It should be enabled on both bare metal and VFs. Fixes: e189be9b2e38 ("drm/amdgpu: Add enforce_isolation sysfs attribute") Signed-off-by: Alex Deucher Cc: Srinivasan Shanmugam Cc: Amber Lin Reviewed-by: Srinivasan Shanmugam --- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c index 83e54697f0ee8..f1ffab5a1eaed 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c @@ -1635,11 +1635,9 @@ int amdgpu_gfx_sysfs_isolation_shader_init(struct amdgpu_device *adev) { int r; - if (!amdgpu_sriov_vf(adev)) { - r = device_create_file(adev->dev, &dev_attr_enforce_isolation); - if (r) - return r; - } + r = device_create_file(adev->dev, &dev_attr_enforce_isolation); + if (r) + return r; r = device_create_file(adev->dev, &dev_attr_run_cleaner_shader); if (r) @@ -1650,8 +1648,7 @@ int amdgpu_gfx_sysfs_isolation_shader_init(struct amdgpu_device *adev) void amdgpu_gfx_sysfs_isolation_shader_fini(struct amdgpu_device *adev) { - if (!amdgpu_sriov_vf(adev)) - device_remove_file(adev->dev, &dev_attr_enforce_isolation); + device_remove_file(adev->dev, &dev_attr_enforce_isolation); device_remove_file(adev->dev, &dev_attr_run_cleaner_shader); } From d2cc2dbfb3a2880c298c576eef21657324874bc1 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Thu, 19 Sep 2024 19:36:19 +0530 Subject: [PATCH 1721/1868] drm/amdgpu: Add sysfs interfaces for NPS mode Add a sysfs interface to see available NPS modes to switch to - cat /sys/bus/pci/devices/../available_memory_paritition Make the current_memory_partition sysfs node read/write for requesting a new NPS mode. The request is only cached and at a later point a driver unload/reload is required to switch to the new NPS mode. Ex: echo NPS1 > /sys/bus/pci/devices/../current_memory_paritition echo NPS4 > /sys/bus/pci/devices/../current_memory_paritition The above interfaces will be available only if the SOC supports more than one NPS mode. Also modify the current memory partition sysfs logic to be more generic. Signed-off-by: Lijo Lazar Reviewed-by: Rajneesh Bhardwaj (cherry picked from commit 3cfa5ffa6717fbc06a6352bcf9ac9002e8bf1cda) --- drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 114 ++++++++++++++++++++---- drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 6 ++ 2 files changed, 104 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c index 23ebda1342207..e61aa073ecc28 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c @@ -1139,6 +1139,79 @@ int amdgpu_gmc_vram_checking(struct amdgpu_device *adev) return ret; } +static const char *nps_desc[] = { + [AMDGPU_NPS1_PARTITION_MODE] = "NPS1", + [AMDGPU_NPS2_PARTITION_MODE] = "NPS2", + [AMDGPU_NPS3_PARTITION_MODE] = "NPS3", + [AMDGPU_NPS4_PARTITION_MODE] = "NPS4", + [AMDGPU_NPS6_PARTITION_MODE] = "NPS6", + [AMDGPU_NPS8_PARTITION_MODE] = "NPS8", +}; + +static ssize_t available_memory_partition_show(struct device *dev, + struct device_attribute *addr, + char *buf) +{ + struct drm_device *ddev = dev_get_drvdata(dev); + struct amdgpu_device *adev = drm_to_adev(ddev); + int size = 0, mode; + char *sep = ""; + + for_each_inst(mode, adev->gmc.supported_nps_modes) { + size += sysfs_emit_at(buf, size, "%s%s", sep, nps_desc[mode]); + sep = ", "; + } + size += sysfs_emit_at(buf, size, "\n"); + + return size; +} + +static ssize_t current_memory_partition_store(struct device *dev, + struct device_attribute *attr, + const char *buf, size_t count) +{ + struct drm_device *ddev = dev_get_drvdata(dev); + struct amdgpu_device *adev = drm_to_adev(ddev); + enum amdgpu_memory_partition mode; + struct amdgpu_hive_info *hive; + int i; + + mode = UNKNOWN_MEMORY_PARTITION_MODE; + for_each_inst(i, adev->gmc.supported_nps_modes) { + if (!strncasecmp(nps_desc[i], buf, strlen(nps_desc[i]))) { + mode = i; + break; + } + } + + if (mode == UNKNOWN_MEMORY_PARTITION_MODE) + return -EINVAL; + + if (mode == adev->gmc.gmc_funcs->query_mem_partition_mode(adev)) { + dev_info( + adev->dev, + "requested NPS mode is same as current NPS mode, skipping\n"); + return count; + } + + /* If device is part of hive, all devices in the hive should request the + * same mode. Hence store the requested mode in hive. + */ + hive = amdgpu_get_xgmi_hive(adev); + if (hive) { + atomic_set(&hive->requested_nps_mode, mode); + amdgpu_put_xgmi_hive(hive); + } else { + adev->gmc.requested_nps_mode = mode; + } + + dev_info( + adev->dev, + "NPS mode change requested, please remove and reload the driver\n"); + + return count; +} + static ssize_t current_memory_partition_show( struct device *dev, struct device_attribute *addr, char *buf) { @@ -1147,38 +1220,47 @@ static ssize_t current_memory_partition_show( enum amdgpu_memory_partition mode; mode = adev->gmc.gmc_funcs->query_mem_partition_mode(adev); - switch (mode) { - case AMDGPU_NPS1_PARTITION_MODE: - return sysfs_emit(buf, "NPS1\n"); - case AMDGPU_NPS2_PARTITION_MODE: - return sysfs_emit(buf, "NPS2\n"); - case AMDGPU_NPS3_PARTITION_MODE: - return sysfs_emit(buf, "NPS3\n"); - case AMDGPU_NPS4_PARTITION_MODE: - return sysfs_emit(buf, "NPS4\n"); - case AMDGPU_NPS6_PARTITION_MODE: - return sysfs_emit(buf, "NPS6\n"); - case AMDGPU_NPS8_PARTITION_MODE: - return sysfs_emit(buf, "NPS8\n"); - default: + if ((mode > ARRAY_SIZE(nps_desc)) || + (BIT(mode) & AMDGPU_ALL_NPS_MASK) != BIT(mode)) return sysfs_emit(buf, "UNKNOWN\n"); - } + + return sysfs_emit(buf, "%s\n", nps_desc[mode]); } -static DEVICE_ATTR_RO(current_memory_partition); +static DEVICE_ATTR_RW(current_memory_partition); +static DEVICE_ATTR_RO(available_memory_partition); int amdgpu_gmc_sysfs_init(struct amdgpu_device *adev) { + bool nps_switch_support; + int r = 0; + if (!adev->gmc.gmc_funcs->query_mem_partition_mode) return 0; + nps_switch_support = (hweight32(adev->gmc.supported_nps_modes & + AMDGPU_ALL_NPS_MASK) > 1); + if (!nps_switch_support) + dev_attr_current_memory_partition.attr.mode &= + ~(S_IWUSR | S_IWGRP | S_IWOTH); + else + r = device_create_file(adev->dev, + &dev_attr_available_memory_partition); + + if (r) + return r; + return device_create_file(adev->dev, &dev_attr_current_memory_partition); } void amdgpu_gmc_sysfs_fini(struct amdgpu_device *adev) { + if (!adev->gmc.gmc_funcs->query_mem_partition_mode) + return; + device_remove_file(adev->dev, &dev_attr_current_memory_partition); + device_remove_file(adev->dev, &dev_attr_available_memory_partition); } int amdgpu_gmc_get_nps_memranges(struct amdgpu_device *adev, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h index 910cd227d8c25..05c70732a3204 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h @@ -73,6 +73,11 @@ enum amdgpu_memory_partition { AMDGPU_NPS8_PARTITION_MODE = 8, }; +#define AMDGPU_ALL_NPS_MASK \ + (BIT(AMDGPU_NPS1_PARTITION_MODE) | BIT(AMDGPU_NPS2_PARTITION_MODE) | \ + BIT(AMDGPU_NPS3_PARTITION_MODE) | BIT(AMDGPU_NPS4_PARTITION_MODE) | \ + BIT(AMDGPU_NPS6_PARTITION_MODE) | BIT(AMDGPU_NPS8_PARTITION_MODE)) + /* * GMC page fault information */ @@ -308,6 +313,7 @@ struct amdgpu_gmc { uint8_t num_mem_partitions; const struct amdgpu_gmc_funcs *gmc_funcs; enum amdgpu_memory_partition requested_nps_mode; + uint32_t supported_nps_modes; struct amdgpu_xgmi xgmi; struct amdgpu_irq_src ecc_irq; From b80672c8546f76bb5ae4ddf1af295540304cf94e Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Fri, 20 Sep 2024 13:14:40 +0530 Subject: [PATCH 1722/1868] drm/amdgpu: Place NPS mode request on unload If a user has requested NPS mode switch, place the request through PSP during unload of the driver. For devices which are part of a hive, all requests are placed together. If one of them fails, revert back to the current NPS mode. Signed-off-by: Lijo Lazar Signed-off-by: Rajneesh Bhardwaj Reviewed-by: Feifei Xu (cherry picked from commit 44d5206ec07c65976f25e13c1de175b0ab5d224d) --- drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 47 ++++++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 38 +++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h | 4 ++ 5 files changed, 92 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 8110dbf8878a5..41e9bf206f7eb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2471,6 +2471,7 @@ amdgpu_pci_remove(struct pci_dev *pdev) struct amdgpu_device *adev = drm_to_adev(dev); amdgpu_xcp_dev_unplug(adev); + amdgpu_gmc_prepare_nps_mode_change(adev); drm_dev_unplug(dev); if (adev->pm.rpm_mode != AMDGPU_RUNPM_NONE) { pm_runtime_get_sync(dev->dev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c index e61aa073ecc28..34e5ccd22b988 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c @@ -1354,3 +1354,50 @@ int amdgpu_gmc_request_memory_partition(struct amdgpu_device *adev, return psp_memory_partition(&adev->psp, nps_mode); } + +static inline bool amdgpu_gmc_need_nps_switch_req(struct amdgpu_device *adev, + int req_nps_mode, + int cur_nps_mode) +{ + return (((BIT(req_nps_mode) & adev->gmc.supported_nps_modes) == + BIT(req_nps_mode)) && + req_nps_mode != cur_nps_mode); +} + +void amdgpu_gmc_prepare_nps_mode_change(struct amdgpu_device *adev) +{ + int req_nps_mode, cur_nps_mode, r; + struct amdgpu_hive_info *hive; + + if (amdgpu_sriov_vf(adev) || !adev->gmc.supported_nps_modes || + !adev->gmc.gmc_funcs->request_mem_partition_mode) + return; + + cur_nps_mode = adev->gmc.gmc_funcs->query_mem_partition_mode(adev); + hive = amdgpu_get_xgmi_hive(adev); + if (hive) { + req_nps_mode = atomic_read(&hive->requested_nps_mode); + if (!amdgpu_gmc_need_nps_switch_req(adev, req_nps_mode, + cur_nps_mode)) { + amdgpu_put_xgmi_hive(hive); + return; + } + r = amdgpu_xgmi_request_nps_change(adev, hive, req_nps_mode); + amdgpu_put_xgmi_hive(hive); + goto out; + } + + req_nps_mode = adev->gmc.requested_nps_mode; + if (!amdgpu_gmc_need_nps_switch_req(adev, req_nps_mode, cur_nps_mode)) + return; + + /* even if this fails, we should let driver unload w/o blocking */ + r = adev->gmc.gmc_funcs->request_mem_partition_mode(adev, req_nps_mode); +out: + if (r) + dev_err(adev->dev, "NPS mode change request failed\n"); + else + dev_info( + adev->dev, + "NPS mode change request done, reload driver to complete the change\n"); +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h index 05c70732a3204..b92f41d1b46f1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h @@ -466,4 +466,6 @@ int amdgpu_gmc_get_nps_memranges(struct amdgpu_device *adev, int amdgpu_gmc_request_memory_partition(struct amdgpu_device *adev, int nps_mode); +void amdgpu_gmc_prepare_nps_mode_change(struct amdgpu_device *adev); + #endif diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c index 9e9a9ba8c342f..6532b7530a5cc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c @@ -1570,3 +1570,41 @@ int amdgpu_xgmi_reset_on_init(struct amdgpu_device *adev) return 0; } + +int amdgpu_xgmi_request_nps_change(struct amdgpu_device *adev, + struct amdgpu_hive_info *hive, + int req_nps_mode) +{ + struct amdgpu_device *tmp_adev; + int cur_nps_mode, r; + + /* This is expected to be called only during unload of driver. The + * request needs to be placed only once for all devices in the hive. If + * one of them fail, revert the request for previous successful devices. + * After placing the request, make hive mode as UNKNOWN so that other + * devices don't request anymore. + */ + mutex_lock(&hive->hive_lock); + list_for_each_entry(tmp_adev, &hive->device_list, gmc.xgmi.head) { + r = adev->gmc.gmc_funcs->request_mem_partition_mode( + tmp_adev, req_nps_mode); + if (r) + goto err; + } + /* Set to UNKNOWN so that other devices don't request anymore */ + atomic_set(&hive->requested_nps_mode, UNKNOWN_MEMORY_PARTITION_MODE); + + mutex_unlock(&hive->hive_lock); + + return 0; +err: + /* Request back current mode if one of the requests failed */ + cur_nps_mode = adev->gmc.gmc_funcs->query_mem_partition_mode(tmp_adev); + list_for_each_entry_continue_reverse(tmp_adev, &hive->device_list, + gmc.xgmi.head) + adev->gmc.gmc_funcs->request_mem_partition_mode(tmp_adev, + cur_nps_mode); + mutex_lock(&hive->hive_lock); + + return r; +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h index 67abadb4f298e..41d5f97fc77ac 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h @@ -79,4 +79,8 @@ static inline bool amdgpu_xgmi_same_hive(struct amdgpu_device *adev, int amdgpu_xgmi_ras_sw_init(struct amdgpu_device *adev); int amdgpu_xgmi_reset_on_init(struct amdgpu_device *adev); +int amdgpu_xgmi_request_nps_change(struct amdgpu_device *adev, + struct amdgpu_hive_info *hive, + int req_nps_mode); + #endif From f5dc150a00fd5e8c7b80b1955c0cd98aff87cd61 Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Mon, 30 Sep 2024 16:29:15 +0530 Subject: [PATCH 1723/1868] drm/amdgpu: update the handle ptr in wait_for_idle MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Update the *handle to amdgpu_ip_block ptr for all functions pointers of wait_for_idle. Signed-off-by: Sunil Khatri Reviewed-by: Christian König Change-Id: I1dfdd90ecd6f2bc9114ae661299e53af9509c092 (cherry picked from commit d8b02111508526a03cd1f9280763bfd94dc1f75e) --- drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 2 +- drivers/gpu/drm/amd/amdgpu/cik.c | 2 +- drivers/gpu/drm/amd/amdgpu/cik_ih.c | 4 +-- drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 4 +-- drivers/gpu/drm/amd/amdgpu/cz_ih.c | 4 +-- drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 4 +-- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 4 +-- drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 4 +-- drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 6 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 4 +-- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 14 +++++--- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 6 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 6 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 32 +++++++++++++------ drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 6 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 24 ++++++++++---- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/iceland_ih.c | 4 +-- drivers/gpu/drm/amd/amdgpu/ih_v6_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/ih_v6_1.c | 2 +- drivers/gpu/drm/amd/amdgpu/ih_v7_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c | 4 +-- drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c | 4 +-- drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c | 4 +-- drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c | 4 +-- drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 4 +-- drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c | 4 +-- drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c | 4 +-- drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 2 +- drivers/gpu/drm/amd/amdgpu/nv.c | 2 +- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 4 +-- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 4 +-- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 4 +-- drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 4 +-- drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 4 +-- drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 4 +-- drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 4 +-- drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c | 4 +-- drivers/gpu/drm/amd/amdgpu/si.c | 2 +- drivers/gpu/drm/amd/amdgpu/si_dma.c | 7 ++-- drivers/gpu/drm/amd/amdgpu/si_ih.c | 6 ++-- drivers/gpu/drm/amd/amdgpu/soc15.c | 2 +- drivers/gpu/drm/amd/amdgpu/soc21.c | 2 +- drivers/gpu/drm/amd/amdgpu/soc24.c | 2 +- drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 4 +-- drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c | 4 +-- drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 4 +-- drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 11 +++++-- drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 13 +++++--- drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 11 +++++-- drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 14 +++++--- drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 15 ++++++--- drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 11 +++++-- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 4 +-- drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 4 +-- drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 4 +-- drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 4 +-- drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 4 +-- drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 4 +-- drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 4 +-- drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 4 +-- drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 2 +- drivers/gpu/drm/amd/amdgpu/vega20_ih.c | 2 +- drivers/gpu/drm/amd/amdgpu/vi.c | 2 +- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- drivers/gpu/drm/amd/include/amd_shared.h | 10 +++--- drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c | 2 +- drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 2 +- .../gpu/drm/amd/pm/powerplay/amd_powerplay.c | 2 +- 79 files changed, 224 insertions(+), 162 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c index d3c6669f66fba..e0f9c73921d51 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c @@ -598,7 +598,7 @@ static bool acp_is_idle(void *handle) return true; } -static int acp_wait_for_idle(void *handle) +static int acp_wait_for_idle(struct amdgpu_ip_block *ip_block) { return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 8ed1d9b03bab4..6303686898a78 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -2225,7 +2225,7 @@ int amdgpu_device_ip_wait_for_idle(struct amdgpu_device *adev, if (!adev->ip_blocks[i].status.valid) continue; if (adev->ip_blocks[i].version->type == block_type) { - r = adev->ip_blocks[i].version->funcs->wait_for_idle((void *)adev); + r = adev->ip_blocks[i].version->funcs->wait_for_idle(&adev->ip_blocks[i]); if (r) return r; break; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c index 7c1f17dc6b4b6..50e56f1093e41 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c @@ -155,7 +155,7 @@ static bool isp_is_idle(void *handle) return true; } -static int isp_wait_for_idle(void *handle) +static int isp_wait_for_idle(struct amdgpu_ip_block *ip_block) { return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c index b2b0cfadc6d22..b64e31ae12483 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c @@ -778,7 +778,7 @@ static bool amdgpu_vkms_is_idle(void *handle) return true; } -static int amdgpu_vkms_wait_for_idle(void *handle) +static int amdgpu_vkms_wait_for_idle(struct amdgpu_ip_block *ip_block) { return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c index 0a0114de11b49..7c3a0bd4c4a39 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik.c +++ b/drivers/gpu/drm/amd/amdgpu/cik.c @@ -2172,7 +2172,7 @@ static bool cik_common_is_idle(void *handle) return true; } -static int cik_common_wait_for_idle(void *handle) +static int cik_common_wait_for_idle(struct amdgpu_ip_block *ip_block) { return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c index 5ccd7e2ebf675..f39f01525f8d9 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c @@ -362,11 +362,11 @@ static bool cik_ih_is_idle(void *handle) return true; } -static int cik_ih_wait_for_idle(void *handle) +static int cik_ih_wait_for_idle(struct amdgpu_ip_block *ip_block) { unsigned i; u32 tmp; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; for (i = 0; i < adev->usec_timeout; i++) { /* read MC_STATUS */ diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c index 3565dbcf7e38d..b0628cba5864e 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c @@ -1039,11 +1039,11 @@ static bool cik_sdma_is_idle(void *handle) return true; } -static int cik_sdma_wait_for_idle(void *handle) +static int cik_sdma_wait_for_idle(struct amdgpu_ip_block *ip_block) { unsigned i; u32 tmp; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; for (i = 0; i < adev->usec_timeout; i++) { tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK | diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c index bbc50a8e3bc48..367dd9aa72fcb 100644 --- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c @@ -358,11 +358,11 @@ static bool cz_ih_is_idle(void *handle) return true; } -static int cz_ih_wait_for_idle(void *handle) +static int cz_ih_wait_for_idle(struct amdgpu_ip_block *ip_block) { unsigned i; u32 tmp; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; for (i = 0; i < adev->usec_timeout; i++) { /* read MC_STATUS */ diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index 8e18fece431f1..eb5d08f493e43 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -2960,7 +2960,7 @@ static bool dce_v10_0_is_idle(void *handle) return true; } -static int dce_v10_0_wait_for_idle(void *handle) +static int dce_v10_0_wait_for_idle(struct amdgpu_ip_block *ip_block) { return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index 870bf80bff5ac..e8298dd0b1dc1 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -3098,7 +3098,7 @@ static bool dce_v11_0_is_idle(void *handle) return true; } -static int dce_v11_0_wait_for_idle(void *handle) +static int dce_v11_0_wait_for_idle(struct amdgpu_ip_block *ip_block) { return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c index a51fa254d770e..5b48f6ea4da76 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c @@ -2855,7 +2855,7 @@ static bool dce_v6_0_is_idle(void *handle) return true; } -static int dce_v6_0_wait_for_idle(void *handle) +static int dce_v6_0_wait_for_idle(struct amdgpu_ip_block *ip_block) { return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index cc916d2948ac1..5e6f671955a5d 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -2877,7 +2877,7 @@ static bool dce_v8_0_is_idle(void *handle) return true; } -static int dce_v8_0_wait_for_idle(void *handle) +static int dce_v8_0_wait_for_idle(struct amdgpu_ip_block *ip_block) { return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 244005d356236..2969bf1c45f22 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -7485,11 +7485,11 @@ static bool gfx_v10_0_is_idle(void *handle) return true; } -static int gfx_v10_0_wait_for_idle(void *handle) +static int gfx_v10_0_wait_for_idle(struct amdgpu_ip_block *ip_block) { unsigned int i; u32 tmp; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; for (i = 0; i < adev->usec_timeout; i++) { /* read MC_STATUS */ diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index 690cd7b173f72..052ecf7ab71f5 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -4726,11 +4726,11 @@ static bool gfx_v11_0_is_idle(void *handle) return true; } -static int gfx_v11_0_wait_for_idle(void *handle) +static int gfx_v11_0_wait_for_idle(struct amdgpu_ip_block *ip_block) { unsigned i; u32 tmp; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; for (i = 0; i < adev->usec_timeout; i++) { /* read MC_STATUS */ diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c index 6423b20e9156c..04efb51375528 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c @@ -3664,11 +3664,11 @@ static bool gfx_v12_0_is_idle(void *handle) return true; } -static int gfx_v12_0_wait_for_idle(void *handle) +static int gfx_v12_0_wait_for_idle(struct amdgpu_ip_block *ip_block) { unsigned i; u32 tmp; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; for (i = 0; i < adev->usec_timeout; i++) { /* read MC_STATUS */ diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c index cc9f9b10b435b..0ddb98b0fa5f4 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c @@ -3177,13 +3177,13 @@ static bool gfx_v6_0_is_idle(void *handle) return true; } -static int gfx_v6_0_wait_for_idle(void *handle) +static int gfx_v6_0_wait_for_idle(struct amdgpu_ip_block *ip_block) { unsigned i; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; for (i = 0; i < adev->usec_timeout; i++) { - if (gfx_v6_0_is_idle(handle)) + if (gfx_v6_0_is_idle(adev)) return 0; udelay(1); } diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index 3babf5b5a9dd2..592a6dbc1bcde 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -4523,11 +4523,11 @@ static bool gfx_v7_0_is_idle(void *handle) return true; } -static int gfx_v7_0_wait_for_idle(void *handle) +static int gfx_v7_0_wait_for_idle(struct amdgpu_ip_block *ip_block) { unsigned i; u32 tmp; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; for (i = 0; i < adev->usec_timeout; i++) { /* read MC_STATUS */ diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 78c766857abb0..910510cdf841d 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -4871,13 +4871,13 @@ static int gfx_v8_0_wait_for_rlc_idle(void *handle) return -ETIMEDOUT; } -static int gfx_v8_0_wait_for_idle(void *handle) +static int gfx_v8_0_wait_for_idle(struct amdgpu_ip_block *ip_block) { unsigned int i; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; for (i = 0; i < adev->usec_timeout; i++) { - if (gfx_v8_0_is_idle(handle)) + if (gfx_v8_0_is_idle(adev)) return 0; udelay(1); @@ -4888,6 +4888,7 @@ static int gfx_v8_0_wait_for_idle(void *handle) static int gfx_v8_0_hw_fini(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_ip_block *ip_block; amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); @@ -4904,8 +4905,13 @@ static int gfx_v8_0_hw_fini(void *handle) pr_debug("For SRIOV client, shouldn't do anything.\n"); return 0; } + + ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX); + if (!ip_block) + return -EINVAL; + amdgpu_gfx_rlc_enter_safe_mode(adev, 0); - if (!gfx_v8_0_wait_for_idle(adev)) + if (!gfx_v8_0_wait_for_idle(ip_block)) gfx_v8_0_cp_enable(adev, false); else pr_err("cp is busy, skip halt cp\n"); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 9ee87f1949009..25959612d221d 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -4101,13 +4101,13 @@ static bool gfx_v9_0_is_idle(void *handle) return true; } -static int gfx_v9_0_wait_for_idle(void *handle) +static int gfx_v9_0_wait_for_idle(struct amdgpu_ip_block *ip_block) { unsigned i; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; for (i = 0; i < adev->usec_timeout; i++) { - if (gfx_v9_0_is_idle(handle)) + if (gfx_v9_0_is_idle(adev)) return 0; udelay(1); } diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index 0dee2102d7598..75d05b94710cb 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -2410,13 +2410,13 @@ static bool gfx_v9_4_3_is_idle(void *handle) return true; } -static int gfx_v9_4_3_wait_for_idle(void *handle) +static int gfx_v9_4_3_wait_for_idle(struct amdgpu_ip_block *ip_block) { unsigned i; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; for (i = 0; i < adev->usec_timeout; i++) { - if (gfx_v9_4_3_is_idle(handle)) + if (gfx_v9_4_3_is_idle(adev)) return 0; udelay(1); } diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c index bee6af1f5289a..0f732f853c55b 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c @@ -1080,7 +1080,7 @@ static bool gmc_v10_0_is_idle(void *handle) return true; } -static int gmc_v10_0_wait_for_idle(void *handle) +static int gmc_v10_0_wait_for_idle(struct amdgpu_ip_block *ip_block) { /* There is no need to wait for MC idle in GMC v10.*/ return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c index 604258f5927b0..39095b28841e5 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c @@ -988,7 +988,7 @@ static bool gmc_v11_0_is_idle(void *handle) return true; } -static int gmc_v11_0_wait_for_idle(void *handle) +static int gmc_v11_0_wait_for_idle(struct amdgpu_ip_block *ip_block) { /* There is no need to wait for MC idle in GMC v11.*/ return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c index 7cd3f180c1591..46408e5835127 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c @@ -957,7 +957,7 @@ static bool gmc_v12_0_is_idle(void *handle) return true; } -static int gmc_v12_0_wait_for_idle(void *handle) +static int gmc_v12_0_wait_for_idle(struct amdgpu_ip_block *ip_block) { /* There is no need to wait for MC idle in GMC v11.*/ return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c index 8afcb19998f91..2759233052b4f 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c @@ -43,7 +43,7 @@ static void gmc_v6_0_set_gmc_funcs(struct amdgpu_device *adev); static void gmc_v6_0_set_irq_funcs(struct amdgpu_device *adev); -static int gmc_v6_0_wait_for_idle(void *handle); +static int gmc_v6_0_wait_for_idle(struct amdgpu_ip_block *ip_block); MODULE_FIRMWARE("amdgpu/tahiti_mc.bin"); MODULE_FIRMWARE("amdgpu/pitcairn_mc.bin"); @@ -64,8 +64,13 @@ MODULE_FIRMWARE("amdgpu/si58_mc.bin"); static void gmc_v6_0_mc_stop(struct amdgpu_device *adev) { u32 blackout; + struct amdgpu_ip_block *ip_block; - gmc_v6_0_wait_for_idle((void *)adev); + ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GMC); + if (!ip_block) + return; + + gmc_v6_0_wait_for_idle(ip_block); blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) { @@ -212,6 +217,8 @@ static void gmc_v6_0_vram_gtt_location(struct amdgpu_device *adev, static void gmc_v6_0_mc_program(struct amdgpu_device *adev) { int i, j; + struct amdgpu_ip_block *ip_block; + /* Initialize HDP */ for (i = 0, j = 0; i < 32; i++, j += 0x6) { @@ -223,7 +230,11 @@ static void gmc_v6_0_mc_program(struct amdgpu_device *adev) } WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0); - if (gmc_v6_0_wait_for_idle((void *)adev)) + ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GMC); + if (!ip_block) + return; + + if (gmc_v6_0_wait_for_idle(ip_block)) dev_warn(adev->dev, "Wait for MC idle timedout !\n"); if (adev->mode_info.num_crtc) { @@ -250,7 +261,7 @@ static void gmc_v6_0_mc_program(struct amdgpu_device *adev) WREG32(mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 22); WREG32(mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 22); - if (gmc_v6_0_wait_for_idle((void *)adev)) + if (gmc_v6_0_wait_for_idle(ip_block)) dev_warn(adev->dev, "Wait for MC idle timedout !\n"); } @@ -949,6 +960,7 @@ static int gmc_v6_0_resume(void *handle) static bool gmc_v6_0_is_idle(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; + u32 tmp = RREG32(mmSRBM_STATUS); if (tmp & (SRBM_STATUS__MCB_BUSY_MASK | SRBM_STATUS__MCB_NON_DISPLAY_BUSY_MASK | @@ -958,13 +970,13 @@ static bool gmc_v6_0_is_idle(void *handle) return true; } -static int gmc_v6_0_wait_for_idle(void *handle) +static int gmc_v6_0_wait_for_idle(struct amdgpu_ip_block *ip_block) { unsigned int i; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; for (i = 0; i < adev->usec_timeout; i++) { - if (gmc_v6_0_is_idle(handle)) + if (gmc_v6_0_is_idle(adev)) return 0; udelay(1); } @@ -974,7 +986,8 @@ static int gmc_v6_0_wait_for_idle(void *handle) static int gmc_v6_0_soft_reset(void *handle) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; + u32 srbm_soft_reset = 0; u32 tmp = RREG32(mmSRBM_STATUS); @@ -991,7 +1004,8 @@ static int gmc_v6_0_soft_reset(void *handle) if (srbm_soft_reset) { gmc_v6_0_mc_stop(adev); - if (gmc_v6_0_wait_for_idle(adev)) + + if (gmc_v6_0_wait_for_idle(ip_block)) dev_warn(adev->dev, "Wait for GMC idle timed out !\n"); tmp = RREG32(mmSRBM_SOFT_RESET); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c index ece84808dee65..20eb42dc0c879 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c @@ -52,7 +52,7 @@ static void gmc_v7_0_set_gmc_funcs(struct amdgpu_device *adev); static void gmc_v7_0_set_irq_funcs(struct amdgpu_device *adev); -static int gmc_v7_0_wait_for_idle(void *handle); +static int gmc_v7_0_wait_for_idle(struct amdgpu_ip_block *ip_block); MODULE_FIRMWARE("amdgpu/bonaire_mc.bin"); MODULE_FIRMWARE("amdgpu/hawaii_mc.bin"); @@ -1145,11 +1145,11 @@ static bool gmc_v7_0_is_idle(void *handle) return true; } -static int gmc_v7_0_wait_for_idle(void *handle) +static int gmc_v7_0_wait_for_idle(struct amdgpu_ip_block *ip_block) { unsigned int i; u32 tmp; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; for (i = 0; i < adev->usec_timeout; i++) { /* read MC_STATUS */ diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index 94ee112c81382..f5fb32a9083d5 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -53,7 +53,7 @@ static void gmc_v8_0_set_gmc_funcs(struct amdgpu_device *adev); static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev); -static int gmc_v8_0_wait_for_idle(void *handle); +static int gmc_v8_0_wait_for_idle(struct amdgpu_ip_block *ip_block); MODULE_FIRMWARE("amdgpu/tonga_mc.bin"); MODULE_FIRMWARE("amdgpu/polaris11_mc.bin"); @@ -170,8 +170,13 @@ static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev) static void gmc_v8_0_mc_stop(struct amdgpu_device *adev) { u32 blackout; + struct amdgpu_ip_block *ip_block; - gmc_v8_0_wait_for_idle(adev); + ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GMC); + if (!ip_block) + return; + + gmc_v8_0_wait_for_idle(ip_block); blackout = RREG32(mmMC_SHARED_BLACKOUT_CNTL); if (REG_GET_FIELD(blackout, MC_SHARED_BLACKOUT_CNTL, BLACKOUT_MODE) != 1) { @@ -425,6 +430,7 @@ static void gmc_v8_0_vram_gtt_location(struct amdgpu_device *adev, */ static void gmc_v8_0_mc_program(struct amdgpu_device *adev) { + struct amdgpu_ip_block *ip_block; u32 tmp; int i, j; @@ -438,7 +444,11 @@ static void gmc_v8_0_mc_program(struct amdgpu_device *adev) } WREG32(mmHDP_REG_COHERENCY_FLUSH_CNTL, 0); - if (gmc_v8_0_wait_for_idle((void *)adev)) + ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GMC); + if (!ip_block) + return; + + if (gmc_v8_0_wait_for_idle(ip_block)) dev_warn(adev->dev, "Wait for MC idle timedout !\n"); if (adev->mode_info.num_crtc) { @@ -473,7 +483,7 @@ static void gmc_v8_0_mc_program(struct amdgpu_device *adev) WREG32(mmMC_VM_AGP_BASE, 0); WREG32(mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 22); WREG32(mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 22); - if (gmc_v8_0_wait_for_idle((void *)adev)) + if (gmc_v8_0_wait_for_idle(ip_block)) dev_warn(adev->dev, "Wait for MC idle timedout !\n"); WREG32(mmBIF_FB_EN, BIF_FB_EN__FB_READ_EN_MASK | BIF_FB_EN__FB_WRITE_EN_MASK); @@ -1271,11 +1281,11 @@ static bool gmc_v8_0_is_idle(void *handle) return true; } -static int gmc_v8_0_wait_for_idle(void *handle) +static int gmc_v8_0_wait_for_idle(struct amdgpu_ip_block *ip_block) { unsigned int i; u32 tmp; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; for (i = 0; i < adev->usec_timeout; i++) { /* read MC_STATUS */ @@ -1328,7 +1338,7 @@ static int gmc_v8_0_pre_soft_reset(void *handle) return 0; gmc_v8_0_mc_stop(adev); - if (gmc_v8_0_wait_for_idle(adev)) + if (gmc_v8_0_wait_for_idle(ip_block)) dev_warn(adev->dev, "Wait for GMC idle timed out !\n"); return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index 84537abe1f5a4..16c7831922054 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -2461,7 +2461,7 @@ static bool gmc_v9_0_is_idle(void *handle) return true; } -static int gmc_v9_0_wait_for_idle(void *handle) +static int gmc_v9_0_wait_for_idle(struct amdgpu_ip_block *ip_block) { /* There is no need to wait for MC idle in GMC v9.*/ return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c index 87b29600cf1fb..ac2cc7db8ba0b 100644 --- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c @@ -352,11 +352,11 @@ static bool iceland_ih_is_idle(void *handle) return true; } -static int iceland_ih_wait_for_idle(void *handle) +static int iceland_ih_wait_for_idle(struct amdgpu_ip_block *ip_block) { unsigned i; u32 tmp; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; for (i = 0; i < adev->usec_timeout; i++) { /* read MC_STATUS */ diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c index fa6c7e5fbbe3b..cbaea52e0255f 100644 --- a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c @@ -664,7 +664,7 @@ static bool ih_v6_0_is_idle(void *handle) return true; } -static int ih_v6_0_wait_for_idle(void *handle) +static int ih_v6_0_wait_for_idle(struct amdgpu_ip_block *ip_block) { /* todo */ return -ETIMEDOUT; diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c index ebe23630e8f67..f0759a8eed29b 100644 --- a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c +++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c @@ -643,7 +643,7 @@ static bool ih_v6_1_is_idle(void *handle) return true; } -static int ih_v6_1_wait_for_idle(void *handle) +static int ih_v6_1_wait_for_idle(struct amdgpu_ip_block *ip_block) { /* todo */ return -ETIMEDOUT; diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c index 1619f0ba4d1b9..4757972aeeb49 100644 --- a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c @@ -633,7 +633,7 @@ static bool ih_v7_0_is_idle(void *handle) return true; } -static int ih_v7_0_wait_for_idle(void *handle) +static int ih_v7_0_wait_for_idle(struct amdgpu_ip_block *ip_block) { /* todo */ return -ETIMEDOUT; diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c index 341c551dad8b0..01dd442a3311e 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c @@ -666,9 +666,9 @@ static bool jpeg_v2_0_is_idle(void *handle) UVD_JRBC_STATUS__RB_JOB_DONE_MASK); } -static int jpeg_v2_0_wait_for_idle(void *handle) +static int jpeg_v2_0_wait_for_idle(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int ret; ret = SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_JRBC_STATUS, UVD_JRBC_STATUS__RB_JOB_DONE_MASK, diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c index ec0fa685e1275..f8589afb2cb26 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c @@ -501,9 +501,9 @@ static bool jpeg_v2_5_is_idle(void *handle) return ret; } -static int jpeg_v2_5_wait_for_idle(void *handle) +static int jpeg_v2_5_wait_for_idle(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i, ret; for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c index dd00daa1d7eda..1d3482be934c0 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c @@ -459,9 +459,9 @@ static bool jpeg_v3_0_is_idle(void *handle) return ret; } -static int jpeg_v3_0_wait_for_idle(void *handle) +static int jpeg_v3_0_wait_for_idle(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return SOC15_WAIT_ON_RREG(JPEG, 0, mmUVD_JRBC_STATUS, UVD_JRBC_STATUS__RB_JOB_DONE_MASK, diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c index b147e0eba31da..afbbc10f07767 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c @@ -621,9 +621,9 @@ static bool jpeg_v4_0_is_idle(void *handle) return ret; } -static int jpeg_v4_0_wait_for_idle(void *handle) +static int jpeg_v4_0_wait_for_idle(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_JRBC_STATUS, UVD_JRBC_STATUS__RB_JOB_DONE_MASK, diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c index 270167c20cfff..0cc1f83859ead 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c @@ -921,9 +921,9 @@ static bool jpeg_v4_0_3_is_idle(void *handle) return ret; } -static int jpeg_v4_0_3_wait_for_idle(void *handle) +static int jpeg_v4_0_3_wait_for_idle(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int ret = 0; int i, j; diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c index 48ab3e0a62d25..d808e5a053e8a 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c @@ -637,9 +637,9 @@ static bool jpeg_v4_0_5_is_idle(void *handle) return ret; } -static int jpeg_v4_0_5_wait_for_idle(void *handle) +static int jpeg_v4_0_5_wait_for_idle(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i; for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c index 61288104060de..a65d92c2e55bd 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c @@ -546,9 +546,9 @@ static bool jpeg_v5_0_0_is_idle(void *handle) return ret; } -static int jpeg_v5_0_0_wait_for_idle(void *handle) +static int jpeg_v5_0_0_wait_for_idle(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return SOC15_WAIT_ON_RREG(JPEG, 0, regUVD_JRBC_STATUS, UVD_JRBC_STATUS__RB_JOB_DONE_MASK, diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c index 17aab897f86b9..60abef755610c 100644 --- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c @@ -638,7 +638,7 @@ static bool navi10_ih_is_idle(void *handle) return true; } -static int navi10_ih_wait_for_idle(void *handle) +static int navi10_ih_wait_for_idle(struct amdgpu_ip_block *ip_block) { /* todo */ return -ETIMEDOUT; diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index 63a3c725ceb95..e2577049d4efa 100644 --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c @@ -1048,7 +1048,7 @@ static bool nv_common_is_idle(void *handle) return true; } -static int nv_common_wait_for_idle(void *handle) +static int nv_common_wait_for_idle(struct amdgpu_ip_block *ip_block) { return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c index 5b81985588690..2fedda7877d90 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c @@ -927,11 +927,11 @@ static bool sdma_v2_4_is_idle(void *handle) return true; } -static int sdma_v2_4_wait_for_idle(void *handle) +static int sdma_v2_4_wait_for_idle(struct amdgpu_ip_block *ip_block) { unsigned i; u32 tmp; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; for (i = 0; i < adev->usec_timeout; i++) { tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK | diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c index 37275b38bca82..9b7dca594acdc 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c @@ -1214,11 +1214,11 @@ static bool sdma_v3_0_is_idle(void *handle) return true; } -static int sdma_v3_0_wait_for_idle(void *handle) +static int sdma_v3_0_wait_for_idle(struct amdgpu_ip_block *ip_block) { unsigned i; u32 tmp; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; for (i = 0; i < adev->usec_timeout; i++) { tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK | diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index 101b38a4d5ced..f2ff7e906c269 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c @@ -2031,11 +2031,11 @@ static bool sdma_v4_0_is_idle(void *handle) return true; } -static int sdma_v4_0_wait_for_idle(void *handle) +static int sdma_v4_0_wait_for_idle(struct amdgpu_ip_block *ip_block) { unsigned i, j; u32 sdma[AMDGPU_MAX_SDMA_INSTANCES]; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; for (i = 0; i < adev->usec_timeout; i++) { for (j = 0; j < adev->sdma.num_instances; j++) { diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c index c7c4456586cc9..dd88e3ce7604a 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c @@ -1540,11 +1540,11 @@ static bool sdma_v4_4_2_is_idle(void *handle) return true; } -static int sdma_v4_4_2_wait_for_idle(void *handle) +static int sdma_v4_4_2_wait_for_idle(struct amdgpu_ip_block *ip_block) { unsigned i, j; u32 sdma[AMDGPU_MAX_SDMA_INSTANCES]; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; for (i = 0; i < adev->usec_timeout; i++) { for (j = 0; j < adev->sdma.num_instances; j++) { diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c index 475629702fa61..7db4fb7a0d1e6 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c @@ -1531,11 +1531,11 @@ static bool sdma_v5_0_is_idle(void *handle) return true; } -static int sdma_v5_0_wait_for_idle(void *handle) +static int sdma_v5_0_wait_for_idle(struct amdgpu_ip_block *ip_block) { unsigned i; u32 sdma0, sdma1; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; for (i = 0; i < adev->usec_timeout; i++) { sdma0 = RREG32(sdma_v5_0_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG)); diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c index 64583cbeeb361..86711ab1a4db1 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c @@ -1426,11 +1426,11 @@ static bool sdma_v5_2_is_idle(void *handle) return true; } -static int sdma_v5_2_wait_for_idle(void *handle) +static int sdma_v5_2_wait_for_idle(struct amdgpu_ip_block *ip_block) { unsigned i; u32 sdma0, sdma1, sdma2, sdma3; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; for (i = 0; i < adev->usec_timeout; i++) { sdma0 = RREG32(sdma_v5_2_get_reg_offset(adev, 0, mmSDMA0_STATUS_REG)); diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c index 5b549e00143ee..5df40f8153e3f 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c @@ -1429,11 +1429,11 @@ static bool sdma_v6_0_is_idle(void *handle) return true; } -static int sdma_v6_0_wait_for_idle(void *handle) +static int sdma_v6_0_wait_for_idle(struct amdgpu_ip_block *ip_block) { unsigned i; u32 sdma0, sdma1; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; for (i = 0; i < adev->usec_timeout; i++) { sdma0 = RREG32(sdma_v6_0_get_reg_offset(adev, 0, regSDMA0_STATUS_REG)); diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c index 90baf9a20b227..5bd3cb5f84f31 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c @@ -1387,11 +1387,11 @@ static bool sdma_v7_0_is_idle(void *handle) return true; } -static int sdma_v7_0_wait_for_idle(void *handle) +static int sdma_v7_0_wait_for_idle(struct amdgpu_ip_block *ip_block) { unsigned i; u32 sdma0, sdma1; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; for (i = 0; i < adev->usec_timeout; i++) { sdma0 = RREG32(sdma_v7_0_get_reg_offset(adev, 0, regSDMA0_STATUS_REG)); diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c index 93c68abf447a6..46d6a2e791903 100644 --- a/drivers/gpu/drm/amd/amdgpu/si.c +++ b/drivers/gpu/drm/amd/amdgpu/si.c @@ -2669,7 +2669,7 @@ static bool si_common_is_idle(void *handle) return true; } -static int si_common_wait_for_idle(void *handle) +static int si_common_wait_for_idle(struct amdgpu_ip_block *ip_block) { return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c index 791d492e991d4..febd28ad95318 100644 --- a/drivers/gpu/drm/amd/amdgpu/si_dma.c +++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c @@ -550,6 +550,7 @@ static int si_dma_resume(void *handle) static bool si_dma_is_idle(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; + u32 tmp = RREG32(SRBM_STATUS2); if (tmp & (DMA_BUSY_MASK | DMA1_BUSY_MASK)) @@ -558,13 +559,13 @@ static bool si_dma_is_idle(void *handle) return true; } -static int si_dma_wait_for_idle(void *handle) +static int si_dma_wait_for_idle(struct amdgpu_ip_block *ip_block) { unsigned i; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; for (i = 0; i < adev->usec_timeout; i++) { - if (si_dma_is_idle(handle)) + if (si_dma_is_idle(adev)) return 0; udelay(1); } diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c b/drivers/gpu/drm/amd/amdgpu/si_ih.c index bd2ae82554982..3cc43ab0df9d9 100644 --- a/drivers/gpu/drm/amd/amdgpu/si_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c @@ -227,13 +227,13 @@ static bool si_ih_is_idle(void *handle) return true; } -static int si_ih_wait_for_idle(void *handle) +static int si_ih_wait_for_idle(struct amdgpu_ip_block *ip_block) { unsigned i; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; for (i = 0; i < adev->usec_timeout; i++) { - if (si_ih_is_idle(handle)) + if (si_ih_is_idle(adev)) return 0; udelay(1); } diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index e1161027ec3b7..4025e3ba55a37 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -1341,7 +1341,7 @@ static bool soc15_common_is_idle(void *handle) return true; } -static int soc15_common_wait_for_idle(void *handle) +static int soc15_common_wait_for_idle(struct amdgpu_ip_block *ip_block) { return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c index c9e88cd4349ae..695c93528dc98 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc21.c +++ b/drivers/gpu/drm/amd/amdgpu/soc21.c @@ -934,7 +934,7 @@ static bool soc21_common_is_idle(void *handle) return true; } -static int soc21_common_wait_for_idle(void *handle) +static int soc21_common_wait_for_idle(struct amdgpu_ip_block *ip_block) { return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/soc24.c b/drivers/gpu/drm/amd/amdgpu/soc24.c index 3dcb3d953509d..d6942fdc2540b 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc24.c +++ b/drivers/gpu/drm/amd/amdgpu/soc24.c @@ -531,7 +531,7 @@ static bool soc24_common_is_idle(void *handle) return true; } -static int soc24_common_wait_for_idle(void *handle) +static int soc24_common_wait_for_idle(struct amdgpu_ip_block *ip_block) { return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c index ae27dac941177..8462328d25de9 100644 --- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c @@ -370,11 +370,11 @@ static bool tonga_ih_is_idle(void *handle) return true; } -static int tonga_ih_wait_for_idle(void *handle) +static int tonga_ih_wait_for_idle(struct amdgpu_ip_block *ip_block) { unsigned i; u32 tmp; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; for (i = 0; i < adev->usec_timeout; i++) { /* read MC_STATUS */ diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c index d5e2b9639238c..a745dba3d361d 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c @@ -766,10 +766,10 @@ static bool uvd_v3_1_is_idle(void *handle) return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); } -static int uvd_v3_1_wait_for_idle(void *handle) +static int uvd_v3_1_wait_for_idle(struct amdgpu_ip_block *ip_block) { unsigned i; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; for (i = 0; i < adev->usec_timeout; i++) { if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK)) diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c index 5c46174dabbf3..8c1283c5e3925 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c @@ -666,10 +666,10 @@ static bool uvd_v4_2_is_idle(void *handle) return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); } -static int uvd_v4_2_wait_for_idle(void *handle) +static int uvd_v4_2_wait_for_idle(struct amdgpu_ip_block *ip_block) { unsigned i; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; for (i = 0; i < adev->usec_timeout; i++) { if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK)) diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c index fd4acb1300f93..5c81304f5b118 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c @@ -588,10 +588,10 @@ static bool uvd_v5_0_is_idle(void *handle) return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); } -static int uvd_v5_0_wait_for_idle(void *handle) +static int uvd_v5_0_wait_for_idle(struct amdgpu_ip_block *ip_block) { unsigned i; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; for (i = 0; i < adev->usec_timeout; i++) { if (!(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK)) @@ -796,10 +796,15 @@ static int uvd_v5_0_set_clockgating_state(void *handle, { struct amdgpu_device *adev = (struct amdgpu_device *)handle; bool enable = (state == AMD_CG_STATE_GATE); + struct amdgpu_ip_block *ip_block; + + ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD); + if (!ip_block) + return -EINVAL; if (enable) { /* wait for STATUS to clear */ - if (uvd_v5_0_wait_for_idle(handle)) + if (uvd_v5_0_wait_for_idle(ip_block)) return -EBUSY; uvd_v5_0_enable_clock_gating(adev, true); diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c index e05e81d6fbd49..bb0eb97849fc7 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c @@ -1151,13 +1151,13 @@ static bool uvd_v6_0_is_idle(void *handle) return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); } -static int uvd_v6_0_wait_for_idle(void *handle) +static int uvd_v6_0_wait_for_idle(struct amdgpu_ip_block *ip_block) { unsigned i; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; for (i = 0; i < adev->usec_timeout; i++) { - if (uvd_v6_0_is_idle(handle)) + if (uvd_v6_0_is_idle(adev)) return 0; } return -ETIMEDOUT; @@ -1455,11 +1455,16 @@ static int uvd_v6_0_set_clockgating_state(void *handle, enum amd_clockgating_state state) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_ip_block *ip_block; bool enable = (state == AMD_CG_STATE_GATE); + ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD); + if (!ip_block) + return -EINVAL; + if (enable) { /* wait for STATUS to clear */ - if (uvd_v6_0_wait_for_idle(handle)) + if (uvd_v6_0_wait_for_idle(ip_block)) return -EBUSY; uvd_v6_0_enable_clock_gating(adev, true); /* enable HW gates because UVD is idle */ diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c index 15b8f6211bb58..2fac0d6fae660 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c @@ -1471,10 +1471,10 @@ static bool uvd_v7_0_is_idle(void *handle) return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK); } -static int uvd_v7_0_wait_for_idle(void *handle) +static int uvd_v7_0_wait_for_idle(struct amdgpu_ip_block *ip_block) { unsigned i; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; for (i = 0; i < adev->usec_timeout; i++) { if (uvd_v7_0_is_idle(handle)) @@ -1728,6 +1728,11 @@ static int uvd_v7_0_set_clockgating_state(void *handle, { struct amdgpu_device *adev = (struct amdgpu_device *)handle; bool enable = (state == AMD_CG_STATE_GATE); + struct amdgpu_ip_block *ip_block; + + ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_UVD); + if (!ip_block) + return -EINVAL; uvd_v7_0_set_bypass_mode(adev, enable); @@ -1739,7 +1744,7 @@ static int uvd_v7_0_set_clockgating_state(void *handle, uvd_v7_0_set_sw_clock_gating(adev); } else { /* wait for STATUS to clear */ - if (uvd_v7_0_wait_for_idle(handle)) + if (uvd_v7_0_wait_for_idle(ip_block)) return -EBUSY; /* enable HW gates because UVD is idle */ diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c index 97ce06228a910..1301172df3e13 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c @@ -208,13 +208,13 @@ static bool vce_v2_0_is_idle(void *handle) return !(RREG32(mmSRBM_STATUS2) & SRBM_STATUS2__VCE_BUSY_MASK); } -static int vce_v2_0_wait_for_idle(void *handle) +static int vce_v2_0_wait_for_idle(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; unsigned i; for (i = 0; i < adev->usec_timeout; i++) { - if (vce_v2_0_is_idle(handle)) + if (vce_v2_0_is_idle(adev)) return 0; } return -ETIMEDOUT; @@ -274,15 +274,21 @@ static int vce_v2_0_start(struct amdgpu_device *adev) static int vce_v2_0_stop(struct amdgpu_device *adev) { + struct amdgpu_ip_block *ip_block; int i; int status; + if (vce_v2_0_lmi_clean(adev)) { DRM_INFO("vce is not idle \n"); return 0; } - if (vce_v2_0_wait_for_idle(adev)) { + ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCN); + if (!ip_block) + return -EINVAL; + + if (vce_v2_0_wait_for_idle(ip_block)) { DRM_INFO("VCE is busy, Can't set clock gating"); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c index 31ca855a950af..db8bdf2efd4fe 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c @@ -64,7 +64,7 @@ static void vce_v3_0_mc_resume(struct amdgpu_device *adev, int idx); static void vce_v3_0_set_ring_funcs(struct amdgpu_device *adev); static void vce_v3_0_set_irq_funcs(struct amdgpu_device *adev); -static int vce_v3_0_wait_for_idle(void *handle); +static int vce_v3_0_wait_for_idle(struct amdgpu_ip_block *ip_block); static int vce_v3_0_set_clockgating_state(void *handle, enum amd_clockgating_state state); /** @@ -489,10 +489,15 @@ static int vce_v3_0_hw_fini(void *handle) { int r; struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_ip_block *ip_block; + + ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE); + if (!ip_block) + return -EINVAL; cancel_delayed_work_sync(&adev->vce.idle_work); - r = vce_v3_0_wait_for_idle(handle); + r = vce_v3_0_wait_for_idle(ip_block); if (r) return r; @@ -609,13 +614,13 @@ static bool vce_v3_0_is_idle(void *handle) return !(RREG32(mmSRBM_STATUS2) & mask); } -static int vce_v3_0_wait_for_idle(void *handle) +static int vce_v3_0_wait_for_idle(struct amdgpu_ip_block *ip_block) { unsigned i; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; for (i = 0; i < adev->usec_timeout; i++) - if (vce_v3_0_is_idle(handle)) + if (vce_v3_0_is_idle(adev)) return 0; return -ETIMEDOUT; diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c index 14ead62ec57db..259be1f6abfa7 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c @@ -539,11 +539,16 @@ static int vce_v4_0_hw_init(void *handle) static int vce_v4_0_hw_fini(void *handle) { struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_ip_block *ip_block; + + ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE); + if (!ip_block) + return -EINVAL; cancel_delayed_work_sync(&adev->vce.idle_work); if (!amdgpu_sriov_vf(adev)) { - /* vce_v4_0_wait_for_idle(handle); */ + /* vce_v4_0_wait_for_idle(ip_block); */ vce_v4_0_stop(adev); } else { /* full access mode, so don't touch any VCE register */ @@ -703,10 +708,10 @@ static bool vce_v4_0_is_idle(void *handle) return !(RREG32(mmSRBM_STATUS2) & mask); } -static int vce_v4_0_wait_for_idle(void *handle) +static int vce_v4_0_wait_for_idle(struct amdgpu_ip_block *ip_block) { unsigned i; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; for (i = 0; i < adev->usec_timeout; i++) if (vce_v4_0_is_idle(handle)) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index b079afa9fff7c..fc2371b506bd3 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c @@ -1384,9 +1384,9 @@ static bool vcn_v1_0_is_idle(void *handle) return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE); } -static int vcn_v1_0_wait_for_idle(void *handle) +static int vcn_v1_0_wait_for_idle(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int ret; ret = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c index 18383e7a13ce1..b6301f10d53f0 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c @@ -1326,9 +1326,9 @@ static bool vcn_v2_0_is_idle(void *handle) return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE); } -static int vcn_v2_0_wait_for_idle(void *handle) +static int vcn_v2_0_wait_for_idle(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int ret; ret = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE, diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c index 0ba7bc0524479..edfce21ff0803 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c @@ -1786,9 +1786,9 @@ static bool vcn_v2_5_is_idle(void *handle) return ret; } -static int vcn_v2_5_wait_for_idle(void *handle) +static int vcn_v2_5_wait_for_idle(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i, ret = 0; for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c index 7204e3630052b..7f9de8209d94b 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c @@ -2116,9 +2116,9 @@ static bool vcn_v3_0_is_idle(void *handle) return ret; } -static int vcn_v3_0_wait_for_idle(void *handle) +static int vcn_v3_0_wait_for_idle(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i, ret = 0; for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c index cfebd1255b758..dab34d0b53a8b 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c @@ -1979,9 +1979,9 @@ static bool vcn_v4_0_is_idle(void *handle) * * Wait for VCN block idle */ -static int vcn_v4_0_wait_for_idle(void *handle) +static int vcn_v4_0_wait_for_idle(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i, ret = 0; for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c index d64f4735ebf37..084b40e24c929 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c @@ -1571,9 +1571,9 @@ static bool vcn_v4_0_3_is_idle(void *handle) * * Wait for VCN block idle */ -static int vcn_v4_0_3_wait_for_idle(void *handle) +static int vcn_v4_0_3_wait_for_idle(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i, ret = 0; for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c index d13f07faae8a0..25a42702edf2f 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c @@ -1473,9 +1473,9 @@ static bool vcn_v4_0_5_is_idle(void *handle) * * Wait for VCN block idle */ -static int vcn_v4_0_5_wait_for_idle(void *handle) +static int vcn_v4_0_5_wait_for_idle(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i, ret = 0; for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c index d9c92df3843f0..67f7de6cdb5a0 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c @@ -1200,9 +1200,9 @@ static bool vcn_v5_0_0_is_idle(void *handle) * * Wait for VCN block idle */ -static int vcn_v5_0_0_wait_for_idle(void *handle) +static int vcn_v5_0_0_wait_for_idle(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i, ret = 0; for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c index 5b0c81d510e7b..d1762b75752cf 100644 --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c @@ -570,7 +570,7 @@ static bool vega10_ih_is_idle(void *handle) return true; } -static int vega10_ih_wait_for_idle(void *handle) +static int vega10_ih_wait_for_idle(struct amdgpu_ip_block *ip_block) { /* todo */ return -ETIMEDOUT; diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c index dec7279c81062..7d312364d07ed 100644 --- a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c @@ -636,7 +636,7 @@ static bool vega20_ih_is_idle(void *handle) return true; } -static int vega20_ih_wait_for_idle(void *handle) +static int vega20_ih_wait_for_idle(struct amdgpu_ip_block *ip_block) { /* todo */ return -ETIMEDOUT; diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index c9ee4491ba64c..f70fb03f4b742 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/drivers/gpu/drm/amd/amdgpu/vi.c @@ -1750,7 +1750,7 @@ static bool vi_common_is_idle(void *handle) return true; } -static int vi_common_wait_for_idle(void *handle) +static int vi_common_wait_for_idle(struct amdgpu_ip_block *ip_block) { return 0; } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index ed4e2defbb444..6262e1cd8b9e2 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -321,7 +321,7 @@ static bool dm_is_idle(void *handle) return true; } -static int dm_wait_for_idle(void *handle) +static int dm_wait_for_idle(struct amdgpu_ip_block *ip_block) { /* XXX todo */ return 0; diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h index 67d75ac339bf1..367d3125b3c9a 100644 --- a/drivers/gpu/drm/amd/include/amd_shared.h +++ b/drivers/gpu/drm/amd/include/amd_shared.h @@ -391,11 +391,11 @@ struct amd_ip_funcs { int (*suspend)(void *handle); int (*resume)(void *handle); bool (*is_idle)(void *handle); - int (*wait_for_idle)(void *handle); - bool (*check_soft_reset)(void *handle); - int (*pre_soft_reset)(void *handle); - int (*soft_reset)(void *handle); - int (*post_soft_reset)(void *handle); + int (*wait_for_idle)(struct amdgpu_ip_block *ip_block); + bool (*check_soft_reset)(struct amdgpu_ip_block *ip_block); + int (*pre_soft_reset)(struct amdgpu_ip_block *ip_block); + int (*soft_reset)(struct amdgpu_ip_block *ip_block); + int (*post_soft_reset)(struct amdgpu_ip_block *ip_block); int (*set_clockgating_state)(void *handle, enum amd_clockgating_state state); int (*set_powergating_state)(void *handle, diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c index ff71af96eb1a9..96d11fb36d9d5 100644 --- a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c @@ -3100,7 +3100,7 @@ static bool kv_dpm_is_idle(void *handle) return true; } -static int kv_dpm_wait_for_idle(void *handle) +static int kv_dpm_wait_for_idle(struct amdgpu_ip_block *ip_block) { return 0; } diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c index 5aa4eca21708c..346a94cfa8d9c 100644 --- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c @@ -7843,7 +7843,7 @@ static bool si_dpm_is_idle(void *handle) return true; } -static int si_dpm_wait_for_idle(void *handle) +static int si_dpm_wait_for_idle(struct amdgpu_ip_block *ip_block) { /* XXX */ return 0; diff --git a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c index 2af325b9fc197..6bbf856b8cc48 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c +++ b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c @@ -245,7 +245,7 @@ static bool pp_is_idle(void *handle) return false; } -static int pp_wait_for_idle(void *handle) +static int pp_wait_for_idle(struct amdgpu_ip_block *ip_block) { return 0; } From 3f609d00ee82ed873634fa49b2ec671346f00b3f Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Mon, 30 Sep 2024 17:00:38 +0530 Subject: [PATCH 1724/1868] drm/amdgpu: update the handle ptr in suspend MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Update the *handle to amdgpu_ip_block ptr for all functions pointers of suspend. Signed-off-by: Sunil Khatri Reviewed-by: Christian König Change-Id: I2f17fd4886e7d660f5e498baf6338aaf23ab7eb9 (cherry picked from commit d2e50048289fbfed15d4f38596aa6f177dc98cf7) --- drivers/gpu/drm/amd/amdgpu/aldebaran.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/cik.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/cik_ih.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/cz_ih.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 6 ++++-- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 6 ++++-- drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 6 ++++-- drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 6 ++++-- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 6 ++++-- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 6 ++++-- drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/iceland_ih.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/ih_v6_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/ih_v6_1.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/ih_v7_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/nv.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/si.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/si_dma.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/si_ih.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c | 2 +- drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.c | 2 +- drivers/gpu/drm/amd/amdgpu/soc15.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/soc21.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/soc24.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vega20_ih.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vi.c | 4 ++-- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++-- drivers/gpu/drm/amd/include/amd_shared.h | 6 +++--- drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c | 4 ++-- drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 4 ++-- drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c | 4 ++-- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 4 ++-- 89 files changed, 192 insertions(+), 180 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/aldebaran.c b/drivers/gpu/drm/amd/amdgpu/aldebaran.c index 98fb0ba4f9cb8..099820015339f 100644 --- a/drivers/gpu/drm/amd/amdgpu/aldebaran.c +++ b/drivers/gpu/drm/amd/amdgpu/aldebaran.c @@ -85,7 +85,7 @@ static int aldebaran_mode2_suspend_ip(struct amdgpu_device *adev) AMD_IP_BLOCK_TYPE_SDMA)) continue; - r = adev->ip_blocks[i].version->funcs->suspend(adev); + r = adev->ip_blocks[i].version->funcs->suspend(&adev->ip_blocks[i]); if (r) { dev_err(adev->dev, diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c index e0f9c73921d51..33b797bd33c58 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c @@ -568,9 +568,9 @@ static int acp_hw_fini(void *handle) return 0; } -static int acp_suspend(void *handle) +static int acp_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; /* power up on suspend */ if (!adev->acp.acp_cell) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 6303686898a78..0a3f986298954 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -3485,7 +3485,7 @@ static int amdgpu_device_ip_suspend_phase1(struct amdgpu_device *adev) continue; /* XXX handle errors */ - r = adev->ip_blocks[i].version->funcs->suspend(adev); + r = adev->ip_blocks[i].version->funcs->suspend(&adev->ip_blocks[i]); /* XXX handle errors */ if (r) { DRM_ERROR("suspend of IP block <%s> failed %d\n", @@ -3567,7 +3567,7 @@ static int amdgpu_device_ip_suspend_phase2(struct amdgpu_device *adev) continue; /* XXX handle errors */ - r = adev->ip_blocks[i].version->funcs->suspend(adev); + r = adev->ip_blocks[i].version->funcs->suspend(&adev->ip_blocks[i]); /* XXX handle errors */ if (r) { DRM_ERROR("suspend of IP block <%s> failed %d\n", diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c index 50e56f1093e41..567e3de5e89b0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c @@ -83,7 +83,7 @@ static int isp_hw_fini(void *handle) return -ENODEV; } -static int isp_suspend(void *handle) +static int isp_suspend(struct amdgpu_ip_block *ip_block) { return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 6a7e2d14f363d..c0c55c0b951de 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -3026,10 +3026,10 @@ static int psp_hw_fini(void *handle) return 0; } -static int psp_suspend(void *handle) +static int psp_suspend(struct amdgpu_ip_block *ip_block) { int ret = 0; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; struct psp_context *psp = &adev->psp; if (adev->gmc.xgmi.num_physical_nodes > 1 && diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c index ea5e861accb13..f34bbf586b288 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c @@ -40,7 +40,7 @@ static int amdgpu_reset_xgmi_reset_on_init_suspend(struct amdgpu_device *adev) continue; /* XXX handle errors */ - r = adev->ip_blocks[i].version->funcs->suspend(adev); + r = adev->ip_blocks[i].version->funcs->suspend(&adev->ip_blocks[i]); /* XXX handle errors */ if (r) { dev_err(adev->dev, "suspend of IP block <%s> failed %d", diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c index d7e3773413676..2116358827ea9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c @@ -873,9 +873,9 @@ static int umsch_mm_hw_fini(void *handle) return 0; } -static int umsch_mm_suspend(void *handle) +static int umsch_mm_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return umsch_mm_hw_fini(adev); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c index b64e31ae12483..fb3fb7c652ae1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c @@ -751,15 +751,15 @@ static int amdgpu_vkms_hw_fini(void *handle) return 0; } -static int amdgpu_vkms_suspend(void *handle) +static int amdgpu_vkms_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; r = drm_mode_config_helper_suspend(adev_to_drm(adev)); if (r) return r; - return amdgpu_vkms_hw_fini(handle); + return amdgpu_vkms_hw_fini(adev); } static int amdgpu_vkms_resume(void *handle) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c index c9c4e8c7dc9f5..dc3da75732fcf 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c @@ -434,9 +434,9 @@ static int vpe_hw_fini(void *handle) return 0; } -static int vpe_suspend(void *handle) +static int vpe_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; cancel_delayed_work_sync(&adev->vpe.idle_work); diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c index 7c3a0bd4c4a39..9e60001d1b8d9 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik.c +++ b/drivers/gpu/drm/amd/amdgpu/cik.c @@ -2153,9 +2153,9 @@ static int cik_common_hw_fini(void *handle) return 0; } -static int cik_common_suspend(void *handle) +static int cik_common_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return cik_common_hw_fini(adev); } diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c index f39f01525f8d9..fa87e51fdb4c1 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c @@ -337,9 +337,9 @@ static int cik_ih_hw_fini(void *handle) return 0; } -static int cik_ih_suspend(void *handle) +static int cik_ih_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return cik_ih_hw_fini(adev); } diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c index b0628cba5864e..4d8c3b4283719 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c @@ -1011,9 +1011,9 @@ static int cik_sdma_hw_fini(void *handle) return 0; } -static int cik_sdma_suspend(void *handle) +static int cik_sdma_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return cik_sdma_hw_fini(adev); } diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c index 367dd9aa72fcb..4a2a3a4f80ef9 100644 --- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c @@ -333,9 +333,9 @@ static int cz_ih_hw_fini(void *handle) return 0; } -static int cz_ih_suspend(void *handle) +static int cz_ih_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return cz_ih_hw_fini(adev); } diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index eb5d08f493e43..6305be9104363 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -2917,9 +2917,9 @@ static int dce_v10_0_hw_fini(void *handle) return 0; } -static int dce_v10_0_suspend(void *handle) +static int dce_v10_0_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; r = amdgpu_display_suspend_helper(adev); @@ -2929,7 +2929,7 @@ static int dce_v10_0_suspend(void *handle) adev->mode_info.bl_level = amdgpu_atombios_encoder_get_backlight_level_from_reg(adev); - return dce_v10_0_hw_fini(handle); + return dce_v10_0_hw_fini(adev); } static int dce_v10_0_resume(void *handle) diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index e8298dd0b1dc1..d460a6e06594a 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -3055,9 +3055,9 @@ static int dce_v11_0_hw_fini(void *handle) return 0; } -static int dce_v11_0_suspend(void *handle) +static int dce_v11_0_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; r = amdgpu_display_suspend_helper(adev); @@ -3067,7 +3067,7 @@ static int dce_v11_0_suspend(void *handle) adev->mode_info.bl_level = amdgpu_atombios_encoder_get_backlight_level_from_reg(adev); - return dce_v11_0_hw_fini(handle); + return dce_v11_0_hw_fini(adev); } static int dce_v11_0_resume(void *handle) diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c index 5b48f6ea4da76..fb0bd39558521 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c @@ -2813,9 +2813,9 @@ static int dce_v6_0_hw_fini(void *handle) return 0; } -static int dce_v6_0_suspend(void *handle) +static int dce_v6_0_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; r = amdgpu_display_suspend_helper(adev); @@ -2824,7 +2824,7 @@ static int dce_v6_0_suspend(void *handle) adev->mode_info.bl_level = amdgpu_atombios_encoder_get_backlight_level_from_reg(adev); - return dce_v6_0_hw_fini(handle); + return dce_v6_0_hw_fini(adev); } static int dce_v6_0_resume(void *handle) diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index 5e6f671955a5d..a42e39240d6ed 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -2834,9 +2834,9 @@ static int dce_v8_0_hw_fini(void *handle) return 0; } -static int dce_v8_0_suspend(void *handle) +static int dce_v8_0_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; r = amdgpu_display_suspend_helper(adev); @@ -2846,7 +2846,7 @@ static int dce_v8_0_suspend(void *handle) adev->mode_info.bl_level = amdgpu_atombios_encoder_get_backlight_level_from_reg(adev); - return dce_v8_0_hw_fini(handle); + return dce_v8_0_hw_fini(adev); } static int dce_v8_0_resume(void *handle) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 2969bf1c45f22..dcb759dca167b 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -7464,9 +7464,11 @@ static int gfx_v10_0_hw_fini(void *handle) return 0; } -static int gfx_v10_0_suspend(void *handle) +static int gfx_v10_0_suspend(struct amdgpu_ip_block *ip_block) { - return gfx_v10_0_hw_fini(handle); + struct amdgpu_device *adev = ip_block->adev; + + return gfx_v10_0_hw_fini(adev); } static int gfx_v10_0_resume(void *handle) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index 052ecf7ab71f5..99dea7ab78b18 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -4705,9 +4705,11 @@ static int gfx_v11_0_hw_fini(void *handle) return 0; } -static int gfx_v11_0_suspend(void *handle) +static int gfx_v11_0_suspend(struct amdgpu_ip_block *ip_block) { - return gfx_v11_0_hw_fini(handle); + struct amdgpu_device *adev = ip_block->adev; + + return gfx_v11_0_hw_fini(adev); } static int gfx_v11_0_resume(void *handle) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c index 04efb51375528..6e1a9b8407b95 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c @@ -3643,9 +3643,11 @@ static int gfx_v12_0_hw_fini(void *handle) return 0; } -static int gfx_v12_0_suspend(void *handle) +static int gfx_v12_0_suspend(struct amdgpu_ip_block *ip_block) { - return gfx_v12_0_hw_fini(handle); + struct amdgpu_device *adev = ip_block->adev; + + return gfx_v12_0_hw_fini(adev); } static int gfx_v12_0_resume(void *handle) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c index 0ddb98b0fa5f4..e810e3853d4fd 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c @@ -3153,9 +3153,9 @@ static int gfx_v6_0_hw_fini(void *handle) return 0; } -static int gfx_v6_0_suspend(void *handle) +static int gfx_v6_0_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return gfx_v6_0_hw_fini(adev); } diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index 592a6dbc1bcde..8bc1315fbe737 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -4499,9 +4499,9 @@ static int gfx_v7_0_hw_fini(void *handle) return 0; } -static int gfx_v7_0_suspend(void *handle) +static int gfx_v7_0_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return gfx_v7_0_hw_fini(adev); } diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 910510cdf841d..278401059fc44 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -4924,9 +4924,11 @@ static int gfx_v8_0_hw_fini(void *handle) return 0; } -static int gfx_v8_0_suspend(void *handle) +static int gfx_v8_0_suspend(struct amdgpu_ip_block *ip_block) { - return gfx_v8_0_hw_fini(handle); + struct amdgpu_device *adev = ip_block->adev; + + return gfx_v8_0_hw_fini(adev); } static int gfx_v8_0_resume(void *handle) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 25959612d221d..d0b11b78fc57b 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -4080,9 +4080,11 @@ static int gfx_v9_0_hw_fini(void *handle) return 0; } -static int gfx_v9_0_suspend(void *handle) +static int gfx_v9_0_suspend(struct amdgpu_ip_block *ip_block) { - return gfx_v9_0_hw_fini(handle); + struct amdgpu_device *adev = ip_block->adev; + + return gfx_v9_0_hw_fini(adev); } static int gfx_v9_0_resume(void *handle) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index 75d05b94710cb..24a0b2cc50261 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -2386,9 +2386,11 @@ static int gfx_v9_4_3_hw_fini(void *handle) return 0; } -static int gfx_v9_4_3_suspend(void *handle) +static int gfx_v9_4_3_suspend(struct amdgpu_ip_block *ip_block) { - return gfx_v9_4_3_hw_fini(handle); + struct amdgpu_device *adev = ip_block->adev; + + return gfx_v9_4_3_hw_fini(adev); } static int gfx_v9_4_3_resume(void *handle) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c index 0f732f853c55b..44679f737f9e6 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c @@ -1051,9 +1051,9 @@ static int gmc_v10_0_hw_fini(void *handle) return 0; } -static int gmc_v10_0_suspend(void *handle) +static int gmc_v10_0_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; gmc_v10_0_hw_fini(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c index 39095b28841e5..fdf2f0b52d72b 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c @@ -959,9 +959,9 @@ static int gmc_v11_0_hw_fini(void *handle) return 0; } -static int gmc_v11_0_suspend(void *handle) +static int gmc_v11_0_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; gmc_v11_0_hw_fini(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c index 46408e5835127..e0d758be5a5ac 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c @@ -928,9 +928,9 @@ static int gmc_v12_0_hw_fini(void *handle) return 0; } -static int gmc_v12_0_suspend(void *handle) +static int gmc_v12_0_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; gmc_v12_0_hw_fini(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c index 2759233052b4f..2c9ac638f7d64 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c @@ -934,9 +934,9 @@ static int gmc_v6_0_hw_fini(void *handle) return 0; } -static int gmc_v6_0_suspend(void *handle) +static int gmc_v6_0_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; gmc_v6_0_hw_fini(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c index 20eb42dc0c879..a8488d4b17e5d 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c @@ -1110,9 +1110,9 @@ static int gmc_v7_0_hw_fini(void *handle) return 0; } -static int gmc_v7_0_suspend(void *handle) +static int gmc_v7_0_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; gmc_v7_0_hw_fini(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index f5fb32a9083d5..48583a928202c 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -1246,9 +1246,9 @@ static int gmc_v8_0_hw_fini(void *handle) return 0; } -static int gmc_v8_0_suspend(void *handle) +static int gmc_v8_0_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; gmc_v8_0_hw_fini(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index 16c7831922054..ba46a4f9f51c3 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -2434,9 +2434,9 @@ static int gmc_v9_0_hw_fini(void *handle) return 0; } -static int gmc_v9_0_suspend(void *handle) +static int gmc_v9_0_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return gmc_v9_0_hw_fini(adev); } diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c index ac2cc7db8ba0b..484f6f8a02c98 100644 --- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c @@ -327,9 +327,9 @@ static int iceland_ih_hw_fini(void *handle) return 0; } -static int iceland_ih_suspend(void *handle) +static int iceland_ih_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return iceland_ih_hw_fini(adev); } diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c index cbaea52e0255f..037dae06526f7 100644 --- a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c @@ -644,9 +644,9 @@ static int ih_v6_0_hw_fini(void *handle) return 0; } -static int ih_v6_0_suspend(void *handle) +static int ih_v6_0_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return ih_v6_0_hw_fini(adev); } diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c index f0759a8eed29b..76201782bddf7 100644 --- a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c +++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c @@ -623,9 +623,9 @@ static int ih_v6_1_hw_fini(void *handle) return 0; } -static int ih_v6_1_suspend(void *handle) +static int ih_v6_1_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return ih_v6_1_hw_fini(adev); } diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c index 4757972aeeb49..b453cd722ba9c 100644 --- a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c @@ -613,9 +613,9 @@ static int ih_v7_0_hw_fini(void *handle) return 0; } -static int ih_v7_0_suspend(void *handle) +static int ih_v7_0_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return ih_v7_0_hw_fini(adev); } diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c index 01dd442a3311e..cc0460621ed1e 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c @@ -166,9 +166,9 @@ static int jpeg_v2_0_hw_fini(void *handle) * * HW fini and suspend JPEG block */ -static int jpeg_v2_0_suspend(void *handle) +static int jpeg_v2_0_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; r = jpeg_v2_0_hw_fini(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c index f8589afb2cb26..642acf969f62b 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c @@ -235,9 +235,9 @@ static int jpeg_v2_5_hw_fini(void *handle) * * HW fini and suspend JPEG block */ -static int jpeg_v2_5_suspend(void *handle) +static int jpeg_v2_5_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; r = jpeg_v2_5_hw_fini(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c index 1d3482be934c0..551bee67acc12 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c @@ -180,9 +180,9 @@ static int jpeg_v3_0_hw_fini(void *handle) * * HW fini and suspend JPEG block */ -static int jpeg_v3_0_suspend(void *handle) +static int jpeg_v3_0_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; r = jpeg_v3_0_hw_fini(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c index afbbc10f07767..703eb51ad8b8f 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c @@ -214,9 +214,9 @@ static int jpeg_v4_0_hw_fini(void *handle) * * HW fini and suspend JPEG block */ -static int jpeg_v4_0_suspend(void *handle) +static int jpeg_v4_0_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; r = jpeg_v4_0_hw_fini(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c index 0cc1f83859ead..a5148ea612c74 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c @@ -382,9 +382,9 @@ static int jpeg_v4_0_3_hw_fini(void *handle) * * HW fini and suspend JPEG block */ -static int jpeg_v4_0_3_suspend(void *handle) +static int jpeg_v4_0_3_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; r = jpeg_v4_0_3_hw_fini(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c index d808e5a053e8a..2cee33c46b97e 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c @@ -241,9 +241,9 @@ static int jpeg_v4_0_5_hw_fini(void *handle) * * HW fini and suspend JPEG block */ -static int jpeg_v4_0_5_suspend(void *handle) +static int jpeg_v4_0_5_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; r = jpeg_v4_0_5_hw_fini(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c index a65d92c2e55bd..41132830ca750 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c @@ -177,9 +177,9 @@ static int jpeg_v5_0_0_hw_fini(void *handle) * * HW fini and suspend JPEG block */ -static int jpeg_v5_0_0_suspend(void *handle) +static int jpeg_v5_0_0_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; r = jpeg_v5_0_0_hw_fini(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c index d476cf771bbe6..8b485e97d067f 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c @@ -1629,10 +1629,10 @@ static int mes_v11_0_hw_fini(void *handle) return 0; } -static int mes_v11_0_suspend(void *handle) +static int mes_v11_0_suspend(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; r = amdgpu_mes_suspend(adev); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c index a490d0e2c2cb4..a42e5e5e9a9b1 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c @@ -1593,10 +1593,10 @@ static int mes_v12_0_hw_fini(void *handle) return 0; } -static int mes_v12_0_suspend(void *handle) +static int mes_v12_0_suspend(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; r = amdgpu_mes_suspend(adev); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c index 60abef755610c..800d063b68010 100644 --- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c @@ -618,9 +618,9 @@ static int navi10_ih_hw_fini(void *handle) return 0; } -static int navi10_ih_suspend(void *handle) +static int navi10_ih_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return navi10_ih_hw_fini(adev); } diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index e2577049d4efa..31c849a3fb246 100644 --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c @@ -1029,9 +1029,9 @@ static int nv_common_hw_fini(void *handle) return 0; } -static int nv_common_suspend(void *handle) +static int nv_common_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return nv_common_hw_fini(adev); } diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c index 2fedda7877d90..de98d787f8a9f 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c @@ -901,9 +901,9 @@ static int sdma_v2_4_hw_fini(void *handle) return 0; } -static int sdma_v2_4_suspend(void *handle) +static int sdma_v2_4_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return sdma_v2_4_hw_fini(adev); } diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c index 9b7dca594acdc..abfcd8b6ef2bd 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c @@ -1188,9 +1188,9 @@ static int sdma_v3_0_hw_fini(void *handle) return 0; } -static int sdma_v3_0_suspend(void *handle) +static int sdma_v3_0_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return sdma_v3_0_hw_fini(adev); } diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index f2ff7e906c269..3d9e9a8357087 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c @@ -1989,9 +1989,9 @@ static int sdma_v4_0_hw_fini(void *handle) return 0; } -static int sdma_v4_0_suspend(void *handle) +static int sdma_v4_0_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; /* SMU saves SDMA state for us */ if (adev->in_s0ix) { diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c index dd88e3ce7604a..89961010d7b43 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c @@ -1508,9 +1508,9 @@ static int sdma_v4_4_2_hw_fini(void *handle) static int sdma_v4_4_2_set_clockgating_state(void *handle, enum amd_clockgating_state state); -static int sdma_v4_4_2_suspend(void *handle) +static int sdma_v4_4_2_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (amdgpu_in_reset(adev)) sdma_v4_4_2_set_clockgating_state(adev, AMD_CG_STATE_UNGATE); diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c index 7db4fb7a0d1e6..2cf1493e42962 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c @@ -1502,9 +1502,9 @@ static int sdma_v5_0_hw_fini(void *handle) return 0; } -static int sdma_v5_0_suspend(void *handle) +static int sdma_v5_0_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return sdma_v5_0_hw_fini(adev); } diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c index 86711ab1a4db1..716e66ea70666 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c @@ -1397,9 +1397,9 @@ static int sdma_v5_2_hw_fini(void *handle) return 0; } -static int sdma_v5_2_suspend(void *handle) +static int sdma_v5_2_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return sdma_v5_2_hw_fini(adev); } diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c index 5df40f8153e3f..96cc696911108 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c @@ -1400,9 +1400,9 @@ static int sdma_v6_0_hw_fini(void *handle) return 0; } -static int sdma_v6_0_suspend(void *handle) +static int sdma_v6_0_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return sdma_v6_0_hw_fini(adev); } diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c index 5bd3cb5f84f31..1ea332b2ff887 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c @@ -1358,9 +1358,9 @@ static int sdma_v7_0_hw_fini(void *handle) return 0; } -static int sdma_v7_0_suspend(void *handle) +static int sdma_v7_0_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return sdma_v7_0_hw_fini(adev); } diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c index 46d6a2e791903..07b360009fbbc 100644 --- a/drivers/gpu/drm/amd/amdgpu/si.c +++ b/drivers/gpu/drm/amd/amdgpu/si.c @@ -2650,9 +2650,9 @@ static int si_common_hw_fini(void *handle) return 0; } -static int si_common_suspend(void *handle) +static int si_common_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return si_common_hw_fini(adev); } diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c index febd28ad95318..e67ed0059cc8f 100644 --- a/drivers/gpu/drm/amd/amdgpu/si_dma.c +++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c @@ -533,9 +533,9 @@ static int si_dma_hw_fini(void *handle) return 0; } -static int si_dma_suspend(void *handle) +static int si_dma_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return si_dma_hw_fini(adev); } diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c b/drivers/gpu/drm/amd/amdgpu/si_ih.c index 3cc43ab0df9d9..b1b5e3c693aa2 100644 --- a/drivers/gpu/drm/amd/amdgpu/si_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c @@ -202,9 +202,9 @@ static int si_ih_hw_fini(void *handle) return 0; } -static int si_ih_suspend(void *handle) +static int si_ih_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return si_ih_hw_fini(adev); } diff --git a/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c b/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c index 481217c32d853..979b186801575 100644 --- a/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c +++ b/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c @@ -81,7 +81,7 @@ static int sienna_cichlid_mode2_suspend_ip(struct amdgpu_device *adev) AMD_IP_BLOCK_TYPE_SDMA)) continue; - r = adev->ip_blocks[i].version->funcs->suspend(adev); + r = adev->ip_blocks[i].version->funcs->suspend(&adev->ip_blocks[i]); if (r) { dev_err(adev->dev, diff --git a/drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.c b/drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.c index 0af648931df58..7c097f35bca6f 100644 --- a/drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.c +++ b/drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.c @@ -80,7 +80,7 @@ static int smu_v13_0_10_mode2_suspend_ip(struct amdgpu_device *adev) AMD_IP_BLOCK_TYPE_MES)) continue; - r = adev->ip_blocks[i].version->funcs->suspend(adev); + r = adev->ip_blocks[i].version->funcs->suspend(&adev->ip_blocks[i]); if (r) { dev_err(adev->dev, diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index 4025e3ba55a37..4ba8e80c4b866 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -1318,9 +1318,9 @@ static int soc15_common_hw_fini(void *handle) return 0; } -static int soc15_common_suspend(void *handle) +static int soc15_common_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return soc15_common_hw_fini(adev); } diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c index 695c93528dc98..3ef5435aef40f 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc21.c +++ b/drivers/gpu/drm/amd/amdgpu/soc21.c @@ -890,9 +890,9 @@ static int soc21_common_hw_fini(void *handle) return 0; } -static int soc21_common_suspend(void *handle) +static int soc21_common_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return soc21_common_hw_fini(adev); } diff --git a/drivers/gpu/drm/amd/amdgpu/soc24.c b/drivers/gpu/drm/amd/amdgpu/soc24.c index d6942fdc2540b..41f9664755aaf 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc24.c +++ b/drivers/gpu/drm/amd/amdgpu/soc24.c @@ -512,9 +512,9 @@ static int soc24_common_hw_fini(void *handle) return 0; } -static int soc24_common_suspend(void *handle) +static int soc24_common_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return soc24_common_hw_fini(adev); } diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c index 8462328d25de9..67b44b5000156 100644 --- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c @@ -345,9 +345,9 @@ static int tonga_ih_hw_fini(void *handle) return 0; } -static int tonga_ih_suspend(void *handle) +static int tonga_ih_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return tonga_ih_hw_fini(adev); } diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c index a745dba3d361d..6c9e0c9f84a9a 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c @@ -711,10 +711,10 @@ static int uvd_v3_1_prepare_suspend(void *handle) return amdgpu_uvd_prepare_suspend(adev); } -static int uvd_v3_1_suspend(void *handle) +static int uvd_v3_1_suspend(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; /* * Proper cleanups before halting the HW engine: diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c index 8c1283c5e3925..c1712e1a1698c 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c @@ -225,10 +225,10 @@ static int uvd_v4_2_prepare_suspend(void *handle) return amdgpu_uvd_prepare_suspend(adev); } -static int uvd_v4_2_suspend(void *handle) +static int uvd_v4_2_suspend(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; /* * Proper cleanups before halting the HW engine: diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c index 5c81304f5b118..95e8418805040 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c @@ -223,10 +223,10 @@ static int uvd_v5_0_prepare_suspend(void *handle) return amdgpu_uvd_prepare_suspend(adev); } -static int uvd_v5_0_suspend(void *handle) +static int uvd_v5_0_suspend(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; /* * Proper cleanups before halting the HW engine: diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c index bb0eb97849fc7..82d9617b71f1e 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c @@ -547,10 +547,10 @@ static int uvd_v6_0_prepare_suspend(void *handle) return amdgpu_uvd_prepare_suspend(adev); } -static int uvd_v6_0_suspend(void *handle) +static int uvd_v6_0_suspend(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; /* * Proper cleanups before halting the HW engine: diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c index 2fac0d6fae660..6229b48d31ce4 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c @@ -615,10 +615,10 @@ static int uvd_v7_0_prepare_suspend(void *handle) return amdgpu_uvd_prepare_suspend(adev); } -static int uvd_v7_0_suspend(void *handle) +static int uvd_v7_0_suspend(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; /* * Proper cleanups before halting the HW engine: diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c index 1301172df3e13..357930179996e 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c @@ -490,10 +490,10 @@ static int vce_v2_0_hw_fini(void *handle) return 0; } -static int vce_v2_0_suspend(void *handle) +static int vce_v2_0_suspend(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; /* diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c index db8bdf2efd4fe..771eadb2d8055 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c @@ -505,10 +505,10 @@ static int vce_v3_0_hw_fini(void *handle) return vce_v3_0_set_clockgating_state(adev, AMD_CG_STATE_GATE); } -static int vce_v3_0_suspend(void *handle) +static int vce_v3_0_suspend(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; /* * Proper cleanups before halting the HW engine: @@ -713,7 +713,7 @@ static int vce_v3_0_pre_soft_reset(void *handle) mdelay(5); - return vce_v3_0_suspend(adev); + return vce_v3_0_suspend(ip_block); } diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c index 259be1f6abfa7..75eb27b5f5e4e 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c @@ -558,9 +558,9 @@ static int vce_v4_0_hw_fini(void *handle) return 0; } -static int vce_v4_0_suspend(void *handle) +static int vce_v4_0_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r, idx; if (adev->vce.vcpu_bo == NULL) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index fc2371b506bd3..6a3909f3ee13f 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c @@ -294,10 +294,10 @@ static int vcn_v1_0_hw_fini(void *handle) * * HW fini and suspend VCN block */ -static int vcn_v1_0_suspend(void *handle) +static int vcn_v1_0_suspend(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; bool idle_work_unexecuted; idle_work_unexecuted = cancel_delayed_work_sync(&adev->vcn.idle_work); diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c index b6301f10d53f0..660e541399427 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c @@ -330,10 +330,10 @@ static int vcn_v2_0_hw_fini(void *handle) * * HW fini and suspend VCN block */ -static int vcn_v2_0_suspend(void *handle) +static int vcn_v2_0_suspend(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; r = vcn_v2_0_hw_fini(adev); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c index edfce21ff0803..072e060c9d6e8 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c @@ -415,10 +415,10 @@ static int vcn_v2_5_hw_fini(void *handle) * * HW fini and suspend VCN block */ -static int vcn_v2_5_suspend(void *handle) +static int vcn_v2_5_suspend(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; r = vcn_v2_5_hw_fini(adev); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c index 7f9de8209d94b..0d6294faaf0bc 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c @@ -447,10 +447,10 @@ static int vcn_v3_0_hw_fini(void *handle) * * HW fini and suspend VCN block */ -static int vcn_v3_0_suspend(void *handle) +static int vcn_v3_0_suspend(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; r = vcn_v3_0_hw_fini(adev); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c index dab34d0b53a8b..0a0b077af901d 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c @@ -376,10 +376,10 @@ static int vcn_v4_0_hw_fini(void *handle) * * HW fini and suspend VCN block */ -static int vcn_v4_0_suspend(void *handle) +static int vcn_v4_0_suspend(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; r = vcn_v4_0_hw_fini(adev); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c index 084b40e24c929..424ffa1327c4b 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c @@ -331,9 +331,9 @@ static int vcn_v4_0_3_hw_fini(void *handle) * * HW fini and suspend VCN block */ -static int vcn_v4_0_3_suspend(void *handle) +static int vcn_v4_0_3_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; r = vcn_v4_0_3_hw_fini(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c index 25a42702edf2f..e2be515304d5a 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c @@ -324,10 +324,10 @@ static int vcn_v4_0_5_hw_fini(void *handle) * * HW fini and suspend VCN block */ -static int vcn_v4_0_5_suspend(void *handle) +static int vcn_v4_0_5_suspend(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; r = vcn_v4_0_5_hw_fini(adev); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c index 67f7de6cdb5a0..648bbe967ecbb 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c @@ -288,10 +288,10 @@ static int vcn_v5_0_0_hw_fini(void *handle) * * HW fini and suspend VCN block */ -static int vcn_v5_0_0_suspend(void *handle) +static int vcn_v5_0_0_suspend(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; r = vcn_v5_0_0_hw_fini(adev); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c index d1762b75752cf..dcc961ebaee2c 100644 --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c @@ -550,9 +550,9 @@ static int vega10_ih_hw_fini(void *handle) return 0; } -static int vega10_ih_suspend(void *handle) +static int vega10_ih_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return vega10_ih_hw_fini(adev); } diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c index 7d312364d07ed..740ffef017cbe 100644 --- a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c @@ -616,9 +616,9 @@ static int vega20_ih_hw_fini(void *handle) return 0; } -static int vega20_ih_suspend(void *handle) +static int vega20_ih_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return vega20_ih_hw_fini(adev); } diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index f70fb03f4b742..7b3f850b131c2 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/drivers/gpu/drm/amd/amdgpu/vi.c @@ -1731,9 +1731,9 @@ static int vi_common_hw_fini(void *handle) return 0; } -static int vi_common_suspend(void *handle) +static int vi_common_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return vi_common_hw_fini(adev); } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 6262e1cd8b9e2..6431a3ba48861 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2971,9 +2971,9 @@ static void hpd_rx_irq_work_suspend(struct amdgpu_display_manager *dm) } } -static int dm_suspend(void *handle) +static int dm_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = handle; + struct amdgpu_device *adev = ip_block->adev; struct amdgpu_display_manager *dm = &adev->dm; int ret = 0; diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h index 367d3125b3c9a..be3c8d58e1104 100644 --- a/drivers/gpu/drm/amd/include/amd_shared.h +++ b/drivers/gpu/drm/amd/include/amd_shared.h @@ -386,9 +386,9 @@ struct amd_ip_funcs { int (*early_fini)(void *handle); int (*hw_init)(void *handle); int (*hw_fini)(void *handle); - void (*late_fini)(void *handle); - int (*prepare_suspend)(void *handle); - int (*suspend)(void *handle); + void (*late_fini)(struct amdgpu_ip_block *ip_block); + int (*prepare_suspend)(struct amdgpu_ip_block *ip_block); + int (*suspend)(struct amdgpu_ip_block *ip_block); int (*resume)(void *handle); bool (*is_idle)(void *handle); int (*wait_for_idle)(struct amdgpu_ip_block *ip_block); diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c index 96d11fb36d9d5..ab4e920819241 100644 --- a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c @@ -3063,9 +3063,9 @@ static int kv_dpm_hw_fini(void *handle) return 0; } -static int kv_dpm_suspend(void *handle) +static int kv_dpm_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (adev->pm.dpm_enabled) { /* disable dpm */ diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c index 346a94cfa8d9c..99818b138ae37 100644 --- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c @@ -7805,9 +7805,9 @@ static int si_dpm_hw_fini(void *handle) return 0; } -static int si_dpm_suspend(void *handle) +static int si_dpm_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (adev->pm.dpm_enabled) { /* disable dpm */ diff --git a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c index 6bbf856b8cc48..5bea27d864fe7 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c +++ b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c @@ -261,9 +261,9 @@ static int pp_set_powergating_state(void *handle, return 0; } -static int pp_suspend(void *handle) +static int pp_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = handle; + struct amdgpu_device *adev = ip_block->adev; struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; cancel_delayed_work_sync(&hwmgr->swctf_delayed_work); diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 8b0182d589b7b..fbc274203cc6f 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -2070,9 +2070,9 @@ static int smu_reset(struct smu_context *smu) return 0; } -static int smu_suspend(void *handle) +static int smu_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; struct smu_context *smu = adev->powerplay.pp_handle; int ret; uint64_t count; From ff43c3686fdbdb7e7f36c9ec6860796056d49daf Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Mon, 30 Sep 2024 17:42:01 +0530 Subject: [PATCH 1725/1868] drm/amdgpu: update the handle ptr in resume MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Update the *handle to amdgpu_ip_block ptr for all functions pointers of resume. Signed-off-by: Sunil Khatri Reviewed-by: Christian König Change-Id: Ie770e52fe7d386bb1e25cf32fcc129e9cd588700 (cherry picked from commit 0b2784ba568506a6f75dc7a786e9ce83f4502f30) --- drivers/gpu/drm/amd/amdgpu/aldebaran.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8 ++++---- drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/cik.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/cik_ih.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/cz_ih.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/iceland_ih.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/ih_v6_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/ih_v6_1.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/ih_v7_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/nv.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/si.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/si_dma.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/si_ih.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.c | 2 +- drivers/gpu/drm/amd/amdgpu/soc15.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/soc21.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/soc24.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vega20_ih.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vi.c | 4 ++-- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++-- drivers/gpu/drm/amd/include/amd_shared.h | 2 +- drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c | 4 ++-- drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 4 ++-- drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c | 4 ++-- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 4 ++-- 88 files changed, 182 insertions(+), 182 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/aldebaran.c b/drivers/gpu/drm/amd/amdgpu/aldebaran.c index 099820015339f..f99bf6bcec9d6 100644 --- a/drivers/gpu/drm/amd/amdgpu/aldebaran.c +++ b/drivers/gpu/drm/amd/amdgpu/aldebaran.c @@ -246,7 +246,7 @@ static int aldebaran_mode2_restore_ip(struct amdgpu_device *adev) dev_err(adev->dev, "Failed to get BIF handle\n"); return -EINVAL; } - r = cmn_block->version->funcs->resume(adev); + r = cmn_block->version->funcs->resume(cmn_block); if (r) return r; @@ -282,7 +282,7 @@ static int aldebaran_mode2_restore_ip(struct amdgpu_device *adev) adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SDMA)) continue; - r = adev->ip_blocks[i].version->funcs->resume(adev); + r = adev->ip_blocks[i].version->funcs->resume(&adev->ip_blocks[i]); if (r) { dev_err(adev->dev, "resume of IP block <%s> failed %d\n", diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c index 33b797bd33c58..d3dda5527cc48 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c @@ -578,9 +578,9 @@ static int acp_suspend(struct amdgpu_ip_block *ip_block) return 0; } -static int acp_resume(void *handle) +static int acp_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; /* power down again on resume */ if (!adev->acp.acp_cell) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 0a3f986298954..5b2e6dffd1630 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -2765,7 +2765,7 @@ static int amdgpu_device_fw_loading(struct amdgpu_device *adev) break; if (amdgpu_in_reset(adev) || adev->in_suspend) { - r = adev->ip_blocks[i].version->funcs->resume(adev); + r = adev->ip_blocks[i].version->funcs->resume(&adev->ip_blocks[i]); if (r) { DRM_ERROR("resume of IP block <%s> failed %d\n", adev->ip_blocks[i].version->funcs->name, r); @@ -3687,7 +3687,7 @@ static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev) continue; if (block->version->type == AMD_IP_BLOCK_TYPE_SMC) - r = block->version->funcs->resume(adev); + r = block->version->funcs->resume(&adev->ip_blocks[i]); else r = block->version->funcs->hw_init(adev); @@ -3725,7 +3725,7 @@ static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev) adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH || (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP && amdgpu_sriov_vf(adev))) { - r = adev->ip_blocks[i].version->funcs->resume(adev); + r = adev->ip_blocks[i].version->funcs->resume(&adev->ip_blocks[i]); if (r) { DRM_ERROR("resume of IP block <%s> failed %d\n", adev->ip_blocks[i].version->funcs->name, r); @@ -3763,7 +3763,7 @@ static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev) adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH || adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) continue; - r = adev->ip_blocks[i].version->funcs->resume(adev); + r = adev->ip_blocks[i].version->funcs->resume(&adev->ip_blocks[i]); if (r) { DRM_ERROR("resume of IP block <%s> failed %d\n", adev->ip_blocks[i].version->funcs->name, r); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c index 567e3de5e89b0..e2a5e84925013 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c @@ -88,7 +88,7 @@ static int isp_suspend(struct amdgpu_ip_block *ip_block) return 0; } -static int isp_resume(void *handle) +static int isp_resume(struct amdgpu_ip_block *ip_block) { return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index c0c55c0b951de..9ffb3629cf417 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -3089,10 +3089,10 @@ static int psp_suspend(struct amdgpu_ip_block *ip_block) return ret; } -static int psp_resume(void *handle) +static int psp_resume(struct amdgpu_ip_block *ip_block) { int ret; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; struct psp_context *psp = &adev->psp; dev_info(adev->dev, "PSP is resuming...\n"); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c index 2116358827ea9..9853214352e51 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c @@ -880,9 +880,9 @@ static int umsch_mm_suspend(struct amdgpu_ip_block *ip_block) return umsch_mm_hw_fini(adev); } -static int umsch_mm_resume(void *handle) +static int umsch_mm_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return umsch_mm_hw_init(adev); } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c index fb3fb7c652ae1..78400ae5dfed7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c @@ -762,12 +762,12 @@ static int amdgpu_vkms_suspend(struct amdgpu_ip_block *ip_block) return amdgpu_vkms_hw_fini(adev); } -static int amdgpu_vkms_resume(void *handle) +static int amdgpu_vkms_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; - r = amdgpu_vkms_hw_init(handle); + r = amdgpu_vkms_hw_init(adev); if (r) return r; return drm_mode_config_helper_resume(adev_to_drm(adev)); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c index dc3da75732fcf..fb6cefdba88e7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c @@ -443,9 +443,9 @@ static int vpe_suspend(struct amdgpu_ip_block *ip_block) return vpe_hw_fini(adev); } -static int vpe_resume(void *handle) +static int vpe_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return vpe_hw_init(adev); } diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c index 9e60001d1b8d9..c06dbb43989d5 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik.c +++ b/drivers/gpu/drm/amd/amdgpu/cik.c @@ -2160,9 +2160,9 @@ static int cik_common_suspend(struct amdgpu_ip_block *ip_block) return cik_common_hw_fini(adev); } -static int cik_common_resume(void *handle) +static int cik_common_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return cik_common_hw_init(adev); } diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c index fa87e51fdb4c1..0e9265d40bfb8 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c @@ -344,9 +344,9 @@ static int cik_ih_suspend(struct amdgpu_ip_block *ip_block) return cik_ih_hw_fini(adev); } -static int cik_ih_resume(void *handle) +static int cik_ih_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return cik_ih_hw_init(adev); } diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c index 4d8c3b4283719..ce72d44d75f0a 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c @@ -1018,11 +1018,11 @@ static int cik_sdma_suspend(struct amdgpu_ip_block *ip_block) return cik_sdma_hw_fini(adev); } -static int cik_sdma_resume(void *handle) +static int cik_sdma_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; - cik_sdma_soft_reset(handle); + cik_sdma_soft_reset(ip_block); return cik_sdma_hw_init(adev); } diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c index 4a2a3a4f80ef9..1c89edded7cb4 100644 --- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c @@ -340,9 +340,9 @@ static int cz_ih_suspend(struct amdgpu_ip_block *ip_block) return cz_ih_hw_fini(adev); } -static int cz_ih_resume(void *handle) +static int cz_ih_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return cz_ih_hw_init(adev); } diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index 6305be9104363..48148bb6ab8a6 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -2932,15 +2932,15 @@ static int dce_v10_0_suspend(struct amdgpu_ip_block *ip_block) return dce_v10_0_hw_fini(adev); } -static int dce_v10_0_resume(void *handle) +static int dce_v10_0_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int ret; amdgpu_atombios_encoder_set_backlight_level_to_reg(adev, adev->mode_info.bl_level); - ret = dce_v10_0_hw_init(handle); + ret = dce_v10_0_hw_init(adev); /* turn on the BL */ if (adev->mode_info.bl_encoder) { diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index d460a6e06594a..ddf84c37cc7f6 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -3070,15 +3070,15 @@ static int dce_v11_0_suspend(struct amdgpu_ip_block *ip_block) return dce_v11_0_hw_fini(adev); } -static int dce_v11_0_resume(void *handle) +static int dce_v11_0_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int ret; amdgpu_atombios_encoder_set_backlight_level_to_reg(adev, adev->mode_info.bl_level); - ret = dce_v11_0_hw_init(handle); + ret = dce_v11_0_hw_init(adev); /* turn on the BL */ if (adev->mode_info.bl_encoder) { diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c index fb0bd39558521..190fd0d9ad520 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c @@ -2827,15 +2827,15 @@ static int dce_v6_0_suspend(struct amdgpu_ip_block *ip_block) return dce_v6_0_hw_fini(adev); } -static int dce_v6_0_resume(void *handle) +static int dce_v6_0_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int ret; amdgpu_atombios_encoder_set_backlight_level_to_reg(adev, adev->mode_info.bl_level); - ret = dce_v6_0_hw_init(handle); + ret = dce_v6_0_hw_init(adev); /* turn on the BL */ if (adev->mode_info.bl_encoder) { diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index a42e39240d6ed..ec5c97c668ebf 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -2849,15 +2849,15 @@ static int dce_v8_0_suspend(struct amdgpu_ip_block *ip_block) return dce_v8_0_hw_fini(adev); } -static int dce_v8_0_resume(void *handle) +static int dce_v8_0_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int ret; amdgpu_atombios_encoder_set_backlight_level_to_reg(adev, adev->mode_info.bl_level); - ret = dce_v8_0_hw_init(handle); + ret = dce_v8_0_hw_init(adev); /* turn on the BL */ if (adev->mode_info.bl_encoder) { diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index dcb759dca167b..f0ed5d45acb41 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -7471,9 +7471,9 @@ static int gfx_v10_0_suspend(struct amdgpu_ip_block *ip_block) return gfx_v10_0_hw_fini(adev); } -static int gfx_v10_0_resume(void *handle) +static int gfx_v10_0_resume(struct amdgpu_ip_block *ip_block) { - return gfx_v10_0_hw_init(handle); + return gfx_v10_0_hw_init(ip_block->adev); } static bool gfx_v10_0_is_idle(void *handle) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index 99dea7ab78b18..1421ebb49ff83 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -4712,9 +4712,9 @@ static int gfx_v11_0_suspend(struct amdgpu_ip_block *ip_block) return gfx_v11_0_hw_fini(adev); } -static int gfx_v11_0_resume(void *handle) +static int gfx_v11_0_resume(struct amdgpu_ip_block *ip_block) { - return gfx_v11_0_hw_init(handle); + return gfx_v11_0_hw_init(ip_block->adev); } static bool gfx_v11_0_is_idle(void *handle) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c index 6e1a9b8407b95..2011d869a978d 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c @@ -3650,9 +3650,9 @@ static int gfx_v12_0_suspend(struct amdgpu_ip_block *ip_block) return gfx_v12_0_hw_fini(adev); } -static int gfx_v12_0_resume(void *handle) +static int gfx_v12_0_resume(struct amdgpu_ip_block *ip_block) { - return gfx_v12_0_hw_init(handle); + return gfx_v12_0_hw_init(ip_block->adev); } static bool gfx_v12_0_is_idle(void *handle) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c index e810e3853d4fd..56c41f1d0c1ef 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c @@ -3160,9 +3160,9 @@ static int gfx_v6_0_suspend(struct amdgpu_ip_block *ip_block) return gfx_v6_0_hw_fini(adev); } -static int gfx_v6_0_resume(void *handle) +static int gfx_v6_0_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return gfx_v6_0_hw_init(adev); } diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index 8bc1315fbe737..63bccbddd0e4a 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -4506,9 +4506,9 @@ static int gfx_v7_0_suspend(struct amdgpu_ip_block *ip_block) return gfx_v7_0_hw_fini(adev); } -static int gfx_v7_0_resume(void *handle) +static int gfx_v7_0_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return gfx_v7_0_hw_init(adev); } diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 278401059fc44..c1ef23b8e44c6 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -4931,9 +4931,9 @@ static int gfx_v8_0_suspend(struct amdgpu_ip_block *ip_block) return gfx_v8_0_hw_fini(adev); } -static int gfx_v8_0_resume(void *handle) +static int gfx_v8_0_resume(struct amdgpu_ip_block *ip_block) { - return gfx_v8_0_hw_init(handle); + return gfx_v8_0_hw_init(ip_block->adev); } static bool gfx_v8_0_check_soft_reset(void *handle) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index d0b11b78fc57b..6226905921684 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -4087,9 +4087,9 @@ static int gfx_v9_0_suspend(struct amdgpu_ip_block *ip_block) return gfx_v9_0_hw_fini(adev); } -static int gfx_v9_0_resume(void *handle) +static int gfx_v9_0_resume(struct amdgpu_ip_block *ip_block) { - return gfx_v9_0_hw_init(handle); + return gfx_v9_0_hw_init(ip_block->adev); } static bool gfx_v9_0_is_idle(void *handle) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index 24a0b2cc50261..9e8af1b8671a4 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -2393,9 +2393,9 @@ static int gfx_v9_4_3_suspend(struct amdgpu_ip_block *ip_block) return gfx_v9_4_3_hw_fini(adev); } -static int gfx_v9_4_3_resume(void *handle) +static int gfx_v9_4_3_resume(struct amdgpu_ip_block *ip_block) { - return gfx_v9_4_3_hw_init(handle); + return gfx_v9_4_3_hw_init(ip_block->adev); } static bool gfx_v9_4_3_is_idle(void *handle) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c index 44679f737f9e6..02f751cb3c577 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c @@ -1060,10 +1060,10 @@ static int gmc_v10_0_suspend(struct amdgpu_ip_block *ip_block) return 0; } -static int gmc_v10_0_resume(void *handle) +static int gmc_v10_0_resume(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; r = gmc_v10_0_hw_init(adev); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c index fdf2f0b52d72b..06d95ecb155e2 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c @@ -968,10 +968,10 @@ static int gmc_v11_0_suspend(struct amdgpu_ip_block *ip_block) return 0; } -static int gmc_v11_0_resume(void *handle) +static int gmc_v11_0_resume(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; r = gmc_v11_0_hw_init(adev); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c index e0d758be5a5ac..00dbcc0230481 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c @@ -937,10 +937,10 @@ static int gmc_v12_0_suspend(struct amdgpu_ip_block *ip_block) return 0; } -static int gmc_v12_0_resume(void *handle) +static int gmc_v12_0_resume(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; r = gmc_v12_0_hw_init(adev); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c index 2c9ac638f7d64..5398fdfd5ab3d 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c @@ -943,10 +943,10 @@ static int gmc_v6_0_suspend(struct amdgpu_ip_block *ip_block) return 0; } -static int gmc_v6_0_resume(void *handle) +static int gmc_v6_0_resume(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; r = gmc_v6_0_hw_init(adev); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c index a8488d4b17e5d..b262bde89d558 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c @@ -1119,10 +1119,10 @@ static int gmc_v7_0_suspend(struct amdgpu_ip_block *ip_block) return 0; } -static int gmc_v7_0_resume(void *handle) +static int gmc_v7_0_resume(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; r = gmc_v7_0_hw_init(adev); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index 48583a928202c..67ec690e68eec 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -1255,10 +1255,10 @@ static int gmc_v8_0_suspend(struct amdgpu_ip_block *ip_block) return 0; } -static int gmc_v8_0_resume(void *handle) +static int gmc_v8_0_resume(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; r = gmc_v8_0_hw_init(adev); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index ba46a4f9f51c3..e5eb4755762c2 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -2441,10 +2441,10 @@ static int gmc_v9_0_suspend(struct amdgpu_ip_block *ip_block) return gmc_v9_0_hw_fini(adev); } -static int gmc_v9_0_resume(void *handle) +static int gmc_v9_0_resume(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; r = gmc_v9_0_hw_init(adev); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c index 484f6f8a02c98..651861e3bc24e 100644 --- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c @@ -334,9 +334,9 @@ static int iceland_ih_suspend(struct amdgpu_ip_block *ip_block) return iceland_ih_hw_fini(adev); } -static int iceland_ih_resume(void *handle) +static int iceland_ih_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return iceland_ih_hw_init(adev); } diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c index 037dae06526f7..5fa5459ff8f0b 100644 --- a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c @@ -651,9 +651,9 @@ static int ih_v6_0_suspend(struct amdgpu_ip_block *ip_block) return ih_v6_0_hw_fini(adev); } -static int ih_v6_0_resume(void *handle) +static int ih_v6_0_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return ih_v6_0_hw_init(adev); } diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c index 76201782bddf7..e70277abed2a4 100644 --- a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c +++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c @@ -630,9 +630,9 @@ static int ih_v6_1_suspend(struct amdgpu_ip_block *ip_block) return ih_v6_1_hw_fini(adev); } -static int ih_v6_1_resume(void *handle) +static int ih_v6_1_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return ih_v6_1_hw_init(adev); } diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c index b453cd722ba9c..e767648593a63 100644 --- a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c @@ -620,9 +620,9 @@ static int ih_v7_0_suspend(struct amdgpu_ip_block *ip_block) return ih_v7_0_hw_fini(adev); } -static int ih_v7_0_resume(void *handle) +static int ih_v7_0_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return ih_v7_0_hw_init(adev); } diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c index cc0460621ed1e..84f6c446bf199 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c @@ -187,10 +187,10 @@ static int jpeg_v2_0_suspend(struct amdgpu_ip_block *ip_block) * * Resume firmware and hw init JPEG block */ -static int jpeg_v2_0_resume(void *handle) +static int jpeg_v2_0_resume(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; r = amdgpu_jpeg_resume(adev); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c index 642acf969f62b..8af78c2da1bd8 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c @@ -256,9 +256,9 @@ static int jpeg_v2_5_suspend(struct amdgpu_ip_block *ip_block) * * Resume firmware and hw init JPEG block */ -static int jpeg_v2_5_resume(void *handle) +static int jpeg_v2_5_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; r = amdgpu_jpeg_resume(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c index 551bee67acc12..f7f357a68a639 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c @@ -201,9 +201,9 @@ static int jpeg_v3_0_suspend(struct amdgpu_ip_block *ip_block) * * Resume firmware and hw init JPEG block */ -static int jpeg_v3_0_resume(void *handle) +static int jpeg_v3_0_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; r = amdgpu_jpeg_resume(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c index 703eb51ad8b8f..584e9657a5f0c 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c @@ -235,9 +235,9 @@ static int jpeg_v4_0_suspend(struct amdgpu_ip_block *ip_block) * * Resume firmware and hw init JPEG block */ -static int jpeg_v4_0_resume(void *handle) +static int jpeg_v4_0_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; r = amdgpu_jpeg_resume(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c index a5148ea612c74..8c594f8f4da59 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c @@ -403,9 +403,9 @@ static int jpeg_v4_0_3_suspend(struct amdgpu_ip_block *ip_block) * * Resume firmware and hw init JPEG block */ -static int jpeg_v4_0_3_resume(void *handle) +static int jpeg_v4_0_3_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; r = amdgpu_jpeg_resume(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c index 2cee33c46b97e..bd1c7f8d7541f 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c @@ -262,9 +262,9 @@ static int jpeg_v4_0_5_suspend(struct amdgpu_ip_block *ip_block) * * Resume firmware and hw init JPEG block */ -static int jpeg_v4_0_5_resume(void *handle) +static int jpeg_v4_0_5_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; r = amdgpu_jpeg_resume(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c index 41132830ca750..0c4eb23b085c4 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c @@ -198,9 +198,9 @@ static int jpeg_v5_0_0_suspend(struct amdgpu_ip_block *ip_block) * * Resume firmware and hw init JPEG block */ -static int jpeg_v5_0_0_resume(void *handle) +static int jpeg_v5_0_0_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; r = amdgpu_jpeg_resume(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c index 8b485e97d067f..458d78007285a 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c @@ -1641,10 +1641,10 @@ static int mes_v11_0_suspend(struct amdgpu_ip_block *ip_block) return mes_v11_0_hw_fini(adev); } -static int mes_v11_0_resume(void *handle) +static int mes_v11_0_resume(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; r = mes_v11_0_hw_init(adev); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c index a42e5e5e9a9b1..6fa4fe47c193b 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c @@ -1605,10 +1605,10 @@ static int mes_v12_0_suspend(struct amdgpu_ip_block *ip_block) return mes_v12_0_hw_fini(adev); } -static int mes_v12_0_resume(void *handle) +static int mes_v12_0_resume(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; r = mes_v12_0_hw_init(adev); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c index 800d063b68010..b94cb6739292e 100644 --- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c @@ -625,9 +625,9 @@ static int navi10_ih_suspend(struct amdgpu_ip_block *ip_block) return navi10_ih_hw_fini(adev); } -static int navi10_ih_resume(void *handle) +static int navi10_ih_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return navi10_ih_hw_init(adev); } diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index 31c849a3fb246..fdbf69284266d 100644 --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c @@ -1036,9 +1036,9 @@ static int nv_common_suspend(struct amdgpu_ip_block *ip_block) return nv_common_hw_fini(adev); } -static int nv_common_resume(void *handle) +static int nv_common_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return nv_common_hw_init(adev); } diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c index de98d787f8a9f..1b04c33deb6f2 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c @@ -908,9 +908,9 @@ static int sdma_v2_4_suspend(struct amdgpu_ip_block *ip_block) return sdma_v2_4_hw_fini(adev); } -static int sdma_v2_4_resume(void *handle) +static int sdma_v2_4_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return sdma_v2_4_hw_init(adev); } diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c index abfcd8b6ef2bd..9752bf74625db 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c @@ -1195,9 +1195,9 @@ static int sdma_v3_0_suspend(struct amdgpu_ip_block *ip_block) return sdma_v3_0_hw_fini(adev); } -static int sdma_v3_0_resume(void *handle) +static int sdma_v3_0_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return sdma_v3_0_hw_init(adev); } diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index 3d9e9a8357087..1b096249660aa 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c @@ -2002,9 +2002,9 @@ static int sdma_v4_0_suspend(struct amdgpu_ip_block *ip_block) return sdma_v4_0_hw_fini(adev); } -static int sdma_v4_0_resume(void *handle) +static int sdma_v4_0_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; /* SMU restores SDMA state for us */ if (adev->in_s0ix) { diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c index 89961010d7b43..a134312585111 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c @@ -1518,9 +1518,9 @@ static int sdma_v4_4_2_suspend(struct amdgpu_ip_block *ip_block) return sdma_v4_4_2_hw_fini(adev); } -static int sdma_v4_4_2_resume(void *handle) +static int sdma_v4_4_2_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return sdma_v4_4_2_hw_init(adev); } diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c index 2cf1493e42962..2cecfc3d9c205 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c @@ -1509,9 +1509,9 @@ static int sdma_v5_0_suspend(struct amdgpu_ip_block *ip_block) return sdma_v5_0_hw_fini(adev); } -static int sdma_v5_0_resume(void *handle) +static int sdma_v5_0_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return sdma_v5_0_hw_init(adev); } diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c index 716e66ea70666..9bd4363181840 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c @@ -1404,9 +1404,9 @@ static int sdma_v5_2_suspend(struct amdgpu_ip_block *ip_block) return sdma_v5_2_hw_fini(adev); } -static int sdma_v5_2_resume(void *handle) +static int sdma_v5_2_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return sdma_v5_2_hw_init(adev); } diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c index 96cc696911108..829ff2a5cbd08 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c @@ -1407,9 +1407,9 @@ static int sdma_v6_0_suspend(struct amdgpu_ip_block *ip_block) return sdma_v6_0_hw_fini(adev); } -static int sdma_v6_0_resume(void *handle) +static int sdma_v6_0_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return sdma_v6_0_hw_init(adev); } diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c index 1ea332b2ff887..ebf1ee43c2cb8 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c @@ -1365,9 +1365,9 @@ static int sdma_v7_0_suspend(struct amdgpu_ip_block *ip_block) return sdma_v7_0_hw_fini(adev); } -static int sdma_v7_0_resume(void *handle) +static int sdma_v7_0_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return sdma_v7_0_hw_init(adev); } diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c index 07b360009fbbc..80b1e8e9c0ef2 100644 --- a/drivers/gpu/drm/amd/amdgpu/si.c +++ b/drivers/gpu/drm/amd/amdgpu/si.c @@ -2657,9 +2657,9 @@ static int si_common_suspend(struct amdgpu_ip_block *ip_block) return si_common_hw_fini(adev); } -static int si_common_resume(void *handle) +static int si_common_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return si_common_hw_init(adev); } diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c index e67ed0059cc8f..24d32410d5ff8 100644 --- a/drivers/gpu/drm/amd/amdgpu/si_dma.c +++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c @@ -540,9 +540,9 @@ static int si_dma_suspend(struct amdgpu_ip_block *ip_block) return si_dma_hw_fini(adev); } -static int si_dma_resume(void *handle) +static int si_dma_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return si_dma_hw_init(adev); } diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c b/drivers/gpu/drm/amd/amdgpu/si_ih.c index b1b5e3c693aa2..ccb3bdb5f67b6 100644 --- a/drivers/gpu/drm/amd/amdgpu/si_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c @@ -209,9 +209,9 @@ static int si_ih_suspend(struct amdgpu_ip_block *ip_block) return si_ih_hw_fini(adev); } -static int si_ih_resume(void *handle) +static int si_ih_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return si_ih_hw_init(adev); } diff --git a/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c b/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c index 979b186801575..2ff6f11bddb66 100644 --- a/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c +++ b/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c @@ -175,7 +175,7 @@ static int sienna_cichlid_mode2_restore_ip(struct amdgpu_device *adev) for (i = 0; i < adev->num_ip_blocks; i++) { if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) { - r = adev->ip_blocks[i].version->funcs->resume(adev); + r = adev->ip_blocks[i].version->funcs->resume(&adev->ip_blocks[i]); if (r) { dev_err(adev->dev, "resume of IP block <%s> failed %d\n", @@ -193,7 +193,7 @@ static int sienna_cichlid_mode2_restore_ip(struct amdgpu_device *adev) adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SDMA)) continue; - r = adev->ip_blocks[i].version->funcs->resume(adev); + r = adev->ip_blocks[i].version->funcs->resume(&adev->ip_blocks[i]); if (r) { dev_err(adev->dev, "resume of IP block <%s> failed %d\n", diff --git a/drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.c b/drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.c index 7c097f35bca6f..71a2770e2a31a 100644 --- a/drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.c +++ b/drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.c @@ -186,7 +186,7 @@ static int smu_v13_0_10_mode2_restore_ip(struct amdgpu_device *adev) adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SDMA)) continue; - r = adev->ip_blocks[i].version->funcs->resume(adev); + r = adev->ip_blocks[i].version->funcs->resume(&adev->ip_blocks[i]); if (r) { dev_err(adev->dev, "resume of IP block <%s> failed %d\n", diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index 4ba8e80c4b866..20fe9fffc58f3 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -1325,9 +1325,9 @@ static int soc15_common_suspend(struct amdgpu_ip_block *ip_block) return soc15_common_hw_fini(adev); } -static int soc15_common_resume(void *handle) +static int soc15_common_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (soc15_need_reset_on_resume(adev)) { dev_info(adev->dev, "S3 suspend abort case, let's reset ASIC.\n"); diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c index 3ef5435aef40f..36f9fe9689a85 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc21.c +++ b/drivers/gpu/drm/amd/amdgpu/soc21.c @@ -917,9 +917,9 @@ static bool soc21_need_reset_on_resume(struct amdgpu_device *adev) return false; } -static int soc21_common_resume(void *handle) +static int soc21_common_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (soc21_need_reset_on_resume(adev)) { dev_info(adev->dev, "S3 suspend aborted, resetting..."); diff --git a/drivers/gpu/drm/amd/amdgpu/soc24.c b/drivers/gpu/drm/amd/amdgpu/soc24.c index 41f9664755aaf..e6d57c61f9c36 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc24.c +++ b/drivers/gpu/drm/amd/amdgpu/soc24.c @@ -519,9 +519,9 @@ static int soc24_common_suspend(struct amdgpu_ip_block *ip_block) return soc24_common_hw_fini(adev); } -static int soc24_common_resume(void *handle) +static int soc24_common_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return soc24_common_hw_init(adev); } diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c index 67b44b5000156..f641e97737df8 100644 --- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c @@ -352,9 +352,9 @@ static int tonga_ih_suspend(struct amdgpu_ip_block *ip_block) return tonga_ih_hw_fini(adev); } -static int tonga_ih_resume(void *handle) +static int tonga_ih_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return tonga_ih_hw_init(adev); } diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c index 6c9e0c9f84a9a..b21a869096881 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c @@ -747,10 +747,10 @@ static int uvd_v3_1_suspend(struct amdgpu_ip_block *ip_block) return amdgpu_uvd_suspend(adev); } -static int uvd_v3_1_resume(void *handle) +static int uvd_v3_1_resume(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; r = amdgpu_uvd_resume(adev); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c index c1712e1a1698c..99bad362f7c15 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c @@ -261,10 +261,10 @@ static int uvd_v4_2_suspend(struct amdgpu_ip_block *ip_block) return amdgpu_uvd_suspend(adev); } -static int uvd_v4_2_resume(void *handle) +static int uvd_v4_2_resume(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; r = amdgpu_uvd_resume(adev); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c index 95e8418805040..3eb46b748f57a 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c @@ -259,10 +259,10 @@ static int uvd_v5_0_suspend(struct amdgpu_ip_block *ip_block) return amdgpu_uvd_suspend(adev); } -static int uvd_v5_0_resume(void *handle) +static int uvd_v5_0_resume(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; r = amdgpu_uvd_resume(adev); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c index 82d9617b71f1e..5f9d9b118bf91 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c @@ -583,10 +583,10 @@ static int uvd_v6_0_suspend(struct amdgpu_ip_block *ip_block) return amdgpu_uvd_suspend(adev); } -static int uvd_v6_0_resume(void *handle) +static int uvd_v6_0_resume(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; r = amdgpu_uvd_resume(adev); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c index 6229b48d31ce4..c6ab0b9c3172f 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c @@ -651,10 +651,10 @@ static int uvd_v7_0_suspend(struct amdgpu_ip_block *ip_block) return amdgpu_uvd_suspend(adev); } -static int uvd_v7_0_resume(void *handle) +static int uvd_v7_0_resume(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; r = amdgpu_uvd_resume(adev); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c index 357930179996e..4adea66dcfade 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c @@ -526,10 +526,10 @@ static int vce_v2_0_suspend(struct amdgpu_ip_block *ip_block) return amdgpu_vce_suspend(adev); } -static int vce_v2_0_resume(void *handle) +static int vce_v2_0_resume(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; r = amdgpu_vce_resume(adev); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c index 771eadb2d8055..cc7a300eefcb0 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c @@ -540,10 +540,10 @@ static int vce_v3_0_suspend(struct amdgpu_ip_block *ip_block) return amdgpu_vce_suspend(adev); } -static int vce_v3_0_resume(void *handle) +static int vce_v3_0_resume(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; r = amdgpu_vce_resume(adev); if (r) @@ -726,7 +726,7 @@ static int vce_v3_0_post_soft_reset(void *handle) mdelay(5); - return vce_v3_0_resume(adev); + return vce_v3_0_resume(ip_block); } static int vce_v3_0_set_interrupt_state(struct amdgpu_device *adev, diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c index 75eb27b5f5e4e..0b9681032e223 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c @@ -606,9 +606,9 @@ static int vce_v4_0_suspend(struct amdgpu_ip_block *ip_block) return amdgpu_vce_suspend(adev); } -static int vce_v4_0_resume(void *handle) +static int vce_v4_0_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r, idx; if (adev->vce.vcpu_bo == NULL) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index 6a3909f3ee13f..ac275ee30ba0b 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c @@ -322,10 +322,10 @@ static int vcn_v1_0_suspend(struct amdgpu_ip_block *ip_block) * * Resume firmware and hw init VCN block */ -static int vcn_v1_0_resume(void *handle) +static int vcn_v1_0_resume(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; r = amdgpu_vcn_resume(adev); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c index 660e541399427..a2030d037502c 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c @@ -351,10 +351,10 @@ static int vcn_v2_0_suspend(struct amdgpu_ip_block *ip_block) * * Resume firmware and hw init VCN block */ -static int vcn_v2_0_resume(void *handle) +static int vcn_v2_0_resume(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; r = amdgpu_vcn_resume(adev); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c index 072e060c9d6e8..cc7418de94748 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c @@ -436,10 +436,10 @@ static int vcn_v2_5_suspend(struct amdgpu_ip_block *ip_block) * * Resume firmware and hw init VCN block */ -static int vcn_v2_5_resume(void *handle) +static int vcn_v2_5_resume(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; r = amdgpu_vcn_resume(adev); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c index 0d6294faaf0bc..977380a524f4a 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c @@ -468,10 +468,10 @@ static int vcn_v3_0_suspend(struct amdgpu_ip_block *ip_block) * * Resume firmware and hw init VCN block */ -static int vcn_v3_0_resume(void *handle) +static int vcn_v3_0_resume(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; r = amdgpu_vcn_resume(adev); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c index 0a0b077af901d..606d765b0023b 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c @@ -397,10 +397,10 @@ static int vcn_v4_0_suspend(struct amdgpu_ip_block *ip_block) * * Resume firmware and hw init VCN block */ -static int vcn_v4_0_resume(void *handle) +static int vcn_v4_0_resume(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; r = amdgpu_vcn_resume(adev); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c index 424ffa1327c4b..16a1995d5d315 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c @@ -352,9 +352,9 @@ static int vcn_v4_0_3_suspend(struct amdgpu_ip_block *ip_block) * * Resume firmware and hw init VCN block */ -static int vcn_v4_0_3_resume(void *handle) +static int vcn_v4_0_3_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; r = amdgpu_vcn_resume(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c index e2be515304d5a..02b1433f46f51 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c @@ -345,10 +345,10 @@ static int vcn_v4_0_5_suspend(struct amdgpu_ip_block *ip_block) * * Resume firmware and hw init VCN block */ -static int vcn_v4_0_5_resume(void *handle) +static int vcn_v4_0_5_resume(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; r = amdgpu_vcn_resume(adev); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c index 648bbe967ecbb..b00c8ac4b7691 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c @@ -309,10 +309,10 @@ static int vcn_v5_0_0_suspend(struct amdgpu_ip_block *ip_block) * * Resume firmware and hw init VCN block */ -static int vcn_v5_0_0_resume(void *handle) +static int vcn_v5_0_0_resume(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; r = amdgpu_vcn_resume(adev); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c index dcc961ebaee2c..e3d7ed7f79619 100644 --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c @@ -557,9 +557,9 @@ static int vega10_ih_suspend(struct amdgpu_ip_block *ip_block) return vega10_ih_hw_fini(adev); } -static int vega10_ih_resume(void *handle) +static int vega10_ih_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return vega10_ih_hw_init(adev); } diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c index 740ffef017cbe..5f0cd522dc06d 100644 --- a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c @@ -623,9 +623,9 @@ static int vega20_ih_suspend(struct amdgpu_ip_block *ip_block) return vega20_ih_hw_fini(adev); } -static int vega20_ih_resume(void *handle) +static int vega20_ih_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return vega20_ih_hw_init(adev); } diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index 7b3f850b131c2..a1380f6700fd4 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/drivers/gpu/drm/amd/amdgpu/vi.c @@ -1738,9 +1738,9 @@ static int vi_common_suspend(struct amdgpu_ip_block *ip_block) return vi_common_hw_fini(adev); } -static int vi_common_resume(void *handle) +static int vi_common_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return vi_common_hw_init(adev); } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 6431a3ba48861..db88a7bae38be 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -3159,9 +3159,9 @@ static void dm_gpureset_commit_state(struct dc_state *dc_state, kfree(bundle); } -static int dm_resume(void *handle) +static int dm_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = handle; + struct amdgpu_device *adev = ip_block->adev; struct drm_device *ddev = adev_to_drm(adev); struct amdgpu_display_manager *dm = &adev->dm; struct amdgpu_dm_connector *aconnector; diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h index be3c8d58e1104..a7dcf0b183cc6 100644 --- a/drivers/gpu/drm/amd/include/amd_shared.h +++ b/drivers/gpu/drm/amd/include/amd_shared.h @@ -389,7 +389,7 @@ struct amd_ip_funcs { void (*late_fini)(struct amdgpu_ip_block *ip_block); int (*prepare_suspend)(struct amdgpu_ip_block *ip_block); int (*suspend)(struct amdgpu_ip_block *ip_block); - int (*resume)(void *handle); + int (*resume)(struct amdgpu_ip_block *ip_block); bool (*is_idle)(void *handle); int (*wait_for_idle)(struct amdgpu_ip_block *ip_block); bool (*check_soft_reset)(struct amdgpu_ip_block *ip_block); diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c index ab4e920819241..1ef029e1c7cf5 100644 --- a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c @@ -3076,10 +3076,10 @@ static int kv_dpm_suspend(struct amdgpu_ip_block *ip_block) return 0; } -static int kv_dpm_resume(void *handle) +static int kv_dpm_resume(struct amdgpu_ip_block *ip_block) { int ret; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (adev->pm.dpm_enabled) { /* asic init will reset to the boot state */ diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c index 99818b138ae37..283c954d10a5c 100644 --- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c @@ -7818,10 +7818,10 @@ static int si_dpm_suspend(struct amdgpu_ip_block *ip_block) return 0; } -static int si_dpm_resume(void *handle) +static int si_dpm_resume(struct amdgpu_ip_block *ip_block) { int ret; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (adev->pm.dpm_enabled) { /* asic init will reset to the boot state */ diff --git a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c index 5bea27d864fe7..9db399b5e2fbb 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c +++ b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c @@ -271,9 +271,9 @@ static int pp_suspend(struct amdgpu_ip_block *ip_block) return hwmgr_suspend(hwmgr); } -static int pp_resume(void *handle) +static int pp_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = handle; + struct amdgpu_device *adev = ip_block->adev; struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; return hwmgr_resume(hwmgr); diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index fbc274203cc6f..4f46034600743 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -2104,10 +2104,10 @@ static int smu_suspend(struct amdgpu_ip_block *ip_block) return 0; } -static int smu_resume(void *handle) +static int smu_resume(struct amdgpu_ip_block *ip_block) { int ret; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; struct smu_context *smu = adev->powerplay.pp_handle; if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev)) From 802795f9452c5a0dd0651f86e2d7b496ef8d2022 Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Tue, 1 Oct 2024 11:35:14 +0530 Subject: [PATCH 1726/1868] drm/amdgpu: update the handle ptr in hw_init MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Update the *handle to amdgpu_ip_block ptr for all functions pointers of hw_init. Also update the ip_block ptr where ever needed as there were cyclic dependency of hw_init on resume. Signed-off-by: Sunil Khatri Reviewed-by: Christian König Change-Id: Ib361f39c00be546c5c19b54640be50fffd71eb2e (cherry picked from commit 43f6302db1b46d9c9d354431736636c864862636) --- drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 10 ++-------- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 14 ++++++------- drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c | 8 +++----- drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 9 ++++----- drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c | 8 +++----- drivers/gpu/drm/amd/amdgpu/cik.c | 8 +++----- drivers/gpu/drm/amd/amdgpu/cik_ih.c | 8 +++----- drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 8 +++----- drivers/gpu/drm/amd/amdgpu/cz_ih.c | 8 +++----- drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 8 +++----- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 8 +++----- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 9 ++++----- drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 9 ++++----- drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c | 9 ++++----- drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 9 ++++----- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 9 ++++----- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 9 ++++----- drivers/gpu/drm/amd/amdgpu/iceland_ih.c | 8 +++----- drivers/gpu/drm/amd/amdgpu/ih_v6_0.c | 8 +++----- drivers/gpu/drm/amd/amdgpu/ih_v6_1.c | 8 +++----- drivers/gpu/drm/amd/amdgpu/ih_v7_0.c | 8 +++----- drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c | 9 ++++----- drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c | 9 ++++----- drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c | 9 ++++----- drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c | 9 ++++----- drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 9 ++++----- drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c | 9 ++++----- drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c | 9 ++++----- drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 20 ++++++++++++------- drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 20 ++++++++++++------- drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 8 +++----- drivers/gpu/drm/amd/amdgpu/nv.c | 8 +++----- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 8 +++----- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 8 +++----- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 8 +++----- drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 8 +++----- drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 8 +++----- drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 8 +++----- drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c | 8 +++----- drivers/gpu/drm/amd/amdgpu/si.c | 8 +++----- drivers/gpu/drm/amd/amdgpu/si_dma.c | 8 +++----- drivers/gpu/drm/amd/amdgpu/si_ih.c | 8 +++----- drivers/gpu/drm/amd/amdgpu/soc15.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/soc21.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/soc24.c | 8 +++----- drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 10 ++++------ drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c | 9 ++++----- drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 9 ++++----- drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 9 ++++----- drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 9 ++++----- drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 9 ++++----- drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 9 ++++----- drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 9 ++++----- drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 9 ++++----- drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 9 ++++----- drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 9 ++++----- drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 9 ++++----- drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 9 ++++----- drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 9 ++++----- drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 9 ++++----- drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 9 ++++----- drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 10 +++------- drivers/gpu/drm/amd/amdgpu/vega20_ih.c | 8 +++----- drivers/gpu/drm/amd/amdgpu/vi.c | 8 +++----- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++-- drivers/gpu/drm/amd/include/amd_shared.h | 10 +++++----- drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c | 4 ++-- drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 4 ++-- .../gpu/drm/amd/pm/powerplay/amd_powerplay.c | 7 +++---- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 12 +++++++---- 85 files changed, 310 insertions(+), 390 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c index d3dda5527cc48..a20b3dc02c8a2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c @@ -225,7 +225,7 @@ static const struct dmi_system_id acp_quirk_table[] = { * @handle: handle used to pass amdgpu_device pointer * */ -static int acp_hw_init(void *handle) +static int acp_hw_init(struct amdgpu_ip_block *ip_block) { int r; u64 acp_base; @@ -233,13 +233,7 @@ static int acp_hw_init(void *handle) u32 count = 0; struct i2s_platform_data *i2s_pdata = NULL; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; - - const struct amdgpu_ip_block *ip_block = - amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_ACP); - - if (!ip_block) - return -EINVAL; + struct amdgpu_device *adev = ip_block->adev; r = amd_acp_hw_init(adev->acp.cgs_device, ip_block->version->major, ip_block->version->minor); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 5b2e6dffd1630..c2d36f99c4ccb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -2705,7 +2705,7 @@ static int amdgpu_device_ip_hw_init_phase1(struct amdgpu_device *adev) if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || (amdgpu_sriov_vf(adev) && (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP)) || adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH) { - r = adev->ip_blocks[i].version->funcs->hw_init(adev); + r = adev->ip_blocks[i].version->funcs->hw_init(&adev->ip_blocks[i]); if (r) { DRM_ERROR("hw_init of IP block <%s> failed %d\n", adev->ip_blocks[i].version->funcs->name, r); @@ -2730,7 +2730,7 @@ static int amdgpu_device_ip_hw_init_phase2(struct amdgpu_device *adev) if (!amdgpu_ip_member_of_hwini( adev, adev->ip_blocks[i].version->type)) continue; - r = adev->ip_blocks[i].version->funcs->hw_init(adev); + r = adev->ip_blocks[i].version->funcs->hw_init(&adev->ip_blocks[i]); if (r) { DRM_ERROR("hw_init of IP block <%s> failed %d\n", adev->ip_blocks[i].version->funcs->name, r); @@ -2772,7 +2772,7 @@ static int amdgpu_device_fw_loading(struct amdgpu_device *adev) return r; } } else { - r = adev->ip_blocks[i].version->funcs->hw_init(adev); + r = adev->ip_blocks[i].version->funcs->hw_init(&adev->ip_blocks[i]); if (r) { DRM_ERROR("hw_init of IP block <%s> failed %d\n", adev->ip_blocks[i].version->funcs->name, r); @@ -2886,7 +2886,7 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev) if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON) { /* need to do common hw init early so everything is set up for gmc */ - r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev); + r = adev->ip_blocks[i].version->funcs->hw_init(&adev->ip_blocks[i]); if (r) { DRM_ERROR("hw_init %d failed %d\n", i, r); goto init_failed; @@ -2903,7 +2903,7 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev) DRM_ERROR("amdgpu_mem_scratch_init failed %d\n", r); goto init_failed; } - r = adev->ip_blocks[i].version->funcs->hw_init((void *)adev); + r = adev->ip_blocks[i].version->funcs->hw_init(&adev->ip_blocks[i]); if (r) { DRM_ERROR("hw_init %d failed %d\n", i, r); goto init_failed; @@ -3647,7 +3647,7 @@ static int amdgpu_device_ip_reinit_early_sriov(struct amdgpu_device *adev) !block->status.valid) continue; - r = block->version->funcs->hw_init(adev); + r = block->version->funcs->hw_init(&adev->ip_blocks[i]); DRM_INFO("RE-INIT-early: %s %s\n", block->version->funcs->name, r?"failed":"succeeded"); if (r) return r; @@ -3689,7 +3689,7 @@ static int amdgpu_device_ip_reinit_late_sriov(struct amdgpu_device *adev) if (block->version->type == AMD_IP_BLOCK_TYPE_SMC) r = block->version->funcs->resume(&adev->ip_blocks[i]); else - r = block->version->funcs->hw_init(adev); + r = block->version->funcs->hw_init(&adev->ip_blocks[i]); DRM_INFO("RE-INIT-late: %s %s\n", block->version->funcs->name, r?"failed":"succeeded"); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c index e2a5e84925013..9a2d8d344ae60 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c @@ -49,9 +49,9 @@ static int isp_sw_fini(void *handle) * @handle: handle for amdgpu_device pointer * */ -static int isp_hw_init(void *handle) +static int isp_hw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; struct amdgpu_isp *isp = &adev->isp; const struct amdgpu_ip_block *ip_block = diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 9ffb3629cf417..7026380fb7ab3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -2973,10 +2973,10 @@ static int psp_load_fw(struct amdgpu_device *adev) return ret; } -static int psp_hw_init(void *handle) +static int psp_hw_init(struct amdgpu_ip_block *ip_block) { int ret; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; mutex_lock(&adev->firmware.mutex); /* diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c index 9853214352e51..9f56e61816b80 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c @@ -839,9 +839,9 @@ static int umsch_mm_sw_fini(void *handle) return 0; } -static int umsch_mm_hw_init(void *handle) +static int umsch_mm_hw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; r = umsch_mm_load_microcode(&adev->umsch_mm); @@ -882,9 +882,7 @@ static int umsch_mm_suspend(struct amdgpu_ip_block *ip_block) static int umsch_mm_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - return umsch_mm_hw_init(adev); + return umsch_mm_hw_init(ip_block); } void amdgpu_umsch_fwlog_init(struct amdgpu_umsch_mm *umsch_mm) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c index 78400ae5dfed7..b7022481d8a5f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c @@ -701,9 +701,9 @@ static int amdgpu_vkms_sw_fini(void *handle) return 0; } -static int amdgpu_vkms_hw_init(void *handle) +static int amdgpu_vkms_hw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; switch (adev->asic_type) { #ifdef CONFIG_DRM_AMDGPU_SI @@ -764,13 +764,12 @@ static int amdgpu_vkms_suspend(struct amdgpu_ip_block *ip_block) static int amdgpu_vkms_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; int r; - r = amdgpu_vkms_hw_init(adev); + r = amdgpu_vkms_hw_init(ip_block); if (r) return r; - return drm_mode_config_helper_resume(adev_to_drm(adev)); + return drm_mode_config_helper_resume(adev_to_drm(ip_block->adev)); } static bool amdgpu_vkms_is_idle(void *handle) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c index fb6cefdba88e7..8b4a0d1649d97 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c @@ -398,9 +398,9 @@ static int vpe_sw_fini(void *handle) return 0; } -static int vpe_hw_init(void *handle) +static int vpe_hw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; struct amdgpu_vpe *vpe = &adev->vpe; int ret; @@ -445,9 +445,7 @@ static int vpe_suspend(struct amdgpu_ip_block *ip_block) static int vpe_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - return vpe_hw_init(adev); + return vpe_hw_init(ip_block); } static void vpe_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count) diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c index c06dbb43989d5..998768cb04174 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik.c +++ b/drivers/gpu/drm/amd/amdgpu/cik.c @@ -2134,9 +2134,9 @@ static int cik_common_sw_fini(void *handle) return 0; } -static int cik_common_hw_init(void *handle) +static int cik_common_hw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; /* move the golden regs per IP block */ cik_init_golden_registers(adev); @@ -2162,9 +2162,7 @@ static int cik_common_suspend(struct amdgpu_ip_block *ip_block) static int cik_common_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - return cik_common_hw_init(adev); + return cik_common_hw_init(ip_block); } static bool cik_common_is_idle(void *handle) diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c index 0e9265d40bfb8..f367523e0468c 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c @@ -321,9 +321,9 @@ static int cik_ih_sw_fini(void *handle) return 0; } -static int cik_ih_hw_init(void *handle) +static int cik_ih_hw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return cik_ih_irq_init(adev); } @@ -346,9 +346,7 @@ static int cik_ih_suspend(struct amdgpu_ip_block *ip_block) static int cik_ih_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - return cik_ih_hw_init(adev); + return cik_ih_hw_init(ip_block); } static bool cik_ih_is_idle(void *handle) diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c index ce72d44d75f0a..b95bae54b0130 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c @@ -989,10 +989,10 @@ static int cik_sdma_sw_fini(void *handle) return 0; } -static int cik_sdma_hw_init(void *handle) +static int cik_sdma_hw_init(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; r = cik_sdma_start(adev); if (r) @@ -1020,11 +1020,9 @@ static int cik_sdma_suspend(struct amdgpu_ip_block *ip_block) static int cik_sdma_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - cik_sdma_soft_reset(ip_block); - return cik_sdma_hw_init(adev); + return cik_sdma_hw_init(ip_block); } static bool cik_sdma_is_idle(void *handle) diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c index 1c89edded7cb4..a060d77924c5e 100644 --- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c @@ -312,10 +312,10 @@ static int cz_ih_sw_fini(void *handle) return 0; } -static int cz_ih_hw_init(void *handle) +static int cz_ih_hw_init(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; r = cz_ih_irq_init(adev); if (r) @@ -342,9 +342,7 @@ static int cz_ih_suspend(struct amdgpu_ip_block *ip_block) static int cz_ih_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - return cz_ih_hw_init(adev); + return cz_ih_hw_init(ip_block); } static bool cz_ih_is_idle(void *handle) diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index 48148bb6ab8a6..abab9e5fdf5a7 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -2874,10 +2874,10 @@ static int dce_v10_0_sw_fini(void *handle) return 0; } -static int dce_v10_0_hw_init(void *handle) +static int dce_v10_0_hw_init(struct amdgpu_ip_block *ip_block) { int i; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; dce_v10_0_init_golden_registers(adev); @@ -2940,7 +2940,7 @@ static int dce_v10_0_resume(struct amdgpu_ip_block *ip_block) amdgpu_atombios_encoder_set_backlight_level_to_reg(adev, adev->mode_info.bl_level); - ret = dce_v10_0_hw_init(adev); + ret = dce_v10_0_hw_init(ip_block); /* turn on the BL */ if (adev->mode_info.bl_encoder) { diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index ddf84c37cc7f6..70a20a03390d1 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -3001,10 +3001,10 @@ static int dce_v11_0_sw_fini(void *handle) return 0; } -static int dce_v11_0_hw_init(void *handle) +static int dce_v11_0_hw_init(struct amdgpu_ip_block *ip_block) { int i; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; dce_v11_0_init_golden_registers(adev); @@ -3078,7 +3078,7 @@ static int dce_v11_0_resume(struct amdgpu_ip_block *ip_block) amdgpu_atombios_encoder_set_backlight_level_to_reg(adev, adev->mode_info.bl_level); - ret = dce_v11_0_hw_init(adev); + ret = dce_v11_0_hw_init(ip_block); /* turn on the BL */ if (adev->mode_info.bl_encoder) { diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c index 190fd0d9ad520..549f18729b428 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c @@ -2772,10 +2772,10 @@ static int dce_v6_0_sw_fini(void *handle) return 0; } -static int dce_v6_0_hw_init(void *handle) +static int dce_v6_0_hw_init(struct amdgpu_ip_block *ip_block) { int i; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; /* disable vga render */ dce_v6_0_set_vga_render_state(adev, false); @@ -2835,7 +2835,7 @@ static int dce_v6_0_resume(struct amdgpu_ip_block *ip_block) amdgpu_atombios_encoder_set_backlight_level_to_reg(adev, adev->mode_info.bl_level); - ret = dce_v6_0_hw_init(adev); + ret = dce_v6_0_hw_init(ip_block); /* turn on the BL */ if (adev->mode_info.bl_encoder) { diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index ec5c97c668ebf..e24503e5fbd4e 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -2793,10 +2793,10 @@ static int dce_v8_0_sw_fini(void *handle) return 0; } -static int dce_v8_0_hw_init(void *handle) +static int dce_v8_0_hw_init(struct amdgpu_ip_block *ip_block) { int i; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; /* disable vga render */ dce_v8_0_set_vga_render_state(adev, false); @@ -2857,7 +2857,7 @@ static int dce_v8_0_resume(struct amdgpu_ip_block *ip_block) amdgpu_atombios_encoder_set_backlight_level_to_reg(adev, adev->mode_info.bl_level); - ret = dce_v8_0_hw_init(adev); + ret = dce_v8_0_hw_init(ip_block); /* turn on the BL */ if (adev->mode_info.bl_encoder) { diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index f0ed5d45acb41..18efa05bfdf6b 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -7373,10 +7373,10 @@ static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev) WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data); } -static int gfx_v10_0_hw_init(void *handle) +static int gfx_v10_0_hw_init(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (!amdgpu_emu_mode) gfx_v10_0_init_golden_registers(adev); @@ -7473,7 +7473,7 @@ static int gfx_v10_0_suspend(struct amdgpu_ip_block *ip_block) static int gfx_v10_0_resume(struct amdgpu_ip_block *ip_block) { - return gfx_v10_0_hw_init(ip_block->adev); + return gfx_v10_0_hw_init(ip_block); } static bool gfx_v10_0_is_idle(void *handle) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index 1421ebb49ff83..ae9acdb9906a1 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -4570,10 +4570,10 @@ static void gfx_v11_0_disable_gpa_mode(struct amdgpu_device *adev) WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data); } -static int gfx_v11_0_hw_init(void *handle) +static int gfx_v11_0_hw_init(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { if (adev->gfx.imu.funcs) { @@ -4714,7 +4714,7 @@ static int gfx_v11_0_suspend(struct amdgpu_ip_block *ip_block) static int gfx_v11_0_resume(struct amdgpu_ip_block *ip_block) { - return gfx_v11_0_hw_init(ip_block->adev); + return gfx_v11_0_hw_init(ip_block); } static bool gfx_v11_0_is_idle(void *handle) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c index 2011d869a978d..eecc7f20be8ac 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c @@ -3513,10 +3513,10 @@ static void gfx_v12_0_init_golden_registers(struct amdgpu_device *adev) } } -static int gfx_v12_0_hw_init(void *handle) +static int gfx_v12_0_hw_init(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) { @@ -3652,7 +3652,7 @@ static int gfx_v12_0_suspend(struct amdgpu_ip_block *ip_block) static int gfx_v12_0_resume(struct amdgpu_ip_block *ip_block) { - return gfx_v12_0_hw_init(ip_block->adev); + return gfx_v12_0_hw_init(ip_block); } static bool gfx_v12_0_is_idle(void *handle) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c index 56c41f1d0c1ef..337f2fc398763 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c @@ -3122,10 +3122,10 @@ static int gfx_v6_0_sw_fini(void *handle) return 0; } -static int gfx_v6_0_hw_init(void *handle) +static int gfx_v6_0_hw_init(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; gfx_v6_0_constants_init(adev); @@ -3162,9 +3162,7 @@ static int gfx_v6_0_suspend(struct amdgpu_ip_block *ip_block) static int gfx_v6_0_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - return gfx_v6_0_hw_init(adev); + return gfx_v6_0_hw_init(ip_block); } static bool gfx_v6_0_is_idle(void *handle) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index 63bccbddd0e4a..b5ea673b2f7ab 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -4465,10 +4465,10 @@ static int gfx_v7_0_sw_fini(void *handle) return 0; } -static int gfx_v7_0_hw_init(void *handle) +static int gfx_v7_0_hw_init(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; gfx_v7_0_constants_init(adev); @@ -4508,9 +4508,7 @@ static int gfx_v7_0_suspend(struct amdgpu_ip_block *ip_block) static int gfx_v7_0_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - return gfx_v7_0_hw_init(adev); + return gfx_v7_0_hw_init(ip_block); } static bool gfx_v7_0_is_idle(void *handle) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index c1ef23b8e44c6..e855f1b69a387 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -4789,10 +4789,10 @@ static void gfx_v8_0_cp_enable(struct amdgpu_device *adev, bool enable) gfx_v8_0_cp_compute_enable(adev, enable); } -static int gfx_v8_0_hw_init(void *handle) +static int gfx_v8_0_hw_init(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; gfx_v8_0_init_golden_registers(adev); gfx_v8_0_constants_init(adev); @@ -4933,7 +4933,7 @@ static int gfx_v8_0_suspend(struct amdgpu_ip_block *ip_block) static int gfx_v8_0_resume(struct amdgpu_ip_block *ip_block) { - return gfx_v8_0_hw_init(ip_block->adev); + return gfx_v8_0_hw_init(ip_block); } static bool gfx_v8_0_check_soft_reset(void *handle) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 6226905921684..e49ea97e571c8 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -3998,10 +3998,10 @@ static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable) gfx_v9_0_cp_compute_enable(adev, enable); } -static int gfx_v9_0_hw_init(void *handle) +static int gfx_v9_0_hw_init(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; amdgpu_gfx_cleaner_shader_init(adev, adev->gfx.cleaner_shader_size, adev->gfx.cleaner_shader_ptr); @@ -4089,7 +4089,7 @@ static int gfx_v9_0_suspend(struct amdgpu_ip_block *ip_block) static int gfx_v9_0_resume(struct amdgpu_ip_block *ip_block) { - return gfx_v9_0_hw_init(ip_block->adev); + return gfx_v9_0_hw_init(ip_block); } static bool gfx_v9_0_is_idle(void *handle) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index 9e8af1b8671a4..7dcd6312364ce 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -2345,10 +2345,10 @@ static void gfx_v9_4_3_xcc_fini(struct amdgpu_device *adev, int xcc_id) gfx_v9_4_3_xcc_cp_compute_enable(adev, false, xcc_id); } -static int gfx_v9_4_3_hw_init(void *handle) +static int gfx_v9_4_3_hw_init(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; amdgpu_gfx_cleaner_shader_init(adev, adev->gfx.cleaner_shader_size, adev->gfx.cleaner_shader_ptr); @@ -2395,7 +2395,7 @@ static int gfx_v9_4_3_suspend(struct amdgpu_ip_block *ip_block) static int gfx_v9_4_3_resume(struct amdgpu_ip_block *ip_block) { - return gfx_v9_4_3_hw_init(ip_block->adev); + return gfx_v9_4_3_hw_init(ip_block); } static bool gfx_v9_4_3_is_idle(void *handle) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c index 02f751cb3c577..8be5c12ef83cc 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c @@ -983,9 +983,9 @@ static int gmc_v10_0_gart_enable(struct amdgpu_device *adev) return 0; } -static int gmc_v10_0_hw_init(void *handle) +static int gmc_v10_0_hw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; adev->gmc.flush_pasid_uses_kiq = !amdgpu_emu_mode; @@ -1063,13 +1063,12 @@ static int gmc_v10_0_suspend(struct amdgpu_ip_block *ip_block) static int gmc_v10_0_resume(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = ip_block->adev; - r = gmc_v10_0_hw_init(adev); + r = gmc_v10_0_hw_init(ip_block); if (r) return r; - amdgpu_vmid_reset_all(adev); + amdgpu_vmid_reset_all(ip_block->adev); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c index 06d95ecb155e2..68c1f59d59338 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c @@ -906,9 +906,9 @@ static int gmc_v11_0_gart_enable(struct amdgpu_device *adev) return 0; } -static int gmc_v11_0_hw_init(void *handle) +static int gmc_v11_0_hw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; adev->gmc.flush_pasid_uses_kiq = !amdgpu_emu_mode; @@ -971,13 +971,12 @@ static int gmc_v11_0_suspend(struct amdgpu_ip_block *ip_block) static int gmc_v11_0_resume(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = ip_block->adev; - r = gmc_v11_0_hw_init(adev); + r = gmc_v11_0_hw_init(ip_block); if (r) return r; - amdgpu_vmid_reset_all(adev); + amdgpu_vmid_reset_all(ip_block->adev); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c index 00dbcc0230481..3672b4443f84b 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c @@ -877,10 +877,10 @@ static int gmc_v12_0_gart_enable(struct amdgpu_device *adev) return 0; } -static int gmc_v12_0_hw_init(void *handle) +static int gmc_v12_0_hw_init(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; /* The sequence of these two function calls matters.*/ gmc_v12_0_init_golden_registers(adev); @@ -940,13 +940,12 @@ static int gmc_v12_0_suspend(struct amdgpu_ip_block *ip_block) static int gmc_v12_0_resume(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = ip_block->adev; - r = gmc_v12_0_hw_init(adev); + r = gmc_v12_0_hw_init(ip_block); if (r) return r; - amdgpu_vmid_reset_all(adev); + amdgpu_vmid_reset_all(ip_block->adev); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c index 5398fdfd5ab3d..e4ea4e34d4e3a 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c @@ -899,10 +899,10 @@ static int gmc_v6_0_sw_fini(void *handle) return 0; } -static int gmc_v6_0_hw_init(void *handle) +static int gmc_v6_0_hw_init(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; gmc_v6_0_mc_program(adev); @@ -948,7 +948,7 @@ static int gmc_v6_0_resume(struct amdgpu_ip_block *ip_block) int r; struct amdgpu_device *adev = ip_block->adev; - r = gmc_v6_0_hw_init(adev); + r = gmc_v6_0_hw_init(ip_block); if (r) return r; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c index b262bde89d558..7da3b73c3653a 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c @@ -1073,10 +1073,10 @@ static int gmc_v7_0_sw_fini(void *handle) return 0; } -static int gmc_v7_0_hw_init(void *handle) +static int gmc_v7_0_hw_init(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; gmc_v7_0_init_golden_registers(adev); @@ -1122,13 +1122,12 @@ static int gmc_v7_0_suspend(struct amdgpu_ip_block *ip_block) static int gmc_v7_0_resume(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = ip_block->adev; - r = gmc_v7_0_hw_init(adev); + r = gmc_v7_0_hw_init(ip_block); if (r) return r; - amdgpu_vmid_reset_all(adev); + amdgpu_vmid_reset_all(ip_block->adev); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index 67ec690e68eec..8688c7a53cb79 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -1201,10 +1201,10 @@ static int gmc_v8_0_sw_fini(void *handle) return 0; } -static int gmc_v8_0_hw_init(void *handle) +static int gmc_v8_0_hw_init(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; gmc_v8_0_init_golden_registers(adev); @@ -1258,13 +1258,12 @@ static int gmc_v8_0_suspend(struct amdgpu_ip_block *ip_block) static int gmc_v8_0_resume(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = ip_block->adev; - r = gmc_v8_0_hw_init(adev); + r = gmc_v8_0_hw_init(ip_block); if (r) return r; - amdgpu_vmid_reset_all(adev); + amdgpu_vmid_reset_all(ip_block->adev); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index e5eb4755762c2..d39066d5adb49 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -2314,9 +2314,9 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) return 0; } -static int gmc_v9_0_hw_init(void *handle) +static int gmc_v9_0_hw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; bool value; int i, r; @@ -2444,13 +2444,12 @@ static int gmc_v9_0_suspend(struct amdgpu_ip_block *ip_block) static int gmc_v9_0_resume(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = ip_block->adev; - r = gmc_v9_0_hw_init(adev); + r = gmc_v9_0_hw_init(ip_block); if (r) return r; - amdgpu_vmid_reset_all(adev); + amdgpu_vmid_reset_all(ip_block->adev); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c index 651861e3bc24e..3902202c7acb8 100644 --- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c @@ -311,9 +311,9 @@ static int iceland_ih_sw_fini(void *handle) return 0; } -static int iceland_ih_hw_init(void *handle) +static int iceland_ih_hw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return iceland_ih_irq_init(adev); } @@ -336,9 +336,7 @@ static int iceland_ih_suspend(struct amdgpu_ip_block *ip_block) static int iceland_ih_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - return iceland_ih_hw_init(adev); + return iceland_ih_hw_init(ip_block); } static bool iceland_ih_is_idle(void *handle) diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c index 5fa5459ff8f0b..8649c6525bfa2 100644 --- a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c @@ -623,10 +623,10 @@ static int ih_v6_0_sw_fini(void *handle) return 0; } -static int ih_v6_0_hw_init(void *handle) +static int ih_v6_0_hw_init(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; r = ih_v6_0_irq_init(adev); if (r) @@ -653,9 +653,7 @@ static int ih_v6_0_suspend(struct amdgpu_ip_block *ip_block) static int ih_v6_0_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - return ih_v6_0_hw_init(adev); + return ih_v6_0_hw_init(ip_block); } static bool ih_v6_0_is_idle(void *handle) diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c index e70277abed2a4..b42b43d4b6971 100644 --- a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c +++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c @@ -602,10 +602,10 @@ static int ih_v6_1_sw_fini(void *handle) return 0; } -static int ih_v6_1_hw_init(void *handle) +static int ih_v6_1_hw_init(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; r = ih_v6_1_irq_init(adev); if (r) @@ -632,9 +632,7 @@ static int ih_v6_1_suspend(struct amdgpu_ip_block *ip_block) static int ih_v6_1_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - return ih_v6_1_hw_init(adev); + return ih_v6_1_hw_init(ip_block); } static bool ih_v6_1_is_idle(void *handle) diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c index e767648593a63..76b136f001f47 100644 --- a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c @@ -592,10 +592,10 @@ static int ih_v7_0_sw_fini(void *handle) return 0; } -static int ih_v7_0_hw_init(void *handle) +static int ih_v7_0_hw_init(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; r = ih_v7_0_irq_init(adev); if (r) @@ -622,9 +622,7 @@ static int ih_v7_0_suspend(struct amdgpu_ip_block *ip_block) static int ih_v7_0_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - return ih_v7_0_hw_init(adev); + return ih_v7_0_hw_init(ip_block); } static bool ih_v7_0_is_idle(void *handle) diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c index 84f6c446bf199..4a3832e28d5ec 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c @@ -128,9 +128,9 @@ static int jpeg_v2_0_sw_fini(void *handle) * @handle: amdgpu_device pointer * */ -static int jpeg_v2_0_hw_init(void *handle) +static int jpeg_v2_0_hw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec; adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, @@ -190,13 +190,12 @@ static int jpeg_v2_0_suspend(struct amdgpu_ip_block *ip_block) static int jpeg_v2_0_resume(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = ip_block->adev; - r = amdgpu_jpeg_resume(adev); + r = amdgpu_jpeg_resume(ip_block->adev); if (r) return r; - r = jpeg_v2_0_hw_init(adev); + r = jpeg_v2_0_hw_init(ip_block); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c index 8af78c2da1bd8..ec3533114daf2 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c @@ -177,9 +177,9 @@ static int jpeg_v2_5_sw_fini(void *handle) * @handle: amdgpu_device pointer * */ -static int jpeg_v2_5_hw_init(void *handle) +static int jpeg_v2_5_hw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; struct amdgpu_ring *ring; int i, r; @@ -258,14 +258,13 @@ static int jpeg_v2_5_suspend(struct amdgpu_ip_block *ip_block) */ static int jpeg_v2_5_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; int r; - r = amdgpu_jpeg_resume(adev); + r = amdgpu_jpeg_resume(ip_block->adev); if (r) return r; - r = jpeg_v2_5_hw_init(adev); + r = jpeg_v2_5_hw_init(ip_block); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c index f7f357a68a639..8b9c0f15a3905 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c @@ -142,9 +142,9 @@ static int jpeg_v3_0_sw_fini(void *handle) * @handle: amdgpu_device pointer * */ -static int jpeg_v3_0_hw_init(void *handle) +static int jpeg_v3_0_hw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec; adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, @@ -203,14 +203,13 @@ static int jpeg_v3_0_suspend(struct amdgpu_ip_block *ip_block) */ static int jpeg_v3_0_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; int r; - r = amdgpu_jpeg_resume(adev); + r = amdgpu_jpeg_resume(ip_block->adev); if (r) return r; - r = jpeg_v3_0_hw_init(adev); + r = jpeg_v3_0_hw_init(ip_block); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c index 584e9657a5f0c..d997e93dce495 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c @@ -154,9 +154,9 @@ static int jpeg_v4_0_sw_fini(void *handle) * @handle: amdgpu_device pointer * */ -static int jpeg_v4_0_hw_init(void *handle) +static int jpeg_v4_0_hw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec; int r; @@ -237,14 +237,13 @@ static int jpeg_v4_0_suspend(struct amdgpu_ip_block *ip_block) */ static int jpeg_v4_0_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; int r; - r = amdgpu_jpeg_resume(adev); + r = amdgpu_jpeg_resume(ip_block->adev); if (r) return r; - r = jpeg_v4_0_hw_init(adev); + r = jpeg_v4_0_hw_init(ip_block); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c index 8c594f8f4da59..88d5ec7441032 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c @@ -302,9 +302,9 @@ static int jpeg_v4_0_3_start_sriov(struct amdgpu_device *adev) * @handle: amdgpu_device pointer * */ -static int jpeg_v4_0_3_hw_init(void *handle) +static int jpeg_v4_0_3_hw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; struct amdgpu_ring *ring; int i, j, r, jpeg_inst; @@ -405,14 +405,13 @@ static int jpeg_v4_0_3_suspend(struct amdgpu_ip_block *ip_block) */ static int jpeg_v4_0_3_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; int r; - r = amdgpu_jpeg_resume(adev); + r = amdgpu_jpeg_resume(ip_block->adev); if (r) return r; - r = jpeg_v4_0_3_hw_init(adev); + r = jpeg_v4_0_3_hw_init(ip_block); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c index bd1c7f8d7541f..f59395f78d99b 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c @@ -183,9 +183,9 @@ static int jpeg_v4_0_5_sw_fini(void *handle) * @handle: amdgpu_device pointer * */ -static int jpeg_v4_0_5_hw_init(void *handle) +static int jpeg_v4_0_5_hw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; struct amdgpu_ring *ring; int i, r = 0; @@ -264,14 +264,13 @@ static int jpeg_v4_0_5_suspend(struct amdgpu_ip_block *ip_block) */ static int jpeg_v4_0_5_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; int r; - r = amdgpu_jpeg_resume(adev); + r = amdgpu_jpeg_resume(ip_block->adev); if (r) return r; - r = jpeg_v4_0_5_hw_init(adev); + r = jpeg_v4_0_5_hw_init(ip_block); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c index 0c4eb23b085c4..4a75ef6823541 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c @@ -130,9 +130,9 @@ static int jpeg_v5_0_0_sw_fini(void *handle) * @handle: amdgpu_device pointer * */ -static int jpeg_v5_0_0_hw_init(void *handle) +static int jpeg_v5_0_0_hw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec; int r; @@ -200,14 +200,13 @@ static int jpeg_v5_0_0_suspend(struct amdgpu_ip_block *ip_block) */ static int jpeg_v5_0_0_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; int r; - r = amdgpu_jpeg_resume(adev); + r = amdgpu_jpeg_resume(ip_block->adev); if (r) return r; - r = jpeg_v5_0_0_hw_init(adev); + r = jpeg_v5_0_0_hw_init(ip_block); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c index 458d78007285a..e2ea54cc77f8f 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c @@ -55,7 +55,7 @@ MODULE_FIRMWARE("amdgpu/gc_11_5_1_mes1.bin"); MODULE_FIRMWARE("amdgpu/gc_11_5_2_mes_2.bin"); MODULE_FIRMWARE("amdgpu/gc_11_5_2_mes1.bin"); -static int mes_v11_0_hw_init(void *handle); +static int mes_v11_0_hw_init(struct amdgpu_ip_block *ip_block); static int mes_v11_0_hw_fini(void *handle); static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev); static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev); @@ -1498,6 +1498,7 @@ static void mes_v11_0_kiq_clear(struct amdgpu_device *adev) static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev) { int r = 0; + struct amdgpu_ip_block *ip_block; if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { @@ -1531,7 +1532,13 @@ static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev) adev->mes.enable_legacy_queue_map = false; if (adev->mes.enable_legacy_queue_map) { - r = mes_v11_0_hw_init(adev); + ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_MES); + if (unlikely(!ip_block)) { + dev_err(adev->dev, "Failed to get MES handle\n"); + return -EINVAL; + } + + r = mes_v11_0_hw_init(ip_block); if (r) goto failure; } @@ -1560,10 +1567,10 @@ static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev) return 0; } -static int mes_v11_0_hw_init(void *handle) +static int mes_v11_0_hw_init(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (adev->mes.ring[0].sched.ready) goto out; @@ -1644,13 +1651,12 @@ static int mes_v11_0_suspend(struct amdgpu_ip_block *ip_block) static int mes_v11_0_resume(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = ip_block->adev; - r = mes_v11_0_hw_init(adev); + r = mes_v11_0_hw_init(ip_block); if (r) return r; - return amdgpu_mes_resume(adev); + return amdgpu_mes_resume(ip_block->adev); } static int mes_v11_0_early_init(struct amdgpu_ip_block *ip_block) diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c index 6fa4fe47c193b..4db4d4d1945f2 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c @@ -39,7 +39,7 @@ MODULE_FIRMWARE("amdgpu/gc_12_0_1_mes.bin"); MODULE_FIRMWARE("amdgpu/gc_12_0_1_mes1.bin"); MODULE_FIRMWARE("amdgpu/gc_12_0_1_uni_mes.bin"); -static int mes_v12_0_hw_init(void *handle); +static int mes_v12_0_hw_init(struct amdgpu_ip_block *ip_block); static int mes_v12_0_hw_fini(void *handle); static int mes_v12_0_kiq_hw_init(struct amdgpu_device *adev); static int mes_v12_0_kiq_hw_fini(struct amdgpu_device *adev); @@ -1452,6 +1452,7 @@ static void mes_v12_0_kiq_setting(struct amdgpu_ring *ring) static int mes_v12_0_kiq_hw_init(struct amdgpu_device *adev) { int r = 0; + struct amdgpu_ip_block *ip_block; if (adev->enable_uni_mes) mes_v12_0_kiq_setting(&adev->mes.ring[AMDGPU_MES_KIQ_PIPE]); @@ -1492,7 +1493,13 @@ static int mes_v12_0_kiq_hw_init(struct amdgpu_device *adev) } if (adev->mes.enable_legacy_queue_map) { - r = mes_v12_0_hw_init(adev); + ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_MES); + if (unlikely(!ip_block)) { + dev_err(adev->dev, "Failed to get MES handle\n"); + return -EINVAL; + } + + r = mes_v12_0_hw_init(ip_block); if (r) goto failure; } @@ -1522,10 +1529,10 @@ static int mes_v12_0_kiq_hw_fini(struct amdgpu_device *adev) return 0; } -static int mes_v12_0_hw_init(void *handle) +static int mes_v12_0_hw_init(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (adev->mes.ring[0].sched.ready) goto out; @@ -1608,13 +1615,12 @@ static int mes_v12_0_suspend(struct amdgpu_ip_block *ip_block) static int mes_v12_0_resume(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = ip_block->adev; - r = mes_v12_0_hw_init(adev); + r = mes_v12_0_hw_init(ip_block); if (r) return r; - return amdgpu_mes_resume(adev); + return amdgpu_mes_resume(ip_block->adev); } static int mes_v12_0_early_init(struct amdgpu_ip_block *ip_block) diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c index b94cb6739292e..c52340d27396d 100644 --- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c @@ -602,9 +602,9 @@ static int navi10_ih_sw_fini(void *handle) return 0; } -static int navi10_ih_hw_init(void *handle) +static int navi10_ih_hw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return navi10_ih_irq_init(adev); } @@ -627,9 +627,7 @@ static int navi10_ih_suspend(struct amdgpu_ip_block *ip_block) static int navi10_ih_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - return navi10_ih_hw_init(adev); + return navi10_ih_hw_init(ip_block); } static bool navi10_ih_is_idle(void *handle) diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index fdbf69284266d..53576bfabd07b 100644 --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c @@ -988,9 +988,9 @@ static int nv_common_sw_fini(void *handle) return 0; } -static int nv_common_hw_init(void *handle) +static int nv_common_hw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (adev->nbio.funcs->apply_lc_spc_mode_wa) adev->nbio.funcs->apply_lc_spc_mode_wa(adev); @@ -1038,9 +1038,7 @@ static int nv_common_suspend(struct amdgpu_ip_block *ip_block) static int nv_common_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - return nv_common_hw_init(adev); + return nv_common_hw_init(ip_block); } static bool nv_common_is_idle(void *handle) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c index 1b04c33deb6f2..7303a8f595fad 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c @@ -878,10 +878,10 @@ static int sdma_v2_4_sw_fini(void *handle) return 0; } -static int sdma_v2_4_hw_init(void *handle) +static int sdma_v2_4_hw_init(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; sdma_v2_4_init_golden_registers(adev); @@ -910,9 +910,7 @@ static int sdma_v2_4_suspend(struct amdgpu_ip_block *ip_block) static int sdma_v2_4_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - return sdma_v2_4_hw_init(adev); + return sdma_v2_4_hw_init(ip_block); } static bool sdma_v2_4_is_idle(void *handle) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c index 9752bf74625db..a7d95aa3d8dfd 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c @@ -1164,10 +1164,10 @@ static int sdma_v3_0_sw_fini(void *handle) return 0; } -static int sdma_v3_0_hw_init(void *handle) +static int sdma_v3_0_hw_init(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; sdma_v3_0_init_golden_registers(adev); @@ -1197,9 +1197,7 @@ static int sdma_v3_0_suspend(struct amdgpu_ip_block *ip_block) static int sdma_v3_0_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - return sdma_v3_0_hw_init(adev); + return sdma_v3_0_hw_init(ip_block); } static bool sdma_v3_0_is_idle(void *handle) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index 1b096249660aa..1aefa437ab90e 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c @@ -1952,9 +1952,9 @@ static int sdma_v4_0_sw_fini(void *handle) return 0; } -static int sdma_v4_0_hw_init(void *handle) +static int sdma_v4_0_hw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (adev->flags & AMD_IS_APU) amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, false); @@ -2013,7 +2013,7 @@ static int sdma_v4_0_resume(struct amdgpu_ip_block *ip_block) return 0; } - return sdma_v4_0_hw_init(adev); + return sdma_v4_0_hw_init(ip_block); } static bool sdma_v4_0_is_idle(void *handle) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c index a134312585111..b6eb413a7aad3 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c @@ -1467,10 +1467,10 @@ static int sdma_v4_4_2_sw_fini(void *handle) return 0; } -static int sdma_v4_4_2_hw_init(void *handle) +static int sdma_v4_4_2_hw_init(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; uint32_t inst_mask; inst_mask = GENMASK(adev->sdma.num_instances - 1, 0); @@ -1520,9 +1520,7 @@ static int sdma_v4_4_2_suspend(struct amdgpu_ip_block *ip_block) static int sdma_v4_4_2_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - return sdma_v4_4_2_hw_init(adev); + return sdma_v4_4_2_hw_init(ip_block); } static bool sdma_v4_4_2_is_idle(void *handle) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c index 2cecfc3d9c205..987be5c74929b 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c @@ -1477,10 +1477,10 @@ static int sdma_v5_0_sw_fini(void *handle) return 0; } -static int sdma_v5_0_hw_init(void *handle) +static int sdma_v5_0_hw_init(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; sdma_v5_0_init_golden_registers(adev); @@ -1511,9 +1511,7 @@ static int sdma_v5_0_suspend(struct amdgpu_ip_block *ip_block) static int sdma_v5_0_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - return sdma_v5_0_hw_init(adev); + return sdma_v5_0_hw_init(ip_block); } static bool sdma_v5_0_is_idle(void *handle) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c index 9bd4363181840..692bbdbf42da9 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c @@ -1377,9 +1377,9 @@ static int sdma_v5_2_sw_fini(void *handle) return 0; } -static int sdma_v5_2_hw_init(void *handle) +static int sdma_v5_2_hw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return sdma_v5_2_start(adev); } @@ -1406,9 +1406,7 @@ static int sdma_v5_2_suspend(struct amdgpu_ip_block *ip_block) static int sdma_v5_2_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - return sdma_v5_2_hw_init(adev); + return sdma_v5_2_hw_init(ip_block); } static bool sdma_v5_2_is_idle(void *handle) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c index 829ff2a5cbd08..12bba9eeb651b 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c @@ -1380,9 +1380,9 @@ static int sdma_v6_0_sw_fini(void *handle) return 0; } -static int sdma_v6_0_hw_init(void *handle) +static int sdma_v6_0_hw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return sdma_v6_0_start(adev); } @@ -1409,9 +1409,7 @@ static int sdma_v6_0_suspend(struct amdgpu_ip_block *ip_block) static int sdma_v6_0_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - return sdma_v6_0_hw_init(adev); + return sdma_v6_0_hw_init(ip_block); } static bool sdma_v6_0_is_idle(void *handle) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c index ebf1ee43c2cb8..33860349e4878 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c @@ -1338,9 +1338,9 @@ static int sdma_v7_0_sw_fini(void *handle) return 0; } -static int sdma_v7_0_hw_init(void *handle) +static int sdma_v7_0_hw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return sdma_v7_0_start(adev); } @@ -1367,9 +1367,7 @@ static int sdma_v7_0_suspend(struct amdgpu_ip_block *ip_block) static int sdma_v7_0_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - return sdma_v7_0_hw_init(adev); + return sdma_v7_0_hw_init(ip_block); } static bool sdma_v7_0_is_idle(void *handle) diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c index 80b1e8e9c0ef2..8170831900e0e 100644 --- a/drivers/gpu/drm/amd/amdgpu/si.c +++ b/drivers/gpu/drm/amd/amdgpu/si.c @@ -2633,9 +2633,9 @@ static void si_fix_pci_max_read_req_size(struct amdgpu_device *adev) pcie_set_readrq(adev->pdev, 512); } -static int si_common_hw_init(void *handle) +static int si_common_hw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; si_fix_pci_max_read_req_size(adev); si_init_golden_registers(adev); @@ -2659,9 +2659,7 @@ static int si_common_suspend(struct amdgpu_ip_block *ip_block) static int si_common_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - return si_common_hw_init(adev); + return si_common_hw_init(ip_block); } static bool si_common_is_idle(void *handle) diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c index 24d32410d5ff8..90a0696d3a773 100644 --- a/drivers/gpu/drm/amd/amdgpu/si_dma.c +++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c @@ -517,9 +517,9 @@ static int si_dma_sw_fini(void *handle) return 0; } -static int si_dma_hw_init(void *handle) +static int si_dma_hw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return si_dma_start(adev); } @@ -542,9 +542,7 @@ static int si_dma_suspend(struct amdgpu_ip_block *ip_block) static int si_dma_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - return si_dma_hw_init(adev); + return si_dma_hw_init(ip_block); } static bool si_dma_is_idle(void *handle) diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c b/drivers/gpu/drm/amd/amdgpu/si_ih.c index ccb3bdb5f67b6..68b217d61a850 100644 --- a/drivers/gpu/drm/amd/amdgpu/si_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c @@ -186,9 +186,9 @@ static int si_ih_sw_fini(void *handle) return 0; } -static int si_ih_hw_init(void *handle) +static int si_ih_hw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return si_ih_irq_init(adev); } @@ -211,9 +211,7 @@ static int si_ih_suspend(struct amdgpu_ip_block *ip_block) static int si_ih_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - return si_ih_hw_init(adev); + return si_ih_hw_init(ip_block); } static bool si_ih_is_idle(void *handle) diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index 20fe9fffc58f3..e0f89f5e850d7 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -1255,9 +1255,9 @@ static void soc15_sdma_doorbell_range_init(struct amdgpu_device *adev) } } -static int soc15_common_hw_init(void *handle) +static int soc15_common_hw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; /* enable aspm */ soc15_program_aspm(adev); @@ -1333,7 +1333,7 @@ static int soc15_common_resume(struct amdgpu_ip_block *ip_block) dev_info(adev->dev, "S3 suspend abort case, let's reset ASIC.\n"); soc15_asic_reset(adev); } - return soc15_common_hw_init(adev); + return soc15_common_hw_init(ip_block); } static bool soc15_common_is_idle(void *handle) diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c index 36f9fe9689a85..52b76693a7073 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc21.c +++ b/drivers/gpu/drm/amd/amdgpu/soc21.c @@ -847,9 +847,9 @@ static int soc21_common_sw_fini(void *handle) return 0; } -static int soc21_common_hw_init(void *handle) +static int soc21_common_hw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; /* enable aspm */ soc21_program_aspm(adev); @@ -926,7 +926,7 @@ static int soc21_common_resume(struct amdgpu_ip_block *ip_block) soc21_asic_reset(adev); } - return soc21_common_hw_init(adev); + return soc21_common_hw_init(ip_block); } static bool soc21_common_is_idle(void *handle) diff --git a/drivers/gpu/drm/amd/amdgpu/soc24.c b/drivers/gpu/drm/amd/amdgpu/soc24.c index e6d57c61f9c36..dc4f2536e2c52 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc24.c +++ b/drivers/gpu/drm/amd/amdgpu/soc24.c @@ -470,9 +470,9 @@ static int soc24_common_sw_fini(void *handle) return 0; } -static int soc24_common_hw_init(void *handle) +static int soc24_common_hw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; /* enable aspm */ soc24_program_aspm(adev); @@ -521,9 +521,7 @@ static int soc24_common_suspend(struct amdgpu_ip_block *ip_block) static int soc24_common_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - return soc24_common_hw_init(adev); + return soc24_common_hw_init(ip_block); } static bool soc24_common_is_idle(void *handle) diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c index f641e97737df8..ffbf33f4ea5d0 100644 --- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c @@ -324,10 +324,10 @@ static int tonga_ih_sw_fini(void *handle) return 0; } -static int tonga_ih_hw_init(void *handle) +static int tonga_ih_hw_init(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; r = tonga_ih_irq_init(adev); if (r) @@ -354,9 +354,7 @@ static int tonga_ih_suspend(struct amdgpu_ip_block *ip_block) static int tonga_ih_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - return tonga_ih_hw_init(adev); + return tonga_ih_hw_init(ip_block); } static bool tonga_ih_is_idle(void *handle) @@ -422,7 +420,7 @@ static int tonga_ih_post_soft_reset(void *handle) if (!adev->irq.srbm_soft_reset) return 0; - return tonga_ih_hw_init(adev); + return tonga_ih_hw_init(ip_block); } static int tonga_ih_soft_reset(void *handle) diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c index b21a869096881..128a8339e58a8 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c @@ -625,9 +625,9 @@ static void uvd_v3_1_enable_mgcg(struct amdgpu_device *adev, * * Initialize the hardware, boot up the VCPU and do some testing */ -static int uvd_v3_1_hw_init(void *handle) +static int uvd_v3_1_hw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; struct amdgpu_ring *ring = &adev->uvd.inst->ring; uint32_t tmp; int r; @@ -750,13 +750,12 @@ static int uvd_v3_1_suspend(struct amdgpu_ip_block *ip_block) static int uvd_v3_1_resume(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = ip_block->adev; - r = amdgpu_uvd_resume(adev); + r = amdgpu_uvd_resume(ip_block->adev); if (r) return r; - return uvd_v3_1_hw_init(adev); + return uvd_v3_1_hw_init(ip_block); } static bool uvd_v3_1_is_idle(void *handle) diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c index 99bad362f7c15..64b1dbffed8a4 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c @@ -151,9 +151,9 @@ static void uvd_v4_2_enable_mgcg(struct amdgpu_device *adev, * * Initialize the hardware, boot up the VCPU and do some testing */ -static int uvd_v4_2_hw_init(void *handle) +static int uvd_v4_2_hw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; struct amdgpu_ring *ring = &adev->uvd.inst->ring; uint32_t tmp; int r; @@ -264,13 +264,12 @@ static int uvd_v4_2_suspend(struct amdgpu_ip_block *ip_block) static int uvd_v4_2_resume(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = ip_block->adev; - r = amdgpu_uvd_resume(adev); + r = amdgpu_uvd_resume(ip_block->adev); if (r) return r; - return uvd_v4_2_hw_init(adev); + return uvd_v4_2_hw_init(ip_block); } /** diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c index 3eb46b748f57a..8fa33c74675c3 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c @@ -147,9 +147,9 @@ static int uvd_v5_0_sw_fini(void *handle) * * Initialize the hardware, boot up the VCPU and do some testing */ -static int uvd_v5_0_hw_init(void *handle) +static int uvd_v5_0_hw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; struct amdgpu_ring *ring = &adev->uvd.inst->ring; uint32_t tmp; int r; @@ -262,13 +262,12 @@ static int uvd_v5_0_suspend(struct amdgpu_ip_block *ip_block) static int uvd_v5_0_resume(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = ip_block->adev; - r = amdgpu_uvd_resume(adev); + r = amdgpu_uvd_resume(ip_block->adev); if (r) return r; - return uvd_v5_0_hw_init(adev); + return uvd_v5_0_hw_init(ip_block); } /** diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c index 5f9d9b118bf91..a48f073e1f598 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c @@ -459,9 +459,9 @@ static int uvd_v6_0_sw_fini(void *handle) * * Initialize the hardware, boot up the VCPU and do some testing */ -static int uvd_v6_0_hw_init(void *handle) +static int uvd_v6_0_hw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; struct amdgpu_ring *ring = &adev->uvd.inst->ring; uint32_t tmp; int i, r; @@ -586,13 +586,12 @@ static int uvd_v6_0_suspend(struct amdgpu_ip_block *ip_block) static int uvd_v6_0_resume(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = ip_block->adev; - r = amdgpu_uvd_resume(adev); + r = amdgpu_uvd_resume(ip_block->adev); if (r) return r; - return uvd_v6_0_hw_init(adev); + return uvd_v6_0_hw_init(ip_block); } /** diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c index c6ab0b9c3172f..c7023379dc47b 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c @@ -514,9 +514,9 @@ static int uvd_v7_0_sw_fini(void *handle) * * Initialize the hardware, boot up the VCPU and do some testing */ -static int uvd_v7_0_hw_init(void *handle) +static int uvd_v7_0_hw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; struct amdgpu_ring *ring; uint32_t tmp; int i, j, r; @@ -654,13 +654,12 @@ static int uvd_v7_0_suspend(struct amdgpu_ip_block *ip_block) static int uvd_v7_0_resume(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = ip_block->adev; - r = amdgpu_uvd_resume(adev); + r = amdgpu_uvd_resume(ip_block->adev); if (r) return r; - return uvd_v7_0_hw_init(adev); + return uvd_v7_0_hw_init(ip_block); } /** diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c index 4adea66dcfade..d11782e43824c 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c @@ -462,10 +462,10 @@ static int vce_v2_0_sw_fini(void *handle) return amdgpu_vce_sw_fini(adev); } -static int vce_v2_0_hw_init(void *handle) +static int vce_v2_0_hw_init(struct amdgpu_ip_block *ip_block) { int r, i; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; amdgpu_asic_set_vce_clocks(adev, 10000, 10000); vce_v2_0_enable_mgcg(adev, true, false); @@ -529,13 +529,12 @@ static int vce_v2_0_suspend(struct amdgpu_ip_block *ip_block) static int vce_v2_0_resume(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = ip_block->adev; - r = amdgpu_vce_resume(adev); + r = amdgpu_vce_resume(ip_block->adev); if (r) return r; - return vce_v2_0_hw_init(adev); + return vce_v2_0_hw_init(ip_block); } static int vce_v2_0_soft_reset(void *handle) diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c index cc7a300eefcb0..b4d5467c48da9 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c @@ -465,10 +465,10 @@ static int vce_v3_0_sw_fini(void *handle) return amdgpu_vce_sw_fini(adev); } -static int vce_v3_0_hw_init(void *handle) +static int vce_v3_0_hw_init(struct amdgpu_ip_block *ip_block) { int r, i; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; vce_v3_0_override_vce_clock_gating(adev, true); @@ -543,13 +543,12 @@ static int vce_v3_0_suspend(struct amdgpu_ip_block *ip_block) static int vce_v3_0_resume(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = ip_block->adev; - r = amdgpu_vce_resume(adev); + r = amdgpu_vce_resume(ip_block->adev); if (r) return r; - return vce_v3_0_hw_init(adev); + return vce_v3_0_hw_init(ip_block); } static void vce_v3_0_mc_resume(struct amdgpu_device *adev, int idx) diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c index 0b9681032e223..f23d3a380f127 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c @@ -513,10 +513,10 @@ static int vce_v4_0_sw_fini(void *handle) return amdgpu_vce_sw_fini(adev); } -static int vce_v4_0_hw_init(void *handle) +static int vce_v4_0_hw_init(struct amdgpu_ip_block *ip_block) { int r, i; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (amdgpu_sriov_vf(adev)) r = vce_v4_0_sriov_start(adev); @@ -629,7 +629,7 @@ static int vce_v4_0_resume(struct amdgpu_ip_block *ip_block) return r; } - return vce_v4_0_hw_init(adev); + return vce_v4_0_hw_init(ip_block); } static void vce_v4_0_mc_resume(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index ac275ee30ba0b..d8fe7e409928b 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c @@ -242,9 +242,9 @@ static int vcn_v1_0_sw_fini(void *handle) * * Initialize the hardware, boot up the VCPU and do some testing */ -static int vcn_v1_0_hw_init(void *handle) +static int vcn_v1_0_hw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; int i, r; @@ -325,13 +325,12 @@ static int vcn_v1_0_suspend(struct amdgpu_ip_block *ip_block) static int vcn_v1_0_resume(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = ip_block->adev; - r = amdgpu_vcn_resume(adev); + r = amdgpu_vcn_resume(ip_block->adev); if (r) return r; - r = vcn_v1_0_hw_init(adev); + r = vcn_v1_0_hw_init(ip_block); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c index a2030d037502c..aab28163cb602 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c @@ -272,9 +272,9 @@ static int vcn_v2_0_sw_fini(void *handle) * * Initialize the hardware, boot up the VCPU and do some testing */ -static int vcn_v2_0_hw_init(void *handle) +static int vcn_v2_0_hw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec; int i, r; @@ -354,13 +354,12 @@ static int vcn_v2_0_suspend(struct amdgpu_ip_block *ip_block) static int vcn_v2_0_resume(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = ip_block->adev; - r = amdgpu_vcn_resume(adev); + r = amdgpu_vcn_resume(ip_block->adev); if (r) return r; - r = vcn_v2_0_hw_init(adev); + r = vcn_v2_0_hw_init(ip_block); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c index cc7418de94748..3cfacd8a46796 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c @@ -337,9 +337,9 @@ static int vcn_v2_5_sw_fini(void *handle) * * Initialize the hardware, boot up the VCPU and do some testing */ -static int vcn_v2_5_hw_init(void *handle) +static int vcn_v2_5_hw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; struct amdgpu_ring *ring; int i, j, r = 0; @@ -439,13 +439,12 @@ static int vcn_v2_5_suspend(struct amdgpu_ip_block *ip_block) static int vcn_v2_5_resume(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = ip_block->adev; - r = amdgpu_vcn_resume(adev); + r = amdgpu_vcn_resume(ip_block->adev); if (r) return r; - r = vcn_v2_5_hw_init(adev); + r = vcn_v2_5_hw_init(ip_block); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c index 977380a524f4a..a44404e88e3b1 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c @@ -342,9 +342,9 @@ static int vcn_v3_0_sw_fini(void *handle) * * Initialize the hardware, boot up the VCPU and do some testing */ -static int vcn_v3_0_hw_init(void *handle) +static int vcn_v3_0_hw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; struct amdgpu_ring *ring; int i, j, r; @@ -471,13 +471,12 @@ static int vcn_v3_0_suspend(struct amdgpu_ip_block *ip_block) static int vcn_v3_0_resume(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = ip_block->adev; - r = amdgpu_vcn_resume(adev); + r = amdgpu_vcn_resume(ip_block->adev); if (r) return r; - r = vcn_v3_0_hw_init(adev); + r = vcn_v3_0_hw_init(ip_block); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c index 606d765b0023b..2dd8697de19ef 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c @@ -298,9 +298,9 @@ static int vcn_v4_0_sw_fini(void *handle) * * Initialize the hardware, boot up the VCPU and do some testing */ -static int vcn_v4_0_hw_init(void *handle) +static int vcn_v4_0_hw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; struct amdgpu_ring *ring; int i, r; @@ -400,13 +400,12 @@ static int vcn_v4_0_suspend(struct amdgpu_ip_block *ip_block) static int vcn_v4_0_resume(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = ip_block->adev; - r = amdgpu_vcn_resume(adev); + r = amdgpu_vcn_resume(ip_block->adev); if (r) return r; - r = vcn_v4_0_hw_init(adev); + r = vcn_v4_0_hw_init(ip_block); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c index 16a1995d5d315..36c39c553827c 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c @@ -253,9 +253,9 @@ static int vcn_v4_0_3_sw_fini(void *handle) * * Initialize the hardware, boot up the VCPU and do some testing */ -static int vcn_v4_0_3_hw_init(void *handle) +static int vcn_v4_0_3_hw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; struct amdgpu_ring *ring; int i, r, vcn_inst; @@ -354,14 +354,13 @@ static int vcn_v4_0_3_suspend(struct amdgpu_ip_block *ip_block) */ static int vcn_v4_0_3_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; int r; - r = amdgpu_vcn_resume(adev); + r = amdgpu_vcn_resume(ip_block->adev); if (r) return r; - r = vcn_v4_0_3_hw_init(adev); + r = vcn_v4_0_3_hw_init(ip_block); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c index 02b1433f46f51..13bed4099faf2 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c @@ -265,9 +265,9 @@ static int vcn_v4_0_5_sw_fini(void *handle) * * Initialize the hardware, boot up the VCPU and do some testing */ -static int vcn_v4_0_5_hw_init(void *handle) +static int vcn_v4_0_5_hw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; struct amdgpu_ring *ring; int i, r; @@ -348,13 +348,12 @@ static int vcn_v4_0_5_suspend(struct amdgpu_ip_block *ip_block) static int vcn_v4_0_5_resume(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = ip_block->adev; - r = amdgpu_vcn_resume(adev); + r = amdgpu_vcn_resume(ip_block->adev); if (r) return r; - r = vcn_v4_0_5_hw_init(adev); + r = vcn_v4_0_5_hw_init(ip_block); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c index b00c8ac4b7691..82ff2dc9dc110 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c @@ -229,9 +229,9 @@ static int vcn_v5_0_0_sw_fini(void *handle) * * Initialize the hardware, boot up the VCPU and do some testing */ -static int vcn_v5_0_0_hw_init(void *handle) +static int vcn_v5_0_0_hw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; struct amdgpu_ring *ring; int i, r; @@ -312,13 +312,12 @@ static int vcn_v5_0_0_suspend(struct amdgpu_ip_block *ip_block) static int vcn_v5_0_0_resume(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = ip_block->adev; - r = amdgpu_vcn_resume(adev); + r = amdgpu_vcn_resume(ip_block->adev); if (r) return r; - r = vcn_v5_0_0_hw_init(adev); + r = vcn_v5_0_0_hw_init(ip_block); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c index e3d7ed7f79619..e1952fb7e4b55 100644 --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c @@ -534,11 +534,9 @@ static int vega10_ih_sw_fini(void *handle) return 0; } -static int vega10_ih_hw_init(void *handle) +static int vega10_ih_hw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; - - return vega10_ih_irq_init(adev); + return vega10_ih_irq_init(ip_block->adev); } static int vega10_ih_hw_fini(void *handle) @@ -559,9 +557,7 @@ static int vega10_ih_suspend(struct amdgpu_ip_block *ip_block) static int vega10_ih_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - return vega10_ih_hw_init(adev); + return vega10_ih_hw_init(ip_block); } static bool vega10_ih_is_idle(void *handle) diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c index 5f0cd522dc06d..8a52313f1368c 100644 --- a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c @@ -595,10 +595,10 @@ static int vega20_ih_sw_fini(void *handle) return 0; } -static int vega20_ih_hw_init(void *handle) +static int vega20_ih_hw_init(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; r = vega20_ih_irq_init(adev); if (r) @@ -625,9 +625,7 @@ static int vega20_ih_suspend(struct amdgpu_ip_block *ip_block) static int vega20_ih_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - return vega20_ih_hw_init(adev); + return vega20_ih_hw_init(ip_block); } static bool vega20_ih_is_idle(void *handle) diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index a1380f6700fd4..11d1389a90d17 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/drivers/gpu/drm/amd/amdgpu/vi.c @@ -1704,9 +1704,9 @@ static int vi_common_sw_fini(void *handle) return 0; } -static int vi_common_hw_init(void *handle) +static int vi_common_hw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; /* move the golden regs per IP block */ vi_init_golden_registers(adev); @@ -1740,9 +1740,7 @@ static int vi_common_suspend(struct amdgpu_ip_block *ip_block) static int vi_common_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - return vi_common_hw_init(adev); + return vi_common_hw_init(ip_block); } static bool vi_common_is_idle(void *handle) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index db88a7bae38be..6900161b0737a 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2843,9 +2843,9 @@ static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev) * - Vblank support * - Debug FS entries, if enabled */ -static int dm_hw_init(void *handle) +static int dm_hw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; /* Create DAL display manager */ diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h index a7dcf0b183cc6..ecf60a8d7be5f 100644 --- a/drivers/gpu/drm/amd/include/amd_shared.h +++ b/drivers/gpu/drm/amd/include/amd_shared.h @@ -380,11 +380,11 @@ struct amdgpu_ip_block; struct amd_ip_funcs { char *name; int (*early_init)(struct amdgpu_ip_block *ip_block); - int (*late_init)(void *handle); - int (*sw_init)(void *handle); - int (*sw_fini)(void *handle); - int (*early_fini)(void *handle); - int (*hw_init)(void *handle); + int (*late_init)(struct amdgpu_ip_block *ip_block); + int (*sw_init)(struct amdgpu_ip_block *ip_block); + int (*sw_fini)(struct amdgpu_ip_block *ip_block); + int (*early_fini)(struct amdgpu_ip_block *ip_block); + int (*hw_init)(struct amdgpu_ip_block *ip_block); int (*hw_fini)(void *handle); void (*late_fini)(struct amdgpu_ip_block *ip_block); int (*prepare_suspend)(struct amdgpu_ip_block *ip_block); diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c index 1ef029e1c7cf5..8dc22378c095f 100644 --- a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c @@ -3035,10 +3035,10 @@ static int kv_dpm_sw_fini(void *handle) return 0; } -static int kv_dpm_hw_init(void *handle) +static int kv_dpm_hw_init(struct amdgpu_ip_block *ip_block) { int ret; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (!amdgpu_dpm) return 0; diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c index 283c954d10a5c..2f4044e0e1b1d 100644 --- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c @@ -7776,11 +7776,11 @@ static int si_dpm_sw_fini(void *handle) return 0; } -static int si_dpm_hw_init(void *handle) +static int si_dpm_hw_init(struct amdgpu_ip_block *ip_block) { int ret; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (!amdgpu_dpm) return 0; diff --git a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c index 9db399b5e2fbb..e5ce94cd0850a 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c +++ b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c @@ -159,10 +159,10 @@ static int pp_sw_fini(void *handle) return 0; } -static int pp_hw_init(void *handle) +static int pp_hw_init(struct amdgpu_ip_block *ip_block) { int ret = 0; - struct amdgpu_device *adev = handle; + struct amdgpu_device *adev = ip_block->adev; struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; ret = hwmgr_hw_init(hwmgr); @@ -273,8 +273,7 @@ static int pp_suspend(struct amdgpu_ip_block *ip_block) static int pp_resume(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; + struct pp_hwmgr *hwmgr = ip_block->adev->powerplay.pp_handle; return hwmgr_resume(hwmgr); } diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 4f46034600743..5c8fc5e5cfa84 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -1787,10 +1787,10 @@ static int smu_start_smc_engine(struct smu_context *smu) return ret; } -static int smu_hw_init(void *handle) +static int smu_hw_init(struct amdgpu_ip_block *ip_block) { int ret; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; struct smu_context *smu = adev->powerplay.pp_handle; if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) { @@ -2055,15 +2055,19 @@ static int smu_reset(struct smu_context *smu) struct amdgpu_device *adev = smu->adev; int ret; + ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_SMC); + if (!ip_block) + return -EINVAL; + ret = smu_hw_fini(adev); if (ret) return ret; - ret = smu_hw_init(adev); + ret = smu_hw_init(ip_block); if (ret) return ret; - ret = smu_late_init(adev); + ret = smu_late_init(ip_block); if (ret) return ret; From 5d93ca6a4a6c6545a9bf90ae9043ba877e5c8175 Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Wed, 2 Oct 2024 11:20:58 +0530 Subject: [PATCH 1727/1868] drm/amdgpu: update the handle ptr in hw_fini MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Update the *handle to amdgpu_ip_block ptr for all functions pointers of hw_fini. Also update the ip_block ptr where ever needed as there were cyclic dependency of hw_fini on suspend and some followed clean up. Signed-off-by: Sunil Khatri Reviewed-by: Christian König Change-Id: I1d252ad221b5d04b973df8a3d4614b83d8d2d534 (cherry picked from commit 6a625e3e29f967e09620ce5b5ed7fc7a30df7cec) --- drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 4 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c | 5 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 4 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c | 8 +++--- drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 4 +-- drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c | 6 ++--- drivers/gpu/drm/amd/amdgpu/cik.c | 6 ++--- drivers/gpu/drm/amd/amdgpu/cik_ih.c | 10 +++---- drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 8 +++--- drivers/gpu/drm/amd/amdgpu/cz_ih.c | 10 +++---- drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 6 ++--- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 6 ++--- drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 6 ++--- drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 6 ++--- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 10 +++---- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 8 +++--- drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 8 +++--- drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 8 +++--- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 8 +++--- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 13 +++------ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 8 +++--- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 8 +++--- drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 8 +++--- drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 8 +++--- drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c | 8 +++--- drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 8 +++--- drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 8 +++--- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 8 +++--- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 8 +++--- drivers/gpu/drm/amd/amdgpu/iceland_ih.c | 10 +++---- drivers/gpu/drm/amd/amdgpu/ih_v6_0.c | 10 +++---- drivers/gpu/drm/amd/amdgpu/ih_v6_1.c | 10 +++---- drivers/gpu/drm/amd/amdgpu/ih_v7_0.c | 10 +++---- drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c | 9 +++---- drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c | 9 +++---- drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c | 9 +++---- drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c | 9 +++---- drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 9 +++---- drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c | 9 +++---- drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c | 9 +++---- drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 27 +++++++++---------- drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 25 +++++++++-------- drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 10 +++---- drivers/gpu/drm/amd/amdgpu/nv.c | 8 +++--- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 10 +++---- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 8 +++--- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 6 ++--- drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 6 ++--- drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 8 +++--- drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 8 +++--- drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 8 +++--- drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c | 8 +++--- drivers/gpu/drm/amd/amdgpu/si.c | 6 ++--- drivers/gpu/drm/amd/amdgpu/si_dma.c | 10 +++---- drivers/gpu/drm/amd/amdgpu/si_ih.c | 10 +++---- drivers/gpu/drm/amd/amdgpu/soc15.c | 8 +++--- drivers/gpu/drm/amd/amdgpu/soc21.c | 8 +++--- drivers/gpu/drm/amd/amdgpu/soc24.c | 8 +++--- drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 16 ++++------- drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c | 6 ++--- drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 6 ++--- drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 6 ++--- drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 6 ++--- drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 6 ++--- drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 8 +++--- drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 11 +++----- drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 11 +++----- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 6 ++--- drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 9 +++---- drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 9 +++---- drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 9 +++---- drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 9 +++---- drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 9 +++---- drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 9 +++---- drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 9 +++---- drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 10 +++---- drivers/gpu/drm/amd/amdgpu/vega20_ih.c | 10 +++---- drivers/gpu/drm/amd/amdgpu/vi.c | 8 +++--- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 +-- drivers/gpu/drm/amd/include/amd_shared.h | 2 +- drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c | 4 +-- drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 4 +-- .../gpu/drm/amd/pm/powerplay/amd_powerplay.c | 5 ++-- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 6 ++--- 85 files changed, 278 insertions(+), 425 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c index a20b3dc02c8a2..9cabfb3439631 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c @@ -503,11 +503,11 @@ static int acp_hw_init(struct amdgpu_ip_block *ip_block) * @handle: handle used to pass amdgpu_device pointer * */ -static int acp_hw_fini(void *handle) +static int acp_hw_fini(struct amdgpu_ip_block *ip_block) { u32 val = 0; u32 count = 0; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; /* return early if no ACP */ if (!adev->acp.acp_genpd) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index c2d36f99c4ccb..7ac422935e305 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -3306,7 +3306,7 @@ static void amdgpu_device_smu_fini_early(struct amdgpu_device *adev) if (!adev->ip_blocks[i].status.hw) continue; if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_SMC) { - r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev); + r = adev->ip_blocks[i].version->funcs->hw_fini(&adev->ip_blocks[i]); /* XXX handle errors */ if (r) { DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", @@ -3345,7 +3345,7 @@ static int amdgpu_device_ip_fini_early(struct amdgpu_device *adev) if (!adev->ip_blocks[i].status.hw) continue; - r = adev->ip_blocks[i].version->funcs->hw_fini((void *)adev); + r = adev->ip_blocks[i].version->funcs->hw_fini(&adev->ip_blocks[i]); /* XXX handle errors */ if (r) { DRM_DEBUG("hw_fini of IP block <%s> failed %d\n", diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c index 9a2d8d344ae60..d73318d91acf9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c @@ -72,10 +72,9 @@ static int isp_hw_init(struct amdgpu_ip_block *ip_block) * @handle: handle for amdgpu_device pointer * */ -static int isp_hw_fini(void *handle) +static int isp_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; - struct amdgpu_isp *isp = &adev->isp; + struct amdgpu_isp *isp = &ip_block->adev->isp; if (isp->funcs->hw_fini != NULL) return isp->funcs->hw_fini(isp); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 7026380fb7ab3..6857f9d09826c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -3002,9 +3002,9 @@ static int psp_hw_init(struct amdgpu_ip_block *ip_block) return -EINVAL; } -static int psp_hw_fini(void *handle) +static int psp_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; struct psp_context *psp = &adev->psp; if (psp->ta_fw) { diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c index 9f56e61816b80..c061b0cee7476 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c @@ -857,9 +857,9 @@ static int umsch_mm_hw_init(struct amdgpu_ip_block *ip_block) return 0; } -static int umsch_mm_hw_fini(void *handle) +static int umsch_mm_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; umsch_mm_ring_stop(&adev->umsch_mm); @@ -875,9 +875,7 @@ static int umsch_mm_hw_fini(void *handle) static int umsch_mm_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - return umsch_mm_hw_fini(adev); + return umsch_mm_hw_fini(ip_block); } static int umsch_mm_resume(struct amdgpu_ip_block *ip_block) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c index b7022481d8a5f..c5deb6210fe1c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c @@ -746,7 +746,7 @@ static int amdgpu_vkms_hw_init(struct amdgpu_ip_block *ip_block) return 0; } -static int amdgpu_vkms_hw_fini(void *handle) +static int amdgpu_vkms_hw_fini(struct amdgpu_ip_block *ip_block) { return 0; } @@ -759,7 +759,7 @@ static int amdgpu_vkms_suspend(struct amdgpu_ip_block *ip_block) r = drm_mode_config_helper_suspend(adev_to_drm(adev)); if (r) return r; - return amdgpu_vkms_hw_fini(adev); + return amdgpu_vkms_hw_fini(ip_block); } static int amdgpu_vkms_resume(struct amdgpu_ip_block *ip_block) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c index 8b4a0d1649d97..46c86b284220f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c @@ -421,9 +421,9 @@ static int vpe_hw_init(struct amdgpu_ip_block *ip_block) return 0; } -static int vpe_hw_fini(void *handle) +static int vpe_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; struct amdgpu_vpe *vpe = &adev->vpe; vpe_ring_stop(vpe); @@ -440,7 +440,7 @@ static int vpe_suspend(struct amdgpu_ip_block *ip_block) cancel_delayed_work_sync(&adev->vpe.idle_work); - return vpe_hw_fini(adev); + return vpe_hw_fini(ip_block); } static int vpe_resume(struct amdgpu_ip_block *ip_block) diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c index 998768cb04174..78b47242fd59a 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik.c +++ b/drivers/gpu/drm/amd/amdgpu/cik.c @@ -2148,16 +2148,14 @@ static int cik_common_hw_init(struct amdgpu_ip_block *ip_block) return 0; } -static int cik_common_hw_fini(void *handle) +static int cik_common_hw_fini(struct amdgpu_ip_block *ip_block) { return 0; } static int cik_common_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - return cik_common_hw_fini(adev); + return cik_common_hw_fini(ip_block); } static int cik_common_resume(struct amdgpu_ip_block *ip_block) diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c index f367523e0468c..4e20c6c84dbc5 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c @@ -328,20 +328,16 @@ static int cik_ih_hw_init(struct amdgpu_ip_block *ip_block) return cik_ih_irq_init(adev); } -static int cik_ih_hw_fini(void *handle) +static int cik_ih_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; - - cik_ih_irq_disable(adev); + cik_ih_irq_disable(ip_block->adev); return 0; } static int cik_ih_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - return cik_ih_hw_fini(adev); + return cik_ih_hw_fini(ip_block); } static int cik_ih_resume(struct amdgpu_ip_block *ip_block) diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c index b95bae54b0130..41c3179a6029a 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c @@ -1001,9 +1001,9 @@ static int cik_sdma_hw_init(struct amdgpu_ip_block *ip_block) return r; } -static int cik_sdma_hw_fini(void *handle) +static int cik_sdma_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; cik_ctx_switch_enable(adev, false); cik_sdma_enable(adev, false); @@ -1013,9 +1013,7 @@ static int cik_sdma_hw_fini(void *handle) static int cik_sdma_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - return cik_sdma_hw_fini(adev); + return cik_sdma_hw_fini(ip_block); } static int cik_sdma_resume(struct amdgpu_ip_block *ip_block) diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c index a060d77924c5e..c62a67f8247ff 100644 --- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c @@ -324,20 +324,16 @@ static int cz_ih_hw_init(struct amdgpu_ip_block *ip_block) return 0; } -static int cz_ih_hw_fini(void *handle) +static int cz_ih_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; - - cz_ih_irq_disable(adev); + cz_ih_irq_disable(ip_block->adev); return 0; } static int cz_ih_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - return cz_ih_hw_fini(adev); + return cz_ih_hw_fini(ip_block); } static int cz_ih_resume(struct amdgpu_ip_block *ip_block) diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index abab9e5fdf5a7..6aed24c721590 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -2899,10 +2899,10 @@ static int dce_v10_0_hw_init(struct amdgpu_ip_block *ip_block) return 0; } -static int dce_v10_0_hw_fini(void *handle) +static int dce_v10_0_hw_fini(struct amdgpu_ip_block *ip_block) { int i; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; dce_v10_0_hpd_fini(adev); @@ -2929,7 +2929,7 @@ static int dce_v10_0_suspend(struct amdgpu_ip_block *ip_block) adev->mode_info.bl_level = amdgpu_atombios_encoder_get_backlight_level_from_reg(adev); - return dce_v10_0_hw_fini(adev); + return dce_v10_0_hw_fini(ip_block); } static int dce_v10_0_resume(struct amdgpu_ip_block *ip_block) diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index 70a20a03390d1..a4198f222e8d7 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -3037,10 +3037,10 @@ static int dce_v11_0_hw_init(struct amdgpu_ip_block *ip_block) return 0; } -static int dce_v11_0_hw_fini(void *handle) +static int dce_v11_0_hw_fini(struct amdgpu_ip_block *ip_block) { int i; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; dce_v11_0_hpd_fini(adev); @@ -3067,7 +3067,7 @@ static int dce_v11_0_suspend(struct amdgpu_ip_block *ip_block) adev->mode_info.bl_level = amdgpu_atombios_encoder_get_backlight_level_from_reg(adev); - return dce_v11_0_hw_fini(adev); + return dce_v11_0_hw_fini(ip_block); } static int dce_v11_0_resume(struct amdgpu_ip_block *ip_block) diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c index 549f18729b428..ae36c5d52dca0 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c @@ -2795,10 +2795,10 @@ static int dce_v6_0_hw_init(struct amdgpu_ip_block *ip_block) return 0; } -static int dce_v6_0_hw_fini(void *handle) +static int dce_v6_0_hw_fini(struct amdgpu_ip_block *ip_block) { int i; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; dce_v6_0_hpd_fini(adev); @@ -2824,7 +2824,7 @@ static int dce_v6_0_suspend(struct amdgpu_ip_block *ip_block) adev->mode_info.bl_level = amdgpu_atombios_encoder_get_backlight_level_from_reg(adev); - return dce_v6_0_hw_fini(adev); + return dce_v6_0_hw_fini(ip_block); } static int dce_v6_0_resume(struct amdgpu_ip_block *ip_block) diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index e24503e5fbd4e..23899f8564a40 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -2816,10 +2816,10 @@ static int dce_v8_0_hw_init(struct amdgpu_ip_block *ip_block) return 0; } -static int dce_v8_0_hw_fini(void *handle) +static int dce_v8_0_hw_fini(struct amdgpu_ip_block *ip_block) { int i; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; dce_v8_0_hpd_fini(adev); @@ -2846,7 +2846,7 @@ static int dce_v8_0_suspend(struct amdgpu_ip_block *ip_block) adev->mode_info.bl_level = amdgpu_atombios_encoder_get_backlight_level_from_reg(adev); - return dce_v8_0_hw_fini(adev); + return dce_v8_0_hw_fini(ip_block); } static int dce_v8_0_resume(struct amdgpu_ip_block *ip_block) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 18efa05bfdf6b..fac275a9ed5be 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -7425,9 +7425,9 @@ static int gfx_v10_0_hw_init(struct amdgpu_ip_block *ip_block) return r; } -static int gfx_v10_0_hw_fini(void *handle) +static int gfx_v10_0_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); @@ -7439,7 +7439,7 @@ static int gfx_v10_0_hw_fini(void *handle) * otherwise the gfxoff disallowing will be failed to set. */ if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(10, 3, 1)) - gfx_v10_0_set_powergating_state(handle, AMD_PG_STATE_UNGATE); + gfx_v10_0_set_powergating_state(ip_block->adev, AMD_PG_STATE_UNGATE); if (!adev->no_hw_access) { if (amdgpu_async_gfx_ring) { @@ -7466,9 +7466,7 @@ static int gfx_v10_0_hw_fini(void *handle) static int gfx_v10_0_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - return gfx_v10_0_hw_fini(adev); + return gfx_v10_0_hw_fini(ip_block); } static int gfx_v10_0_resume(struct amdgpu_ip_block *ip_block) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index ae9acdb9906a1..745ed5dc3b362 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -4667,9 +4667,9 @@ static int gfx_v11_0_hw_init(struct amdgpu_ip_block *ip_block) return r; } -static int gfx_v11_0_hw_fini(void *handle) +static int gfx_v11_0_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); @@ -4707,9 +4707,7 @@ static int gfx_v11_0_hw_fini(void *handle) static int gfx_v11_0_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - return gfx_v11_0_hw_fini(adev); + return gfx_v11_0_hw_fini(ip_block); } static int gfx_v11_0_resume(struct amdgpu_ip_block *ip_block) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c index eecc7f20be8ac..e36cdbd052581 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c @@ -3603,9 +3603,9 @@ static int gfx_v12_0_hw_init(struct amdgpu_ip_block *ip_block) return r; } -static int gfx_v12_0_hw_fini(void *handle) +static int gfx_v12_0_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; uint32_t tmp; amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); @@ -3645,9 +3645,7 @@ static int gfx_v12_0_hw_fini(void *handle) static int gfx_v12_0_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - return gfx_v12_0_hw_fini(adev); + return gfx_v12_0_hw_fini(ip_block); } static int gfx_v12_0_resume(struct amdgpu_ip_block *ip_block) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c index 337f2fc398763..62bc6ac2df935 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c @@ -3142,9 +3142,9 @@ static int gfx_v6_0_hw_init(struct amdgpu_ip_block *ip_block) return r; } -static int gfx_v6_0_hw_fini(void *handle) +static int gfx_v6_0_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; gfx_v6_0_cp_enable(adev, false); adev->gfx.rlc.funcs->stop(adev); @@ -3155,9 +3155,7 @@ static int gfx_v6_0_hw_fini(void *handle) static int gfx_v6_0_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - return gfx_v6_0_hw_fini(adev); + return gfx_v6_0_hw_fini(ip_block); } static int gfx_v6_0_resume(struct amdgpu_ip_block *ip_block) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index b5ea673b2f7ab..b7342f290e173 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -4486,9 +4486,9 @@ static int gfx_v7_0_hw_init(struct amdgpu_ip_block *ip_block) return r; } -static int gfx_v7_0_hw_fini(void *handle) +static int gfx_v7_0_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); @@ -4501,9 +4501,7 @@ static int gfx_v7_0_hw_fini(void *handle) static int gfx_v7_0_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - return gfx_v7_0_hw_fini(adev); + return gfx_v7_0_hw_fini(ip_block); } static int gfx_v7_0_resume(struct amdgpu_ip_block *ip_block) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index e855f1b69a387..d0605dd323fee 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -4885,10 +4885,9 @@ static int gfx_v8_0_wait_for_idle(struct amdgpu_ip_block *ip_block) return -ETIMEDOUT; } -static int gfx_v8_0_hw_fini(void *handle) +static int gfx_v8_0_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; - struct amdgpu_ip_block *ip_block; + struct amdgpu_device *adev = ip_block->adev; amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); @@ -4906,10 +4905,6 @@ static int gfx_v8_0_hw_fini(void *handle) return 0; } - ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_GFX); - if (!ip_block) - return -EINVAL; - amdgpu_gfx_rlc_enter_safe_mode(adev, 0); if (!gfx_v8_0_wait_for_idle(ip_block)) gfx_v8_0_cp_enable(adev, false); @@ -4926,9 +4921,7 @@ static int gfx_v8_0_hw_fini(void *handle) static int gfx_v8_0_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - return gfx_v8_0_hw_fini(adev); + return gfx_v8_0_hw_fini(ip_block); } static int gfx_v8_0_resume(struct amdgpu_ip_block *ip_block) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index e49ea97e571c8..c67c2161054c1 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -4027,9 +4027,9 @@ static int gfx_v9_0_hw_init(struct amdgpu_ip_block *ip_block) return r; } -static int gfx_v9_0_hw_fini(void *handle) +static int gfx_v9_0_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX)) amdgpu_irq_put(adev, &adev->gfx.cp_ecc_error_irq, 0); @@ -4082,9 +4082,7 @@ static int gfx_v9_0_hw_fini(void *handle) static int gfx_v9_0_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - return gfx_v9_0_hw_fini(adev); + return gfx_v9_0_hw_fini(ip_block); } static int gfx_v9_0_resume(struct amdgpu_ip_block *ip_block) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index 7dcd6312364ce..fd3126c8f575b 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -2369,9 +2369,9 @@ static int gfx_v9_4_3_hw_init(struct amdgpu_ip_block *ip_block) return r; } -static int gfx_v9_4_3_hw_fini(void *handle) +static int gfx_v9_4_3_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i, num_xcc; amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); @@ -2388,9 +2388,7 @@ static int gfx_v9_4_3_hw_fini(void *handle) static int gfx_v9_4_3_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - return gfx_v9_4_3_hw_fini(adev); + return gfx_v9_4_3_hw_fini(ip_block); } static int gfx_v9_4_3_resume(struct amdgpu_ip_block *ip_block) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c index 8be5c12ef83cc..01ccea2f23815 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c @@ -1030,9 +1030,9 @@ static void gmc_v10_0_gart_disable(struct amdgpu_device *adev) adev->mmhub.funcs->gart_disable(adev); } -static int gmc_v10_0_hw_fini(void *handle) +static int gmc_v10_0_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; gmc_v10_0_gart_disable(adev); @@ -1053,9 +1053,7 @@ static int gmc_v10_0_hw_fini(void *handle) static int gmc_v10_0_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - gmc_v10_0_hw_fini(adev); + gmc_v10_0_hw_fini(ip_block); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c index 68c1f59d59338..7b7055b6f3a41 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c @@ -938,9 +938,9 @@ static void gmc_v11_0_gart_disable(struct amdgpu_device *adev) adev->mmhub.funcs->gart_disable(adev); } -static int gmc_v11_0_hw_fini(void *handle) +static int gmc_v11_0_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (amdgpu_sriov_vf(adev)) { /* full access mode, so don't touch any GMC register */ @@ -961,9 +961,7 @@ static int gmc_v11_0_hw_fini(void *handle) static int gmc_v11_0_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - gmc_v11_0_hw_fini(adev); + gmc_v11_0_hw_fini(ip_block); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c index 3672b4443f84b..676ed1e0fefac 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c @@ -907,9 +907,9 @@ static void gmc_v12_0_gart_disable(struct amdgpu_device *adev) adev->mmhub.funcs->gart_disable(adev); } -static int gmc_v12_0_hw_fini(void *handle) +static int gmc_v12_0_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (amdgpu_sriov_vf(adev)) { /* full access mode, so don't touch any GMC register */ @@ -930,9 +930,7 @@ static int gmc_v12_0_hw_fini(void *handle) static int gmc_v12_0_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - gmc_v12_0_hw_fini(adev); + gmc_v12_0_hw_fini(ip_block); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c index e4ea4e34d4e3a..7ca816e253bf5 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c @@ -924,9 +924,9 @@ static int gmc_v6_0_hw_init(struct amdgpu_ip_block *ip_block) return 0; } -static int gmc_v6_0_hw_fini(void *handle) +static int gmc_v6_0_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); gmc_v6_0_gart_disable(adev); @@ -936,9 +936,7 @@ static int gmc_v6_0_hw_fini(void *handle) static int gmc_v6_0_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - gmc_v6_0_hw_fini(adev); + gmc_v6_0_hw_fini(ip_block); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c index 7da3b73c3653a..da9154ca48043 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c @@ -1100,9 +1100,9 @@ static int gmc_v7_0_hw_init(struct amdgpu_ip_block *ip_block) return 0; } -static int gmc_v7_0_hw_fini(void *handle) +static int gmc_v7_0_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); gmc_v7_0_gart_disable(adev); @@ -1112,9 +1112,7 @@ static int gmc_v7_0_hw_fini(void *handle) static int gmc_v7_0_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - gmc_v7_0_hw_fini(adev); + gmc_v7_0_hw_fini(ip_block); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index 8688c7a53cb79..a2b5accc3fe3d 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -1236,9 +1236,9 @@ static int gmc_v8_0_hw_init(struct amdgpu_ip_block *ip_block) return 0; } -static int gmc_v8_0_hw_fini(void *handle) +static int gmc_v8_0_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); gmc_v8_0_gart_disable(adev); @@ -1248,9 +1248,7 @@ static int gmc_v8_0_hw_fini(void *handle) static int gmc_v8_0_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - gmc_v8_0_hw_fini(adev); + gmc_v8_0_hw_fini(ip_block); return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index d39066d5adb49..4dc7c04f201a3 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -2399,9 +2399,9 @@ static void gmc_v9_0_gart_disable(struct amdgpu_device *adev) adev->mmhub.funcs->gart_disable(adev); } -static int gmc_v9_0_hw_fini(void *handle) +static int gmc_v9_0_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; gmc_v9_0_gart_disable(adev); @@ -2436,9 +2436,7 @@ static int gmc_v9_0_hw_fini(void *handle) static int gmc_v9_0_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - return gmc_v9_0_hw_fini(adev); + return gmc_v9_0_hw_fini(ip_block); } static int gmc_v9_0_resume(struct amdgpu_ip_block *ip_block) diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c index 3902202c7acb8..2122da177acc4 100644 --- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c @@ -318,20 +318,16 @@ static int iceland_ih_hw_init(struct amdgpu_ip_block *ip_block) return iceland_ih_irq_init(adev); } -static int iceland_ih_hw_fini(void *handle) +static int iceland_ih_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; - - iceland_ih_irq_disable(adev); + iceland_ih_irq_disable(ip_block->adev); return 0; } static int iceland_ih_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - return iceland_ih_hw_fini(adev); + return iceland_ih_hw_fini(ip_block); } static int iceland_ih_resume(struct amdgpu_ip_block *ip_block) diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c index 8649c6525bfa2..8666ace8a1cbd 100644 --- a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c @@ -635,20 +635,16 @@ static int ih_v6_0_hw_init(struct amdgpu_ip_block *ip_block) return 0; } -static int ih_v6_0_hw_fini(void *handle) +static int ih_v6_0_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; - - ih_v6_0_irq_disable(adev); + ih_v6_0_irq_disable(ip_block->adev); return 0; } static int ih_v6_0_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - return ih_v6_0_hw_fini(adev); + return ih_v6_0_hw_fini(ip_block); } static int ih_v6_0_resume(struct amdgpu_ip_block *ip_block) diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c index b42b43d4b6971..075e9f02c4a63 100644 --- a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c +++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c @@ -614,20 +614,16 @@ static int ih_v6_1_hw_init(struct amdgpu_ip_block *ip_block) return 0; } -static int ih_v6_1_hw_fini(void *handle) +static int ih_v6_1_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; - - ih_v6_1_irq_disable(adev); + ih_v6_1_irq_disable(ip_block->adev); return 0; } static int ih_v6_1_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - return ih_v6_1_hw_fini(adev); + return ih_v6_1_hw_fini(ip_block); } static int ih_v6_1_resume(struct amdgpu_ip_block *ip_block) diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c index 76b136f001f47..d78053e8dd6c0 100644 --- a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c @@ -604,20 +604,16 @@ static int ih_v7_0_hw_init(struct amdgpu_ip_block *ip_block) return 0; } -static int ih_v7_0_hw_fini(void *handle) +static int ih_v7_0_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; - - ih_v7_0_irq_disable(adev); + ih_v7_0_irq_disable(ip_block->adev); return 0; } static int ih_v7_0_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - return ih_v7_0_hw_fini(adev); + return ih_v7_0_hw_fini(ip_block); } static int ih_v7_0_resume(struct amdgpu_ip_block *ip_block) diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c index 4a3832e28d5ec..34361c6d4c502 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c @@ -146,9 +146,9 @@ static int jpeg_v2_0_hw_init(struct amdgpu_ip_block *ip_block) * * Stop the JPEG block, mark ring as not ready any more */ -static int jpeg_v2_0_hw_fini(void *handle) +static int jpeg_v2_0_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; cancel_delayed_work_sync(&adev->vcn.idle_work); @@ -168,14 +168,13 @@ static int jpeg_v2_0_hw_fini(void *handle) */ static int jpeg_v2_0_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; int r; - r = jpeg_v2_0_hw_fini(adev); + r = jpeg_v2_0_hw_fini(ip_block); if (r) return r; - r = amdgpu_jpeg_suspend(adev); + r = amdgpu_jpeg_suspend(ip_block->adev); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c index ec3533114daf2..5c0e49ae452cf 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c @@ -206,9 +206,9 @@ static int jpeg_v2_5_hw_init(struct amdgpu_ip_block *ip_block) * * Stop the JPEG block, mark ring as not ready any more */ -static int jpeg_v2_5_hw_fini(void *handle) +static int jpeg_v2_5_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i; cancel_delayed_work_sync(&adev->vcn.idle_work); @@ -237,14 +237,13 @@ static int jpeg_v2_5_hw_fini(void *handle) */ static int jpeg_v2_5_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; int r; - r = jpeg_v2_5_hw_fini(adev); + r = jpeg_v2_5_hw_fini(ip_block); if (r) return r; - r = amdgpu_jpeg_suspend(adev); + r = amdgpu_jpeg_suspend(ip_block->adev); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c index 8b9c0f15a3905..23d24db76a76d 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c @@ -160,9 +160,9 @@ static int jpeg_v3_0_hw_init(struct amdgpu_ip_block *ip_block) * * Stop the JPEG block, mark ring as not ready any more */ -static int jpeg_v3_0_hw_fini(void *handle) +static int jpeg_v3_0_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; cancel_delayed_work_sync(&adev->vcn.idle_work); @@ -182,14 +182,13 @@ static int jpeg_v3_0_hw_fini(void *handle) */ static int jpeg_v3_0_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; int r; - r = jpeg_v3_0_hw_fini(adev); + r = jpeg_v3_0_hw_fini(ip_block); if (r) return r; - r = amdgpu_jpeg_suspend(adev); + r = amdgpu_jpeg_suspend(ip_block->adev); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c index d997e93dce495..ad30e3f7578ad 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c @@ -191,9 +191,9 @@ static int jpeg_v4_0_hw_init(struct amdgpu_ip_block *ip_block) * * Stop the JPEG block, mark ring as not ready any more */ -static int jpeg_v4_0_hw_fini(void *handle) +static int jpeg_v4_0_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; cancel_delayed_work_sync(&adev->vcn.idle_work); if (!amdgpu_sriov_vf(adev)) { @@ -216,14 +216,13 @@ static int jpeg_v4_0_hw_fini(void *handle) */ static int jpeg_v4_0_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; int r; - r = jpeg_v4_0_hw_fini(adev); + r = jpeg_v4_0_hw_fini(ip_block); if (r) return r; - r = amdgpu_jpeg_suspend(adev); + r = amdgpu_jpeg_suspend(ip_block->adev); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c index 88d5ec7441032..1940a79db1ce0 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c @@ -362,9 +362,9 @@ static int jpeg_v4_0_3_hw_init(struct amdgpu_ip_block *ip_block) * * Stop the JPEG block, mark ring as not ready any more */ -static int jpeg_v4_0_3_hw_fini(void *handle) +static int jpeg_v4_0_3_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int ret = 0; cancel_delayed_work_sync(&adev->jpeg.idle_work); @@ -384,14 +384,13 @@ static int jpeg_v4_0_3_hw_fini(void *handle) */ static int jpeg_v4_0_3_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; int r; - r = jpeg_v4_0_3_hw_fini(adev); + r = jpeg_v4_0_3_hw_fini(ip_block); if (r) return r; - r = amdgpu_jpeg_suspend(adev); + r = amdgpu_jpeg_suspend(ip_block->adev); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c index f59395f78d99b..a3ac5ad40eab7 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c @@ -214,9 +214,9 @@ static int jpeg_v4_0_5_hw_init(struct amdgpu_ip_block *ip_block) * * Stop the JPEG block, mark ring as not ready any more */ -static int jpeg_v4_0_5_hw_fini(void *handle) +static int jpeg_v4_0_5_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i; cancel_delayed_work_sync(&adev->vcn.idle_work); @@ -243,14 +243,13 @@ static int jpeg_v4_0_5_hw_fini(void *handle) */ static int jpeg_v4_0_5_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; int r; - r = jpeg_v4_0_5_hw_fini(adev); + r = jpeg_v4_0_5_hw_fini(ip_block); if (r) return r; - r = amdgpu_jpeg_suspend(adev); + r = amdgpu_jpeg_suspend(ip_block->adev); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c index 4a75ef6823541..5a102dab87da9 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c @@ -157,9 +157,9 @@ static int jpeg_v5_0_0_hw_init(struct amdgpu_ip_block *ip_block) * * Stop the JPEG block, mark ring as not ready any more */ -static int jpeg_v5_0_0_hw_fini(void *handle) +static int jpeg_v5_0_0_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; cancel_delayed_work_sync(&adev->vcn.idle_work); @@ -179,14 +179,13 @@ static int jpeg_v5_0_0_hw_fini(void *handle) */ static int jpeg_v5_0_0_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; int r; - r = jpeg_v5_0_0_hw_fini(adev); + r = jpeg_v5_0_0_hw_fini(ip_block); if (r) return r; - r = amdgpu_jpeg_suspend(adev); + r = amdgpu_jpeg_suspend(ip_block->adev); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c index e2ea54cc77f8f..30f09f78ae23c 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c @@ -56,7 +56,7 @@ MODULE_FIRMWARE("amdgpu/gc_11_5_2_mes_2.bin"); MODULE_FIRMWARE("amdgpu/gc_11_5_2_mes1.bin"); static int mes_v11_0_hw_init(struct amdgpu_ip_block *ip_block); -static int mes_v11_0_hw_fini(void *handle); +static int mes_v11_0_hw_fini(struct amdgpu_ip_block *ip_block); static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev); static int mes_v11_0_kiq_hw_fini(struct amdgpu_device *adev); @@ -1522,6 +1522,12 @@ static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev) mes_v11_0_kiq_setting(&adev->gfx.kiq[0].ring); + ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_MES); + if (unlikely(!ip_block)) { + dev_err(adev->dev, "Failed to get MES handle\n"); + return -EINVAL; + } + r = mes_v11_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE); if (r) goto failure; @@ -1532,12 +1538,6 @@ static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev) adev->mes.enable_legacy_queue_map = false; if (adev->mes.enable_legacy_queue_map) { - ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_MES); - if (unlikely(!ip_block)) { - dev_err(adev->dev, "Failed to get MES handle\n"); - return -EINVAL; - } - r = mes_v11_0_hw_init(ip_block); if (r) goto failure; @@ -1546,7 +1546,7 @@ static int mes_v11_0_kiq_hw_init(struct amdgpu_device *adev) return r; failure: - mes_v11_0_hw_fini(adev); + mes_v11_0_hw_fini(ip_block); return r; } @@ -1622,13 +1622,13 @@ static int mes_v11_0_hw_init(struct amdgpu_ip_block *ip_block) return 0; failure: - mes_v11_0_hw_fini(adev); + mes_v11_0_hw_fini(ip_block); return r; } -static int mes_v11_0_hw_fini(void *handle) +static int mes_v11_0_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (amdgpu_sriov_is_mes_info_enable(adev)) { amdgpu_bo_free_kernel(&adev->mes.resource_1, &adev->mes.resource_1_gpu_addr, &adev->mes.resource_1_addr); @@ -1639,13 +1639,12 @@ static int mes_v11_0_hw_fini(void *handle) static int mes_v11_0_suspend(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = ip_block->adev; - r = amdgpu_mes_suspend(adev); + r = amdgpu_mes_suspend(ip_block->adev); if (r) return r; - return mes_v11_0_hw_fini(adev); + return mes_v11_0_hw_fini(ip_block); } static int mes_v11_0_resume(struct amdgpu_ip_block *ip_block) diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c index 4db4d4d1945f2..9d65f4f64476a 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c @@ -40,7 +40,7 @@ MODULE_FIRMWARE("amdgpu/gc_12_0_1_mes1.bin"); MODULE_FIRMWARE("amdgpu/gc_12_0_1_uni_mes.bin"); static int mes_v12_0_hw_init(struct amdgpu_ip_block *ip_block); -static int mes_v12_0_hw_fini(void *handle); +static int mes_v12_0_hw_fini(struct amdgpu_ip_block *ip_block); static int mes_v12_0_kiq_hw_init(struct amdgpu_device *adev); static int mes_v12_0_kiq_hw_fini(struct amdgpu_device *adev); @@ -1480,6 +1480,12 @@ static int mes_v12_0_kiq_hw_init(struct amdgpu_device *adev) mes_v12_0_enable(adev, true); + ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_MES); + if (unlikely(!ip_block)) { + dev_err(adev->dev, "Failed to get MES handle\n"); + return -EINVAL; + } + r = mes_v12_0_queue_init(adev, AMDGPU_MES_KIQ_PIPE); if (r) goto failure; @@ -1493,12 +1499,6 @@ static int mes_v12_0_kiq_hw_init(struct amdgpu_device *adev) } if (adev->mes.enable_legacy_queue_map) { - ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_MES); - if (unlikely(!ip_block)) { - dev_err(adev->dev, "Failed to get MES handle\n"); - return -EINVAL; - } - r = mes_v12_0_hw_init(ip_block); if (r) goto failure; @@ -1507,7 +1507,7 @@ static int mes_v12_0_kiq_hw_init(struct amdgpu_device *adev) return r; failure: - mes_v12_0_hw_fini(adev); + mes_v12_0_hw_fini(ip_block); return r; } @@ -1591,11 +1591,11 @@ static int mes_v12_0_hw_init(struct amdgpu_ip_block *ip_block) return 0; failure: - mes_v12_0_hw_fini(adev); + mes_v12_0_hw_fini(ip_block); return r; } -static int mes_v12_0_hw_fini(void *handle) +static int mes_v12_0_hw_fini(struct amdgpu_ip_block *ip_block) { return 0; } @@ -1603,13 +1603,12 @@ static int mes_v12_0_hw_fini(void *handle) static int mes_v12_0_suspend(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = ip_block->adev; - r = amdgpu_mes_suspend(adev); + r = amdgpu_mes_suspend(ip_block->adev); if (r) return r; - return mes_v12_0_hw_fini(adev); + return mes_v12_0_hw_fini(ip_block); } static int mes_v12_0_resume(struct amdgpu_ip_block *ip_block) diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c index c52340d27396d..6a13f4dd54c16 100644 --- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c @@ -609,20 +609,16 @@ static int navi10_ih_hw_init(struct amdgpu_ip_block *ip_block) return navi10_ih_irq_init(adev); } -static int navi10_ih_hw_fini(void *handle) +static int navi10_ih_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; - - navi10_ih_irq_disable(adev); + navi10_ih_irq_disable(ip_block->adev); return 0; } static int navi10_ih_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - return navi10_ih_hw_fini(adev); + return navi10_ih_hw_fini(ip_block); } static int navi10_ih_resume(struct amdgpu_ip_block *ip_block) diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index 53576bfabd07b..c428cd01ac26f 100644 --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c @@ -1014,9 +1014,9 @@ static int nv_common_hw_init(struct amdgpu_ip_block *ip_block) return 0; } -static int nv_common_hw_fini(void *handle) +static int nv_common_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; /* Disable the doorbell aperture and selfring doorbell aperture * separately in hw_fini because nv_enable_doorbell_aperture @@ -1031,9 +1031,7 @@ static int nv_common_hw_fini(void *handle) static int nv_common_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - return nv_common_hw_fini(adev); + return nv_common_hw_fini(ip_block); } static int nv_common_resume(struct amdgpu_ip_block *ip_block) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c index 7303a8f595fad..185baac48529d 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c @@ -892,20 +892,16 @@ static int sdma_v2_4_hw_init(struct amdgpu_ip_block *ip_block) return r; } -static int sdma_v2_4_hw_fini(void *handle) +static int sdma_v2_4_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; - - sdma_v2_4_enable(adev, false); + sdma_v2_4_enable(ip_block->adev, false); return 0; } static int sdma_v2_4_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - return sdma_v2_4_hw_fini(adev); + return sdma_v2_4_hw_fini(ip_block); } static int sdma_v2_4_resume(struct amdgpu_ip_block *ip_block) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c index a7d95aa3d8dfd..735e7830d49ba 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c @@ -1178,9 +1178,9 @@ static int sdma_v3_0_hw_init(struct amdgpu_ip_block *ip_block) return r; } -static int sdma_v3_0_hw_fini(void *handle) +static int sdma_v3_0_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; sdma_v3_0_ctx_switch_enable(adev, false); sdma_v3_0_enable(adev, false); @@ -1190,9 +1190,7 @@ static int sdma_v3_0_hw_fini(void *handle) static int sdma_v3_0_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - return sdma_v3_0_hw_fini(adev); + return sdma_v3_0_hw_fini(ip_block); } static int sdma_v3_0_resume(struct amdgpu_ip_block *ip_block) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index 1aefa437ab90e..d4e28733dd1c7 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c @@ -1965,9 +1965,9 @@ static int sdma_v4_0_hw_init(struct amdgpu_ip_block *ip_block) return sdma_v4_0_start(adev); } -static int sdma_v4_0_hw_fini(void *handle) +static int sdma_v4_0_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i; if (amdgpu_sriov_vf(adev)) @@ -1999,7 +1999,7 @@ static int sdma_v4_0_suspend(struct amdgpu_ip_block *ip_block) return 0; } - return sdma_v4_0_hw_fini(adev); + return sdma_v4_0_hw_fini(ip_block); } static int sdma_v4_0_resume(struct amdgpu_ip_block *ip_block) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c index b6eb413a7aad3..87b524d6a3393 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c @@ -1482,9 +1482,9 @@ static int sdma_v4_4_2_hw_init(struct amdgpu_ip_block *ip_block) return r; } -static int sdma_v4_4_2_hw_fini(void *handle) +static int sdma_v4_4_2_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; uint32_t inst_mask; int i; @@ -1515,7 +1515,7 @@ static int sdma_v4_4_2_suspend(struct amdgpu_ip_block *ip_block) if (amdgpu_in_reset(adev)) sdma_v4_4_2_set_clockgating_state(adev, AMD_CG_STATE_UNGATE); - return sdma_v4_4_2_hw_fini(adev); + return sdma_v4_4_2_hw_fini(ip_block); } static int sdma_v4_4_2_resume(struct amdgpu_ip_block *ip_block) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c index 987be5c74929b..ce3f6f38b0dba 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c @@ -1489,9 +1489,9 @@ static int sdma_v5_0_hw_init(struct amdgpu_ip_block *ip_block) return r; } -static int sdma_v5_0_hw_fini(void *handle) +static int sdma_v5_0_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (amdgpu_sriov_vf(adev)) return 0; @@ -1504,9 +1504,7 @@ static int sdma_v5_0_hw_fini(void *handle) static int sdma_v5_0_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - return sdma_v5_0_hw_fini(adev); + return sdma_v5_0_hw_fini(ip_block); } static int sdma_v5_0_resume(struct amdgpu_ip_block *ip_block) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c index 692bbdbf42da9..3fe03b3409092 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c @@ -1384,9 +1384,9 @@ static int sdma_v5_2_hw_init(struct amdgpu_ip_block *ip_block) return sdma_v5_2_start(adev); } -static int sdma_v5_2_hw_fini(void *handle) +static int sdma_v5_2_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (amdgpu_sriov_vf(adev)) return 0; @@ -1399,9 +1399,7 @@ static int sdma_v5_2_hw_fini(void *handle) static int sdma_v5_2_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - return sdma_v5_2_hw_fini(adev); + return sdma_v5_2_hw_fini(ip_block); } static int sdma_v5_2_resume(struct amdgpu_ip_block *ip_block) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c index 12bba9eeb651b..05f0576c708bd 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c @@ -1387,9 +1387,9 @@ static int sdma_v6_0_hw_init(struct amdgpu_ip_block *ip_block) return sdma_v6_0_start(adev); } -static int sdma_v6_0_hw_fini(void *handle) +static int sdma_v6_0_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (amdgpu_sriov_vf(adev)) return 0; @@ -1402,9 +1402,7 @@ static int sdma_v6_0_hw_fini(void *handle) static int sdma_v6_0_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - return sdma_v6_0_hw_fini(adev); + return sdma_v6_0_hw_fini(ip_block); } static int sdma_v6_0_resume(struct amdgpu_ip_block *ip_block) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c index 33860349e4878..a7b9a66c7a32c 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c @@ -1345,9 +1345,9 @@ static int sdma_v7_0_hw_init(struct amdgpu_ip_block *ip_block) return sdma_v7_0_start(adev); } -static int sdma_v7_0_hw_fini(void *handle) +static int sdma_v7_0_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (amdgpu_sriov_vf(adev)) return 0; @@ -1360,9 +1360,7 @@ static int sdma_v7_0_hw_fini(void *handle) static int sdma_v7_0_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - return sdma_v7_0_hw_fini(adev); + return sdma_v7_0_hw_fini(ip_block); } static int sdma_v7_0_resume(struct amdgpu_ip_block *ip_block) diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c index 8170831900e0e..68b04f6aff8a9 100644 --- a/drivers/gpu/drm/amd/amdgpu/si.c +++ b/drivers/gpu/drm/amd/amdgpu/si.c @@ -2645,16 +2645,14 @@ static int si_common_hw_init(struct amdgpu_ip_block *ip_block) return 0; } -static int si_common_hw_fini(void *handle) +static int si_common_hw_fini(struct amdgpu_ip_block *ip_block) { return 0; } static int si_common_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - return si_common_hw_fini(adev); + return si_common_hw_fini(ip_block); } static int si_common_resume(struct amdgpu_ip_block *ip_block) diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c index 90a0696d3a773..c82d335573f23 100644 --- a/drivers/gpu/drm/amd/amdgpu/si_dma.c +++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c @@ -524,20 +524,16 @@ static int si_dma_hw_init(struct amdgpu_ip_block *ip_block) return si_dma_start(adev); } -static int si_dma_hw_fini(void *handle) +static int si_dma_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; - - si_dma_stop(adev); + si_dma_stop(ip_block->adev); return 0; } static int si_dma_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - return si_dma_hw_fini(adev); + return si_dma_hw_fini(ip_block); } static int si_dma_resume(struct amdgpu_ip_block *ip_block) diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c b/drivers/gpu/drm/amd/amdgpu/si_ih.c index 68b217d61a850..14b6aef01d50e 100644 --- a/drivers/gpu/drm/amd/amdgpu/si_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c @@ -193,20 +193,16 @@ static int si_ih_hw_init(struct amdgpu_ip_block *ip_block) return si_ih_irq_init(adev); } -static int si_ih_hw_fini(void *handle) +static int si_ih_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; - - si_ih_irq_disable(adev); + si_ih_irq_disable(ip_block->adev); return 0; } static int si_ih_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - return si_ih_hw_fini(adev); + return si_ih_hw_fini(ip_block); } static int si_ih_resume(struct amdgpu_ip_block *ip_block) diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index e0f89f5e850d7..9d6ddbc8cbf5f 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -1284,9 +1284,9 @@ static int soc15_common_hw_init(struct amdgpu_ip_block *ip_block) return 0; } -static int soc15_common_hw_fini(void *handle) +static int soc15_common_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; /* Disable the doorbell aperture and selfring doorbell aperture * separately in hw_fini because soc15_enable_doorbell_aperture @@ -1320,9 +1320,7 @@ static int soc15_common_hw_fini(void *handle) static int soc15_common_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - return soc15_common_hw_fini(adev); + return soc15_common_hw_fini(ip_block); } static int soc15_common_resume(struct amdgpu_ip_block *ip_block) diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c index 52b76693a7073..fcc351326fcbc 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc21.c +++ b/drivers/gpu/drm/amd/amdgpu/soc21.c @@ -867,9 +867,9 @@ static int soc21_common_hw_init(struct amdgpu_ip_block *ip_block) return 0; } -static int soc21_common_hw_fini(void *handle) +static int soc21_common_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; /* Disable the doorbell aperture and selfring doorbell aperture * separately in hw_fini because soc21_enable_doorbell_aperture @@ -892,9 +892,7 @@ static int soc21_common_hw_fini(void *handle) static int soc21_common_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - return soc21_common_hw_fini(adev); + return soc21_common_hw_fini(ip_block); } static bool soc21_need_reset_on_resume(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/soc24.c b/drivers/gpu/drm/amd/amdgpu/soc24.c index dc4f2536e2c52..dd4438236054c 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc24.c +++ b/drivers/gpu/drm/amd/amdgpu/soc24.c @@ -494,9 +494,9 @@ static int soc24_common_hw_init(struct amdgpu_ip_block *ip_block) return 0; } -static int soc24_common_hw_fini(void *handle) +static int soc24_common_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; /* Disable the doorbell aperture and selfring doorbell aperture * separately in hw_fini because soc21_enable_doorbell_aperture @@ -514,9 +514,7 @@ static int soc24_common_hw_fini(void *handle) static int soc24_common_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - return soc24_common_hw_fini(adev); + return soc24_common_hw_fini(ip_block); } static int soc24_common_resume(struct amdgpu_ip_block *ip_block) diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c index ffbf33f4ea5d0..c3a46c494d3dd 100644 --- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c @@ -336,20 +336,16 @@ static int tonga_ih_hw_init(struct amdgpu_ip_block *ip_block) return 0; } -static int tonga_ih_hw_fini(void *handle) +static int tonga_ih_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; - - tonga_ih_irq_disable(adev); + tonga_ih_irq_disable(ip_block->adev); return 0; } static int tonga_ih_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - return tonga_ih_hw_fini(adev); + return tonga_ih_hw_fini(ip_block); } static int tonga_ih_resume(struct amdgpu_ip_block *ip_block) @@ -405,12 +401,10 @@ static bool tonga_ih_check_soft_reset(void *handle) static int tonga_ih_pre_soft_reset(void *handle) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; - - if (!adev->irq.srbm_soft_reset) + if (!ip_block->adev->irq.srbm_soft_reset) return 0; - return tonga_ih_hw_fini(adev); + return tonga_ih_hw_fini(ip_block); } static int tonga_ih_post_soft_reset(void *handle) diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c index 128a8339e58a8..eb0be2a4b7da5 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c @@ -692,9 +692,9 @@ static int uvd_v3_1_hw_init(struct amdgpu_ip_block *ip_block) * * Stop the UVD block, mark ring as not ready any more */ -static int uvd_v3_1_hw_fini(void *handle) +static int uvd_v3_1_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; cancel_delayed_work_sync(&adev->uvd.idle_work); @@ -740,7 +740,7 @@ static int uvd_v3_1_suspend(struct amdgpu_ip_block *ip_block) AMD_CG_STATE_GATE); } - r = uvd_v3_1_hw_fini(adev); + r = uvd_v3_1_hw_fini(ip_block); if (r) return r; diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c index 64b1dbffed8a4..462e6a1075a81 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c @@ -206,9 +206,9 @@ static int uvd_v4_2_hw_init(struct amdgpu_ip_block *ip_block) * * Stop the UVD block, mark ring as not ready any more */ -static int uvd_v4_2_hw_fini(void *handle) +static int uvd_v4_2_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; cancel_delayed_work_sync(&adev->uvd.idle_work); @@ -254,7 +254,7 @@ static int uvd_v4_2_suspend(struct amdgpu_ip_block *ip_block) AMD_CG_STATE_GATE); } - r = uvd_v4_2_hw_fini(adev); + r = uvd_v4_2_hw_fini(ip_block); if (r) return r; diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c index 8fa33c74675c3..96435ce51ac25 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c @@ -204,9 +204,9 @@ static int uvd_v5_0_hw_init(struct amdgpu_ip_block *ip_block) * * Stop the UVD block, mark ring as not ready any more */ -static int uvd_v5_0_hw_fini(void *handle) +static int uvd_v5_0_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; cancel_delayed_work_sync(&adev->uvd.idle_work); @@ -252,7 +252,7 @@ static int uvd_v5_0_suspend(struct amdgpu_ip_block *ip_block) AMD_CG_STATE_GATE); } - r = uvd_v5_0_hw_fini(adev); + r = uvd_v5_0_hw_fini(ip_block); if (r) return r; diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c index a48f073e1f598..bc28fe939ac3e 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c @@ -528,9 +528,9 @@ static int uvd_v6_0_hw_init(struct amdgpu_ip_block *ip_block) * * Stop the UVD block, mark ring as not ready any more */ -static int uvd_v6_0_hw_fini(void *handle) +static int uvd_v6_0_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; cancel_delayed_work_sync(&adev->uvd.idle_work); @@ -576,7 +576,7 @@ static int uvd_v6_0_suspend(struct amdgpu_ip_block *ip_block) AMD_CG_STATE_GATE); } - r = uvd_v6_0_hw_fini(adev); + r = uvd_v6_0_hw_fini(ip_block); if (r) return r; diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c index c7023379dc47b..595180f27eac5 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c @@ -592,9 +592,9 @@ static int uvd_v7_0_hw_init(struct amdgpu_ip_block *ip_block) * * Stop the UVD block, mark ring as not ready any more */ -static int uvd_v7_0_hw_fini(void *handle) +static int uvd_v7_0_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; cancel_delayed_work_sync(&adev->uvd.idle_work); @@ -644,7 +644,7 @@ static int uvd_v7_0_suspend(struct amdgpu_ip_block *ip_block) AMD_CG_STATE_GATE); } - r = uvd_v7_0_hw_fini(adev); + r = uvd_v7_0_hw_fini(ip_block); if (r) return r; diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c index d11782e43824c..54ecb5d3cac33 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c @@ -481,11 +481,9 @@ static int vce_v2_0_hw_init(struct amdgpu_ip_block *ip_block) return 0; } -static int vce_v2_0_hw_fini(void *handle) +static int vce_v2_0_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; - - cancel_delayed_work_sync(&adev->vce.idle_work); + cancel_delayed_work_sync(&ip_block->adev->vce.idle_work); return 0; } @@ -519,7 +517,7 @@ static int vce_v2_0_suspend(struct amdgpu_ip_block *ip_block) AMD_CG_STATE_GATE); } - r = vce_v2_0_hw_fini(adev); + r = vce_v2_0_hw_fini(ip_block); if (r) return r; diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c index b4d5467c48da9..2372d761ce385 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c @@ -485,15 +485,10 @@ static int vce_v3_0_hw_init(struct amdgpu_ip_block *ip_block) return 0; } -static int vce_v3_0_hw_fini(void *handle) +static int vce_v3_0_hw_fini(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; - struct amdgpu_ip_block *ip_block; - - ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE); - if (!ip_block) - return -EINVAL; + struct amdgpu_device *adev = ip_block->adev; cancel_delayed_work_sync(&adev->vce.idle_work); @@ -533,7 +528,7 @@ static int vce_v3_0_suspend(struct amdgpu_ip_block *ip_block) AMD_CG_STATE_GATE); } - r = vce_v3_0_hw_fini(adev); + r = vce_v3_0_hw_fini(ip_block); if (r) return r; diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c index f23d3a380f127..7098c4268900d 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c @@ -536,14 +536,9 @@ static int vce_v4_0_hw_init(struct amdgpu_ip_block *ip_block) return 0; } -static int vce_v4_0_hw_fini(void *handle) +static int vce_v4_0_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; - struct amdgpu_ip_block *ip_block; - - ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_VCE); - if (!ip_block) - return -EINVAL; + struct amdgpu_device *adev = ip_block->adev; cancel_delayed_work_sync(&adev->vce.idle_work); @@ -599,7 +594,7 @@ static int vce_v4_0_suspend(struct amdgpu_ip_block *ip_block) AMD_CG_STATE_GATE); } - r = vce_v4_0_hw_fini(adev); + r = vce_v4_0_hw_fini(ip_block); if (r) return r; diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index d8fe7e409928b..cf6eb9d9b692c 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c @@ -272,9 +272,9 @@ static int vcn_v1_0_hw_init(struct amdgpu_ip_block *ip_block) * * Stop the VCN block, mark ring as not ready any more */ -static int vcn_v1_0_hw_fini(void *handle) +static int vcn_v1_0_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; cancel_delayed_work_sync(&adev->vcn.idle_work); @@ -306,7 +306,7 @@ static int vcn_v1_0_suspend(struct amdgpu_ip_block *ip_block) amdgpu_dpm_enable_uvd(adev, false); } - r = vcn_v1_0_hw_fini(adev); + r = vcn_v1_0_hw_fini(ip_block); if (r) return r; diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c index aab28163cb602..7334e307845d7 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c @@ -309,9 +309,9 @@ static int vcn_v2_0_hw_init(struct amdgpu_ip_block *ip_block) * * Stop the VCN block, mark ring as not ready any more */ -static int vcn_v2_0_hw_fini(void *handle) +static int vcn_v2_0_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; cancel_delayed_work_sync(&adev->vcn.idle_work); @@ -333,13 +333,12 @@ static int vcn_v2_0_hw_fini(void *handle) static int vcn_v2_0_suspend(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = ip_block->adev; - r = vcn_v2_0_hw_fini(adev); + r = vcn_v2_0_hw_fini(ip_block); if (r) return r; - r = amdgpu_vcn_suspend(adev); + r = amdgpu_vcn_suspend(ip_block->adev); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c index 3cfacd8a46796..bbb56951f83e3 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c @@ -385,9 +385,9 @@ static int vcn_v2_5_hw_init(struct amdgpu_ip_block *ip_block) * * Stop the VCN block, mark ring as not ready any more */ -static int vcn_v2_5_hw_fini(void *handle) +static int vcn_v2_5_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i; cancel_delayed_work_sync(&adev->vcn.idle_work); @@ -418,13 +418,12 @@ static int vcn_v2_5_hw_fini(void *handle) static int vcn_v2_5_suspend(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = ip_block->adev; - r = vcn_v2_5_hw_fini(adev); + r = vcn_v2_5_hw_fini(ip_block); if (r) return r; - r = amdgpu_vcn_suspend(adev); + r = amdgpu_vcn_suspend(ip_block->adev); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c index a44404e88e3b1..5e970f959962e 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c @@ -417,9 +417,9 @@ static int vcn_v3_0_hw_init(struct amdgpu_ip_block *ip_block) * * Stop the VCN block, mark ring as not ready any more */ -static int vcn_v3_0_hw_fini(void *handle) +static int vcn_v3_0_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i; cancel_delayed_work_sync(&adev->vcn.idle_work); @@ -450,13 +450,12 @@ static int vcn_v3_0_hw_fini(void *handle) static int vcn_v3_0_suspend(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = ip_block->adev; - r = vcn_v3_0_hw_fini(adev); + r = vcn_v3_0_hw_fini(ip_block); if (r) return r; - r = amdgpu_vcn_suspend(adev); + r = amdgpu_vcn_suspend(ip_block->adev); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c index 2dd8697de19ef..f7abddacd394c 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c @@ -345,9 +345,9 @@ static int vcn_v4_0_hw_init(struct amdgpu_ip_block *ip_block) * * Stop the VCN block, mark ring as not ready any more */ -static int vcn_v4_0_hw_fini(void *handle) +static int vcn_v4_0_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i; cancel_delayed_work_sync(&adev->vcn.idle_work); @@ -379,13 +379,12 @@ static int vcn_v4_0_hw_fini(void *handle) static int vcn_v4_0_suspend(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = ip_block->adev; - r = vcn_v4_0_hw_fini(adev); + r = vcn_v4_0_hw_fini(ip_block); if (r) return r; - r = amdgpu_vcn_suspend(adev); + r = amdgpu_vcn_suspend(ip_block->adev); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c index 36c39c553827c..090d51f849a09 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c @@ -312,9 +312,9 @@ static int vcn_v4_0_3_hw_init(struct amdgpu_ip_block *ip_block) * * Stop the VCN block, mark ring as not ready any more */ -static int vcn_v4_0_3_hw_fini(void *handle) +static int vcn_v4_0_3_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; cancel_delayed_work_sync(&adev->vcn.idle_work); @@ -333,14 +333,13 @@ static int vcn_v4_0_3_hw_fini(void *handle) */ static int vcn_v4_0_3_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; int r; - r = vcn_v4_0_3_hw_fini(adev); + r = vcn_v4_0_3_hw_fini(ip_block); if (r) return r; - r = amdgpu_vcn_suspend(adev); + r = amdgpu_vcn_suspend(ip_block->adev); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c index 13bed4099faf2..4094507a03074 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c @@ -295,9 +295,9 @@ static int vcn_v4_0_5_hw_init(struct amdgpu_ip_block *ip_block) * * Stop the VCN block, mark ring as not ready any more */ -static int vcn_v4_0_5_hw_fini(void *handle) +static int vcn_v4_0_5_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i; cancel_delayed_work_sync(&adev->vcn.idle_work); @@ -327,13 +327,12 @@ static int vcn_v4_0_5_hw_fini(void *handle) static int vcn_v4_0_5_suspend(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = ip_block->adev; - r = vcn_v4_0_5_hw_fini(adev); + r = vcn_v4_0_5_hw_fini(ip_block); if (r) return r; - r = amdgpu_vcn_suspend(adev); + r = amdgpu_vcn_suspend(ip_block->adev); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c index 82ff2dc9dc110..eb63b6d4a9342 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c @@ -259,9 +259,9 @@ static int vcn_v5_0_0_hw_init(struct amdgpu_ip_block *ip_block) * * Stop the VCN block, mark ring as not ready any more */ -static int vcn_v5_0_0_hw_fini(void *handle) +static int vcn_v5_0_0_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i; cancel_delayed_work_sync(&adev->vcn.idle_work); @@ -291,13 +291,12 @@ static int vcn_v5_0_0_hw_fini(void *handle) static int vcn_v5_0_0_suspend(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = ip_block->adev; - r = vcn_v5_0_0_hw_fini(adev); + r = vcn_v5_0_0_hw_fini(ip_block); if (r) return r; - r = amdgpu_vcn_suspend(adev); + r = amdgpu_vcn_suspend(ip_block->adev); return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c index e1952fb7e4b55..64a9ebe512c4d 100644 --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c @@ -539,20 +539,16 @@ static int vega10_ih_hw_init(struct amdgpu_ip_block *ip_block) return vega10_ih_irq_init(ip_block->adev); } -static int vega10_ih_hw_fini(void *handle) +static int vega10_ih_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; - - vega10_ih_irq_disable(adev); + vega10_ih_irq_disable(ip_block->adev); return 0; } static int vega10_ih_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - return vega10_ih_hw_fini(adev); + return vega10_ih_hw_fini(ip_block); } static int vega10_ih_resume(struct amdgpu_ip_block *ip_block) diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c index 8a52313f1368c..84301b5252acb 100644 --- a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c @@ -607,20 +607,16 @@ static int vega20_ih_hw_init(struct amdgpu_ip_block *ip_block) return 0; } -static int vega20_ih_hw_fini(void *handle) +static int vega20_ih_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; - - vega20_ih_irq_disable(adev); + vega20_ih_irq_disable(ip_block->adev); return 0; } static int vega20_ih_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - return vega20_ih_hw_fini(adev); + return vega20_ih_hw_fini(ip_block); } static int vega20_ih_resume(struct amdgpu_ip_block *ip_block) diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index 11d1389a90d17..b45b370d3c979 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/drivers/gpu/drm/amd/amdgpu/vi.c @@ -1718,9 +1718,9 @@ static int vi_common_hw_init(struct amdgpu_ip_block *ip_block) return 0; } -static int vi_common_hw_fini(void *handle) +static int vi_common_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; /* enable the doorbell aperture */ vi_enable_doorbell_aperture(adev, false); @@ -1733,9 +1733,7 @@ static int vi_common_hw_fini(void *handle) static int vi_common_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = ip_block->adev; - - return vi_common_hw_fini(adev); + return vi_common_hw_fini(ip_block); } static int vi_common_resume(struct amdgpu_ip_block *ip_block) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 6900161b0737a..a67fe8f654d46 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2865,9 +2865,9 @@ static int dm_hw_init(struct amdgpu_ip_block *ip_block) * cleanup. This involves cleaning up the DRM device, DC, and any modules that * were loaded. Also flush IRQ workqueues and disable them. */ -static int dm_hw_fini(void *handle) +static int dm_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; amdgpu_dm_hpd_fini(adev); diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h index ecf60a8d7be5f..d892273fdb10d 100644 --- a/drivers/gpu/drm/amd/include/amd_shared.h +++ b/drivers/gpu/drm/amd/include/amd_shared.h @@ -385,7 +385,7 @@ struct amd_ip_funcs { int (*sw_fini)(struct amdgpu_ip_block *ip_block); int (*early_fini)(struct amdgpu_ip_block *ip_block); int (*hw_init)(struct amdgpu_ip_block *ip_block); - int (*hw_fini)(void *handle); + int (*hw_fini)(struct amdgpu_ip_block *ip_block); void (*late_fini)(struct amdgpu_ip_block *ip_block); int (*prepare_suspend)(struct amdgpu_ip_block *ip_block); int (*suspend)(struct amdgpu_ip_block *ip_block); diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c index 8dc22378c095f..323f2e79db45c 100644 --- a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c @@ -3053,9 +3053,9 @@ static int kv_dpm_hw_init(struct amdgpu_ip_block *ip_block) return ret; } -static int kv_dpm_hw_fini(void *handle) +static int kv_dpm_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (adev->pm.dpm_enabled) kv_dpm_disable(adev); diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c index 2f4044e0e1b1d..7ac5720199930 100644 --- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c @@ -7795,9 +7795,9 @@ static int si_dpm_hw_init(struct amdgpu_ip_block *ip_block) return ret; } -static int si_dpm_hw_fini(void *handle) +static int si_dpm_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (adev->pm.dpm_enabled) si_dpm_disable(adev); diff --git a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c index e5ce94cd0850a..cd44f56b6e00c 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c +++ b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c @@ -173,10 +173,9 @@ static int pp_hw_init(struct amdgpu_ip_block *ip_block) return ret; } -static int pp_hw_fini(void *handle) +static int pp_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = handle; - struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; + struct pp_hwmgr *hwmgr = ip_block->adev->powerplay.pp_handle; cancel_delayed_work_sync(&hwmgr->swctf_delayed_work); diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 5c8fc5e5cfa84..1651d473072d1 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -2009,9 +2009,9 @@ static int smu_reset_mp1_state(struct smu_context *smu) return ret; } -static int smu_hw_fini(void *handle) +static int smu_hw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; struct smu_context *smu = adev->powerplay.pp_handle; int ret; @@ -2059,7 +2059,7 @@ static int smu_reset(struct smu_context *smu) if (!ip_block) return -EINVAL; - ret = smu_hw_fini(adev); + ret = smu_hw_fini(ip_block); if (ret) return ret; From 441cb8e1cdaa1499e81db8fe1688f946162b80ff Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Wed, 2 Oct 2024 14:52:52 +0530 Subject: [PATCH 1728/1868] drm/amdgpu: fix html doc generation warning MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fix the html doc warning due to mix up of the forward declaration of struct amdgpu_ip_block. Signed-off-by: Sunil Khatri Reviewed-by: Christian König (cherry picked from commit 47b6056b652d455c6c9b82e0032912234dcf4dc4) --- drivers/gpu/drm/amd/include/amd_shared.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h index d892273fdb10d..f98b3a5444779 100644 --- a/drivers/gpu/drm/amd/include/amd_shared.h +++ b/drivers/gpu/drm/amd/include/amd_shared.h @@ -28,6 +28,8 @@ #define AMD_MAX_USEC_TIMEOUT 1000000 /* 1000 ms */ +struct amdgpu_ip_block; + /* * Chip flags @@ -375,8 +377,6 @@ enum amd_dpm_forced_level; * making calls to hooks from each IP block. This list is ordered to ensure * that the driver initializes the IP blocks in a safe sequence. */ -struct amdgpu_ip_block; - struct amd_ip_funcs { char *name; int (*early_init)(struct amdgpu_ip_block *ip_block); From 0440399d211ef8af4bdebf664ce21ee43e8e3ad4 Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Mon, 30 Sep 2024 15:00:30 +0530 Subject: [PATCH 1729/1868] drm/amdgpu: update the handle ptr in soft_reset MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Update the *handle to amdgpu_ip_block ptr for all functions pointers of soft_reset. Signed-off-by: Sunil Khatri Reviewed-by: Christian König Change-Id: I6a3bdfaf740eedad8b29aef9f67ceac4c177e826 (cherry picked from commit a93729bf33414340e9816afdfb61ddfc4eb65703) --- drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 2 +- drivers/gpu/drm/amd/amdgpu/cik.c | 2 +- drivers/gpu/drm/amd/amdgpu/cik_ih.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/cz_ih.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 3 +-- drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/iceland_ih.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/ih_v6_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/ih_v6_1.c | 2 +- drivers/gpu/drm/amd/amdgpu/ih_v7_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 2 +- drivers/gpu/drm/amd/amdgpu/nv.c | 2 +- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 2 +- drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 2 +- drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 11 ++++++++--- drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/si.c | 2 +- drivers/gpu/drm/amd/amdgpu/si_dma.c | 2 +- drivers/gpu/drm/amd/amdgpu/si_ih.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/soc15.c | 2 +- drivers/gpu/drm/amd/amdgpu/soc21.c | 2 +- drivers/gpu/drm/amd/amdgpu/soc24.c | 2 +- drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 2 +- drivers/gpu/drm/amd/amdgpu/vega20_ih.c | 2 +- drivers/gpu/drm/amd/amdgpu/vi.c | 2 +- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c | 2 +- drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 2 +- drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c | 2 +- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 1 + 63 files changed, 100 insertions(+), 95 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c index 9cabfb3439631..235772073f3e5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c @@ -597,7 +597,7 @@ static int acp_wait_for_idle(struct amdgpu_ip_block *ip_block) return 0; } -static int acp_soft_reset(void *handle) +static int acp_soft_reset(struct amdgpu_ip_block *ip_block) { return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 7ac422935e305..e05507b7d4cb1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -5065,7 +5065,7 @@ static int amdgpu_device_ip_soft_reset(struct amdgpu_device *adev) continue; if (adev->ip_blocks[i].status.hang && adev->ip_blocks[i].version->funcs->soft_reset) { - r = adev->ip_blocks[i].version->funcs->soft_reset(adev); + r = adev->ip_blocks[i].version->funcs->soft_reset(&adev->ip_blocks[i]); if (r) return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c index d73318d91acf9..527da07cb4cc4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c @@ -159,7 +159,7 @@ static int isp_wait_for_idle(struct amdgpu_ip_block *ip_block) return 0; } -static int isp_soft_reset(void *handle) +static int isp_soft_reset(struct amdgpu_ip_block *ip_block) { return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c index c5deb6210fe1c..6ec5b624a3ef1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c @@ -782,7 +782,7 @@ static int amdgpu_vkms_wait_for_idle(struct amdgpu_ip_block *ip_block) return 0; } -static int amdgpu_vkms_soft_reset(void *handle) +static int amdgpu_vkms_soft_reset(struct amdgpu_ip_block *ip_block) { return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c index 78b47242fd59a..e95f8e29d631c 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik.c +++ b/drivers/gpu/drm/amd/amdgpu/cik.c @@ -2173,7 +2173,7 @@ static int cik_common_wait_for_idle(struct amdgpu_ip_block *ip_block) return 0; } -static int cik_common_soft_reset(void *handle) +static int cik_common_soft_reset(struct amdgpu_ip_block *ip_block) { /* XXX hard reset?? */ return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c index 4e20c6c84dbc5..b259f969580e6 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c @@ -372,9 +372,9 @@ static int cik_ih_wait_for_idle(struct amdgpu_ip_block *ip_block) return -ETIMEDOUT; } -static int cik_ih_soft_reset(void *handle) +static int cik_ih_soft_reset(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; u32 srbm_soft_reset = 0; u32 tmp = RREG32(mmSRBM_STATUS); diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c index 41c3179a6029a..ed527b02c4213 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c @@ -54,7 +54,7 @@ static void cik_sdma_set_ring_funcs(struct amdgpu_device *adev); static void cik_sdma_set_irq_funcs(struct amdgpu_device *adev); static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev); static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev); -static int cik_sdma_soft_reset(void *handle); +static int cik_sdma_soft_reset(struct amdgpu_ip_block *ip_block); MODULE_FIRMWARE("amdgpu/bonaire_sdma.bin"); MODULE_FIRMWARE("amdgpu/bonaire_sdma1.bin"); @@ -1052,10 +1052,10 @@ static int cik_sdma_wait_for_idle(struct amdgpu_ip_block *ip_block) return -ETIMEDOUT; } -static int cik_sdma_soft_reset(void *handle) +static int cik_sdma_soft_reset(struct amdgpu_ip_block *ip_block) { u32 srbm_soft_reset = 0; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; u32 tmp; /* sdma0 */ diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c index c62a67f8247ff..b555afd6eb96e 100644 --- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c @@ -368,10 +368,10 @@ static int cz_ih_wait_for_idle(struct amdgpu_ip_block *ip_block) return -ETIMEDOUT; } -static int cz_ih_soft_reset(void *handle) +static int cz_ih_soft_reset(struct amdgpu_ip_block *ip_block) { u32 srbm_soft_reset = 0; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; u32 tmp = RREG32(mmSRBM_STATUS); if (tmp & SRBM_STATUS__IH_BUSY_MASK) diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index 6aed24c721590..c0313474fd691 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -2972,10 +2972,10 @@ static bool dce_v10_0_check_soft_reset(void *handle) return dce_v10_0_is_display_hung(adev); } -static int dce_v10_0_soft_reset(void *handle) +static int dce_v10_0_soft_reset(struct amdgpu_ip_block *ip_block) { u32 srbm_soft_reset = 0, tmp; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (dce_v10_0_is_display_hung(adev)) srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK; diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index a4198f222e8d7..986c589e37da7 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -3103,10 +3103,10 @@ static int dce_v11_0_wait_for_idle(struct amdgpu_ip_block *ip_block) return 0; } -static int dce_v11_0_soft_reset(void *handle) +static int dce_v11_0_soft_reset(struct amdgpu_ip_block *ip_block) { u32 srbm_soft_reset = 0, tmp; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (dce_v11_0_is_display_hung(adev)) srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK; diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c index ae36c5d52dca0..e98639d7305c4 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c @@ -2860,7 +2860,7 @@ static int dce_v6_0_wait_for_idle(struct amdgpu_ip_block *ip_block) return 0; } -static int dce_v6_0_soft_reset(void *handle) +static int dce_v6_0_soft_reset(struct amdgpu_ip_block *ip_block) { DRM_INFO("xxxx: dce_v6_0_soft_reset --- no impl!!\n"); return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index 23899f8564a40..f00f5be74b258 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -2882,10 +2882,10 @@ static int dce_v8_0_wait_for_idle(struct amdgpu_ip_block *ip_block) return 0; } -static int dce_v8_0_soft_reset(void *handle) +static int dce_v8_0_soft_reset(struct amdgpu_ip_block *ip_block) { u32 srbm_soft_reset = 0, tmp; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (dce_v8_0_is_display_hung(adev)) srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index fac275a9ed5be..38013a542f1ad 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -7503,11 +7503,11 @@ static int gfx_v10_0_wait_for_idle(struct amdgpu_ip_block *ip_block) return -ETIMEDOUT; } -static int gfx_v10_0_soft_reset(void *handle) +static int gfx_v10_0_soft_reset(struct amdgpu_ip_block *ip_block) { u32 grbm_soft_reset = 0; u32 tmp; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; /* GRBM_STATUS */ tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index 745ed5dc3b362..44ef391f0770e 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -4776,12 +4776,12 @@ int gfx_v11_0_request_gfx_index_mutex(struct amdgpu_device *adev, return 0; } -static int gfx_v11_0_soft_reset(void *handle) +static int gfx_v11_0_soft_reset(struct amdgpu_ip_block *ip_block) { u32 grbm_soft_reset = 0; u32 tmp; int r, i, j, k; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; amdgpu_gfx_rlc_enter_safe_mode(adev, 0); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c index 62bc6ac2df935..4ce1013c22e39 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c @@ -3186,7 +3186,7 @@ static int gfx_v6_0_wait_for_idle(struct amdgpu_ip_block *ip_block) return -ETIMEDOUT; } -static int gfx_v6_0_soft_reset(void *handle) +static int gfx_v6_0_soft_reset(struct amdgpu_ip_block *ip_block) { return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index b7342f290e173..1e101de505fc0 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -4536,11 +4536,11 @@ static int gfx_v7_0_wait_for_idle(struct amdgpu_ip_block *ip_block) return -ETIMEDOUT; } -static int gfx_v7_0_soft_reset(void *handle) +static int gfx_v7_0_soft_reset(struct amdgpu_ip_block *ip_block) { u32 grbm_soft_reset = 0, srbm_soft_reset = 0; u32 tmp; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; /* GRBM_STATUS */ tmp = RREG32(mmGRBM_STATUS); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index d0605dd323fee..a0e4a2244dc58 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -5032,9 +5032,9 @@ static int gfx_v8_0_pre_soft_reset(void *handle) return 0; } -static int gfx_v8_0_soft_reset(void *handle) +static int gfx_v8_0_soft_reset(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; u32 grbm_soft_reset = 0, srbm_soft_reset = 0; u32 tmp; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index c67c2161054c1..9a769a9733ad1 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -4114,11 +4114,11 @@ static int gfx_v9_0_wait_for_idle(struct amdgpu_ip_block *ip_block) return -ETIMEDOUT; } -static int gfx_v9_0_soft_reset(void *handle) +static int gfx_v9_0_soft_reset(struct amdgpu_ip_block *ip_block) { u32 grbm_soft_reset = 0; u32 tmp; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; /* GRBM_STATUS */ tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index fd3126c8f575b..4678bf5606c75 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -2423,11 +2423,11 @@ static int gfx_v9_4_3_wait_for_idle(struct amdgpu_ip_block *ip_block) return -ETIMEDOUT; } -static int gfx_v9_4_3_soft_reset(void *handle) +static int gfx_v9_4_3_soft_reset(struct amdgpu_ip_block *ip_block) { u32 grbm_soft_reset = 0; u32 tmp; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; /* GRBM_STATUS */ tmp = RREG32_SOC15(GC, GET_INST(GC, 0), regGRBM_STATUS); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c index 01ccea2f23815..301a42359ae1a 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c @@ -1083,7 +1083,7 @@ static int gmc_v10_0_wait_for_idle(struct amdgpu_ip_block *ip_block) return 0; } -static int gmc_v10_0_soft_reset(void *handle) +static int gmc_v10_0_soft_reset(struct amdgpu_ip_block *ip_block) { return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c index 7b7055b6f3a41..749a2ed91a4f8 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c @@ -991,7 +991,7 @@ static int gmc_v11_0_wait_for_idle(struct amdgpu_ip_block *ip_block) return 0; } -static int gmc_v11_0_soft_reset(void *handle) +static int gmc_v11_0_soft_reset(struct amdgpu_ip_block *ip_block) { return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c index 676ed1e0fefac..ba3bc3ed71070 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c @@ -960,7 +960,7 @@ static int gmc_v12_0_wait_for_idle(struct amdgpu_ip_block *ip_block) return 0; } -static int gmc_v12_0_soft_reset(void *handle) +static int gmc_v12_0_soft_reset(struct amdgpu_ip_block *ip_block) { return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c index 7ca816e253bf5..c3a8a582bd56f 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c @@ -982,10 +982,9 @@ static int gmc_v6_0_wait_for_idle(struct amdgpu_ip_block *ip_block) } -static int gmc_v6_0_soft_reset(void *handle) +static int gmc_v6_0_soft_reset(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; - u32 srbm_soft_reset = 0; u32 tmp = RREG32(mmSRBM_STATUS); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c index da9154ca48043..a5b096e52e78a 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c @@ -1163,9 +1163,9 @@ static int gmc_v7_0_wait_for_idle(struct amdgpu_ip_block *ip_block) } -static int gmc_v7_0_soft_reset(void *handle) +static int gmc_v7_0_soft_reset(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; u32 srbm_soft_reset = 0; u32 tmp = RREG32(mmSRBM_STATUS); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index a2b5accc3fe3d..6bf8a83390110 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -1341,9 +1341,9 @@ static int gmc_v8_0_pre_soft_reset(void *handle) return 0; } -static int gmc_v8_0_soft_reset(void *handle) +static int gmc_v8_0_soft_reset(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; u32 srbm_soft_reset; if (!adev->gmc.srbm_soft_reset) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index 4dc7c04f201a3..f541e45b5557c 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -2464,7 +2464,7 @@ static int gmc_v9_0_wait_for_idle(struct amdgpu_ip_block *ip_block) return 0; } -static int gmc_v9_0_soft_reset(void *handle) +static int gmc_v9_0_soft_reset(struct amdgpu_ip_block *ip_block) { /* XXX for emulation.*/ return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c index 2122da177acc4..570efe59111f3 100644 --- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c @@ -362,10 +362,10 @@ static int iceland_ih_wait_for_idle(struct amdgpu_ip_block *ip_block) return -ETIMEDOUT; } -static int iceland_ih_soft_reset(void *handle) +static int iceland_ih_soft_reset(struct amdgpu_ip_block *ip_block) { u32 srbm_soft_reset = 0; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; u32 tmp = RREG32(mmSRBM_STATUS); if (tmp & SRBM_STATUS__IH_BUSY_MASK) diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c index 8666ace8a1cbd..51284ca9c827c 100644 --- a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c @@ -664,7 +664,7 @@ static int ih_v6_0_wait_for_idle(struct amdgpu_ip_block *ip_block) return -ETIMEDOUT; } -static int ih_v6_0_soft_reset(void *handle) +static int ih_v6_0_soft_reset(struct amdgpu_ip_block *ip_block) { /* todo */ return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c index 075e9f02c4a63..c4fd5454ddfd6 100644 --- a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c +++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c @@ -643,7 +643,7 @@ static int ih_v6_1_wait_for_idle(struct amdgpu_ip_block *ip_block) return -ETIMEDOUT; } -static int ih_v6_1_soft_reset(void *handle) +static int ih_v6_1_soft_reset(struct amdgpu_ip_block *ip_block) { /* todo */ return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c index d78053e8dd6c0..de830824fa0b5 100644 --- a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c @@ -633,7 +633,7 @@ static int ih_v7_0_wait_for_idle(struct amdgpu_ip_block *ip_block) return -ETIMEDOUT; } -static int ih_v7_0_soft_reset(void *handle) +static int ih_v7_0_soft_reset(struct amdgpu_ip_block *ip_block) { /* todo */ return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c index 6a13f4dd54c16..58d0a74842b7c 100644 --- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c @@ -638,7 +638,7 @@ static int navi10_ih_wait_for_idle(struct amdgpu_ip_block *ip_block) return -ETIMEDOUT; } -static int navi10_ih_soft_reset(void *handle) +static int navi10_ih_soft_reset(struct amdgpu_ip_block *ip_block) { /* todo */ return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index c428cd01ac26f..373f2641cd255 100644 --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c @@ -1049,7 +1049,7 @@ static int nv_common_wait_for_idle(struct amdgpu_ip_block *ip_block) return 0; } -static int nv_common_soft_reset(void *handle) +static int nv_common_soft_reset(struct amdgpu_ip_block *ip_block) { return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c index 185baac48529d..4dc507c67d1e7 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c @@ -938,10 +938,10 @@ static int sdma_v2_4_wait_for_idle(struct amdgpu_ip_block *ip_block) return -ETIMEDOUT; } -static int sdma_v2_4_soft_reset(void *handle) +static int sdma_v2_4_soft_reset(struct amdgpu_ip_block *ip_block) { u32 srbm_soft_reset = 0; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; u32 tmp = RREG32(mmSRBM_STATUS2); if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) { diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c index 735e7830d49ba..4e34f55acb366 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c @@ -1286,9 +1286,9 @@ static int sdma_v3_0_post_soft_reset(void *handle) return 0; } -static int sdma_v3_0_soft_reset(void *handle) +static int sdma_v3_0_soft_reset(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; u32 srbm_soft_reset = 0; u32 tmp; diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index d4e28733dd1c7..ff39a0c6c287f 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c @@ -2050,7 +2050,7 @@ static int sdma_v4_0_wait_for_idle(struct amdgpu_ip_block *ip_block) return -ETIMEDOUT; } -static int sdma_v4_0_soft_reset(void *handle) +static int sdma_v4_0_soft_reset(struct amdgpu_ip_block *ip_block) { /* todo */ diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c index 87b524d6a3393..3f95cb232bb69 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c @@ -1557,7 +1557,7 @@ static int sdma_v4_4_2_wait_for_idle(struct amdgpu_ip_block *ip_block) return -ETIMEDOUT; } -static int sdma_v4_4_2_soft_reset(void *handle) +static int sdma_v4_4_2_soft_reset(struct amdgpu_ip_block *ip_block) { /* todo */ diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c index ce3f6f38b0dba..fd769a576a2bd 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c @@ -1544,7 +1544,7 @@ static int sdma_v5_0_wait_for_idle(struct amdgpu_ip_block *ip_block) return -ETIMEDOUT; } -static int sdma_v5_0_soft_reset(void *handle) +static int sdma_v5_0_soft_reset(struct amdgpu_ip_block *ip_block) { /* todo */ diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c index 3fe03b3409092..56146075928c3 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c @@ -761,9 +761,9 @@ static int sdma_v5_2_load_microcode(struct amdgpu_device *adev) return 0; } -static int sdma_v5_2_soft_reset(void *handle) +static int sdma_v5_2_soft_reset(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; u32 grbm_soft_reset; u32 tmp; int i; @@ -803,6 +803,7 @@ static int sdma_v5_2_soft_reset(void *handle) static int sdma_v5_2_start(struct amdgpu_device *adev) { int r = 0; + struct amdgpu_ip_block *ip_block; if (amdgpu_sriov_vf(adev)) { sdma_v5_2_ctx_switch_enable(adev, false); @@ -823,7 +824,11 @@ static int sdma_v5_2_start(struct amdgpu_device *adev) msleep(1000); } - sdma_v5_2_soft_reset(adev); + ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_SDMA); + if (!ip_block) + return -EINVAL; + + sdma_v5_2_soft_reset(ip_block); /* unhalt the MEs */ sdma_v5_2_enable(adev, true); /* enable sdma ring preemption */ diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c index 05f0576c708bd..637eebe747dd5 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c @@ -755,9 +755,9 @@ static int sdma_v6_0_load_microcode(struct amdgpu_device *adev) return 0; } -static int sdma_v6_0_soft_reset(void *handle) +static int sdma_v6_0_soft_reset(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; u32 tmp; int i; diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c index a7b9a66c7a32c..16570d1fbeb8f 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c @@ -747,9 +747,9 @@ static int sdma_v7_0_load_microcode(struct amdgpu_device *adev) return 0; } -static int sdma_v7_0_soft_reset(void *handle) +static int sdma_v7_0_soft_reset(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; u32 tmp; int i; diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c index 68b04f6aff8a9..75634c23a4db7 100644 --- a/drivers/gpu/drm/amd/amdgpu/si.c +++ b/drivers/gpu/drm/amd/amdgpu/si.c @@ -2670,7 +2670,7 @@ static int si_common_wait_for_idle(struct amdgpu_ip_block *ip_block) return 0; } -static int si_common_soft_reset(void *handle) +static int si_common_soft_reset(struct amdgpu_ip_block *ip_block) { return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c index c82d335573f23..46e6273aeb1f0 100644 --- a/drivers/gpu/drm/amd/amdgpu/si_dma.c +++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c @@ -566,7 +566,7 @@ static int si_dma_wait_for_idle(struct amdgpu_ip_block *ip_block) return -ETIMEDOUT; } -static int si_dma_soft_reset(void *handle) +static int si_dma_soft_reset(struct amdgpu_ip_block *ip_block) { DRM_INFO("si_dma_soft_reset --- not implemented !!!!!!!\n"); return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c b/drivers/gpu/drm/amd/amdgpu/si_ih.c index 14b6aef01d50e..3afbb47242ccd 100644 --- a/drivers/gpu/drm/amd/amdgpu/si_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c @@ -234,9 +234,9 @@ static int si_ih_wait_for_idle(struct amdgpu_ip_block *ip_block) return -ETIMEDOUT; } -static int si_ih_soft_reset(void *handle) +static int si_ih_soft_reset(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; u32 srbm_soft_reset = 0; u32 tmp = RREG32(SRBM_STATUS); diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index 9d6ddbc8cbf5f..d63a88e3c4b74 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -1344,7 +1344,7 @@ static int soc15_common_wait_for_idle(struct amdgpu_ip_block *ip_block) return 0; } -static int soc15_common_soft_reset(void *handle) +static int soc15_common_soft_reset(struct amdgpu_ip_block *ip_block) { return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c index fcc351326fcbc..89951073ec3a3 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc21.c +++ b/drivers/gpu/drm/amd/amdgpu/soc21.c @@ -937,7 +937,7 @@ static int soc21_common_wait_for_idle(struct amdgpu_ip_block *ip_block) return 0; } -static int soc21_common_soft_reset(void *handle) +static int soc21_common_soft_reset(struct amdgpu_ip_block *ip_block) { return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/soc24.c b/drivers/gpu/drm/amd/amdgpu/soc24.c index dd4438236054c..546a67c44f19e 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc24.c +++ b/drivers/gpu/drm/amd/amdgpu/soc24.c @@ -532,7 +532,7 @@ static int soc24_common_wait_for_idle(struct amdgpu_ip_block *ip_block) return 0; } -static int soc24_common_soft_reset(void *handle) +static int soc24_common_soft_reset(struct amdgpu_ip_block *ip_block) { return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c index c3a46c494d3dd..adc309e8a28e1 100644 --- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c @@ -417,9 +417,9 @@ static int tonga_ih_post_soft_reset(void *handle) return tonga_ih_hw_init(ip_block); } -static int tonga_ih_soft_reset(void *handle) +static int tonga_ih_soft_reset(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; u32 srbm_soft_reset; if (!adev->irq.srbm_soft_reset) diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c index eb0be2a4b7da5..ad148a7cf3424 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c @@ -777,9 +777,9 @@ static int uvd_v3_1_wait_for_idle(struct amdgpu_ip_block *ip_block) return -ETIMEDOUT; } -static int uvd_v3_1_soft_reset(void *handle) +static int uvd_v3_1_soft_reset(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; uvd_v3_1_stop(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c index 462e6a1075a81..7e5ef65566d9b 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c @@ -677,9 +677,9 @@ static int uvd_v4_2_wait_for_idle(struct amdgpu_ip_block *ip_block) return -ETIMEDOUT; } -static int uvd_v4_2_soft_reset(void *handle) +static int uvd_v4_2_soft_reset(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; uvd_v4_2_stop(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c index 96435ce51ac25..7a78e3ef54b53 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c @@ -599,9 +599,9 @@ static int uvd_v5_0_wait_for_idle(struct amdgpu_ip_block *ip_block) return -ETIMEDOUT; } -static int uvd_v5_0_soft_reset(void *handle) +static int uvd_v5_0_soft_reset(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; uvd_v5_0_stop(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c index bc28fe939ac3e..d3e1411849659 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c @@ -1194,9 +1194,9 @@ static int uvd_v6_0_pre_soft_reset(void *handle) return 0; } -static int uvd_v6_0_soft_reset(void *handle) +static int uvd_v6_0_soft_reset(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; u32 srbm_soft_reset; if (!adev->uvd.inst->srbm_soft_reset) diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c index 595180f27eac5..a1bea0013ef2a 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c @@ -1516,9 +1516,9 @@ static int uvd_v7_0_pre_soft_reset(void *handle) return 0; } -static int uvd_v7_0_soft_reset(void *handle) +static int uvd_v7_0_soft_reset(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; u32 srbm_soft_reset; if (!adev->uvd.inst[ring->me].srbm_soft_reset) diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c index 54ecb5d3cac33..bb0c390b6a1da 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c @@ -535,9 +535,9 @@ static int vce_v2_0_resume(struct amdgpu_ip_block *ip_block) return vce_v2_0_hw_init(ip_block); } -static int vce_v2_0_soft_reset(void *handle) +static int vce_v2_0_soft_reset(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; WREG32_FIELD(SRBM_SOFT_RESET, SOFT_RESET_VCE, 1); mdelay(5); diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c index 2372d761ce385..344e4b8087caf 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c @@ -667,9 +667,9 @@ static bool vce_v3_0_check_soft_reset(void *handle) } } -static int vce_v3_0_soft_reset(void *handle) +static int vce_v3_0_soft_reset(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; u32 srbm_soft_reset; if (!adev->vce.srbm_soft_reset) diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c index 7098c4268900d..379d2cc1125c2 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c @@ -762,9 +762,9 @@ static bool vce_v4_0_check_soft_reset(void *handle) } } -static int vce_v4_0_soft_reset(void *handle) +static int vce_v4_0_soft_reset(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; u32 srbm_soft_reset; if (!adev->vce.srbm_soft_reset) diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c index 64a9ebe512c4d..26da7a1881b55 100644 --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c @@ -568,7 +568,7 @@ static int vega10_ih_wait_for_idle(struct amdgpu_ip_block *ip_block) return -ETIMEDOUT; } -static int vega10_ih_soft_reset(void *handle) +static int vega10_ih_soft_reset(struct amdgpu_ip_block *ip_block) { /* todo */ diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c index 84301b5252acb..1cbfc5188f9b7 100644 --- a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c @@ -636,7 +636,7 @@ static int vega20_ih_wait_for_idle(struct amdgpu_ip_block *ip_block) return -ETIMEDOUT; } -static int vega20_ih_soft_reset(void *handle) +static int vega20_ih_soft_reset(struct amdgpu_ip_block *ip_block) { /* todo */ diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index b45b370d3c979..7ddd3b358d62f 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/drivers/gpu/drm/amd/amdgpu/vi.c @@ -1751,7 +1751,7 @@ static int vi_common_wait_for_idle(struct amdgpu_ip_block *ip_block) return 0; } -static int vi_common_soft_reset(void *handle) +static int vi_common_soft_reset(struct amdgpu_ip_block *ip_block) { return 0; } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index a67fe8f654d46..ae9ce0b94bb57 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -332,7 +332,7 @@ static bool dm_check_soft_reset(void *handle) return false; } -static int dm_soft_reset(void *handle) +static int dm_soft_reset(struct amdgpu_ip_block *ip_block) { /* XXX todo */ return 0; diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c index 323f2e79db45c..cb2e8a1a5483b 100644 --- a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c @@ -3106,7 +3106,7 @@ static int kv_dpm_wait_for_idle(struct amdgpu_ip_block *ip_block) } -static int kv_dpm_soft_reset(void *handle) +static int kv_dpm_soft_reset(struct amdgpu_ip_block *ip_block) { return 0; } diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c index 7ac5720199930..f42726dd69682 100644 --- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c @@ -7849,7 +7849,7 @@ static int si_dpm_wait_for_idle(struct amdgpu_ip_block *ip_block) return 0; } -static int si_dpm_soft_reset(void *handle) +static int si_dpm_soft_reset(struct amdgpu_ip_block *ip_block) { return 0; } diff --git a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c index cd44f56b6e00c..f65fb0ec7d599 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c +++ b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c @@ -249,7 +249,7 @@ static int pp_wait_for_idle(struct amdgpu_ip_block *ip_block) return 0; } -static int pp_sw_reset(void *handle) +static int pp_sw_reset(struct amdgpu_ip_block *ip_block) { return 0; } diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 1651d473072d1..dd23ab0eeb2f4 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -2053,6 +2053,7 @@ static void smu_late_fini(void *handle) static int smu_reset(struct smu_context *smu) { struct amdgpu_device *adev = smu->adev; + struct amdgpu_ip_block *ip_block; int ret; ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_SMC); From 0c9ca8ad6ed056d5fea9e72c1a793f73fa032f93 Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Mon, 30 Sep 2024 15:08:44 +0530 Subject: [PATCH 1730/1868] drm/amdgpu: update the handle ptr in post_soft_reset MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Update the *handle to amdgpu_ip_block ptr for all functions pointers of post_soft_reset. Signed-off-by: Sunil Khatri Reviewed-by: Christian König Change-Id: I8de3b3dcaba88bca5cf4a12e5f4e734d6c92fbf0 (cherry picked from commit 92fceacd0916bf621a0f7ba99779441807e646d2) --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 5 +++-- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 4 ++-- 10 files changed, 20 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index e05507b7d4cb1..0fabd204445ca 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -5094,7 +5094,7 @@ static int amdgpu_device_ip_post_soft_reset(struct amdgpu_device *adev) continue; if (adev->ip_blocks[i].status.hang && adev->ip_blocks[i].version->funcs->post_soft_reset) - r = adev->ip_blocks[i].version->funcs->post_soft_reset(adev); + r = adev->ip_blocks[i].version->funcs->post_soft_reset(&adev->ip_blocks[i]); if (r) return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index 44ef391f0770e..c27141751dec2 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -4931,12 +4931,13 @@ static bool gfx_v11_0_check_soft_reset(void *handle) return false; } -static int gfx_v11_0_post_soft_reset(void *handle) +static int gfx_v11_0_post_soft_reset(struct amdgpu_ip_block *ip_block) { + struct amdgpu_device *adev = ip_block->adev; /** * GFX soft reset will impact MES, need resume MES when do GFX soft reset */ - return amdgpu_mes_resume((struct amdgpu_device *)handle); + return amdgpu_mes_resume(adev); } static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index a0e4a2244dc58..6d06d90b9d180 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -5094,9 +5094,9 @@ static int gfx_v8_0_soft_reset(struct amdgpu_ip_block *ip_block) return 0; } -static int gfx_v8_0_post_soft_reset(void *handle) +static int gfx_v8_0_post_soft_reset(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; u32 grbm_soft_reset = 0; if ((!adev->gfx.grbm_soft_reset) && diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index 6bf8a83390110..25b30203ceb11 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -1372,9 +1372,9 @@ static int gmc_v8_0_soft_reset(struct amdgpu_ip_block *ip_block) return 0; } -static int gmc_v8_0_post_soft_reset(void *handle) +static int gmc_v8_0_post_soft_reset(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (!adev->gmc.srbm_soft_reset) return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c index 4e34f55acb366..112a56fd3a2af 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c @@ -1267,9 +1267,9 @@ static int sdma_v3_0_pre_soft_reset(void *handle) return 0; } -static int sdma_v3_0_post_soft_reset(void *handle) +static int sdma_v3_0_post_soft_reset(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; u32 srbm_soft_reset = 0; if (!adev->sdma.srbm_soft_reset) diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c index adc309e8a28e1..f550454f015bf 100644 --- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c @@ -407,9 +407,9 @@ static int tonga_ih_pre_soft_reset(void *handle) return tonga_ih_hw_fini(ip_block); } -static int tonga_ih_post_soft_reset(void *handle) +static int tonga_ih_post_soft_reset(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (!adev->irq.srbm_soft_reset) return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c index d3e1411849659..2293151504e46 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c @@ -1225,9 +1225,9 @@ static int uvd_v6_0_soft_reset(struct amdgpu_ip_block *ip_block) return 0; } -static int uvd_v6_0_post_soft_reset(void *handle) +static int uvd_v6_0_post_soft_reset(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (!adev->uvd.inst->srbm_soft_reset) return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c index a1bea0013ef2a..f8bfc22105921 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c @@ -1547,9 +1547,9 @@ static int uvd_v7_0_soft_reset(struct amdgpu_ip_block *ip_block) return 0; } -static int uvd_v7_0_post_soft_reset(void *handle) +static int uvd_v7_0_post_soft_reset(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (!adev->uvd.inst[ring->me].srbm_soft_reset) return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c index 344e4b8087caf..dc5c210b54e49 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c @@ -711,9 +711,9 @@ static int vce_v3_0_pre_soft_reset(void *handle) } -static int vce_v3_0_post_soft_reset(void *handle) +static int vce_v3_0_post_soft_reset(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (!adev->vce.srbm_soft_reset) return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c index 379d2cc1125c2..7c7e07c52ed3f 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c @@ -806,9 +806,9 @@ static int vce_v4_0_pre_soft_reset(void *handle) } -static int vce_v4_0_post_soft_reset(void *handle) +static int vce_v4_0_post_soft_reset(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (!adev->vce.srbm_soft_reset) return 0; From c61056696ed2eca156e6596645fbbb4b4d1c8a9d Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Fri, 20 Sep 2024 15:25:10 +0530 Subject: [PATCH 1731/1868] drm/amdgpu: Add NPS switch support for GC 9.4.3 Add dynamic NPS switch support for GC 9.4.3 variants. Only GC v9.4.3 and GC v9.4.4 currently support this. NPS switch is only supported if an SOC supports multiple NPS modes. Signed-off-by: Lijo Lazar Signed-off-by: Rajneesh Bhardwaj Reviewed-by: Feifei Xu Reviewed-by: Hawking Zhang (cherry picked from commit f75564dea3b2ee2b83c662e88d28e6b2fa021d8a) --- drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h | 1 + drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 45 ++++++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c | 12 +++++++ 3 files changed, 58 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h index f61d117b0cafe..79c2f807b9fe8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h @@ -101,6 +101,7 @@ struct amdgpu_nbio_funcs { int (*get_compute_partition_mode)(struct amdgpu_device *adev); u32 (*get_memory_partition_mode)(struct amdgpu_device *adev, u32 *supp_modes); + bool (*is_nps_switch_requested)(struct amdgpu_device *adev); u64 (*get_pcie_replay_count)(struct amdgpu_device *adev); void (*set_reg_remap)(struct amdgpu_device *adev); }; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index f541e45b5557c..23e7d366ab499 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -1397,6 +1397,17 @@ gmc_v9_0_query_memory_partition(struct amdgpu_device *adev) return gmc_v9_0_get_memory_partition(adev, NULL); } +static bool gmc_v9_0_need_reset_on_init(struct amdgpu_device *adev) +{ + if (adev->nbio.funcs && adev->nbio.funcs->is_nps_switch_requested && + adev->nbio.funcs->is_nps_switch_requested(adev)) { + adev->gmc.reset_flags |= AMDGPU_GMC_INIT_RESET_NPS; + return true; + } + + return false; +} + static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = { .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb, .flush_gpu_tlb_pasid = gmc_v9_0_flush_gpu_tlb_pasid, @@ -1408,6 +1419,8 @@ static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = { .override_vm_pte_flags = gmc_v9_0_override_vm_pte_flags, .get_vbios_fb_size = gmc_v9_0_get_vbios_fb_size, .query_mem_partition_mode = &gmc_v9_0_query_memory_partition, + .request_mem_partition_mode = &amdgpu_gmc_request_memory_partition, + .need_reset_on_init = &gmc_v9_0_need_reset_on_init, }; static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev) @@ -1547,6 +1560,28 @@ static void gmc_v9_0_set_xgmi_ras_funcs(struct amdgpu_device *adev) adev->gmc.xgmi.ras = &xgmi_ras; } +static void gmc_v9_0_init_nps_details(struct amdgpu_device *adev) +{ + adev->gmc.supported_nps_modes = 0; + + if (amdgpu_sriov_vf(adev) || (adev->flags & AMD_IS_APU)) + return; + + /*TODO: Check PSP version also which supports NPS switch. Otherwise keep + * supported modes as 0. + */ + switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { + case IP_VERSION(9, 4, 3): + case IP_VERSION(9, 4, 4): + adev->gmc.supported_nps_modes = + BIT(AMDGPU_NPS1_PARTITION_MODE) | + BIT(AMDGPU_NPS4_PARTITION_MODE); + break; + default: + break; + } +} + static int gmc_v9_0_early_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_device *adev = ip_block->adev; @@ -2169,6 +2204,7 @@ static int gmc_v9_0_sw_init(void *handle) if (r) return r; + gmc_v9_0_init_nps_details(adev); /* * number of VMs * VMID 0 is reserved for System @@ -2441,8 +2477,17 @@ static int gmc_v9_0_suspend(struct amdgpu_ip_block *ip_block) static int gmc_v9_0_resume(struct amdgpu_ip_block *ip_block) { + struct amdgpu_device *adev = ip_block->adev; int r; + /* If a reset is done for NPS mode switch, read the memory range + * information again. + */ + if (adev->gmc.reset_flags & AMDGPU_GMC_INIT_RESET_NPS) { + gmc_v9_0_init_sw_mem_ranges(adev, adev->gmc.mem_partitions); + adev->gmc.reset_flags &= ~AMDGPU_GMC_INIT_RESET_NPS; + } + r = gmc_v9_0_hw_init(ip_block); if (r) return r; diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c index d1bd79bbae532..8a0a63ac88d2b 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_9.c @@ -401,6 +401,17 @@ static int nbio_v7_9_get_compute_partition_mode(struct amdgpu_device *adev) return px; } +static bool nbio_v7_9_is_nps_switch_requested(struct amdgpu_device *adev) +{ + u32 tmp; + + tmp = RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_MEM_STATUS); + tmp = REG_GET_FIELD(tmp, BIF_BX_PF0_PARTITION_MEM_STATUS, + CHANGE_STATUE); + + /* 0x8 - NPS switch requested */ + return (tmp == 0x8); +} static u32 nbio_v7_9_get_memory_partition_mode(struct amdgpu_device *adev, u32 *supp_modes) { @@ -508,6 +519,7 @@ const struct amdgpu_nbio_funcs nbio_v7_9_funcs = { .remap_hdp_registers = nbio_v7_9_remap_hdp_registers, .get_compute_partition_mode = nbio_v7_9_get_compute_partition_mode, .get_memory_partition_mode = nbio_v7_9_get_memory_partition_mode, + .is_nps_switch_requested = nbio_v7_9_is_nps_switch_requested, .init_registers = nbio_v7_9_init_registers, .get_pcie_replay_count = nbio_v7_9_get_pcie_replay_count, .set_reg_remap = nbio_v7_9_set_reg_remap, From 988913bdf2d07bcf7ad8c37fc63aebe0e29f83a0 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Thu, 19 Sep 2024 17:22:50 +0530 Subject: [PATCH 1732/1868] drm/amdgpu: Add PSP interface for NPS switch Implement PSP ring command interface for memory partitioning on the fly on the supported asics. Signed-off-by: Rajneesh Bhardwaj Reviewed-by: Feifei Xu (cherry picked from commit b2076d212d69095b06350a721dea3911ff60d522) --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 25 +++++++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 1 + drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h | 14 +++++++++++--- 3 files changed, 37 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 6857f9d09826c..ec2a205dcca87 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -1045,6 +1045,31 @@ static int psp_rl_load(struct amdgpu_device *adev) return ret; } +int psp_memory_partition(struct psp_context *psp, int mode) +{ + struct psp_gfx_cmd_resp *cmd; + int ret; + + if (amdgpu_sriov_vf(psp->adev)) + return 0; + + cmd = acquire_psp_cmd_buf(psp); + + cmd->cmd_id = GFX_CMD_ID_FB_NPS_MODE; + cmd->cmd.cmd_memory_part.mode = mode; + + dev_info(psp->adev->dev, + "Requesting %d memory partition change through PSP", mode); + ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr); + if (ret) + dev_err(psp->adev->dev, + "PSP request failed to change to NPS%d mode\n", mode); + + release_psp_cmd_buf(psp); + + return ret; +} + int psp_spatial_partition(struct psp_context *psp, int mode) { struct psp_gfx_cmd_resp *cmd; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h index 76fa18ffc0452..567cb1f924ca8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h @@ -553,6 +553,7 @@ int psp_load_fw_list(struct psp_context *psp, void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size); int psp_spatial_partition(struct psp_context *psp, int mode); +int psp_memory_partition(struct psp_context *psp, int mode); int is_psp_fw_valid(struct psp_bin_desc bin); diff --git a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h b/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h index 604301371e4f6..f4a91b126c73c 100644 --- a/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h +++ b/drivers/gpu/drm/amd/amdgpu/psp_gfx_if.h @@ -103,8 +103,10 @@ enum psp_gfx_cmd_id GFX_CMD_ID_AUTOLOAD_RLC = 0x00000021, /* Indicates all graphics fw loaded, start RLC autoload */ GFX_CMD_ID_BOOT_CFG = 0x00000022, /* Boot Config */ GFX_CMD_ID_SRIOV_SPATIAL_PART = 0x00000027, /* Configure spatial partitioning mode */ - /*IDs of performance monitoring/profiling*/ - GFX_CMD_ID_CONFIG_SQ_PERFMON = 0x00000046, /* Config CGTT_SQ_CLK_CTRL */ + /*IDs of performance monitoring/profiling*/ + GFX_CMD_ID_CONFIG_SQ_PERFMON = 0x00000046, /* Config CGTT_SQ_CLK_CTRL */ + /* Dynamic memory partitioninig (NPS mode change)*/ + GFX_CMD_ID_FB_NPS_MODE = 0x00000048, /* Configure memory partitioning mode */ }; /* PSP boot config sub-commands */ @@ -362,6 +364,11 @@ struct psp_gfx_cmd_config_sq_perfmon { uint8_t reserved[5]; }; +struct psp_gfx_cmd_fb_memory_part { + uint32_t mode; /* requested NPS mode */ + uint32_t resvd; +}; + /* All GFX ring buffer commands. */ union psp_gfx_commands { @@ -376,7 +383,8 @@ union psp_gfx_commands struct psp_gfx_cmd_load_toc cmd_load_toc; struct psp_gfx_cmd_boot_cfg boot_cfg; struct psp_gfx_cmd_sriov_spatial_part cmd_spatial_part; - struct psp_gfx_cmd_config_sq_perfmon config_sq_perfmon; + struct psp_gfx_cmd_config_sq_perfmon config_sq_perfmon; + struct psp_gfx_cmd_fb_memory_part cmd_memory_part; }; struct psp_gfx_uresp_reserved From 5cf4f8b6c48c520192f02757b153374d26cecfeb Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Mon, 30 Sep 2024 14:37:11 +0530 Subject: [PATCH 1733/1868] drm/amdgpu: update the handle ptr in pre_soft_reset MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Update the *handle to amdgpu_ip_block ptr for all functions pointers of pre_soft_reset. Signed-off-by: Sunil Khatri Reviewed-by: Christian König Change-Id: Ica495f2759ac465e41c28a4b94c67cccbc1226be (cherry picked from commit f71332689cc7554f63a5af9e0e0f9409039ea92b) --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 2 +- drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 4 ++-- 9 files changed, 16 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 0fabd204445ca..e6409e4aba311 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -5003,7 +5003,7 @@ static int amdgpu_device_ip_pre_soft_reset(struct amdgpu_device *adev) continue; if (adev->ip_blocks[i].status.hang && adev->ip_blocks[i].version->funcs->pre_soft_reset) { - r = adev->ip_blocks[i].version->funcs->pre_soft_reset(adev); + r = adev->ip_blocks[i].version->funcs->pre_soft_reset(&adev->ip_blocks[i]); if (r) return r; } diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 6d06d90b9d180..712c4f5ecb06c 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -4991,9 +4991,9 @@ static bool gfx_v8_0_check_soft_reset(void *handle) } } -static int gfx_v8_0_pre_soft_reset(void *handle) +static int gfx_v8_0_pre_soft_reset(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; u32 grbm_soft_reset = 0; if ((!adev->gfx.grbm_soft_reset) && diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index 25b30203ceb11..d670926c9a19f 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -1327,9 +1327,9 @@ static bool gmc_v8_0_check_soft_reset(void *handle) return false; } -static int gmc_v8_0_pre_soft_reset(void *handle) +static int gmc_v8_0_pre_soft_reset(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (!adev->gmc.srbm_soft_reset) return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c index 112a56fd3a2af..0108d053ae2d8 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c @@ -1248,9 +1248,9 @@ static bool sdma_v3_0_check_soft_reset(void *handle) } } -static int sdma_v3_0_pre_soft_reset(void *handle) +static int sdma_v3_0_pre_soft_reset(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; u32 srbm_soft_reset = 0; if (!adev->sdma.srbm_soft_reset) diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c index f550454f015bf..1a2b8dc4c3030 100644 --- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c @@ -399,7 +399,7 @@ static bool tonga_ih_check_soft_reset(void *handle) } } -static int tonga_ih_pre_soft_reset(void *handle) +static int tonga_ih_pre_soft_reset(struct amdgpu_ip_block *ip_block) { if (!ip_block->adev->irq.srbm_soft_reset) return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c index 2293151504e46..502e609c8205f 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c @@ -1183,9 +1183,9 @@ static bool uvd_v6_0_check_soft_reset(void *handle) } } -static int uvd_v6_0_pre_soft_reset(void *handle) +static int uvd_v6_0_pre_soft_reset(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (!adev->uvd.inst->srbm_soft_reset) return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c index f8bfc22105921..fcd4f477c3477 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c @@ -1505,9 +1505,9 @@ static bool uvd_v7_0_check_soft_reset(void *handle) } } -static int uvd_v7_0_pre_soft_reset(void *handle) +static int uvd_v7_0_pre_soft_reset(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (!adev->uvd.inst[ring->me].srbm_soft_reset) return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c index dc5c210b54e49..eccbea2bddafa 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c @@ -698,9 +698,9 @@ static int vce_v3_0_soft_reset(struct amdgpu_ip_block *ip_block) return 0; } -static int vce_v3_0_pre_soft_reset(void *handle) +static int vce_v3_0_pre_soft_reset(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (!adev->vce.srbm_soft_reset) return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c index 7c7e07c52ed3f..bf33d6d615861 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c @@ -793,9 +793,9 @@ static int vce_v4_0_soft_reset(struct amdgpu_ip_block *ip_block) return 0; } -static int vce_v4_0_pre_soft_reset(void *handle) +static int vce_v4_0_pre_soft_reset(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (!adev->vce.srbm_soft_reset) return 0; From bb9f70610d751801456a44632cafacb2b156d849 Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Mon, 30 Sep 2024 14:32:13 +0530 Subject: [PATCH 1734/1868] drm/amdgpu: update the handle ptr in check_soft_reset MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Update the *handle to amdgpu_ip_block ptr for all functions pointers of check_soft_reset. Signed-off-by: Sunil Khatri Reviewed-by: Christian König (cherry picked from commit c6f86b2c049bb96347a2defd02bf030298232518) --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 ++- drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 4 ++-- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +- 14 files changed, 27 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index e6409e4aba311..47440d9bbb102 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -4974,7 +4974,8 @@ static bool amdgpu_device_ip_check_soft_reset(struct amdgpu_device *adev) continue; if (adev->ip_blocks[i].version->funcs->check_soft_reset) adev->ip_blocks[i].status.hang = - adev->ip_blocks[i].version->funcs->check_soft_reset(adev); + adev->ip_blocks[i].version->funcs->check_soft_reset( + &adev->ip_blocks[i]); if (adev->ip_blocks[i].status.hang) { dev_info(adev->dev, "IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name); asic_hang = true; diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index c0313474fd691..4581e8eebccd1 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -2965,9 +2965,9 @@ static int dce_v10_0_wait_for_idle(struct amdgpu_ip_block *ip_block) return 0; } -static bool dce_v10_0_check_soft_reset(void *handle) +static bool dce_v10_0_check_soft_reset(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return dce_v10_0_is_display_hung(adev); } diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index c27141751dec2..db7d9bbe9eab7 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -4907,10 +4907,10 @@ static int gfx_v11_0_soft_reset(struct amdgpu_ip_block *ip_block) return gfx_v11_0_cp_resume(adev); } -static bool gfx_v11_0_check_soft_reset(void *handle) +static bool gfx_v11_0_check_soft_reset(struct amdgpu_ip_block *ip_block) { int i, r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; struct amdgpu_ring *ring; long tmo = msecs_to_jiffies(1000); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 712c4f5ecb06c..546fa0c6cf4aa 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -4929,9 +4929,9 @@ static int gfx_v8_0_resume(struct amdgpu_ip_block *ip_block) return gfx_v8_0_hw_init(ip_block); } -static bool gfx_v8_0_check_soft_reset(void *handle) +static bool gfx_v8_0_check_soft_reset(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; u32 grbm_soft_reset = 0, srbm_soft_reset = 0; u32 tmp; diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index d670926c9a19f..0f68ffb20c1b6 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -1300,10 +1300,10 @@ static int gmc_v8_0_wait_for_idle(struct amdgpu_ip_block *ip_block) } -static bool gmc_v8_0_check_soft_reset(void *handle) +static bool gmc_v8_0_check_soft_reset(struct amdgpu_ip_block *ip_block) { u32 srbm_soft_reset = 0; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; u32 tmp = RREG32(mmSRBM_STATUS); if (tmp & SRBM_STATUS__VMC_BUSY_MASK) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c index 0108d053ae2d8..ca2d3212bb424 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c @@ -1227,9 +1227,9 @@ static int sdma_v3_0_wait_for_idle(struct amdgpu_ip_block *ip_block) return -ETIMEDOUT; } -static bool sdma_v3_0_check_soft_reset(void *handle) +static bool sdma_v3_0_check_soft_reset(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; u32 srbm_soft_reset = 0; u32 tmp = RREG32(mmSRBM_STATUS2); diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c index 637eebe747dd5..47c8edb4d5a0c 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c @@ -791,9 +791,9 @@ static int sdma_v6_0_soft_reset(struct amdgpu_ip_block *ip_block) return sdma_v6_0_start(adev); } -static bool sdma_v6_0_check_soft_reset(void *handle) +static bool sdma_v6_0_check_soft_reset(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; struct amdgpu_ring *ring; int i, r; long tmo = msecs_to_jiffies(1000); diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c index 16570d1fbeb8f..cf3f7726f4760 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c @@ -783,9 +783,9 @@ static int sdma_v7_0_soft_reset(struct amdgpu_ip_block *ip_block) return sdma_v7_0_start(adev); } -static bool sdma_v7_0_check_soft_reset(void *handle) +static bool sdma_v7_0_check_soft_reset(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; struct amdgpu_ring *ring; int i, r; long tmo = msecs_to_jiffies(1000); diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c index 1a2b8dc4c3030..c9807afc102da 100644 --- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c @@ -380,9 +380,9 @@ static int tonga_ih_wait_for_idle(struct amdgpu_ip_block *ip_block) return -ETIMEDOUT; } -static bool tonga_ih_check_soft_reset(void *handle) +static bool tonga_ih_check_soft_reset(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; u32 srbm_soft_reset = 0; u32 tmp = RREG32(mmSRBM_STATUS); diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c index 502e609c8205f..45b83476ad78f 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c @@ -1163,9 +1163,9 @@ static int uvd_v6_0_wait_for_idle(struct amdgpu_ip_block *ip_block) } #define AMDGPU_UVD_STATUS_BUSY_MASK 0xfd -static bool uvd_v6_0_check_soft_reset(void *handle) +static bool uvd_v6_0_check_soft_reset(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; u32 srbm_soft_reset = 0; u32 tmp = RREG32(mmSRBM_STATUS); diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c index fcd4f477c3477..b4ed1a659d318 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c @@ -1483,9 +1483,9 @@ static int uvd_v7_0_wait_for_idle(struct amdgpu_ip_block *ip_block) } #define AMDGPU_UVD_STATUS_BUSY_MASK 0xfd -static bool uvd_v7_0_check_soft_reset(void *handle) +static bool uvd_v7_0_check_soft_reset(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; u32 srbm_soft_reset = 0; u32 tmp = RREG32(mmSRBM_STATUS); diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c index eccbea2bddafa..a6eff9fa96f04 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c @@ -626,9 +626,9 @@ static int vce_v3_0_wait_for_idle(struct amdgpu_ip_block *ip_block) #define AMDGPU_VCE_STATUS_BUSY_MASK (VCE_STATUS_VCPU_REPORT_AUTO_BUSY_MASK | \ VCE_STATUS_VCPU_REPORT_RB0_BUSY_MASK) -static bool vce_v3_0_check_soft_reset(void *handle) +static bool vce_v3_0_check_soft_reset(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; u32 srbm_soft_reset = 0; /* According to VCE team , we should use VCE_STATUS instead diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c index bf33d6d615861..8ec37c14f76c3 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c @@ -721,9 +721,9 @@ static int vce_v4_0_wait_for_idle(struct amdgpu_ip_block *ip_block) #define AMDGPU_VCE_STATUS_BUSY_MASK (VCE_STATUS_VCPU_REPORT_AUTO_BUSY_MASK | \ VCE_STATUS_VCPU_REPORT_RB0_BUSY_MASK) -static bool vce_v4_0_check_soft_reset(void *handle) +static bool vce_v4_0_check_soft_reset(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; u32 srbm_soft_reset = 0; /* According to VCE team , we should use VCE_STATUS instead diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index ae9ce0b94bb57..c02a7b2be968b 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -327,7 +327,7 @@ static int dm_wait_for_idle(struct amdgpu_ip_block *ip_block) return 0; } -static bool dm_check_soft_reset(void *handle) +static bool dm_check_soft_reset(struct amdgpu_ip_block *ip_block) { return false; } From a5898e743754c257f07151087c5eea7641a91b8f Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Thu, 26 Sep 2024 13:29:24 +0530 Subject: [PATCH 1735/1868] drm/amdgpu: update the handle ptr in late_init MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Update the ptr handle to amdgpu_ip_block ptr in all the functions of late_init function ptr. Signed-off-by: Sunil Khatri Reviewed-by: Christian König (cherry picked from commit 813dabea1d31e017d948bc93bde568aff870c00d) --- drivers/gpu/drm/amd/amdgpu/aldebaran.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 10 +++++----- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/nv.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c | 2 +- drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.c | 2 +- drivers/gpu/drm/amd/amdgpu/soc15.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/soc21.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/soc24.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vi.c | 4 ++-- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++-- drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c | 4 ++-- drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 4 ++-- drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c | 4 ++-- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 8 ++++++-- 33 files changed, 69 insertions(+), 65 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/aldebaran.c b/drivers/gpu/drm/amd/amdgpu/aldebaran.c index f99bf6bcec9d6..c1ff24335a0c5 100644 --- a/drivers/gpu/drm/amd/amdgpu/aldebaran.c +++ b/drivers/gpu/drm/amd/amdgpu/aldebaran.c @@ -304,7 +304,7 @@ static int aldebaran_mode2_restore_ip(struct amdgpu_device *adev) if (adev->ip_blocks[i].version->funcs->late_init) { r = adev->ip_blocks[i].version->funcs->late_init( - (void *)adev); + &adev->ip_blocks[i]); if (r) { dev_err(adev->dev, "late_init of IP block <%s> failed %d after reset\n", diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 47440d9bbb102..c8b2828b34713 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -3217,7 +3217,7 @@ static int amdgpu_device_ip_late_init(struct amdgpu_device *adev) if (!adev->ip_blocks[i].status.hw) continue; if (adev->ip_blocks[i].version->funcs->late_init) { - r = adev->ip_blocks[i].version->funcs->late_init((void *)adev); + r = adev->ip_blocks[i].version->funcs->late_init(&adev->ip_blocks[i]); if (r) { DRM_ERROR("late_init of IP block <%s> failed %d\n", adev->ip_blocks[i].version->funcs->name, r); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c index c061b0cee7476..ee99827d7b4d1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c @@ -784,9 +784,9 @@ static int umsch_mm_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int umsch_mm_late_init(void *handle) +static int umsch_mm_late_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (amdgpu_in_reset(adev) || adev->in_s0ix || adev->in_suspend) return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index 38013a542f1ad..fd1241033e430 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -7819,9 +7819,9 @@ static int gfx_v10_0_early_init(struct amdgpu_ip_block *ip_block) return gfx_v10_0_init_microcode(adev); } -static int gfx_v10_0_late_init(void *handle) +static int gfx_v10_0_late_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index db7d9bbe9eab7..d9fb3afef885c 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -5021,9 +5021,9 @@ static int gfx_v11_0_early_init(struct amdgpu_ip_block *ip_block) return gfx_v11_0_init_microcode(adev); } -static int gfx_v11_0_late_init(void *handle) +static int gfx_v11_0_late_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c index e36cdbd052581..ca7e0a88eb4ec 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c @@ -3717,9 +3717,9 @@ static int gfx_v12_0_early_init(struct amdgpu_ip_block *ip_block) return gfx_v12_0_init_microcode(adev); } -static int gfx_v12_0_late_init(void *handle) +static int gfx_v12_0_late_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index 1e101de505fc0..96356bbf09258 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -4151,9 +4151,9 @@ static int gfx_v7_0_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int gfx_v7_0_late_init(void *handle) +static int gfx_v7_0_late_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 546fa0c6cf4aa..bda0002977985 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -5371,9 +5371,9 @@ static int gfx_v8_0_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int gfx_v8_0_late_init(void *handle) +static int gfx_v8_0_late_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 9a769a9733ad1..afe5ea49204d6 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -4889,9 +4889,9 @@ static int gfx_v9_0_early_init(struct amdgpu_ip_block *ip_block) return gfx_v9_0_init_microcode(adev); } -static int gfx_v9_0_ecc_late_init(void *handle) +static int gfx_v9_0_ecc_late_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; /* @@ -4923,9 +4923,9 @@ static int gfx_v9_0_ecc_late_init(void *handle) return 0; } -static int gfx_v9_0_late_init(void *handle) +static int gfx_v9_0_late_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); @@ -4944,7 +4944,7 @@ static int gfx_v9_0_late_init(void *handle) if (r) return r; - r = gfx_v9_0_ecc_late_init(handle); + r = gfx_v9_0_ecc_late_init(ip_block); if (r) return r; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index 4678bf5606c75..e41a6421dcbee 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -2529,9 +2529,9 @@ static int gfx_v9_4_3_early_init(struct amdgpu_ip_block *ip_block) return gfx_v9_4_3_init_microcode(adev); } -static int gfx_v9_4_3_late_init(void *handle) +static int gfx_v9_4_3_late_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c index 301a42359ae1a..fe9112b612df5 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c @@ -650,9 +650,9 @@ static int gmc_v10_0_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int gmc_v10_0_late_init(void *handle) +static int gmc_v10_0_late_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; r = amdgpu_gmc_allocate_vm_inv_eng(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c index 749a2ed91a4f8..9a89e949dba48 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c @@ -621,9 +621,9 @@ static int gmc_v11_0_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int gmc_v11_0_late_init(void *handle) +static int gmc_v11_0_late_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; r = amdgpu_gmc_allocate_vm_inv_eng(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c index ba3bc3ed71070..fdaee0014b674 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c @@ -607,9 +607,9 @@ static int gmc_v12_0_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int gmc_v12_0_late_init(void *handle) +static int gmc_v12_0_late_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; r = amdgpu_gmc_allocate_vm_inv_eng(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c index c3a8a582bd56f..1fdb6feb168ab 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c @@ -782,9 +782,9 @@ static int gmc_v6_0_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int gmc_v6_0_late_init(void *handle) +static int gmc_v6_0_late_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS) return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c index a5b096e52e78a..9ec5433e79568 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c @@ -939,9 +939,9 @@ static int gmc_v7_0_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int gmc_v7_0_late_init(void *handle) +static int gmc_v7_0_late_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS) return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index 0f68ffb20c1b6..1fff8a5242226 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -1060,9 +1060,9 @@ static int gmc_v8_0_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int gmc_v8_0_late_init(void *handle) +static int gmc_v8_0_late_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS) return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index 23e7d366ab499..8943720395d39 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -1638,9 +1638,9 @@ static int gmc_v9_0_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int gmc_v9_0_late_init(void *handle) +static int gmc_v9_0_late_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; r = amdgpu_gmc_allocate_vm_inv_eng(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c index 30f09f78ae23c..2545a63a5d29c 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c @@ -1674,9 +1674,9 @@ static int mes_v11_0_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int mes_v11_0_late_init(void *handle) +static int mes_v11_0_late_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; /* it's only intended for use in mes_self_test case, not for s0ix and reset */ if (!amdgpu_in_reset(adev) && !adev->in_s0ix && !adev->in_suspend && diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c index 9d65f4f64476a..487d2fab5101e 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c @@ -1636,9 +1636,9 @@ static int mes_v12_0_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int mes_v12_0_late_init(void *handle) +static int mes_v12_0_late_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; /* it's only intended for use in mes_self_test case, not for s0ix and reset */ if (!amdgpu_in_reset(adev) && !adev->in_s0ix && !adev->in_suspend) diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index 373f2641cd255..176157b697fb2 100644 --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c @@ -944,9 +944,9 @@ static int nv_common_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int nv_common_late_init(void *handle) +static int nv_common_late_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (amdgpu_sriov_vf(adev)) { xgpu_nv_mailbox_get_irq(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index ff39a0c6c287f..519da8225c4ba 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c @@ -1781,9 +1781,9 @@ static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev, void *err_data, struct amdgpu_iv_entry *entry); -static int sdma_v4_0_late_init(void *handle) +static int sdma_v4_0_late_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; sdma_v4_0_setup_ulv(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c index 3f95cb232bb69..f9dc0b417f7d7 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c @@ -1318,9 +1318,9 @@ static int sdma_v4_4_2_process_ras_data_cb(struct amdgpu_device *adev, struct amdgpu_iv_entry *entry); #endif -static int sdma_v4_4_2_late_init(void *handle) +static int sdma_v4_4_2_late_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; #if 0 struct ras_ih_if ih_info = { .cb = sdma_v4_4_2_process_ras_data_cb, diff --git a/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c b/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c index 2ff6f11bddb66..475b7df3a9089 100644 --- a/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c +++ b/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c @@ -213,7 +213,7 @@ static int sienna_cichlid_mode2_restore_ip(struct amdgpu_device *adev) if (adev->ip_blocks[i].version->funcs->late_init) { r = adev->ip_blocks[i].version->funcs->late_init( - (void *)adev); + &adev->ip_blocks[i]); if (r) { dev_err(adev->dev, "late_init of IP block <%s> failed %d after reset\n", diff --git a/drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.c b/drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.c index 71a2770e2a31a..5ea9090b5040a 100644 --- a/drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.c +++ b/drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.c @@ -208,7 +208,7 @@ static int smu_v13_0_10_mode2_restore_ip(struct amdgpu_device *adev) if (adev->ip_blocks[i].version->funcs->late_init) { r = adev->ip_blocks[i].version->funcs->late_init( - (void *)adev); + &adev->ip_blocks[i]); if (r) { dev_err(adev->dev, "late_init of IP block <%s> failed %d after reset\n", diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index d63a88e3c4b74..b59d95c5bafbe 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -1202,9 +1202,9 @@ static int soc15_common_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int soc15_common_late_init(void *handle) +static int soc15_common_late_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (amdgpu_sriov_vf(adev)) xgpu_ai_mailbox_get_irq(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c index 89951073ec3a3..2b02b0916de0c 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc21.c +++ b/drivers/gpu/drm/amd/amdgpu/soc21.c @@ -794,9 +794,9 @@ static int soc21_common_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int soc21_common_late_init(void *handle) +static int soc21_common_late_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (amdgpu_sriov_vf(adev)) { xgpu_nv_mailbox_get_irq(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/soc24.c b/drivers/gpu/drm/amd/amdgpu/soc24.c index 546a67c44f19e..9efb1cce5bf31 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc24.c +++ b/drivers/gpu/drm/amd/amdgpu/soc24.c @@ -440,9 +440,9 @@ static int soc24_common_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int soc24_common_late_init(void *handle) +static int soc24_common_late_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (amdgpu_sriov_vf(adev)) xgpu_nv_mailbox_get_irq(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index 7ddd3b358d62f..4d5fb773a500f 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/drivers/gpu/drm/amd/amdgpu/vi.c @@ -1679,9 +1679,9 @@ static int vi_common_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int vi_common_late_init(void *handle) +static int vi_common_late_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (amdgpu_sriov_vf(adev)) xgpu_vi_mailbox_get_irq(adev); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index c02a7b2be968b..c90a543f5d827 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2629,9 +2629,9 @@ static int detect_mst_link_for_all_connectors(struct drm_device *dev) return ret; } -static int dm_late_init(void *handle) +static int dm_late_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; struct dmcu_iram_parameters params; unsigned int linear_lut[16]; diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c index cb2e8a1a5483b..af457b3724888 100644 --- a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c @@ -2965,10 +2965,10 @@ static int kv_dpm_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int kv_dpm_late_init(void *handle) +static int kv_dpm_late_init(struct amdgpu_ip_block *ip_block) { /* powerdown unused blocks for now */ - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (!adev->pm.dpm_enabled) return 0; diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c index f42726dd69682..7f01837182df3 100644 --- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c @@ -7621,10 +7621,10 @@ static int si_dpm_process_interrupt(struct amdgpu_device *adev, return 0; } -static int si_dpm_late_init(void *handle) +static int si_dpm_late_init(struct amdgpu_ip_block *ip_block) { int ret; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (!adev->pm.dpm_enabled) return 0; diff --git a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c index f65fb0ec7d599..588620d60e545 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c +++ b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c @@ -215,9 +215,9 @@ static void pp_reserve_vram_for_smu(struct amdgpu_device *adev) } } -static int pp_late_init(void *handle) +static int pp_late_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = handle; + struct amdgpu_device *adev = ip_block->adev; struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; if (hwmgr && hwmgr->pm_en) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index dd23ab0eeb2f4..746c1f896204e 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -826,9 +826,9 @@ static int smu_apply_default_config_table_settings(struct smu_context *smu) return smu_set_config_table(smu, &adev->pm.config_table); } -static int smu_late_init(void *handle) +static int smu_late_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; struct smu_context *smu = adev->powerplay.pp_handle; int ret = 0; @@ -2068,7 +2068,11 @@ static int smu_reset(struct smu_context *smu) if (ret) return ret; +<<<<<<< HEAD ret = smu_late_init(ip_block); +======= + ret = smu_late_init(&adev->ip_blocks[AMD_IP_BLOCK_TYPE_SMC]); +>>>>>>> 813dabea1d31 (drm/amdgpu: update the handle ptr in late_init) if (ret) return ret; From ef460dd9c74806bda0dcbad49170886a099864bb Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Thu, 26 Sep 2024 14:30:28 +0530 Subject: [PATCH 1736/1868] drm/amdgpu: update the handle ptr in sw_init MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit update the *handle to amdgpu_ip_block ptr for all functions pointers of sw_init. Signed-off-by: Sunil Khatri Reviewed-by: Christian König (cherry picked from commit 2fba0a3d7c5adaea379e4a622c5b43292b3a37de) --- drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/cik.c | 2 +- drivers/gpu/drm/amd/amdgpu/cik_ih.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/cz_ih.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/iceland_ih.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/ih_v6_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/ih_v6_1.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/ih_v7_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.h | 2 +- drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/nv.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/si.c | 2 +- drivers/gpu/drm/amd/amdgpu/si_dma.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/si_ih.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/soc15.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/soc21.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/soc24.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vega20_ih.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vi.c | 4 ++-- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++-- drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c | 5 ++--- drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 4 ++-- drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c | 4 ++-- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 4 ++-- 86 files changed, 168 insertions(+), 169 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c index 235772073f3e5..ba5aa38dd12b5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c @@ -101,9 +101,9 @@ enum { ACP_TILE_DSP2, }; -static int acp_sw_init(void *handle) +static int acp_sw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; adev->acp.parent = adev->dev; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index c8b2828b34713..5fbcd0d42551b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -2872,7 +2872,7 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev) for (i = 0; i < adev->num_ip_blocks; i++) { if (!adev->ip_blocks[i].status.valid) continue; - r = adev->ip_blocks[i].version->funcs->sw_init((void *)adev); + r = adev->ip_blocks[i].version->funcs->sw_init(&adev->ip_blocks[i]); if (r) { DRM_ERROR("sw_init of IP block <%s> failed %d\n", adev->ip_blocks[i].version->funcs->name, r); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c index 527da07cb4cc4..cf621bd518ffe 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c @@ -33,7 +33,7 @@ #include "isp_v4_1_0.h" #include "isp_v4_1_1.h" -static int isp_sw_init(void *handle) +static int isp_sw_init(struct amdgpu_ip_block *ip_block) { return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index ec2a205dcca87..6a4fc7953c95b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -421,9 +421,9 @@ static bool psp_get_runtime_db_entry(struct amdgpu_device *adev, return ret; } -static int psp_sw_init(void *handle) +static int psp_sw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; struct psp_context *psp = &adev->psp; int ret; struct psp_runtime_boot_cfg_entry boot_cfg_entry; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c index ee99827d7b4d1..71eda4e2279a5 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c @@ -794,9 +794,9 @@ static int umsch_mm_late_init(struct amdgpu_ip_block *ip_block) return umsch_mm_test(adev); } -static int umsch_mm_sw_init(void *handle) +static int umsch_mm_sw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; r = umsch_mm_init(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c index 6ec5b624a3ef1..7fc9d5e415845 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c @@ -637,10 +637,10 @@ const struct drm_mode_config_funcs amdgpu_vkms_mode_funcs = { .atomic_commit = drm_atomic_helper_commit, }; -static int amdgpu_vkms_sw_init(void *handle) +static int amdgpu_vkms_sw_init(struct amdgpu_ip_block *ip_block) { int r, i; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; adev->amdgpu_vkms_output = kcalloc(adev->mode_info.num_crtc, sizeof(struct amdgpu_vkms_output), GFP_KERNEL); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c index 46c86b284220f..9a3fe6856ac5d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c @@ -356,9 +356,9 @@ static int vpe_common_init(struct amdgpu_vpe *vpe) return 0; } -static int vpe_sw_init(void *handle) +static int vpe_sw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; struct amdgpu_vpe *vpe = &adev->vpe; int ret; diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c index e95f8e29d631c..a4d67fda11f2f 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik.c +++ b/drivers/gpu/drm/amd/amdgpu/cik.c @@ -2124,7 +2124,7 @@ static int cik_common_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int cik_common_sw_init(void *handle) +static int cik_common_sw_init(struct amdgpu_ip_block *ip_block) { return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c index b259f969580e6..717e68acacf50 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c @@ -297,10 +297,10 @@ static int cik_ih_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int cik_ih_sw_init(void *handle) +static int cik_ih_sw_init(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, false); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c index ed527b02c4213..c58a66d30130e 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c @@ -937,10 +937,10 @@ static int cik_sdma_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int cik_sdma_sw_init(void *handle) +static int cik_sdma_sw_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_ring *ring; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r, i; /* SDMA trap event */ diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c index b555afd6eb96e..526866d68a0ad 100644 --- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c @@ -288,10 +288,10 @@ static int cz_ih_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int cz_ih_sw_init(void *handle) +static int cz_ih_sw_init(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, false); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index 4581e8eebccd1..bc015ad84331b 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -2775,10 +2775,10 @@ static int dce_v10_0_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int dce_v10_0_sw_init(void *handle) +static int dce_v10_0_sw_init(struct amdgpu_ip_block *ip_block) { int r, i; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; for (i = 0; i < adev->mode_info.num_crtc; i++) { r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + 1, &adev->crtc_irq); diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index 986c589e37da7..c9cf1983403b5 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -2901,10 +2901,10 @@ static int dce_v11_0_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int dce_v11_0_sw_init(void *handle) +static int dce_v11_0_sw_init(struct amdgpu_ip_block *ip_block) { int r, i; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; for (i = 0; i < adev->mode_info.num_crtc; i++) { r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + 1, &adev->crtc_irq); diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c index e98639d7305c4..7b7a87627d9c9 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c @@ -2674,11 +2674,11 @@ static int dce_v6_0_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int dce_v6_0_sw_init(void *handle) +static int dce_v6_0_sw_init(struct amdgpu_ip_block *ip_block) { int r, i; bool ret; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; for (i = 0; i < adev->mode_info.num_crtc; i++) { r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + 1, &adev->crtc_irq); diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index f00f5be74b258..56fdde489cdec 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -2689,10 +2689,10 @@ static int dce_v8_0_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int dce_v8_0_sw_init(void *handle) +static int dce_v8_0_sw_init(struct amdgpu_ip_block *ip_block) { int r, i; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; for (i = 0; i < adev->mode_info.num_crtc; i++) { r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + 1, &adev->crtc_irq); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index fd1241033e430..acb93a6eccde9 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -4683,11 +4683,11 @@ static void gfx_v10_0_alloc_ip_dump(struct amdgpu_device *adev) } } -static int gfx_v10_0_sw_init(void *handle) +static int gfx_v10_0_sw_init(struct amdgpu_ip_block *ip_block) { int i, j, k, r, ring_id = 0; int xcc_id = 0; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { case IP_VERSION(10, 1, 10): diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index d9fb3afef885c..c4fff777a0bef 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -1536,11 +1536,11 @@ static void gfx_v11_0_alloc_ip_dump(struct amdgpu_device *adev) } } -static int gfx_v11_0_sw_init(void *handle) +static int gfx_v11_0_sw_init(struct amdgpu_ip_block *ip_block) { int i, j, k, r, ring_id = 0; int xcc_id = 0; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { case IP_VERSION(11, 0, 0): diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c index ca7e0a88eb4ec..9c0d375965c2f 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c @@ -1319,12 +1319,12 @@ static void gfx_v12_0_alloc_ip_dump(struct amdgpu_device *adev) } } -static int gfx_v12_0_sw_init(void *handle) +static int gfx_v12_0_sw_init(struct amdgpu_ip_block *ip_block) { int i, j, k, r, ring_id = 0; unsigned num_compute_rings; int xcc_id = 0; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { case IP_VERSION(12, 0, 0): diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c index 4ce1013c22e39..6e243ae07bdff 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c @@ -3039,10 +3039,10 @@ static int gfx_v6_0_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int gfx_v6_0_sw_init(void *handle) +static int gfx_v6_0_sw_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_ring *ring; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i, r; r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index 96356bbf09258..927a0baf8de22 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -4343,10 +4343,10 @@ static int gfx_v7_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, return 0; } -static int gfx_v7_0_sw_init(void *handle) +static int gfx_v7_0_sw_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_ring *ring; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i, j, k, r, ring_id; switch (adev->asic_type) { diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index bda0002977985..80b39b8794e46 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -1894,12 +1894,12 @@ static int gfx_v8_0_compute_ring_init(struct amdgpu_device *adev, int ring_id, static void gfx_v8_0_sq_irq_work_func(struct work_struct *work); -static int gfx_v8_0_sw_init(void *handle) +static int gfx_v8_0_sw_init(struct amdgpu_ip_block *ip_block) { int i, j, k, r, ring_id; int xcc_id = 0; struct amdgpu_ring *ring; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; switch (adev->asic_type) { case CHIP_TONGA: diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index afe5ea49204d6..3045a2dac99b4 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -2198,12 +2198,12 @@ static void gfx_v9_0_alloc_ip_dump(struct amdgpu_device *adev) } } -static int gfx_v9_0_sw_init(void *handle) +static int gfx_v9_0_sw_init(struct amdgpu_ip_block *ip_block) { int i, j, k, r, ring_id; int xcc_id = 0; struct amdgpu_ring *ring; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; unsigned int hw_prio; switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index e41a6421dcbee..7520f8a241b58 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -1049,10 +1049,10 @@ static void gfx_v9_4_3_alloc_ip_dump(struct amdgpu_device *adev) } } -static int gfx_v9_4_3_sw_init(void *handle) +static int gfx_v9_4_3_sw_init(struct amdgpu_ip_block *ip_block) { int i, j, k, r, ring_id, xcc_id, num_xcc; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { case IP_VERSION(9, 4, 3): diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c index fe9112b612df5..106c9fc7308ff 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c @@ -767,10 +767,10 @@ static int gmc_v10_0_gart_init(struct amdgpu_device *adev) return amdgpu_gart_table_vram_alloc(adev); } -static int gmc_v10_0_sw_init(void *handle) +static int gmc_v10_0_sw_init(struct amdgpu_ip_block *ip_block) { int r, vram_width = 0, vram_type = 0, vram_vendor = 0; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; adev->gfxhub.funcs->init(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c index 9a89e949dba48..3c62b755e3264 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c @@ -727,10 +727,10 @@ static int gmc_v11_0_gart_init(struct amdgpu_device *adev) return amdgpu_gart_table_vram_alloc(adev); } -static int gmc_v11_0_sw_init(void *handle) +static int gmc_v11_0_sw_init(struct amdgpu_ip_block *ip_block) { int r, vram_width = 0, vram_type = 0, vram_vendor = 0; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; adev->mmhub.funcs->init(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c index fdaee0014b674..5111a054fbb0a 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c @@ -714,10 +714,10 @@ static int gmc_v12_0_gart_init(struct amdgpu_device *adev) return amdgpu_gart_table_vram_alloc(adev); } -static int gmc_v12_0_sw_init(void *handle) +static int gmc_v12_0_sw_init(struct amdgpu_ip_block *ip_block) { int r, vram_width = 0, vram_type = 0, vram_vendor = 0; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; adev->mmhub.funcs->init(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c index 1fdb6feb168ab..00b81c1924e3b 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c @@ -809,10 +809,10 @@ static unsigned int gmc_v6_0_get_vbios_fb_size(struct amdgpu_device *adev) return size; } -static int gmc_v6_0_sw_init(void *handle) +static int gmc_v6_0_sw_init(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c index 9ec5433e79568..d54430e44b194 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c @@ -967,10 +967,10 @@ static unsigned int gmc_v7_0_get_vbios_fb_size(struct amdgpu_device *adev) return size; } -static int gmc_v7_0_sw_init(void *handle) +static int gmc_v7_0_sw_init(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index 1fff8a5242226..e459f342bde1e 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -1090,10 +1090,10 @@ static unsigned int gmc_v8_0_get_vbios_fb_size(struct amdgpu_device *adev) #define mmMC_SEQ_MISC0_FIJI 0xA71 -static int gmc_v8_0_sw_init(void *handle) +static int gmc_v8_0_sw_init(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index 8943720395d39..179689190f923 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -2024,10 +2024,10 @@ static void gmc_v9_4_3_init_vram_info(struct amdgpu_device *adev) adev->gmc.vram_width = 128 * 64; } -static int gmc_v9_0_sw_init(void *handle) +static int gmc_v9_0_sw_init(struct amdgpu_ip_block *ip_block) { int r, vram_width = 0, vram_type = 0, vram_vendor = 0, dma_addr_bits; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; unsigned long inst_mask = adev->aid_mask; adev->gfxhub.funcs->init(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c index 570efe59111f3..aaf59915dbfa2 100644 --- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c @@ -287,10 +287,10 @@ static int iceland_ih_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int iceland_ih_sw_init(void *handle) +static int iceland_ih_sw_init(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, false); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c index 51284ca9c827c..e0c55d282f7cc 100644 --- a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c @@ -568,10 +568,10 @@ static int ih_v6_0_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int ih_v6_0_sw_init(void *handle) +static int ih_v6_0_sw_init(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; bool use_bus_addr; r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_IH, 0, diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c index c4fd5454ddfd6..f9bab7005bf3a 100644 --- a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c +++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c @@ -547,10 +547,10 @@ static int ih_v6_1_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int ih_v6_1_sw_init(void *handle) +static int ih_v6_1_sw_init(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; bool use_bus_addr; r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_IH, 0, diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c index de830824fa0b5..533e408f4dd0f 100644 --- a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c @@ -537,10 +537,10 @@ static int ih_v7_0_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int ih_v7_0_sw_init(void *handle) +static int ih_v7_0_sw_init(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; bool use_bus_addr; r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_IH, 0, diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c index 8effd6dc65d41..24ac589f200a7 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c @@ -481,9 +481,9 @@ int jpeg_v1_0_early_init(struct amdgpu_ip_block *ip_block) * @handle: amdgpu_device pointer * */ -int jpeg_v1_0_sw_init(void *handle) +int jpeg_v1_0_sw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; struct amdgpu_ring *ring; int r; diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.h b/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.h index 791de235cd8bd..d978422ddbd76 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.h +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.h @@ -25,7 +25,7 @@ #define __JPEG_V1_0_H__ int jpeg_v1_0_early_init(struct amdgpu_ip_block *ip_block); -int jpeg_v1_0_sw_init(void *handle); +int jpeg_v1_0_sw_init(struct amdgpu_ip_block *ip_block); void jpeg_v1_0_sw_fini(void *handle); void jpeg_v1_0_start(struct amdgpu_device *adev, int mode); diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c index 34361c6d4c502..aa2d3e5a7f96d 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c @@ -65,9 +65,9 @@ static int jpeg_v2_0_early_init(struct amdgpu_ip_block *ip_block) * * Load firmware and sw initialization */ -static int jpeg_v2_0_sw_init(void *handle) +static int jpeg_v2_0_sw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; struct amdgpu_ring *ring; int r; diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c index 5c0e49ae452cf..a53c3d53ec160 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c @@ -85,11 +85,11 @@ static int jpeg_v2_5_early_init(struct amdgpu_ip_block *ip_block) * * Load firmware and sw initialization */ -static int jpeg_v2_5_sw_init(void *handle) +static int jpeg_v2_5_sw_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_ring *ring; int i, r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { if (adev->jpeg.harvest_config & (1 << i)) diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c index 23d24db76a76d..54ebf29f3b8c2 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c @@ -79,9 +79,9 @@ static int jpeg_v3_0_early_init(struct amdgpu_ip_block *ip_block) * * Load firmware and sw initialization */ -static int jpeg_v3_0_sw_init(void *handle) +static int jpeg_v3_0_sw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; struct amdgpu_ring *ring; int r; diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c index ad30e3f7578ad..bb460a6753b76 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c @@ -74,9 +74,9 @@ static int jpeg_v4_0_early_init(struct amdgpu_ip_block *ip_block) * * Load firmware and sw initialization */ -static int jpeg_v4_0_sw_init(void *handle) +static int jpeg_v4_0_sw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; struct amdgpu_ring *ring; int r; diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c index 1940a79db1ce0..c8a27f4e2e5d4 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c @@ -92,9 +92,9 @@ static int jpeg_v4_0_3_early_init(struct amdgpu_ip_block *ip_block) * * Load firmware and sw initialization */ -static int jpeg_v4_0_3_sw_init(void *handle) +static int jpeg_v4_0_3_sw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; struct amdgpu_ring *ring; int i, j, r, jpeg_inst; diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c index a3ac5ad40eab7..cdb6fde4bd512 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c @@ -98,9 +98,9 @@ static int jpeg_v4_0_5_early_init(struct amdgpu_ip_block *ip_block) * * Load firmware and sw initialization */ -static int jpeg_v4_0_5_sw_init(void *handle) +static int jpeg_v4_0_5_sw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; struct amdgpu_ring *ring; int r, i; diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c index 5a102dab87da9..ec468458f583d 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c @@ -66,9 +66,9 @@ static int jpeg_v5_0_0_early_init(struct amdgpu_ip_block *ip_block) * * Load firmware and sw initialization */ -static int jpeg_v5_0_0_sw_init(void *handle) +static int jpeg_v5_0_0_sw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; struct amdgpu_ring *ring; int r; diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c index 2545a63a5d29c..ea3da196bfa7e 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c @@ -1361,9 +1361,9 @@ static int mes_v11_0_mqd_sw_init(struct amdgpu_device *adev, return 0; } -static int mes_v11_0_sw_init(void *handle) +static int mes_v11_0_sw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int pipe, r; adev->mes.funcs = &mes_v11_0_funcs; diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c index 487d2fab5101e..c1d4984c37918 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c @@ -1326,9 +1326,9 @@ static int mes_v12_0_mqd_sw_init(struct amdgpu_device *adev, return 0; } -static int mes_v12_0_sw_init(void *handle) +static int mes_v12_0_sw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int pipe, r; adev->mes.funcs = &mes_v12_0_funcs; diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c index 58d0a74842b7c..eb2e11bf2fb83 100644 --- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c @@ -551,10 +551,10 @@ static int navi10_ih_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int navi10_ih_sw_init(void *handle) +static int navi10_ih_sw_init(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; bool use_bus_addr; r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0, diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index 176157b697fb2..080d8fb3ea818 100644 --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c @@ -973,9 +973,9 @@ static int nv_common_late_init(struct amdgpu_ip_block *ip_block) return 0; } -static int nv_common_sw_init(void *handle) +static int nv_common_sw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (amdgpu_sriov_vf(adev)) xgpu_nv_mailbox_add_irq_id(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c index 4dc507c67d1e7..34081989e4888 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c @@ -826,11 +826,11 @@ static int sdma_v2_4_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int sdma_v2_4_sw_init(void *handle) +static int sdma_v2_4_sw_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_ring *ring; int r, i; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; /* SDMA trap event */ r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_TRAP, diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c index ca2d3212bb424..f4f5cb8542798 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c @@ -1106,11 +1106,11 @@ static int sdma_v3_0_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int sdma_v3_0_sw_init(void *handle) +static int sdma_v3_0_sw_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_ring *ring; int r, i; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; /* SDMA trap event */ r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_TRAP, diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index 519da8225c4ba..4f9638cb2cdfe 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c @@ -1793,11 +1793,11 @@ static int sdma_v4_0_late_init(struct amdgpu_ip_block *ip_block) return 0; } -static int sdma_v4_0_sw_init(void *handle) +static int sdma_v4_0_sw_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_ring *ring; int r, i; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_4_0); uint32_t *ptr; diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c index f9dc0b417f7d7..da0ab9df3f6bc 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c @@ -1332,11 +1332,11 @@ static int sdma_v4_4_2_late_init(struct amdgpu_ip_block *ip_block) return 0; } -static int sdma_v4_4_2_sw_init(void *handle) +static int sdma_v4_4_2_sw_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_ring *ring; int r, i; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; u32 aid_id; uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_4_4_2); uint32_t *ptr; diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c index fd769a576a2bd..12c71d9cde75a 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c @@ -1408,11 +1408,11 @@ static int sdma_v5_0_early_init(struct amdgpu_ip_block *ip_block) } -static int sdma_v5_0_sw_init(void *handle) +static int sdma_v5_0_sw_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_ring *ring; int r, i; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_5_0); uint32_t *ptr; diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c index 56146075928c3..575b72e3940ba 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c @@ -1319,11 +1319,11 @@ static unsigned sdma_v5_2_seq_to_trap_id(int seq_num) return -EINVAL; } -static int sdma_v5_2_sw_init(void *handle) +static int sdma_v5_2_sw_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_ring *ring; int r, i; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_5_2); uint32_t *ptr; diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c index 47c8edb4d5a0c..7692c9942259c 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c @@ -1313,11 +1313,11 @@ static int sdma_v6_0_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int sdma_v6_0_sw_init(void *handle) +static int sdma_v6_0_sw_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_ring *ring; int r, i; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_6_0); uint32_t *ptr; diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c index cf3f7726f4760..a0029c1d164c3 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c @@ -1273,11 +1273,11 @@ static int sdma_v7_0_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int sdma_v7_0_sw_init(void *handle) +static int sdma_v7_0_sw_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_ring *ring; int r, i; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; uint32_t reg_count = ARRAY_SIZE(sdma_reg_list_7_0); uint32_t *ptr; diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c index 75634c23a4db7..54efbb032da19 100644 --- a/drivers/gpu/drm/amd/amdgpu/si.c +++ b/drivers/gpu/drm/amd/amdgpu/si.c @@ -2148,7 +2148,7 @@ static int si_common_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int si_common_sw_init(void *handle) +static int si_common_sw_init(struct amdgpu_ip_block *ip_block) { return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c index 46e6273aeb1f0..5991649ef540c 100644 --- a/drivers/gpu/drm/amd/amdgpu/si_dma.c +++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c @@ -471,11 +471,11 @@ static int si_dma_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int si_dma_sw_init(void *handle) +static int si_dma_sw_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_ring *ring; int r, i; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; /* DMA0 trap event */ r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 224, diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c b/drivers/gpu/drm/amd/amdgpu/si_ih.c index 3afbb47242ccd..5291641ad7990 100644 --- a/drivers/gpu/drm/amd/amdgpu/si_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c @@ -165,10 +165,10 @@ static int si_ih_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int si_ih_sw_init(void *handle) +static int si_ih_sw_init(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, false); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index b59d95c5bafbe..64e16d7a75f80 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -1217,9 +1217,9 @@ static int soc15_common_late_init(struct amdgpu_ip_block *ip_block) return 0; } -static int soc15_common_sw_init(void *handle) +static int soc15_common_sw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (amdgpu_sriov_vf(adev)) xgpu_ai_mailbox_add_irq_id(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c index 2b02b0916de0c..d0d7cd17c7832 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc21.c +++ b/drivers/gpu/drm/amd/amdgpu/soc21.c @@ -832,9 +832,9 @@ static int soc21_common_late_init(struct amdgpu_ip_block *ip_block) return 0; } -static int soc21_common_sw_init(void *handle) +static int soc21_common_sw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (amdgpu_sriov_vf(adev)) xgpu_nv_mailbox_add_irq_id(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/soc24.c b/drivers/gpu/drm/amd/amdgpu/soc24.c index 9efb1cce5bf31..0fe572335b2a6 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc24.c +++ b/drivers/gpu/drm/amd/amdgpu/soc24.c @@ -455,9 +455,9 @@ static int soc24_common_late_init(struct amdgpu_ip_block *ip_block) return 0; } -static int soc24_common_sw_init(void *handle) +static int soc24_common_sw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (amdgpu_sriov_vf(adev)) xgpu_nv_mailbox_add_irq_id(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c index c9807afc102da..c0c008251bf0c 100644 --- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c @@ -297,10 +297,10 @@ static int tonga_ih_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int tonga_ih_sw_init(void *handle) +static int tonga_ih_sw_init(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 64 * 1024, true); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c index ad148a7cf3424..341f6ae68b08c 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c @@ -542,10 +542,10 @@ static int uvd_v3_1_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int uvd_v3_1_sw_init(void *handle) +static int uvd_v3_1_sw_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_ring *ring; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; void *ptr; uint32_t ucode_len; diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c index 7e5ef65566d9b..dd63bad21d181 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c @@ -101,10 +101,10 @@ static int uvd_v4_2_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int uvd_v4_2_sw_init(void *handle) +static int uvd_v4_2_sw_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_ring *ring; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; /* UVD TRAP */ diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c index 7a78e3ef54b53..f83ecc092e721 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c @@ -99,10 +99,10 @@ static int uvd_v5_0_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int uvd_v5_0_sw_init(void *handle) +static int uvd_v5_0_sw_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_ring *ring; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; /* UVD TRAP */ diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c index 45b83476ad78f..4b8d81bf19314 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c @@ -375,11 +375,11 @@ static int uvd_v6_0_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int uvd_v6_0_sw_init(void *handle) +static int uvd_v6_0_sw_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_ring *ring; int i, r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; /* UVD TRAP */ r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE, &adev->uvd.inst->irq); diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c index b4ed1a659d318..63e8cd5d282d0 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c @@ -395,12 +395,12 @@ static int uvd_v7_0_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int uvd_v7_0_sw_init(void *handle) +static int uvd_v7_0_sw_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_ring *ring; int i, j, r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; for (j = 0; j < adev->uvd.num_uvd_inst; j++) { if (adev->uvd.harvest_config & (1 << j)) diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c index bb0c390b6a1da..0f65d4ea63d03 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c @@ -416,11 +416,11 @@ static int vce_v2_0_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int vce_v2_0_sw_init(void *handle) +static int vce_v2_0_sw_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_ring *ring; int r, i; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; /* VCE */ r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 167, &adev->vce.irq); diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c index a6eff9fa96f04..8124f8cd8cc74 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c @@ -415,9 +415,9 @@ static int vce_v3_0_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int vce_v3_0_sw_init(void *handle) +static int vce_v3_0_sw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; struct amdgpu_ring *ring; int r, i; diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c index 8ec37c14f76c3..b3532240da015 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c @@ -422,9 +422,9 @@ static int vce_v4_0_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int vce_v4_0_sw_init(void *handle) +static int vce_v4_0_sw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; struct amdgpu_ring *ring; unsigned size; diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index cf6eb9d9b692c..ea20d16e173f9 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c @@ -122,13 +122,13 @@ static int vcn_v1_0_early_init(struct amdgpu_ip_block *ip_block) * * Load firmware and sw initialization */ -static int vcn_v1_0_sw_init(void *handle) +static int vcn_v1_0_sw_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_ring *ring; int i, r; uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_1_0); uint32_t *ptr; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; /* VCN DEC TRAP */ r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, @@ -197,7 +197,7 @@ static int vcn_v1_0_sw_init(void *handle) amdgpu_vcn_fwlog_init(adev->vcn.inst); } - r = jpeg_v1_0_sw_init(handle); + r = jpeg_v1_0_sw_init(ip_block); /* Allocate memory for VCN IP Dump buffer */ ptr = kcalloc(adev->vcn.num_vcn_inst * reg_count, sizeof(uint32_t), GFP_KERNEL); diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c index 7334e307845d7..a66cad2667dba 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c @@ -128,13 +128,13 @@ static int vcn_v2_0_early_init(struct amdgpu_ip_block *ip_block) * * Load firmware and sw initialization */ -static int vcn_v2_0_sw_init(void *handle) +static int vcn_v2_0_sw_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_ring *ring; int i, r; uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_0); uint32_t *ptr; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; volatile struct amdgpu_fw_shared *fw_shared; /* VCN DEC TRAP */ diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c index bbb56951f83e3..b070f73453177 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c @@ -155,13 +155,13 @@ static int vcn_v2_5_early_init(struct amdgpu_ip_block *ip_block) * * Load firmware and sw initialization */ -static int vcn_v2_5_sw_init(void *handle) +static int vcn_v2_5_sw_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_ring *ring; int i, j, r; uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_2_5); uint32_t *ptr; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; for (j = 0; j < adev->vcn.num_vcn_inst; j++) { if (adev->vcn.harvest_config & (1 << j)) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c index 5e970f959962e..083e4f9c4520c 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c @@ -157,14 +157,14 @@ static int vcn_v3_0_early_init(struct amdgpu_ip_block *ip_block) * * Load firmware and sw initialization */ -static int vcn_v3_0_sw_init(void *handle) +static int vcn_v3_0_sw_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_ring *ring; int i, j, r; int vcn_doorbell_index = 0; uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_3_0); uint32_t *ptr; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; r = amdgpu_vcn_sw_init(adev); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c index f7abddacd394c..99c2b594c6872 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c @@ -168,10 +168,10 @@ static int vcn_v4_0_fw_shared_init(struct amdgpu_device *adev, int inst_idx) * * Load firmware and sw initialization */ -static int vcn_v4_0_sw_init(void *handle) +static int vcn_v4_0_sw_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_ring *ring; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i, r; uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0); uint32_t *ptr; diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c index 090d51f849a09..2c32825172efb 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c @@ -123,9 +123,9 @@ static int vcn_v4_0_3_early_init(struct amdgpu_ip_block *ip_block) * * Load firmware and sw initialization */ -static int vcn_v4_0_3_sw_init(void *handle) +static int vcn_v4_0_3_sw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; struct amdgpu_ring *ring; int i, r, vcn_inst; uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_3); diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c index 4094507a03074..695e53184faa0 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c @@ -128,10 +128,10 @@ static int vcn_v4_0_5_early_init(struct amdgpu_ip_block *ip_block) * * Load firmware and sw initialization */ -static int vcn_v4_0_5_sw_init(void *handle) +static int vcn_v4_0_5_sw_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_ring *ring; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i, r; uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_4_0_5); uint32_t *ptr; diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c index eb63b6d4a9342..795ab0256948c 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c @@ -112,10 +112,10 @@ static int vcn_v5_0_0_early_init(struct amdgpu_ip_block *ip_block) * * Load firmware and sw initialization */ -static int vcn_v5_0_0_sw_init(void *handle) +static int vcn_v5_0_0_sw_init(struct amdgpu_ip_block *ip_block) { struct amdgpu_ring *ring; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i, r; uint32_t reg_count = ARRAY_SIZE(vcn_reg_list_5_0); uint32_t *ptr; diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c index 26da7a1881b55..781845811f700 100644 --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c @@ -481,9 +481,9 @@ static int vega10_ih_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int vega10_ih_sw_init(void *handle) +static int vega10_ih_sw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_IH, 0, diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c index 1cbfc5188f9b7..b90f553faafa6 100644 --- a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c @@ -535,9 +535,9 @@ static int vega20_ih_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int vega20_ih_sw_init(void *handle) +static int vega20_ih_sw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; bool use_bus_addr = true; int r; diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index 4d5fb773a500f..e67c5f1fe32ed 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/drivers/gpu/drm/amd/amdgpu/vi.c @@ -1689,9 +1689,9 @@ static int vi_common_late_init(struct amdgpu_ip_block *ip_block) return 0; } -static int vi_common_sw_init(void *handle) +static int vi_common_sw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (amdgpu_sriov_vf(adev)) xgpu_vi_mailbox_add_irq_id(adev); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index c90a543f5d827..f491de05ca572 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2541,9 +2541,9 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev) return 0; } -static int dm_sw_init(void *handle) +static int dm_sw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; adev->dm.cgs_device = amdgpu_cgs_create_device(adev); diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c index af457b3724888..5e840528eaa9c 100644 --- a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c @@ -2979,11 +2979,10 @@ static int kv_dpm_late_init(struct amdgpu_ip_block *ip_block) return 0; } -static int kv_dpm_sw_init(void *handle) +static int kv_dpm_sw_init(struct amdgpu_ip_block *ip_block) { int ret; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; - + struct amdgpu_device *adev = ip_block->adev; ret = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 230, &adev->pm.dpm.thermal.irq); if (ret) diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c index 7f01837182df3..9f140b6e7b320 100644 --- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c @@ -7718,10 +7718,10 @@ static int si_dpm_init_microcode(struct amdgpu_device *adev) return err; } -static int si_dpm_sw_init(void *handle) +static int si_dpm_sw_init(struct amdgpu_ip_block *ip_block) { int ret; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; ret = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 230, &adev->pm.dpm.thermal.irq); if (ret) diff --git a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c index 588620d60e545..70e78e64bee0d 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c +++ b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c @@ -130,9 +130,9 @@ static void pp_swctf_delayed_work_handler(struct work_struct *work) orderly_poweroff(true); } -static int pp_sw_init(void *handle) +static int pp_sw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = handle; + struct amdgpu_device *adev = ip_block->adev; struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; int ret = 0; diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 746c1f896204e..14c0db494388f 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -1235,9 +1235,9 @@ static void smu_init_xgmi_plpd_mode(struct smu_context *smu) } } -static int smu_sw_init(void *handle) +static int smu_sw_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; struct smu_context *smu = adev->powerplay.pp_handle; int ret; From f8abf3453886bfa8dbd9bdeab1f367677a161464 Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Thu, 26 Sep 2024 20:47:32 +0530 Subject: [PATCH 1737/1868] drm/amdgpu: update the handle ptr in sw_fini MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit update the *handle to amdgpu_ip_block ptr for all functions pointers of sw_fini. Signed-off-by: Sunil Khatri Reviewed-by: Christian König (cherry picked from commit 61d2447378e39384db75115bb8575fa2ca0cbc69) --- drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/cik.c | 2 +- drivers/gpu/drm/amd/amdgpu/cik_ih.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/cz_ih.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/iceland_ih.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/ih_v6_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/ih_v6_1.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/ih_v7_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.h | 2 +- drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/navi10_ih.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/nv.c | 2 +- drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/si.c | 2 +- drivers/gpu/drm/amd/amdgpu/si_dma.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/si_ih.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/soc15.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/soc21.c | 2 +- drivers/gpu/drm/amd/amdgpu/soc24.c | 2 +- drivers/gpu/drm/amd/amdgpu/tonga_ih.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vce_v3_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vce_v4_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c | 6 +++--- drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vega10_ih.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vega20_ih.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vi.c | 2 +- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++-- drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c | 4 ++-- drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 4 ++-- drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c | 4 ++-- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 4 ++-- 86 files changed, 164 insertions(+), 164 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c index ba5aa38dd12b5..baefcc21d7973 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c @@ -115,9 +115,9 @@ static int acp_sw_init(struct amdgpu_ip_block *ip_block) return 0; } -static int acp_sw_fini(void *handle) +static int acp_sw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (adev->acp.cgs_device) amdgpu_cgs_destroy_device(adev->acp.cgs_device); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 5fbcd0d42551b..7ec8f46640ec1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -3399,7 +3399,7 @@ static int amdgpu_device_ip_fini(struct amdgpu_device *adev) amdgpu_seq64_fini(adev); } - r = adev->ip_blocks[i].version->funcs->sw_fini((void *)adev); + r = adev->ip_blocks[i].version->funcs->sw_fini(&adev->ip_blocks[i]); /* XXX handle errors */ if (r) { DRM_DEBUG("sw_fini of IP block <%s> failed %d\n", diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c index cf621bd518ffe..5a919dae8d8eb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c @@ -38,7 +38,7 @@ static int isp_sw_init(struct amdgpu_ip_block *ip_block) return 0; } -static int isp_sw_fini(void *handle) +static int isp_sw_fini(struct amdgpu_ip_block *ip_block) { return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c index 6a4fc7953c95b..0b1e280ee2289 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -527,9 +527,9 @@ static int psp_sw_init(struct amdgpu_ip_block *ip_block) return ret; } -static int psp_sw_fini(void *handle) +static int psp_sw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; struct psp_context *psp = &adev->psp; struct psp_gfx_cmd_resp *cmd = psp->cmd; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c index 71eda4e2279a5..3ef75f1a47f65 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c @@ -815,9 +815,9 @@ static int umsch_mm_sw_init(struct amdgpu_ip_block *ip_block) return 0; } -static int umsch_mm_sw_fini(void *handle) +static int umsch_mm_sw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; release_firmware(adev->umsch_mm.fw); adev->umsch_mm.fw = NULL; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c index 7fc9d5e415845..f5a24d70ccd5d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c @@ -682,9 +682,9 @@ static int amdgpu_vkms_sw_init(struct amdgpu_ip_block *ip_block) return 0; } -static int amdgpu_vkms_sw_fini(void *handle) +static int amdgpu_vkms_sw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i = 0; for (i = 0; i < adev->mode_info.num_crtc; i++) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c index 9a3fe6856ac5d..6d96e1f21e201 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vpe.c @@ -381,9 +381,9 @@ static int vpe_sw_init(struct amdgpu_ip_block *ip_block) return ret; } -static int vpe_sw_fini(void *handle) +static int vpe_sw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; struct amdgpu_vpe *vpe = &adev->vpe; release_firmware(vpe->fw); diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c index a4d67fda11f2f..6c18ab35cf698 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik.c +++ b/drivers/gpu/drm/amd/amdgpu/cik.c @@ -2129,7 +2129,7 @@ static int cik_common_sw_init(struct amdgpu_ip_block *ip_block) return 0; } -static int cik_common_sw_fini(void *handle) +static int cik_common_sw_fini(struct amdgpu_ip_block *ip_block) { return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c index 717e68acacf50..9e9a58fd86cec 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c @@ -311,9 +311,9 @@ static int cik_ih_sw_init(struct amdgpu_ip_block *ip_block) return r; } -static int cik_ih_sw_fini(void *handle) +static int cik_ih_sw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; amdgpu_irq_fini_sw(adev); amdgpu_irq_remove_domain(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c index c58a66d30130e..df3f429e003e3 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c @@ -977,9 +977,9 @@ static int cik_sdma_sw_init(struct amdgpu_ip_block *ip_block) return r; } -static int cik_sdma_sw_fini(void *handle) +static int cik_sdma_sw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i; for (i = 0; i < adev->sdma.num_instances; i++) diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c index 526866d68a0ad..cadd69a243af1 100644 --- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c @@ -302,9 +302,9 @@ static int cz_ih_sw_init(struct amdgpu_ip_block *ip_block) return r; } -static int cz_ih_sw_fini(void *handle) +static int cz_ih_sw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; amdgpu_irq_fini_sw(adev); amdgpu_irq_remove_domain(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index bc015ad84331b..9cd254a026030 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -2856,9 +2856,9 @@ static int dce_v10_0_sw_init(struct amdgpu_ip_block *ip_block) return 0; } -static int dce_v10_0_sw_fini(void *handle) +static int dce_v10_0_sw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; drm_edid_free(adev->mode_info.bios_hardcoded_edid); diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index c9cf1983403b5..00ba63df1111a 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -2983,9 +2983,9 @@ static int dce_v11_0_sw_init(struct amdgpu_ip_block *ip_block) return 0; } -static int dce_v11_0_sw_fini(void *handle) +static int dce_v11_0_sw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; drm_edid_free(adev->mode_info.bios_hardcoded_edid); diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c index 7b7a87627d9c9..9a29af5cc879d 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c @@ -2755,9 +2755,9 @@ static int dce_v6_0_sw_init(struct amdgpu_ip_block *ip_block) return r; } -static int dce_v6_0_sw_fini(void *handle) +static int dce_v6_0_sw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; drm_edid_free(adev->mode_info.bios_hardcoded_edid); diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index 56fdde489cdec..e3b05911913a0 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -2775,9 +2775,9 @@ static int dce_v8_0_sw_init(struct amdgpu_ip_block *ip_block) return 0; } -static int dce_v8_0_sw_fini(void *handle) +static int dce_v8_0_sw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; drm_edid_free(adev->mode_info.bios_hardcoded_edid); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index acb93a6eccde9..f0fb4717b40a3 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -4873,10 +4873,10 @@ static void gfx_v10_0_me_fini(struct amdgpu_device *adev) (void **)&adev->gfx.me.me_fw_ptr); } -static int gfx_v10_0_sw_fini(void *handle) +static int gfx_v10_0_sw_fini(struct amdgpu_ip_block *ip_block) { int i; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; for (i = 0; i < adev->gfx.num_gfx_rings; i++) amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index c4fff777a0bef..6b22128ab004b 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -1732,10 +1732,10 @@ static void gfx_v11_0_rlc_autoload_buffer_fini(struct amdgpu_device *adev) (void **)&adev->gfx.rlc.rlc_autoload_ptr); } -static int gfx_v11_0_sw_fini(void *handle) +static int gfx_v11_0_sw_fini(struct amdgpu_ip_block *ip_block) { int i; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; for (i = 0; i < adev->gfx.num_gfx_rings; i++) amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c index 9c0d375965c2f..dc25fcb89b131 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c @@ -1492,10 +1492,10 @@ static void gfx_v12_0_rlc_autoload_buffer_fini(struct amdgpu_device *adev) (void **)&adev->gfx.rlc.rlc_autoload_ptr); } -static int gfx_v12_0_sw_fini(void *handle) +static int gfx_v12_0_sw_fini(struct amdgpu_ip_block *ip_block) { int i; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; for (i = 0; i < adev->gfx.num_gfx_rings; i++) amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c index 6e243ae07bdff..6ac6d4dfa49f0 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c @@ -3107,10 +3107,10 @@ static int gfx_v6_0_sw_init(struct amdgpu_ip_block *ip_block) return r; } -static int gfx_v6_0_sw_fini(void *handle) +static int gfx_v6_0_sw_fini(struct amdgpu_ip_block *ip_block) { int i; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; for (i = 0; i < adev->gfx.num_gfx_rings; i++) amdgpu_ring_fini(&adev->gfx.gfx_ring[i]); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index 927a0baf8de22..77150c9f1e182 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -4439,9 +4439,9 @@ static int gfx_v7_0_sw_init(struct amdgpu_ip_block *ip_block) return r; } -static int gfx_v7_0_sw_fini(void *handle) +static int gfx_v7_0_sw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i; for (i = 0; i < adev->gfx.num_gfx_rings; i++) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 80b39b8794e46..8f9f8e6d57a12 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -2043,9 +2043,9 @@ static int gfx_v8_0_sw_init(struct amdgpu_ip_block *ip_block) return 0; } -static int gfx_v8_0_sw_fini(void *handle) +static int gfx_v8_0_sw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i; for (i = 0; i < adev->gfx.num_gfx_rings; i++) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 3045a2dac99b4..8c95b0194197b 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -2405,10 +2405,10 @@ static int gfx_v9_0_sw_init(struct amdgpu_ip_block *ip_block) } -static int gfx_v9_0_sw_fini(void *handle) +static int gfx_v9_0_sw_fini(struct amdgpu_ip_block *ip_block) { int i; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (adev->gfx.mcbp && adev->gfx.num_gfx_rings) { for (i = 0; i < GFX9_NUM_SW_GFX_RINGS; i++) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index 7520f8a241b58..7d425d2e7ab00 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -1181,10 +1181,10 @@ static int gfx_v9_4_3_sw_init(struct amdgpu_ip_block *ip_block) return 0; } -static int gfx_v9_4_3_sw_fini(void *handle) +static int gfx_v9_4_3_sw_fini(struct amdgpu_ip_block *ip_block) { int i, num_xcc; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; num_xcc = NUM_XCC(adev->gfx.xcc_mask); for (i = 0; i < adev->gfx.num_compute_rings * num_xcc; i++) diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c index 106c9fc7308ff..2f1af50aae1ec 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c @@ -918,9 +918,9 @@ static void gmc_v10_0_gart_fini(struct amdgpu_device *adev) amdgpu_gart_table_vram_free(adev); } -static int gmc_v10_0_sw_fini(void *handle) +static int gmc_v10_0_sw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; amdgpu_vm_manager_fini(adev); gmc_v10_0_gart_fini(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c index 3c62b755e3264..82b905271547f 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c @@ -847,9 +847,9 @@ static void gmc_v11_0_gart_fini(struct amdgpu_device *adev) amdgpu_gart_table_vram_free(adev); } -static int gmc_v11_0_sw_fini(void *handle) +static int gmc_v11_0_sw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; amdgpu_vm_manager_fini(adev); gmc_v11_0_gart_fini(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c index 5111a054fbb0a..dcc44e688175e 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c @@ -824,9 +824,9 @@ static void gmc_v12_0_gart_fini(struct amdgpu_device *adev) amdgpu_gart_table_vram_free(adev); } -static int gmc_v12_0_sw_fini(void *handle) +static int gmc_v12_0_sw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; amdgpu_vm_manager_fini(adev); gmc_v12_0_gart_fini(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c index 00b81c1924e3b..b66707f7d5941 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c @@ -886,9 +886,9 @@ static int gmc_v6_0_sw_init(struct amdgpu_ip_block *ip_block) return 0; } -static int gmc_v6_0_sw_fini(void *handle) +static int gmc_v6_0_sw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; amdgpu_gem_force_release(adev); amdgpu_vm_manager_fini(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c index d54430e44b194..e2331a5aac0ee 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c @@ -1059,9 +1059,9 @@ static int gmc_v7_0_sw_init(struct amdgpu_ip_block *ip_block) return 0; } -static int gmc_v7_0_sw_fini(void *handle) +static int gmc_v7_0_sw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; amdgpu_gem_force_release(adev); amdgpu_vm_manager_fini(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index e459f342bde1e..f5c1ebce73f4f 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -1187,9 +1187,9 @@ static int gmc_v8_0_sw_init(struct amdgpu_ip_block *ip_block) return 0; } -static int gmc_v8_0_sw_fini(void *handle) +static int gmc_v8_0_sw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; amdgpu_gem_force_release(adev); amdgpu_vm_manager_fini(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index 179689190f923..8cf8520f1dc2b 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -2238,9 +2238,9 @@ static int gmc_v9_0_sw_init(struct amdgpu_ip_block *ip_block) return 0; } -static int gmc_v9_0_sw_fini(void *handle) +static int gmc_v9_0_sw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3) || amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4)) diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c index aaf59915dbfa2..a3fb01f905d43 100644 --- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c @@ -301,9 +301,9 @@ static int iceland_ih_sw_init(struct amdgpu_ip_block *ip_block) return r; } -static int iceland_ih_sw_fini(void *handle) +static int iceland_ih_sw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; amdgpu_irq_fini_sw(adev); amdgpu_irq_remove_domain(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c index e0c55d282f7cc..09403eac483bc 100644 --- a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c @@ -614,9 +614,9 @@ static int ih_v6_0_sw_init(struct amdgpu_ip_block *ip_block) return r; } -static int ih_v6_0_sw_fini(void *handle) +static int ih_v6_0_sw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; amdgpu_irq_fini_sw(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c index f9bab7005bf3a..9706d7593d267 100644 --- a/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c +++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_1.c @@ -593,9 +593,9 @@ static int ih_v6_1_sw_init(struct amdgpu_ip_block *ip_block) return r; } -static int ih_v6_1_sw_fini(void *handle) +static int ih_v6_1_sw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; amdgpu_irq_fini_sw(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c index 533e408f4dd0f..9657145d7ccea 100644 --- a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c @@ -583,9 +583,9 @@ static int ih_v7_0_sw_init(struct amdgpu_ip_block *ip_block) return r; } -static int ih_v7_0_sw_fini(void *handle) +static int ih_v7_0_sw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; amdgpu_irq_fini_sw(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c index 24ac589f200a7..33da094f1a7dc 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.c @@ -513,9 +513,9 @@ int jpeg_v1_0_sw_init(struct amdgpu_ip_block *ip_block) * * JPEG free up sw allocation */ -void jpeg_v1_0_sw_fini(void *handle) +void jpeg_v1_0_sw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; amdgpu_ring_fini(adev->jpeg.inst->ring_dec); } diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.h b/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.h index d978422ddbd76..0973286350835 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.h +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.h @@ -26,7 +26,7 @@ int jpeg_v1_0_early_init(struct amdgpu_ip_block *ip_block); int jpeg_v1_0_sw_init(struct amdgpu_ip_block *ip_block); -void jpeg_v1_0_sw_fini(void *handle); +void jpeg_v1_0_sw_fini(struct amdgpu_ip_block *ip_block); void jpeg_v1_0_start(struct amdgpu_device *adev, int mode); #define JPEG_V1_REG_RANGE_START 0x8000 diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c index aa2d3e5a7f96d..ec3d341fef61b 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.c @@ -108,10 +108,10 @@ static int jpeg_v2_0_sw_init(struct amdgpu_ip_block *ip_block) * * JPEG suspend and free up sw allocation */ -static int jpeg_v2_0_sw_fini(void *handle) +static int jpeg_v2_0_sw_fini(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; r = amdgpu_jpeg_suspend(adev); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c index a53c3d53ec160..37cf415b6b410 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c @@ -157,10 +157,10 @@ static int jpeg_v2_5_sw_init(struct amdgpu_ip_block *ip_block) * * JPEG suspend and free up sw allocation */ -static int jpeg_v2_5_sw_fini(void *handle) +static int jpeg_v2_5_sw_fini(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; r = amdgpu_jpeg_suspend(adev); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c index 54ebf29f3b8c2..2fa866a3e39db 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.c @@ -122,9 +122,9 @@ static int jpeg_v3_0_sw_init(struct amdgpu_ip_block *ip_block) * * JPEG suspend and free up sw allocation */ -static int jpeg_v3_0_sw_fini(void *handle) +static int jpeg_v3_0_sw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; r = amdgpu_jpeg_suspend(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c index bb460a6753b76..3cef4124b171b 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.c @@ -134,9 +134,9 @@ static int jpeg_v4_0_sw_init(struct amdgpu_ip_block *ip_block) * * JPEG suspend and free up sw allocation */ -static int jpeg_v4_0_sw_fini(void *handle) +static int jpeg_v4_0_sw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; r = amdgpu_jpeg_suspend(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c index c8a27f4e2e5d4..fd108f992ab15 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.c @@ -169,9 +169,9 @@ static int jpeg_v4_0_3_sw_init(struct amdgpu_ip_block *ip_block) * * JPEG suspend and free up sw allocation */ -static int jpeg_v4_0_3_sw_fini(void *handle) +static int jpeg_v4_0_3_sw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; r = amdgpu_jpeg_suspend(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c index cdb6fde4bd512..2f9749b00eaf1 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_5.c @@ -163,9 +163,9 @@ static int jpeg_v4_0_5_sw_init(struct amdgpu_ip_block *ip_block) * * JPEG suspend and free up sw allocation */ -static int jpeg_v4_0_5_sw_fini(void *handle) +static int jpeg_v4_0_5_sw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; r = amdgpu_jpeg_suspend(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c index ec468458f583d..a9a0b3f250dee 100644 --- a/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c +++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v5_0_0.c @@ -110,9 +110,9 @@ static int jpeg_v5_0_0_sw_init(struct amdgpu_ip_block *ip_block) * * JPEG suspend and free up sw allocation */ -static int jpeg_v5_0_0_sw_fini(void *handle) +static int jpeg_v5_0_0_sw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; r = amdgpu_jpeg_suspend(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c index ea3da196bfa7e..4b0f83fe9dd98 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c @@ -1402,9 +1402,9 @@ static int mes_v11_0_sw_init(struct amdgpu_ip_block *ip_block) return 0; } -static int mes_v11_0_sw_fini(void *handle) +static int mes_v11_0_sw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int pipe; for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c index c1d4984c37918..f50071cf95b96 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c @@ -1362,9 +1362,9 @@ static int mes_v12_0_sw_init(struct amdgpu_ip_block *ip_block) return 0; } -static int mes_v12_0_sw_fini(void *handle) +static int mes_v12_0_sw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int pipe; for (pipe = 0; pipe < AMDGPU_MAX_MES_PIPES; pipe++) { diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c index eb2e11bf2fb83..93da900b7ee2c 100644 --- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c @@ -593,9 +593,9 @@ static int navi10_ih_sw_init(struct amdgpu_ip_block *ip_block) return r; } -static int navi10_ih_sw_fini(void *handle) +static int navi10_ih_sw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; amdgpu_irq_fini_sw(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index 080d8fb3ea818..4e8f9af1e2bec 100644 --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c @@ -983,7 +983,7 @@ static int nv_common_sw_init(struct amdgpu_ip_block *ip_block) return 0; } -static int nv_common_sw_fini(void *handle) +static int nv_common_sw_fini(struct amdgpu_ip_block *ip_block) { return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c index 34081989e4888..10fd772cb80fd 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c @@ -866,9 +866,9 @@ static int sdma_v2_4_sw_init(struct amdgpu_ip_block *ip_block) return r; } -static int sdma_v2_4_sw_fini(void *handle) +static int sdma_v2_4_sw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i; for (i = 0; i < adev->sdma.num_instances; i++) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c index f4f5cb8542798..69fba087e09c7 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c @@ -1152,9 +1152,9 @@ static int sdma_v3_0_sw_init(struct amdgpu_ip_block *ip_block) return r; } -static int sdma_v3_0_sw_fini(void *handle) +static int sdma_v3_0_sw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i; for (i = 0; i < adev->sdma.num_instances; i++) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index 4f9638cb2cdfe..ccf0d531776d9 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c @@ -1930,9 +1930,9 @@ static int sdma_v4_0_sw_init(struct amdgpu_ip_block *ip_block) return r; } -static int sdma_v4_0_sw_fini(void *handle) +static int sdma_v4_0_sw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i; for (i = 0; i < adev->sdma.num_instances; i++) { diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c index da0ab9df3f6bc..9c7cea0890c98 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c @@ -1445,9 +1445,9 @@ static int sdma_v4_4_2_sw_init(struct amdgpu_ip_block *ip_block) return r; } -static int sdma_v4_4_2_sw_fini(void *handle) +static int sdma_v4_4_2_sw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i; for (i = 0; i < adev->sdma.num_instances; i++) { diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c index 12c71d9cde75a..6a675daf56202 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c @@ -1462,9 +1462,9 @@ static int sdma_v5_0_sw_init(struct amdgpu_ip_block *ip_block) return r; } -static int sdma_v5_0_sw_fini(void *handle) +static int sdma_v5_0_sw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i; for (i = 0; i < adev->sdma.num_instances; i++) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c index 575b72e3940ba..e1413ccaf7e41 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c @@ -1367,9 +1367,9 @@ static int sdma_v5_2_sw_init(struct amdgpu_ip_block *ip_block) return r; } -static int sdma_v5_2_sw_fini(void *handle) +static int sdma_v5_2_sw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i; for (i = 0; i < adev->sdma.num_instances; i++) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c index 7692c9942259c..4b33bd6b776db 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c @@ -1365,9 +1365,9 @@ static int sdma_v6_0_sw_init(struct amdgpu_ip_block *ip_block) return r; } -static int sdma_v6_0_sw_fini(void *handle) +static int sdma_v6_0_sw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i; for (i = 0; i < adev->sdma.num_instances; i++) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c index a0029c1d164c3..24f24974ac1d8 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c @@ -1320,9 +1320,9 @@ static int sdma_v7_0_sw_init(struct amdgpu_ip_block *ip_block) return r; } -static int sdma_v7_0_sw_fini(void *handle) +static int sdma_v7_0_sw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i; for (i = 0; i < adev->sdma.num_instances; i++) diff --git a/drivers/gpu/drm/amd/amdgpu/si.c b/drivers/gpu/drm/amd/amdgpu/si.c index 54efbb032da19..b9934661a92ee 100644 --- a/drivers/gpu/drm/amd/amdgpu/si.c +++ b/drivers/gpu/drm/amd/amdgpu/si.c @@ -2153,7 +2153,7 @@ static int si_common_sw_init(struct amdgpu_ip_block *ip_block) return 0; } -static int si_common_sw_fini(void *handle) +static int si_common_sw_fini(struct amdgpu_ip_block *ip_block) { return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c index 5991649ef540c..d44483ed3363e 100644 --- a/drivers/gpu/drm/amd/amdgpu/si_dma.c +++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c @@ -506,9 +506,9 @@ static int si_dma_sw_init(struct amdgpu_ip_block *ip_block) return r; } -static int si_dma_sw_fini(void *handle) +static int si_dma_sw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i; for (i = 0; i < adev->sdma.num_instances; i++) diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c b/drivers/gpu/drm/amd/amdgpu/si_ih.c index 5291641ad7990..b018a3b904019 100644 --- a/drivers/gpu/drm/amd/amdgpu/si_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c @@ -177,9 +177,9 @@ static int si_ih_sw_init(struct amdgpu_ip_block *ip_block) return amdgpu_irq_init(adev); } -static int si_ih_sw_fini(void *handle) +static int si_ih_sw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; amdgpu_irq_fini_sw(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index 64e16d7a75f80..6ab34c526c863 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -1231,9 +1231,9 @@ static int soc15_common_sw_init(struct amdgpu_ip_block *ip_block) return 0; } -static int soc15_common_sw_fini(void *handle) +static int soc15_common_sw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (adev->df.funcs && adev->df.funcs->sw_fini) diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c index d0d7cd17c7832..c4b950e75133f 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc21.c +++ b/drivers/gpu/drm/amd/amdgpu/soc21.c @@ -842,7 +842,7 @@ static int soc21_common_sw_init(struct amdgpu_ip_block *ip_block) return 0; } -static int soc21_common_sw_fini(void *handle) +static int soc21_common_sw_fini(struct amdgpu_ip_block *ip_block) { return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/soc24.c b/drivers/gpu/drm/amd/amdgpu/soc24.c index 0fe572335b2a6..b20dc81dc2574 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc24.c +++ b/drivers/gpu/drm/amd/amdgpu/soc24.c @@ -465,7 +465,7 @@ static int soc24_common_sw_init(struct amdgpu_ip_block *ip_block) return 0; } -static int soc24_common_sw_fini(void *handle) +static int soc24_common_sw_fini(struct amdgpu_ip_block *ip_block) { return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c index c0c008251bf0c..45fb5140c8b71 100644 --- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c @@ -314,9 +314,9 @@ static int tonga_ih_sw_init(struct amdgpu_ip_block *ip_block) return r; } -static int tonga_ih_sw_fini(void *handle) +static int tonga_ih_sw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; amdgpu_irq_fini_sw(adev); amdgpu_irq_remove_domain(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c index 341f6ae68b08c..11a081a53788a 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c @@ -580,10 +580,10 @@ static int uvd_v3_1_sw_init(struct amdgpu_ip_block *ip_block) return r; } -static int uvd_v3_1_sw_fini(void *handle) +static int uvd_v3_1_sw_fini(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; r = amdgpu_uvd_suspend(adev); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c index dd63bad21d181..93df9a2c08fbe 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c @@ -130,10 +130,10 @@ static int uvd_v4_2_sw_init(struct amdgpu_ip_block *ip_block) return r; } -static int uvd_v4_2_sw_fini(void *handle) +static int uvd_v4_2_sw_fini(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; r = amdgpu_uvd_suspend(adev); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c index f83ecc092e721..0dc00924a674f 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c @@ -128,10 +128,10 @@ static int uvd_v5_0_sw_init(struct amdgpu_ip_block *ip_block) return r; } -static int uvd_v5_0_sw_fini(void *handle) +static int uvd_v5_0_sw_fini(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; r = amdgpu_uvd_suspend(adev); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c index 4b8d81bf19314..5c525bb77b5bc 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c @@ -435,10 +435,10 @@ static int uvd_v6_0_sw_init(struct amdgpu_ip_block *ip_block) return r; } -static int uvd_v6_0_sw_fini(void *handle) +static int uvd_v6_0_sw_fini(struct amdgpu_ip_block *ip_block) { int i, r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; r = amdgpu_uvd_suspend(adev); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c index 63e8cd5d282d0..8fee1e1328489 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c @@ -487,10 +487,10 @@ static int uvd_v7_0_sw_init(struct amdgpu_ip_block *ip_block) return r; } -static int uvd_v7_0_sw_fini(void *handle) +static int uvd_v7_0_sw_fini(struct amdgpu_ip_block *ip_block) { int i, j, r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; amdgpu_virt_free_mm_table(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c index 0f65d4ea63d03..a4531000ec0bf 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c @@ -450,10 +450,10 @@ static int vce_v2_0_sw_init(struct amdgpu_ip_block *ip_block) return r; } -static int vce_v2_0_sw_fini(void *handle) +static int vce_v2_0_sw_fini(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; r = amdgpu_vce_suspend(adev); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c index 8124f8cd8cc74..9f9a9d89bcdc2 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c @@ -453,10 +453,10 @@ static int vce_v3_0_sw_init(struct amdgpu_ip_block *ip_block) return r; } -static int vce_v3_0_sw_fini(void *handle) +static int vce_v3_0_sw_fini(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; r = amdgpu_vce_suspend(adev); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c index b3532240da015..f4d2650e6b7a2 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c @@ -493,10 +493,10 @@ static int vce_v4_0_sw_init(struct amdgpu_ip_block *ip_block) return r; } -static int vce_v4_0_sw_fini(void *handle) +static int vce_v4_0_sw_fini(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; /* free MM table */ amdgpu_virt_free_mm_table(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c index ea20d16e173f9..add33f1b6aa24 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c @@ -217,16 +217,16 @@ static int vcn_v1_0_sw_init(struct amdgpu_ip_block *ip_block) * * VCN suspend and free up sw allocation */ -static int vcn_v1_0_sw_fini(void *handle) +static int vcn_v1_0_sw_fini(struct amdgpu_ip_block *ip_block) { int r; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; r = amdgpu_vcn_suspend(adev); if (r) return r; - jpeg_v1_0_sw_fini(handle); + jpeg_v1_0_sw_fini(ip_block); r = amdgpu_vcn_sw_fini(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c index a66cad2667dba..c104c47301c7f 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c @@ -241,10 +241,10 @@ static int vcn_v2_0_sw_init(struct amdgpu_ip_block *ip_block) * * VCN suspend and free up sw allocation */ -static int vcn_v2_0_sw_fini(void *handle) +static int vcn_v2_0_sw_fini(struct amdgpu_ip_block *ip_block) { int r, idx; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; volatile struct amdgpu_fw_shared *fw_shared = adev->vcn.inst->fw_shared.cpu_addr; if (drm_dev_enter(adev_to_drm(adev), &idx)) { diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c index b070f73453177..e76e1168d6f8d 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c @@ -299,10 +299,10 @@ static int vcn_v2_5_sw_init(struct amdgpu_ip_block *ip_block) * * VCN suspend and free up sw allocation */ -static int vcn_v2_5_sw_fini(void *handle) +static int vcn_v2_5_sw_fini(struct amdgpu_ip_block *ip_block) { int i, r, idx; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; volatile struct amdgpu_fw_shared *fw_shared; if (drm_dev_enter(adev_to_drm(adev), &idx)) { diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c index 083e4f9c4520c..51ea9a83204f6 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c @@ -303,9 +303,9 @@ static int vcn_v3_0_sw_init(struct amdgpu_ip_block *ip_block) * * VCN suspend and free up sw allocation */ -static int vcn_v3_0_sw_fini(void *handle) +static int vcn_v3_0_sw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i, r, idx; if (drm_dev_enter(adev_to_drm(adev), &idx)) { diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c index 99c2b594c6872..e33cc611f2154 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c @@ -257,9 +257,9 @@ static int vcn_v4_0_sw_init(struct amdgpu_ip_block *ip_block) * * VCN suspend and free up sw allocation */ -static int vcn_v4_0_sw_fini(void *handle) +static int vcn_v4_0_sw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i, r, idx; if (drm_dev_enter(adev_to_drm(adev), &idx)) { diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c index 2c32825172efb..f02699a92e501 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c @@ -216,9 +216,9 @@ static int vcn_v4_0_3_sw_init(struct amdgpu_ip_block *ip_block) * * VCN suspend and free up sw allocation */ -static int vcn_v4_0_3_sw_fini(void *handle) +static int vcn_v4_0_3_sw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i, r, idx; if (drm_dev_enter(&adev->ddev, &idx)) { diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c index 695e53184faa0..6d277ee27f463 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c @@ -224,9 +224,9 @@ static int vcn_v4_0_5_sw_init(struct amdgpu_ip_block *ip_block) * * VCN suspend and free up sw allocation */ -static int vcn_v4_0_5_sw_fini(void *handle) +static int vcn_v4_0_5_sw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i, r, idx; if (drm_dev_enter(adev_to_drm(adev), &idx)) { diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c index 795ab0256948c..89e813b7ba5df 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c @@ -191,9 +191,9 @@ static int vcn_v5_0_0_sw_init(struct amdgpu_ip_block *ip_block) * * VCN suspend and free up sw allocation */ -static int vcn_v5_0_0_sw_fini(void *handle) +static int vcn_v5_0_0_sw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int i, r, idx; if (drm_dev_enter(adev_to_drm(adev), &idx)) { diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c index 781845811f700..73de5909f655b 100644 --- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c @@ -525,9 +525,9 @@ static int vega10_ih_sw_init(struct amdgpu_ip_block *ip_block) return r; } -static int vega10_ih_sw_fini(void *handle) +static int vega10_ih_sw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; amdgpu_irq_fini_sw(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c index b90f553faafa6..a42404a58015d 100644 --- a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c +++ b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c @@ -586,9 +586,9 @@ static int vega20_ih_sw_init(struct amdgpu_ip_block *ip_block) return r; } -static int vega20_ih_sw_fini(void *handle) +static int vega20_ih_sw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; amdgpu_irq_fini_sw(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index e67c5f1fe32ed..4996049dc1995 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/drivers/gpu/drm/amd/amdgpu/vi.c @@ -1699,7 +1699,7 @@ static int vi_common_sw_init(struct amdgpu_ip_block *ip_block) return 0; } -static int vi_common_sw_fini(void *handle) +static int vi_common_sw_fini(struct amdgpu_ip_block *ip_block) { return 0; } diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index f491de05ca572..c320d748d7cb1 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2563,9 +2563,9 @@ static int dm_sw_init(struct amdgpu_ip_block *ip_block) return load_dmcu_fw(adev); } -static int dm_sw_fini(void *handle) +static int dm_sw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; struct dal_allocation *da; list_for_each_entry(da, &adev->dm.da_list, list) { diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c index 5e840528eaa9c..2cd6cb991f29c 100644 --- a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c @@ -3023,9 +3023,9 @@ static int kv_dpm_sw_init(struct amdgpu_ip_block *ip_block) return ret; } -static int kv_dpm_sw_fini(void *handle) +static int kv_dpm_sw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; flush_work(&adev->pm.dpm.thermal.work); diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c index 9f140b6e7b320..a4908f0402f1a 100644 --- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c @@ -7765,9 +7765,9 @@ static int si_dpm_sw_init(struct amdgpu_ip_block *ip_block) return ret; } -static int si_dpm_sw_fini(void *handle) +static int si_dpm_sw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; flush_work(&adev->pm.dpm.thermal.work); diff --git a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c index 70e78e64bee0d..bda5a208852fb 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c +++ b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c @@ -147,9 +147,9 @@ static int pp_sw_init(struct amdgpu_ip_block *ip_block) return ret; } -static int pp_sw_fini(void *handle) +static int pp_sw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = handle; + struct amdgpu_device *adev = ip_block->adev; struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; hwmgr_sw_fini(hwmgr); diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 14c0db494388f..af1dc8bd75e6f 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -1314,9 +1314,9 @@ static int smu_sw_init(struct amdgpu_ip_block *ip_block) return 0; } -static int smu_sw_fini(void *handle) +static int smu_sw_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; struct smu_context *smu = adev->powerplay.pp_handle; int ret; From a655f8ccb7096b257785831ad3521e1a5a80c47d Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Thu, 26 Sep 2024 21:01:55 +0530 Subject: [PATCH 1738/1868] drm/amdgpu: update the handle ptr in early_fini MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Update the *handle to amdgpu_ip_block ptr for all functions pointers of early_fini. Signed-off-by: Sunil Khatri Reviewed-by: Christian König (cherry picked from commit e80945a98a2cdcc7c062a20f61aa5b800d26d870) --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 7ec8f46640ec1..6996d58f78bee 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -3326,7 +3326,7 @@ static int amdgpu_device_ip_fini_early(struct amdgpu_device *adev) if (!adev->ip_blocks[i].version->funcs->early_fini) continue; - r = adev->ip_blocks[i].version->funcs->early_fini((void *)adev); + r = adev->ip_blocks[i].version->funcs->early_fini(&adev->ip_blocks[i]); if (r) { DRM_DEBUG("early_fini of IP block <%s> failed %d\n", adev->ip_blocks[i].version->funcs->name, r); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index c320d748d7cb1..d9bcf0ba06ad0 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2147,9 +2147,9 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) return -EINVAL; } -static int amdgpu_dm_early_fini(void *handle) +static int amdgpu_dm_early_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; amdgpu_dm_audio_fini(adev); From bc45ae4323020e3e044bce665a749aa130a30eb9 Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Mon, 30 Sep 2024 13:50:15 +0530 Subject: [PATCH 1739/1868] drm/amdgpu: remove the dummy fn acp_early_init MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit acp_early_init is a dummy function and is not being used and hence removed. Signed-off-by: Sunil Khatri Reviewed-by: Christian König (cherry picked from commit 6604ea725b3db7c038ee6f041ebeb57e9dad3177) --- drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c index baefcc21d7973..b3a6470175baf 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c @@ -582,11 +582,6 @@ static int acp_resume(struct amdgpu_ip_block *ip_block) return 0; } -static int acp_early_init(struct amdgpu_ip_block *ip_block) -{ - return 0; -} - static bool acp_is_idle(void *handle) { return true; @@ -621,7 +616,7 @@ static int acp_set_powergating_state(void *handle, static const struct amd_ip_funcs acp_ip_funcs = { .name = "acp_ip", - .early_init = acp_early_init, + .early_init = NULL, .late_init = NULL, .sw_init = acp_sw_init, .sw_fini = acp_sw_fini, From 7f98b28c5ed3dcc710b091f4ff61b56bd52ae0a8 Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Mon, 30 Sep 2024 14:05:49 +0530 Subject: [PATCH 1740/1868] drm/amdgpu: update the handle ptr in late_fini MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Update the *handle to amdgpu_ip_block ptr for all functions pointers of late_fini. Signed-off-by: Sunil Khatri Reviewed-by: Christian König (cherry picked from commit b3199c1104a61b874763748fb066515a5ae7dd2d) --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +- drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c | 4 ++-- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 6996d58f78bee..3964c7a1ce3a8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -3413,7 +3413,7 @@ static int amdgpu_device_ip_fini(struct amdgpu_device *adev) if (!adev->ip_blocks[i].status.late_initialized) continue; if (adev->ip_blocks[i].version->funcs->late_fini) - adev->ip_blocks[i].version->funcs->late_fini((void *)adev); + adev->ip_blocks[i].version->funcs->late_fini(&adev->ip_blocks[i]); adev->ip_blocks[i].status.late_initialized = false; } diff --git a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c index bda5a208852fb..f193c77cc1413 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c +++ b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c @@ -229,9 +229,9 @@ static int pp_late_init(struct amdgpu_ip_block *ip_block) return 0; } -static void pp_late_fini(void *handle) +static void pp_late_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = handle; + struct amdgpu_device *adev = ip_block->adev; if (adev->pm.smu_prv_buffer) amdgpu_bo_free_kernel(&adev->pm.smu_prv_buffer, NULL, NULL); diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index af1dc8bd75e6f..bc82ae41c2dda 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -2042,9 +2042,9 @@ static int smu_hw_fini(struct amdgpu_ip_block *ip_block) return 0; } -static void smu_late_fini(void *handle) +static void smu_late_fini(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = handle; + struct amdgpu_device *adev = ip_block->adev; struct smu_context *smu = adev->powerplay.pp_handle; kfree(smu); From 5da76e68bf2485977dc498d23e7c5e79ae50a871 Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Mon, 30 Sep 2024 14:11:22 +0530 Subject: [PATCH 1741/1868] drm/amdgpu: update the handle ptr in prepare_suspend MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Update the *handle to amdgpu_ip_block ptr for all functions pointers of prepare_suspend. Signed-off-by: Sunil Khatri Reviewed-by: Christian König (cherry picked from commit 1f033201be23d181cb83541a21ce84d99a3aa5b3) --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +- drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 4 ++-- 6 files changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 3964c7a1ce3a8..66e911b3308e2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -4770,7 +4770,7 @@ int amdgpu_device_prepare(struct drm_device *dev) continue; if (!adev->ip_blocks[i].version->funcs->prepare_suspend) continue; - r = adev->ip_blocks[i].version->funcs->prepare_suspend((void *)adev); + r = adev->ip_blocks[i].version->funcs->prepare_suspend(&adev->ip_blocks[i]); if (r) goto unprepare; } diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c index 11a081a53788a..c5540c30d1bbc 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c @@ -704,9 +704,9 @@ static int uvd_v3_1_hw_fini(struct amdgpu_ip_block *ip_block) return 0; } -static int uvd_v3_1_prepare_suspend(void *handle) +static int uvd_v3_1_prepare_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return amdgpu_uvd_prepare_suspend(adev); } diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c index 93df9a2c08fbe..02e2dda638282 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c @@ -218,9 +218,9 @@ static int uvd_v4_2_hw_fini(struct amdgpu_ip_block *ip_block) return 0; } -static int uvd_v4_2_prepare_suspend(void *handle) +static int uvd_v4_2_prepare_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return amdgpu_uvd_prepare_suspend(adev); } diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c index 0dc00924a674f..d84b49064138d 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c @@ -216,9 +216,9 @@ static int uvd_v5_0_hw_fini(struct amdgpu_ip_block *ip_block) return 0; } -static int uvd_v5_0_prepare_suspend(void *handle) +static int uvd_v5_0_prepare_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return amdgpu_uvd_prepare_suspend(adev); } diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c index 5c525bb77b5bc..d14b1769f74ce 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c @@ -540,9 +540,9 @@ static int uvd_v6_0_hw_fini(struct amdgpu_ip_block *ip_block) return 0; } -static int uvd_v6_0_prepare_suspend(void *handle) +static int uvd_v6_0_prepare_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return amdgpu_uvd_prepare_suspend(adev); } diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c index 8fee1e1328489..52ce3ac38215c 100644 --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c @@ -608,9 +608,9 @@ static int uvd_v7_0_hw_fini(struct amdgpu_ip_block *ip_block) return 0; } -static int uvd_v7_0_prepare_suspend(void *handle) +static int uvd_v7_0_prepare_suspend(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; return amdgpu_uvd_prepare_suspend(adev); } From b29aea788c135ca5ab5bd6165e1030a718ff43d1 Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Tue, 1 Oct 2024 12:26:46 +0530 Subject: [PATCH 1742/1868] drm/amdgpu/gfx9: Add Cleaner Shader Deinitialization in gfx_v9_0 Module MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This commit addresses an omission in the previous patch related to the cleaner shader support for GFX9 hardware. Specifically, it adds the necessary deinitialization code for the cleaner shader in the gfx_v9_0_sw_fini function. The added line amdgpu_gfx_cleaner_shader_sw_fini(adev); ensures that any allocated resources for the cleaner shader are freed correctly, avoiding potential memory leaks and ensuring that the GPU state is clean for the next initialization sequence. Cc: Christian König Cc: Alex Deucher Signed-off-by: Srinivasan Shanmugam Acked-by: Christian König (cherry picked from commit eafafcbd992e34a68026fc429eda59afe87783c2) --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 8c95b0194197b..3537c3fb63fe7 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -2425,6 +2425,8 @@ static int gfx_v9_0_sw_fini(struct amdgpu_ip_block *ip_block) amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring); amdgpu_gfx_kiq_fini(adev, 0); + amdgpu_gfx_cleaner_shader_sw_fini(adev); + gfx_v9_0_mec_fini(adev); amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, &adev->gfx.rlc.clear_state_gpu_addr, From fe0505923a6ecb07bda61fb58a1d7ead363a9c69 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Fri, 20 Sep 2024 14:17:30 +0530 Subject: [PATCH 1743/1868] drm/amdgpu: Check gmc requirement for reset on init Add a callback to check if there is any condition detected by GMC block for reset on init. One case is if a pending NPS change request is detected. If reset is done because of NPS switch, refresh NPS info from discovery table. Signed-off-by: Lijo Lazar Reviewed-by: Feifei Xu (cherry picked from commit b07a4318bd74626cfac6f24479bdeb4d5a6abdff) --- drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 13 ++++++++++++- drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 5 +++++ drivers/gpu/drm/amd/amdgpu/soc15.c | 2 ++ 3 files changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c index 34e5ccd22b988..68b374a0cdf72 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c @@ -1270,12 +1270,15 @@ int amdgpu_gmc_get_nps_memranges(struct amdgpu_device *adev, struct amdgpu_gmc_memrange *ranges; int range_cnt, ret, i, j; uint32_t nps_type; + bool refresh; if (!mem_ranges) return -EINVAL; + refresh = (adev->init_lvl->level != AMDGPU_INIT_LEVEL_MINIMAL_XGMI) && + (adev->gmc.reset_flags & AMDGPU_GMC_INIT_RESET_NPS); ret = amdgpu_discovery_get_nps_info(adev, &nps_type, &ranges, - &range_cnt, false); + &range_cnt, refresh); if (ret) return ret; @@ -1401,3 +1404,11 @@ void amdgpu_gmc_prepare_nps_mode_change(struct amdgpu_device *adev) adev->dev, "NPS mode change request done, reload driver to complete the change\n"); } + +bool amdgpu_gmc_need_reset_on_init(struct amdgpu_device *adev) +{ + if (adev->gmc.gmc_funcs->need_reset_on_init) + return adev->gmc.gmc_funcs->need_reset_on_init(adev); + + return false; +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h index b92f41d1b46f1..c66b6dbe9ac65 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h @@ -78,6 +78,8 @@ enum amdgpu_memory_partition { BIT(AMDGPU_NPS3_PARTITION_MODE) | BIT(AMDGPU_NPS4_PARTITION_MODE) | \ BIT(AMDGPU_NPS6_PARTITION_MODE) | BIT(AMDGPU_NPS8_PARTITION_MODE)) +#define AMDGPU_GMC_INIT_RESET_NPS BIT(0) + /* * GMC page fault information */ @@ -169,6 +171,7 @@ struct amdgpu_gmc_funcs { /* Request NPS mode */ int (*request_mem_partition_mode)(struct amdgpu_device *adev, int nps_mode); + bool (*need_reset_on_init)(struct amdgpu_device *adev); }; struct amdgpu_xgmi_ras { @@ -314,6 +317,7 @@ struct amdgpu_gmc { const struct amdgpu_gmc_funcs *gmc_funcs; enum amdgpu_memory_partition requested_nps_mode; uint32_t supported_nps_modes; + uint32_t reset_flags; struct amdgpu_xgmi xgmi; struct amdgpu_irq_src ecc_irq; @@ -467,5 +471,6 @@ int amdgpu_gmc_get_nps_memranges(struct amdgpu_device *adev, int amdgpu_gmc_request_memory_partition(struct amdgpu_device *adev, int nps_mode); void amdgpu_gmc_prepare_nps_mode_change(struct amdgpu_device *adev); +bool amdgpu_gmc_need_reset_on_init(struct amdgpu_device *adev); #endif diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index 6ab34c526c863..dd1c1aacdd8e1 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -831,6 +831,8 @@ static bool soc15_need_reset_on_init(struct amdgpu_device *adev) if (adev->asic_type == CHIP_RENOIR) return true; + if (amdgpu_gmc_need_reset_on_init(adev)) + return true; if (amdgpu_psp_tos_reload_needed(adev)) return true; /* Just return false for soc15 GPUs. Reset does not seem to From 7b9b2b39485cc914572a5f922735a60ad73d7cf5 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 11 Oct 2024 10:15:25 +0800 Subject: [PATCH 1744/1868] Revert "drm/amdgpu: update the handle ptr in late_init" This reverts commit a5898e743754c257f07151087c5eea7641a91b8f. --- drivers/gpu/drm/amd/amdgpu/aldebaran.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 10 +++++----- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/nv.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c | 2 +- drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.c | 2 +- drivers/gpu/drm/amd/amdgpu/soc15.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/soc21.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/soc24.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vi.c | 4 ++-- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++-- drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c | 4 ++-- drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 4 ++-- drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c | 4 ++-- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 8 ++------ 33 files changed, 65 insertions(+), 69 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/aldebaran.c b/drivers/gpu/drm/amd/amdgpu/aldebaran.c index c1ff24335a0c5..f99bf6bcec9d6 100644 --- a/drivers/gpu/drm/amd/amdgpu/aldebaran.c +++ b/drivers/gpu/drm/amd/amdgpu/aldebaran.c @@ -304,7 +304,7 @@ static int aldebaran_mode2_restore_ip(struct amdgpu_device *adev) if (adev->ip_blocks[i].version->funcs->late_init) { r = adev->ip_blocks[i].version->funcs->late_init( - &adev->ip_blocks[i]); + (void *)adev); if (r) { dev_err(adev->dev, "late_init of IP block <%s> failed %d after reset\n", diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 66e911b3308e2..cc819cc2d736f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -3217,7 +3217,7 @@ static int amdgpu_device_ip_late_init(struct amdgpu_device *adev) if (!adev->ip_blocks[i].status.hw) continue; if (adev->ip_blocks[i].version->funcs->late_init) { - r = adev->ip_blocks[i].version->funcs->late_init(&adev->ip_blocks[i]); + r = adev->ip_blocks[i].version->funcs->late_init((void *)adev); if (r) { DRM_ERROR("late_init of IP block <%s> failed %d\n", adev->ip_blocks[i].version->funcs->name, r); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c index 3ef75f1a47f65..9953c7aad71b2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c @@ -784,9 +784,9 @@ static int umsch_mm_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int umsch_mm_late_init(struct amdgpu_ip_block *ip_block) +static int umsch_mm_late_init(void *handle) { - struct amdgpu_device *adev = ip_block->adev; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; if (amdgpu_in_reset(adev) || adev->in_s0ix || adev->in_suspend) return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index f0fb4717b40a3..e51f03c1d554b 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -7819,9 +7819,9 @@ static int gfx_v10_0_early_init(struct amdgpu_ip_block *ip_block) return gfx_v10_0_init_microcode(adev); } -static int gfx_v10_0_late_init(struct amdgpu_ip_block *ip_block) +static int gfx_v10_0_late_init(void *handle) { - struct amdgpu_device *adev = ip_block->adev; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; int r; r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index 6b22128ab004b..4322e7a494b5b 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -5021,9 +5021,9 @@ static int gfx_v11_0_early_init(struct amdgpu_ip_block *ip_block) return gfx_v11_0_init_microcode(adev); } -static int gfx_v11_0_late_init(struct amdgpu_ip_block *ip_block) +static int gfx_v11_0_late_init(void *handle) { - struct amdgpu_device *adev = ip_block->adev; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; int r; r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c index dc25fcb89b131..fd6e18808225d 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c @@ -3717,9 +3717,9 @@ static int gfx_v12_0_early_init(struct amdgpu_ip_block *ip_block) return gfx_v12_0_init_microcode(adev); } -static int gfx_v12_0_late_init(struct amdgpu_ip_block *ip_block) +static int gfx_v12_0_late_init(void *handle) { - struct amdgpu_device *adev = ip_block->adev; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; int r; r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index 77150c9f1e182..5401cae8f96af 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -4151,9 +4151,9 @@ static int gfx_v7_0_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int gfx_v7_0_late_init(struct amdgpu_ip_block *ip_block) +static int gfx_v7_0_late_init(void *handle) { - struct amdgpu_device *adev = ip_block->adev; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; int r; r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 8f9f8e6d57a12..8e018e0352d1b 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -5371,9 +5371,9 @@ static int gfx_v8_0_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int gfx_v8_0_late_init(struct amdgpu_ip_block *ip_block) +static int gfx_v8_0_late_init(void *handle) { - struct amdgpu_device *adev = ip_block->adev; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; int r; r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 3537c3fb63fe7..be7fdb199877c 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -4891,9 +4891,9 @@ static int gfx_v9_0_early_init(struct amdgpu_ip_block *ip_block) return gfx_v9_0_init_microcode(adev); } -static int gfx_v9_0_ecc_late_init(struct amdgpu_ip_block *ip_block) +static int gfx_v9_0_ecc_late_init(void *handle) { - struct amdgpu_device *adev = ip_block->adev; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; int r; /* @@ -4925,9 +4925,9 @@ static int gfx_v9_0_ecc_late_init(struct amdgpu_ip_block *ip_block) return 0; } -static int gfx_v9_0_late_init(struct amdgpu_ip_block *ip_block) +static int gfx_v9_0_late_init(void *handle) { - struct amdgpu_device *adev = ip_block->adev; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; int r; r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); @@ -4946,7 +4946,7 @@ static int gfx_v9_0_late_init(struct amdgpu_ip_block *ip_block) if (r) return r; - r = gfx_v9_0_ecc_late_init(ip_block); + r = gfx_v9_0_ecc_late_init(handle); if (r) return r; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index 7d425d2e7ab00..8fdae9f385c67 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -2529,9 +2529,9 @@ static int gfx_v9_4_3_early_init(struct amdgpu_ip_block *ip_block) return gfx_v9_4_3_init_microcode(adev); } -static int gfx_v9_4_3_late_init(struct amdgpu_ip_block *ip_block) +static int gfx_v9_4_3_late_init(void *handle) { - struct amdgpu_device *adev = ip_block->adev; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; int r; r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c index 2f1af50aae1ec..cf1fdc11c260e 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c @@ -650,9 +650,9 @@ static int gmc_v10_0_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int gmc_v10_0_late_init(struct amdgpu_ip_block *ip_block) +static int gmc_v10_0_late_init(void *handle) { - struct amdgpu_device *adev = ip_block->adev; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; int r; r = amdgpu_gmc_allocate_vm_inv_eng(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c index 82b905271547f..b2284564fafb3 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c @@ -621,9 +621,9 @@ static int gmc_v11_0_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int gmc_v11_0_late_init(struct amdgpu_ip_block *ip_block) +static int gmc_v11_0_late_init(void *handle) { - struct amdgpu_device *adev = ip_block->adev; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; int r; r = amdgpu_gmc_allocate_vm_inv_eng(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c index dcc44e688175e..95afd637c06d2 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c @@ -607,9 +607,9 @@ static int gmc_v12_0_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int gmc_v12_0_late_init(struct amdgpu_ip_block *ip_block) +static int gmc_v12_0_late_init(void *handle) { - struct amdgpu_device *adev = ip_block->adev; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; int r; r = amdgpu_gmc_allocate_vm_inv_eng(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c index b66707f7d5941..a2bad88ebeaac 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c @@ -782,9 +782,9 @@ static int gmc_v6_0_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int gmc_v6_0_late_init(struct amdgpu_ip_block *ip_block) +static int gmc_v6_0_late_init(void *handle) { - struct amdgpu_device *adev = ip_block->adev; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS) return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c index e2331a5aac0ee..a527a1b0aab0f 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c @@ -939,9 +939,9 @@ static int gmc_v7_0_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int gmc_v7_0_late_init(struct amdgpu_ip_block *ip_block) +static int gmc_v7_0_late_init(void *handle) { - struct amdgpu_device *adev = ip_block->adev; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS) return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index f5c1ebce73f4f..e40b4c84c23c7 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -1060,9 +1060,9 @@ static int gmc_v8_0_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int gmc_v8_0_late_init(struct amdgpu_ip_block *ip_block) +static int gmc_v8_0_late_init(void *handle) { - struct amdgpu_device *adev = ip_block->adev; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS) return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index 8cf8520f1dc2b..57ab55e46911d 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -1638,9 +1638,9 @@ static int gmc_v9_0_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int gmc_v9_0_late_init(struct amdgpu_ip_block *ip_block) +static int gmc_v9_0_late_init(void *handle) { - struct amdgpu_device *adev = ip_block->adev; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; int r; r = amdgpu_gmc_allocate_vm_inv_eng(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c index 4b0f83fe9dd98..f48e93f00e4ad 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c @@ -1674,9 +1674,9 @@ static int mes_v11_0_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int mes_v11_0_late_init(struct amdgpu_ip_block *ip_block) +static int mes_v11_0_late_init(void *handle) { - struct amdgpu_device *adev = ip_block->adev; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; /* it's only intended for use in mes_self_test case, not for s0ix and reset */ if (!amdgpu_in_reset(adev) && !adev->in_s0ix && !adev->in_suspend && diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c index f50071cf95b96..6685715fc4ba2 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c @@ -1636,9 +1636,9 @@ static int mes_v12_0_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int mes_v12_0_late_init(struct amdgpu_ip_block *ip_block) +static int mes_v12_0_late_init(void *handle) { - struct amdgpu_device *adev = ip_block->adev; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; /* it's only intended for use in mes_self_test case, not for s0ix and reset */ if (!amdgpu_in_reset(adev) && !adev->in_s0ix && !adev->in_suspend) diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index 4e8f9af1e2bec..d5229bc226b18 100644 --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c @@ -944,9 +944,9 @@ static int nv_common_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int nv_common_late_init(struct amdgpu_ip_block *ip_block) +static int nv_common_late_init(void *handle) { - struct amdgpu_device *adev = ip_block->adev; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; if (amdgpu_sriov_vf(adev)) { xgpu_nv_mailbox_get_irq(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index ccf0d531776d9..5953c8a7d816b 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c @@ -1781,9 +1781,9 @@ static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev, void *err_data, struct amdgpu_iv_entry *entry); -static int sdma_v4_0_late_init(struct amdgpu_ip_block *ip_block) +static int sdma_v4_0_late_init(void *handle) { - struct amdgpu_device *adev = ip_block->adev; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; sdma_v4_0_setup_ulv(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c index 9c7cea0890c98..adfc092995ce9 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c @@ -1318,9 +1318,9 @@ static int sdma_v4_4_2_process_ras_data_cb(struct amdgpu_device *adev, struct amdgpu_iv_entry *entry); #endif -static int sdma_v4_4_2_late_init(struct amdgpu_ip_block *ip_block) +static int sdma_v4_4_2_late_init(void *handle) { - struct amdgpu_device *adev = ip_block->adev; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; #if 0 struct ras_ih_if ih_info = { .cb = sdma_v4_4_2_process_ras_data_cb, diff --git a/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c b/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c index 475b7df3a9089..2ff6f11bddb66 100644 --- a/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c +++ b/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c @@ -213,7 +213,7 @@ static int sienna_cichlid_mode2_restore_ip(struct amdgpu_device *adev) if (adev->ip_blocks[i].version->funcs->late_init) { r = adev->ip_blocks[i].version->funcs->late_init( - &adev->ip_blocks[i]); + (void *)adev); if (r) { dev_err(adev->dev, "late_init of IP block <%s> failed %d after reset\n", diff --git a/drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.c b/drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.c index 5ea9090b5040a..71a2770e2a31a 100644 --- a/drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.c +++ b/drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.c @@ -208,7 +208,7 @@ static int smu_v13_0_10_mode2_restore_ip(struct amdgpu_device *adev) if (adev->ip_blocks[i].version->funcs->late_init) { r = adev->ip_blocks[i].version->funcs->late_init( - &adev->ip_blocks[i]); + (void *)adev); if (r) { dev_err(adev->dev, "late_init of IP block <%s> failed %d after reset\n", diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index dd1c1aacdd8e1..cb9793f3a4dda 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -1204,9 +1204,9 @@ static int soc15_common_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int soc15_common_late_init(struct amdgpu_ip_block *ip_block) +static int soc15_common_late_init(void *handle) { - struct amdgpu_device *adev = ip_block->adev; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; if (amdgpu_sriov_vf(adev)) xgpu_ai_mailbox_get_irq(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c index c4b950e75133f..8959aa18e0b9a 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc21.c +++ b/drivers/gpu/drm/amd/amdgpu/soc21.c @@ -794,9 +794,9 @@ static int soc21_common_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int soc21_common_late_init(struct amdgpu_ip_block *ip_block) +static int soc21_common_late_init(void *handle) { - struct amdgpu_device *adev = ip_block->adev; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; if (amdgpu_sriov_vf(adev)) { xgpu_nv_mailbox_get_irq(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/soc24.c b/drivers/gpu/drm/amd/amdgpu/soc24.c index b20dc81dc2574..c7ab7274af073 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc24.c +++ b/drivers/gpu/drm/amd/amdgpu/soc24.c @@ -440,9 +440,9 @@ static int soc24_common_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int soc24_common_late_init(struct amdgpu_ip_block *ip_block) +static int soc24_common_late_init(void *handle) { - struct amdgpu_device *adev = ip_block->adev; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; if (amdgpu_sriov_vf(adev)) xgpu_nv_mailbox_get_irq(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index 4996049dc1995..7a450ae9d3a75 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/drivers/gpu/drm/amd/amdgpu/vi.c @@ -1679,9 +1679,9 @@ static int vi_common_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int vi_common_late_init(struct amdgpu_ip_block *ip_block) +static int vi_common_late_init(void *handle) { - struct amdgpu_device *adev = ip_block->adev; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; if (amdgpu_sriov_vf(adev)) xgpu_vi_mailbox_get_irq(adev); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index d9bcf0ba06ad0..0e6a7db3cac64 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2629,9 +2629,9 @@ static int detect_mst_link_for_all_connectors(struct drm_device *dev) return ret; } -static int dm_late_init(struct amdgpu_ip_block *ip_block) +static int dm_late_init(void *handle) { - struct amdgpu_device *adev = ip_block->adev; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct dmcu_iram_parameters params; unsigned int linear_lut[16]; diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c index 2cd6cb991f29c..6119580453991 100644 --- a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c @@ -2965,10 +2965,10 @@ static int kv_dpm_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int kv_dpm_late_init(struct amdgpu_ip_block *ip_block) +static int kv_dpm_late_init(void *handle) { /* powerdown unused blocks for now */ - struct amdgpu_device *adev = ip_block->adev; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; if (!adev->pm.dpm_enabled) return 0; diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c index a4908f0402f1a..c9f230e61d132 100644 --- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c @@ -7621,10 +7621,10 @@ static int si_dpm_process_interrupt(struct amdgpu_device *adev, return 0; } -static int si_dpm_late_init(struct amdgpu_ip_block *ip_block) +static int si_dpm_late_init(void *handle) { int ret; - struct amdgpu_device *adev = ip_block->adev; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; if (!adev->pm.dpm_enabled) return 0; diff --git a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c index f193c77cc1413..ddb85f83bae26 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c +++ b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c @@ -215,9 +215,9 @@ static void pp_reserve_vram_for_smu(struct amdgpu_device *adev) } } -static int pp_late_init(struct amdgpu_ip_block *ip_block) +static int pp_late_init(void *handle) { - struct amdgpu_device *adev = ip_block->adev; + struct amdgpu_device *adev = handle; struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; if (hwmgr && hwmgr->pm_en) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index bc82ae41c2dda..27f14993116f0 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -826,9 +826,9 @@ static int smu_apply_default_config_table_settings(struct smu_context *smu) return smu_set_config_table(smu, &adev->pm.config_table); } -static int smu_late_init(struct amdgpu_ip_block *ip_block) +static int smu_late_init(void *handle) { - struct amdgpu_device *adev = ip_block->adev; + struct amdgpu_device *adev = (struct amdgpu_device *)handle; struct smu_context *smu = adev->powerplay.pp_handle; int ret = 0; @@ -2068,11 +2068,7 @@ static int smu_reset(struct smu_context *smu) if (ret) return ret; -<<<<<<< HEAD ret = smu_late_init(ip_block); -======= - ret = smu_late_init(&adev->ip_blocks[AMD_IP_BLOCK_TYPE_SMC]); ->>>>>>> 813dabea1d31 (drm/amdgpu: update the handle ptr in late_init) if (ret) return ret; From 5b9700158eeb7405252a2da7fbbbe10e18dd7034 Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Thu, 26 Sep 2024 13:29:24 +0530 Subject: [PATCH 1745/1868] drm/amdgpu: update the handle ptr in late_init MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Update the ptr handle to amdgpu_ip_block ptr in all the functions of late_init function ptr. Signed-off-by: Sunil Khatri Reviewed-by: Christian König (cherry picked from commit 813dabea1d31e017d948bc93bde568aff870c00d) --- drivers/gpu/drm/amd/amdgpu/aldebaran.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 10 +++++----- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/mes_v11_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/mes_v12_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/nv.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c | 2 +- drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.c | 2 +- drivers/gpu/drm/amd/amdgpu/soc15.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/soc21.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/soc24.c | 4 ++-- drivers/gpu/drm/amd/amdgpu/vi.c | 4 ++-- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 4 ++-- drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c | 4 ++-- drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c | 4 ++-- drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c | 4 ++-- drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c | 4 ++-- 33 files changed, 65 insertions(+), 65 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/aldebaran.c b/drivers/gpu/drm/amd/amdgpu/aldebaran.c index f99bf6bcec9d6..c1ff24335a0c5 100644 --- a/drivers/gpu/drm/amd/amdgpu/aldebaran.c +++ b/drivers/gpu/drm/amd/amdgpu/aldebaran.c @@ -304,7 +304,7 @@ static int aldebaran_mode2_restore_ip(struct amdgpu_device *adev) if (adev->ip_blocks[i].version->funcs->late_init) { r = adev->ip_blocks[i].version->funcs->late_init( - (void *)adev); + &adev->ip_blocks[i]); if (r) { dev_err(adev->dev, "late_init of IP block <%s> failed %d after reset\n", diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index cc819cc2d736f..66e911b3308e2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -3217,7 +3217,7 @@ static int amdgpu_device_ip_late_init(struct amdgpu_device *adev) if (!adev->ip_blocks[i].status.hw) continue; if (adev->ip_blocks[i].version->funcs->late_init) { - r = adev->ip_blocks[i].version->funcs->late_init((void *)adev); + r = adev->ip_blocks[i].version->funcs->late_init(&adev->ip_blocks[i]); if (r) { DRM_ERROR("late_init of IP block <%s> failed %d\n", adev->ip_blocks[i].version->funcs->name, r); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c index 9953c7aad71b2..3ef75f1a47f65 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c @@ -784,9 +784,9 @@ static int umsch_mm_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int umsch_mm_late_init(void *handle) +static int umsch_mm_late_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (amdgpu_in_reset(adev) || adev->in_s0ix || adev->in_suspend) return 0; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index e51f03c1d554b..f0fb4717b40a3 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -7819,9 +7819,9 @@ static int gfx_v10_0_early_init(struct amdgpu_ip_block *ip_block) return gfx_v10_0_init_microcode(adev); } -static int gfx_v10_0_late_init(void *handle) +static int gfx_v10_0_late_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c index 4322e7a494b5b..6b22128ab004b 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c @@ -5021,9 +5021,9 @@ static int gfx_v11_0_early_init(struct amdgpu_ip_block *ip_block) return gfx_v11_0_init_microcode(adev); } -static int gfx_v11_0_late_init(void *handle) +static int gfx_v11_0_late_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c index fd6e18808225d..dc25fcb89b131 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c @@ -3717,9 +3717,9 @@ static int gfx_v12_0_early_init(struct amdgpu_ip_block *ip_block) return gfx_v12_0_init_microcode(adev); } -static int gfx_v12_0_late_init(void *handle) +static int gfx_v12_0_late_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index 5401cae8f96af..77150c9f1e182 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c @@ -4151,9 +4151,9 @@ static int gfx_v7_0_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int gfx_v7_0_late_init(void *handle) +static int gfx_v7_0_late_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 8e018e0352d1b..8f9f8e6d57a12 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -5371,9 +5371,9 @@ static int gfx_v8_0_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int gfx_v8_0_late_init(void *handle) +static int gfx_v8_0_late_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index be7fdb199877c..3537c3fb63fe7 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -4891,9 +4891,9 @@ static int gfx_v9_0_early_init(struct amdgpu_ip_block *ip_block) return gfx_v9_0_init_microcode(adev); } -static int gfx_v9_0_ecc_late_init(void *handle) +static int gfx_v9_0_ecc_late_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; /* @@ -4925,9 +4925,9 @@ static int gfx_v9_0_ecc_late_init(void *handle) return 0; } -static int gfx_v9_0_late_init(void *handle) +static int gfx_v9_0_late_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); @@ -4946,7 +4946,7 @@ static int gfx_v9_0_late_init(void *handle) if (r) return r; - r = gfx_v9_0_ecc_late_init(handle); + r = gfx_v9_0_ecc_late_init(ip_block); if (r) return r; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index 8fdae9f385c67..7d425d2e7ab00 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -2529,9 +2529,9 @@ static int gfx_v9_4_3_early_init(struct amdgpu_ip_block *ip_block) return gfx_v9_4_3_init_microcode(adev); } -static int gfx_v9_4_3_late_init(void *handle) +static int gfx_v9_4_3_late_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c index cf1fdc11c260e..2f1af50aae1ec 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c @@ -650,9 +650,9 @@ static int gmc_v10_0_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int gmc_v10_0_late_init(void *handle) +static int gmc_v10_0_late_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; r = amdgpu_gmc_allocate_vm_inv_eng(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c index b2284564fafb3..82b905271547f 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c @@ -621,9 +621,9 @@ static int gmc_v11_0_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int gmc_v11_0_late_init(void *handle) +static int gmc_v11_0_late_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; r = amdgpu_gmc_allocate_vm_inv_eng(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c index 95afd637c06d2..dcc44e688175e 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c @@ -607,9 +607,9 @@ static int gmc_v12_0_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int gmc_v12_0_late_init(void *handle) +static int gmc_v12_0_late_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; r = amdgpu_gmc_allocate_vm_inv_eng(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c index a2bad88ebeaac..b66707f7d5941 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c @@ -782,9 +782,9 @@ static int gmc_v6_0_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int gmc_v6_0_late_init(void *handle) +static int gmc_v6_0_late_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS) return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c index a527a1b0aab0f..e2331a5aac0ee 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c @@ -939,9 +939,9 @@ static int gmc_v7_0_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int gmc_v7_0_late_init(void *handle) +static int gmc_v7_0_late_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS) return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index e40b4c84c23c7..f5c1ebce73f4f 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -1060,9 +1060,9 @@ static int gmc_v8_0_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int gmc_v8_0_late_init(void *handle) +static int gmc_v8_0_late_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (amdgpu_vm_fault_stop != AMDGPU_VM_FAULT_STOP_ALWAYS) return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index 57ab55e46911d..8cf8520f1dc2b 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -1638,9 +1638,9 @@ static int gmc_v9_0_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int gmc_v9_0_late_init(void *handle) +static int gmc_v9_0_late_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; int r; r = amdgpu_gmc_allocate_vm_inv_eng(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c index f48e93f00e4ad..4b0f83fe9dd98 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v11_0.c @@ -1674,9 +1674,9 @@ static int mes_v11_0_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int mes_v11_0_late_init(void *handle) +static int mes_v11_0_late_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; /* it's only intended for use in mes_self_test case, not for s0ix and reset */ if (!amdgpu_in_reset(adev) && !adev->in_s0ix && !adev->in_suspend && diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c index 6685715fc4ba2..f50071cf95b96 100644 --- a/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c +++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_0.c @@ -1636,9 +1636,9 @@ static int mes_v12_0_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int mes_v12_0_late_init(void *handle) +static int mes_v12_0_late_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; /* it's only intended for use in mes_self_test case, not for s0ix and reset */ if (!amdgpu_in_reset(adev) && !adev->in_s0ix && !adev->in_suspend) diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c index d5229bc226b18..4e8f9af1e2bec 100644 --- a/drivers/gpu/drm/amd/amdgpu/nv.c +++ b/drivers/gpu/drm/amd/amdgpu/nv.c @@ -944,9 +944,9 @@ static int nv_common_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int nv_common_late_init(void *handle) +static int nv_common_late_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (amdgpu_sriov_vf(adev)) { xgpu_nv_mailbox_get_irq(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c index 5953c8a7d816b..ccf0d531776d9 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c @@ -1781,9 +1781,9 @@ static int sdma_v4_0_process_ras_data_cb(struct amdgpu_device *adev, void *err_data, struct amdgpu_iv_entry *entry); -static int sdma_v4_0_late_init(void *handle) +static int sdma_v4_0_late_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; sdma_v4_0_setup_ulv(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c index adfc092995ce9..9c7cea0890c98 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c @@ -1318,9 +1318,9 @@ static int sdma_v4_4_2_process_ras_data_cb(struct amdgpu_device *adev, struct amdgpu_iv_entry *entry); #endif -static int sdma_v4_4_2_late_init(void *handle) +static int sdma_v4_4_2_late_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; #if 0 struct ras_ih_if ih_info = { .cb = sdma_v4_4_2_process_ras_data_cb, diff --git a/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c b/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c index 2ff6f11bddb66..475b7df3a9089 100644 --- a/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c +++ b/drivers/gpu/drm/amd/amdgpu/sienna_cichlid.c @@ -213,7 +213,7 @@ static int sienna_cichlid_mode2_restore_ip(struct amdgpu_device *adev) if (adev->ip_blocks[i].version->funcs->late_init) { r = adev->ip_blocks[i].version->funcs->late_init( - (void *)adev); + &adev->ip_blocks[i]); if (r) { dev_err(adev->dev, "late_init of IP block <%s> failed %d after reset\n", diff --git a/drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.c b/drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.c index 71a2770e2a31a..5ea9090b5040a 100644 --- a/drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.c +++ b/drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.c @@ -208,7 +208,7 @@ static int smu_v13_0_10_mode2_restore_ip(struct amdgpu_device *adev) if (adev->ip_blocks[i].version->funcs->late_init) { r = adev->ip_blocks[i].version->funcs->late_init( - (void *)adev); + &adev->ip_blocks[i]); if (r) { dev_err(adev->dev, "late_init of IP block <%s> failed %d after reset\n", diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index cb9793f3a4dda..dd1c1aacdd8e1 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -1204,9 +1204,9 @@ static int soc15_common_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int soc15_common_late_init(void *handle) +static int soc15_common_late_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (amdgpu_sriov_vf(adev)) xgpu_ai_mailbox_get_irq(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c index 8959aa18e0b9a..c4b950e75133f 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc21.c +++ b/drivers/gpu/drm/amd/amdgpu/soc21.c @@ -794,9 +794,9 @@ static int soc21_common_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int soc21_common_late_init(void *handle) +static int soc21_common_late_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (amdgpu_sriov_vf(adev)) { xgpu_nv_mailbox_get_irq(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/soc24.c b/drivers/gpu/drm/amd/amdgpu/soc24.c index c7ab7274af073..b20dc81dc2574 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc24.c +++ b/drivers/gpu/drm/amd/amdgpu/soc24.c @@ -440,9 +440,9 @@ static int soc24_common_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int soc24_common_late_init(void *handle) +static int soc24_common_late_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (amdgpu_sriov_vf(adev)) xgpu_nv_mailbox_get_irq(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index 7a450ae9d3a75..4996049dc1995 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/drivers/gpu/drm/amd/amdgpu/vi.c @@ -1679,9 +1679,9 @@ static int vi_common_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int vi_common_late_init(void *handle) +static int vi_common_late_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (amdgpu_sriov_vf(adev)) xgpu_vi_mailbox_get_irq(adev); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 0e6a7db3cac64..d9bcf0ba06ad0 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -2629,9 +2629,9 @@ static int detect_mst_link_for_all_connectors(struct drm_device *dev) return ret; } -static int dm_late_init(void *handle) +static int dm_late_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; struct dmcu_iram_parameters params; unsigned int linear_lut[16]; diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c index 6119580453991..2cd6cb991f29c 100644 --- a/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/kv_dpm.c @@ -2965,10 +2965,10 @@ static int kv_dpm_early_init(struct amdgpu_ip_block *ip_block) return 0; } -static int kv_dpm_late_init(void *handle) +static int kv_dpm_late_init(struct amdgpu_ip_block *ip_block) { /* powerdown unused blocks for now */ - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (!adev->pm.dpm_enabled) return 0; diff --git a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c index c9f230e61d132..a4908f0402f1a 100644 --- a/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c +++ b/drivers/gpu/drm/amd/pm/legacy-dpm/si_dpm.c @@ -7621,10 +7621,10 @@ static int si_dpm_process_interrupt(struct amdgpu_device *adev, return 0; } -static int si_dpm_late_init(void *handle) +static int si_dpm_late_init(struct amdgpu_ip_block *ip_block) { int ret; - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; if (!adev->pm.dpm_enabled) return 0; diff --git a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c index ddb85f83bae26..f193c77cc1413 100644 --- a/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c +++ b/drivers/gpu/drm/amd/pm/powerplay/amd_powerplay.c @@ -215,9 +215,9 @@ static void pp_reserve_vram_for_smu(struct amdgpu_device *adev) } } -static int pp_late_init(void *handle) +static int pp_late_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = handle; + struct amdgpu_device *adev = ip_block->adev; struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle; if (hwmgr && hwmgr->pm_en) diff --git a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c index 27f14993116f0..a6011cdf79f0d 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c @@ -826,9 +826,9 @@ static int smu_apply_default_config_table_settings(struct smu_context *smu) return smu_set_config_table(smu, &adev->pm.config_table); } -static int smu_late_init(void *handle) +static int smu_late_init(struct amdgpu_ip_block *ip_block) { - struct amdgpu_device *adev = (struct amdgpu_device *)handle; + struct amdgpu_device *adev = ip_block->adev; struct smu_context *smu = adev->powerplay.pp_handle; int ret = 0; From 40cc451500bddbad7f539e173ce8c041d73ac6d2 Mon Sep 17 00:00:00 2001 From: Yang Su Date: Fri, 11 Oct 2024 13:41:00 +0800 Subject: [PATCH 1746/1868] Bump AMDGPU version to 6.10.4 Signed-off-by: Yang Su --- drivers/gpu/drm/amd/dkms/configure.ac | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/configure.ac b/drivers/gpu/drm/amd/dkms/configure.ac index be3642117a8b2..468ecba24e512 100644 --- a/drivers/gpu/drm/amd/dkms/configure.ac +++ b/drivers/gpu/drm/amd/dkms/configure.ac @@ -1,4 +1,4 @@ -AC_INIT(amdgpu-dkms, 6.10.3) +AC_INIT(amdgpu-dkms, 6.10.4) AC_LANG(C) AC_CONFIG_AUX_DIR([config]) From 3663d61b583089dec9ca5e487eae0ff4a67f0f2f Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Fri, 11 Oct 2024 02:10:22 -0400 Subject: [PATCH 1747/1868] Revert "drm/amd/pm: update workload mask after the setting" This reverts commit a097cff1e6e627ca08f27c6fe2679905684ef0b5. The reverted patch causes a Jira issue SWDEV-490889. Reason for revert: Change-Id: I7792660f85826b73bf53461ef185e37fcbdbb1f7 --- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 6 +----- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 3 --- drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c | 6 +----- 3 files changed, 2 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c index d5d74e4913223..c9639141792f4 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c @@ -2569,14 +2569,10 @@ static int smu_v13_0_0_set_power_profile_mode(struct smu_context *smu, } } - ret = smu_cmn_send_smc_msg_with_param(smu, + return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask, workload_mask, NULL); - if (!ret) - smu->workload_mask = workload_mask; - - return ret; } static bool smu_v13_0_0_is_mode1_reset_supported(struct smu_context *smu) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c index b891a5e0a3969..7bc95c4043778 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c @@ -2501,11 +2501,8 @@ static int smu_v13_0_7_set_power_profile_mode(struct smu_context *smu, long *inp return -EINVAL; ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask, 1 << workload_type, NULL); - if (ret) dev_err(smu->adev->dev, "[%s] Failed to set work load mask!", __func__); - else - smu->workload_mask = (1 << workload_type); return ret; } diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c index 5899d01fa73d3..43820d7d2c54a 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c @@ -1861,14 +1861,10 @@ static int smu_v14_0_2_set_power_profile_mode(struct smu_context *smu, if (workload_type < 0) return -EINVAL; - ret = smu_cmn_send_smc_msg_with_param(smu, + return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask, 1 << workload_type, NULL); - if (!ret) - smu->workload_mask = 1 << workload_type; - - return ret; } static int smu_v14_0_2_baco_enter(struct smu_context *smu) From 4267e728e07f1f92812b0ce91bae55e377e8256d Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Fri, 11 Oct 2024 02:10:22 -0400 Subject: [PATCH 1748/1868] Revert "drm/amd/pm: update workload mask after the setting" This reverts commit a097cff1e6e627ca08f27c6fe2679905684ef0b5. The reverted patch causes a Jira issue SWDEV-490889. Reason for revert: Change-Id: I7792660f85826b73bf53461ef185e37fcbdbb1f7 --- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 6 +----- drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c | 3 --- drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c | 6 +----- 3 files changed, 2 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c index d5d74e4913223..c9639141792f4 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c @@ -2569,14 +2569,10 @@ static int smu_v13_0_0_set_power_profile_mode(struct smu_context *smu, } } - ret = smu_cmn_send_smc_msg_with_param(smu, + return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask, workload_mask, NULL); - if (!ret) - smu->workload_mask = workload_mask; - - return ret; } static bool smu_v13_0_0_is_mode1_reset_supported(struct smu_context *smu) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c index b891a5e0a3969..7bc95c4043778 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c @@ -2501,11 +2501,8 @@ static int smu_v13_0_7_set_power_profile_mode(struct smu_context *smu, long *inp return -EINVAL; ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask, 1 << workload_type, NULL); - if (ret) dev_err(smu->adev->dev, "[%s] Failed to set work load mask!", __func__); - else - smu->workload_mask = (1 << workload_type); return ret; } diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c index 5899d01fa73d3..43820d7d2c54a 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c @@ -1861,14 +1861,10 @@ static int smu_v14_0_2_set_power_profile_mode(struct smu_context *smu, if (workload_type < 0) return -EINVAL; - ret = smu_cmn_send_smc_msg_with_param(smu, + return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask, 1 << workload_type, NULL); - if (!ret) - smu->workload_mask = 1 << workload_type; - - return ret; } static int smu_v14_0_2_baco_enter(struct smu_context *smu) From 1bafdfc0b2b14b623d381690640b4d328ca1711f Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Wed, 25 Sep 2024 20:29:48 +0530 Subject: [PATCH 1749/1868] drm/amdkfd: Fix kdoc entry for 'get_wave_count()' function parameters MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Update kdoc entries to reflect the function's parameters. The descriptor for the 'queue_cnt' parameter has been added, and the incorrect mentions of 'wave_cnt' and 'vmid', which are not parameters but local variables, have been removed. Fixes the below with gcc W=1: drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c:954: warning: Function parameter or struct member 'queue_cnt' not described in 'get_wave_count' drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c:954: warning: Excess function parameter 'wave_cnt' description in 'get_wave_count' drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c:954: warning: Excess function parameter 'vmid' description in 'get_wave_count' Cc: Ramesh Errabolu Cc: Harish Kasiviswanathan Cc: Felix Kuehling Cc: Christian König Cc: Alex Deucher Signed-off-by: Srinivasan Shanmugam Reviewed-by: Mukul Joshi (cherry picked from commit 79fdad4eccfdb98204c4e3c74ee78fd31513f6fc) --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c index 52a8aea4d9b26..8ae676146e1c1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c @@ -944,9 +944,7 @@ static void unlock_spi_csq_mutexes(struct amdgpu_device *adev) * * @adev: Handle of device whose registers are to be read * @queue_idx: Index of queue in the queue-map bit-field - * @wave_cnt: Output parameter updated with number of waves in flight - * @vmid: Output parameter updated with VMID of queue whose wave count - * is being collected + * @queue_cnt: Stores the wave count and doorbell offset for an active queue * @inst: xcc's instance number on a multi-XCC setup */ static void get_wave_count(struct amdgpu_device *adev, int queue_idx, From 6dda5f1798c73cdf1c2455a5a521c64d08b56a7f Mon Sep 17 00:00:00 2001 From: Julia Lawall Date: Mon, 30 Sep 2024 13:21:11 +0200 Subject: [PATCH 1750/1868] drm/amd/display: Reorganize kerneldoc parameter names Reorganize kerneldoc parameter names to match the parameter order in the function header. Problems identified using Coccinelle. Reviewed-by: Harry Wentland Signed-off-by: Julia Lawall Signed-off-by: Alex Deucher (cherry picked from commit 95eb6b5dc14b954f439e95abed721a24a6065cae) --- drivers/gpu/drm/amd/display/dc/core/dc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 8d5a4e4e234fc..309b121ba87cb 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -621,8 +621,8 @@ dc_stream_forward_crc_window(struct dc_stream_state *stream, * dc_stream_configure_crc() - Configure CRC capture for the given stream. * @dc: DC Object * @stream: The stream to configure CRC on. - * @enable: Enable CRC if true, disable otherwise. * @crc_window: CRC window (x/y start/end) information + * @enable: Enable CRC if true, disable otherwise. * @continuous: Capture CRC on every frame if true. Otherwise, only capture * once. * From ea4ac90f9e243ff80d63a55a4de8ad90a7939862 Mon Sep 17 00:00:00 2001 From: Igor Artemiev Date: Fri, 27 Sep 2024 18:07:19 +0300 Subject: [PATCH 1751/1868] drm/radeon/r600_cs: Fix possible int overflow in r600_packet3_check() It is possible, although unlikely, that an integer overflow will occur when the result of radeon_get_ib_value() is shifted to the left. Avoid it by casting one of the operands to larger data type (u64). Found by Linux Verification Center (linuxtesting.org) with static analysis tool SVACE. Signed-off-by: Igor Artemiev Signed-off-by: Alex Deucher (cherry picked from commit 7d9131c40fc100003dca99e634357bda6d7c2ac9) --- drivers/gpu/drm/radeon/r600_cs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c index 1b2d31c4d77ca..ac77d1246b945 100644 --- a/drivers/gpu/drm/radeon/r600_cs.c +++ b/drivers/gpu/drm/radeon/r600_cs.c @@ -2104,7 +2104,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p, return -EINVAL; } - offset = radeon_get_ib_value(p, idx+1) << 8; + offset = (u64)radeon_get_ib_value(p, idx+1) << 8; if (offset != track->vgt_strmout_bo_offset[idx_value]) { DRM_ERROR("bad STRMOUT_BASE_UPDATE, bo offset does not match: 0x%llx, 0x%x\n", offset, track->vgt_strmout_bo_offset[idx_value]); From 968203fba328ae72cc873d3cb4a395cafc04a633 Mon Sep 17 00:00:00 2001 From: Yang Su Date: Thu, 17 Oct 2024 13:40:04 +0800 Subject: [PATCH 1752/1868] Bump AMDGPU version to 6.10.5 Signed-off-by: Yang Su --- drivers/gpu/drm/amd/dkms/configure.ac | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/dkms/configure.ac b/drivers/gpu/drm/amd/dkms/configure.ac index 468ecba24e512..ec686045c8995 100644 --- a/drivers/gpu/drm/amd/dkms/configure.ac +++ b/drivers/gpu/drm/amd/dkms/configure.ac @@ -1,4 +1,4 @@ -AC_INIT(amdgpu-dkms, 6.10.4) +AC_INIT(amdgpu-dkms, 6.10.5) AC_LANG(C) AC_CONFIG_AUX_DIR([config]) From 0d1bb57249bba695e7d035392878dffd66ee5a41 Mon Sep 17 00:00:00 2001 From: Chengjun Yao Date: Thu, 17 Oct 2024 01:47:29 -0400 Subject: [PATCH 1753/1868] Revert "drm/amdgpu: Add supported partition mode node" This reverts commit 1f70f4627cee281f5cb5297a2c27a44cd23dec47. The reverted patch causes BUG 23608:"UBSAN: shift-out-of-bounds when reload driver with PSP TOS change" Change-Id: I372a5437b247522e589ec602f466d9fcaac1d258 --- drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c | 45 ++----------------------- 1 file changed, 3 insertions(+), 42 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c index 6e0d6da1df500..39b181e2d9546 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c @@ -462,15 +462,6 @@ static struct attribute *xcp_cfg_res_sysfs_attrs[] = { &XCP_CFG_SYSFS_RES_ATTR_PTR(num_inst), &XCP_CFG_SYSFS_RES_ATTR_PTR(num_shared), NULL }; - -static const char *xcp_desc[] = { - [AMDGPU_SPX_PARTITION_MODE] = "SPX", - [AMDGPU_DPX_PARTITION_MODE] = "DPX", - [AMDGPU_TPX_PARTITION_MODE] = "TPX", - [AMDGPU_QPX_PARTITION_MODE] = "QPX", - [AMDGPU_CPX_PARTITION_MODE] = "CPX", -}; - #ifdef HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE ATTRIBUTE_GROUPS(xcp_cfg_res_sysfs); #endif @@ -525,27 +516,6 @@ static int amdgpu_xcp_get_res_info(struct amdgpu_xcp_mgr *xcp_mgr, } #define to_xcp_cfg(x) container_of(x, struct amdgpu_xcp_cfg, kobj) -static ssize_t supported_xcp_configs_show(struct kobject *kobj, - struct kobj_attribute *attr, char *buf) -{ - struct amdgpu_xcp_cfg *xcp_cfg = to_xcp_cfg(kobj); - struct amdgpu_xcp_mgr *xcp_mgr = xcp_cfg->xcp_mgr; - int size = 0, mode; - char *sep = ""; - - if (!xcp_mgr || !xcp_mgr->supp_xcp_modes) - return sysfs_emit(buf, "Not supported\n"); - - for_each_inst(mode, xcp_mgr->supp_xcp_modes) { - size += sysfs_emit_at(buf, size, "%s%s", sep, xcp_desc[mode]); - sep = ", "; - } - - size += sysfs_emit_at(buf, size, "\n"); - - return size; -} - static ssize_t xcp_config_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf) { @@ -603,15 +573,6 @@ static const struct kobj_type xcp_cfg_sysfs_ktype = { .sysfs_ops = &kobj_sysfs_ops, }; -static struct kobj_attribute supp_part_sysfs_mode = - __ATTR_RO(supported_xcp_configs); - -static const struct attribute *xcp_attrs[] = { - &supp_part_sysfs_mode.attr, - &xcp_cfg_sysfs_mode.attr, - NULL, -}; - void amdgpu_xcp_cfg_sysfs_init(struct amdgpu_device *adev) { struct amdgpu_xcp_res_details *xcp_res; @@ -631,7 +592,7 @@ void amdgpu_xcp_cfg_sysfs_init(struct amdgpu_device *adev) if (r) goto err1; - r = sysfs_create_files(&xcp_cfg->kobj, xcp_attrs); + r = sysfs_create_file(&xcp_cfg->kobj, &xcp_cfg_sysfs_mode.attr); if (r) goto err1; @@ -659,7 +620,7 @@ void amdgpu_xcp_cfg_sysfs_init(struct amdgpu_device *adev) kobject_put(&xcp_res->kobj); } - sysfs_remove_files(&xcp_cfg->kobj, xcp_attrs); + sysfs_remove_file(&xcp_cfg->kobj, &xcp_cfg_sysfs_mode.attr); err1: kobject_put(&xcp_cfg->kobj); } @@ -679,6 +640,6 @@ void amdgpu_xcp_cfg_sysfs_fini(struct amdgpu_device *adev) kobject_put(&xcp_res->kobj); } - sysfs_remove_files(&xcp_cfg->kobj, xcp_attrs); + sysfs_remove_file(&xcp_cfg->kobj, &xcp_cfg_sysfs_mode.attr); kobject_put(&xcp_cfg->kobj); } From 2bcbd74e89de4c3ffafa34899921c319f432ced8 Mon Sep 17 00:00:00 2001 From: chengjya Date: Thu, 17 Oct 2024 13:56:52 +0800 Subject: [PATCH 1754/1868] Revert "drm/amdgpu: Add sysfs nodes to get xcp details" This reverts commit 627f3798d53d1f1f966c74fecd05b99a411bae39. The reverted patch causes BUG 23608:"UBSAN: shift-out-of-bounds when reload driver with PSP TOS change" --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 - drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c | 210 --------------------- drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h | 5 - 3 files changed, 217 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 66e911b3308e2..c6763f1ffb582 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -4503,7 +4503,6 @@ int amdgpu_device_init(struct amdgpu_device *adev, amdgpu_fru_sysfs_init(adev); amdgpu_reg_state_sysfs_init(adev); - amdgpu_xcp_cfg_sysfs_init(adev); if (IS_ENABLED(CONFIG_PERF_EVENTS)) r = amdgpu_pmu_init(adev); @@ -4630,7 +4629,6 @@ void amdgpu_device_fini_hw(struct amdgpu_device *adev) amdgpu_fru_sysfs_fini(adev); amdgpu_reg_state_sysfs_fini(adev); - amdgpu_xcp_cfg_sysfs_fini(adev); /* disable ras feature must before hw fini */ amdgpu_ras_pre_fini(adev); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c index 39b181e2d9546..a6d456ec6aeb1 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.c @@ -433,213 +433,3 @@ void amdgpu_xcp_release_sched(struct amdgpu_device *adev, } } -#define XCP_CFG_SYSFS_RES_ATTR_SHOW(_name) \ - static ssize_t amdgpu_xcp_res_sysfs_##_name##_show( \ - struct amdgpu_xcp_res_details *xcp_res, char *buf) \ - { \ - return sysfs_emit(buf, "%d\n", xcp_res->_name); \ - } - -struct amdgpu_xcp_res_sysfs_attribute { - struct attribute attr; - ssize_t (*show)(struct amdgpu_xcp_res_details *xcp_res, char *buf); -}; - -#define XCP_CFG_SYSFS_RES_ATTR(_name) \ - struct amdgpu_xcp_res_sysfs_attribute xcp_res_sysfs_attr_##_name = { \ - .attr = { .name = __stringify(_name), .mode = 0400 }, \ - .show = amdgpu_xcp_res_sysfs_##_name##_show, \ - } - -XCP_CFG_SYSFS_RES_ATTR_SHOW(num_inst) -XCP_CFG_SYSFS_RES_ATTR(num_inst); -XCP_CFG_SYSFS_RES_ATTR_SHOW(num_shared) -XCP_CFG_SYSFS_RES_ATTR(num_shared); - -#define XCP_CFG_SYSFS_RES_ATTR_PTR(_name) xcp_res_sysfs_attr_##_name.attr - -static struct attribute *xcp_cfg_res_sysfs_attrs[] = { - &XCP_CFG_SYSFS_RES_ATTR_PTR(num_inst), - &XCP_CFG_SYSFS_RES_ATTR_PTR(num_shared), NULL -}; -#ifdef HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE -ATTRIBUTE_GROUPS(xcp_cfg_res_sysfs); -#endif - -#define to_xcp_attr(x) \ - container_of(x, struct amdgpu_xcp_res_sysfs_attribute, attr) -#define to_xcp_res(x) container_of(x, struct amdgpu_xcp_res_details, kobj) - -static ssize_t xcp_cfg_res_sysfs_attr_show(struct kobject *kobj, - struct attribute *attr, char *buf) -{ - struct amdgpu_xcp_res_sysfs_attribute *attribute; - struct amdgpu_xcp_res_details *xcp_res; - - attribute = to_xcp_attr(attr); - xcp_res = to_xcp_res(kobj); - - if (!attribute->show) - return -EIO; - - return attribute->show(xcp_res, buf); -} - -static const struct sysfs_ops xcp_cfg_res_sysfs_ops = { - .show = xcp_cfg_res_sysfs_attr_show, -}; - -static const struct kobj_type xcp_cfg_res_sysfs_ktype = { - .sysfs_ops = &xcp_cfg_res_sysfs_ops, -#ifdef HAVE_DEFAULT_GROUP_IN_KOBJ_TYPE - .default_groups = xcp_cfg_res_sysfs_groups, -#else - .default_attrs = xcp_cfg_res_sysfs_attrs, -#endif -}; - -const char *xcp_res_names[] = { - [AMDGPU_XCP_RES_XCC] = "xcc", - [AMDGPU_XCP_RES_DMA] = "dma", - [AMDGPU_XCP_RES_DEC] = "dec", - [AMDGPU_XCP_RES_JPEG] = "jpeg", -}; - -static int amdgpu_xcp_get_res_info(struct amdgpu_xcp_mgr *xcp_mgr, - int mode, - struct amdgpu_xcp_cfg *xcp_cfg) -{ - if (xcp_mgr->funcs && xcp_mgr->funcs->get_xcp_res_info) - return xcp_mgr->funcs->get_xcp_res_info(xcp_mgr, mode, xcp_cfg); - - return -EOPNOTSUPP; -} - -#define to_xcp_cfg(x) container_of(x, struct amdgpu_xcp_cfg, kobj) -static ssize_t xcp_config_show(struct kobject *kobj, - struct kobj_attribute *attr, char *buf) -{ - struct amdgpu_xcp_cfg *xcp_cfg = to_xcp_cfg(kobj); - - return sysfs_emit(buf, "%s\n", - amdgpu_gfx_compute_mode_desc(xcp_cfg->mode)); -} - -static ssize_t xcp_config_store(struct kobject *kobj, - struct kobj_attribute *attr, - const char *buf, size_t size) -{ - struct amdgpu_xcp_cfg *xcp_cfg = to_xcp_cfg(kobj); - int mode, r; - - if (!strncasecmp("SPX", buf, strlen("SPX"))) - mode = AMDGPU_SPX_PARTITION_MODE; - else if (!strncasecmp("DPX", buf, strlen("DPX"))) - mode = AMDGPU_DPX_PARTITION_MODE; - else if (!strncasecmp("TPX", buf, strlen("TPX"))) - mode = AMDGPU_TPX_PARTITION_MODE; - else if (!strncasecmp("QPX", buf, strlen("QPX"))) - mode = AMDGPU_QPX_PARTITION_MODE; - else if (!strncasecmp("CPX", buf, strlen("CPX"))) - mode = AMDGPU_CPX_PARTITION_MODE; - else - return -EINVAL; - - r = amdgpu_xcp_get_res_info(xcp_cfg->xcp_mgr, mode, xcp_cfg); - - if (r) - return r; - - xcp_cfg->mode = mode; - return size; -} - -static struct kobj_attribute xcp_cfg_sysfs_mode = -#ifdef __ATTR_RW_MODE - __ATTR_RW_MODE(xcp_config, 0644); -#else - __ATTR(xcp_config, 0644, xcp_config_show, xcp_config_store); -#endif - -static void xcp_cfg_sysfs_release(struct kobject *kobj) -{ - struct amdgpu_xcp_cfg *xcp_cfg = to_xcp_cfg(kobj); - - kfree(xcp_cfg); -} - -static const struct kobj_type xcp_cfg_sysfs_ktype = { - .release = xcp_cfg_sysfs_release, - .sysfs_ops = &kobj_sysfs_ops, -}; - -void amdgpu_xcp_cfg_sysfs_init(struct amdgpu_device *adev) -{ - struct amdgpu_xcp_res_details *xcp_res; - struct amdgpu_xcp_cfg *xcp_cfg; - int i, r, j, rid; - - if (!adev->xcp_mgr) - return; - - xcp_cfg = kzalloc(sizeof(*xcp_cfg), GFP_KERNEL); - if (!xcp_cfg) - return; - xcp_cfg->xcp_mgr = adev->xcp_mgr; - - r = kobject_init_and_add(&xcp_cfg->kobj, &xcp_cfg_sysfs_ktype, - &adev->dev->kobj, "compute_partition_config"); - if (r) - goto err1; - - r = sysfs_create_file(&xcp_cfg->kobj, &xcp_cfg_sysfs_mode.attr); - if (r) - goto err1; - - r = amdgpu_xcp_get_res_info(xcp_cfg->xcp_mgr, xcp_cfg->xcp_mgr->mode, xcp_cfg); - if (r) - goto err1; - - xcp_cfg->mode = xcp_cfg->xcp_mgr->mode; - for (i = 0; i < xcp_cfg->num_res; i++) { - xcp_res = &xcp_cfg->xcp_res[i]; - rid = xcp_res->id; - r = kobject_init_and_add(&xcp_res->kobj, - &xcp_cfg_res_sysfs_ktype, - &xcp_cfg->kobj, "%s", - xcp_res_names[rid]); - if (r) - goto err; - } - - adev->xcp_mgr->xcp_cfg = xcp_cfg; - return; -err: - for (j = 0; j < i; j++) { - xcp_res = &xcp_cfg->xcp_res[i]; - kobject_put(&xcp_res->kobj); - } - - sysfs_remove_file(&xcp_cfg->kobj, &xcp_cfg_sysfs_mode.attr); -err1: - kobject_put(&xcp_cfg->kobj); -} - -void amdgpu_xcp_cfg_sysfs_fini(struct amdgpu_device *adev) -{ - struct amdgpu_xcp_res_details *xcp_res; - struct amdgpu_xcp_cfg *xcp_cfg; - int i; - - if (!adev->xcp_mgr) - return; - - xcp_cfg = adev->xcp_mgr->xcp_cfg; - for (i = 0; i < xcp_cfg->num_res; i++) { - xcp_res = &xcp_cfg->xcp_res[i]; - kobject_put(&xcp_res->kobj); - } - - sysfs_remove_file(&xcp_cfg->kobj, &xcp_cfg_sysfs_mode.attr); - kobject_put(&xcp_cfg->kobj); -} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h index c0ec1ad4a606c..3aa3996c0250d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h @@ -68,7 +68,6 @@ struct amdgpu_xcp_res_details { enum amdgpu_xcp_res_id id; u8 num_inst; u8 num_shared; - struct kobject kobj; }; struct amdgpu_xcp_cfg { @@ -76,7 +75,6 @@ struct amdgpu_xcp_cfg { struct amdgpu_xcp_res_details xcp_res[AMDGPU_XCP_RES_MAX]; u8 num_res; struct amdgpu_xcp_mgr *xcp_mgr; - struct kobject kobj; }; struct amdgpu_xcp_ip_funcs { @@ -174,9 +172,6 @@ int amdgpu_xcp_open_device(struct amdgpu_device *adev, void amdgpu_xcp_release_sched(struct amdgpu_device *adev, struct amdgpu_ctx_entity *entity); -void amdgpu_xcp_cfg_sysfs_init(struct amdgpu_device *adev); -void amdgpu_xcp_cfg_sysfs_fini(struct amdgpu_device *adev); - #define amdgpu_xcp_select_scheds(adev, e, c, d, x, y) \ ((adev)->xcp_mgr && (adev)->xcp_mgr->funcs && \ (adev)->xcp_mgr->funcs->select_scheds ? \ From 6f0fe0cfece1c9220d547933a4fca985c536dc0c Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 15 Oct 2024 15:55:10 -0400 Subject: [PATCH 1755/1868] Revert "drm/amdgpu/gfx9: put queue resets behind a debug option" This reverts commit 7c1a2d8aba6cadde0cc542b2d805edc0be667e79. Extended validation has completed successfully, so enable these features by default. Acked-by: Jiadong Zhu Signed-off-by: Alex Deucher Cc: Jonathan Kim Cc: Jiadong Zhu --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c | 4 ---- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ---- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 6 ------ 3 files changed, 14 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c index 8ae676146e1c1..9e0e664dbc4f0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c @@ -1131,10 +1131,6 @@ uint64_t kgd_gfx_v9_hqd_get_pq_addr(struct amdgpu_device *adev, uint32_t low, high; uint64_t queue_addr = 0; - if (!adev->debug_exp_resets && - !adev->gfx.num_gfx_rings) - return 0; - kgd_gfx_v9_acquire_queue(adev, pipe_id, queue_id, inst); amdgpu_gfx_rlc_enter_safe_mode(adev, inst); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index 3537c3fb63fe7..c53cfa14c70f5 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -7387,10 +7387,6 @@ static int gfx_v9_0_reset_kcq(struct amdgpu_ring *ring, unsigned long flags; int i, r; - if (!adev->debug_exp_resets && - !adev->gfx.num_gfx_rings) - return -EINVAL; - if (amdgpu_sriov_vf(adev)) return -EINVAL; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index 7d425d2e7ab00..4968b6db62b46 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -3058,9 +3058,6 @@ static void gfx_v9_4_3_ring_soft_recovery(struct amdgpu_ring *ring, struct amdgpu_device *adev = ring->adev; uint32_t value = 0; - if (!adev->debug_exp_resets) - return; - value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); @@ -3576,9 +3573,6 @@ static int gfx_v9_4_3_reset_kcq(struct amdgpu_ring *ring, unsigned long flags; int r; - if (!adev->debug_exp_resets) - return -EINVAL; - if (amdgpu_sriov_vf(adev)) return -EINVAL; From a34acbf1618a8d115ba86c19a135e24181f8eb72 Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Thu, 18 Jul 2024 18:55:06 +0800 Subject: [PATCH 1756/1868] drm/amd/pm: Use same metric table for APU Use same metric table for APU and Non APU systems for smu_v_13_0_6 to get metric data based on newer pmfw versions v2: Use inline func to check for unified metrics support Signed-off-by: Asad Kamal Reviewed-by: Lijo Lazar --- .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 102 ++++++++++-------- 1 file changed, 55 insertions(+), 47 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index c70b6ef5e5f3a..52eff3dab8a80 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -102,6 +102,12 @@ MODULE_FIRMWARE("amdgpu/smu_13_0_14.bin"); #define MCA_BANK_IPID(_ip, _hwid, _type) \ [AMDGPU_MCA_IP_##_ip] = { .hwid = _hwid, .mcatype = _type, } +static inline bool smu_v13_0_6_is_unified_metrics(struct smu_context *smu) +{ + return (smu->adev->flags & AMD_IS_APU) && + smu->smc_fw_version <= 0x4556900; +} + struct mca_bank_ipid { enum amdgpu_mca_ip ip; uint16_t hwid; @@ -260,7 +266,7 @@ struct PPTable_t { #define SMUQ10_TO_UINT(x) ((x) >> 10) #define SMUQ10_FRAC(x) ((x) & 0x3ff) #define SMUQ10_ROUND(x) ((SMUQ10_TO_UINT(x)) + ((SMUQ10_FRAC(x)) >= 0x200)) -#define GET_METRIC_FIELD(field) ((adev->flags & AMD_IS_APU) ?\ +#define GET_METRIC_FIELD(field, flag) ((flag) ?\ (metrics_a->field) : (metrics_x->field)) struct smu_v13_0_6_dpm_map { @@ -732,7 +738,7 @@ static int smu_v13_0_6_setup_driver_pptable(struct smu_context *smu) MetricsTableA_t *metrics_a = (MetricsTableA_t *)smu_table->metrics_table; struct PPTable_t *pptable = (struct PPTable_t *)smu_table->driver_pptable; - struct amdgpu_device *adev = smu->adev; + bool flag = smu_v13_0_6_is_unified_metrics(smu); int ret, i, retry = 100; uint32_t table_version; @@ -744,7 +750,7 @@ static int smu_v13_0_6_setup_driver_pptable(struct smu_context *smu) return ret; /* Ensure that metrics have been updated */ - if (GET_METRIC_FIELD(AccumulationCounter)) + if (GET_METRIC_FIELD(AccumulationCounter, flag)) break; usleep_range(1000, 1100); @@ -761,29 +767,29 @@ static int smu_v13_0_6_setup_driver_pptable(struct smu_context *smu) table_version; pptable->MaxSocketPowerLimit = - SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketPowerLimit)); + SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketPowerLimit, flag)); pptable->MaxGfxclkFrequency = - SMUQ10_ROUND(GET_METRIC_FIELD(MaxGfxclkFrequency)); + SMUQ10_ROUND(GET_METRIC_FIELD(MaxGfxclkFrequency, flag)); pptable->MinGfxclkFrequency = - SMUQ10_ROUND(GET_METRIC_FIELD(MinGfxclkFrequency)); + SMUQ10_ROUND(GET_METRIC_FIELD(MinGfxclkFrequency, flag)); for (i = 0; i < 4; ++i) { pptable->FclkFrequencyTable[i] = - SMUQ10_ROUND(GET_METRIC_FIELD(FclkFrequencyTable)[i]); + SMUQ10_ROUND(GET_METRIC_FIELD(FclkFrequencyTable, flag)[i]); pptable->UclkFrequencyTable[i] = - SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequencyTable)[i]); + SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequencyTable, flag)[i]); pptable->SocclkFrequencyTable[i] = SMUQ10_ROUND( - GET_METRIC_FIELD(SocclkFrequencyTable)[i]); + GET_METRIC_FIELD(SocclkFrequencyTable, flag)[i]); pptable->VclkFrequencyTable[i] = - SMUQ10_ROUND(GET_METRIC_FIELD(VclkFrequencyTable)[i]); + SMUQ10_ROUND(GET_METRIC_FIELD(VclkFrequencyTable, flag)[i]); pptable->DclkFrequencyTable[i] = - SMUQ10_ROUND(GET_METRIC_FIELD(DclkFrequencyTable)[i]); + SMUQ10_ROUND(GET_METRIC_FIELD(DclkFrequencyTable, flag)[i]); pptable->LclkFrequencyTable[i] = - SMUQ10_ROUND(GET_METRIC_FIELD(LclkFrequencyTable)[i]); + SMUQ10_ROUND(GET_METRIC_FIELD(LclkFrequencyTable, flag)[i]); } /* use AID0 serial number by default */ - pptable->PublicSerialNumber_AID = GET_METRIC_FIELD(PublicSerialNumber_AID)[0]; + pptable->PublicSerialNumber_AID = GET_METRIC_FIELD(PublicSerialNumber_AID, flag)[0]; pptable->Init = true; } @@ -1115,6 +1121,7 @@ static int smu_v13_0_6_get_smu_metrics_data(struct smu_context *smu, struct smu_table_context *smu_table = &smu->smu_table; MetricsTableX_t *metrics_x = (MetricsTableX_t *)smu_table->metrics_table; MetricsTableA_t *metrics_a = (MetricsTableA_t *)smu_table->metrics_table; + bool flag = smu_v13_0_6_is_unified_metrics(smu); struct amdgpu_device *adev = smu->adev; int ret = 0; int xcc_id; @@ -1129,50 +1136,50 @@ static int smu_v13_0_6_get_smu_metrics_data(struct smu_context *smu, case METRICS_AVERAGE_GFXCLK: if (smu->smc_fw_version >= 0x552F00) { xcc_id = GET_INST(GC, 0); - *value = SMUQ10_ROUND(GET_METRIC_FIELD(GfxclkFrequency)[xcc_id]); + *value = SMUQ10_ROUND(GET_METRIC_FIELD(GfxclkFrequency, flag)[xcc_id]); } else { *value = 0; } break; case METRICS_CURR_SOCCLK: case METRICS_AVERAGE_SOCCLK: - *value = SMUQ10_ROUND(GET_METRIC_FIELD(SocclkFrequency)[0]); + *value = SMUQ10_ROUND(GET_METRIC_FIELD(SocclkFrequency, flag)[0]); break; case METRICS_CURR_UCLK: case METRICS_AVERAGE_UCLK: - *value = SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequency)); + *value = SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequency, flag)); break; case METRICS_CURR_VCLK: - *value = SMUQ10_ROUND(GET_METRIC_FIELD(VclkFrequency)[0]); + *value = SMUQ10_ROUND(GET_METRIC_FIELD(VclkFrequency, flag)[0]); break; case METRICS_CURR_DCLK: - *value = SMUQ10_ROUND(GET_METRIC_FIELD(DclkFrequency)[0]); + *value = SMUQ10_ROUND(GET_METRIC_FIELD(DclkFrequency, flag)[0]); break; case METRICS_CURR_FCLK: - *value = SMUQ10_ROUND(GET_METRIC_FIELD(FclkFrequency)); + *value = SMUQ10_ROUND(GET_METRIC_FIELD(FclkFrequency, flag)); break; case METRICS_AVERAGE_GFXACTIVITY: - *value = SMUQ10_ROUND(GET_METRIC_FIELD(SocketGfxBusy)); + *value = SMUQ10_ROUND(GET_METRIC_FIELD(SocketGfxBusy, flag)); break; case METRICS_AVERAGE_MEMACTIVITY: - *value = SMUQ10_ROUND(GET_METRIC_FIELD(DramBandwidthUtilization)); + *value = SMUQ10_ROUND(GET_METRIC_FIELD(DramBandwidthUtilization, flag)); break; case METRICS_CURR_SOCKETPOWER: - *value = SMUQ10_ROUND(GET_METRIC_FIELD(SocketPower)) << 8; + *value = SMUQ10_ROUND(GET_METRIC_FIELD(SocketPower, flag)) << 8; break; case METRICS_TEMPERATURE_HOTSPOT: - *value = SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketTemperature)) * + *value = SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketTemperature, flag)) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; break; case METRICS_TEMPERATURE_MEM: - *value = SMUQ10_ROUND(GET_METRIC_FIELD(MaxHbmTemperature)) * + *value = SMUQ10_ROUND(GET_METRIC_FIELD(MaxHbmTemperature, flag)) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; break; /* This is the max of all VRs and not just SOC VR. * No need to define another data type for the same. */ case METRICS_TEMPERATURE_VRSOC: - *value = SMUQ10_ROUND(GET_METRIC_FIELD(MaxVrTemperature)) * + *value = SMUQ10_ROUND(GET_METRIC_FIELD(MaxVrTemperature, flag)) * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES; break; default: @@ -2460,6 +2467,7 @@ static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table struct smu_table_context *smu_table = &smu->smu_table; struct gpu_metrics_v1_5 *gpu_metrics = (struct gpu_metrics_v1_5 *)smu_table->gpu_metrics_table; + bool flag = smu_v13_0_6_is_unified_metrics(smu); struct amdgpu_device *adev = smu->adev; int ret = 0, xcc_id, inst, i, j; MetricsTableX_t *metrics_x; @@ -2478,50 +2486,50 @@ static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 5); gpu_metrics->temperature_hotspot = - SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketTemperature)); + SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketTemperature, flag)); /* Individual HBM stack temperature is not reported */ gpu_metrics->temperature_mem = - SMUQ10_ROUND(GET_METRIC_FIELD(MaxHbmTemperature)); + SMUQ10_ROUND(GET_METRIC_FIELD(MaxHbmTemperature, flag)); /* Reports max temperature of all voltage rails */ gpu_metrics->temperature_vrsoc = - SMUQ10_ROUND(GET_METRIC_FIELD(MaxVrTemperature)); + SMUQ10_ROUND(GET_METRIC_FIELD(MaxVrTemperature, flag)); gpu_metrics->average_gfx_activity = - SMUQ10_ROUND(GET_METRIC_FIELD(SocketGfxBusy)); + SMUQ10_ROUND(GET_METRIC_FIELD(SocketGfxBusy, flag)); gpu_metrics->average_umc_activity = - SMUQ10_ROUND(GET_METRIC_FIELD(DramBandwidthUtilization)); + SMUQ10_ROUND(GET_METRIC_FIELD(DramBandwidthUtilization, flag)); gpu_metrics->curr_socket_power = - SMUQ10_ROUND(GET_METRIC_FIELD(SocketPower)); + SMUQ10_ROUND(GET_METRIC_FIELD(SocketPower, flag)); /* Energy counter reported in 15.259uJ (2^-16) units */ - gpu_metrics->energy_accumulator = GET_METRIC_FIELD(SocketEnergyAcc); + gpu_metrics->energy_accumulator = GET_METRIC_FIELD(SocketEnergyAcc, flag); for (i = 0; i < MAX_GFX_CLKS; i++) { xcc_id = GET_INST(GC, i); if (xcc_id >= 0) gpu_metrics->current_gfxclk[i] = - SMUQ10_ROUND(GET_METRIC_FIELD(GfxclkFrequency)[xcc_id]); + SMUQ10_ROUND(GET_METRIC_FIELD(GfxclkFrequency, flag)[xcc_id]); if (i < MAX_CLKS) { gpu_metrics->current_socclk[i] = - SMUQ10_ROUND(GET_METRIC_FIELD(SocclkFrequency)[i]); + SMUQ10_ROUND(GET_METRIC_FIELD(SocclkFrequency, flag)[i]); inst = GET_INST(VCN, i); if (inst >= 0) { gpu_metrics->current_vclk0[i] = - SMUQ10_ROUND(GET_METRIC_FIELD(VclkFrequency)[inst]); + SMUQ10_ROUND(GET_METRIC_FIELD(VclkFrequency, flag)[inst]); gpu_metrics->current_dclk0[i] = - SMUQ10_ROUND(GET_METRIC_FIELD(DclkFrequency)[inst]); + SMUQ10_ROUND(GET_METRIC_FIELD(DclkFrequency, flag)[inst]); } } } - gpu_metrics->current_uclk = SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequency)); + gpu_metrics->current_uclk = SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequency, flag)); /* Throttle status is not reported through metrics now */ gpu_metrics->throttle_status = 0; /* Clock Lock Status. Each bit corresponds to each GFXCLK instance */ - gpu_metrics->gfxclk_lock_status = GET_METRIC_FIELD(GfxLockXCDMak) >> GET_INST(GC, 0); + gpu_metrics->gfxclk_lock_status = GET_METRIC_FIELD(GfxLockXCDMak, flag) >> GET_INST(GC, 0); if (!(adev->flags & AMD_IS_APU)) { /*Check smu version, PCIE link speed and width will be reported from pmfw metric @@ -2562,22 +2570,22 @@ static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table gpu_metrics->system_clock_counter = ktime_get_boottime_ns(); gpu_metrics->gfx_activity_acc = - SMUQ10_ROUND(GET_METRIC_FIELD(SocketGfxBusyAcc)); + SMUQ10_ROUND(GET_METRIC_FIELD(SocketGfxBusyAcc, flag)); gpu_metrics->mem_activity_acc = - SMUQ10_ROUND(GET_METRIC_FIELD(DramBandwidthUtilizationAcc)); + SMUQ10_ROUND(GET_METRIC_FIELD(DramBandwidthUtilizationAcc, flag)); for (i = 0; i < NUM_XGMI_LINKS; i++) { gpu_metrics->xgmi_read_data_acc[i] = - SMUQ10_ROUND(GET_METRIC_FIELD(XgmiReadDataSizeAcc)[i]); + SMUQ10_ROUND(GET_METRIC_FIELD(XgmiReadDataSizeAcc, flag)[i]); gpu_metrics->xgmi_write_data_acc[i] = - SMUQ10_ROUND(GET_METRIC_FIELD(XgmiWriteDataSizeAcc)[i]); + SMUQ10_ROUND(GET_METRIC_FIELD(XgmiWriteDataSizeAcc, flag)[i]); } for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { inst = GET_INST(JPEG, i); for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { gpu_metrics->jpeg_activity[(i * adev->jpeg.num_jpeg_rings) + j] = - SMUQ10_ROUND(GET_METRIC_FIELD(JpegBusy) + SMUQ10_ROUND(GET_METRIC_FIELD(JpegBusy, flag) [(inst * adev->jpeg.num_jpeg_rings) + j]); } } @@ -2585,13 +2593,13 @@ static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { inst = GET_INST(VCN, i); gpu_metrics->vcn_activity[i] = - SMUQ10_ROUND(GET_METRIC_FIELD(VcnBusy)[inst]); + SMUQ10_ROUND(GET_METRIC_FIELD(VcnBusy, flag)[inst]); } - gpu_metrics->xgmi_link_width = SMUQ10_ROUND(GET_METRIC_FIELD(XgmiWidth)); - gpu_metrics->xgmi_link_speed = SMUQ10_ROUND(GET_METRIC_FIELD(XgmiBitrate)); + gpu_metrics->xgmi_link_width = SMUQ10_ROUND(GET_METRIC_FIELD(XgmiWidth, flag)); + gpu_metrics->xgmi_link_speed = SMUQ10_ROUND(GET_METRIC_FIELD(XgmiBitrate, flag)); - gpu_metrics->firmware_timestamp = GET_METRIC_FIELD(Timestamp); + gpu_metrics->firmware_timestamp = GET_METRIC_FIELD(Timestamp, flag); *table = (void *)gpu_metrics; kfree(metrics_x); From e4ecf5c0a9f97a5387b00d30bd41e7a91f82c57f Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Sun, 14 Jul 2024 04:04:51 +0800 Subject: [PATCH 1757/1868] drm/amd/pm: Add gpu_metrics_v1_6 Add new gpu_metrics_v1_6 with activities per partition Signed-off-by: Asad Kamal Reviewed-by: Lijo Lazar --- .../gpu/drm/amd/include/kgd_pp_interface.h | 103 +++++++++++++++++- drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c | 3 + 2 files changed, 105 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/include/kgd_pp_interface.h b/drivers/gpu/drm/amd/include/kgd_pp_interface.h index 79020d17ac784..0cec1c4d4e266 100644 --- a/drivers/gpu/drm/amd/include/kgd_pp_interface.h +++ b/drivers/gpu/drm/amd/include/kgd_pp_interface.h @@ -345,7 +345,8 @@ enum pp_pm_phase_det_param_id { #define MAX_CLKS 4 #define NUM_VCN 4 #define NUM_JPEG_ENG 32 - +#define MAX_XCC 8 +#define NUM_XCP 8 struct seq_file; enum amd_pp_clock_type; struct amd_pp_simple_clock_info; @@ -359,6 +360,15 @@ struct pp_smu_wm_range_sets; struct pp_smu_nv_clock_table; struct dpm_clocks; +struct amdgpu_xcp_metrics { + /* Utilization Instantaneous (%) */ + u32 gfx_busy_inst[MAX_XCC]; + u16 jpeg_busy[NUM_JPEG_ENG]; + u16 vcn_busy[NUM_VCN]; + /* Utilization Accumulated (%) */ + u64 gfx_busy_acc[MAX_XCC]; +}; + struct amd_pm_funcs { /* export for dpm on ci and si */ int (*pre_set_power_state)(void *handle); @@ -881,6 +891,97 @@ struct gpu_metrics_v1_5 { uint16_t padding; }; +struct gpu_metrics_v1_6 { + struct metrics_table_header common_header; + + /* Temperature (Celsius) */ + uint16_t temperature_hotspot; + uint16_t temperature_mem; + uint16_t temperature_vrsoc; + + /* Power (Watts) */ + uint16_t curr_socket_power; + + /* Utilization (%) */ + uint16_t average_gfx_activity; + uint16_t average_umc_activity; // memory controller + + /* Energy (15.259uJ (2^-16) units) */ + uint64_t energy_accumulator; + + /* Driver attached timestamp (in ns) */ + uint64_t system_clock_counter; + + /* Accumulation cycle counter */ + uint32_t accumulation_counter; + + /* Accumulated throttler residencies */ + uint32_t prochot_residency_acc; + uint32_t ppt_residency_acc; + uint32_t socket_thm_residency_acc; + uint32_t vr_thm_residency_acc; + uint32_t hbm_thm_residency_acc; + + /* Clock Lock Status. Each bit corresponds to clock instance */ + uint32_t gfxclk_lock_status; + + /* Link width (number of lanes) and speed (in 0.1 GT/s) */ + uint16_t pcie_link_width; + uint16_t pcie_link_speed; + + /* XGMI bus width and bitrate (in Gbps) */ + uint16_t xgmi_link_width; + uint16_t xgmi_link_speed; + + /* Utilization Accumulated (%) */ + uint32_t gfx_activity_acc; + uint32_t mem_activity_acc; + + /*PCIE accumulated bandwidth (GB/sec) */ + uint64_t pcie_bandwidth_acc; + + /*PCIE instantaneous bandwidth (GB/sec) */ + uint64_t pcie_bandwidth_inst; + + /* PCIE L0 to recovery state transition accumulated count */ + uint64_t pcie_l0_to_recov_count_acc; + + /* PCIE replay accumulated count */ + uint64_t pcie_replay_count_acc; + + /* PCIE replay rollover accumulated count */ + uint64_t pcie_replay_rover_count_acc; + + /* PCIE NAK sent accumulated count */ + uint32_t pcie_nak_sent_count_acc; + + /* PCIE NAK received accumulated count */ + uint32_t pcie_nak_rcvd_count_acc; + + /* XGMI accumulated data transfer size(KiloBytes) */ + uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS]; + uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS]; + + /* PMFW attached timestamp (10ns resolution) */ + uint64_t firmware_timestamp; + + /* Current clocks (Mhz) */ + uint16_t current_gfxclk[MAX_GFX_CLKS]; + uint16_t current_socclk[MAX_CLKS]; + uint16_t current_vclk0[MAX_CLKS]; + uint16_t current_dclk0[MAX_CLKS]; + uint16_t current_uclk; + + /* Number of current partition */ + uint16_t num_partition; + + /* XCP metrics stats */ + struct amdgpu_xcp_metrics xcp_stats[NUM_XCP]; + + /* PCIE other end recovery counter */ + uint32_t pcie_lc_perf_other_end_recovery; +}; + /* * gpu_metrics_v2_0 is not recommended as it's not naturally aligned. * Use gpu_metrics_v2_1 or later instead. diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c index 88eefef05faed..63c4f75fa1183 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c @@ -1078,6 +1078,9 @@ void smu_cmn_init_soft_gpu_metrics(void *table, uint8_t frev, uint8_t crev) case METRICS_VERSION(1, 5): structure_size = sizeof(struct gpu_metrics_v1_5); break; + case METRICS_VERSION(1, 6): + structure_size = sizeof(struct gpu_metrics_v1_6); + break; case METRICS_VERSION(2, 0): structure_size = sizeof(struct gpu_metrics_v2_0); break; From a1e84e238fa416d598438095156a010311adbda1 Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Mon, 22 Jul 2024 19:45:11 +0800 Subject: [PATCH 1758/1868] drm/amdgpu: Fix get each xcp macro Fix get each xcp macro to loop over each partition correctly Fixes: 4bdca2057933 ("drm/amdgpu: Add utility functions for xcp") Signed-off-by: Asad Kamal Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h index 3aa3996c0250d..648237f27d1ca 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.h @@ -206,6 +206,6 @@ amdgpu_get_next_xcp(struct amdgpu_xcp_mgr *xcp_mgr, int *from) #define for_each_xcp(xcp_mgr, xcp, i) \ for (i = 0, xcp = amdgpu_get_next_xcp(xcp_mgr, &i); xcp; \ - xcp = amdgpu_get_next_xcp(xcp_mgr, &i)) + ++i, xcp = amdgpu_get_next_xcp(xcp_mgr, &i)) #endif From 1f89d98e0f357dbfdf21e08dce5bb460882bda39 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Wed, 11 Sep 2024 13:49:51 +0530 Subject: [PATCH 1759/1868] drm/amdgpu: Fix XCP instance mask calculation Fix instance mask calculation for VCN IP. There are cases where VCN instance could be shared across partitions. Fix here so that other blocks don't need to check for any shared instances based on partition mode. Signed-off-by: Lijo Lazar Reviewed-by: Asad Kamal --- drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c | 32 +++++++++------------- 1 file changed, 13 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c b/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c index f2fe6dafe62dd..fba9fadf9212c 100644 --- a/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c +++ b/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c @@ -94,8 +94,6 @@ static void aqua_vanjaram_set_xcp_id(struct amdgpu_device *adev, case AMDGPU_RING_TYPE_VCN_ENC: case AMDGPU_RING_TYPE_VCN_JPEG: ip_blk = AMDGPU_XCP_VCN; - if (aqua_vanjaram_xcp_vcn_shared(adev)) - inst_mask = 1 << (inst_idx * 2); break; default: DRM_ERROR("Not support ring type %d!", ring->funcs->type); @@ -105,6 +103,8 @@ static void aqua_vanjaram_set_xcp_id(struct amdgpu_device *adev, for (xcp_id = 0; xcp_id < adev->xcp_mgr->num_xcps; xcp_id++) { if (adev->xcp_mgr->xcp[xcp_id].ip[ip_blk].inst_mask & inst_mask) { ring->xcp_id = xcp_id; + dev_dbg(adev->dev, "ring:%s xcp_id :%u", ring->name, + ring->xcp_id); if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) adev->gfx.enforce_isolation[xcp_id].xcp_id = xcp_id; break; @@ -394,38 +394,31 @@ static int __aqua_vanjaram_get_xcp_ip_info(struct amdgpu_xcp_mgr *xcp_mgr, int x struct amdgpu_xcp_ip *ip) { struct amdgpu_device *adev = xcp_mgr->adev; + int num_sdma, num_vcn, num_shared_vcn, num_xcp; int num_xcc_xcp, num_sdma_xcp, num_vcn_xcp; - int num_sdma, num_vcn; num_sdma = adev->sdma.num_instances; num_vcn = adev->vcn.num_vcn_inst; + num_shared_vcn = 1; + + num_xcc_xcp = adev->gfx.num_xcc_per_xcp; + num_xcp = NUM_XCC(adev->gfx.xcc_mask) / num_xcc_xcp; switch (xcp_mgr->mode) { case AMDGPU_SPX_PARTITION_MODE: - num_sdma_xcp = num_sdma; - num_vcn_xcp = num_vcn; - break; case AMDGPU_DPX_PARTITION_MODE: - num_sdma_xcp = num_sdma / 2; - num_vcn_xcp = num_vcn / 2; - break; case AMDGPU_TPX_PARTITION_MODE: - num_sdma_xcp = num_sdma / 3; - num_vcn_xcp = num_vcn / 3; - break; case AMDGPU_QPX_PARTITION_MODE: - num_sdma_xcp = num_sdma / 4; - num_vcn_xcp = num_vcn / 4; - break; case AMDGPU_CPX_PARTITION_MODE: - num_sdma_xcp = 2; - num_vcn_xcp = num_vcn ? 1 : 0; + num_sdma_xcp = DIV_ROUND_UP(num_sdma, num_xcp); + num_vcn_xcp = DIV_ROUND_UP(num_vcn, num_xcp); break; default: return -EINVAL; } - num_xcc_xcp = adev->gfx.num_xcc_per_xcp; + if (num_vcn && num_xcp > num_vcn) + num_shared_vcn = num_xcp / num_vcn; switch (ip_id) { case AMDGPU_XCP_GFXHUB: @@ -441,7 +434,8 @@ static int __aqua_vanjaram_get_xcp_ip_info(struct amdgpu_xcp_mgr *xcp_mgr, int x ip->ip_funcs = &sdma_v4_4_2_xcp_funcs; break; case AMDGPU_XCP_VCN: - ip->inst_mask = XCP_INST_MASK(num_vcn_xcp, xcp_id); + ip->inst_mask = + XCP_INST_MASK(num_vcn_xcp, xcp_id / num_shared_vcn); /* TODO : Assign IP funcs */ break; default: From 88db87115f5059a180e1fa6bf3805e202e237fcc Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Mon, 22 Jul 2024 20:00:52 +0800 Subject: [PATCH 1760/1868] drm/amd/pm: Use metrics 1_6 Use metrics 1_6 to report activities per partition v2: Use separate per instance for different platforms, shared vcn handled by other fix Signed-off-by: Asad Kamal Reviewed-by: Lijo Lazar --- .../drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c | 78 ++++++++++++++----- 1 file changed, 60 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c index 52eff3dab8a80..a91a39bc44c3b 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c @@ -365,7 +365,7 @@ static int smu_v13_0_6_tables_init(struct smu_context *smu) return -ENOMEM; smu_table->metrics_time = 0; - smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_5); + smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_6); smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL); if (!smu_table->gpu_metrics_table) { @@ -2464,15 +2464,18 @@ static int smu_v13_0_6_get_current_pcie_link_speed(struct smu_context *smu) static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table) { + bool per_inst, smu_13_0_6_per_inst, smu_13_0_14_per_inst, apu_per_inst; struct smu_table_context *smu_table = &smu->smu_table; - struct gpu_metrics_v1_5 *gpu_metrics = - (struct gpu_metrics_v1_5 *)smu_table->gpu_metrics_table; + struct gpu_metrics_v1_6 *gpu_metrics = + (struct gpu_metrics_v1_6 *)smu_table->gpu_metrics_table; bool flag = smu_v13_0_6_is_unified_metrics(smu); + int ret = 0, xcc_id, inst, i, j, k, idx; struct amdgpu_device *adev = smu->adev; - int ret = 0, xcc_id, inst, i, j; MetricsTableX_t *metrics_x; MetricsTableA_t *metrics_a; + struct amdgpu_xcp *xcp; u16 link_width_level; + u32 inst_mask; metrics_x = kzalloc(max(sizeof(MetricsTableX_t), sizeof(MetricsTableA_t)), GFP_KERNEL); ret = smu_v13_0_6_get_metrics_table(smu, metrics_x, true); @@ -2483,7 +2486,7 @@ static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table metrics_a = (MetricsTableA_t *)metrics_x; - smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 5); + smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 6); gpu_metrics->temperature_hotspot = SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketTemperature, flag)); @@ -2525,8 +2528,15 @@ static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table gpu_metrics->current_uclk = SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequency, flag)); - /* Throttle status is not reported through metrics now */ - gpu_metrics->throttle_status = 0; + /* Total accumulated cycle counter */ + gpu_metrics->accumulation_counter = GET_METRIC_FIELD(AccumulationCounter, flag); + + /* Accumulated throttler residencies */ + gpu_metrics->prochot_residency_acc = GET_METRIC_FIELD(ProchotResidencyAcc, flag); + gpu_metrics->ppt_residency_acc = GET_METRIC_FIELD(PptResidencyAcc, flag); + gpu_metrics->socket_thm_residency_acc = GET_METRIC_FIELD(SocketThmResidencyAcc, flag); + gpu_metrics->vr_thm_residency_acc = GET_METRIC_FIELD(VrThmResidencyAcc, flag); + gpu_metrics->hbm_thm_residency_acc = GET_METRIC_FIELD(HbmThmResidencyAcc, flag); /* Clock Lock Status. Each bit corresponds to each GFXCLK instance */ gpu_metrics->gfxclk_lock_status = GET_METRIC_FIELD(GfxLockXCDMak, flag) >> GET_INST(GC, 0); @@ -2581,19 +2591,51 @@ static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table SMUQ10_ROUND(GET_METRIC_FIELD(XgmiWriteDataSizeAcc, flag)[i]); } - for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) { - inst = GET_INST(JPEG, i); - for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { - gpu_metrics->jpeg_activity[(i * adev->jpeg.num_jpeg_rings) + j] = - SMUQ10_ROUND(GET_METRIC_FIELD(JpegBusy, flag) - [(inst * adev->jpeg.num_jpeg_rings) + j]); + gpu_metrics->num_partition = adev->xcp_mgr->num_xcps; + + apu_per_inst = (adev->flags & AMD_IS_APU) && (smu->smc_fw_version >= 0x04556A00); + smu_13_0_6_per_inst = !(adev->flags & AMD_IS_APU) && + (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) + == IP_VERSION(13, 0, 6)) && + (smu->smc_fw_version >= 0x556F00); + smu_13_0_14_per_inst = !(adev->flags & AMD_IS_APU) && + (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) + == IP_VERSION(13, 0, 14)) && + (smu->smc_fw_version >= 0x05550B00); + + per_inst = apu_per_inst || smu_13_0_6_per_inst || smu_13_0_14_per_inst; + + for_each_xcp(adev->xcp_mgr, xcp, i) { + amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_VCN, &inst_mask); + idx = 0; + for_each_inst(k, inst_mask) { + /* Both JPEG and VCN has same instances */ + inst = GET_INST(VCN, k); + + for (j = 0; j < adev->jpeg.num_jpeg_rings; ++j) { + gpu_metrics->xcp_stats[i].jpeg_busy + [(idx * adev->jpeg.num_jpeg_rings) + j] = + SMUQ10_ROUND(GET_METRIC_FIELD(JpegBusy, flag) + [(inst * adev->jpeg.num_jpeg_rings) + j]); + } + gpu_metrics->xcp_stats[i].vcn_busy[idx] = + SMUQ10_ROUND(GET_METRIC_FIELD(VcnBusy, flag)[inst]); + idx++; + } - } - for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { - inst = GET_INST(VCN, i); - gpu_metrics->vcn_activity[i] = - SMUQ10_ROUND(GET_METRIC_FIELD(VcnBusy, flag)[inst]); + if (per_inst) { + amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_GFX, &inst_mask); + idx = 0; + for_each_inst(k, inst_mask) { + inst = GET_INST(GC, k); + gpu_metrics->xcp_stats[i].gfx_busy_inst[idx] = + SMUQ10_ROUND(metrics_x->GfxBusy[inst]); + gpu_metrics->xcp_stats[i].gfx_busy_acc[idx] = + SMUQ10_ROUND(metrics_x->GfxBusyAcc[inst]); + idx++; + } + } } gpu_metrics->xgmi_link_width = SMUQ10_ROUND(GET_METRIC_FIELD(XgmiWidth, flag)); From 45700f979b6240782fc3bf0aca80e7d8689803f0 Mon Sep 17 00:00:00 2001 From: Asad Kamal Date: Thu, 18 Jul 2024 18:09:17 +0800 Subject: [PATCH 1761/1868] drm/amd/pm: Update SMUv13.0.6 PMFW headers Update PMFW interface headers for updated metrics table with gfx activity per xcd Signed-off-by: Asad Kamal Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h index 0b3c2f54a3433..822c6425d90e0 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu_v13_0_6_pmfw.h @@ -123,7 +123,7 @@ typedef enum { VOLTAGE_GUARDBAND_COUNT } GFX_GUARDBAND_e; -#define SMU_METRICS_TABLE_VERSION 0xC +#define SMU_METRICS_TABLE_VERSION 0xD typedef struct __attribute__((packed, aligned(4))) { uint32_t AccumulationCounter; @@ -227,6 +227,10 @@ typedef struct __attribute__((packed, aligned(4))) { // PCIE LINK Speed and width uint32_t PCIeLinkSpeed; uint32_t PCIeLinkWidth; + + // PER XCD ACTIVITY + uint32_t GfxBusy[8]; + uint64_t GfxBusyAcc[8]; } MetricsTableX_t; typedef struct __attribute__((packed, aligned(4))) { From 5375b0f0b97c340954b60d3dcaffde30a99212e9 Mon Sep 17 00:00:00 2001 From: Victor Zhao Date: Thu, 17 Oct 2024 16:20:40 +0800 Subject: [PATCH 1762/1868] drm/amdkfd: fix the hang caused by the write reorder to fence_addr make sure KFD_FENCE_INIT write to fence_addr before pm_send_query_status called, to avoid qcm fence timeout caused by incorrect ordering. Signed-off-by: Victor Zhao Reviewed-by: Philip Yang --- drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 3 ++- drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index 53e0cd5c11860..f7a0f53026548 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -2075,7 +2075,7 @@ int amdkfd_fence_wait_timeout(struct device_queue_manager *dqm, { unsigned long end_jiffies = msecs_to_jiffies(timeout_ms) + jiffies; struct device *dev = dqm->dev->adev->dev; - uint64_t *fence_addr = dqm->fence_addr; + volatile uint64_t *fence_addr = dqm->fence_addr; while (*fence_addr != fence_value) { /* Fatal err detected, this response won't come */ @@ -2280,6 +2280,7 @@ static int unmap_queues_cpsch(struct device_queue_manager *dqm, goto out; *dqm->fence_addr = KFD_FENCE_INIT; + mb(); pm_send_query_status(&dqm->packet_mgr, dqm->fence_gpu_addr, KFD_FENCE_COMPLETED); /* should be timed out */ diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h index 75bdc066166c2..2aab6bc434f52 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h @@ -260,7 +260,7 @@ struct device_queue_manager { uint16_t vmid_pasid[VMID_NUM]; uint64_t pipelines_addr; uint64_t fence_gpu_addr; - uint64_t *fence_addr; + volatile uint64_t *fence_addr; struct kfd_mem_obj *fence_mem; bool active_runlist; int sched_policy; From 169e87728adad2f17a313c80692c5d49fd773d46 Mon Sep 17 00:00:00 2001 From: Asher Song Date: Wed, 23 Oct 2024 15:09:09 +0800 Subject: [PATCH 1763/1868] Revert "drm/amdkfd: fix the hang caused by the write reorder to fence_addr" This reverts commit 5375b0f0b97c340954b60d3dcaffde30a99212e9. --- drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 3 +-- drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h | 2 +- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index f7a0f53026548..53e0cd5c11860 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -2075,7 +2075,7 @@ int amdkfd_fence_wait_timeout(struct device_queue_manager *dqm, { unsigned long end_jiffies = msecs_to_jiffies(timeout_ms) + jiffies; struct device *dev = dqm->dev->adev->dev; - volatile uint64_t *fence_addr = dqm->fence_addr; + uint64_t *fence_addr = dqm->fence_addr; while (*fence_addr != fence_value) { /* Fatal err detected, this response won't come */ @@ -2280,7 +2280,6 @@ static int unmap_queues_cpsch(struct device_queue_manager *dqm, goto out; *dqm->fence_addr = KFD_FENCE_INIT; - mb(); pm_send_query_status(&dqm->packet_mgr, dqm->fence_gpu_addr, KFD_FENCE_COMPLETED); /* should be timed out */ diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h index 2aab6bc434f52..75bdc066166c2 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h @@ -260,7 +260,7 @@ struct device_queue_manager { uint16_t vmid_pasid[VMID_NUM]; uint64_t pipelines_addr; uint64_t fence_gpu_addr; - volatile uint64_t *fence_addr; + uint64_t *fence_addr; struct kfd_mem_obj *fence_mem; bool active_runlist; int sched_policy; From b2e6156d31286290e512a6b98d0038e05797c257 Mon Sep 17 00:00:00 2001 From: Victor Zhao Date: Thu, 17 Oct 2024 16:20:40 +0800 Subject: [PATCH 1764/1868] drm/amdkfd: fix the hang caused by the write reorder to fence_addr make sure KFD_FENCE_INIT write to fence_addr before pm_send_query_status called, to avoid qcm fence timeout caused by incorrect ordering. Signed-off-by: Victor Zhao Reviewed-by: Philip Yang --- drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c | 3 ++- drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c index 53e0cd5c11860..f7a0f53026548 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c @@ -2075,7 +2075,7 @@ int amdkfd_fence_wait_timeout(struct device_queue_manager *dqm, { unsigned long end_jiffies = msecs_to_jiffies(timeout_ms) + jiffies; struct device *dev = dqm->dev->adev->dev; - uint64_t *fence_addr = dqm->fence_addr; + volatile uint64_t *fence_addr = dqm->fence_addr; while (*fence_addr != fence_value) { /* Fatal err detected, this response won't come */ @@ -2280,6 +2280,7 @@ static int unmap_queues_cpsch(struct device_queue_manager *dqm, goto out; *dqm->fence_addr = KFD_FENCE_INIT; + mb(); pm_send_query_status(&dqm->packet_mgr, dqm->fence_gpu_addr, KFD_FENCE_COMPLETED); /* should be timed out */ diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h index 75bdc066166c2..2aab6bc434f52 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h @@ -260,7 +260,7 @@ struct device_queue_manager { uint16_t vmid_pasid[VMID_NUM]; uint64_t pipelines_addr; uint64_t fence_gpu_addr; - uint64_t *fence_addr; + volatile uint64_t *fence_addr; struct kfd_mem_obj *fence_mem; bool active_runlist; int sched_policy; From 8aa866a179c783870fe17c4a3abf5b92ff09f93f Mon Sep 17 00:00:00 2001 From: YiPeng Chai Date: Tue, 22 Oct 2024 13:42:38 +0800 Subject: [PATCH 1765/1868] drm/amdgpu: Reduce redundant gpu resets on nbio v7.4 On nbio v7.4, ras controller interrupt and athub interrupt are generated after injecting UE to PCIE, but gpu reset only needs to be triggered once. Signed-off-by: YiPeng Chai Reviewed-by: Tao Zhou --- drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c index 9446bf6f82c1e..97782a73f4b02 100644 --- a/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c +++ b/drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c @@ -414,8 +414,7 @@ static void nbio_v7_4_handle_ras_controller_intr_no_bifring(struct amdgpu_device /* ras_controller_int is dedicated for nbif ras error, * not the global interrupt for sync flood */ - amdgpu_ras_set_fed(adev, true); - amdgpu_ras_reset_gpu(adev); + amdgpu_ras_global_ras_isr(adev); } amdgpu_ras_error_data_fini(&err_data); From fa42a566a5e29a95e1145c525999b1acdbe8f0f5 Mon Sep 17 00:00:00 2001 From: Philip Yang Date: Fri, 4 Oct 2024 16:28:07 -0400 Subject: [PATCH 1766/1868] drm/amdkfd: Accounting pdd vram_usage for svm Process device data pdd->vram_usage is read by rocm-smi via sysfs, this is currently missing the svm_bo usage accounting, so "rocm-smi --showpids" per process VRAM usage report is incorrect. Add pdd->vram_usage accounting when svm_bo allocation and release, change to atomic64_t type because it is updated outside process mutex now. Signed-off-by: Philip Yang Reviewed-by: Felix Kuehling --- drivers/gpu/drm/amd/amdkfd/kfd_chardev.c | 8 ++++---- drivers/gpu/drm/amd/amdkfd/kfd_priv.h | 2 +- drivers/gpu/drm/amd/amdkfd/kfd_process.c | 4 ++-- drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 26 ++++++++++++++++++++++++ 4 files changed, 33 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c index a61d019485665..0f8bde24dc05c 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c @@ -1192,7 +1192,7 @@ static int kfd_ioctl_alloc_memory_of_gpu(struct file *filep, if (flags & KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM) size >>= 1; - WRITE_ONCE(pdd->vram_usage, pdd->vram_usage + PAGE_ALIGN(size)); + atomic64_add(PAGE_ALIGN(size), &pdd->vram_usage); } mutex_unlock(&p->mutex); @@ -1263,7 +1263,7 @@ static int kfd_ioctl_free_memory_of_gpu(struct file *filep, kfd_process_device_remove_obj_handle( pdd, GET_IDR_HANDLE(args->handle)); - WRITE_ONCE(pdd->vram_usage, pdd->vram_usage - size); + atomic64_sub(size, &pdd->vram_usage); err_unlock: err_pdd: @@ -2524,7 +2524,7 @@ static int criu_restore_memory_of_gpu_ipc(struct kfd_process_device *pdd, bo_bucket->restored_offset = offset; if ((bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) && !bo_priv->is_imported) /* Update the VRAM usage count */ - WRITE_ONCE(pdd->vram_usage, pdd->vram_usage + bo_bucket->size); + atomic64_add(bo_bucket->size, &pdd->vram_usage); return 0; } @@ -2602,7 +2602,7 @@ static int criu_restore_memory_of_gpu(struct kfd_process_device *pdd, } else if (bo_bucket->alloc_flags & KFD_IOC_ALLOC_MEM_FLAGS_VRAM) { bo_bucket->restored_offset = offset; /* Update the VRAM usage count */ - WRITE_ONCE(pdd->vram_usage, pdd->vram_usage + bo_bucket->size); + atomic64_add(bo_bucket->size, &pdd->vram_usage); } return 0; } diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h index 01781a43836a6..670e6442dc692 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h +++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h @@ -861,7 +861,7 @@ struct kfd_process_device { enum kfd_pdd_bound bound; /* VRAM usage */ - uint64_t vram_usage; + atomic64_t vram_usage; struct attribute attr_vram; char vram_filename[MAX_SYSFS_FILENAME_LEN]; diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_process.c b/drivers/gpu/drm/amd/amdkfd/kfd_process.c index af56e600d7a15..8ae011de71347 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_process.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_process.c @@ -336,7 +336,7 @@ static ssize_t kfd_procfs_show(struct kobject *kobj, struct attribute *attr, } else if (strncmp(attr->name, "vram_", 5) == 0) { struct kfd_process_device *pdd = container_of(attr, struct kfd_process_device, attr_vram); - return snprintf(buffer, PAGE_SIZE, "%llu\n", READ_ONCE(pdd->vram_usage)); + return snprintf(buffer, PAGE_SIZE, "%llu\n", atomic64_read(&pdd->vram_usage)); } else if (strncmp(attr->name, "sdma_", 5) == 0) { struct kfd_process_device *pdd = container_of(attr, struct kfd_process_device, attr_sdma); @@ -1671,7 +1671,7 @@ struct kfd_process_device *kfd_create_process_device_data(struct kfd_node *dev, pdd->bound = PDD_UNBOUND; pdd->already_dequeued = false; pdd->runtime_inuse = false; - pdd->vram_usage = 0; + atomic64_set(&pdd->vram_usage, 0); pdd->sdma_past_activity_counter = 0; pdd->user_gpu_id = dev->id; atomic64_set(&pdd->evict_duration_counter, 0); diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c index 53bf2c9f7a0d6..8eb37bd0ebcae 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c @@ -409,6 +409,27 @@ static void svm_range_bo_release(struct kref *kref) spin_lock(&svm_bo->list_lock); } spin_unlock(&svm_bo->list_lock); + + if (mmget_not_zero(svm_bo->eviction_fence->mm)) { + struct kfd_process_device *pdd; + struct kfd_process *p; + struct mm_struct *mm; + + mm = svm_bo->eviction_fence->mm; + /* + * The forked child process takes svm_bo device pages ref, svm_bo could be + * released after parent process is gone. + */ + p = kfd_lookup_process_by_mm(mm); + if (p) { + pdd = kfd_get_process_device_data(svm_bo->node, p); + if (pdd) + atomic64_sub(amdgpu_bo_size(svm_bo->bo), &pdd->vram_usage); + kfd_unref_process(p); + } + mmput(mm); + } + if (!dma_fence_is_signaled(&svm_bo->eviction_fence->base)) /* We're not in the eviction worker. Signal the fence. */ dma_fence_signal(&svm_bo->eviction_fence->base); @@ -536,6 +557,7 @@ int svm_range_vram_node_new(struct kfd_node *node, struct svm_range *prange, bool clear) { + struct kfd_process_device *pdd; struct amdgpu_bo_param bp; struct svm_range_bo *svm_bo; struct amdgpu_bo_user *ubo; @@ -627,6 +649,10 @@ svm_range_vram_node_new(struct kfd_node *node, struct svm_range *prange, list_add(&prange->svm_bo_list, &svm_bo->range_list); spin_unlock(&svm_bo->list_lock); + pdd = svm_range_get_pdd_by_node(prange, node); + if (pdd) + atomic64_add(amdgpu_bo_size(bo), &pdd->vram_usage); + return 0; reserve_bo_failed: From f038c8ab796cae7979b31f469fafb269041fc6ee Mon Sep 17 00:00:00 2001 From: Cruz Zhao Date: Thu, 31 Oct 2024 12:33:05 +0800 Subject: [PATCH 1767/1868] drm/amdkfd: fix the incorrect exception handling logic in function amd_acquire() In function amd_acquire(), kfd_get_process() is call to get process. When judge whether we get an exception pointer, we shouldn't judge whether it's a null pointer, because kfd_get_process will return ERR_PTR(-EINVAL) instead of null pointer if error. Because of this wrong logic, the kernel will panic then once kfd_get_process() returns ERR_PTR(-EINVAL). So, the correct logic should be: if (IS_ERR(p)) { Fixes: commit 779b4d05a1c9("drm/amdkfd: Add RDMA and PeerDirect support") Signed-off-by: Cruz Zhao Signed-off-by: Harish Kasiviswanathan (cherry picked from commit 1e3dca9dd0564fa46241bf3f839de82600495c7e) Change-Id: I42d7b77c8bb7c1b8923dbef748a36c8cf3e7fa24 --- drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c b/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c index 637a6ceaffefe..ed93247d83caa 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_peerdirect.c @@ -178,7 +178,7 @@ static int amd_acquire(unsigned long addr, size_t size, p = peer_mem_private_data; } else { p = kfd_get_process(current); - if (!p) { + if (IS_ERR(p)) { pr_debug("Not a KFD process\n"); return 0; } From 781df169b5b37704211af7038d5a2194d061743a Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Mon, 7 Oct 2024 13:49:45 +0530 Subject: [PATCH 1768/1868] drm/amdgpu: Wait for reset on init completion When reset on initialization is requested, wait for the reset to finish. In cases where module is loaded after boot, this makes sure all initialization work is done after a successful return of modprobe. Signed-off-by: Lijo Lazar Reviewed-by: Ramesh Errabolu --- drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c index 6532b7530a5cc..8e697273d2ac4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c @@ -1554,6 +1554,7 @@ static void amdgpu_xgmi_schedule_reset_on_init(struct amdgpu_hive_info *hive) int amdgpu_xgmi_reset_on_init(struct amdgpu_device *adev) { struct amdgpu_hive_info *hive; + bool reset_scheduled; int num_devs; hive = amdgpu_get_xgmi_hive(adev); @@ -1562,12 +1563,18 @@ int amdgpu_xgmi_reset_on_init(struct amdgpu_device *adev) mutex_lock(&hive->hive_lock); num_devs = atomic_read(&hive->number_devices); - if (num_devs == adev->gmc.xgmi.num_physical_nodes) + reset_scheduled = false; + if (num_devs == adev->gmc.xgmi.num_physical_nodes) { amdgpu_xgmi_schedule_reset_on_init(hive); + reset_scheduled = true; + } mutex_unlock(&hive->hive_lock); amdgpu_put_xgmi_hive(hive); + if (reset_scheduled) + flush_work(&hive->reset_on_init_work); + return 0; } From 8165df8ddf52d435b123d37dc59a9393b53aaaaa Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Fri, 13 Sep 2024 17:17:19 +0530 Subject: [PATCH 1769/1868] drm/amdgpu: Fetch NPS mode for GCv9.4.3 VFs Use the memory ranges published in discovery table to deduce NPS mode of GC v9.4.3 VFs. Signed-off-by: Lijo Lazar Reviewed-by: Vignesh.Chander@amd.com Tested-by: Vignesh.Chander@amd.com --- drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 12 +++++----- drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h | 2 +- drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 30 +++++++++++++++++++++++-- 3 files changed, 36 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c index 68b374a0cdf72..e3974cf40256b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c @@ -1265,14 +1265,14 @@ void amdgpu_gmc_sysfs_fini(struct amdgpu_device *adev) int amdgpu_gmc_get_nps_memranges(struct amdgpu_device *adev, struct amdgpu_mem_partition_info *mem_ranges, - int exp_ranges) + uint8_t *exp_ranges) { struct amdgpu_gmc_memrange *ranges; int range_cnt, ret, i, j; uint32_t nps_type; bool refresh; - if (!mem_ranges) + if (!mem_ranges || !exp_ranges) return -EINVAL; refresh = (adev->init_lvl->level != AMDGPU_INIT_LEVEL_MINIMAL_XGMI) && @@ -1286,16 +1286,16 @@ int amdgpu_gmc_get_nps_memranges(struct amdgpu_device *adev, /* TODO: For now, expect ranges and partition count to be the same. * Adjust if there are holes expected in any NPS domain. */ - if (range_cnt != exp_ranges) { + if (*exp_ranges && (range_cnt != *exp_ranges)) { dev_warn( adev->dev, "NPS config mismatch - expected ranges: %d discovery - nps mode: %d, nps ranges: %d", - exp_ranges, nps_type, range_cnt); + *exp_ranges, nps_type, range_cnt); ret = -EINVAL; goto err; } - for (i = 0; i < exp_ranges; ++i) { + for (i = 0; i < range_cnt; ++i) { if (ranges[i].base_address >= ranges[i].limit_address) { dev_warn( adev->dev, @@ -1336,6 +1336,8 @@ int amdgpu_gmc_get_nps_memranges(struct amdgpu_device *adev, ranges[i].limit_address - ranges[i].base_address + 1; } + if (!*exp_ranges) + *exp_ranges = range_cnt; err: kfree(ranges); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h index c66b6dbe9ac65..459a30fe239f7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h @@ -466,7 +466,7 @@ void amdgpu_gmc_sysfs_fini(struct amdgpu_device *adev); int amdgpu_gmc_get_nps_memranges(struct amdgpu_device *adev, struct amdgpu_mem_partition_info *mem_ranges, - int exp_ranges); + uint8_t *exp_ranges); int amdgpu_gmc_request_memory_partition(struct amdgpu_device *adev, int nps_mode); diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c index 8cf8520f1dc2b..d32bb02253d8b 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c @@ -1388,11 +1388,30 @@ gmc_v9_0_get_memory_partition(struct amdgpu_device *adev, u32 *supp_modes) return mode; } +static enum amdgpu_memory_partition +gmc_v9_0_query_vf_memory_partition(struct amdgpu_device *adev) +{ + switch (adev->gmc.num_mem_partitions) { + case 0: + return UNKNOWN_MEMORY_PARTITION_MODE; + case 1: + return AMDGPU_NPS1_PARTITION_MODE; + case 2: + return AMDGPU_NPS2_PARTITION_MODE; + case 4: + return AMDGPU_NPS4_PARTITION_MODE; + default: + return AMDGPU_NPS1_PARTITION_MODE; + } + + return AMDGPU_NPS1_PARTITION_MODE; +} + static enum amdgpu_memory_partition gmc_v9_0_query_memory_partition(struct amdgpu_device *adev) { if (amdgpu_sriov_vf(adev)) - return AMDGPU_NPS1_PARTITION_MODE; + return gmc_v9_0_query_vf_memory_partition(adev); return gmc_v9_0_get_memory_partition(adev, NULL); } @@ -1936,6 +1955,8 @@ gmc_v9_0_init_sw_mem_ranges(struct amdgpu_device *adev, switch (mode) { case UNKNOWN_MEMORY_PARTITION_MODE: + adev->gmc.num_mem_partitions = 0; + break; case AMDGPU_NPS1_PARTITION_MODE: adev->gmc.num_mem_partitions = 1; break; @@ -1955,7 +1976,7 @@ gmc_v9_0_init_sw_mem_ranges(struct amdgpu_device *adev, /* Use NPS range info, if populated */ r = amdgpu_gmc_get_nps_memranges(adev, mem_ranges, - adev->gmc.num_mem_partitions); + &adev->gmc.num_mem_partitions); if (!r) { l = 0; for (i = 1; i < adev->gmc.num_mem_partitions; ++i) { @@ -1965,6 +1986,11 @@ gmc_v9_0_init_sw_mem_ranges(struct amdgpu_device *adev, } } else { + if (!adev->gmc.num_mem_partitions) { + dev_err(adev->dev, + "Not able to detect NPS mode, fall back to NPS1"); + adev->gmc.num_mem_partitions = 1; + } /* Fallback to sw based calculation */ size = (adev->gmc.real_vram_size + SZ_16M) >> AMDGPU_GPU_PAGE_SHIFT; size /= adev->gmc.num_mem_partitions; From e562be898eb57191054047567aea3ef9152d333a Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Tue, 17 Sep 2024 11:46:44 +0530 Subject: [PATCH 1770/1868] drm/amdgpu: Show current compute partition on VF Enable sysfs node for current compute partition mode on VFs also. Signed-off-by: Lijo Lazar Reviewed-by: Vignesh.Chander@amd.com Tested-by: Vignesh.Chander@amd.com --- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 29 +++++++++++++++++++++++-- drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c | 12 ++++------ 2 files changed, 31 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c index ae692d0591bab..b6acbe923b6b0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c @@ -1604,21 +1604,46 @@ static DEVICE_ATTR(available_compute_partition, 0444, int amdgpu_gfx_sysfs_init(struct amdgpu_device *adev) { + struct amdgpu_xcp_mgr *xcp_mgr = adev->xcp_mgr; + bool xcp_switch_supported; int r; + if (!xcp_mgr) + return 0; + + xcp_switch_supported = + (xcp_mgr->funcs && xcp_mgr->funcs->switch_partition_mode); + + if (!xcp_switch_supported) + dev_attr_current_compute_partition.attr.mode &= + ~(S_IWUSR | S_IWGRP | S_IWOTH); + r = device_create_file(adev->dev, &dev_attr_current_compute_partition); if (r) return r; - r = device_create_file(adev->dev, &dev_attr_available_compute_partition); + if (xcp_switch_supported) + r = device_create_file(adev->dev, + &dev_attr_available_compute_partition); return r; } void amdgpu_gfx_sysfs_fini(struct amdgpu_device *adev) { + struct amdgpu_xcp_mgr *xcp_mgr = adev->xcp_mgr; + bool xcp_switch_supported; + + if (!xcp_mgr) + return; + + xcp_switch_supported = + (xcp_mgr->funcs && xcp_mgr->funcs->switch_partition_mode); device_remove_file(adev->dev, &dev_attr_current_compute_partition); - device_remove_file(adev->dev, &dev_attr_available_compute_partition); + + if (xcp_switch_supported) + device_remove_file(adev->dev, + &dev_attr_available_compute_partition); } int amdgpu_gfx_sysfs_isolation_shader_init(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c index 4968b6db62b46..4d5b48dbc0057 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c @@ -1165,12 +1165,9 @@ static int gfx_v9_4_3_sw_init(struct amdgpu_ip_block *ip_block) if (r) return r; - - if (!amdgpu_sriov_vf(adev)) { - r = amdgpu_gfx_sysfs_init(adev); - if (r) - return r; - } + r = amdgpu_gfx_sysfs_init(adev); + if (r) + return r; gfx_v9_4_3_alloc_ip_dump(adev); @@ -1201,8 +1198,7 @@ static int gfx_v9_4_3_sw_fini(struct amdgpu_ip_block *ip_block) gfx_v9_4_3_mec_fini(adev); amdgpu_bo_unref(&adev->gfx.rlc.clear_state_obj); gfx_v9_4_3_free_microcode(adev); - if (!amdgpu_sriov_vf(adev)) - amdgpu_gfx_sysfs_fini(adev); + amdgpu_gfx_sysfs_fini(adev); amdgpu_gfx_sysfs_isolation_shader_fini(adev); kfree(adev->gfx.ip_dump_core); From c84f83f9a97fbcb44824912bfeb40a79523ca986 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Tue, 15 Oct 2024 08:43:45 +0530 Subject: [PATCH 1771/1868] drm/amdgpu: Save VCN shared memory with init reset VCN shared memory is in framebuffer and there are some flags initialized during sw_init. Ideally, such programming should be during hw_init. Make sure the flags are saved during reset on initialization since that reset will affect frame buffer region. For clarity, separate it out to another function. Signed-off-by: Lijo Lazar Reported-by: Hao Zhou Reviewed-by: Leo Liu Fixes: 1b665567fd6d ("drm/amdgpu: Add reset on init handler for XGMI") --- drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c | 6 ++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 26 ++++++++++++++--------- drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 1 + 3 files changed, 23 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c index f34bbf586b288..647ffb69754eb 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reset.c @@ -49,6 +49,12 @@ static int amdgpu_reset_xgmi_reset_on_init_suspend(struct amdgpu_device *adev) adev->ip_blocks[i].status.hw = false; } + /* VCN FW shared region is in frambuffer, there are some flags + * initialized in that region during sw_init. Make sure the region is + * backed up. + */ + amdgpu_vcn_save_vcpu_bo(adev); + return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c index 43f44cc201cb8..aecb78e0519f6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c @@ -294,21 +294,12 @@ bool amdgpu_vcn_is_disabled_vcn(struct amdgpu_device *adev, enum vcn_ring_type t return ret; } -int amdgpu_vcn_suspend(struct amdgpu_device *adev) +int amdgpu_vcn_save_vcpu_bo(struct amdgpu_device *adev) { unsigned int size; void *ptr; int i, idx; - bool in_ras_intr = amdgpu_ras_intr_triggered(); - - cancel_delayed_work_sync(&adev->vcn.idle_work); - - /* err_event_athub will corrupt VCPU buffer, so we need to - * restore fw data and clear buffer in amdgpu_vcn_resume() */ - if (in_ras_intr) - return 0; - for (i = 0; i < adev->vcn.num_vcn_inst; ++i) { if (adev->vcn.harvest_config & (1 << i)) continue; @@ -327,9 +318,24 @@ int amdgpu_vcn_suspend(struct amdgpu_device *adev) drm_dev_exit(idx); } } + return 0; } +int amdgpu_vcn_suspend(struct amdgpu_device *adev) +{ + bool in_ras_intr = amdgpu_ras_intr_triggered(); + + cancel_delayed_work_sync(&adev->vcn.idle_work); + + /* err_event_athub will corrupt VCPU buffer, so we need to + * restore fw data and clear buffer in amdgpu_vcn_resume() */ + if (in_ras_intr) + return 0; + + return amdgpu_vcn_save_vcpu_bo(adev); +} + int amdgpu_vcn_resume(struct amdgpu_device *adev) { unsigned int size; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h index 2a1f3dbb14d3f..765b809d48a25 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h @@ -518,5 +518,6 @@ int amdgpu_vcn_ras_sw_init(struct amdgpu_device *adev); int amdgpu_vcn_psp_update_sram(struct amdgpu_device *adev, int inst_idx, enum AMDGPU_UCODE_ID ucode_id); +int amdgpu_vcn_save_vcpu_bo(struct amdgpu_device *adev); #endif From c718d39904bc5a580eccc2adb466567aaa338dac Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Tue, 15 Oct 2024 09:53:51 +0530 Subject: [PATCH 1772/1868] drm/amdgpu: Zero-initialize mqd backup memory Zero-initialize mqd backup memory, otherwise the check for 'already-backed-up' could go wrong. Signed-off-by: Lijo Lazar Reviewed-by: Yang Wang --- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c index b6acbe923b6b0..e96984c53e72c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c @@ -405,7 +405,7 @@ int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev, } /* prepare MQD backup */ - kiq->mqd_backup = kmalloc(mqd_size, GFP_KERNEL); + kiq->mqd_backup = kzalloc(mqd_size, GFP_KERNEL); if (!kiq->mqd_backup) { dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name); @@ -428,7 +428,7 @@ int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev, ring->mqd_size = mqd_size; /* prepare MQD backup */ - adev->gfx.me.mqd_backup[i] = kmalloc(mqd_size, GFP_KERNEL); + adev->gfx.me.mqd_backup[i] = kzalloc(mqd_size, GFP_KERNEL); if (!adev->gfx.me.mqd_backup[i]) { dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name); return -ENOMEM; @@ -452,7 +452,7 @@ int amdgpu_gfx_mqd_sw_init(struct amdgpu_device *adev, ring->mqd_size = mqd_size; /* prepare MQD backup */ - adev->gfx.mec.mqd_backup[j] = kmalloc(mqd_size, GFP_KERNEL); + adev->gfx.mec.mqd_backup[j] = kzalloc(mqd_size, GFP_KERNEL); if (!adev->gfx.mec.mqd_backup[j]) { dev_warn(adev->dev, "no memory to create MQD backup for ring %s\n", ring->name); return -ENOMEM; From c1f71dfae0e5ddbe6787ab41cfd04d3f647ee16f Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 7 Nov 2024 14:40:44 +0800 Subject: [PATCH 1773/1868] drm/amdkcl: use kprobe for address resolution of unexported functions Replaces the usage of kallsyms_lookup_name with kprobe to obtain the addresses of kernel functions that are not exported. Signed-off-by: Flora Cui Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdkcl/kcl_common.c | 41 ++++++++++++------------- drivers/gpu/drm/amd/amdkcl/main.c | 2 -- 2 files changed, 20 insertions(+), 23 deletions(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_common.c b/drivers/gpu/drm/amd/amdkcl/kcl_common.c index 5867b4d1a6c38..3d11e965887ea 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_common.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_common.c @@ -5,7 +5,26 @@ #include #include -unsigned long (*_kcl_kallsyms_lookup_name)(const char *name); +static unsigned long _kcl_kallsyms_lookup_name(const char *name) +{ + unsigned long addr = 0; +#ifndef HAVE_KALLSYMS_LOOKUP_NAME + struct kprobe kp; + int r; + + memset(&kp, 0, sizeof(kp)); + kp.symbol_name = name; + r = register_kprobe(&kp); + if (!r) { + addr = (unsigned long)kp.addr; + unregister_kprobe(&kp); + } +#else + addr = kallsyms_lookup_name(name); +#endif + + return addr; +} void *amdkcl_fp_setup(const char *symbol, void *dummy) { @@ -27,23 +46,3 @@ void *amdkcl_fp_setup(const char *symbol, void *dummy) return fp; } -void amdkcl_symbol_init(void) -{ -#ifndef HAVE_KALLSYMS_LOOKUP_NAME - struct kprobe kp; - int r; - - memset(&kp, 0, sizeof(kp)); - kp.symbol_name = "kallsyms_lookup_name"; - r = register_kprobe(&kp); - if (!r) { - _kcl_kallsyms_lookup_name = (void *)kp.addr; - unregister_kprobe(&kp); - } else { - pr_err("fail to get kallsyms_lookup_name, abort...\n"); - BUG(); - } -#else - _kcl_kallsyms_lookup_name = kallsyms_lookup_name; -#endif -} diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c index 7ede3a4fa2a6f..284aad3cb7078 100644 --- a/drivers/gpu/drm/amd/amdkcl/main.c +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -2,7 +2,6 @@ #include #include -extern void amdkcl_symbol_init(void); extern void amdkcl_dev_cgroup_init(void); extern void amdkcl_fence_init(void); extern void amdkcl_reservation_init(void); @@ -16,7 +15,6 @@ extern void amdkcl_prime_init(void); int __init amdkcl_init(void) { - amdkcl_symbol_init(); amdkcl_dev_cgroup_init(); amdkcl_fence_init(); amdkcl_reservation_init(); From 74253112fffacbfaf9eb94937f7724496193e61d Mon Sep 17 00:00:00 2001 From: Flora Cui Date: Thu, 7 Nov 2024 14:36:23 +0800 Subject: [PATCH 1774/1868] drm/amdkcl: move reservation_ww_class check to compile-time Signed-off-by: Flora Cui Reviewed-by: Bob Zhou --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_reservation.c | 40 -------------------- drivers/gpu/drm/amd/amdkcl/main.c | 2 - drivers/gpu/drm/amd/dkms/Makefile | 4 ++ drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 | 10 +++++ 5 files changed, 15 insertions(+), 43 deletions(-) delete mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_reservation.c diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index fd7c388cef2bf..a3fad367ae6aa 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -7,7 +7,7 @@ amdkcl-y += dma-buf/dma-resv.o kcl_dma-resv.o amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_kthread.o kcl_io.o kcl_seq_file.o \ kcl_suspend.o kcl_pci.o kcl_mm.o kcl_memory.o kcl_sched.o \ - kcl_fence.o kcl_reservation.o kcl_drm_cache.o \ + kcl_fence.o kcl_drm_cache.o \ kcl_drm_fb.o kcl_drm_print.o kcl_drm_edid.o\ kcl_drm_crtc.o kcl_drm_connector.o kcl_drm_atomic_helper.o \ kcl_device_cgroup.o kcl_mn.o kcl_drm_modes.o kcl_time.o \ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_reservation.c b/drivers/gpu/drm/amd/amdkcl/kcl_reservation.c deleted file mode 100644 index e1b018386c601..0000000000000 --- a/drivers/gpu/drm/amd/amdkcl/kcl_reservation.c +++ /dev/null @@ -1,40 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2012-2014 Canonical Ltd (Maarten Lankhorst) - * - * Based on bo.c which bears the following copyright notice, - * but is dual licensed: - * - * Copyright (c) 2006-2009 VMware, Inc., Palo Alto, CA., USA - * All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the - * "Software"), to deal in the Software without restriction, including - * without limitation the rights to use, copy, modify, merge, publish, - * distribute, sub license, and/or sell copies of the Software, and to - * permit persons to whom the Software is furnished to do so, subject to - * the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, - * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR - * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE - * USE OR OTHER DEALINGS IN THE SOFTWARE. - * - **************************************************************************/ -/* - * Authors: Thomas Hellstrom - */ -#include - -void amdkcl_reservation_init(void) -{ - amdkcl_fp_setup("reservation_ww_class", NULL); -} \ No newline at end of file diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c index 284aad3cb7078..8b80eceddcad5 100644 --- a/drivers/gpu/drm/amd/amdkcl/main.c +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -4,7 +4,6 @@ extern void amdkcl_dev_cgroup_init(void); extern void amdkcl_fence_init(void); -extern void amdkcl_reservation_init(void); extern void amdkcl_io_init(void); extern void amdkcl_mm_init(void); extern void amdkcl_suspend_init(void); @@ -17,7 +16,6 @@ int __init amdkcl_init(void) { amdkcl_dev_cgroup_init(); amdkcl_fence_init(); - amdkcl_reservation_init(); amdkcl_io_init(); amdkcl_mm_init(); amdkcl_suspend_init(); diff --git a/drivers/gpu/drm/amd/dkms/Makefile b/drivers/gpu/drm/amd/dkms/Makefile index 0e41d5633a6f9..6153df061bcd8 100644 --- a/drivers/gpu/drm/amd/dkms/Makefile +++ b/drivers/gpu/drm/amd/dkms/Makefile @@ -52,6 +52,10 @@ ifeq ($(call _is_kcl_macro_defined,HAVE_DMA_RESV_SEQ_BUG),y) $(error dma_resv->seq is missing. exit...) endif +ifeq ($(call _is_kcl_macro_defined,HAVE_RESERVATION_WW_CLASS_BUG),y) +$(error reservation_ww_class is missing. exit...) +endif + DRM_VER=$(shell sed -n 's/^RHEL_DRM_VERSION = \(.*\)/\1/p' $(srctree)/Makefile) DRM_PATCH=$(shell sed -n 's/^RHEL_DRM_PATCHLEVEL = \(.*\)/\1/p' $(srctree)/Makefile) ifeq ($(DRM_VER),) diff --git a/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 b/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 index baeb0ee766979..8f83620935f38 100644 --- a/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/dma-resv.m4 @@ -56,6 +56,16 @@ AC_DEFUN([AC_AMDGPU_DMA_RESV_FENCES], [ ]) ]) +AC_DEFUN([AC_AMDGPU_DMA_RESV_RESERVATION_WW_CLASS], [ + AC_KERNEL_DO_BACKGROUND([ + AC_KERNEL_CHECK_SYMBOL_EXPORT([reservation_ww_class],[drivers/dma-buf/dma-resv.c], + [],[ + AC_DEFINE(HAVE_RESERVATION_WW_CLASS_BUG, 1, [Reporting reservation_ww_class missing]) + ]) + ]) +]) + AC_DEFUN([AC_AMDGPU_DMA_RESV], [ AC_AMDGPU_DMA_RESV_FENCES + AC_AMDGPU_DMA_RESV_RESERVATION_WW_CLASS ]) From 2638cfbe275294b5ee71059cb075384ec961c3e5 Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Fri, 8 Nov 2024 14:43:26 +0800 Subject: [PATCH 1775/1868] drm/amdkcl: wrap code under macro AMDKCL_FENCE_DEFAULT_WAIT_TIMEOUT when AMDKCL_FENCE_DEFAULT_WAIT_TIMEOUT isn't defined, _kcl_fence_default_wait_cb isn't used. So avoid call the amdkcl_fp_setup. Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/kcl_fence.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_fence.c b/drivers/gpu/drm/amd/amdkcl/kcl_fence.c index 6b962278954e6..e79e331222d00 100644 --- a/drivers/gpu/drm/amd/amdkcl/kcl_fence.c +++ b/drivers/gpu/drm/amd/amdkcl/kcl_fence.c @@ -50,9 +50,9 @@ struct default_wait_cb { struct task_struct *task; }; +#ifdef AMDKCL_FENCE_DEFAULT_WAIT_TIMEOUT static void (*_kcl_fence_default_wait_cb)(struct dma_fence *fence, struct dma_fence_cb *cb); -#ifdef AMDKCL_FENCE_DEFAULT_WAIT_TIMEOUT signed long _kcl_fence_default_wait(struct dma_fence *fence, bool intr, signed long timeout) { @@ -238,7 +238,9 @@ EXPORT_SYMBOL(_kcl_fence_enable_signaling); */ void amdkcl_fence_init(void) { +#ifdef AMDKCL_FENCE_DEFAULT_WAIT_TIMEOUT _kcl_fence_default_wait_cb = amdkcl_fp_setup("dma_fence_default_wait_cb", NULL); +#endif } #if !defined(HAVE_DMA_FENCE_DESCRIBE) From 11be698da3e69e54c7d07a2c25abdb422a6d6c3a Mon Sep 17 00:00:00 2001 From: Bob Zhou Date: Sat, 9 Nov 2024 21:02:03 +0800 Subject: [PATCH 1776/1868] drm/amdkcl: clean macro HAVE_SCHED_SET_FIFO_LOW Signed-off-by: Bob Zhou Reviewed-by: Flora Cui --- drivers/gpu/drm/amd/amdkcl/Makefile | 2 +- drivers/gpu/drm/amd/amdkcl/kcl_sched.c | 30 ------------------- drivers/gpu/drm/amd/amdkcl/main.c | 2 -- drivers/gpu/drm/amd/dkms/config/config.h | 3 -- drivers/gpu/drm/amd/dkms/m4/kernel.m4 | 1 - .../gpu/drm/amd/dkms/m4/sched_set_fifo_low.m4 | 16 ---------- drivers/gpu/drm/scheduler/backport/backport.h | 1 - include/kcl/kcl_sched.h | 12 -------- 8 files changed, 1 insertion(+), 66 deletions(-) delete mode 100644 drivers/gpu/drm/amd/amdkcl/kcl_sched.c delete mode 100644 drivers/gpu/drm/amd/dkms/m4/sched_set_fifo_low.m4 delete mode 100644 include/kcl/kcl_sched.h diff --git a/drivers/gpu/drm/amd/amdkcl/Makefile b/drivers/gpu/drm/amd/amdkcl/Makefile index a3fad367ae6aa..5d1a6ec853128 100644 --- a/drivers/gpu/drm/amd/amdkcl/Makefile +++ b/drivers/gpu/drm/amd/amdkcl/Makefile @@ -6,7 +6,7 @@ amdkcl-y += dma-buf/dma-resv.o kcl_dma-resv.o amdkcl-y += kcl_backlight.o kcl_ioctl.o \ kcl_kthread.o kcl_io.o kcl_seq_file.o \ - kcl_suspend.o kcl_pci.o kcl_mm.o kcl_memory.o kcl_sched.o \ + kcl_suspend.o kcl_pci.o kcl_mm.o kcl_memory.o \ kcl_fence.o kcl_drm_cache.o \ kcl_drm_fb.o kcl_drm_print.o kcl_drm_edid.o\ kcl_drm_crtc.o kcl_drm_connector.o kcl_drm_atomic_helper.o \ diff --git a/drivers/gpu/drm/amd/amdkcl/kcl_sched.c b/drivers/gpu/drm/amd/amdkcl/kcl_sched.c deleted file mode 100644 index e57b29e7a7a73..0000000000000 --- a/drivers/gpu/drm/amd/amdkcl/kcl_sched.c +++ /dev/null @@ -1,30 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * kernel/sched/core.c - * - * Core kernel scheduler code and related syscalls - * - * Copyright (C) 1991-2002 Linus Torvalds - */ - -#include - -/* Copied from kernel/sched/core.c and modified for KCL */ -#ifndef HAVE_SCHED_SET_FIFO_LOW -int (*_kcl_sched_setscheduler_nocheck)(struct task_struct *p, int policy, - const struct sched_param *param); -void sched_set_fifo_low(struct task_struct *p) -{ - struct sched_param sp = { .sched_priority = 1 }; - WARN_ON_ONCE(_kcl_sched_setscheduler_nocheck(p, SCHED_FIFO, &sp) != 0); -} -EXPORT_SYMBOL_GPL(sched_set_fifo_low); -#endif - -void amdkcl_sched_init(void) -{ -#ifndef HAVE_SCHED_SET_FIFO_LOW - _kcl_sched_setscheduler_nocheck = amdkcl_fp_setup("sched_setscheduler_nocheck", - NULL); -#endif -} diff --git a/drivers/gpu/drm/amd/amdkcl/main.c b/drivers/gpu/drm/amd/amdkcl/main.c index 8b80eceddcad5..e02c5db0eb328 100644 --- a/drivers/gpu/drm/amd/amdkcl/main.c +++ b/drivers/gpu/drm/amd/amdkcl/main.c @@ -7,7 +7,6 @@ extern void amdkcl_fence_init(void); extern void amdkcl_io_init(void); extern void amdkcl_mm_init(void); extern void amdkcl_suspend_init(void); -extern void amdkcl_sched_init(void); extern void amdkcl_numa_init(void); extern void amdkcl_workqueue_init(void); extern void amdkcl_prime_init(void); @@ -19,7 +18,6 @@ int __init amdkcl_init(void) amdkcl_io_init(); amdkcl_mm_init(); amdkcl_suspend_init(); - amdkcl_sched_init(); amdkcl_numa_init(); amdkcl_workqueue_init(); amdkcl_prime_init(); diff --git a/drivers/gpu/drm/amd/dkms/config/config.h b/drivers/gpu/drm/amd/dkms/config/config.h index 1ce9545fdce37..57c340185ca23 100644 --- a/drivers/gpu/drm/amd/dkms/config/config.h +++ b/drivers/gpu/drm/amd/dkms/config/config.h @@ -938,9 +938,6 @@ /* remove_conflicting_pci_framebuffers() wants p,p args */ /* #undef HAVE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PP */ -/* sched_set_fifo_low() is available */ -#define HAVE_SCHED_SET_FIFO_LOW 1 - /* seq_hex_dump() is available */ #define HAVE_SEQ_HEX_DUMP 1 diff --git a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 index c2a10026eb98e..a391cda05a40f 100644 --- a/drivers/gpu/drm/amd/dkms/m4/kernel.m4 +++ b/drivers/gpu/drm/amd/dkms/m4/kernel.m4 @@ -42,7 +42,6 @@ AC_DEFUN([AC_CONFIG_KERNEL], [ AC_AMDGPU_MMU_NOTIFIER_SYNCHRONIZE AC_AMDGPU_MMU_NOTIFIER_CALL_SRCU AC_AMDGPU_MM_RELEASE_PAGES - AC_AMDGPU_SCHED_SET_FIFO_LOW AC_AMDGPU_DMA_RESV AC_AMDGPU_TTM_BUFFER_OBJECT AC_AMDGPU_DEVCGROUP_CHECK_PERMISSION diff --git a/drivers/gpu/drm/amd/dkms/m4/sched_set_fifo_low.m4 b/drivers/gpu/drm/amd/dkms/m4/sched_set_fifo_low.m4 deleted file mode 100644 index 6a7fdf55ded70..0000000000000 --- a/drivers/gpu/drm/amd/dkms/m4/sched_set_fifo_low.m4 +++ /dev/null @@ -1,16 +0,0 @@ -dnl # -dnl # v5.8-rc1-23-g7318d4cc14c8 -dnl # sched: Provide sched_set_fifo() -dnl # -AC_DEFUN([AC_AMDGPU_SCHED_SET_FIFO_LOW], [ - AC_KERNEL_DO_BACKGROUND([ - AC_KERNEL_TRY_COMPILE_SYMBOL([ - #include - ], [ - sched_set_fifo_low(NULL); - ], [sched_set_fifo_low], [kernel/sched/core.c], [ - AC_DEFINE(HAVE_SCHED_SET_FIFO_LOW, 1, - [sched_set_fifo_low() is available]) - ]) - ]) -]) diff --git a/drivers/gpu/drm/scheduler/backport/backport.h b/drivers/gpu/drm/scheduler/backport/backport.h index ead9183b08d56..8f980b3fc2384 100644 --- a/drivers/gpu/drm/scheduler/backport/backport.h +++ b/drivers/gpu/drm/scheduler/backport/backport.h @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include diff --git a/include/kcl/kcl_sched.h b/include/kcl/kcl_sched.h deleted file mode 100644 index 2ed8d6a01cd1f..0000000000000 --- a/include/kcl/kcl_sched.h +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef _KCL_KCL_SCHED_H -#define _KCL_KCL_SCHED_H - -#include -#include - -#ifndef HAVE_SCHED_SET_FIFO_LOW -void sched_set_fifo_low(struct task_struct *p); -#endif - -#endif From 4a6d6fdd3cb83073f5b07379d70b81d4b5ca49bf Mon Sep 17 00:00:00 2001 From: Kenneth Feng Date: Thu, 17 Oct 2024 16:32:22 +0800 Subject: [PATCH 1777/1868] drm/amd/pm: update deep sleep status on smu v14.0.2/3 disable deep sleep during the compute workload for the potential performance loss on smu v14.0.2/3 Signed-off-by: Kenneth Feng Reviewed-by: Lijo Lazar (cherry picked from commit 8d64db6f7e871ea13b054296d003a18bf95176a6) Change-Id: Ifa0f8e1b90117b993850f2bef4030fed68c8a351 --- drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c index 43820d7d2c54a..3fba96982c852 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c @@ -1796,7 +1796,7 @@ static int smu_v14_0_2_set_power_profile_mode(struct smu_context *smu, DpmActivityMonitorCoeffInt_t *activity_monitor = &(activity_monitor_external.DpmActivityMonitorCoeffInt); int workload_type, ret = 0; - + uint32_t current_profile_mode = smu->power_profile_mode; smu->power_profile_mode = input[size]; if (smu->power_profile_mode >= PP_SMC_POWER_PROFILE_COUNT) { @@ -1854,6 +1854,11 @@ static int smu_v14_0_2_set_power_profile_mode(struct smu_context *smu, } } + if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_COMPUTE) + smu_v14_0_deep_sleep_control(smu, false); + else if (current_profile_mode == PP_SMC_POWER_PROFILE_COMPUTE) + smu_v14_0_deep_sleep_control(smu, true); + /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */ workload_type = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_WORKLOAD, From 2e4bea86340c6148b786866a6290cc053df5a47c Mon Sep 17 00:00:00 2001 From: Frank Min Date: Thu, 10 Oct 2024 16:41:32 +0800 Subject: [PATCH 1778/1868] drm/amdgpu: fix random data corruption for sdma 7 There is random data corruption caused by const fill, this is caused by write compression mode not correctly configured. So correct compression mode for const fill. Signed-off-by: Frank Min Reviewed-by: Alex Deucher (cherry picked from commit e3905feb321cc1420e1d35c98f5b941ba9177980) Change-Id: I7343c3fb102fa3967cbbd62d681579b6453fdf96 --- drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c index 24f24974ac1d8..d2ce6b6a7ff64 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c @@ -51,6 +51,12 @@ MODULE_FIRMWARE("amdgpu/sdma_7_0_1.bin"); #define SDMA0_HYP_DEC_REG_END 0x589a #define SDMA1_HYP_DEC_REG_OFFSET 0x20 +/*define for compression field for sdma7*/ +#define SDMA_PKT_CONSTANT_FILL_HEADER_compress_offset 0 +#define SDMA_PKT_CONSTANT_FILL_HEADER_compress_mask 0x00000001 +#define SDMA_PKT_CONSTANT_FILL_HEADER_compress_shift 16 +#define SDMA_PKT_CONSTANT_FILL_HEADER_COMPRESS(x) (((x) & SDMA_PKT_CONSTANT_FILL_HEADER_compress_mask) << SDMA_PKT_CONSTANT_FILL_HEADER_compress_shift) + static const struct amdgpu_hwip_reg_entry sdma_reg_list_7_0[] = { SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS_REG), SOC15_REG_ENTRY_STR(GC, 0, regSDMA0_STATUS1_REG), @@ -1720,7 +1726,8 @@ static void sdma_v7_0_emit_fill_buffer(struct amdgpu_ib *ib, uint64_t dst_offset, uint32_t byte_count) { - ib->ptr[ib->length_dw++] = SDMA_PKT_COPY_LINEAR_HEADER_OP(SDMA_OP_CONST_FILL); + ib->ptr[ib->length_dw++] = SDMA_PKT_CONSTANT_FILL_HEADER_OP(SDMA_OP_CONST_FILL) | + SDMA_PKT_CONSTANT_FILL_HEADER_COMPRESS(1); ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset); ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset); ib->ptr[ib->length_dw++] = src_data; From 9d1e278c6d99b39783253a395be60a41769c7652 Mon Sep 17 00:00:00 2001 From: Kenneth Feng Date: Thu, 17 Oct 2024 10:13:41 +0800 Subject: [PATCH 1779/1868] drm/amd/pm: update overdrive function on smu v14.0.2/3 update overdrive function on smu v14.0.2/3 Signed-off-by: Kenneth Feng Acked-by: Yang Wang (cherry picked from commit 59004add8761bea943ecee43b1ab4363c202f434) Change-Id: Icd8efbaf04518f4557f07b437d44ca08c9f76f0a --- drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c index 3fba96982c852..cae0b1f39d7d9 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c @@ -1414,7 +1414,7 @@ static int smu_v14_0_2_print_clk_levels(struct smu_context *smu, PP_OD_FEATURE_GFXCLK_FMAX, NULL, &max_value); - size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n", + size += sysfs_emit_at(buf, size, "SCLK_OFFSET: %7dMhz %10uMhz\n", min_value, max_value); } From 518d4daa6a3b7d8fa3bb10610ff10363d77bbbbf Mon Sep 17 00:00:00 2001 From: Kenneth Feng Date: Wed, 16 Oct 2024 15:58:45 +0800 Subject: [PATCH 1780/1868] drm/amd/pm: update the driver-fw interface file for smu v14.0.2/3 update the driver-fw interface file for smu v14.0.2/3 Signed-off-by: Kenneth Feng Reviewed-by: Yang Wang (cherry picked from commit 5a57f58428a8fd92bc631d2708133c02c882c28d) Change-Id: I8d691b3df37ee10b7549c05dcc46745e5d815b09 --- .../swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h | 132 +++++++++++------- drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h | 2 +- .../drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c | 57 +++----- 3 files changed, 102 insertions(+), 89 deletions(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h index ee457a6f08130..c2fd0a4a13e5d 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/smu14_driver_if_v14_0.h @@ -25,7 +25,7 @@ #define SMU14_DRIVER_IF_V14_0_H //Increment this version if SkuTable_t or BoardTable_t change -#define PPTABLE_VERSION 0x18 +#define PPTABLE_VERSION 0x1B #define NUM_GFXCLK_DPM_LEVELS 16 #define NUM_SOCCLK_DPM_LEVELS 8 @@ -145,7 +145,7 @@ typedef enum { } FEATURE_BTC_e; // Debug Overrides Bitmask -#define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_VCN_FCLK 0x00000001 +#define DEBUG_OVERRIDE_NOT_USE 0x00000001 #define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_DCN_FCLK 0x00000002 #define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_MP0_FCLK 0x00000004 #define DEBUG_OVERRIDE_DISABLE_VOLT_LINK_VCN_DCFCLK 0x00000008 @@ -161,6 +161,7 @@ typedef enum { #define DEBUG_OVERRIDE_ENABLE_SOC_VF_BRINGUP_MODE 0x00002000 #define DEBUG_OVERRIDE_ENABLE_PER_WGP_RESIENCY 0x00004000 #define DEBUG_OVERRIDE_DISABLE_MEMORY_VOLTAGE_SCALING 0x00008000 +#define DEBUG_OVERRIDE_DFLL_BTC_FCW_LOG 0x00010000 // VR Mapping Bit Defines #define VR_MAPPING_VR_SELECT_MASK 0x01 @@ -391,6 +392,21 @@ typedef struct { EccInfo_t EccInfo[24]; } EccInfoTable_t; +#define EPCS_HIGH_POWER 600 +#define EPCS_NORMAL_POWER 450 +#define EPCS_LOW_POWER 300 +#define EPCS_SHORTED_POWER 150 +#define EPCS_NO_BOOTUP 0 + +typedef enum{ + EPCS_SHORTED_LIMIT, + EPCS_LOW_POWER_LIMIT, + EPCS_NORMAL_POWER_LIMIT, + EPCS_HIGH_POWER_LIMIT, + EPCS_NOT_CONFIGURED, + EPCS_STATUS_COUNT, +} EPCS_STATUS_e; + //D3HOT sequences typedef enum { BACO_SEQUENCE, @@ -662,7 +678,7 @@ typedef enum { } PP_GRTAVFS_FW_SEP_FUSE_e; #define PP_NUM_RTAVFS_PWL_ZONES 5 - +#define PP_NUM_PSM_DIDT_PWL_ZONES 3 // VBIOS or PPLIB configures telemetry slope and offset. Only slope expected to be set for SVI3 // Slope Q1.7, Offset Q1.2 @@ -746,10 +762,10 @@ typedef struct { uint16_t Padding; //Frequency changes - int16_t GfxclkFmin; // MHz - int16_t GfxclkFmax; // MHz - uint16_t UclkFmin; // MHz - uint16_t UclkFmax; // MHz + int16_t GfxclkFoffset; + uint16_t Padding1; + uint16_t UclkFmin; + uint16_t UclkFmax; uint16_t FclkFmin; uint16_t FclkFmax; @@ -770,19 +786,23 @@ typedef struct { uint8_t MaxOpTemp; uint8_t AdvancedOdModeEnabled; - uint8_t Padding1[3]; + uint8_t Padding2[3]; uint16_t GfxVoltageFullCtrlMode; uint16_t SocVoltageFullCtrlMode; uint16_t GfxclkFullCtrlMode; uint16_t UclkFullCtrlMode; uint16_t FclkFullCtrlMode; - uint16_t Padding2; + uint16_t Padding3; int16_t GfxEdc; int16_t GfxPccLimitControl; - uint32_t Spare[10]; + uint16_t GfxclkFmaxVmax; + uint8_t GfxclkFmaxVmaxTemperature; + uint8_t Padding4[1]; + + uint32_t Spare[9]; uint32_t MmHubPadding[8]; // SMU internal use. Adding here instead of external as a workaround } OverDriveTable_t; @@ -802,8 +822,8 @@ typedef struct { uint16_t VddSocVmax; //gfxclk - int16_t GfxclkFmin; // MHz - int16_t GfxclkFmax; // MHz + int16_t GfxclkFoffset; + uint16_t Padding; //uclk uint16_t UclkFmin; // MHz uint16_t UclkFmax; // MHz @@ -828,7 +848,7 @@ typedef struct { uint8_t FanZeroRpmEnable; //temperature uint8_t MaxOpTemp; - uint8_t Padding[2]; + uint8_t Padding1[2]; //Full Ctrl uint16_t GfxVoltageFullCtrlMode; @@ -839,7 +859,7 @@ typedef struct { //EDC int16_t GfxEdc; int16_t GfxPccLimitControl; - int16_t Padding1; + int16_t Padding2; uint32_t Spare[5]; } OverDriveLimits_t; @@ -987,8 +1007,9 @@ typedef struct { uint16_t BaseClockDc; uint16_t GameClockDc; uint16_t BoostClockDc; - - uint32_t Reserved[4]; + uint16_t MaxReportedClock; + uint16_t Padding; + uint32_t Reserved[3]; } DriverReportedClocks_t; typedef struct { @@ -1132,7 +1153,7 @@ typedef struct { uint32_t DcModeMaxFreq [PPCLK_COUNT ]; // In MHz uint16_t GfxclkAibFmax; - uint16_t GfxclkFreqCap; + uint16_t GfxDpmPadding; //GFX Idle Power Settings uint16_t GfxclkFgfxoffEntry; // Entry in RLC stage (PLL), in Mhz @@ -1172,8 +1193,7 @@ typedef struct { uint32_t DvoFmaxLowScaler; //Unitless float // GFX DCS - uint16_t DcsGfxOffVoltage; //Voltage in mV(Q2) applied to VDDGFX when entering DCS GFXOFF phase - uint16_t PaddingDcs; + uint32_t PaddingDcs; uint16_t DcsMinGfxOffTime; //Minimum amount of time PMFW shuts GFX OFF as part of GFX DCS phase uint16_t DcsMaxGfxOffTime; //Maximum amount of time PMFW can shut GFX OFF as part of GFX DCS phase at a stretch. @@ -1205,8 +1225,7 @@ typedef struct { uint16_t DalDcModeMaxUclkFreq; uint8_t PaddingsMem[2]; //FCLK Section - uint16_t FclkDpmDisallowPstateFreq; //Frequency which FW will target when indicated that display config cannot support P-state. Set to 0 use FW calculated value - uint16_t PaddingFclk; + uint32_t PaddingFclk; // Link DPM Settings uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; ///< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 3:PciE-gen4 4:PciE-gen5 @@ -1215,12 +1234,19 @@ typedef struct { // SECTION: VDD_GFX AVFS uint8_t OverrideGfxAvfsFuses; - uint8_t GfxAvfsPadding[3]; + uint8_t GfxAvfsPadding[1]; + uint16_t DroopGBStDev; uint32_t SocHwRtAvfsFuses[PP_GRTAVFS_HW_FUSE_COUNT]; //new added for Soc domain uint32_t GfxL2HwRtAvfsFuses[PP_GRTAVFS_HW_FUSE_COUNT]; //see fusedoc for encoding //uint32_t GfxSeHwRtAvfsFuses[PP_GRTAVFS_HW_FUSE_COUNT]; - uint32_t spare_HwRtAvfsFuses[PP_GRTAVFS_HW_FUSE_COUNT]; + + uint16_t PsmDidt_Vcross[PP_NUM_PSM_DIDT_PWL_ZONES-1]; + uint32_t PsmDidt_StaticDroop_A[PP_NUM_PSM_DIDT_PWL_ZONES]; + uint32_t PsmDidt_StaticDroop_B[PP_NUM_PSM_DIDT_PWL_ZONES]; + uint32_t PsmDidt_DynDroop_A[PP_NUM_PSM_DIDT_PWL_ZONES]; + uint32_t PsmDidt_DynDroop_B[PP_NUM_PSM_DIDT_PWL_ZONES]; + uint32_t spare_HwRtAvfsFuses[19]; uint32_t SocCommonRtAvfs[PP_GRTAVFS_FW_COMMON_FUSE_COUNT]; uint32_t GfxCommonRtAvfs[PP_GRTAVFS_FW_COMMON_FUSE_COUNT]; @@ -1246,11 +1272,7 @@ typedef struct { uint32_t dGbV_dT_vmin; uint32_t dGbV_dT_vmax; - //Unused: PMFW-9370 - uint32_t V2F_vmin_range_low; - uint32_t V2F_vmin_range_high; - uint32_t V2F_vmax_range_low; - uint32_t V2F_vmax_range_high; + uint32_t PaddingV2F[4]; AvfsDcBtcParams_t DcBtcGfxParams; QuadraticInt_t SSCurve_GFX; @@ -1327,18 +1349,18 @@ typedef struct { uint16_t PsmDidtReleaseTimer; uint32_t PsmDidtStallPattern; //Will be written to both pattern 1 and didt_static_level_prog // CAC EDC - uint32_t Leakage_C0; // in IEEE float - uint32_t Leakage_C1; // in IEEE float - uint32_t Leakage_C2; // in IEEE float - uint32_t Leakage_C3; // in IEEE float - uint32_t Leakage_C4; // in IEEE float - uint32_t Leakage_C5; // in IEEE float - uint32_t GFX_CLK_SCALAR; // in IEEE float - uint32_t GFX_CLK_INTERCEPT; // in IEEE float - uint32_t GFX_CAC_M; // in IEEE float - uint32_t GFX_CAC_B; // in IEEE float - uint32_t VDD_GFX_CurrentLimitGuardband; // in IEEE float - uint32_t DynToTotalCacScalar; // in IEEE + uint32_t CacEdcCacLeakageC0; + uint32_t CacEdcCacLeakageC1; + uint32_t CacEdcCacLeakageC2; + uint32_t CacEdcCacLeakageC3; + uint32_t CacEdcCacLeakageC4; + uint32_t CacEdcCacLeakageC5; + uint32_t CacEdcGfxClkScalar; + uint32_t CacEdcGfxClkIntercept; + uint32_t CacEdcCac_m; + uint32_t CacEdcCac_b; + uint32_t CacEdcCurrLimitGuardband; + uint32_t CacEdcDynToTotalCacRatio; // GFX EDC XVMIN uint32_t XVmin_Gfx_EdcThreshScalar; uint32_t XVmin_Gfx_EdcEnableFreq; @@ -1467,7 +1489,7 @@ typedef struct { uint8_t VddqOffEnabled; uint8_t PaddingUmcFlags[2]; - uint32_t PostVoltageSetBacoDelay; // in microseconds. Amount of time FW will wait after power good is established or PSI0 command is issued + uint32_t Paddign1; uint32_t BacoEntryDelay; // in milliseconds. Amount of time FW will wait to trigger BACO entry after receiving entry notification from OS uint8_t FuseWritePowerMuxPresent; @@ -1530,7 +1552,7 @@ typedef struct { int16_t FuzzyFan_ErrorSetDelta; int16_t FuzzyFan_ErrorRateSetDelta; int16_t FuzzyFan_PwmSetDelta; - uint16_t FuzzyFan_Reserved; + uint16_t FanPadding2; uint16_t FwCtfLimit[TEMP_COUNT]; @@ -1547,9 +1569,10 @@ typedef struct { uint16_t FanSpare[1]; uint8_t FanIntakeSensorSupport; uint8_t FanIntakePadding; - uint32_t FanAmbientPerfBoostThreshold; uint32_t FanSpare2[12]; + uint32_t ODFeatureCtrlMask; + uint16_t TemperatureLimit_Hynix; // In degrees Celsius. Memory temperature limit associated with Hynix uint16_t TemperatureLimit_Micron; // In degrees Celsius. Memory temperature limit associated with Micron uint16_t TemperatureFwCtfLimit_Hynix; @@ -1637,7 +1660,7 @@ typedef struct { uint16_t AverageDclk0Frequency ; uint16_t AverageVclk1Frequency ; uint16_t AverageDclk1Frequency ; - uint16_t PCIeBusy ; + uint16_t AveragePCIeBusy ; uint16_t dGPU_W_MAX ; uint16_t padding ; @@ -1665,12 +1688,12 @@ typedef struct { uint16_t AverageGfxActivity ; uint16_t AverageUclkActivity ; - uint16_t Vcn0ActivityPercentage ; + uint16_t AverageVcn0ActivityPercentage; uint16_t Vcn1ActivityPercentage ; uint32_t EnergyAccumulator; uint16_t AverageSocketPower; - uint16_t MovingAverageTotalBoardPower; + uint16_t AverageTotalBoardPower; uint16_t AvgTemperature[TEMP_COUNT]; uint16_t AvgTemperatureFanIntake; @@ -1684,7 +1707,8 @@ typedef struct { uint8_t ThrottlingPercentage[THROTTLER_COUNT]; - uint8_t padding1[3]; + uint8_t VmaxThrottlingPercentage; + uint8_t padding1[2]; //metrics for D3hot entry/exit and driver ARM msgs uint32_t D3HotEntryCountPerMode[D3HOT_SEQUENCE_COUNT]; @@ -1693,7 +1717,7 @@ typedef struct { uint16_t ApuSTAPMSmartShiftLimit; uint16_t ApuSTAPMLimit; - uint16_t MovingAvgApuSocketPower; + uint16_t AvgApuSocketPower; uint16_t AverageUclkActivity_MAX; @@ -1823,6 +1847,17 @@ typedef struct { #define TABLE_TRANSFER_FAILED 0xFF #define TABLE_TRANSFER_PENDING 0xAB +#define TABLE_PPT_FAILED 0x100 +#define TABLE_TDC_FAILED 0x200 +#define TABLE_TEMP_FAILED 0x400 +#define TABLE_FAN_TARGET_TEMP_FAILED 0x800 +#define TABLE_FAN_STOP_TEMP_FAILED 0x1000 +#define TABLE_FAN_START_TEMP_FAILED 0x2000 +#define TABLE_FAN_PWM_MIN_FAILED 0x4000 +#define TABLE_ACOUSTIC_TARGET_RPM_FAILED 0x8000 +#define TABLE_ACOUSTIC_LIMIT_RPM_FAILED 0x10000 +#define TABLE_MGPU_ACOUSTIC_TARGET_RPM_FAILED 0x20000 + // Table types #define TABLE_PPTABLE 0 #define TABLE_COMBO_PPTABLE 1 @@ -1849,5 +1884,6 @@ typedef struct { #define IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING 0x7 #define IH_INTERRUPT_CONTEXT_ID_FAN_ABNORMAL 0x8 #define IH_INTERRUPT_CONTEXT_ID_FAN_RECOVERY 0x9 +#define IH_INTERRUPT_CONTEXT_ID_DYNAMIC_TABLE 0xA #endif diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h index 46b456590a080..727d5b405435d 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h +++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v14_0.h @@ -28,7 +28,7 @@ #define SMU14_DRIVER_IF_VERSION_INV 0xFFFFFFFF #define SMU14_DRIVER_IF_VERSION_SMU_V14_0_0 0x7 #define SMU14_DRIVER_IF_VERSION_SMU_V14_0_1 0x6 -#define SMU14_DRIVER_IF_VERSION_SMU_V14_0_2 0x26 +#define SMU14_DRIVER_IF_VERSION_SMU_V14_0_2 0x2E #define FEATURE_MASK(feature) (1ULL << feature) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c index cae0b1f39d7d9..cbad0deb43f3a 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c @@ -1077,12 +1077,9 @@ static void smu_v14_0_2_get_od_setting_limits(struct smu_context *smu, switch (od_feature_bit) { case PP_OD_FEATURE_GFXCLK_FMIN: - od_min_setting = overdrive_lowerlimits->GfxclkFmin; - od_max_setting = overdrive_upperlimits->GfxclkFmin; - break; case PP_OD_FEATURE_GFXCLK_FMAX: - od_min_setting = overdrive_lowerlimits->GfxclkFmax; - od_max_setting = overdrive_upperlimits->GfxclkFmax; + od_min_setting = overdrive_lowerlimits->GfxclkFoffset; + od_max_setting = overdrive_upperlimits->GfxclkFoffset; break; case PP_OD_FEATURE_UCLK_FMIN: od_min_setting = overdrive_lowerlimits->UclkFmin; @@ -1269,10 +1266,16 @@ static int smu_v14_0_2_print_clk_levels(struct smu_context *smu, PP_OD_FEATURE_GFXCLK_BIT)) break; - size += sysfs_emit_at(buf, size, "OD_SCLK:\n"); - size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n", - od_table->OverDriveTable.GfxclkFmin, - od_table->OverDriveTable.GfxclkFmax); + PPTable_t *pptable = smu->smu_table.driver_pptable; + const OverDriveLimits_t * const overdrive_upperlimits = + &pptable->SkuTable.OverDriveLimitsBasicMax; + const OverDriveLimits_t * const overdrive_lowerlimits = + &pptable->SkuTable.OverDriveLimitsBasicMin; + + size += sysfs_emit_at(buf, size, "OD_SCLK_OFFSET:\n"); + size += sysfs_emit_at(buf, size, "0: %dMhz\n1: %uMhz\n", + overdrive_lowerlimits->GfxclkFoffset, + overdrive_upperlimits->GfxclkFoffset); break; case SMU_OD_MCLK: @@ -2159,7 +2162,7 @@ static ssize_t smu_v14_0_2_get_gpu_metrics(struct smu_context *smu, gpu_metrics->average_gfx_activity = metrics->AverageGfxActivity; gpu_metrics->average_umc_activity = metrics->AverageUclkActivity; - gpu_metrics->average_mm_activity = max(metrics->Vcn0ActivityPercentage, + gpu_metrics->average_mm_activity = max(metrics->AverageVcn0ActivityPercentage, metrics->Vcn1ActivityPercentage); gpu_metrics->average_socket_power = metrics->AverageSocketPower; @@ -2218,8 +2221,7 @@ static void smu_v14_0_2_dump_od_table(struct smu_context *smu, { struct amdgpu_device *adev = smu->adev; - dev_dbg(adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->OverDriveTable.GfxclkFmin, - od_table->OverDriveTable.GfxclkFmax); + dev_dbg(adev->dev, "OD: Gfxclk offset: (%d)\n", od_table->OverDriveTable.GfxclkFoffset); dev_dbg(adev->dev, "OD: Uclk: (%d, %d)\n", od_table->OverDriveTable.UclkFmin, od_table->OverDriveTable.UclkFmax); } @@ -2310,10 +2312,8 @@ static int smu_v14_0_2_set_default_od_settings(struct smu_context *smu) memcpy(user_od_table, boot_od_table, sizeof(OverDriveTableExternal_t)); - user_od_table->OverDriveTable.GfxclkFmin = - user_od_table_bak.OverDriveTable.GfxclkFmin; - user_od_table->OverDriveTable.GfxclkFmax = - user_od_table_bak.OverDriveTable.GfxclkFmax; + user_od_table->OverDriveTable.GfxclkFoffset = + user_od_table_bak.OverDriveTable.GfxclkFoffset; user_od_table->OverDriveTable.UclkFmin = user_od_table_bak.OverDriveTable.UclkFmin; user_od_table->OverDriveTable.UclkFmax = @@ -2442,22 +2442,6 @@ static int smu_v14_0_2_od_edit_dpm_table(struct smu_context *smu, } switch (input[i]) { - case 0: - smu_v14_0_2_get_od_setting_limits(smu, - PP_OD_FEATURE_GFXCLK_FMIN, - &minimum, - &maximum); - if (input[i + 1] < minimum || - input[i + 1] > maximum) { - dev_info(adev->dev, "GfxclkFmin (%ld) must be within [%u, %u]!\n", - input[i + 1], minimum, maximum); - return -EINVAL; - } - - od_table->OverDriveTable.GfxclkFmin = input[i + 1]; - od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_GFXCLK_BIT; - break; - case 1: smu_v14_0_2_get_od_setting_limits(smu, PP_OD_FEATURE_GFXCLK_FMAX, @@ -2470,7 +2454,7 @@ static int smu_v14_0_2_od_edit_dpm_table(struct smu_context *smu, return -EINVAL; } - od_table->OverDriveTable.GfxclkFmax = input[i + 1]; + od_table->OverDriveTable.GfxclkFoffset = input[i + 1]; od_table->OverDriveTable.FeatureCtrlMask |= 1U << PP_OD_FEATURE_GFXCLK_BIT; break; @@ -2481,13 +2465,6 @@ static int smu_v14_0_2_od_edit_dpm_table(struct smu_context *smu, } } - if (od_table->OverDriveTable.GfxclkFmin > od_table->OverDriveTable.GfxclkFmax) { - dev_err(adev->dev, - "Invalid setting: GfxclkFmin(%u) is bigger than GfxclkFmax(%u)\n", - (uint32_t)od_table->OverDriveTable.GfxclkFmin, - (uint32_t)od_table->OverDriveTable.GfxclkFmax); - return -EINVAL; - } break; case PP_OD_EDIT_MCLK_VDDC_TABLE: From 65544ccdb03d9e1de45904e437874e08f9c64071 Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Fri, 18 Oct 2024 07:26:19 +0530 Subject: [PATCH 1781/1868] drm/amdgpu/gfx9: Add cleaner shader for GFX9.4.2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This commit adds the cleaner shader microcode for GFX9.4.2 GPUs. The cleaner shader is a piece of GPU code that is used to clear or initialize certain GPU resources, such as Local Data Share (LDS), Vector General Purpose Registers (VGPRs), and Scalar General Purpose Registers (SGPRs). Clearing these resources is important for ensuring data isolation between different workloads running on the GPU. Without the cleaner shader, residual data from a previous workload could potentially be accessed by a subsequent workload, leading to data leaks and incorrect computation results. The cleaner shader microcode is represented as an array of 32-bit words (`gfx_9_4_2_cleaner_shader_hex`). This array is the binary representation of the cleaner shader code, which is written in a low-level GPU instruction set. Also, this patch updates the `gfx_v9_0_sw_init` function to initialize the cleaner shader if the MEC firmware version is 88 or higher. It sets the `cleaner_shader_ptr` and `cleaner_shader_size` to the appropriate values and attempts to initialize the cleaner shader. When the cleaner shader feature is enabled, the AMDGPU driver loads this array into a specific location in the GPU memory. The GPU then reads this memory location to fetch and execute the cleaner shader instructions. The cleaner shader is executed automatically by the GPU at the end of each workload, before the next workload starts. This ensures that all GPU resources are in a clean state before the start of each workload. This change ensures that the GPU memory is properly cleared between different processes, preventing data leakage and enhancing security. It also aligns with the serialization mechanism between KGD and KFD, ensuring that the GPU state is consistent across different workloads. Cc: Christian König Cc: Alex Deucher Signed-off-by: Srinivasan Shanmugam Suggested-by: Alex Deucher Reviewed-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 12 ++ .../drm/amd/amdgpu/gfx_v9_0_cleaner_shader.h | 44 ++++- .../amd/amdgpu/gfx_v9_4_2_cleaner_shader.asm | 153 ++++++++++++++++++ 3 files changed, 208 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2_cleaner_shader.asm diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c index c53cfa14c70f5..89fda6a05fcd8 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c @@ -2223,6 +2223,18 @@ static int gfx_v9_0_sw_init(struct amdgpu_ip_block *ip_block) } switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { + case IP_VERSION(9, 4, 2): + adev->gfx.cleaner_shader_ptr = gfx_9_4_2_cleaner_shader_hex; + adev->gfx.cleaner_shader_size = sizeof(gfx_9_4_2_cleaner_shader_hex); + if (adev->gfx.mec_fw_version >= 88) { + adev->gfx.enable_cleaner_shader = true; + r = amdgpu_gfx_cleaner_shader_sw_init(adev, adev->gfx.cleaner_shader_size); + if (r) { + adev->gfx.enable_cleaner_shader = false; + dev_err(adev->dev, "Failed to initialize cleaner shader\n"); + } + } + break; default: adev->gfx.enable_cleaner_shader = false; break; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0_cleaner_shader.h b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0_cleaner_shader.h index 36c0292b51106..0b6bd09b75299 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0_cleaner_shader.h +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0_cleaner_shader.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: MIT */ /* - * Copyright 2018 Advanced Micro Devices, Inc. + * Copyright 2024 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -24,3 +24,45 @@ static const u32 __maybe_unused gfx_9_0_cleaner_shader_hex[] = { /* Add the cleaner shader code here */ }; + +/* Define the cleaner shader gfx_9_4_2 */ +static const u32 gfx_9_4_2_cleaner_shader_hex[] = { + 0xbf068100, 0xbf84003b, + 0xbf8a0000, 0xb07c0000, + 0xbe8200ff, 0x00000078, + 0xbf110802, 0x7e000280, + 0x7e020280, 0x7e040280, + 0x7e060280, 0x7e080280, + 0x7e0a0280, 0x7e0c0280, + 0x7e0e0280, 0x80828802, + 0xbe803202, 0xbf84fff5, + 0xbf9c0000, 0xbe8200ff, + 0x80000000, 0x86020102, + 0xbf840011, 0xbefe00c1, + 0xbeff00c1, 0xd28c0001, + 0x0001007f, 0xd28d0001, + 0x0002027e, 0x10020288, + 0xbe8200bf, 0xbefc00c1, + 0xd89c2000, 0x00020201, + 0xd89c6040, 0x00040401, + 0x320202ff, 0x00000400, + 0x80828102, 0xbf84fff8, + 0xbefc00ff, 0x0000005c, + 0xbf800000, 0xbe802c80, + 0xbe812c80, 0xbe822c80, + 0xbe832c80, 0x80fc847c, + 0xbf84fffa, 0xbee60080, + 0xbee70080, 0xbeea0180, + 0xbeec0180, 0xbeee0180, + 0xbef00180, 0xbef20180, + 0xbef40180, 0xbef60180, + 0xbef80180, 0xbefa0180, + 0xbf810000, 0xbf8d0001, + 0xbefc00ff, 0x0000005c, + 0xbf800000, 0xbe802c80, + 0xbe812c80, 0xbe822c80, + 0xbe832c80, 0x80fc847c, + 0xbf84fffa, 0xbee60080, + 0xbee70080, 0xbeea01ff, + 0x000000ee, 0xbf810000, +}; diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2_cleaner_shader.asm b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2_cleaner_shader.asm new file mode 100644 index 0000000000000..35b8cf9070bd9 --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2_cleaner_shader.asm @@ -0,0 +1,153 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright 2024 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + +// This shader is to clean LDS, SGPRs and VGPRs. It is first 64 Dwords or 256 bytes of 192 Dwords cleaner shader. +//To turn this shader program on for complitaion change this to main and lower shader main to main_1 + +// MI200 : Clear SGPRs, VGPRs and LDS +// Uses two kernels launched separately: +// 1. Clean VGPRs, LDS, and lower SGPRs +// Launches one workgroup per CU, each workgroup with 4x wave64 per SIMD in the CU +// Waves are "wave64" and have 128 VGPRs each, which uses all 512 VGPRs per SIMD +// Waves in the workgroup share the 64KB of LDS +// Each wave clears SGPRs 0 - 95. Because there are 4 waves/SIMD, this is physical SGPRs 0-383 +// Each wave clears 128 VGPRs, so all 512 in the SIMD +// The first wave of the workgroup clears its 64KB of LDS +// The shader starts with "S_BARRIER" to ensure SPI has launched all waves of the workgroup +// before any wave in the workgroup could end. Without this, it is possible not all SGPRs get cleared. +// 2. Clean remaining SGPRs +// Launches a workgroup with 24 waves per workgroup, yielding 6 waves per SIMD in each CU +// Waves are allocating 96 SGPRs +// CP sets up SPI_RESOURCE_RESERVE_* registers to prevent these waves from allocating SGPRs 0-223. +// As such, these 6 waves per SIMD are allocated physical SGPRs 224-799 +// Barriers do not work for >16 waves per workgroup, so we cannot start with S_BARRIER +// Instead, the shader starts with an S_SETHALT 1. Once all waves are launched CP will send unhalt command +// The shader then clears all SGPRs allocated to it, cleaning out physical SGPRs 224-799 + +shader main + asic(MI200) + type(CS) + wave_size(64) +// Note: original source code from SQ team + +// (theorhetical fastest = ~512clks vgpr + 1536 lds + ~128 sgpr = 2176 clks) + + s_cmp_eq_u32 s0, 1 // Bit0 is set, sgpr0 is set then clear VGPRS and LDS as FW set COMPUTE_USER_DATA_3 + s_cbranch_scc0 label_0023 // Clean VGPRs and LDS if sgpr0 of wave is set, scc = (s3 == 1) + S_BARRIER + + s_movk_i32 m0, 0x0000 + s_mov_b32 s2, 0x00000078 // Loop 128/8=16 times (loop unrolled for performance) + // + // CLEAR VGPRs + // + s_set_gpr_idx_on s2, 0x8 // enable Dest VGPR indexing +label_0005: + v_mov_b32 v0, 0 + v_mov_b32 v1, 0 + v_mov_b32 v2, 0 + v_mov_b32 v3, 0 + v_mov_b32 v4, 0 + v_mov_b32 v5, 0 + v_mov_b32 v6, 0 + v_mov_b32 v7, 0 + s_sub_u32 s2, s2, 8 + s_set_gpr_idx_idx s2 + s_cbranch_scc0 label_0005 + s_set_gpr_idx_off + + // + // + + s_mov_b32 s2, 0x80000000 // Bit31 is first_wave + s_and_b32 s2, s2, s1 // sgpr0 has tg_size (first_wave) term as in ucode only COMPUTE_PGM_RSRC2.tg_size_en is set + s_cbranch_scc0 label_clean_sgpr_1 // Clean LDS if its first wave of ThreadGroup/WorkGroup + // CLEAR LDS + // + s_mov_b32 exec_lo, 0xffffffff + s_mov_b32 exec_hi, 0xffffffff + v_mbcnt_lo_u32_b32 v1, exec_hi, 0 // Set V1 to thread-ID (0..63) + v_mbcnt_hi_u32_b32 v1, exec_lo, v1 // Set V1 to thread-ID (0..63) + v_mul_u32_u24 v1, 0x00000008, v1 // * 8, so each thread is a double-dword address (8byte) + s_mov_b32 s2, 0x00000003f // 64 loop iterations + s_mov_b32 m0, 0xffffffff + // Clear all of LDS space + // Each FirstWave of WorkGroup clears 64kbyte block + +label_001F: + ds_write2_b64 v1, v[2:3], v[2:3] offset1:32 + ds_write2_b64 v1, v[4:5], v[4:5] offset0:64 offset1:96 + v_add_co_u32 v1, vcc, 0x00000400, v1 + s_sub_u32 s2, s2, 1 + s_cbranch_scc0 label_001F + // + // CLEAR SGPRs + // +label_clean_sgpr_1: + s_mov_b32 m0, 0x0000005c // Loop 96/4=24 times (loop unrolled for performance) + s_nop 0 +label_sgpr_loop: + s_movreld_b32 s0, 0 + s_movreld_b32 s1, 0 + s_movreld_b32 s2, 0 + s_movreld_b32 s3, 0 + s_sub_u32 m0, m0, 4 + s_cbranch_scc0 label_sgpr_loop + + //clear vcc, flat scratch + s_mov_b32 flat_scratch_lo, 0 //clear flat scratch lo SGPR + s_mov_b32 flat_scratch_hi, 0 //clear flat scratch hi SGPR + s_mov_b64 vcc, 0 //clear vcc + s_mov_b64 ttmp0, 0 //Clear ttmp0 and ttmp1 + s_mov_b64 ttmp2, 0 //Clear ttmp2 and ttmp3 + s_mov_b64 ttmp4, 0 //Clear ttmp4 and ttmp5 + s_mov_b64 ttmp6, 0 //Clear ttmp6 and ttmp7 + s_mov_b64 ttmp8, 0 //Clear ttmp8 and ttmp9 + s_mov_b64 ttmp10, 0 //Clear ttmp10 and ttmp11 + s_mov_b64 ttmp12, 0 //Clear ttmp12 and ttmp13 + s_mov_b64 ttmp14, 0 //Clear ttmp14 and ttmp15 +s_endpgm + +label_0023: + + s_sethalt 1 + + s_mov_b32 m0, 0x0000005c // Loop 96/4=24 times (loop unrolled for performance) + s_nop 0 +label_sgpr_loop1: + + s_movreld_b32 s0, 0 + s_movreld_b32 s1, 0 + s_movreld_b32 s2, 0 + s_movreld_b32 s3, 0 + s_sub_u32 m0, m0, 4 + s_cbranch_scc0 label_sgpr_loop1 + + //clear vcc, flat scratch + s_mov_b32 flat_scratch_lo, 0 //clear flat scratch lo SGPR + s_mov_b32 flat_scratch_hi, 0 //clear flat scratch hi SGPR + s_mov_b64 vcc, 0xee //clear vcc + +s_endpgm +end + From 40f8704112056a20a0b9ea6ff4becd6520583d13 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 14 Oct 2024 10:51:10 -0400 Subject: [PATCH 1782/1868] drm/amdkfd: add an interface to query whether is KFD is active Add an interface to query whether KFD has any active queues. v2: fix build issues Acked-by: Srinivasan Shanmugam Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c | 9 ++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h | 7 ++++++ drivers/gpu/drm/amd/amdkfd/kfd_device.c | 25 ++++++++++++++++++++++ 3 files changed, 41 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c index 9f39f8d8350b9..f0ab00c2e1342 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.c @@ -902,6 +902,15 @@ int amdgpu_amdkfd_start_sched(struct amdgpu_device *adev, uint32_t node_id) return kgd2kfd_start_sched(adev->kfd.dev, node_id); } +/* check if there are KFD queues active */ +bool amdgpu_amdkfd_compute_active(struct amdgpu_device *adev, uint32_t node_id) +{ + if (!adev->kfd.init_complete) + return false; + + return kgd2kfd_compute_active(adev->kfd.dev, node_id); +} + /* Config CGTT_SQ_CLK_CTRL */ int amdgpu_amdkfd_config_sq_perfmon(struct amdgpu_device *adev, uint32_t xcp_id, bool core_override_enable, bool reg_override_enable, bool perfmon_override_enable) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h index 4f59b80af73c3..d62bf78c4883a 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.h @@ -284,6 +284,7 @@ int amdgpu_amdkfd_start_sched(struct amdgpu_device *adev, uint32_t node_id); int amdgpu_amdkfd_stop_sched(struct amdgpu_device *adev, uint32_t node_id); int amdgpu_amdkfd_config_sq_perfmon(struct amdgpu_device *adev, uint32_t xcp_id, bool core_override_enable, bool reg_override_enable, bool perfmon_override_enable); +bool amdgpu_amdkfd_compute_active(struct amdgpu_device *adev, uint32_t node_id); /* Read user wptr from a specified user address space with page fault @@ -504,6 +505,7 @@ int kgd2kfd_check_and_lock_kfd(void); void kgd2kfd_unlock_kfd(void); int kgd2kfd_start_sched(struct kfd_dev *kfd, uint32_t node_id); int kgd2kfd_stop_sched(struct kfd_dev *kfd, uint32_t node_id); +bool kgd2kfd_compute_active(struct kfd_dev *kfd, uint32_t node_id); #else static inline int kgd2kfd_init(void) { @@ -584,5 +586,10 @@ static inline int kgd2kfd_stop_sched(struct kfd_dev *kfd, uint32_t node_id) { return 0; } + +static inline bool kgd2kfd_compute_active(struct kfd_dev *kfd, uint32_t node_id) +{ + return false; +} #endif #endif /* AMDGPU_AMDKFD_H_INCLUDED */ diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device.c b/drivers/gpu/drm/amd/amdkfd/kfd_device.c index b587dd8dc8988..b6c5ffd4630be 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_device.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_device.c @@ -1431,6 +1431,13 @@ void kfd_dec_compute_active(struct kfd_node *node) WARN_ONCE(count < 0, "Compute profile ref. count error"); } +static bool kfd_compute_active(struct kfd_node *node) +{ + if (atomic_read(&node->kfd->compute_profile)) + return true; + return false; +} + void kgd2kfd_smi_event_throttle(struct kfd_dev *kfd, uint64_t throttle_bitmask) { /* @@ -1524,6 +1531,24 @@ int kgd2kfd_stop_sched(struct kfd_dev *kfd, uint32_t node_id) return node->dqm->ops.halt(node->dqm); } +bool kgd2kfd_compute_active(struct kfd_dev *kfd, uint32_t node_id) +{ + struct kfd_node *node; + + if (!kfd->init_complete) + return false; + + if (node_id >= kfd->num_nodes) { + dev_warn(kfd->adev->dev, "Invalid node ID: %u exceeds %u\n", + node_id, kfd->num_nodes - 1); + return false; + } + + node = kfd->nodes[node_id]; + + return kfd_compute_active(node); +} + #if defined(CONFIG_DEBUG_FS) /* This function will send a package to HIQ to hang the HWS From 2b14628092c821e8f040989cdd6ee4084a8672f9 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 14 Oct 2024 11:58:34 -0400 Subject: [PATCH 1783/1868] drm/amdgpu: fix fairness in enforce isolation handling Make sure KFD gets a turn when serializing access to the GC IP. Currently non-KFD jobs can starve KFD if they submit often enough. This patch prevents that by stalling non-KFD if its time period has elapsed. v2: fix units v3: check enablement properly Acked-by: Srinivasan Shanmugam Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 2 +- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 53 ++++++++++++++++++++++++- drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h | 2 + 3 files changed, 54 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index d240dd8e15248..22c7e9669162e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -119,7 +119,7 @@ #define MAX_GPU_INSTANCE 64 -#define GFX_SLICE_PERIOD msecs_to_jiffies(250) +#define GFX_SLICE_PERIOD_MS 250 struct amdgpu_gpu_instance { struct amdgpu_device *adev; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c index e96984c53e72c..b8cc4b146bdc6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c @@ -1752,7 +1752,7 @@ static void amdgpu_gfx_kfd_sch_ctrl(struct amdgpu_device *adev, u32 idx, if (adev->gfx.kfd_sch_req_count[idx] == 0 && adev->gfx.kfd_sch_inactive[idx]) { schedule_delayed_work(&adev->gfx.enforce_isolation[idx].work, - GFX_SLICE_PERIOD); + msecs_to_jiffies(adev->gfx.enforce_isolation_time[idx])); } } else { if (adev->gfx.kfd_sch_req_count[idx] == 0) { @@ -1807,8 +1807,9 @@ void amdgpu_gfx_enforce_isolation_handler(struct work_struct *work) fences += amdgpu_fence_count_emitted(&adev->gfx.compute_ring[i]); } if (fences) { + /* we've already had our timeslice, so let's wrap this up */ schedule_delayed_work(&adev->gfx.enforce_isolation[idx].work, - GFX_SLICE_PERIOD); + msecs_to_jiffies(1)); } else { /* Tell KFD to resume the runqueue */ if (adev->kfd.init_complete) { @@ -1821,6 +1822,51 @@ void amdgpu_gfx_enforce_isolation_handler(struct work_struct *work) mutex_unlock(&adev->enforce_isolation_mutex); } +static void +amdgpu_gfx_enforce_isolation_wait_for_kfd(struct amdgpu_device *adev, + u32 idx) +{ + unsigned long cjiffies; + bool wait = false; + + mutex_lock(&adev->enforce_isolation_mutex); + if (adev->enforce_isolation[idx]) { + /* set the initial values if nothing is set */ + if (!adev->gfx.enforce_isolation_jiffies[idx]) { + adev->gfx.enforce_isolation_jiffies[idx] = jiffies; + adev->gfx.enforce_isolation_time[idx] = GFX_SLICE_PERIOD_MS; + } + /* Make sure KFD gets a chance to run */ + if (amdgpu_amdkfd_compute_active(adev, idx)) { + cjiffies = jiffies; + if (time_after(cjiffies, adev->gfx.enforce_isolation_jiffies[idx])) { + cjiffies -= adev->gfx.enforce_isolation_jiffies[idx]; + if ((jiffies_to_msecs(cjiffies) >= GFX_SLICE_PERIOD_MS)) { + /* if our time is up, let KGD work drain before scheduling more */ + wait = true; + /* reset the timer period */ + adev->gfx.enforce_isolation_time[idx] = GFX_SLICE_PERIOD_MS; + } else { + /* set the timer period to what's left in our time slice */ + adev->gfx.enforce_isolation_time[idx] = + GFX_SLICE_PERIOD_MS - jiffies_to_msecs(cjiffies); + } + } else { + /* if jiffies wrap around we will just wait a little longer */ + adev->gfx.enforce_isolation_jiffies[idx] = jiffies; + } + } else { + /* if there is no KFD work, then set the full slice period */ + adev->gfx.enforce_isolation_jiffies[idx] = jiffies; + adev->gfx.enforce_isolation_time[idx] = GFX_SLICE_PERIOD_MS; + } + } + mutex_unlock(&adev->enforce_isolation_mutex); + + if (wait) + msleep(GFX_SLICE_PERIOD_MS); +} + void amdgpu_gfx_enforce_isolation_ring_begin_use(struct amdgpu_ring *ring) { struct amdgpu_device *adev = ring->adev; @@ -1837,6 +1883,9 @@ void amdgpu_gfx_enforce_isolation_ring_begin_use(struct amdgpu_ring *ring) if (idx >= MAX_XCP) return; + /* Don't submit more work until KFD has had some time */ + amdgpu_gfx_enforce_isolation_wait_for_kfd(adev, idx); + mutex_lock(&adev->enforce_isolation_mutex); if (adev->enforce_isolation[idx]) { if (adev->kfd.init_complete) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h index 15fffc2875e70..fbc6240febf52 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h @@ -483,6 +483,8 @@ struct amdgpu_gfx { struct mutex kfd_sch_mutex; u64 kfd_sch_req_count[MAX_XCP]; bool kfd_sch_inactive[MAX_XCP]; + unsigned long enforce_isolation_jiffies[MAX_XCP]; + unsigned long enforce_isolation_time[MAX_XCP]; }; struct amdgpu_gfx_ras_reg_entry { From e48e2693941bdb96ef38ce52109182aef6ff591c Mon Sep 17 00:00:00 2001 From: Srinivasan Shanmugam Date: Wed, 6 Nov 2024 19:25:50 +0530 Subject: [PATCH 1784/1868] drm/amdgpu: Add documentation for enforce isolation feature MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This feature enables process isolation on the graphics engine by serializing access to it and adding a cleaner shader which clears LDS (Local Data Store) and GPRs (General Purpose Registers) between jobs. Cc: Christian König Cc: Alex Deucher Signed-off-by: Srinivasan Shanmugam Suggested-by: Alex Deucher Suggested-by: Asad Kamal Reviewed-by: Alex Deucher --- Documentation/gpu/amdgpu/index.rst | 1 + .../gpu/amdgpu/process-isolation.rst | 59 +++++++++++++++++++ 2 files changed, 60 insertions(+) create mode 100644 Documentation/gpu/amdgpu/process-isolation.rst diff --git a/Documentation/gpu/amdgpu/index.rst b/Documentation/gpu/amdgpu/index.rst index 847e04924030c..302d039928ee8 100644 --- a/Documentation/gpu/amdgpu/index.rst +++ b/Documentation/gpu/amdgpu/index.rst @@ -16,4 +16,5 @@ Next (GCN), Radeon DNA (RDNA), and Compute DNA (CDNA) architectures. thermal driver-misc debugging + process-isolation amdgpu-glossary diff --git a/Documentation/gpu/amdgpu/process-isolation.rst b/Documentation/gpu/amdgpu/process-isolation.rst new file mode 100644 index 0000000000000..6b6d70e357a75 --- /dev/null +++ b/Documentation/gpu/amdgpu/process-isolation.rst @@ -0,0 +1,59 @@ +.. SPDX-License-Identifier: GPL-2.0 + +========================= + AMDGPU Process Isolation +========================= + +The AMDGPU driver includes a feature that enables automatic process isolation on the graphics engine. This feature serializes access to the graphics engine and adds a cleaner shader which clears the Local Data Store (LDS) and General Purpose Registers (GPRs) between jobs. All processes using the GPU, including both graphics and compute workloads, are serialized when this feature is enabled. On GPUs that support partitionable graphics engines, this feature can be enabled on a per-partition basis. + +In addition, there is an interface to manually run the cleaner shader when the use of the GPU is complete. This may be preferable in some use cases, such as a single-user system where the login manager triggers the cleaner shader when the user logs out. + +Process Isolation +================= + +The `run_cleaner_shader` and `enforce_isolation` sysfs interfaces allow users to manually execute the cleaner shader and control the process isolation feature, respectively. + +Partition Handling +------------------ + +The `enforce_isolation` file in sysfs can be used to enable process isolation and automatic shader cleanup between processes. On GPUs that support graphics engine partitioning, this can be enabled per partition. The partition and its current setting (0 disabled, 1 enabled) can be read from sysfs. On GPUs that do not support graphics engine partitioning, only a single partition will be present. Writing 1 to the partition position enables enforce isolation, writing 0 disables it. + +Example of enabling enforce isolation on a GPU with multiple partitions: + +.. code-block:: console + + $ echo 1 0 1 0 > /sys/class/drm/card0/device/enforce_isolation + $ cat /sys/class/drm/card0/device/enforce_isolation + 1 0 1 0 + +The output indicates that enforce isolation is enabled on zeroth and second parition and disabled on first and fourth parition. + +For devices with a single partition or those that do not support partitions, there will be only one element: + +.. code-block:: console + + $ echo 1 > /sys/class/drm/card0/device/enforce_isolation + $ cat /sys/class/drm/card0/device/enforce_isolation + 1 + +Cleaner Shader Execution +======================== + +The driver can trigger a cleaner shader to clean up the LDS and GPR state on the graphics engine. When process isolation is enabled, this happens automatically between processes. In addition, there is a sysfs file to manually trigger cleaner shader execution. + +To manually trigger the execution of the cleaner shader, write `0` to the `run_cleaner_shader` sysfs file: + +.. code-block:: console + + $ echo 0 > /sys/class/drm/card0/device/run_cleaner_shader + +For multi-partition devices, you can specify the partition index when triggering the cleaner shader: + +.. code-block:: console + + $ echo 0 > /sys/class/drm/card0/device/run_cleaner_shader # For partition 0 + $ echo 1 > /sys/class/drm/card0/device/run_cleaner_shader # For partition 1 + $ echo 2 > /sys/class/drm/card0/device/run_cleaner_shader # For partition 2 + # ... and so on for each partition + +This command initiates the cleaner shader, which will run and complete before any new tasks are scheduled on the GPU. From 4a0ac21661f1a7db55dfa635fd4107045bd47843 Mon Sep 17 00:00:00 2001 From: Shyam Sundar S K Date: Thu, 18 Jul 2024 20:31:19 +0530 Subject: [PATCH 1785/1868] platform/x86/amd/pmc: Send OS_HINT command for new AMD platform MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit To initiate the HW deep state transition, the OS_HINT command has to be sent to the PMFW. Add this support to the platforms that belong to family 1Ah model 60h series. Signed-off-by: Shyam Sundar S K Reviewed-by: Ilpo Järvinen Link: https://lore.kernel.org/r/20240718150119.3427190-1-Shyam-sundar.S-k@amd.com Signed-off-by: Ilpo Järvinen (cherry picked from commit c3f4ebce08064c8844957334c9b6a2595d8f461f) Signed-off-by: Alex Hung --- drivers/platform/x86/amd/pmc/pmc.c | 2 ++ drivers/platform/x86/amd/pmc/pmc.h | 1 + 2 files changed, 3 insertions(+) diff --git a/drivers/platform/x86/amd/pmc/pmc.c b/drivers/platform/x86/amd/pmc/pmc.c index 3bfa312839b3c..87f0af3ff4b3a 100644 --- a/drivers/platform/x86/amd/pmc/pmc.c +++ b/drivers/platform/x86/amd/pmc/pmc.c @@ -766,6 +766,7 @@ static int amd_pmc_get_os_hint(struct amd_pmc_dev *dev) case AMD_CPU_ID_CB: case AMD_CPU_ID_PS: case PCI_DEVICE_ID_AMD_1AH_M20H_ROOT: + case PCI_DEVICE_ID_AMD_1AH_M60H_ROOT: return MSG_OS_HINT_RN; } return -EINVAL; @@ -969,6 +970,7 @@ static const struct pci_device_id pmc_pci_ids[] = { { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_RV) }, { PCI_DEVICE(PCI_VENDOR_ID_AMD, AMD_CPU_ID_SP) }, { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M20H_ROOT) }, + { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_1AH_M60H_ROOT) }, { } }; diff --git a/drivers/platform/x86/amd/pmc/pmc.h b/drivers/platform/x86/amd/pmc/pmc.h index 9e32d3128c3a2..f1166d15c8562 100644 --- a/drivers/platform/x86/amd/pmc/pmc.h +++ b/drivers/platform/x86/amd/pmc/pmc.h @@ -67,6 +67,7 @@ void amd_mp2_stb_deinit(struct amd_pmc_dev *dev); #define AMD_CPU_ID_PS 0x14E8 #define AMD_CPU_ID_SP 0x14A4 #define PCI_DEVICE_ID_AMD_1AH_M20H_ROOT 0x1507 +#define PCI_DEVICE_ID_AMD_1AH_M60H_ROOT 0x1122 #define PCI_DEVICE_ID_AMD_MP2_STB 0x172c #endif /* PMC_H */ From 329bc46d0ce64ab61a8fde21c878a3651d2d869b Mon Sep 17 00:00:00 2001 From: Austin Zheng Date: Mon, 16 Sep 2024 13:09:19 -0400 Subject: [PATCH 1786/1868] drm/amd/display: Unify blank_phantom and blank_pixel_data [Why] dcn32_blank_phantom() does not consider the subVP+ODM case when blanking. Only one of the pipes will get blanked. Remaining pipes are not blanked. Will cause underflow in the phantom pipe when enabling the CRTC. [How] Use blank_pixel_data() instead of blank_phantom(). remove dcn32_blank_phantom() since logic is identical. Different DPG dimensions get programmed when blanking phantom pipes. Previously had phantom pipes use DPG dimensions of the main stream. Now use DPG dimensions of the phantom streams Reviewed-by: Alvin Lee Signed-off-by: Austin Zheng Signed-off-by: Rodrigo Siqueira Tested-by: Daniel Wheeler (cherry picked from commit 8929b7e45bcdaa8db8d2f56c8b4184b2d8f846e0) Signed-off-by: Alex Hung --- drivers/gpu/drm/amd/display/dc/core/dc.c | 12 +---- .../amd/display/dc/hwss/dcn20/dcn20_hwseq.c | 15 ++---- .../amd/display/dc/hwss/dcn32/dcn32_hwseq.c | 46 ------------------- .../amd/display/dc/hwss/dcn32/dcn32_hwseq.h | 5 -- .../amd/display/dc/hwss/dcn32/dcn32_init.c | 1 - .../amd/display/dc/hwss/dcn401/dcn401_init.c | 1 - 6 files changed, 6 insertions(+), 74 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 309b121ba87cb..65f6e4e4c01d4 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1235,16 +1235,8 @@ static void disable_dangling_plane(struct dc *dc, struct dc_state *context) */ if (is_phantom) { if (tg->funcs->enable_crtc) { - int main_pipe_width = 0, main_pipe_height = 0; - struct dc_stream_state *old_paired_stream = dc_state_get_paired_subvp_stream(dc->current_state, old_stream); - - if (old_paired_stream) { - main_pipe_width = old_paired_stream->dst.width; - main_pipe_height = old_paired_stream->dst.height; - } - - if (dc->hwss.blank_phantom) - dc->hwss.blank_phantom(dc, tg, main_pipe_width, main_pipe_height); + if (dc->hwseq->funcs.blank_pixel_data) + dc->hwseq->funcs.blank_pixel_data(dc, pipe, true); tg->funcs->enable_crtc(tg); } } diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c index e89499536c460..1a32e53c1b22a 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c @@ -2054,22 +2054,15 @@ void dcn20_program_front_end_for_ctx( */ for (i = 0; i < dc->res_pool->pipe_count; i++) { struct dc_stream_state *stream = dc->current_state->res_ctx.pipe_ctx[i].stream; + pipe = &dc->current_state->res_ctx.pipe_ctx[i]; if (context->res_ctx.pipe_ctx[i].update_flags.bits.disable && stream && - dc_state_get_pipe_subvp_type(dc->current_state, &dc->current_state->res_ctx.pipe_ctx[i]) == SUBVP_PHANTOM) { + dc_state_get_pipe_subvp_type(dc->current_state, pipe) == SUBVP_PHANTOM) { struct timing_generator *tg = dc->current_state->res_ctx.pipe_ctx[i].stream_res.tg; if (tg->funcs->enable_crtc) { - if (dc->hwss.blank_phantom) { - int main_pipe_width = 0, main_pipe_height = 0; - struct dc_stream_state *phantom_stream = dc_state_get_paired_subvp_stream(dc->current_state, dc->current_state->res_ctx.pipe_ctx[i].stream); - - if (phantom_stream) { - main_pipe_width = phantom_stream->dst.width; - main_pipe_height = phantom_stream->dst.height; - } - - dc->hwss.blank_phantom(dc, tg, main_pipe_width, main_pipe_height); + if (dc->hwseq->funcs.blank_pixel_data) { + dc->hwseq->funcs.blank_pixel_data(dc, pipe, true); } tg->funcs->enable_crtc(tg); } diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c index dd6dac7b46194..5e2edba93a199 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c @@ -1697,52 +1697,6 @@ void dcn32_init_blank( hws->funcs.wait_for_blank_complete(opp); } -void dcn32_blank_phantom(struct dc *dc, - struct timing_generator *tg, - int width, - int height) -{ - struct dce_hwseq *hws = dc->hwseq; - enum dc_color_space color_space; - struct tg_color black_color = {0}; - struct output_pixel_processor *opp = NULL; - uint32_t num_opps, opp_id_src0, opp_id_src1; - uint32_t otg_active_width, otg_active_height; - uint32_t i; - - /* program opp dpg blank color */ - color_space = COLOR_SPACE_SRGB; - color_space_to_black_color(dc, color_space, &black_color); - - otg_active_width = width; - otg_active_height = height; - - /* get the OPTC source */ - tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1); - ASSERT(opp_id_src0 < dc->res_pool->res_cap->num_opp); - - for (i = 0; i < dc->res_pool->res_cap->num_opp; i++) { - if (dc->res_pool->opps[i] != NULL && dc->res_pool->opps[i]->inst == opp_id_src0) { - opp = dc->res_pool->opps[i]; - break; - } - } - - if (opp && opp->funcs->opp_set_disp_pattern_generator) - opp->funcs->opp_set_disp_pattern_generator( - opp, - CONTROLLER_DP_TEST_PATTERN_SOLID_COLOR, - CONTROLLER_DP_COLOR_SPACE_UDEFINED, - COLOR_DEPTH_UNDEFINED, - &black_color, - otg_active_width, - otg_active_height, - 0); - - if (tg->funcs->is_tg_enabled(tg)) - hws->funcs.wait_for_blank_complete(opp); -} - /* phantom stream id's can change often, but can be identical between contexts. * This function checks for the condition the streams are identical to avoid * redundant pipe transitions. diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h index cac4a08b92a4d..0303a59536737 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.h @@ -119,11 +119,6 @@ void dcn32_init_blank( struct dc *dc, struct timing_generator *tg); -void dcn32_blank_phantom(struct dc *dc, - struct timing_generator *tg, - int width, - int height); - bool dcn32_is_pipe_topology_transition_seamless(struct dc *dc, const struct dc_state *cur_ctx, const struct dc_state *new_ctx); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c index 8e0946fd5b7fe..dbcd2dfb19c12 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c @@ -117,7 +117,6 @@ static const struct hw_sequencer_funcs dcn32_funcs = { .update_phantom_vp_position = dcn32_update_phantom_vp_position, .update_dsc_pg = dcn32_update_dsc_pg, .apply_update_flags_for_phantom = dcn32_apply_update_flags_for_phantom, - .blank_phantom = dcn32_blank_phantom, .is_pipe_topology_transition_seamless = dcn32_is_pipe_topology_transition_seamless, .calculate_pix_rate_divider = dcn32_calculate_pix_rate_divider, .program_outstanding_updates = dcn32_program_outstanding_updates, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c index af0d40a5cb77a..a1392e776709d 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c @@ -93,7 +93,6 @@ static const struct hw_sequencer_funcs dcn401_funcs = { .update_phantom_vp_position = dcn32_update_phantom_vp_position, .update_dsc_pg = dcn32_update_dsc_pg, .apply_update_flags_for_phantom = dcn32_apply_update_flags_for_phantom, - .blank_phantom = dcn32_blank_phantom, .wait_for_dcc_meta_propagation = dcn401_wait_for_dcc_meta_propagation, .is_pipe_topology_transition_seamless = dcn32_is_pipe_topology_transition_seamless, .fams2_global_control_lock = dcn401_fams2_global_control_lock, From dfc62228d41ba95715c3b08fdf663ecbb36175d1 Mon Sep 17 00:00:00 2001 From: Fudongwang Date: Sat, 14 Sep 2024 09:33:44 +0800 Subject: [PATCH 1787/1868] drm/amd/display: skip disable CRTC in seemless bootup case Resync FIFO is a workaround to write the same value to DENTIST_DISPCLK_CNTL register after programming OTG_PIXEL_RATE_DIV register, in case seemless boot, there is no OTG_PIXEL_RATE_DIV register update, so skip CRTC disable when resync FIFO to avoid random FIFO error and garbage. Reviewed-by: Nicholas Kazlauskas Signed-off-by: Fudongwang Signed-off-by: Rodrigo Siqueira Tested-by: Daniel Wheeler (cherry picked from commit 4ea5249e51437769afe9793c2e06ba9fe3adc0e1) Signed-off-by: Alex Hung --- drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c index 5b6cf2a8e38da..e0054e654db62 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c @@ -371,7 +371,9 @@ void dcn314_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc if (pipe->top_pipe || pipe->prev_odm_pipe) continue; - if (pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal))) { + if (pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal)) && + !pipe->stream->apply_seamless_boot_optimization && + !pipe->stream->apply_edp_fast_boot_optimization) { pipe->stream_res.tg->funcs->disable_crtc(pipe->stream_res.tg); reset_sync_context_for_pipe(dc, context, i); otg_disabled[i] = true; From ab5b75f56578f87deab8d4de2eea4dbdc3079635 Mon Sep 17 00:00:00 2001 From: Austin Zheng Date: Fri, 20 Sep 2024 14:22:38 -0400 Subject: [PATCH 1788/1868] drm/amd/display: Flip All Planes Under OTG Master When Flip Immediate [Why] The MPO plane will receive a flip but desktop plane may not receive a flip when GSL is enabled. As a result, system will be stuck waiting for a flip that was never sent. [How] Set update address update flag of all flip_immediate planes if there are multiple planes. Reviewed-by: Dillon Varone Signed-off-by: Austin Zheng Signed-off-by: Rodrigo Siqueira Tested-by: Daniel Wheeler (cherry picked from commit 1ea3e1958e4bad7d6242973ca6f5916a068e5ca4) Signed-off-by: Alex Hung --- drivers/gpu/drm/amd/display/dc/core/dc.c | 33 ++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 65f6e4e4c01d4..5510719a82da8 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -2661,6 +2661,29 @@ static enum surface_update_type det_surface_update(const struct dc *dc, return overall_type; } +/* May need to flip the desktop plane in cases where MPO plane receives a flip but desktop plane doesn't + * while both planes are flip_immediate + */ +static void force_immediate_gsl_plane_flip(struct dc *dc, struct dc_surface_update *updates, int surface_count) +{ + bool has_flip_immediate_plane = false; + int i; + + for (i = 0; i < surface_count; i++) { + if (updates[i].surface->flip_immediate) { + has_flip_immediate_plane = true; + break; + } + } + + if (has_flip_immediate_plane && surface_count > 1) { + for (i = 0; i < surface_count; i++) { + if (updates[i].surface->flip_immediate) + updates[i].surface->update_flags.bits.addr_update = 1; + } + } +} + static enum surface_update_type check_update_surfaces_for_stream( struct dc *dc, struct dc_surface_update *updates, @@ -3178,6 +3201,11 @@ static bool update_planes_and_stream_state(struct dc *dc, context = dc->current_state; update_type = dc_check_update_surfaces_for_stream( dc, srf_updates, surface_count, stream_update, stream_status); + /* It is possible to receive a flip for one plane while there are multiple flip_immediate planes in the same stream. + * E.g. Desktop and MPO plane are flip_immediate but only the MPO plane received a flip + * Force the other flip_immediate planes to flip so GSL doesn't wait for a flip that won't come. + */ + force_immediate_gsl_plane_flip(dc, srf_updates, surface_count); if (update_type == UPDATE_TYPE_FULL) backup_planes_and_stream_state(&dc->scratch.current_state, stream); @@ -4808,6 +4836,11 @@ static bool update_planes_and_stream_v1(struct dc *dc, update_type = dc_check_update_surfaces_for_stream( dc, srf_updates, surface_count, stream_update, stream_status); + /* It is possible to receive a flip for one plane while there are multiple flip_immediate planes in the same stream. + * E.g. Desktop and MPO plane are flip_immediate but only the MPO plane received a flip + * Force the other flip_immediate planes to flip so GSL doesn't wait for a flip that won't come. + */ + force_immediate_gsl_plane_flip(dc, srf_updates, surface_count); if (update_type >= UPDATE_TYPE_FULL) { From bf2c50dd0327c583cf67d66b6987d5a98dc50195 Mon Sep 17 00:00:00 2001 From: Austin Zheng Date: Mon, 23 Sep 2024 10:07:32 -0400 Subject: [PATCH 1789/1868] drm/amd/display: Revert commit Update Interface to Check UCLK DPM This reverts commit 1b4ef7a2d5bcf9ab7e58e7c1efacd458f645b824. Reverting as regression discovered on certain systems and golden values need to updated. Reviewed-by: Alvin Lee Signed-off-by: Austin Zheng Signed-off-by: Rodrigo Siqueira Tested-by: Daniel Wheeler (cherry picked from commit 0e04c80be460a111e8ea234cab307348f25d6289) Signed-off-by: Alex Hung --- drivers/gpu/drm/amd/display/dc/core/dc.c | 9 +-------- .../dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c | 1 - drivers/gpu/drm/amd/display/dc/inc/core_types.h | 4 ---- .../dc/resource/dcn315/dcn315_resource.c | 6 ------ .../dc/resource/dcn401/dcn401_resource.c | 17 ----------------- 5 files changed, 1 insertion(+), 36 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 5510719a82da8..c4d59ad5fa9f4 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -6039,15 +6039,8 @@ void dc_set_edp_power(const struct dc *dc, struct dc_link *edp_link, struct dc_power_profile dc_get_power_profile_for_dc_state(const struct dc_state *context) { struct dc_power_profile profile = { 0 }; - struct dc *dc = NULL; - if (!context || !context->clk_mgr || !context->clk_mgr->ctx || !context->clk_mgr->ctx->dc) - return profile; - - dc = context->clk_mgr->ctx->dc; - - if (dc->res_pool->funcs->get_power_profile) - profile.power_level = dc->res_pool->funcs->get_power_profile(context); + profile.power_level += !context->bw_ctx.bw.dcn.clk.p_state_change_support; return profile; } diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c index 2e9c59e9e0c13..1cf9015e854a9 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c @@ -1798,7 +1798,6 @@ bool pmo_dcn4_fams2_init_for_pstate_support(struct dml2_pmo_init_for_pstate_supp } if (s->pmo_dcn4.num_pstate_candidates > 0) { - s->pmo_dcn4.pstate_strategy_candidates[s->pmo_dcn4.num_pstate_candidates-1].allow_state_increase = true; s->pmo_dcn4.cur_pstate_candidate = -1; return true; } else { diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index 7de2dc933a098..805b25676734e 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -214,10 +214,6 @@ struct resource_funcs { void (*get_panel_config_defaults)(struct dc_panel_config *panel_config); void (*build_pipe_pix_clk_params)(struct pipe_ctx *pipe_ctx); - /* - * Get indicator of power from a context that went through full validation - */ - int (*get_power_profile)(const struct dc_state *context); }; struct audio_support{ diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c index f6b840f046a5d..3f4b9dba41124 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c @@ -1812,11 +1812,6 @@ static void dcn315_get_panel_config_defaults(struct dc_panel_config *panel_confi *panel_config = panel_config_defaults; } -static int dcn315_get_power_profile(const struct dc_state *context) -{ - return !context->bw_ctx.bw.dcn.clk.p_state_change_support; -} - static struct dc_cap_funcs cap_funcs = { .get_dcc_compression_cap = dcn20_get_dcc_compression_cap }; @@ -1845,7 +1840,6 @@ static struct resource_funcs dcn315_res_pool_funcs = { .update_bw_bounding_box = dcn315_update_bw_bounding_box, .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, .get_panel_config_defaults = dcn315_get_panel_config_defaults, - .get_power_profile = dcn315_get_power_profile, }; static bool dcn315_resource_construct( diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c index 59184abab1a70..f2653a86d3e7d 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c @@ -1688,22 +1688,6 @@ static void dcn401_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx) } } -static int dcn401_get_power_profile(const struct dc_state *context) -{ - int uclk_mhz = context->bw_ctx.bw.dcn.clk.dramclk_khz / 1000; - int dpm_level = 0; - - for (int i = 0; i < context->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels; i++) { - if (context->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz == 0 || - uclk_mhz < context->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz) - break; - if (uclk_mhz > context->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz) - dpm_level++; - } - - return dpm_level; -} - static struct resource_funcs dcn401_res_pool_funcs = { .destroy = dcn401_destroy_resource_pool, .link_enc_create = dcn401_link_encoder_create, @@ -1730,7 +1714,6 @@ static struct resource_funcs dcn401_res_pool_funcs = { .prepare_mcache_programming = dcn401_prepare_mcache_programming, .build_pipe_pix_clk_params = dcn401_build_pipe_pix_clk_params, .calculate_mall_ways_from_bytes = dcn32_calculate_mall_ways_from_bytes, - .get_power_profile = dcn401_get_power_profile, }; static uint32_t read_pipe_fuses(struct dc_context *ctx) From 3fc510bbfc860c9f7a7ba1c5ee1e0b518f237e8a Mon Sep 17 00:00:00 2001 From: Fudongwang Date: Sat, 14 Sep 2024 17:57:06 +0800 Subject: [PATCH 1790/1868] drm/amd/display: force TBT4 dock dsc on [why] TBT4 dock have bandwidth limitation, need dsc always on to support all modes. [how] force dsc always on when detect TBT4 dock. Reviewed-by: Aric Cyr Signed-off-by: Fudongwang Signed-off-by: Rodrigo Siqueira Tested-by: Daniel Wheeler (cherry picked from commit dc3f3d71cf3610df918a83358ff89b86281ff61b) Signed-off-by: Alex Hung --- drivers/gpu/drm/amd/display/dc/dc_dp_types.h | 4 ++++ drivers/gpu/drm/amd/display/dc/link/link_detection.c | 12 ++++++++++++ .../display/dc/link/protocols/link_dp_capability.c | 7 +++++++ 3 files changed, 23 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h index 41bd95e9177a4..50fa8547d718e 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h @@ -1166,6 +1166,7 @@ struct dpcd_caps { int8_t branch_dev_name[6]; int8_t branch_hw_revision; int8_t branch_fw_revision[2]; + int8_t branch_vendor_specific_data[4]; bool allow_invalid_MSA_timing_param; bool panel_mode_edp; @@ -1358,6 +1359,9 @@ struct dp_trace { #ifndef DP_TUNNELING_IRQ #define DP_TUNNELING_IRQ (1 << 5) #endif +#ifndef DP_BRANCH_VENDOR_SPECIFIC_START +#define DP_BRANCH_VENDOR_SPECIFIC_START 0x50C +#endif /** USB4 DPCD BW Allocation Registers Chapter 10.7 **/ #ifndef DP_TUNNELING_CAPABILITIES #define DP_TUNNELING_CAPABILITIES 0xE000D /* 1.4a */ diff --git a/drivers/gpu/drm/amd/display/dc/link/link_detection.c b/drivers/gpu/drm/amd/display/dc/link/link_detection.c index d21ee9d12d269..e026c728042a5 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_detection.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_detection.c @@ -48,6 +48,9 @@ #include "dm_helpers.h" #include "clk_mgr.h" + // Offset DPCD 050Eh == 0x5A +#define MST_HUB_ID_0x5A 0x5A + #define DC_LOGGER \ link->ctx->logger #define DC_LOGGER_INIT(logger) @@ -692,6 +695,15 @@ static void apply_dpia_mst_dsc_always_on_wa(struct dc_link *link) link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT && !link->dc->debug.dpia_debug.bits.disable_mst_dsc_work_around) link->wa_flags.dpia_mst_dsc_always_on = true; + + if (link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA && + link->type == dc_connection_mst_branch && + link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_90CC24 && + link->dpcd_caps.branch_vendor_specific_data[2] == MST_HUB_ID_0x5A && + link->dpcd_caps.dsc_caps.dsc_basic_caps.fields.dsc_support.DSC_SUPPORT && + !link->dc->debug.dpia_debug.bits.disable_mst_dsc_work_around) { + link->wa_flags.dpia_mst_dsc_always_on = true; + } } static void revert_dpia_mst_dsc_always_on_wa(struct dc_link *link) diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c index 571825e29c7b2..db0777661b320 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c @@ -1208,6 +1208,13 @@ static void get_active_converter_info( dp_hw_fw_revision.ieee_fw_rev, sizeof(dp_hw_fw_revision.ieee_fw_rev)); } + + core_link_read_dpcd( + link, + DP_BRANCH_VENDOR_SPECIFIC_START, + (uint8_t *)link->dpcd_caps.branch_vendor_specific_data, + sizeof(link->dpcd_caps.branch_vendor_specific_data)); + if (link->dpcd_caps.dpcd_rev.raw >= DPCD_REV_14 && link->dpcd_caps.dongle_type != DISPLAY_DONGLE_NONE) { union dp_dfp_cap_ext dfp_cap_ext; From 5adaecdcae330c2686dccd292fac06167c7bc0db Mon Sep 17 00:00:00 2001 From: Sridevi Arvindekar Date: Fri, 20 Sep 2024 14:43:09 -0400 Subject: [PATCH 1791/1868] drm/amd/display: Assign socclk in dml Assign socclk_khz value from dcn4x. Reviewed-by: Ariel Bernstein Signed-off-by: Sridevi Arvindekar Signed-off-by: Rodrigo Siqueira Tested-by: Daniel Wheeler (cherry picked from commit 8303ec54668978d2915c6ef8b34503a8739cf486) Signed-off-by: Alex Hung --- .../gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c index 8697eac1e1f7e..7a01a956e4bbd 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c @@ -1036,6 +1036,7 @@ void dml21_copy_clocks_to_dc_state(struct dml2_context *in_ctx, struct dc_state context->bw_ctx.bw.dcn.clk.p_state_change_support = in_ctx->v21.mode_programming.programming->uclk_pstate_supported; context->bw_ctx.bw.dcn.clk.dtbclk_en = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.dtbrefclk_khz > 0; context->bw_ctx.bw.dcn.clk.ref_dtbclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.dtbrefclk_khz; + context->bw_ctx.bw.dcn.clk.socclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.socclk_khz; } void dml21_extract_legacy_watermark_set(const struct dc *in_dc, struct dcn_watermarks *watermark, enum dml2_dchub_watermark_reg_set_index reg_set_idx, struct dml2_context *in_ctx) From 25a833f4ce0dc2bc07586451c54f592557cbe066 Mon Sep 17 00:00:00 2001 From: Zhongwei Date: Wed, 18 Sep 2024 14:43:49 +0800 Subject: [PATCH 1792/1868] drm/amd/display: Fix garbage or black screen when resetting otg [Why] For some EDP to MIPI panel, disabling OTG when link is alive like boot case, the converter might output garbage or show no display because our GPU is not sending required pixel data. Alos Dig fifo underflow was found which might cause garbage, when resetting otg for other types of EDP panels. [How] Skipping resetting OTG if the dig fifo is on. Make sure that the otg for the pipe is the one that the dig fifo is selecting via the FE mask. Reviewed-by: Nicholas Kazlauskas Signed-off-by: Zhongwei Signed-off-by: Rodrigo Siqueira Tested-by: Daniel Wheeler (cherry picked from commit 4acd063a2f37bae39aa8172150ac3af2e4acc356) Signed-off-by: Alex Hung --- .../dc/dio/dcn314/dcn314_dio_stream_encoder.c | 10 ++++++++++ .../amd/display/dc/hwss/dcn314/dcn314_hwseq.c | 16 ++++++++++++++++ 2 files changed, 26 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c index de4c574fe9750..1153caa60d5b7 100644 --- a/drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c +++ b/drivers/gpu/drm/amd/display/dc/dio/dcn314/dcn314_dio_stream_encoder.c @@ -83,6 +83,15 @@ void enc314_disable_fifo(struct stream_encoder *enc) REG_UPDATE(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, 0); } +static bool enc314_is_fifo_enabled(struct stream_encoder *enc) +{ + struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc); + uint32_t reset_val; + + REG_GET(DIG_FIFO_CTRL0, DIG_FIFO_ENABLE, &reset_val); + return (reset_val != 0); +} + void enc314_dp_set_odm_combine( struct stream_encoder *enc, bool odm_combine) @@ -466,6 +475,7 @@ static const struct stream_encoder_funcs dcn314_str_enc_funcs = { .enable_fifo = enc314_enable_fifo, .disable_fifo = enc314_disable_fifo, + .is_fifo_enabled = enc314_is_fifo_enabled, .set_input_mode = enc314_set_dig_input_mode, }; diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c index e0054e654db62..9b88eb72086db 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c @@ -355,6 +355,20 @@ void dcn314_calculate_pix_rate_divider( } } +static bool dcn314_is_pipe_dig_fifo_on(struct pipe_ctx *pipe) +{ + return pipe && pipe->stream + // Check dig's otg instance. + && pipe->stream_res.stream_enc + && pipe->stream_res.stream_enc->funcs->dig_source_otg + && pipe->stream_res.tg->inst == pipe->stream_res.stream_enc->funcs->dig_source_otg(pipe->stream_res.stream_enc) + && pipe->stream->link && pipe->stream->link->link_enc + && pipe->stream->link->link_enc->funcs->is_dig_enabled + && pipe->stream->link->link_enc->funcs->is_dig_enabled(pipe->stream->link->link_enc) + && pipe->stream_res.stream_enc->funcs->is_fifo_enabled + && pipe->stream_res.stream_enc->funcs->is_fifo_enabled(pipe->stream_res.stream_enc); +} + void dcn314_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_state *context, unsigned int current_pipe_idx) { unsigned int i; @@ -374,6 +388,8 @@ void dcn314_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc if (pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal)) && !pipe->stream->apply_seamless_boot_optimization && !pipe->stream->apply_edp_fast_boot_optimization) { + if (dcn314_is_pipe_dig_fifo_on(pipe)) + continue; pipe->stream_res.tg->funcs->disable_crtc(pipe->stream_res.tg); reset_sync_context_for_pipe(dc, context, i); otg_disabled[i] = true; From 9da3854f990fe2161259dbe6869c619745002559 Mon Sep 17 00:00:00 2001 From: po-tchen Date: Fri, 20 Sep 2024 15:41:55 +0800 Subject: [PATCH 1793/1868] drm/amd/display: Display lost signal on playing video [Why] When Source extend the vblank to reach the minimum panel refresh rate, the vtotal length could have 1 line longer than the maximum supported vtotal. The reason is we optimized the vtotal/refresh-rate calculation to get more accurate vtotal number by rounding the calculation result. But when the target refresh rate is the minimum refresh rate, the vtotal result could be round up and over the maximum supported vtotal. Reviewed-by: Anthony Koo Signed-off-by: po-tchen Signed-off-by: Rodrigo Siqueira Tested-by: Daniel Wheeler (cherry picked from commit be2ef6d147e349f718d0d8a4bf6f7748728fec39) Signed-off-by: Alex Hung --- .../drm/amd/display/modules/freesync/freesync.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c index bbd259cea4f4f..fc4268729017e 100644 --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c @@ -48,6 +48,7 @@ #define VSYNCS_BETWEEN_FLIP_THRESHOLD 2 #define FREESYNC_CONSEC_FLIP_AFTER_VSYNC 5 #define FREESYNC_VSYNC_TO_FLIP_DELTA_IN_US 500 +#define MICRO_HZ_TO_HZ(x) (x / 1000000) struct core_freesync { struct mod_freesync public; @@ -132,9 +133,19 @@ unsigned int mod_freesync_calc_v_total_from_refresh( ((unsigned int)(div64_u64((1000000000ULL * 1000000), refresh_in_uhz))); - v_total = div64_u64(div64_u64(((unsigned long long)( - frame_duration_in_ns) * (stream->timing.pix_clk_100hz / 10)), - stream->timing.h_total) + 500000, 1000000); + if (MICRO_HZ_TO_HZ(refresh_in_uhz) <= stream->timing.min_refresh_in_uhz) { + /* When the target refresh rate is the minimum panel refresh rate, + * round down the vtotal value to avoid stretching vblank over + * panel's vtotal boundary. + */ + v_total = div64_u64(div64_u64(((unsigned long long)( + frame_duration_in_ns) * (stream->timing.pix_clk_100hz / 10)), + stream->timing.h_total), 1000000); + } else { + v_total = div64_u64(div64_u64(((unsigned long long)( + frame_duration_in_ns) * (stream->timing.pix_clk_100hz / 10)), + stream->timing.h_total) + 500000, 1000000); + } /* v_total cannot be less than nominal */ if (v_total < stream->timing.v_total) { From ea60abd89c9bc6258caeb6cab4d314caef526470 Mon Sep 17 00:00:00 2001 From: "JinZe.Xu" Date: Thu, 26 Sep 2024 16:31:21 +0800 Subject: [PATCH 1794/1868] drm/amd/display: Noitfy DMCUB of D0/D3 state in hardware init [Why] Missing a dc_dmub_srv_notify_fw_dc_power_state in driver init. [How] Notify DMCUB of D0 state in hardware_init. Reviewed-by: Nicholas Kazlauskas Signed-off-by: JinZe.Xu Signed-off-by: Rodrigo Siqueira Tested-by: Daniel Wheeler (cherry picked from commit 3921a2d10952e28d816187f4f11099a5f68de3c4) Signed-off-by: Alex Hung --- drivers/gpu/drm/amd/display/dc/core/dc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index c4d59ad5fa9f4..8d25846534bee 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1431,6 +1431,7 @@ void dc_hardware_init(struct dc *dc) detect_edp_presence(dc); if (dc->ctx->dce_environment != DCE_ENV_VIRTUAL_HW) dc->hwss.init_hw(dc); + dc_dmub_srv_notify_fw_dc_power_state(dc->ctx->dmub_srv, DC_ACPI_CM_POWER_STATE_D0); } void dc_init_callbacks(struct dc *dc, From 5f39b8ecd0ceb7ce7a5520be6bfec0a14956093d Mon Sep 17 00:00:00 2001 From: Peterson Date: Mon, 23 Sep 2024 10:30:50 -0400 Subject: [PATCH 1795/1868] drm/amd/display: Fix low black values by increasing error [WHY] Regamma resolution for the first few black levels can have problems for calibration. [HOW] HW LUT is divided into N power-of-2 regions each with K segments. For SDR mode we set min point at 2^-10 and increments of 2^-13. It's generally more than 8-bit SDR needs, but some calibration tools and API use 12-bit curves. The fix shifts starting point to 2^-12 and starting increments at 2^-16. Reviewed-by: Krunoslav Kovac Signed-off-by: Peterson Signed-off-by: Rodrigo Siqueira Tested-by: Daniel Wheeler (cherry picked from commit d02bb5c032c37c43041c1072cbdf5285b3684bb6) Signed-off-by: Alex Hung --- .../amd/display/dc/dcn10/dcn10_cm_common.c | 25 ++++++++----------- .../amd/display/dc/dcn30/dcn30_cm_common.c | 25 ++++++++----------- 2 files changed, 20 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c index eaed5d1c398aa..dcd2cdfe91eb6 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c @@ -365,23 +365,18 @@ bool cm_helper_translate_curve_to_hw_format(struct dc_context *ctx, region_start = -MAX_LOW_POINT; region_end = NUMBER_REGIONS - MAX_LOW_POINT; } else { - /* 11 segments - * segment is from 2^-10 to 2^1 + /* 13 segments + * segment is from 2^-12 to 2^0 * There are less than 256 points, for optimization */ - seg_distr[0] = 3; - seg_distr[1] = 4; - seg_distr[2] = 4; - seg_distr[3] = 4; - seg_distr[4] = 4; - seg_distr[5] = 4; - seg_distr[6] = 4; - seg_distr[7] = 4; - seg_distr[8] = 4; - seg_distr[9] = 4; - seg_distr[10] = 1; - - region_start = -10; + const uint8_t SEG_COUNT = 12; + + for (i = 0; i < SEG_COUNT; i++) + seg_distr[i] = 4; + + seg_distr[SEG_COUNT] = 1; + + region_start = -SEG_COUNT; region_end = 1; } diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c index f31f0e3abfc0f..1e1038fb04e8d 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c +++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_cm_common.c @@ -140,23 +140,18 @@ bool cm3_helper_translate_curve_to_hw_format( region_start = -MAX_LOW_POINT; region_end = NUMBER_REGIONS - MAX_LOW_POINT; } else { - /* 11 segments - * segment is from 2^-10 to 2^0 + /* 13 segments + * segment is from 2^-12 to 2^0 * There are less than 256 points, for optimization */ - seg_distr[0] = 3; - seg_distr[1] = 4; - seg_distr[2] = 4; - seg_distr[3] = 4; - seg_distr[4] = 4; - seg_distr[5] = 4; - seg_distr[6] = 4; - seg_distr[7] = 4; - seg_distr[8] = 4; - seg_distr[9] = 4; - seg_distr[10] = 1; - - region_start = -10; + const uint8_t SEG_COUNT = 12; + + for (i = 0; i < SEG_COUNT; i++) + seg_distr[i] = 4; + + seg_distr[SEG_COUNT] = 1; + + region_start = -SEG_COUNT; region_end = 1; } From c07ec31bf143fac887d51a61300f15101c420a11 Mon Sep 17 00:00:00 2001 From: Dillon Varone Date: Thu, 26 Sep 2024 12:45:41 -0400 Subject: [PATCH 1796/1868] drm/amd/display: Remove programming outstanding updates for dcn35 [WHY&HOW] Programming outstanding updates is causing hangs on dcn35, so remove for now. Reviewed-by: Martin Leung Signed-off-by: Dillon Varone Signed-off-by: Rodrigo Siqueira Tested-by: Daniel Wheeler (cherry picked from commit ab9318ea1aacce1c9467b15afd36ec2d743ffc39) Signed-off-by: Alex Hung --- drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c | 1 - drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c | 1 - 2 files changed, 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c index 2bbf1fef94fd2..55dc5799e725a 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_init.c @@ -123,7 +123,6 @@ static const struct hw_sequencer_funcs dcn35_funcs = { .root_clock_control = dcn35_root_clock_control, .set_long_vtotal = dcn35_set_long_vblank, .calculate_pix_rate_divider = dcn32_calculate_pix_rate_divider, - .program_outstanding_updates = dcn32_program_outstanding_updates, }; static const struct hwseq_private_funcs dcn35_private_funcs = { diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c index d00822e8daa52..a93864b63d48f 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn351/dcn351_init.c @@ -122,7 +122,6 @@ static const struct hw_sequencer_funcs dcn351_funcs = { .root_clock_control = dcn35_root_clock_control, .set_long_vtotal = dcn35_set_long_vblank, .calculate_pix_rate_divider = dcn32_calculate_pix_rate_divider, - .program_outstanding_updates = dcn32_program_outstanding_updates, .setup_hpo_hw_control = dcn35_setup_hpo_hw_control, }; From 15596eda181ad8ffc87aeb1408f0140cde5e9f67 Mon Sep 17 00:00:00 2001 From: Charlene Liu Date: Wed, 25 Sep 2024 20:57:00 -0400 Subject: [PATCH 1797/1868] drm/amd/display: update sr_exit latency for z8 This is based on real asic performance result. Reviewed-by: Alvin Lee Signed-off-by: Charlene Liu Signed-off-by: Rodrigo Siqueira Tested-by: Daniel Wheeler (cherry picked from commit d2392e45c238c945501c6dbaec06032834f52b84) Signed-off-by: Alex Hung --- drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c index a201dbb743d79..d9e63c4fdd95c 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn351/dcn351_fpu.c @@ -204,8 +204,8 @@ struct _vcs_dpi_soc_bounding_box_st dcn3_51_soc = { .num_states = 8, .sr_exit_time_us = 28.0, .sr_enter_plus_exit_time_us = 30.0, - .sr_exit_z8_time_us = 250.0, - .sr_enter_plus_exit_z8_time_us = 350.0, + .sr_exit_z8_time_us = 263.0, + .sr_enter_plus_exit_z8_time_us = 363.0, .fclk_change_latency_us = 24.0, .usr_retraining_latency_us = 2, .writeback_latency_us = 12.0, From 033e39a4a197cf55b02cd8f644953115397235ef Mon Sep 17 00:00:00 2001 From: Josip Pavic Date: Tue, 24 Sep 2024 17:25:54 -0400 Subject: [PATCH 1798/1868] drm/amd/display: Clear update flags after update has been applied [Why] Since the surface/stream update flags aren't cleared after applying updates, those same updates may be applied again in a future call to update surfaces/streams for surfaces/streams that aren't actually part of that update (i.e. applying an update for one surface/stream can trigger unintended programming on a different surface/stream). For example, when an update results in a call to program_front_end_for_ctx, that function may call program_pipe on all pipes. If there are surface update flags that were never cleared on the surface some pipe is attached to, then the same update will be programmed again. [How] Clear the surface and stream update flags after applying the updates. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/3441 Cc: stable@vger.kernel.org Cc: Melissa Wen Reviewed-by: Aric Cyr Signed-off-by: Josip Pavic Signed-off-by: Rodrigo Siqueira Tested-by: Daniel Wheeler (cherry picked from commit 5b5900507b77f7f6fbfba5cdb286e76b463a86ad) Signed-off-by: Alex Hung --- drivers/gpu/drm/amd/display/dc/core/dc.c | 45 ++++++++++++++++++------ 1 file changed, 34 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 8d25846534bee..5c73b7de1697b 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -5130,11 +5130,26 @@ static bool update_planes_and_stream_v3(struct dc *dc, return true; } +static void clear_update_flags(struct dc_surface_update *srf_updates, + int surface_count, struct dc_stream_state *stream) +{ + int i; + + if (stream) + stream->update_flags.raw = 0; + + for (i = 0; i < surface_count; i++) + if (srf_updates[i].surface) + srf_updates[i].surface->update_flags.raw = 0; +} + bool dc_update_planes_and_stream(struct dc *dc, struct dc_surface_update *srf_updates, int surface_count, struct dc_stream_state *stream, struct dc_stream_update *stream_update) { + bool ret = false; + dc_exit_ips_for_hw_access(dc); /* * update planes and stream version 3 separates FULL and FAST updates @@ -5151,10 +5166,16 @@ bool dc_update_planes_and_stream(struct dc *dc, * features as they are now transparent to the new sequence. */ if (dc->ctx->dce_version >= DCN_VERSION_4_01) - return update_planes_and_stream_v3(dc, srf_updates, + ret = update_planes_and_stream_v3(dc, srf_updates, surface_count, stream, stream_update); - return update_planes_and_stream_v2(dc, srf_updates, + else + ret = update_planes_and_stream_v2(dc, srf_updates, surface_count, stream, stream_update); + + if (ret) + clear_update_flags(srf_updates, surface_count, stream); + + return ret; } void dc_commit_updates_for_stream(struct dc *dc, @@ -5164,6 +5185,8 @@ void dc_commit_updates_for_stream(struct dc *dc, struct dc_stream_update *stream_update, struct dc_state *state) { + bool ret = false; + dc_exit_ips_for_hw_access(dc); /* TODO: Since change commit sequence can have a huge impact, * we decided to only enable it for DCN3x. However, as soon as @@ -5171,17 +5194,17 @@ void dc_commit_updates_for_stream(struct dc *dc, * the new sequence for all ASICs. */ if (dc->ctx->dce_version >= DCN_VERSION_4_01) { - update_planes_and_stream_v3(dc, srf_updates, surface_count, + ret = update_planes_and_stream_v3(dc, srf_updates, surface_count, stream, stream_update); - return; - } - if (dc->ctx->dce_version >= DCN_VERSION_3_2) { - update_planes_and_stream_v2(dc, srf_updates, surface_count, + } else if (dc->ctx->dce_version >= DCN_VERSION_3_2) { + ret = update_planes_and_stream_v2(dc, srf_updates, surface_count, stream, stream_update); - return; - } - update_planes_and_stream_v1(dc, srf_updates, surface_count, stream, - stream_update, state); + } else + ret = update_planes_and_stream_v1(dc, srf_updates, surface_count, stream, + stream_update, state); + + if (ret) + clear_update_flags(srf_updates, surface_count, stream); } uint8_t dc_get_current_stream_count(struct dc *dc) From 60c1db389cea7c909c1542931bf4f5fd9840eeda Mon Sep 17 00:00:00 2001 From: Aurabindo Pillai Date: Mon, 23 Sep 2024 20:07:25 +0000 Subject: [PATCH 1799/1868] drm/amd/display: fix a memleak issue when driver is removed Running "modprobe amdgpu" the second time (followed by a modprobe -r amdgpu) causes a call trace like: [ 845.212163] Memory manager not clean during takedown. [ 845.212170] WARNING: CPU: 4 PID: 2481 at drivers/gpu/drm/drm_mm.c:999 drm_mm_takedown+0x2b/0x40 [ 845.212177] Modules linked in: amdgpu(OE-) amddrm_ttm_helper(OE) amddrm_buddy(OE) amdxcp(OE) amd_sched(OE) drm_exec drm_suballoc_helper drm_display_helper i2c_algo_bit amdttm(OE) amdkcl(OE) cec rc_core sunrpc qrtr intel_rapl_msr intel_rapl_common snd_hda_codec_hdmi edac_mce_amd snd_hda_intel snd_intel_dspcfg snd_intel_sdw_acpi snd_usb_audio snd_hda_codec snd_usbmidi_lib kvm_amd snd_hda_core snd_ump mc snd_hwdep kvm snd_pcm snd_seq_midi snd_seq_midi_event irqbypass crct10dif_pclmul snd_rawmidi polyval_clmulni polyval_generic ghash_clmulni_intel sha256_ssse3 sha1_ssse3 snd_seq aesni_intel crypto_simd snd_seq_device cryptd snd_timer mfd_aaeon asus_nb_wmi eeepc_wmi joydev asus_wmi snd ledtrig_audio sparse_keymap ccp wmi_bmof input_leds k10temp i2c_piix4 platform_profile rapl soundcore gpio_amdpt mac_hid binfmt_misc msr parport_pc ppdev lp parport efi_pstore nfnetlink dmi_sysfs ip_tables x_tables autofs4 hid_logitech_hidpp hid_logitech_dj hid_generic usbhid hid ahci xhci_pci igc crc32_pclmul libahci xhci_pci_renesas video [ 845.212284] wmi [last unloaded: amddrm_ttm_helper(OE)] [ 845.212290] CPU: 4 PID: 2481 Comm: modprobe Tainted: G W OE 6.8.0-31-generic #31-Ubuntu [ 845.212296] RIP: 0010:drm_mm_takedown+0x2b/0x40 [ 845.212300] Code: 1f 44 00 00 48 8b 47 38 48 83 c7 38 48 39 f8 75 09 31 c0 31 ff e9 90 2e 86 00 55 48 c7 c7 d0 f6 8e 8a 48 89 e5 e8 f5 db 45 ff <0f> 0b 5d 31 c0 31 ff e9 74 2e 86 00 66 0f 1f 84 00 00 00 00 00 90 [ 845.212302] RSP: 0018:ffffb11302127ae0 EFLAGS: 00010246 [ 845.212305] RAX: 0000000000000000 RBX: ffff92aa5020fc08 RCX: 0000000000000000 [ 845.212307] RDX: 0000000000000000 RSI: 0000000000000000 RDI: 0000000000000000 [ 845.212309] RBP: ffffb11302127ae0 R08: 0000000000000000 R09: 0000000000000000 [ 845.212310] R10: 0000000000000000 R11: 0000000000000000 R12: 0000000000000004 [ 845.212312] R13: ffff92aa50200000 R14: ffff92aa5020fb10 R15: ffff92aa5020faa0 [ 845.212313] FS: 0000707dd7c7c080(0000) GS:ffff92b93de00000(0000) knlGS:0000000000000000 [ 845.212316] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 845.212318] CR2: 00007d48b0aee200 CR3: 0000000115a58000 CR4: 0000000000f50ef0 [ 845.212320] PKRU: 55555554 [ 845.212321] Call Trace: [ 845.212323] [ 845.212328] ? show_regs+0x6d/0x80 [ 845.212333] ? __warn+0x89/0x160 [ 845.212339] ? drm_mm_takedown+0x2b/0x40 [ 845.212344] ? report_bug+0x17e/0x1b0 [ 845.212350] ? handle_bug+0x51/0xa0 [ 845.212355] ? exc_invalid_op+0x18/0x80 [ 845.212359] ? asm_exc_invalid_op+0x1b/0x20 [ 845.212366] ? drm_mm_takedown+0x2b/0x40 [ 845.212371] amdgpu_gtt_mgr_fini+0xa9/0x130 [amdgpu] [ 845.212645] amdgpu_ttm_fini+0x264/0x340 [amdgpu] [ 845.212770] amdgpu_bo_fini+0x2e/0xc0 [amdgpu] [ 845.212894] gmc_v12_0_sw_fini+0x2a/0x40 [amdgpu] [ 845.213036] amdgpu_device_fini_sw+0x11a/0x590 [amdgpu] [ 845.213159] amdgpu_driver_release_kms+0x16/0x40 [amdgpu] [ 845.213302] devm_drm_dev_init_release+0x5e/0x90 [ 845.213305] devm_action_release+0x12/0x30 [ 845.213308] release_nodes+0x42/0xd0 [ 845.213311] devres_release_all+0x97/0xe0 [ 845.213314] device_unbind_cleanup+0x12/0x80 [ 845.213317] device_release_driver_internal+0x230/0x270 [ 845.213319] ? srso_alias_return_thunk+0x5/0xfbef5 This is caused by lost memory during early init phase. First time driver is removed, memory is freed but when second time the driver is inserted, VBIOS dmub is not active, since the PSP policy is to retain the driver loaded version on subsequent warm boots. Hence, communication with VBIOS DMUB fails. Fix this by aborting further communication with vbios dmub and release the memory immediately. Fixes: 3284f08a2324 ("drm/amd/display: free bo used for dmub bounding box") Reviewed-by: Rodrigo Siqueira Signed-off-by: Aurabindo Pillai Signed-off-by: Rodrigo Siqueira Tested-by: Daniel Wheeler (cherry picked from commit 278a268a1234c8284c55c09d71f356e777d7668a) Signed-off-by: Alex Hung --- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 32 ++++++++++++++++--- .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h | 3 ++ .../amd/display/amdgpu_dm/amdgpu_dm_helpers.c | 13 ++------ 3 files changed, 33 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index d9bcf0ba06ad0..8d85badafbceb 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1708,6 +1708,26 @@ dm_allocate_gpu_mem( return da->cpu_ptr; } +void +dm_free_gpu_mem( + struct amdgpu_device *adev, + enum dc_gpu_mem_alloc_type type, + void *pvMem) +{ + struct dal_allocation *da; + + /* walk the da list in DM */ + list_for_each_entry(da, &adev->dm.da_list, list) { + if (pvMem == da->cpu_ptr) { + amdgpu_bo_free_kernel(&da->bo, &da->gpu_addr, &da->cpu_ptr); + list_del(&da->list); + kfree(da); + break; + } + } + +} + static enum dmub_status dm_dmub_send_vbios_gpint_command(struct amdgpu_device *adev, enum dmub_gpint_command command_code, @@ -1774,16 +1794,20 @@ static struct dml2_soc_bb *dm_dmub_get_vbios_bounding_box(struct amdgpu_device * /* Send the chunk */ ret = dm_dmub_send_vbios_gpint_command(adev, send_addrs[i], chunk, 30000); if (ret != DMUB_STATUS_OK) - /* No need to free bb here since it shall be done in dm_sw_fini() */ - return NULL; + goto free_bb; } /* Now ask DMUB to copy the bb */ ret = dm_dmub_send_vbios_gpint_command(adev, DMUB_GPINT__BB_COPY, 1, 200000); if (ret != DMUB_STATUS_OK) - return NULL; + goto free_bb; return bb; + +free_bb: + dm_free_gpu_mem(adev, DC_MEM_ALLOC_TYPE_GART, (void *) bb); + return NULL; + } static enum dmub_ips_disable_type dm_get_default_ips_mode( @@ -2573,11 +2597,11 @@ static int dm_sw_fini(struct amdgpu_ip_block *ip_block) amdgpu_bo_free_kernel(&da->bo, &da->gpu_addr, &da->cpu_ptr); list_del(&da->list); kfree(da); + adev->dm.bb_from_dmub = NULL; break; } } - adev->dm.bb_from_dmub = NULL; kfree(adev->dm.dmub_fb_info); adev->dm.dmub_fb_info = NULL; diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h index 9fe06a6290a9f..45f63822e7847 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h @@ -1017,6 +1017,9 @@ void *dm_allocate_gpu_mem(struct amdgpu_device *adev, enum dc_gpu_mem_alloc_type type, size_t size, long long *addr); +void dm_free_gpu_mem(struct amdgpu_device *adev, + enum dc_gpu_mem_alloc_type type, + void *addr); bool amdgpu_dm_is_headless(struct amdgpu_device *adev); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c index 2379d40c3121f..8f58dbb28ee39 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_helpers.c @@ -1291,17 +1291,8 @@ void dm_helpers_free_gpu_mem( void *pvMem) { struct amdgpu_device *adev = ctx->driver_context; - struct dal_allocation *da; - - /* walk the da list in DM */ - list_for_each_entry(da, &adev->dm.da_list, list) { - if (pvMem == da->cpu_ptr) { - amdgpu_bo_free_kernel(&da->bo, &da->gpu_addr, &da->cpu_ptr); - list_del(&da->list); - kfree(da); - break; - } - } + + dm_free_gpu_mem(adev, type, pvMem); } bool dm_helpers_dmub_outbox_interrupt_control(struct dc_context *ctx, bool enable) From ecbb9f4806a8bb98c0c2fd8fe7c457a463c63fb6 Mon Sep 17 00:00:00 2001 From: Yihan Zhu Date: Thu, 26 Sep 2024 09:49:25 -0400 Subject: [PATCH 1800/1868] drm/amd/display: calculate final viewport before TAP optimization Viewport size excess surface size observed sometime with some timings or resizing the MPO video window to cause MPO unsupported. Calculate final viewport size first with a 100x100 dummy viewport to get the max TAP support and then re-run final viewport calculation if TAP value changed. Removed obsolete preliminary viewport calculation for TAP validation. Reviewed-by: Dmytro Laktyushkin Signed-off-by: Yihan Zhu Signed-off-by: Rodrigo Siqueira Tested-by: Daniel Wheeler (cherry picked from commit aaa8fcd374c1fd119e7410f32710c0964de294a8) Signed-off-by: Alex Hung --- .../gpu/drm/amd/display/dc/core/dc_resource.c | 49 +++++++++---------- 1 file changed, 23 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index c7599c40d4be3..df513dbd32bdf 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -765,25 +765,6 @@ static inline void get_vp_scan_direction( *flip_horz_scan_dir = !*flip_horz_scan_dir; } -/* - * This is a preliminary vp size calculation to allow us to check taps support. - * The result is completely overridden afterwards. - */ -static void calculate_viewport_size(struct pipe_ctx *pipe_ctx) -{ - struct scaler_data *data = &pipe_ctx->plane_res.scl_data; - - data->viewport.width = dc_fixpt_ceil(dc_fixpt_mul_int(data->ratios.horz, data->recout.width)); - data->viewport.height = dc_fixpt_ceil(dc_fixpt_mul_int(data->ratios.vert, data->recout.height)); - data->viewport_c.width = dc_fixpt_ceil(dc_fixpt_mul_int(data->ratios.horz_c, data->recout.width)); - data->viewport_c.height = dc_fixpt_ceil(dc_fixpt_mul_int(data->ratios.vert_c, data->recout.height)); - if (pipe_ctx->plane_state->rotation == ROTATION_ANGLE_90 || - pipe_ctx->plane_state->rotation == ROTATION_ANGLE_270) { - swap(data->viewport.width, data->viewport.height); - swap(data->viewport_c.width, data->viewport_c.height); - } -} - static struct rect intersect_rec(const struct rect *r0, const struct rect *r1) { struct rect rec; @@ -1468,6 +1449,7 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) const struct dc_plane_state *plane_state = pipe_ctx->plane_state; struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; const struct rect odm_slice_src = resource_get_odm_slice_src_rect(pipe_ctx); + struct scaling_taps temp = {0}; bool res = false; DC_LOGGER_INIT(pipe_ctx->stream->ctx->logger); @@ -1525,8 +1507,6 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) calculate_recout(pipe_ctx); /* depends on pixel format */ calculate_scaling_ratios(pipe_ctx); - /* depends on scaling ratios and recout, does not calculate offset yet */ - calculate_viewport_size(pipe_ctx); /* * LB calculations depend on vp size, h/v_active and scaling ratios @@ -1547,6 +1527,24 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) pipe_ctx->plane_res.scl_data.lb_params.alpha_en = plane_state->per_pixel_alpha; + // get TAP value with 100x100 dummy data for max scaling qualify, override + // if a new scaling quality required + pipe_ctx->plane_res.scl_data.viewport.width = 100; + pipe_ctx->plane_res.scl_data.viewport.height = 100; + pipe_ctx->plane_res.scl_data.viewport_c.width = 100; + pipe_ctx->plane_res.scl_data.viewport_c.height = 100; + if (pipe_ctx->plane_res.xfm != NULL) + res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps( + pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality); + + if (pipe_ctx->plane_res.dpp != NULL) + res = pipe_ctx->plane_res.dpp->funcs->dpp_get_optimal_number_of_taps( + pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality); + + temp = pipe_ctx->plane_res.scl_data.taps; + + calculate_inits_and_viewports(pipe_ctx); + if (pipe_ctx->plane_res.xfm != NULL) res = pipe_ctx->plane_res.xfm->funcs->transform_get_optimal_number_of_taps( pipe_ctx->plane_res.xfm, &pipe_ctx->plane_res.scl_data, &plane_state->scaling_quality); @@ -1573,11 +1571,10 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx) &plane_state->scaling_quality); } - /* - * Depends on recout, scaling ratios, h_active and taps - * May need to re-check lb size after this in some obscure scenario - */ - if (res) + if (res && (pipe_ctx->plane_res.scl_data.taps.v_taps != temp.v_taps || + pipe_ctx->plane_res.scl_data.taps.h_taps != temp.h_taps || + pipe_ctx->plane_res.scl_data.taps.v_taps_c != temp.v_taps_c || + pipe_ctx->plane_res.scl_data.taps.h_taps_c != temp.h_taps_c)) calculate_inits_and_viewports(pipe_ctx); /* From 706a1005ee67a4c42cfa81b659b38dde682241c9 Mon Sep 17 00:00:00 2001 From: Roman Li Date: Thu, 26 Sep 2024 16:36:15 -0400 Subject: [PATCH 1801/1868] drm/amd/display: Align static screen idle worker with IPX mode [Why] Idle worker thread serves for periodic detection of HPD while system is in IPS2. Currently it is used in headless and static screen scenarios. IPX can be configured not to execute IPS2 for static screen. In this case idle worker is redundant. [How] Only use periodic detection for static screen if IPS is fully enabled. Reviewed-by: Sun peng Li Signed-off-by: Roman Li Signed-off-by: Rodrigo Siqueira Tested-by: Daniel Wheeler (cherry picked from commit ed991bfdaad3c6e37ac2b43fb65d11acddde775f) Signed-off-by: Alex Hung --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c index cc86f8fb5b0a8..ce3bb6eee157e 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c @@ -154,6 +154,7 @@ static void amdgpu_dm_crtc_set_panel_sr_feature( amdgpu_dm_psr_enable(vblank_work->stream); if (dm->idle_workqueue && + (dm->dc->config.disable_ips == DMUB_IPS_ENABLE) && dm->dc->idle_optimizations_allowed && dm->idle_workqueue->enable && !dm->idle_workqueue->running) From 8a9f5deeebd3957ada1bad950729e49cc358d595 Mon Sep 17 00:00:00 2001 From: Fangzhi Zuo Date: Mon, 23 Sep 2024 16:20:40 -0400 Subject: [PATCH 1802/1868] drm/amd/display: Skip Invalid Streams from DSC Policy Streams with invalid new connector state should be elimiated from dsc policy. Reviewed-by: Aurabindo Pillai Signed-off-by: Fangzhi Zuo Signed-off-by: Rodrigo Siqueira Tested-by: Daniel Wheeler (cherry picked from commit ac0303129a081d6825b3f6a436e23ada197056af) Signed-off-by: Alex Hung --- .../drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c index f4214dc372da3..dd7117db38479 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c @@ -1341,6 +1341,7 @@ static int compute_mst_dsc_configs_for_link(struct drm_atomic_state *state, int i, k, ret; bool debugfs_overwrite = false; uint16_t fec_overhead_multiplier_x1000 = get_fec_overhead_multiplier(dc_link); + struct drm_connector_state *new_conn_state; memset(params, 0, sizeof(params)); @@ -1348,7 +1349,7 @@ static int compute_mst_dsc_configs_for_link(struct drm_atomic_state *state, return PTR_ERR(mst_state); /* Set up params */ - DRM_DEBUG_DRIVER("%s: MST_DSC Set up params for %d streams\n", __func__, dc_state->stream_count); + DRM_DEBUG_DRIVER("%s: MST_DSC Try to set up params from %d streams\n", __func__, dc_state->stream_count); for (i = 0; i < dc_state->stream_count; i++) { struct dc_dsc_policy dsc_policy = {0}; @@ -1364,6 +1365,14 @@ static int compute_mst_dsc_configs_for_link(struct drm_atomic_state *state, if (!aconnector->mst_output_port) continue; + new_conn_state = drm_atomic_get_new_connector_state(state, &aconnector->base); + + if (!new_conn_state) { + DRM_DEBUG_DRIVER("%s:%d MST_DSC Skip the stream 0x%p with invalid new_conn_state\n", + __func__, __LINE__, stream); + continue; + } + stream->timing.flags.DSC = 0; params[count].timing = &stream->timing; @@ -1396,6 +1405,8 @@ static int compute_mst_dsc_configs_for_link(struct drm_atomic_state *state, count++; } + DRM_DEBUG_DRIVER("%s: MST_DSC Params set up for %d streams\n", __func__, count); + if (count == 0) { ASSERT(0); return 0; From 8a72617b56860a39093d323071a584befdaa1254 Mon Sep 17 00:00:00 2001 From: Austin Zheng Date: Thu, 26 Sep 2024 16:18:10 -0400 Subject: [PATCH 1803/1868] drm/amd/display: Allow Latency Increase For Last Strategy [Why] Playing 1080p video on 4k60 timing uses UCLK DPM5 and mode support determines that p-state switching is not supported. [How] Allow DML to increase latency as the last strategy so strategies such as VBlank p-state switching may become possible Reviewed-by: Alvin Lee Signed-off-by: Austin Zheng Signed-off-by: Rodrigo Siqueira Tested-by: Daniel Wheeler (cherry picked from commit d8b8b61780adcbb0c21f9818f55ed62c05fe6805) Signed-off-by: Alex Hung --- .../amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c index 1cf9015e854a9..5a09dd298e6f3 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c @@ -1798,6 +1798,7 @@ bool pmo_dcn4_fams2_init_for_pstate_support(struct dml2_pmo_init_for_pstate_supp } if (s->pmo_dcn4.num_pstate_candidates > 0) { + s->pmo_dcn4.pstate_strategy_candidates[s->pmo_dcn4.num_pstate_candidates - 1].allow_state_increase = true; s->pmo_dcn4.cur_pstate_candidate = -1; return true; } else { From efe804c5db64cd6ea17d34020e5373705a936440 Mon Sep 17 00:00:00 2001 From: Austin Zheng Date: Thu, 26 Sep 2024 16:53:17 -0400 Subject: [PATCH 1804/1868] drm/amd/display: Move Link Encoder Assignment Out Of dc_global_validate Assigning link encoder is not relevant to validating bandwidth so move the logic outside of dc_global_validate. Reviewed-by: Alvin Lee Signed-off-by: Austin Zheng Signed-off-by: Rodrigo Siqueira Tested-by: Daniel Wheeler (cherry picked from commit e5c89c3e7142318e24d9208e21613b5861da77d6) Signed-off-by: Alex Hung --- drivers/gpu/drm/amd/display/dc/core/dc.c | 8 ++++++++ drivers/gpu/drm/amd/display/dc/core/dc_resource.c | 8 -------- 2 files changed, 8 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 5c73b7de1697b..4488736e7a039 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -2187,6 +2187,14 @@ enum dc_status dc_commit_streams(struct dc *dc, struct dc_commit_streams_params context->power_source = params->power_source; res = dc_validate_with_context(dc, set, params->stream_count, context, false); + + /* + * Only update link encoder to stream assignment after bandwidth validation passed. + */ + if (res == DC_OK && dc->res_pool->funcs->link_encs_assign) + dc->res_pool->funcs->link_encs_assign( + dc, context, context->streams, context->stream_count); + if (res != DC_OK) { BREAK_TO_DEBUGGER(); goto fail; diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c index df513dbd32bdf..33125b95c3a13 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c @@ -4091,14 +4091,6 @@ enum dc_status dc_validate_global_state( if (!dc->res_pool->funcs->validate_bandwidth(dc, new_ctx, fast_validate)) result = DC_FAIL_BANDWIDTH_VALIDATE; - /* - * Only update link encoder to stream assignment after bandwidth validation passed. - * TODO: Split out assignment and validation. - */ - if (result == DC_OK && dc->res_pool->funcs->link_encs_assign && fast_validate == false) - dc->res_pool->funcs->link_encs_assign( - dc, new_ctx, new_ctx->streams, new_ctx->stream_count); - return result; } From 67e41db52cfc5a3082578e590947848ea2ae896d Mon Sep 17 00:00:00 2001 From: Austin Zheng Date: Tue, 10 Sep 2024 16:41:20 -0400 Subject: [PATCH 1805/1868] drm/amd/display: Update Interface to Check UCLK DPM [Why] Videos using YUV420 format may result in high power being used. Disabling MPO may result in lower power usage. Update interface that can be used to check power profile of a dc_state. [How] Add helper functions that can be used to determine power level: - get power profile after a dc_state has undergone full validation Reviewed-by: Alvin Lee Signed-off-by: Austin Zheng Signed-off-by: Rodrigo Siqueira Tested-by: Daniel Wheeler (cherry picked from commit fc8c959496fa88a3d8d7480469b2c2ee0f915095) Signed-off-by: Alex Hung --- drivers/gpu/drm/amd/display/dc/core/dc.c | 7 ++++++- drivers/gpu/drm/amd/display/dc/inc/core_types.h | 4 ++++ .../dc/resource/dcn315/dcn315_resource.c | 6 ++++++ .../dc/resource/dcn401/dcn401_resource.c | 17 +++++++++++++++++ 4 files changed, 33 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 4488736e7a039..11d1153ae9fdf 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -6072,7 +6072,12 @@ struct dc_power_profile dc_get_power_profile_for_dc_state(const struct dc_state { struct dc_power_profile profile = { 0 }; - profile.power_level += !context->bw_ctx.bw.dcn.clk.p_state_change_support; + if (!context || !context->clk_mgr || !context->clk_mgr->ctx || !context->clk_mgr->ctx->dc) + return profile; + struct dc *dc = context->clk_mgr->ctx->dc; + + if (dc->res_pool->funcs->get_power_profile) + profile.power_level = dc->res_pool->funcs->get_power_profile(context); return profile; } diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index 805b25676734e..7de2dc933a098 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -214,6 +214,10 @@ struct resource_funcs { void (*get_panel_config_defaults)(struct dc_panel_config *panel_config); void (*build_pipe_pix_clk_params)(struct pipe_ctx *pipe_ctx); + /* + * Get indicator of power from a context that went through full validation + */ + int (*get_power_profile)(const struct dc_state *context); }; struct audio_support{ diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c index 3f4b9dba41124..f6b840f046a5d 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c @@ -1812,6 +1812,11 @@ static void dcn315_get_panel_config_defaults(struct dc_panel_config *panel_confi *panel_config = panel_config_defaults; } +static int dcn315_get_power_profile(const struct dc_state *context) +{ + return !context->bw_ctx.bw.dcn.clk.p_state_change_support; +} + static struct dc_cap_funcs cap_funcs = { .get_dcc_compression_cap = dcn20_get_dcc_compression_cap }; @@ -1840,6 +1845,7 @@ static struct resource_funcs dcn315_res_pool_funcs = { .update_bw_bounding_box = dcn315_update_bw_bounding_box, .patch_unknown_plane_state = dcn20_patch_unknown_plane_state, .get_panel_config_defaults = dcn315_get_panel_config_defaults, + .get_power_profile = dcn315_get_power_profile, }; static bool dcn315_resource_construct( diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c index f2653a86d3e7d..59184abab1a70 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c @@ -1688,6 +1688,22 @@ static void dcn401_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx) } } +static int dcn401_get_power_profile(const struct dc_state *context) +{ + int uclk_mhz = context->bw_ctx.bw.dcn.clk.dramclk_khz / 1000; + int dpm_level = 0; + + for (int i = 0; i < context->clk_mgr->bw_params->clk_table.num_entries_per_clk.num_memclk_levels; i++) { + if (context->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz == 0 || + uclk_mhz < context->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz) + break; + if (uclk_mhz > context->clk_mgr->bw_params->clk_table.entries[i].memclk_mhz) + dpm_level++; + } + + return dpm_level; +} + static struct resource_funcs dcn401_res_pool_funcs = { .destroy = dcn401_destroy_resource_pool, .link_enc_create = dcn401_link_encoder_create, @@ -1714,6 +1730,7 @@ static struct resource_funcs dcn401_res_pool_funcs = { .prepare_mcache_programming = dcn401_prepare_mcache_programming, .build_pipe_pix_clk_params = dcn401_build_pipe_pix_clk_params, .calculate_mall_ways_from_bytes = dcn32_calculate_mall_ways_from_bytes, + .get_power_profile = dcn401_get_power_profile, }; static uint32_t read_pipe_fuses(struct dc_context *ctx) From 882949990d8f3589e198edbeff747acb752ee3e6 Mon Sep 17 00:00:00 2001 From: Taimur Hassan Date: Sun, 29 Sep 2024 00:21:23 -0400 Subject: [PATCH 1806/1868] drm/amd/display: Add DMUB debug offset Add DMUB offset for future use. Signed-off-by: Taimur Hassan Acked-by: Rodrigo Siqueira Signed-off-by: Rodrigo Siqueira Tested-by: Daniel Wheeler (cherry picked from commit 5ba9c88b4d049abebb6062010becc44cf748c2bb) Signed-off-by: Alex Hung --- drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index 05d352c7b1d3c..f9e82c4f8deb6 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -170,6 +170,11 @@ #pragma pack(push, 1) #define ABM_NUM_OF_ACE_SEGMENTS 5 +/** + * Debug FW state offset + */ +#define DMUB_DEBUG_FW_STATE_OFFSET 0x300 + union abm_flags { struct { /** From f0f1568a56471e63eb3d56daf0f4905304cd4313 Mon Sep 17 00:00:00 2001 From: Alex Hung Date: Mon, 23 Sep 2024 14:24:49 -0600 Subject: [PATCH 1807/1868] drm/amd/display: Remove unnecessary assignments [WHAT & HOW] TimeForFetchingMetaPTE, TimeForFetchingRowInVBlank and LinesToRequestPrefetchPixelData are local variables. They are freed when CalculatePrefetchSchedule() ends and need not clearing explicitly. This fixes 21 UNUSED_VALUE issues reported by Coverity. Reviewed-by: Nevenko Stupar Signed-off-by: Alex Hung Signed-off-by: Rodrigo Siqueira Tested-by: Daniel Wheeler (cherry picked from commit 1b08a04a6f8d2ab98814791b5fd686fc96543c8d) Signed-off-by: Alex Hung --- drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c | 3 --- .../gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c | 3 --- drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c | 3 --- drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c | 3 --- drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c | 3 --- .../gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c | 3 --- .../drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c | 3 --- 7 files changed, 21 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c index 565f3c4924770..0c8c4a080c50e 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20.c @@ -785,12 +785,9 @@ static bool CalculatePrefetchSchedule( if (MyError) { *PrefetchBandwidth = 0; - TimeForFetchingMetaPTE = 0; - TimeForFetchingRowInVBlank = 0; *DestinationLinesToRequestVMInVBlank = 0; *DestinationLinesToRequestRowInVBlank = 0; *DestinationLinesForPrefetch = 0; - LinesToRequestPrefetchPixelData = 0; *VRatioPrefetchY = 0; *VRatioPrefetchC = 0; *RequiredPrefetchPixDataBW = 0; diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c index 9d6675ecc5f11..c935903b68e10 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_mode_vba_20v2.c @@ -845,12 +845,9 @@ static bool CalculatePrefetchSchedule( if (MyError) { *PrefetchBandwidth = 0; - TimeForFetchingMetaPTE = 0; - TimeForFetchingRowInVBlank = 0; *DestinationLinesToRequestVMInVBlank = 0; *DestinationLinesToRequestRowInVBlank = 0; *DestinationLinesForPrefetch = 0; - LinesToRequestPrefetchPixelData = 0; *VRatioPrefetchY = 0; *VRatioPrefetchC = 0; *RequiredPrefetchPixDataBW = 0; diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c index eb3ed965e48b7..cd8cca6514196 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_mode_vba_21.c @@ -1049,12 +1049,9 @@ static bool CalculatePrefetchSchedule( if (MyError) { *PrefetchBandwidth = 0; - TimeForFetchingMetaPTE = 0; - TimeForFetchingRowInVBlank = 0; *DestinationLinesToRequestVMInVBlank = 0; *DestinationLinesToRequestRowInVBlank = 0; *DestinationLinesForPrefetch = 0; - LinesToRequestPrefetchPixelData = 0; *VRatioPrefetchY = 0; *VRatioPrefetchC = 0; *RequiredPrefetchPixDataBWLuma = 0; diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c index 4822fad6ce3a1..cee1b351e1058 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_mode_vba_30.c @@ -1280,12 +1280,9 @@ static bool CalculatePrefetchSchedule( if (MyError) { *PrefetchBandwidth = 0; - TimeForFetchingMetaPTE = 0; - TimeForFetchingRowInVBlank = 0; *DestinationLinesToRequestVMInVBlank = 0; *DestinationLinesToRequestRowInVBlank = 0; *DestinationLinesForPrefetch = 0; - LinesToRequestPrefetchPixelData = 0; *VRatioPrefetchY = 0; *VRatioPrefetchC = 0; *RequiredPrefetchPixDataBWLuma = 0; diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c index 2b275e6803797..f567a9023682d 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c @@ -1444,12 +1444,9 @@ static bool CalculatePrefetchSchedule( if (MyError) { *PrefetchBandwidth = 0; - TimeForFetchingMetaPTE = 0; - TimeForFetchingRowInVBlank = 0; *DestinationLinesToRequestVMInVBlank = 0; *DestinationLinesToRequestRowInVBlank = 0; *DestinationLinesForPrefetch = 0; - LinesToRequestPrefetchPixelData = 0; *VRatioPrefetchY = 0; *VRatioPrefetchC = 0; *RequiredPrefetchPixDataBWLuma = 0; diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c index debfa31583a69..5865e8fa2d8e8 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_mode_vba_314.c @@ -1461,12 +1461,9 @@ static bool CalculatePrefetchSchedule( if (MyError) { *PrefetchBandwidth = 0; - TimeForFetchingMetaPTE = 0; - TimeForFetchingRowInVBlank = 0; *DestinationLinesToRequestVMInVBlank = 0; *DestinationLinesToRequestRowInVBlank = 0; *DestinationLinesForPrefetch = 0; - LinesToRequestPrefetchPixelData = 0; *VRatioPrefetchY = 0; *VRatioPrefetchC = 0; *RequiredPrefetchPixDataBWLuma = 0; diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c index d92fb428ee96f..86ac7d59fd325 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/display_mode_vba_util_32.c @@ -4097,12 +4097,9 @@ bool dml32_CalculatePrefetchSchedule( if (MyError) { *PrefetchBandwidth = 0; - TimeForFetchingMetaPTE = 0; - TimeForFetchingRowInVBlank = 0; *DestinationLinesToRequestVMInVBlank = 0; *DestinationLinesToRequestRowInVBlank = 0; *DestinationLinesForPrefetch = 0; - LinesToRequestPrefetchPixelData = 0; *VRatioPrefetchY = 0; *VRatioPrefetchC = 0; *RequiredPrefetchPixDataBWLuma = 0; From 07fd381009e189bfae111dfb076f0ead25fa5cd8 Mon Sep 17 00:00:00 2001 From: Alex Hung Date: Mon, 23 Sep 2024 17:48:47 -0600 Subject: [PATCH 1808/1868] drm/amd/display: Remove redundant assignments [WHAT & HOW] log2_blk_height and log2_blk_width are assigned to 0 and then immediately are updated to other values. The assignments to zero are redudant and removed. This fixes 18 UNUSED_VALUE issues reported by Coverity. Reviewed-by: Rodrigo Siqueira Signed-off-by: Alex Hung Signed-off-by: Rodrigo Siqueira Tested-by: Daniel Wheeler (cherry picked from commit e2cd446eb456d19d8fa272ee7915a65901ccde84) Signed-off-by: Alex Hung --- .../gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c | 4 ---- .../drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c | 4 ---- .../gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c | 4 ---- .../gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c | 4 ---- .../gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c | 4 ---- .../drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c | 4 ---- 6 files changed, 24 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c index 4fce64a030b60..390c1a77fda6a 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c @@ -443,8 +443,6 @@ static void get_meta_and_pte_attr(struct display_mode_lib *mode_lib, blk_bytes = surf_linear ? 256 : get_blk_size_bytes((enum source_macro_tile_size) macro_tile_size); log2_blk_bytes = dml_log2((double) blk_bytes); - log2_blk_height = 0; - log2_blk_width = 0; // remember log rule // "+" in log is multiply @@ -491,8 +489,6 @@ static void get_meta_and_pte_attr(struct display_mode_lib *mode_lib, - log2_meta_req_height; meta_req_width = 1 << log2_meta_req_width; meta_req_height = 1 << log2_meta_req_height; - log2_meta_row_height = 0; - meta_row_width_ub = 0; // the dimensions of a meta row are meta_row_width x meta_row_height in elements. // calculate upper bound of the meta_row_width diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c index 3fa9a5da02f6a..843d6004258ce 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c @@ -443,8 +443,6 @@ static void get_meta_and_pte_attr(struct display_mode_lib *mode_lib, blk_bytes = surf_linear ? 256 : get_blk_size_bytes((enum source_macro_tile_size) macro_tile_size); log2_blk_bytes = dml_log2((double) blk_bytes); - log2_blk_height = 0; - log2_blk_width = 0; // remember log rule // "+" in log is multiply @@ -491,8 +489,6 @@ static void get_meta_and_pte_attr(struct display_mode_lib *mode_lib, - log2_meta_req_height; meta_req_width = 1 << log2_meta_req_width; meta_req_height = 1 << log2_meta_req_height; - log2_meta_row_height = 0; - meta_row_width_ub = 0; // the dimensions of a meta row are meta_row_width x meta_row_height in elements. // calculate upper bound of the meta_row_width diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c index 9e1c18b90805d..5718000627b08 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c @@ -435,8 +435,6 @@ static void get_meta_and_pte_attr( blk_bytes = surf_linear ? 256 : get_blk_size_bytes((enum source_macro_tile_size) macro_tile_size); log2_blk_bytes = dml_log2((double) blk_bytes); - log2_blk_height = 0; - log2_blk_width = 0; // remember log rule // "+" in log is multiply @@ -485,8 +483,6 @@ static void get_meta_and_pte_attr( - log2_meta_req_height; meta_req_width = 1 << log2_meta_req_width; meta_req_height = 1 << log2_meta_req_height; - log2_meta_row_height = 0; - meta_row_width_ub = 0; // the dimensions of a meta row are meta_row_width x meta_row_height in elements. // calculate upper bound of the meta_row_width diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c index b28fcc8608ff8..76d3bb3c91550 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/display_rq_dlg_calc_30.c @@ -392,8 +392,6 @@ static void get_meta_and_pte_attr(struct display_mode_lib *mode_lib, blk_bytes = surf_linear ? 256 : get_blk_size_bytes((enum source_macro_tile_size) macro_tile_size); log2_blk_bytes = dml_log2((double)blk_bytes); - log2_blk_height = 0; - log2_blk_width = 0; // remember log rule // "+" in log is multiply @@ -464,8 +462,6 @@ static void get_meta_and_pte_attr(struct display_mode_lib *mode_lib, - log2_meta_req_height; meta_req_width = 1 << log2_meta_req_width; meta_req_height = 1 << log2_meta_req_height; - log2_meta_row_height = 0; - meta_row_width_ub = 0; // the dimensions of a meta row are meta_row_width x meta_row_height in elements. // calculate upper bound of the meta_row_width diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c index b57b095cd4a81..c46bda2141acd 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/display_rq_dlg_calc_31.c @@ -413,8 +413,6 @@ static void get_meta_and_pte_attr( log2_blk256_height = dml_log2((double) blk256_height); blk_bytes = surf_linear ? 256 : get_blk_size_bytes((enum source_macro_tile_size) macro_tile_size); log2_blk_bytes = dml_log2((double) blk_bytes); - log2_blk_height = 0; - log2_blk_width = 0; // remember log rule // "+" in log is multiply @@ -481,8 +479,6 @@ static void get_meta_and_pte_attr( log2_meta_req_width = log2_meta_req_bytes + 8 - log2_bytes_per_element - log2_meta_req_height; meta_req_width = 1 << log2_meta_req_width; meta_req_height = 1 << log2_meta_req_height; - log2_meta_row_height = 0; - meta_row_width_ub = 0; // the dimensions of a meta row are meta_row_width x meta_row_height in elements. // calculate upper bound of the meta_row_width diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c index 61b3bebf24c96..b7d2a0caec11b 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn314/display_rq_dlg_calc_314.c @@ -501,8 +501,6 @@ static void get_meta_and_pte_attr( log2_blk256_height = dml_log2((double) blk256_height); blk_bytes = surf_linear ? 256 : get_blk_size_bytes((enum source_macro_tile_size) macro_tile_size); log2_blk_bytes = dml_log2((double) blk_bytes); - log2_blk_height = 0; - log2_blk_width = 0; // remember log rule // "+" in log is multiply @@ -569,8 +567,6 @@ static void get_meta_and_pte_attr( log2_meta_req_width = log2_meta_req_bytes + 8 - log2_bytes_per_element - log2_meta_req_height; meta_req_width = 1 << log2_meta_req_width; meta_req_height = 1 << log2_meta_req_height; - log2_meta_row_height = 0; - meta_row_width_ub = 0; // the dimensions of a meta row are meta_row_width x meta_row_height in elements. // calculate upper bound of the meta_row_width From 379c6911b5071a449e019d9b9ad1599eaeb855a2 Mon Sep 17 00:00:00 2001 From: Kaitlyn Tse Date: Mon, 23 Sep 2024 12:29:12 -0400 Subject: [PATCH 1809/1868] drm/amd/display: Initialize replay_config var [Why] Uninitialized variables could cause some bits to be set, thus enabling features unintentionally. [How] Initialize replay_config variable to avoid future issues. Reviewed-by: Harry Vanzylldejong Reviewed-by: Iswara Nagulendran Reviewed-by: Anthony Koo Signed-off-by: Kaitlyn Tse Signed-off-by: Rodrigo Siqueira Tested-by: Daniel Wheeler (cherry picked from commit ef9634fac716ab229d8f627f1fe8432c070a0f91) Signed-off-by: Alex Hung --- .../drm/amd/display/dc/link/protocols/link_edp_panel_control.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c index 7680bc8845d42..cbea36916d35c 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c @@ -938,8 +938,7 @@ bool edp_setup_replay(struct dc_link *link, const struct dc_stream_state *stream struct replay_context replay_context = { 0 }; unsigned int lineTimeInNs = 0; - - union replay_enable_and_configuration replay_config; + union replay_enable_and_configuration replay_config = { 0 }; union dpcd_alpm_configuration alpm_config; From f040cb9274341d8dfc7f91838baa1118cfd30f2c Mon Sep 17 00:00:00 2001 From: Kaitlyn Tse Date: Wed, 4 Sep 2024 11:54:15 -0400 Subject: [PATCH 1810/1868] drm/amd/display: Initialize new backlight_level_params structure [Why] Initialize the new backlight_level_params structure as part of the ABC framework, the information in this structure is needed to be passed down to the DMCUB to identify the backlight control type, to adjust the backlight of the panel and to perform any required conversions from PWM to nits or vice versa. [How] Created initial framework of the backlight_level_params struct and modified existing functions to include the new structure. Reviewed-by: Harry Vanzylldejong Reviewed-by: Iswara Nagulendran Reviewed-by: Anthony Koo Signed-off-by: Kaitlyn Tse Signed-off-by: Rodrigo Siqueira Tested-by: Daniel Wheeler (cherry picked from commit 7cf3e09b3bbac87bad56d9c2cde9f3965299aa8b) Signed-off-by: Alex Hung --- drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c | 5 +++-- drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h | 3 +-- drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c | 7 ++++--- drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.h | 3 +-- drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h | 8 ++++++-- .../display/dc/link/protocols/link_edp_panel_control.c | 8 +++++--- 6 files changed, 20 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c index 9d00d8dc5ae87..c31ec44ccd8c0 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c @@ -3142,9 +3142,10 @@ static void dce110_set_cursor_attribute(struct pipe_ctx *pipe_ctx) } bool dce110_set_backlight_level(struct pipe_ctx *pipe_ctx, - uint32_t backlight_pwm_u16_16, - uint32_t frame_ramp) + struct set_backlight_level_params *params) { + uint32_t backlight_pwm_u16_16 = params->backlight_pwm_u16_16; + uint32_t frame_ramp = params->frame_ramp; struct dc_link *link = pipe_ctx->stream->link; struct dc *dc = link->ctx->dc; struct abm *abm = pipe_ctx->stream_res.abm; diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h index ed3cc3648e8e2..06789ac3a2245 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.h @@ -88,8 +88,7 @@ void dce110_edp_wait_for_hpd_ready( bool power_up); bool dce110_set_backlight_level(struct pipe_ctx *pipe_ctx, - uint32_t backlight_pwm_u16_16, - uint32_t frame_ramp); + struct set_backlight_level_params *params); void dce110_set_abm_immediate_disable(struct pipe_ctx *pipe_ctx); void dce110_set_pipe(struct pipe_ctx *pipe_ctx); void dce110_disable_link_output(struct dc_link *link, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c index 1ea95f8d4cbcc..630e05f32c806 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c @@ -242,14 +242,15 @@ void dcn21_set_pipe(struct pipe_ctx *pipe_ctx) } bool dcn21_set_backlight_level(struct pipe_ctx *pipe_ctx, - uint32_t backlight_pwm_u16_16, - uint32_t frame_ramp) + struct set_backlight_level_params *params) { struct dc_context *dc = pipe_ctx->stream->ctx; struct abm *abm = pipe_ctx->stream_res.abm; struct timing_generator *tg = pipe_ctx->stream_res.tg; struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl; uint32_t otg_inst; + uint32_t backlight_pwm_u16_16 = params->backlight_pwm_u16_16; + uint32_t frame_ramp = params->frame_ramp; if (!abm || !tg || !panel_cntl) return false; @@ -257,7 +258,7 @@ bool dcn21_set_backlight_level(struct pipe_ctx *pipe_ctx, otg_inst = tg->inst; if (dc->dc->res_pool->dmcu) { - dce110_set_backlight_level(pipe_ctx, backlight_pwm_u16_16, frame_ramp); + dce110_set_backlight_level(pipe_ctx, params); return true; } diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.h index 9cee9bdb8de95..a7eaaa4596be4 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.h @@ -50,8 +50,7 @@ void dcn21_PLAT_58856_wa(struct dc_state *context, void dcn21_set_pipe(struct pipe_ctx *pipe_ctx); void dcn21_set_abm_immediate_disable(struct pipe_ctx *pipe_ctx); bool dcn21_set_backlight_level(struct pipe_ctx *pipe_ctx, - uint32_t backlight_pwm_u16_16, - uint32_t frame_ramp); + struct set_backlight_level_params *params); bool dcn21_is_abm_supported(struct dc *dc, struct dc_state *context, struct dc_stream_state *stream); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h index 2f56c36e42510..1df17c54f3a9f 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h @@ -174,6 +174,11 @@ union block_sequence_params { struct fams2_global_control_lock_fast_params fams2_global_control_lock_fast_params; }; +struct set_backlight_level_params { + uint32_t backlight_pwm_u16_16; + uint32_t frame_ramp; +}; + enum block_sequence_func { DMUB_SUBVP_PIPE_CONTROL_LOCK_FAST = 0, OPTC_PIPE_CONTROL_LOCK, @@ -365,8 +370,7 @@ struct hw_sequencer_funcs { void (*clear_status_bits)(struct dc *dc, unsigned int mask); bool (*set_backlight_level)(struct pipe_ctx *pipe_ctx, - uint32_t backlight_pwm_u16_16, - uint32_t frame_ramp); + struct set_backlight_level_params *params); void (*set_abm_immediate_disable)(struct pipe_ctx *pipe_ctx); diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c index cbea36916d35c..43a467f6ce7bd 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c @@ -521,13 +521,13 @@ bool edp_set_backlight_level(const struct dc_link *link, uint32_t frame_ramp) { struct dc *dc = link->ctx->dc; - DC_LOGGER_INIT(link->ctx->logger); DC_LOG_BACKLIGHT("New Backlight level: %d (0x%X)\n", backlight_pwm_u16_16, backlight_pwm_u16_16); if (dc_is_embedded_signal(link->connector_signal)) { struct pipe_ctx *pipe_ctx = get_pipe_from_link(link); + struct set_backlight_level_params backlight_level_param = { 0 }; if (link->panel_cntl) link->panel_cntl->stored_backlight_registers.USER_LEVEL = backlight_pwm_u16_16; @@ -542,10 +542,12 @@ bool edp_set_backlight_level(const struct dc_link *link, return false; } + backlight_level_param.backlight_pwm_u16_16 = backlight_pwm_u16_16; + backlight_level_param.frame_ramp = frame_ramp; + dc->hwss.set_backlight_level( pipe_ctx, - backlight_pwm_u16_16, - frame_ramp); + &backlight_level_param); } return true; } From 7a0dba913134ccfe8595fa179308a1d40e299776 Mon Sep 17 00:00:00 2001 From: Aric Cyr Date: Mon, 30 Sep 2024 09:05:49 -0400 Subject: [PATCH 1811/1868] drm/amd/display: 3.2.304 This DC patchset brings improvements in multiple areas. In summary, we highlight: - Improvements to seemless boot. - Adjustments for DSC dock. - DML improvements - DMCUB fixes for D0/D3 and new register offset. - Code cleanup. Signed-off-by: Aric Cyr Signed-off-by: Rodrigo Siqueira Acked-by: Rodrigo Siqueira Tested-by: Daniel Wheeler (cherry picked from commit 57ca5ad04443a9187bb51c69eaafc7df617a2a74) Signed-off-by: Alex Hung --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 36e059c55dc50..18d472e5ce1ad 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -55,7 +55,7 @@ struct aux_payload; struct set_config_cmd_payload; struct dmub_notification; -#define DC_VER "3.2.303" +#define DC_VER "3.2.304" #define MAX_SURFACES 3 #define MAX_PLANES 6 From 04011b6efc154326a16562f8cf914d8d25c13824 Mon Sep 17 00:00:00 2001 From: Samson Tam Date: Wed, 2 Oct 2024 21:51:18 -0400 Subject: [PATCH 1812/1868] drm/amd/display: add sharpening policy to plane state [Why] Pass in sharpening policy through plane state from control side [How] Add sharpener support through dc_caps. Add sharpen policy to plane state and move to spl_input. Pass sharpen policy from plane state to SPL. Reviewed-by: Aric Cyr Signed-off-by: Samson Tam Signed-off-by: Roman Li Tested-by: Daniel Wheeler (cherry picked from commit c1e6a6ed2f45e6bf0396b7242f9ac24c218b87f1) Signed-off-by: Alex Hung --- drivers/gpu/drm/amd/display/dc/dc.h | 6 ++++++ drivers/gpu/drm/amd/display/dc/dc_spl_translate.c | 2 +- .../drm/amd/display/dc/resource/dcn401/dcn401_resource.c | 1 + drivers/gpu/drm/amd/display/dc/spl/dc_spl.c | 6 +++--- drivers/gpu/drm/amd/display/dc/spl/dc_spl_types.h | 2 +- 5 files changed, 12 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 18d472e5ce1ad..30a544e218b6c 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -227,6 +227,10 @@ struct dc_dmub_caps { uint8_t fams_ver; }; +struct dc_scl_caps { + bool sharpener_support; +}; + struct dc_caps { uint32_t max_streams; uint32_t max_links; @@ -292,6 +296,7 @@ struct dc_caps { bool sequential_ono; /* Conservative limit for DCC cases which require ODM4:1 to support*/ uint32_t dcc_plane_width_limit; + struct dc_scl_caps scl_caps; }; struct dc_bug_wa { @@ -1358,6 +1363,7 @@ struct dc_plane_state { enum mpcc_movable_cm_location mcm_location; struct dc_csc_transform cursor_csc_color_matrix; bool adaptive_sharpness_en; + int adaptive_sharpness_policy; int sharpness_level; enum linear_light_scaling linear_light_scaling; unsigned int sdr_white_level_nits; diff --git a/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c b/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c index 20fd0afca8cb0..eeffe44be9e32 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c +++ b/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c @@ -188,7 +188,7 @@ void translate_SPL_in_params_from_pipe_ctx(struct pipe_ctx *pipe_ctx, struct spl spl_in->h_active = pipe_ctx->plane_res.scl_data.h_active; spl_in->v_active = pipe_ctx->plane_res.scl_data.v_active; - spl_in->debug.sharpen_policy = (enum sharpen_policy)pipe_ctx->stream->ctx->dc->debug.sharpen_policy; + spl_in->sharpen_policy = (enum sharpen_policy)plane_state->adaptive_sharpness_policy; spl_in->debug.scale_to_sharpness_policy = (enum scale_to_sharpness_policy)pipe_ctx->stream->ctx->dc->debug.scale_to_sharpness_policy; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c index 59184abab1a70..2a71611da2e70 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c @@ -2150,6 +2150,7 @@ static bool dcn401_resource_construct( /* SPL */ spl_init_easf_filter_coeffs(); spl_init_blur_scale_coeffs(); + dc->caps.scl_caps.sharpener_support = true; return true; diff --git a/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c b/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c index c38a5c8646e86..f043c7e32e169 100644 --- a/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c +++ b/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c @@ -848,13 +848,13 @@ static bool spl_get_isharp_en(struct spl_in *spl_in, * surfaces based on policy setting */ if (!spl_is_yuv420(spl_in->basic_in.format) && - (spl_in->debug.sharpen_policy == SHARPEN_YUV)) + (spl_in->sharpen_policy == SHARPEN_YUV)) return enable_isharp; else if ((spl_is_yuv420(spl_in->basic_in.format) && !fullscreen) && - (spl_in->debug.sharpen_policy == SHARPEN_RGB_FULLSCREEN_YUV)) + (spl_in->sharpen_policy == SHARPEN_RGB_FULLSCREEN_YUV)) return enable_isharp; else if (!spl_in->is_fullscreen && - spl_in->debug.sharpen_policy == SHARPEN_FULLSCREEN_ALL) + spl_in->sharpen_policy == SHARPEN_FULLSCREEN_ALL) return enable_isharp; /* diff --git a/drivers/gpu/drm/amd/display/dc/spl/dc_spl_types.h b/drivers/gpu/drm/amd/display/dc/spl/dc_spl_types.h index 48e4217555f84..fcb5d389592be 100644 --- a/drivers/gpu/drm/amd/display/dc/spl/dc_spl_types.h +++ b/drivers/gpu/drm/amd/display/dc/spl/dc_spl_types.h @@ -508,7 +508,6 @@ struct spl_funcs { struct spl_debug { int visual_confirm_base_offset; int visual_confirm_dpp_offset; - enum sharpen_policy sharpen_policy; enum scale_to_sharpness_policy scale_to_sharpness_policy; }; @@ -530,6 +529,7 @@ struct spl_in { int h_active; int v_active; int sdr_white_level_nits; + enum sharpen_policy sharpen_policy; }; // end of SPL inputs From a2abd6e30cbb09c7ac37e8f3ca53a01cc520c9a6 Mon Sep 17 00:00:00 2001 From: Dillon Varone Date: Tue, 8 Oct 2024 15:25:45 -0400 Subject: [PATCH 1813/1868] drm/amd/display: Recalculate SubVP Phantom VBlank End in dml21 [WHY] The phantom stream timing is copied from the main stream as most parameters are identical, however some need to be recalculated. Currently VBlank End is not recalculated and copied from the main incorrectly. [HOW] Recalculate VBlank End for phantom stream timing. Reviewed-by: Alvin Lee Signed-off-by: Dillon Varone Signed-off-by: Wayne Lin Tested-by: Daniel Wheeler (cherry picked from commit 6ed4c8612efc176434b854bc7169eb792778207c) Signed-off-by: Alex Hung --- .../drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c | 1 + .../amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c index 0aa4e4d343b04..3d41ffde91c1b 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4.c @@ -159,6 +159,7 @@ static void create_phantom_stream_from_main_stream(struct dml2_stream_parameters phantom->timing.v_total = meta->v_total; phantom->timing.v_active = meta->v_active; phantom->timing.v_front_porch = meta->v_front_porch; + phantom->timing.v_blank_end = phantom->timing.v_total - phantom->timing.v_front_porch - phantom->timing.v_active; phantom->timing.vblank_nom = phantom->timing.v_total - phantom->timing.v_active; phantom->timing.drr_config.enabled = false; } diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c index ab229e1598aef..714b5c39b7e6c 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_utils.c @@ -425,6 +425,7 @@ static void create_phantom_stream_from_main_stream(struct dml2_stream_parameters phantom->timing.v_total = meta->v_total; phantom->timing.v_active = meta->v_active; phantom->timing.v_front_porch = meta->v_front_porch; + phantom->timing.v_blank_end = phantom->timing.v_total - phantom->timing.v_front_porch - phantom->timing.v_active; phantom->timing.vblank_nom = phantom->timing.v_total - phantom->timing.v_active; phantom->timing.drr_config.enabled = false; } From 418de26f62e07e91965c92da64ca67cb8fa2c131 Mon Sep 17 00:00:00 2001 From: Leo Chen Date: Mon, 7 Oct 2024 15:50:35 -0400 Subject: [PATCH 1814/1868] drm/amd/display: Adding array index check to prevent memory corruption [Why & How] Array indices out of bound caused memory corruption. Adding checks to ensure that array index stays in bound. Reviewed-by: Charlene Liu Reviewed-by: Nicholas Kazlauskas Signed-off-by: Leo Chen Signed-off-by: Wayne Lin Tested-by: Daniel Wheeler (cherry picked from commit f4d1ac79cdaac6476435430020c8bf6fd58baea4) Signed-off-by: Alex Hung --- .../gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c index b46a3afe48ca7..7d68006137a97 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c @@ -257,11 +257,11 @@ static void dcn35_notify_host_router_bw(struct clk_mgr *clk_mgr_base, struct dc_ struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base); uint32_t host_router_bw_kbps[MAX_HOST_ROUTERS_NUM] = { 0 }; int i; - for (i = 0; i < context->stream_count; ++i) { const struct dc_stream_state *stream = context->streams[i]; const struct dc_link *link = stream->link; - uint8_t lowest_dpia_index = 0, hr_index = 0; + uint8_t lowest_dpia_index = 0; + unsigned int hr_index = 0; if (!link) continue; @@ -271,6 +271,8 @@ static void dcn35_notify_host_router_bw(struct clk_mgr *clk_mgr_base, struct dc_ continue; hr_index = (link->link_index - lowest_dpia_index) / 2; + if (hr_index >= MAX_HOST_ROUTERS_NUM) + continue; host_router_bw_kbps[hr_index] += dc_bandwidth_in_kbps_from_timing( &stream->timing, dc_link_get_highest_encoding_format(link)); } From f55c99e940fb71f8953cc3fb0e20cadb8c4394d7 Mon Sep 17 00:00:00 2001 From: Samson Tam Date: Wed, 9 Oct 2024 10:00:04 -0400 Subject: [PATCH 1815/1868] drm/amd/display: update fullscreen status to SPL [Why] Current fullscreen check in SPL using dm_helpers is out-of-sync with dc state. This causes an issue during minimal transition where we pick an invalid intermediate state because the pre and post fullscreen status are different. [How] Add sharpening_required flag to dc_stream_state. Use this flag to indicate if we are in fullscreen or not. Propagate flag to SPL for fullscreen status. Remove workaround in DML Reviewed-by: Alvin Lee Signed-off-by: Samson Tam Signed-off-by: Wayne Lin Tested-by: Daniel Wheeler (cherry picked from commit eda396ff6b27e1904ab16e1e5b0f1d7f734cf68c) Signed-off-by: Alex Hung --- drivers/gpu/drm/amd/display/dc/core/dc.c | 5 +++++ drivers/gpu/drm/amd/display/dc/dc_spl_translate.c | 2 +- drivers/gpu/drm/amd/display/dc/dc_stream.h | 3 +++ 3 files changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 11d1153ae9fdf..e5ebb5aa89a7f 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -2755,6 +2755,9 @@ static enum surface_update_type check_update_surfaces_for_stream( if (stream_update->scaler_sharpener_update) su_flags->bits.scaler_sharpener = 1; + if (stream_update->sharpening_required) + su_flags->bits.sharpening_required = 1; + if (su_flags->raw != 0) overall_type = UPDATE_TYPE_FULL; @@ -3094,6 +3097,8 @@ static void copy_stream_update_to_stream(struct dc *dc, } if (update->scaler_sharpener_update) stream->scaler_sharpener_update = *update->scaler_sharpener_update; + if (update->sharpening_required) + stream->sharpening_required = *update->sharpening_required; } static void backup_planes_and_stream_state( diff --git a/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c b/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c index eeffe44be9e32..24aa9df892f3a 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c +++ b/drivers/gpu/drm/amd/display/dc/dc_spl_translate.c @@ -195,7 +195,7 @@ void translate_SPL_in_params_from_pipe_ctx(struct pipe_ctx *pipe_ctx, struct spl /* Check if it is stream is in fullscreen and if its HDR. * Use this to determine sharpness levels */ - spl_in->is_fullscreen = dm_helpers_is_fullscreen(pipe_ctx->stream->ctx, pipe_ctx->stream); + spl_in->is_fullscreen = pipe_ctx->stream->sharpening_required; spl_in->is_hdr_on = dm_helpers_is_hdr_on(pipe_ctx->stream->ctx, pipe_ctx->stream); spl_in->sdr_white_level_nits = plane_state->sdr_white_level_nits; } diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h index 14ea47eda0c87..413970588a26d 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_stream.h +++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h @@ -143,6 +143,7 @@ union stream_update_flags { uint32_t crtc_timing_adjust : 1; uint32_t fams_changed : 1; uint32_t scaler_sharpener : 1; + uint32_t sharpening_required : 1; } bits; uint32_t raw; @@ -310,6 +311,7 @@ struct dc_stream_state { struct luminance_data lumin_data; bool scaler_sharpener_update; + bool sharpening_required; }; #define ABM_LEVEL_IMMEDIATE_DISABLE 255 @@ -356,6 +358,7 @@ struct dc_stream_update { struct dc_cursor_position *cursor_position; bool *hw_cursor_req; bool *scaler_sharpener_update; + bool *sharpening_required; }; bool dc_is_stream_unchanged( From d8ad546e08f6c260de36b875048605823fa20012 Mon Sep 17 00:00:00 2001 From: Robin Chen Date: Thu, 12 Sep 2024 20:59:36 +0800 Subject: [PATCH 1816/1868] drm/amd/display: Read Sink emission rate capability [WHY] To get sink emission rate information for future supported refresh rate calculation. Reviewed-by: ChunTao Tso Signed-off-by: Robin Chen Signed-off-by: Roman Li Tested-by: Daniel Wheeler (cherry picked from commit d5e5b0675d8485dda927c1bcd0a3a4f16a760978) Signed-off-by: Alex Hung --- drivers/gpu/drm/amd/display/dc/dc_dp_types.h | 3 ++- .../dc/link/protocols/link_dp_capability.c | 8 ++++++++ .../gpu/drm/amd/display/include/dpcd_defs.h | 19 ++++++++++--------- 3 files changed, 20 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h index 50fa8547d718e..8dd6eb044829a 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h @@ -1192,6 +1192,7 @@ struct dpcd_caps { struct edp_psr_info psr_info; struct replay_info pr_info; + uint16_t edp_oled_emission_rate; }; union dpcd_sink_ext_caps { @@ -1205,7 +1206,7 @@ union dpcd_sink_ext_caps { uint8_t oled : 1; uint8_t reserved_2 : 1; uint8_t miniled : 1; - uint8_t reserved : 1; + uint8_t emission_output : 1; } bits; uint8_t raw; }; diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c index db0777661b320..6c89b6b58906c 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c @@ -2066,6 +2066,14 @@ void detect_edp_sink_caps(struct dc_link *link) core_link_read_dpcd(link, DP_SINK_PR_MAX_NUMBER_OF_DEVIATION_LINE, &link->dpcd_caps.pr_info.max_deviation_line, sizeof(link->dpcd_caps.pr_info.max_deviation_line)); + + /* + * OLED Emission Rate info + */ + if (link->dpcd_sink_ext_caps.bits.emission_output) + core_link_read_dpcd(link, DP_SINK_EMISSION_RATE, + (uint8_t *)&link->dpcd_caps.edp_oled_emission_rate, + sizeof(link->dpcd_caps.edp_oled_emission_rate)); } bool dp_get_max_link_enc_cap(const struct dc_link *link, struct dc_link_settings *max_link_enc_cap) diff --git a/drivers/gpu/drm/amd/display/include/dpcd_defs.h b/drivers/gpu/drm/amd/display/include/dpcd_defs.h index aee5170f5fb23..de8f3cfed6c84 100644 --- a/drivers/gpu/drm/amd/display/include/dpcd_defs.h +++ b/drivers/gpu/drm/amd/display/include/dpcd_defs.h @@ -164,18 +164,19 @@ enum dpcd_psr_sink_states { PSR_SINK_STATE_SINK_INTERNAL_ERROR = 7, }; -#define DP_SOURCE_SEQUENCE 0x30c -#define DP_SOURCE_TABLE_REVISION 0x310 -#define DP_SOURCE_PAYLOAD_SIZE 0x311 -#define DP_SOURCE_SINK_CAP 0x317 -#define DP_SOURCE_BACKLIGHT_LEVEL 0x320 -#define DP_SOURCE_BACKLIGHT_CURRENT_PEAK 0x326 -#define DP_SOURCE_BACKLIGHT_CONTROL 0x32E -#define DP_SOURCE_BACKLIGHT_ENABLE 0x32F -#define DP_SOURCE_MINIMUM_HBLANK_SUPPORTED 0x340 +#define DP_SOURCE_SEQUENCE 0x30C +#define DP_SOURCE_TABLE_REVISION 0x310 +#define DP_SOURCE_PAYLOAD_SIZE 0x311 +#define DP_SOURCE_SINK_CAP 0x317 +#define DP_SOURCE_BACKLIGHT_LEVEL 0x320 +#define DP_SOURCE_BACKLIGHT_CURRENT_PEAK 0x326 +#define DP_SOURCE_BACKLIGHT_CONTROL 0x32E +#define DP_SOURCE_BACKLIGHT_ENABLE 0x32F +#define DP_SOURCE_MINIMUM_HBLANK_SUPPORTED 0x340 #define DP_SINK_PR_REPLAY_STATUS 0x378 #define DP_SINK_PR_PIXEL_DEVIATION_PER_LINE 0x379 #define DP_SINK_PR_MAX_NUMBER_OF_DEVIATION_LINE 0x37A +#define DP_SINK_EMISSION_RATE 0x37E /* Remove once drm_dp_helper.h is updated upstream */ #ifndef DP_TOTAL_LTTPR_CNT From 6568057a63f8b9bcf175f5d9ff85d31375d2873b Mon Sep 17 00:00:00 2001 From: Ausef Yousof Date: Wed, 23 Oct 2024 13:24:11 -0400 Subject: [PATCH 1817/1868] Revert "drm/amd/display: Block UHBR Based On USB-C PD Cable ID" This reverts commit f767e41a6f6b70cd222edd24549c1fa753c550fc. [why & how] The offending commit caused a lighting issue for Samsung Odyssey G9 monitors when connecting via USB-C. The commit was intended to block certain UHBR rates. Reviewed-by: Charlene Liu Signed-off-by: Ausef Yousof Signed-off-by: Zaeem Mohamed Tested-by: Daniel Wheeler (cherry picked from commit 9e999e87e9b47cd19d43383b0daa33be2b425d38) Signed-off-by: Alex Hung --- .../dc/link/protocols/link_dp_capability.c | 22 +++++-------------- 1 file changed, 6 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c index 6c89b6b58906c..8c7f8b3e57a25 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c @@ -1417,8 +1417,7 @@ static bool get_usbc_cable_id(struct dc_link *link, union dp_cable_id *cable_id) if (!link->ctx->dmub_srv || link->ep_type != DISPLAY_ENDPOINT_PHY || - link->link_enc->features.flags.bits.DP_IS_USB_C == 0 || - link->link_enc->features.flags.bits.IS_DP2_CAPABLE == 0) + link->link_enc->features.flags.bits.DP_IS_USB_C == 0) return false; memset(&cmd, 0, sizeof(cmd)); @@ -1431,9 +1430,7 @@ static bool get_usbc_cable_id(struct dc_link *link, union dp_cable_id *cable_id) cable_id->raw = cmd.cable_id.data.output_raw; DC_LOG_DC("usbc_cable_id = %d.\n", cable_id->raw); } - - ASSERT(cmd.cable_id.header.ret_status); - return true; + return cmd.cable_id.header.ret_status == 1; } static void retrieve_cable_id(struct dc_link *link) @@ -2122,8 +2119,6 @@ struct dc_link_settings dp_get_max_link_cap(struct dc_link *link) /* get max link encoder capability */ if (link_enc) link_enc->funcs->get_max_link_cap(link_enc, &max_link_cap); - else - return max_link_cap; /* Lower link settings based on sink's link cap */ if (link->reported_link_cap.lane_count < max_link_cap.lane_count) @@ -2157,15 +2152,10 @@ struct dc_link_settings dp_get_max_link_cap(struct dc_link *link) */ cable_max_link_rate = get_cable_max_link_rate(link); - if (!link->dc->debug.ignore_cable_id) { - if (cable_max_link_rate != LINK_RATE_UNKNOWN) - // cable max link rate known - max_link_cap.link_rate = MIN(max_link_cap.link_rate, cable_max_link_rate); - else if (link_enc->funcs->is_in_alt_mode && link_enc->funcs->is_in_alt_mode(link_enc)) - // cable max link rate ambiguous, DP alt mode, limit to HBR3 - max_link_cap.link_rate = MIN(max_link_cap.link_rate, LINK_RATE_HIGH3); - //else {} - // cable max link rate ambiguous, DP, do nothing + if (!link->dc->debug.ignore_cable_id && + cable_max_link_rate != LINK_RATE_UNKNOWN) { + if (cable_max_link_rate < max_link_cap.link_rate) + max_link_cap.link_rate = cable_max_link_rate; if (!link->dpcd_caps.cable_id.bits.UHBR13_5_CAPABILITY && link->dpcd_caps.cable_id.bits.CABLE_TYPE >= 2) From fdbc912d492e265f3d0354e1d4c2d5cad49b633e Mon Sep 17 00:00:00 2001 From: Samson Tam Date: Wed, 16 Oct 2024 14:11:35 -0400 Subject: [PATCH 1818/1868] drm/amd/display: fix handling of max_downscale_src_width fail check in SPL [Why] If max_downscale_src_width check fails, we exit early from spl_calculate_scaler_params but dscl_prog_data is not fully populated. If viewport is left at 0, it can cause crash in dml. [How] Call spl_set_dscl_prog_data before we exit early from spl_calculate_scaler_params to populate dscl_prog_data Populate taps in spl_get_optimal_number_of_taps Reviewed-by: Alvin Lee Signed-off-by: Samson Tam Signed-off-by: Tom Chung Tested-by: Daniel Wheeler (cherry picked from commit 6651ffb374de8be12bb241f7ec6967368dceccd3) Signed-off-by: Alex Hung --- drivers/gpu/drm/amd/display/dc/spl/dc_spl.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c b/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c index f043c7e32e169..403fd1221803b 100644 --- a/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c +++ b/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c @@ -882,8 +882,13 @@ static bool spl_get_optimal_number_of_taps( if (spl_scratch->scl_data.viewport.width > spl_scratch->scl_data.h_active && max_downscale_src_width != 0 && - spl_scratch->scl_data.viewport.width > max_downscale_src_width) + spl_scratch->scl_data.viewport.width > max_downscale_src_width) { + memcpy(&spl_scratch->scl_data.taps, in_taps, sizeof(struct spl_taps)); + *enable_easf_v = false; + *enable_easf_h = false; + *enable_isharp = false; return false; + } /* Disable adaptive scaler and sharpener when integer scaling is enabled */ if (spl_in->scaling_quality.integer_scaling) { @@ -1765,12 +1770,12 @@ bool spl_calculate_scaler_params(struct spl_in *spl_in, struct spl_out *spl_out) // Clamp spl_clamp_viewport(&spl_scratch.scl_data.viewport); - if (!res) - return res; - // Save all calculated parameters in dscl_prog_data structure to program hw registers spl_set_dscl_prog_data(spl_in, &spl_scratch, spl_out, enable_easf_v, enable_easf_h, enable_isharp); + if (!res) + return res; + if (spl_in->lls_pref == LLS_PREF_YES) { if (spl_in->is_hdr_on) setup = HDR_L; From 859edc6d9d3b27ae629d06fad34b0d04031d8fc2 Mon Sep 17 00:00:00 2001 From: Samson Tam Date: Fri, 18 Oct 2024 00:26:41 -0400 Subject: [PATCH 1819/1868] drm/amd/display: store sharpness 1dlut table in dscl_prog_data [Why] Previously dscl_prog_data stored pointer to sharpness 1dlut table. SPL had four pre-generated tables, one for each setup. This allowed us to minimize number of times we had to recalculate table when switching between setups. However, with dual display, this becomes an issue because for a given setup, we could have a different per app sharpness value than the global sharpness value. So the pre-generated table will change but both displays may point to the same table and one of them will have the wrong sharpness setting. [How] Store the sharpness 1dlut table in dscl_prog_data. This ensures that each display can have its own sharpness setting. Reviewed-by: Ilya Bakoulin Signed-off-by: Samson Tam Signed-off-by: Tom Chung Tested-by: Daniel Wheeler (cherry picked from commit 123826bcb6a21c8853273e6dfe8a7b2f8ff3ebac) Signed-off-by: Alex Hung --- drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c | 3 ++- drivers/gpu/drm/amd/display/dc/spl/dc_spl.c | 3 ++- drivers/gpu/drm/amd/display/dc/spl/dc_spl_isharp_filters.h | 1 - drivers/gpu/drm/amd/display/dc/spl/dc_spl_types.h | 3 ++- 4 files changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c index 5105fd580017c..2f92e7d4981ba 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp_dscl.c @@ -1091,7 +1091,8 @@ void dpp401_dscl_set_scaler_manual_scale(struct dpp *dpp_base, /* ISHARP_DELTA_LUT */ dpp401_dscl_set_isharp_filter(dpp, scl_data->dscl_prog_data.isharp_delta); dpp->scl_data.dscl_prog_data.sharpness_level = scl_data->dscl_prog_data.sharpness_level; - dpp->scl_data.dscl_prog_data.isharp_delta = scl_data->dscl_prog_data.isharp_delta; + memcpy(dpp->scl_data.dscl_prog_data.isharp_delta, scl_data->dscl_prog_data.isharp_delta, + sizeof(uint32_t) * ISHARP_LUT_TABLE_SIZE); if (memcmp(&dpp->scl_data, scl_data, sizeof(*scl_data)) == 0) return; diff --git a/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c b/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c index 403fd1221803b..133906e73a65c 100644 --- a/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c +++ b/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c @@ -1607,7 +1607,8 @@ static void spl_set_isharp_data(struct dscl_prog_data *dscl_prog_data, spl_build_isharp_1dlut_from_reference_curve(ratio, setup, adp_sharpness, scale_to_sharpness_policy); - dscl_prog_data->isharp_delta = spl_get_pregen_filter_isharp_1D_lut(setup); + memcpy(dscl_prog_data->isharp_delta, spl_get_pregen_filter_isharp_1D_lut(setup), + sizeof(uint32_t) * ISHARP_LUT_TABLE_SIZE); dscl_prog_data->sharpness_level = adp_sharpness.sharpness_level; dscl_prog_data->isharp_en = 1; // ISHARP_EN diff --git a/drivers/gpu/drm/amd/display/dc/spl/dc_spl_isharp_filters.h b/drivers/gpu/drm/amd/display/dc/spl/dc_spl_isharp_filters.h index afcc66206ca2a..89af91e19b6ce 100644 --- a/drivers/gpu/drm/amd/display/dc/spl/dc_spl_isharp_filters.h +++ b/drivers/gpu/drm/amd/display/dc/spl/dc_spl_isharp_filters.h @@ -7,7 +7,6 @@ #include "dc_spl_types.h" -#define ISHARP_LUT_TABLE_SIZE 32 const uint32_t *spl_get_filter_isharp_1D_lut_0(void); const uint32_t *spl_get_filter_isharp_1D_lut_0p5x(void); const uint32_t *spl_get_filter_isharp_1D_lut_1p0x(void); diff --git a/drivers/gpu/drm/amd/display/dc/spl/dc_spl_types.h b/drivers/gpu/drm/amd/display/dc/spl/dc_spl_types.h index fcb5d389592be..8b00ccb1dfdad 100644 --- a/drivers/gpu/drm/amd/display/dc/spl/dc_spl_types.h +++ b/drivers/gpu/drm/amd/display/dc/spl/dc_spl_types.h @@ -250,6 +250,7 @@ enum isharp_en { ISHARP_DISABLE, ISHARP_ENABLE }; +#define ISHARP_LUT_TABLE_SIZE 32 // Below struct holds values that can be directly used to program // hardware registers. No conversion/clamping is required struct dscl_prog_data { @@ -400,7 +401,7 @@ struct dscl_prog_data { uint32_t isharp_nl_en; // ISHARP_NL_EN ? TODO:check this struct isharp_lba isharp_lba; // ISHARP_LBA struct isharp_fmt isharp_fmt; // ISHARP_FMT - const uint32_t *isharp_delta; + uint32_t isharp_delta[ISHARP_LUT_TABLE_SIZE]; struct isharp_nldelta_sclip isharp_nldelta_sclip; // ISHARP_NLDELTA_SCLIP /* blur and scale filter */ const uint16_t *filter_blur_scale_v; From 05bda48fb0b47b7676370fc21e374031927c51d6 Mon Sep 17 00:00:00 2001 From: Leo Ma Date: Fri, 11 Oct 2024 14:08:34 -0400 Subject: [PATCH 1820/1868] drm/amd/display: Fix underflow when playing 8K video in full screen mode [Why&How] Flickering observed while playing 8k HEVC-10 bit video in full screen mode with black border. We didn't support this case for subvp. Make change to the existing check to disable subvp for this corner case. Reviewed-by: Alvin Lee Signed-off-by: Leo Ma Signed-off-by: Dillon Varone Signed-off-by: Tom Chung Tested-by: Daniel Wheeler (cherry picked from commit 9869ba6285127a36a558b09fa2cc70da18dc58c5) Signed-off-by: Alex Hung --- .../drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c index 7a01a956e4bbd..138b4b1e42ed7 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c @@ -859,7 +859,7 @@ static void populate_dml21_plane_config_from_plane_state(struct dml2_context *dm plane->immediate_flip = plane_state->flip_immediate; plane->composition.rect_out_height_spans_vactive = - plane_state->dst_rect.height >= stream->timing.v_addressable && + plane_state->dst_rect.height >= stream->src.height && stream->dst.height >= stream->timing.v_addressable; } From 3fdf64855165951d872f9d174e4029599ca3a307 Mon Sep 17 00:00:00 2001 From: Leo Chen Date: Thu, 3 Oct 2024 12:20:23 -0400 Subject: [PATCH 1821/1868] drm/amd/display: Full exit out of IPS2 when all allow signals have been cleared [Why] A race condition occurs between cursor movement and vertical interrupt control thread from OS, with both threads trying to exit IPS2. Vertical interrupt control thread clears the prev driver allow signal while not fully finishing the IPS2 exit process. [How] We want to detect all the allow signals have been cleared before we perform the full exit. Reviewed-by: Nicholas Kazlauskas Signed-off-by: Leo Chen Signed-off-by: Roman Li Tested-by: Daniel Wheeler (cherry picked from commit 307e9a097e2fa87f645f3a122a58cfb217646177) Signed-off-by: Alex Hung --- drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c | 6 ++++-- drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 3 ++- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c index 9291f078ffde7..3096f24012f85 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c +++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c @@ -1294,6 +1294,8 @@ static void dc_dmub_srv_notify_idle(const struct dc *dc, bool allow_idle) memset(&new_signals, 0, sizeof(new_signals)); + new_signals.bits.allow_idle = 1; /* always set */ + if (dc->config.disable_ips == DMUB_IPS_ENABLE || dc->config.disable_ips == DMUB_IPS_DISABLE_DYNAMIC) { new_signals.bits.allow_pg = 1; @@ -1389,7 +1391,7 @@ static void dc_dmub_srv_exit_low_power_state(const struct dc *dc) */ dc_dmub_srv->needs_idle_wake = false; - if (prev_driver_signals.bits.allow_ips2 && + if ((prev_driver_signals.bits.allow_ips2 || prev_driver_signals.all == 0) && (!dc->debug.optimize_ips_handshake || ips_fw->signals.bits.ips2_commit || !ips_fw->signals.bits.in_idle)) { DC_LOG_IPS( @@ -1450,7 +1452,7 @@ static void dc_dmub_srv_exit_low_power_state(const struct dc *dc) } dc_dmub_srv_notify_idle(dc, false); - if (prev_driver_signals.bits.allow_ips1) { + if (prev_driver_signals.bits.allow_ips1 || prev_driver_signals.all == 0) { DC_LOG_IPS( "wait for IPS1 commit clear (ips1_commit=%u ips2_commit=%u)", ips_fw->signals.bits.ips1_commit, diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index f9e82c4f8deb6..6edd3d34c7b59 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -752,7 +752,8 @@ union dmub_shared_state_ips_driver_signals { uint32_t allow_ips1 : 1; /**< 1 is IPS1 is allowed */ uint32_t allow_ips2 : 1; /**< 1 is IPS1 is allowed */ uint32_t allow_z10 : 1; /**< 1 if Z10 is allowed */ - uint32_t reserved_bits : 28; /**< Reversed bits */ + uint32_t allow_idle : 1; /**< 1 if driver is allowing idle */ + uint32_t reserved_bits : 27; /**< Reversed bits */ } bits; uint32_t all; }; From 2cafd2ec2b83dfb32b9b98448c5fa33de032986b Mon Sep 17 00:00:00 2001 From: Ovidiu Bunea Date: Fri, 11 Oct 2024 14:55:52 -0400 Subject: [PATCH 1822/1868] drm/amd/display: Optimize power up sequence for specific OLED [why & how] OLED power up sequence takes an extra 150ms via hardcoded delay, but there is a strict requirement on DisplayOn resume time. For customer panel, remove these delays to meet target until a cleaner solution is can be put in place. Reviewed-by: Charlene Liu Signed-off-by: Ovidiu Bunea Signed-off-by: Tom Chung Tested-by: Daniel Wheeler (cherry picked from commit e80b4504e901aa4e7b7c5767e7981828ad41ff7f) Signed-off-by: Alex Hung --- drivers/gpu/drm/amd/display/dc/dc.h | 1 + drivers/gpu/drm/amd/display/dc/dc_types.h | 1 + .../drm/amd/display/dc/hwss/dce110/dce110_hwseq.c | 3 ++- drivers/gpu/drm/amd/display/dc/link/link_dpms.c | 15 +++++++++++---- 4 files changed, 15 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 30a544e218b6c..6f3875b212eb2 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -1070,6 +1070,7 @@ struct dc_debug_options { unsigned int sharpen_policy; unsigned int scale_to_sharpness_policy; bool skip_full_updated_if_possible; + unsigned int enable_oled_edp_power_up_opt; }; diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h index 3401f4c9fb10e..f0776484abb75 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_types.h @@ -180,6 +180,7 @@ struct dc_panel_patch { unsigned int remove_sink_ext_caps; unsigned int disable_colorimetry; uint8_t blankstream_before_otg_off; + bool oled_optimize_display_on; }; struct dc_edid_caps { diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c index c31ec44ccd8c0..427fd6ea062a1 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c @@ -1039,7 +1039,8 @@ void dce110_edp_backlight_control( link_transmitter_control(ctx->dc_bios, &cntl); if (enable && link->dpcd_sink_ext_caps.bits.oled && - !link->dc->config.edp_no_power_sequencing) { + !link->dc->config.edp_no_power_sequencing && + !link->local_sink->edid_caps.panel_patch.oled_optimize_display_on) { post_T7_delay += link->panel_config.pps.extra_post_t7_ms; msleep(post_T7_delay); } diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c index b4c206c20b458..6a2fecb49dea7 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c @@ -2164,6 +2164,9 @@ static enum dc_status enable_link_dp(struct dc_state *state, if (link_settings->link_rate == LINK_RATE_LOW) skip_video_pattern = false; + if (stream->sink_patches.oled_optimize_display_on) + set_default_brightness_aux(link); + if (perform_link_training_with_retries(link_settings, skip_video_pattern, lt_attempts, @@ -2187,10 +2190,14 @@ static enum dc_status enable_link_dp(struct dc_state *state, if (link->dpcd_sink_ext_caps.bits.oled == 1 || link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1 || link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1) { - set_default_brightness_aux(link); - if (link->dpcd_sink_ext_caps.bits.oled == 1) - msleep(bl_oled_enable_delay); - edp_backlight_enable_aux(link, true); + if (!stream->sink_patches.oled_optimize_display_on) { + set_default_brightness_aux(link); + if (link->dpcd_sink_ext_caps.bits.oled == 1) + msleep(bl_oled_enable_delay); + edp_backlight_enable_aux(link, true); + } else { + edp_backlight_enable_aux(link, true); + } } return status; From 2bca6d333c95c284f54a299a80f0264730bab180 Mon Sep 17 00:00:00 2001 From: Dillon Varone Date: Fri, 11 Oct 2024 13:51:11 -0400 Subject: [PATCH 1823/1868] drm/amd/display: Add P-State Stall Timeout Recovery Support for dcn401 [WHY&HOW] Adds support for P-State stall timeout detection in DCHUBBUB. Reviewed-by: Alvin Lee Signed-off-by: Dillon Varone Signed-off-by: Tom Chung Tested-by: Daniel Wheeler (cherry picked from commit c48a1a4f0de94dfe2e6d447598d08a66433cf3ba) Signed-off-by: Alex Hung --- .../dc/dml2/dml21/inc/dml_top_dchub_registers.h | 1 + .../dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c | 3 +++ .../drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h | 9 ++++++++- .../drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c | 12 ++++++++++++ .../drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.h | 8 ++++++-- .../drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 5 +++++ drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h | 1 + .../amd/display/dc/resource/dcn401/dcn401_resource.h | 4 +++- 8 files changed, 39 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h b/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h index 83fc15bf13cf7..25b607e7b726e 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/dml_top_dchub_registers.h @@ -88,6 +88,7 @@ struct dml2_display_arb_regs { uint32_t sdpif_request_rate_limit; uint32_t allow_sdpif_rate_limit_when_cstate_req; uint32_t dcfclk_deep_sleep_hysteresis; + uint32_t pstate_stall_threshold; }; struct dml2_cursor_dlg_regs{ diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c index 3ea54fd52e468..92e43a1e4dd46 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c @@ -12236,6 +12236,8 @@ static void rq_dlg_get_dlg_reg( static void rq_dlg_get_arb_params(const struct dml2_display_cfg *display_cfg, const struct dml2_core_internal_display_mode_lib *mode_lib, struct dml2_display_arb_regs *arb_param) { + double refclk_freq_in_mhz = (display_cfg->overrides.hw.dlg_ref_clk_mhz > 0) ? (double)display_cfg->overrides.hw.dlg_ref_clk_mhz : mode_lib->soc.dchub_refclk_mhz; + arb_param->max_req_outstanding = mode_lib->soc.max_outstanding_reqs; arb_param->min_req_outstanding = mode_lib->soc.max_outstanding_reqs; // turn off the sat level feature if this set to max arb_param->sdpif_request_rate_limit = (3 * mode_lib->ip.words_per_channel * mode_lib->soc.clk_table.dram_config.channel_count) / 4; @@ -12247,6 +12249,7 @@ static void rq_dlg_get_arb_params(const struct dml2_display_cfg *display_cfg, co arb_param->compbuf_size = mode_lib->mp.CompressedBufferSizeInkByte / mode_lib->ip.compressed_buffer_segment_size_in_kbytes; arb_param->allow_sdpif_rate_limit_when_cstate_req = dml_get_hw_debug5(mode_lib); arb_param->dcfclk_deep_sleep_hysteresis = dml_get_dcfclk_deep_sleep_hysteresis(mode_lib); + arb_param->pstate_stall_threshold = (unsigned int)(mode_lib->ip_caps.fams2.max_allow_delay_us * refclk_freq_in_mhz); #ifdef __DML_VBA_DEBUG__ dml2_printf("DML::%s: max_req_outstanding = %d\n", __func__, arb_param->max_req_outstanding); diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h b/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h index a1e2cde9c4cca..4bd1dda077196 100644 --- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h +++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h @@ -198,6 +198,8 @@ struct dcn_hubbub_registers { uint32_t DCHUBBUB_ARB_REFCYC_PER_META_TRIP_B; uint32_t DCHUBBUB_ARB_FRAC_URG_BW_MALL_A; uint32_t DCHUBBUB_ARB_FRAC_URG_BW_MALL_B; + uint32_t DCHUBBUB_TIMEOUT_DETECTION_CTRL1; + uint32_t DCHUBBUB_TIMEOUT_DETECTION_CTRL2; }; #define HUBBUB_REG_FIELD_LIST_DCN32(type) \ @@ -313,7 +315,12 @@ struct dcn_hubbub_registers { type DCN_VM_ERROR_VMID;\ type DCN_VM_ERROR_TABLE_LEVEL;\ type DCN_VM_ERROR_PIPE;\ - type DCN_VM_ERROR_INTERRUPT_STATUS + type DCN_VM_ERROR_INTERRUPT_STATUS;\ + type DCHUBBUB_TIMEOUT_ERROR_STATUS;\ + type DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD;\ + type DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD;\ + type DCHUBBUB_TIMEOUT_DETECTION_EN;\ + type DCHUBBUB_TIMEOUT_TIMER_RESET #define HUBBUB_STUTTER_REG_FIELD_LIST(type) \ type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A;\ diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c index 37d26fa0b6fbb..5d658e9bef640 100644 --- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c +++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c @@ -1192,6 +1192,17 @@ static void dcn401_wait_for_det_update(struct hubbub *hubbub, int hubp_inst) } } +static void dcn401_program_timeout_thresholds(struct hubbub *hubbub, struct dml2_display_arb_regs *arb_regs) +{ + struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); + + /* request backpressure and outstanding return threshold (unused)*/ + //REG_UPDATE(DCHUBBUB_TIMEOUT_DETECTION_CTRL1, DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD, arb_regs->req_stall_threshold); + + /* P-State stall threshold */ + REG_UPDATE(DCHUBBUB_TIMEOUT_DETECTION_CTRL2, DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD, arb_regs->pstate_stall_threshold); +} + static const struct hubbub_funcs hubbub4_01_funcs = { .update_dchub = hubbub2_update_dchub, .init_dchub_sys_ctx = hubbub3_init_dchub_sys_ctx, @@ -1215,6 +1226,7 @@ static const struct hubbub_funcs hubbub4_01_funcs = { .program_det_segments = dcn401_program_det_segments, .program_compbuf_segments = dcn401_program_compbuf_segments, .wait_for_det_update = dcn401_wait_for_det_update, + .program_timeout_thresholds = dcn401_program_timeout_thresholds, }; void hubbub401_construct(struct dcn20_hubbub *hubbub2, diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.h b/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.h index f35f19ba3e18b..5f1960722ebdd 100644 --- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.h +++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.h @@ -123,8 +123,12 @@ HUBBUB_SF(DCHUBBUB_CLOCK_CNTL, DCFCLK_R_DCHUBBUB_GATE_DIS, mask_sh),\ HUBBUB_SF(DCHUBBUB_SDPIF_CFG0, SDPIF_PORT_CONTROL, mask_sh),\ HUBBUB_SF(DCHUBBUB_SDPIF_CFG1, SDPIF_MAX_NUM_OUTSTANDING, mask_sh),\ - HUBBUB_SF(DCHUBBUB_MEM_PWR_MODE_CTRL, DET_MEM_PWR_LS_MODE, mask_sh) - + HUBBUB_SF(DCHUBBUB_MEM_PWR_MODE_CTRL, DET_MEM_PWR_LS_MODE, mask_sh),\ + HUBBUB_SF(DCHUBBUB_TIMEOUT_DETECTION_CTRL1, DCHUBBUB_TIMEOUT_ERROR_STATUS, mask_sh),\ + HUBBUB_SF(DCHUBBUB_TIMEOUT_DETECTION_CTRL1, DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD, mask_sh),\ + HUBBUB_SF(DCHUBBUB_TIMEOUT_DETECTION_CTRL2, DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD, mask_sh),\ + HUBBUB_SF(DCHUBBUB_TIMEOUT_DETECTION_CTRL2, DCHUBBUB_TIMEOUT_DETECTION_EN, mask_sh),\ + HUBBUB_SF(DCHUBBUB_TIMEOUT_DETECTION_CTRL2, DCHUBBUB_TIMEOUT_TIMER_RESET, mask_sh) bool hubbub401_program_urgent_watermarks( struct hubbub *hubbub, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c index 49a37f5ee28e7..b0b2b195e7d80 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c @@ -1549,6 +1549,11 @@ void dcn401_optimize_bandwidth( pipe_ctx->dlg_regs.min_dst_y_next_start); } } + + /* update timeout thresholds */ + if (hubbub->funcs->program_timeout_thresholds) { + hubbub->funcs->program_timeout_thresholds(hubbub, &context->bw_ctx.bw.dcn.arb_regs); + } } void dcn401_fams2_global_control_lock(struct dc *dc, diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h index 67c32401893e8..6c1d41c0f0992 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h @@ -228,6 +228,7 @@ struct hubbub_funcs { void (*program_det_segments)(struct hubbub *hubbub, int hubp_inst, unsigned det_buffer_size_seg); void (*program_compbuf_segments)(struct hubbub *hubbub, unsigned compbuf_size_seg, bool safe_to_increase); void (*wait_for_det_update)(struct hubbub *hubbub, int hubp_inst); + void (*program_timeout_thresholds)(struct hubbub *hubbub, struct dml2_display_arb_regs *arb_regs); }; struct hubbub { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h index bdafa7496ceae..7c8d61db153d3 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h @@ -610,7 +610,9 @@ void dcn401_prepare_mcache_programming(struct dc *dc, struct dc_state *context); SR(DCHUBBUB_CLOCK_CNTL), \ SR(DCHUBBUB_SDPIF_CFG0), \ SR(DCHUBBUB_SDPIF_CFG1), \ - SR(DCHUBBUB_MEM_PWR_MODE_CTRL) + SR(DCHUBBUB_MEM_PWR_MODE_CTRL), \ + SR(DCHUBBUB_TIMEOUT_DETECTION_CTRL1), \ + SR(DCHUBBUB_TIMEOUT_DETECTION_CTRL2) /* DCCG */ From f0d9fd416fb47a4b3f5d6e8c26db2a4d54ef7916 Mon Sep 17 00:00:00 2001 From: Dillon Varone Date: Wed, 25 Sep 2024 20:18:07 -0400 Subject: [PATCH 1824/1868] drm/amd/display: resolve correct MALL size for dcn401 [WHY] Code for dcn401 to calculate available MALL size for display was shared with dcn32 and did not provide the correct result for all ASICs. [HOW] Add dcn401 specific function to properly calculate the available MALL for display. Reviewed-by: Chris Park Signed-off-by: Dillon Varone Signed-off-by: Roman Li Tested-by: Daniel Wheeler (cherry picked from commit 4a7f6834238bca9cee93bd8bddf8dc0d21cd68c4) Signed-off-by: Alex Hung --- .../dc/resource/dcn32/dcn32_resource.c | 4 +++ .../dc/resource/dcn401/dcn401_resource.c | 27 ++++++++++++++++--- 2 files changed, 28 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c index a124ad9bd108c..f758d463e460e 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c @@ -1990,6 +1990,10 @@ unsigned int dcn32_calculate_mall_ways_from_bytes(const struct dc *dc, unsigned return 0; } + if (dc->caps.max_cab_allocation_bytes == 0) { + return 0xffffffff; + } + /* add 2 lines for worst case alignment */ cache_lines_used = total_size_in_mall_bytes / dc->caps.cache_line_size + 2; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c index 2a71611da2e70..46feff9348d96 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c @@ -1704,6 +1704,29 @@ static int dcn401_get_power_profile(const struct dc_state *context) return dpm_level; } +static unsigned int dcn401_calc_num_avail_chans_for_mall(struct dc *dc, unsigned int num_chans) +{ + unsigned int num_available_chans = 1; + + /* channels for MALL must be a power of 2 */ + while (num_chans > 1) { + num_available_chans = (num_available_chans << 1); + num_chans = (num_chans >> 1); + } + + /* cannot be odd */ + num_available_chans &= ~1; + + /* clamp to max available channels for MALL per ASIC */ + if (ASICREV_IS_GC_12_0_0_A0(dc->ctx->asic_id.hw_internal_rev)) { + num_available_chans = num_available_chans > 16 ? 16 : num_available_chans; + } else if (ASICREV_IS_GC_12_0_1_A0(dc->ctx->asic_id.hw_internal_rev)) { + num_available_chans = num_available_chans > 8 ? 8 : num_available_chans; + } + + return num_available_chans; +} + static struct resource_funcs dcn401_res_pool_funcs = { .destroy = dcn401_destroy_resource_pool, .link_enc_create = dcn401_link_encoder_create, @@ -1812,14 +1835,12 @@ static bool dcn401_resource_construct( dc->caps.min_horizontal_blanking_period = 80; dc->caps.dmdata_alloc_size = 2048; dc->caps.mall_size_per_mem_channel = 4; - /* total size = mall per channel * num channels * 1024 * 1024 */ - dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576; dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8; dc->caps.cache_line_size = 64; dc->caps.cache_num_ways = 16; /* Calculate the available MALL space */ - dc->caps.max_cab_allocation_bytes = dcn32_calc_num_avail_chans_for_mall( + dc->caps.max_cab_allocation_bytes = dcn401_calc_num_avail_chans_for_mall( dc, dc->ctx->dc_bios->vram_info.num_chans) * dc->caps.mall_size_per_mem_channel * 1024 * 1024; dc->caps.mall_size_total = dc->caps.max_cab_allocation_bytes; From 8e9b1be6aa274fe60922a3d6beb387cc10294f6e Mon Sep 17 00:00:00 2001 From: Austin Zheng Date: Fri, 18 Oct 2024 14:55:21 -0400 Subject: [PATCH 1825/1868] drm/amd/display: Do Not Fallback To SW Cursor If HW Cursor Required [Why/How] Tearing can occur if there is a flip immediate plane and SW cursor. check_subvp_sw_cursor_fallback_req falls back to SW cursor if the stream has the potential to use subVP. Check for fallback not needed if HW cursor is required. e.g. Fullscreen gaming Reviewed-by: Dillon Varone Signed-off-by: Austin Zheng Signed-off-by: Zaeem Mohamed Tested-by: Daniel Wheeler (cherry picked from commit 1204337d11ca5465adb341d3b2da3b860cd5b3ee) Signed-off-by: Alex Hung --- drivers/gpu/drm/amd/display/dc/core/dc_stream.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c index b000bf39762f0..aca2821d546b1 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c @@ -290,7 +290,9 @@ bool dc_stream_set_cursor_attributes( * 2. If not subvp high refresh, for single display cases, if resolution is >= 5K and refresh rate < 120hz * 3. If not subvp high refresh, for multi display cases, if resolution is >= 4K and refresh rate < 120hz */ - if (dc->debug.allow_sw_cursor_fallback && attributes->height * attributes->width * 4 > 16384) { + if (dc->debug.allow_sw_cursor_fallback && + attributes->height * attributes->width * 4 > 16384 && + !stream->hw_cursor_req) { if (check_subvp_sw_cursor_fallback_req(dc, stream)) return false; } From 91ec05174327fd7f854db1e3495cec76e01c0e54 Mon Sep 17 00:00:00 2001 From: Ausef Yousof Date: Thu, 24 Oct 2024 14:06:39 -0400 Subject: [PATCH 1826/1868] drm/amd/display: Remove hw w/a toggle if on DP2/HPO [why&how] Applying a hw w/a only relevant to DIG FIFO causing corruption using HPO, do not apply the w/a if on DP2/HPO Reviewed-by: Charlene Liu Signed-off-by: Ausef Yousof Signed-off-by: Zaeem Mohamed Tested-by: Daniel Wheeler (cherry picked from commit c9b267cb191f5a5e2d4090b9b9862634750edcda) Signed-off-by: Alex Hung --- .../drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c index 7d68006137a97..3bd0d46c17010 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c @@ -132,6 +132,8 @@ static void dcn35_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state * for (i = 0; i < dc->res_pool->pipe_count; ++i) { struct pipe_ctx *old_pipe = &dc->current_state->res_ctx.pipe_ctx[i]; struct pipe_ctx *new_pipe = &context->res_ctx.pipe_ctx[i]; + struct clk_mgr_internal *clk_mgr_internal = TO_CLK_MGR_INTERNAL(clk_mgr_base); + struct dccg *dccg = clk_mgr_internal->dccg; struct pipe_ctx *pipe = safe_to_lower ? &context->res_ctx.pipe_ctx[i] : &dc->current_state->res_ctx.pipe_ctx[i]; @@ -148,8 +150,13 @@ static void dcn35_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state * new_pipe->stream_res.stream_enc && new_pipe->stream_res.stream_enc->funcs->is_fifo_enabled && new_pipe->stream_res.stream_enc->funcs->is_fifo_enabled(new_pipe->stream_res.stream_enc); - if (pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal) || - !pipe->stream->link_enc) && !stream_changed_otg_dig_on) { + bool has_active_hpo = dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(old_pipe) && dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(new_pipe); + + if (!has_active_hpo && !dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe) && + (pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal) || + !pipe->stream->link_enc) && !stream_changed_otg_dig_on)) { + + /* This w/a should not trigger when we have a dig active */ if (disable) { if (pipe->stream_res.tg && pipe->stream_res.tg->funcs->immediate_disable_crtc) From 28850c27c4dc197365235b14f3435cc9155c96a2 Mon Sep 17 00:00:00 2001 From: Ausef Yousof Date: Thu, 24 Oct 2024 15:17:20 -0400 Subject: [PATCH 1827/1868] drm/amd/display: Remove otg w/a toggling on HPO interfaces [why&how] Adjust otg w/a disable condition to include HPO explicitly rather than assuming it is implicitly used through DP2. Reviewed-by: Charlene Liu Signed-off-by: Ausef Yousof Signed-off-by: Zaeem Mohamed Tested-by: Daniel Wheeler (cherry picked from commit 63d36cdea42fd8610ae123c405cb33534a5b023c) Signed-off-by: Alex Hung --- .../drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c index 3bd0d46c17010..734c0819bb3f3 100644 --- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c +++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c @@ -150,7 +150,15 @@ static void dcn35_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state * new_pipe->stream_res.stream_enc && new_pipe->stream_res.stream_enc->funcs->is_fifo_enabled && new_pipe->stream_res.stream_enc->funcs->is_fifo_enabled(new_pipe->stream_res.stream_enc); - bool has_active_hpo = dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(old_pipe) && dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(new_pipe); + + bool has_active_hpo = false; + + if (old_pipe->stream && new_pipe->stream && old_pipe->stream == new_pipe->stream) { + has_active_hpo = dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(old_pipe) && + dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(new_pipe); + + } + if (!has_active_hpo && !dccg->ctx->dc->link_srv->dp_is_128b_132b_signal(pipe) && (pipe->stream && (pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal) || From 627f8902a961693b39445cee090d35ad654065d1 Mon Sep 17 00:00:00 2001 From: Ilya Bakoulin Date: Wed, 9 Oct 2024 15:26:48 -0400 Subject: [PATCH 1828/1868] drm/amd/display: Minimize wait for pending updates [Why/How] Move the wait for pending updates past prepare_bandwidth if the previous update was not a full update to reduce the average time it takes to complete a full update. Reviewed-by: Dillon Varone Reviewed-by: Alvin Lee Signed-off-by: Ilya Bakoulin Signed-off-by: Zaeem Mohamed Tested-by: Daniel Wheeler (cherry picked from commit 022f0d692c8bccf51b10f2ac4ea6341c646a0986) Signed-off-by: Alex Hung --- drivers/gpu/drm/amd/display/dc/core/dc.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index e5ebb5aa89a7f..74719ea4a858a 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -3822,7 +3822,7 @@ static void commit_planes_for_stream(struct dc *dc, dc_exit_ips_for_hw_access(dc); dc_z10_restore(dc); - if (update_type == UPDATE_TYPE_FULL) + if (update_type == UPDATE_TYPE_FULL && dc->optimized_required) hwss_process_outstanding_hw_updates(dc, dc->current_state); for (i = 0; i < dc->res_pool->pipe_count; i++) { @@ -3849,6 +3849,9 @@ static void commit_planes_for_stream(struct dc *dc, context_clock_trace(dc, context); } + if (update_type == UPDATE_TYPE_FULL) + hwss_wait_for_outstanding_hw_updates(dc, dc->current_state); + top_pipe_to_program = resource_get_otg_master_for_stream( &context->res_ctx, stream); From 09b0aa80bed6a6bad39f5daf2c2f595441d1474b Mon Sep 17 00:00:00 2001 From: Victor Skvortsov Date: Wed, 30 Oct 2024 09:33:51 -0400 Subject: [PATCH 1829/1868] drm/amdgpu: Update SRIOV Exchange Headers for RAS Telemetry Support The SRIOV PF/VF Data exchange is extended by 64KB for VF RAS Telemetry data. Add Host RAS Telemetry enable capabilities bitfields. Add a new VF msg REQ_RAS_ERROR_COUNT, the host response data will be populated in the RAS Telemetry region. Signed-off-by: Victor Skvortsov Reviewed-by: Zhigang Luo --- drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h | 131 +++++++++++++++++--- drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h | 3 + 2 files changed, 115 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h b/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h index 6e9eeaeb3de1d..b4f9c2f4e92cc 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h @@ -28,17 +28,21 @@ #define AMD_SRIOV_MSG_VBIOS_SIZE_KB 64 #define AMD_SRIOV_MSG_DATAEXCHANGE_OFFSET_KB AMD_SRIOV_MSG_VBIOS_SIZE_KB #define AMD_SRIOV_MSG_DATAEXCHANGE_SIZE_KB 4 - +#define AMD_SRIOV_MSG_TMR_OFFSET_KB 2048 +#define AMD_SRIOV_MSG_BAD_PAGE_SIZE_KB 2 +#define AMD_SRIOV_RAS_TELEMETRY_SIZE_KB 64 /* * layout - * 0 64KB 65KB 66KB - * | VBIOS | PF2VF | VF2PF | Bad Page | ... - * | 64KB | 1KB | 1KB | + * 0 64KB 65KB 66KB 68KB 132KB + * | VBIOS | PF2VF | VF2PF | Bad Page | RAS Telemetry Region | ... + * | 64KB | 1KB | 1KB | 2KB | 64KB | ... */ + #define AMD_SRIOV_MSG_SIZE_KB 1 #define AMD_SRIOV_MSG_PF2VF_OFFSET_KB AMD_SRIOV_MSG_DATAEXCHANGE_OFFSET_KB #define AMD_SRIOV_MSG_VF2PF_OFFSET_KB (AMD_SRIOV_MSG_PF2VF_OFFSET_KB + AMD_SRIOV_MSG_SIZE_KB) #define AMD_SRIOV_MSG_BAD_PAGE_OFFSET_KB (AMD_SRIOV_MSG_VF2PF_OFFSET_KB + AMD_SRIOV_MSG_SIZE_KB) +#define AMD_SRIOV_MSG_RAS_TELEMETRY_OFFSET_KB (AMD_SRIOV_MSG_BAD_PAGE_OFFSET_KB + AMD_SRIOV_MSG_BAD_PAGE_SIZE_KB) /* * PF2VF history log: @@ -86,30 +90,59 @@ enum amd_sriov_ucode_engine_id { union amd_sriov_msg_feature_flags { struct { - uint32_t error_log_collect : 1; - uint32_t host_load_ucodes : 1; - uint32_t host_flr_vramlost : 1; - uint32_t mm_bw_management : 1; - uint32_t pp_one_vf_mode : 1; - uint32_t reg_indirect_acc : 1; - uint32_t av1_support : 1; - uint32_t vcn_rb_decouple : 1; - uint32_t mes_info_enable : 1; - uint32_t reserved : 23; + uint32_t error_log_collect : 1; + uint32_t host_load_ucodes : 1; + uint32_t host_flr_vramlost : 1; + uint32_t mm_bw_management : 1; + uint32_t pp_one_vf_mode : 1; + uint32_t reg_indirect_acc : 1; + uint32_t av1_support : 1; + uint32_t vcn_rb_decouple : 1; + uint32_t mes_info_dump_enable : 1; + uint32_t ras_caps : 1; + uint32_t ras_telemetry : 1; + uint32_t reserved : 21; } flags; uint32_t all; }; union amd_sriov_reg_access_flags { struct { - uint32_t vf_reg_access_ih : 1; - uint32_t vf_reg_access_mmhub : 1; - uint32_t vf_reg_access_gc : 1; - uint32_t reserved : 29; + uint32_t vf_reg_access_ih : 1; + uint32_t vf_reg_access_mmhub : 1; + uint32_t vf_reg_access_gc : 1; + uint32_t reserved : 29; } flags; uint32_t all; }; +union amd_sriov_ras_caps { + struct { + uint64_t block_umc : 1; + uint64_t block_sdma : 1; + uint64_t block_gfx : 1; + uint64_t block_mmhub : 1; + uint64_t block_athub : 1; + uint64_t block_pcie_bif : 1; + uint64_t block_hdp : 1; + uint64_t block_xgmi_wafl : 1; + uint64_t block_df : 1; + uint64_t block_smn : 1; + uint64_t block_sem : 1; + uint64_t block_mp0 : 1; + uint64_t block_mp1 : 1; + uint64_t block_fuse : 1; + uint64_t block_mca : 1; + uint64_t block_vcn : 1; + uint64_t block_jpeg : 1; + uint64_t block_ih : 1; + uint64_t block_mpio : 1; + uint64_t poison_propogation_mode : 1; + uint64_t reserved : 44; + } bits; + uint64_t all; +}; + union amd_sriov_msg_os_info { struct { uint32_t windows : 1; @@ -158,7 +191,7 @@ struct amd_sriov_msg_pf2vf_info_header { uint32_t reserved[2]; }; -#define AMD_SRIOV_MSG_PF2VF_INFO_FILLED_SIZE (49) +#define AMD_SRIOV_MSG_PF2VF_INFO_FILLED_SIZE (55) struct amd_sriov_msg_pf2vf_info { /* header contains size and version */ struct amd_sriov_msg_pf2vf_info_header header; @@ -211,6 +244,12 @@ struct amd_sriov_msg_pf2vf_info { uint32_t pcie_atomic_ops_support_flags; /* Portion of GPU memory occupied by VF. MAX value is 65535, but set to uint32_t to maintain alignment with reserved size */ uint32_t gpu_capacity; + /* vf bdf on host pci tree for debug only */ + uint32_t bdf_on_host; + uint32_t more_bp; //Reserved for future use. + union amd_sriov_ras_caps ras_en_caps; + union amd_sriov_ras_caps ras_telemetry_en_caps; + /* reserved */ uint32_t reserved[256 - AMD_SRIOV_MSG_PF2VF_INFO_FILLED_SIZE]; } __packed; @@ -283,8 +322,12 @@ enum amd_sriov_mailbox_request_message { MB_REQ_MSG_REL_GPU_FINI_ACCESS, MB_REQ_MSG_REQ_GPU_RESET_ACCESS, MB_REQ_MSG_REQ_GPU_INIT_DATA, + MB_REQ_MSG_PSP_VF_CMD_RELAY, MB_REQ_MSG_LOG_VF_ERROR = 200, + MB_REQ_MSG_READY_TO_RESET = 201, + MB_REQ_MSG_RAS_POISON = 202, + MB_REQ_RAS_ERROR_COUNT = 203, }; /* mailbox message send from host to guest */ @@ -297,10 +340,60 @@ enum amd_sriov_mailbox_response_message { MB_RES_MSG_FAIL, MB_RES_MSG_QUERY_ALIVE, MB_RES_MSG_GPU_INIT_DATA_READY, + MB_RES_MSG_RAS_ERROR_COUNT_READY = 11, MB_RES_MSG_TEXT_MESSAGE = 255 }; +enum amd_sriov_ras_telemetry_gpu_block { + RAS_TELEMETRY_GPU_BLOCK_UMC = 0, + RAS_TELEMETRY_GPU_BLOCK_SDMA = 1, + RAS_TELEMETRY_GPU_BLOCK_GFX = 2, + RAS_TELEMETRY_GPU_BLOCK_MMHUB = 3, + RAS_TELEMETRY_GPU_BLOCK_ATHUB = 4, + RAS_TELEMETRY_GPU_BLOCK_PCIE_BIF = 5, + RAS_TELEMETRY_GPU_BLOCK_HDP = 6, + RAS_TELEMETRY_GPU_BLOCK_XGMI_WAFL = 7, + RAS_TELEMETRY_GPU_BLOCK_DF = 8, + RAS_TELEMETRY_GPU_BLOCK_SMN = 9, + RAS_TELEMETRY_GPU_BLOCK_SEM = 10, + RAS_TELEMETRY_GPU_BLOCK_MP0 = 11, + RAS_TELEMETRY_GPU_BLOCK_MP1 = 12, + RAS_TELEMETRY_GPU_BLOCK_FUSE = 13, + RAS_TELEMETRY_GPU_BLOCK_MCA = 14, + RAS_TELEMETRY_GPU_BLOCK_VCN = 15, + RAS_TELEMETRY_GPU_BLOCK_JPEG = 16, + RAS_TELEMETRY_GPU_BLOCK_IH = 17, + RAS_TELEMETRY_GPU_BLOCK_MPIO = 18, + RAS_TELEMETRY_GPU_BLOCK_COUNT = 19, +}; + +struct amd_sriov_ras_telemetry_header { + uint32_t checksum; + uint32_t used_size; + uint32_t reserved[2]; +}; + +struct amd_sriov_ras_telemetry_error_count { + struct { + uint32_t ce_count; + uint32_t ue_count; + uint32_t de_count; + uint32_t ce_overflow_count; + uint32_t ue_overflow_count; + uint32_t de_overflow_count; + uint32_t reserved[6]; + } block[RAS_TELEMETRY_GPU_BLOCK_COUNT]; +}; + +struct amdsriov_ras_telemetry { + struct amd_sriov_ras_telemetry_header header; + + union { + struct amd_sriov_ras_telemetry_error_count error_count; + } body; +}; + /* version data stored in MAILBOX_MSGBUF_RCV_DW1 for future expansion */ enum amd_sriov_gpu_init_data_version { GPU_INIT_DATA_READY_V1 = 1, diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h b/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h index 1d099ffb3a5a2..9d61d76e1bf96 100644 --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.h @@ -40,6 +40,7 @@ enum idh_request { IDH_LOG_VF_ERROR = 200, IDH_READY_TO_RESET = 201, IDH_RAS_POISON = 202, + IDH_REQ_RAS_ERROR_COUNT = 203, }; enum idh_event { @@ -54,6 +55,8 @@ enum idh_event { IDH_RAS_POISON_READY, IDH_PF_SOFT_FLR_NOTIFICATION, IDH_RAS_ERROR_DETECTED, + IDH_RAS_ERROR_COUNT_READY = 11, + IDH_TEXT_MESSAGE = 255, }; From 4342e53dc595975dabd531475ac3b9a1e0a2b4f4 Mon Sep 17 00:00:00 2001 From: Victor Skvortsov Date: Wed, 30 Oct 2024 09:45:27 -0400 Subject: [PATCH 1830/1868] drm/amdgpu: Add msg handlers for SRIOV RAS Telemetry Signed-off-by: Victor Skvortsov Reviewed-by: Zhigang Luo --- drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 1 + drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c | 16 ++++++++++++++-- 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h index b650a2032c42b..f6eee57338df8 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h @@ -95,6 +95,7 @@ struct amdgpu_virt_ops { void (*ras_poison_handler)(struct amdgpu_device *adev, enum amdgpu_ras_block block); bool (*rcvd_ras_intr)(struct amdgpu_device *adev); + int (*req_ras_err_count)(struct amdgpu_device *adev); }; /* diff --git a/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c b/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c index f47bd7ada4d79..4dcb72d1bdda2 100644 --- a/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c +++ b/drivers/gpu/drm/amd/amdgpu/mxgpu_nv.c @@ -61,15 +61,18 @@ static enum idh_event xgpu_nv_mailbox_peek_msg(struct amdgpu_device *adev) static int xgpu_nv_mailbox_rcv_msg(struct amdgpu_device *adev, enum idh_event event) { + int r = 0; u32 reg; reg = RREG32_NO_KIQ(mmMAILBOX_MSGBUF_RCV_DW0); - if (reg != event) + if (reg == IDH_FAIL) + r = -EINVAL; + else if (reg != event) return -ENOENT; xgpu_nv_mailbox_send_ack(adev); - return 0; + return r; } static uint8_t xgpu_nv_peek_ack(struct amdgpu_device *adev) @@ -178,6 +181,9 @@ static int xgpu_nv_send_access_requests_with_param(struct amdgpu_device *adev, if (data1 != 0) event = IDH_RAS_POISON_READY; break; + case IDH_REQ_RAS_ERROR_COUNT: + event = IDH_RAS_ERROR_COUNT_READY; + break; default: break; } @@ -456,6 +462,11 @@ static bool xgpu_nv_rcvd_ras_intr(struct amdgpu_device *adev) return (msg == IDH_RAS_ERROR_DETECTED || msg == 0xFFFFFFFF); } +static int xgpu_nv_req_ras_err_count(struct amdgpu_device *adev) +{ + return xgpu_nv_send_access_requests(adev, IDH_REQ_RAS_ERROR_COUNT); +} + const struct amdgpu_virt_ops xgpu_nv_virt_ops = { .req_full_gpu = xgpu_nv_request_full_gpu_access, .rel_full_gpu = xgpu_nv_release_full_gpu_access, @@ -466,4 +477,5 @@ const struct amdgpu_virt_ops xgpu_nv_virt_ops = { .trans_msg = xgpu_nv_mailbox_trans_msg, .ras_poison_handler = xgpu_nv_ras_poison_handler, .rcvd_ras_intr = xgpu_nv_rcvd_ras_intr, + .req_ras_err_count = xgpu_nv_req_ras_err_count, }; From 79b98d569b5cab0f020a662ecb6821987c283896 Mon Sep 17 00:00:00 2001 From: Victor Skvortsov Date: Wed, 30 Oct 2024 09:58:56 -0400 Subject: [PATCH 1831/1868] drm/amdgpu: VF Query RAS Caps from Host if supported If VF RAS Capability support is enabled, guest is able to retrieve the real RAS support from the host. Signed-off-by: Victor Skvortsov Reviewed-by: Zhigang Luo --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 5 +++ drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 53 ++++++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 7 ++++ 3 files changed, 65 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 5307012f6de7d..d3f22a4f724b6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -3467,6 +3467,11 @@ static void amdgpu_ras_check_supported(struct amdgpu_device *adev) if (!amdgpu_ras_asic_supported(adev)) return; + if (amdgpu_sriov_vf(adev)) { + if (amdgpu_virt_get_ras_capability(adev)) + goto init_ras_enabled_flag; + } + /* query ras capability from psp */ if (amdgpu_psp_get_ras_capability(&adev->psp)) goto init_ras_enabled_flag; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c index b6397d3229e1b..53297c40f09c7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c @@ -523,6 +523,7 @@ static int amdgpu_virt_read_pf2vf_data(struct amdgpu_device *adev) adev->unique_id = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->uuid; + adev->virt.ras_en_caps.all = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->ras_en_caps.all; break; default: dev_err(adev->dev, "invalid pf2vf version: 0x%x\n", pf2vf_info->version); @@ -1144,3 +1145,55 @@ bool amdgpu_sriov_xnack_support(struct amdgpu_device *adev) return xnack_mode; } + +bool amdgpu_virt_get_ras_capability(struct amdgpu_device *adev) +{ + struct amdgpu_ras *con = amdgpu_ras_get_context(adev); + + if (!amdgpu_sriov_ras_caps_en(adev)) + return false; + + if (adev->virt.ras_en_caps.bits.block_umc) + adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__UMC); + if (adev->virt.ras_en_caps.bits.block_sdma) + adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__SDMA); + if (adev->virt.ras_en_caps.bits.block_gfx) + adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__GFX); + if (adev->virt.ras_en_caps.bits.block_mmhub) + adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__MMHUB); + if (adev->virt.ras_en_caps.bits.block_athub) + adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__ATHUB); + if (adev->virt.ras_en_caps.bits.block_pcie_bif) + adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__PCIE_BIF); + if (adev->virt.ras_en_caps.bits.block_hdp) + adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__HDP); + if (adev->virt.ras_en_caps.bits.block_xgmi_wafl) + adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__XGMI_WAFL); + if (adev->virt.ras_en_caps.bits.block_df) + adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__DF); + if (adev->virt.ras_en_caps.bits.block_smn) + adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__SMN); + if (adev->virt.ras_en_caps.bits.block_sem) + adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__SEM); + if (adev->virt.ras_en_caps.bits.block_mp0) + adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__MP0); + if (adev->virt.ras_en_caps.bits.block_mp1) + adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__MP1); + if (adev->virt.ras_en_caps.bits.block_fuse) + adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__FUSE); + if (adev->virt.ras_en_caps.bits.block_mca) + adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__MCA); + if (adev->virt.ras_en_caps.bits.block_vcn) + adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__VCN); + if (adev->virt.ras_en_caps.bits.block_jpeg) + adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__JPEG); + if (adev->virt.ras_en_caps.bits.block_ih) + adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__IH); + if (adev->virt.ras_en_caps.bits.block_mpio) + adev->ras_hw_enabled |= BIT(AMDGPU_RAS_BLOCK__MPIO); + + if (adev->virt.ras_en_caps.bits.poison_propogation_mode) + con->poison_supported = true; /* Poison is handled by host */ + + return true; +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h index f6eee57338df8..f0ff84add6926 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h @@ -137,6 +137,7 @@ enum AMDGIM_FEATURE_FLAG { AMDGIM_FEATURE_VCN_RB_DECOUPLE = (1 << 7), /* MES info */ AMDGIM_FEATURE_MES_INFO_ENABLE = (1 << 8), + AMDGIM_FEATURE_RAS_CAPS = (1 << 9), }; enum AMDGIM_REG_ACCESS_FLAG { @@ -277,6 +278,8 @@ struct amdgpu_virt { uint32_t autoload_ucode_id; struct mutex rlcg_reg_lock; + + union amd_sriov_ras_caps ras_en_caps; }; struct amdgpu_video_codec_info; @@ -321,6 +324,9 @@ struct amdgpu_video_codec_info; #define amdgpu_sriov_vf_mmio_access_protection(adev) \ ((adev)->virt.caps & AMDGPU_VF_MMIO_ACCESS_PROTECT) +#define amdgpu_sriov_ras_caps_en(adev) \ +((adev)->virt.gim_feature & AMDGIM_FEATURE_RAS_CAPS) + static inline bool is_virtual_machine(void) { #if defined(CONFIG_X86) @@ -384,4 +390,5 @@ bool amdgpu_virt_get_rlcg_reg_access_flag(struct amdgpu_device *adev, u32 acc_flags, u32 hwip, bool write, u32 *rlcg_flag); u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag, u32 xcc_id); +bool amdgpu_virt_get_ras_capability(struct amdgpu_device *adev); #endif From 60f3e16b67aa8d0393f70e2ff49bb3c9c99e97e3 Mon Sep 17 00:00:00 2001 From: Victor Skvortsov Date: Wed, 30 Oct 2024 10:18:00 -0400 Subject: [PATCH 1832/1868] drm/amdgpu: Implement virt req_ras_err_count Enable RAS late init if VF RAS Telemetry is supported. When enabled, the VF can use this interface to query total RAS error counts from the host. The VF FB access may abruptly end due to a fatal error, therefore the VF must cache and sanitize the input. The Host allows 15 Telemetry messages every 60 seconds, afterwhich the host will ignore any more in-coming telemetry messages. The VF will rate limit its msg calling to once every 5 seconds (12 times in 60 seconds). While the VF is rate limited, it will continue to report the last good cached data. v2: Flip generate report & update statistics order for VF Signed-off-by: Victor Skvortsov Acked-by: Tao Zhou Reviewed-by: Zhigang Luo --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 6 + drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 3 + drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 72 +++++++++-- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c | 3 + drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c | 136 +++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 15 +++ 7 files changed, 229 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index c6763f1ffb582..b765fa840f63d 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -4207,8 +4207,11 @@ int amdgpu_device_init(struct amdgpu_device *adev, * for throttling interrupt) = 60 seconds. */ ratelimit_state_init(&adev->throttling_logging_rs, (60 - 1) * HZ, 1); + ratelimit_state_init(&adev->virt.ras_telemetry_rs, 5 * HZ, 1); + #ifdef RATELIMIT_MSG_ON_RELEASE ratelimit_set_flags(&adev->throttling_logging_rs, RATELIMIT_MSG_ON_RELEASE); + ratelimit_set_flags(&adev->virt.ras_telemetry_rs, RATELIMIT_MSG_ON_RELEASE); #endif /* Registers mapping */ @@ -5178,6 +5181,9 @@ static int amdgpu_device_reset_sriov(struct amdgpu_device *adev, amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) || amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 0, 3)) amdgpu_ras_resume(adev); + + amdgpu_virt_ras_telemetry_post_reset(adev); + return 0; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c index b8cc4b146bdc6..8c9fcfb7f22e2 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c @@ -885,6 +885,9 @@ int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *r if (r) return r; + if (amdgpu_sriov_vf(adev)) + return r; + if (adev->gfx.cp_ecc_error_irq.funcs) { r = amdgpu_irq_get(adev, &adev->gfx.cp_ecc_error_irq, 0); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index d3f22a4f724b6..b91163d6df9e0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -1214,6 +1214,42 @@ static void amdgpu_ras_error_generate_report(struct amdgpu_device *adev, } } +static void amdgpu_ras_virt_error_generate_report(struct amdgpu_device *adev, + struct ras_query_if *query_if, + struct ras_err_data *err_data, + struct ras_query_context *qctx) +{ + unsigned long new_ue, new_ce, new_de; + struct ras_manager *obj = amdgpu_ras_find_obj(adev, &query_if->head); + const char *blk_name = get_ras_block_str(&query_if->head); + u64 event_id = qctx->event_id; + + new_ce = err_data->ce_count - obj->err_data.ce_count; + new_ue = err_data->ue_count - obj->err_data.ue_count; + new_de = err_data->de_count - obj->err_data.de_count; + + if (new_ce) { + RAS_EVENT_LOG(adev, event_id, "%lu correctable hardware errors " + "detected in %s block\n", + new_ce, + blk_name); + } + + if (new_ue) { + RAS_EVENT_LOG(adev, event_id, "%lu uncorrectable hardware errors " + "detected in %s block\n", + new_ue, + blk_name); + } + + if (new_de) { + RAS_EVENT_LOG(adev, event_id, "%lu deferred hardware errors " + "detected in %s block\n", + new_de, + blk_name); + } +} + static void amdgpu_rasmgr_error_data_statistic_update(struct ras_manager *obj, struct ras_err_data *err_data) { struct ras_err_node *err_node; @@ -1237,6 +1273,15 @@ static void amdgpu_rasmgr_error_data_statistic_update(struct ras_manager *obj, s } } +static void amdgpu_ras_mgr_virt_error_data_statistics_update(struct ras_manager *obj, + struct ras_err_data *err_data) +{ + /* Host reports absolute counts */ + obj->err_data.ue_count = err_data->ue_count; + obj->err_data.ce_count = err_data->ce_count; + obj->err_data.de_count = err_data->de_count; +} + static struct ras_manager *get_ras_manager(struct amdgpu_device *adev, enum amdgpu_ras_block blk) { struct ras_common_if head; @@ -1323,7 +1368,9 @@ static int amdgpu_ras_query_error_status_helper(struct amdgpu_device *adev, if (error_query_mode == AMDGPU_RAS_INVALID_ERROR_QUERY) return -EINVAL; - if (error_query_mode == AMDGPU_RAS_DIRECT_ERROR_QUERY) { + if (error_query_mode == AMDGPU_RAS_VIRT_ERROR_COUNT_QUERY) { + return amdgpu_virt_req_ras_err_count(adev, blk, err_data); + } else if (error_query_mode == AMDGPU_RAS_DIRECT_ERROR_QUERY) { if (info->head.block == AMDGPU_RAS_BLOCK__UMC) { amdgpu_ras_get_ecc_info(adev, err_data); } else { @@ -1405,14 +1452,22 @@ static int amdgpu_ras_query_error_status_with_event(struct amdgpu_device *adev, if (ret) goto out_fini_err_data; - amdgpu_rasmgr_error_data_statistic_update(obj, &err_data); + if (error_query_mode != AMDGPU_RAS_VIRT_ERROR_COUNT_QUERY) { + amdgpu_rasmgr_error_data_statistic_update(obj, &err_data); + amdgpu_ras_error_generate_report(adev, info, &err_data, &qctx); + } else { + /* Host provides absolute error counts. First generate the report + * using the previous VF internal count against new host count. + * Then Update VF internal count. + */ + amdgpu_ras_virt_error_generate_report(adev, info, &err_data, &qctx); + amdgpu_ras_mgr_virt_error_data_statistics_update(obj, &err_data); + } info->ue_count = obj->err_data.ue_count; info->ce_count = obj->err_data.ce_count; info->de_count = obj->err_data.de_count; - amdgpu_ras_error_generate_report(adev, info, &err_data, &qctx); - out_fini_err_data: amdgpu_ras_error_data_fini(&err_data); @@ -3944,7 +3999,7 @@ int amdgpu_ras_late_init(struct amdgpu_device *adev) } /* Guest side doesn't need init ras feature */ - if (amdgpu_sriov_vf(adev)) + if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_ras_telemetry_en(adev)) return 0; list_for_each_entry_safe(node, tmp, &adev->ras_list, node) { @@ -4413,11 +4468,14 @@ bool amdgpu_ras_get_error_query_mode(struct amdgpu_device *adev, return false; } - if ((smu_funcs && smu_funcs->set_debug_mode) || (mca_funcs && mca_funcs->mca_set_debug_mode)) + if (amdgpu_sriov_vf(adev)) { + *error_query_mode = AMDGPU_RAS_VIRT_ERROR_COUNT_QUERY; + } else if ((smu_funcs && smu_funcs->set_debug_mode) || (mca_funcs && mca_funcs->mca_set_debug_mode)) { *error_query_mode = (con->is_aca_debug_mode) ? AMDGPU_RAS_DIRECT_ERROR_QUERY : AMDGPU_RAS_FIRMWARE_ERROR_QUERY; - else + } else { *error_query_mode = AMDGPU_RAS_DIRECT_ERROR_QUERY; + } return true; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h index 871b2d6278e07..6db772ecfee47 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h @@ -365,6 +365,7 @@ enum amdgpu_ras_error_query_mode { AMDGPU_RAS_INVALID_ERROR_QUERY = 0, AMDGPU_RAS_DIRECT_ERROR_QUERY = 1, AMDGPU_RAS_FIRMWARE_ERROR_QUERY = 2, + AMDGPU_RAS_VIRT_ERROR_COUNT_QUERY = 3, }; /* ras error status reisger fields */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c index 9e70a7b3aa64f..b9fec295b9a67 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c @@ -322,6 +322,9 @@ int amdgpu_umc_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *r if (r) return r; + if (amdgpu_sriov_vf(adev)) + return r; + if (amdgpu_ras_is_supported(adev, ras_block->block)) { r = amdgpu_irq_get(adev, &adev->gmc.ecc_irq, 0); if (r) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c index 53297c40f09c7..c704e9803e110 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c @@ -524,6 +524,8 @@ static int amdgpu_virt_read_pf2vf_data(struct amdgpu_device *adev) adev->unique_id = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->uuid; adev->virt.ras_en_caps.all = ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->ras_en_caps.all; + adev->virt.ras_telemetry_en_caps.all = + ((struct amd_sriov_msg_pf2vf_info *)pf2vf_info)->ras_telemetry_en_caps.all; break; default: dev_err(adev->dev, "invalid pf2vf version: 0x%x\n", pf2vf_info->version); @@ -704,6 +706,8 @@ void amdgpu_virt_exchange_data(struct amdgpu_device *adev) adev->virt.fw_reserve.p_vf2pf = (struct amd_sriov_msg_vf2pf_info_header *) (adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_VF2PF_OFFSET_KB << 10)); + adev->virt.fw_reserve.ras_telemetry = + (adev->mman.fw_vram_usage_va + (AMD_SRIOV_MSG_RAS_TELEMETRY_OFFSET_KB << 10)); } else if (adev->mman.drv_vram_usage_va) { adev->virt.fw_reserve.p_pf2vf = (struct amd_sriov_msg_pf2vf_info_header *) @@ -711,6 +715,8 @@ void amdgpu_virt_exchange_data(struct amdgpu_device *adev) adev->virt.fw_reserve.p_vf2pf = (struct amd_sriov_msg_vf2pf_info_header *) (adev->mman.drv_vram_usage_va + (AMD_SRIOV_MSG_VF2PF_OFFSET_KB << 10)); + adev->virt.fw_reserve.ras_telemetry = + (adev->mman.drv_vram_usage_va + (AMD_SRIOV_MSG_RAS_TELEMETRY_OFFSET_KB << 10)); } amdgpu_virt_read_pf2vf_data(adev); @@ -1197,3 +1203,133 @@ bool amdgpu_virt_get_ras_capability(struct amdgpu_device *adev) return true; } + +static inline enum amd_sriov_ras_telemetry_gpu_block +amdgpu_ras_block_to_sriov(struct amdgpu_device *adev, enum amdgpu_ras_block block) { + switch (block) { + case AMDGPU_RAS_BLOCK__UMC: + return RAS_TELEMETRY_GPU_BLOCK_UMC; + case AMDGPU_RAS_BLOCK__SDMA: + return RAS_TELEMETRY_GPU_BLOCK_SDMA; + case AMDGPU_RAS_BLOCK__GFX: + return RAS_TELEMETRY_GPU_BLOCK_GFX; + case AMDGPU_RAS_BLOCK__MMHUB: + return RAS_TELEMETRY_GPU_BLOCK_MMHUB; + case AMDGPU_RAS_BLOCK__ATHUB: + return RAS_TELEMETRY_GPU_BLOCK_ATHUB; + case AMDGPU_RAS_BLOCK__PCIE_BIF: + return RAS_TELEMETRY_GPU_BLOCK_PCIE_BIF; + case AMDGPU_RAS_BLOCK__HDP: + return RAS_TELEMETRY_GPU_BLOCK_HDP; + case AMDGPU_RAS_BLOCK__XGMI_WAFL: + return RAS_TELEMETRY_GPU_BLOCK_XGMI_WAFL; + case AMDGPU_RAS_BLOCK__DF: + return RAS_TELEMETRY_GPU_BLOCK_DF; + case AMDGPU_RAS_BLOCK__SMN: + return RAS_TELEMETRY_GPU_BLOCK_SMN; + case AMDGPU_RAS_BLOCK__SEM: + return RAS_TELEMETRY_GPU_BLOCK_SEM; + case AMDGPU_RAS_BLOCK__MP0: + return RAS_TELEMETRY_GPU_BLOCK_MP0; + case AMDGPU_RAS_BLOCK__MP1: + return RAS_TELEMETRY_GPU_BLOCK_MP1; + case AMDGPU_RAS_BLOCK__FUSE: + return RAS_TELEMETRY_GPU_BLOCK_FUSE; + case AMDGPU_RAS_BLOCK__MCA: + return RAS_TELEMETRY_GPU_BLOCK_MCA; + case AMDGPU_RAS_BLOCK__VCN: + return RAS_TELEMETRY_GPU_BLOCK_VCN; + case AMDGPU_RAS_BLOCK__JPEG: + return RAS_TELEMETRY_GPU_BLOCK_JPEG; + case AMDGPU_RAS_BLOCK__IH: + return RAS_TELEMETRY_GPU_BLOCK_IH; + case AMDGPU_RAS_BLOCK__MPIO: + return RAS_TELEMETRY_GPU_BLOCK_MPIO; + default: + dev_err(adev->dev, "Unsupported SRIOV RAS telemetry block 0x%x\n", block); + return RAS_TELEMETRY_GPU_BLOCK_COUNT; + } +} + +static int amdgpu_virt_cache_host_error_counts(struct amdgpu_device *adev, + struct amdsriov_ras_telemetry *host_telemetry) +{ + struct amd_sriov_ras_telemetry_error_count *tmp = NULL; + uint32_t checksum, used_size; + + checksum = host_telemetry->header.checksum; + used_size = host_telemetry->header.used_size; + + if (used_size > (AMD_SRIOV_RAS_TELEMETRY_SIZE_KB << 10)) + return 0; + + tmp = kmalloc(used_size, GFP_KERNEL); + if (!tmp) + return -ENOMEM; + + memcpy(tmp, &host_telemetry->body.error_count, used_size); + + if (checksum != amd_sriov_msg_checksum(tmp, used_size, 0, 0)) + goto out; + + memcpy(&adev->virt.count_cache, tmp, + min(used_size, sizeof(adev->virt.count_cache))); +out: + kfree(tmp); + + return 0; +} + +static int amdgpu_virt_req_ras_err_count_internal(struct amdgpu_device *adev, bool force_update) +{ + struct amdgpu_virt *virt = &adev->virt; + + /* Host allows 15 ras telemetry requests per 60 seconds. Afterwhich, the Host + * will ignore incoming guest messages. Ratelimit the guest messages to + * prevent guest self DOS. + */ + if (__ratelimit(&adev->virt.ras_telemetry_rs) || force_update) { + if (!virt->ops->req_ras_err_count(adev)) + amdgpu_virt_cache_host_error_counts(adev, + adev->virt.fw_reserve.ras_telemetry); + } + + return 0; +} + +/* Bypass ACA interface and query ECC counts directly from host */ +int amdgpu_virt_req_ras_err_count(struct amdgpu_device *adev, enum amdgpu_ras_block block, + struct ras_err_data *err_data) +{ + enum amd_sriov_ras_telemetry_gpu_block sriov_block; + + sriov_block = amdgpu_ras_block_to_sriov(adev, block); + + if (sriov_block >= RAS_TELEMETRY_GPU_BLOCK_COUNT || + !amdgpu_sriov_ras_telemetry_block_en(adev, sriov_block)) + return -EOPNOTSUPP; + + /* Host Access may be lost during reset, just return last cached data. */ + if (down_read_trylock(&adev->reset_domain->sem)) { + amdgpu_virt_req_ras_err_count_internal(adev, false); + up_read(&adev->reset_domain->sem); + } + + err_data->ue_count = adev->virt.count_cache.block[sriov_block].ue_count; + err_data->ce_count = adev->virt.count_cache.block[sriov_block].ce_count; + err_data->de_count = adev->virt.count_cache.block[sriov_block].de_count; + + return 0; +} + +int amdgpu_virt_ras_telemetry_post_reset(struct amdgpu_device *adev) +{ + unsigned long ue_count, ce_count; + + if (amdgpu_sriov_ras_telemetry_en(adev)) { + amdgpu_virt_req_ras_err_count_internal(adev, true); + amdgpu_ras_query_error_count(adev, &ce_count, &ue_count, NULL); + } + + return 0; +} diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h index f0ff84add6926..5381b8d596e62 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h @@ -104,6 +104,7 @@ struct amdgpu_virt_ops { struct amdgpu_virt_fw_reserve { struct amd_sriov_msg_pf2vf_info_header *p_pf2vf; struct amd_sriov_msg_vf2pf_info_header *p_vf2pf; + void *ras_telemetry; unsigned int checksum_key; }; @@ -138,6 +139,7 @@ enum AMDGIM_FEATURE_FLAG { /* MES info */ AMDGIM_FEATURE_MES_INFO_ENABLE = (1 << 8), AMDGIM_FEATURE_RAS_CAPS = (1 << 9), + AMDGIM_FEATURE_RAS_TELEMETRY = (1 << 10), }; enum AMDGIM_REG_ACCESS_FLAG { @@ -280,6 +282,10 @@ struct amdgpu_virt { struct mutex rlcg_reg_lock; union amd_sriov_ras_caps ras_en_caps; + union amd_sriov_ras_caps ras_telemetry_en_caps; + + struct ratelimit_state ras_telemetry_rs; + struct amd_sriov_ras_telemetry_error_count count_cache; }; struct amdgpu_video_codec_info; @@ -327,6 +333,12 @@ struct amdgpu_video_codec_info; #define amdgpu_sriov_ras_caps_en(adev) \ ((adev)->virt.gim_feature & AMDGIM_FEATURE_RAS_CAPS) +#define amdgpu_sriov_ras_telemetry_en(adev) \ +(((adev)->virt.gim_feature & AMDGIM_FEATURE_RAS_TELEMETRY) && (adev)->virt.fw_reserve.ras_telemetry) + +#define amdgpu_sriov_ras_telemetry_block_en(adev, sriov_blk) \ +(amdgpu_sriov_ras_telemetry_en((adev)) && (adev)->virt.ras_telemetry_en_caps.all & BIT(sriov_blk)) + static inline bool is_virtual_machine(void) { #if defined(CONFIG_X86) @@ -391,4 +403,7 @@ bool amdgpu_virt_get_rlcg_reg_access_flag(struct amdgpu_device *adev, bool write, u32 *rlcg_flag); u32 amdgpu_virt_rlcg_reg_rw(struct amdgpu_device *adev, u32 offset, u32 v, u32 flag, u32 xcc_id); bool amdgpu_virt_get_ras_capability(struct amdgpu_device *adev); +int amdgpu_virt_req_ras_err_count(struct amdgpu_device *adev, enum amdgpu_ras_block block, + struct ras_err_data *err_data); +int amdgpu_virt_ras_telemetry_post_reset(struct amdgpu_device *adev); #endif From de30b6c58b1a95eb01183cc8015792f51424c8fd Mon Sep 17 00:00:00 2001 From: Victor Skvortsov Date: Thu, 5 Dec 2024 09:10:49 -0500 Subject: [PATCH 1833/1868] drm/amdgpu: fix compile error inside amdgpu_ras_virt_error_generate_report Fixing compile error caused by 60f3e16b67aa8d0393f70e2ff49bb3c9c99e97e3 Signed-off-by: Victor Skvortsov --- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index b91163d6df9e0..82a412211dd9c 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -1222,7 +1222,7 @@ static void amdgpu_ras_virt_error_generate_report(struct amdgpu_device *adev, unsigned long new_ue, new_ce, new_de; struct ras_manager *obj = amdgpu_ras_find_obj(adev, &query_if->head); const char *blk_name = get_ras_block_str(&query_if->head); - u64 event_id = qctx->event_id; + u64 event_id = qctx->evid.event_id; new_ce = err_data->ce_count - obj->err_data.ce_count; new_ue = err_data->ue_count - obj->err_data.ue_count; From e17d8a2ce8cc9762bdae40c75fc796318b5a165d Mon Sep 17 00:00:00 2001 From: Kenneth Feng Date: Tue, 19 Nov 2024 15:03:22 +0800 Subject: [PATCH 1834/1868] drm/amd/pm: skip setting the power source on smu v14.0.2/3 skip setting power source on smu v14.0.2/3 Signed-off-by: Kenneth Feng Reviewed-by: Lijo Lazar --- drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c index cbad0deb43f3a..882e51044dfb6 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c @@ -2826,7 +2826,6 @@ static const struct pptable_funcs smu_v14_0_2_ppt_funcs = { .get_unique_id = smu_v14_0_2_get_unique_id, .get_power_limit = smu_v14_0_2_get_power_limit, .set_power_limit = smu_v14_0_2_set_power_limit, - .set_power_source = smu_v14_0_set_power_source, .get_power_profile_mode = smu_v14_0_2_get_power_profile_mode, .set_power_profile_mode = smu_v14_0_2_set_power_profile_mode, .run_btc = smu_v14_0_run_btc, From eb5edf5d2de10cc4699ed28d597deddb3eec2a7a Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Mon, 4 Nov 2024 10:36:13 +0530 Subject: [PATCH 1835/1868] drm/amdgpu: Fix DPX valid mode check on GC 9.4.3 For DPX mode, the number of memory partitions supported should be less than or equal to 2. Signed-off-by: Lijo Lazar Reviewed-by: Hawking Zhang Fixes: 1589c82a1085 ("drm/amdgpu: Check memory ranges for valid xcp mode") --- drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c b/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c index fba9fadf9212c..81f4354cbd6ae 100644 --- a/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c +++ b/drivers/gpu/drm/amd/amdgpu/aqua_vanjaram.c @@ -537,7 +537,7 @@ static bool __aqua_vanjaram_is_valid_mode(struct amdgpu_xcp_mgr *xcp_mgr, case AMDGPU_SPX_PARTITION_MODE: return adev->gmc.num_mem_partitions == 1 && num_xcc > 0; case AMDGPU_DPX_PARTITION_MODE: - return adev->gmc.num_mem_partitions != 8 && (num_xcc % 4) == 0; + return adev->gmc.num_mem_partitions <= 2 && (num_xcc % 4) == 0; case AMDGPU_TPX_PARTITION_MODE: return (adev->gmc.num_mem_partitions == 1 || adev->gmc.num_mem_partitions == 3) && From 833bf22961fd003894eb1a166b77dd25f78a5279 Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Thu, 24 Oct 2024 11:01:57 +0530 Subject: [PATCH 1836/1868] drm/amdgpu: Prefer RAS recovery for scheduler hang Before scheduling a recovery due to scheduler/job hang, check if a RAS error is detected. If so, choose RAS recovery to handle the situation. A scheduler/job hang could be the side effect of a RAS error. In such cases, it is required to go through the RAS error recovery process. A RAS error recovery process in certains cases also could avoid a full device device reset. An error state is maintained in RAS context to detect the block affected. Fatal Error state uses unused block id. Set the block id when error is detected. If the interrupt handler detected a poison error, it's not required to look for a fatal error. Skip fatal error checking in such cases. Signed-off-by: Lijo Lazar Reviewed-by: Hawking Zhang --- drivers/gpu/drm/amd/amdgpu/aldebaran.c | 2 + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 15 ++++- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 55 ++++++++++++++++++- drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h | 11 +++- .../gpu/drm/amd/amdkfd/kfd_int_process_v9.c | 2 + 5 files changed, 78 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/aldebaran.c b/drivers/gpu/drm/amd/amdgpu/aldebaran.c index c1ff24335a0c5..15bb26b76ed48 100644 --- a/drivers/gpu/drm/amd/amdgpu/aldebaran.c +++ b/drivers/gpu/drm/amd/amdgpu/aldebaran.c @@ -344,6 +344,8 @@ aldebaran_mode2_restore_hwcontext(struct amdgpu_reset_control *reset_ctl, list_for_each_entry(tmp_adev, reset_device_list, reset_list) { dev_info(tmp_adev->dev, "GPU reset succeeded, trying to resume\n"); + /*TBD: Ideally should clear only GFX, SDMA blocks*/ + amdgpu_ras_clear_err_state(tmp_adev); r = aldebaran_mode2_restore_ip(tmp_adev); if (r) goto end; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index b765fa840f63d..be37a46a6c038 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -5131,7 +5131,7 @@ static int amdgpu_device_reset_sriov(struct amdgpu_device *adev, if (r) return r; - amdgpu_ras_set_fed(adev, false); + amdgpu_ras_clear_err_state(adev); amdgpu_irq_gpu_reset_resume_helper(adev); /* some sw clean up VF needs to do before recover */ @@ -5426,7 +5426,7 @@ int amdgpu_device_reinit_after_reset(struct amdgpu_reset_context *reset_context) amdgpu_set_init_level(tmp_adev, AMDGPU_INIT_LEVEL_DEFAULT); if (full_reset) { /* post card */ - amdgpu_ras_set_fed(tmp_adev, false); + amdgpu_ras_clear_err_state(tmp_adev); r = amdgpu_device_asic_init(tmp_adev); if (r) { dev_warn(tmp_adev->dev, "asic atom init failed!"); @@ -5757,6 +5757,17 @@ int amdgpu_device_gpu_recover(struct amdgpu_device *adev, if (amdgpu_reset_domain_in_drain_mode(adev->reset_domain)) return 0; + /* + * If it reaches here because of hang/timeout and a RAS error is + * detected at the same time, let RAS recovery take care of it. + */ + if (amdgpu_ras_is_err_state(adev, AMDGPU_RAS_BLOCK__ANY) && + reset_context->src != AMDGPU_RESET_SRC_RAS) { + dev_dbg(adev->dev, + "Gpu recovery from source: %d yielding to RAS error recovery handling", + reset_context->src); + return 0; + } /* * Special case: RAS triggered and full reset isn't supported */ diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 82a412211dd9c..71e8eafbbfbce 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c @@ -2156,6 +2156,16 @@ void amdgpu_ras_interrupt_fatal_error_handler(struct amdgpu_device *adev) /* Fatal error events are handled on host side */ if (amdgpu_sriov_vf(adev)) return; + /** + * If the current interrupt is caused by a non-fatal RAS error, skip + * check for fatal error. For fatal errors, FED status of all devices + * in XGMI hive gets set when the first device gets fatal error + * interrupt. The error gets propagated to other devices as well, so + * make sure to ack the interrupt regardless of FED status. + */ + if (!amdgpu_ras_get_fed_status(adev) && + amdgpu_ras_is_err_state(adev, AMDGPU_RAS_BLOCK__ANY)) + return; if (adev->nbio.ras && adev->nbio.ras->handle_ras_controller_intr_no_bifring) @@ -2185,6 +2195,7 @@ static void amdgpu_ras_interrupt_poison_consumption_handler(struct ras_manager * if (ret) return; + amdgpu_ras_set_err_poison(adev, block_obj->ras_comm.block); /* both query_poison_status and handle_poison_consumption are optional, * but at least one of them should be implemented if we need poison * consumption handler @@ -4097,16 +4108,56 @@ bool amdgpu_ras_get_fed_status(struct amdgpu_device *adev) if (!ras) return false; - return atomic_read(&ras->fed); + return test_bit(AMDGPU_RAS_BLOCK__LAST, &ras->ras_err_state); } void amdgpu_ras_set_fed(struct amdgpu_device *adev, bool status) { struct amdgpu_ras *ras; + ras = amdgpu_ras_get_context(adev); + if (ras) { + if (status) + set_bit(AMDGPU_RAS_BLOCK__LAST, &ras->ras_err_state); + else + clear_bit(AMDGPU_RAS_BLOCK__LAST, &ras->ras_err_state); + } +} + +void amdgpu_ras_clear_err_state(struct amdgpu_device *adev) +{ + struct amdgpu_ras *ras; + ras = amdgpu_ras_get_context(adev); if (ras) - atomic_set(&ras->fed, !!status); + ras->ras_err_state = 0; +} + +void amdgpu_ras_set_err_poison(struct amdgpu_device *adev, + enum amdgpu_ras_block block) +{ + struct amdgpu_ras *ras; + + ras = amdgpu_ras_get_context(adev); + if (ras) + set_bit(block, &ras->ras_err_state); +} + +bool amdgpu_ras_is_err_state(struct amdgpu_device *adev, int block) +{ + struct amdgpu_ras *ras; + + ras = amdgpu_ras_get_context(adev); + if (ras) { + if (block == AMDGPU_RAS_BLOCK__ANY) + return (ras->ras_err_state != 0); + else + return test_bit(block, &ras->ras_err_state) || + test_bit(AMDGPU_RAS_BLOCK__LAST, + &ras->ras_err_state); + } + + return false; } static struct ras_event_manager *__get_ras_event_mgr(struct amdgpu_device *adev) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h index 6db772ecfee47..b13debcf48ee3 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h @@ -99,7 +99,8 @@ enum amdgpu_ras_block { AMDGPU_RAS_BLOCK__IH, AMDGPU_RAS_BLOCK__MPIO, - AMDGPU_RAS_BLOCK__LAST + AMDGPU_RAS_BLOCK__LAST, + AMDGPU_RAS_BLOCK__ANY = -1 }; enum amdgpu_ras_mca_block { @@ -558,8 +559,8 @@ struct amdgpu_ras { struct ras_ecc_log_info umc_ecc_log; struct delayed_work page_retirement_dwork; - /* Fatal error detected flag */ - atomic_t fed; + /* ras errors detected */ + unsigned long ras_err_state; /* RAS event manager */ struct ras_event_manager __event_mgr; @@ -952,6 +953,10 @@ ssize_t amdgpu_ras_aca_sysfs_read(struct device *dev, struct device_attribute *a void amdgpu_ras_set_fed(struct amdgpu_device *adev, bool status); bool amdgpu_ras_get_fed_status(struct amdgpu_device *adev); +void amdgpu_ras_set_err_poison(struct amdgpu_device *adev, + enum amdgpu_ras_block block); +void amdgpu_ras_clear_err_state(struct amdgpu_device *adev); +bool amdgpu_ras_is_err_state(struct amdgpu_device *adev, int block); u64 amdgpu_ras_acquire_event_id(struct amdgpu_device *adev, enum ras_event_type type); int amdgpu_ras_mark_ras_event_caller(struct amdgpu_device *adev, enum ras_event_type type, diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c index d46a13156ee9d..0cb5c582ce7dc 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_int_process_v9.c @@ -184,6 +184,7 @@ static void event_interrupt_poison_consumption_v9(struct kfd_node *dev, } else { reset = AMDGPU_RAS_GPU_RESET_MODE2_RESET; } + amdgpu_ras_set_err_poison(dev->adev, AMDGPU_RAS_BLOCK__GFX); break; case SOC15_IH_CLIENTID_VMC: case SOC15_IH_CLIENTID_VMC1: @@ -213,6 +214,7 @@ static void event_interrupt_poison_consumption_v9(struct kfd_node *dev, } else { reset = AMDGPU_RAS_GPU_RESET_MODE2_RESET; } + amdgpu_ras_set_err_poison(dev->adev, AMDGPU_RAS_BLOCK__SDMA); break; default: dev_warn(dev->adev->dev, From 16ac390be64fdb21656cb132949738325315fccf Mon Sep 17 00:00:00 2001 From: Frank Min Date: Thu, 28 Nov 2024 16:05:24 +0800 Subject: [PATCH 1837/1868] drm/amdgpu/hdp7.0: do a posting read when flushing HDP Need to read back to make sure the write goes through. Cc: David Belanger Signed-off-by: Alex Deucher Reviewed-by: Frank Min (cherry picked from commit 0f3da2b20e158ccfc79103117e70e0858a5c2294) Change-Id: I3d0cfb1bf9fc348750efc091333a750ee4ad09a5 --- drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c b/drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c index 1c99bb09e2a12..63820329f67eb 100644 --- a/drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c +++ b/drivers/gpu/drm/amd/amdgpu/hdp_v7_0.c @@ -31,10 +31,12 @@ static void hdp_v7_0_flush_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) { - if (!ring || !ring->funcs->emit_wreg) + if (!ring || !ring->funcs->emit_wreg) { WREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); - else + RREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2); + } else { amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0); + } } static void hdp_v7_0_update_clock_gating(struct amdgpu_device *adev, From 4b6f830af7ba1e6caf1c4868f22155f87f0fddbb Mon Sep 17 00:00:00 2001 From: Ryan Seto Date: Fri, 1 Nov 2024 10:19:56 -0400 Subject: [PATCH 1838/1868] drm/amd/display: Handle dml allocation failure to avoid BSOD [Why] In the case where a dml allocation fails for any reason, the current state's dml contexts would no longer be valid. Then subsequent calls dc_state_copy_internal would shallow copy invalid memory and if the new state was released, a double free would occur. [How] Reset dml pointers in new_state to NULL and avoid invalid pointer Signed-off-by: Ryan Seto --- drivers/gpu/drm/amd/display/dc/core/dc_state.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_state.c b/drivers/gpu/drm/amd/display/dc/core/dc_state.c index 2597e3fd562bb..e006f816ff2f7 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_state.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_state.c @@ -265,6 +265,9 @@ struct dc_state *dc_state_create_copy(struct dc_state *src_state) dc_state_copy_internal(new_state, src_state); #ifdef CONFIG_DRM_AMD_DC_FP + new_state->bw_ctx.dml2 = NULL; + new_state->bw_ctx.dml2_dc_power_source = NULL; + if (src_state->bw_ctx.dml2 && !dml2_create_copy(&new_state->bw_ctx.dml2, src_state->bw_ctx.dml2)) { dc_state_release(new_state); From 7367bbdf8e0ac627ca2cb0786195504522d9da27 Mon Sep 17 00:00:00 2001 From: Aurabindo Pillai Date: Fri, 1 Nov 2024 16:16:18 +0000 Subject: [PATCH 1839/1868] drm/amd/display: Add a missing DCN401 reg definition Add a mising reg field to the autogenerated header for future use Signed-off-by: Aurabindo Pillai --- drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_1_0_sh_mask.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_1_0_sh_mask.h index f42a276499cd1..5d9d5fea6e06b 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_1_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_4_1_0_sh_mask.h @@ -6199,10 +6199,12 @@ #define DCHUBBUB_CTRL_STATUS__ROB_UNDERFLOW_STATUS__SHIFT 0x1 #define DCHUBBUB_CTRL_STATUS__ROB_OVERFLOW_STATUS__SHIFT 0x2 #define DCHUBBUB_CTRL_STATUS__ROB_OVERFLOW_CLEAR__SHIFT 0x3 +#define DCHUBBUB_CTRL_STATUS__DCHUBBUB_HW_DEBUG__SHIFT 0x4 #define DCHUBBUB_CTRL_STATUS__CSTATE_SWATH_CHK_GOOD_MODE__SHIFT 0x1f #define DCHUBBUB_CTRL_STATUS__ROB_UNDERFLOW_STATUS_MASK 0x00000002L #define DCHUBBUB_CTRL_STATUS__ROB_OVERFLOW_STATUS_MASK 0x00000004L #define DCHUBBUB_CTRL_STATUS__ROB_OVERFLOW_CLEAR_MASK 0x00000008L +#define DCHUBBUB_CTRL_STATUS__DCHUBBUB_HW_DEBUG_MASK 0x3FFFFFF0L #define DCHUBBUB_CTRL_STATUS__CSTATE_SWATH_CHK_GOOD_MODE_MASK 0x80000000L //DCHUBBUB_TIMEOUT_DETECTION_CTRL1 #define DCHUBBUB_TIMEOUT_DETECTION_CTRL1__DCHUBBUB_TIMEOUT_ERROR_STATUS__SHIFT 0x0 From 6085345d14c3a1b291b5316dc1dcd9600f7ca744 Mon Sep 17 00:00:00 2001 From: Dillon Varone Date: Fri, 1 Nov 2024 10:51:02 -0400 Subject: [PATCH 1840/1868] drm/amd/display: Enable Request rate limiter during C-State on dcn401 [WHY] When C-State entry is requested, the rate limiter will be disabled which can result in high contention in the DCHUB return path. [HOW] Enable the rate limiter during C-state requests to prevent contention. Signed-off-by: Dillon Varone --- .../src/dml2_core/dml2_core_dcn4_calcs.c | 6 +++++ .../display/dc/hubbub/dcn10/dcn10_hubbub.h | 8 ++++++- .../display/dc/hubbub/dcn20/dcn20_hubbub.h | 1 + .../display/dc/hubbub/dcn401/dcn401_hubbub.c | 24 +++++++++++++++++-- .../display/dc/hubbub/dcn401/dcn401_hubbub.h | 7 +++++- .../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 13 ++++++---- .../gpu/drm/amd/display/dc/inc/hw/dchubbub.h | 2 +- .../dc/resource/dcn401/dcn401_resource.h | 3 ++- 8 files changed, 53 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c index 92e43a1e4dd46..601320b1be817 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/dml2_core_dcn4_calcs.c @@ -11,6 +11,7 @@ #define DML2_MAX_FMT_420_BUFFER_WIDTH 4096 #define DML_MAX_NUM_OF_SLICES_PER_DSC 4 +#define ALLOW_SDPIF_RATE_LIMIT_PRE_CSTATE const char *dml2_core_internal_bw_type_str(enum dml2_core_internal_bw_type bw_type) { @@ -3886,6 +3887,10 @@ static void CalculateSwathAndDETConfiguration(struct dml2_core_internal_scratch #endif *p->hw_debug5 = false; +#ifdef ALLOW_SDPIF_RATE_LIMIT_PRE_CSTATE + if (p->NumberOfActiveSurfaces > 1) + *p->hw_debug5 = true; +#else for (unsigned int k = 0; k < p->NumberOfActiveSurfaces; ++k) { if (!(p->mrq_present) && (!(*p->UnboundedRequestEnabled)) && (TotalActiveDPP == 1) && p->display_cfg->plane_descriptors[k].surface.dcc.enable @@ -3901,6 +3906,7 @@ static void CalculateSwathAndDETConfiguration(struct dml2_core_internal_scratch dml2_printf("DML::%s: k=%u hw_debug5 = %u\n", __func__, k, *p->hw_debug5); #endif } +#endif } static enum dml2_odm_mode DecideODMMode(unsigned int HActive, diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h b/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h index 4bd1dda077196..9fbd45c7dfef2 100644 --- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h +++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.h @@ -200,6 +200,7 @@ struct dcn_hubbub_registers { uint32_t DCHUBBUB_ARB_FRAC_URG_BW_MALL_B; uint32_t DCHUBBUB_TIMEOUT_DETECTION_CTRL1; uint32_t DCHUBBUB_TIMEOUT_DETECTION_CTRL2; + uint32_t DCHUBBUB_CTRL_STATUS; }; #define HUBBUB_REG_FIELD_LIST_DCN32(type) \ @@ -320,7 +321,12 @@ struct dcn_hubbub_registers { type DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD;\ type DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD;\ type DCHUBBUB_TIMEOUT_DETECTION_EN;\ - type DCHUBBUB_TIMEOUT_TIMER_RESET + type DCHUBBUB_TIMEOUT_TIMER_RESET;\ + type ROB_UNDERFLOW_STATUS;\ + type ROB_OVERFLOW_STATUS;\ + type ROB_OVERFLOW_CLEAR;\ + type DCHUBBUB_HW_DEBUG;\ + type CSTATE_SWATH_CHK_GOOD_MODE #define HUBBUB_STUTTER_REG_FIELD_LIST(type) \ type DCHUBBUB_ARB_ALLOW_SR_ENTER_WATERMARK_A;\ diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.h b/drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.h index 036bb3e6c9575..46d8f5c70750a 100644 --- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.h +++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.h @@ -96,6 +96,7 @@ struct dcn20_hubbub { unsigned int det1_size; unsigned int det2_size; unsigned int det3_size; + bool allow_sdpif_rate_limit_when_cstate_req; }; void hubbub2_construct(struct dcn20_hubbub *hubbub, diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c index 5d658e9bef640..92fab471b1836 100644 --- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c +++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.c @@ -1192,15 +1192,35 @@ static void dcn401_wait_for_det_update(struct hubbub *hubbub, int hubp_inst) } } -static void dcn401_program_timeout_thresholds(struct hubbub *hubbub, struct dml2_display_arb_regs *arb_regs) +static bool dcn401_program_arbiter(struct hubbub *hubbub, struct dml2_display_arb_regs *arb_regs, bool safe_to_lower) { struct dcn20_hubbub *hubbub2 = TO_DCN20_HUBBUB(hubbub); + bool wm_pending = false; + uint32_t temp; + /* request backpressure and outstanding return threshold (unused)*/ //REG_UPDATE(DCHUBBUB_TIMEOUT_DETECTION_CTRL1, DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD, arb_regs->req_stall_threshold); /* P-State stall threshold */ REG_UPDATE(DCHUBBUB_TIMEOUT_DETECTION_CTRL2, DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD, arb_regs->pstate_stall_threshold); + + if (safe_to_lower || arb_regs->allow_sdpif_rate_limit_when_cstate_req > hubbub2->allow_sdpif_rate_limit_when_cstate_req) { + hubbub2->allow_sdpif_rate_limit_when_cstate_req = arb_regs->allow_sdpif_rate_limit_when_cstate_req; + + /* only update the required bits */ + REG_GET(DCHUBBUB_CTRL_STATUS, DCHUBBUB_HW_DEBUG, &temp); + if (hubbub2->allow_sdpif_rate_limit_when_cstate_req) { + temp |= (1 << 5); + } else { + temp &= ~(1 << 5); + } + REG_UPDATE(DCHUBBUB_CTRL_STATUS, DCHUBBUB_HW_DEBUG, temp); + } else { + wm_pending = true; + } + + return wm_pending; } static const struct hubbub_funcs hubbub4_01_funcs = { @@ -1226,7 +1246,7 @@ static const struct hubbub_funcs hubbub4_01_funcs = { .program_det_segments = dcn401_program_det_segments, .program_compbuf_segments = dcn401_program_compbuf_segments, .wait_for_det_update = dcn401_wait_for_det_update, - .program_timeout_thresholds = dcn401_program_timeout_thresholds, + .program_arbiter = dcn401_program_arbiter, }; void hubbub401_construct(struct dcn20_hubbub *hubbub2, diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.h b/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.h index 5f1960722ebdd..b1d9ea9d1c3d6 100644 --- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.h +++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn401/dcn401_hubbub.h @@ -128,7 +128,12 @@ HUBBUB_SF(DCHUBBUB_TIMEOUT_DETECTION_CTRL1, DCHUBBUB_TIMEOUT_REQ_STALL_THRESHOLD, mask_sh),\ HUBBUB_SF(DCHUBBUB_TIMEOUT_DETECTION_CTRL2, DCHUBBUB_TIMEOUT_PSTATE_STALL_THRESHOLD, mask_sh),\ HUBBUB_SF(DCHUBBUB_TIMEOUT_DETECTION_CTRL2, DCHUBBUB_TIMEOUT_DETECTION_EN, mask_sh),\ - HUBBUB_SF(DCHUBBUB_TIMEOUT_DETECTION_CTRL2, DCHUBBUB_TIMEOUT_TIMER_RESET, mask_sh) + HUBBUB_SF(DCHUBBUB_TIMEOUT_DETECTION_CTRL2, DCHUBBUB_TIMEOUT_TIMER_RESET, mask_sh),\ + HUBBUB_SF(DCHUBBUB_CTRL_STATUS, ROB_UNDERFLOW_STATUS, mask_sh),\ + HUBBUB_SF(DCHUBBUB_CTRL_STATUS, ROB_OVERFLOW_STATUS, mask_sh),\ + HUBBUB_SF(DCHUBBUB_CTRL_STATUS, ROB_OVERFLOW_CLEAR, mask_sh),\ + HUBBUB_SF(DCHUBBUB_CTRL_STATUS, DCHUBBUB_HW_DEBUG, mask_sh),\ + HUBBUB_SF(DCHUBBUB_CTRL_STATUS, CSTATE_SWATH_CHK_GOOD_MODE, mask_sh) bool hubbub401_program_urgent_watermarks( struct hubbub *hubbub, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c index b0b2b195e7d80..721eb77bf1685 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c @@ -1483,6 +1483,10 @@ void dcn401_prepare_bandwidth(struct dc *dc, &context->bw_ctx.bw.dcn.watermarks, dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000, false); + /* update timeout thresholds */ + if (hubbub->funcs->program_arbiter) { + dc->wm_optimized_required |= hubbub->funcs->program_arbiter(hubbub, &context->bw_ctx.bw.dcn.arb_regs, false); + } /* decrease compbuf size */ if (hubbub->funcs->program_compbuf_segments) { @@ -1524,6 +1528,10 @@ void dcn401_optimize_bandwidth( &context->bw_ctx.bw.dcn.watermarks, dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000, true); + /* update timeout thresholds */ + if (hubbub->funcs->program_arbiter) { + hubbub->funcs->program_arbiter(hubbub, &context->bw_ctx.bw.dcn.arb_regs, true); + } if (dc->clk_mgr->dc_mode_softmax_enabled) if (dc->clk_mgr->clks.dramclk_khz > dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000 && @@ -1549,11 +1557,6 @@ void dcn401_optimize_bandwidth( pipe_ctx->dlg_regs.min_dst_y_next_start); } } - - /* update timeout thresholds */ - if (hubbub->funcs->program_timeout_thresholds) { - hubbub->funcs->program_timeout_thresholds(hubbub, &context->bw_ctx.bw.dcn.arb_regs); - } } void dcn401_fams2_global_control_lock(struct dc *dc, diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h index 6c1d41c0f0992..52b745667ef75 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h @@ -228,7 +228,7 @@ struct hubbub_funcs { void (*program_det_segments)(struct hubbub *hubbub, int hubp_inst, unsigned det_buffer_size_seg); void (*program_compbuf_segments)(struct hubbub *hubbub, unsigned compbuf_size_seg, bool safe_to_increase); void (*wait_for_det_update)(struct hubbub *hubbub, int hubp_inst); - void (*program_timeout_thresholds)(struct hubbub *hubbub, struct dml2_display_arb_regs *arb_regs); + bool (*program_arbiter)(struct hubbub *hubbub, struct dml2_display_arb_regs *arb_regs, bool safe_to_lower); }; struct hubbub { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h index 7c8d61db153d3..19568c3596694 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.h @@ -612,7 +612,8 @@ void dcn401_prepare_mcache_programming(struct dc *dc, struct dc_state *context); SR(DCHUBBUB_SDPIF_CFG1), \ SR(DCHUBBUB_MEM_PWR_MODE_CTRL), \ SR(DCHUBBUB_TIMEOUT_DETECTION_CTRL1), \ - SR(DCHUBBUB_TIMEOUT_DETECTION_CTRL2) + SR(DCHUBBUB_TIMEOUT_DETECTION_CTRL2), \ + SR(DCHUBBUB_CTRL_STATUS) /* DCCG */ From 3e72c45fbc66fba936c21e95f2711bc6e79a219c Mon Sep 17 00:00:00 2001 From: Dillon Varone Date: Fri, 1 Nov 2024 12:00:14 -0400 Subject: [PATCH 1841/1868] drm/amd/display: Require minimum VBlank size for stutter optimization [WHY&HOW] If the nominal VBlank is too small, optimizing for stutter can cause the prefetch bandwidth to increase drasticaly, resulting in higher clock and power requirements. Only optimize if it is >3x the stutter latency. Signed-off-by: Dillon Varone --- .../dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c index 5a09dd298e6f3..92269f0e50ed2 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_pmo/dml2_pmo_dcn4_fams2.c @@ -8,6 +8,7 @@ #include "dml2_pmo_dcn4_fams2.h" static const double MIN_VACTIVE_MARGIN_PCT = 0.25; // We need more than non-zero margin because DET buffer granularity can alter vactive latency hiding +static const double MIN_BLANK_STUTTER_FACTOR = 3.0; static const struct dml2_pmo_pstate_strategy base_strategy_list_1_display[] = { // VActive Preferred @@ -2140,6 +2141,7 @@ bool pmo_dcn4_fams2_init_for_stutter(struct dml2_pmo_init_for_stutter_in_out *in struct dml2_pmo_instance *pmo = in_out->instance; bool stutter_period_meets_z8_eco = true; bool z8_stutter_optimization_too_expensive = false; + bool stutter_optimization_too_expensive = false; double line_time_us, vblank_nom_time_us; unsigned int i; @@ -2161,10 +2163,15 @@ bool pmo_dcn4_fams2_init_for_stutter(struct dml2_pmo_init_for_stutter_in_out *in line_time_us = (double)in_out->base_display_config->display_config.stream_descriptors[i].timing.h_total / (in_out->base_display_config->display_config.stream_descriptors[i].timing.pixel_clock_khz * 1000) * 1000000; vblank_nom_time_us = line_time_us * in_out->base_display_config->display_config.stream_descriptors[i].timing.vblank_nom; - if (vblank_nom_time_us < pmo->soc_bb->power_management_parameters.z8_stutter_exit_latency_us) { + if (vblank_nom_time_us < pmo->soc_bb->power_management_parameters.z8_stutter_exit_latency_us * MIN_BLANK_STUTTER_FACTOR) { z8_stutter_optimization_too_expensive = true; break; } + + if (vblank_nom_time_us < pmo->soc_bb->power_management_parameters.stutter_enter_plus_exit_latency_us * MIN_BLANK_STUTTER_FACTOR) { + stutter_optimization_too_expensive = true; + break; + } } pmo->scratch.pmo_dcn4.num_stutter_candidates = 0; @@ -2180,7 +2187,7 @@ bool pmo_dcn4_fams2_init_for_stutter(struct dml2_pmo_init_for_stutter_in_out *in pmo->scratch.pmo_dcn4.z8_vblank_optimizable = false; } - if (pmo->soc_bb->power_management_parameters.stutter_enter_plus_exit_latency_us > 0) { + if (!stutter_optimization_too_expensive && pmo->soc_bb->power_management_parameters.stutter_enter_plus_exit_latency_us > 0) { pmo->scratch.pmo_dcn4.optimal_vblank_reserved_time_for_stutter_us[pmo->scratch.pmo_dcn4.num_stutter_candidates] = (unsigned int)pmo->soc_bb->power_management_parameters.stutter_enter_plus_exit_latency_us; pmo->scratch.pmo_dcn4.num_stutter_candidates++; } From c9924feac91db4e59a9f3d1bc21b526c603846c0 Mon Sep 17 00:00:00 2001 From: Samson Tam Date: Sat, 19 Oct 2024 22:07:31 -0400 Subject: [PATCH 1842/1868] drm/amd/display: fix asserts in SPL during bootup [Why] During mode validation, there maybe modes that fail max_downscale_src_width check and scaling_quality taps are 0. This will cause an assert to trigger in spl_set_filters_data() because taps are 0. [How] Move taps calculation for non-adaptive scaling mode to separate function and call it if max_downscale_src_width fails. This will populate taps if scaling_quality taps are 0. Signed-off-by: Samson Tam --- drivers/gpu/drm/amd/display/dc/spl/dc_spl.c | 86 ++++++++++++--------- 1 file changed, 48 insertions(+), 38 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c b/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c index 133906e73a65c..9095da7b842bc 100644 --- a/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c +++ b/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c @@ -868,6 +868,50 @@ static bool spl_get_isharp_en(struct spl_in *spl_in, return enable_isharp; } +/* Calculate number of tap with adaptive scaling off */ +static void spl_get_taps_non_adaptive_scaler( + struct spl_scratch *spl_scratch, const struct spl_taps *in_taps) +{ + if (in_taps->h_taps == 0) { + if (spl_fixpt_ceil(spl_scratch->scl_data.ratios.horz) > 1) + spl_scratch->scl_data.taps.h_taps = spl_min(2 * spl_fixpt_ceil( + spl_scratch->scl_data.ratios.horz), 8); + else + spl_scratch->scl_data.taps.h_taps = 4; + } else + spl_scratch->scl_data.taps.h_taps = in_taps->h_taps; + + if (in_taps->v_taps == 0) { + if (spl_fixpt_ceil(spl_scratch->scl_data.ratios.vert) > 1) + spl_scratch->scl_data.taps.v_taps = spl_min(spl_fixpt_ceil(spl_fixpt_mul_int( + spl_scratch->scl_data.ratios.vert, 2)), 8); + else + spl_scratch->scl_data.taps.v_taps = 4; + } else + spl_scratch->scl_data.taps.v_taps = in_taps->v_taps; + + if (in_taps->v_taps_c == 0) { + if (spl_fixpt_ceil(spl_scratch->scl_data.ratios.vert_c) > 1) + spl_scratch->scl_data.taps.v_taps_c = spl_min(spl_fixpt_ceil(spl_fixpt_mul_int( + spl_scratch->scl_data.ratios.vert_c, 2)), 8); + else + spl_scratch->scl_data.taps.v_taps_c = 4; + } else + spl_scratch->scl_data.taps.v_taps_c = in_taps->v_taps_c; + + if (in_taps->h_taps_c == 0) { + if (spl_fixpt_ceil(spl_scratch->scl_data.ratios.horz_c) > 1) + spl_scratch->scl_data.taps.h_taps_c = spl_min(2 * spl_fixpt_ceil( + spl_scratch->scl_data.ratios.horz_c), 8); + else + spl_scratch->scl_data.taps.h_taps_c = 4; + } else if ((in_taps->h_taps_c % 2) != 0 && in_taps->h_taps_c != 1) + /* Only 1 and even h_taps_c are supported by hw */ + spl_scratch->scl_data.taps.h_taps_c = in_taps->h_taps_c - 1; + else + spl_scratch->scl_data.taps.h_taps_c = in_taps->h_taps_c; +} + /* Calculate optimal number of taps */ static bool spl_get_optimal_number_of_taps( int max_downscale_src_width, struct spl_in *spl_in, struct spl_scratch *spl_scratch, @@ -883,7 +927,7 @@ static bool spl_get_optimal_number_of_taps( if (spl_scratch->scl_data.viewport.width > spl_scratch->scl_data.h_active && max_downscale_src_width != 0 && spl_scratch->scl_data.viewport.width > max_downscale_src_width) { - memcpy(&spl_scratch->scl_data.taps, in_taps, sizeof(struct spl_taps)); + spl_get_taps_non_adaptive_scaler(spl_scratch, in_taps); *enable_easf_v = false; *enable_easf_h = false; *enable_isharp = false; @@ -910,43 +954,9 @@ static bool spl_get_optimal_number_of_taps( * From programming guide: taps = min{ ceil(2*H_RATIO,1), 8} for downscaling * taps = 4 for upscaling */ - if (skip_easf) { - if (in_taps->h_taps == 0) { - if (spl_fixpt_ceil(spl_scratch->scl_data.ratios.horz) > 1) - spl_scratch->scl_data.taps.h_taps = spl_min(2 * spl_fixpt_ceil( - spl_scratch->scl_data.ratios.horz), 8); - else - spl_scratch->scl_data.taps.h_taps = 4; - } else - spl_scratch->scl_data.taps.h_taps = in_taps->h_taps; - if (in_taps->v_taps == 0) { - if (spl_fixpt_ceil(spl_scratch->scl_data.ratios.vert) > 1) - spl_scratch->scl_data.taps.v_taps = spl_min(spl_fixpt_ceil(spl_fixpt_mul_int( - spl_scratch->scl_data.ratios.vert, 2)), 8); - else - spl_scratch->scl_data.taps.v_taps = 4; - } else - spl_scratch->scl_data.taps.v_taps = in_taps->v_taps; - if (in_taps->v_taps_c == 0) { - if (spl_fixpt_ceil(spl_scratch->scl_data.ratios.vert_c) > 1) - spl_scratch->scl_data.taps.v_taps_c = spl_min(spl_fixpt_ceil(spl_fixpt_mul_int( - spl_scratch->scl_data.ratios.vert_c, 2)), 8); - else - spl_scratch->scl_data.taps.v_taps_c = 4; - } else - spl_scratch->scl_data.taps.v_taps_c = in_taps->v_taps_c; - if (in_taps->h_taps_c == 0) { - if (spl_fixpt_ceil(spl_scratch->scl_data.ratios.horz_c) > 1) - spl_scratch->scl_data.taps.h_taps_c = spl_min(2 * spl_fixpt_ceil( - spl_scratch->scl_data.ratios.horz_c), 8); - else - spl_scratch->scl_data.taps.h_taps_c = 4; - } else if ((in_taps->h_taps_c % 2) != 0 && in_taps->h_taps_c != 1) - /* Only 1 and even h_taps_c are supported by hw */ - spl_scratch->scl_data.taps.h_taps_c = in_taps->h_taps_c - 1; - else - spl_scratch->scl_data.taps.h_taps_c = in_taps->h_taps_c; - } else { + if (skip_easf) + spl_get_taps_non_adaptive_scaler(spl_scratch, in_taps); + else { if (spl_is_yuv420(spl_in->basic_in.format)) { spl_scratch->scl_data.taps.h_taps = 6; spl_scratch->scl_data.taps.v_taps = 6; From 833476fcde44f891ca0448ba98aca538592e24a3 Mon Sep 17 00:00:00 2001 From: Austin Zheng Date: Tue, 5 Nov 2024 10:22:02 -0500 Subject: [PATCH 1843/1868] drm/amd/display: Improve Logic When Deciding MPO Support [Why/How] Early return possible if context has no clk_mgr. This will lead to an invalid power profile being returned which looks identical to a profile with the lowest power level. Add back logic that populated the power profile and overwrite the value if needed. Also, full validate should only done when prefer low power over MPO policy is set. Do fast validate if the regkey is set to a different policy. [Cleaned] Populate Power Profile In Case of Early Return [Why/How] Early return possible if context has no clk_mgr. This will lead to an invalid power profile being returned which looks identical to a profile with the lowest power level. Add back logic that populated the power profile and overwrite the value if needed. Signed-off-by: Austin Zheng --- drivers/gpu/drm/amd/display/dc/core/dc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 74719ea4a858a..51541e95fd47f 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -6080,11 +6080,11 @@ struct dc_power_profile dc_get_power_profile_for_dc_state(const struct dc_state { struct dc_power_profile profile = { 0 }; - if (!context || !context->clk_mgr || !context->clk_mgr->ctx || !context->clk_mgr->ctx->dc) + profile.power_level = !context->bw_ctx.bw.dcn.clk.p_state_change_support; + if (!context->clk_mgr || !context->clk_mgr->ctx || !context->clk_mgr->ctx->dc) return profile; struct dc *dc = context->clk_mgr->ctx->dc; - if (dc->res_pool->funcs->get_power_profile) profile.power_level = dc->res_pool->funcs->get_power_profile(context); return profile; From d9ca27468c49a4eb88cd99b0e876f0ff4d4071d3 Mon Sep 17 00:00:00 2001 From: Austin Zheng Date: Thu, 31 Oct 2024 14:10:39 -0400 Subject: [PATCH 1844/1868] drm/amd/display: Update SPL Taps Required For Integer Scaling [Why/How] Number of taps is incorrectly being set when integer scaling is enabled. Taps required when src_rect != dst_rect previously not considered. Perform the calculations when integer scaling is enabled. Set taps to 1 if the scaling ratio is 1:1. Signed-off-by: Austin Zheng --- drivers/gpu/drm/amd/display/dc/spl/dc_spl.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c b/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c index 9095da7b842bc..0ff30da9173b3 100644 --- a/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c +++ b/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c @@ -910,6 +910,16 @@ static void spl_get_taps_non_adaptive_scaler( spl_scratch->scl_data.taps.h_taps_c = in_taps->h_taps_c - 1; else spl_scratch->scl_data.taps.h_taps_c = in_taps->h_taps_c; + + if (IDENTITY_RATIO(spl_scratch->scl_data.ratios.horz)) + spl_scratch->scl_data.taps.h_taps = 1; + if (IDENTITY_RATIO(spl_scratch->scl_data.ratios.vert)) + spl_scratch->scl_data.taps.v_taps = 1; + if (IDENTITY_RATIO(spl_scratch->scl_data.ratios.horz_c)) + spl_scratch->scl_data.taps.h_taps_c = 1; + if (IDENTITY_RATIO(spl_scratch->scl_data.ratios.vert_c)) + spl_scratch->scl_data.taps.v_taps_c = 1; + } /* Calculate optimal number of taps */ @@ -936,10 +946,7 @@ static bool spl_get_optimal_number_of_taps( /* Disable adaptive scaler and sharpener when integer scaling is enabled */ if (spl_in->scaling_quality.integer_scaling) { - spl_scratch->scl_data.taps.h_taps = 1; - spl_scratch->scl_data.taps.v_taps = 1; - spl_scratch->scl_data.taps.v_taps_c = 1; - spl_scratch->scl_data.taps.h_taps_c = 1; + spl_get_taps_non_adaptive_scaler(spl_scratch, in_taps); *enable_easf_v = false; *enable_easf_h = false; *enable_isharp = false; From de023ce94edabb23b78aaa3a00b880e49b003d55 Mon Sep 17 00:00:00 2001 From: Nicholas Kazlauskas Date: Wed, 23 Oct 2024 12:53:37 -0400 Subject: [PATCH 1845/1868] drm/amd/display: Remove inaccessible registers from DMU diagnostics [Why] SEC_CNTL isn't readable by x86 and can block Z8 entry if read. [How] Remove the read. Signed-off-by: Nicholas Kazlauskas --- drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c index 2ccad79053c58..07336382471e6 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn35.c @@ -463,7 +463,7 @@ uint32_t dmub_dcn35_get_current_time(struct dmub_srv *dmub) void dmub_dcn35_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnostic_data *diag_data) { - uint32_t is_dmub_enabled, is_soft_reset, is_sec_reset; + uint32_t is_dmub_enabled, is_soft_reset; uint32_t is_traceport_enabled, is_cw6_enabled; if (!dmub || !diag_data) @@ -513,9 +513,6 @@ void dmub_dcn35_get_diagnostic_data(struct dmub_srv *dmub, struct dmub_diagnosti REG_GET(DMCUB_CNTL2, DMCUB_SOFT_RESET, &is_soft_reset); diag_data->is_dmcub_soft_reset = is_soft_reset; - REG_GET(DMCUB_SEC_CNTL, DMCUB_SEC_RESET_STATUS, &is_sec_reset); - diag_data->is_dmcub_secure_reset = is_sec_reset; - REG_GET(DMCUB_CNTL, DMCUB_TRACEPORT_EN, &is_traceport_enabled); diag_data->is_traceport_en = is_traceport_enabled; From 7d313299bc3bf1d9daaffa9eb278f0faa3c5f37d Mon Sep 17 00:00:00 2001 From: Meenakshikumar Somasundaram Date: Thu, 24 Oct 2024 23:06:37 -0400 Subject: [PATCH 1846/1868] drm/amd/display: Force MST blocked discovery for Asus ProArt display [Why] With 3 MST Asus ProArt MST display config in compliance test, couple of displays enumerated with side band messages in parallel, resulting in side band message timeouts. [How] Forcing MST blocked discovery for Asus ProArt monitor by adding monitor patch. [CLEANED] Adding flag for forced MST blocked discovery [Why] Need a flag to force MST blocked discovery for certain branch devices. [How] Added a flag to force MST blocked discovery in struct dc_panel_patch. Signed-off-by: Meenakshikumar Somasundaram --- drivers/gpu/drm/amd/display/dc/dc_types.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h index f0776484abb75..c7fa6d0f8f0ea 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_types.h @@ -181,6 +181,7 @@ struct dc_panel_patch { unsigned int disable_colorimetry; uint8_t blankstream_before_otg_off; bool oled_optimize_display_on; + unsigned int force_mst_blocked_discovery; }; struct dc_edid_caps { From 788b5a67a0c3741bd6de952c7af0e5c5dc0acbdf Mon Sep 17 00:00:00 2001 From: Ovidiu Bunea Date: Wed, 6 Nov 2024 16:25:18 -0500 Subject: [PATCH 1847/1868] drm/amd/display: Remove PIPE_DTO_SRC_SEL programming from set_dtbclk_dto This cherry-picks the following commit to 24.30: - 03f2fd76f82d7e6fe52a71e11d7dedca5f46d1db [why & how] There are cases where an OTG is remapped from driving a regular HDMI display to a DP/eDP display. There are also cases where DTBCLK needs to be enabled for HPO, but DTBCLK DTO programming may be done while OTG is still enabled which is dangerous as the PIPE_DTO_SRC_SEL programming may change the pixel clock generator source for a mapped and running OTG and cause it to hang. Remove the PIPE_DTO_SRC_SEL programming from this sequence since it is already done in program_pixel_clk(). Additionally, make sure that program_pixel_clk sets DTBCLK DTO as source for special HDMI cases. Signed-off-by: Ovidiu Bunea --- .../drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c | 15 +++++++++------ .../gpu/drm/amd/display/dc/dce/dce_clock_source.c | 6 ++++++ 2 files changed, 15 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c index 838d72eaa87fb..b363f5360818d 100644 --- a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c +++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c @@ -1392,10 +1392,10 @@ static void dccg35_set_dtbclk_dto( /* The recommended programming sequence to enable DTBCLK DTO to generate * valid pixel HPO DPSTREAM ENCODER, specifies that DTO source select should - * be set only after DTO is enabled + * be set only after DTO is enabled. + * PIPEx_DTO_SRC_SEL should not be programmed during DTBCLK update since OTG may still be on, and the + * programming is handled in program_pix_clk() regardless, so it can be removed from here. */ - REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst], - PIPE_DTO_SRC_SEL[params->otg_inst], 2); } else { switch (params->otg_inst) { case 0: @@ -1412,9 +1412,12 @@ static void dccg35_set_dtbclk_dto( break; } - REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[params->otg_inst], - DTBCLK_DTO_ENABLE[params->otg_inst], 0, - PIPE_DTO_SRC_SEL[params->otg_inst], params->is_hdmi ? 0 : 1); + /** + * PIPEx_DTO_SRC_SEL should not be programmed during DTBCLK update since OTG may still be on, and the + * programming is handled in program_pix_clk() regardless, so it can be removed from here. + */ + REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst], + DTBCLK_DTO_ENABLE[params->otg_inst], 0); REG_WRITE(DTBCLK_DTO_MODULO[params->otg_inst], 0); REG_WRITE(DTBCLK_DTO_PHASE[params->otg_inst], 0); diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c index b700608e42403..d6e7aaeb909ca 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c @@ -998,6 +998,12 @@ static bool dcn31_program_pix_clk( REG_UPDATE_2(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1, PIPE0_DTO_SRC_SEL, 2); +#if defined(CONFIG_DRM_AMD_DC_HDMI2_1) + else if (dc_is_hdmi_frl_signal(pix_clk_params->signal_type) || encoding == DP_128b_132b_ENCODING) + REG_UPDATE_2(PIXEL_RATE_CNTL[inst], + DP_DTO0_ENABLE, 0, + PIPE0_DTO_SRC_SEL, 2); +#endif else REG_UPDATE_2(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1, From 6c1732f81442f03d80acb9024367c407a1dc7480 Mon Sep 17 00:00:00 2001 From: Yihan Zhu Date: Wed, 30 Oct 2024 16:20:21 -0400 Subject: [PATCH 1848/1868] drm/amd/display: update pipe selection policy to check head pipe [Why] No check on head pipe during the dml to dc hw mapping will allow illegal pipe usage. This will result in a wrong pipe topology to cause mpcc tree totally mess up then cause system TDR. [How] Avoid to use the pipe is head in all check and avoid ODM slice during preferred pipe check. Signed-off-by: Yihan Zhu --- .../display/dc/dml2/dml2_dc_resource_mgmt.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c b/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c index 6eccf0241d857..9be9ed7e01d34 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c @@ -258,12 +258,23 @@ static unsigned int find_preferred_pipe_candidates(const struct dc_state *existi * However this condition comes with a caveat. We need to ignore pipes that will * require a change in OPP but still have the same stream id. For example during * an MPC to ODM transiton. + * + * Adding check to avoid pipe select on the head pipe by utilizing dc resource + * helper function resource_get_primary_dpp_pipe and comparing the pipe index. */ if (existing_state) { for (i = 0; i < pipe_count; i++) { if (existing_state->res_ctx.pipe_ctx[i].stream && existing_state->res_ctx.pipe_ctx[i].stream->stream_id == stream_id) { + struct pipe_ctx *head_pipe = + resource_get_primary_dpp_pipe(&existing_state->res_ctx.pipe_ctx[i]); + + // we should always respect the head pipe from selection + if (head_pipe && head_pipe->pipe_idx == i) + continue; if (existing_state->res_ctx.pipe_ctx[i].plane_res.hubp && - existing_state->res_ctx.pipe_ctx[i].plane_res.hubp->opp_id != i) + existing_state->res_ctx.pipe_ctx[i].plane_res.hubp->opp_id != i && + (existing_state->res_ctx.pipe_ctx[i].prev_odm_pipe || + existing_state->res_ctx.pipe_ctx[i].next_odm_pipe)) continue; preferred_pipe_candidates[num_preferred_candidates++] = i; @@ -292,6 +303,12 @@ static unsigned int find_last_resort_pipe_candidates(const struct dc_state *exis */ if (existing_state) { for (i = 0; i < pipe_count; i++) { + struct pipe_ctx *head_pipe = + resource_get_primary_dpp_pipe(&existing_state->res_ctx.pipe_ctx[i]); + + // we should always respect the head pipe from selection + if (head_pipe && head_pipe->pipe_idx == i) + continue; if ((existing_state->res_ctx.pipe_ctx[i].plane_res.hubp && existing_state->res_ctx.pipe_ctx[i].plane_res.hubp->opp_id != i) || existing_state->res_ctx.pipe_ctx[i].stream_res.tg) From 17a3f1bdf97ff1c3c608de5fbfc3a44a5d2cb188 Mon Sep 17 00:00:00 2001 From: Yihan Zhu Date: Mon, 11 Nov 2024 12:23:22 -0500 Subject: [PATCH 1849/1868] drm/amd/display: update head pipe check logic in pipe selection [WHY & HOW] Added pipe type check for DPP pipe type before executing head pipe check in the pipe selection logic in DML2 to avoid NULL pointer de-reference. Signed-off-by: Yihan Zhu --- .../gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c b/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c index 9be9ed7e01d34..1ed21c1b86a5b 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_dc_resource_mgmt.c @@ -266,7 +266,9 @@ static unsigned int find_preferred_pipe_candidates(const struct dc_state *existi for (i = 0; i < pipe_count; i++) { if (existing_state->res_ctx.pipe_ctx[i].stream && existing_state->res_ctx.pipe_ctx[i].stream->stream_id == stream_id) { struct pipe_ctx *head_pipe = - resource_get_primary_dpp_pipe(&existing_state->res_ctx.pipe_ctx[i]); + resource_is_pipe_type(&existing_state->res_ctx.pipe_ctx[i], DPP_PIPE) ? + resource_get_primary_dpp_pipe(&existing_state->res_ctx.pipe_ctx[i]) : + NULL; // we should always respect the head pipe from selection if (head_pipe && head_pipe->pipe_idx == i) @@ -304,7 +306,9 @@ static unsigned int find_last_resort_pipe_candidates(const struct dc_state *exis if (existing_state) { for (i = 0; i < pipe_count; i++) { struct pipe_ctx *head_pipe = - resource_get_primary_dpp_pipe(&existing_state->res_ctx.pipe_ctx[i]); + resource_is_pipe_type(&existing_state->res_ctx.pipe_ctx[i], DPP_PIPE) ? + resource_get_primary_dpp_pipe(&existing_state->res_ctx.pipe_ctx[i]) : + NULL; // we should always respect the head pipe from selection if (head_pipe && head_pipe->pipe_idx == i) From 0201e7bbb8b90550bf68f5d80b63c80a0adb2044 Mon Sep 17 00:00:00 2001 From: Peterson Date: Thu, 7 Nov 2024 19:20:02 -0500 Subject: [PATCH 1850/1868] drm/amd/display: Add a left edge pixel if in YCbCr422 or YCbCr420 and odm [Why] On some cards when odm is used, the monitor will have 2 separate pipes split vertically. When compression is used on the YCbCr colour space on the second pipe to have correct colours, we need to read a pixel from the end of first pipe to accurately display colours. Hardware was programmed properly to account for this extra pixel but it was not calculated properly in software causing a split screen on some monitors. [How] The fix adjusts the second pipe's viewport and timings if the pixel encoding is YCbCr422 or YCbCr420. Signed-off-by: Peterson --- .../dc/resource/dcn20/dcn20_resource.c | 23 +++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c index 7d14b6538ebb1..afc02462f191f 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c @@ -1505,6 +1505,7 @@ bool dcn20_split_stream_for_odm( if (prev_odm_pipe->plane_state) { struct scaler_data *sd = &prev_odm_pipe->plane_res.scl_data; + struct output_pixel_processor *opp = next_odm_pipe->stream_res.opp; int new_width; /* HACTIVE halved for odm combine */ @@ -1538,7 +1539,28 @@ bool dcn20_split_stream_for_odm( sd->viewport_c.x += dc_fixpt_floor(dc_fixpt_mul_int( sd->ratios.horz_c, sd->h_active - sd->recout.x)); sd->recout.x = 0; + + /* + * When odm is used in YcbCr422 or 420 colour space, a split screen + * will be seen with the previous calculations since the extra left + * edge pixel is accounted for in fmt but not in viewport. + * + * Below are calculations which fix the split by fixing the calculations + * if there is an extra left edge pixel. + */ + if (opp && opp->funcs->opp_get_left_edge_extra_pixel_count + && opp->funcs->opp_get_left_edge_extra_pixel_count( + opp, next_odm_pipe->stream->timing.pixel_encoding, + resource_is_pipe_type(next_odm_pipe, OTG_MASTER)) == 1) { + sd->h_active += 1; + sd->recout.width += 1; + sd->viewport.x -= dc_fixpt_ceil(dc_fixpt_mul_int(sd->ratios.horz, 1)); + sd->viewport_c.x -= dc_fixpt_ceil(dc_fixpt_mul_int(sd->ratios.horz, 1)); + sd->viewport_c.width += dc_fixpt_ceil(dc_fixpt_mul_int(sd->ratios.horz, 1)); + sd->viewport.width += dc_fixpt_ceil(dc_fixpt_mul_int(sd->ratios.horz, 1)); + } } + if (!next_odm_pipe->top_pipe) next_odm_pipe->stream_res.opp = pool->opps[next_odm_pipe->pipe_idx]; else @@ -2126,6 +2148,7 @@ bool dcn20_fast_validate_bw( ASSERT(0); } } + /* Actual dsc count per stream dsc validation*/ if (!dcn20_validate_dsc(dc, context)) { context->bw_ctx.dml.vba.ValidationStatus[context->bw_ctx.dml.vba.soc.num_states] = From 25a4e59a19750f9eff2676a74a83a3f3a84a7f47 Mon Sep 17 00:00:00 2001 From: Zhikai Zhai Date: Mon, 14 Oct 2024 18:19:31 +0800 Subject: [PATCH 1851/1868] drm/amd/display: skip set AVmute when hdmi frl dsc [Why & How] The GCP is not required to be transmitted when video stream is compressed accroding to the HDMI2.1 specification, and skip it. Signed-off-by: Zhikai Zhai --- drivers/gpu/drm/amd/display/dc/link/link_dpms.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c index 6a2fecb49dea7..5d90096df60a9 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c @@ -721,6 +721,11 @@ static void set_avmute(struct pipe_ctx *pipe_ctx, bool enable) if (!dc_is_hdmi_signal(pipe_ctx->stream->signal)) return; +#if defined(CONFIG_DRM_AMD_DC_HDMI2_1) + if (pipe_ctx->stream->timing.flags.DSC) + return; +#endif + dc->hwss.set_avmute(pipe_ctx, enable); } From 853289b97e7750f5be700c02c45c10a332bf0f82 Mon Sep 17 00:00:00 2001 From: loanchen Date: Thu, 14 Nov 2024 17:53:41 +0800 Subject: [PATCH 1852/1868] drm/amd/display: Correct prefetch calculation Cherry-pick from ec0ab6b5. [Why] The minimum value of the dst_y_prefetch_equ was not correct in prefetch calculation whice causes OPTC underflow. [How] Add the min operation of dst_y_prefetch_equ in prefetch calculation. Signed-off-by: loanchen Signed-off-by: Hugo Hu --- drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c b/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c index d851c081e3768..8dabb1ac0b684 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c @@ -1222,6 +1222,7 @@ static dml_bool_t CalculatePrefetchSchedule(struct display_mode_lib_scratch_st * s->dst_y_prefetch_oto = s->Tvm_oto_lines + 2 * s->Tr0_oto_lines + s->Lsw_oto; s->dst_y_prefetch_equ = p->VStartup - (*p->TSetup + dml_max(p->TWait + p->TCalc, *p->Tdmdl)) / s->LineTime - (*p->DSTYAfterScaler + (dml_float_t) *p->DSTXAfterScaler / (dml_float_t)p->myPipe->HTotal); + s->dst_y_prefetch_equ = dml_min(s->dst_y_prefetch_equ, 63.75); // limit to the reg limit of U6.2 for DST_Y_PREFETCH #ifdef __DML_VBA_DEBUG__ dml_print("DML::%s: HTotal = %u\n", __func__, p->myPipe->HTotal); From f5b5dc451174c4cfff2150db9145bcd30eddde46 Mon Sep 17 00:00:00 2001 From: Yihan Zhu Date: Mon, 7 Oct 2024 14:32:59 -0400 Subject: [PATCH 1853/1868] drm/amd/display: w/a to program DISPCLK_R_GATE_DISABLE DCN35 [WHY & HOW] Cursor corruption observed on USBC display only when system setup Eyefinity with a reboot. Cursor memory might still in the lightsleep state due to voltage issue, we need program DISPCLK_R_GATE_DISABLE to avoid this issue only on DCN35. port commit id: f7101578789 Signed-off-by: Yihan Zhu Signed-off-by: Fudong Wang --- .../drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h | 1 + .../drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h | 1 + .../drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c | 22 +++++++++++++++---- 3 files changed, 20 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h b/drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h index cd1706d301e77..f09cba8e29cce 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn20/dcn20_dpp.h @@ -690,6 +690,7 @@ struct dcn20_dpp { int lb_memory_size; int lb_bits_per_entry; bool is_write_to_ram_a_safe; + bool dispclk_r_gate_disable; struct scaler_data scl_data; struct pwl_params pwl_data; }; diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h index b110f35ef66bd..f236824126e94 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h @@ -572,6 +572,7 @@ struct dcn3_dpp { int lb_memory_size; int lb_bits_per_entry; bool is_write_to_ram_a_safe; + bool dispclk_r_gate_disable; struct scaler_data scl_data; struct pwl_params pwl_data; }; diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c index 9f885a03eec6a..62b7012cda430 100644 --- a/drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c +++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c @@ -50,11 +50,21 @@ void dpp35_dppclk_control( DPPCLK_RATE_CONTROL, dppclk_div, DPP_CLOCK_ENABLE, 1); else - REG_UPDATE(DPP_CONTROL, - DPP_CLOCK_ENABLE, 1); + if (dpp->dispclk_r_gate_disable) + REG_UPDATE_2(DPP_CONTROL, + DPP_CLOCK_ENABLE, 1, + DISPCLK_R_GATE_DISABLE, 1); + else + REG_UPDATE(DPP_CONTROL, + DPP_CLOCK_ENABLE, 1); } else - REG_UPDATE(DPP_CONTROL, - DPP_CLOCK_ENABLE, 0); + if (dpp->dispclk_r_gate_disable) + REG_UPDATE_2(DPP_CONTROL, + DPP_CLOCK_ENABLE, 0, + DISPCLK_R_GATE_DISABLE, 0); + else + REG_UPDATE(DPP_CONTROL, + DPP_CLOCK_ENABLE, 0); } void dpp35_program_bias_and_scale_fcnv( @@ -126,6 +136,10 @@ bool dpp35_construct( (const struct dcn3_dpp_mask *)(tf_mask)); dpp->base.funcs = &dcn35_dpp_funcs; + + // w/a for cursor memory stuck in LS by programming DISPCLK_R_GATE_DISABLE, limit w/a to some ASIC revs + if (dpp->base.ctx->asic_id.hw_internal_rev <= 0x10) + dpp->dispclk_r_gate_disable = true; return ret; } From 098c46bdf40bd632f2429cd98a914916d9bb9813 Mon Sep 17 00:00:00 2001 From: Fudongwang Date: Wed, 30 Oct 2024 16:45:56 +0800 Subject: [PATCH 1854/1868] drm/amd/display: always blank stream before disable crtc. [why & how] Garbage will show due to dig is on. So blank stream needed. port commit id: 1e8f0e34c300 Signed-off-by: Fudongwang --- .../gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c index bfc78a42bc2a7..0f746f12b385e 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c @@ -517,15 +517,18 @@ static void dcn31_reset_back_end_for_pipe( dc->hwss.set_abm_immediate_disable(pipe_ctx); - if ((!pipe_ctx->stream->dpms_off || pipe_ctx->stream->link->link_status.link_active) - && pipe_ctx->stream->sink && pipe_ctx->stream->sink->edid_caps.panel_patch.blankstream_before_otg_off) { + link = pipe_ctx->stream->link; + + if ((!pipe_ctx->stream->dpms_off || link->link_status.link_active) && + (link->connector_signal == SIGNAL_TYPE_EDP)) dc->hwss.blank_stream(pipe_ctx); - } pipe_ctx->stream_res.tg->funcs->set_dsc_config( pipe_ctx->stream_res.tg, OPTC_DSC_DISABLED, 0, 0); + pipe_ctx->stream_res.tg->funcs->disable_crtc(pipe_ctx->stream_res.tg); + pipe_ctx->stream_res.tg->funcs->enable_optc_clock(pipe_ctx->stream_res.tg, false); if (pipe_ctx->stream_res.tg->funcs->set_odm_bypass) pipe_ctx->stream_res.tg->funcs->set_odm_bypass( @@ -537,7 +540,6 @@ static void dcn31_reset_back_end_for_pipe( pipe_ctx->stream_res.tg->funcs->set_drr( pipe_ctx->stream_res.tg, NULL); - link = pipe_ctx->stream->link; /* DPMS may already disable or */ /* dpms_off status is incorrect due to fastboot * feature. When system resume from S4 with second From 0df912ab39efd40507a11a74ac5aa5d325cac4c6 Mon Sep 17 00:00:00 2001 From: Joshua Aberback Date: Mon, 28 Oct 2024 17:12:22 -0400 Subject: [PATCH 1855/1868] drm/amd/display: Fix handling of plane refcount [Why] In commit_planes_and_stream_update_with_new_context, it is possible to encounter a scenario where a plane with only one reference is retrieved in dc_plane_get_plane_configs, then this plane is released during the minimal transition, then in reconfigure_hwfq there's a crash due to the plane's memory having been freed. Since dc_plane_get_plane_configs is creating new references to existing planes, the planes should be retained and released accordingly, which should resolve the issue above. However, doing so exposed another issue, the backup / restore planes mechanism doesn't maintain current refcount, which can also cause crashes if the refcount changes in between backup and restore operations. [How] - retain planes in dc_plane_get_plane_configs - add new function dc_plane_release_plane_configs - release planes in callers of dc_plane_get_plane_configs where needed - cache and re-apply current refcount when restoring planes Signed-off-by: Joshua Aberback --- drivers/gpu/drm/amd/display/dc/core/dc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 51541e95fd47f..edb70cc0ccba7 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -3128,7 +3128,10 @@ static void restore_planes_and_stream_state( return; for (i = 0; i < status->plane_count; i++) { + /* refcount will always be valid, restore everything else */ + struct kref refcount = status->plane_states[i]->refcount; *status->plane_states[i] = scratch->plane_states[i]; + status->plane_states[i]->refcount = refcount; } *stream = scratch->stream_state; } From dec18a7bd64aab481caedb42a72e550f56feb5f2 Mon Sep 17 00:00:00 2001 From: Dillon Varone Date: Wed, 13 Nov 2024 16:44:15 -0500 Subject: [PATCH 1856/1868] drm/amd/display: Limit VTotal range to max hw cap minus fp [WHY&HOW] Hardware does not support the VTotal to be between fp2 lines of the maximum possible VTotal, so add a capability flag to track it and apply where necessary. Signed-off-by: Dillon Varone --- drivers/gpu/drm/amd/display/dc/dc.h | 1 + .../dc/dml2/dml21/dml21_translation_helper.c | 27 +++++++++++++++++-- .../dc/resource/dcn30/dcn30_resource.c | 1 + .../dc/resource/dcn302/dcn302_resource.c | 1 + .../dc/resource/dcn303/dcn303_resource.c | 1 + .../dc/resource/dcn32/dcn32_resource.c | 1 + .../dc/resource/dcn321/dcn321_resource.c | 1 + .../dc/resource/dcn35/dcn35_resource.c | 1 + .../dc/resource/dcn351/dcn351_resource.c | 1 + .../dc/resource/dcn401/dcn401_resource.c | 1 + .../amd/display/modules/freesync/freesync.c | 13 ++++++++- 11 files changed, 46 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 6f3875b212eb2..940d2fb0ee83d 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -289,6 +289,7 @@ struct dc_caps { uint16_t subvp_vertical_int_margin_us; bool seamless_odm; uint32_t max_v_total; + bool vtotal_limited_by_fp2; uint32_t max_disp_clock_khz_at_vmin; uint8_t subvp_drr_vblank_start_margin_us; bool cursor_not_scaled; diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c index 138b4b1e42ed7..f66493528f420 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml21/dml21_translation_helper.c @@ -339,11 +339,22 @@ void dml21_apply_soc_bb_overrides(struct dml2_initialize_instance_in_out *dml_in // } } +static unsigned int calc_max_hardware_v_total(const struct dc_stream_state *stream) +{ + unsigned int max_hw_v_total = stream->ctx->dc->caps.max_v_total; + + if (stream->ctx->dc->caps.vtotal_limited_by_fp2) { + max_hw_v_total -= stream->timing.v_front_porch + 1; + } + + return max_hw_v_total; +} + static void populate_dml21_timing_config_from_stream_state(struct dml2_timing_cfg *timing, struct dc_stream_state *stream, struct dml2_context *dml_ctx) { - unsigned int hblank_start, vblank_start; + unsigned int hblank_start, vblank_start, min_hardware_refresh_in_uhz; timing->h_active = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right; timing->v_active = stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.v_border_top; @@ -371,11 +382,23 @@ static void populate_dml21_timing_config_from_stream_state(struct dml2_timing_cf - stream->timing.v_border_top - stream->timing.v_border_bottom; timing->drr_config.enabled = stream->ignore_msa_timing_param; - timing->drr_config.min_refresh_uhz = stream->timing.min_refresh_in_uhz; timing->drr_config.drr_active_variable = stream->vrr_active_variable; timing->drr_config.drr_active_fixed = stream->vrr_active_fixed; timing->drr_config.disallowed = !stream->allow_freesync; + /* limit min refresh rate to DC cap */ + min_hardware_refresh_in_uhz = stream->timing.min_refresh_in_uhz; + if (stream->ctx->dc->caps.max_v_total != 0) { + min_hardware_refresh_in_uhz = div64_u64((stream->timing.pix_clk_100hz * 100000000ULL), + (stream->timing.h_total * (long long)calc_max_hardware_v_total(stream))); + } + + if (stream->timing.min_refresh_in_uhz > min_hardware_refresh_in_uhz) { + timing->drr_config.min_refresh_uhz = stream->timing.min_refresh_in_uhz; + } else { + timing->drr_config.min_refresh_uhz = min_hardware_refresh_in_uhz; + } + if (dml_ctx->config.callbacks.get_max_flickerless_instant_vtotal_increase && stream->ctx->dc->config.enable_fpo_flicker_detection == 1) timing->drr_config.max_instant_vtotal_delta = dml_ctx->config.callbacks.get_max_flickerless_instant_vtotal_increase(stream, false); diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c index 5040a4c6ed186..75cc84473a577 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c @@ -2354,6 +2354,7 @@ static bool dcn30_resource_construct( dc->caps.dp_hdmi21_pcon_support = true; dc->caps.max_v_total = (1 << 15) - 1; + dc->caps.vtotal_limited_by_fp2 = true; /* read VBIOS LTTPR caps */ { diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c index 5791b5cc28752..320b040d591d1 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c @@ -1234,6 +1234,7 @@ static bool dcn302_resource_construct( dc->caps.extended_aux_timeout_support = true; dc->caps.dmcub_support = true; dc->caps.max_v_total = (1 << 15) - 1; + dc->caps.vtotal_limited_by_fp2 = true; /* Color pipeline capabilities */ dc->caps.color.dpp.dcn_arch = 1; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c index 63f0f882c8610..297cf4b5600da 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c @@ -1179,6 +1179,7 @@ static bool dcn303_resource_construct( dc->caps.extended_aux_timeout_support = true; dc->caps.dmcub_support = true; dc->caps.max_v_total = (1 << 15) - 1; + dc->caps.vtotal_limited_by_fp2 = true; /* Color pipeline capabilities */ dc->caps.color.dpp.dcn_arch = 1; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c index f758d463e460e..21ee6c3180645 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c @@ -2190,6 +2190,7 @@ static bool dcn32_resource_construct( dc->caps.dmcub_support = true; dc->caps.seamless_odm = true; dc->caps.max_v_total = (1 << 15) - 1; + dc->caps.vtotal_limited_by_fp2 = true; /* Color pipeline capabilities */ dc->caps.color.dpp.dcn_arch = 1; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c index c401d713ada51..1617bdfba0025 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c @@ -1741,6 +1741,7 @@ static bool dcn321_resource_construct( dc->caps.extended_aux_timeout_support = true; dc->caps.dmcub_support = true; dc->caps.max_v_total = (1 << 15) - 1; + dc->caps.vtotal_limited_by_fp2 = true; /* Color pipeline capabilities */ dc->caps.color.dpp.dcn_arch = 1; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c index 893a9d9ee870d..ed3238edaf791 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c @@ -1850,6 +1850,7 @@ static bool dcn35_resource_construct( dc->caps.zstate_support = true; dc->caps.ips_support = true; dc->caps.max_v_total = (1 << 15) - 1; + dc->caps.vtotal_limited_by_fp2 = true; /* Color pipeline capabilities */ dc->caps.color.dpp.dcn_arch = 1; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c index 70abd32ce2ad1..c274861e83c73 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c @@ -1829,6 +1829,7 @@ static bool dcn351_resource_construct( dc->caps.zstate_support = true; dc->caps.ips_support = true; dc->caps.max_v_total = (1 << 15) - 1; + dc->caps.vtotal_limited_by_fp2 = true; /* Color pipeline capabilities */ dc->caps.color.dpp.dcn_arch = 1; diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c index 46feff9348d96..2b79a8783f41c 100644 --- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c +++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c @@ -1864,6 +1864,7 @@ static bool dcn401_resource_construct( dc->caps.extended_aux_timeout_support = true; dc->caps.dmcub_support = true; dc->caps.max_v_total = (1 << 15) - 1; + dc->caps.vtotal_limited_by_fp2 = true; if (ASICREV_IS_GC_12_0_1_A0(dc->ctx->asic_id.hw_internal_rev)) dc->caps.dcc_plane_width_limit = 7680; diff --git a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c index fc4268729017e..fc4f5415ce0ba 100644 --- a/drivers/gpu/drm/amd/display/modules/freesync/freesync.c +++ b/drivers/gpu/drm/amd/display/modules/freesync/freesync.c @@ -122,6 +122,17 @@ static unsigned int calc_duration_in_us_from_v_total( return duration_in_us; } +static unsigned int calc_max_hardware_v_total(const struct dc_stream_state *stream) +{ + unsigned int max_hw_v_total = stream->ctx->dc->caps.max_v_total; + + if (stream->ctx->dc->caps.vtotal_limited_by_fp2) { + max_hw_v_total -= stream->timing.v_front_porch + 1; + } + + return max_hw_v_total; +} + unsigned int mod_freesync_calc_v_total_from_refresh( const struct dc_stream_state *stream, unsigned int refresh_in_uhz) @@ -1013,7 +1024,7 @@ void mod_freesync_build_vrr_params(struct mod_freesync *mod_freesync, if (stream->ctx->dc->caps.max_v_total != 0 && stream->timing.h_total != 0) { min_hardware_refresh_in_uhz = div64_u64((stream->timing.pix_clk_100hz * 100000000ULL), - (stream->timing.h_total * (long long)stream->ctx->dc->caps.max_v_total)); + (stream->timing.h_total * (long long)calc_max_hardware_v_total(stream))); } /* Limit minimum refresh rate to what can be supported by hardware */ min_refresh_in_uhz = min_hardware_refresh_in_uhz > in_config->min_refresh_in_uhz ? From 9f385fd1379fa99f44e0c16a6ca8041dedf23e8b Mon Sep 17 00:00:00 2001 From: Samson Tam Date: Thu, 7 Nov 2024 19:05:03 -0500 Subject: [PATCH 1857/1868] drm/amd/display: allow chroma 1:1 scaling when sharpness is off [Why] SPL code forces taps to 1 when ratio is 1:1 and sharpness is off But for chroma 1:1, need taps > 1 to handle cositing EASF only applies to luma. Previously was checking both luma and chroma taps to determine whether to enable EASF [How] Do not force chroma taps to 1 when ratio is 1:1 for YUV420 Remove 420_CHROMA_BYPASS mode for scaler Only check if luma taps are supported before determine whether to enable EASF or not Signed-off-by: Samson Tam --- drivers/gpu/drm/amd/display/dc/spl/dc_spl.c | 40 +++++++++++---------- 1 file changed, 22 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c b/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c index 0ff30da9173b3..7ceeefac31f72 100644 --- a/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c +++ b/drivers/gpu/drm/amd/display/dc/spl/dc_spl.c @@ -739,14 +739,13 @@ static enum scl_mode spl_get_dscl_mode(const struct spl_in *spl_in, return SCL_MODE_SCALING_444_RGB_ENABLE; } - /* Bypass YUV if at 1:1 with no ISHARP or if doing 2:1 YUV - * downscale without EASF + /* + * Bypass YUV if Y is 1:1 with no ISHARP + * Do not bypass UV at 1:1 for cositing to be applied */ - if ((!enable_isharp) && (!enable_easf)) { + if (!enable_isharp) { if (data->ratios.horz.value == one && data->ratios.vert.value == one) return SCL_MODE_SCALING_420_LUMA_BYPASS; - if (data->ratios.horz_c.value == one && data->ratios.vert_c.value == one) - return SCL_MODE_SCALING_420_CHROMA_BYPASS; } return SCL_MODE_SCALING_420_YCBCR_ENABLE; @@ -933,6 +932,7 @@ static bool spl_get_optimal_number_of_taps( int min_taps_y, min_taps_c; enum lb_memory_config lb_config; bool skip_easf = false; + bool is_ycbcr = spl_dscl_is_video_format(spl_in->basic_in.format); if (spl_scratch->scl_data.viewport.width > spl_scratch->scl_data.h_active && max_downscale_src_width != 0 && @@ -1040,12 +1040,10 @@ static bool spl_get_optimal_number_of_taps( spl_scratch->scl_data.taps.h_taps_c = 4; if (spl_is_yuv420(spl_in->basic_in.format)) { - if ((spl_scratch->scl_data.taps.h_taps <= 4) || - (spl_scratch->scl_data.taps.h_taps_c <= 3)) { + if (spl_scratch->scl_data.taps.h_taps <= 4) { *enable_easf_v = false; *enable_easf_h = false; - } else if ((spl_scratch->scl_data.taps.v_taps <= 3) || - (spl_scratch->scl_data.taps.v_taps_c <= 3)) { + } else if (spl_scratch->scl_data.taps.v_taps <= 3) { *enable_easf_v = false; *enable_easf_h = true; } else { @@ -1074,10 +1072,9 @@ static bool spl_get_optimal_number_of_taps( /* Sharpener requires scaler to be enabled, including for 1:1 * Check if ISHARP can be enabled - * If ISHARP is not enabled, for 1:1, set taps to 1 and disable - * EASF - * For case of 2:1 YUV where chroma is 1:1, set taps to 1 if - * EASF is not enabled + * If ISHARP is not enabled, set taps to 1 if ratio is 1:1 + * except for chroma taps. Keep previous taps so it can + * handle cositing */ *enable_isharp = spl_get_isharp_en(spl_in, spl_scratch); @@ -1087,20 +1084,28 @@ static bool spl_get_optimal_number_of_taps( spl_scratch->scl_data.taps.h_taps = 1; spl_scratch->scl_data.taps.v_taps = 1; - if (IDENTITY_RATIO(spl_scratch->scl_data.ratios.horz_c)) + if (IDENTITY_RATIO(spl_scratch->scl_data.ratios.horz_c) && !is_ycbcr) spl_scratch->scl_data.taps.h_taps_c = 1; - if (IDENTITY_RATIO(spl_scratch->scl_data.ratios.vert_c)) + if (IDENTITY_RATIO(spl_scratch->scl_data.ratios.vert_c) && !is_ycbcr) spl_scratch->scl_data.taps.v_taps_c = 1; *enable_easf_v = false; *enable_easf_h = false; } else { if ((!*enable_easf_h) && + (IDENTITY_RATIO(spl_scratch->scl_data.ratios.horz))) + spl_scratch->scl_data.taps.h_taps = 1; + + if ((!*enable_easf_v) && + (IDENTITY_RATIO(spl_scratch->scl_data.ratios.vert))) + spl_scratch->scl_data.taps.v_taps = 1; + + if ((!*enable_easf_h) && !is_ycbcr && (IDENTITY_RATIO(spl_scratch->scl_data.ratios.horz_c))) spl_scratch->scl_data.taps.h_taps_c = 1; - if ((!*enable_easf_v) && + if ((!*enable_easf_v) && !is_ycbcr && (IDENTITY_RATIO(spl_scratch->scl_data.ratios.vert_c))) spl_scratch->scl_data.taps.v_taps_c = 1; } @@ -1111,8 +1116,7 @@ static bool spl_get_optimal_number_of_taps( static void spl_set_black_color_data(enum spl_pixel_format format, struct scl_black_color *scl_black_color) { - bool ycbcr = format >= SPL_PIXEL_FORMAT_VIDEO_BEGIN - && format <= SPL_PIXEL_FORMAT_VIDEO_END; + bool ycbcr = spl_dscl_is_video_format(format); if (ycbcr) { scl_black_color->offset_rgb_y = BLACK_OFFSET_RGB_Y; scl_black_color->offset_rgb_cbcr = BLACK_OFFSET_CBCR; From 503d1d651b043b158ce4582c7c9d491565be0541 Mon Sep 17 00:00:00 2001 From: loanchen Date: Wed, 27 Nov 2024 17:45:52 +0800 Subject: [PATCH 1858/1868] drm/amd/display: Populate chroma prefetch parameters, DET buffer fix [WHY] Soft hang/lag observed during 10bit playback + moving cursor, corruption observed in other tickets for same reason, also failing MPO. 1. Currently, we are always running calculate_lowest_supported_state_for_temp_read which is only necessary on dGPU 2. Fast validate path does not apply DET buffer allocation policy 3. Prefetch UrgBFactor chroma parameter not populated in prefetch calculation [HOW] 1. Add a check to see if we are on APU, if so, skip the code 2. Add det buffer alloc policy checks to fast validate path 3. Populate UrgentBurstChroma param in call to calculate UrgBChroma prefetch values -revision commits: small formatting/brackets/null check addition + remove test change + dGPU code Signed-off-by: Ausef Yousof Signed-off-by: loanchen --- .../amd/display/dc/dml2/display_mode_core.c | 5 ++- .../drm/amd/display/dc/dml2/dml2_wrapper.c | 35 +++++++++++++------ 2 files changed, 29 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c b/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c index 8dabb1ac0b684..be87dc0f07799 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/display_mode_core.c @@ -6434,7 +6434,7 @@ static void dml_prefetch_check(struct display_mode_lib_st *mode_lib) /* Output */ &mode_lib->ms.UrgentBurstFactorCursorPre[k], &mode_lib->ms.UrgentBurstFactorLumaPre[k], - &mode_lib->ms.UrgentBurstFactorChroma[k], + &mode_lib->ms.UrgentBurstFactorChromaPre[k], &mode_lib->ms.NotUrgentLatencyHidingPre[k]); mode_lib->ms.cursor_bw_pre[k] = mode_lib->ms.cache_display_cfg.plane.NumberOfCursors[k] * mode_lib->ms.cache_display_cfg.plane.CursorWidth[k] * @@ -9190,6 +9190,8 @@ void dml_core_mode_programming(struct display_mode_lib_st *mode_lib, const struc &locals->FractionOfUrgentBandwidth, &s->dummy_boolean[0]); // dml_bool_t *PrefetchBandwidthSupport + + if (s->VRatioPrefetchMoreThanMax != false || s->DestinationLineTimesForPrefetchLessThan2 != false) { dml_print("DML::%s: VRatioPrefetchMoreThanMax = %u\n", __func__, s->VRatioPrefetchMoreThanMax); dml_print("DML::%s: DestinationLineTimesForPrefetchLessThan2 = %u\n", __func__, s->DestinationLineTimesForPrefetchLessThan2); @@ -9204,6 +9206,7 @@ void dml_core_mode_programming(struct display_mode_lib_st *mode_lib, const struc } } + if (locals->PrefetchModeSupported == true && mode_lib->ms.support.ImmediateFlipSupport == true) { locals->BandwidthAvailableForImmediateFlip = CalculateBandwidthAvailableForImmediateFlip( mode_lib->ms.num_active_planes, diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c b/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c index 866b0abcff1ba..4d64c45930da4 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c +++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c @@ -533,14 +533,21 @@ static bool optimize_pstate_with_svp_and_drr(struct dml2_context *dml2, struct d static bool call_dml_mode_support_and_programming(struct dc_state *context) { unsigned int result = 0; - unsigned int min_state; + unsigned int min_state = 0; int min_state_for_g6_temp_read = 0; + + + if (!context) + return false; + struct dml2_context *dml2 = context->bw_ctx.dml2; struct dml2_wrapper_scratch *s = &dml2->v20.scratch; - min_state_for_g6_temp_read = calculate_lowest_supported_state_for_temp_read(dml2, context); + if (!context->streams[0]->sink->link->dc->caps.is_apu) { + min_state_for_g6_temp_read = calculate_lowest_supported_state_for_temp_read(dml2, context); - ASSERT(min_state_for_g6_temp_read >= 0); + ASSERT(min_state_for_g6_temp_read >= 0); + } if (!dml2->config.use_native_pstate_optimization) { result = optimize_pstate_with_svp_and_drr(dml2, context); @@ -551,14 +558,20 @@ static bool call_dml_mode_support_and_programming(struct dc_state *context) /* Upon trying to sett certain frequencies in FRL, min_state_for_g6_temp_read is reported as -1. This leads to an invalid value of min_state causing crashes later on. * Use the default logic for min_state only when min_state_for_g6_temp_read is a valid value. In other cases, use the value calculated by the DML directly. */ - if (min_state_for_g6_temp_read >= 0) - min_state = min_state_for_g6_temp_read > s->mode_support_params.out_lowest_state_idx ? min_state_for_g6_temp_read : s->mode_support_params.out_lowest_state_idx; - else - min_state = s->mode_support_params.out_lowest_state_idx; - - if (result) - result = dml_mode_programming(&dml2->v20.dml_core_ctx, min_state, &s->cur_display_config, true); + if (!context->streams[0]->sink->link->dc->caps.is_apu) { + if (min_state_for_g6_temp_read >= 0) + min_state = min_state_for_g6_temp_read > s->mode_support_params.out_lowest_state_idx ? min_state_for_g6_temp_read : s->mode_support_params.out_lowest_state_idx; + else + min_state = s->mode_support_params.out_lowest_state_idx; + } + if (result) { + if (!context->streams[0]->sink->link->dc->caps.is_apu) { + result = dml_mode_programming(&dml2->v20.dml_core_ctx, min_state, &s->cur_display_config, true); + } else { + result = dml_mode_programming(&dml2->v20.dml_core_ctx, s->mode_support_params.out_lowest_state_idx, &s->cur_display_config, true); + } + } return result; } @@ -687,6 +700,8 @@ static bool dml2_validate_only(struct dc_state *context) build_unoptimized_policy_settings(dml2->v20.dml_core_ctx.project, &dml2->v20.dml_core_ctx.policy); map_dc_state_into_dml_display_cfg(dml2, context, &dml2->v20.scratch.cur_display_config); + if (!dml2->config.skip_hw_state_mapping) + dml2_apply_det_buffer_allocation_policy(dml2, &dml2->v20.scratch.cur_display_config); result = pack_and_call_dml_mode_support_ex(dml2, &dml2->v20.scratch.cur_display_config, From 795c51cd760e2926da28aae19532ad399aa1efab Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Tue, 8 Oct 2024 09:23:12 +0530 Subject: [PATCH 1859/1868] drm/amdgpu: fix dm_suspend/resume arguments to ip_block MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit "build failure after merge of the amdgpu tree" dm_suspend/dm_resume functions argument mismatch not caught in validation as it was under config CONFIG_DEBUG_KERNEL_DC which wasnt enabled by default. Change argument from adev to ip_block. Signed-off-by: Sunil Khatri Acked-by: Christian König (cherry picked from commit 0d1c554f95e555bc5164e73caafb3f2b243c87e2) --- drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 8d85badafbceb..f622eb1551df7 100755 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -5298,15 +5298,20 @@ static ssize_t s3_debug_store(struct device *device, int s3_state; struct drm_device *drm_dev = dev_get_drvdata(device); struct amdgpu_device *adev = drm_to_adev(drm_dev); + struct amdgpu_ip_block *ip_block; + + ip_block = amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_DCE); + if (!ip_block) + return -EINVAL; ret = kstrtoint(buf, 0, &s3_state); if (ret == 0) { if (s3_state) { - dm_resume(adev); + dm_resume(ip_block); drm_kms_helper_hotplug_event(adev_to_drm(adev)); } else - dm_suspend(adev); + dm_suspend(ip_block); } return ret == 0 ? count : 0; From f3747ee3a623213788208002ce9d511974367ccc Mon Sep 17 00:00:00 2001 From: Sunil Khatri Date: Thu, 3 Oct 2024 19:16:26 +0530 Subject: [PATCH 1860/1868] drm/amdgpu: Clean up duplicate ip_block object remove the duplicate ip_block object in the isp_hw_init function. Signed-off-by: Sunil Khatri Reviewed-by: Alex Deucher (cherry picked from commit be64d3a4cbc63cc5e38c56392c04ae207c7c153c) --- drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c index 5a919dae8d8eb..478086f166507 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_isp.c @@ -54,12 +54,6 @@ static int isp_hw_init(struct amdgpu_ip_block *ip_block) struct amdgpu_device *adev = ip_block->adev; struct amdgpu_isp *isp = &adev->isp; - const struct amdgpu_ip_block *ip_block = - amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_ISP); - - if (!ip_block) - return -EINVAL; - if (isp->funcs->hw_init != NULL) return isp->funcs->hw_init(isp); From f02e746d18ffdd745f6abb568ab31f7399a4c57b Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Mon, 25 Nov 2024 13:59:09 -0500 Subject: [PATCH 1861/1868] drm/amdgpu: rework resume handling for display (v2) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Split resume into a 3rd step to handle displays when DCC is enabled on DCN 4.0.1. Move display after the buffer funcs have been re-enabled so that the GPU will do the move and properly set the DCC metadata for DCN. v2: fix fence irq resume ordering Reviewed-by: Christian König Signed-off-by: Alex Deucher (cherry picked from commit 32a8dc1b252b9066366a27d3d9ce571278212418) --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 45 +++++++++++++++++++++- 1 file changed, 43 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index be37a46a6c038..4a561d55a4fe6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -3743,7 +3743,7 @@ static int amdgpu_device_ip_resume_phase1(struct amdgpu_device *adev) * * @adev: amdgpu_device pointer * - * First resume function for hardware IPs. The list of all the hardware + * Second resume function for hardware IPs. The list of all the hardware * IPs that make up the asic is walked and the resume callbacks are run for * all blocks except COMMON, GMC, and IH. resume puts the hardware into a * functional state after a suspend and updates the software state as @@ -3761,6 +3761,7 @@ static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev) if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_COMMON || adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_GMC || adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_IH || + adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE || adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_PSP) continue; r = adev->ip_blocks[i].version->funcs->resume(&adev->ip_blocks[i]); @@ -3775,6 +3776,36 @@ static int amdgpu_device_ip_resume_phase2(struct amdgpu_device *adev) return 0; } +/** + * amdgpu_device_ip_resume_phase3 - run resume for hardware IPs + * + * @adev: amdgpu_device pointer + * + * Third resume function for hardware IPs. The list of all the hardware + * IPs that make up the asic is walked and the resume callbacks are run for + * all DCE. resume puts the hardware into a functional state after a suspend + * and updates the software state as necessary. This function is also used + * for restoring the GPU after a GPU reset. + * + * Returns 0 on success, negative error code on failure. + */ +static int amdgpu_device_ip_resume_phase3(struct amdgpu_device *adev) +{ + int i, r; + + for (i = 0; i < adev->num_ip_blocks; i++) { + if (!adev->ip_blocks[i].status.valid || adev->ip_blocks[i].status.hw) + continue; + if (adev->ip_blocks[i].version->type == AMD_IP_BLOCK_TYPE_DCE) { + r = adev->ip_blocks[i].version->funcs->resume(&adev->ip_blocks[i]); + if (r) + return r; + } + } + + return 0; +} + /** * amdgpu_device_ip_resume - run resume for hardware IPs * @@ -3804,6 +3835,13 @@ static int amdgpu_device_ip_resume(struct amdgpu_device *adev) if (adev->mman.buffer_funcs_ring->sched.ready) amdgpu_ttm_set_buffer_funcs_status(adev, true); + if (r) + return r; + + amdgpu_fence_driver_hw_init(adev); + + r = amdgpu_device_ip_resume_phase3(adev); + return r; } @@ -4886,7 +4924,6 @@ int amdgpu_device_resume(struct drm_device *dev, bool fbcon) dev_err(adev->dev, "amdgpu_device_ip_resume failed (%d).\n", r); goto exit; } - amdgpu_fence_driver_hw_init(adev); if (!adev->in_s0ix) { r = amdgpu_amdkfd_resume(adev, adev->in_runpm); @@ -5463,6 +5500,10 @@ int amdgpu_device_reinit_after_reset(struct amdgpu_reset_context *reset_context) if (tmp_adev->mman.buffer_funcs_ring->sched.ready) amdgpu_ttm_set_buffer_funcs_status(tmp_adev, true); + r = amdgpu_device_ip_resume_phase3(tmp_adev); + if (r) + goto out; + if (vram_lost) amdgpu_device_fill_reset_magic(tmp_adev); From 3e4510338ca641019bd4f6eec1ea9788e0b31adc Mon Sep 17 00:00:00 2001 From: Victor Zhao Date: Thu, 24 Oct 2024 13:40:39 +0800 Subject: [PATCH 1862/1868] drm/amdgpu: skip amdgpu_device_cache_pci_state under sriov Under sriov, host driver will save and restore vf pci cfg space during reset. And during device init, under sriov, pci_restore_state happens after fullaccess released, and it can have race condition with mmio protection enable from host side leading to missing interrupts. So skip amdgpu_device_cache_pci_state for sriov. Signed-off-by: Victor Zhao Acked-by: Lijo Lazar --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 4a561d55a4fe6..a5c734877de43 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -6506,6 +6506,9 @@ bool amdgpu_device_cache_pci_state(struct pci_dev *pdev) struct amdgpu_device *adev = drm_to_adev(dev); int r; + if (amdgpu_sriov_vf(adev)) + return false; + r = pci_save_state(pdev); if (!r) { kfree(adev->pci_state); From 3841fa70be048b8f4020d5a1519cb57b31a6521b Mon Sep 17 00:00:00 2001 From: Victor Zhao Date: Thu, 14 Nov 2024 17:45:34 +0800 Subject: [PATCH 1863/1868] drm/amdkfd: make sure ring buffer is flushed before update wptr MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In a consecutive packet submission, for example unmap and query status, when CP is reading wptr caused by unmap packet doorbell ring, if in some case CP operates slower (e.g. doorbell_mode=1) and wptr has been updated to next packet (query status), but the query status packet content has not been flushed to memory yet, it will cause CP fetched stalled data. Adding mb to ensure ring buffer has been updated before updating wptr. Also adding a mb to ensure wptr updated before doorbell ring. Signed-off-by: Victor Zhao Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c index 4843dcb9a5f79..55d18aed257bc 100644 --- a/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c +++ b/drivers/gpu/drm/amd/amdkfd/kfd_kernel_queue.c @@ -306,12 +306,17 @@ int kq_submit_packet(struct kernel_queue *kq) if (amdgpu_amdkfd_is_fed(kq->dev->adev)) return -EIO; + /* Make sure ring buffer is updated before wptr updated */ + mb(); + if (kq->dev->kfd->device_info.doorbell_size == 8) { *kq->wptr64_kernel = kq->pending_wptr64; + mb(); /* Make sure wptr updated before ring doorbell */ write_kernel_doorbell64(kq->queue->properties.doorbell_ptr, kq->pending_wptr64); } else { *kq->wptr_kernel = kq->pending_wptr; + mb(); /* Make sure wptr updated before ring doorbell */ write_kernel_doorbell(kq->queue->properties.doorbell_ptr, kq->pending_wptr); } From 842772464598507db8966609b54b97d0629dada0 Mon Sep 17 00:00:00 2001 From: Shikang Fan Date: Thu, 21 Nov 2024 17:06:30 +0800 Subject: [PATCH 1864/1868] drm/amdgpu: Check fence emitted count to identify bad jobs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In SRIOV, when host driver performs MODE 1 reset and notifies FLR to guest driver, there is a small chance that there is no job running on hw but the driver has not updated the pending list yet, causing the driver not respond the FLR request. Modify the has_job_running function to make sure if there is still running job. v2: Use amdgpu_fence_count_emitted to determine job running status. v3: Remove the timeout wait in has_job_running Signed-off-by: Emily Deng Signed-off-by: Shikang Fan Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index a5c734877de43..d1bb9e85b6d73 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -5225,16 +5225,18 @@ static int amdgpu_device_reset_sriov(struct amdgpu_device *adev, } /** - * amdgpu_device_has_job_running - check if there is any job in mirror list + * amdgpu_device_has_job_running - check if there is any unfinished job * * @adev: amdgpu_device pointer * - * check if there is any job in mirror list + * check if there is any job running on the device when guest driver receives + * FLR notification from host driver. If there are still jobs running, then + * the guest driver will not respond the FLR reset. Instead, let the job hit + * the timeout and guest driver then issue the reset request. */ bool amdgpu_device_has_job_running(struct amdgpu_device *adev) { int i; - struct drm_sched_job *job; for (i = 0; i < AMDGPU_MAX_RINGS; ++i) { struct amdgpu_ring *ring = adev->rings[i]; @@ -5242,11 +5244,7 @@ bool amdgpu_device_has_job_running(struct amdgpu_device *adev) if (!amdgpu_ring_sched_ready(ring)) continue; - spin_lock(&ring->sched.job_list_lock); - job = list_first_entry_or_null(&ring->sched.pending_list, - struct drm_sched_job, list); - spin_unlock(&ring->sched.job_list_lock); - if (job) + if (amdgpu_fence_count_emitted(ring)) return true; } return false; From f73c8084a8bedbc605f98f115edfb3221b197bfc Mon Sep 17 00:00:00 2001 From: Lijo Lazar Date: Tue, 3 Dec 2024 14:41:31 +0530 Subject: [PATCH 1865/1868] drm/amdgpu: Increase FRU File Id buffer size Some boards use longer File Ids. Signed-off-by: Lijo Lazar Reviewed-by: Asad Kamal --- drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.h index bc58dca18035a..98f3196599ef7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.h @@ -32,7 +32,7 @@ struct amdgpu_fru_info { char product_name[AMDGPU_PRODUCT_NAME_LEN]; char serial[20]; char manufacturer_name[32]; - char fru_id[32]; + char fru_id[50]; }; int amdgpu_fru_get_product_info(struct amdgpu_device *adev); From 49cf5a6cfbc364b9902c20143c59302e6317ca6d Mon Sep 17 00:00:00 2001 From: chongli2 Date: Wed, 6 Nov 2024 11:43:09 +0800 Subject: [PATCH 1866/1868] drm/amdgpu: fix return random value when multiple threads read registers via mes. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The currect code use the address "adev->mes.read_val_ptr" to store the value read from register via mes. So when multiple threads read register, multiple threads have to share the one address, and overwrite the value each other. Assign an address by "amdgpu_device_wb_get" to store register value. each thread will has an address to store register value. Signed-off-by: chongli2 Reviewed-by: Emily Deng Reviewed-by: Christian König --- drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c | 30 +++++++++++-------------- drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h | 3 --- 2 files changed, 13 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c index 331d7cb0beb5c..a072cdd316810 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c @@ -192,17 +192,6 @@ int amdgpu_mes_init(struct amdgpu_device *adev) (uint64_t *)&adev->wb.wb[adev->mes.query_status_fence_offs[i]]; } - r = amdgpu_device_wb_get(adev, &adev->mes.read_val_offs); - if (r) { - dev_err(adev->dev, - "(%d) read_val_offs alloc failed\n", r); - goto error; - } - adev->mes.read_val_gpu_addr = - adev->wb.gpu_addr + (adev->mes.read_val_offs * 4); - adev->mes.read_val_ptr = - (uint32_t *)&adev->wb.wb[adev->mes.read_val_offs]; - r = amdgpu_mes_doorbell_init(adev); if (r) goto error; @@ -223,8 +212,6 @@ int amdgpu_mes_init(struct amdgpu_device *adev) amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs[i]); } - if (adev->mes.read_val_ptr) - amdgpu_device_wb_free(adev, adev->mes.read_val_offs); idr_destroy(&adev->mes.pasid_idr); idr_destroy(&adev->mes.gang_id_idr); @@ -249,8 +236,6 @@ void amdgpu_mes_fini(struct amdgpu_device *adev) amdgpu_device_wb_free(adev, adev->mes.query_status_fence_offs[i]); } - if (adev->mes.read_val_ptr) - amdgpu_device_wb_free(adev, adev->mes.read_val_offs); amdgpu_mes_doorbell_free(adev); @@ -921,10 +906,19 @@ uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg) { struct mes_misc_op_input op_input; int r, val = 0; + uint32_t addr_offset = 0; + uint64_t read_val_gpu_addr; + uint32_t *read_val_ptr; + if (amdgpu_device_wb_get(adev, &addr_offset)) { + DRM_ERROR("critical bug! too many mes readers\n"); + goto error; + } + read_val_gpu_addr = adev->wb.gpu_addr + (addr_offset * 4); + read_val_ptr = (uint32_t *)&adev->wb.wb[addr_offset]; op_input.op = MES_MISC_OP_READ_REG; op_input.read_reg.reg_offset = reg; - op_input.read_reg.buffer_addr = adev->mes.read_val_gpu_addr; + op_input.read_reg.buffer_addr = read_val_gpu_addr; if (!adev->mes.funcs->misc_op) { DRM_ERROR("mes rreg is not supported!\n"); @@ -935,9 +929,11 @@ uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg) if (r) DRM_ERROR("failed to read reg (0x%x)\n", reg); else - val = *(adev->mes.read_val_ptr); + val = *(read_val_ptr); error: + if (addr_offset) + amdgpu_device_wb_free(adev, addr_offset); return val; } diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h index 96788c0f42f1b..5edc3fbbbb18f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h @@ -119,9 +119,6 @@ struct amdgpu_mes { uint32_t query_status_fence_offs[AMDGPU_MAX_MES_PIPES]; uint64_t query_status_fence_gpu_addr[AMDGPU_MAX_MES_PIPES]; uint64_t *query_status_fence_ptr[AMDGPU_MAX_MES_PIPES]; - uint32_t read_val_offs; - uint64_t read_val_gpu_addr; - uint32_t *read_val_ptr; uint32_t saved_flags; From c0af1d36ab441c253f5746620a48bbae0865d291 Mon Sep 17 00:00:00 2001 From: Jiang Liu Date: Sun, 29 Dec 2024 10:26:34 +0800 Subject: [PATCH 1867/1868] amdgpu/soc15: enable asic reset for dGPU in case of suspend abort When GPU suspend is aborted, do the same for dGPU as APU to reset soc15 asic. Otherwise it may cause following errors: [ 547.229463] amdgpu 0001:81:00.0: [drm:amdgpu_ring_test_helper [amdgpu]] *ERROR* ring kiq_0.2.1.0 test failed (-110) [ 555.126827] amdgpu 0000:0a:00.0: [drm:amdgpu_ring_test_helper [amdgpu]] *ERROR* ring kiq_0.2.1.0 test failed (-110) [ 555.126901] [drm:amdgpu_gfx_enable_kcq [amdgpu]] *ERROR* KCQ enable failed [ 555.126957] [drm:amdgpu_device_ip_resume_phase2 [amdgpu]] *ERROR* resume of IP block failed -110 [ 555.126959] amdgpu 0000:0a:00.0: amdgpu: amdgpu_device_ip_resume failed (-110). [ 555.126965] PM: dpm_run_callback(): pci_pm_resume+0x0/0xe0 returns -110 [ 555.126966] PM: Device 0000:0a:00.0 failed to resume async: error -110 Signed-off-by: Jiang Liu Tested-by: Shuo Liu --- drivers/gpu/drm/amd/amdgpu/soc15.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index dd1c1aacdd8e1..6fcdeb265a22c 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -583,11 +583,9 @@ static bool soc15_need_reset_on_resume(struct amdgpu_device *adev) sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81); /* Will reset for the following suspend abort cases. - * 1) Only reset limit on APU side, dGPU hasn't checked yet. - * 2) S3 suspend abort and TOS already launched. + * 1) S3 suspend abort and TOS already launched. */ - if (adev->flags & AMD_IS_APU && adev->in_s3 && - sol_reg) { + if (adev->in_s3 && sol_reg) { adev->suspend_complete = false; return true; } else { From 6c345c7784a1c3c09a21e3a0dc43c86024d526f1 Mon Sep 17 00:00:00 2001 From: Jiang Liu Date: Mon, 30 Dec 2024 11:14:17 +0800 Subject: [PATCH 1868/1868] amdgpu/soc21: port commit 9cef84b0a3b to soc21 commit 9cef84b0a3bcc35fed8fb750b5d7b1ae1fe11a9c drm/amdgpu: update suspend status for aborting from deeper suspend There're some other suspend abort cases which can call the noirq suspend except for executing _S3 method. In those cases need to process as incomplete suspendsion. Signed-off-by: Jiang Liu --- drivers/gpu/drm/amd/amdgpu/soc21.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c index c4b950e75133f..03b9bcb8eb6d5 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc21.c +++ b/drivers/gpu/drm/amd/amdgpu/soc21.c @@ -903,13 +903,14 @@ static bool soc21_need_reset_on_resume(struct amdgpu_device *adev) * 1) Only reset dGPU side. * 2) S3 suspend got aborted and TOS is active. */ - if (!(adev->flags & AMD_IS_APU) && adev->in_s3 && - !adev->suspend_complete) { + if (!(adev->flags & AMD_IS_APU) && adev->in_s3) { sol_reg1 = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); msleep(100); sol_reg2 = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81); - - return (sol_reg1 != sol_reg2); + if (sol_reg1 != sol_reg2) { + adev->suspend_complete = false; + return true; + } } return false;