Skip to content

Commit f87404b

Browse files
aggargaggarg
committed
Associate secure context with task handle
The secure side context management code now checks that the secure context being saved or restored belongs to the task being switched-out or switched-in respectively. Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
1 parent 6646679 commit f87404b

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

53 files changed

+1800
-1357
lines changed

‎portable/ARMv8M/non_secure/port.c‎

Lines changed: 10 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -779,7 +779,8 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
779779
uint32_t ulPC;
780780

781781
#if ( configENABLE_TRUSTZONE == 1 )
782-
uint32_t ulR0;
782+
uint32_t ulR0, ulR1;
783+
extern TaskHandle_t pxCurrentTCB;
783784
#if ( configENABLE_MPU == 1 )
784785
uint32_t ulControl, ulIsTaskPrivileged;
785786
#endif /* configENABLE_MPU */
@@ -810,25 +811,27 @@ void vPortSVCHandler_C( uint32_t * pulCallerStackAddress ) /* PRIVILEGED_FUNCTIO
810811
ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
811812

812813
/* Allocate and load a context for the secure task. */
813-
xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
814+
xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged, pxCurrentTCB );
814815
}
815816
#else /* if ( configENABLE_MPU == 1 ) */
816817
{
817818
/* Allocate and load a context for the secure task. */
818-
xSecureContext = SecureContext_AllocateContext( ulR0 );
819+
xSecureContext = SecureContext_AllocateContext( ulR0, pxCurrentTCB );
819820
}
820821
#endif /* configENABLE_MPU */
821822

822-
configASSERT( xSecureContext != NULL );
823-
SecureContext_LoadContext( xSecureContext );
823+
configASSERT( xSecureContext != securecontextINVALID_CONTEXT_ID );
824+
SecureContext_LoadContext( xSecureContext, pxCurrentTCB );
824825
break;
825826

826827
case portSVC_FREE_SECURE_CONTEXT:
827-
/* R0 contains the secure context handle to be freed. */
828+
/* R0 contains TCB being freed and R1 contains the secure
829+
* context handle to be freed. */
828830
ulR0 = pulCallerStackAddress[ 0 ];
831+
ulR1 = pulCallerStackAddress[ 1 ];
829832

830833
/* Free the secure context. */
831-
SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );
834+
SecureContext_FreeContext( ( SecureContextHandle_t ) ulR1, ( void * ) ulR0 );
832835
break;
833836
#endif /* configENABLE_TRUSTZONE */
834837

‎portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portasm.c‎

Lines changed: 196 additions & 190 deletions
Large diffs are not rendered by default.

‎portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c‎

Lines changed: 163 additions & 156 deletions
Large diffs are not rendered by default.

‎portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portasm.s‎

Lines changed: 104 additions & 91 deletions
Large diffs are not rendered by default.

‎portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portasm.s‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -24,6 +24,12 @@
2424
*
2525
* 1 tab == 4 spaces!
2626
*/
27+
/* Including FreeRTOSConfig.h here will cause build errors if the header file
28+
contains code not understood by the assembler - for example the 'extern' keyword.
29+
To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so
30+
the code is included in C files but excluded by the preprocessor in assembly
31+
files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
32+
#include "FreeRTOSConfig.h"
2733

2834
EXTERN pxCurrentTCB
2935
EXTERN vTaskSwitchContext

‎portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portasm.s‎

Lines changed: 86 additions & 79 deletions
Original file line numberDiff line numberDiff line change
@@ -183,62 +183,65 @@ vClearInterruptMask:
183183
/*-----------------------------------------------------------*/
184184

185185
PendSV_Handler:
186-
mrs r1, psp /* Read PSP in r1. */
187-
ldr r2, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
188-
ldr r0, [r2] /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
186+
ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
187+
ldr r0, [r3] /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
188+
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
189+
ldr r1, [r3] /* Read pxCurrentTCB - Value of pxCurrentTCB must be in r1 as it is used as a parameter later. */
190+
mrs r2, psp /* Read PSP in r2. */
189191

190192
cbz r0, save_ns_context /* No secure context to save. */
191193
push {r0-r2, r14}
192-
bl SecureContext_SaveContext
194+
bl SecureContext_SaveContext /* Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
193195
pop {r0-r3} /* LR is now in r3. */
194196
mov lr, r3 /* LR = r3. */
195-
lsls r2, r3, #25 /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
196-
bpl save_ns_context /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
197+
lsls r1, r3, #25 /* r1 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
198+
bpl save_ns_context /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
199+
197200
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
198-
ldr r2, [r3] /* Read pxCurrentTCB. */
201+
ldr r1, [r3] /* Read pxCurrentTCB. */
199202
#if ( configENABLE_MPU == 1 )
200-
subs r1, r1, #16 /* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
201-
str r1, [r2] /* Save the new top of stack in TCB. */
202-
mrs r2, psplim /* r2 = PSPLIM. */
203+
subs r2, r2, #16 /* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
204+
str r2, [r1] /* Save the new top of stack in TCB. */
205+
mrs r1, psplim /* r1 = PSPLIM. */
203206
mrs r3, control /* r3 = CONTROL. */
204207
mov r4, lr /* r4 = LR/EXC_RETURN. */
205-
stmia r1!, {r0, r2-r4} /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
208+
stmia r2!, {r0, r1, r3, r4} /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
206209
#else /* configENABLE_MPU */
207-
subs r1, r1, #12 /* Make space for xSecureContext, PSPLIM and LR on the stack. */
208-
str r1, [r2] /* Save the new top of stack in TCB. */
209-
mrs r2, psplim /* r2 = PSPLIM. */
210+
subs r2, r2, #12 /* Make space for xSecureContext, PSPLIM and LR on the stack. */
211+
str r2, [r1] /* Save the new top of stack in TCB. */
212+
mrs r1, psplim /* r1 = PSPLIM. */
210213
mov r3, lr /* r3 = LR/EXC_RETURN. */
211-
stmia r1!, {r0, r2-r3} /* Store xSecureContext, PSPLIM and LR on the stack. */
214+
stmia r2!, {r0, r1, r3} /* Store xSecureContext, PSPLIM and LR on the stack. */
212215
#endif /* configENABLE_MPU */
213216
b select_next_task
214217

215218
save_ns_context:
216219
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
217-
ldr r2, [r3] /* Read pxCurrentTCB. */
220+
ldr r1, [r3] /* Read pxCurrentTCB. */
218221
#if ( configENABLE_FPU == 1 )
219222
tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
220223
it eq
221-
vstmdbeq r1!, {s16-s31} /* Store the FPU registers which are not saved automatically. */
224+
vstmdbeq r2!, {s16-s31} /* Store the FPU registers which are not saved automatically. */
222225
#endif /* configENABLE_FPU */
223226
#if ( configENABLE_MPU == 1 )
224-
subs r1, r1, #48 /* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
225-
str r1, [r2] /* Save the new top of stack in TCB. */
226-
adds r1, r1, #16 /* r1 = r1 + 16. */
227-
stm r1, {r4-r11} /* Store the registers that are not saved automatically. */
228-
mrs r2, psplim /* r2 = PSPLIM. */
227+
subs r2, r2, #48 /* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
228+
str r2, [r1] /* Save the new top of stack in TCB. */
229+
adds r2, r2, #16 /* r2 = r2 + 16. */
230+
stm r2, {r4-r11} /* Store the registers that are not saved automatically. */
231+
mrs r1, psplim /* r1 = PSPLIM. */
229232
mrs r3, control /* r3 = CONTROL. */
230233
mov r4, lr /* r4 = LR/EXC_RETURN. */
231-
subs r1, r1, #16 /* r1 = r1 - 16. */
232-
stm r1, {r0, r2-r4} /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
234+
subs r2, r2, #16 /* r2 = r2 - 16. */
235+
stmia r2!, {r0, r1, r3, r4} /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
233236
#else /* configENABLE_MPU */
234-
subs r1, r1, #44 /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
235-
str r1, [r2] /* Save the new top of stack in TCB. */
236-
adds r1, r1, #12 /* r1 = r1 + 12. */
237-
stm r1, {r4-r11} /* Store the registers that are not saved automatically. */
238-
mrs r2, psplim /* r2 = PSPLIM. */
237+
subs r2, r2, #44 /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
238+
str r2, [r1] /* Save the new top of stack in TCB. */
239+
adds r2, r2, #12 /* r2 = r2 + 12. */
240+
stm r2, {r4-r11} /* Store the registers that are not saved automatically. */
241+
mrs r1, psplim /* r1 = PSPLIM. */
239242
mov r3, lr /* r3 = LR/EXC_RETURN. */
240-
subs r1, r1, #12 /* r1 = r1 - 12. */
241-
stmia r1!, {r0, r2-r3} /* Store xSecureContext, PSPLIM and LR on the stack. */
243+
subs r2, r2, #12 /* r2 = r2 - 12. */
244+
stmia r2!, {r0, r1, r3} /* Store xSecureContext, PSPLIM and LR on the stack. */
242245
#endif /* configENABLE_MPU */
243246

244247
select_next_task:
@@ -250,77 +253,81 @@ PendSV_Handler:
250253
mov r0, #0 /* r0 = 0. */
251254
msr basepri, r0 /* Enable interrupts. */
252255

253-
ldr r2, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
254-
ldr r3, [r2] /* Read pxCurrentTCB. */
255-
ldr r1, [r3] /* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */
256+
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
257+
ldr r1, [r3] /* Read pxCurrentTCB. */
258+
ldr r2, [r1] /* The first item in pxCurrentTCB is the task top of stack. r2 now points to the top of stack. */
256259

257260
#if ( configENABLE_MPU == 1 )
258261
dmb /* Complete outstanding transfers before disabling MPU. */
259-
ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
260-
ldr r4, [r2] /* Read the value of MPU_CTRL. */
262+
ldr r3, =0xe000ed94 /* r3 = 0xe000ed94 [Location of MPU_CTRL]. */
263+
ldr r4, [r3] /* Read the value of MPU_CTRL. */
261264
bic r4, r4, #1 /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
262-
str r4, [r2] /* Disable MPU. */
265+
str r4, [r3] /* Disable MPU. */
263266

264-
adds r3, #4 /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
265-
ldr r4, [r3] /* r4 = *r3 i.e. r4 = MAIR0. */
266-
ldr r2, =0xe000edc0 /* r2 = 0xe000edc0 [Location of MAIR0]. */
267-
str r4, [r2] /* Program MAIR0. */
268-
ldr r2, =0xe000ed98 /* r2 = 0xe000ed98 [Location of RNR]. */
267+
adds r1, #4 /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
268+
ldr r4, [r1] /* r4 = *r1 i.e. r4 = MAIR0. */
269+
ldr r3, =0xe000edc0 /* r3 = 0xe000edc0 [Location of MAIR0]. */
270+
str r4, [r3] /* Program MAIR0. */
271+
ldr r3, =0xe000ed98 /* r3 = 0xe000ed98 [Location of RNR]. */
269272
movs r4, #4 /* r4 = 4. */
270-
str r4, [r2] /* Program RNR = 4. */
271-
adds r3, #4 /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
272-
ldr r2, =0xe000ed9c /* r2 = 0xe000ed9c [Location of RBAR]. */
273-
ldmia r3!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */
274-
stmia r2!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
275-
276-
ldr r2, =0xe000ed94 /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
277-
ldr r4, [r2] /* Read the value of MPU_CTRL. */
273+
str r4, [r3] /* Program RNR = 4. */
274+
adds r1, #4 /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
275+
ldr r3, =0xe000ed9c /* r3 = 0xe000ed9c [Location of RBAR]. */
276+
ldmia r1!, {r4-r11} /* Read 4 sets of RBAR/RLAR registers from TCB. */
277+
stmia r3!, {r4-r11} /* Write 4 set of RBAR/RLAR registers using alias registers. */
278+
279+
ldr r3, =0xe000ed94 /* r3 = 0xe000ed94 [Location of MPU_CTRL]. */
280+
ldr r4, [r3] /* Read the value of MPU_CTRL. */
278281
orr r4, r4, #1 /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
279-
str r4, [r2] /* Enable MPU. */
282+
str r4, [r3] /* Enable MPU. */
280283
dsb /* Force memory writes before continuing. */
281284
#endif /* configENABLE_MPU */
282285

283286
#if ( configENABLE_MPU == 1 )
284-
ldmia r1!, {r0, r2-r4} /* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */
285-
msr psplim, r2 /* Restore the PSPLIM register value for the task. */
287+
ldmia r2!, {r0, r1, r3, r4} /* Read from stack - r0 = xSecureContext, r1 = PSPLIM, r3 = CONTROL and r4 = LR. */
288+
msr psplim, r1 /* Restore the PSPLIM register value for the task. */
286289
msr control, r3 /* Restore the CONTROL register value for the task. */
287290
mov lr, r4 /* LR = r4. */
288-
ldr r2, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
289-
str r0, [r2] /* Restore the task's xSecureContext. */
291+
ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
292+
str r0, [r3] /* Restore the task's xSecureContext. */
290293
cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */
291-
push {r1,r4}
292-
bl SecureContext_LoadContext /* Restore the secure context. */
293-
pop {r1,r4}
294+
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
295+
ldr r1, [r3] /* Read pxCurrentTCB. */
296+
push {r2, r4}
297+
bl SecureContext_LoadContext /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
298+
pop {r2, r4}
294299
mov lr, r4 /* LR = r4. */
295-
lsls r2, r4, #25 /* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
296-
bpl restore_ns_context /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
297-
msr psp, r1 /* Remember the new top of stack for the task. */
300+
lsls r1, r4, #25 /* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
301+
bpl restore_ns_context /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
302+
msr psp, r2 /* Remember the new top of stack for the task. */
298303
bx lr
299304
#else /* configENABLE_MPU */
300-
ldmia r1!, {r0, r2-r3} /* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */
301-
msr psplim, r2 /* Restore the PSPLIM register value for the task. */
302-
mov lr, r3 /* LR = r3. */
303-
ldr r2, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
304-
str r0, [r2] /* Restore the task's xSecureContext. */
305+
ldmia r2!, {r0, r1, r4} /* Read from stack - r0 = xSecureContext, r1 = PSPLIM and r4 = LR. */
306+
msr psplim, r1 /* Restore the PSPLIM register value for the task. */
307+
mov lr, r4 /* LR = r4. */
308+
ldr r3, =xSecureContext /* Read the location of xSecureContext i.e. &( xSecureContext ). */
309+
str r0, [r3] /* Restore the task's xSecureContext. */
305310
cbz r0, restore_ns_context /* If there is no secure context for the task, restore the non-secure context. */
306-
push {r1,r3}
307-
bl SecureContext_LoadContext /* Restore the secure context. */
308-
pop {r1,r3}
309-
mov lr, r3 /* LR = r3. */
310-
lsls r2, r3, #25 /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
311-
bpl restore_ns_context /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
312-
msr psp, r1 /* Remember the new top of stack for the task. */
311+
ldr r3, =pxCurrentTCB /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
312+
ldr r1, [r3] /* Read pxCurrentTCB. */
313+
push {r2, r4}
314+
bl SecureContext_LoadContext /* Restore the secure context. Params are in r0 and r1. r0 = xSecureContext and r1 = pxCurrentTCB. */
315+
pop {r2, r4}
316+
mov lr, r4 /* LR = r4. */
317+
lsls r1, r4, #25 /* r1 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
318+
bpl restore_ns_context /* bpl - branch if positive or zero. If r1 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
319+
msr psp, r2 /* Remember the new top of stack for the task. */
313320
bx lr
314321
#endif /* configENABLE_MPU */
315322

316323
restore_ns_context:
317-
ldmia r1!, {r4-r11} /* Restore the registers that are not automatically restored. */
324+
ldmia r2!, {r4-r11} /* Restore the registers that are not automatically restored. */
318325
#if ( configENABLE_FPU == 1 )
319326
tst lr, #0x10 /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
320327
it eq
321-
vldmiaeq r1!, {s16-s31} /* Restore the FPU registers which are not restored automatically. */
328+
vldmiaeq r2!, {s16-s31} /* Restore the FPU registers which are not restored automatically. */
322329
#endif /* configENABLE_FPU */
323-
msr psp, r1 /* Remember the new top of stack for the task. */
330+
msr psp, r2 /* Remember the new top of stack for the task. */
324331
bx lr
325332
/*-----------------------------------------------------------*/
326333

@@ -334,9 +341,9 @@ SVC_Handler:
334341

335342
vPortFreeSecureContext:
336343
/* r0 = uint32_t *pulTCB. */
337-
ldr r1, [r0] /* The first item in the TCB is the top of the stack. */
338-
ldr r0, [r1] /* The first item on the stack is the task's xSecureContext. */
339-
cmp r0, #0 /* Raise svc if task's xSecureContext is not NULL. */
344+
ldr r2, [r0] /* The first item in the TCB is the top of the stack. */
345+
ldr r1, [r2] /* The first item on the stack is the task's xSecureContext. */
346+
cmp r1, #0 /* Raise svc if task's xSecureContext is not NULL. */
340347
it ne
341348
svcne 1 /* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 1. */
342349
bx lr /* Return. */

‎portable/ARMv8M/secure/context/portable/GCC/ARM_CM23/secure_context_port.c‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -35,6 +35,9 @@
3535
#error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
3636
#endif
3737

38+
void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) );
39+
void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) );
40+
3841
void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext )
3942
{
4043
/* pxSecureContext value is in r0. */

‎portable/ARMv8M/secure/context/portable/GCC/ARM_CM33/secure_context_port.c‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -31,6 +31,9 @@
3131
/* Secure port macros. */
3232
#include "secure_port_macros.h"
3333

34+
void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) );
35+
void SecureContext_SaveContextAsm( SecureContext_t * pxSecureContext ) __attribute__( ( naked ) );
36+
3437
void SecureContext_LoadContextAsm( SecureContext_t * pxSecureContext )
3538
{
3639
/* pxSecureContext value is in r0. */

‎portable/ARMv8M/secure/context/portable/IAR/ARM_CM23/secure_context_port_asm.s‎

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -28,6 +28,13 @@
2828
SECTION .text:CODE:NOROOT(2)
2929
THUMB
3030

31+
/* Including FreeRTOSConfig.h here will cause build errors if the header file
32+
contains code not understood by the assembler - for example the 'extern' keyword.
33+
To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so
34+
the code is included in C files but excluded by the preprocessor in assembly
35+
files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
36+
#include "FreeRTOSConfig.h"
37+
3138
PUBLIC SecureContext_LoadContextAsm
3239
PUBLIC SecureContext_SaveContextAsm
3340

‎portable/ARMv8M/secure/context/portable/IAR/ARM_CM33/secure_context_port_asm.s‎

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -28,6 +28,13 @@
2828
SECTION .text:CODE:NOROOT(2)
2929
THUMB
3030

31+
/* Including FreeRTOSConfig.h here will cause build errors if the header file
32+
contains code not understood by the assembler - for example the 'extern' keyword.
33+
To avoid errors place any such code inside a #ifdef __ICCARM__/#endif block so
34+
the code is included in C files but excluded by the preprocessor in assembly
35+
files (__ICCARM__ is defined by the IAR C compiler but not by the IAR assembler. */
36+
#include "FreeRTOSConfig.h"
37+
3138
PUBLIC SecureContext_LoadContextAsm
3239
PUBLIC SecureContext_SaveContextAsm
3340
/*-----------------------------------------------------------*/

0 commit comments

Comments
 (0)