--pd-info: Print which ports are enabled

Signed-off-by: Daniel Schaefer <dhs@frame.work>

Author: JohnAZoidberg

EXAMPLES_ADVANCED.md

@@ -5,19 +5,22 @@
 ### Check PD state
 
 Example on Framework 13 AMD Ryzen AI 300
+
 ```
 > sudo framework_tool.exe --pd-info
 Left / Ports 01
   Silicon ID:     0x3580
   Mode:           MainFw
   Flash Row Size: 256 B
+  Ports Enabled:  0, 1
   Bootloader Version:   Base: 3.6.0.009,  App: 0.0.01
   FW1 (Backup) Version: Base: 3.7.0.197,  App: 0.0.0B
   FW2 (Main)   Version: Base: 3.7.0.197,  App: 0.0.0B
 Right / Ports 23
   Silicon ID:     0x3580
   Mode:           MainFw
   Flash Row Size: 256 B
+  Ports Enabled:  0, 1
   Bootloader Version:   Base: 3.6.0.009,  App: 0.0.01
   FW1 (Backup) Version: Base: 3.7.0.197,  App: 0.0.0B
   FW2 (Main)   Version: Base: 3.7.0.197,  App: 0.0.0B

framework_lib/src/ccgx/device.rs

@@ -372,4 +372,10 @@ impl PdController {
         self.ccgx_write(ControlRegisters::PdPortsEnable, &[mask])?;
         Ok(())
     }
+
+    pub fn get_port_status(&self) -> EcResult<u8> {
+        let data = self.ccgx_read(ControlRegisters::PdPortsEnable, 1)?;
+        assert_win_len(data.len(), 1);
+        Ok(data[0])
+    }
 }

framework_lib/src/commandline/mod.rs

@@ -227,6 +227,17 @@ fn print_single_pd_details(pd: &PdController) {
     } else {
         println!("  Failed to device info");
     }
+    if let Ok(port_mask) = pd.get_port_status() {
+        let ports = match port_mask {
+            1 => "0",
+            2 => "1",
+            3 => "0, 1",
+            _ => "None",
+        };
+        println!("  Ports Enabled:  {}", ports);
+    } else {
+        println!("  Ports Enabled:  Unknown");
+    }
     pd.print_fw_info();
 }