diff --git a/clang/tools/driver/cc1_main.cpp b/clang/tools/driver/cc1_main.cpp
index bbf371779341d..9cf186a238438 100644
--- a/clang/tools/driver/cc1_main.cpp
+++ b/clang/tools/driver/cc1_main.cpp
@@ -288,7 +288,7 @@ int cc1_main(ArrayRef<const char *> Argv, const char *Argv0, void *MainAddr) {
     llvm::initializeCodeGen(Registry);
     llvm::initializeLoopStrengthReducePass(Registry);
     llvm::initializeLowerIntrinsicsPass(Registry);
-    llvm::initializeEntryExitInstrumenterPass(Registry);
+    llvm::initializePostInlineEntryExitInstrumenterPass(Registry);
     llvm::initializePostInlineEntryExitInstrumenterPass(Registry);
     llvm::initializeUnreachableBlockElimLegacyPassPass(Registry);
     llvm::initializeConstantHoistingLegacyPassPass(Registry);
@@ -296,7 +296,7 @@ int cc1_main(ArrayRef<const char *> Argv, const char *Argv0, void *MainAddr) {
     llvm::initializeVectorization(Registry);
     llvm::initializeScalarizeMaskedMemIntrinLegacyPassPass(Registry);
     llvm::initializeExpandReductionsPass(Registry);
-    llvm::initializeHardwareLoopsPass(Registry);
+    llvm::initializeHardwareLoopsLegacyPass(Registry);
     llvm::initializeTransformUtils(Registry);
   }
 
diff --git a/llvm/include/llvm/BinaryFormat/ELFRelocs/Z80.def b/llvm/include/llvm/BinaryFormat/ELFRelocs/Z80.def
new file mode 100644
index 0000000000000..627d9f39873af
--- /dev/null
+++ b/llvm/include/llvm/BinaryFormat/ELFRelocs/Z80.def
@@ -0,0 +1,19 @@
+
+#ifndef ELF_RELOC
+#error "ELF_RELOC must be defined"
+#endif
+
+ELF_RELOC(R_Z80_NONE,    0)
+ELF_RELOC(R_Z80_8,       1)
+ELF_RELOC(R_Z80_8_DIS,   2)
+ELF_RELOC(R_Z80_8_PCREL, 3)
+ELF_RELOC(R_Z80_16,      4)
+ELF_RELOC(R_Z80_24,      5)
+ELF_RELOC(R_Z80_32,      6)
+ELF_RELOC(R_Z80_BYTE0,   7)
+ELF_RELOC(R_Z80_BYTE1,   8)
+ELF_RELOC(R_Z80_BYTE2,   9)
+ELF_RELOC(R_Z80_BYTE3,   10)
+ELF_RELOC(R_Z80_WORD0,   11)
+ELF_RELOC(R_Z80_WORD1,   12)
+ELF_RELOC(R_Z80_16_BE,   13)
diff --git a/llvm/include/llvm/BinaryFormat/ELFRelocs/z80.def b/llvm/include/llvm/BinaryFormat/ELFRelocs/z80.def
deleted file mode 100644
index 627d9f39873af..0000000000000
--- a/llvm/include/llvm/BinaryFormat/ELFRelocs/z80.def
+++ /dev/null
@@ -1,19 +0,0 @@
-
-#ifndef ELF_RELOC
-#error "ELF_RELOC must be defined"
-#endif
-
-ELF_RELOC(R_Z80_NONE,    0)
-ELF_RELOC(R_Z80_8,       1)
-ELF_RELOC(R_Z80_8_DIS,   2)
-ELF_RELOC(R_Z80_8_PCREL, 3)
-ELF_RELOC(R_Z80_16,      4)
-ELF_RELOC(R_Z80_24,      5)
-ELF_RELOC(R_Z80_32,      6)
-ELF_RELOC(R_Z80_BYTE0,   7)
-ELF_RELOC(R_Z80_BYTE1,   8)
-ELF_RELOC(R_Z80_BYTE2,   9)
-ELF_RELOC(R_Z80_BYTE3,   10)
-ELF_RELOC(R_Z80_WORD0,   11)
-ELF_RELOC(R_Z80_WORD1,   12)
-ELF_RELOC(R_Z80_16_BE,   13)
diff --git a/llvm/include/llvm/BinaryFormat/ELFRelocs/z80.def b/llvm/include/llvm/BinaryFormat/ELFRelocs/z80.def
new file mode 120000
index 0000000000000..2d718fc70c08c
--- /dev/null
+++ b/llvm/include/llvm/BinaryFormat/ELFRelocs/z80.def
@@ -0,0 +1 @@
+Z80.def
\ No newline at end of file
diff --git a/llvm/include/llvm/CodeGen/AsmPrinter.h b/llvm/include/llvm/CodeGen/AsmPrinter.h
index 20f5403cf6793..f57be39076a78 100644
--- a/llvm/include/llvm/CodeGen/AsmPrinter.h
+++ b/llvm/include/llvm/CodeGen/AsmPrinter.h
@@ -848,8 +848,6 @@ class AsmPrinter : public MachineFunctionPass {
   static Align getGVAlignment(const GlobalObject *GV, const DataLayout &DL,
                               Align InAlign = Align(1));
 
-  virtual void emitGlobalAlias(Module &M, const GlobalAlias &GA);
-
 private:
   /// Private state for PrintSpecial()
   // Assign a unique ID to this machine instruction.
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h b/llvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h
index 04fe5aa1017a0..eb14cbd2149a3 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h
@@ -92,6 +92,54 @@ matchConstant<const IgnoreMatch>(Register Reg, const MachineRegisterInfo &MRI) {
   return std::optional<const IgnoreMatch>{ IgnoreMatch{} };
 }
 
+template <>
+inline std::optional<uint64_t>
+matchConstant<uint64_t>(Register Reg, const MachineRegisterInfo &MRI) {
+  if (auto Val = matchConstant<APInt>(Reg, MRI)) {
+    if (Val->getBitWidth() <= 64)
+      return Val->getZExtValue();
+  }
+  return std::nullopt;
+}
+
+template <>
+inline std::optional<int64_t>
+matchConstant<int64_t>(Register Reg, const MachineRegisterInfo &MRI) {
+  if (auto Val = matchConstant<APInt>(Reg, MRI)) {
+    if (Val->getBitWidth() <= 64)
+      return Val->getSExtValue();
+  }
+  return std::nullopt;
+}
+
+template <>
+inline std::optional<bool>
+matchConstant<bool>(Register Reg, const MachineRegisterInfo &MRI) {
+  if (auto Val = matchConstant<APInt>(Reg, MRI))
+    return Val->getBoolValue();
+  return std::nullopt;
+}
+
+template <>
+inline std::optional<unsigned>
+matchConstant<unsigned>(Register Reg, const MachineRegisterInfo &MRI) {
+  if (auto Val = matchConstant<APInt>(Reg, MRI)) {
+    if (Val->getBitWidth() <= 32)
+      return static_cast<unsigned>(Val->getZExtValue());
+  }
+  return std::nullopt;
+}
+
+template <>
+inline std::optional<unsigned char>
+matchConstant<unsigned char>(Register Reg, const MachineRegisterInfo &MRI) {
+  if (auto Val = matchConstant<APInt>(Reg, MRI)) {
+    if (Val->getBitWidth() <= 8)
+      return static_cast<unsigned char>(Val->getZExtValue());
+  }
+  return std::nullopt;
+}
+
 // template <typename ConstT>
 // inline std::optional<ConstT> matchConstant(Register Reg,
 //                                       const MachineRegisterInfo &MRI) {
diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
index ea1dc0f505a7e..5a68348c7231b 100644
--- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
@@ -6365,14 +6365,14 @@ bool CombinerHelper::matchBuildVectorIdentityFold(MachineInstr &MI,
     return MRI.getType(MatchInfo) == DstVecTy;
   }
 
-  std::optional<ValueAndVReg> ShiftAmount;
+  ValueAndVReg ShiftAmount;
   const auto LoPattern = m_GBitcast(m_Reg(Lo));
   const auto HiPattern = m_GLShr(m_GBitcast(m_Reg(Hi)), m_ICst(ShiftAmount));
   if (mi_match(
           MI, MRI,
           m_any_of(m_GBuildVectorTrunc(LoPattern, HiPattern),
                    m_GBuildVector(m_GTrunc(LoPattern), m_GTrunc(HiPattern))))) {
-    if (Lo == Hi && ShiftAmount->Value == DstEltTy.getSizeInBits()) {
+    if (Lo == Hi && ShiftAmount.Value == DstEltTy.getSizeInBits()) {
       MatchInfo = Lo;
       return MRI.getType(MatchInfo) == DstVecTy;
     }
@@ -6396,14 +6396,14 @@ bool CombinerHelper::matchTruncLshrBuildVectorFold(MachineInstr &MI,
                                                    Register &MatchInfo) {
   // Replace (G_TRUNC (G_LSHR (G_BITCAST (G_BUILD_VECTOR x, y)), K)) with
   //    y if K == size of vector element type
-  std::optional<ValueAndVReg> ShiftAmt;
+  ValueAndVReg ShiftAmt;
   if (!mi_match(MI.getOperand(1).getReg(), MRI,
                 m_GLShr(m_GBitcast(m_GBuildVector(m_Reg(), m_Reg(MatchInfo))),
                         m_ICst(ShiftAmt))))
     return false;
 
   LLT MatchTy = MRI.getType(MatchInfo);
-  return ShiftAmt->Value.getZExtValue() == MatchTy.getSizeInBits() &&
+  return ShiftAmt.Value.getZExtValue() == MatchTy.getSizeInBits() &&
          MatchTy == MRI.getType(MI.getOperand(0).getReg());
 }
 
diff --git a/llvm/lib/CodeGen/GlobalISel/Utils.cpp b/llvm/lib/CodeGen/GlobalISel/Utils.cpp
index e821609bcc812..a10c834133e52 100644
--- a/llvm/lib/CodeGen/GlobalISel/Utils.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/Utils.cpp
@@ -536,7 +536,7 @@ Register llvm::getSrcRegIgnoringCopies(Register Reg,
 /// Returns -1 in the first element of the pair if the breakdown is not
 /// satisfiable.
 std::pair<int, int>
-getNarrowTypeBreakDown(LLT OrigTy, LLT NarrowTy, LLT &LeftoverTy) {
+llvm::getNarrowTypeBreakDown(LLT OrigTy, LLT NarrowTy, LLT &LeftoverTy) {
   unsigned Size = OrigTy.getSizeInBits();
   unsigned NarrowSize = NarrowTy.getSizeInBits();
   unsigned NumParts = Size / NarrowSize;
diff --git a/llvm/lib/Target/Z80/CMakeLists.txt b/llvm/lib/Target/Z80/CMakeLists.txt
index 2e81f7fa71882..1a17d5d029c41 100644
--- a/llvm/lib/Target/Z80/CMakeLists.txt
+++ b/llvm/lib/Target/Z80/CMakeLists.txt
@@ -6,9 +6,9 @@ tablegen(LLVM EZ80GenAsmWriter.inc -gen-asm-writer -asmwriternum=1)
 tablegen(LLVM Z80GenAsmWriter.inc -gen-asm-writer)
 tablegen(LLVM Z80GenCallingConv.inc -gen-callingconv)
 tablegen(LLVM Z80GenPostLegalizeGICombiner.inc -gen-global-isel-combiner
-              -combiners="Z80PostLegalizerCombinerHelper")
+              -combiners="Z80PostLegalizerCombiner")
 tablegen(LLVM Z80GenPreLegalizeGICombiner.inc -gen-global-isel-combiner
-              -combiners="Z80PreLegalizerCombinerHelper")
+              -combiners="Z80PreLegalizerCombiner")
 tablegen(LLVM Z80GenGlobalISel.inc -gen-global-isel)
 tablegen(LLVM Z80GenInstrInfo.inc -gen-instr-info)
 tablegen(LLVM Z80GenRegisterBank.inc -gen-register-bank)
diff --git a/llvm/lib/Target/Z80/GISel/Z80CallLowering.cpp b/llvm/lib/Target/Z80/GISel/Z80CallLowering.cpp
index 7db08361684aa..0421243a20c0b 100644
--- a/llvm/lib/Target/Z80/GISel/Z80CallLowering.cpp
+++ b/llvm/lib/Target/Z80/GISel/Z80CallLowering.cpp
@@ -24,6 +24,7 @@
 #include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
 #include "llvm/Support/Debug.h"
+#include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/Target/TargetMachine.h"
 using namespace llvm;
 using namespace MIPatternMatch;
@@ -59,13 +60,13 @@ struct Z80OutgoingValueHandler : public CallLowering::OutgoingValueHandler {
   }
 
   void assignValueToReg(Register ValVReg, Register PhysReg,
-                        CCValAssign VA) override {
+                        const CCValAssign &VA) override {
     MIB.addReg(PhysReg, RegState::Implicit);
     MIRBuilder.buildCopy(PhysReg, ValVReg);
   }
 
   void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
-                            MachinePointerInfo &MPO, CCValAssign &VA) override {
+                            const MachinePointerInfo &MPO, const CCValAssign &VA) override {
     auto MMO = MIRBuilder.getMF().getMachineMemOperand(
         MPO, MachineMemOperand::MOStore, VA.getLocVT().getStoreSize(),
         Align());
@@ -123,7 +124,7 @@ struct CallArgHandler : public Z80OutgoingValueHandler {
         StackPushes(MIRBuilder.getInsertPt()), RegCopies(StackPushes) {}
 
   void assignValueToReg(Register ValVReg, Register PhysReg,
-                        CCValAssign VA) override {
+                        const CCValAssign &VA) override {
     auto SaveInsertPt = std::prev(MIRBuilder.getInsertPt());
     --StackPushes;
     MIRBuilder.setInsertPt(MIRBuilder.getMBB(), RegCopies);
@@ -140,7 +141,7 @@ struct CallArgHandler : public Z80OutgoingValueHandler {
   }
 
   void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
-                            MachinePointerInfo &MPO, CCValAssign &VA) override {
+                            const MachinePointerInfo &MPO, const CCValAssign &VA) override {
     LLT SlotTy = LLT::scalar(DL.getIndexSizeInBits(0));
     if (VA.getLocVT().getStoreSize() != SlotTy.getSizeInBytes() ||
         !mi_match(Addr, MRI,
@@ -167,7 +168,7 @@ struct CallArgHandler : public Z80OutgoingValueHandler {
   }
 
   bool finalize(CCState &State) override {
-    FrameSize = State.getNextStackOffset();
+    FrameSize = State.getStackSize();
     bool Success = Z80OutgoingValueHandler::finalize(State);
     MIRBuilder.setInsertPt(MIRBuilder.getMBB(), RegCopies);
     return Success;
@@ -215,7 +216,7 @@ struct Z80IncomingValueHandler : public CallLowering::IncomingValueHandler {
   }
 
   void assignValueToAddress(Register ValVReg, Register Addr, LLT MemTy,
-                            MachinePointerInfo &MPO, CCValAssign &VA) override {
+                            const MachinePointerInfo &MPO, const CCValAssign &VA) override {
     auto MMO = MIRBuilder.getMF().getMachineMemOperand(
         MPO, MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant, MemTy,
         Align());
@@ -223,7 +224,7 @@ struct Z80IncomingValueHandler : public CallLowering::IncomingValueHandler {
   }
 
   void assignValueToReg(Register ValVReg, Register PhysReg,
-                        CCValAssign VA) override {
+                        const CCValAssign &VA) override {
     markPhysRegUsed(PhysReg);
     MIRBuilder.buildCopy(ValVReg, PhysReg);
   }
@@ -249,10 +250,10 @@ struct FormalArgHandler : public Z80IncomingValueHandler {
   bool finalize(CCState &State) override {
     MachineFunction &MF = MIRBuilder.getMF();
     auto &FuncInfo = *MF.getInfo<Z80MachineFunctionInfo>();
-    FuncInfo.setArgFrameSize(State.getNextStackOffset());
+    FuncInfo.setArgFrameSize(State.getStackSize());
     if (State.isVarArg()) {
       int FrameIdx = MF.getFrameInfo().CreateFixedObject(
-          1, State.getNextStackOffset(), true);
+          1, State.getStackSize(), true);
       FuncInfo.setVarArgsFrameIndex(FrameIdx);
     }
     return true;
@@ -346,7 +347,7 @@ bool Z80CallLowering::areCalleeOutgoingArgsTailCallable(
 
   // Make sure that they can fit on the caller's stack.
   const auto &FuncInfo = *MF.getInfo<Z80MachineFunctionInfo>();
-  if (OutInfo.getNextStackOffset() > FuncInfo.getArgFrameSize()) {
+  if (OutInfo.getStackSize() > FuncInfo.getArgFrameSize()) {
     LLVM_DEBUG(dbgs() << "... Cannot fit call operands on caller's stack.\n");
     return false;
   }
@@ -761,7 +762,7 @@ bool Z80CallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
   if (!MBB.empty())
     MIRBuilder.setInstr(*MBB.begin());
 
-  OutgoingValueAssigner Assigner(CC_Z80);
+  IncomingValueAssigner Assigner(CC_Z80);
   FormalArgHandler Handler(MIRBuilder, MRI);
   if (!determineAndHandleAssignments(Handler, Assigner, SplitArgs, MIRBuilder,
                                      F.getCallingConv(), F.isVarArg()))
@@ -796,7 +797,7 @@ bool Z80CallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
   Type *RetTy = nullptr;
   if (SRetReturnReg) {
     VRegs = SRetReturnReg;
-    RetTy = Type::getInt8PtrTy(Ctx);
+    RetTy = PointerType::getUnqual(Ctx);
   } else if (!VRegs.empty())
     RetTy = Val->getType();
 
diff --git a/llvm/lib/Target/Z80/GISel/Z80InlineAsmLowering.cpp b/llvm/lib/Target/Z80/GISel/Z80InlineAsmLowering.cpp
index 1ac9adaa4f541..f6ad9eca15a6a 100644
--- a/llvm/lib/Target/Z80/GISel/Z80InlineAsmLowering.cpp
+++ b/llvm/lib/Target/Z80/GISel/Z80InlineAsmLowering.cpp
@@ -33,7 +33,7 @@ bool Z80InlineAsmLowering::lowerInputAsmOperandForConstraint(
     case 'I':
       if (ConstantInt *CI = dyn_cast<ConstantInt>(OpInfo.CallOperandVal)) {
         if (CI->getValue().isIntN(3)) {
-          Inst.addImm(InlineAsm::getFlagWord(InlineAsm::Kind_Imm, 1));
+          Inst.addImm(InlineAsm::Flag(InlineAsm::Kind::Imm, 1));
           Inst.addImm(CI->getZExtValue());
           return true;
         }
@@ -42,7 +42,7 @@ bool Z80InlineAsmLowering::lowerInputAsmOperandForConstraint(
     case 'J':
       if (ConstantInt *CI = dyn_cast<ConstantInt>(OpInfo.CallOperandVal)) {
         if (CI->getValue().isIntN(8)) {
-          Inst.addImm(InlineAsm::getFlagWord(InlineAsm::Kind_Imm, 1));
+          Inst.addImm(InlineAsm::Flag(InlineAsm::Kind::Imm, 1));
           Inst.addImm(CI->getZExtValue());
           return true;
         }
@@ -51,7 +51,7 @@ bool Z80InlineAsmLowering::lowerInputAsmOperandForConstraint(
     case 'M':
       if (ConstantInt *CI = dyn_cast<ConstantInt>(OpInfo.CallOperandVal)) {
         if (CI->getValue().ule(2)) {
-          Inst.addImm(InlineAsm::getFlagWord(InlineAsm::Kind_Imm, 1));
+          Inst.addImm(InlineAsm::Flag(InlineAsm::Kind::Imm, 1));
           Inst.addImm(CI->getZExtValue());
           return true;
         }
@@ -60,7 +60,7 @@ bool Z80InlineAsmLowering::lowerInputAsmOperandForConstraint(
     case 'N':
       if (ConstantInt *CI = dyn_cast<ConstantInt>(OpInfo.CallOperandVal)) {
         if (CI->getValue().isIntN(6) && !(CI->getZExtValue() & 7)) {
-          Inst.addImm(InlineAsm::getFlagWord(InlineAsm::Kind_Imm, 1));
+          Inst.addImm(InlineAsm::Flag(InlineAsm::Kind::Imm, 1));
           Inst.addImm(CI->getZExtValue());
           return true;
         }
@@ -69,7 +69,7 @@ bool Z80InlineAsmLowering::lowerInputAsmOperandForConstraint(
     case 'O':
       if (ConstantInt *CI = dyn_cast<ConstantInt>(OpInfo.CallOperandVal)) {
         if (CI->getValue().isSignedIntN(8)) {
-          Inst.addImm(InlineAsm::getFlagWord(InlineAsm::Kind_Imm, 1));
+          Inst.addImm(InlineAsm::Flag(InlineAsm::Kind::Imm, 1));
           Inst.addImm(CI->getSExtValue());
           return true;
         }
@@ -87,9 +87,9 @@ bool Z80InlineAsmLowering::lowerOutputAsmOperandForConstraint(
   if (OpInfo.ConstraintType == TargetLowering::C_Other) {
     Z80::CondCode CC = Z80::parseConstraintCode(OpInfo.ConstraintCode);
     if (CC != Z80::COND_INVALID) {
-      Inst.addImm(InlineAsm::getFlagWord(
-          OpInfo.isEarlyClobber ? InlineAsm::Kind_RegDefEarlyClobber
-                                : InlineAsm::Kind_RegDef,
+      Inst.addImm(InlineAsm::Flag(
+          OpInfo.isEarlyClobber ? InlineAsm::Kind::RegDefEarlyClobber
+                                : InlineAsm::Kind::RegDef,
           1));
       Inst.addReg(Z80::F,
                   RegState::ImplicitDefine |
diff --git a/llvm/lib/Target/Z80/GISel/Z80InstructionSelector.cpp b/llvm/lib/Target/Z80/GISel/Z80InstructionSelector.cpp
index 328480ab823ef..0fb7dd6d65ee1 100644
--- a/llvm/lib/Target/Z80/GISel/Z80InstructionSelector.cpp
+++ b/llvm/lib/Target/Z80/GISel/Z80InstructionSelector.cpp
@@ -20,9 +20,11 @@
 #include "Z80TargetMachine.h"
 #include "llvm/ADT/Sequence.h"
 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
-#include "llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h"
+#include "llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h"
 #include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
+#include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineJumpTableInfo.h"
+#include "llvm/Support/CodeGenCoverage.h"
 #include "llvm/Support/Debug.h"
 
 using namespace llvm;
@@ -104,6 +106,7 @@ class Z80InstructionSelector : public InstructionSelector {
   bool selectBrJT(MachineInstr &I, MachineRegisterInfo &MRI,
                   MachineFunction &MF) const;
   bool selectImplicitDefOrPHI(MachineInstr &I, MachineRegisterInfo &MRI) const;
+  bool selectAdd(MachineInstr &I, MachineRegisterInfo &MRI) const;
 
   bool selectInlineAsm(MachineInstr &I, MachineRegisterInfo &MRI) const;
 
@@ -320,7 +323,8 @@ bool Z80InstructionSelector::select(MachineInstr &I) const {
   assert(I.getNumOperands() == I.getNumExplicitOperands() &&
          "Generic instruction has unexpected implicit operands");
 
-  if (selectImpl(I, *CoverageInfo))
+  CodeGenCoverage DummyCoverage;
+  if (selectImpl(I, CoverageInfo ? *CoverageInfo : DummyCoverage))
     return true;
 
   LLVM_DEBUG(dbgs() << " C++ instruction selection: "; I.print(dbgs()));
@@ -390,6 +394,8 @@ bool Z80InstructionSelector::select(MachineInstr &I) const {
   case TargetOpcode::G_IMPLICIT_DEF:
   case TargetOpcode::G_PHI:
     return selectImplicitDefOrPHI(I, MRI);
+  case TargetOpcode::G_ADD:
+    return selectAdd(I, MRI);
   default:
     return false;
   }
@@ -509,7 +515,7 @@ bool Z80InstructionSelector::selectSExt(MachineInstr &I,
   if (!constrainSelectedInstRegOperands(*Rotate, TII, TRI, RBI))
     return false;
   auto Fill = MIB.buildInstr(FillOpc);
-  Fill->findRegisterUseOperand(FillReg)->setIsUndef();
+  Fill->findRegisterUseOperand(FillReg, /*TRI=*/nullptr)->setIsUndef();
   if (FillOpc == Z80::SBC8ar)
     Fill.addReg(FillReg, RegState::Undef);
   if (!constrainSelectedInstRegOperands(*Fill, TII, TRI, RBI))
@@ -760,7 +766,7 @@ bool Z80InstructionSelector::selectLoadStore(MachineInstr &I,
             case TargetOpcode::G_FSHL:
               if (ValMI->getOperand(2).getReg() != LoadReg)
                 break;
-              if (ImmConst->isOneValue())
+              if (ImmConst->isOne())
                 RMWOps = {Z80::RLC8p, Z80::RLC8o};
               else if (*ImmConst == 7)
                 RMWOps = {Z80::RRC8p, Z80::RRC8o};
@@ -768,21 +774,21 @@ bool Z80InstructionSelector::selectLoadStore(MachineInstr &I,
             case TargetOpcode::G_FSHR:
               if (ValMI->getOperand(2).getReg() != LoadReg)
                 break;
-              if (ImmConst->isOneValue())
+              if (ImmConst->isOne())
                 RMWOps = {Z80::RLC8p, Z80::RLC8o};
               else if (*ImmConst == 7)
                 RMWOps = {Z80::RRC8p, Z80::RRC8o};
               break;
             case TargetOpcode::G_SHL:
-              if (ImmConst->isOneValue())
+              if (ImmConst->isOne())
                 RMWOps = {Z80::SLA8p, Z80::SLA8o};
               break;
             case TargetOpcode::G_ASHR:
-              if (ImmConst->isOneValue())
+              if (ImmConst->isOne())
                 RMWOps = {Z80::SRA8p, Z80::SRA8o};
               break;
             case TargetOpcode::G_LSHR:
-              if (ImmConst->isOneValue())
+              if (ImmConst->isOne())
                 RMWOps = {Z80::SRL8p, Z80::SRL8o};
               break;
             case TargetOpcode::G_AND: {
@@ -798,9 +804,9 @@ bool Z80InstructionSelector::selectLoadStore(MachineInstr &I,
               break;
             }
             case TargetOpcode::G_ADD:
-              if (ImmConst->isOneValue())
+              if (ImmConst->isOne())
                 RMWOps = {Z80::INC8p, Z80::INC8o};
-              else if (ImmConst->isAllOnesValue())
+              else if (ImmConst->isAllOnes())
                 RMWOps = {Z80::DEC8p, Z80::DEC8o};
               break;
             }
@@ -810,8 +816,8 @@ bool Z80InstructionSelector::selectLoadStore(MachineInstr &I,
     }
   }
 
-  I.RemoveOperand(1);
-  I.RemoveOperand(0);
+  I.removeOperand(1);
+  I.removeOperand(0);
   MachineInstrBuilder MIB(MF, I);
   SmallVector<MachineOperand, 2> MOs;
   int32_t Off = 0;
@@ -901,7 +907,7 @@ bool Z80InstructionSelector::selectLoadStore(MachineInstr &I,
   }
   bool IsOff = MOs.size() == 2;
   if (RMWOps.empty()) {
-    Optional<APInt> ValConst;
+    std::optional<APInt> ValConst;
     switch (Ty.getSizeInBits()) {
     case 8:
       if (!IsLoad)
@@ -976,7 +982,7 @@ bool Z80InstructionSelector::selectLoadStore(MachineInstr &I,
       MachineInstr &LoadMI = *MemMOs[1];
       LoadMI.setDesc(TII.get(TargetOpcode::IMPLICIT_DEF));
       while (LoadMI.getNumOperands() > 1)
-        LoadMI.RemoveOperand(1);
+        LoadMI.removeOperand(1);
       LoadMI.dropMemRefs(MF);
     }
   }
@@ -1012,12 +1018,12 @@ bool Z80InstructionSelector::selectFrameIndexOrGep(MachineInstr &I,
   if (I.getOpcode() == TargetOpcode::G_PTR_ADD) {
     auto OffConst = getIConstantVRegVal(I.getOperand(2).getReg(), MRI);
     if (OffConst && OffConst->sge(-1) && OffConst->sle(1)) {
-      I.RemoveOperand(2);
-      if (OffConst->isNullValue()) {
+      I.removeOperand(2);
+      if (OffConst->isZero()) {
         I.setDesc(TII.get(TargetOpcode::COPY));
         return selectCopy(I, MRI);
       }
-      bool IsInc = OffConst->isOneValue();
+      bool IsInc = OffConst->isOne();
       switch (PtrSize) {
       default: llvm_unreachable("Unexpected pointer size");
       case  8: Opc = IsInc ? Z80::INC8r  : Z80::DEC8r;  break;
@@ -1289,7 +1295,7 @@ bool Z80InstructionSelector::selectMergeValues(MachineInstr &I,
     if (mi_match(UpReg, MRI, m_GAShr(m_Reg(TmpReg), m_SpecificICst(7)))) {
       auto AddI = MIB.buildInstr(Z80::RLC8g, {LLT::scalar(8)}, {TmpReg});
       auto SbcI = MIB.buildInstr(Z80::SBC24aa);
-      SbcI->findRegisterUseOperand(Z80::UHL)->setIsUndef();
+      SbcI->findRegisterUseOperand(Z80::UHL, /*TRI=*/nullptr)->setIsUndef();
       TmpReg = MIB.buildCopy(RC, Register(Z80::UHL)).getReg(0);
       if (!constrainSelectedInstRegOperands(*AddI, TII, TRI, RBI) ||
           !constrainSelectedInstRegOperands(*SbcI, TII, TRI, RBI))
@@ -1451,7 +1457,7 @@ Z80InstructionSelector::foldCompare(MachineInstr &I, MachineIRBuilder &MIB,
             isPowerOf2_32(Mask)) {
           Opc = Z80::BIT8gb;
           Reg = {};
-          Ops = {SrcReg, uint64_t(findFirstSet(Mask))};
+          Ops = {SrcReg, uint64_t(llvm::countr_zero(Mask))};
         } else {
           Opc = Z80::OR8ar;
           Ops = {Reg};
@@ -1524,7 +1530,7 @@ Z80::CondCode Z80InstructionSelector::foldExtendedAddSub(
   Register DstReg = DstMO.getReg();
   Register LHSReg = I.getOperand(2).getReg();
   Register RHSReg = I.getOperand(3).getReg();
-  Optional<ValueAndVReg> RHSConst = None;
+  std::optional<ValueAndVReg> RHSConst = std::nullopt;
   LLT OpTy = MRI.getType(DstReg);
 
   unsigned AddSubOpc;
@@ -1807,7 +1813,7 @@ bool Z80InstructionSelector::selectShift(MachineInstr &I,
     auto AddI = MIB.buildInstr(AddOpc, {Ty}, {SrcReg});
     auto SbcI = MIB.buildInstr(SbcOpc);
     if (Ty == LLT::scalar(8)) {
-      SbcI->findRegisterUseOperand(Reg)->setIsUndef();
+      SbcI->findRegisterUseOperand(Reg, /*TRI=*/nullptr)->setIsUndef();
       SbcI.addReg(Reg, RegState::Undef);
     }
     MIB.buildCopy(DstReg, Reg);
@@ -1930,13 +1936,13 @@ bool Z80InstructionSelector::selectSetCond(unsigned ExtOpc, Register DstReg,
     Register UndefReg = Z80::NoRegister;
     if (FillOpc == Z80::SBC8ar) {
       auto CopyUndefI = MIB.buildCopy(DstTy, FillReg);
-      CopyUndefI->findRegisterUseOperand(FillReg)->setIsUndef();
+      CopyUndefI->findRegisterUseOperand(FillReg, /*TRI=*/nullptr)->setIsUndef();
       UndefReg = CopyUndefI.getReg(0);
       if (!RBI.constrainGenericRegister(UndefReg, *DstRC, MRI))
         return false;
     }
     auto FillI = MIB.buildInstr(FillOpc);
-    FillI->findRegisterUseOperand(FillReg)->setIsUndef();
+    FillI->findRegisterUseOperand(FillReg, /*TRI=*/nullptr)->setIsUndef();
     if (UndefReg)
       FillI.addReg(UndefReg, RegState::Undef);
     if (!constrainSelectedInstRegOperands(*FillI, TII, TRI, RBI))
@@ -2058,6 +2064,46 @@ bool Z80InstructionSelector::selectImplicitDefOrPHI(
   return RBI.constrainGenericRegister(DstReg, *getRegClass(DstReg, MRI), MRI);
 }
 
+bool Z80InstructionSelector::selectAdd(MachineInstr &I,
+                                       MachineRegisterInfo &MRI) const {
+  assert(I.getOpcode() == TargetOpcode::G_ADD && "unexpected instruction");
+
+  Register DstReg = I.getOperand(0).getReg();
+  Register Src0Reg = I.getOperand(1).getReg();
+  Register Src1Reg = I.getOperand(2).getReg();
+
+  LLT Ty = MRI.getType(DstReg);
+  unsigned Size = Ty.getSizeInBits();
+
+  // Check if Src1Reg is a constant 1 or -1
+  MachineInstr *Src1Def = MRI.getVRegDef(Src1Reg);
+  if (Src1Def && Src1Def->getOpcode() == TargetOpcode::G_CONSTANT) {
+    auto Val = Src1Def->getOperand(1).getCImm()->getSExtValue();
+    unsigned IncOpc = 0, DecOpc = 0;
+
+    if (Size == 16) {
+      IncOpc = Z80::INC16r;
+      DecOpc = Z80::DEC16r;
+    } else if (Size == 24) {
+      IncOpc = Z80::INC24r;
+      DecOpc = Z80::DEC24r;
+    }
+
+    if (IncOpc && (Val == 1 || Val == -1)) {
+      unsigned Opc = (Val == 1) ? IncOpc : DecOpc;
+      MachineIRBuilder MIB(I);
+      auto NewI = MIB.buildInstr(Opc, {DstReg}, {Src0Reg});
+      if (!constrainSelectedInstRegOperands(*NewI, TII, TRI, RBI))
+        return false;
+      I.eraseFromParent();
+      return true;
+    }
+  }
+
+  // Fall back to generic selection failure - let other patterns handle it
+  return false;
+}
+
 bool Z80InstructionSelector::selectInlineAsm(MachineInstr &I,
                                              MachineRegisterInfo &MRI) const {
   for (unsigned Idx :
diff --git a/llvm/lib/Target/Z80/GISel/Z80LegalizerInfo.cpp b/llvm/lib/Target/Z80/GISel/Z80LegalizerInfo.cpp
index c388cdf179830..fc261cbda68b7 100644
--- a/llvm/lib/Target/Z80/GISel/Z80LegalizerInfo.cpp
+++ b/llvm/lib/Target/Z80/GISel/Z80LegalizerInfo.cpp
@@ -19,6 +19,7 @@
 #include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
 #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
+#include "llvm/CodeGen/GlobalISel/GenericMachineInstrs.h"
 #include <functional>
 #include <initializer_list>
 using namespace llvm;
@@ -260,13 +261,8 @@ Z80LegalizerInfo::Z80LegalizerInfo(const Z80Subtarget &STI,
       .legalForCartesianProduct(LegalTypes, {p[0]})
       .legalForCartesianProduct(LegalTypesOther, {p[1]})
       .legalForCartesianProduct({s8}, {p[2], p[3], p[4]})
-      .minScalar(0, s8)
-      .maxScalarIf(IsSpecificType(1, p[0]), 0, sMax)
-      .maxScalarIf(IsSpecificType(1, p[1]), 0, sOther)
-      .maxScalar(0, s8);
-  for (unsigned MemOp : {G_LOAD, G_STORE})
-    getLegacyLegalizerInfo().setLegalizeScalarToDifferentSizeStrategy(
-        MemOp, 0, LegacyLegalizerInfo::narrowToSmallerAndWidenToSmallest);
+      .widenScalarToNextPow2(0, /*Min=*/8)
+      .clampScalar(0, s8, sMax);
 
   getActionDefinitionsBuilder(
       {G_FRAME_INDEX, G_GLOBAL_VALUE, G_BRINDIRECT, G_JUMP_TABLE})
@@ -320,67 +316,76 @@ Z80LegalizerInfo::Z80LegalizerInfo(const Z80Subtarget &STI,
       .libcallFor(LegalLibcallScalars)
       .clampScalar(0, s8, s64);
 
-  getLegacyLegalizerInfo().computeTables();
+
   verify(*STI.getInstrInfo());
 }
 
-LegalizerHelper::LegalizeResult Z80LegalizerInfo::legalizeCustomMaybeLegal(
+bool Z80LegalizerInfo::legalizeCustomMaybeLegal(
     LegalizerHelper &Helper, MachineInstr &MI,
     LostDebugLocObserver &LocObserver) const {
   Helper.MIRBuilder.setInstrAndDebugLoc(MI);
   switch (MI.getOpcode()) {
   default:
     // No idea what to do.
-    return LegalizerHelper::UnableToLegalize;
+    return false;
   case G_ADD:
   case G_SUB:
-    return legalizeAddSub(Helper, MI, LocObserver);
+    return legalizeAddSub(Helper, MI, LocObserver) !=
+           LegalizerHelper::UnableToLegalize;
   case G_AND:
   case G_OR:
   case G_XOR:
   case G_PTRMASK:
-    return legalizeBitwise(Helper, MI, LocObserver);
+    return legalizeBitwise(Helper, MI, LocObserver) !=
+           LegalizerHelper::UnableToLegalize;
   case G_EXTRACT:
   case G_INSERT:
-    return legalizeExtractInsert(Helper, MI);
+    return legalizeExtractInsert(Helper, MI) !=
+           LegalizerHelper::UnableToLegalize;
   case G_FCONSTANT:
-    return legalizeFConstant(Helper, MI);
+    return legalizeFConstant(Helper, MI) != LegalizerHelper::UnableToLegalize;
   case G_VASTART:
-    return legalizeVAStart(Helper, MI);
+    return legalizeVAStart(Helper, MI) != LegalizerHelper::UnableToLegalize;
   case G_SHL:
   case G_LSHR:
   case G_ASHR:
-    return legalizeShift(Helper, MI, LocObserver);
+    return legalizeShift(Helper, MI, LocObserver) !=
+           LegalizerHelper::UnableToLegalize;
   case G_FSHL:
   case G_FSHR:
   case G_ROTR:
   case G_ROTL:
-    return legalizeFunnelShift(Helper, MI);
+    return legalizeFunnelShift(Helper, MI) != LegalizerHelper::UnableToLegalize;
   case G_ICMP:
   case G_FCMP:
-    return legalizeCompare(Helper, MI);
+    return legalizeCompare(Helper, MI, LocObserver) != LegalizerHelper::UnableToLegalize;
   case G_UMULO:
-    return legalizeMultiplyWithOverflow(Helper, MI);
+    return legalizeMultiplyWithOverflow(Helper, MI) !=
+           LegalizerHelper::UnableToLegalize;
   case G_SMULFIX:
   case G_UMULFIX:
   case G_SMULFIXSAT:
   case G_UMULFIXSAT:
-    return legalizeFixedMultiply(Helper, MI);
+    return legalizeFixedMultiply(Helper, MI) !=
+           LegalizerHelper::UnableToLegalize;
   case G_SDIVFIX:
   case G_UDIVFIX:
   case G_SDIVFIXSAT:
   case G_UDIVFIXSAT:
-    return legalizeFixedDivide(Helper, MI);
+    return legalizeFixedDivide(Helper, MI) != LegalizerHelper::UnableToLegalize;
   case G_FCANONICALIZE:
-    return legalizeFCanonicalize(Helper, MI);
+    return legalizeFCanonicalize(Helper, MI) !=
+           LegalizerHelper::UnableToLegalize;
   case G_CTLZ:
-    return legalizeCtlz(Helper, MI);
+    return legalizeCtlz(Helper, MI, LocObserver) !=
+           LegalizerHelper::UnableToLegalize;
   case G_MEMCPY:
   case G_MEMCPY_INLINE:
   case G_MEMMOVE:
   case G_MEMSET:
   case G_BZERO:
-    return legalizeMemIntrinsic(Helper, MI, LocObserver);
+    return legalizeMemIntrinsic(Helper, MI, LocObserver) !=
+           LegalizerHelper::UnableToLegalize;
   }
 }
 
@@ -422,7 +427,7 @@ Z80LegalizerInfo::legalizeAddSub(LegalizerHelper &Helper, MachineInstr &MI,
     }
     Type *Ty = IntegerType::get(Ctx, Size);
     auto Result = createLibcall(Helper.MIRBuilder, Libcall, {DstReg, Ty, 0},
-                                {{LHSReg, Ty, 0}});
+                                {{LHSReg, Ty, 0}}, LocObserver);
     MI.eraseFromParent();
     return Result;
   }
@@ -469,7 +474,7 @@ Z80LegalizerInfo::legalizeBitwise(LegalizerHelper &Helper, MachineInstr &MI,
     }
     Type *Ty = IntegerType::get(Ctx, Size);
     auto Result = createLibcall(Helper.MIRBuilder, Libcall, {DstReg, Ty, 0},
-                                {{LHSReg, Ty, 0}});
+                                {{LHSReg, Ty, 0}}, LocObserver);
     MI.eraseFromParent();
     return Result;
   }
@@ -487,7 +492,7 @@ Z80LegalizerInfo::legalizeBitwise(LegalizerHelper &Helper, MachineInstr &MI,
     Type *Ty = IntegerType::get(Ctx, Size);
     auto Result = createLibcall(Helper.MIRBuilder, Libcall, {DstReg, Ty, 0},
                                 {{MI.getOperand(1).getReg(), Ty, 0},
-                                 {MI.getOperand(2).getReg(), Ty, 1}});
+                                 {MI.getOperand(2).getReg(), Ty, 1}}, LocObserver);
     MI.eraseFromParent();
     return Result;
   }
@@ -598,8 +603,8 @@ Z80LegalizerInfo::legalizeFunnelShift(LegalizerHelper &Helper,
 }
 
 LegalizerHelper::LegalizeResult
-Z80LegalizerInfo::legalizeCompare(LegalizerHelper &Helper,
-                                  MachineInstr &MI) const {
+Z80LegalizerInfo::legalizeCompare(LegalizerHelper &Helper, MachineInstr &MI,
+                                  LostDebugLocObserver &LocObserver) const {
   MachineIRBuilder &MIRBuilder = Helper.MIRBuilder;
   MachineRegisterInfo &MRI = *MIRBuilder.getMRI();
   Register DstReg = MI.getOperand(0).getReg();
@@ -667,7 +672,7 @@ Z80LegalizerInfo::legalizeCompare(LegalizerHelper &Helper,
                                    CallLowering::ArgInfo::NoArgIndex);
     CallLowering::ArgInfo Args[2] = {{LHSReg, Ty, 0}, {RHSReg, Ty, 1}};
     auto Result = createLibcall(MIRBuilder, Libcall, FlagsArg,
-                                makeArrayRef(Args, 2 - ZeroRHS));
+                                ArrayRef(Args, 2 - ZeroRHS), LocObserver);
     if (Result != LegalizerHelper::Legalized)
       return Result;
     MIRBuilder.buildCopy(Register(Z80::F), FlagsReg);
@@ -892,8 +897,8 @@ Z80LegalizerInfo::legalizeFCanonicalize(LegalizerHelper &Helper,
 }
 
 LegalizerHelper::LegalizeResult
-Z80LegalizerInfo::legalizeCtlz(LegalizerHelper &Helper,
-                               MachineInstr &MI) const {
+Z80LegalizerInfo::legalizeCtlz(LegalizerHelper &Helper, MachineInstr &MI,
+                               LostDebugLocObserver &LocObserver) const {
   assert(MI.getOpcode() == G_CTLZ);
   MachineIRBuilder &MIRBuilder = Helper.MIRBuilder;
   MachineRegisterInfo &MRI = *MIRBuilder.getMRI();
@@ -921,7 +926,7 @@ Z80LegalizerInfo::legalizeCtlz(LegalizerHelper &Helper,
   }
   auto Result = createLibcall(MIRBuilder, Libcall,
                               {DstReg, IntegerType::get(Ctx, DstSize), 0},
-                              {{SrcReg, IntegerType::get(Ctx, SrcSize), 0}});
+                              {{SrcReg, IntegerType::get(Ctx, SrcSize), 0}}, LocObserver);
   MI.eraseFromParent();
   return Result;
 }
@@ -1081,12 +1086,12 @@ bool Z80LegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
   auto &Ctx = MF.getFunction().getContext();
   auto &CLI = *MF.getSubtarget().getCallLowering();
 
-  switch (MI.getIntrinsicID()) {
+  switch (cast<GIntrinsic>(MI).getIntrinsicID()) {
   case Intrinsic::trap: {
     CallLowering::CallLoweringInfo Info;
     Info.CallConv = CallingConv::C;
     Info.Callee = MachineOperand::CreateES("abort");
-    Info.OrigRet = CallLowering::ArgInfo{None, Type::getVoidTy(Ctx), 0};
+    Info.OrigRet = CallLowering::ArgInfo{{}, Type::getVoidTy(Ctx), 0};
     if (!CLI.lowerCall(MIRBuilder, Info))
       return false;
     break;
diff --git a/llvm/lib/Target/Z80/GISel/Z80LegalizerInfo.h b/llvm/lib/Target/Z80/GISel/Z80LegalizerInfo.h
index 5fcc66f0b6af4..4505d893a55b6 100644
--- a/llvm/lib/Target/Z80/GISel/Z80LegalizerInfo.h
+++ b/llvm/lib/Target/Z80/GISel/Z80LegalizerInfo.h
@@ -13,6 +13,7 @@
 #ifndef LLVM_LIB_TARGET_Z80_Z80MACHINELEGALIZER_H
 #define LLVM_LIB_TARGET_Z80_Z80MACHINELEGALIZER_H
 
+#include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
 
 namespace llvm {
@@ -32,9 +33,8 @@ class Z80LegalizerInfo : public LegalizerInfo {
 public:
   Z80LegalizerInfo(const Z80Subtarget &STI, const Z80TargetMachine &TM);
 
-  LegalizerHelper::LegalizeResult
-  legalizeCustomMaybeLegal(LegalizerHelper &Helper, MachineInstr &MI,
-                           LostDebugLocObserver &LocObserver) const override;
+  bool legalizeCustomMaybeLegal(LegalizerHelper &Helper, MachineInstr &MI,
+                                LostDebugLocObserver &LocObserver) const override;
 
   bool legalizeIntrinsic(LegalizerHelper &Helper,
                          MachineInstr &MI) const override;
@@ -58,7 +58,8 @@ class Z80LegalizerInfo : public LegalizerInfo {
   LegalizerHelper::LegalizeResult legalizeFunnelShift(LegalizerHelper &Helper,
                                                       MachineInstr &MI) const;
   LegalizerHelper::LegalizeResult legalizeCompare(LegalizerHelper &Helper,
-                                                  MachineInstr &MI) const;
+                                                  MachineInstr &MI,
+                                                  LostDebugLocObserver &LocObserver) const;
   LegalizerHelper::LegalizeResult legalizeFixedMultiply(LegalizerHelper &Helper,
                                                         MachineInstr &MI) const;
   LegalizerHelper::LegalizeResult legalizeFixedDivide(LegalizerHelper &Helper,
@@ -68,7 +69,8 @@ class Z80LegalizerInfo : public LegalizerInfo {
   LegalizerHelper::LegalizeResult legalizeFCanonicalize(LegalizerHelper &Helper,
                                                         MachineInstr &MI) const;
   LegalizerHelper::LegalizeResult legalizeCtlz(LegalizerHelper &Helper,
-                                               MachineInstr &MI) const;
+                                               MachineInstr &MI,
+                                               LostDebugLocObserver &LocObserver) const;
   LegalizerHelper::LegalizeResult
   legalizeMemIntrinsic(LegalizerHelper &Helper, MachineInstr &MI,
                        LostDebugLocObserver &LocObserver) const;
diff --git a/llvm/lib/Target/Z80/GISel/Z80PostLegalizerCombiner.cpp b/llvm/lib/Target/Z80/GISel/Z80PostLegalizerCombiner.cpp
index 3abfa9fd9ffde..d0d2ca4cdae95 100644
--- a/llvm/lib/Target/Z80/GISel/Z80PostLegalizerCombiner.cpp
+++ b/llvm/lib/Target/Z80/GISel/Z80PostLegalizerCombiner.cpp
@@ -12,78 +12,94 @@
 //===----------------------------------------------------------------------===//
 
 #include "Z80.h"
+#include "Z80Subtarget.h"
+#include "llvm/CodeGen/GlobalISel/CSEInfo.h"
 #include "llvm/CodeGen/GlobalISel/Combiner.h"
 #include "llvm/CodeGen/GlobalISel/CombinerHelper.h"
 #include "llvm/CodeGen/GlobalISel/CombinerInfo.h"
+#include "llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h"
 #include "llvm/CodeGen/GlobalISel/GISelKnownBits.h"
+#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
 #include "llvm/CodeGen/MachineDominators.h"
+#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/TargetPassConfig.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Target/TargetMachine.h"
 
+#define GET_GICOMBINER_DEPS
+#include "Z80GenPostLegalizeGICombiner.inc"
+#undef GET_GICOMBINER_DEPS
+
 #define DEBUG_TYPE "z80-postlegalizer-combiner"
 
 using namespace llvm;
 
-#define Z80POSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_DEPS
-#include "Z80GenPostLegalizeGICombiner.inc"
-#undef Z80POSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_DEPS
-
 namespace {
-#define Z80POSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_H
+
+#define GET_GICOMBINER_TYPES
 #include "Z80GenPostLegalizeGICombiner.inc"
-#undef Z80POSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_H
+#undef GET_GICOMBINER_TYPES
 
-class Z80PostLegalizerCombinerInfo : public CombinerInfo {
-  GISelKnownBits *KB;
-  MachineDominatorTree *MDT;
-  Z80GenPostLegalizerCombinerHelperRuleConfig GeneratedRuleCfg;
+class Z80PostLegalizerCombinerImpl : public Combiner {
+protected:
+  mutable CombinerHelper Helper;
+  const Z80PostLegalizerCombinerImplRuleConfig &RuleConfig;
+  const Z80Subtarget &STI;
 
 public:
-  Z80PostLegalizerCombinerInfo(bool EnableOpt, bool OptSize, bool MinSize,
-                               GISelKnownBits *KB, MachineDominatorTree *MDT)
-      : CombinerInfo(/*AllowIllegalOps*/ true, /*ShouldLegalizeIllegal*/ false,
-                     /*LegalizerInfo*/ nullptr, EnableOpt, OptSize, MinSize),
-        KB(KB), MDT(MDT) {
-    if (!GeneratedRuleCfg.parseCommandLineOption())
-      report_fatal_error("Invalid rule identifier");
-  }
+  Z80PostLegalizerCombinerImpl(
+      MachineFunction &MF, CombinerInfo &CInfo, const TargetPassConfig *TPC,
+      GISelKnownBits &KB, GISelCSEInfo *CSEInfo,
+      const Z80PostLegalizerCombinerImplRuleConfig &RuleConfig,
+      const Z80Subtarget &STI, MachineDominatorTree *MDT,
+      const LegalizerInfo *LI);
 
-  virtual bool combine(GISelChangeObserver &Observer, MachineInstr &MI,
-                       MachineIRBuilder &B) const override;
-};
+  static const char *getName() { return "Z80PostLegalizerCombiner"; }
 
-bool Z80PostLegalizerCombinerInfo::combine(GISelChangeObserver &Observer,
-                                           MachineInstr &MI,
-                                           MachineIRBuilder &B) const {
-  CombinerHelper Helper(Observer, B, KB, MDT,
-                        MI.getMF()->getSubtarget().getLegalizerInfo());
-  Z80GenPostLegalizerCombinerHelper Generated(GeneratedRuleCfg, Helper);
-  return Generated.tryCombineAll(Observer, MI, B, Helper);
-}
+  bool tryCombineAll(MachineInstr &I) const override;
 
-#define Z80POSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_CPP
+private:
+#define GET_GICOMBINER_CLASS_MEMBERS
 #include "Z80GenPostLegalizeGICombiner.inc"
-#undef Z80POSTLEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_CPP
+#undef GET_GICOMBINER_CLASS_MEMBERS
+};
 
-// Pass boilerplate
-// ================
+#define GET_GICOMBINER_IMPL
+#include "Z80GenPostLegalizeGICombiner.inc"
+#undef GET_GICOMBINER_IMPL
+
+Z80PostLegalizerCombinerImpl::Z80PostLegalizerCombinerImpl(
+    MachineFunction &MF, CombinerInfo &CInfo, const TargetPassConfig *TPC,
+    GISelKnownBits &KB, GISelCSEInfo *CSEInfo,
+    const Z80PostLegalizerCombinerImplRuleConfig &RuleConfig,
+    const Z80Subtarget &STI, MachineDominatorTree *MDT,
+    const LegalizerInfo *LI)
+    : Combiner(MF, CInfo, TPC, &KB, CSEInfo),
+      Helper(Observer, B, /*IsPreLegalize*/ false, &KB, MDT, LI),
+      RuleConfig(RuleConfig), STI(STI),
+#define GET_GICOMBINER_CONSTRUCTOR_INITS
+#include "Z80GenPostLegalizeGICombiner.inc"
+#undef GET_GICOMBINER_CONSTRUCTOR_INITS
+{
+}
 
 class Z80PostLegalizerCombiner : public MachineFunctionPass {
 public:
   static char ID;
 
-  Z80PostLegalizerCombiner(bool IsOptNone = false);
+  Z80PostLegalizerCombiner();
 
   StringRef getPassName() const override {
     return "Z80 Post-Legalizer Combiner";
   }
 
   bool runOnMachineFunction(MachineFunction &MF) override;
-
   void getAnalysisUsage(AnalysisUsage &AU) const override;
+
 private:
-  bool IsOptNone;
+  Z80PostLegalizerCombinerImplRuleConfig RuleConfig;
 };
 } // end anonymous namespace
 
@@ -93,45 +109,61 @@ void Z80PostLegalizerCombiner::getAnalysisUsage(AnalysisUsage &AU) const {
   getSelectionDAGFallbackAnalysisUsage(AU);
   AU.addRequired<GISelKnownBitsAnalysis>();
   AU.addPreserved<GISelKnownBitsAnalysis>();
-  if (!IsOptNone) {
-    AU.addRequired<MachineDominatorTree>();
-    AU.addPreserved<MachineDominatorTree>();
-  }
+  AU.addRequired<MachineDominatorTreeWrapperPass>();
+  AU.addPreserved<MachineDominatorTreeWrapperPass>();
+  AU.addRequired<GISelCSEAnalysisWrapperPass>();
+  AU.addPreserved<GISelCSEAnalysisWrapperPass>();
   MachineFunctionPass::getAnalysisUsage(AU);
 }
 
-Z80PostLegalizerCombiner::Z80PostLegalizerCombiner(bool IsOptNone)
-    : MachineFunctionPass(ID), IsOptNone(IsOptNone) {
+Z80PostLegalizerCombiner::Z80PostLegalizerCombiner()
+    : MachineFunctionPass(ID) {
   initializeZ80PostLegalizerCombinerPass(*PassRegistry::getPassRegistry());
+
+  if (!RuleConfig.parseCommandLineOption())
+    report_fatal_error("Invalid rule identifier");
 }
 
 bool Z80PostLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
   if (MF.getProperties().hasProperty(
           MachineFunctionProperties::Property::FailedISel))
     return false;
+  assert(MF.getProperties().hasProperty(
+             MachineFunctionProperties::Property::Legalized) &&
+         "Expected a legalized function?");
   auto *TPC = &getAnalysis<TargetPassConfig>();
   const Function &F = MF.getFunction();
   bool EnableOpt =
-      MF.getTarget().getOptLevel() != CodeGenOpt::None && !skipFunction(F);
+      MF.getTarget().getOptLevel() != CodeGenOptLevel::None && !skipFunction(F);
+
+  const Z80Subtarget &ST = MF.getSubtarget<Z80Subtarget>();
+  const auto *LI = ST.getLegalizerInfo();
+
   GISelKnownBits *KB = &getAnalysis<GISelKnownBitsAnalysis>().get(MF);
   MachineDominatorTree *MDT =
-      IsOptNone ? nullptr : &getAnalysis<MachineDominatorTree>();
-  Z80PostLegalizerCombinerInfo PCInfo(EnableOpt, F.hasOptSize(), F.hasMinSize(),
-                                      KB, MDT);
-  Combiner C(PCInfo, TPC);
-  return C.combineMachineInstrs(MF, /*CSEInfo*/ nullptr);
+      &getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
+  GISelCSEAnalysisWrapper &Wrapper =
+      getAnalysis<GISelCSEAnalysisWrapperPass>().getCSEWrapper();
+  auto *CSEInfo = &Wrapper.get(TPC->getCSEConfig());
+
+  CombinerInfo CInfo(/*AllowIllegalOps*/ true, /*ShouldLegalizeIllegal*/ false,
+                     /*LegalizerInfo*/ nullptr, EnableOpt, F.hasOptSize(),
+                     F.hasMinSize());
+  Z80PostLegalizerCombinerImpl Impl(MF, CInfo, TPC, *KB, CSEInfo,
+                                    RuleConfig, ST, MDT, LI);
+  return Impl.combineMachineInstrs();
 }
 
 char Z80PostLegalizerCombiner::ID = 0;
 INITIALIZE_PASS_BEGIN(Z80PostLegalizerCombiner, DEBUG_TYPE,
-                      "Combine Z80 machine instrs after legalization", false,
+                      "Combine Z80 MachineInstrs after legalization", false,
                       false)
 INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
 INITIALIZE_PASS_DEPENDENCY(GISelKnownBitsAnalysis)
 INITIALIZE_PASS_END(Z80PostLegalizerCombiner, DEBUG_TYPE,
-                    "Combine Z80 machine instrs after legalization", false,
+                    "Combine Z80 MachineInstrs after legalization", false,
                     false)
 
-FunctionPass *llvm::createZ80PostLegalizeCombiner(bool IsOptNone) {
-  return new Z80PostLegalizerCombiner(IsOptNone);
+FunctionPass *llvm::createZ80PostLegalizeCombiner() {
+  return new Z80PostLegalizerCombiner();
 }
diff --git a/llvm/lib/Target/Z80/GISel/Z80PreLegalizerCombiner.cpp b/llvm/lib/Target/Z80/GISel/Z80PreLegalizerCombiner.cpp
index 19788a80c3d47..de7e7acb4d6f4 100644
--- a/llvm/lib/Target/Z80/GISel/Z80PreLegalizerCombiner.cpp
+++ b/llvm/lib/Target/Z80/GISel/Z80PreLegalizerCombiner.cpp
@@ -12,61 +12,45 @@
 //===----------------------------------------------------------------------===//
 
 #include "Z80.h"
+#include "Z80Subtarget.h"
 #include "MCTargetDesc/Z80MCTargetDesc.h"
 #include "Z80InstrInfo.h"
+#include "llvm/CodeGen/GlobalISel/CSEInfo.h"
 #include "llvm/CodeGen/GlobalISel/Combiner.h"
 #include "llvm/CodeGen/GlobalISel/CombinerHelper.h"
 #include "llvm/CodeGen/GlobalISel/CombinerInfo.h"
+#include "llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h"
 #include "llvm/CodeGen/GlobalISel/GISelKnownBits.h"
+#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
 #include "llvm/CodeGen/GlobalISel/MIPatternMatch.h"
 #include "llvm/CodeGen/MachineDominators.h"
+#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/TargetPassConfig.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Target/TargetMachine.h"
 
+#define GET_GICOMBINER_DEPS
+#include "Z80GenPreLegalizeGICombiner.inc"
+#undef GET_GICOMBINER_DEPS
+
 #define DEBUG_TYPE "z80-prelegalizer-combiner"
 
 using namespace llvm;
 using namespace llvm::MIPatternMatch;
 
-#define Z80PRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_DEPS
-#include "Z80GenPreLegalizeGICombiner.inc"
-#undef Z80PRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_DEPS
-
 namespace {
-#define Z80PRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_H
-#include "Z80GenPreLegalizeGICombiner.inc"
-#undef Z80PRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_H
-
-class Z80PreLegalizerCombinerInfo : public CombinerInfo {
-  GISelKnownBits *KB;
-  MachineDominatorTree *MDT;
-  Z80GenPreLegalizerCombinerHelperRuleConfig GeneratedRuleCfg;
-
-public:
-  Z80PreLegalizerCombinerInfo(bool EnableOpt, bool OptSize, bool MinSize,
-                              GISelKnownBits *KB, MachineDominatorTree *MDT)
-      : CombinerInfo(/*AllowIllegalOps*/ true, /*ShouldLegalizeIllegal*/ false,
-                     /*LegalizerInfo*/ nullptr, EnableOpt, OptSize, MinSize),
-        KB(KB), MDT(MDT) {
-    if (!GeneratedRuleCfg.parseCommandLineOption())
-      report_fatal_error("Invalid rule identifier");
-  }
 
-  virtual bool combine(GISelChangeObserver &Observer, MachineInstr &MI,
-                       MachineIRBuilder &B) const override;
-};
+// Alias for std::optional to satisfy generated code which uses Optional<T>
+template <typename T> using Optional = std::optional<T>;
 
-bool Z80PreLegalizerCombinerInfo::combine(GISelChangeObserver &Observer,
-                                          MachineInstr &MI,
-                                          MachineIRBuilder &B) const {
-  CombinerHelper Helper(Observer, B, KB, MDT);
-  Z80GenPreLegalizerCombinerHelper Generated(GeneratedRuleCfg, Helper);
-  return Generated.tryCombineAll(Observer, MI, B, Helper);
-}
+#define GET_GICOMBINER_TYPES
+#include "Z80GenPreLegalizeGICombiner.inc"
+#undef GET_GICOMBINER_TYPES
 
-static bool matchCombineTruncShift(MachineInstr &MI, MachineRegisterInfo &MRI,
-                                   Register &SrcReg) {
+bool matchCombineTruncShift(MachineInstr &MI, MachineRegisterInfo &MRI,
+                            Register &SrcReg) {
   Register DstReg = MI.getOperand(0).getReg();
   LLT DstTy = MRI.getType(DstReg);
   if (DstTy != LLT::scalar(8))
@@ -80,9 +64,9 @@ static bool matchCombineTruncShift(MachineInstr &MI, MachineRegisterInfo &MRI,
   return SrcTy.isScalar() && SrcTy.getSizeInBits() >= 16;
 }
 
-static void applyCombineTruncShift(MachineInstr &MI, MachineIRBuilder &Builder,
-                                   GISelChangeObserver &Observer,
-                                   Register SrcReg) {
+void applyCombineTruncShift(MachineInstr &MI, MachineIRBuilder &Builder,
+                            GISelChangeObserver &Observer,
+                            Register SrcReg) {
   Builder.setInstrAndDebugLoc(MI);
   Builder.buildExtract(MI.getOperand(0), SrcReg, 8);
 
@@ -90,17 +74,17 @@ static void applyCombineTruncShift(MachineInstr &MI, MachineIRBuilder &Builder,
   MI.eraseFromParent();
 }
 
-static bool matchFlipSetCCCond(MachineInstr &MI, MachineRegisterInfo &MRI,
-                               MachineInstr *&SetCCMI) {
+bool matchFlipSetCCCond(MachineInstr &MI, MachineRegisterInfo &MRI,
+                        MachineInstr *&SetCCMI) {
   bool Imm;
   return mi_match(MI.getOperand(0).getReg(), MRI,
                   m_GXor(m_OneUse(m_MInstr(SetCCMI)), m_ICst(Imm))) &&
          SetCCMI->getOpcode() == Z80::SetCC && Imm;
 }
 
-static void applyFlipSetCCCond(MachineInstr &MI, MachineIRBuilder &Builder,
-                               GISelChangeObserver &Observer,
-                               MachineInstr &SetCCMI) {
+void applyFlipSetCCCond(MachineInstr &MI, MachineIRBuilder &Builder,
+                        GISelChangeObserver &Observer,
+                        MachineInstr &SetCCMI) {
   // Warning, SetCC has a physreg use, so don't create the SetCC at the G_XOR!
   Observer.changingInstr(SetCCMI);
   SetCCMI.getOperand(0).setReg(MI.getOperand(0).getReg());
@@ -112,9 +96,54 @@ static void applyFlipSetCCCond(MachineInstr &MI, MachineIRBuilder &Builder,
   MI.eraseFromParent();
 }
 
-#define Z80PRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_CPP
+class Z80PreLegalizerCombinerImpl : public Combiner {
+protected:
+  mutable CombinerHelper Helper;
+  const Z80PreLegalizerCombinerImplRuleConfig &RuleConfig;
+  const Z80Subtarget &STI;
+
+public:
+  Z80PreLegalizerCombinerImpl(
+      MachineFunction &MF, CombinerInfo &CInfo, const TargetPassConfig *TPC,
+      GISelKnownBits &KB, GISelCSEInfo *CSEInfo,
+      const Z80PreLegalizerCombinerImplRuleConfig &RuleConfig,
+      const Z80Subtarget &STI, MachineDominatorTree *MDT,
+      const LegalizerInfo *LI);
+
+  static const char *getName() { return "Z80PreLegalizerCombiner"; }
+
+  bool tryCombineAll(MachineInstr &I) const override;
+
+  bool tryCombineAllImpl(MachineInstr &I) const;
+
+private:
+#define GET_GICOMBINER_CLASS_MEMBERS
+#include "Z80GenPreLegalizeGICombiner.inc"
+#undef GET_GICOMBINER_CLASS_MEMBERS
+};
+
+#define GET_GICOMBINER_IMPL
 #include "Z80GenPreLegalizeGICombiner.inc"
-#undef Z80PRELEGALIZERCOMBINERHELPER_GENCOMBINERHELPER_CPP
+#undef GET_GICOMBINER_IMPL
+
+Z80PreLegalizerCombinerImpl::Z80PreLegalizerCombinerImpl(
+    MachineFunction &MF, CombinerInfo &CInfo, const TargetPassConfig *TPC,
+    GISelKnownBits &KB, GISelCSEInfo *CSEInfo,
+    const Z80PreLegalizerCombinerImplRuleConfig &RuleConfig,
+    const Z80Subtarget &STI, MachineDominatorTree *MDT,
+    const LegalizerInfo *LI)
+    : Combiner(MF, CInfo, TPC, &KB, CSEInfo),
+      Helper(Observer, B, /*IsPreLegalize*/ true, &KB, MDT, LI),
+      RuleConfig(RuleConfig), STI(STI),
+#define GET_GICOMBINER_CONSTRUCTOR_INITS
+#include "Z80GenPreLegalizeGICombiner.inc"
+#undef GET_GICOMBINER_CONSTRUCTOR_INITS
+{
+}
+
+bool Z80PreLegalizerCombinerImpl::tryCombineAll(MachineInstr &I) const {
+  return tryCombineAllImpl(I);
+}
 
 // Pass boilerplate
 // ================
@@ -123,7 +152,7 @@ class Z80PreLegalizerCombiner : public MachineFunctionPass {
 public:
   static char ID;
 
-  Z80PreLegalizerCombiner(bool IsOptNone = false);
+  Z80PreLegalizerCombiner();
 
   StringRef getPassName() const override {
     return "Z80 Pre-Legalizer Combiner";
@@ -132,8 +161,9 @@ class Z80PreLegalizerCombiner : public MachineFunctionPass {
   bool runOnMachineFunction(MachineFunction &MF) override;
 
   void getAnalysisUsage(AnalysisUsage &AU) const override;
+
 private:
-  bool IsOptNone;
+  Z80PreLegalizerCombinerImplRuleConfig RuleConfig;
 };
 } // end anonymous namespace
 
@@ -143,33 +173,47 @@ void Z80PreLegalizerCombiner::getAnalysisUsage(AnalysisUsage &AU) const {
   getSelectionDAGFallbackAnalysisUsage(AU);
   AU.addRequired<GISelKnownBitsAnalysis>();
   AU.addPreserved<GISelKnownBitsAnalysis>();
-  if (!IsOptNone) {
-    AU.addRequired<MachineDominatorTree>();
-    AU.addPreserved<MachineDominatorTree>();
-  }
+  AU.addRequired<MachineDominatorTreeWrapperPass>();
+  AU.addPreserved<MachineDominatorTreeWrapperPass>();
+  AU.addRequired<GISelCSEAnalysisWrapperPass>();
+  AU.addPreserved<GISelCSEAnalysisWrapperPass>();
   MachineFunctionPass::getAnalysisUsage(AU);
 }
 
-Z80PreLegalizerCombiner::Z80PreLegalizerCombiner(bool IsOptNone)
-    : MachineFunctionPass(ID), IsOptNone(IsOptNone) {
+Z80PreLegalizerCombiner::Z80PreLegalizerCombiner()
+    : MachineFunctionPass(ID) {
   initializeZ80PreLegalizerCombinerPass(*PassRegistry::getPassRegistry());
+
+  if (!RuleConfig.parseCommandLineOption())
+    report_fatal_error("Invalid rule identifier");
 }
 
 bool Z80PreLegalizerCombiner::runOnMachineFunction(MachineFunction &MF) {
   if (MF.getProperties().hasProperty(
           MachineFunctionProperties::Property::FailedISel))
     return false;
-  auto *TPC = &getAnalysis<TargetPassConfig>();
+  auto &TPC = getAnalysis<TargetPassConfig>();
+
+  // Enable CSE.
+  GISelCSEAnalysisWrapper &Wrapper =
+      getAnalysis<GISelCSEAnalysisWrapperPass>().getCSEWrapper();
+  auto *CSEInfo = &Wrapper.get(TPC.getCSEConfig());
+
+  const Z80Subtarget &ST = MF.getSubtarget<Z80Subtarget>();
+  const auto *LI = ST.getLegalizerInfo();
+
   const Function &F = MF.getFunction();
   bool EnableOpt =
-      MF.getTarget().getOptLevel() != CodeGenOpt::None && !skipFunction(F);
+      MF.getTarget().getOptLevel() != CodeGenOptLevel::None && !skipFunction(F);
   GISelKnownBits *KB = &getAnalysis<GISelKnownBitsAnalysis>().get(MF);
   MachineDominatorTree *MDT =
-      IsOptNone ? nullptr : &getAnalysis<MachineDominatorTree>();
-  Z80PreLegalizerCombinerInfo PCInfo(EnableOpt, F.hasOptSize(), F.hasMinSize(),
-                                     KB, MDT);
-  Combiner C(PCInfo, TPC);
-  return C.combineMachineInstrs(MF, /*CSEInfo*/ nullptr);
+      &getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
+  CombinerInfo CInfo(/*AllowIllegalOps*/ true, /*ShouldLegalizeIllegal*/ false,
+                     /*LegalizerInfo*/ nullptr, EnableOpt, F.hasOptSize(),
+                     F.hasMinSize());
+  Z80PreLegalizerCombinerImpl Impl(MF, CInfo, &TPC, *KB, CSEInfo, RuleConfig,
+                                   ST, MDT, LI);
+  return Impl.combineMachineInstrs();
 }
 
 char Z80PreLegalizerCombiner::ID = 0;
@@ -178,10 +222,11 @@ INITIALIZE_PASS_BEGIN(Z80PreLegalizerCombiner, DEBUG_TYPE,
                       false)
 INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
 INITIALIZE_PASS_DEPENDENCY(GISelKnownBitsAnalysis)
+INITIALIZE_PASS_DEPENDENCY(GISelCSEAnalysisWrapperPass)
 INITIALIZE_PASS_END(Z80PreLegalizerCombiner, DEBUG_TYPE,
                     "Combine Z80 machine instrs before legalization", false,
                     false)
 
-FunctionPass *llvm::createZ80PreLegalizeCombiner(bool IsOptNone) {
-  return new Z80PreLegalizerCombiner(IsOptNone);
+FunctionPass *llvm::createZ80PreLegalizeCombiner() {
+  return new Z80PreLegalizerCombiner();
 }
diff --git a/llvm/lib/Target/Z80/GISel/Z80RegisterBankInfo.cpp b/llvm/lib/Target/Z80/GISel/Z80RegisterBankInfo.cpp
index 97bfc18c03575..2c9a6a89a1329 100644
--- a/llvm/lib/Target/Z80/GISel/Z80RegisterBankInfo.cpp
+++ b/llvm/lib/Target/Z80/GISel/Z80RegisterBankInfo.cpp
@@ -13,8 +13,8 @@
 #include "Z80RegisterBankInfo.h"
 #include "Z80RegisterInfo.h"
 #include "MCTargetDesc/Z80MCTargetDesc.h"
-#include "llvm/CodeGen/GlobalISel/RegisterBank.h"
-#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
+#include "llvm/CodeGen/RegisterBank.h"
+#include "llvm/CodeGen/RegisterBankInfo.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/TargetRegisterInfo.h"
 
@@ -37,7 +37,6 @@ Z80RegisterBankInfo::Z80RegisterBankInfo(const TargetRegisterInfo &TRI) {
   // R24 + its subclasses.
   assert(RBGPR.covers(*TRI.getRegClass(Z80::R24RegClassID)) &&
          "Subclass not added?");
-  assert(RBGPR.getSize() == 24 && "GPRs should hold up to 24-bits");
 }
 
 const RegisterBank &
@@ -164,6 +163,6 @@ Z80RegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
 }
 
 void Z80RegisterBankInfo::applyMappingImpl(
-    const OperandsMapper &OpdMapper) const {
+    MachineIRBuilder &Builder, const OperandsMapper &OpdMapper) const {
   return applyDefaultMapping(OpdMapper);
 }
diff --git a/llvm/lib/Target/Z80/GISel/Z80RegisterBankInfo.h b/llvm/lib/Target/Z80/GISel/Z80RegisterBankInfo.h
index 7b9e2b9b52e1a..a2899abfdab37 100644
--- a/llvm/lib/Target/Z80/GISel/Z80RegisterBankInfo.h
+++ b/llvm/lib/Target/Z80/GISel/Z80RegisterBankInfo.h
@@ -13,7 +13,7 @@
 #ifndef LLVM_LIB_TARGET_Z80_Z80REGISTERBANKINFO_H
 #define LLVM_LIB_TARGET_Z80_Z80REGISTERBANKINFO_H
 
-#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
+#include "llvm/CodeGen/RegisterBankInfo.h"
 
 #define GET_REGBANK_DECLARATIONS
 #include "Z80GenRegisterBank.inc"
@@ -21,6 +21,7 @@
 namespace llvm {
 
 class LLT;
+class MachineIRBuilder;
 
 class Z80GenRegisterBankInfo : public RegisterBankInfo {
 protected:
@@ -68,7 +69,8 @@ class Z80RegisterBankInfo final : public Z80GenRegisterBankInfo {
                                              LLT Ty) const override;
 
   /// See RegisterBankInfo::applyMapping.
-  void applyMappingImpl(const OperandsMapper &OpdMapper) const override;
+  void applyMappingImpl(MachineIRBuilder &Builder,
+                        const OperandsMapper &OpdMapper) const override;
 
   const InstructionMapping &
   getInstrMapping(const MachineInstr &MI) const override;
diff --git a/llvm/lib/Target/Z80/MCTargetDesc/EZ80InstPrinter.h b/llvm/lib/Target/Z80/MCTargetDesc/EZ80InstPrinter.h
index d0f7b46ac7770..0b1c6d9cff3c8 100644
--- a/llvm/lib/Target/Z80/MCTargetDesc/EZ80InstPrinter.h
+++ b/llvm/lib/Target/Z80/MCTargetDesc/EZ80InstPrinter.h
@@ -27,10 +27,10 @@ namespace llvm {
     std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override;
     void printInstruction(const MCInst *MI, uint64_t Address,
                           raw_ostream &OS) override;
-    static const char *getRegisterName(unsigned RegNo);
+    static const char *getRegisterName(MCRegister Reg);
 
-    StringRef getRegName(unsigned RegNo) const override {
-      return getRegisterName(RegNo);
+    StringRef getRegName(MCRegister Reg) const override {
+      return getRegisterName(Reg);
     }
   };
 }
diff --git a/llvm/lib/Target/Z80/MCTargetDesc/Z80InstPrinter.h b/llvm/lib/Target/Z80/MCTargetDesc/Z80InstPrinter.h
index d10ae49961666..6e2f583fe4942 100644
--- a/llvm/lib/Target/Z80/MCTargetDesc/Z80InstPrinter.h
+++ b/llvm/lib/Target/Z80/MCTargetDesc/Z80InstPrinter.h
@@ -27,10 +27,10 @@ namespace llvm {
     std::pair<const char *, uint64_t> getMnemonic(const MCInst *MI) override;
     void printInstruction(const MCInst *MI, uint64_t Address,
                           raw_ostream &OS) override;
-    static const char *getRegisterName(unsigned RegNo);
+    static const char *getRegisterName(MCRegister Reg);
 
-    StringRef getRegName(unsigned RegNo) const override {
-      return getRegisterName(RegNo);
+    StringRef getRegName(MCRegister Reg) const override {
+      return getRegisterName(Reg);
     }
   };
 }
diff --git a/llvm/lib/Target/Z80/MCTargetDesc/Z80InstPrinterCommon.cpp b/llvm/lib/Target/Z80/MCTargetDesc/Z80InstPrinterCommon.cpp
index 5048ec228c32a..8149c327c4b0b 100644
--- a/llvm/lib/Target/Z80/MCTargetDesc/Z80InstPrinterCommon.cpp
+++ b/llvm/lib/Target/Z80/MCTargetDesc/Z80InstPrinterCommon.cpp
@@ -60,8 +60,9 @@ bool Z80InstPrinterCommon::applyTargetSpecificCLOption(StringRef Opt) {
   return false;
 }
 
-void Z80InstPrinterCommon::printRegName(raw_ostream &OS, unsigned RegNo) const {
-  OS << markup("<reg:") << getRegName(RegNo) << markup(">");
+void Z80InstPrinterCommon::printRegName(raw_ostream &OS,
+                                         MCRegister Reg) const {
+  markup(OS, Markup::Register) << getRegName(Reg);
 }
 
 void Z80InstPrinterCommon::printInst(const MCInst *MI, uint64_t Address,
@@ -78,12 +79,11 @@ void Z80InstPrinterCommon::printOperand(const MCInst *MI, unsigned OpNo,
   if (Op.isReg())
     printRegName(OS, Op.getReg());
   else if (Op.isImm())
-    OS << markup("<imm:") << formatImm(Op.getImm()) << markup(">");
+    markup(OS, Markup::Immediate) << formatImm(Op.getImm());
   else {
     assert(Op.isExpr() && "unknown operand kind in printOperand");
-    OS << markup("<imm:");
+    WithMarkup M = markup(OS, Markup::Immediate);
     Op.getExpr()->print(OS, &MAI);
-    OS << markup(">");
   }
 }
 
@@ -94,7 +94,7 @@ void Z80InstPrinterCommon::printOperand(const MCInst *MI, uint64_t Address,
 
 void Z80InstPrinterCommon::printCondCode(const MCInst *MI, unsigned Op,
                                          raw_ostream &OS) {
-  OS << markup("<cc:");
+  WithMarkup M = markup(OS, Markup::Immediate);
   switch (unsigned CondCode = MI->getOperand(Op).getImm()) {
   default:
     llvm_unreachable("Invalid condition code operand!");
@@ -127,7 +127,6 @@ void Z80InstPrinterCommon::printCondCode(const MCInst *MI, unsigned Op,
     OS << 'm';
     break;
   }
-  OS << markup(">");
 }
 
 void Z80InstPrinterCommon::printOffset(const MCInst *MI, unsigned Op,
@@ -142,14 +141,16 @@ void Z80InstPrinterCommon::printOffset(const MCInst *MI, unsigned Op,
 
 void Z80InstPrinterCommon::printIndirect(const MCInst *MI, unsigned Op,
                                          raw_ostream &OS) {
-  OS << markup("<mem:") << '(';
+  WithMarkup M = markup(OS, Markup::Memory);
+  OS << '(';
   printOperand(MI, Op, OS);
-  OS << ')' << markup(">");
+  OS << ')';
 }
 
 void Z80InstPrinterCommon::printIndirectOffset(const MCInst *MI, unsigned Op,
                                                raw_ostream &OS) {
-  OS << markup("<mem:") << '(';
+  WithMarkup M = markup(OS, Markup::Memory);
+  OS << '(';
   printOffset(MI, Op, OS);
-  OS << ')' << markup(">");
+  OS << ')';
 }
diff --git a/llvm/lib/Target/Z80/MCTargetDesc/Z80InstPrinterCommon.h b/llvm/lib/Target/Z80/MCTargetDesc/Z80InstPrinterCommon.h
index 52ec94c136218..18fc2e670c0e2 100644
--- a/llvm/lib/Target/Z80/MCTargetDesc/Z80InstPrinterCommon.h
+++ b/llvm/lib/Target/Z80/MCTargetDesc/Z80InstPrinterCommon.h
@@ -16,6 +16,7 @@
 #define LLVM_LIB_TARGET_Z80_INSTPRINTER_Z80INSTPRINTERCOMMON_H
 
 #include "llvm/MC/MCInstPrinter.h"
+#include "llvm/MC/MCRegister.h"
 
 namespace llvm {
 class Z80InstPrinterCommon : public MCInstPrinter {
@@ -25,14 +26,14 @@ class Z80InstPrinterCommon : public MCInstPrinter {
 
   bool applyTargetSpecificCLOption(StringRef Opt) override;
 
-  void printRegName(raw_ostream &OS, unsigned RegNo) const override;
+  void printRegName(raw_ostream &OS, MCRegister Reg) const override;
   void printInst(const MCInst *MI, uint64_t Address, StringRef Annot,
                  const MCSubtargetInfo &STI, raw_ostream &OS) override;
 
   // Autogenerated by tblgen.
   virtual void printInstruction(const MCInst *MI, uint64_t Address,
                                 raw_ostream &OS) = 0;
-  virtual StringRef getRegName(unsigned RegNo) const = 0;
+  virtual StringRef getRegName(MCRegister Reg) const = 0;
 
   void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &OS);
   void printOperand(const MCInst *MI, uint64_t Address, unsigned OpNo,
diff --git a/llvm/lib/Target/Z80/MCTargetDesc/Z80MCAsmInfo.cpp b/llvm/lib/Target/Z80/MCTargetDesc/Z80MCAsmInfo.cpp
index f47c4d8fa7e4f..24a42b6a466a4 100644
--- a/llvm/lib/Target/Z80/MCTargetDesc/Z80MCAsmInfo.cpp
+++ b/llvm/lib/Target/Z80/MCTargetDesc/Z80MCAsmInfo.cpp
@@ -13,7 +13,7 @@
 
 #include "Z80MCAsmInfo.h"
 #include "llvm/ADT/StringSwitch.h"
-#include "llvm/ADT/Triple.h"
+#include "llvm/TargetParser/Triple.h"
 #include "llvm/MC/MCExpr.h"
 #include "llvm/Support/CommandLine.h"
 using namespace llvm;
diff --git a/llvm/lib/Target/Z80/MCTargetDesc/Z80MCTargetDesc.cpp b/llvm/lib/Target/Z80/MCTargetDesc/Z80MCTargetDesc.cpp
index 6f5787a720570..0aa44007541af 100644
--- a/llvm/lib/Target/Z80/MCTargetDesc/Z80MCTargetDesc.cpp
+++ b/llvm/lib/Target/Z80/MCTargetDesc/Z80MCTargetDesc.cpp
@@ -102,8 +102,7 @@ static MCInstPrinter *createZ80MCInstPrinter(const Triple &T,
 
 static MCTargetStreamer *
 createZ80AsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS,
-                           MCInstPrinter */*InstPrint*/,
-                           bool /*isVerboseAsm*/) {
+                           MCInstPrinter */*InstPrint*/) {
   return new Z80TargetAsmStreamer(S, OS);
 }
 
diff --git a/llvm/lib/Target/Z80/MCTargetDesc/Z80TargetStreamer.cpp b/llvm/lib/Target/Z80/MCTargetDesc/Z80TargetStreamer.cpp
index 160d370086826..ce2c3f3ea8c2c 100644
--- a/llvm/lib/Target/Z80/MCTargetDesc/Z80TargetStreamer.cpp
+++ b/llvm/lib/Target/Z80/MCTargetDesc/Z80TargetStreamer.cpp
@@ -13,6 +13,7 @@
 
 #include "Z80TargetStreamer.h"
 #include "llvm/MC/MCContext.h"
+#include "llvm/MC/MCSymbol.h"
 #include "llvm/Support/FormattedStream.h"
 
 using namespace llvm;
diff --git a/llvm/lib/Target/Z80/MCTargetDesc/Z80TargetStreamer.h b/llvm/lib/Target/Z80/MCTargetDesc/Z80TargetStreamer.h
index bcca97d3b286b..ca0e24bb1b710 100644
--- a/llvm/lib/Target/Z80/MCTargetDesc/Z80TargetStreamer.h
+++ b/llvm/lib/Target/Z80/MCTargetDesc/Z80TargetStreamer.h
@@ -16,6 +16,7 @@
 #ifndef LLVM_LIB_TARGET_Z80_MCTARGETDESC_Z80TARGETSTREAMER_H
 #define LLVM_LIB_TARGET_Z80_MCTARGETDESC_Z80TARGETSTREAMER_H
 
+#include "llvm/MC/MCAsmInfo.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/Support/Alignment.h"
 
diff --git a/llvm/lib/Target/Z80/Z80.h b/llvm/lib/Target/Z80/Z80.h
index 50a98240bbf8e..a11d402fee753 100644
--- a/llvm/lib/Target/Z80/Z80.h
+++ b/llvm/lib/Target/Z80/Z80.h
@@ -24,8 +24,8 @@ class Z80RegisterBankInfo;
 class Z80Subtarget;
 class Z80TargetMachine;
 
-FunctionPass *createZ80PreLegalizeCombiner(bool IsOptNone);
-FunctionPass *createZ80PostLegalizeCombiner(bool IsOptNone);
+FunctionPass *createZ80PreLegalizeCombiner();
+FunctionPass *createZ80PostLegalizeCombiner();
 InstructionSelector *createZ80InstructionSelector(const Z80TargetMachine &TM,
                                                   Z80Subtarget &,
                                                   Z80RegisterBankInfo &);
diff --git a/llvm/lib/Target/Z80/Z80AsmPrinter.cpp b/llvm/lib/Target/Z80/Z80AsmPrinter.cpp
index 69e64fd449578..a43a5b4b0dda7 100644
--- a/llvm/lib/Target/Z80/Z80AsmPrinter.cpp
+++ b/llvm/lib/Target/Z80/Z80AsmPrinter.cpp
@@ -18,7 +18,9 @@
 #include "MCTargetDesc/Z80TargetStreamer.h"
 #include "Z80.h"
 #include "Z80Subtarget.h"
+#include "llvm/IR/GlobalAlias.h"
 #include "llvm/IR/GlobalVariable.h"
+#include "llvm/IR/Module.h"
 #include "llvm/MC/MCContext.h"
 #include "llvm/MC/MCStreamer.h"
 #include "llvm/MC/TargetRegistry.h"
@@ -56,8 +58,8 @@ void Z80AsmPrinter::emitEndOfAsmFile(Module &M) {
   Z80TargetStreamer *TS =
       static_cast<Z80TargetStreamer *>(OutStreamer->getTargetStreamer());
   for (const auto &Symbol : OutContext.getSymbols())
-    if (!Symbol.second->isDefined())
-      TS->emitExtern(Symbol.second);
+    if (Symbol.second.Symbol && !Symbol.second.Symbol->isDefined())
+      TS->emitExtern(Symbol.second.Symbol);
 }
 
 void Z80AsmPrinter::emitGlobalVariable(const GlobalVariable *GV) {
@@ -99,13 +101,13 @@ void Z80AsmPrinter::emitGlobalVariable(const GlobalVariable *GV) {
     TS->emitBlock(DL.getTypeAllocSize(GV->getValueType()));
   else
     emitGlobalConstant(DL, GV->getInitializer());
-  OutStreamer->AddBlankLine();
+  OutStreamer->addBlankLine();
 }
 
-void Z80AsmPrinter::emitGlobalAlias(Module &M, const GlobalAlias &GA) {
+void Z80AsmPrinter::emitGlobalAlias(const Module &M, const GlobalAlias &GA) {
   SwitchSectionForGlobal(GA.getAliaseeObject());
   AsmPrinter::emitGlobalAlias(M, GA);
-  OutStreamer->AddBlankLine();
+  OutStreamer->addBlankLine();
 }
 
 SectionKind Z80AsmPrinter::SwitchSectionForGlobal(const GlobalObject *GO) {
@@ -116,7 +118,7 @@ SectionKind Z80AsmPrinter::SwitchSectionForGlobal(const GlobalObject *GO) {
     // Determine to which section this global should be emitted.
     Section = getObjFileLowering().SectionForGlobal(GO, GOKind, TM);
   }
-  OutStreamer->SwitchSection(Section);
+  OutStreamer->switchSection(Section);
   return GOKind;
 }
 
diff --git a/llvm/lib/Target/Z80/Z80AsmPrinter.h b/llvm/lib/Target/Z80/Z80AsmPrinter.h
index 887c7436f0d18..59e65e92ef1b8 100644
--- a/llvm/lib/Target/Z80/Z80AsmPrinter.h
+++ b/llvm/lib/Target/Z80/Z80AsmPrinter.h
@@ -38,7 +38,7 @@ class LLVM_LIBRARY_VISIBILITY Z80AsmPrinter : public AsmPrinter {
                         const MCSubtargetInfo *EndInfo) const override;
   void emitEndOfAsmFile(Module &M) override;
   void emitGlobalVariable(const GlobalVariable *GV) override;
-  void emitGlobalAlias(Module &M, const GlobalAlias &GA) override;
+  void emitGlobalAlias(const Module &M, const GlobalAlias &GA) override;
   void emitInstruction(const MachineInstr *MI) override;
 
 private:
diff --git a/llvm/lib/Target/Z80/Z80BranchSelector.cpp b/llvm/lib/Target/Z80/Z80BranchSelector.cpp
index 249447ef608be..60d6c94c8a911 100644
--- a/llvm/lib/Target/Z80/Z80BranchSelector.cpp
+++ b/llvm/lib/Target/Z80/Z80BranchSelector.cpp
@@ -18,7 +18,7 @@
 #include "Z80.h"
 #include "Z80InstrInfo.h"
 #include "Z80Subtarget.h"
-#include "llvm/ADT/Optional.h"
+#include <optional>
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 using namespace llvm;
@@ -123,7 +123,7 @@ template <typename T> class OffsetTree {
     )
       return Tree[Idx];
     T Result{};
-    Optional<size_type> CurrentIdx = Idx;
+    std::optional<size_type> CurrentIdx = Idx;
     do
       Result += Tree[*CurrentIdx];
     while ((CurrentIdx = toParentIndex(*CurrentIdx)));
@@ -145,7 +145,7 @@ template <typename T> class OffsetTree {
 
   void adjust(size_type Idx, T Amt) {
     assert(IsFrozen);
-    Optional<size_type> ParentIdx = Idx, ChildIdx = toFirstChildIndex(Idx);
+    std::optional<size_type> ParentIdx = Idx, ChildIdx = toFirstChildIndex(Idx);
     do {
       if (ChildIdx)
         Tree[*ChildIdx] -= Amt;
@@ -164,42 +164,42 @@ template <typename T> class OffsetTree {
   // This returns a mask with a single bit set in the same location as the least
   // significant unset bit of X.
   static size_type lowestZeroMask(size_type X) { return ~X & (X + 1); }
-  Optional<size_type> toParentIndex(size_type Idx) const {
+  std::optional<size_type> toParentIndex(size_type Idx) const {
     assert(Idx <= size());
     size_type Mask = lowestZeroMask(Idx);
     do {
       if (Mask > size())
-        return None;
+        return std::nullopt;
       Idx |= Mask;
       Mask <<= 1;
       Idx &= ~Mask;
     } while (Idx > size());
     return Idx;
   }
-  Optional<size_type> toFirstChildIndex(size_type Idx) {
+  std::optional<size_type> toFirstChildIndex(size_type Idx) {
     assert(Idx <= size());
     size_type Mask = lowestZeroMask(Idx) >> 1;
     if (!Mask)
-      return None;
+      return std::nullopt;
     return Idx & ~Mask;
   }
-  Optional<size_type> toSecondChildIndex(size_type Idx) {
+  std::optional<size_type> toSecondChildIndex(size_type Idx) {
     assert(Idx <= size());
     size_type Mask = lowestZeroMask(Idx);
     Idx |= Mask;
     do {
       Mask >>= 1;
       if (!Mask)
-        return None;
+        return std::nullopt;
       Idx &= ~Mask;
     } while (Idx > size());
     return Idx;
   }
-  Optional<size_type> toSiblingIndex(size_type Idx) {
+  std::optional<size_type> toSiblingIndex(size_type Idx) {
     assert(Idx <= size());
     Idx ^= lowestZeroMask(Idx) << 1;
     if (Idx > size())
-      return None;
+      return std::nullopt;
     return Idx;
   }
 
@@ -266,12 +266,12 @@ class BranchTracker {
     TargetTree.add();
   }
 
-  Optional<Range<Offset>>
+  std::optional<Range<Offset>>
   getBranchDisplacementIfAdded(const MachineInstr &Branch) const {
     assert(Phase == Phase::Build);
     size_type TargetIdx = getBranchTargetIndex(Branch);
     if (TargetIdx >= TargetTree.size())
-      return None;
+      return std::nullopt;
     return TargetTree.get<Tree::Unfrozen>(TargetIdx) -
            TargetTree.current<Tree::Unfrozen>();
   }
diff --git a/llvm/lib/Target/Z80/Z80Combine.td b/llvm/lib/Target/Z80/Z80Combine.td
index f3c57e50e6e7f..b48668a546967 100644
--- a/llvm/lib/Target/Z80/Z80Combine.td
+++ b/llvm/lib/Target/Z80/Z80Combine.td
@@ -25,8 +25,8 @@ def flip_setcc_cond : GICombineRule<
          [{ return matchFlipSetCCCond(*${mi}, MRI, ${matchinfo}); }]),
   (apply [{ applyFlipSetCCCond(*${mi}, B, Observer, *${matchinfo}); }])>;
 
-def Z80PreLegalizerCombinerHelper
-    : GICombiner<"Z80GenPreLegalizerCombinerHelper", [
+def Z80PreLegalizerCombiner
+    : GICombiner<"Z80PreLegalizerCombinerImpl", [
         and_ext, and_or_disjoint_mask, combine_ext_or_trunc, combine_identity,
         combine_trunc_shift, /* constant_fold, */ const_combines, div_rem_to_divrem,
         ext_ext_fold, /*fabs_fabs_fold,*/ fabs_fneg_fold, flip_cmp_cond,
@@ -40,20 +40,19 @@ def Z80PreLegalizerCombinerHelper
         ptr_add_with_zero, reassocs, reassoc_fold_consts,
         redundant_neg_operands, select_combines, sext_to_zext,
         shift_immed_chain, shift_of_shifted_logic_chain, shl_ashr_to_sext_inreg,
-        simplify_add_to_sub, simplify_const, simplify_icmp_bool,
+        simplify_add_to_sub, simplify_icmp_bool,
         simplify_known_const, split_brcond, sub_const_to_add_neg,
         trivial_combines, /*truncstore_merge,*/ trunc_ext_fold, /*trunc_shl,*/
         undef_combines, unmerge_cst, unmerge_dead_to_trunc, unmerge_merge,
         unmerge_zext_to_zext, width_reduction_combines,
         xor_of_and_with_same_reg,
     ]> {
-  /*let DisableRuleOption = "z80prelegalizercombiner-disable-rule";*/
+  let CombineAllMethodName = "tryCombineAllImpl";
 }
 
-def Z80PostLegalizerCombinerHelper
-    : GICombiner<"Z80GenPostLegalizerCombinerHelper", [
+def Z80PostLegalizerCombiner
+    : GICombiner<"Z80PostLegalizerCombinerImpl", [
         combine_identity, narrow_op, simplify_known_const, trunc_ext_fold,
         unmerge_zext_to_zext,
     ]> {
-  /*let DisableRuleOption = "z80postlegalizercombiner-disable-rule";*/
 }
diff --git a/llvm/lib/Target/Z80/Z80FrameLowering.cpp b/llvm/lib/Target/Z80/Z80FrameLowering.cpp
index 861a1a3e8ab4f..58a55b6a6d2fd 100644
--- a/llvm/lib/Target/Z80/Z80FrameLowering.cpp
+++ b/llvm/lib/Target/Z80/Z80FrameLowering.cpp
@@ -415,7 +415,7 @@ bool Z80FrameLowering::assignCalleeSavedSpillSlots(
     std::vector<CalleeSavedInfo> &CSI) const {
   auto &FuncInfo = *MF.getInfo<Z80MachineFunctionInfo>();
   FuncInfo.setUsesAltFP(shouldUseAltFP(MF, Is24Bit ? Z80::UIY : Z80::IY, TRI));
-  MF.getRegInfo().freezeReservedRegs(MF);
+  MF.getRegInfo().freezeReservedRegs();
 
   bool UseShadow = shouldUseShadow(MF);
   unsigned CalleeSavedFrameSize = isFPSaved(MF) ? SlotSize : 0;
diff --git a/llvm/lib/Target/Z80/Z80ISelLowering.cpp b/llvm/lib/Target/Z80/Z80ISelLowering.cpp
index 676565e2beec6..8d2c6277356af 100644
--- a/llvm/lib/Target/Z80/Z80ISelLowering.cpp
+++ b/llvm/lib/Target/Z80/Z80ISelLowering.cpp
@@ -457,7 +457,7 @@ MachineBasicBlock *Z80TargetLowering::EmitLoweredSExt(
     break;
   }
   MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, TII->get(Opc));
-  MIB->findRegisterUseOperand(Reg)->setIsUndef();
+  MIB->findRegisterUseOperand(Reg, Subtarget.getRegisterInfo())->setIsUndef();
   if (Reg == Z80::A)
     MIB.addReg(Reg, RegState::Undef);
   MI.eraseFromParent();
@@ -654,13 +654,13 @@ Z80TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
   return std::make_pair(Z80::NoRegister, nullptr);
 }
 
-unsigned
+InlineAsm::ConstraintCode
 Z80TargetLowering::getInlineAsmMemConstraint(StringRef Constraint) const {
   if (Constraint.size() == 1)
     switch (Constraint[0]) {
-    case 'V': return InlineAsm::Constraint_V;
-    case 'o': return InlineAsm::Constraint_o;
-    case 'X': return InlineAsm::Constraint_X;
+    case 'V': return InlineAsm::ConstraintCode::V;
+    case 'o': return InlineAsm::ConstraintCode::o;
+    case 'X': return InlineAsm::ConstraintCode::X;
     }
   return TargetLowering::getInlineAsmMemConstraint(Constraint);
 }
diff --git a/llvm/lib/Target/Z80/Z80ISelLowering.h b/llvm/lib/Target/Z80/Z80ISelLowering.h
index 602876817d3c2..db1eb73ab5499 100644
--- a/llvm/lib/Target/Z80/Z80ISelLowering.h
+++ b/llvm/lib/Target/Z80/Z80ISelLowering.h
@@ -130,7 +130,7 @@ class Z80TargetLowering final : public TargetLowering {
   getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
                                StringRef Constraint, MVT VT) const override;
 
-  unsigned getInlineAsmMemConstraint(StringRef Constraint) const override;
+  InlineAsm::ConstraintCode getInlineAsmMemConstraint(StringRef Constraint) const override;
 };
 } // End llvm namespace
 
diff --git a/llvm/lib/Target/Z80/Z80InstrInfo.cpp b/llvm/lib/Target/Z80/Z80InstrInfo.cpp
index fb7093fac224e..54892ec633069 100644
--- a/llvm/lib/Target/Z80/Z80InstrInfo.cpp
+++ b/llvm/lib/Target/Z80/Z80InstrInfo.cpp
@@ -116,7 +116,7 @@ unsigned Z80InstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
     // index prefix cannot be combined with ED prefix
     EDPre = false;
     // (ix) gains an offset
-    if (MI.getDesc().OpInfo[OpIdx].OperandType == MCOI::OPERAND_MEMORY)
+    if (MI.getDesc().operands()[OpIdx].OperandType == MCOI::OPERAND_MEMORY)
       HasOff = true;
   }
 
@@ -526,7 +526,7 @@ void Z80InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
         // an intermediate register.
         applySPAdjust(
             *BuildMI(MBB, MI, DL, get(Is24Bit ? Z80::PUSH24AF : Z80::PUSH16AF)))
-            .findRegisterUseOperand(Z80::AF)->setIsUndef();
+            .findRegisterUseOperand(Z80::AF, &RI)->setIsUndef();
         BuildMI(MBB, MI, DL, get(Z80::X8RegClass.contains(SrcReg) ? Z80::LD8xx
                                                                   : Z80::LD8yy),
                 Z80::A).addReg(SrcReg, getKillRegState(KillSrc));
@@ -552,9 +552,9 @@ void Z80InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
         // If the prev instr was an EX DE,HL, just kill it.
         if (MI == MBB.begin() || std::prev(MI)->getOpcode() != ExOpc) {
           auto Ex = BuildMI(MBB, MI, DL, get(ExOpc));
-          Ex->findRegisterUseOperand(Is24Bit ? Z80::UDE : Z80::DE)
+          Ex->findRegisterUseOperand(Is24Bit ? Z80::UDE : Z80::DE, &RI)
               ->setIsUndef();
-          Ex->findRegisterUseOperand(Is24Bit ? Z80::UHL : Z80::HL)
+          Ex->findRegisterUseOperand(Is24Bit ? Z80::UHL : Z80::HL, &RI)
               ->setIsUndef();
         } else
           std::prev(MI)->eraseFromParent();
@@ -565,7 +565,7 @@ void Z80InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
               DstReg).addReg(SrcReg, getKillRegState(KillSrc));
       if (NeedEX)
         BuildMI(MBB, MI, DL, get(ExOpc))
-          ->findRegisterUseOperand(Is24Bit ? Z80::UHL : Z80::HL)->setIsUndef();
+          ->findRegisterUseOperand(Is24Bit ? Z80::UHL : Z80::HL, &RI)->setIsUndef();
     }
     return;
   }
@@ -612,7 +612,7 @@ void Z80InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
           .addReg(TempReg, RegState::ImplicitDefine);
     applySPAdjust(
         *BuildMI(MBB, MI, DL, get(Is24Bit ? Z80::PUSH24AF : Z80::PUSH16AF)))
-        .findRegisterUseOperand(Z80::AF)->setIsUndef();
+        .findRegisterUseOperand(Z80::AF, &RI)->setIsUndef();
     BuildMI(MBB, MI, DL, get(Is24Bit ? Z80::EX24sa : Z80::EX16sa), TempReg)
         .addReg(TempReg, RegState::Undef);
     copyPhysReg(MBB, MI, DL, DstReg, Z80::L, KillSrc);
@@ -687,9 +687,9 @@ void Z80InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
       MachineInstrBuilder MIB = BuildMI(MBB, MI, DL,
                                         get(Is24Bit ? Z80::EX24DE
                                                     : Z80::EX16DE));
-      MIB->findRegisterUseOperand(SrcReg)->setIsKill();
-      MIB->findRegisterDefOperand(SrcReg)->setIsDead();
-      MIB->findRegisterUseOperand(DstReg)->setIsUndef();
+      MIB->findRegisterUseOperand(SrcReg, &RI)->setIsKill();
+      MIB->findRegisterDefOperand(SrcReg, &RI)->setIsDead();
+      MIB->findRegisterUseOperand(DstReg, &RI)->setIsUndef();
       return;
     }
     bool IsSrcIndexReg = Z80::I16RegClass.contains(SrcReg) ||
@@ -793,7 +793,8 @@ void Z80InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
                                        MachineBasicBlock::iterator MI,
                                        Register SrcReg, bool IsKill, int FI,
                                        const TargetRegisterClass *TRC,
-                                       const TargetRegisterInfo *TRI) const {
+                                       const TargetRegisterInfo *TRI,
+                                       Register VReg) const {
   const DebugLoc &DL = MBB.findDebugLoc(MI);
   bool Is24Bit = Subtarget.is24Bit();
 
@@ -803,10 +804,10 @@ void Z80InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
     Register TempReg = Is24Bit ? Z80::UHL : Z80::HL;
     applySPAdjust(
         *BuildMI(MBB, MI, DL, get(Is24Bit ? Z80::PUSH24AF : Z80::PUSH16AF)))
-        .findRegisterUseOperand(Z80::AF)->setIsUndef();
+        .findRegisterUseOperand(Z80::AF, &RI)->setIsUndef();
     BuildMI(MBB, MI, DL, get(Is24Bit ? Z80::EX24sa : Z80::EX16sa), TempReg)
         .addReg(TempReg, RegState::Undef);
-    storeRegToStackSlot(MBB, MI, Z80::L, true, FI, &Z80::R8RegClass, TRI);
+    storeRegToStackSlot(MBB, MI, Z80::L, true, FI, &Z80::R8RegClass, TRI, Register());
     applySPAdjust(*BuildMI(MBB, MI, DL,
                            get(Is24Bit ? Z80::POP24r : Z80::POP16r), TempReg));
     return;
@@ -836,7 +837,8 @@ void Z80InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
                                         MachineBasicBlock::iterator MI,
                                         Register DstReg, int FI,
                                         const TargetRegisterClass *TRC,
-                                        const TargetRegisterInfo *TRI) const {
+                                        const TargetRegisterInfo *TRI,
+                                        Register VReg) const {
   const DebugLoc &DL = MBB.findDebugLoc(MI);
   bool Is24Bit = Subtarget.is24Bit();
 
@@ -847,7 +849,7 @@ void Z80InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
     applySPAdjust(
         *BuildMI(MBB, MI, DL, get(Is24Bit ? Z80::PUSH24r : Z80::PUSH16r))
              .addReg(TempReg, RegState::Undef));
-    loadRegFromStackSlot(MBB, MI, Z80::L, FI, &Z80::R8RegClass, TRI);
+    loadRegFromStackSlot(MBB, MI, Z80::L, FI, &Z80::R8RegClass, TRI, Register());
     BuildMI(MBB, MI, DL, get(TargetOpcode::COPY), Z80::H)
         .addReg(Z80::A, RegState::Undef); // Preserve A
     BuildMI(MBB, MI, DL, get(Is24Bit ? Z80::EX24sa : Z80::EX16sa), TempReg)
@@ -909,7 +911,7 @@ static bool isFrameLoadOpcode(int Opcode) {
     return true;
   }
 }
-unsigned Z80InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
+Register Z80InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
                                            int &FrameIndex) const {
   if (isFrameLoadOpcode(MI.getOpcode()) && !MI.getOperand(0).getSubReg() &&
       isFrameOperand(MI, 1, FrameIndex))
@@ -923,7 +925,7 @@ static Register scavengeOrCreateRegister(const TargetRegisterClass *RC,
                                          RegScavenger *RS = nullptr,
                                          int SPAdj = 0,
                                          bool AllowSpill = true) {
-  return RS ? RS->scavengeRegister(RC, II, SPAdj, AllowSpill)
+  return RS ? RS->scavengeRegisterBackwards(*RC, II, /*RestoreAfter=*/false, SPAdj, AllowSpill)
             : MRI.createVirtualRegister(RC);
 }
 
@@ -954,7 +956,7 @@ void Z80InstrInfo::rewriteFrameIndex(MachineInstr &MI, unsigned FIOperandNum,
     MI.getOperand(FIOperandNum).ChangeToRegister(BaseReg, false);
     if (!NewOffset && (Opc == Z80::PEA24o || Opc == Z80::PEA16o)) {
       MI.setDesc(get(Opc == Z80::PEA24o ? Z80::PUSH24r : Z80::PUSH16r));
-      MI.RemoveOperand(FIOperandNum + 1);
+      MI.removeOperand(FIOperandNum + 1);
       return;
     }
     MI.getOperand(FIOperandNum + 1).ChangeToImmediate(NewOffset);
@@ -975,7 +977,7 @@ void Z80InstrInfo::rewriteFrameIndex(MachineInstr &MI, unsigned FIOperandNum,
     if (SaveFlags)
       applySPAdjust(
           *BuildMI(MBB, II, DL, get(Is24Bit ? Z80::PUSH24AF : Z80::PUSH16AF)))
-          .findRegisterUseOperand(Z80::AF)->setIsUndef();
+          .findRegisterUseOperand(Z80::AF, &RI)->setIsUndef();
     BuildMI(MBB, II, DL, get(Is24Bit ? Z80::ADD24ao : Z80::ADD16ao), Op0Reg)
         .addReg(Op0Reg).addReg(OffsetReg, RegState::Kill)
         ->addRegisterDead(Z80::F, &TRI);
@@ -994,7 +996,7 @@ void Z80InstrInfo::rewriteFrameIndex(MachineInstr &MI, unsigned FIOperandNum,
     if (SaveFlags)
       applySPAdjust(
           *BuildMI(MBB, II, DL, get(Is24Bit ? Z80::PUSH24AF : Z80::PUSH16AF)))
-          .findRegisterUseOperand(Z80::AF)->setIsUndef();
+          .findRegisterUseOperand(Z80::AF, &RI)->setIsUndef();
     Register TempReg = createIfVirtual(ScratchReg, MRI);
     BuildMI(MBB, II, DL, get(Is24Bit ? Z80::ADD24ao : Z80::ADD16ao), TempReg)
         .addReg(ScratchReg).addReg(OffsetReg, RegState::Kill)
@@ -1054,7 +1056,7 @@ void Z80InstrInfo::rewriteFrameIndex(MachineInstr &MI, unsigned FIOperandNum,
       return;
     }
     MI.setDesc(get(Opc));
-    MI.RemoveOperand(FIOperandNum + 1);
+    MI.removeOperand(FIOperandNum + 1);
     return;
   }
 
@@ -1066,7 +1068,7 @@ void Z80InstrInfo::rewriteFrameIndex(MachineInstr &MI, unsigned FIOperandNum,
   if (SaveFlags)
     applySPAdjust(
         *BuildMI(MBB, II, DL, get(Is24Bit ? Z80::PUSH24AF : Z80::PUSH16AF)))
-        .findRegisterUseOperand(Z80::AF)->setIsUndef();
+        .findRegisterUseOperand(Z80::AF, &RI)->setIsUndef();
   BuildMI(MBB, II, DL, get(Is24Bit ? Z80::ADD24ao : Z80::ADD16ao), BaseReg)
       .addReg(BaseReg).addReg(OffsetReg, RegState::Kill)
       ->addRegisterDead(Z80::F, &TRI);
@@ -1104,7 +1106,7 @@ static bool isFrameStoreOpcode(int Opcode) {
     return true;
   }
 }
-unsigned Z80InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
+Register Z80InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
                                           int &FrameIndex) const {
   if (isFrameStoreOpcode(MI.getOpcode()) && !MI.getOperand(2).getSubReg() &&
       isFrameOperand(MI, 0, FrameIndex))
@@ -1112,8 +1114,7 @@ unsigned Z80InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
   return 0;
 }
 
-bool Z80InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI,
-                                                     AAResults *AA) const {
+bool Z80InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI) const {
   switch (MI.getOpcode()) {
   case Z80::LD8r0:
   case Z80::LD24r0:
@@ -1183,7 +1184,7 @@ bool Z80InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
       MIB.addReg(Z80::A, RegState::ImplicitDefine);
     } else {
       MI.setDesc(get(Z80::LD8ri));
-      MI.findRegisterDefOperand(Z80::F)->ChangeToImmediate(0);
+      MI.findRegisterDefOperand(Z80::F, &RI)->ChangeToImmediate(0);
     }
     break;
   case Z80::LD24r0:
@@ -1199,7 +1200,7 @@ bool Z80InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
           .addReg(Z80::F, RegState::Implicit);
     } else {
       MI.setDesc(get(Z80::LD24ri));
-      MI.findRegisterDefOperand(Z80::F)
+      MI.findRegisterDefOperand(Z80::F, &RI)
         ->ChangeToImmediate(Opc == Z80::LD24r0 ? 0 : -1);
     }
     break;
@@ -1241,7 +1242,7 @@ bool Z80InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
     if (Z80::I8RegClass.contains(DstOp.getReg())) {
       applySPAdjust(
           *BuildMI(MBB, MI, DL, get(Is24Bit ? Z80::PUSH24AF : Z80::PUSH16AF)))
-          .findRegisterUseOperand(Z80::AF)->setIsUndef();
+          .findRegisterUseOperand(Z80::AF, &RI)->setIsUndef();
       copyPhysReg(MBB, Next, DL, DstOp.getReg(), Z80::A, true);
       DstOp.setReg(Z80::A);
       applySPAdjust(
@@ -1331,7 +1332,7 @@ bool Z80InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
     if (Z80::I8RegClass.contains(SrcOp.getReg())) {
       applySPAdjust(
           *BuildMI(MBB, MI, DL, get(Is24Bit ? Z80::PUSH24AF : Z80::PUSH16AF)))
-          .findRegisterUseOperand(Z80::AF)->setIsUndef();
+          .findRegisterUseOperand(Z80::AF, &RI)->setIsUndef();
       copyPhysReg(MBB, MI, DL, Z80::A, SrcOp.getReg(), SrcOp.isKill());
       SrcOp.setReg(Z80::A);
       SrcOp.setIsKill();
@@ -1395,7 +1396,7 @@ bool Z80InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
       // Save A
       applySPAdjust(
           *BuildMI(MBB, MI, DL, get(Is24Bit ? Z80::PUSH24AF : Z80::PUSH16AF)))
-          .findRegisterUseOperand(Z80::AF)->setIsUndef();
+          .findRegisterUseOperand(Z80::AF, &RI)->setIsUndef();
       HighReg = Z80::A;
     }
     MI.setDesc(get(HighOpc));
@@ -1667,7 +1668,7 @@ bool Z80InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
   case Z80::SUB8ao: CpOpc = Z80::CP8ao; break;
   }
   if (CpOpc) {
-    int DeadDef = CmpInstr.findRegisterDefOperandIdx(Z80::A, /*isDead*/true);
+    int DeadDef = CmpInstr.findRegisterDefOperandIdx(Z80::A, &getRegisterInfo(), /*isDead*/true);
     if (DeadDef == -1)
       return false;
     // There is no use of the destination register, so we replace SUB with CP.
@@ -1675,7 +1676,7 @@ bool Z80InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg,
     if (CpOpc == Z80::OR8ar)
       CmpInstr.getOperand(0).ChangeToRegister(Z80::A, false);
     else
-      CmpInstr.RemoveOperand(DeadDef);
+      CmpInstr.removeOperand(DeadDef);
   }
 
   // Get the unique definition of SrcReg.
diff --git a/llvm/lib/Target/Z80/Z80InstrInfo.h b/llvm/lib/Target/Z80/Z80InstrInfo.h
index 97fe6ec100f0e..a1f07dfed9031 100644
--- a/llvm/lib/Target/Z80/Z80InstrInfo.h
+++ b/llvm/lib/Target/Z80/Z80InstrInfo.h
@@ -133,22 +133,23 @@ class Z80InstrInfo final : public Z80GenInstrInfo {
                            MachineBasicBlock::iterator MI, Register SrcReg,
                            bool isKill, int FrameIndex,
                            const TargetRegisterClass *RC,
-                           const TargetRegisterInfo *TRI) const override;
-  unsigned isStoreToStackSlot(const MachineInstr &MI,
+                           const TargetRegisterInfo *TRI,
+                           Register VReg) const override;
+  Register isStoreToStackSlot(const MachineInstr &MI,
                               int &FrameIndex) const override;
   void loadRegFromStackSlot(MachineBasicBlock &MBB,
                             MachineBasicBlock::iterator MI, Register DstReg,
                             int FrameIndex, const TargetRegisterClass *RC,
-                            const TargetRegisterInfo *TRI) const override;
-  unsigned isLoadFromStackSlot(const MachineInstr &MI,
+                            const TargetRegisterInfo *TRI,
+                            Register VReg) const override;
+  Register isLoadFromStackSlot(const MachineInstr &MI,
                                int &FrameIndex) const override;
 
   void rewriteFrameIndex(MachineInstr &MI, unsigned FIOperandNum,
                          Register BaseReg, int64_t Offset,
                          RegScavenger *RS = nullptr, int SPAdj = 0) const;
 
-  bool isReallyTriviallyReMaterializable(const MachineInstr &MI,
-                                         AAResults *AA) const override;
+  bool isReallyTriviallyReMaterializable(const MachineInstr &MI) const override;
   void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
                      Register DstReg, unsigned SubIdx, const MachineInstr &Orig,
                      const TargetRegisterInfo &TRI) const override;
diff --git a/llvm/lib/Target/Z80/Z80InstrInfo.td b/llvm/lib/Target/Z80/Z80InstrInfo.td
index 7c6ebe72a8d60..68fe11f4fff31 100644
--- a/llvm/lib/Target/Z80/Z80InstrInfo.td
+++ b/llvm/lib/Target/Z80/Z80InstrInfo.td
@@ -978,10 +978,14 @@ def INC24s : I24<  NoPre, 0x33, "inc", "\tsp", "",
 def DEC24s : I24<  NoPre, 0x3B, "dec", "\tsp", "",
                  (outs), (ins), [(set SPL, (Z80dec_flag SPL))]>;
 }
+// GISelShouldIgnore: These patterns have tied operands that cause TableGen
+// to generate incorrect GlobalISel code (double-erase bug). Handle in C++ instead.
+let GISelShouldIgnore = 1 in {
 def : Pat<(add R16:$imp,  1), (INC16r R16:$imp)>;
 def : Pat<(add R16:$imp, -1), (DEC16r R16:$imp)>;
 def : Pat<(add R24:$imp,  1), (INC24r R24:$imp)>;
 def : Pat<(add R24:$imp, -1), (DEC24r R24:$imp)>;
+}
 
 let Defs = [F] in {
   def ADD16ao : I16<Idx01Pre, 0x09, "add", "\t$dst, $src", "$imp = $dst",
diff --git a/llvm/lib/Target/Z80/Z80MCInstLower.cpp b/llvm/lib/Target/Z80/Z80MCInstLower.cpp
index 69025c9ea9aa7..3fdc4c3b66d83 100644
--- a/llvm/lib/Target/Z80/Z80MCInstLower.cpp
+++ b/llvm/lib/Target/Z80/Z80MCInstLower.cpp
@@ -32,7 +32,7 @@ class Z80MCInstLower {
 public:
   Z80MCInstLower(const MachineFunction &MF, Z80AsmPrinter &AP);
 
-  Optional<MCOperand> LowerMachineOperand(const MachineInstr *MI,
+  std::optional<MCOperand> LowerMachineOperand(const MachineInstr *MI,
                                           const MachineOperand &MO) const;
 
   MCSymbol *GetGlobalAddressSymbol(const MachineOperand &MO) const;
@@ -70,7 +70,7 @@ MCOperand Z80MCInstLower::LowerSymbolOperand(const MachineOperand &MO,
   return MCOperand::createExpr(Expr);
 }
 
-Optional<MCOperand>
+std::optional<MCOperand>
 Z80MCInstLower::LowerMachineOperand(const MachineInstr *MI,
                                     const MachineOperand &MO) const {
   switch (MO.getType()) {
@@ -93,7 +93,7 @@ Z80MCInstLower::LowerMachineOperand(const MachineInstr *MI,
   case MachineOperand::MO_JumpTableIndex:
     return LowerSymbolOperand(MO, AsmPrinter.GetJTISymbol(MO.getIndex()));
   case MachineOperand::MO_RegisterMask:
-    return None; // Ignore call clobbers.
+    return std::nullopt; // Ignore call clobbers.
   }
 }
 
diff --git a/llvm/lib/Target/Z80/Z80MachineEarlyOptimization.cpp b/llvm/lib/Target/Z80/Z80MachineEarlyOptimization.cpp
index 59ad8e11d2ba7..cd6947547cbab 100644
--- a/llvm/lib/Target/Z80/Z80MachineEarlyOptimization.cpp
+++ b/llvm/lib/Target/Z80/Z80MachineEarlyOptimization.cpp
@@ -149,7 +149,7 @@ bool Z80MachineEarlyOptimization::runOnMachineFunction(MachineFunction &MF) {
           if (CallMI) {
             for (Result &Res : Results) {
               if (!Res.FalseReg.isValid() ||
-                  CallMI->readsRegister(Res.PhysReg)) {
+                  CallMI->readsRegister(Res.PhysReg, &TRI)) {
                 CallMI = nullptr;
                 break;
               }
@@ -169,7 +169,7 @@ bool Z80MachineEarlyOptimization::runOnMachineFunction(MachineFunction &MF) {
             CallMI->setDesc(TII.get(CallMI->getOpcode() == Z80::CALL24
                                     ? Z80::CALL24CC : Z80::CALL16CC));
             auto RegMask = CallMI->getOperand(1).getRegMask();
-            CallMI->RemoveOperand(1);
+            CallMI->removeOperand(1);
             MachineInstrBuilder(MF, CallMI)
                 .add(Cond[0]).addRegMask(RegMask)
                 .addReg(Z80::F, RegState::Implicit);
diff --git a/llvm/lib/Target/Z80/Z80MachineFunctionInfo.h b/llvm/lib/Target/Z80/Z80MachineFunctionInfo.h
index 8179e01392918..ea3aa54adcc02 100644
--- a/llvm/lib/Target/Z80/Z80MachineFunctionInfo.h
+++ b/llvm/lib/Target/Z80/Z80MachineFunctionInfo.h
@@ -52,6 +52,8 @@ class Z80MachineFunctionInfo : public MachineFunctionInfo {
 public:
   Z80MachineFunctionInfo() = default;
 
+  Z80MachineFunctionInfo(const Function &F, const TargetSubtargetInfo *STI) {}
+
   explicit Z80MachineFunctionInfo(MachineFunction &MF) {}
 
   unsigned getArgFrameSize() const { return ArgFrameSize; }
diff --git a/llvm/lib/Target/Z80/Z80MachineLateOptimization.cpp b/llvm/lib/Target/Z80/Z80MachineLateOptimization.cpp
index c92c4ae631d73..a589e87eb8640 100644
--- a/llvm/lib/Target/Z80/Z80MachineLateOptimization.cpp
+++ b/llvm/lib/Target/Z80/Z80MachineLateOptimization.cpp
@@ -548,7 +548,7 @@ bool Z80MachineLateOptimization::runOnMachineFunction(MachineFunction &MF) {
           }
           assert(Opc == Z80::LD8r0);
           MIB.addReg(SrcReg, getKillRegState(reuse(SrcReg)));
-          int ImpDefIdx = MIB->findRegisterDefOperandIdx(Z80::F, true);
+          int ImpDefIdx = MIB->findRegisterDefOperandIdx(Z80::F, TRI, true, false);
           if (ImpDefIdx >= 0)
             MIB->removeOperand(ImpDefIdx);
           break;
diff --git a/llvm/lib/Target/Z80/Z80PostSelectCombiner.cpp b/llvm/lib/Target/Z80/Z80PostSelectCombiner.cpp
index 879d2fab62255..bdd9d77ffad8b 100644
--- a/llvm/lib/Target/Z80/Z80PostSelectCombiner.cpp
+++ b/llvm/lib/Target/Z80/Z80PostSelectCombiner.cpp
@@ -143,7 +143,7 @@ bool Z80PostSelectCombiner::runOnMachineFunction(MachineFunction &MF) {
         BuildMI(MBB, MI, MI.getDebugLoc(), TII.get(TargetOpcode::COPY), TmpReg)
             .add(MI.getOperand(1));
         MI.setDesc(TII.get(DstReg == Z80::SPL ? Z80::LD24sa : Z80::LD16sa));
-        MI.RemoveOperand(0);
+        MI.removeOperand(0);
         MI.getOperand(0).setReg(TmpReg);
         MachineInstrBuilder(MF, MI).addReg(DstReg, RegState::ImplicitDefine);
         Changed = true;
@@ -164,7 +164,7 @@ bool Z80PostSelectCombiner::runOnMachineFunction(MachineFunction &MF) {
         MachineOperand &BaseMO = SrcMI->getOperand(1);
         auto NewOff = SrcMI->getOperand(2).getImm();
         if (!BaseMO.isReg() || NewOff) {
-          MI.RemoveOperand(0);
+          MI.removeOperand(0);
           MI.setDesc(TII.get(IsPush24 ? Z80::PEA24o : Z80::PEA16o));
           MachineInstrBuilder(MF, MI).add(SrcMI->getOperand(1)).addImm(NewOff);
         } else
diff --git a/llvm/lib/Target/Z80/Z80RegisterInfo.cpp b/llvm/lib/Target/Z80/Z80RegisterInfo.cpp
index 089ea9c2a154b..918f5aadfd730 100644
--- a/llvm/lib/Target/Z80/Z80RegisterInfo.cpp
+++ b/llvm/lib/Target/Z80/Z80RegisterInfo.cpp
@@ -62,9 +62,9 @@ Z80RegisterInfo::getPointerRegClassForConstraint(const MachineFunction &MF,
   unsigned Kind;
   switch (Constraint) {
   default: llvm_unreachable("Unexpected Constraint!");
-  case InlineAsm::Constraint_V: Kind = 1; break;
-  case InlineAsm::Constraint_m: Kind = 2; break;
-  case InlineAsm::Constraint_o: Kind = 3; break;
+  case static_cast<unsigned>(InlineAsm::ConstraintCode::V): Kind = 1; break;
+  case static_cast<unsigned>(InlineAsm::ConstraintCode::m): Kind = 2; break;
+  case static_cast<unsigned>(InlineAsm::ConstraintCode::o): Kind = 3; break;
   }
   return getPointerRegClass(MF, Kind);
 }
@@ -197,7 +197,7 @@ bool Z80RegisterInfo::saveScavengerRegister(MachineBasicBlock &MBB,
   return true;
 }
 
-void Z80RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
+bool Z80RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
                                           int SPAdj, unsigned FIOperandNum,
                                           RegScavenger *RS) const {
   MachineInstr &MI = *II;
@@ -215,6 +215,7 @@ void Z80RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
     // For fixed indices, skip over callee save slots.
     Offset += MF.getInfo<Z80MachineFunctionInfo>()->getCalleeSavedFrameSize();
   TII.rewriteFrameIndex(MI, FIOperandNum, BaseReg, Offset, RS, SPAdj);
+  return false;
 }
 
 Register Z80RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
diff --git a/llvm/lib/Target/Z80/Z80RegisterInfo.h b/llvm/lib/Target/Z80/Z80RegisterInfo.h
index 05521f7858572..972a61d54441c 100644
--- a/llvm/lib/Target/Z80/Z80RegisterInfo.h
+++ b/llvm/lib/Target/Z80/Z80RegisterInfo.h
@@ -15,6 +15,7 @@
 #define LLVM_LIB_TARGET_Z80_Z80REGISTERINFO_H
 
 #include "llvm/CodeGen/TargetRegisterInfo.h"
+#include "llvm/IR/InlineAsm.h"
 
 #define GET_REGINFO_HEADER
 #include "Z80GenRegisterInfo.inc"
@@ -50,7 +51,7 @@ class Z80RegisterInfo final : public Z80GenRegisterInfo {
                      unsigned Kind = 0) const override;
   const TargetRegisterClass *getPointerRegClassForConstraint(
       const MachineFunction &MF,
-      unsigned Constraint = InlineAsm::Constraint_m) const override;
+      unsigned Constraint = static_cast<unsigned>(InlineAsm::ConstraintCode::m)) const override;
 
   const TargetRegisterClass *
   getLargestLegalSuperClass(const TargetRegisterClass *RC,
@@ -90,7 +91,7 @@ class Z80RegisterInfo final : public Z80GenRegisterInfo {
                              const TargetRegisterClass *RC,
                              Register Reg) const override;
 
-  void eliminateFrameIndex(MachineBasicBlock::iterator MI,
+  bool eliminateFrameIndex(MachineBasicBlock::iterator MI,
                            int SPAdj, unsigned FIOperandNum,
                            RegScavenger *RS = nullptr) const override;
 
diff --git a/llvm/lib/Target/Z80/Z80Subtarget.h b/llvm/lib/Target/Z80/Z80Subtarget.h
index 2805d0aab6303..4d76df9d8aa2a 100644
--- a/llvm/lib/Target/Z80/Z80Subtarget.h
+++ b/llvm/lib/Target/Z80/Z80Subtarget.h
@@ -25,7 +25,7 @@
 #include "llvm/CodeGen/GlobalISel/InlineAsmLowering.h"
 #include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
 #include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
-#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
+#include "llvm/CodeGen/RegisterBankInfo.h"
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
 
 #define GET_SUBTARGETINFO_HEADER
diff --git a/llvm/lib/Target/Z80/Z80TargetMachine.cpp b/llvm/lib/Target/Z80/Z80TargetMachine.cpp
index 382a58303e3fc..37034f2dec38d 100644
--- a/llvm/lib/Target/Z80/Z80TargetMachine.cpp
+++ b/llvm/lib/Target/Z80/Z80TargetMachine.cpp
@@ -12,6 +12,7 @@
 //===----------------------------------------------------------------------===//
 
 #include "Z80TargetMachine.h"
+#include "Z80MachineFunctionInfo.h"
 #include "TargetInfo/Z80TargetInfo.h"
 #include "Z80.h"
 #include "Z80Subtarget.h"
@@ -23,6 +24,7 @@
 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
+#include "llvm/CodeGen/GlobalISel/CSEInfo.h"
 #include "llvm/CodeGen/Passes.h"
 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
 #include "llvm/CodeGen/TargetPassConfig.h"
@@ -68,7 +70,7 @@ static std::string computeDataLayout(const Triple &TT) {
   return Ret;
 }
 
-static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
+static Reloc::Model getEffectiveRelocModel(std::optional<Reloc::Model> RM) {
   if (RM)
     return *RM;
   return Reloc::Static;
@@ -79,9 +81,9 @@ static Reloc::Model getEffectiveRelocModel(Optional<Reloc::Model> RM) {
 Z80TargetMachine::Z80TargetMachine(const Target &T, const Triple &TT,
                                    StringRef CPU, StringRef FS,
                                    const TargetOptions &Options,
-                                   Optional<Reloc::Model> RM,
-                                   Optional<CodeModel::Model> CM,
-                                   CodeGenOpt::Level OL, bool JIT)
+                                   std::optional<Reloc::Model> RM,
+                                   std::optional<CodeModel::Model> CM,
+                                   CodeGenOptLevel OL, bool JIT)
     : LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
                         getEffectiveRelocModel(RM),
                         getEffectiveCodeModel(CM, CodeModel::Small), OL),
@@ -128,6 +130,13 @@ Z80TargetMachine::getSubtargetImpl(const Function &F) const {
   return I.get();
 }
 
+MachineFunctionInfo *Z80TargetMachine::createMachineFunctionInfo(
+    BumpPtrAllocator &Allocator, const Function &F,
+    const TargetSubtargetInfo *STI) const {
+  return Z80MachineFunctionInfo::create<Z80MachineFunctionInfo>(Allocator, F,
+                                                                STI);
+}
+
 //===----------------------------------------------------------------------===//
 // Pass Pipeline Configuration
 //===----------------------------------------------------------------------===//
@@ -169,8 +178,7 @@ bool Z80PassConfig::addIRTranslator() {
 }
 
 void Z80PassConfig::addPreLegalizeMachineIR() {
-  bool IsOptNone = getOptLevel() == CodeGenOpt::None;
-  addPass(createZ80PreLegalizeCombiner(IsOptNone));
+  addPass(createZ80PreLegalizeCombiner());
 }
 
 bool Z80PassConfig::addLegalizeMachineIR() {
@@ -181,9 +189,8 @@ bool Z80PassConfig::addLegalizeMachineIR() {
 void Z80PassConfig::addPreRegBankSelect() {
   // For now we don't add this to the pipeline for -O0. We could do in future
   // if we split the combines into separate O0/opt groupings.
-  bool IsOptNone = getOptLevel() == CodeGenOpt::None;
-  if (!IsOptNone)
-    addPass(createZ80PostLegalizeCombiner(IsOptNone));
+  if (getOptLevel() != CodeGenOptLevel::None)
+    addPass(createZ80PostLegalizeCombiner());
 }
 
 bool Z80PassConfig::addRegBankSelect() {
diff --git a/llvm/lib/Target/Z80/Z80TargetMachine.h b/llvm/lib/Target/Z80/Z80TargetMachine.h
index 3c0a734b384a8..2b8901efc1d54 100644
--- a/llvm/lib/Target/Z80/Z80TargetMachine.h
+++ b/llvm/lib/Target/Z80/Z80TargetMachine.h
@@ -26,11 +26,15 @@ class Z80TargetMachine : public LLVMTargetMachine {
 public:
   Z80TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
                    StringRef FS, const TargetOptions &Options,
-                   Optional<Reloc::Model> RM, Optional<CodeModel::Model> CM,
-                   CodeGenOpt::Level OL, bool JIT);
+                   std::optional<Reloc::Model> RM, std::optional<CodeModel::Model> CM,
+                   CodeGenOptLevel OL, bool JIT);
   ~Z80TargetMachine() override;
   const Z80Subtarget *getSubtargetImpl(const Function &F) const override;
 
+  MachineFunctionInfo *
+  createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F,
+                            const TargetSubtargetInfo *STI) const override;
+
   // Set up the pass pipeline.
   TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
   TargetLoweringObjectFile *getObjFileLowering() const override {
diff --git a/llvm/utils/TableGen/GlobalISelEmitter.cpp b/llvm/utils/TableGen/GlobalISelEmitter.cpp
index f8ae8ac1715f5..845d2358e8d6a 100644
--- a/llvm/utils/TableGen/GlobalISelEmitter.cpp
+++ b/llvm/utils/TableGen/GlobalISelEmitter.cpp
@@ -1817,6 +1817,9 @@ Error GlobalISelEmitter::importImplicitDefRenderers(
   const CodeGenInstruction &DstI = *DstMIBuilder.getCGI();
   int DstINumImplicitDefs = Src->getNumResults() - DstI.Operands.NumDefs;
 
+  if (DstINumImplicitDefs > 0)
+    return failedImport("Cannot import pattern with implicit def results but no explicit def operands");
+
   for (int I = 0; I < DstINumImplicitDefs; ++I) {
     auto PhysOutput = DstI.ImplicitDefs[I];
     assert(PhysOutput->isSubClassOf("Register"));
@@ -2084,6 +2087,9 @@ Expected<RuleMatcher> GlobalISelEmitter::runOnPattern(const PatternToMatch &P) {
   // matches the result instruction.
   unsigned OpIdx = 0;
   unsigned N = std::min(DstNumDefs, SrcNumResults);
+  if (N > 0 && DstI.Operands.NumDefs == 0)
+    return failedImport("Dst instruction has no explicit def operands");
+
   for (unsigned I = 0; I < N; ++I) {
     const TypeSetByHwMode &VTy = Src.getExtType(I);