fix GlobalISEL

adriweb · adriweb · commit a7b4a4ba5d55 · 2025-03-03T13:55:22.000+01:00
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h b/llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h
@@ -19,6 +19,7 @@
 #include "llvm/CodeGen/CallingConvLower.h"
 #include "llvm/CodeGen/MachineOperand.h"
 #include "llvm/CodeGen/TargetCallingConv.h"
+#include "llvm/IR/Attributes.h"
 #include "llvm/IR/CallingConv.h"
 #include "llvm/IR/Type.h"
 #include "llvm/IR/Value.h"
@@ -30,7 +31,6 @@
 
 namespace llvm {
 
-class AttributeList;
 class CallBase;
 class DataLayout;
 class Function;
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h b/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h
@@ -1540,7 +1540,7 @@ class LegalizationArtifactCombiner {
         SubRegs.reserve(NumSubSrcs);
         for (unsigned Idx = MergeSrcIdx; Idx <= EndMergeSrcIdx; ++Idx)
           SubRegs.push_back(SrcDef->getOperand(Idx + 1).getReg());
-        UpdatedDefs.push_back(Builder.buildMerge(DstReg, SubRegs).getReg(0));
+        UpdatedDefs.push_back(Builder.buildMergeValues(DstReg, SubRegs).getReg(0));
         markInstAndDefDead(MI, *SrcDef, DeadInsts);
         return true;
       }
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h b/llvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h
@@ -69,37 +69,82 @@ struct IgnoreMatch {
 };
 
 template <typename ConstT>
-Optional<ConstT> matchConstant(Register Reg, const MachineRegisterInfo &MRI);
+std::optional<ConstT> matchConstant(Register Reg, const MachineRegisterInfo &MRI);
 
 template <>
-inline Optional<ValueAndVReg>
-matchConstant<ValueAndVReg>(Register Reg, const MachineRegisterInfo &MRI) {
+inline std::optional<std::optional<ValueAndVReg>>
+matchConstant<std::optional<ValueAndVReg>>(Register Reg,
+                                      const MachineRegisterInfo &MRI) {
   return getIConstantVRegValWithLookThrough(Reg, MRI);
 }
 
 template <>
-inline Optional<APInt> matchConstant<APInt>(Register Reg,
+inline std::optional<APInt> matchConstant<APInt>(Register Reg,
                                             const MachineRegisterInfo &MRI) {
-  return matchConstant<ValueAndVReg>(Reg, MRI).map(
-      [](ValueAndVReg &&ValAndVReg) { return ValAndVReg.Value; });
+  const auto& Val = matchConstant<std::optional<ValueAndVReg>>(Reg, MRI);
+  if (Val.has_value())
+    return { Val.value()->Value };
+  return { std::nullopt };
 }
 
 template <>
-inline Optional<const IgnoreMatch>
+inline std::optional<const IgnoreMatch>
 matchConstant<const IgnoreMatch>(Register Reg, const MachineRegisterInfo &MRI) {
-  return matchConstant<APInt>(Reg, MRI).map(
-      [](const APInt &) -> const IgnoreMatch { return {}; });
+  matchConstant<APInt>(Reg, MRI);
+  return std::optional<const IgnoreMatch>{ IgnoreMatch{} };
 }
 
-template <typename ConstT>
-inline std::optional<ConstT> matchConstant(Register Reg,
-                                           const MachineRegisterInfo &MRI) {
+template <>
+inline std::optional<int64_t> matchConstant<int64_t>(Register Reg,
+                                                     const MachineRegisterInfo &MRI) {
+  auto Val = matchConstant<APInt>(Reg, MRI);
+  if (Val && Val->getBitWidth() <= 64)
+    return Val->getSExtValue();
+  return std::nullopt;
+}
+
+template <>
+inline std::optional<uint64_t> matchConstant<uint64_t>(Register Reg,
+                                                       const MachineRegisterInfo &MRI) {
+  auto Val = matchConstant<APInt>(Reg, MRI);
+  if (Val && Val->getBitWidth() <= 64)
+    return Val->getSExtValue();
+  return std::nullopt;
+}
+
+template <>
+inline std::optional<unsigned char> matchConstant<unsigned char>(Register Reg,
+                                                                 const MachineRegisterInfo &MRI) {
   auto Val = matchConstant<APInt>(Reg, MRI);
   if (Val && Val->getBitWidth() <= 64)
     return Val->getSExtValue();
   return std::nullopt;
 }
 
+template <>
+inline std::optional<unsigned int> matchConstant<unsigned int>(Register Reg,
+                                                               const MachineRegisterInfo &MRI) {
+  auto Val = matchConstant<APInt>(Reg, MRI);
+  if (Val && Val->getBitWidth() <= 64)
+    return Val->getSExtValue();
+  return std::nullopt;
+}
+
+template <>
+inline std::optional<bool> matchConstant<bool>(Register Reg,
+                                               const MachineRegisterInfo &MRI) {
+  auto Val = matchConstant<APInt>(Reg, MRI);
+  if (Val && Val->getBitWidth() <= 64)
+    return Val->getSExtValue();
+  return std::nullopt;
+}
+
+template <>
+inline std::optional<ValueAndVReg> matchConstant<ValueAndVReg>(Register Reg,
+    const MachineRegisterInfo &MRI) {
+  return getIConstantVRegValWithLookThrough(Reg, MRI);
+}
+
 template <typename ConstT> struct ConstantMatch {
   ConstT &CR;
   ConstantMatch(ConstT &C) : CR(C) {}
@@ -165,10 +210,12 @@ struct GCstAndRegMatch {
   bool match(const MachineRegisterInfo &MRI, Register Reg) {
     ValReg = getIConstantVRegValWithLookThrough(Reg, MRI);
     return ValReg ? true : false;
-}
+  }
+};
 
 template <typename ConstT> inline ConstantMatch<ConstT> m_ICst(ConstT &Cst) {
   return {Cst};
+}
 
 inline GCstAndRegMatch m_GCst(std::optional<ValueAndVReg> &ValReg) {
   return GCstAndRegMatch(ValReg);
diff --git a/llvm/include/llvm/Target/GlobalISel/Combine.td b/llvm/include/llvm/Target/GlobalISel/Combine.td
@@ -1167,13 +1167,13 @@ def lower_is_power_of_two : GICombineRule<
          [{ return Helper.matchLowerIsPowerOfTwo(*${mi}); }]),
   (apply [{ Helper.applyLowerIsPowerOfTwo(*${mi}); }])>;
 
-def simplify_const_matchdata : GIDefMatchData<"Optional<ValueAndVReg>">;
+def simplify_const_matchdata : GIDefMatchData<"std::optional<ValueAndVReg>">;
 def simplify_const : GICombineRule<
   (defs root:$mi, simplify_const_matchdata:$matchinfo),
   (match (wip_match_opcode G_TRUNC, G_SEXT, G_ZEXT):$mi,
          [{ ${matchinfo} = getIConstantVRegValWithLookThrough(
                 ${mi}->getOperand(0).getReg(), MRI);
-            return ${matchinfo}.hasValue(); }]),
+            return ${matchinfo}.has_value(); }]),
   (apply [{ Helper.replaceInstWithConstant(*${mi}, ${matchinfo}->Value); }])>;
 
 def simplify_known_const_matchdata : GIDefMatchData<"APInt">;
diff --git a/llvm/lib/CodeGen/GlobalISel/Utils.cpp b/llvm/lib/CodeGen/GlobalISel/Utils.cpp
@@ -473,7 +473,7 @@ std::optional<DefinitionAndSourceRegister>
 llvm::getDefSrcRegIgnoringCopies(Register Reg, const MachineRegisterInfo &MRI,
                                  bool HasOneNonDBGUse) {
   if (HasOneNonDBGUse && !MRI.hasOneNonDBGUse(Reg))
-    return None;
+    return std::nullopt;
   Register DefSrcReg = Reg;
   auto *DefMI = MRI.getVRegDef(Reg);
   auto DstTy = MRI.getType(DefMI->getOperand(0).getReg());
diff --git a/llvm/lib/Target/Z80/GISel/Z80InstructionSelector.cpp b/llvm/lib/Target/Z80/GISel/Z80InstructionSelector.cpp
@@ -903,7 +903,7 @@ bool Z80InstructionSelector::selectLoadStore(MachineInstr &I,
   }
   bool IsOff = MOs.size() == 2;
   if (RMWOps.empty()) {
-    Optional<APInt> ValConst;
+    std::optional<APInt> ValConst;
     switch (Ty.getSizeInBits()) {
     case 8:
       if (!IsLoad)
@@ -1526,7 +1526,7 @@ Z80::CondCode Z80InstructionSelector::foldExtendedAddSub(
   Register DstReg = DstMO.getReg();
   Register LHSReg = I.getOperand(2).getReg();
   Register RHSReg = I.getOperand(3).getReg();
-  Optional<ValueAndVReg> RHSConst = None;
+  std::optional<ValueAndVReg> RHSConst = std::nullopt;
   LLT OpTy = MRI.getType(DstReg);
 
   unsigned AddSubOpc;
diff --git a/llvm/lib/Target/Z80/GISel/Z80LegalizerInfo.cpp b/llvm/lib/Target/Z80/GISel/Z80LegalizerInfo.cpp
@@ -667,7 +667,7 @@ Z80LegalizerInfo::legalizeCompare(LegalizerHelper &Helper,
                                    CallLowering::ArgInfo::NoArgIndex);
     CallLowering::ArgInfo Args[2] = {{LHSReg, Ty, 0}, {RHSReg, Ty, 1}};
     auto Result = createLibcall(MIRBuilder, Libcall, FlagsArg,
-                                makeArrayRef(Args, 2 - ZeroRHS));
+                                ArrayRef(Args, 2 - ZeroRHS));
     if (Result != LegalizerHelper::Legalized)
       return Result;
     MIRBuilder.buildCopy(Register(Z80::F), FlagsReg);
@@ -1086,7 +1086,7 @@ bool Z80LegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
     CallLowering::CallLoweringInfo Info;
     Info.CallConv = CallingConv::C;
     Info.Callee = MachineOperand::CreateES("abort");
-    Info.OrigRet = CallLowering::ArgInfo{None, Type::getVoidTy(Ctx), 0};
+    Info.OrigRet = CallLowering::ArgInfo{{}, Type::getVoidTy(Ctx), 0};
     if (!CLI.lowerCall(MIRBuilder, Info))
       return false;
     break;
diff --git a/llvm/lib/Target/Z80/GISel/Z80PostLegalizerCombiner.cpp b/llvm/lib/Target/Z80/GISel/Z80PostLegalizerCombiner.cpp
@@ -56,7 +56,7 @@ class Z80PostLegalizerCombinerInfo : public CombinerInfo {
 bool Z80PostLegalizerCombinerInfo::combine(GISelChangeObserver &Observer,
                                            MachineInstr &MI,
                                            MachineIRBuilder &B) const {
-  CombinerHelper Helper(Observer, B, KB, MDT,
+  CombinerHelper Helper(Observer, B, false, KB, MDT,
                         MI.getMF()->getSubtarget().getLegalizerInfo());
   Z80GenPostLegalizerCombinerHelper Generated(GeneratedRuleCfg, Helper);
   return Generated.tryCombineAll(Observer, MI, B, Helper);
diff --git a/llvm/lib/Target/Z80/GISel/Z80PreLegalizerCombiner.cpp b/llvm/lib/Target/Z80/GISel/Z80PreLegalizerCombiner.cpp
@@ -60,7 +60,8 @@ class Z80PreLegalizerCombinerInfo : public CombinerInfo {
 bool Z80PreLegalizerCombinerInfo::combine(GISelChangeObserver &Observer,
                                           MachineInstr &MI,
                                           MachineIRBuilder &B) const {
-  CombinerHelper Helper(Observer, B, KB, MDT);
+  CombinerHelper Helper(Observer, B, true, KB, MDT,
+                        MI.getMF()->getSubtarget().getLegalizerInfo());
   Z80GenPreLegalizerCombinerHelper Generated(GeneratedRuleCfg, Helper);
   return Generated.tryCombineAll(Observer, MI, B, Helper);
 }
diff --git a/llvm/utils/TableGen/GlobalISelEmitter.cpp b/llvm/utils/TableGen/GlobalISelEmitter.cpp
@@ -2259,7 +2259,7 @@ class NoUsePredicateMatcher : public InstructionPredicateMatcher {
   }
 
   void emitPredicateOpcodes(MatchTable &Table,
-                            RuleMatcher &Rule) const override {
+                            Matcher &Rule) const override {
     Table << MatchTable::Opcode("GIM_CheckHasNoUse")
           << MatchTable::Comment("MI") << MatchTable::IntValue(InsnVarID)
           << MatchTable::LineBreak;

Original file line number	Diff line number	Diff line change
`@@ -1540,7 +1540,7 @@ class LegalizationArtifactCombiner {`
`1540`	`1540`	`SubRegs.reserve(NumSubSrcs);`
`1541`	`1541`	`for (unsigned Idx = MergeSrcIdx; Idx <= EndMergeSrcIdx; ++Idx)`
`1542`	`1542`	`SubRegs.push_back(SrcDef->getOperand(Idx + 1).getReg());`
`1543`		`- UpdatedDefs.push_back(Builder.buildMerge(DstReg, SubRegs).getReg(0));`
	`1543`	`+ UpdatedDefs.push_back(Builder.buildMergeValues(DstReg, SubRegs).getReg(0));`
`1544`	`1544`	`markInstAndDefDead(MI, *SrcDef, DeadInsts);`
`1545`	`1545`	`return true;`
`1546`	`1546`	`}`
Original file line number	Diff line number	Diff line change
`@@ -2259,7 +2259,7 @@ class NoUsePredicateMatcher : public InstructionPredicateMatcher {`
`2259`	`2259`	`}`
`2260`	`2260`
`2261`	`2261`	`void emitPredicateOpcodes(MatchTable &Table,`
`2262`		`- RuleMatcher &Rule) const override {`
	`2262`	`+ Matcher &Rule) const override {`
`2263`	`2263`	`Table << MatchTable::Opcode("GIM_CheckHasNoUse")`
`2264`	`2264`	`<< MatchTable::Comment("MI") << MatchTable::IntValue(InsnVarID)`
`2265`	`2265`	`<< MatchTable::LineBreak;`