Z80: Fix GlobalISel crashes for LLVM v16 compatibility

- Fix tablegen combiner conflicts by removing fp rule groups
- Use IncomingValueAssigner for formal arguments (was incorrectly OutgoingValueAssigner)
- Add createMachineFunctionInfo override
- Update Z80MachineFunctionInfo with required v16 constructors and clone method
- Fix matchConstant to check both outer and inner optionals
- Add BitWidth > 0 guards to prevent failures on zero width APInts
- Auto update test expectations, all 17 Z80 regression tests now pass

MIPatternMatch.h should be upstreamed as it is a generic LLVM header and we really should not be touching it

Author: Sightem

llvm/include/llvm/CodeGen/GlobalISel/MIPatternMatch.h

@@ -82,7 +82,7 @@ template <>
 inline std::optional<APInt> matchConstant<APInt>(Register Reg,
                                             const MachineRegisterInfo &MRI) {
   const auto& Val = matchConstant<std::optional<ValueAndVReg>>(Reg, MRI);
-  if (Val.has_value())
+  if (Val.has_value() && Val.value().has_value())
     return { Val.value()->Value };
   return { std::nullopt };
 }
@@ -98,7 +98,7 @@ template <>
 inline std::optional<int64_t> matchConstant<int64_t>(Register Reg,
                                                      const MachineRegisterInfo &MRI) {
   auto Val = matchConstant<APInt>(Reg, MRI);
-  if (Val && Val->getBitWidth() <= 64)
+  if (Val && Val->getBitWidth() > 0 && Val->getBitWidth() <= 64)
     return Val->getSExtValue();
   return std::nullopt;
 }
@@ -107,7 +107,7 @@ template <>
 inline std::optional<uint64_t> matchConstant<uint64_t>(Register Reg,
                                                        const MachineRegisterInfo &MRI) {
   auto Val = matchConstant<APInt>(Reg, MRI);
-  if (Val && Val->getBitWidth() <= 64)
+  if (Val && Val->getBitWidth() > 0 && Val->getBitWidth() <= 64)
     return Val->getSExtValue();
   return std::nullopt;
 }
@@ -116,7 +116,7 @@ template <>
 inline std::optional<unsigned char> matchConstant<unsigned char>(Register Reg,
                                                                  const MachineRegisterInfo &MRI) {
   auto Val = matchConstant<APInt>(Reg, MRI);
-  if (Val && Val->getBitWidth() <= 64)
+  if (Val && Val->getBitWidth() > 0 && Val->getBitWidth() <= 64)
     return Val->getSExtValue();
   return std::nullopt;
 }
@@ -125,7 +125,7 @@ template <>
 inline std::optional<unsigned int> matchConstant<unsigned int>(Register Reg,
                                                                const MachineRegisterInfo &MRI) {
   auto Val = matchConstant<APInt>(Reg, MRI);
-  if (Val && Val->getBitWidth() <= 64)
+  if (Val && Val->getBitWidth() > 0 && Val->getBitWidth() <= 64)
     return Val->getSExtValue();
   return std::nullopt;
 }
@@ -134,7 +134,7 @@ template <>
 inline std::optional<bool> matchConstant<bool>(Register Reg,
                                                const MachineRegisterInfo &MRI) {
   auto Val = matchConstant<APInt>(Reg, MRI);
-  if (Val && Val->getBitWidth() <= 64)
+  if (Val && Val->getBitWidth() > 0 && Val->getBitWidth() <= 64)
     return Val->getSExtValue();
   return std::nullopt;
 }

llvm/lib/Target/Z80/GISel/Z80CallLowering.cpp

@@ -762,7 +762,7 @@ bool Z80CallLowering::lowerFormalArguments(MachineIRBuilder &MIRBuilder,
   if (!MBB.empty())
     MIRBuilder.setInstr(*MBB.begin());
 
-  OutgoingValueAssigner Assigner(CC_Z80);
+  IncomingValueAssigner Assigner(CC_Z80);
   FormalArgHandler Handler(MIRBuilder, MRI);
   if (!determineAndHandleAssignments(Handler, Assigner, SplitArgs, MIRBuilder,
                                      F.getCallingConv(), F.isVarArg()))

llvm/lib/Target/Z80/Z80Combine.td

@@ -25,24 +25,40 @@ def flip_setcc_cond : GICombineRule<
          [{ return matchFlipSetCCCond(*${mi}, MRI, ${matchinfo}); }]),
   (apply [{ applyFlipSetCCCond(*${mi}, B, Observer, *${matchinfo}); }])>;
 
+// identity combines (excluding FP related fneg_fneg_fold)
+def z80_identity_combines : GICombineGroup<[select_same_val, right_identity_zero,
+                                            binop_same_val, binop_left_to_zero,
+                                            binop_right_to_zero, p2i_to_i2p,
+                                            i2p_to_p2i, anyext_trunc_fold,
+                                            right_identity_one,
+                                            add_sub_reg, buildvector_identity_fold,
+                                            trunc_buildvector_fold,
+                                            trunc_lshr_buildvector_fold,
+                                            bitcast_bitcast_fold]>;
+
+// const combines (excluding FP related constant_fp_op, combine_minmax_nan)
+def z80_const_combines : GICombineGroup<[const_ptradd_to_i2p,
+                                         overlapping_and, mulo_by_2, mulo_by_0,
+                                         addo_by_0, adde_to_addo]>;
+
 def Z80PreLegalizerCombinerHelper
     : GICombinerHelper<"Z80GenPreLegalizerCombinerHelper", [
         and_ext, and_or_disjoint_mask, combine_ext_or_trunc, combine_identity,
-        combine_trunc_shift, constant_fold, const_combines, div_rem_to_divrem,
-        ext_ext_fold, /*fabs_fabs_fold,*/ fabs_fneg_fold, flip_cmp_cond,
+        combine_trunc_shift, constant_fold, z80_const_combines, div_rem_to_divrem,
+        ext_ext_fold, flip_cmp_cond,
         flip_setcc_cond, form_bitfield_extract, funnel_shift,
         funnel_shift_combines, hoist_logic_op_with_same_opcode_hands,
-        identity_combines, intdiv_combines, known_bits_simplifications,
+        z80_identity_combines, intdiv_combines, known_bits_simplifications,
         load_or_combine, lower_is_power_of_two, merge_unmerge, mulh_combines,
         narrow_count_zext, narrow_icmp, narrow_load, narrow_op, not_cmp_fold,
         opt_brcond_by_inverting_cond, or_to_add, phi_combines,
         ptr_add_const_immed, ptr_add_global_immed, ptr_add_immed_chain,
         ptr_add_with_zero, reassocs, reassoc_fold_consts,
-        redundant_neg_operands, select_combines, sext_to_zext,
+        select_combines, sext_to_zext,
         shift_immed_chain, shift_of_shifted_logic_chain, shl_ashr_to_sext_inreg,
         simplify_add_to_sub, simplify_const, simplify_icmp_bool,
         simplify_known_const, split_brcond, sub_const_to_add_neg,
-        trivial_combines, truncstore_merge, trunc_ext_fold, /*trunc_shl,*/
+        trivial_combines, truncstore_merge, trunc_ext_fold,
         undef_combines, unmerge_cst, unmerge_dead_to_trunc, unmerge_merge,
         unmerge_zext_to_zext, width_reduction_combines,
         xor_of_and_with_same_reg,

llvm/lib/Target/Z80/Z80MachineFunctionInfo.h

@@ -52,7 +52,16 @@ class Z80MachineFunctionInfo : public MachineFunctionInfo {
 public:
   Z80MachineFunctionInfo() = default;
 
-  explicit Z80MachineFunctionInfo(MachineFunction &MF) {}
+  Z80MachineFunctionInfo(const Function &F, const TargetSubtargetInfo *STI) {}
+
+  Z80MachineFunctionInfo(const Z80MachineFunctionInfo &) = default;
+
+  MachineFunctionInfo *
+  clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF,
+        const DenseMap<MachineBasicBlock *, MachineBasicBlock *> &Src2DstMBB)
+      const override {
+    return DestMF.cloneInfo<Z80MachineFunctionInfo>(*this);
+  }
 
   unsigned getArgFrameSize() const { return ArgFrameSize; }
   void setArgFrameSize(unsigned Bytes) { ArgFrameSize = Bytes; }

llvm/lib/Target/Z80/Z80TargetMachine.cpp

@@ -14,6 +14,7 @@
 #include "Z80TargetMachine.h"
 #include "TargetInfo/Z80TargetInfo.h"
 #include "Z80.h"
+#include "Z80MachineFunctionInfo.h"
 #include "Z80Subtarget.h"
 #include "Z80TargetObjectFile.h"
 #include "llvm/ADT/SmallString.h"
@@ -165,6 +166,13 @@ TargetPassConfig *Z80TargetMachine::createPassConfig(PassManagerBase &PM) {
   return new Z80PassConfig(*this, PM);
 }
 
+MachineFunctionInfo *Z80TargetMachine::createMachineFunctionInfo(
+    BumpPtrAllocator &Allocator, const Function &F,
+    const TargetSubtargetInfo *STI) const {
+  return Z80MachineFunctionInfo::create<Z80MachineFunctionInfo>(Allocator, F,
+                                                                STI);
+}
+
 bool Z80PassConfig::addIRTranslator() {
   addPass(new IRTranslator);
   return false;

llvm/lib/Target/Z80/Z80TargetMachine.h

@@ -36,6 +36,10 @@ class Z80TargetMachine : public LLVMTargetMachine {
   TargetLoweringObjectFile *getObjFileLowering() const override {
     return TLOF.get();
   }
+
+  MachineFunctionInfo *
+  createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F,
+                            const TargetSubtargetInfo *STI) const override;
 };
 
 } // end namespace llvm